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net/mlx5: Fix modify_cq_in alignment
[thirdparty/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "en.h"
2c81bfd5 34#include "en/port.h"
db05815b 35#include "en/xsk/umem.h"
6dbc80ca 36#include "lib/clock.h"
f62b8bb8 37
076b0936
ES		 38void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
39 struct ethtool_drvinfo *drvinfo)
f62b8bb8 40{
f62b8bb8
AV		 41 struct mlx5_core_dev *mdev = priv->mdev;
42
43 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
7913d205 44 strlcpy(drvinfo->version, DRIVER_VERSION,
f62b8bb8
AV		 45 sizeof(drvinfo->version));
46 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
84e11edb
IK		 47 "%d.%d.%04d (%.16s)",
48 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
49 mdev->board_id);
f72e6c3e 50 strlcpy(drvinfo->bus_info, dev_name(mdev->device),
f62b8bb8
AV		 51 sizeof(drvinfo->bus_info));
52}
53
076b0936
ES		 54static void mlx5e_get_drvinfo(struct net_device *dev,
55 struct ethtool_drvinfo *drvinfo)
56{
57 struct mlx5e_priv *priv = netdev_priv(dev);
58
59 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
60}
61
665bc539
GP		 62struct ptys2ethtool_config {
63 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
64 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
f62b8bb8
AV		 65};
66
6a897372
AL		 67static
68struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
69static
70struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
665bc539 71
6a897372 72#define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \
665bc539
GP		 73 ({ \
74 struct ptys2ethtool_config *cfg; \
75 const unsigned int modes[] = { __VA_ARGS__ }; \
6a897372
AL		 76 unsigned int i, bit, idx; \
77 cfg = &ptys2##table##_ethtool_table[reg_]; \
665bc539
GP		 78 bitmap_zero(cfg->supported, \
79 __ETHTOOL_LINK_MODE_MASK_NBITS); \
80 bitmap_zero(cfg->advertised, \
81 __ETHTOOL_LINK_MODE_MASK_NBITS); \
82 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
6a897372
AL		 83 bit = modes[i] % 64; \
84 idx = modes[i] / 64; \
85 __set_bit(bit, &cfg->supported[idx]); \
86 __set_bit(bit, &cfg->advertised[idx]); \
665bc539
GP		 87 } \
88 })
89
90void mlx5e_build_ptys2ethtool_map(void)
91{
6a897372
AL		 92 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
93 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
665bc539 95 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
6a897372 96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
665bc539 97 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
6a897372 98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
665bc539 99 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
6a897372 100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
665bc539 101 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
6a897372 102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
665bc539 103 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
6a897372 104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
665bc539 105 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
6a897372 106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
665bc539 107 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
6a897372 108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
665bc539 109 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
6a897372 110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
665bc539 111 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
6a897372 112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
665bc539 113 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
6a897372 114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
665bc539 115 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
6a897372 116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
665bc539 117 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
6a897372 118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
665bc539 119 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
6a897372 120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
665bc539 121 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
6a897372 122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
665bc539 123 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
6a897372 124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
665bc539 125 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
6a897372 126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
665bc539 127 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
6a897372 128 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
665bc539 129 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
6a897372 130 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
665bc539 131 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
6a897372 132 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
665bc539 133 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
6a897372 134 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
665bc539 135 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
6a897372 136 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
665bc539 137 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
6a897372 138 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
665bc539 139 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
6a897372 140 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
665bc539 141 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
6a897372 142 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
665bc539 143 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
6a897372
AL		 144 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
145 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
146 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
147 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
148 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
149 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
150 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
151 ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
152 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
153 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
154 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
155 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
156 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
157 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
158 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
159 ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
160 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
161 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
162 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
163 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
164 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
165 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
166 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
167 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
168 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
169 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
170 ext,
171 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
172 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
173 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
174 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
175 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
176 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
177 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
178 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
179 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
180 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
181 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
182 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
183 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
184 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
185 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
186 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
187 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
188 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
189 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
190 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
191 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
192 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
193 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
194 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
195 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
196 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
197}
198
199static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
200 struct ptys2ethtool_config **arr,
201 u32 *size)
202{
203 bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
204
205 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
206 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
207 ARRAY_SIZE(ptys2legacy_ethtool_table);
665bc539
GP		 208}
209
8ff57c18
TT		 210typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
211
212struct pflag_desc {
213 char name[ETH_GSTRING_LEN];
214 mlx5e_pflag_handler handler;
d2408205
KH		 215};
216
8ff57c18
TT		 217static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
218
076b0936 219int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
f62b8bb8 220{
c0752f2b
KH		 221 int i, num_stats = 0;
222
f62b8bb8
AV		 223 switch (sset) {
224 case ETH_SS_STATS:
c0752f2b
KH		 225 for (i = 0; i < mlx5e_num_stats_grps; i++)
226 num_stats += mlx5e_stats_grps[i].get_num_stats(priv);
1fe85006 227 return num_stats;
4e59e288 228 case ETH_SS_PRIV_FLAGS:
8ff57c18 229 return MLX5E_NUM_PFLAGS;
d605d668
KH		 230 case ETH_SS_TEST:
231 return mlx5e_self_test_num(priv);
f62b8bb8
AV		 232 /* fallthrough */
233 default:
234 return -EOPNOTSUPP;
235 }
236}
237
076b0936
ES		 238static int mlx5e_get_sset_count(struct net_device *dev, int sset)
239{
240 struct mlx5e_priv *priv = netdev_priv(dev);
241
242 return mlx5e_ethtool_get_sset_count(priv, sset);
243}
244
c045deef 245static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, u8 *data)
9218b44d 246{
1fe85006 247 int i, idx = 0;
9218b44d 248
c0752f2b
KH		 249 for (i = 0; i < mlx5e_num_stats_grps; i++)
250 idx = mlx5e_stats_grps[i].fill_strings(priv, data, idx);
9218b44d
GP		 251}
252
c045deef 253void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
f62b8bb8 254{
4e59e288 255 int i;
f62b8bb8
AV		 256
257 switch (stringset) {
258 case ETH_SS_PRIV_FLAGS:
8ff57c18
TT		 259 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
260 strcpy(data + i * ETH_GSTRING_LEN,
261 mlx5e_priv_flags[i].name);
f62b8bb8
AV		 262 break;
263
264 case ETH_SS_TEST:
d605d668
KH		 265 for (i = 0; i < mlx5e_self_test_num(priv); i++)
266 strcpy(data + i * ETH_GSTRING_LEN,
267 mlx5e_self_tests[i]);
f62b8bb8
AV		 268 break;
269
270 case ETH_SS_STATS:
9218b44d 271 mlx5e_fill_stats_strings(priv, data);
f62b8bb8
AV		 272 break;
273 }
274}
275
c045deef 276static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
f62b8bb8
AV		 277{
278 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 279
280 mlx5e_ethtool_get_strings(priv, stringset, data);
281}
282
283void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
284 struct ethtool_stats *stats, u64 *data)
285{
1fe85006 286 int i, idx = 0;
f62b8bb8 287
f62b8bb8 288 mutex_lock(&priv->state_lock);
19386177 289 mlx5e_update_stats(priv);
f62b8bb8
AV		 290 mutex_unlock(&priv->state_lock);
291
c0752f2b
KH		 292 for (i = 0; i < mlx5e_num_stats_grps; i++)
293 idx = mlx5e_stats_grps[i].fill_stats(priv, data, idx);
f62b8bb8
AV		 294}
295
076b0936
ES		 296static void mlx5e_get_ethtool_stats(struct net_device *dev,
297 struct ethtool_stats *stats,
298 u64 *data)
299{
300 struct mlx5e_priv *priv = netdev_priv(dev);
301
302 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
303}
304
076b0936
ES		 305void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
306 struct ethtool_ringparam *param)
f62b8bb8 307{
73281b78 308 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
f62b8bb8 309 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
73281b78 310 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
6a9764ef 311 param->tx_pending = 1 << priv->channels.params.log_sq_size;
f62b8bb8
AV		 312}
313
076b0936
ES		 314static void mlx5e_get_ringparam(struct net_device *dev,
315 struct ethtool_ringparam *param)
f62b8bb8
AV		 316{
317 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 318
319 mlx5e_ethtool_get_ringparam(priv, param);
320}
321
322int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
323 struct ethtool_ringparam *param)
324{
546f18ed 325 struct mlx5e_channels new_channels = {};
f62b8bb8
AV		 326 u8 log_rq_size;
327 u8 log_sq_size;
328 int err = 0;
329
330 if (param->rx_jumbo_pending) {
076b0936 331 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
f62b8bb8
AV		 332 __func__);
333 return -EINVAL;
334 }
335 if (param->rx_mini_pending) {
076b0936 336 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
f62b8bb8
AV		 337 __func__);
338 return -EINVAL;
339 }
cc8e9ebf 340
73281b78 341 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
076b0936 342 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
f62b8bb8 343 __func__, param->rx_pending,
73281b78 344 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
fe4c988b
SM		 345 return -EINVAL;
346 }
347
f62b8bb8 348 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
076b0936 349 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
f62b8bb8
AV		 350 __func__, param->tx_pending,
351 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
352 return -EINVAL;
353 }
f62b8bb8 354
73281b78 355 log_rq_size = order_base_2(param->rx_pending);
f62b8bb8 356 log_sq_size = order_base_2(param->tx_pending);
f62b8bb8 357
73281b78 358 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
6a9764ef 359 log_sq_size == priv->channels.params.log_sq_size)
f62b8bb8
AV		 360 return 0;
361
362 mutex_lock(&priv->state_lock);
98e81b0a 363
546f18ed 364 new_channels.params = priv->channels.params;
73281b78 365 new_channels.params.log_rq_mtu_frames = log_rq_size;
546f18ed 366 new_channels.params.log_sq_size = log_sq_size;
98e81b0a 367
546f18ed
SM		 368 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
369 priv->channels.params = new_channels.params;
370 goto unlock;
371 }
98e81b0a 372
877662e2 373 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
98e81b0a 374
546f18ed 375unlock:
f62b8bb8
AV		 376 mutex_unlock(&priv->state_lock);
377
378 return err;
379}
380
076b0936
ES		 381static int mlx5e_set_ringparam(struct net_device *dev,
382 struct ethtool_ringparam *param)
f62b8bb8
AV		 383{
384 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 385
076b0936
ES		 386 return mlx5e_ethtool_set_ringparam(priv, param);
387}
388
389void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
390 struct ethtool_channels *ch)
391{
db05815b
MM		 392 mutex_lock(&priv->state_lock);
393
779d986d 394 ch->max_combined = mlx5e_get_netdev_max_channels(priv->netdev);
6a9764ef 395 ch->combined_count = priv->channels.params.num_channels;
db05815b
MM		 396 if (priv->xsk.refcnt) {
397 /* The upper half are XSK queues. */
398 ch->max_combined *= 2;
399 ch->combined_count *= 2;
400 }
401
402 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 403}
404
076b0936
ES		 405static void mlx5e_get_channels(struct net_device *dev,
406 struct ethtool_channels *ch)
f62b8bb8
AV		 407{
408 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 409
410 mlx5e_ethtool_get_channels(priv, ch);
411}
412
413int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
414 struct ethtool_channels *ch)
415{
db05815b 416 struct mlx5e_params *cur_params = &priv->channels.params;
f62b8bb8 417 unsigned int count = ch->combined_count;
55c2503d 418 struct mlx5e_channels new_channels = {};
45bf454a 419 bool arfs_enabled;
f62b8bb8
AV		 420 int err = 0;
421
422 if (!count) {
076b0936 423 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
f62b8bb8
AV		 424 __func__);
425 return -EINVAL;
426 }
f62b8bb8 427
db05815b 428 if (cur_params->num_channels == count)
f62b8bb8
AV		 429 return 0;
430
431 mutex_lock(&priv->state_lock);
98e81b0a 432
db05815b
MM		 433 /* Don't allow changing the number of channels if there is an active
434 * XSK, because the numeration of the XSK and regular RQs will change.
435 */
436 if (priv->xsk.refcnt) {
437 err = -EINVAL;
438 netdev_err(priv->netdev, "%s: AF_XDP is active, cannot change the number of channels\n",
439 __func__);
440 goto out;
441 }
442
55c2503d
SM		 443 new_channels.params = priv->channels.params;
444 new_channels.params.num_channels = count;
55c2503d
SM		 445
446 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
db05815b 447 *cur_params = new_channels.params;
c475e11e
TT		 448 if (!netif_is_rxfh_configured(priv->netdev))
449 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
450 MLX5E_INDIR_RQT_SIZE, count);
55c2503d
SM		 451 goto out;
452 }
453
076b0936 454 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
45bf454a
MG		 455 if (arfs_enabled)
456 mlx5e_arfs_disable(priv);
457
fb35c534
MP		 458 if (!netif_is_rxfh_configured(priv->netdev))
459 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
460 MLX5E_INDIR_RQT_SIZE, count);
461
55c2503d 462 /* Switch to new channels, set new parameters and close old ones */
877662e2 463 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
45bf454a
MG		 464
465 if (arfs_enabled) {
877662e2
TT		 466 int err2 = mlx5e_arfs_enable(priv);
467
468 if (err2)
076b0936 469 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
877662e2 470 __func__, err2);
45bf454a 471 }
98e81b0a 472
45bf454a 473out:
f62b8bb8
AV		 474 mutex_unlock(&priv->state_lock);
475
476 return err;
477}
478
076b0936
ES		 479static int mlx5e_set_channels(struct net_device *dev,
480 struct ethtool_channels *ch)
f62b8bb8 481{
076b0936
ES		 482 struct mlx5e_priv *priv = netdev_priv(dev);
483
484 return mlx5e_ethtool_set_channels(priv, ch);
485}
f62b8bb8 486
076b0936
ES		 487int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
488 struct ethtool_coalesce *coal)
489{
8960b389 490 struct dim_cq_moder *rx_moder, *tx_moder;
cbce4f44 491
7524a5d8 492 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
9eb78923 493 return -EOPNOTSUPP;
7524a5d8 494
cbce4f44
TG		 495 rx_moder = &priv->channels.params.rx_cq_moderation;
496 coal->rx_coalesce_usecs = rx_moder->usec;
497 coal->rx_max_coalesced_frames = rx_moder->pkts;
498 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
499
500 tx_moder = &priv->channels.params.tx_cq_moderation;
501 coal->tx_coalesce_usecs = tx_moder->usec;
502 coal->tx_max_coalesced_frames = tx_moder->pkts;
503 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
f62b8bb8
AV		 504
505 return 0;
506}
507
076b0936
ES		 508static int mlx5e_get_coalesce(struct net_device *netdev,
509 struct ethtool_coalesce *coal)
510{
511 struct mlx5e_priv *priv = netdev_priv(netdev);
512
513 return mlx5e_ethtool_get_coalesce(priv, coal);
514}
515
b392a207
MS		 516#define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
517#define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
518
546f18ed
SM		 519static void
520mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
f62b8bb8 521{
f62b8bb8 522 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 523 int tc;
524 int i;
525
ff9c852f
SM		 526 for (i = 0; i < priv->channels.num; ++i) {
527 struct mlx5e_channel *c = priv->channels.c[i];
f62b8bb8
AV		 528
529 for (tc = 0; tc < c->num_tc; tc++) {
530 mlx5_core_modify_cq_moderation(mdev,
531 &c->sq[tc].cq.mcq,
532 coal->tx_coalesce_usecs,
533 coal->tx_max_coalesced_frames);
534 }
535
536 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
537 coal->rx_coalesce_usecs,
538 coal->rx_max_coalesced_frames);
539 }
546f18ed 540}
f62b8bb8 541
076b0936
ES		 542int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
543 struct ethtool_coalesce *coal)
546f18ed 544{
8960b389 545 struct dim_cq_moder *rx_moder, *tx_moder;
546f18ed
SM		 546 struct mlx5_core_dev *mdev = priv->mdev;
547 struct mlx5e_channels new_channels = {};
548 int err = 0;
549 bool reset;
cb3c7fd4 550
546f18ed
SM		 551 if (!MLX5_CAP_GEN(mdev, cq_moderation))
552 return -EOPNOTSUPP;
553
b392a207
MS		 554 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
555 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
556 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
557 __func__, MLX5E_MAX_COAL_TIME);
558 return -ERANGE;
559 }
560
561 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
562 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
563 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
564 __func__, MLX5E_MAX_COAL_FRAMES);
565 return -ERANGE;
566 }
567
546f18ed
SM		 568 mutex_lock(&priv->state_lock);
569 new_channels.params = priv->channels.params;
570
cbce4f44
TG		 571 rx_moder = &new_channels.params.rx_cq_moderation;
572 rx_moder->usec = coal->rx_coalesce_usecs;
573 rx_moder->pkts = coal->rx_max_coalesced_frames;
574 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
575
576 tx_moder = &new_channels.params.tx_cq_moderation;
577 tx_moder->usec = coal->tx_coalesce_usecs;
578 tx_moder->pkts = coal->tx_max_coalesced_frames;
579 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
546f18ed
SM		 580
581 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
582 priv->channels.params = new_channels.params;
583 goto out;
584 }
585 /* we are opened */
586
cbce4f44
TG		 587 reset = (!!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled) ||
588 (!!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled);
589
546f18ed
SM		 590 if (!reset) {
591 mlx5e_set_priv_channels_coalesce(priv, coal);
592 priv->channels.params = new_channels.params;
593 goto out;
594 }
595
877662e2 596 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
546f18ed
SM		 597
598out:
2fcb92fb 599 mutex_unlock(&priv->state_lock);
cb3c7fd4 600 return err;
f62b8bb8
AV		 601}
602
076b0936
ES		 603static int mlx5e_set_coalesce(struct net_device *netdev,
604 struct ethtool_coalesce *coal)
605{
606 struct mlx5e_priv *priv = netdev_priv(netdev);
607
608 return mlx5e_ethtool_set_coalesce(priv, coal);
609}
610
6a897372
AL		 611static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev,
612 unsigned long *supported_modes,
665bc539 613 u32 eth_proto_cap)
f62b8bb8 614{
7abc2110 615 unsigned long proto_cap = eth_proto_cap;
6a897372
AL		 616 struct ptys2ethtool_config *table;
617 u32 max_size;
665bc539 618 int proto;
f62b8bb8 619
6a897372
AL		 620 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size);
621 for_each_set_bit(proto, &proto_cap, max_size)
665bc539 622 bitmap_or(supported_modes, supported_modes,
6a897372 623 table[proto].supported,
665bc539 624 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 625}
626
dd1b9e09
AL		 627static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
628 u32 eth_proto_cap, bool ext)
f62b8bb8 629{
7abc2110 630 unsigned long proto_cap = eth_proto_cap;
6a897372
AL		 631 struct ptys2ethtool_config *table;
632 u32 max_size;
665bc539 633 int proto;
f62b8bb8 634
dd1b9e09
AL		 635 table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
636 max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
637 ARRAY_SIZE(ptys2legacy_ethtool_table);
638
6a897372 639 for_each_set_bit(proto, &proto_cap, max_size)
665bc539 640 bitmap_or(advertising_modes, advertising_modes,
6a897372 641 table[proto].advertised,
665bc539 642 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 643}
644
6cfa9460
SA		 645static const u32 pplm_fec_2_ethtool[] = {
646 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
647 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
648 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
649};
650
651static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
652{
653 int mode = 0;
654
655 if (!fec_mode)
656 return ETHTOOL_FEC_AUTO;
657
658 mode = find_first_bit(&fec_mode, size);
659
660 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
661 return pplm_fec_2_ethtool[mode];
662
663 return 0;
664}
665
666/* we use ETHTOOL_FEC_* offset and apply it to ETHTOOL_LINK_MODE_FEC_*_BIT */
667static u32 ethtool_fec2ethtool_caps(u_long ethtool_fec_code)
668{
669 u32 offset;
670
671 offset = find_first_bit(&ethtool_fec_code, sizeof(u32));
672 offset -= ETHTOOL_FEC_OFF_BIT;
673 offset += ETHTOOL_LINK_MODE_FEC_NONE_BIT;
674
675 return offset;
676}
677
678static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
679 struct ethtool_link_ksettings *link_ksettings)
680{
681 u_long fec_caps = 0;
682 u32 active_fec = 0;
683 u32 offset;
684 u32 bitn;
685 int err;
686
687 err = mlx5e_get_fec_caps(dev, (u8 *)&fec_caps);
688 if (err)
689 return (err == -EOPNOTSUPP) ? 0 : err;
690
691 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
692 if (err)
693 return err;
694
695 for_each_set_bit(bitn, &fec_caps, ARRAY_SIZE(pplm_fec_2_ethtool)) {
696 u_long ethtool_bitmask = pplm_fec_2_ethtool[bitn];
697
698 offset = ethtool_fec2ethtool_caps(ethtool_bitmask);
699 __set_bit(offset, link_ksettings->link_modes.supported);
700 }
701
702 active_fec = pplm2ethtool_fec(active_fec, sizeof(u32) * BITS_PER_BYTE);
703 offset = ethtool_fec2ethtool_caps(active_fec);
704 __set_bit(offset, link_ksettings->link_modes.advertising);
705
706 return 0;
707}
708
46e9d0b6
EBE		 709static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
710 u32 eth_proto_cap,
711 u8 connector_type)
f62b8bb8 712{
46e9d0b6
EBE		 713 if (!connector_type || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
714 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
715 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
716 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
717 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
718 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
719 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
720 ethtool_link_ksettings_add_link_mode(link_ksettings,
721 supported,
722 FIBRE);
723 ethtool_link_ksettings_add_link_mode(link_ksettings,
724 advertising,
725 FIBRE);
726 }
727
728 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
729 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
730 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
731 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
732 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
733 ethtool_link_ksettings_add_link_mode(link_ksettings,
734 supported,
735 Backplane);
736 ethtool_link_ksettings_add_link_mode(link_ksettings,
737 advertising,
738 Backplane);
739 }
740 return;
f62b8bb8
AV		 741 }
742
46e9d0b6
EBE		 743 switch (connector_type) {
744 case MLX5E_PORT_TP:
745 ethtool_link_ksettings_add_link_mode(link_ksettings,
746 supported, TP);
747 ethtool_link_ksettings_add_link_mode(link_ksettings,
748 advertising, TP);
749 break;
750 case MLX5E_PORT_AUI:
751 ethtool_link_ksettings_add_link_mode(link_ksettings,
752 supported, AUI);
753 ethtool_link_ksettings_add_link_mode(link_ksettings,
754 advertising, AUI);
755 break;
756 case MLX5E_PORT_BNC:
757 ethtool_link_ksettings_add_link_mode(link_ksettings,
758 supported, BNC);
759 ethtool_link_ksettings_add_link_mode(link_ksettings,
760 advertising, BNC);
761 break;
762 case MLX5E_PORT_MII:
763 ethtool_link_ksettings_add_link_mode(link_ksettings,
764 supported, MII);
765 ethtool_link_ksettings_add_link_mode(link_ksettings,
766 advertising, MII);
767 break;
768 case MLX5E_PORT_FIBRE:
769 ethtool_link_ksettings_add_link_mode(link_ksettings,
770 supported, FIBRE);
771 ethtool_link_ksettings_add_link_mode(link_ksettings,
772 advertising, FIBRE);
773 break;
774 case MLX5E_PORT_DA:
775 ethtool_link_ksettings_add_link_mode(link_ksettings,
776 supported, Backplane);
777 ethtool_link_ksettings_add_link_mode(link_ksettings,
778 advertising, Backplane);
779 break;
780 case MLX5E_PORT_NONE:
781 case MLX5E_PORT_OTHER:
782 default:
783 break;
f62b8bb8 784 }
f62b8bb8
AV		 785}
786
787static void get_speed_duplex(struct net_device *netdev,
788 u32 eth_proto_oper,
665bc539 789 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 790{
a08b4ed1 791 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8
AV		 792 u32 speed = SPEED_UNKNOWN;
793 u8 duplex = DUPLEX_UNKNOWN;
794
795 if (!netif_carrier_ok(netdev))
796 goto out;
797
a08b4ed1 798 speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper);
2c81bfd5
HN		 799 if (!speed) {
800 speed = SPEED_UNKNOWN;
801 goto out;
f62b8bb8 802 }
2c81bfd5
HN		 803
804 duplex = DUPLEX_FULL;
805
f62b8bb8 806out:
665bc539
GP		 807 link_ksettings->base.speed = speed;
808 link_ksettings->base.duplex = duplex;
f62b8bb8
AV		 809}
810
6a897372 811static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
665bc539 812 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 813{
665bc539 814 unsigned long *supported = link_ksettings->link_modes.supported;
6a897372 815 ptys2ethtool_supported_link(mdev, supported, eth_proto_cap);
665bc539 816
665bc539 817 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
f62b8bb8
AV		 818}
819
dd1b9e09
AL		 820static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause,
821 struct ethtool_link_ksettings *link_ksettings,
822 bool ext)
f62b8bb8 823{
665bc539 824 unsigned long *advertising = link_ksettings->link_modes.advertising;
dd1b9e09 825 ptys2ethtool_adver_link(advertising, eth_proto_cap, ext);
665bc539 826
e3c19503 827 if (rx_pause)
665bc539
GP		 828 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
829 if (tx_pause ^ rx_pause)
830 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
f62b8bb8
AV		 831}
832
5b4793f8
EBE		 833static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
834 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
835 [MLX5E_PORT_NONE] = PORT_NONE,
836 [MLX5E_PORT_TP] = PORT_TP,
837 [MLX5E_PORT_AUI] = PORT_AUI,
838 [MLX5E_PORT_BNC] = PORT_BNC,
839 [MLX5E_PORT_MII] = PORT_MII,
840 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
841 [MLX5E_PORT_DA] = PORT_DA,
842 [MLX5E_PORT_OTHER] = PORT_OTHER,
843 };
844
845static u8 get_connector_port(u32 eth_proto, u8 connector_type)
f62b8bb8 846{
5b4793f8
EBE		 847 if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
848 return ptys2connector_type[connector_type];
849
61bf2125
OG		 850 if (eth_proto &
851 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
852 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
853 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
854 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
855 return PORT_FIBRE;
f62b8bb8
AV		 856 }
857
61bf2125
OG		 858 if (eth_proto &
859 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
860 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
861 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
862 return PORT_DA;
f62b8bb8
AV		 863 }
864
61bf2125
OG		 865 if (eth_proto &
866 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
867 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
868 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
869 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
870 return PORT_NONE;
f62b8bb8
AV		 871 }
872
873 return PORT_OTHER;
874}
875
6a897372 876static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
665bc539 877 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 878{
665bc539 879 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
dd1b9e09 880 bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
665bc539 881
dd1b9e09 882 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext);
f62b8bb8
AV		 883}
884
371289b6
OG		 885int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
886 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 887{
f62b8bb8 888 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 889 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
b383b544
GP		 890 u32 rx_pause = 0;
891 u32 tx_pause = 0;
f62b8bb8
AV		 892 u32 eth_proto_cap;
893 u32 eth_proto_admin;
894 u32 eth_proto_lp;
895 u32 eth_proto_oper;
52244d96
GP		 896 u8 an_disable_admin;
897 u8 an_status;
5b4793f8 898 u8 connector_type;
dd1b9e09 899 bool admin_ext;
6a897372 900 bool ext;
f62b8bb8
AV		 901 int err;
902
a05bdefa 903 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
f62b8bb8 904 if (err) {
371289b6 905 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
f62b8bb8 906 __func__, err);
6cfa9460 907 goto err_query_regs;
f62b8bb8 908 }
6a897372
AL		 909 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
910 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
911 eth_proto_capability);
912 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
913 eth_proto_admin);
dd1b9e09
AL		 914 /* Fields: eth_proto_admin and ext_eth_proto_admin are
915 * mutually exclusive. Hence try reading legacy advertising
916 * when extended advertising is zero.
917 * admin_ext indicates how eth_proto_admin should be
918 * interpreted
919 */
920 admin_ext = ext;
921 if (ext && !eth_proto_admin) {
922 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false,
923 eth_proto_admin);
924 admin_ext = false;
925 }
926
6a897372
AL		 927 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
928 eth_proto_oper);
929 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
930 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
931 an_status = MLX5_GET(ptys_reg, out, an_status);
932 connector_type = MLX5_GET(ptys_reg, out, connector_type);
f62b8bb8 933
b383b544
GP		 934 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
935
665bc539
GP		 936 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
937 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
f62b8bb8 938
6a897372 939 get_supported(mdev, eth_proto_cap, link_ksettings);
dd1b9e09
AL		 940 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings,
941 admin_ext);
371289b6 942 get_speed_duplex(priv->netdev, eth_proto_oper, link_ksettings);
f62b8bb8
AV		 943
944 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
945
5b4793f8
EBE		 946 link_ksettings->base.port = get_connector_port(eth_proto_oper,
947 connector_type);
46e9d0b6
EBE		 948 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
949 connector_type);
6a897372 950 get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
f62b8bb8 951
52244d96
GP		 952 if (an_status == MLX5_AN_COMPLETE)
953 ethtool_link_ksettings_add_link_mode(link_ksettings,
954 lp_advertising, Autoneg);
955
956 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
957 AUTONEG_ENABLE;
958 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
959 Autoneg);
6cfa9460 960
2eb1e425
SA		 961 err = get_fec_supported_advertised(mdev, link_ksettings);
962 if (err) {
371289b6 963 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
6cfa9460 964 __func__, err);
2eb1e425
SA		 965 err = 0; /* don't fail caps query because of FEC error */
966 }
6cfa9460 967
52244d96
GP		 968 if (!an_disable_admin)
969 ethtool_link_ksettings_add_link_mode(link_ksettings,
970 advertising, Autoneg);
971
6cfa9460 972err_query_regs:
f62b8bb8
AV		 973 return err;
974}
975
371289b6
OG		 976static int mlx5e_get_link_ksettings(struct net_device *netdev,
977 struct ethtool_link_ksettings *link_ksettings)
978{
979 struct mlx5e_priv *priv = netdev_priv(netdev);
980
981 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
982}
983
665bc539 984static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
f62b8bb8
AV		 985{
986 u32 i, ptys_modes = 0;
987
988 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
6a897372
AL		 989 if (*ptys2legacy_ethtool_table[i].advertised == 0)
990 continue;
991 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
665bc539
GP		 992 link_modes,
993 __ETHTOOL_LINK_MODE_MASK_NBITS))
f62b8bb8
AV		 994 ptys_modes |= MLX5E_PROT_MASK(i);
995 }
996
997 return ptys_modes;
998}
999
6a897372
AL		 1000static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
1001{
1002 u32 i, ptys_modes = 0;
1003 unsigned long modes[2];
1004
1005 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
1006 if (*ptys2ext_ethtool_table[i].advertised == 0)
1007 continue;
1008 memset(modes, 0, sizeof(modes));
1009 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
1010 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1011
1012 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] &&
1013 modes[1] == ptys2ext_ethtool_table[i].advertised[1])
1014 ptys_modes |= MLX5E_PROT_MASK(i);
1015 }
1016 return ptys_modes;
1017}
1018
371289b6
OG		 1019int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1020 const struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 1021{
f62b8bb8 1022 struct mlx5_core_dev *mdev = priv->mdev;
bc4e12ff 1023 struct mlx5e_port_eth_proto eproto;
52244d96
GP		 1024 bool an_changes = false;
1025 u8 an_disable_admin;
6a897372
AL		 1026 bool ext_supported;
1027 bool ext_requested;
52244d96
GP		 1028 u8 an_disable_cap;
1029 bool an_disable;
f62b8bb8 1030 u32 link_modes;
52244d96 1031 u8 an_status;
f62b8bb8 1032 u32 speed;
f62b8bb8
AV		 1033 int err;
1034
6a897372 1035 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
f62b8bb8 1036
6a897372
AL		 1037#define MLX5E_PTYS_EXT ((1ULL << ETHTOOL_LINK_MODE_50000baseKR_Full_BIT) - 1)
1038
8d047bf5
AL		 1039 ext_requested = !!(link_ksettings->link_modes.advertising[0] >
1040 MLX5E_PTYS_EXT ||
1041 link_ksettings->link_modes.advertising[1]);
6a897372 1042 ext_supported = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
dd1b9e09 1043 ext_requested &= ext_supported;
f62b8bb8 1044
6a897372
AL		 1045 speed = link_ksettings->base.speed;
1046 ethtool2ptys_adver_func = ext_requested ?
1047 mlx5e_ethtool2ptys_ext_adver_link :
1048 mlx5e_ethtool2ptys_adver_link;
dd1b9e09 1049 err = mlx5_port_query_eth_proto(mdev, 1, ext_requested, &eproto);
f62b8bb8 1050 if (err) {
bc4e12ff 1051 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
f62b8bb8
AV		 1052 __func__, err);
1053 goto out;
1054 }
6a897372
AL		 1055 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
1056 ethtool2ptys_adver_func(link_ksettings->link_modes.advertising) :
1057 mlx5e_port_speed2linkmodes(mdev, speed);
f62b8bb8 1058
bc4e12ff 1059 link_modes = link_modes & eproto.cap;
f62b8bb8 1060 if (!link_modes) {
371289b6 1061 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
f62b8bb8
AV		 1062 __func__);
1063 err = -EINVAL;
1064 goto out;
1065 }
1066
bc4e12ff
AL		 1067 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1068 &an_disable_admin);
52244d96
GP		 1069
1070 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
1071 an_changes = ((!an_disable && an_disable_admin) ||
1072 (an_disable && !an_disable_admin));
1073
bc4e12ff 1074 if (!an_changes && link_modes == eproto.admin)
f62b8bb8
AV		 1075 goto out;
1076
dd1b9e09 1077 mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext_requested);
667daeda 1078 mlx5_toggle_port_link(mdev);
f62b8bb8 1079
f62b8bb8
AV		 1080out:
1081 return err;
1082}
1083
371289b6
OG		 1084static int mlx5e_set_link_ksettings(struct net_device *netdev,
1085 const struct ethtool_link_ksettings *link_ksettings)
1086{
1087 struct mlx5e_priv *priv = netdev_priv(netdev);
1088
1089 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1090}
1091
a5355de8
OG		 1092u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1093{
bbeb53b8 1094 return sizeof(priv->rss_params.toeplitz_hash_key);
a5355de8
OG		 1095}
1096
2d75b2bc
AS		 1097static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1098{
1099 struct mlx5e_priv *priv = netdev_priv(netdev);
1100
a5355de8 1101 return mlx5e_ethtool_get_rxfh_key_size(priv);
2d75b2bc
AS		 1102}
1103
a5355de8 1104u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
2d75b2bc
AS		 1105{
1106 return MLX5E_INDIR_RQT_SIZE;
1107}
1108
a5355de8
OG		 1109static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1110{
1111 struct mlx5e_priv *priv = netdev_priv(netdev);
1112
1113 return mlx5e_ethtool_get_rxfh_indir_size(priv);
1114}
1115
2be6967c
SM		 1116static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1117 u8 *hfunc)
1118{
1119 struct mlx5e_priv *priv = netdev_priv(netdev);
bbeb53b8 1120 struct mlx5e_rss_params *rss = &priv->rss_params;
2be6967c 1121
2d75b2bc 1122 if (indir)
bbeb53b8
AL		 1123 memcpy(indir, rss->indirection_rqt,
1124 sizeof(rss->indirection_rqt));
2d75b2bc
AS		 1125
1126 if (key)
bbeb53b8
AL		 1127 memcpy(key, rss->toeplitz_hash_key,
1128 sizeof(rss->toeplitz_hash_key));
2d75b2bc 1129
2be6967c 1130 if (hfunc)
bbeb53b8 1131 *hfunc = rss->hfunc;
2be6967c
SM		 1132
1133 return 0;
1134}
1135
98e81b0a 1136static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
2be6967c
SM		 1137 const u8 *key, const u8 hfunc)
1138{
98e81b0a 1139 struct mlx5e_priv *priv = netdev_priv(dev);
bbeb53b8 1140 struct mlx5e_rss_params *rss = &priv->rss_params;
bdfc028d 1141 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1d3398fa 1142 bool hash_changed = false;
bdfc028d 1143 void *in;
2be6967c 1144
2d75b2bc
AS		 1145 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1146 (hfunc != ETH_RSS_HASH_XOR) &&
2be6967c
SM		 1147 (hfunc != ETH_RSS_HASH_TOP))
1148 return -EINVAL;
1149
1b9a07ee 1150 in = kvzalloc(inlen, GFP_KERNEL);
bdfc028d
TT		 1151 if (!in)
1152 return -ENOMEM;
1153
2be6967c
SM		 1154 mutex_lock(&priv->state_lock);
1155
bbeb53b8
AL		 1156 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) {
1157 rss->hfunc = hfunc;
1d3398fa
GP		 1158 hash_changed = true;
1159 }
1160
a5f97fee 1161 if (indir) {
bbeb53b8
AL		 1162 memcpy(rss->indirection_rqt, indir,
1163 sizeof(rss->indirection_rqt));
a5f97fee
SM		 1164
1165 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1166 u32 rqtn = priv->indir_rqt.rqtn;
1167 struct mlx5e_redirect_rqt_param rrp = {
1168 .is_rss = true,
e270e966
AM		 1169 {
1170 .rss = {
bbeb53b8 1171 .hfunc = rss->hfunc,
e270e966
AM		 1172 .channels = &priv->channels,
1173 },
1174 },
a5f97fee
SM		 1175 };
1176
1177 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1178 }
1179 }
1180
1d3398fa 1181 if (key) {
bbeb53b8
AL		 1182 memcpy(rss->toeplitz_hash_key, key,
1183 sizeof(rss->toeplitz_hash_key));
1184 hash_changed = hash_changed || rss->hfunc == ETH_RSS_HASH_TOP;
1d3398fa 1185 }
2d75b2bc 1186
1d3398fa
GP		 1187 if (hash_changed)
1188 mlx5e_modify_tirs_hash(priv, in, inlen);
2d75b2bc 1189
2be6967c
SM		 1190 mutex_unlock(&priv->state_lock);
1191
bdfc028d
TT		 1192 kvfree(in);
1193
1194 return 0;
2be6967c
SM		 1195}
1196
2afa609f
IK		 1197#define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1198#define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1199#define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1200#define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1201#define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1202 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1203 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1204
1205static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1206 u16 *pfc_prevention_tout)
1207{
1208 struct mlx5e_priv *priv = netdev_priv(netdev);
1209 struct mlx5_core_dev *mdev = priv->mdev;
1210
1211 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1212 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1213 return -EOPNOTSUPP;
1214
1215 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1216}
1217
1218static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1219 u16 pfc_preven)
1220{
1221 struct mlx5e_priv *priv = netdev_priv(netdev);
1222 struct mlx5_core_dev *mdev = priv->mdev;
1223 u16 critical_tout;
1224 u16 minor;
1225
1226 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1227 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1228 return -EOPNOTSUPP;
1229
1230 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1231 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1232 pfc_preven;
1233
1234 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1235 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1236 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1237 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1238 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1239 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1240 return -EINVAL;
1241 }
1242
1243 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1244 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1245 minor);
1246}
1247
58d52291
AS		 1248static int mlx5e_get_tunable(struct net_device *dev,
1249 const struct ethtool_tunable *tuna,
1250 void *data)
1251{
c4554fbc 1252 int err;
58d52291
AS		 1253
1254 switch (tuna->id) {
2afa609f
IK		 1255 case ETHTOOL_PFC_PREVENTION_TOUT:
1256 err = mlx5e_get_pfc_prevention_tout(dev, data);
1257 break;
58d52291
AS		 1258 default:
1259 err = -EINVAL;
1260 break;
1261 }
1262
1263 return err;
1264}
1265
1266static int mlx5e_set_tunable(struct net_device *dev,
1267 const struct ethtool_tunable *tuna,
1268 const void *data)
1269{
1270 struct mlx5e_priv *priv = netdev_priv(dev);
c4554fbc 1271 int err;
546f18ed
SM		 1272
1273 mutex_lock(&priv->state_lock);
58d52291
AS		 1274
1275 switch (tuna->id) {
2afa609f
IK		 1276 case ETHTOOL_PFC_PREVENTION_TOUT:
1277 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
58d52291
AS		 1278 break;
1279 default:
1280 err = -EINVAL;
1281 break;
1282 }
1283
546f18ed 1284 mutex_unlock(&priv->state_lock);
58d52291
AS		 1285 return err;
1286}
1287
371289b6
OG		 1288void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1289 struct ethtool_pauseparam *pauseparam)
3c2d18ef 1290{
3c2d18ef
AS		 1291 struct mlx5_core_dev *mdev = priv->mdev;
1292 int err;
1293
1294 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1295 &pauseparam->tx_pause);
1296 if (err) {
371289b6 1297 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
3c2d18ef
AS		 1298 __func__, err);
1299 }
1300}
1301
371289b6
OG		 1302static void mlx5e_get_pauseparam(struct net_device *netdev,
1303 struct ethtool_pauseparam *pauseparam)
1304{
1305 struct mlx5e_priv *priv = netdev_priv(netdev);
1306
1307 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1308}
1309
1310int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1311 struct ethtool_pauseparam *pauseparam)
3c2d18ef 1312{
3c2d18ef
AS		 1313 struct mlx5_core_dev *mdev = priv->mdev;
1314 int err;
1315
1316 if (pauseparam->autoneg)
1317 return -EINVAL;
1318
1319 err = mlx5_set_port_pause(mdev,
1320 pauseparam->rx_pause ? 1 : 0,
1321 pauseparam->tx_pause ? 1 : 0);
1322 if (err) {
371289b6 1323 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
3c2d18ef
AS		 1324 __func__, err);
1325 }
1326
1327 return err;
1328}
1329
371289b6
OG		 1330static int mlx5e_set_pauseparam(struct net_device *netdev,
1331 struct ethtool_pauseparam *pauseparam)
1332{
1333 struct mlx5e_priv *priv = netdev_priv(netdev);
1334
1335 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1336}
1337
3844b07e
FD		 1338int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1339 struct ethtool_ts_info *info)
ef9814de 1340{
7c39afb3 1341 struct mlx5_core_dev *mdev = priv->mdev;
ef9814de 1342
6dbc80ca 1343 info->phc_index = mlx5_clock_get_ptp_index(mdev);
ef9814de 1344
6dbc80ca
MS		 1345 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1346 info->phc_index == -1)
ef9814de
EBE		 1347 return 0;
1348
47654204
AH		 1349 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1350 SOF_TIMESTAMPING_RX_HARDWARE |
1351 SOF_TIMESTAMPING_RAW_HARDWARE;
ef9814de 1352
f0b38117
MD		 1353 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1354 BIT(HWTSTAMP_TX_ON);
ef9814de 1355
f0b38117
MD		 1356 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1357 BIT(HWTSTAMP_FILTER_ALL);
ef9814de
EBE		 1358
1359 return 0;
1360}
1361
3844b07e
FD		 1362static int mlx5e_get_ts_info(struct net_device *dev,
1363 struct ethtool_ts_info *info)
1364{
1365 struct mlx5e_priv *priv = netdev_priv(dev);
1366
1367 return mlx5e_ethtool_get_ts_info(priv, info);
1368}
1369
928cfe87
TT		 1370static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1371{
1372 __u32 ret = 0;
1373
1374 if (MLX5_CAP_GEN(mdev, wol_g))
1375 ret |= WAKE_MAGIC;
1376
1377 if (MLX5_CAP_GEN(mdev, wol_s))
1378 ret |= WAKE_MAGICSECURE;
1379
1380 if (MLX5_CAP_GEN(mdev, wol_a))
1381 ret |= WAKE_ARP;
1382
1383 if (MLX5_CAP_GEN(mdev, wol_b))
1384 ret |= WAKE_BCAST;
1385
1386 if (MLX5_CAP_GEN(mdev, wol_m))
1387 ret |= WAKE_MCAST;
1388
1389 if (MLX5_CAP_GEN(mdev, wol_u))
1390 ret |= WAKE_UCAST;
1391
1392 if (MLX5_CAP_GEN(mdev, wol_p))
1393 ret |= WAKE_PHY;
1394
1395 return ret;
1396}
1397
1398static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1399{
1400 __u32 ret = 0;
1401
1402 if (mode & MLX5_WOL_MAGIC)
1403 ret |= WAKE_MAGIC;
1404
1405 if (mode & MLX5_WOL_SECURED_MAGIC)
1406 ret |= WAKE_MAGICSECURE;
1407
1408 if (mode & MLX5_WOL_ARP)
1409 ret |= WAKE_ARP;
1410
1411 if (mode & MLX5_WOL_BROADCAST)
1412 ret |= WAKE_BCAST;
1413
1414 if (mode & MLX5_WOL_MULTICAST)
1415 ret |= WAKE_MCAST;
1416
1417 if (mode & MLX5_WOL_UNICAST)
1418 ret |= WAKE_UCAST;
1419
1420 if (mode & MLX5_WOL_PHY_ACTIVITY)
1421 ret |= WAKE_PHY;
1422
1423 return ret;
1424}
1425
1426static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1427{
1428 u8 ret = 0;
1429
1430 if (mode & WAKE_MAGIC)
1431 ret |= MLX5_WOL_MAGIC;
1432
1433 if (mode & WAKE_MAGICSECURE)
1434 ret |= MLX5_WOL_SECURED_MAGIC;
1435
1436 if (mode & WAKE_ARP)
1437 ret |= MLX5_WOL_ARP;
1438
1439 if (mode & WAKE_BCAST)
1440 ret |= MLX5_WOL_BROADCAST;
1441
1442 if (mode & WAKE_MCAST)
1443 ret |= MLX5_WOL_MULTICAST;
1444
1445 if (mode & WAKE_UCAST)
1446 ret |= MLX5_WOL_UNICAST;
1447
1448 if (mode & WAKE_PHY)
1449 ret |= MLX5_WOL_PHY_ACTIVITY;
1450
1451 return ret;
1452}
1453
1454static void mlx5e_get_wol(struct net_device *netdev,
1455 struct ethtool_wolinfo *wol)
1456{
1457 struct mlx5e_priv *priv = netdev_priv(netdev);
1458 struct mlx5_core_dev *mdev = priv->mdev;
1459 u8 mlx5_wol_mode;
1460 int err;
1461
1462 memset(wol, 0, sizeof(*wol));
1463
1464 wol->supported = mlx5e_get_wol_supported(mdev);
1465 if (!wol->supported)
1466 return;
1467
1468 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1469 if (err)
1470 return;
1471
1472 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1473}
1474
1475static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1476{
1477 struct mlx5e_priv *priv = netdev_priv(netdev);
1478 struct mlx5_core_dev *mdev = priv->mdev;
1479 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1480 u32 mlx5_wol_mode;
1481
1482 if (!wol_supported)
9eb78923 1483 return -EOPNOTSUPP;
928cfe87
TT		 1484
1485 if (wol->wolopts & ~wol_supported)
1486 return -EINVAL;
1487
1488 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1489
1490 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1491}
1492
6cfa9460
SA		 1493static int mlx5e_get_fecparam(struct net_device *netdev,
1494 struct ethtool_fecparam *fecparam)
1495{
1496 struct mlx5e_priv *priv = netdev_priv(netdev);
1497 struct mlx5_core_dev *mdev = priv->mdev;
1498 u8 fec_configured = 0;
1499 u32 fec_active = 0;
1500 int err;
1501
1502 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1503
1504 if (err)
1505 return err;
1506
1507 fecparam->active_fec = pplm2ethtool_fec((u_long)fec_active,
1508 sizeof(u32) * BITS_PER_BYTE);
1509
1510 if (!fecparam->active_fec)
1511 return -EOPNOTSUPP;
1512
1513 fecparam->fec = pplm2ethtool_fec((u_long)fec_configured,
1514 sizeof(u8) * BITS_PER_BYTE);
1515
1516 return 0;
1517}
1518
1519static int mlx5e_set_fecparam(struct net_device *netdev,
1520 struct ethtool_fecparam *fecparam)
1521{
1522 struct mlx5e_priv *priv = netdev_priv(netdev);
1523 struct mlx5_core_dev *mdev = priv->mdev;
1524 u8 fec_policy = 0;
1525 int mode;
1526 int err;
1527
1528 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1529 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1530 continue;
1531 fec_policy |= (1 << mode);
1532 break;
1533 }
1534
1535 err = mlx5e_set_fec_mode(mdev, fec_policy);
1536
1537 if (err)
1538 return err;
1539
1540 mlx5_toggle_port_link(mdev);
1541
1542 return 0;
1543}
1544
79c48764
GP		 1545static u32 mlx5e_get_msglevel(struct net_device *dev)
1546{
1547 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1548}
1549
1550static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1551{
1552 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1553}
1554
da54d24e
GP		 1555static int mlx5e_set_phys_id(struct net_device *dev,
1556 enum ethtool_phys_id_state state)
1557{
1558 struct mlx5e_priv *priv = netdev_priv(dev);
1559 struct mlx5_core_dev *mdev = priv->mdev;
1560 u16 beacon_duration;
1561
1562 if (!MLX5_CAP_GEN(mdev, beacon_led))
1563 return -EOPNOTSUPP;
1564
1565 switch (state) {
1566 case ETHTOOL_ID_ACTIVE:
1567 beacon_duration = MLX5_BEACON_DURATION_INF;
1568 break;
1569 case ETHTOOL_ID_INACTIVE:
1570 beacon_duration = MLX5_BEACON_DURATION_OFF;
1571 break;
1572 default:
1573 return -EOPNOTSUPP;
1574 }
1575
1576 return mlx5_set_port_beacon(mdev, beacon_duration);
1577}
1578
bb64143e
GP		 1579static int mlx5e_get_module_info(struct net_device *netdev,
1580 struct ethtool_modinfo *modinfo)
1581{
1582 struct mlx5e_priv *priv = netdev_priv(netdev);
1583 struct mlx5_core_dev *dev = priv->mdev;
1584 int size_read = 0;
a708fb7b 1585 u8 data[4] = {0};
bb64143e
GP		 1586
1587 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1588 if (size_read < 2)
1589 return -EIO;
1590
1591 /* data[0] = identifier byte */
1592 switch (data[0]) {
1593 case MLX5_MODULE_ID_QSFP:
1594 modinfo->type = ETH_MODULE_SFF_8436;
a708fb7b 1595 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
bb64143e
GP		 1596 break;
1597 case MLX5_MODULE_ID_QSFP_PLUS:
1598 case MLX5_MODULE_ID_QSFP28:
1599 /* data[1] = revision id */
1600 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1601 modinfo->type = ETH_MODULE_SFF_8636;
a708fb7b 1602 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
bb64143e
GP		 1603 } else {
1604 modinfo->type = ETH_MODULE_SFF_8436;
a708fb7b 1605 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
bb64143e
GP		 1606 }
1607 break;
1608 case MLX5_MODULE_ID_SFP:
1609 modinfo->type = ETH_MODULE_SFF_8472;
ace329f4 1610 modinfo->eeprom_len = MLX5_EEPROM_PAGE_LENGTH;
bb64143e
GP		 1611 break;
1612 default:
1613 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1614 __func__, data[0]);
1615 return -EINVAL;
1616 }
1617
1618 return 0;
1619}
1620
1621static int mlx5e_get_module_eeprom(struct net_device *netdev,
1622 struct ethtool_eeprom *ee,
1623 u8 *data)
1624{
1625 struct mlx5e_priv *priv = netdev_priv(netdev);
1626 struct mlx5_core_dev *mdev = priv->mdev;
1627 int offset = ee->offset;
1628 int size_read;
1629 int i = 0;
1630
1631 if (!ee->len)
1632 return -EINVAL;
1633
1634 memset(data, 0, ee->len);
1635
1636 while (i < ee->len) {
1637 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1638 data + i);
1639
1640 if (!size_read)
1641 /* Done reading */
1642 return 0;
1643
1644 if (size_read < 0) {
1645 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1646 __func__, size_read);
1647 return 0;
1648 }
1649
1650 i += size_read;
1651 offset += size_read;
1652 }
1653
1654 return 0;
1655}
1656
0088cbbc
TG		 1657static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1658 bool is_rx_cq)
4e59e288 1659{
9908aa29
TT		 1660 struct mlx5e_priv *priv = netdev_priv(netdev);
1661 struct mlx5_core_dev *mdev = priv->mdev;
be7e87f9 1662 struct mlx5e_channels new_channels = {};
0088cbbc
TG		 1663 bool mode_changed;
1664 u8 cq_period_mode, current_cq_period_mode;
9908aa29 1665
0088cbbc 1666 cq_period_mode = enable ?
9908aa29
TT		 1667 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1668 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
0088cbbc
TG		 1669 current_cq_period_mode = is_rx_cq ?
1670 priv->channels.params.rx_cq_moderation.cq_period_mode :
1671 priv->channels.params.tx_cq_moderation.cq_period_mode;
1672 mode_changed = cq_period_mode != current_cq_period_mode;
9908aa29 1673
0088cbbc 1674 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
9908aa29 1675 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
9eb78923 1676 return -EOPNOTSUPP;
9908aa29 1677
0088cbbc 1678 if (!mode_changed)
9908aa29
TT		 1679 return 0;
1680
be7e87f9 1681 new_channels.params = priv->channels.params;
0088cbbc
TG		 1682 if (is_rx_cq)
1683 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1684 else
1685 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
9908aa29 1686
be7e87f9
SM		 1687 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1688 priv->channels.params = new_channels.params;
1689 return 0;
1690 }
1691
877662e2 1692 return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
be7e87f9 1693}
9908aa29 1694
0088cbbc
TG		 1695static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1696{
1697 return set_pflag_cqe_based_moder(netdev, enable, false);
1698}
1699
1700static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1701{
1702 return set_pflag_cqe_based_moder(netdev, enable, true);
1703}
1704
be7e87f9
SM		 1705int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1706{
1707 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1708 struct mlx5e_channels new_channels = {};
1709 int err = 0;
1710
1711 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1712 return new_val ? -EOPNOTSUPP : 0;
1713
1714 if (curr_val == new_val)
1715 return 0;
1716
1717 new_channels.params = priv->channels.params;
1718 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1719
be7e87f9
SM		 1720 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1721 priv->channels.params = new_channels.params;
1722 return 0;
1723 }
1724
877662e2 1725 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
be7e87f9
SM		 1726 if (err)
1727 return err;
1728
696a97cf
EE		 1729 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1730 MLX5E_GET_PFLAG(&priv->channels.params,
1731 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1732
be7e87f9 1733 return 0;
4e59e288
GP		 1734}
1735
9bcc8606
SD		 1736static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1737 bool enable)
1738{
1739 struct mlx5e_priv *priv = netdev_priv(netdev);
1740 struct mlx5_core_dev *mdev = priv->mdev;
9bcc8606
SD		 1741
1742 if (!MLX5_CAP_GEN(mdev, cqe_compression))
9eb78923 1743 return -EOPNOTSUPP;
9bcc8606 1744
7c39afb3 1745 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
9bcc8606
SD		 1746 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1747 return -EINVAL;
1748 }
1749
5eb0249b 1750 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
6a9764ef 1751 priv->channels.params.rx_cqe_compress_def = enable;
9bcc8606 1752
5eb0249b 1753 return 0;
9bcc8606
SD		 1754}
1755
2ccb0a79
TT		 1756static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1757{
1758 struct mlx5e_priv *priv = netdev_priv(netdev);
1759 struct mlx5_core_dev *mdev = priv->mdev;
1760 struct mlx5e_channels new_channels = {};
2ccb0a79
TT		 1761
1762 if (enable) {
1763 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1764 return -EOPNOTSUPP;
1765 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1766 return -EINVAL;
6c3a823e
TT		 1767 } else if (priv->channels.params.lro_en) {
1768 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n");
1769 return -EINVAL;
2ccb0a79
TT		 1770 }
1771
1772 new_channels.params = priv->channels.params;
1773
1774 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1775 mlx5e_set_rq_type(mdev, &new_channels.params);
1776
1777 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1778 priv->channels.params = new_channels.params;
1779 return 0;
1780 }
1781
877662e2 1782 return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
2ccb0a79
TT		 1783}
1784
b856df28
OG		 1785static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
1786{
1787 struct mlx5e_priv *priv = netdev_priv(netdev);
1788 struct mlx5e_channels *channels = &priv->channels;
1789 struct mlx5e_channel *c;
1790 int i;
1791
5d0bb3ba
SM		 1792 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) ||
1793 priv->channels.params.xdp_prog)
b856df28
OG		 1794 return 0;
1795
1796 for (i = 0; i < channels->num; i++) {
1797 c = channels->c[i];
1798 if (enable)
1799 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1800 else
1801 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1802 }
1803
1804 return 0;
1805}
1806
6277053a
TT		 1807static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
1808{
1809 struct mlx5e_priv *priv = netdev_priv(netdev);
1810 struct mlx5_core_dev *mdev = priv->mdev;
1811 struct mlx5e_channels new_channels = {};
1812 int err;
1813
1814 if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1815 return -EOPNOTSUPP;
1816
1817 new_channels.params = priv->channels.params;
1818
1819 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
1820
1821 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1822 priv->channels.params = new_channels.params;
1823 return 0;
1824 }
1825
877662e2
TT		 1826 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
1827 return err;
6277053a
TT		 1828}
1829
8ff57c18
TT		 1830static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
1831 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
1832 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
1833 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
1834 { "rx_striding_rq", set_pflag_rx_striding_rq },
1835 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
6277053a 1836 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
8ff57c18
TT		 1837};
1838
4e59e288
GP		 1839static int mlx5e_handle_pflag(struct net_device *netdev,
1840 u32 wanted_flags,
8ff57c18 1841 enum mlx5e_priv_flag flag)
4e59e288
GP		 1842{
1843 struct mlx5e_priv *priv = netdev_priv(netdev);
8ff57c18 1844 bool enable = !!(wanted_flags & BIT(flag));
6a9764ef 1845 u32 changes = wanted_flags ^ priv->channels.params.pflags;
4e59e288
GP		 1846 int err;
1847
8ff57c18 1848 if (!(changes & BIT(flag)))
4e59e288
GP		 1849 return 0;
1850
8ff57c18 1851 err = mlx5e_priv_flags[flag].handler(netdev, enable);
4e59e288 1852 if (err) {
8ff57c18
TT		 1853 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
1854 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
4e59e288
GP		 1855 return err;
1856 }
1857
6a9764ef 1858 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
4e59e288
GP		 1859 return 0;
1860}
1861
1862static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1863{
1864 struct mlx5e_priv *priv = netdev_priv(netdev);
8ff57c18 1865 enum mlx5e_priv_flag pflag;
4e59e288
GP		 1866 int err;
1867
1868 mutex_lock(&priv->state_lock);
2ccb0a79 1869
8ff57c18
TT		 1870 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
1871 err = mlx5e_handle_pflag(netdev, pflags, pflag);
1872 if (err)
1873 break;
1874 }
9bcc8606 1875
4e59e288 1876 mutex_unlock(&priv->state_lock);
6c3a823e
TT		 1877
1878 /* Need to fix some features.. */
1879 netdev_update_features(netdev);
1880
9bcc8606 1881 return err;
4e59e288
GP		 1882}
1883
1884static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1885{
1886 struct mlx5e_priv *priv = netdev_priv(netdev);
1887
6a9764ef 1888 return priv->channels.params.pflags;
4e59e288
GP		 1889}
1890
8f0916c6
SM		 1891#ifndef CONFIG_MLX5_EN_RXNFC
1892/* When CONFIG_MLX5_EN_RXNFC=n we only support ETHTOOL_GRXRINGS
1893 * otherwise this function will be defined from en_fs_ethtool.c
1894 */
1895static int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, u32 *rule_locs)
1896{
1897 struct mlx5e_priv *priv = netdev_priv(dev);
1898
1899 if (info->cmd != ETHTOOL_GRXRINGS)
1900 return -EOPNOTSUPP;
1901 /* ring_count is needed by ethtool -x */
1902 info->data = priv->channels.params.num_channels;
1903 return 0;
1904}
1905#endif
1906
f62b8bb8
AV		 1907const struct ethtool_ops mlx5e_ethtool_ops = {
1908 .get_drvinfo = mlx5e_get_drvinfo,
1909 .get_link = ethtool_op_get_link,
1910 .get_strings = mlx5e_get_strings,
1911 .get_sset_count = mlx5e_get_sset_count,
1912 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1913 .get_ringparam = mlx5e_get_ringparam,
1914 .set_ringparam = mlx5e_set_ringparam,
1915 .get_channels = mlx5e_get_channels,
1916 .set_channels = mlx5e_set_channels,
1917 .get_coalesce = mlx5e_get_coalesce,
1918 .set_coalesce = mlx5e_set_coalesce,
665bc539
GP		 1919 .get_link_ksettings = mlx5e_get_link_ksettings,
1920 .set_link_ksettings = mlx5e_set_link_ksettings,
2d75b2bc
AS		 1921 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1922 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2be6967c
SM		 1923 .get_rxfh = mlx5e_get_rxfh,
1924 .set_rxfh = mlx5e_set_rxfh,
2d75b2bc 1925 .get_rxnfc = mlx5e_get_rxnfc,
8f0916c6 1926#ifdef CONFIG_MLX5_EN_RXNFC
6dc6071c 1927 .set_rxnfc = mlx5e_set_rxnfc,
fe6d86b3 1928#endif
58d52291
AS		 1929 .get_tunable = mlx5e_get_tunable,
1930 .set_tunable = mlx5e_set_tunable,
3c2d18ef
AS		 1931 .get_pauseparam = mlx5e_get_pauseparam,
1932 .set_pauseparam = mlx5e_set_pauseparam,
ef9814de 1933 .get_ts_info = mlx5e_get_ts_info,
da54d24e 1934 .set_phys_id = mlx5e_set_phys_id,
928cfe87
TT		 1935 .get_wol = mlx5e_get_wol,
1936 .set_wol = mlx5e_set_wol,
bb64143e
GP		 1937 .get_module_info = mlx5e_get_module_info,
1938 .get_module_eeprom = mlx5e_get_module_eeprom,
4e59e288 1939 .get_priv_flags = mlx5e_get_priv_flags,
d605d668
KH		 1940 .set_priv_flags = mlx5e_set_priv_flags,
1941 .self_test = mlx5e_self_test,
79c48764
GP		 1942 .get_msglevel = mlx5e_get_msglevel,
1943 .set_msglevel = mlx5e_set_msglevel,
6cfa9460
SA		 1944 .get_fecparam = mlx5e_get_fecparam,
1945 .set_fecparam = mlx5e_set_fecparam,
f62b8bb8 1946};
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