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net/mlx5: ethtool, Fix type analysis of advertised link-mode
[thirdparty/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "en.h"
2c81bfd5 34#include "en/port.h"
6dbc80ca 35#include "lib/clock.h"
f62b8bb8 36
076b0936
ES		 37void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
38 struct ethtool_drvinfo *drvinfo)
f62b8bb8 39{
f62b8bb8
AV		 40 struct mlx5_core_dev *mdev = priv->mdev;
41
42 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
7913d205 43 strlcpy(drvinfo->version, DRIVER_VERSION,
f62b8bb8
AV		 44 sizeof(drvinfo->version));
45 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
84e11edb
IK		 46 "%d.%d.%04d (%.16s)",
47 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
48 mdev->board_id);
f62b8bb8
AV		 49 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
50 sizeof(drvinfo->bus_info));
51}
52
076b0936
ES		 53static void mlx5e_get_drvinfo(struct net_device *dev,
54 struct ethtool_drvinfo *drvinfo)
55{
56 struct mlx5e_priv *priv = netdev_priv(dev);
57
58 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
59}
60
665bc539
GP		 61struct ptys2ethtool_config {
62 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
63 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
f62b8bb8
AV		 64};
65
6a897372
AL		 66static
67struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
68static
69struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
665bc539 70
6a897372 71#define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \
665bc539
GP		 72 ({ \
73 struct ptys2ethtool_config *cfg; \
74 const unsigned int modes[] = { __VA_ARGS__ }; \
6a897372
AL		 75 unsigned int i, bit, idx; \
76 cfg = &ptys2##table##_ethtool_table[reg_]; \
665bc539
GP		 77 bitmap_zero(cfg->supported, \
78 __ETHTOOL_LINK_MODE_MASK_NBITS); \
79 bitmap_zero(cfg->advertised, \
80 __ETHTOOL_LINK_MODE_MASK_NBITS); \
81 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
6a897372
AL		 82 bit = modes[i] % 64; \
83 idx = modes[i] / 64; \
84 __set_bit(bit, &cfg->supported[idx]); \
85 __set_bit(bit, &cfg->advertised[idx]); \
665bc539
GP		 86 } \
87 })
88
89void mlx5e_build_ptys2ethtool_map(void)
90{
6a897372
AL		 91 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
92 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
93 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
665bc539 94 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
6a897372 95 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
665bc539 96 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
6a897372 97 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
665bc539 98 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
6a897372 99 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
665bc539 100 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
6a897372 101 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
665bc539 102 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
6a897372 103 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
665bc539 104 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
6a897372 105 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
665bc539 106 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
6a897372 107 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
665bc539 108 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
6a897372 109 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
665bc539 110 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
6a897372 111 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
665bc539 112 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
6a897372 113 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
665bc539 114 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
6a897372 115 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
665bc539 116 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
6a897372 117 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
665bc539 118 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
6a897372 119 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
665bc539 120 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
6a897372 121 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
665bc539 122 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
6a897372 123 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
665bc539 124 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
6a897372 125 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
665bc539 126 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
6a897372 127 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
665bc539 128 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
6a897372 129 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
665bc539 130 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
6a897372 131 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
665bc539 132 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
6a897372 133 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
665bc539 134 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
6a897372 135 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
665bc539 136 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
6a897372 137 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
665bc539 138 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
6a897372 139 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
665bc539 140 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
6a897372 141 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
665bc539 142 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
6a897372
AL		 143 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
144 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
145 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
146 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
147 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
148 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
149 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
150 ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
151 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
152 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
153 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
154 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
155 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
156 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
157 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
158 ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
159 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
160 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
161 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
162 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
163 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
164 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
165 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
166 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
167 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
168 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
169 ext,
170 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
171 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
172 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
173 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
174 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
175 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
176 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
177 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
178 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
179 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
180 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
181 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
182 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
183 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
184 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
185 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
186 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
187 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
188 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
189 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
190 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
191 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
192 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
193 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
194 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
195 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
196}
197
198static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
199 struct ptys2ethtool_config **arr,
200 u32 *size)
201{
202 bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
203
204 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
205 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
206 ARRAY_SIZE(ptys2legacy_ethtool_table);
665bc539
GP		 207}
208
8ff57c18
TT		 209typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
210
211struct pflag_desc {
212 char name[ETH_GSTRING_LEN];
213 mlx5e_pflag_handler handler;
d2408205
KH		 214};
215
8ff57c18
TT		 216static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
217
076b0936 218int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
f62b8bb8 219{
c0752f2b
KH		 220 int i, num_stats = 0;
221
f62b8bb8
AV		 222 switch (sset) {
223 case ETH_SS_STATS:
c0752f2b
KH		 224 for (i = 0; i < mlx5e_num_stats_grps; i++)
225 num_stats += mlx5e_stats_grps[i].get_num_stats(priv);
1fe85006 226 return num_stats;
4e59e288 227 case ETH_SS_PRIV_FLAGS:
8ff57c18 228 return MLX5E_NUM_PFLAGS;
d605d668
KH		 229 case ETH_SS_TEST:
230 return mlx5e_self_test_num(priv);
f62b8bb8
AV		 231 /* fallthrough */
232 default:
233 return -EOPNOTSUPP;
234 }
235}
236
076b0936
ES		 237static int mlx5e_get_sset_count(struct net_device *dev, int sset)
238{
239 struct mlx5e_priv *priv = netdev_priv(dev);
240
241 return mlx5e_ethtool_get_sset_count(priv, sset);
242}
243
c045deef 244static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, u8 *data)
9218b44d 245{
1fe85006 246 int i, idx = 0;
9218b44d 247
c0752f2b
KH		 248 for (i = 0; i < mlx5e_num_stats_grps; i++)
249 idx = mlx5e_stats_grps[i].fill_strings(priv, data, idx);
9218b44d
GP		 250}
251
c045deef 252void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
f62b8bb8 253{
4e59e288 254 int i;
f62b8bb8
AV		 255
256 switch (stringset) {
257 case ETH_SS_PRIV_FLAGS:
8ff57c18
TT		 258 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
259 strcpy(data + i * ETH_GSTRING_LEN,
260 mlx5e_priv_flags[i].name);
f62b8bb8
AV		 261 break;
262
263 case ETH_SS_TEST:
d605d668
KH		 264 for (i = 0; i < mlx5e_self_test_num(priv); i++)
265 strcpy(data + i * ETH_GSTRING_LEN,
266 mlx5e_self_tests[i]);
f62b8bb8
AV		 267 break;
268
269 case ETH_SS_STATS:
9218b44d 270 mlx5e_fill_stats_strings(priv, data);
f62b8bb8
AV		 271 break;
272 }
273}
274
c045deef 275static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
f62b8bb8
AV		 276{
277 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 278
279 mlx5e_ethtool_get_strings(priv, stringset, data);
280}
281
282void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
283 struct ethtool_stats *stats, u64 *data)
284{
1fe85006 285 int i, idx = 0;
f62b8bb8 286
f62b8bb8 287 mutex_lock(&priv->state_lock);
19386177 288 mlx5e_update_stats(priv);
f62b8bb8
AV		 289 mutex_unlock(&priv->state_lock);
290
c0752f2b
KH		 291 for (i = 0; i < mlx5e_num_stats_grps; i++)
292 idx = mlx5e_stats_grps[i].fill_stats(priv, data, idx);
f62b8bb8
AV		 293}
294
076b0936
ES		 295static void mlx5e_get_ethtool_stats(struct net_device *dev,
296 struct ethtool_stats *stats,
297 u64 *data)
298{
299 struct mlx5e_priv *priv = netdev_priv(dev);
300
301 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
302}
303
076b0936
ES		 304void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
305 struct ethtool_ringparam *param)
f62b8bb8 306{
73281b78 307 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
f62b8bb8 308 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
73281b78 309 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
6a9764ef 310 param->tx_pending = 1 << priv->channels.params.log_sq_size;
f62b8bb8
AV		 311}
312
076b0936
ES		 313static void mlx5e_get_ringparam(struct net_device *dev,
314 struct ethtool_ringparam *param)
f62b8bb8
AV		 315{
316 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 317
318 mlx5e_ethtool_get_ringparam(priv, param);
319}
320
321int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
322 struct ethtool_ringparam *param)
323{
546f18ed 324 struct mlx5e_channels new_channels = {};
f62b8bb8
AV		 325 u8 log_rq_size;
326 u8 log_sq_size;
327 int err = 0;
328
329 if (param->rx_jumbo_pending) {
076b0936 330 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
f62b8bb8
AV		 331 __func__);
332 return -EINVAL;
333 }
334 if (param->rx_mini_pending) {
076b0936 335 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
f62b8bb8
AV		 336 __func__);
337 return -EINVAL;
338 }
cc8e9ebf 339
73281b78 340 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
076b0936 341 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
f62b8bb8 342 __func__, param->rx_pending,
73281b78 343 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
fe4c988b
SM		 344 return -EINVAL;
345 }
346
f62b8bb8 347 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
076b0936 348 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
f62b8bb8
AV		 349 __func__, param->tx_pending,
350 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
351 return -EINVAL;
352 }
f62b8bb8 353
73281b78 354 log_rq_size = order_base_2(param->rx_pending);
f62b8bb8 355 log_sq_size = order_base_2(param->tx_pending);
f62b8bb8 356
73281b78 357 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
6a9764ef 358 log_sq_size == priv->channels.params.log_sq_size)
f62b8bb8
AV		 359 return 0;
360
361 mutex_lock(&priv->state_lock);
98e81b0a 362
546f18ed 363 new_channels.params = priv->channels.params;
73281b78 364 new_channels.params.log_rq_mtu_frames = log_rq_size;
546f18ed 365 new_channels.params.log_sq_size = log_sq_size;
98e81b0a 366
546f18ed
SM		 367 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
368 priv->channels.params = new_channels.params;
369 goto unlock;
370 }
98e81b0a 371
877662e2 372 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
98e81b0a 373
546f18ed 374unlock:
f62b8bb8
AV		 375 mutex_unlock(&priv->state_lock);
376
377 return err;
378}
379
076b0936
ES		 380static int mlx5e_set_ringparam(struct net_device *dev,
381 struct ethtool_ringparam *param)
f62b8bb8
AV		 382{
383 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 384
076b0936
ES		 385 return mlx5e_ethtool_set_ringparam(priv, param);
386}
387
388void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
389 struct ethtool_channels *ch)
390{
779d986d 391 ch->max_combined = mlx5e_get_netdev_max_channels(priv->netdev);
6a9764ef 392 ch->combined_count = priv->channels.params.num_channels;
f62b8bb8
AV		 393}
394
076b0936
ES		 395static void mlx5e_get_channels(struct net_device *dev,
396 struct ethtool_channels *ch)
f62b8bb8
AV		 397{
398 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 399
400 mlx5e_ethtool_get_channels(priv, ch);
401}
402
403int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
404 struct ethtool_channels *ch)
405{
f62b8bb8 406 unsigned int count = ch->combined_count;
55c2503d 407 struct mlx5e_channels new_channels = {};
45bf454a 408 bool arfs_enabled;
f62b8bb8
AV		 409 int err = 0;
410
411 if (!count) {
076b0936 412 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
f62b8bb8
AV		 413 __func__);
414 return -EINVAL;
415 }
f62b8bb8 416
6a9764ef 417 if (priv->channels.params.num_channels == count)
f62b8bb8
AV		 418 return 0;
419
420 mutex_lock(&priv->state_lock);
98e81b0a 421
55c2503d
SM		 422 new_channels.params = priv->channels.params;
423 new_channels.params.num_channels = count;
55c2503d
SM		 424
425 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
426 priv->channels.params = new_channels.params;
c475e11e
TT		 427 if (!netif_is_rxfh_configured(priv->netdev))
428 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
429 MLX5E_INDIR_RQT_SIZE, count);
55c2503d
SM		 430 goto out;
431 }
432
076b0936 433 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
45bf454a
MG		 434 if (arfs_enabled)
435 mlx5e_arfs_disable(priv);
436
fb35c534
MP		 437 if (!netif_is_rxfh_configured(priv->netdev))
438 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
439 MLX5E_INDIR_RQT_SIZE, count);
440
55c2503d 441 /* Switch to new channels, set new parameters and close old ones */
877662e2 442 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
45bf454a
MG		 443
444 if (arfs_enabled) {
877662e2
TT		 445 int err2 = mlx5e_arfs_enable(priv);
446
447 if (err2)
076b0936 448 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
877662e2 449 __func__, err2);
45bf454a 450 }
98e81b0a 451
45bf454a 452out:
f62b8bb8
AV		 453 mutex_unlock(&priv->state_lock);
454
455 return err;
456}
457
076b0936
ES		 458static int mlx5e_set_channels(struct net_device *dev,
459 struct ethtool_channels *ch)
f62b8bb8 460{
076b0936
ES		 461 struct mlx5e_priv *priv = netdev_priv(dev);
462
463 return mlx5e_ethtool_set_channels(priv, ch);
464}
f62b8bb8 465
076b0936
ES		 466int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
467 struct ethtool_coalesce *coal)
468{
cbce4f44
TG		 469 struct net_dim_cq_moder *rx_moder, *tx_moder;
470
7524a5d8 471 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
9eb78923 472 return -EOPNOTSUPP;
7524a5d8 473
cbce4f44
TG		 474 rx_moder = &priv->channels.params.rx_cq_moderation;
475 coal->rx_coalesce_usecs = rx_moder->usec;
476 coal->rx_max_coalesced_frames = rx_moder->pkts;
477 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
478
479 tx_moder = &priv->channels.params.tx_cq_moderation;
480 coal->tx_coalesce_usecs = tx_moder->usec;
481 coal->tx_max_coalesced_frames = tx_moder->pkts;
482 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
f62b8bb8
AV		 483
484 return 0;
485}
486
076b0936
ES		 487static int mlx5e_get_coalesce(struct net_device *netdev,
488 struct ethtool_coalesce *coal)
489{
490 struct mlx5e_priv *priv = netdev_priv(netdev);
491
492 return mlx5e_ethtool_get_coalesce(priv, coal);
493}
494
b392a207
MS		 495#define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
496#define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
497
546f18ed
SM		 498static void
499mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
f62b8bb8 500{
f62b8bb8 501 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 502 int tc;
503 int i;
504
ff9c852f
SM		 505 for (i = 0; i < priv->channels.num; ++i) {
506 struct mlx5e_channel *c = priv->channels.c[i];
f62b8bb8
AV		 507
508 for (tc = 0; tc < c->num_tc; tc++) {
509 mlx5_core_modify_cq_moderation(mdev,
510 &c->sq[tc].cq.mcq,
511 coal->tx_coalesce_usecs,
512 coal->tx_max_coalesced_frames);
513 }
514
515 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
516 coal->rx_coalesce_usecs,
517 coal->rx_max_coalesced_frames);
518 }
546f18ed 519}
f62b8bb8 520
076b0936
ES		 521int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
522 struct ethtool_coalesce *coal)
546f18ed 523{
cbce4f44 524 struct net_dim_cq_moder *rx_moder, *tx_moder;
546f18ed
SM		 525 struct mlx5_core_dev *mdev = priv->mdev;
526 struct mlx5e_channels new_channels = {};
527 int err = 0;
528 bool reset;
cb3c7fd4 529
546f18ed
SM		 530 if (!MLX5_CAP_GEN(mdev, cq_moderation))
531 return -EOPNOTSUPP;
532
b392a207
MS		 533 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
534 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
535 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
536 __func__, MLX5E_MAX_COAL_TIME);
537 return -ERANGE;
538 }
539
540 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
541 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
542 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
543 __func__, MLX5E_MAX_COAL_FRAMES);
544 return -ERANGE;
545 }
546
546f18ed
SM		 547 mutex_lock(&priv->state_lock);
548 new_channels.params = priv->channels.params;
549
cbce4f44
TG		 550 rx_moder = &new_channels.params.rx_cq_moderation;
551 rx_moder->usec = coal->rx_coalesce_usecs;
552 rx_moder->pkts = coal->rx_max_coalesced_frames;
553 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
554
555 tx_moder = &new_channels.params.tx_cq_moderation;
556 tx_moder->usec = coal->tx_coalesce_usecs;
557 tx_moder->pkts = coal->tx_max_coalesced_frames;
558 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
546f18ed
SM		 559
560 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
561 priv->channels.params = new_channels.params;
562 goto out;
563 }
564 /* we are opened */
565
cbce4f44
TG		 566 reset = (!!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled) ||
567 (!!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled);
568
546f18ed
SM		 569 if (!reset) {
570 mlx5e_set_priv_channels_coalesce(priv, coal);
571 priv->channels.params = new_channels.params;
572 goto out;
573 }
574
877662e2 575 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
546f18ed
SM		 576
577out:
2fcb92fb 578 mutex_unlock(&priv->state_lock);
cb3c7fd4 579 return err;
f62b8bb8
AV		 580}
581
076b0936
ES		 582static int mlx5e_set_coalesce(struct net_device *netdev,
583 struct ethtool_coalesce *coal)
584{
585 struct mlx5e_priv *priv = netdev_priv(netdev);
586
587 return mlx5e_ethtool_set_coalesce(priv, coal);
588}
589
6a897372
AL		 590static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev,
591 unsigned long *supported_modes,
665bc539 592 u32 eth_proto_cap)
f62b8bb8 593{
7abc2110 594 unsigned long proto_cap = eth_proto_cap;
6a897372
AL		 595 struct ptys2ethtool_config *table;
596 u32 max_size;
665bc539 597 int proto;
f62b8bb8 598
6a897372
AL		 599 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size);
600 for_each_set_bit(proto, &proto_cap, max_size)
665bc539 601 bitmap_or(supported_modes, supported_modes,
6a897372 602 table[proto].supported,
665bc539 603 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 604}
605
6a897372
AL		 606static void ptys2ethtool_adver_link(struct mlx5_core_dev *mdev,
607 unsigned long *advertising_modes,
665bc539 608 u32 eth_proto_cap)
f62b8bb8 609{
7abc2110 610 unsigned long proto_cap = eth_proto_cap;
6a897372
AL		 611 struct ptys2ethtool_config *table;
612 u32 max_size;
665bc539 613 int proto;
f62b8bb8 614
6a897372
AL		 615 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size);
616 for_each_set_bit(proto, &proto_cap, max_size)
665bc539 617 bitmap_or(advertising_modes, advertising_modes,
6a897372 618 table[proto].advertised,
665bc539 619 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 620}
621
6cfa9460
SA		 622static const u32 pplm_fec_2_ethtool[] = {
623 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
624 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
625 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
626};
627
628static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
629{
630 int mode = 0;
631
632 if (!fec_mode)
633 return ETHTOOL_FEC_AUTO;
634
635 mode = find_first_bit(&fec_mode, size);
636
637 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
638 return pplm_fec_2_ethtool[mode];
639
640 return 0;
641}
642
643/* we use ETHTOOL_FEC_* offset and apply it to ETHTOOL_LINK_MODE_FEC_*_BIT */
644static u32 ethtool_fec2ethtool_caps(u_long ethtool_fec_code)
645{
646 u32 offset;
647
648 offset = find_first_bit(&ethtool_fec_code, sizeof(u32));
649 offset -= ETHTOOL_FEC_OFF_BIT;
650 offset += ETHTOOL_LINK_MODE_FEC_NONE_BIT;
651
652 return offset;
653}
654
655static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
656 struct ethtool_link_ksettings *link_ksettings)
657{
658 u_long fec_caps = 0;
659 u32 active_fec = 0;
660 u32 offset;
661 u32 bitn;
662 int err;
663
664 err = mlx5e_get_fec_caps(dev, (u8 *)&fec_caps);
665 if (err)
666 return (err == -EOPNOTSUPP) ? 0 : err;
667
668 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
669 if (err)
670 return err;
671
672 for_each_set_bit(bitn, &fec_caps, ARRAY_SIZE(pplm_fec_2_ethtool)) {
673 u_long ethtool_bitmask = pplm_fec_2_ethtool[bitn];
674
675 offset = ethtool_fec2ethtool_caps(ethtool_bitmask);
676 __set_bit(offset, link_ksettings->link_modes.supported);
677 }
678
679 active_fec = pplm2ethtool_fec(active_fec, sizeof(u32) * BITS_PER_BYTE);
680 offset = ethtool_fec2ethtool_caps(active_fec);
681 __set_bit(offset, link_ksettings->link_modes.advertising);
682
683 return 0;
684}
685
46e9d0b6
EBE		 686static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
687 u32 eth_proto_cap,
688 u8 connector_type)
f62b8bb8 689{
46e9d0b6
EBE		 690 if (!connector_type || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
691 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
692 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
693 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
694 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
695 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
696 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
697 ethtool_link_ksettings_add_link_mode(link_ksettings,
698 supported,
699 FIBRE);
700 ethtool_link_ksettings_add_link_mode(link_ksettings,
701 advertising,
702 FIBRE);
703 }
704
705 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
706 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
707 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
708 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
709 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
710 ethtool_link_ksettings_add_link_mode(link_ksettings,
711 supported,
712 Backplane);
713 ethtool_link_ksettings_add_link_mode(link_ksettings,
714 advertising,
715 Backplane);
716 }
717 return;
f62b8bb8
AV		 718 }
719
46e9d0b6
EBE		 720 switch (connector_type) {
721 case MLX5E_PORT_TP:
722 ethtool_link_ksettings_add_link_mode(link_ksettings,
723 supported, TP);
724 ethtool_link_ksettings_add_link_mode(link_ksettings,
725 advertising, TP);
726 break;
727 case MLX5E_PORT_AUI:
728 ethtool_link_ksettings_add_link_mode(link_ksettings,
729 supported, AUI);
730 ethtool_link_ksettings_add_link_mode(link_ksettings,
731 advertising, AUI);
732 break;
733 case MLX5E_PORT_BNC:
734 ethtool_link_ksettings_add_link_mode(link_ksettings,
735 supported, BNC);
736 ethtool_link_ksettings_add_link_mode(link_ksettings,
737 advertising, BNC);
738 break;
739 case MLX5E_PORT_MII:
740 ethtool_link_ksettings_add_link_mode(link_ksettings,
741 supported, MII);
742 ethtool_link_ksettings_add_link_mode(link_ksettings,
743 advertising, MII);
744 break;
745 case MLX5E_PORT_FIBRE:
746 ethtool_link_ksettings_add_link_mode(link_ksettings,
747 supported, FIBRE);
748 ethtool_link_ksettings_add_link_mode(link_ksettings,
749 advertising, FIBRE);
750 break;
751 case MLX5E_PORT_DA:
752 ethtool_link_ksettings_add_link_mode(link_ksettings,
753 supported, Backplane);
754 ethtool_link_ksettings_add_link_mode(link_ksettings,
755 advertising, Backplane);
756 break;
757 case MLX5E_PORT_NONE:
758 case MLX5E_PORT_OTHER:
759 default:
760 break;
f62b8bb8 761 }
f62b8bb8
AV		 762}
763
764static void get_speed_duplex(struct net_device *netdev,
765 u32 eth_proto_oper,
665bc539 766 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 767{
a08b4ed1 768 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8
AV		 769 u32 speed = SPEED_UNKNOWN;
770 u8 duplex = DUPLEX_UNKNOWN;
771
772 if (!netif_carrier_ok(netdev))
773 goto out;
774
a08b4ed1 775 speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper);
2c81bfd5
HN		 776 if (!speed) {
777 speed = SPEED_UNKNOWN;
778 goto out;
f62b8bb8 779 }
2c81bfd5
HN		 780
781 duplex = DUPLEX_FULL;
782
f62b8bb8 783out:
665bc539
GP		 784 link_ksettings->base.speed = speed;
785 link_ksettings->base.duplex = duplex;
f62b8bb8
AV		 786}
787
6a897372 788static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
665bc539 789 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 790{
665bc539 791 unsigned long *supported = link_ksettings->link_modes.supported;
6a897372 792 ptys2ethtool_supported_link(mdev, supported, eth_proto_cap);
665bc539 793
665bc539 794 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
f62b8bb8
AV		 795}
796
6a897372
AL		 797static void get_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
798 u8 tx_pause, u8 rx_pause,
665bc539 799 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 800{
665bc539 801 unsigned long *advertising = link_ksettings->link_modes.advertising;
6a897372 802 ptys2ethtool_adver_link(mdev, advertising, eth_proto_cap);
665bc539 803
e3c19503 804 if (rx_pause)
665bc539
GP		 805 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
806 if (tx_pause ^ rx_pause)
807 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
f62b8bb8
AV		 808}
809
5b4793f8
EBE		 810static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
811 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
812 [MLX5E_PORT_NONE] = PORT_NONE,
813 [MLX5E_PORT_TP] = PORT_TP,
814 [MLX5E_PORT_AUI] = PORT_AUI,
815 [MLX5E_PORT_BNC] = PORT_BNC,
816 [MLX5E_PORT_MII] = PORT_MII,
817 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
818 [MLX5E_PORT_DA] = PORT_DA,
819 [MLX5E_PORT_OTHER] = PORT_OTHER,
820 };
821
822static u8 get_connector_port(u32 eth_proto, u8 connector_type)
f62b8bb8 823{
5b4793f8
EBE		 824 if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
825 return ptys2connector_type[connector_type];
826
61bf2125
OG		 827 if (eth_proto &
828 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
829 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
830 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
831 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
832 return PORT_FIBRE;
f62b8bb8
AV		 833 }
834
61bf2125
OG		 835 if (eth_proto &
836 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
837 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
838 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
839 return PORT_DA;
f62b8bb8
AV		 840 }
841
61bf2125
OG		 842 if (eth_proto &
843 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
844 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
845 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
846 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
847 return PORT_NONE;
f62b8bb8
AV		 848 }
849
850 return PORT_OTHER;
851}
852
6a897372 853static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
665bc539 854 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 855{
665bc539
GP		 856 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
857
6a897372 858 ptys2ethtool_adver_link(mdev, lp_advertising, eth_proto_lp);
f62b8bb8
AV		 859}
860
371289b6
OG		 861int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
862 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 863{
f62b8bb8 864 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 865 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
b383b544
GP		 866 u32 rx_pause = 0;
867 u32 tx_pause = 0;
f62b8bb8
AV		 868 u32 eth_proto_cap;
869 u32 eth_proto_admin;
870 u32 eth_proto_lp;
871 u32 eth_proto_oper;
52244d96
GP		 872 u8 an_disable_admin;
873 u8 an_status;
5b4793f8 874 u8 connector_type;
6a897372 875 bool ext;
f62b8bb8
AV		 876 int err;
877
a05bdefa 878 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
f62b8bb8 879 if (err) {
371289b6 880 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
f62b8bb8 881 __func__, err);
6cfa9460 882 goto err_query_regs;
f62b8bb8 883 }
6a897372
AL		 884 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
885 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
886 eth_proto_capability);
887 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
888 eth_proto_admin);
889 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
890 eth_proto_oper);
891 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
892 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
893 an_status = MLX5_GET(ptys_reg, out, an_status);
894 connector_type = MLX5_GET(ptys_reg, out, connector_type);
f62b8bb8 895
b383b544
GP		 896 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
897
665bc539
GP		 898 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
899 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
f62b8bb8 900
6a897372
AL		 901 get_supported(mdev, eth_proto_cap, link_ksettings);
902 get_advertising(mdev, eth_proto_admin, tx_pause, rx_pause, link_ksettings);
371289b6 903 get_speed_duplex(priv->netdev, eth_proto_oper, link_ksettings);
f62b8bb8
AV		 904
905 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
906
5b4793f8
EBE		 907 link_ksettings->base.port = get_connector_port(eth_proto_oper,
908 connector_type);
46e9d0b6
EBE		 909 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
910 connector_type);
6a897372 911 get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
f62b8bb8 912
52244d96
GP		 913 if (an_status == MLX5_AN_COMPLETE)
914 ethtool_link_ksettings_add_link_mode(link_ksettings,
915 lp_advertising, Autoneg);
916
917 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
918 AUTONEG_ENABLE;
919 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
920 Autoneg);
6cfa9460 921
2eb1e425
SA		 922 err = get_fec_supported_advertised(mdev, link_ksettings);
923 if (err) {
371289b6 924 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
6cfa9460 925 __func__, err);
2eb1e425
SA		 926 err = 0; /* don't fail caps query because of FEC error */
927 }
6cfa9460 928
52244d96
GP		 929 if (!an_disable_admin)
930 ethtool_link_ksettings_add_link_mode(link_ksettings,
931 advertising, Autoneg);
932
6cfa9460 933err_query_regs:
f62b8bb8
AV		 934 return err;
935}
936
371289b6
OG		 937static int mlx5e_get_link_ksettings(struct net_device *netdev,
938 struct ethtool_link_ksettings *link_ksettings)
939{
940 struct mlx5e_priv *priv = netdev_priv(netdev);
941
942 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
943}
944
665bc539 945static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
f62b8bb8
AV		 946{
947 u32 i, ptys_modes = 0;
948
949 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
6a897372
AL		 950 if (*ptys2legacy_ethtool_table[i].advertised == 0)
951 continue;
952 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
665bc539
GP		 953 link_modes,
954 __ETHTOOL_LINK_MODE_MASK_NBITS))
f62b8bb8
AV		 955 ptys_modes |= MLX5E_PROT_MASK(i);
956 }
957
958 return ptys_modes;
959}
960
6a897372
AL		 961static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
962{
963 u32 i, ptys_modes = 0;
964 unsigned long modes[2];
965
966 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
967 if (*ptys2ext_ethtool_table[i].advertised == 0)
968 continue;
969 memset(modes, 0, sizeof(modes));
970 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
971 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
972
973 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] &&
974 modes[1] == ptys2ext_ethtool_table[i].advertised[1])
975 ptys_modes |= MLX5E_PROT_MASK(i);
976 }
977 return ptys_modes;
978}
979
371289b6
OG		 980int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
981 const struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 982{
f62b8bb8 983 struct mlx5_core_dev *mdev = priv->mdev;
bc4e12ff 984 struct mlx5e_port_eth_proto eproto;
52244d96
GP		 985 bool an_changes = false;
986 u8 an_disable_admin;
6a897372
AL		 987 bool ext_supported;
988 bool ext_requested;
52244d96
GP		 989 u8 an_disable_cap;
990 bool an_disable;
f62b8bb8 991 u32 link_modes;
52244d96 992 u8 an_status;
f62b8bb8 993 u32 speed;
f62b8bb8
AV		 994 int err;
995
6a897372 996 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
f62b8bb8 997
6a897372
AL		 998#define MLX5E_PTYS_EXT ((1ULL << ETHTOOL_LINK_MODE_50000baseKR_Full_BIT) - 1)
999
8d047bf5
AL		 1000 ext_requested = !!(link_ksettings->link_modes.advertising[0] >
1001 MLX5E_PTYS_EXT ||
1002 link_ksettings->link_modes.advertising[1]);
6a897372
AL		 1003 ext_supported = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
1004
1005 /*when ptys_extended_ethernet is set legacy link modes are deprecated */
1006 if (ext_requested != ext_supported)
1007 return -EPROTONOSUPPORT;
f62b8bb8 1008
6a897372
AL		 1009 speed = link_ksettings->base.speed;
1010 ethtool2ptys_adver_func = ext_requested ?
1011 mlx5e_ethtool2ptys_ext_adver_link :
1012 mlx5e_ethtool2ptys_adver_link;
1013 err = mlx5_port_query_eth_proto(mdev, 1, ext_supported, &eproto);
f62b8bb8 1014 if (err) {
bc4e12ff 1015 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
f62b8bb8
AV		 1016 __func__, err);
1017 goto out;
1018 }
6a897372
AL		 1019 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
1020 ethtool2ptys_adver_func(link_ksettings->link_modes.advertising) :
1021 mlx5e_port_speed2linkmodes(mdev, speed);
f62b8bb8 1022
bc4e12ff 1023 link_modes = link_modes & eproto.cap;
f62b8bb8 1024 if (!link_modes) {
371289b6 1025 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
f62b8bb8
AV		 1026 __func__);
1027 err = -EINVAL;
1028 goto out;
1029 }
1030
bc4e12ff
AL		 1031 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1032 &an_disable_admin);
52244d96
GP		 1033
1034 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
1035 an_changes = ((!an_disable && an_disable_admin) ||
1036 (an_disable && !an_disable_admin));
1037
bc4e12ff 1038 if (!an_changes && link_modes == eproto.admin)
f62b8bb8
AV		 1039 goto out;
1040
6a897372 1041 mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext_supported);
667daeda 1042 mlx5_toggle_port_link(mdev);
f62b8bb8 1043
f62b8bb8
AV		 1044out:
1045 return err;
1046}
1047
371289b6
OG		 1048static int mlx5e_set_link_ksettings(struct net_device *netdev,
1049 const struct ethtool_link_ksettings *link_ksettings)
1050{
1051 struct mlx5e_priv *priv = netdev_priv(netdev);
1052
1053 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1054}
1055
a5355de8
OG		 1056u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1057{
bbeb53b8 1058 return sizeof(priv->rss_params.toeplitz_hash_key);
a5355de8
OG		 1059}
1060
2d75b2bc
AS		 1061static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1062{
1063 struct mlx5e_priv *priv = netdev_priv(netdev);
1064
a5355de8 1065 return mlx5e_ethtool_get_rxfh_key_size(priv);
2d75b2bc
AS		 1066}
1067
a5355de8 1068u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
2d75b2bc
AS		 1069{
1070 return MLX5E_INDIR_RQT_SIZE;
1071}
1072
a5355de8
OG		 1073static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1074{
1075 struct mlx5e_priv *priv = netdev_priv(netdev);
1076
1077 return mlx5e_ethtool_get_rxfh_indir_size(priv);
1078}
1079
2be6967c
SM		 1080static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1081 u8 *hfunc)
1082{
1083 struct mlx5e_priv *priv = netdev_priv(netdev);
bbeb53b8 1084 struct mlx5e_rss_params *rss = &priv->rss_params;
2be6967c 1085
2d75b2bc 1086 if (indir)
bbeb53b8
AL		 1087 memcpy(indir, rss->indirection_rqt,
1088 sizeof(rss->indirection_rqt));
2d75b2bc
AS		 1089
1090 if (key)
bbeb53b8
AL		 1091 memcpy(key, rss->toeplitz_hash_key,
1092 sizeof(rss->toeplitz_hash_key));
2d75b2bc 1093
2be6967c 1094 if (hfunc)
bbeb53b8 1095 *hfunc = rss->hfunc;
2be6967c
SM		 1096
1097 return 0;
1098}
1099
98e81b0a 1100static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
2be6967c
SM		 1101 const u8 *key, const u8 hfunc)
1102{
98e81b0a 1103 struct mlx5e_priv *priv = netdev_priv(dev);
bbeb53b8 1104 struct mlx5e_rss_params *rss = &priv->rss_params;
bdfc028d 1105 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1d3398fa 1106 bool hash_changed = false;
bdfc028d 1107 void *in;
2be6967c 1108
2d75b2bc
AS		 1109 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1110 (hfunc != ETH_RSS_HASH_XOR) &&
2be6967c
SM		 1111 (hfunc != ETH_RSS_HASH_TOP))
1112 return -EINVAL;
1113
1b9a07ee 1114 in = kvzalloc(inlen, GFP_KERNEL);
bdfc028d
TT		 1115 if (!in)
1116 return -ENOMEM;
1117
2be6967c
SM		 1118 mutex_lock(&priv->state_lock);
1119
bbeb53b8
AL		 1120 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) {
1121 rss->hfunc = hfunc;
1d3398fa
GP		 1122 hash_changed = true;
1123 }
1124
a5f97fee 1125 if (indir) {
bbeb53b8
AL		 1126 memcpy(rss->indirection_rqt, indir,
1127 sizeof(rss->indirection_rqt));
a5f97fee
SM		 1128
1129 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1130 u32 rqtn = priv->indir_rqt.rqtn;
1131 struct mlx5e_redirect_rqt_param rrp = {
1132 .is_rss = true,
e270e966
AM		 1133 {
1134 .rss = {
bbeb53b8 1135 .hfunc = rss->hfunc,
e270e966
AM		 1136 .channels = &priv->channels,
1137 },
1138 },
a5f97fee
SM		 1139 };
1140
1141 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1142 }
1143 }
1144
1d3398fa 1145 if (key) {
bbeb53b8
AL		 1146 memcpy(rss->toeplitz_hash_key, key,
1147 sizeof(rss->toeplitz_hash_key));
1148 hash_changed = hash_changed || rss->hfunc == ETH_RSS_HASH_TOP;
1d3398fa 1149 }
2d75b2bc 1150
1d3398fa
GP		 1151 if (hash_changed)
1152 mlx5e_modify_tirs_hash(priv, in, inlen);
2d75b2bc 1153
2be6967c
SM		 1154 mutex_unlock(&priv->state_lock);
1155
bdfc028d
TT		 1156 kvfree(in);
1157
1158 return 0;
2be6967c
SM		 1159}
1160
2afa609f
IK		 1161#define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1162#define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1163#define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1164#define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1165#define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1166 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1167 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1168
1169static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1170 u16 *pfc_prevention_tout)
1171{
1172 struct mlx5e_priv *priv = netdev_priv(netdev);
1173 struct mlx5_core_dev *mdev = priv->mdev;
1174
1175 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1176 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1177 return -EOPNOTSUPP;
1178
1179 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1180}
1181
1182static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1183 u16 pfc_preven)
1184{
1185 struct mlx5e_priv *priv = netdev_priv(netdev);
1186 struct mlx5_core_dev *mdev = priv->mdev;
1187 u16 critical_tout;
1188 u16 minor;
1189
1190 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1191 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1192 return -EOPNOTSUPP;
1193
1194 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1195 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1196 pfc_preven;
1197
1198 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1199 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1200 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1201 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1202 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1203 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1204 return -EINVAL;
1205 }
1206
1207 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1208 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1209 minor);
1210}
1211
58d52291
AS		 1212static int mlx5e_get_tunable(struct net_device *dev,
1213 const struct ethtool_tunable *tuna,
1214 void *data)
1215{
c4554fbc 1216 int err;
58d52291
AS		 1217
1218 switch (tuna->id) {
2afa609f
IK		 1219 case ETHTOOL_PFC_PREVENTION_TOUT:
1220 err = mlx5e_get_pfc_prevention_tout(dev, data);
1221 break;
58d52291
AS		 1222 default:
1223 err = -EINVAL;
1224 break;
1225 }
1226
1227 return err;
1228}
1229
1230static int mlx5e_set_tunable(struct net_device *dev,
1231 const struct ethtool_tunable *tuna,
1232 const void *data)
1233{
1234 struct mlx5e_priv *priv = netdev_priv(dev);
c4554fbc 1235 int err;
546f18ed
SM		 1236
1237 mutex_lock(&priv->state_lock);
58d52291
AS		 1238
1239 switch (tuna->id) {
2afa609f
IK		 1240 case ETHTOOL_PFC_PREVENTION_TOUT:
1241 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
58d52291
AS		 1242 break;
1243 default:
1244 err = -EINVAL;
1245 break;
1246 }
1247
546f18ed 1248 mutex_unlock(&priv->state_lock);
58d52291
AS		 1249 return err;
1250}
1251
371289b6
OG		 1252void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1253 struct ethtool_pauseparam *pauseparam)
3c2d18ef 1254{
3c2d18ef
AS		 1255 struct mlx5_core_dev *mdev = priv->mdev;
1256 int err;
1257
1258 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1259 &pauseparam->tx_pause);
1260 if (err) {
371289b6 1261 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
3c2d18ef
AS		 1262 __func__, err);
1263 }
1264}
1265
371289b6
OG		 1266static void mlx5e_get_pauseparam(struct net_device *netdev,
1267 struct ethtool_pauseparam *pauseparam)
1268{
1269 struct mlx5e_priv *priv = netdev_priv(netdev);
1270
1271 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1272}
1273
1274int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1275 struct ethtool_pauseparam *pauseparam)
3c2d18ef 1276{
3c2d18ef
AS		 1277 struct mlx5_core_dev *mdev = priv->mdev;
1278 int err;
1279
1280 if (pauseparam->autoneg)
1281 return -EINVAL;
1282
1283 err = mlx5_set_port_pause(mdev,
1284 pauseparam->rx_pause ? 1 : 0,
1285 pauseparam->tx_pause ? 1 : 0);
1286 if (err) {
371289b6 1287 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
3c2d18ef
AS		 1288 __func__, err);
1289 }
1290
1291 return err;
1292}
1293
371289b6
OG		 1294static int mlx5e_set_pauseparam(struct net_device *netdev,
1295 struct ethtool_pauseparam *pauseparam)
1296{
1297 struct mlx5e_priv *priv = netdev_priv(netdev);
1298
1299 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1300}
1301
3844b07e
FD		 1302int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1303 struct ethtool_ts_info *info)
ef9814de 1304{
7c39afb3 1305 struct mlx5_core_dev *mdev = priv->mdev;
ef9814de 1306
6dbc80ca 1307 info->phc_index = mlx5_clock_get_ptp_index(mdev);
ef9814de 1308
6dbc80ca
MS		 1309 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1310 info->phc_index == -1)
ef9814de
EBE		 1311 return 0;
1312
47654204
AH		 1313 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1314 SOF_TIMESTAMPING_RX_HARDWARE |
1315 SOF_TIMESTAMPING_RAW_HARDWARE;
ef9814de 1316
f0b38117
MD		 1317 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1318 BIT(HWTSTAMP_TX_ON);
ef9814de 1319
f0b38117
MD		 1320 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1321 BIT(HWTSTAMP_FILTER_ALL);
ef9814de
EBE		 1322
1323 return 0;
1324}
1325
3844b07e
FD		 1326static int mlx5e_get_ts_info(struct net_device *dev,
1327 struct ethtool_ts_info *info)
1328{
1329 struct mlx5e_priv *priv = netdev_priv(dev);
1330
1331 return mlx5e_ethtool_get_ts_info(priv, info);
1332}
1333
928cfe87
TT		 1334static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1335{
1336 __u32 ret = 0;
1337
1338 if (MLX5_CAP_GEN(mdev, wol_g))
1339 ret |= WAKE_MAGIC;
1340
1341 if (MLX5_CAP_GEN(mdev, wol_s))
1342 ret |= WAKE_MAGICSECURE;
1343
1344 if (MLX5_CAP_GEN(mdev, wol_a))
1345 ret |= WAKE_ARP;
1346
1347 if (MLX5_CAP_GEN(mdev, wol_b))
1348 ret |= WAKE_BCAST;
1349
1350 if (MLX5_CAP_GEN(mdev, wol_m))
1351 ret |= WAKE_MCAST;
1352
1353 if (MLX5_CAP_GEN(mdev, wol_u))
1354 ret |= WAKE_UCAST;
1355
1356 if (MLX5_CAP_GEN(mdev, wol_p))
1357 ret |= WAKE_PHY;
1358
1359 return ret;
1360}
1361
1362static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1363{
1364 __u32 ret = 0;
1365
1366 if (mode & MLX5_WOL_MAGIC)
1367 ret |= WAKE_MAGIC;
1368
1369 if (mode & MLX5_WOL_SECURED_MAGIC)
1370 ret |= WAKE_MAGICSECURE;
1371
1372 if (mode & MLX5_WOL_ARP)
1373 ret |= WAKE_ARP;
1374
1375 if (mode & MLX5_WOL_BROADCAST)
1376 ret |= WAKE_BCAST;
1377
1378 if (mode & MLX5_WOL_MULTICAST)
1379 ret |= WAKE_MCAST;
1380
1381 if (mode & MLX5_WOL_UNICAST)
1382 ret |= WAKE_UCAST;
1383
1384 if (mode & MLX5_WOL_PHY_ACTIVITY)
1385 ret |= WAKE_PHY;
1386
1387 return ret;
1388}
1389
1390static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1391{
1392 u8 ret = 0;
1393
1394 if (mode & WAKE_MAGIC)
1395 ret |= MLX5_WOL_MAGIC;
1396
1397 if (mode & WAKE_MAGICSECURE)
1398 ret |= MLX5_WOL_SECURED_MAGIC;
1399
1400 if (mode & WAKE_ARP)
1401 ret |= MLX5_WOL_ARP;
1402
1403 if (mode & WAKE_BCAST)
1404 ret |= MLX5_WOL_BROADCAST;
1405
1406 if (mode & WAKE_MCAST)
1407 ret |= MLX5_WOL_MULTICAST;
1408
1409 if (mode & WAKE_UCAST)
1410 ret |= MLX5_WOL_UNICAST;
1411
1412 if (mode & WAKE_PHY)
1413 ret |= MLX5_WOL_PHY_ACTIVITY;
1414
1415 return ret;
1416}
1417
1418static void mlx5e_get_wol(struct net_device *netdev,
1419 struct ethtool_wolinfo *wol)
1420{
1421 struct mlx5e_priv *priv = netdev_priv(netdev);
1422 struct mlx5_core_dev *mdev = priv->mdev;
1423 u8 mlx5_wol_mode;
1424 int err;
1425
1426 memset(wol, 0, sizeof(*wol));
1427
1428 wol->supported = mlx5e_get_wol_supported(mdev);
1429 if (!wol->supported)
1430 return;
1431
1432 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1433 if (err)
1434 return;
1435
1436 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1437}
1438
1439static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1440{
1441 struct mlx5e_priv *priv = netdev_priv(netdev);
1442 struct mlx5_core_dev *mdev = priv->mdev;
1443 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1444 u32 mlx5_wol_mode;
1445
1446 if (!wol_supported)
9eb78923 1447 return -EOPNOTSUPP;
928cfe87
TT		 1448
1449 if (wol->wolopts & ~wol_supported)
1450 return -EINVAL;
1451
1452 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1453
1454 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1455}
1456
6cfa9460
SA		 1457static int mlx5e_get_fecparam(struct net_device *netdev,
1458 struct ethtool_fecparam *fecparam)
1459{
1460 struct mlx5e_priv *priv = netdev_priv(netdev);
1461 struct mlx5_core_dev *mdev = priv->mdev;
1462 u8 fec_configured = 0;
1463 u32 fec_active = 0;
1464 int err;
1465
1466 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1467
1468 if (err)
1469 return err;
1470
1471 fecparam->active_fec = pplm2ethtool_fec((u_long)fec_active,
1472 sizeof(u32) * BITS_PER_BYTE);
1473
1474 if (!fecparam->active_fec)
1475 return -EOPNOTSUPP;
1476
1477 fecparam->fec = pplm2ethtool_fec((u_long)fec_configured,
1478 sizeof(u8) * BITS_PER_BYTE);
1479
1480 return 0;
1481}
1482
1483static int mlx5e_set_fecparam(struct net_device *netdev,
1484 struct ethtool_fecparam *fecparam)
1485{
1486 struct mlx5e_priv *priv = netdev_priv(netdev);
1487 struct mlx5_core_dev *mdev = priv->mdev;
1488 u8 fec_policy = 0;
1489 int mode;
1490 int err;
1491
1492 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1493 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1494 continue;
1495 fec_policy |= (1 << mode);
1496 break;
1497 }
1498
1499 err = mlx5e_set_fec_mode(mdev, fec_policy);
1500
1501 if (err)
1502 return err;
1503
1504 mlx5_toggle_port_link(mdev);
1505
1506 return 0;
1507}
1508
79c48764
GP		 1509static u32 mlx5e_get_msglevel(struct net_device *dev)
1510{
1511 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1512}
1513
1514static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1515{
1516 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1517}
1518
da54d24e
GP		 1519static int mlx5e_set_phys_id(struct net_device *dev,
1520 enum ethtool_phys_id_state state)
1521{
1522 struct mlx5e_priv *priv = netdev_priv(dev);
1523 struct mlx5_core_dev *mdev = priv->mdev;
1524 u16 beacon_duration;
1525
1526 if (!MLX5_CAP_GEN(mdev, beacon_led))
1527 return -EOPNOTSUPP;
1528
1529 switch (state) {
1530 case ETHTOOL_ID_ACTIVE:
1531 beacon_duration = MLX5_BEACON_DURATION_INF;
1532 break;
1533 case ETHTOOL_ID_INACTIVE:
1534 beacon_duration = MLX5_BEACON_DURATION_OFF;
1535 break;
1536 default:
1537 return -EOPNOTSUPP;
1538 }
1539
1540 return mlx5_set_port_beacon(mdev, beacon_duration);
1541}
1542
bb64143e
GP		 1543static int mlx5e_get_module_info(struct net_device *netdev,
1544 struct ethtool_modinfo *modinfo)
1545{
1546 struct mlx5e_priv *priv = netdev_priv(netdev);
1547 struct mlx5_core_dev *dev = priv->mdev;
1548 int size_read = 0;
1549 u8 data[4];
1550
1551 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1552 if (size_read < 2)
1553 return -EIO;
1554
1555 /* data[0] = identifier byte */
1556 switch (data[0]) {
1557 case MLX5_MODULE_ID_QSFP:
1558 modinfo->type = ETH_MODULE_SFF_8436;
1559 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1560 break;
1561 case MLX5_MODULE_ID_QSFP_PLUS:
1562 case MLX5_MODULE_ID_QSFP28:
1563 /* data[1] = revision id */
1564 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1565 modinfo->type = ETH_MODULE_SFF_8636;
1566 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1567 } else {
1568 modinfo->type = ETH_MODULE_SFF_8436;
1569 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1570 }
1571 break;
1572 case MLX5_MODULE_ID_SFP:
1573 modinfo->type = ETH_MODULE_SFF_8472;
1574 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1575 break;
1576 default:
1577 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1578 __func__, data[0]);
1579 return -EINVAL;
1580 }
1581
1582 return 0;
1583}
1584
1585static int mlx5e_get_module_eeprom(struct net_device *netdev,
1586 struct ethtool_eeprom *ee,
1587 u8 *data)
1588{
1589 struct mlx5e_priv *priv = netdev_priv(netdev);
1590 struct mlx5_core_dev *mdev = priv->mdev;
1591 int offset = ee->offset;
1592 int size_read;
1593 int i = 0;
1594
1595 if (!ee->len)
1596 return -EINVAL;
1597
1598 memset(data, 0, ee->len);
1599
1600 while (i < ee->len) {
1601 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1602 data + i);
1603
1604 if (!size_read)
1605 /* Done reading */
1606 return 0;
1607
1608 if (size_read < 0) {
1609 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1610 __func__, size_read);
1611 return 0;
1612 }
1613
1614 i += size_read;
1615 offset += size_read;
1616 }
1617
1618 return 0;
1619}
1620
0088cbbc
TG		 1621static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1622 bool is_rx_cq)
4e59e288 1623{
9908aa29
TT		 1624 struct mlx5e_priv *priv = netdev_priv(netdev);
1625 struct mlx5_core_dev *mdev = priv->mdev;
be7e87f9 1626 struct mlx5e_channels new_channels = {};
0088cbbc
TG		 1627 bool mode_changed;
1628 u8 cq_period_mode, current_cq_period_mode;
9908aa29 1629
0088cbbc 1630 cq_period_mode = enable ?
9908aa29
TT		 1631 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1632 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
0088cbbc
TG		 1633 current_cq_period_mode = is_rx_cq ?
1634 priv->channels.params.rx_cq_moderation.cq_period_mode :
1635 priv->channels.params.tx_cq_moderation.cq_period_mode;
1636 mode_changed = cq_period_mode != current_cq_period_mode;
9908aa29 1637
0088cbbc 1638 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
9908aa29 1639 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
9eb78923 1640 return -EOPNOTSUPP;
9908aa29 1641
0088cbbc 1642 if (!mode_changed)
9908aa29
TT		 1643 return 0;
1644
be7e87f9 1645 new_channels.params = priv->channels.params;
0088cbbc
TG		 1646 if (is_rx_cq)
1647 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1648 else
1649 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
9908aa29 1650
be7e87f9
SM		 1651 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1652 priv->channels.params = new_channels.params;
1653 return 0;
1654 }
1655
877662e2 1656 return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
be7e87f9 1657}
9908aa29 1658
0088cbbc
TG		 1659static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1660{
1661 return set_pflag_cqe_based_moder(netdev, enable, false);
1662}
1663
1664static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1665{
1666 return set_pflag_cqe_based_moder(netdev, enable, true);
1667}
1668
be7e87f9
SM		 1669int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1670{
1671 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1672 struct mlx5e_channels new_channels = {};
1673 int err = 0;
1674
1675 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1676 return new_val ? -EOPNOTSUPP : 0;
1677
1678 if (curr_val == new_val)
1679 return 0;
1680
1681 new_channels.params = priv->channels.params;
1682 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1683
be7e87f9
SM		 1684 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1685 priv->channels.params = new_channels.params;
1686 return 0;
1687 }
1688
877662e2 1689 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
be7e87f9
SM		 1690 if (err)
1691 return err;
1692
696a97cf
EE		 1693 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1694 MLX5E_GET_PFLAG(&priv->channels.params,
1695 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1696
be7e87f9 1697 return 0;
4e59e288
GP		 1698}
1699
9bcc8606
SD		 1700static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1701 bool enable)
1702{
1703 struct mlx5e_priv *priv = netdev_priv(netdev);
1704 struct mlx5_core_dev *mdev = priv->mdev;
9bcc8606
SD		 1705
1706 if (!MLX5_CAP_GEN(mdev, cqe_compression))
9eb78923 1707 return -EOPNOTSUPP;
9bcc8606 1708
7c39afb3 1709 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
9bcc8606
SD		 1710 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1711 return -EINVAL;
1712 }
1713
5eb0249b 1714 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
6a9764ef 1715 priv->channels.params.rx_cqe_compress_def = enable;
9bcc8606 1716
5eb0249b 1717 return 0;
9bcc8606
SD		 1718}
1719
2ccb0a79
TT		 1720static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1721{
1722 struct mlx5e_priv *priv = netdev_priv(netdev);
1723 struct mlx5_core_dev *mdev = priv->mdev;
1724 struct mlx5e_channels new_channels = {};
2ccb0a79
TT		 1725
1726 if (enable) {
1727 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1728 return -EOPNOTSUPP;
1729 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1730 return -EINVAL;
6c3a823e
TT		 1731 } else if (priv->channels.params.lro_en) {
1732 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n");
1733 return -EINVAL;
2ccb0a79
TT		 1734 }
1735
1736 new_channels.params = priv->channels.params;
1737
1738 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1739 mlx5e_set_rq_type(mdev, &new_channels.params);
1740
1741 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1742 priv->channels.params = new_channels.params;
1743 return 0;
1744 }
1745
877662e2 1746 return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
2ccb0a79
TT		 1747}
1748
b856df28
OG		 1749static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
1750{
1751 struct mlx5e_priv *priv = netdev_priv(netdev);
1752 struct mlx5e_channels *channels = &priv->channels;
1753 struct mlx5e_channel *c;
1754 int i;
1755
1756 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1757 return 0;
1758
1759 for (i = 0; i < channels->num; i++) {
1760 c = channels->c[i];
1761 if (enable)
1762 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1763 else
1764 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1765 }
1766
1767 return 0;
1768}
1769
6277053a
TT		 1770static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
1771{
1772 struct mlx5e_priv *priv = netdev_priv(netdev);
1773 struct mlx5_core_dev *mdev = priv->mdev;
1774 struct mlx5e_channels new_channels = {};
1775 int err;
1776
1777 if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1778 return -EOPNOTSUPP;
1779
1780 new_channels.params = priv->channels.params;
1781
1782 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
1783
1784 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1785 priv->channels.params = new_channels.params;
1786 return 0;
1787 }
1788
877662e2
TT		 1789 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
1790 return err;
6277053a
TT		 1791}
1792
8ff57c18
TT		 1793static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
1794 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
1795 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
1796 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
1797 { "rx_striding_rq", set_pflag_rx_striding_rq },
1798 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
6277053a 1799 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
8ff57c18
TT		 1800};
1801
4e59e288
GP		 1802static int mlx5e_handle_pflag(struct net_device *netdev,
1803 u32 wanted_flags,
8ff57c18 1804 enum mlx5e_priv_flag flag)
4e59e288
GP		 1805{
1806 struct mlx5e_priv *priv = netdev_priv(netdev);
8ff57c18 1807 bool enable = !!(wanted_flags & BIT(flag));
6a9764ef 1808 u32 changes = wanted_flags ^ priv->channels.params.pflags;
4e59e288
GP		 1809 int err;
1810
8ff57c18 1811 if (!(changes & BIT(flag)))
4e59e288
GP		 1812 return 0;
1813
8ff57c18 1814 err = mlx5e_priv_flags[flag].handler(netdev, enable);
4e59e288 1815 if (err) {
8ff57c18
TT		 1816 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
1817 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
4e59e288
GP		 1818 return err;
1819 }
1820
6a9764ef 1821 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
4e59e288
GP		 1822 return 0;
1823}
1824
1825static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1826{
1827 struct mlx5e_priv *priv = netdev_priv(netdev);
8ff57c18 1828 enum mlx5e_priv_flag pflag;
4e59e288
GP		 1829 int err;
1830
1831 mutex_lock(&priv->state_lock);
2ccb0a79 1832
8ff57c18
TT		 1833 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
1834 err = mlx5e_handle_pflag(netdev, pflags, pflag);
1835 if (err)
1836 break;
1837 }
9bcc8606 1838
4e59e288 1839 mutex_unlock(&priv->state_lock);
6c3a823e
TT		 1840
1841 /* Need to fix some features.. */
1842 netdev_update_features(netdev);
1843
9bcc8606 1844 return err;
4e59e288
GP		 1845}
1846
1847static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1848{
1849 struct mlx5e_priv *priv = netdev_priv(netdev);
1850
6a9764ef 1851 return priv->channels.params.pflags;
4e59e288
GP		 1852}
1853
3ffaabec
OG		 1854int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1855 struct ethtool_flash *flash)
1856{
1857 struct mlx5_core_dev *mdev = priv->mdev;
1858 struct net_device *dev = priv->netdev;
1859 const struct firmware *fw;
1860 int err;
1861
1862 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1863 return -EOPNOTSUPP;
1864
1865 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1866 if (err)
1867 return err;
1868
1869 dev_hold(dev);
1870 rtnl_unlock();
1871
1872 err = mlx5_firmware_flash(mdev, fw);
1873 release_firmware(fw);
1874
1875 rtnl_lock();
1876 dev_put(dev);
1877 return err;
1878}
1879
1880static int mlx5e_flash_device(struct net_device *dev,
1881 struct ethtool_flash *flash)
1882{
1883 struct mlx5e_priv *priv = netdev_priv(dev);
1884
1885 return mlx5e_ethtool_flash_device(priv, flash);
1886}
1887
f62b8bb8
AV		 1888const struct ethtool_ops mlx5e_ethtool_ops = {
1889 .get_drvinfo = mlx5e_get_drvinfo,
1890 .get_link = ethtool_op_get_link,
1891 .get_strings = mlx5e_get_strings,
1892 .get_sset_count = mlx5e_get_sset_count,
1893 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1894 .get_ringparam = mlx5e_get_ringparam,
1895 .set_ringparam = mlx5e_set_ringparam,
1896 .get_channels = mlx5e_get_channels,
1897 .set_channels = mlx5e_set_channels,
1898 .get_coalesce = mlx5e_get_coalesce,
1899 .set_coalesce = mlx5e_set_coalesce,
665bc539
GP		 1900 .get_link_ksettings = mlx5e_get_link_ksettings,
1901 .set_link_ksettings = mlx5e_set_link_ksettings,
2d75b2bc
AS		 1902 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1903 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2be6967c
SM		 1904 .get_rxfh = mlx5e_get_rxfh,
1905 .set_rxfh = mlx5e_set_rxfh,
fe6d86b3 1906#ifdef CONFIG_MLX5_EN_RXNFC
2d75b2bc 1907 .get_rxnfc = mlx5e_get_rxnfc,
6dc6071c 1908 .set_rxnfc = mlx5e_set_rxnfc,
fe6d86b3 1909#endif
3ffaabec 1910 .flash_device = mlx5e_flash_device,
58d52291
AS		 1911 .get_tunable = mlx5e_get_tunable,
1912 .set_tunable = mlx5e_set_tunable,
3c2d18ef
AS		 1913 .get_pauseparam = mlx5e_get_pauseparam,
1914 .set_pauseparam = mlx5e_set_pauseparam,
ef9814de 1915 .get_ts_info = mlx5e_get_ts_info,
da54d24e 1916 .set_phys_id = mlx5e_set_phys_id,
928cfe87
TT		 1917 .get_wol = mlx5e_get_wol,
1918 .set_wol = mlx5e_set_wol,
bb64143e
GP		 1919 .get_module_info = mlx5e_get_module_info,
1920 .get_module_eeprom = mlx5e_get_module_eeprom,
4e59e288 1921 .get_priv_flags = mlx5e_get_priv_flags,
d605d668
KH		 1922 .set_priv_flags = mlx5e_set_priv_flags,
1923 .self_test = mlx5e_self_test,
79c48764
GP		 1924 .get_msglevel = mlx5e_get_msglevel,
1925 .set_msglevel = mlx5e_set_msglevel,
6cfa9460
SA		 1926 .get_fecparam = mlx5e_get_fecparam,
1927 .set_fecparam = mlx5e_set_fecparam,
f62b8bb8 1928};
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