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net/mlx5e: Minimize mlx5e_{open/close}_locked
[thirdparty/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "en.h"
34
35static void mlx5e_get_drvinfo(struct net_device *dev,
36 struct ethtool_drvinfo *drvinfo)
37{
38 struct mlx5e_priv *priv = netdev_priv(dev);
39 struct mlx5_core_dev *mdev = priv->mdev;
40
41 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
42 strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")",
43 sizeof(drvinfo->version));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
45 "%d.%d.%d",
46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev));
47 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
48 sizeof(drvinfo->bus_info));
49}
50
665bc539
GP		 51struct ptys2ethtool_config {
52 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
53 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
f62b8bb8 54 u32 speed;
f62b8bb8
AV		 55};
56
665bc539
GP		 57static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
58
59#define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
60 ({ \
61 struct ptys2ethtool_config *cfg; \
62 const unsigned int modes[] = { __VA_ARGS__ }; \
63 unsigned int i; \
64 cfg = &ptys2ethtool_table[reg_]; \
65 cfg->speed = speed_; \
66 bitmap_zero(cfg->supported, \
67 __ETHTOOL_LINK_MODE_MASK_NBITS); \
68 bitmap_zero(cfg->advertised, \
69 __ETHTOOL_LINK_MODE_MASK_NBITS); \
70 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
71 __set_bit(modes[i], cfg->supported); \
72 __set_bit(modes[i], cfg->advertised); \
73 } \
74 })
75
76void mlx5e_build_ptys2ethtool_map(void)
77{
78 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000,
79 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
80 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000,
81 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
82 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000,
83 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
84 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000,
85 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
86 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000,
87 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
88 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000,
89 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
90 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000,
91 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
92 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000,
93 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000,
95 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000,
97 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000,
99 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000,
101 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000,
103 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000,
105 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000,
107 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000,
109 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000,
111 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000,
113 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000,
115 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000,
117 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000,
119 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000,
121 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000,
123 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000,
125 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000,
127 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
128}
129
cf678570
GP		 130static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
131{
132 struct mlx5_core_dev *mdev = priv->mdev;
133 u8 pfc_en_tx;
134 u8 pfc_en_rx;
135 int err;
136
137 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
138
139 return err ? 0 : pfc_en_tx | pfc_en_rx;
140}
141
e989d5a5
GP		 142static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
143{
144 struct mlx5_core_dev *mdev = priv->mdev;
145 u32 rx_pause;
146 u32 tx_pause;
147 int err;
148
149 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
150
151 return err ? false : rx_pause | tx_pause;
152}
153
593cf338 154#define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
ff9c852f 155#define MLX5E_NUM_RQ_STATS(priv) (NUM_RQ_STATS * (priv)->channels.num)
9218b44d 156#define MLX5E_NUM_SQ_STATS(priv) \
6a9764ef 157 (NUM_SQ_STATS * (priv)->channels.num * (priv)->channels.params.num_tc)
ed80ec4c 158#define MLX5E_NUM_PFC_COUNTERS(priv) \
e989d5a5
GP		 159 ((mlx5e_query_global_pause_combined(priv) + hweight8(mlx5e_query_pfc_combined(priv))) * \
160 NUM_PPORT_PER_PRIO_PFC_COUNTERS)
593cf338 161
f62b8bb8
AV		 162static int mlx5e_get_sset_count(struct net_device *dev, int sset)
163{
164 struct mlx5e_priv *priv = netdev_priv(dev);
165
166 switch (sset) {
167 case ETH_SS_STATS:
9218b44d 168 return NUM_SW_COUNTERS +
593cf338 169 MLX5E_NUM_Q_CNTRS(priv) +
5db0a4f6 170 NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS(priv) +
0f7f3481 171 NUM_PCIE_COUNTERS(priv) +
9218b44d 172 MLX5E_NUM_RQ_STATS(priv) +
cf678570 173 MLX5E_NUM_SQ_STATS(priv) +
bedb7c90
HN		 174 MLX5E_NUM_PFC_COUNTERS(priv) +
175 ARRAY_SIZE(mlx5e_pme_status_desc) +
176 ARRAY_SIZE(mlx5e_pme_error_desc);
177
4e59e288
GP		 178 case ETH_SS_PRIV_FLAGS:
179 return ARRAY_SIZE(mlx5e_priv_flags);
d605d668
KH		 180 case ETH_SS_TEST:
181 return mlx5e_self_test_num(priv);
f62b8bb8
AV		 182 /* fallthrough */
183 default:
184 return -EOPNOTSUPP;
185 }
186}
187
9218b44d
GP		 188static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
189{
cf678570
GP		 190 int i, j, tc, prio, idx = 0;
191 unsigned long pfc_combined;
9218b44d
GP		 192
193 /* SW counters */
194 for (i = 0; i < NUM_SW_COUNTERS; i++)
bfe6d8d1 195 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
9218b44d
GP		 196
197 /* Q counters */
198 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
bfe6d8d1 199 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].format);
9218b44d
GP		 200
201 /* VPORT counters */
202 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
203 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 204 vport_stats_desc[i].format);
9218b44d
GP		 205
206 /* PPORT counters */
207 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
208 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 209 pport_802_3_stats_desc[i].format);
9218b44d
GP		 210
211 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
212 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 213 pport_2863_stats_desc[i].format);
9218b44d
GP		 214
215 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
216 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 217 pport_2819_stats_desc[i].format);
9218b44d 218
5db0a4f6
GP		 219 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
220 strcpy(data + (idx++) * ETH_GSTRING_LEN,
221 pport_phy_statistical_stats_desc[i].format);
222
0f7f3481
GP		 223 for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
224 strcpy(data + (idx++) * ETH_GSTRING_LEN,
225 pcie_perf_stats_desc[i].format);
226
cf678570
GP		 227 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
228 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
bfe6d8d1
GP		 229 sprintf(data + (idx++) * ETH_GSTRING_LEN,
230 pport_per_prio_traffic_stats_desc[i].format, prio);
cf678570
GP		 231 }
232
233 pfc_combined = mlx5e_query_pfc_combined(priv);
234 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
235 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
e989d5a5
GP		 236 char pfc_string[ETH_GSTRING_LEN];
237
238 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
bfe6d8d1 239 sprintf(data + (idx++) * ETH_GSTRING_LEN,
e989d5a5
GP		 240 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
241 }
242 }
243
244 if (mlx5e_query_global_pause_combined(priv)) {
245 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
246 sprintf(data + (idx++) * ETH_GSTRING_LEN,
247 pport_per_prio_pfc_stats_desc[i].format, "global");
cf678570
GP		 248 }
249 }
250
bedb7c90
HN		 251 /* port module event counters */
252 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
253 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
254
255 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
256 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
257
9218b44d
GP		 258 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
259 return;
260
261 /* per channel counters */
ff9c852f 262 for (i = 0; i < priv->channels.num; i++)
9218b44d 263 for (j = 0; j < NUM_RQ_STATS; j++)
bfe6d8d1
GP		 264 sprintf(data + (idx++) * ETH_GSTRING_LEN,
265 rq_stats_desc[j].format, i);
9218b44d 266
6a9764ef 267 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
ff9c852f 268 for (i = 0; i < priv->channels.num; i++)
9218b44d
GP		 269 for (j = 0; j < NUM_SQ_STATS; j++)
270 sprintf(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 271 sq_stats_desc[j].format,
acc6c595 272 priv->channel_tc2txq[i][tc]);
9218b44d
GP		 273}
274
f62b8bb8
AV		 275static void mlx5e_get_strings(struct net_device *dev,
276 uint32_t stringset, uint8_t *data)
277{
f62b8bb8 278 struct mlx5e_priv *priv = netdev_priv(dev);
4e59e288 279 int i;
f62b8bb8
AV		 280
281 switch (stringset) {
282 case ETH_SS_PRIV_FLAGS:
4e59e288
GP		 283 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
284 strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
f62b8bb8
AV		 285 break;
286
287 case ETH_SS_TEST:
d605d668
KH		 288 for (i = 0; i < mlx5e_self_test_num(priv); i++)
289 strcpy(data + i * ETH_GSTRING_LEN,
290 mlx5e_self_tests[i]);
f62b8bb8
AV		 291 break;
292
293 case ETH_SS_STATS:
9218b44d 294 mlx5e_fill_stats_strings(priv, data);
f62b8bb8
AV		 295 break;
296 }
297}
298
299static void mlx5e_get_ethtool_stats(struct net_device *dev,
300 struct ethtool_stats *stats, u64 *data)
301{
302 struct mlx5e_priv *priv = netdev_priv(dev);
ff9c852f 303 struct mlx5e_channels *channels;
bedb7c90 304 struct mlx5_priv *mlx5_priv;
cf678570
GP		 305 int i, j, tc, prio, idx = 0;
306 unsigned long pfc_combined;
f62b8bb8
AV		 307
308 if (!data)
309 return;
310
311 mutex_lock(&priv->state_lock);
312 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
313 mlx5e_update_stats(priv);
ff9c852f 314 channels = &priv->channels;
f62b8bb8
AV		 315 mutex_unlock(&priv->state_lock);
316
9218b44d
GP		 317 for (i = 0; i < NUM_SW_COUNTERS; i++)
318 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
319 sw_stats_desc, i);
f62b8bb8 320
593cf338 321 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
9218b44d
GP		 322 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
323 q_stats_desc, i);
324
325 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
326 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
327 vport_stats_desc, i);
593cf338 328
9218b44d
GP		 329 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
330 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
331 pport_802_3_stats_desc, i);
332
333 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
334 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
335 pport_2863_stats_desc, i);
336
337 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
338 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
339 pport_2819_stats_desc, i);
340
5db0a4f6
GP		 341 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
342 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
343 pport_phy_statistical_stats_desc, i);
344
0f7f3481
GP		 345 for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
346 data[idx++] = MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
347 pcie_perf_stats_desc, i);
348
cf678570
GP		 349 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
350 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
351 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
352 pport_per_prio_traffic_stats_desc, i);
353 }
354
355 pfc_combined = mlx5e_query_pfc_combined(priv);
356 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
357 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
358 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
359 pport_per_prio_pfc_stats_desc, i);
360 }
361 }
362
e989d5a5
GP		 363 if (mlx5e_query_global_pause_combined(priv)) {
364 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
365 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
4e39883d 366 pport_per_prio_pfc_stats_desc, i);
e989d5a5
GP		 367 }
368 }
369
bedb7c90
HN		 370 /* port module event counters */
371 mlx5_priv = &priv->mdev->priv;
372 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
373 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
374 mlx5e_pme_status_desc, i);
375
376 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
377 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
378 mlx5e_pme_error_desc, i);
379
9218b44d
GP		 380 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
381 return;
efea389d 382
f62b8bb8 383 /* per channel counters */
ff9c852f 384 for (i = 0; i < channels->num; i++)
f62b8bb8 385 for (j = 0; j < NUM_RQ_STATS; j++)
9218b44d 386 data[idx++] =
ff9c852f 387 MLX5E_READ_CTR64_CPU(&channels->c[i]->rq.stats,
9218b44d 388 rq_stats_desc, j);
f62b8bb8 389
6a9764ef 390 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
ff9c852f 391 for (i = 0; i < channels->num; i++)
f62b8bb8 392 for (j = 0; j < NUM_SQ_STATS; j++)
ff9c852f 393 data[idx++] = MLX5E_READ_CTR64_CPU(&channels->c[i]->sq[tc].stats,
9218b44d 394 sq_stats_desc, j);
f62b8bb8
AV		 395}
396
cc8e9ebf
EBE		 397static u32 mlx5e_rx_wqes_to_packets(struct mlx5e_priv *priv, int rq_wq_type,
398 int num_wqe)
399{
400 int packets_per_wqe;
401 int stride_size;
402 int num_strides;
403 int wqe_size;
404
405 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
406 return num_wqe;
407
6a9764ef
SM		 408 stride_size = 1 << priv->channels.params.mpwqe_log_stride_sz;
409 num_strides = 1 << priv->channels.params.mpwqe_log_num_strides;
cc8e9ebf
EBE		 410 wqe_size = stride_size * num_strides;
411
412 packets_per_wqe = wqe_size /
413 ALIGN(ETH_DATA_LEN, stride_size);
414 return (1 << (order_base_2(num_wqe * packets_per_wqe) - 1));
415}
416
417static u32 mlx5e_packets_to_rx_wqes(struct mlx5e_priv *priv, int rq_wq_type,
418 int num_packets)
419{
420 int packets_per_wqe;
421 int stride_size;
422 int num_strides;
423 int wqe_size;
424 int num_wqes;
425
426 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
427 return num_packets;
428
6a9764ef
SM		 429 stride_size = 1 << priv->channels.params.mpwqe_log_stride_sz;
430 num_strides = 1 << priv->channels.params.mpwqe_log_num_strides;
cc8e9ebf
EBE		 431 wqe_size = stride_size * num_strides;
432
433 num_packets = (1 << order_base_2(num_packets));
434
435 packets_per_wqe = wqe_size /
436 ALIGN(ETH_DATA_LEN, stride_size);
437 num_wqes = DIV_ROUND_UP(num_packets, packets_per_wqe);
438 return 1 << (order_base_2(num_wqes));
439}
440
f62b8bb8
AV		 441static void mlx5e_get_ringparam(struct net_device *dev,
442 struct ethtool_ringparam *param)
443{
444 struct mlx5e_priv *priv = netdev_priv(dev);
6a9764ef 445 int rq_wq_type = priv->channels.params.rq_wq_type;
f62b8bb8 446
cc8e9ebf
EBE		 447 param->rx_max_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
448 1 << mlx5_max_log_rq_size(rq_wq_type));
f62b8bb8 449 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
cc8e9ebf 450 param->rx_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
6a9764ef
SM		 451 1 << priv->channels.params.log_rq_size);
452 param->tx_pending = 1 << priv->channels.params.log_sq_size;
f62b8bb8
AV		 453}
454
455static int mlx5e_set_ringparam(struct net_device *dev,
456 struct ethtool_ringparam *param)
457{
458 struct mlx5e_priv *priv = netdev_priv(dev);
6a9764ef 459 int rq_wq_type = priv->channels.params.rq_wq_type;
cc8e9ebf 460 u32 rx_pending_wqes;
6a9764ef 461 bool was_opened;
cc8e9ebf
EBE		 462 u32 min_rq_size;
463 u32 max_rq_size;
f62b8bb8
AV		 464 u8 log_rq_size;
465 u8 log_sq_size;
fe4c988b 466 u32 num_mtts;
f62b8bb8
AV		 467 int err = 0;
468
469 if (param->rx_jumbo_pending) {
470 netdev_info(dev, "%s: rx_jumbo_pending not supported\n",
471 __func__);
472 return -EINVAL;
473 }
474 if (param->rx_mini_pending) {
475 netdev_info(dev, "%s: rx_mini_pending not supported\n",
476 __func__);
477 return -EINVAL;
478 }
cc8e9ebf
EBE		 479
480 min_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
481 1 << mlx5_min_log_rq_size(rq_wq_type));
482 max_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
483 1 << mlx5_max_log_rq_size(rq_wq_type));
484 rx_pending_wqes = mlx5e_packets_to_rx_wqes(priv, rq_wq_type,
485 param->rx_pending);
486
487 if (param->rx_pending < min_rq_size) {
f62b8bb8
AV		 488 netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n",
489 __func__, param->rx_pending,
cc8e9ebf 490 min_rq_size);
f62b8bb8
AV		 491 return -EINVAL;
492 }
cc8e9ebf 493 if (param->rx_pending > max_rq_size) {
f62b8bb8
AV		 494 netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n",
495 __func__, param->rx_pending,
cc8e9ebf 496 max_rq_size);
f62b8bb8
AV		 497 return -EINVAL;
498 }
fe4c988b 499
ec8b9981 500 num_mtts = MLX5E_REQUIRED_MTTS(rx_pending_wqes);
6a9764ef 501 if (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
fe4c988b
SM		 502 !MLX5E_VALID_NUM_MTTS(num_mtts)) {
503 netdev_info(dev, "%s: rx_pending (%d) request can't be satisfied, try to reduce.\n",
504 __func__, param->rx_pending);
505 return -EINVAL;
506 }
507
f62b8bb8
AV		 508 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
509 netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n",
510 __func__, param->tx_pending,
511 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
512 return -EINVAL;
513 }
514 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
515 netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n",
516 __func__, param->tx_pending,
517 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
518 return -EINVAL;
519 }
520
cc8e9ebf 521 log_rq_size = order_base_2(rx_pending_wqes);
f62b8bb8 522 log_sq_size = order_base_2(param->tx_pending);
f62b8bb8 523
6a9764ef
SM		 524 if (log_rq_size == priv->channels.params.log_rq_size &&
525 log_sq_size == priv->channels.params.log_sq_size)
f62b8bb8
AV		 526 return 0;
527
528 mutex_lock(&priv->state_lock);
98e81b0a
AS		 529
530 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
531 if (was_opened)
532 mlx5e_close_locked(dev);
533
6a9764ef
SM		 534 priv->channels.params.log_rq_size = log_rq_size;
535 priv->channels.params.log_sq_size = log_sq_size;
98e81b0a
AS		 536
537 if (was_opened)
538 err = mlx5e_open_locked(dev);
539
f62b8bb8
AV		 540 mutex_unlock(&priv->state_lock);
541
542 return err;
543}
544
545static void mlx5e_get_channels(struct net_device *dev,
546 struct ethtool_channels *ch)
547{
548 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 549
b4e029da 550 ch->max_combined = priv->profile->max_nch(priv->mdev);
6a9764ef 551 ch->combined_count = priv->channels.params.num_channels;
f62b8bb8
AV		 552}
553
554static int mlx5e_set_channels(struct net_device *dev,
555 struct ethtool_channels *ch)
556{
557 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 558 unsigned int count = ch->combined_count;
45bf454a 559 bool arfs_enabled;
98e81b0a 560 bool was_opened;
f62b8bb8
AV		 561 int err = 0;
562
563 if (!count) {
564 netdev_info(dev, "%s: combined_count=0 not supported\n",
565 __func__);
566 return -EINVAL;
567 }
f62b8bb8 568
6a9764ef 569 if (priv->channels.params.num_channels == count)
f62b8bb8
AV		 570 return 0;
571
572 mutex_lock(&priv->state_lock);
98e81b0a
AS		 573
574 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
575 if (was_opened)
576 mlx5e_close_locked(dev);
577
45bf454a
MG		 578 arfs_enabled = dev->features & NETIF_F_NTUPLE;
579 if (arfs_enabled)
580 mlx5e_arfs_disable(priv);
581
6a9764ef
SM		 582 priv->channels.params.num_channels = count;
583 mlx5e_build_default_indir_rqt(priv->mdev, priv->channels.params.indirection_rqt,
85082dba 584 MLX5E_INDIR_RQT_SIZE, count);
98e81b0a
AS		 585
586 if (was_opened)
587 err = mlx5e_open_locked(dev);
45bf454a
MG		 588 if (err)
589 goto out;
590
591 if (arfs_enabled) {
592 err = mlx5e_arfs_enable(priv);
593 if (err)
594 netdev_err(dev, "%s: mlx5e_arfs_enable failed: %d\n",
595 __func__, err);
596 }
98e81b0a 597
45bf454a 598out:
f62b8bb8
AV		 599 mutex_unlock(&priv->state_lock);
600
601 return err;
602}
603
604static int mlx5e_get_coalesce(struct net_device *netdev,
605 struct ethtool_coalesce *coal)
606{
607 struct mlx5e_priv *priv = netdev_priv(netdev);
608
7524a5d8 609 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
9eb78923 610 return -EOPNOTSUPP;
7524a5d8 611
6a9764ef
SM		 612 coal->rx_coalesce_usecs = priv->channels.params.rx_cq_moderation.usec;
613 coal->rx_max_coalesced_frames = priv->channels.params.rx_cq_moderation.pkts;
614 coal->tx_coalesce_usecs = priv->channels.params.tx_cq_moderation.usec;
615 coal->tx_max_coalesced_frames = priv->channels.params.tx_cq_moderation.pkts;
616 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_am_enabled;
f62b8bb8
AV		 617
618 return 0;
619}
620
621static int mlx5e_set_coalesce(struct net_device *netdev,
622 struct ethtool_coalesce *coal)
623{
624 struct mlx5e_priv *priv = netdev_priv(netdev);
625 struct mlx5_core_dev *mdev = priv->mdev;
cb3c7fd4 626 bool restart =
6a9764ef 627 !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_am_enabled;
cb3c7fd4
GR		 628 bool was_opened;
629 int err = 0;
f62b8bb8
AV		 630 int tc;
631 int i;
632
7524a5d8 633 if (!MLX5_CAP_GEN(mdev, cq_moderation))
9eb78923 634 return -EOPNOTSUPP;
7524a5d8 635
2fcb92fb 636 mutex_lock(&priv->state_lock);
9908aa29 637
cb3c7fd4
GR		 638 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
639 if (was_opened && restart) {
640 mlx5e_close_locked(netdev);
6a9764ef 641 priv->channels.params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce;
cb3c7fd4
GR		 642 }
643
6a9764ef
SM		 644 priv->channels.params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
645 priv->channels.params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
646 priv->channels.params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
647 priv->channels.params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
f62b8bb8 648
cb3c7fd4 649 if (!was_opened || restart)
2fcb92fb 650 goto out;
ff9c852f
SM		 651 for (i = 0; i < priv->channels.num; ++i) {
652 struct mlx5e_channel *c = priv->channels.c[i];
f62b8bb8
AV		 653
654 for (tc = 0; tc < c->num_tc; tc++) {
655 mlx5_core_modify_cq_moderation(mdev,
656 &c->sq[tc].cq.mcq,
657 coal->tx_coalesce_usecs,
658 coal->tx_max_coalesced_frames);
659 }
660
661 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
662 coal->rx_coalesce_usecs,
663 coal->rx_max_coalesced_frames);
664 }
665
2fcb92fb 666out:
cb3c7fd4
GR		 667 if (was_opened && restart)
668 err = mlx5e_open_locked(netdev);
669
2fcb92fb 670 mutex_unlock(&priv->state_lock);
cb3c7fd4 671 return err;
f62b8bb8
AV		 672}
673
665bc539
GP		 674static void ptys2ethtool_supported_link(unsigned long *supported_modes,
675 u32 eth_proto_cap)
f62b8bb8 676{
7abc2110 677 unsigned long proto_cap = eth_proto_cap;
665bc539 678 int proto;
f62b8bb8 679
7abc2110 680 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP		 681 bitmap_or(supported_modes, supported_modes,
682 ptys2ethtool_table[proto].supported,
683 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 684}
685
665bc539
GP		 686static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
687 u32 eth_proto_cap)
f62b8bb8 688{
7abc2110 689 unsigned long proto_cap = eth_proto_cap;
665bc539 690 int proto;
f62b8bb8 691
7abc2110 692 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP		 693 bitmap_or(advertising_modes, advertising_modes,
694 ptys2ethtool_table[proto].advertised,
695 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 696}
697
665bc539
GP		 698static void ptys2ethtool_supported_port(struct ethtool_link_ksettings *link_ksettings,
699 u32 eth_proto_cap)
f62b8bb8
AV		 700{
701 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
702 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
703 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
704 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
705 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
706 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
665bc539 707 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, FIBRE);
f62b8bb8
AV		 708 }
709
710 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
711 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
712 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
713 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
714 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
665bc539 715 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Backplane);
f62b8bb8 716 }
f62b8bb8
AV		 717}
718
b797a684
SM		 719int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
720{
721 u32 max_speed = 0;
722 u32 proto_cap;
723 int err;
724 int i;
725
726 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
727 if (err)
728 return err;
729
730 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
731 if (proto_cap & MLX5E_PROT_MASK(i))
732 max_speed = max(max_speed, ptys2ethtool_table[i].speed);
733
734 *speed = max_speed;
735 return 0;
736}
737
f62b8bb8
AV		 738static void get_speed_duplex(struct net_device *netdev,
739 u32 eth_proto_oper,
665bc539 740 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 741{
742 int i;
743 u32 speed = SPEED_UNKNOWN;
744 u8 duplex = DUPLEX_UNKNOWN;
745
746 if (!netif_carrier_ok(netdev))
747 goto out;
748
749 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
750 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
751 speed = ptys2ethtool_table[i].speed;
752 duplex = DUPLEX_FULL;
753 break;
754 }
755 }
756out:
665bc539
GP		 757 link_ksettings->base.speed = speed;
758 link_ksettings->base.duplex = duplex;
f62b8bb8
AV		 759}
760
665bc539
GP		 761static void get_supported(u32 eth_proto_cap,
762 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 763{
665bc539
GP		 764 unsigned long *supported = link_ksettings->link_modes.supported;
765
766 ptys2ethtool_supported_port(link_ksettings, eth_proto_cap);
767 ptys2ethtool_supported_link(supported, eth_proto_cap);
768 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
769 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Asym_Pause);
f62b8bb8
AV		 770}
771
772static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
665bc539
GP		 773 u8 rx_pause,
774 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 775{
665bc539
GP		 776 unsigned long *advertising = link_ksettings->link_modes.advertising;
777
778 ptys2ethtool_adver_link(advertising, eth_proto_cap);
779 if (tx_pause)
780 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
781 if (tx_pause ^ rx_pause)
782 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
f62b8bb8
AV		 783}
784
785static u8 get_connector_port(u32 eth_proto)
786{
787 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
788 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
789 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
790 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
791 return PORT_FIBRE;
792 }
793
794 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
795 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
796 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
797 return PORT_DA;
798 }
799
800 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
801 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
802 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
803 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
804 return PORT_NONE;
805 }
806
807 return PORT_OTHER;
808}
809
665bc539
GP		 810static void get_lp_advertising(u32 eth_proto_lp,
811 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 812{
665bc539
GP		 813 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
814
815 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
f62b8bb8
AV		 816}
817
665bc539
GP		 818static int mlx5e_get_link_ksettings(struct net_device *netdev,
819 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 820{
821 struct mlx5e_priv *priv = netdev_priv(netdev);
822 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 823 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
f62b8bb8
AV		 824 u32 eth_proto_cap;
825 u32 eth_proto_admin;
826 u32 eth_proto_lp;
827 u32 eth_proto_oper;
52244d96
GP		 828 u8 an_disable_admin;
829 u8 an_status;
f62b8bb8
AV		 830 int err;
831
a05bdefa 832 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
f62b8bb8
AV		 833 if (err) {
834 netdev_err(netdev, "%s: query port ptys failed: %d\n",
835 __func__, err);
836 goto err_query_ptys;
837 }
838
52244d96
GP		 839 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
840 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
841 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
842 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
843 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
844 an_status = MLX5_GET(ptys_reg, out, an_status);
f62b8bb8 845
665bc539
GP		 846 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
847 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
f62b8bb8 848
665bc539
GP		 849 get_supported(eth_proto_cap, link_ksettings);
850 get_advertising(eth_proto_admin, 0, 0, link_ksettings);
851 get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
f62b8bb8
AV		 852
853 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
854
665bc539
GP		 855 link_ksettings->base.port = get_connector_port(eth_proto_oper);
856 get_lp_advertising(eth_proto_lp, link_ksettings);
f62b8bb8 857
52244d96
GP		 858 if (an_status == MLX5_AN_COMPLETE)
859 ethtool_link_ksettings_add_link_mode(link_ksettings,
860 lp_advertising, Autoneg);
861
862 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
863 AUTONEG_ENABLE;
864 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
865 Autoneg);
866 if (!an_disable_admin)
867 ethtool_link_ksettings_add_link_mode(link_ksettings,
868 advertising, Autoneg);
869
f62b8bb8
AV		 870err_query_ptys:
871 return err;
872}
873
665bc539 874static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
f62b8bb8
AV		 875{
876 u32 i, ptys_modes = 0;
877
878 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
665bc539
GP		 879 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
880 link_modes,
881 __ETHTOOL_LINK_MODE_MASK_NBITS))
f62b8bb8
AV		 882 ptys_modes |= MLX5E_PROT_MASK(i);
883 }
884
885 return ptys_modes;
886}
887
888static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
889{
890 u32 i, speed_links = 0;
891
892 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
893 if (ptys2ethtool_table[i].speed == speed)
894 speed_links |= MLX5E_PROT_MASK(i);
895 }
896
897 return speed_links;
898}
899
665bc539
GP		 900static int mlx5e_set_link_ksettings(struct net_device *netdev,
901 const struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 902{
903 struct mlx5e_priv *priv = netdev_priv(netdev);
904 struct mlx5_core_dev *mdev = priv->mdev;
52244d96
GP		 905 u32 eth_proto_cap, eth_proto_admin;
906 bool an_changes = false;
907 u8 an_disable_admin;
908 u8 an_disable_cap;
909 bool an_disable;
f62b8bb8 910 u32 link_modes;
52244d96 911 u8 an_status;
f62b8bb8 912 u32 speed;
f62b8bb8
AV		 913 int err;
914
665bc539 915 speed = link_ksettings->base.speed;
f62b8bb8 916
665bc539
GP		 917 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
918 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
f62b8bb8
AV		 919 mlx5e_ethtool2ptys_speed_link(speed);
920
921 err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
922 if (err) {
923 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
924 __func__, err);
925 goto out;
926 }
927
928 link_modes = link_modes & eth_proto_cap;
929 if (!link_modes) {
930 netdev_err(netdev, "%s: Not supported link mode(s) requested",
931 __func__);
932 err = -EINVAL;
933 goto out;
934 }
935
936 err = mlx5_query_port_proto_admin(mdev, &eth_proto_admin, MLX5_PTYS_EN);
937 if (err) {
938 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
939 __func__, err);
940 goto out;
941 }
942
52244d96
GP		 943 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
944 &an_disable_cap, &an_disable_admin);
945
946 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
947 an_changes = ((!an_disable && an_disable_admin) ||
948 (an_disable && !an_disable_admin));
949
950 if (!an_changes && link_modes == eth_proto_admin)
f62b8bb8
AV		 951 goto out;
952
52244d96 953 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
667daeda 954 mlx5_toggle_port_link(mdev);
f62b8bb8 955
f62b8bb8
AV		 956out:
957 return err;
958}
959
2d75b2bc
AS		 960static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
961{
962 struct mlx5e_priv *priv = netdev_priv(netdev);
963
6a9764ef 964 return sizeof(priv->channels.params.toeplitz_hash_key);
2d75b2bc
AS		 965}
966
967static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
968{
969 return MLX5E_INDIR_RQT_SIZE;
970}
971
2be6967c
SM		 972static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
973 u8 *hfunc)
974{
975 struct mlx5e_priv *priv = netdev_priv(netdev);
976
2d75b2bc 977 if (indir)
6a9764ef
SM		 978 memcpy(indir, priv->channels.params.indirection_rqt,
979 sizeof(priv->channels.params.indirection_rqt));
2d75b2bc
AS		 980
981 if (key)
6a9764ef
SM		 982 memcpy(key, priv->channels.params.toeplitz_hash_key,
983 sizeof(priv->channels.params.toeplitz_hash_key));
2d75b2bc 984
2be6967c 985 if (hfunc)
6a9764ef 986 *hfunc = priv->channels.params.rss_hfunc;
2be6967c
SM		 987
988 return 0;
989}
990
bdfc028d
TT		 991static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
992{
bdfc028d 993 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
a100ff3e
GP		 994 struct mlx5_core_dev *mdev = priv->mdev;
995 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
996 int tt;
bdfc028d
TT		 997
998 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
bdfc028d 999
a100ff3e
GP		 1000 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1001 memset(tirc, 0, ctxlen);
6a9764ef 1002 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
a100ff3e
GP		 1003 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
1004 }
bdfc028d
TT		 1005}
1006
98e81b0a 1007static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
2be6967c
SM		 1008 const u8 *key, const u8 hfunc)
1009{
98e81b0a 1010 struct mlx5e_priv *priv = netdev_priv(dev);
bdfc028d 1011 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1d3398fa 1012 bool hash_changed = false;
bdfc028d 1013 void *in;
2be6967c 1014
2d75b2bc
AS		 1015 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1016 (hfunc != ETH_RSS_HASH_XOR) &&
2be6967c
SM		 1017 (hfunc != ETH_RSS_HASH_TOP))
1018 return -EINVAL;
1019
bdfc028d
TT		 1020 in = mlx5_vzalloc(inlen);
1021 if (!in)
1022 return -ENOMEM;
1023
2be6967c
SM		 1024 mutex_lock(&priv->state_lock);
1025
1d3398fa 1026 if (hfunc != ETH_RSS_HASH_NO_CHANGE &&
6a9764ef
SM		 1027 hfunc != priv->channels.params.rss_hfunc) {
1028 priv->channels.params.rss_hfunc = hfunc;
1d3398fa
GP		 1029 hash_changed = true;
1030 }
1031
a5f97fee 1032 if (indir) {
6a9764ef
SM		 1033 memcpy(priv->channels.params.indirection_rqt, indir,
1034 sizeof(priv->channels.params.indirection_rqt));
a5f97fee
SM		 1035
1036 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1037 u32 rqtn = priv->indir_rqt.rqtn;
1038 struct mlx5e_redirect_rqt_param rrp = {
1039 .is_rss = true,
6a9764ef 1040 .rss.hfunc = priv->channels.params.rss_hfunc,
a5f97fee
SM		 1041 .rss.channels = &priv->channels
1042 };
1043
1044 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1045 }
1046 }
1047
1d3398fa 1048 if (key) {
6a9764ef
SM		 1049 memcpy(priv->channels.params.toeplitz_hash_key, key,
1050 sizeof(priv->channels.params.toeplitz_hash_key));
1d3398fa 1051 hash_changed = hash_changed ||
6a9764ef 1052 priv->channels.params.rss_hfunc == ETH_RSS_HASH_TOP;
1d3398fa 1053 }
2d75b2bc 1054
1d3398fa
GP		 1055 if (hash_changed)
1056 mlx5e_modify_tirs_hash(priv, in, inlen);
2d75b2bc 1057
2be6967c
SM		 1058 mutex_unlock(&priv->state_lock);
1059
bdfc028d
TT		 1060 kvfree(in);
1061
1062 return 0;
2be6967c
SM		 1063}
1064
2d75b2bc
AS		 1065static int mlx5e_get_rxnfc(struct net_device *netdev,
1066 struct ethtool_rxnfc *info, u32 *rule_locs)
1067{
1068 struct mlx5e_priv *priv = netdev_priv(netdev);
1069 int err = 0;
1070
1071 switch (info->cmd) {
1072 case ETHTOOL_GRXRINGS:
6a9764ef 1073 info->data = priv->channels.params.num_channels;
2d75b2bc 1074 break;
f913a72a
MG		 1075 case ETHTOOL_GRXCLSRLCNT:
1076 info->rule_cnt = priv->fs.ethtool.tot_num_rules;
1077 break;
1078 case ETHTOOL_GRXCLSRULE:
1079 err = mlx5e_ethtool_get_flow(priv, info, info->fs.location);
1080 break;
1081 case ETHTOOL_GRXCLSRLALL:
1082 err = mlx5e_ethtool_get_all_flows(priv, info, rule_locs);
1083 break;
2d75b2bc
AS		 1084 default:
1085 err = -EOPNOTSUPP;
1086 break;
1087 }
1088
1089 return err;
1090}
1091
58d52291
AS		 1092static int mlx5e_get_tunable(struct net_device *dev,
1093 const struct ethtool_tunable *tuna,
1094 void *data)
1095{
1096 const struct mlx5e_priv *priv = netdev_priv(dev);
1097 int err = 0;
1098
1099 switch (tuna->id) {
1100 case ETHTOOL_TX_COPYBREAK:
6a9764ef 1101 *(u32 *)data = priv->channels.params.tx_max_inline;
58d52291
AS		 1102 break;
1103 default:
1104 err = -EINVAL;
1105 break;
1106 }
1107
1108 return err;
1109}
1110
1111static int mlx5e_set_tunable(struct net_device *dev,
1112 const struct ethtool_tunable *tuna,
1113 const void *data)
1114{
1115 struct mlx5e_priv *priv = netdev_priv(dev);
1116 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 1117 bool was_opened;
58d52291
AS		 1118 u32 val;
1119 int err = 0;
1120
1121 switch (tuna->id) {
1122 case ETHTOOL_TX_COPYBREAK:
1123 val = *(u32 *)data;
1124 if (val > mlx5e_get_max_inline_cap(mdev)) {
1125 err = -EINVAL;
1126 break;
1127 }
1128
1129 mutex_lock(&priv->state_lock);
98e81b0a
AS		 1130
1131 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1132 if (was_opened)
1133 mlx5e_close_locked(dev);
1134
6a9764ef 1135 priv->channels.params.tx_max_inline = val;
98e81b0a
AS		 1136
1137 if (was_opened)
1138 err = mlx5e_open_locked(dev);
1139
58d52291
AS		 1140 mutex_unlock(&priv->state_lock);
1141 break;
1142 default:
1143 err = -EINVAL;
1144 break;
1145 }
1146
1147 return err;
1148}
1149
3c2d18ef
AS		 1150static void mlx5e_get_pauseparam(struct net_device *netdev,
1151 struct ethtool_pauseparam *pauseparam)
1152{
1153 struct mlx5e_priv *priv = netdev_priv(netdev);
1154 struct mlx5_core_dev *mdev = priv->mdev;
1155 int err;
1156
1157 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1158 &pauseparam->tx_pause);
1159 if (err) {
1160 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1161 __func__, err);
1162 }
1163}
1164
1165static int mlx5e_set_pauseparam(struct net_device *netdev,
1166 struct ethtool_pauseparam *pauseparam)
1167{
1168 struct mlx5e_priv *priv = netdev_priv(netdev);
1169 struct mlx5_core_dev *mdev = priv->mdev;
1170 int err;
1171
1172 if (pauseparam->autoneg)
1173 return -EINVAL;
1174
1175 err = mlx5_set_port_pause(mdev,
1176 pauseparam->rx_pause ? 1 : 0,
1177 pauseparam->tx_pause ? 1 : 0);
1178 if (err) {
1179 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1180 __func__, err);
1181 }
1182
1183 return err;
1184}
1185
ef9814de
EBE		 1186static int mlx5e_get_ts_info(struct net_device *dev,
1187 struct ethtool_ts_info *info)
1188{
1189 struct mlx5e_priv *priv = netdev_priv(dev);
1190 int ret;
1191
1192 ret = ethtool_op_get_ts_info(dev, info);
1193 if (ret)
1194 return ret;
1195
3d8c38af
EBE		 1196 info->phc_index = priv->tstamp.ptp ?
1197 ptp_clock_index(priv->tstamp.ptp) : -1;
ef9814de
EBE		 1198
1199 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1200 return 0;
1201
1202 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1203 SOF_TIMESTAMPING_RX_HARDWARE |
1204 SOF_TIMESTAMPING_RAW_HARDWARE;
1205
1206 info->tx_types = (BIT(1) << HWTSTAMP_TX_OFF) |
1207 (BIT(1) << HWTSTAMP_TX_ON);
1208
1209 info->rx_filters = (BIT(1) << HWTSTAMP_FILTER_NONE) |
1210 (BIT(1) << HWTSTAMP_FILTER_ALL);
1211
1212 return 0;
1213}
1214
928cfe87
TT		 1215static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1216{
1217 __u32 ret = 0;
1218
1219 if (MLX5_CAP_GEN(mdev, wol_g))
1220 ret |= WAKE_MAGIC;
1221
1222 if (MLX5_CAP_GEN(mdev, wol_s))
1223 ret |= WAKE_MAGICSECURE;
1224
1225 if (MLX5_CAP_GEN(mdev, wol_a))
1226 ret |= WAKE_ARP;
1227
1228 if (MLX5_CAP_GEN(mdev, wol_b))
1229 ret |= WAKE_BCAST;
1230
1231 if (MLX5_CAP_GEN(mdev, wol_m))
1232 ret |= WAKE_MCAST;
1233
1234 if (MLX5_CAP_GEN(mdev, wol_u))
1235 ret |= WAKE_UCAST;
1236
1237 if (MLX5_CAP_GEN(mdev, wol_p))
1238 ret |= WAKE_PHY;
1239
1240 return ret;
1241}
1242
1243static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1244{
1245 __u32 ret = 0;
1246
1247 if (mode & MLX5_WOL_MAGIC)
1248 ret |= WAKE_MAGIC;
1249
1250 if (mode & MLX5_WOL_SECURED_MAGIC)
1251 ret |= WAKE_MAGICSECURE;
1252
1253 if (mode & MLX5_WOL_ARP)
1254 ret |= WAKE_ARP;
1255
1256 if (mode & MLX5_WOL_BROADCAST)
1257 ret |= WAKE_BCAST;
1258
1259 if (mode & MLX5_WOL_MULTICAST)
1260 ret |= WAKE_MCAST;
1261
1262 if (mode & MLX5_WOL_UNICAST)
1263 ret |= WAKE_UCAST;
1264
1265 if (mode & MLX5_WOL_PHY_ACTIVITY)
1266 ret |= WAKE_PHY;
1267
1268 return ret;
1269}
1270
1271static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1272{
1273 u8 ret = 0;
1274
1275 if (mode & WAKE_MAGIC)
1276 ret |= MLX5_WOL_MAGIC;
1277
1278 if (mode & WAKE_MAGICSECURE)
1279 ret |= MLX5_WOL_SECURED_MAGIC;
1280
1281 if (mode & WAKE_ARP)
1282 ret |= MLX5_WOL_ARP;
1283
1284 if (mode & WAKE_BCAST)
1285 ret |= MLX5_WOL_BROADCAST;
1286
1287 if (mode & WAKE_MCAST)
1288 ret |= MLX5_WOL_MULTICAST;
1289
1290 if (mode & WAKE_UCAST)
1291 ret |= MLX5_WOL_UNICAST;
1292
1293 if (mode & WAKE_PHY)
1294 ret |= MLX5_WOL_PHY_ACTIVITY;
1295
1296 return ret;
1297}
1298
1299static void mlx5e_get_wol(struct net_device *netdev,
1300 struct ethtool_wolinfo *wol)
1301{
1302 struct mlx5e_priv *priv = netdev_priv(netdev);
1303 struct mlx5_core_dev *mdev = priv->mdev;
1304 u8 mlx5_wol_mode;
1305 int err;
1306
1307 memset(wol, 0, sizeof(*wol));
1308
1309 wol->supported = mlx5e_get_wol_supported(mdev);
1310 if (!wol->supported)
1311 return;
1312
1313 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1314 if (err)
1315 return;
1316
1317 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1318}
1319
1320static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1321{
1322 struct mlx5e_priv *priv = netdev_priv(netdev);
1323 struct mlx5_core_dev *mdev = priv->mdev;
1324 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1325 u32 mlx5_wol_mode;
1326
1327 if (!wol_supported)
9eb78923 1328 return -EOPNOTSUPP;
928cfe87
TT		 1329
1330 if (wol->wolopts & ~wol_supported)
1331 return -EINVAL;
1332
1333 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1334
1335 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1336}
1337
da54d24e
GP		 1338static int mlx5e_set_phys_id(struct net_device *dev,
1339 enum ethtool_phys_id_state state)
1340{
1341 struct mlx5e_priv *priv = netdev_priv(dev);
1342 struct mlx5_core_dev *mdev = priv->mdev;
1343 u16 beacon_duration;
1344
1345 if (!MLX5_CAP_GEN(mdev, beacon_led))
1346 return -EOPNOTSUPP;
1347
1348 switch (state) {
1349 case ETHTOOL_ID_ACTIVE:
1350 beacon_duration = MLX5_BEACON_DURATION_INF;
1351 break;
1352 case ETHTOOL_ID_INACTIVE:
1353 beacon_duration = MLX5_BEACON_DURATION_OFF;
1354 break;
1355 default:
1356 return -EOPNOTSUPP;
1357 }
1358
1359 return mlx5_set_port_beacon(mdev, beacon_duration);
1360}
1361
bb64143e
GP		 1362static int mlx5e_get_module_info(struct net_device *netdev,
1363 struct ethtool_modinfo *modinfo)
1364{
1365 struct mlx5e_priv *priv = netdev_priv(netdev);
1366 struct mlx5_core_dev *dev = priv->mdev;
1367 int size_read = 0;
1368 u8 data[4];
1369
1370 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1371 if (size_read < 2)
1372 return -EIO;
1373
1374 /* data[0] = identifier byte */
1375 switch (data[0]) {
1376 case MLX5_MODULE_ID_QSFP:
1377 modinfo->type = ETH_MODULE_SFF_8436;
1378 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1379 break;
1380 case MLX5_MODULE_ID_QSFP_PLUS:
1381 case MLX5_MODULE_ID_QSFP28:
1382 /* data[1] = revision id */
1383 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1384 modinfo->type = ETH_MODULE_SFF_8636;
1385 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1386 } else {
1387 modinfo->type = ETH_MODULE_SFF_8436;
1388 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1389 }
1390 break;
1391 case MLX5_MODULE_ID_SFP:
1392 modinfo->type = ETH_MODULE_SFF_8472;
1393 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1394 break;
1395 default:
1396 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1397 __func__, data[0]);
1398 return -EINVAL;
1399 }
1400
1401 return 0;
1402}
1403
1404static int mlx5e_get_module_eeprom(struct net_device *netdev,
1405 struct ethtool_eeprom *ee,
1406 u8 *data)
1407{
1408 struct mlx5e_priv *priv = netdev_priv(netdev);
1409 struct mlx5_core_dev *mdev = priv->mdev;
1410 int offset = ee->offset;
1411 int size_read;
1412 int i = 0;
1413
1414 if (!ee->len)
1415 return -EINVAL;
1416
1417 memset(data, 0, ee->len);
1418
1419 while (i < ee->len) {
1420 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1421 data + i);
1422
1423 if (!size_read)
1424 /* Done reading */
1425 return 0;
1426
1427 if (size_read < 0) {
1428 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1429 __func__, size_read);
1430 return 0;
1431 }
1432
1433 i += size_read;
1434 offset += size_read;
1435 }
1436
1437 return 0;
1438}
1439
4e59e288
GP		 1440typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1441
9908aa29 1442static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
4e59e288 1443{
9908aa29
TT		 1444 struct mlx5e_priv *priv = netdev_priv(netdev);
1445 struct mlx5_core_dev *mdev = priv->mdev;
1446 bool rx_mode_changed;
1447 u8 rx_cq_period_mode;
1448 int err = 0;
1449 bool reset;
1450
1451 rx_cq_period_mode = enable ?
1452 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1453 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
6a9764ef 1454 rx_mode_changed = rx_cq_period_mode != priv->channels.params.rx_cq_period_mode;
9908aa29
TT		 1455
1456 if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1457 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
9eb78923 1458 return -EOPNOTSUPP;
9908aa29
TT		 1459
1460 if (!rx_mode_changed)
1461 return 0;
1462
1463 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
1464 if (reset)
1465 mlx5e_close_locked(netdev);
1466
6a9764ef 1467 mlx5e_set_rx_cq_mode_params(&priv->channels.params, rx_cq_period_mode);
9908aa29
TT		 1468
1469 if (reset)
1470 err = mlx5e_open_locked(netdev);
1471
1472 return err;
4e59e288
GP		 1473}
1474
9bcc8606
SD		 1475static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1476 bool enable)
1477{
1478 struct mlx5e_priv *priv = netdev_priv(netdev);
1479 struct mlx5_core_dev *mdev = priv->mdev;
9bcc8606
SD		 1480
1481 if (!MLX5_CAP_GEN(mdev, cqe_compression))
9eb78923 1482 return -EOPNOTSUPP;
9bcc8606
SD		 1483
1484 if (enable && priv->tstamp.hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
1485 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1486 return -EINVAL;
1487 }
1488
5eb0249b 1489 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
6a9764ef
SM		 1490 priv->channels.params.rx_cqe_compress_def = enable;
1491 mlx5e_set_rq_type_params(priv->mdev, &priv->channels.params,
1492 priv->channels.params.rq_wq_type);
9bcc8606 1493
5eb0249b 1494 return 0;
9bcc8606
SD		 1495}
1496
4e59e288
GP		 1497static int mlx5e_handle_pflag(struct net_device *netdev,
1498 u32 wanted_flags,
1499 enum mlx5e_priv_flag flag,
1500 mlx5e_pflag_handler pflag_handler)
1501{
1502 struct mlx5e_priv *priv = netdev_priv(netdev);
1503 bool enable = !!(wanted_flags & flag);
6a9764ef 1504 u32 changes = wanted_flags ^ priv->channels.params.pflags;
4e59e288
GP		 1505 int err;
1506
1507 if (!(changes & flag))
1508 return 0;
1509
1510 err = pflag_handler(netdev, enable);
1511 if (err) {
1512 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1513 enable ? "Enable" : "Disable", flag, err);
1514 return err;
1515 }
1516
6a9764ef 1517 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
4e59e288
GP		 1518 return 0;
1519}
1520
1521static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1522{
1523 struct mlx5e_priv *priv = netdev_priv(netdev);
1524 int err;
1525
1526 mutex_lock(&priv->state_lock);
9908aa29
TT		 1527 err = mlx5e_handle_pflag(netdev, pflags,
1528 MLX5E_PFLAG_RX_CQE_BASED_MODER,
1529 set_pflag_rx_cqe_based_moder);
9bcc8606
SD		 1530 if (err)
1531 goto out;
4e59e288 1532
9bcc8606
SD		 1533 err = mlx5e_handle_pflag(netdev, pflags,
1534 MLX5E_PFLAG_RX_CQE_COMPRESS,
1535 set_pflag_rx_cqe_compress);
1536
1537out:
4e59e288 1538 mutex_unlock(&priv->state_lock);
9bcc8606 1539 return err;
4e59e288
GP		 1540}
1541
1542static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1543{
1544 struct mlx5e_priv *priv = netdev_priv(netdev);
1545
6a9764ef 1546 return priv->channels.params.pflags;
4e59e288
GP		 1547}
1548
6dc6071c
MG		 1549static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1550{
1551 int err = 0;
1552 struct mlx5e_priv *priv = netdev_priv(dev);
1553
1554 switch (cmd->cmd) {
1555 case ETHTOOL_SRXCLSRLINS:
1556 err = mlx5e_ethtool_flow_replace(priv, &cmd->fs);
1557 break;
1558 case ETHTOOL_SRXCLSRLDEL:
1559 err = mlx5e_ethtool_flow_remove(priv, cmd->fs.location);
1560 break;
1561 default:
1562 err = -EOPNOTSUPP;
1563 break;
1564 }
1565
1566 return err;
1567}
1568
f62b8bb8
AV		 1569const struct ethtool_ops mlx5e_ethtool_ops = {
1570 .get_drvinfo = mlx5e_get_drvinfo,
1571 .get_link = ethtool_op_get_link,
1572 .get_strings = mlx5e_get_strings,
1573 .get_sset_count = mlx5e_get_sset_count,
1574 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1575 .get_ringparam = mlx5e_get_ringparam,
1576 .set_ringparam = mlx5e_set_ringparam,
1577 .get_channels = mlx5e_get_channels,
1578 .set_channels = mlx5e_set_channels,
1579 .get_coalesce = mlx5e_get_coalesce,
1580 .set_coalesce = mlx5e_set_coalesce,
665bc539
GP		 1581 .get_link_ksettings = mlx5e_get_link_ksettings,
1582 .set_link_ksettings = mlx5e_set_link_ksettings,
2d75b2bc
AS		 1583 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1584 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2be6967c
SM		 1585 .get_rxfh = mlx5e_get_rxfh,
1586 .set_rxfh = mlx5e_set_rxfh,
2d75b2bc 1587 .get_rxnfc = mlx5e_get_rxnfc,
6dc6071c 1588 .set_rxnfc = mlx5e_set_rxnfc,
58d52291
AS		 1589 .get_tunable = mlx5e_get_tunable,
1590 .set_tunable = mlx5e_set_tunable,
3c2d18ef
AS		 1591 .get_pauseparam = mlx5e_get_pauseparam,
1592 .set_pauseparam = mlx5e_set_pauseparam,
ef9814de 1593 .get_ts_info = mlx5e_get_ts_info,
da54d24e 1594 .set_phys_id = mlx5e_set_phys_id,
928cfe87
TT		 1595 .get_wol = mlx5e_get_wol,
1596 .set_wol = mlx5e_set_wol,
bb64143e
GP		 1597 .get_module_info = mlx5e_get_module_info,
1598 .get_module_eeprom = mlx5e_get_module_eeprom,
4e59e288 1599 .get_priv_flags = mlx5e_get_priv_flags,
d605d668
KH		 1600 .set_priv_flags = mlx5e_set_priv_flags,
1601 .self_test = mlx5e_self_test,
f62b8bb8 1602};
A mirror of Linus' kernel repository