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[thirdparty/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "en.h"
164f16f7 34#include "en_accel/ipsec.h"
f62b8bb8 35
076b0936
ES		 36void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
37 struct ethtool_drvinfo *drvinfo)
f62b8bb8 38{
f62b8bb8
AV		 39 struct mlx5_core_dev *mdev = priv->mdev;
40
41 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
7913d205 42 strlcpy(drvinfo->version, DRIVER_VERSION,
f62b8bb8
AV		 43 sizeof(drvinfo->version));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
84e11edb
IK		 45 "%d.%d.%04d (%.16s)",
46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
47 mdev->board_id);
f62b8bb8
AV		 48 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
49 sizeof(drvinfo->bus_info));
50}
51
076b0936
ES		 52static void mlx5e_get_drvinfo(struct net_device *dev,
53 struct ethtool_drvinfo *drvinfo)
54{
55 struct mlx5e_priv *priv = netdev_priv(dev);
56
57 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
58}
59
665bc539
GP		 60struct ptys2ethtool_config {
61 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
62 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
f62b8bb8 63 u32 speed;
f62b8bb8
AV		 64};
65
665bc539
GP		 66static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
67
68#define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
69 ({ \
70 struct ptys2ethtool_config *cfg; \
71 const unsigned int modes[] = { __VA_ARGS__ }; \
72 unsigned int i; \
73 cfg = &ptys2ethtool_table[reg_]; \
74 cfg->speed = speed_; \
75 bitmap_zero(cfg->supported, \
76 __ETHTOOL_LINK_MODE_MASK_NBITS); \
77 bitmap_zero(cfg->advertised, \
78 __ETHTOOL_LINK_MODE_MASK_NBITS); \
79 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
80 __set_bit(modes[i], cfg->supported); \
81 __set_bit(modes[i], cfg->advertised); \
82 } \
83 })
84
85void mlx5e_build_ptys2ethtool_map(void)
86{
87 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000,
88 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
89 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000,
90 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
91 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000,
92 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
93 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000,
94 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
95 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000,
96 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
97 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000,
98 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
99 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000,
100 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
101 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000,
102 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
103 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000,
104 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
105 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000,
106 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
107 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000,
108 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
109 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000,
110 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
111 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000,
112 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
113 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000,
114 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
115 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000,
116 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
117 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000,
118 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
119 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000,
120 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
121 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000,
122 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
123 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000,
124 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
125 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000,
126 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
127 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000,
128 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
129 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000,
130 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
131 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000,
132 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
133 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000,
134 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
135 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000,
136 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
137}
138
cf678570
GP		 139static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
140{
141 struct mlx5_core_dev *mdev = priv->mdev;
142 u8 pfc_en_tx;
143 u8 pfc_en_rx;
144 int err;
145
c66f2091
FD		 146 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
147 return 0;
148
cf678570
GP		 149 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
150
151 return err ? 0 : pfc_en_tx | pfc_en_rx;
152}
153
e989d5a5
GP		 154static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
155{
156 struct mlx5_core_dev *mdev = priv->mdev;
157 u32 rx_pause;
158 u32 tx_pause;
159 int err;
160
c66f2091
FD		 161 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
162 return false;
163
e989d5a5
GP		 164 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
165
166 return err ? false : rx_pause | tx_pause;
167}
168
593cf338 169#define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
ff9c852f 170#define MLX5E_NUM_RQ_STATS(priv) (NUM_RQ_STATS * (priv)->channels.num)
9218b44d 171#define MLX5E_NUM_SQ_STATS(priv) \
6a9764ef 172 (NUM_SQ_STATS * (priv)->channels.num * (priv)->channels.params.num_tc)
ed80ec4c 173#define MLX5E_NUM_PFC_COUNTERS(priv) \
e989d5a5
GP		 174 ((mlx5e_query_global_pause_combined(priv) + hweight8(mlx5e_query_pfc_combined(priv))) * \
175 NUM_PPORT_PER_PRIO_PFC_COUNTERS)
593cf338 176
076b0936 177int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
f62b8bb8 178{
f62b8bb8
AV		 179 switch (sset) {
180 case ETH_SS_STATS:
9218b44d 181 return NUM_SW_COUNTERS +
593cf338 182 MLX5E_NUM_Q_CNTRS(priv) +
5db0a4f6 183 NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS(priv) +
0f7f3481 184 NUM_PCIE_COUNTERS(priv) +
9218b44d 185 MLX5E_NUM_RQ_STATS(priv) +
cf678570 186 MLX5E_NUM_SQ_STATS(priv) +
bedb7c90
HN		 187 MLX5E_NUM_PFC_COUNTERS(priv) +
188 ARRAY_SIZE(mlx5e_pme_status_desc) +
164f16f7
IT		 189 ARRAY_SIZE(mlx5e_pme_error_desc) +
190 mlx5e_ipsec_get_count(priv);
bedb7c90 191
4e59e288
GP		 192 case ETH_SS_PRIV_FLAGS:
193 return ARRAY_SIZE(mlx5e_priv_flags);
d605d668
KH		 194 case ETH_SS_TEST:
195 return mlx5e_self_test_num(priv);
f62b8bb8
AV		 196 /* fallthrough */
197 default:
198 return -EOPNOTSUPP;
199 }
200}
201
076b0936
ES		 202static int mlx5e_get_sset_count(struct net_device *dev, int sset)
203{
204 struct mlx5e_priv *priv = netdev_priv(dev);
205
206 return mlx5e_ethtool_get_sset_count(priv, sset);
207}
208
9218b44d
GP		 209static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
210{
cf678570
GP		 211 int i, j, tc, prio, idx = 0;
212 unsigned long pfc_combined;
9218b44d
GP		 213
214 /* SW counters */
215 for (i = 0; i < NUM_SW_COUNTERS; i++)
bfe6d8d1 216 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
9218b44d
GP		 217
218 /* Q counters */
219 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
bfe6d8d1 220 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].format);
9218b44d
GP		 221
222 /* VPORT counters */
223 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
224 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 225 vport_stats_desc[i].format);
9218b44d
GP		 226
227 /* PPORT counters */
228 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
229 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 230 pport_802_3_stats_desc[i].format);
9218b44d
GP		 231
232 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
233 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 234 pport_2863_stats_desc[i].format);
9218b44d
GP		 235
236 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
237 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 238 pport_2819_stats_desc[i].format);
9218b44d 239
5db0a4f6
GP		 240 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
241 strcpy(data + (idx++) * ETH_GSTRING_LEN,
242 pport_phy_statistical_stats_desc[i].format);
243
068aef33
GP		 244 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS(priv); i++)
245 strcpy(data + (idx++) * ETH_GSTRING_LEN,
246 pport_eth_ext_stats_desc[i].format);
247
0f7f3481
GP		 248 for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
249 strcpy(data + (idx++) * ETH_GSTRING_LEN,
250 pcie_perf_stats_desc[i].format);
251
efae7f78 252 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64(priv); i++)
73e90646 253 strcpy(data + (idx++) * ETH_GSTRING_LEN,
efae7f78
EBE		 254 pcie_perf_stats_desc64[i].format);
255
256 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS(priv); i++)
257 strcpy(data + (idx++) * ETH_GSTRING_LEN,
258 pcie_perf_stall_stats_desc[i].format);
73e90646 259
cf678570
GP		 260 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
261 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
bfe6d8d1
GP		 262 sprintf(data + (idx++) * ETH_GSTRING_LEN,
263 pport_per_prio_traffic_stats_desc[i].format, prio);
cf678570
GP		 264 }
265
266 pfc_combined = mlx5e_query_pfc_combined(priv);
267 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
268 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
e989d5a5
GP		 269 char pfc_string[ETH_GSTRING_LEN];
270
271 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
bfe6d8d1 272 sprintf(data + (idx++) * ETH_GSTRING_LEN,
e989d5a5
GP		 273 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
274 }
275 }
276
277 if (mlx5e_query_global_pause_combined(priv)) {
278 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
279 sprintf(data + (idx++) * ETH_GSTRING_LEN,
280 pport_per_prio_pfc_stats_desc[i].format, "global");
cf678570
GP		 281 }
282 }
283
bedb7c90
HN		 284 /* port module event counters */
285 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
286 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
287
288 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
289 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
290
164f16f7
IT		 291 /* IPSec counters */
292 idx += mlx5e_ipsec_get_strings(priv, data + idx * ETH_GSTRING_LEN);
293
9218b44d
GP		 294 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
295 return;
296
297 /* per channel counters */
ff9c852f 298 for (i = 0; i < priv->channels.num; i++)
9218b44d 299 for (j = 0; j < NUM_RQ_STATS; j++)
bfe6d8d1
GP		 300 sprintf(data + (idx++) * ETH_GSTRING_LEN,
301 rq_stats_desc[j].format, i);
9218b44d 302
6a9764ef 303 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
ff9c852f 304 for (i = 0; i < priv->channels.num; i++)
9218b44d
GP		 305 for (j = 0; j < NUM_SQ_STATS; j++)
306 sprintf(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 307 sq_stats_desc[j].format,
acc6c595 308 priv->channel_tc2txq[i][tc]);
9218b44d
GP		 309}
310
076b0936
ES		 311void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
312 uint32_t stringset, uint8_t *data)
f62b8bb8 313{
4e59e288 314 int i;
f62b8bb8
AV		 315
316 switch (stringset) {
317 case ETH_SS_PRIV_FLAGS:
4e59e288
GP		 318 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
319 strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
f62b8bb8
AV		 320 break;
321
322 case ETH_SS_TEST:
d605d668
KH		 323 for (i = 0; i < mlx5e_self_test_num(priv); i++)
324 strcpy(data + i * ETH_GSTRING_LEN,
325 mlx5e_self_tests[i]);
f62b8bb8
AV		 326 break;
327
328 case ETH_SS_STATS:
9218b44d 329 mlx5e_fill_stats_strings(priv, data);
f62b8bb8
AV		 330 break;
331 }
332}
333
076b0936
ES		 334static void mlx5e_get_strings(struct net_device *dev,
335 uint32_t stringset, uint8_t *data)
f62b8bb8
AV		 336{
337 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 338
339 mlx5e_ethtool_get_strings(priv, stringset, data);
340}
341
342void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
343 struct ethtool_stats *stats, u64 *data)
344{
ff9c852f 345 struct mlx5e_channels *channels;
bedb7c90 346 struct mlx5_priv *mlx5_priv;
cf678570
GP		 347 int i, j, tc, prio, idx = 0;
348 unsigned long pfc_combined;
f62b8bb8
AV		 349
350 if (!data)
351 return;
352
353 mutex_lock(&priv->state_lock);
354 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
3834a5e6 355 mlx5e_update_stats(priv, true);
ff9c852f 356 channels = &priv->channels;
f62b8bb8
AV		 357 mutex_unlock(&priv->state_lock);
358
9218b44d
GP		 359 for (i = 0; i < NUM_SW_COUNTERS; i++)
360 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
361 sw_stats_desc, i);
f62b8bb8 362
593cf338 363 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
9218b44d
GP		 364 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
365 q_stats_desc, i);
366
367 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
368 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
369 vport_stats_desc, i);
593cf338 370
9218b44d
GP		 371 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
372 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
373 pport_802_3_stats_desc, i);
374
375 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
376 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
377 pport_2863_stats_desc, i);
378
379 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
380 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
381 pport_2819_stats_desc, i);
382
5db0a4f6
GP		 383 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
384 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
385 pport_phy_statistical_stats_desc, i);
068aef33
GP		 386
387 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS(priv); i++)
388 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters,
389 pport_eth_ext_stats_desc, i);
5db0a4f6 390
0f7f3481
GP		 391 for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
392 data[idx++] = MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
393 pcie_perf_stats_desc, i);
394
efae7f78
EBE		 395 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64(priv); i++)
396 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters,
397 pcie_perf_stats_desc64, i);
398
73e90646
GP		 399 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS(priv); i++)
400 data[idx++] = MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
401 pcie_perf_stall_stats_desc, i);
402
cf678570
GP		 403 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
404 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
405 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
406 pport_per_prio_traffic_stats_desc, i);
407 }
408
409 pfc_combined = mlx5e_query_pfc_combined(priv);
410 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
411 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
412 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
413 pport_per_prio_pfc_stats_desc, i);
414 }
415 }
416
e989d5a5
GP		 417 if (mlx5e_query_global_pause_combined(priv)) {
418 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
419 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
4e39883d 420 pport_per_prio_pfc_stats_desc, i);
e989d5a5
GP		 421 }
422 }
423
bedb7c90
HN		 424 /* port module event counters */
425 mlx5_priv = &priv->mdev->priv;
426 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
427 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
428 mlx5e_pme_status_desc, i);
429
430 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
431 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
432 mlx5e_pme_error_desc, i);
433
164f16f7
IT		 434 /* IPSec counters */
435 idx += mlx5e_ipsec_get_stats(priv, data + idx);
436
9218b44d
GP		 437 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
438 return;
efea389d 439
f62b8bb8 440 /* per channel counters */
ff9c852f 441 for (i = 0; i < channels->num; i++)
f62b8bb8 442 for (j = 0; j < NUM_RQ_STATS; j++)
9218b44d 443 data[idx++] =
ff9c852f 444 MLX5E_READ_CTR64_CPU(&channels->c[i]->rq.stats,
9218b44d 445 rq_stats_desc, j);
f62b8bb8 446
6a9764ef 447 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
ff9c852f 448 for (i = 0; i < channels->num; i++)
f62b8bb8 449 for (j = 0; j < NUM_SQ_STATS; j++)
ff9c852f 450 data[idx++] = MLX5E_READ_CTR64_CPU(&channels->c[i]->sq[tc].stats,
9218b44d 451 sq_stats_desc, j);
f62b8bb8
AV		 452}
453
076b0936
ES		 454static void mlx5e_get_ethtool_stats(struct net_device *dev,
455 struct ethtool_stats *stats,
456 u64 *data)
457{
458 struct mlx5e_priv *priv = netdev_priv(dev);
459
460 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
461}
462
cc8e9ebf
EBE		 463static u32 mlx5e_rx_wqes_to_packets(struct mlx5e_priv *priv, int rq_wq_type,
464 int num_wqe)
465{
466 int packets_per_wqe;
467 int stride_size;
468 int num_strides;
469 int wqe_size;
470
471 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
472 return num_wqe;
473
6a9764ef
SM		 474 stride_size = 1 << priv->channels.params.mpwqe_log_stride_sz;
475 num_strides = 1 << priv->channels.params.mpwqe_log_num_strides;
cc8e9ebf
EBE		 476 wqe_size = stride_size * num_strides;
477
478 packets_per_wqe = wqe_size /
479 ALIGN(ETH_DATA_LEN, stride_size);
480 return (1 << (order_base_2(num_wqe * packets_per_wqe) - 1));
481}
482
483static u32 mlx5e_packets_to_rx_wqes(struct mlx5e_priv *priv, int rq_wq_type,
484 int num_packets)
485{
486 int packets_per_wqe;
487 int stride_size;
488 int num_strides;
489 int wqe_size;
490 int num_wqes;
491
492 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
493 return num_packets;
494
6a9764ef
SM		 495 stride_size = 1 << priv->channels.params.mpwqe_log_stride_sz;
496 num_strides = 1 << priv->channels.params.mpwqe_log_num_strides;
cc8e9ebf
EBE		 497 wqe_size = stride_size * num_strides;
498
499 num_packets = (1 << order_base_2(num_packets));
500
501 packets_per_wqe = wqe_size /
502 ALIGN(ETH_DATA_LEN, stride_size);
503 num_wqes = DIV_ROUND_UP(num_packets, packets_per_wqe);
504 return 1 << (order_base_2(num_wqes));
505}
506
076b0936
ES		 507void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
508 struct ethtool_ringparam *param)
f62b8bb8 509{
6a9764ef 510 int rq_wq_type = priv->channels.params.rq_wq_type;
f62b8bb8 511
cc8e9ebf
EBE		 512 param->rx_max_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
513 1 << mlx5_max_log_rq_size(rq_wq_type));
f62b8bb8 514 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
cc8e9ebf 515 param->rx_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
6a9764ef
SM		 516 1 << priv->channels.params.log_rq_size);
517 param->tx_pending = 1 << priv->channels.params.log_sq_size;
f62b8bb8
AV		 518}
519
076b0936
ES		 520static void mlx5e_get_ringparam(struct net_device *dev,
521 struct ethtool_ringparam *param)
f62b8bb8
AV		 522{
523 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 524
525 mlx5e_ethtool_get_ringparam(priv, param);
526}
527
528int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
529 struct ethtool_ringparam *param)
530{
6a9764ef 531 int rq_wq_type = priv->channels.params.rq_wq_type;
546f18ed 532 struct mlx5e_channels new_channels = {};
cc8e9ebf
EBE		 533 u32 rx_pending_wqes;
534 u32 min_rq_size;
535 u32 max_rq_size;
f62b8bb8
AV		 536 u8 log_rq_size;
537 u8 log_sq_size;
fe4c988b 538 u32 num_mtts;
f62b8bb8
AV		 539 int err = 0;
540
541 if (param->rx_jumbo_pending) {
076b0936 542 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
f62b8bb8
AV		 543 __func__);
544 return -EINVAL;
545 }
546 if (param->rx_mini_pending) {
076b0936 547 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
f62b8bb8
AV		 548 __func__);
549 return -EINVAL;
550 }
cc8e9ebf
EBE		 551
552 min_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
553 1 << mlx5_min_log_rq_size(rq_wq_type));
554 max_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
555 1 << mlx5_max_log_rq_size(rq_wq_type));
556 rx_pending_wqes = mlx5e_packets_to_rx_wqes(priv, rq_wq_type,
557 param->rx_pending);
558
559 if (param->rx_pending < min_rq_size) {
076b0936 560 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
f62b8bb8 561 __func__, param->rx_pending,
cc8e9ebf 562 min_rq_size);
f62b8bb8
AV		 563 return -EINVAL;
564 }
cc8e9ebf 565 if (param->rx_pending > max_rq_size) {
076b0936 566 netdev_info(priv->netdev, "%s: rx_pending (%d) > max (%d)\n",
f62b8bb8 567 __func__, param->rx_pending,
cc8e9ebf 568 max_rq_size);
f62b8bb8
AV		 569 return -EINVAL;
570 }
fe4c988b 571
ec8b9981 572 num_mtts = MLX5E_REQUIRED_MTTS(rx_pending_wqes);
6a9764ef 573 if (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
fe4c988b 574 !MLX5E_VALID_NUM_MTTS(num_mtts)) {
076b0936 575 netdev_info(priv->netdev, "%s: rx_pending (%d) request can't be satisfied, try to reduce.\n",
fe4c988b
SM		 576 __func__, param->rx_pending);
577 return -EINVAL;
578 }
579
f62b8bb8 580 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
076b0936 581 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
f62b8bb8
AV		 582 __func__, param->tx_pending,
583 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
584 return -EINVAL;
585 }
586 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
076b0936 587 netdev_info(priv->netdev, "%s: tx_pending (%d) > max (%d)\n",
f62b8bb8
AV		 588 __func__, param->tx_pending,
589 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
590 return -EINVAL;
591 }
592
cc8e9ebf 593 log_rq_size = order_base_2(rx_pending_wqes);
f62b8bb8 594 log_sq_size = order_base_2(param->tx_pending);
f62b8bb8 595
6a9764ef
SM		 596 if (log_rq_size == priv->channels.params.log_rq_size &&
597 log_sq_size == priv->channels.params.log_sq_size)
f62b8bb8
AV		 598 return 0;
599
600 mutex_lock(&priv->state_lock);
98e81b0a 601
546f18ed
SM		 602 new_channels.params = priv->channels.params;
603 new_channels.params.log_rq_size = log_rq_size;
604 new_channels.params.log_sq_size = log_sq_size;
98e81b0a 605
546f18ed
SM		 606 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
607 priv->channels.params = new_channels.params;
608 goto unlock;
609 }
98e81b0a 610
546f18ed
SM		 611 err = mlx5e_open_channels(priv, &new_channels);
612 if (err)
613 goto unlock;
614
2e20a151 615 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
98e81b0a 616
546f18ed 617unlock:
f62b8bb8
AV		 618 mutex_unlock(&priv->state_lock);
619
620 return err;
621}
622
076b0936
ES		 623static int mlx5e_set_ringparam(struct net_device *dev,
624 struct ethtool_ringparam *param)
f62b8bb8
AV		 625{
626 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 627
076b0936
ES		 628 return mlx5e_ethtool_set_ringparam(priv, param);
629}
630
631void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
632 struct ethtool_channels *ch)
633{
b4e029da 634 ch->max_combined = priv->profile->max_nch(priv->mdev);
6a9764ef 635 ch->combined_count = priv->channels.params.num_channels;
f62b8bb8
AV		 636}
637
076b0936
ES		 638static void mlx5e_get_channels(struct net_device *dev,
639 struct ethtool_channels *ch)
f62b8bb8
AV		 640{
641 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 642
643 mlx5e_ethtool_get_channels(priv, ch);
644}
645
646int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
647 struct ethtool_channels *ch)
648{
f62b8bb8 649 unsigned int count = ch->combined_count;
55c2503d 650 struct mlx5e_channels new_channels = {};
45bf454a 651 bool arfs_enabled;
f62b8bb8
AV		 652 int err = 0;
653
654 if (!count) {
076b0936 655 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
f62b8bb8
AV		 656 __func__);
657 return -EINVAL;
658 }
f62b8bb8 659
6a9764ef 660 if (priv->channels.params.num_channels == count)
f62b8bb8
AV		 661 return 0;
662
663 mutex_lock(&priv->state_lock);
98e81b0a 664
55c2503d
SM		 665 new_channels.params = priv->channels.params;
666 new_channels.params.num_channels = count;
667 mlx5e_build_default_indir_rqt(priv->mdev, new_channels.params.indirection_rqt,
668 MLX5E_INDIR_RQT_SIZE, count);
669
670 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
671 priv->channels.params = new_channels.params;
672 goto out;
673 }
674
675 /* Create fresh channels with new parameters */
676 err = mlx5e_open_channels(priv, &new_channels);
677 if (err)
678 goto out;
98e81b0a 679
076b0936 680 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
45bf454a
MG		 681 if (arfs_enabled)
682 mlx5e_arfs_disable(priv);
683
55c2503d 684 /* Switch to new channels, set new parameters and close old ones */
2e20a151 685 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
45bf454a
MG		 686
687 if (arfs_enabled) {
688 err = mlx5e_arfs_enable(priv);
689 if (err)
076b0936 690 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
45bf454a
MG		 691 __func__, err);
692 }
98e81b0a 693
45bf454a 694out:
f62b8bb8
AV		 695 mutex_unlock(&priv->state_lock);
696
697 return err;
698}
699
076b0936
ES		 700static int mlx5e_set_channels(struct net_device *dev,
701 struct ethtool_channels *ch)
f62b8bb8 702{
076b0936
ES		 703 struct mlx5e_priv *priv = netdev_priv(dev);
704
705 return mlx5e_ethtool_set_channels(priv, ch);
706}
f62b8bb8 707
076b0936
ES		 708int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
709 struct ethtool_coalesce *coal)
710{
7524a5d8 711 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
9eb78923 712 return -EOPNOTSUPP;
7524a5d8 713
6a9764ef
SM		 714 coal->rx_coalesce_usecs = priv->channels.params.rx_cq_moderation.usec;
715 coal->rx_max_coalesced_frames = priv->channels.params.rx_cq_moderation.pkts;
716 coal->tx_coalesce_usecs = priv->channels.params.tx_cq_moderation.usec;
717 coal->tx_max_coalesced_frames = priv->channels.params.tx_cq_moderation.pkts;
718 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_am_enabled;
f62b8bb8
AV		 719
720 return 0;
721}
722
076b0936
ES		 723static int mlx5e_get_coalesce(struct net_device *netdev,
724 struct ethtool_coalesce *coal)
725{
726 struct mlx5e_priv *priv = netdev_priv(netdev);
727
728 return mlx5e_ethtool_get_coalesce(priv, coal);
729}
730
546f18ed
SM		 731static void
732mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
f62b8bb8 733{
f62b8bb8 734 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 735 int tc;
736 int i;
737
ff9c852f
SM		 738 for (i = 0; i < priv->channels.num; ++i) {
739 struct mlx5e_channel *c = priv->channels.c[i];
f62b8bb8
AV		 740
741 for (tc = 0; tc < c->num_tc; tc++) {
742 mlx5_core_modify_cq_moderation(mdev,
743 &c->sq[tc].cq.mcq,
744 coal->tx_coalesce_usecs,
745 coal->tx_max_coalesced_frames);
746 }
747
748 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
749 coal->rx_coalesce_usecs,
750 coal->rx_max_coalesced_frames);
751 }
546f18ed 752}
f62b8bb8 753
076b0936
ES		 754int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
755 struct ethtool_coalesce *coal)
546f18ed 756{
546f18ed
SM		 757 struct mlx5_core_dev *mdev = priv->mdev;
758 struct mlx5e_channels new_channels = {};
759 int err = 0;
760 bool reset;
cb3c7fd4 761
546f18ed
SM		 762 if (!MLX5_CAP_GEN(mdev, cq_moderation))
763 return -EOPNOTSUPP;
764
765 mutex_lock(&priv->state_lock);
766 new_channels.params = priv->channels.params;
767
768 new_channels.params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
769 new_channels.params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
770 new_channels.params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
771 new_channels.params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
772 new_channels.params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce;
773
774 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
775 priv->channels.params = new_channels.params;
776 goto out;
777 }
778 /* we are opened */
779
780 reset = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_am_enabled;
781 if (!reset) {
782 mlx5e_set_priv_channels_coalesce(priv, coal);
783 priv->channels.params = new_channels.params;
784 goto out;
785 }
786
787 /* open fresh channels with new coal parameters */
788 err = mlx5e_open_channels(priv, &new_channels);
789 if (err)
790 goto out;
791
2e20a151 792 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
546f18ed
SM		 793
794out:
2fcb92fb 795 mutex_unlock(&priv->state_lock);
cb3c7fd4 796 return err;
f62b8bb8
AV		 797}
798
076b0936
ES		 799static int mlx5e_set_coalesce(struct net_device *netdev,
800 struct ethtool_coalesce *coal)
801{
802 struct mlx5e_priv *priv = netdev_priv(netdev);
803
804 return mlx5e_ethtool_set_coalesce(priv, coal);
805}
806
665bc539
GP		 807static void ptys2ethtool_supported_link(unsigned long *supported_modes,
808 u32 eth_proto_cap)
f62b8bb8 809{
7abc2110 810 unsigned long proto_cap = eth_proto_cap;
665bc539 811 int proto;
f62b8bb8 812
7abc2110 813 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP		 814 bitmap_or(supported_modes, supported_modes,
815 ptys2ethtool_table[proto].supported,
816 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 817}
818
665bc539
GP		 819static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
820 u32 eth_proto_cap)
f62b8bb8 821{
7abc2110 822 unsigned long proto_cap = eth_proto_cap;
665bc539 823 int proto;
f62b8bb8 824
7abc2110 825 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP		 826 bitmap_or(advertising_modes, advertising_modes,
827 ptys2ethtool_table[proto].advertised,
828 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 829}
830
46e9d0b6
EBE		 831static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
832 u32 eth_proto_cap,
833 u8 connector_type)
f62b8bb8 834{
46e9d0b6
EBE		 835 if (!connector_type || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
836 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
837 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
838 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
839 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
840 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
841 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
842 ethtool_link_ksettings_add_link_mode(link_ksettings,
843 supported,
844 FIBRE);
845 ethtool_link_ksettings_add_link_mode(link_ksettings,
846 advertising,
847 FIBRE);
848 }
849
850 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
851 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
852 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
853 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
854 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
855 ethtool_link_ksettings_add_link_mode(link_ksettings,
856 supported,
857 Backplane);
858 ethtool_link_ksettings_add_link_mode(link_ksettings,
859 advertising,
860 Backplane);
861 }
862 return;
f62b8bb8
AV		 863 }
864
46e9d0b6
EBE		 865 switch (connector_type) {
866 case MLX5E_PORT_TP:
867 ethtool_link_ksettings_add_link_mode(link_ksettings,
868 supported, TP);
869 ethtool_link_ksettings_add_link_mode(link_ksettings,
870 advertising, TP);
871 break;
872 case MLX5E_PORT_AUI:
873 ethtool_link_ksettings_add_link_mode(link_ksettings,
874 supported, AUI);
875 ethtool_link_ksettings_add_link_mode(link_ksettings,
876 advertising, AUI);
877 break;
878 case MLX5E_PORT_BNC:
879 ethtool_link_ksettings_add_link_mode(link_ksettings,
880 supported, BNC);
881 ethtool_link_ksettings_add_link_mode(link_ksettings,
882 advertising, BNC);
883 break;
884 case MLX5E_PORT_MII:
885 ethtool_link_ksettings_add_link_mode(link_ksettings,
886 supported, MII);
887 ethtool_link_ksettings_add_link_mode(link_ksettings,
888 advertising, MII);
889 break;
890 case MLX5E_PORT_FIBRE:
891 ethtool_link_ksettings_add_link_mode(link_ksettings,
892 supported, FIBRE);
893 ethtool_link_ksettings_add_link_mode(link_ksettings,
894 advertising, FIBRE);
895 break;
896 case MLX5E_PORT_DA:
897 ethtool_link_ksettings_add_link_mode(link_ksettings,
898 supported, Backplane);
899 ethtool_link_ksettings_add_link_mode(link_ksettings,
900 advertising, Backplane);
901 break;
902 case MLX5E_PORT_NONE:
903 case MLX5E_PORT_OTHER:
904 default:
905 break;
f62b8bb8 906 }
f62b8bb8
AV		 907}
908
b797a684
SM		 909int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
910{
911 u32 max_speed = 0;
912 u32 proto_cap;
913 int err;
914 int i;
915
916 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
917 if (err)
918 return err;
919
920 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
921 if (proto_cap & MLX5E_PROT_MASK(i))
922 max_speed = max(max_speed, ptys2ethtool_table[i].speed);
923
924 *speed = max_speed;
925 return 0;
926}
927
f62b8bb8
AV		 928static void get_speed_duplex(struct net_device *netdev,
929 u32 eth_proto_oper,
665bc539 930 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 931{
932 int i;
933 u32 speed = SPEED_UNKNOWN;
934 u8 duplex = DUPLEX_UNKNOWN;
935
936 if (!netif_carrier_ok(netdev))
937 goto out;
938
939 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
940 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
941 speed = ptys2ethtool_table[i].speed;
942 duplex = DUPLEX_FULL;
943 break;
944 }
945 }
946out:
665bc539
GP		 947 link_ksettings->base.speed = speed;
948 link_ksettings->base.duplex = duplex;
f62b8bb8
AV		 949}
950
665bc539
GP		 951static void get_supported(u32 eth_proto_cap,
952 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 953{
665bc539
GP		 954 unsigned long *supported = link_ksettings->link_modes.supported;
955
665bc539
GP		 956 ptys2ethtool_supported_link(supported, eth_proto_cap);
957 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
f62b8bb8
AV		 958}
959
960static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
665bc539
GP		 961 u8 rx_pause,
962 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 963{
665bc539
GP		 964 unsigned long *advertising = link_ksettings->link_modes.advertising;
965
966 ptys2ethtool_adver_link(advertising, eth_proto_cap);
e3c19503 967 if (rx_pause)
665bc539
GP		 968 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
969 if (tx_pause ^ rx_pause)
970 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
f62b8bb8
AV		 971}
972
5b4793f8
EBE		 973static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
974 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
975 [MLX5E_PORT_NONE] = PORT_NONE,
976 [MLX5E_PORT_TP] = PORT_TP,
977 [MLX5E_PORT_AUI] = PORT_AUI,
978 [MLX5E_PORT_BNC] = PORT_BNC,
979 [MLX5E_PORT_MII] = PORT_MII,
980 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
981 [MLX5E_PORT_DA] = PORT_DA,
982 [MLX5E_PORT_OTHER] = PORT_OTHER,
983 };
984
985static u8 get_connector_port(u32 eth_proto, u8 connector_type)
f62b8bb8 986{
5b4793f8
EBE		 987 if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
988 return ptys2connector_type[connector_type];
989
f62b8bb8
AV		 990 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
991 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
992 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
993 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
994 return PORT_FIBRE;
995 }
996
997 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
998 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
999 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
1000 return PORT_DA;
1001 }
1002
1003 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
1004 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
1005 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
1006 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
1007 return PORT_NONE;
1008 }
1009
1010 return PORT_OTHER;
1011}
1012
665bc539
GP		 1013static void get_lp_advertising(u32 eth_proto_lp,
1014 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 1015{
665bc539
GP		 1016 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
1017
1018 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
f62b8bb8
AV		 1019}
1020
665bc539
GP		 1021static int mlx5e_get_link_ksettings(struct net_device *netdev,
1022 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 1023{
1024 struct mlx5e_priv *priv = netdev_priv(netdev);
1025 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 1026 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
b383b544
GP		 1027 u32 rx_pause = 0;
1028 u32 tx_pause = 0;
f62b8bb8
AV		 1029 u32 eth_proto_cap;
1030 u32 eth_proto_admin;
1031 u32 eth_proto_lp;
1032 u32 eth_proto_oper;
52244d96
GP		 1033 u8 an_disable_admin;
1034 u8 an_status;
5b4793f8 1035 u8 connector_type;
f62b8bb8
AV		 1036 int err;
1037
a05bdefa 1038 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
f62b8bb8
AV		 1039 if (err) {
1040 netdev_err(netdev, "%s: query port ptys failed: %d\n",
1041 __func__, err);
1042 goto err_query_ptys;
1043 }
1044
52244d96
GP		 1045 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
1046 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
1047 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
1048 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
1049 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
1050 an_status = MLX5_GET(ptys_reg, out, an_status);
5b4793f8 1051 connector_type = MLX5_GET(ptys_reg, out, connector_type);
f62b8bb8 1052
b383b544
GP		 1053 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
1054
665bc539
GP		 1055 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
1056 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
f62b8bb8 1057
665bc539 1058 get_supported(eth_proto_cap, link_ksettings);
b383b544 1059 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings);
665bc539 1060 get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
f62b8bb8
AV		 1061
1062 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1063
5b4793f8
EBE		 1064 link_ksettings->base.port = get_connector_port(eth_proto_oper,
1065 connector_type);
46e9d0b6
EBE		 1066 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
1067 connector_type);
665bc539 1068 get_lp_advertising(eth_proto_lp, link_ksettings);
f62b8bb8 1069
52244d96
GP		 1070 if (an_status == MLX5_AN_COMPLETE)
1071 ethtool_link_ksettings_add_link_mode(link_ksettings,
1072 lp_advertising, Autoneg);
1073
1074 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
1075 AUTONEG_ENABLE;
1076 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
1077 Autoneg);
1078 if (!an_disable_admin)
1079 ethtool_link_ksettings_add_link_mode(link_ksettings,
1080 advertising, Autoneg);
1081
f62b8bb8
AV		 1082err_query_ptys:
1083 return err;
1084}
1085
665bc539 1086static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
f62b8bb8
AV		 1087{
1088 u32 i, ptys_modes = 0;
1089
1090 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
665bc539
GP		 1091 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
1092 link_modes,
1093 __ETHTOOL_LINK_MODE_MASK_NBITS))
f62b8bb8
AV		 1094 ptys_modes |= MLX5E_PROT_MASK(i);
1095 }
1096
1097 return ptys_modes;
1098}
1099
1100static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
1101{
1102 u32 i, speed_links = 0;
1103
1104 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
1105 if (ptys2ethtool_table[i].speed == speed)
1106 speed_links |= MLX5E_PROT_MASK(i);
1107 }
1108
1109 return speed_links;
1110}
1111
665bc539
GP		 1112static int mlx5e_set_link_ksettings(struct net_device *netdev,
1113 const struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 1114{
1115 struct mlx5e_priv *priv = netdev_priv(netdev);
1116 struct mlx5_core_dev *mdev = priv->mdev;
52244d96
GP		 1117 u32 eth_proto_cap, eth_proto_admin;
1118 bool an_changes = false;
1119 u8 an_disable_admin;
1120 u8 an_disable_cap;
1121 bool an_disable;
f62b8bb8 1122 u32 link_modes;
52244d96 1123 u8 an_status;
f62b8bb8 1124 u32 speed;
f62b8bb8
AV		 1125 int err;
1126
665bc539 1127 speed = link_ksettings->base.speed;
f62b8bb8 1128
665bc539
GP		 1129 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
1130 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
f62b8bb8
AV		 1131 mlx5e_ethtool2ptys_speed_link(speed);
1132
1133 err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
1134 if (err) {
1135 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
1136 __func__, err);
1137 goto out;
1138 }
1139
1140 link_modes = link_modes & eth_proto_cap;
1141 if (!link_modes) {
1142 netdev_err(netdev, "%s: Not supported link mode(s) requested",
1143 __func__);
1144 err = -EINVAL;
1145 goto out;
1146 }
1147
1148 err = mlx5_query_port_proto_admin(mdev, &eth_proto_admin, MLX5_PTYS_EN);
1149 if (err) {
1150 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
1151 __func__, err);
1152 goto out;
1153 }
1154
52244d96
GP		 1155 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
1156 &an_disable_cap, &an_disable_admin);
1157
1158 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
1159 an_changes = ((!an_disable && an_disable_admin) ||
1160 (an_disable && !an_disable_admin));
1161
1162 if (!an_changes && link_modes == eth_proto_admin)
f62b8bb8
AV		 1163 goto out;
1164
52244d96 1165 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
667daeda 1166 mlx5_toggle_port_link(mdev);
f62b8bb8 1167
f62b8bb8
AV		 1168out:
1169 return err;
1170}
1171
2d75b2bc
AS		 1172static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1173{
1174 struct mlx5e_priv *priv = netdev_priv(netdev);
1175
6a9764ef 1176 return sizeof(priv->channels.params.toeplitz_hash_key);
2d75b2bc
AS		 1177}
1178
1179static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1180{
1181 return MLX5E_INDIR_RQT_SIZE;
1182}
1183
2be6967c
SM		 1184static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1185 u8 *hfunc)
1186{
1187 struct mlx5e_priv *priv = netdev_priv(netdev);
1188
2d75b2bc 1189 if (indir)
6a9764ef
SM		 1190 memcpy(indir, priv->channels.params.indirection_rqt,
1191 sizeof(priv->channels.params.indirection_rqt));
2d75b2bc
AS		 1192
1193 if (key)
6a9764ef
SM		 1194 memcpy(key, priv->channels.params.toeplitz_hash_key,
1195 sizeof(priv->channels.params.toeplitz_hash_key));
2d75b2bc 1196
2be6967c 1197 if (hfunc)
6a9764ef 1198 *hfunc = priv->channels.params.rss_hfunc;
2be6967c
SM		 1199
1200 return 0;
1201}
1202
bdfc028d
TT		 1203static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
1204{
bdfc028d 1205 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
a100ff3e
GP		 1206 struct mlx5_core_dev *mdev = priv->mdev;
1207 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
1208 int tt;
bdfc028d
TT		 1209
1210 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
bdfc028d 1211
a100ff3e
GP		 1212 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1213 memset(tirc, 0, ctxlen);
6a9764ef 1214 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
a100ff3e
GP		 1215 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
1216 }
bdfc028d
TT		 1217}
1218
98e81b0a 1219static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
2be6967c
SM		 1220 const u8 *key, const u8 hfunc)
1221{
98e81b0a 1222 struct mlx5e_priv *priv = netdev_priv(dev);
bdfc028d 1223 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1d3398fa 1224 bool hash_changed = false;
bdfc028d 1225 void *in;
2be6967c 1226
2d75b2bc
AS		 1227 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1228 (hfunc != ETH_RSS_HASH_XOR) &&
2be6967c
SM		 1229 (hfunc != ETH_RSS_HASH_TOP))
1230 return -EINVAL;
1231
1b9a07ee 1232 in = kvzalloc(inlen, GFP_KERNEL);
bdfc028d
TT		 1233 if (!in)
1234 return -ENOMEM;
1235
2be6967c
SM		 1236 mutex_lock(&priv->state_lock);
1237
1d3398fa 1238 if (hfunc != ETH_RSS_HASH_NO_CHANGE &&
6a9764ef
SM		 1239 hfunc != priv->channels.params.rss_hfunc) {
1240 priv->channels.params.rss_hfunc = hfunc;
1d3398fa
GP		 1241 hash_changed = true;
1242 }
1243
a5f97fee 1244 if (indir) {
6a9764ef
SM		 1245 memcpy(priv->channels.params.indirection_rqt, indir,
1246 sizeof(priv->channels.params.indirection_rqt));
a5f97fee
SM		 1247
1248 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1249 u32 rqtn = priv->indir_rqt.rqtn;
1250 struct mlx5e_redirect_rqt_param rrp = {
1251 .is_rss = true,
e270e966
AM		 1252 {
1253 .rss = {
1254 .hfunc = priv->channels.params.rss_hfunc,
1255 .channels = &priv->channels,
1256 },
1257 },
a5f97fee
SM		 1258 };
1259
1260 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1261 }
1262 }
1263
1d3398fa 1264 if (key) {
6a9764ef
SM		 1265 memcpy(priv->channels.params.toeplitz_hash_key, key,
1266 sizeof(priv->channels.params.toeplitz_hash_key));
1d3398fa 1267 hash_changed = hash_changed ||
6a9764ef 1268 priv->channels.params.rss_hfunc == ETH_RSS_HASH_TOP;
1d3398fa 1269 }
2d75b2bc 1270
1d3398fa
GP		 1271 if (hash_changed)
1272 mlx5e_modify_tirs_hash(priv, in, inlen);
2d75b2bc 1273
2be6967c
SM		 1274 mutex_unlock(&priv->state_lock);
1275
bdfc028d
TT		 1276 kvfree(in);
1277
1278 return 0;
2be6967c
SM		 1279}
1280
2d75b2bc
AS		 1281static int mlx5e_get_rxnfc(struct net_device *netdev,
1282 struct ethtool_rxnfc *info, u32 *rule_locs)
1283{
1284 struct mlx5e_priv *priv = netdev_priv(netdev);
1285 int err = 0;
1286
1287 switch (info->cmd) {
1288 case ETHTOOL_GRXRINGS:
6a9764ef 1289 info->data = priv->channels.params.num_channels;
2d75b2bc 1290 break;
f913a72a
MG		 1291 case ETHTOOL_GRXCLSRLCNT:
1292 info->rule_cnt = priv->fs.ethtool.tot_num_rules;
1293 break;
1294 case ETHTOOL_GRXCLSRULE:
1295 err = mlx5e_ethtool_get_flow(priv, info, info->fs.location);
1296 break;
1297 case ETHTOOL_GRXCLSRLALL:
1298 err = mlx5e_ethtool_get_all_flows(priv, info, rule_locs);
1299 break;
2d75b2bc
AS		 1300 default:
1301 err = -EOPNOTSUPP;
1302 break;
1303 }
1304
1305 return err;
1306}
1307
58d52291
AS		 1308static int mlx5e_get_tunable(struct net_device *dev,
1309 const struct ethtool_tunable *tuna,
1310 void *data)
1311{
1312 const struct mlx5e_priv *priv = netdev_priv(dev);
1313 int err = 0;
1314
1315 switch (tuna->id) {
1316 case ETHTOOL_TX_COPYBREAK:
6a9764ef 1317 *(u32 *)data = priv->channels.params.tx_max_inline;
58d52291
AS		 1318 break;
1319 default:
1320 err = -EINVAL;
1321 break;
1322 }
1323
1324 return err;
1325}
1326
1327static int mlx5e_set_tunable(struct net_device *dev,
1328 const struct ethtool_tunable *tuna,
1329 const void *data)
1330{
1331 struct mlx5e_priv *priv = netdev_priv(dev);
1332 struct mlx5_core_dev *mdev = priv->mdev;
546f18ed 1333 struct mlx5e_channels new_channels = {};
58d52291 1334 int err = 0;
546f18ed
SM		 1335 u32 val;
1336
1337 mutex_lock(&priv->state_lock);
58d52291
AS		 1338
1339 switch (tuna->id) {
1340 case ETHTOOL_TX_COPYBREAK:
1341 val = *(u32 *)data;
1342 if (val > mlx5e_get_max_inline_cap(mdev)) {
1343 err = -EINVAL;
1344 break;
1345 }
1346
546f18ed
SM		 1347 new_channels.params = priv->channels.params;
1348 new_channels.params.tx_max_inline = val;
98e81b0a 1349
546f18ed
SM		 1350 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1351 priv->channels.params = new_channels.params;
1352 break;
1353 }
98e81b0a 1354
546f18ed
SM		 1355 err = mlx5e_open_channels(priv, &new_channels);
1356 if (err)
1357 break;
2e20a151 1358 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
98e81b0a 1359
58d52291
AS		 1360 break;
1361 default:
1362 err = -EINVAL;
1363 break;
1364 }
1365
546f18ed 1366 mutex_unlock(&priv->state_lock);
58d52291
AS		 1367 return err;
1368}
1369
3c2d18ef
AS		 1370static void mlx5e_get_pauseparam(struct net_device *netdev,
1371 struct ethtool_pauseparam *pauseparam)
1372{
1373 struct mlx5e_priv *priv = netdev_priv(netdev);
1374 struct mlx5_core_dev *mdev = priv->mdev;
1375 int err;
1376
1377 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1378 &pauseparam->tx_pause);
1379 if (err) {
1380 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1381 __func__, err);
1382 }
1383}
1384
1385static int mlx5e_set_pauseparam(struct net_device *netdev,
1386 struct ethtool_pauseparam *pauseparam)
1387{
1388 struct mlx5e_priv *priv = netdev_priv(netdev);
1389 struct mlx5_core_dev *mdev = priv->mdev;
1390 int err;
1391
1392 if (pauseparam->autoneg)
1393 return -EINVAL;
1394
1395 err = mlx5_set_port_pause(mdev,
1396 pauseparam->rx_pause ? 1 : 0,
1397 pauseparam->tx_pause ? 1 : 0);
1398 if (err) {
1399 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1400 __func__, err);
1401 }
1402
1403 return err;
1404}
1405
3844b07e
FD		 1406int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1407 struct ethtool_ts_info *info)
ef9814de 1408{
ef9814de
EBE		 1409 int ret;
1410
3844b07e 1411 ret = ethtool_op_get_ts_info(priv->netdev, info);
ef9814de
EBE		 1412 if (ret)
1413 return ret;
1414
3d8c38af
EBE		 1415 info->phc_index = priv->tstamp.ptp ?
1416 ptp_clock_index(priv->tstamp.ptp) : -1;
ef9814de
EBE		 1417
1418 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1419 return 0;
1420
1421 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1422 SOF_TIMESTAMPING_RX_HARDWARE |
1423 SOF_TIMESTAMPING_RAW_HARDWARE;
1424
f0b38117
MD		 1425 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1426 BIT(HWTSTAMP_TX_ON);
ef9814de 1427
f0b38117
MD		 1428 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1429 BIT(HWTSTAMP_FILTER_ALL);
ef9814de
EBE		 1430
1431 return 0;
1432}
1433
3844b07e
FD		 1434static int mlx5e_get_ts_info(struct net_device *dev,
1435 struct ethtool_ts_info *info)
1436{
1437 struct mlx5e_priv *priv = netdev_priv(dev);
1438
1439 return mlx5e_ethtool_get_ts_info(priv, info);
1440}
1441
928cfe87
TT		 1442static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1443{
1444 __u32 ret = 0;
1445
1446 if (MLX5_CAP_GEN(mdev, wol_g))
1447 ret |= WAKE_MAGIC;
1448
1449 if (MLX5_CAP_GEN(mdev, wol_s))
1450 ret |= WAKE_MAGICSECURE;
1451
1452 if (MLX5_CAP_GEN(mdev, wol_a))
1453 ret |= WAKE_ARP;
1454
1455 if (MLX5_CAP_GEN(mdev, wol_b))
1456 ret |= WAKE_BCAST;
1457
1458 if (MLX5_CAP_GEN(mdev, wol_m))
1459 ret |= WAKE_MCAST;
1460
1461 if (MLX5_CAP_GEN(mdev, wol_u))
1462 ret |= WAKE_UCAST;
1463
1464 if (MLX5_CAP_GEN(mdev, wol_p))
1465 ret |= WAKE_PHY;
1466
1467 return ret;
1468}
1469
1470static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1471{
1472 __u32 ret = 0;
1473
1474 if (mode & MLX5_WOL_MAGIC)
1475 ret |= WAKE_MAGIC;
1476
1477 if (mode & MLX5_WOL_SECURED_MAGIC)
1478 ret |= WAKE_MAGICSECURE;
1479
1480 if (mode & MLX5_WOL_ARP)
1481 ret |= WAKE_ARP;
1482
1483 if (mode & MLX5_WOL_BROADCAST)
1484 ret |= WAKE_BCAST;
1485
1486 if (mode & MLX5_WOL_MULTICAST)
1487 ret |= WAKE_MCAST;
1488
1489 if (mode & MLX5_WOL_UNICAST)
1490 ret |= WAKE_UCAST;
1491
1492 if (mode & MLX5_WOL_PHY_ACTIVITY)
1493 ret |= WAKE_PHY;
1494
1495 return ret;
1496}
1497
1498static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1499{
1500 u8 ret = 0;
1501
1502 if (mode & WAKE_MAGIC)
1503 ret |= MLX5_WOL_MAGIC;
1504
1505 if (mode & WAKE_MAGICSECURE)
1506 ret |= MLX5_WOL_SECURED_MAGIC;
1507
1508 if (mode & WAKE_ARP)
1509 ret |= MLX5_WOL_ARP;
1510
1511 if (mode & WAKE_BCAST)
1512 ret |= MLX5_WOL_BROADCAST;
1513
1514 if (mode & WAKE_MCAST)
1515 ret |= MLX5_WOL_MULTICAST;
1516
1517 if (mode & WAKE_UCAST)
1518 ret |= MLX5_WOL_UNICAST;
1519
1520 if (mode & WAKE_PHY)
1521 ret |= MLX5_WOL_PHY_ACTIVITY;
1522
1523 return ret;
1524}
1525
1526static void mlx5e_get_wol(struct net_device *netdev,
1527 struct ethtool_wolinfo *wol)
1528{
1529 struct mlx5e_priv *priv = netdev_priv(netdev);
1530 struct mlx5_core_dev *mdev = priv->mdev;
1531 u8 mlx5_wol_mode;
1532 int err;
1533
1534 memset(wol, 0, sizeof(*wol));
1535
1536 wol->supported = mlx5e_get_wol_supported(mdev);
1537 if (!wol->supported)
1538 return;
1539
1540 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1541 if (err)
1542 return;
1543
1544 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1545}
1546
1547static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1548{
1549 struct mlx5e_priv *priv = netdev_priv(netdev);
1550 struct mlx5_core_dev *mdev = priv->mdev;
1551 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1552 u32 mlx5_wol_mode;
1553
1554 if (!wol_supported)
9eb78923 1555 return -EOPNOTSUPP;
928cfe87
TT		 1556
1557 if (wol->wolopts & ~wol_supported)
1558 return -EINVAL;
1559
1560 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1561
1562 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1563}
1564
da54d24e
GP		 1565static int mlx5e_set_phys_id(struct net_device *dev,
1566 enum ethtool_phys_id_state state)
1567{
1568 struct mlx5e_priv *priv = netdev_priv(dev);
1569 struct mlx5_core_dev *mdev = priv->mdev;
1570 u16 beacon_duration;
1571
1572 if (!MLX5_CAP_GEN(mdev, beacon_led))
1573 return -EOPNOTSUPP;
1574
1575 switch (state) {
1576 case ETHTOOL_ID_ACTIVE:
1577 beacon_duration = MLX5_BEACON_DURATION_INF;
1578 break;
1579 case ETHTOOL_ID_INACTIVE:
1580 beacon_duration = MLX5_BEACON_DURATION_OFF;
1581 break;
1582 default:
1583 return -EOPNOTSUPP;
1584 }
1585
1586 return mlx5_set_port_beacon(mdev, beacon_duration);
1587}
1588
bb64143e
GP		 1589static int mlx5e_get_module_info(struct net_device *netdev,
1590 struct ethtool_modinfo *modinfo)
1591{
1592 struct mlx5e_priv *priv = netdev_priv(netdev);
1593 struct mlx5_core_dev *dev = priv->mdev;
1594 int size_read = 0;
1595 u8 data[4];
1596
1597 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1598 if (size_read < 2)
1599 return -EIO;
1600
1601 /* data[0] = identifier byte */
1602 switch (data[0]) {
1603 case MLX5_MODULE_ID_QSFP:
1604 modinfo->type = ETH_MODULE_SFF_8436;
1605 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1606 break;
1607 case MLX5_MODULE_ID_QSFP_PLUS:
1608 case MLX5_MODULE_ID_QSFP28:
1609 /* data[1] = revision id */
1610 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1611 modinfo->type = ETH_MODULE_SFF_8636;
1612 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1613 } else {
1614 modinfo->type = ETH_MODULE_SFF_8436;
1615 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1616 }
1617 break;
1618 case MLX5_MODULE_ID_SFP:
1619 modinfo->type = ETH_MODULE_SFF_8472;
1620 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1621 break;
1622 default:
1623 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1624 __func__, data[0]);
1625 return -EINVAL;
1626 }
1627
1628 return 0;
1629}
1630
1631static int mlx5e_get_module_eeprom(struct net_device *netdev,
1632 struct ethtool_eeprom *ee,
1633 u8 *data)
1634{
1635 struct mlx5e_priv *priv = netdev_priv(netdev);
1636 struct mlx5_core_dev *mdev = priv->mdev;
1637 int offset = ee->offset;
1638 int size_read;
1639 int i = 0;
1640
1641 if (!ee->len)
1642 return -EINVAL;
1643
1644 memset(data, 0, ee->len);
1645
1646 while (i < ee->len) {
1647 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1648 data + i);
1649
1650 if (!size_read)
1651 /* Done reading */
1652 return 0;
1653
1654 if (size_read < 0) {
1655 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1656 __func__, size_read);
1657 return 0;
1658 }
1659
1660 i += size_read;
1661 offset += size_read;
1662 }
1663
1664 return 0;
1665}
1666
4e59e288
GP		 1667typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1668
9908aa29 1669static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
4e59e288 1670{
9908aa29
TT		 1671 struct mlx5e_priv *priv = netdev_priv(netdev);
1672 struct mlx5_core_dev *mdev = priv->mdev;
be7e87f9 1673 struct mlx5e_channels new_channels = {};
9908aa29
TT		 1674 bool rx_mode_changed;
1675 u8 rx_cq_period_mode;
1676 int err = 0;
9908aa29
TT		 1677
1678 rx_cq_period_mode = enable ?
1679 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1680 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
6a9764ef 1681 rx_mode_changed = rx_cq_period_mode != priv->channels.params.rx_cq_period_mode;
9908aa29
TT		 1682
1683 if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1684 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
9eb78923 1685 return -EOPNOTSUPP;
9908aa29
TT		 1686
1687 if (!rx_mode_changed)
1688 return 0;
1689
be7e87f9
SM		 1690 new_channels.params = priv->channels.params;
1691 mlx5e_set_rx_cq_mode_params(&new_channels.params, rx_cq_period_mode);
9908aa29 1692
be7e87f9
SM		 1693 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1694 priv->channels.params = new_channels.params;
1695 return 0;
1696 }
1697
1698 err = mlx5e_open_channels(priv, &new_channels);
1699 if (err)
1700 return err;
9908aa29 1701
2e20a151 1702 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
be7e87f9
SM		 1703 return 0;
1704}
9908aa29 1705
be7e87f9
SM		 1706int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1707{
1708 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1709 struct mlx5e_channels new_channels = {};
1710 int err = 0;
1711
1712 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1713 return new_val ? -EOPNOTSUPP : 0;
1714
1715 if (curr_val == new_val)
1716 return 0;
1717
1718 new_channels.params = priv->channels.params;
1719 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1720
1721 mlx5e_set_rq_type_params(priv->mdev, &new_channels.params,
1722 new_channels.params.rq_wq_type);
1723
1724 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1725 priv->channels.params = new_channels.params;
1726 return 0;
1727 }
1728
1729 err = mlx5e_open_channels(priv, &new_channels);
1730 if (err)
1731 return err;
1732
2e20a151 1733 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
be7e87f9 1734 return 0;
4e59e288
GP		 1735}
1736
9bcc8606
SD		 1737static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1738 bool enable)
1739{
1740 struct mlx5e_priv *priv = netdev_priv(netdev);
1741 struct mlx5_core_dev *mdev = priv->mdev;
9bcc8606
SD		 1742
1743 if (!MLX5_CAP_GEN(mdev, cqe_compression))
9eb78923 1744 return -EOPNOTSUPP;
9bcc8606
SD		 1745
1746 if (enable && priv->tstamp.hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
1747 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1748 return -EINVAL;
1749 }
1750
5eb0249b 1751 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
6a9764ef 1752 priv->channels.params.rx_cqe_compress_def = enable;
9bcc8606 1753
5eb0249b 1754 return 0;
9bcc8606
SD		 1755}
1756
4e59e288
GP		 1757static int mlx5e_handle_pflag(struct net_device *netdev,
1758 u32 wanted_flags,
1759 enum mlx5e_priv_flag flag,
1760 mlx5e_pflag_handler pflag_handler)
1761{
1762 struct mlx5e_priv *priv = netdev_priv(netdev);
1763 bool enable = !!(wanted_flags & flag);
6a9764ef 1764 u32 changes = wanted_flags ^ priv->channels.params.pflags;
4e59e288
GP		 1765 int err;
1766
1767 if (!(changes & flag))
1768 return 0;
1769
1770 err = pflag_handler(netdev, enable);
1771 if (err) {
1772 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1773 enable ? "Enable" : "Disable", flag, err);
1774 return err;
1775 }
1776
6a9764ef 1777 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
4e59e288
GP		 1778 return 0;
1779}
1780
1781static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1782{
1783 struct mlx5e_priv *priv = netdev_priv(netdev);
1784 int err;
1785
1786 mutex_lock(&priv->state_lock);
9908aa29
TT		 1787 err = mlx5e_handle_pflag(netdev, pflags,
1788 MLX5E_PFLAG_RX_CQE_BASED_MODER,
1789 set_pflag_rx_cqe_based_moder);
9bcc8606
SD		 1790 if (err)
1791 goto out;
4e59e288 1792
9bcc8606
SD		 1793 err = mlx5e_handle_pflag(netdev, pflags,
1794 MLX5E_PFLAG_RX_CQE_COMPRESS,
1795 set_pflag_rx_cqe_compress);
1796
1797out:
4e59e288 1798 mutex_unlock(&priv->state_lock);
9bcc8606 1799 return err;
4e59e288
GP		 1800}
1801
1802static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1803{
1804 struct mlx5e_priv *priv = netdev_priv(netdev);
1805
6a9764ef 1806 return priv->channels.params.pflags;
4e59e288
GP		 1807}
1808
6dc6071c
MG		 1809static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1810{
1811 int err = 0;
1812 struct mlx5e_priv *priv = netdev_priv(dev);
1813
1814 switch (cmd->cmd) {
1815 case ETHTOOL_SRXCLSRLINS:
1816 err = mlx5e_ethtool_flow_replace(priv, &cmd->fs);
1817 break;
1818 case ETHTOOL_SRXCLSRLDEL:
1819 err = mlx5e_ethtool_flow_remove(priv, cmd->fs.location);
1820 break;
1821 default:
1822 err = -EOPNOTSUPP;
1823 break;
1824 }
1825
1826 return err;
1827}
1828
3ffaabec
OG		 1829int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1830 struct ethtool_flash *flash)
1831{
1832 struct mlx5_core_dev *mdev = priv->mdev;
1833 struct net_device *dev = priv->netdev;
1834 const struct firmware *fw;
1835 int err;
1836
1837 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1838 return -EOPNOTSUPP;
1839
1840 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1841 if (err)
1842 return err;
1843
1844 dev_hold(dev);
1845 rtnl_unlock();
1846
1847 err = mlx5_firmware_flash(mdev, fw);
1848 release_firmware(fw);
1849
1850 rtnl_lock();
1851 dev_put(dev);
1852 return err;
1853}
1854
1855static int mlx5e_flash_device(struct net_device *dev,
1856 struct ethtool_flash *flash)
1857{
1858 struct mlx5e_priv *priv = netdev_priv(dev);
1859
1860 return mlx5e_ethtool_flash_device(priv, flash);
1861}
1862
f62b8bb8
AV		 1863const struct ethtool_ops mlx5e_ethtool_ops = {
1864 .get_drvinfo = mlx5e_get_drvinfo,
1865 .get_link = ethtool_op_get_link,
1866 .get_strings = mlx5e_get_strings,
1867 .get_sset_count = mlx5e_get_sset_count,
1868 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1869 .get_ringparam = mlx5e_get_ringparam,
1870 .set_ringparam = mlx5e_set_ringparam,
1871 .get_channels = mlx5e_get_channels,
1872 .set_channels = mlx5e_set_channels,
1873 .get_coalesce = mlx5e_get_coalesce,
1874 .set_coalesce = mlx5e_set_coalesce,
665bc539
GP		 1875 .get_link_ksettings = mlx5e_get_link_ksettings,
1876 .set_link_ksettings = mlx5e_set_link_ksettings,
2d75b2bc
AS		 1877 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1878 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2be6967c
SM		 1879 .get_rxfh = mlx5e_get_rxfh,
1880 .set_rxfh = mlx5e_set_rxfh,
2d75b2bc 1881 .get_rxnfc = mlx5e_get_rxnfc,
6dc6071c 1882 .set_rxnfc = mlx5e_set_rxnfc,
3ffaabec 1883 .flash_device = mlx5e_flash_device,
58d52291
AS		 1884 .get_tunable = mlx5e_get_tunable,
1885 .set_tunable = mlx5e_set_tunable,
3c2d18ef
AS		 1886 .get_pauseparam = mlx5e_get_pauseparam,
1887 .set_pauseparam = mlx5e_set_pauseparam,
ef9814de 1888 .get_ts_info = mlx5e_get_ts_info,
da54d24e 1889 .set_phys_id = mlx5e_set_phys_id,
928cfe87
TT		 1890 .get_wol = mlx5e_get_wol,
1891 .set_wol = mlx5e_set_wol,
bb64143e
GP		 1892 .get_module_info = mlx5e_get_module_info,
1893 .get_module_eeprom = mlx5e_get_module_eeprom,
4e59e288 1894 .get_priv_flags = mlx5e_get_priv_flags,
d605d668
KH		 1895 .set_priv_flags = mlx5e_set_priv_flags,
1896 .self_test = mlx5e_self_test,
f62b8bb8 1897};
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