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net/mlx5e: Reduce memory consumption on kdump kernel
[thirdparty/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "en.h"
34
35static void mlx5e_get_drvinfo(struct net_device *dev,
36 struct ethtool_drvinfo *drvinfo)
37{
38 struct mlx5e_priv *priv = netdev_priv(dev);
39 struct mlx5_core_dev *mdev = priv->mdev;
40
41 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
42 strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")",
43 sizeof(drvinfo->version));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
45 "%d.%d.%d",
46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev));
47 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
48 sizeof(drvinfo->bus_info));
49}
50
665bc539
GP		 51struct ptys2ethtool_config {
52 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
53 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
f62b8bb8 54 u32 speed;
f62b8bb8
AV		 55};
56
665bc539
GP		 57static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
58
59#define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
60 ({ \
61 struct ptys2ethtool_config *cfg; \
62 const unsigned int modes[] = { __VA_ARGS__ }; \
63 unsigned int i; \
64 cfg = &ptys2ethtool_table[reg_]; \
65 cfg->speed = speed_; \
66 bitmap_zero(cfg->supported, \
67 __ETHTOOL_LINK_MODE_MASK_NBITS); \
68 bitmap_zero(cfg->advertised, \
69 __ETHTOOL_LINK_MODE_MASK_NBITS); \
70 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
71 __set_bit(modes[i], cfg->supported); \
72 __set_bit(modes[i], cfg->advertised); \
73 } \
74 })
75
76void mlx5e_build_ptys2ethtool_map(void)
77{
78 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000,
79 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
80 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000,
81 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
82 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000,
83 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
84 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000,
85 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
86 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000,
87 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
88 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000,
89 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
90 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000,
91 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
92 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000,
93 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000,
95 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000,
97 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000,
99 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000,
101 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000,
103 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000,
105 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000,
107 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000,
109 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000,
111 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000,
113 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000,
115 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000,
117 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000,
119 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000,
121 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000,
123 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000,
125 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000,
127 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
128}
129
cf678570
GP		 130static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
131{
132 struct mlx5_core_dev *mdev = priv->mdev;
133 u8 pfc_en_tx;
134 u8 pfc_en_rx;
135 int err;
136
137 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
138
139 return err ? 0 : pfc_en_tx | pfc_en_rx;
140}
141
e989d5a5
GP		 142static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
143{
144 struct mlx5_core_dev *mdev = priv->mdev;
145 u32 rx_pause;
146 u32 tx_pause;
147 int err;
148
149 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
150
151 return err ? false : rx_pause | tx_pause;
152}
153
593cf338 154#define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
9218b44d
GP		 155#define MLX5E_NUM_RQ_STATS(priv) \
156 (NUM_RQ_STATS * priv->params.num_channels * \
157 test_bit(MLX5E_STATE_OPENED, &priv->state))
158#define MLX5E_NUM_SQ_STATS(priv) \
159 (NUM_SQ_STATS * priv->params.num_channels * priv->params.num_tc * \
160 test_bit(MLX5E_STATE_OPENED, &priv->state))
ed80ec4c 161#define MLX5E_NUM_PFC_COUNTERS(priv) \
e989d5a5
GP		 162 ((mlx5e_query_global_pause_combined(priv) + hweight8(mlx5e_query_pfc_combined(priv))) * \
163 NUM_PPORT_PER_PRIO_PFC_COUNTERS)
593cf338 164
f62b8bb8
AV		 165static int mlx5e_get_sset_count(struct net_device *dev, int sset)
166{
167 struct mlx5e_priv *priv = netdev_priv(dev);
168
169 switch (sset) {
170 case ETH_SS_STATS:
9218b44d 171 return NUM_SW_COUNTERS +
593cf338 172 MLX5E_NUM_Q_CNTRS(priv) +
5db0a4f6 173 NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS(priv) +
0f7f3481 174 NUM_PCIE_COUNTERS(priv) +
9218b44d 175 MLX5E_NUM_RQ_STATS(priv) +
cf678570 176 MLX5E_NUM_SQ_STATS(priv) +
bedb7c90
HN		 177 MLX5E_NUM_PFC_COUNTERS(priv) +
178 ARRAY_SIZE(mlx5e_pme_status_desc) +
179 ARRAY_SIZE(mlx5e_pme_error_desc);
180
4e59e288
GP		 181 case ETH_SS_PRIV_FLAGS:
182 return ARRAY_SIZE(mlx5e_priv_flags);
d605d668
KH		 183 case ETH_SS_TEST:
184 return mlx5e_self_test_num(priv);
f62b8bb8
AV		 185 /* fallthrough */
186 default:
187 return -EOPNOTSUPP;
188 }
189}
190
9218b44d
GP		 191static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
192{
cf678570
GP		 193 int i, j, tc, prio, idx = 0;
194 unsigned long pfc_combined;
9218b44d
GP		 195
196 /* SW counters */
197 for (i = 0; i < NUM_SW_COUNTERS; i++)
bfe6d8d1 198 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
9218b44d
GP		 199
200 /* Q counters */
201 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
bfe6d8d1 202 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].format);
9218b44d
GP		 203
204 /* VPORT counters */
205 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
206 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 207 vport_stats_desc[i].format);
9218b44d
GP		 208
209 /* PPORT counters */
210 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
211 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 212 pport_802_3_stats_desc[i].format);
9218b44d
GP		 213
214 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
215 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 216 pport_2863_stats_desc[i].format);
9218b44d
GP		 217
218 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
219 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 220 pport_2819_stats_desc[i].format);
9218b44d 221
5db0a4f6
GP		 222 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
223 strcpy(data + (idx++) * ETH_GSTRING_LEN,
224 pport_phy_statistical_stats_desc[i].format);
225
0f7f3481
GP		 226 for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
227 strcpy(data + (idx++) * ETH_GSTRING_LEN,
228 pcie_perf_stats_desc[i].format);
229
cf678570
GP		 230 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
231 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
bfe6d8d1
GP		 232 sprintf(data + (idx++) * ETH_GSTRING_LEN,
233 pport_per_prio_traffic_stats_desc[i].format, prio);
cf678570
GP		 234 }
235
236 pfc_combined = mlx5e_query_pfc_combined(priv);
237 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
238 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
e989d5a5
GP		 239 char pfc_string[ETH_GSTRING_LEN];
240
241 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
bfe6d8d1 242 sprintf(data + (idx++) * ETH_GSTRING_LEN,
e989d5a5
GP		 243 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
244 }
245 }
246
247 if (mlx5e_query_global_pause_combined(priv)) {
248 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
249 sprintf(data + (idx++) * ETH_GSTRING_LEN,
250 pport_per_prio_pfc_stats_desc[i].format, "global");
cf678570
GP		 251 }
252 }
253
bedb7c90
HN		 254 /* port module event counters */
255 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
256 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
257
258 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
259 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
260
9218b44d
GP		 261 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
262 return;
263
264 /* per channel counters */
265 for (i = 0; i < priv->params.num_channels; i++)
266 for (j = 0; j < NUM_RQ_STATS; j++)
bfe6d8d1
GP		 267 sprintf(data + (idx++) * ETH_GSTRING_LEN,
268 rq_stats_desc[j].format, i);
9218b44d
GP		 269
270 for (tc = 0; tc < priv->params.num_tc; tc++)
271 for (i = 0; i < priv->params.num_channels; i++)
272 for (j = 0; j < NUM_SQ_STATS; j++)
273 sprintf(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1
GP		 274 sq_stats_desc[j].format,
275 priv->channeltc_to_txq_map[i][tc]);
9218b44d
GP		 276}
277
f62b8bb8
AV		 278static void mlx5e_get_strings(struct net_device *dev,
279 uint32_t stringset, uint8_t *data)
280{
f62b8bb8 281 struct mlx5e_priv *priv = netdev_priv(dev);
4e59e288 282 int i;
f62b8bb8
AV		 283
284 switch (stringset) {
285 case ETH_SS_PRIV_FLAGS:
4e59e288
GP		 286 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
287 strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
f62b8bb8
AV		 288 break;
289
290 case ETH_SS_TEST:
d605d668
KH		 291 for (i = 0; i < mlx5e_self_test_num(priv); i++)
292 strcpy(data + i * ETH_GSTRING_LEN,
293 mlx5e_self_tests[i]);
f62b8bb8
AV		 294 break;
295
296 case ETH_SS_STATS:
9218b44d 297 mlx5e_fill_stats_strings(priv, data);
f62b8bb8
AV		 298 break;
299 }
300}
301
302static void mlx5e_get_ethtool_stats(struct net_device *dev,
303 struct ethtool_stats *stats, u64 *data)
304{
305 struct mlx5e_priv *priv = netdev_priv(dev);
bedb7c90 306 struct mlx5_priv *mlx5_priv;
cf678570
GP		 307 int i, j, tc, prio, idx = 0;
308 unsigned long pfc_combined;
f62b8bb8
AV		 309
310 if (!data)
311 return;
312
313 mutex_lock(&priv->state_lock);
314 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
315 mlx5e_update_stats(priv);
316 mutex_unlock(&priv->state_lock);
317
9218b44d
GP		 318 for (i = 0; i < NUM_SW_COUNTERS; i++)
319 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
320 sw_stats_desc, i);
f62b8bb8 321
593cf338 322 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
9218b44d
GP		 323 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
324 q_stats_desc, i);
325
326 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
327 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
328 vport_stats_desc, i);
593cf338 329
9218b44d
GP		 330 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
331 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
332 pport_802_3_stats_desc, i);
333
334 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
335 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
336 pport_2863_stats_desc, i);
337
338 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
339 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
340 pport_2819_stats_desc, i);
341
5db0a4f6
GP		 342 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
343 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
344 pport_phy_statistical_stats_desc, i);
345
0f7f3481
GP		 346 for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
347 data[idx++] = MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
348 pcie_perf_stats_desc, i);
349
cf678570
GP		 350 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
351 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
352 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
353 pport_per_prio_traffic_stats_desc, i);
354 }
355
356 pfc_combined = mlx5e_query_pfc_combined(priv);
357 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
358 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
359 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
360 pport_per_prio_pfc_stats_desc, i);
361 }
362 }
363
e989d5a5
GP		 364 if (mlx5e_query_global_pause_combined(priv)) {
365 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
366 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
4e39883d 367 pport_per_prio_pfc_stats_desc, i);
e989d5a5
GP		 368 }
369 }
370
bedb7c90
HN		 371 /* port module event counters */
372 mlx5_priv = &priv->mdev->priv;
373 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
374 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
375 mlx5e_pme_status_desc, i);
376
377 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
378 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
379 mlx5e_pme_error_desc, i);
380
9218b44d
GP		 381 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
382 return;
efea389d 383
f62b8bb8
AV		 384 /* per channel counters */
385 for (i = 0; i < priv->params.num_channels; i++)
386 for (j = 0; j < NUM_RQ_STATS; j++)
9218b44d
GP		 387 data[idx++] =
388 MLX5E_READ_CTR64_CPU(&priv->channel[i]->rq.stats,
389 rq_stats_desc, j);
f62b8bb8 390
3b619524
TT		 391 for (tc = 0; tc < priv->params.num_tc; tc++)
392 for (i = 0; i < priv->params.num_channels; i++)
f62b8bb8 393 for (j = 0; j < NUM_SQ_STATS; j++)
9218b44d
GP		 394 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->channel[i]->sq[tc].stats,
395 sq_stats_desc, j);
f62b8bb8
AV		 396}
397
cc8e9ebf
EBE		 398static u32 mlx5e_rx_wqes_to_packets(struct mlx5e_priv *priv, int rq_wq_type,
399 int num_wqe)
400{
401 int packets_per_wqe;
402 int stride_size;
403 int num_strides;
404 int wqe_size;
405
406 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
407 return num_wqe;
408
409 stride_size = 1 << priv->params.mpwqe_log_stride_sz;
410 num_strides = 1 << priv->params.mpwqe_log_num_strides;
411 wqe_size = stride_size * num_strides;
412
413 packets_per_wqe = wqe_size /
414 ALIGN(ETH_DATA_LEN, stride_size);
415 return (1 << (order_base_2(num_wqe * packets_per_wqe) - 1));
416}
417
418static u32 mlx5e_packets_to_rx_wqes(struct mlx5e_priv *priv, int rq_wq_type,
419 int num_packets)
420{
421 int packets_per_wqe;
422 int stride_size;
423 int num_strides;
424 int wqe_size;
425 int num_wqes;
426
427 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
428 return num_packets;
429
430 stride_size = 1 << priv->params.mpwqe_log_stride_sz;
431 num_strides = 1 << priv->params.mpwqe_log_num_strides;
432 wqe_size = stride_size * num_strides;
433
434 num_packets = (1 << order_base_2(num_packets));
435
436 packets_per_wqe = wqe_size /
437 ALIGN(ETH_DATA_LEN, stride_size);
438 num_wqes = DIV_ROUND_UP(num_packets, packets_per_wqe);
439 return 1 << (order_base_2(num_wqes));
440}
441
f62b8bb8
AV		 442static void mlx5e_get_ringparam(struct net_device *dev,
443 struct ethtool_ringparam *param)
444{
445 struct mlx5e_priv *priv = netdev_priv(dev);
461017cb 446 int rq_wq_type = priv->params.rq_wq_type;
f62b8bb8 447
cc8e9ebf
EBE		 448 param->rx_max_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
449 1 << mlx5_max_log_rq_size(rq_wq_type));
f62b8bb8 450 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
cc8e9ebf
EBE		 451 param->rx_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
452 1 << priv->params.log_rq_size);
f62b8bb8
AV		 453 param->tx_pending = 1 << priv->params.log_sq_size;
454}
455
456static int mlx5e_set_ringparam(struct net_device *dev,
457 struct ethtool_ringparam *param)
458{
459 struct mlx5e_priv *priv = netdev_priv(dev);
98e81b0a 460 bool was_opened;
461017cb 461 int rq_wq_type = priv->params.rq_wq_type;
cc8e9ebf
EBE		 462 u32 rx_pending_wqes;
463 u32 min_rq_size;
464 u32 max_rq_size;
f62b8bb8
AV		 465 u16 min_rx_wqes;
466 u8 log_rq_size;
467 u8 log_sq_size;
fe4c988b 468 u32 num_mtts;
f62b8bb8
AV		 469 int err = 0;
470
471 if (param->rx_jumbo_pending) {
472 netdev_info(dev, "%s: rx_jumbo_pending not supported\n",
473 __func__);
474 return -EINVAL;
475 }
476 if (param->rx_mini_pending) {
477 netdev_info(dev, "%s: rx_mini_pending not supported\n",
478 __func__);
479 return -EINVAL;
480 }
cc8e9ebf
EBE		 481
482 min_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
483 1 << mlx5_min_log_rq_size(rq_wq_type));
484 max_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
485 1 << mlx5_max_log_rq_size(rq_wq_type));
486 rx_pending_wqes = mlx5e_packets_to_rx_wqes(priv, rq_wq_type,
487 param->rx_pending);
488
489 if (param->rx_pending < min_rq_size) {
f62b8bb8
AV		 490 netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n",
491 __func__, param->rx_pending,
cc8e9ebf 492 min_rq_size);
f62b8bb8
AV		 493 return -EINVAL;
494 }
cc8e9ebf 495 if (param->rx_pending > max_rq_size) {
f62b8bb8
AV		 496 netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n",
497 __func__, param->rx_pending,
cc8e9ebf 498 max_rq_size);
f62b8bb8
AV		 499 return -EINVAL;
500 }
fe4c988b 501
ec8b9981 502 num_mtts = MLX5E_REQUIRED_MTTS(rx_pending_wqes);
fe4c988b
SM		 503 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
504 !MLX5E_VALID_NUM_MTTS(num_mtts)) {
505 netdev_info(dev, "%s: rx_pending (%d) request can't be satisfied, try to reduce.\n",
506 __func__, param->rx_pending);
507 return -EINVAL;
508 }
509
f62b8bb8
AV		 510 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
511 netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n",
512 __func__, param->tx_pending,
513 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
514 return -EINVAL;
515 }
516 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
517 netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n",
518 __func__, param->tx_pending,
519 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
520 return -EINVAL;
521 }
522
cc8e9ebf 523 log_rq_size = order_base_2(rx_pending_wqes);
f62b8bb8 524 log_sq_size = order_base_2(param->tx_pending);
cc8e9ebf 525 min_rx_wqes = mlx5_min_rx_wqes(rq_wq_type, rx_pending_wqes);
f62b8bb8
AV		 526
527 if (log_rq_size == priv->params.log_rq_size &&
528 log_sq_size == priv->params.log_sq_size &&
529 min_rx_wqes == priv->params.min_rx_wqes)
530 return 0;
531
532 mutex_lock(&priv->state_lock);
98e81b0a
AS		 533
534 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
535 if (was_opened)
536 mlx5e_close_locked(dev);
537
538 priv->params.log_rq_size = log_rq_size;
539 priv->params.log_sq_size = log_sq_size;
540 priv->params.min_rx_wqes = min_rx_wqes;
541
542 if (was_opened)
543 err = mlx5e_open_locked(dev);
544
f62b8bb8
AV		 545 mutex_unlock(&priv->state_lock);
546
547 return err;
548}
549
550static void mlx5e_get_channels(struct net_device *dev,
551 struct ethtool_channels *ch)
552{
553 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 554
b4e029da 555 ch->max_combined = priv->profile->max_nch(priv->mdev);
f62b8bb8
AV		 556 ch->combined_count = priv->params.num_channels;
557}
558
559static int mlx5e_set_channels(struct net_device *dev,
560 struct ethtool_channels *ch)
561{
562 struct mlx5e_priv *priv = netdev_priv(dev);
b4e029da 563 int ncv = priv->profile->max_nch(priv->mdev);
f62b8bb8 564 unsigned int count = ch->combined_count;
45bf454a 565 bool arfs_enabled;
98e81b0a 566 bool was_opened;
f62b8bb8
AV		 567 int err = 0;
568
569 if (!count) {
570 netdev_info(dev, "%s: combined_count=0 not supported\n",
571 __func__);
572 return -EINVAL;
573 }
574 if (ch->rx_count || ch->tx_count) {
575 netdev_info(dev, "%s: separate rx/tx count not supported\n",
576 __func__);
577 return -EINVAL;
578 }
579 if (count > ncv) {
580 netdev_info(dev, "%s: count (%d) > max (%d)\n",
581 __func__, count, ncv);
582 return -EINVAL;
583 }
584
585 if (priv->params.num_channels == count)
586 return 0;
587
588 mutex_lock(&priv->state_lock);
98e81b0a
AS		 589
590 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
591 if (was_opened)
592 mlx5e_close_locked(dev);
593
45bf454a
MG		 594 arfs_enabled = dev->features & NETIF_F_NTUPLE;
595 if (arfs_enabled)
596 mlx5e_arfs_disable(priv);
597
98e81b0a 598 priv->params.num_channels = count;
d8c9660d 599 mlx5e_build_default_indir_rqt(priv->mdev, priv->params.indirection_rqt,
85082dba 600 MLX5E_INDIR_RQT_SIZE, count);
98e81b0a
AS		 601
602 if (was_opened)
603 err = mlx5e_open_locked(dev);
45bf454a
MG		 604 if (err)
605 goto out;
606
607 if (arfs_enabled) {
608 err = mlx5e_arfs_enable(priv);
609 if (err)
610 netdev_err(dev, "%s: mlx5e_arfs_enable failed: %d\n",
611 __func__, err);
612 }
98e81b0a 613
45bf454a 614out:
f62b8bb8
AV		 615 mutex_unlock(&priv->state_lock);
616
617 return err;
618}
619
620static int mlx5e_get_coalesce(struct net_device *netdev,
621 struct ethtool_coalesce *coal)
622{
623 struct mlx5e_priv *priv = netdev_priv(netdev);
624
7524a5d8
GP		 625 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
626 return -ENOTSUPP;
627
9908aa29
TT		 628 coal->rx_coalesce_usecs = priv->params.rx_cq_moderation.usec;
629 coal->rx_max_coalesced_frames = priv->params.rx_cq_moderation.pkts;
630 coal->tx_coalesce_usecs = priv->params.tx_cq_moderation.usec;
631 coal->tx_max_coalesced_frames = priv->params.tx_cq_moderation.pkts;
cb3c7fd4 632 coal->use_adaptive_rx_coalesce = priv->params.rx_am_enabled;
f62b8bb8
AV		 633
634 return 0;
635}
636
637static int mlx5e_set_coalesce(struct net_device *netdev,
638 struct ethtool_coalesce *coal)
639{
640 struct mlx5e_priv *priv = netdev_priv(netdev);
641 struct mlx5_core_dev *mdev = priv->mdev;
642 struct mlx5e_channel *c;
cb3c7fd4
GR		 643 bool restart =
644 !!coal->use_adaptive_rx_coalesce != priv->params.rx_am_enabled;
645 bool was_opened;
646 int err = 0;
f62b8bb8
AV		 647 int tc;
648 int i;
649
7524a5d8
GP		 650 if (!MLX5_CAP_GEN(mdev, cq_moderation))
651 return -ENOTSUPP;
652
2fcb92fb 653 mutex_lock(&priv->state_lock);
9908aa29 654
cb3c7fd4
GR		 655 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
656 if (was_opened && restart) {
657 mlx5e_close_locked(netdev);
658 priv->params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce;
659 }
660
9908aa29
TT		 661 priv->params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
662 priv->params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
663 priv->params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
664 priv->params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
f62b8bb8 665
cb3c7fd4 666 if (!was_opened || restart)
2fcb92fb
GP		 667 goto out;
668
f62b8bb8
AV		 669 for (i = 0; i < priv->params.num_channels; ++i) {
670 c = priv->channel[i];
671
672 for (tc = 0; tc < c->num_tc; tc++) {
673 mlx5_core_modify_cq_moderation(mdev,
674 &c->sq[tc].cq.mcq,
675 coal->tx_coalesce_usecs,
676 coal->tx_max_coalesced_frames);
677 }
678
679 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
680 coal->rx_coalesce_usecs,
681 coal->rx_max_coalesced_frames);
682 }
683
2fcb92fb 684out:
cb3c7fd4
GR		 685 if (was_opened && restart)
686 err = mlx5e_open_locked(netdev);
687
2fcb92fb 688 mutex_unlock(&priv->state_lock);
cb3c7fd4 689 return err;
f62b8bb8
AV		 690}
691
665bc539
GP		 692static void ptys2ethtool_supported_link(unsigned long *supported_modes,
693 u32 eth_proto_cap)
f62b8bb8 694{
7abc2110 695 unsigned long proto_cap = eth_proto_cap;
665bc539 696 int proto;
f62b8bb8 697
7abc2110 698 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP		 699 bitmap_or(supported_modes, supported_modes,
700 ptys2ethtool_table[proto].supported,
701 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 702}
703
665bc539
GP		 704static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
705 u32 eth_proto_cap)
f62b8bb8 706{
7abc2110 707 unsigned long proto_cap = eth_proto_cap;
665bc539 708 int proto;
f62b8bb8 709
7abc2110 710 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP		 711 bitmap_or(advertising_modes, advertising_modes,
712 ptys2ethtool_table[proto].advertised,
713 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 714}
715
665bc539
GP		 716static void ptys2ethtool_supported_port(struct ethtool_link_ksettings *link_ksettings,
717 u32 eth_proto_cap)
f62b8bb8
AV		 718{
719 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
720 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
721 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
722 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
723 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
724 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
665bc539 725 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, FIBRE);
f62b8bb8
AV		 726 }
727
728 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
729 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
730 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
731 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
732 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
665bc539 733 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Backplane);
f62b8bb8 734 }
f62b8bb8
AV		 735}
736
b797a684
SM		 737int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
738{
739 u32 max_speed = 0;
740 u32 proto_cap;
741 int err;
742 int i;
743
744 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
745 if (err)
746 return err;
747
748 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
749 if (proto_cap & MLX5E_PROT_MASK(i))
750 max_speed = max(max_speed, ptys2ethtool_table[i].speed);
751
752 *speed = max_speed;
753 return 0;
754}
755
f62b8bb8
AV		 756static void get_speed_duplex(struct net_device *netdev,
757 u32 eth_proto_oper,
665bc539 758 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 759{
760 int i;
761 u32 speed = SPEED_UNKNOWN;
762 u8 duplex = DUPLEX_UNKNOWN;
763
764 if (!netif_carrier_ok(netdev))
765 goto out;
766
767 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
768 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
769 speed = ptys2ethtool_table[i].speed;
770 duplex = DUPLEX_FULL;
771 break;
772 }
773 }
774out:
665bc539
GP		 775 link_ksettings->base.speed = speed;
776 link_ksettings->base.duplex = duplex;
f62b8bb8
AV		 777}
778
665bc539
GP		 779static void get_supported(u32 eth_proto_cap,
780 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 781{
665bc539
GP		 782 unsigned long *supported = link_ksettings->link_modes.supported;
783
784 ptys2ethtool_supported_port(link_ksettings, eth_proto_cap);
785 ptys2ethtool_supported_link(supported, eth_proto_cap);
786 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
787 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Asym_Pause);
f62b8bb8
AV		 788}
789
790static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
665bc539
GP		 791 u8 rx_pause,
792 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 793{
665bc539
GP		 794 unsigned long *advertising = link_ksettings->link_modes.advertising;
795
796 ptys2ethtool_adver_link(advertising, eth_proto_cap);
797 if (tx_pause)
798 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
799 if (tx_pause ^ rx_pause)
800 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
f62b8bb8
AV		 801}
802
803static u8 get_connector_port(u32 eth_proto)
804{
805 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
806 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
807 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
808 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
809 return PORT_FIBRE;
810 }
811
812 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
813 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
814 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
815 return PORT_DA;
816 }
817
818 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
819 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
820 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
821 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
822 return PORT_NONE;
823 }
824
825 return PORT_OTHER;
826}
827
665bc539
GP		 828static void get_lp_advertising(u32 eth_proto_lp,
829 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 830{
665bc539
GP		 831 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
832
833 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
f62b8bb8
AV		 834}
835
665bc539
GP		 836static int mlx5e_get_link_ksettings(struct net_device *netdev,
837 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 838{
839 struct mlx5e_priv *priv = netdev_priv(netdev);
840 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 841 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
f62b8bb8
AV		 842 u32 eth_proto_cap;
843 u32 eth_proto_admin;
844 u32 eth_proto_lp;
845 u32 eth_proto_oper;
52244d96
GP		 846 u8 an_disable_admin;
847 u8 an_status;
f62b8bb8
AV		 848 int err;
849
a05bdefa 850 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
f62b8bb8
AV		 851 if (err) {
852 netdev_err(netdev, "%s: query port ptys failed: %d\n",
853 __func__, err);
854 goto err_query_ptys;
855 }
856
52244d96
GP		 857 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
858 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
859 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
860 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
861 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
862 an_status = MLX5_GET(ptys_reg, out, an_status);
f62b8bb8 863
665bc539
GP		 864 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
865 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
f62b8bb8 866
665bc539
GP		 867 get_supported(eth_proto_cap, link_ksettings);
868 get_advertising(eth_proto_admin, 0, 0, link_ksettings);
869 get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
f62b8bb8
AV		 870
871 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
872
665bc539
GP		 873 link_ksettings->base.port = get_connector_port(eth_proto_oper);
874 get_lp_advertising(eth_proto_lp, link_ksettings);
f62b8bb8 875
52244d96
GP		 876 if (an_status == MLX5_AN_COMPLETE)
877 ethtool_link_ksettings_add_link_mode(link_ksettings,
878 lp_advertising, Autoneg);
879
880 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
881 AUTONEG_ENABLE;
882 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
883 Autoneg);
884 if (!an_disable_admin)
885 ethtool_link_ksettings_add_link_mode(link_ksettings,
886 advertising, Autoneg);
887
f62b8bb8
AV		 888err_query_ptys:
889 return err;
890}
891
665bc539 892static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
f62b8bb8
AV		 893{
894 u32 i, ptys_modes = 0;
895
896 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
665bc539
GP		 897 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
898 link_modes,
899 __ETHTOOL_LINK_MODE_MASK_NBITS))
f62b8bb8
AV		 900 ptys_modes |= MLX5E_PROT_MASK(i);
901 }
902
903 return ptys_modes;
904}
905
906static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
907{
908 u32 i, speed_links = 0;
909
910 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
911 if (ptys2ethtool_table[i].speed == speed)
912 speed_links |= MLX5E_PROT_MASK(i);
913 }
914
915 return speed_links;
916}
917
665bc539
GP		 918static int mlx5e_set_link_ksettings(struct net_device *netdev,
919 const struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 920{
921 struct mlx5e_priv *priv = netdev_priv(netdev);
922 struct mlx5_core_dev *mdev = priv->mdev;
52244d96
GP		 923 u32 eth_proto_cap, eth_proto_admin;
924 bool an_changes = false;
925 u8 an_disable_admin;
926 u8 an_disable_cap;
927 bool an_disable;
f62b8bb8 928 u32 link_modes;
52244d96 929 u8 an_status;
f62b8bb8 930 u32 speed;
f62b8bb8
AV		 931 int err;
932
665bc539 933 speed = link_ksettings->base.speed;
f62b8bb8 934
665bc539
GP		 935 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
936 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
f62b8bb8
AV		 937 mlx5e_ethtool2ptys_speed_link(speed);
938
939 err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
940 if (err) {
941 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
942 __func__, err);
943 goto out;
944 }
945
946 link_modes = link_modes & eth_proto_cap;
947 if (!link_modes) {
948 netdev_err(netdev, "%s: Not supported link mode(s) requested",
949 __func__);
950 err = -EINVAL;
951 goto out;
952 }
953
954 err = mlx5_query_port_proto_admin(mdev, &eth_proto_admin, MLX5_PTYS_EN);
955 if (err) {
956 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
957 __func__, err);
958 goto out;
959 }
960
52244d96
GP		 961 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
962 &an_disable_cap, &an_disable_admin);
963
964 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
965 an_changes = ((!an_disable && an_disable_admin) ||
966 (an_disable && !an_disable_admin));
967
968 if (!an_changes && link_modes == eth_proto_admin)
f62b8bb8
AV		 969 goto out;
970
52244d96 971 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
667daeda 972 mlx5_toggle_port_link(mdev);
f62b8bb8 973
f62b8bb8
AV		 974out:
975 return err;
976}
977
2d75b2bc
AS		 978static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
979{
980 struct mlx5e_priv *priv = netdev_priv(netdev);
981
982 return sizeof(priv->params.toeplitz_hash_key);
983}
984
985static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
986{
987 return MLX5E_INDIR_RQT_SIZE;
988}
989
2be6967c
SM		 990static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
991 u8 *hfunc)
992{
993 struct mlx5e_priv *priv = netdev_priv(netdev);
994
2d75b2bc
AS		 995 if (indir)
996 memcpy(indir, priv->params.indirection_rqt,
997 sizeof(priv->params.indirection_rqt));
998
999 if (key)
1000 memcpy(key, priv->params.toeplitz_hash_key,
1001 sizeof(priv->params.toeplitz_hash_key));
1002
2be6967c
SM		 1003 if (hfunc)
1004 *hfunc = priv->params.rss_hfunc;
1005
1006 return 0;
1007}
1008
bdfc028d
TT		 1009static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
1010{
1011 struct mlx5_core_dev *mdev = priv->mdev;
1012 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1013 int i;
1014
1015 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
1016 mlx5e_build_tir_ctx_hash(tirc, priv);
1017
1da36696 1018 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 1019 mlx5_core_modify_tir(mdev, priv->indir_tir[i].tirn, in, inlen);
bdfc028d
TT		 1020}
1021
98e81b0a 1022static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
2be6967c
SM		 1023 const u8 *key, const u8 hfunc)
1024{
98e81b0a 1025 struct mlx5e_priv *priv = netdev_priv(dev);
bdfc028d
TT		 1026 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1027 void *in;
2be6967c 1028
2d75b2bc
AS		 1029 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1030 (hfunc != ETH_RSS_HASH_XOR) &&
2be6967c
SM		 1031 (hfunc != ETH_RSS_HASH_TOP))
1032 return -EINVAL;
1033
bdfc028d
TT		 1034 in = mlx5_vzalloc(inlen);
1035 if (!in)
1036 return -ENOMEM;
1037
2be6967c
SM		 1038 mutex_lock(&priv->state_lock);
1039
2d75b2bc 1040 if (indir) {
398f3351 1041 u32 rqtn = priv->indir_rqt.rqtn;
1da36696 1042
2d75b2bc
AS		 1043 memcpy(priv->params.indirection_rqt, indir,
1044 sizeof(priv->params.indirection_rqt));
1da36696 1045 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
2be6967c
SM		 1046 }
1047
2d75b2bc
AS		 1048 if (key)
1049 memcpy(priv->params.toeplitz_hash_key, key,
1050 sizeof(priv->params.toeplitz_hash_key));
1051
1052 if (hfunc != ETH_RSS_HASH_NO_CHANGE)
1053 priv->params.rss_hfunc = hfunc;
1054
bdfc028d 1055 mlx5e_modify_tirs_hash(priv, in, inlen);
2d75b2bc 1056
2be6967c
SM		 1057 mutex_unlock(&priv->state_lock);
1058
bdfc028d
TT		 1059 kvfree(in);
1060
1061 return 0;
2be6967c
SM		 1062}
1063
2d75b2bc
AS		 1064static int mlx5e_get_rxnfc(struct net_device *netdev,
1065 struct ethtool_rxnfc *info, u32 *rule_locs)
1066{
1067 struct mlx5e_priv *priv = netdev_priv(netdev);
1068 int err = 0;
1069
1070 switch (info->cmd) {
1071 case ETHTOOL_GRXRINGS:
1072 info->data = priv->params.num_channels;
1073 break;
f913a72a
MG		 1074 case ETHTOOL_GRXCLSRLCNT:
1075 info->rule_cnt = priv->fs.ethtool.tot_num_rules;
1076 break;
1077 case ETHTOOL_GRXCLSRULE:
1078 err = mlx5e_ethtool_get_flow(priv, info, info->fs.location);
1079 break;
1080 case ETHTOOL_GRXCLSRLALL:
1081 err = mlx5e_ethtool_get_all_flows(priv, info, rule_locs);
1082 break;
2d75b2bc
AS		 1083 default:
1084 err = -EOPNOTSUPP;
1085 break;
1086 }
1087
1088 return err;
1089}
1090
58d52291
AS		 1091static int mlx5e_get_tunable(struct net_device *dev,
1092 const struct ethtool_tunable *tuna,
1093 void *data)
1094{
1095 const struct mlx5e_priv *priv = netdev_priv(dev);
1096 int err = 0;
1097
1098 switch (tuna->id) {
1099 case ETHTOOL_TX_COPYBREAK:
1100 *(u32 *)data = priv->params.tx_max_inline;
1101 break;
1102 default:
1103 err = -EINVAL;
1104 break;
1105 }
1106
1107 return err;
1108}
1109
1110static int mlx5e_set_tunable(struct net_device *dev,
1111 const struct ethtool_tunable *tuna,
1112 const void *data)
1113{
1114 struct mlx5e_priv *priv = netdev_priv(dev);
1115 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 1116 bool was_opened;
58d52291
AS		 1117 u32 val;
1118 int err = 0;
1119
1120 switch (tuna->id) {
1121 case ETHTOOL_TX_COPYBREAK:
1122 val = *(u32 *)data;
1123 if (val > mlx5e_get_max_inline_cap(mdev)) {
1124 err = -EINVAL;
1125 break;
1126 }
1127
1128 mutex_lock(&priv->state_lock);
98e81b0a
AS		 1129
1130 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1131 if (was_opened)
1132 mlx5e_close_locked(dev);
1133
1134 priv->params.tx_max_inline = val;
1135
1136 if (was_opened)
1137 err = mlx5e_open_locked(dev);
1138
58d52291
AS		 1139 mutex_unlock(&priv->state_lock);
1140 break;
1141 default:
1142 err = -EINVAL;
1143 break;
1144 }
1145
1146 return err;
1147}
1148
3c2d18ef
AS		 1149static void mlx5e_get_pauseparam(struct net_device *netdev,
1150 struct ethtool_pauseparam *pauseparam)
1151{
1152 struct mlx5e_priv *priv = netdev_priv(netdev);
1153 struct mlx5_core_dev *mdev = priv->mdev;
1154 int err;
1155
1156 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1157 &pauseparam->tx_pause);
1158 if (err) {
1159 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1160 __func__, err);
1161 }
1162}
1163
1164static int mlx5e_set_pauseparam(struct net_device *netdev,
1165 struct ethtool_pauseparam *pauseparam)
1166{
1167 struct mlx5e_priv *priv = netdev_priv(netdev);
1168 struct mlx5_core_dev *mdev = priv->mdev;
1169 int err;
1170
1171 if (pauseparam->autoneg)
1172 return -EINVAL;
1173
1174 err = mlx5_set_port_pause(mdev,
1175 pauseparam->rx_pause ? 1 : 0,
1176 pauseparam->tx_pause ? 1 : 0);
1177 if (err) {
1178 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1179 __func__, err);
1180 }
1181
1182 return err;
1183}
1184
ef9814de
EBE		 1185static int mlx5e_get_ts_info(struct net_device *dev,
1186 struct ethtool_ts_info *info)
1187{
1188 struct mlx5e_priv *priv = netdev_priv(dev);
1189 int ret;
1190
1191 ret = ethtool_op_get_ts_info(dev, info);
1192 if (ret)
1193 return ret;
1194
3d8c38af
EBE		 1195 info->phc_index = priv->tstamp.ptp ?
1196 ptp_clock_index(priv->tstamp.ptp) : -1;
ef9814de
EBE		 1197
1198 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1199 return 0;
1200
1201 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1202 SOF_TIMESTAMPING_RX_HARDWARE |
1203 SOF_TIMESTAMPING_RAW_HARDWARE;
1204
1205 info->tx_types = (BIT(1) << HWTSTAMP_TX_OFF) |
1206 (BIT(1) << HWTSTAMP_TX_ON);
1207
1208 info->rx_filters = (BIT(1) << HWTSTAMP_FILTER_NONE) |
1209 (BIT(1) << HWTSTAMP_FILTER_ALL);
1210
1211 return 0;
1212}
1213
928cfe87
TT		 1214static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1215{
1216 __u32 ret = 0;
1217
1218 if (MLX5_CAP_GEN(mdev, wol_g))
1219 ret |= WAKE_MAGIC;
1220
1221 if (MLX5_CAP_GEN(mdev, wol_s))
1222 ret |= WAKE_MAGICSECURE;
1223
1224 if (MLX5_CAP_GEN(mdev, wol_a))
1225 ret |= WAKE_ARP;
1226
1227 if (MLX5_CAP_GEN(mdev, wol_b))
1228 ret |= WAKE_BCAST;
1229
1230 if (MLX5_CAP_GEN(mdev, wol_m))
1231 ret |= WAKE_MCAST;
1232
1233 if (MLX5_CAP_GEN(mdev, wol_u))
1234 ret |= WAKE_UCAST;
1235
1236 if (MLX5_CAP_GEN(mdev, wol_p))
1237 ret |= WAKE_PHY;
1238
1239 return ret;
1240}
1241
1242static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1243{
1244 __u32 ret = 0;
1245
1246 if (mode & MLX5_WOL_MAGIC)
1247 ret |= WAKE_MAGIC;
1248
1249 if (mode & MLX5_WOL_SECURED_MAGIC)
1250 ret |= WAKE_MAGICSECURE;
1251
1252 if (mode & MLX5_WOL_ARP)
1253 ret |= WAKE_ARP;
1254
1255 if (mode & MLX5_WOL_BROADCAST)
1256 ret |= WAKE_BCAST;
1257
1258 if (mode & MLX5_WOL_MULTICAST)
1259 ret |= WAKE_MCAST;
1260
1261 if (mode & MLX5_WOL_UNICAST)
1262 ret |= WAKE_UCAST;
1263
1264 if (mode & MLX5_WOL_PHY_ACTIVITY)
1265 ret |= WAKE_PHY;
1266
1267 return ret;
1268}
1269
1270static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1271{
1272 u8 ret = 0;
1273
1274 if (mode & WAKE_MAGIC)
1275 ret |= MLX5_WOL_MAGIC;
1276
1277 if (mode & WAKE_MAGICSECURE)
1278 ret |= MLX5_WOL_SECURED_MAGIC;
1279
1280 if (mode & WAKE_ARP)
1281 ret |= MLX5_WOL_ARP;
1282
1283 if (mode & WAKE_BCAST)
1284 ret |= MLX5_WOL_BROADCAST;
1285
1286 if (mode & WAKE_MCAST)
1287 ret |= MLX5_WOL_MULTICAST;
1288
1289 if (mode & WAKE_UCAST)
1290 ret |= MLX5_WOL_UNICAST;
1291
1292 if (mode & WAKE_PHY)
1293 ret |= MLX5_WOL_PHY_ACTIVITY;
1294
1295 return ret;
1296}
1297
1298static void mlx5e_get_wol(struct net_device *netdev,
1299 struct ethtool_wolinfo *wol)
1300{
1301 struct mlx5e_priv *priv = netdev_priv(netdev);
1302 struct mlx5_core_dev *mdev = priv->mdev;
1303 u8 mlx5_wol_mode;
1304 int err;
1305
1306 memset(wol, 0, sizeof(*wol));
1307
1308 wol->supported = mlx5e_get_wol_supported(mdev);
1309 if (!wol->supported)
1310 return;
1311
1312 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1313 if (err)
1314 return;
1315
1316 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1317}
1318
1319static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1320{
1321 struct mlx5e_priv *priv = netdev_priv(netdev);
1322 struct mlx5_core_dev *mdev = priv->mdev;
1323 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1324 u32 mlx5_wol_mode;
1325
1326 if (!wol_supported)
1327 return -ENOTSUPP;
1328
1329 if (wol->wolopts & ~wol_supported)
1330 return -EINVAL;
1331
1332 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1333
1334 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1335}
1336
da54d24e
GP		 1337static int mlx5e_set_phys_id(struct net_device *dev,
1338 enum ethtool_phys_id_state state)
1339{
1340 struct mlx5e_priv *priv = netdev_priv(dev);
1341 struct mlx5_core_dev *mdev = priv->mdev;
1342 u16 beacon_duration;
1343
1344 if (!MLX5_CAP_GEN(mdev, beacon_led))
1345 return -EOPNOTSUPP;
1346
1347 switch (state) {
1348 case ETHTOOL_ID_ACTIVE:
1349 beacon_duration = MLX5_BEACON_DURATION_INF;
1350 break;
1351 case ETHTOOL_ID_INACTIVE:
1352 beacon_duration = MLX5_BEACON_DURATION_OFF;
1353 break;
1354 default:
1355 return -EOPNOTSUPP;
1356 }
1357
1358 return mlx5_set_port_beacon(mdev, beacon_duration);
1359}
1360
bb64143e
GP		 1361static int mlx5e_get_module_info(struct net_device *netdev,
1362 struct ethtool_modinfo *modinfo)
1363{
1364 struct mlx5e_priv *priv = netdev_priv(netdev);
1365 struct mlx5_core_dev *dev = priv->mdev;
1366 int size_read = 0;
1367 u8 data[4];
1368
1369 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1370 if (size_read < 2)
1371 return -EIO;
1372
1373 /* data[0] = identifier byte */
1374 switch (data[0]) {
1375 case MLX5_MODULE_ID_QSFP:
1376 modinfo->type = ETH_MODULE_SFF_8436;
1377 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1378 break;
1379 case MLX5_MODULE_ID_QSFP_PLUS:
1380 case MLX5_MODULE_ID_QSFP28:
1381 /* data[1] = revision id */
1382 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1383 modinfo->type = ETH_MODULE_SFF_8636;
1384 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1385 } else {
1386 modinfo->type = ETH_MODULE_SFF_8436;
1387 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1388 }
1389 break;
1390 case MLX5_MODULE_ID_SFP:
1391 modinfo->type = ETH_MODULE_SFF_8472;
1392 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1393 break;
1394 default:
1395 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1396 __func__, data[0]);
1397 return -EINVAL;
1398 }
1399
1400 return 0;
1401}
1402
1403static int mlx5e_get_module_eeprom(struct net_device *netdev,
1404 struct ethtool_eeprom *ee,
1405 u8 *data)
1406{
1407 struct mlx5e_priv *priv = netdev_priv(netdev);
1408 struct mlx5_core_dev *mdev = priv->mdev;
1409 int offset = ee->offset;
1410 int size_read;
1411 int i = 0;
1412
1413 if (!ee->len)
1414 return -EINVAL;
1415
1416 memset(data, 0, ee->len);
1417
1418 while (i < ee->len) {
1419 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1420 data + i);
1421
1422 if (!size_read)
1423 /* Done reading */
1424 return 0;
1425
1426 if (size_read < 0) {
1427 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1428 __func__, size_read);
1429 return 0;
1430 }
1431
1432 i += size_read;
1433 offset += size_read;
1434 }
1435
1436 return 0;
1437}
1438
4e59e288
GP		 1439typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1440
9908aa29 1441static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
4e59e288 1442{
9908aa29
TT		 1443 struct mlx5e_priv *priv = netdev_priv(netdev);
1444 struct mlx5_core_dev *mdev = priv->mdev;
1445 bool rx_mode_changed;
1446 u8 rx_cq_period_mode;
1447 int err = 0;
1448 bool reset;
1449
1450 rx_cq_period_mode = enable ?
1451 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1452 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1453 rx_mode_changed = rx_cq_period_mode != priv->params.rx_cq_period_mode;
1454
1455 if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1456 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1457 return -ENOTSUPP;
1458
1459 if (!rx_mode_changed)
1460 return 0;
1461
1462 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
1463 if (reset)
1464 mlx5e_close_locked(netdev);
1465
1466 mlx5e_set_rx_cq_mode_params(&priv->params, rx_cq_period_mode);
1467
1468 if (reset)
1469 err = mlx5e_open_locked(netdev);
1470
1471 return err;
4e59e288
GP		 1472}
1473
9bcc8606
SD		 1474static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1475 bool enable)
1476{
1477 struct mlx5e_priv *priv = netdev_priv(netdev);
1478 struct mlx5_core_dev *mdev = priv->mdev;
1479 int err = 0;
1480 bool reset;
1481
1482 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1483 return -ENOTSUPP;
1484
1485 if (enable && priv->tstamp.hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
1486 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1487 return -EINVAL;
1488 }
1489
1490 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
1491
1492 if (reset)
1493 mlx5e_close_locked(netdev);
1494
1495 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, enable);
1496 priv->params.rx_cqe_compress_def = enable;
1497
1498 if (reset)
1499 err = mlx5e_open_locked(netdev);
1500 return err;
1501}
1502
4e59e288
GP		 1503static int mlx5e_handle_pflag(struct net_device *netdev,
1504 u32 wanted_flags,
1505 enum mlx5e_priv_flag flag,
1506 mlx5e_pflag_handler pflag_handler)
1507{
1508 struct mlx5e_priv *priv = netdev_priv(netdev);
1509 bool enable = !!(wanted_flags & flag);
59ece1c9 1510 u32 changes = wanted_flags ^ priv->params.pflags;
4e59e288
GP		 1511 int err;
1512
1513 if (!(changes & flag))
1514 return 0;
1515
1516 err = pflag_handler(netdev, enable);
1517 if (err) {
1518 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1519 enable ? "Enable" : "Disable", flag, err);
1520 return err;
1521 }
1522
59ece1c9 1523 MLX5E_SET_PFLAG(priv, flag, enable);
4e59e288
GP		 1524 return 0;
1525}
1526
1527static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1528{
1529 struct mlx5e_priv *priv = netdev_priv(netdev);
1530 int err;
1531
1532 mutex_lock(&priv->state_lock);
9908aa29
TT		 1533 err = mlx5e_handle_pflag(netdev, pflags,
1534 MLX5E_PFLAG_RX_CQE_BASED_MODER,
1535 set_pflag_rx_cqe_based_moder);
9bcc8606
SD		 1536 if (err)
1537 goto out;
4e59e288 1538
9bcc8606
SD		 1539 err = mlx5e_handle_pflag(netdev, pflags,
1540 MLX5E_PFLAG_RX_CQE_COMPRESS,
1541 set_pflag_rx_cqe_compress);
1542
1543out:
4e59e288 1544 mutex_unlock(&priv->state_lock);
9bcc8606 1545 return err;
4e59e288
GP		 1546}
1547
1548static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1549{
1550 struct mlx5e_priv *priv = netdev_priv(netdev);
1551
59ece1c9 1552 return priv->params.pflags;
4e59e288
GP		 1553}
1554
6dc6071c
MG		 1555static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1556{
1557 int err = 0;
1558 struct mlx5e_priv *priv = netdev_priv(dev);
1559
1560 switch (cmd->cmd) {
1561 case ETHTOOL_SRXCLSRLINS:
1562 err = mlx5e_ethtool_flow_replace(priv, &cmd->fs);
1563 break;
1564 case ETHTOOL_SRXCLSRLDEL:
1565 err = mlx5e_ethtool_flow_remove(priv, cmd->fs.location);
1566 break;
1567 default:
1568 err = -EOPNOTSUPP;
1569 break;
1570 }
1571
1572 return err;
1573}
1574
f62b8bb8
AV		 1575const struct ethtool_ops mlx5e_ethtool_ops = {
1576 .get_drvinfo = mlx5e_get_drvinfo,
1577 .get_link = ethtool_op_get_link,
1578 .get_strings = mlx5e_get_strings,
1579 .get_sset_count = mlx5e_get_sset_count,
1580 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1581 .get_ringparam = mlx5e_get_ringparam,
1582 .set_ringparam = mlx5e_set_ringparam,
1583 .get_channels = mlx5e_get_channels,
1584 .set_channels = mlx5e_set_channels,
1585 .get_coalesce = mlx5e_get_coalesce,
1586 .set_coalesce = mlx5e_set_coalesce,
665bc539
GP		 1587 .get_link_ksettings = mlx5e_get_link_ksettings,
1588 .set_link_ksettings = mlx5e_set_link_ksettings,
2d75b2bc
AS		 1589 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1590 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2be6967c
SM		 1591 .get_rxfh = mlx5e_get_rxfh,
1592 .set_rxfh = mlx5e_set_rxfh,
2d75b2bc 1593 .get_rxnfc = mlx5e_get_rxnfc,
6dc6071c 1594 .set_rxnfc = mlx5e_set_rxnfc,
58d52291
AS		 1595 .get_tunable = mlx5e_get_tunable,
1596 .set_tunable = mlx5e_set_tunable,
3c2d18ef
AS		 1597 .get_pauseparam = mlx5e_get_pauseparam,
1598 .set_pauseparam = mlx5e_set_pauseparam,
ef9814de 1599 .get_ts_info = mlx5e_get_ts_info,
da54d24e 1600 .set_phys_id = mlx5e_set_phys_id,
928cfe87
TT		 1601 .get_wol = mlx5e_get_wol,
1602 .set_wol = mlx5e_set_wol,
bb64143e
GP		 1603 .get_module_info = mlx5e_get_module_info,
1604 .get_module_eeprom = mlx5e_get_module_eeprom,
4e59e288 1605 .get_priv_flags = mlx5e_get_priv_flags,
d605d668
KH		 1606 .set_priv_flags = mlx5e_set_priv_flags,
1607 .self_test = mlx5e_self_test,
f62b8bb8 1608};
A mirror of Linus' kernel repository