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net/mlx5e: Refactor TIR configuration function
[thirdparty/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "en.h"
2c81bfd5 34#include "en/port.h"
6dbc80ca 35#include "lib/clock.h"
f62b8bb8 36
076b0936
ES		 37void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
38 struct ethtool_drvinfo *drvinfo)
f62b8bb8 39{
f62b8bb8
AV		 40 struct mlx5_core_dev *mdev = priv->mdev;
41
42 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
7913d205 43 strlcpy(drvinfo->version, DRIVER_VERSION,
f62b8bb8
AV		 44 sizeof(drvinfo->version));
45 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
84e11edb
IK		 46 "%d.%d.%04d (%.16s)",
47 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
48 mdev->board_id);
f62b8bb8
AV		 49 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
50 sizeof(drvinfo->bus_info));
51}
52
076b0936
ES		 53static void mlx5e_get_drvinfo(struct net_device *dev,
54 struct ethtool_drvinfo *drvinfo)
55{
56 struct mlx5e_priv *priv = netdev_priv(dev);
57
58 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
59}
60
665bc539
GP		 61struct ptys2ethtool_config {
62 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
63 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
f62b8bb8
AV		 64};
65
665bc539
GP		 66static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
67
2c81bfd5 68#define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, ...) \
665bc539
GP		 69 ({ \
70 struct ptys2ethtool_config *cfg; \
71 const unsigned int modes[] = { __VA_ARGS__ }; \
72 unsigned int i; \
73 cfg = &ptys2ethtool_table[reg_]; \
665bc539
GP		 74 bitmap_zero(cfg->supported, \
75 __ETHTOOL_LINK_MODE_MASK_NBITS); \
76 bitmap_zero(cfg->advertised, \
77 __ETHTOOL_LINK_MODE_MASK_NBITS); \
78 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
79 __set_bit(modes[i], cfg->supported); \
80 __set_bit(modes[i], cfg->advertised); \
81 } \
82 })
83
84void mlx5e_build_ptys2ethtool_map(void)
85{
2c81bfd5 86 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII,
665bc539 87 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
2c81bfd5 88 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX,
665bc539 89 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
2c81bfd5 90 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4,
665bc539 91 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
2c81bfd5 92 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4,
665bc539 93 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
2c81bfd5 94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR,
665bc539 95 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
2c81bfd5 96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2,
665bc539 97 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
2c81bfd5 98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4,
665bc539 99 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
2c81bfd5 100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4,
665bc539 101 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
2c81bfd5 102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4,
665bc539 103 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
2c81bfd5 104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR,
665bc539 105 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
2c81bfd5 106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR,
665bc539 107 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
2c81bfd5 108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER,
665bc539 109 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
2c81bfd5 110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4,
665bc539 111 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
2c81bfd5 112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4,
665bc539 113 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
2c81bfd5 114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2,
665bc539 115 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
2c81bfd5 116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4,
665bc539 117 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
2c81bfd5 118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4,
665bc539 119 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
2c81bfd5 120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4,
665bc539 121 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
2c81bfd5 122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4,
665bc539 123 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
2c81bfd5 124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T,
665bc539 125 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
2c81bfd5 126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR,
665bc539 127 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
2c81bfd5 128 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR,
665bc539 129 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
2c81bfd5 130 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR,
665bc539 131 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
2c81bfd5 132 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2,
665bc539 133 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
2c81bfd5 134 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2,
665bc539
GP		 135 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
136}
137
d2408205
KH		 138static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
139 "rx_cqe_moder",
140 "tx_cqe_moder",
141 "rx_cqe_compress",
142 "rx_striding_rq",
b856df28 143 "rx_no_csum_complete",
d2408205
KH		 144};
145
076b0936 146int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
f62b8bb8 147{
c0752f2b
KH		 148 int i, num_stats = 0;
149
f62b8bb8
AV		 150 switch (sset) {
151 case ETH_SS_STATS:
c0752f2b
KH		 152 for (i = 0; i < mlx5e_num_stats_grps; i++)
153 num_stats += mlx5e_stats_grps[i].get_num_stats(priv);
1fe85006 154 return num_stats;
4e59e288
GP		 155 case ETH_SS_PRIV_FLAGS:
156 return ARRAY_SIZE(mlx5e_priv_flags);
d605d668
KH		 157 case ETH_SS_TEST:
158 return mlx5e_self_test_num(priv);
f62b8bb8
AV		 159 /* fallthrough */
160 default:
161 return -EOPNOTSUPP;
162 }
163}
164
076b0936
ES		 165static int mlx5e_get_sset_count(struct net_device *dev, int sset)
166{
167 struct mlx5e_priv *priv = netdev_priv(dev);
168
169 return mlx5e_ethtool_get_sset_count(priv, sset);
170}
171
c045deef 172static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, u8 *data)
9218b44d 173{
1fe85006 174 int i, idx = 0;
9218b44d 175
c0752f2b
KH		 176 for (i = 0; i < mlx5e_num_stats_grps; i++)
177 idx = mlx5e_stats_grps[i].fill_strings(priv, data, idx);
9218b44d
GP		 178}
179
c045deef 180void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
f62b8bb8 181{
4e59e288 182 int i;
f62b8bb8
AV		 183
184 switch (stringset) {
185 case ETH_SS_PRIV_FLAGS:
4e59e288
GP		 186 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
187 strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
f62b8bb8
AV		 188 break;
189
190 case ETH_SS_TEST:
d605d668
KH		 191 for (i = 0; i < mlx5e_self_test_num(priv); i++)
192 strcpy(data + i * ETH_GSTRING_LEN,
193 mlx5e_self_tests[i]);
f62b8bb8
AV		 194 break;
195
196 case ETH_SS_STATS:
9218b44d 197 mlx5e_fill_stats_strings(priv, data);
f62b8bb8
AV		 198 break;
199 }
200}
201
c045deef 202static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
f62b8bb8
AV		 203{
204 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 205
206 mlx5e_ethtool_get_strings(priv, stringset, data);
207}
208
209void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
210 struct ethtool_stats *stats, u64 *data)
211{
1fe85006 212 int i, idx = 0;
f62b8bb8 213
f62b8bb8 214 mutex_lock(&priv->state_lock);
19386177 215 mlx5e_update_stats(priv);
f62b8bb8
AV		 216 mutex_unlock(&priv->state_lock);
217
c0752f2b
KH		 218 for (i = 0; i < mlx5e_num_stats_grps; i++)
219 idx = mlx5e_stats_grps[i].fill_stats(priv, data, idx);
f62b8bb8
AV		 220}
221
076b0936
ES		 222static void mlx5e_get_ethtool_stats(struct net_device *dev,
223 struct ethtool_stats *stats,
224 u64 *data)
225{
226 struct mlx5e_priv *priv = netdev_priv(dev);
227
228 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
229}
230
076b0936
ES		 231void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
232 struct ethtool_ringparam *param)
f62b8bb8 233{
73281b78 234 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
f62b8bb8 235 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
73281b78 236 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
6a9764ef 237 param->tx_pending = 1 << priv->channels.params.log_sq_size;
f62b8bb8
AV		 238}
239
076b0936
ES		 240static void mlx5e_get_ringparam(struct net_device *dev,
241 struct ethtool_ringparam *param)
f62b8bb8
AV		 242{
243 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 244
245 mlx5e_ethtool_get_ringparam(priv, param);
246}
247
248int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
249 struct ethtool_ringparam *param)
250{
546f18ed 251 struct mlx5e_channels new_channels = {};
f62b8bb8
AV		 252 u8 log_rq_size;
253 u8 log_sq_size;
254 int err = 0;
255
256 if (param->rx_jumbo_pending) {
076b0936 257 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
f62b8bb8
AV		 258 __func__);
259 return -EINVAL;
260 }
261 if (param->rx_mini_pending) {
076b0936 262 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
f62b8bb8
AV		 263 __func__);
264 return -EINVAL;
265 }
cc8e9ebf 266
73281b78 267 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
076b0936 268 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
f62b8bb8 269 __func__, param->rx_pending,
73281b78 270 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
fe4c988b
SM		 271 return -EINVAL;
272 }
273
f62b8bb8 274 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
076b0936 275 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
f62b8bb8
AV		 276 __func__, param->tx_pending,
277 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
278 return -EINVAL;
279 }
f62b8bb8 280
73281b78 281 log_rq_size = order_base_2(param->rx_pending);
f62b8bb8 282 log_sq_size = order_base_2(param->tx_pending);
f62b8bb8 283
73281b78 284 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
6a9764ef 285 log_sq_size == priv->channels.params.log_sq_size)
f62b8bb8
AV		 286 return 0;
287
288 mutex_lock(&priv->state_lock);
98e81b0a 289
546f18ed 290 new_channels.params = priv->channels.params;
73281b78 291 new_channels.params.log_rq_mtu_frames = log_rq_size;
546f18ed 292 new_channels.params.log_sq_size = log_sq_size;
98e81b0a 293
546f18ed
SM		 294 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
295 priv->channels.params = new_channels.params;
296 goto unlock;
297 }
98e81b0a 298
546f18ed
SM		 299 err = mlx5e_open_channels(priv, &new_channels);
300 if (err)
301 goto unlock;
302
2e20a151 303 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
98e81b0a 304
546f18ed 305unlock:
f62b8bb8
AV		 306 mutex_unlock(&priv->state_lock);
307
308 return err;
309}
310
076b0936
ES		 311static int mlx5e_set_ringparam(struct net_device *dev,
312 struct ethtool_ringparam *param)
f62b8bb8
AV		 313{
314 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 315
076b0936
ES		 316 return mlx5e_ethtool_set_ringparam(priv, param);
317}
318
319void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
320 struct ethtool_channels *ch)
321{
779d986d 322 ch->max_combined = mlx5e_get_netdev_max_channels(priv->netdev);
6a9764ef 323 ch->combined_count = priv->channels.params.num_channels;
f62b8bb8
AV		 324}
325
076b0936
ES		 326static void mlx5e_get_channels(struct net_device *dev,
327 struct ethtool_channels *ch)
f62b8bb8
AV		 328{
329 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 330
331 mlx5e_ethtool_get_channels(priv, ch);
332}
333
334int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
335 struct ethtool_channels *ch)
336{
f62b8bb8 337 unsigned int count = ch->combined_count;
55c2503d 338 struct mlx5e_channels new_channels = {};
45bf454a 339 bool arfs_enabled;
f62b8bb8
AV		 340 int err = 0;
341
342 if (!count) {
076b0936 343 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
f62b8bb8
AV		 344 __func__);
345 return -EINVAL;
346 }
f62b8bb8 347
6a9764ef 348 if (priv->channels.params.num_channels == count)
f62b8bb8
AV		 349 return 0;
350
351 mutex_lock(&priv->state_lock);
98e81b0a 352
55c2503d
SM		 353 new_channels.params = priv->channels.params;
354 new_channels.params.num_channels = count;
5a8e1267 355 if (!netif_is_rxfh_configured(priv->netdev))
d4b6c488 356 mlx5e_build_default_indir_rqt(new_channels.params.indirection_rqt,
5a8e1267 357 MLX5E_INDIR_RQT_SIZE, count);
55c2503d
SM		 358
359 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
360 priv->channels.params = new_channels.params;
361 goto out;
362 }
363
364 /* Create fresh channels with new parameters */
365 err = mlx5e_open_channels(priv, &new_channels);
366 if (err)
367 goto out;
98e81b0a 368
076b0936 369 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
45bf454a
MG		 370 if (arfs_enabled)
371 mlx5e_arfs_disable(priv);
372
55c2503d 373 /* Switch to new channels, set new parameters and close old ones */
2e20a151 374 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
45bf454a
MG		 375
376 if (arfs_enabled) {
377 err = mlx5e_arfs_enable(priv);
378 if (err)
076b0936 379 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
45bf454a
MG		 380 __func__, err);
381 }
98e81b0a 382
45bf454a 383out:
f62b8bb8
AV		 384 mutex_unlock(&priv->state_lock);
385
386 return err;
387}
388
076b0936
ES		 389static int mlx5e_set_channels(struct net_device *dev,
390 struct ethtool_channels *ch)
f62b8bb8 391{
076b0936
ES		 392 struct mlx5e_priv *priv = netdev_priv(dev);
393
394 return mlx5e_ethtool_set_channels(priv, ch);
395}
f62b8bb8 396
076b0936
ES		 397int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
398 struct ethtool_coalesce *coal)
399{
cbce4f44
TG		 400 struct net_dim_cq_moder *rx_moder, *tx_moder;
401
7524a5d8 402 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
9eb78923 403 return -EOPNOTSUPP;
7524a5d8 404
cbce4f44
TG		 405 rx_moder = &priv->channels.params.rx_cq_moderation;
406 coal->rx_coalesce_usecs = rx_moder->usec;
407 coal->rx_max_coalesced_frames = rx_moder->pkts;
408 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
409
410 tx_moder = &priv->channels.params.tx_cq_moderation;
411 coal->tx_coalesce_usecs = tx_moder->usec;
412 coal->tx_max_coalesced_frames = tx_moder->pkts;
413 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
f62b8bb8
AV		 414
415 return 0;
416}
417
076b0936
ES		 418static int mlx5e_get_coalesce(struct net_device *netdev,
419 struct ethtool_coalesce *coal)
420{
421 struct mlx5e_priv *priv = netdev_priv(netdev);
422
423 return mlx5e_ethtool_get_coalesce(priv, coal);
424}
425
b392a207
MS		 426#define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
427#define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
428
546f18ed
SM		 429static void
430mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
f62b8bb8 431{
f62b8bb8 432 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 433 int tc;
434 int i;
435
ff9c852f
SM		 436 for (i = 0; i < priv->channels.num; ++i) {
437 struct mlx5e_channel *c = priv->channels.c[i];
f62b8bb8
AV		 438
439 for (tc = 0; tc < c->num_tc; tc++) {
440 mlx5_core_modify_cq_moderation(mdev,
441 &c->sq[tc].cq.mcq,
442 coal->tx_coalesce_usecs,
443 coal->tx_max_coalesced_frames);
444 }
445
446 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
447 coal->rx_coalesce_usecs,
448 coal->rx_max_coalesced_frames);
449 }
546f18ed 450}
f62b8bb8 451
076b0936
ES		 452int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
453 struct ethtool_coalesce *coal)
546f18ed 454{
cbce4f44 455 struct net_dim_cq_moder *rx_moder, *tx_moder;
546f18ed
SM		 456 struct mlx5_core_dev *mdev = priv->mdev;
457 struct mlx5e_channels new_channels = {};
458 int err = 0;
459 bool reset;
cb3c7fd4 460
546f18ed
SM		 461 if (!MLX5_CAP_GEN(mdev, cq_moderation))
462 return -EOPNOTSUPP;
463
b392a207
MS		 464 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
465 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
466 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
467 __func__, MLX5E_MAX_COAL_TIME);
468 return -ERANGE;
469 }
470
471 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
472 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
473 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
474 __func__, MLX5E_MAX_COAL_FRAMES);
475 return -ERANGE;
476 }
477
546f18ed
SM		 478 mutex_lock(&priv->state_lock);
479 new_channels.params = priv->channels.params;
480
cbce4f44
TG		 481 rx_moder = &new_channels.params.rx_cq_moderation;
482 rx_moder->usec = coal->rx_coalesce_usecs;
483 rx_moder->pkts = coal->rx_max_coalesced_frames;
484 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
485
486 tx_moder = &new_channels.params.tx_cq_moderation;
487 tx_moder->usec = coal->tx_coalesce_usecs;
488 tx_moder->pkts = coal->tx_max_coalesced_frames;
489 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
546f18ed
SM		 490
491 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
492 priv->channels.params = new_channels.params;
493 goto out;
494 }
495 /* we are opened */
496
cbce4f44
TG		 497 reset = (!!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled) ||
498 (!!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled);
499
546f18ed
SM		 500 if (!reset) {
501 mlx5e_set_priv_channels_coalesce(priv, coal);
502 priv->channels.params = new_channels.params;
503 goto out;
504 }
505
506 /* open fresh channels with new coal parameters */
507 err = mlx5e_open_channels(priv, &new_channels);
508 if (err)
509 goto out;
510
2e20a151 511 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
546f18ed
SM		 512
513out:
2fcb92fb 514 mutex_unlock(&priv->state_lock);
cb3c7fd4 515 return err;
f62b8bb8
AV		 516}
517
076b0936
ES		 518static int mlx5e_set_coalesce(struct net_device *netdev,
519 struct ethtool_coalesce *coal)
520{
521 struct mlx5e_priv *priv = netdev_priv(netdev);
522
523 return mlx5e_ethtool_set_coalesce(priv, coal);
524}
525
665bc539
GP		 526static void ptys2ethtool_supported_link(unsigned long *supported_modes,
527 u32 eth_proto_cap)
f62b8bb8 528{
7abc2110 529 unsigned long proto_cap = eth_proto_cap;
665bc539 530 int proto;
f62b8bb8 531
7abc2110 532 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP		 533 bitmap_or(supported_modes, supported_modes,
534 ptys2ethtool_table[proto].supported,
535 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 536}
537
665bc539
GP		 538static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
539 u32 eth_proto_cap)
f62b8bb8 540{
7abc2110 541 unsigned long proto_cap = eth_proto_cap;
665bc539 542 int proto;
f62b8bb8 543
7abc2110 544 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP		 545 bitmap_or(advertising_modes, advertising_modes,
546 ptys2ethtool_table[proto].advertised,
547 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 548}
549
6cfa9460
SA		 550static const u32 pplm_fec_2_ethtool[] = {
551 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
552 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
553 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
554};
555
556static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
557{
558 int mode = 0;
559
560 if (!fec_mode)
561 return ETHTOOL_FEC_AUTO;
562
563 mode = find_first_bit(&fec_mode, size);
564
565 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
566 return pplm_fec_2_ethtool[mode];
567
568 return 0;
569}
570
571/* we use ETHTOOL_FEC_* offset and apply it to ETHTOOL_LINK_MODE_FEC_*_BIT */
572static u32 ethtool_fec2ethtool_caps(u_long ethtool_fec_code)
573{
574 u32 offset;
575
576 offset = find_first_bit(&ethtool_fec_code, sizeof(u32));
577 offset -= ETHTOOL_FEC_OFF_BIT;
578 offset += ETHTOOL_LINK_MODE_FEC_NONE_BIT;
579
580 return offset;
581}
582
583static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
584 struct ethtool_link_ksettings *link_ksettings)
585{
586 u_long fec_caps = 0;
587 u32 active_fec = 0;
588 u32 offset;
589 u32 bitn;
590 int err;
591
592 err = mlx5e_get_fec_caps(dev, (u8 *)&fec_caps);
593 if (err)
594 return (err == -EOPNOTSUPP) ? 0 : err;
595
596 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
597 if (err)
598 return err;
599
600 for_each_set_bit(bitn, &fec_caps, ARRAY_SIZE(pplm_fec_2_ethtool)) {
601 u_long ethtool_bitmask = pplm_fec_2_ethtool[bitn];
602
603 offset = ethtool_fec2ethtool_caps(ethtool_bitmask);
604 __set_bit(offset, link_ksettings->link_modes.supported);
605 }
606
607 active_fec = pplm2ethtool_fec(active_fec, sizeof(u32) * BITS_PER_BYTE);
608 offset = ethtool_fec2ethtool_caps(active_fec);
609 __set_bit(offset, link_ksettings->link_modes.advertising);
610
611 return 0;
612}
613
46e9d0b6
EBE		 614static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
615 u32 eth_proto_cap,
616 u8 connector_type)
f62b8bb8 617{
46e9d0b6
EBE		 618 if (!connector_type || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
619 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
620 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
621 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
622 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
623 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
624 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
625 ethtool_link_ksettings_add_link_mode(link_ksettings,
626 supported,
627 FIBRE);
628 ethtool_link_ksettings_add_link_mode(link_ksettings,
629 advertising,
630 FIBRE);
631 }
632
633 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
634 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
635 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
636 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
637 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
638 ethtool_link_ksettings_add_link_mode(link_ksettings,
639 supported,
640 Backplane);
641 ethtool_link_ksettings_add_link_mode(link_ksettings,
642 advertising,
643 Backplane);
644 }
645 return;
f62b8bb8
AV		 646 }
647
46e9d0b6
EBE		 648 switch (connector_type) {
649 case MLX5E_PORT_TP:
650 ethtool_link_ksettings_add_link_mode(link_ksettings,
651 supported, TP);
652 ethtool_link_ksettings_add_link_mode(link_ksettings,
653 advertising, TP);
654 break;
655 case MLX5E_PORT_AUI:
656 ethtool_link_ksettings_add_link_mode(link_ksettings,
657 supported, AUI);
658 ethtool_link_ksettings_add_link_mode(link_ksettings,
659 advertising, AUI);
660 break;
661 case MLX5E_PORT_BNC:
662 ethtool_link_ksettings_add_link_mode(link_ksettings,
663 supported, BNC);
664 ethtool_link_ksettings_add_link_mode(link_ksettings,
665 advertising, BNC);
666 break;
667 case MLX5E_PORT_MII:
668 ethtool_link_ksettings_add_link_mode(link_ksettings,
669 supported, MII);
670 ethtool_link_ksettings_add_link_mode(link_ksettings,
671 advertising, MII);
672 break;
673 case MLX5E_PORT_FIBRE:
674 ethtool_link_ksettings_add_link_mode(link_ksettings,
675 supported, FIBRE);
676 ethtool_link_ksettings_add_link_mode(link_ksettings,
677 advertising, FIBRE);
678 break;
679 case MLX5E_PORT_DA:
680 ethtool_link_ksettings_add_link_mode(link_ksettings,
681 supported, Backplane);
682 ethtool_link_ksettings_add_link_mode(link_ksettings,
683 advertising, Backplane);
684 break;
685 case MLX5E_PORT_NONE:
686 case MLX5E_PORT_OTHER:
687 default:
688 break;
f62b8bb8 689 }
f62b8bb8
AV		 690}
691
692static void get_speed_duplex(struct net_device *netdev,
693 u32 eth_proto_oper,
665bc539 694 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 695{
f62b8bb8
AV		 696 u32 speed = SPEED_UNKNOWN;
697 u8 duplex = DUPLEX_UNKNOWN;
698
699 if (!netif_carrier_ok(netdev))
700 goto out;
701
2c81bfd5
HN		 702 speed = mlx5e_port_ptys2speed(eth_proto_oper);
703 if (!speed) {
704 speed = SPEED_UNKNOWN;
705 goto out;
f62b8bb8 706 }
2c81bfd5
HN		 707
708 duplex = DUPLEX_FULL;
709
f62b8bb8 710out:
665bc539
GP		 711 link_ksettings->base.speed = speed;
712 link_ksettings->base.duplex = duplex;
f62b8bb8
AV		 713}
714
665bc539
GP		 715static void get_supported(u32 eth_proto_cap,
716 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 717{
665bc539
GP		 718 unsigned long *supported = link_ksettings->link_modes.supported;
719
665bc539
GP		 720 ptys2ethtool_supported_link(supported, eth_proto_cap);
721 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
f62b8bb8
AV		 722}
723
724static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
665bc539
GP		 725 u8 rx_pause,
726 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 727{
665bc539
GP		 728 unsigned long *advertising = link_ksettings->link_modes.advertising;
729
730 ptys2ethtool_adver_link(advertising, eth_proto_cap);
e3c19503 731 if (rx_pause)
665bc539
GP		 732 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
733 if (tx_pause ^ rx_pause)
734 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
f62b8bb8
AV		 735}
736
5b4793f8
EBE		 737static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
738 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
739 [MLX5E_PORT_NONE] = PORT_NONE,
740 [MLX5E_PORT_TP] = PORT_TP,
741 [MLX5E_PORT_AUI] = PORT_AUI,
742 [MLX5E_PORT_BNC] = PORT_BNC,
743 [MLX5E_PORT_MII] = PORT_MII,
744 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
745 [MLX5E_PORT_DA] = PORT_DA,
746 [MLX5E_PORT_OTHER] = PORT_OTHER,
747 };
748
749static u8 get_connector_port(u32 eth_proto, u8 connector_type)
f62b8bb8 750{
5b4793f8
EBE		 751 if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
752 return ptys2connector_type[connector_type];
753
61bf2125
OG		 754 if (eth_proto &
755 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
756 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
757 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
758 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
759 return PORT_FIBRE;
f62b8bb8
AV		 760 }
761
61bf2125
OG		 762 if (eth_proto &
763 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
764 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
765 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
766 return PORT_DA;
f62b8bb8
AV		 767 }
768
61bf2125
OG		 769 if (eth_proto &
770 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
771 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
772 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
773 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
774 return PORT_NONE;
f62b8bb8
AV		 775 }
776
777 return PORT_OTHER;
778}
779
665bc539
GP		 780static void get_lp_advertising(u32 eth_proto_lp,
781 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 782{
665bc539
GP		 783 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
784
785 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
f62b8bb8
AV		 786}
787
665bc539
GP		 788static int mlx5e_get_link_ksettings(struct net_device *netdev,
789 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 790{
791 struct mlx5e_priv *priv = netdev_priv(netdev);
792 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 793 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
b383b544
GP		 794 u32 rx_pause = 0;
795 u32 tx_pause = 0;
f62b8bb8
AV		 796 u32 eth_proto_cap;
797 u32 eth_proto_admin;
798 u32 eth_proto_lp;
799 u32 eth_proto_oper;
52244d96
GP		 800 u8 an_disable_admin;
801 u8 an_status;
5b4793f8 802 u8 connector_type;
f62b8bb8
AV		 803 int err;
804
a05bdefa 805 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
f62b8bb8
AV		 806 if (err) {
807 netdev_err(netdev, "%s: query port ptys failed: %d\n",
808 __func__, err);
6cfa9460 809 goto err_query_regs;
f62b8bb8
AV		 810 }
811
52244d96
GP		 812 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
813 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
814 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
815 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
816 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
817 an_status = MLX5_GET(ptys_reg, out, an_status);
5b4793f8 818 connector_type = MLX5_GET(ptys_reg, out, connector_type);
f62b8bb8 819
b383b544
GP		 820 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
821
665bc539
GP		 822 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
823 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
f62b8bb8 824
665bc539 825 get_supported(eth_proto_cap, link_ksettings);
b383b544 826 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings);
665bc539 827 get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
f62b8bb8
AV		 828
829 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
830
5b4793f8
EBE		 831 link_ksettings->base.port = get_connector_port(eth_proto_oper,
832 connector_type);
46e9d0b6
EBE		 833 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
834 connector_type);
665bc539 835 get_lp_advertising(eth_proto_lp, link_ksettings);
f62b8bb8 836
52244d96
GP		 837 if (an_status == MLX5_AN_COMPLETE)
838 ethtool_link_ksettings_add_link_mode(link_ksettings,
839 lp_advertising, Autoneg);
840
841 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
842 AUTONEG_ENABLE;
843 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
844 Autoneg);
6cfa9460 845
9184e51b 846 if (get_fec_supported_advertised(mdev, link_ksettings))
6cfa9460
SA		 847 netdev_dbg(netdev, "%s: FEC caps query failed: %d\n",
848 __func__, err);
849
52244d96
GP		 850 if (!an_disable_admin)
851 ethtool_link_ksettings_add_link_mode(link_ksettings,
852 advertising, Autoneg);
853
6cfa9460 854err_query_regs:
f62b8bb8
AV		 855 return err;
856}
857
665bc539 858static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
f62b8bb8
AV		 859{
860 u32 i, ptys_modes = 0;
861
862 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
665bc539
GP		 863 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
864 link_modes,
865 __ETHTOOL_LINK_MODE_MASK_NBITS))
f62b8bb8
AV		 866 ptys_modes |= MLX5E_PROT_MASK(i);
867 }
868
869 return ptys_modes;
870}
871
665bc539
GP		 872static int mlx5e_set_link_ksettings(struct net_device *netdev,
873 const struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 874{
875 struct mlx5e_priv *priv = netdev_priv(netdev);
876 struct mlx5_core_dev *mdev = priv->mdev;
52244d96
GP		 877 u32 eth_proto_cap, eth_proto_admin;
878 bool an_changes = false;
879 u8 an_disable_admin;
880 u8 an_disable_cap;
881 bool an_disable;
f62b8bb8 882 u32 link_modes;
52244d96 883 u8 an_status;
f62b8bb8 884 u32 speed;
f62b8bb8
AV		 885 int err;
886
665bc539 887 speed = link_ksettings->base.speed;
f62b8bb8 888
665bc539
GP		 889 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
890 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
2c81bfd5 891 mlx5e_port_speed2linkmodes(speed);
f62b8bb8
AV		 892
893 err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
894 if (err) {
895 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
896 __func__, err);
897 goto out;
898 }
899
900 link_modes = link_modes & eth_proto_cap;
901 if (!link_modes) {
902 netdev_err(netdev, "%s: Not supported link mode(s) requested",
903 __func__);
904 err = -EINVAL;
905 goto out;
906 }
907
908 err = mlx5_query_port_proto_admin(mdev, &eth_proto_admin, MLX5_PTYS_EN);
909 if (err) {
910 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
911 __func__, err);
912 goto out;
913 }
914
52244d96
GP		 915 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
916 &an_disable_cap, &an_disable_admin);
917
918 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
919 an_changes = ((!an_disable && an_disable_admin) ||
920 (an_disable && !an_disable_admin));
921
922 if (!an_changes && link_modes == eth_proto_admin)
f62b8bb8
AV		 923 goto out;
924
52244d96 925 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
667daeda 926 mlx5_toggle_port_link(mdev);
f62b8bb8 927
f62b8bb8
AV		 928out:
929 return err;
930}
931
a5355de8
OG		 932u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
933{
934 return sizeof(priv->channels.params.toeplitz_hash_key);
935}
936
2d75b2bc
AS		 937static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
938{
939 struct mlx5e_priv *priv = netdev_priv(netdev);
940
a5355de8 941 return mlx5e_ethtool_get_rxfh_key_size(priv);
2d75b2bc
AS		 942}
943
a5355de8 944u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
2d75b2bc
AS		 945{
946 return MLX5E_INDIR_RQT_SIZE;
947}
948
a5355de8
OG		 949static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
950{
951 struct mlx5e_priv *priv = netdev_priv(netdev);
952
953 return mlx5e_ethtool_get_rxfh_indir_size(priv);
954}
955
2be6967c
SM		 956static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
957 u8 *hfunc)
958{
959 struct mlx5e_priv *priv = netdev_priv(netdev);
960
2d75b2bc 961 if (indir)
6a9764ef
SM		 962 memcpy(indir, priv->channels.params.indirection_rqt,
963 sizeof(priv->channels.params.indirection_rqt));
2d75b2bc
AS		 964
965 if (key)
6a9764ef
SM		 966 memcpy(key, priv->channels.params.toeplitz_hash_key,
967 sizeof(priv->channels.params.toeplitz_hash_key));
2d75b2bc 968
2be6967c 969 if (hfunc)
6a9764ef 970 *hfunc = priv->channels.params.rss_hfunc;
2be6967c
SM		 971
972 return 0;
973}
974
98e81b0a 975static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
2be6967c
SM		 976 const u8 *key, const u8 hfunc)
977{
98e81b0a 978 struct mlx5e_priv *priv = netdev_priv(dev);
bdfc028d 979 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1d3398fa 980 bool hash_changed = false;
bdfc028d 981 void *in;
2be6967c 982
2d75b2bc
AS		 983 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
984 (hfunc != ETH_RSS_HASH_XOR) &&
2be6967c
SM		 985 (hfunc != ETH_RSS_HASH_TOP))
986 return -EINVAL;
987
1b9a07ee 988 in = kvzalloc(inlen, GFP_KERNEL);
bdfc028d
TT		 989 if (!in)
990 return -ENOMEM;
991
2be6967c
SM		 992 mutex_lock(&priv->state_lock);
993
1d3398fa 994 if (hfunc != ETH_RSS_HASH_NO_CHANGE &&
6a9764ef
SM		 995 hfunc != priv->channels.params.rss_hfunc) {
996 priv->channels.params.rss_hfunc = hfunc;
1d3398fa
GP		 997 hash_changed = true;
998 }
999
a5f97fee 1000 if (indir) {
6a9764ef
SM		 1001 memcpy(priv->channels.params.indirection_rqt, indir,
1002 sizeof(priv->channels.params.indirection_rqt));
a5f97fee
SM		 1003
1004 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1005 u32 rqtn = priv->indir_rqt.rqtn;
1006 struct mlx5e_redirect_rqt_param rrp = {
1007 .is_rss = true,
e270e966
AM		 1008 {
1009 .rss = {
1010 .hfunc = priv->channels.params.rss_hfunc,
1011 .channels = &priv->channels,
1012 },
1013 },
a5f97fee
SM		 1014 };
1015
1016 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1017 }
1018 }
1019
1d3398fa 1020 if (key) {
6a9764ef
SM		 1021 memcpy(priv->channels.params.toeplitz_hash_key, key,
1022 sizeof(priv->channels.params.toeplitz_hash_key));
1d3398fa 1023 hash_changed = hash_changed ||
6a9764ef 1024 priv->channels.params.rss_hfunc == ETH_RSS_HASH_TOP;
1d3398fa 1025 }
2d75b2bc 1026
1d3398fa
GP		 1027 if (hash_changed)
1028 mlx5e_modify_tirs_hash(priv, in, inlen);
2d75b2bc 1029
2be6967c
SM		 1030 mutex_unlock(&priv->state_lock);
1031
bdfc028d
TT		 1032 kvfree(in);
1033
1034 return 0;
2be6967c
SM		 1035}
1036
2afa609f
IK		 1037#define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1038#define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1039#define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1040#define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1041#define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1042 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1043 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1044
1045static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1046 u16 *pfc_prevention_tout)
1047{
1048 struct mlx5e_priv *priv = netdev_priv(netdev);
1049 struct mlx5_core_dev *mdev = priv->mdev;
1050
1051 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1052 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1053 return -EOPNOTSUPP;
1054
1055 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1056}
1057
1058static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1059 u16 pfc_preven)
1060{
1061 struct mlx5e_priv *priv = netdev_priv(netdev);
1062 struct mlx5_core_dev *mdev = priv->mdev;
1063 u16 critical_tout;
1064 u16 minor;
1065
1066 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1067 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1068 return -EOPNOTSUPP;
1069
1070 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1071 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1072 pfc_preven;
1073
1074 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1075 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1076 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1077 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1078 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1079 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1080 return -EINVAL;
1081 }
1082
1083 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1084 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1085 minor);
1086}
1087
58d52291
AS		 1088static int mlx5e_get_tunable(struct net_device *dev,
1089 const struct ethtool_tunable *tuna,
1090 void *data)
1091{
c4554fbc 1092 int err;
58d52291
AS		 1093
1094 switch (tuna->id) {
2afa609f
IK		 1095 case ETHTOOL_PFC_PREVENTION_TOUT:
1096 err = mlx5e_get_pfc_prevention_tout(dev, data);
1097 break;
58d52291
AS		 1098 default:
1099 err = -EINVAL;
1100 break;
1101 }
1102
1103 return err;
1104}
1105
1106static int mlx5e_set_tunable(struct net_device *dev,
1107 const struct ethtool_tunable *tuna,
1108 const void *data)
1109{
1110 struct mlx5e_priv *priv = netdev_priv(dev);
c4554fbc 1111 int err;
546f18ed
SM		 1112
1113 mutex_lock(&priv->state_lock);
58d52291
AS		 1114
1115 switch (tuna->id) {
2afa609f
IK		 1116 case ETHTOOL_PFC_PREVENTION_TOUT:
1117 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
58d52291
AS		 1118 break;
1119 default:
1120 err = -EINVAL;
1121 break;
1122 }
1123
546f18ed 1124 mutex_unlock(&priv->state_lock);
58d52291
AS		 1125 return err;
1126}
1127
3c2d18ef
AS		 1128static void mlx5e_get_pauseparam(struct net_device *netdev,
1129 struct ethtool_pauseparam *pauseparam)
1130{
1131 struct mlx5e_priv *priv = netdev_priv(netdev);
1132 struct mlx5_core_dev *mdev = priv->mdev;
1133 int err;
1134
1135 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1136 &pauseparam->tx_pause);
1137 if (err) {
1138 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1139 __func__, err);
1140 }
1141}
1142
1143static int mlx5e_set_pauseparam(struct net_device *netdev,
1144 struct ethtool_pauseparam *pauseparam)
1145{
1146 struct mlx5e_priv *priv = netdev_priv(netdev);
1147 struct mlx5_core_dev *mdev = priv->mdev;
1148 int err;
1149
1150 if (pauseparam->autoneg)
1151 return -EINVAL;
1152
1153 err = mlx5_set_port_pause(mdev,
1154 pauseparam->rx_pause ? 1 : 0,
1155 pauseparam->tx_pause ? 1 : 0);
1156 if (err) {
1157 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1158 __func__, err);
1159 }
1160
1161 return err;
1162}
1163
3844b07e
FD		 1164int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1165 struct ethtool_ts_info *info)
ef9814de 1166{
7c39afb3 1167 struct mlx5_core_dev *mdev = priv->mdev;
ef9814de
EBE		 1168 int ret;
1169
3844b07e 1170 ret = ethtool_op_get_ts_info(priv->netdev, info);
ef9814de
EBE		 1171 if (ret)
1172 return ret;
1173
6dbc80ca 1174 info->phc_index = mlx5_clock_get_ptp_index(mdev);
ef9814de 1175
6dbc80ca
MS		 1176 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1177 info->phc_index == -1)
ef9814de
EBE		 1178 return 0;
1179
1180 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1181 SOF_TIMESTAMPING_RX_HARDWARE |
1182 SOF_TIMESTAMPING_RAW_HARDWARE;
1183
f0b38117
MD		 1184 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1185 BIT(HWTSTAMP_TX_ON);
ef9814de 1186
f0b38117
MD		 1187 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1188 BIT(HWTSTAMP_FILTER_ALL);
ef9814de
EBE		 1189
1190 return 0;
1191}
1192
3844b07e
FD		 1193static int mlx5e_get_ts_info(struct net_device *dev,
1194 struct ethtool_ts_info *info)
1195{
1196 struct mlx5e_priv *priv = netdev_priv(dev);
1197
1198 return mlx5e_ethtool_get_ts_info(priv, info);
1199}
1200
928cfe87
TT		 1201static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1202{
1203 __u32 ret = 0;
1204
1205 if (MLX5_CAP_GEN(mdev, wol_g))
1206 ret |= WAKE_MAGIC;
1207
1208 if (MLX5_CAP_GEN(mdev, wol_s))
1209 ret |= WAKE_MAGICSECURE;
1210
1211 if (MLX5_CAP_GEN(mdev, wol_a))
1212 ret |= WAKE_ARP;
1213
1214 if (MLX5_CAP_GEN(mdev, wol_b))
1215 ret |= WAKE_BCAST;
1216
1217 if (MLX5_CAP_GEN(mdev, wol_m))
1218 ret |= WAKE_MCAST;
1219
1220 if (MLX5_CAP_GEN(mdev, wol_u))
1221 ret |= WAKE_UCAST;
1222
1223 if (MLX5_CAP_GEN(mdev, wol_p))
1224 ret |= WAKE_PHY;
1225
1226 return ret;
1227}
1228
1229static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1230{
1231 __u32 ret = 0;
1232
1233 if (mode & MLX5_WOL_MAGIC)
1234 ret |= WAKE_MAGIC;
1235
1236 if (mode & MLX5_WOL_SECURED_MAGIC)
1237 ret |= WAKE_MAGICSECURE;
1238
1239 if (mode & MLX5_WOL_ARP)
1240 ret |= WAKE_ARP;
1241
1242 if (mode & MLX5_WOL_BROADCAST)
1243 ret |= WAKE_BCAST;
1244
1245 if (mode & MLX5_WOL_MULTICAST)
1246 ret |= WAKE_MCAST;
1247
1248 if (mode & MLX5_WOL_UNICAST)
1249 ret |= WAKE_UCAST;
1250
1251 if (mode & MLX5_WOL_PHY_ACTIVITY)
1252 ret |= WAKE_PHY;
1253
1254 return ret;
1255}
1256
1257static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1258{
1259 u8 ret = 0;
1260
1261 if (mode & WAKE_MAGIC)
1262 ret |= MLX5_WOL_MAGIC;
1263
1264 if (mode & WAKE_MAGICSECURE)
1265 ret |= MLX5_WOL_SECURED_MAGIC;
1266
1267 if (mode & WAKE_ARP)
1268 ret |= MLX5_WOL_ARP;
1269
1270 if (mode & WAKE_BCAST)
1271 ret |= MLX5_WOL_BROADCAST;
1272
1273 if (mode & WAKE_MCAST)
1274 ret |= MLX5_WOL_MULTICAST;
1275
1276 if (mode & WAKE_UCAST)
1277 ret |= MLX5_WOL_UNICAST;
1278
1279 if (mode & WAKE_PHY)
1280 ret |= MLX5_WOL_PHY_ACTIVITY;
1281
1282 return ret;
1283}
1284
1285static void mlx5e_get_wol(struct net_device *netdev,
1286 struct ethtool_wolinfo *wol)
1287{
1288 struct mlx5e_priv *priv = netdev_priv(netdev);
1289 struct mlx5_core_dev *mdev = priv->mdev;
1290 u8 mlx5_wol_mode;
1291 int err;
1292
1293 memset(wol, 0, sizeof(*wol));
1294
1295 wol->supported = mlx5e_get_wol_supported(mdev);
1296 if (!wol->supported)
1297 return;
1298
1299 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1300 if (err)
1301 return;
1302
1303 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1304}
1305
1306static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1307{
1308 struct mlx5e_priv *priv = netdev_priv(netdev);
1309 struct mlx5_core_dev *mdev = priv->mdev;
1310 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1311 u32 mlx5_wol_mode;
1312
1313 if (!wol_supported)
9eb78923 1314 return -EOPNOTSUPP;
928cfe87
TT		 1315
1316 if (wol->wolopts & ~wol_supported)
1317 return -EINVAL;
1318
1319 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1320
1321 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1322}
1323
6cfa9460
SA		 1324static int mlx5e_get_fecparam(struct net_device *netdev,
1325 struct ethtool_fecparam *fecparam)
1326{
1327 struct mlx5e_priv *priv = netdev_priv(netdev);
1328 struct mlx5_core_dev *mdev = priv->mdev;
1329 u8 fec_configured = 0;
1330 u32 fec_active = 0;
1331 int err;
1332
1333 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1334
1335 if (err)
1336 return err;
1337
1338 fecparam->active_fec = pplm2ethtool_fec((u_long)fec_active,
1339 sizeof(u32) * BITS_PER_BYTE);
1340
1341 if (!fecparam->active_fec)
1342 return -EOPNOTSUPP;
1343
1344 fecparam->fec = pplm2ethtool_fec((u_long)fec_configured,
1345 sizeof(u8) * BITS_PER_BYTE);
1346
1347 return 0;
1348}
1349
1350static int mlx5e_set_fecparam(struct net_device *netdev,
1351 struct ethtool_fecparam *fecparam)
1352{
1353 struct mlx5e_priv *priv = netdev_priv(netdev);
1354 struct mlx5_core_dev *mdev = priv->mdev;
1355 u8 fec_policy = 0;
1356 int mode;
1357 int err;
1358
1359 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1360 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1361 continue;
1362 fec_policy |= (1 << mode);
1363 break;
1364 }
1365
1366 err = mlx5e_set_fec_mode(mdev, fec_policy);
1367
1368 if (err)
1369 return err;
1370
1371 mlx5_toggle_port_link(mdev);
1372
1373 return 0;
1374}
1375
79c48764
GP		 1376static u32 mlx5e_get_msglevel(struct net_device *dev)
1377{
1378 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1379}
1380
1381static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1382{
1383 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1384}
1385
da54d24e
GP		 1386static int mlx5e_set_phys_id(struct net_device *dev,
1387 enum ethtool_phys_id_state state)
1388{
1389 struct mlx5e_priv *priv = netdev_priv(dev);
1390 struct mlx5_core_dev *mdev = priv->mdev;
1391 u16 beacon_duration;
1392
1393 if (!MLX5_CAP_GEN(mdev, beacon_led))
1394 return -EOPNOTSUPP;
1395
1396 switch (state) {
1397 case ETHTOOL_ID_ACTIVE:
1398 beacon_duration = MLX5_BEACON_DURATION_INF;
1399 break;
1400 case ETHTOOL_ID_INACTIVE:
1401 beacon_duration = MLX5_BEACON_DURATION_OFF;
1402 break;
1403 default:
1404 return -EOPNOTSUPP;
1405 }
1406
1407 return mlx5_set_port_beacon(mdev, beacon_duration);
1408}
1409
bb64143e
GP		 1410static int mlx5e_get_module_info(struct net_device *netdev,
1411 struct ethtool_modinfo *modinfo)
1412{
1413 struct mlx5e_priv *priv = netdev_priv(netdev);
1414 struct mlx5_core_dev *dev = priv->mdev;
1415 int size_read = 0;
1416 u8 data[4];
1417
1418 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1419 if (size_read < 2)
1420 return -EIO;
1421
1422 /* data[0] = identifier byte */
1423 switch (data[0]) {
1424 case MLX5_MODULE_ID_QSFP:
1425 modinfo->type = ETH_MODULE_SFF_8436;
1426 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1427 break;
1428 case MLX5_MODULE_ID_QSFP_PLUS:
1429 case MLX5_MODULE_ID_QSFP28:
1430 /* data[1] = revision id */
1431 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1432 modinfo->type = ETH_MODULE_SFF_8636;
1433 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1434 } else {
1435 modinfo->type = ETH_MODULE_SFF_8436;
1436 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1437 }
1438 break;
1439 case MLX5_MODULE_ID_SFP:
1440 modinfo->type = ETH_MODULE_SFF_8472;
1441 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1442 break;
1443 default:
1444 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1445 __func__, data[0]);
1446 return -EINVAL;
1447 }
1448
1449 return 0;
1450}
1451
1452static int mlx5e_get_module_eeprom(struct net_device *netdev,
1453 struct ethtool_eeprom *ee,
1454 u8 *data)
1455{
1456 struct mlx5e_priv *priv = netdev_priv(netdev);
1457 struct mlx5_core_dev *mdev = priv->mdev;
1458 int offset = ee->offset;
1459 int size_read;
1460 int i = 0;
1461
1462 if (!ee->len)
1463 return -EINVAL;
1464
1465 memset(data, 0, ee->len);
1466
1467 while (i < ee->len) {
1468 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1469 data + i);
1470
1471 if (!size_read)
1472 /* Done reading */
1473 return 0;
1474
1475 if (size_read < 0) {
1476 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1477 __func__, size_read);
1478 return 0;
1479 }
1480
1481 i += size_read;
1482 offset += size_read;
1483 }
1484
1485 return 0;
1486}
1487
4e59e288
GP		 1488typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1489
0088cbbc
TG		 1490static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1491 bool is_rx_cq)
4e59e288 1492{
9908aa29
TT		 1493 struct mlx5e_priv *priv = netdev_priv(netdev);
1494 struct mlx5_core_dev *mdev = priv->mdev;
be7e87f9 1495 struct mlx5e_channels new_channels = {};
0088cbbc
TG		 1496 bool mode_changed;
1497 u8 cq_period_mode, current_cq_period_mode;
9908aa29 1498 int err = 0;
9908aa29 1499
0088cbbc 1500 cq_period_mode = enable ?
9908aa29
TT		 1501 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1502 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
0088cbbc
TG		 1503 current_cq_period_mode = is_rx_cq ?
1504 priv->channels.params.rx_cq_moderation.cq_period_mode :
1505 priv->channels.params.tx_cq_moderation.cq_period_mode;
1506 mode_changed = cq_period_mode != current_cq_period_mode;
9908aa29 1507
0088cbbc 1508 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
9908aa29 1509 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
9eb78923 1510 return -EOPNOTSUPP;
9908aa29 1511
0088cbbc 1512 if (!mode_changed)
9908aa29
TT		 1513 return 0;
1514
be7e87f9 1515 new_channels.params = priv->channels.params;
0088cbbc
TG		 1516 if (is_rx_cq)
1517 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1518 else
1519 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
9908aa29 1520
be7e87f9
SM		 1521 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1522 priv->channels.params = new_channels.params;
1523 return 0;
1524 }
1525
1526 err = mlx5e_open_channels(priv, &new_channels);
1527 if (err)
1528 return err;
9908aa29 1529
2e20a151 1530 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
be7e87f9
SM		 1531 return 0;
1532}
9908aa29 1533
0088cbbc
TG		 1534static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1535{
1536 return set_pflag_cqe_based_moder(netdev, enable, false);
1537}
1538
1539static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1540{
1541 return set_pflag_cqe_based_moder(netdev, enable, true);
1542}
1543
be7e87f9
SM		 1544int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1545{
1546 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1547 struct mlx5e_channels new_channels = {};
1548 int err = 0;
1549
1550 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1551 return new_val ? -EOPNOTSUPP : 0;
1552
1553 if (curr_val == new_val)
1554 return 0;
1555
1556 new_channels.params = priv->channels.params;
1557 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1558
be7e87f9
SM		 1559 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1560 priv->channels.params = new_channels.params;
1561 return 0;
1562 }
1563
1564 err = mlx5e_open_channels(priv, &new_channels);
1565 if (err)
1566 return err;
1567
2e20a151 1568 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
696a97cf
EE		 1569 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1570 MLX5E_GET_PFLAG(&priv->channels.params,
1571 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1572
be7e87f9 1573 return 0;
4e59e288
GP		 1574}
1575
9bcc8606
SD		 1576static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1577 bool enable)
1578{
1579 struct mlx5e_priv *priv = netdev_priv(netdev);
1580 struct mlx5_core_dev *mdev = priv->mdev;
9bcc8606
SD		 1581
1582 if (!MLX5_CAP_GEN(mdev, cqe_compression))
9eb78923 1583 return -EOPNOTSUPP;
9bcc8606 1584
7c39afb3 1585 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
9bcc8606
SD		 1586 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1587 return -EINVAL;
1588 }
1589
5eb0249b 1590 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
6a9764ef 1591 priv->channels.params.rx_cqe_compress_def = enable;
9bcc8606 1592
5eb0249b 1593 return 0;
9bcc8606
SD		 1594}
1595
2ccb0a79
TT		 1596static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1597{
1598 struct mlx5e_priv *priv = netdev_priv(netdev);
1599 struct mlx5_core_dev *mdev = priv->mdev;
1600 struct mlx5e_channels new_channels = {};
1601 int err;
1602
1603 if (enable) {
1604 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1605 return -EOPNOTSUPP;
1606 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1607 return -EINVAL;
6c3a823e
TT		 1608 } else if (priv->channels.params.lro_en) {
1609 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n");
1610 return -EINVAL;
2ccb0a79
TT		 1611 }
1612
1613 new_channels.params = priv->channels.params;
1614
1615 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1616 mlx5e_set_rq_type(mdev, &new_channels.params);
1617
1618 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1619 priv->channels.params = new_channels.params;
1620 return 0;
1621 }
1622
1623 err = mlx5e_open_channels(priv, &new_channels);
1624 if (err)
1625 return err;
1626
1627 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1628 return 0;
1629}
1630
b856df28
OG		 1631static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
1632{
1633 struct mlx5e_priv *priv = netdev_priv(netdev);
1634 struct mlx5e_channels *channels = &priv->channels;
1635 struct mlx5e_channel *c;
1636 int i;
1637
1638 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1639 return 0;
1640
1641 for (i = 0; i < channels->num; i++) {
1642 c = channels->c[i];
1643 if (enable)
1644 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1645 else
1646 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1647 }
1648
1649 return 0;
1650}
1651
4e59e288
GP		 1652static int mlx5e_handle_pflag(struct net_device *netdev,
1653 u32 wanted_flags,
1654 enum mlx5e_priv_flag flag,
1655 mlx5e_pflag_handler pflag_handler)
1656{
1657 struct mlx5e_priv *priv = netdev_priv(netdev);
1658 bool enable = !!(wanted_flags & flag);
6a9764ef 1659 u32 changes = wanted_flags ^ priv->channels.params.pflags;
4e59e288
GP		 1660 int err;
1661
1662 if (!(changes & flag))
1663 return 0;
1664
1665 err = pflag_handler(netdev, enable);
1666 if (err) {
1667 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1668 enable ? "Enable" : "Disable", flag, err);
1669 return err;
1670 }
1671
6a9764ef 1672 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
4e59e288
GP		 1673 return 0;
1674}
1675
1676static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1677{
1678 struct mlx5e_priv *priv = netdev_priv(netdev);
1679 int err;
1680
1681 mutex_lock(&priv->state_lock);
9908aa29
TT		 1682 err = mlx5e_handle_pflag(netdev, pflags,
1683 MLX5E_PFLAG_RX_CQE_BASED_MODER,
1684 set_pflag_rx_cqe_based_moder);
9bcc8606
SD		 1685 if (err)
1686 goto out;
4e59e288 1687
0088cbbc
TG		 1688 err = mlx5e_handle_pflag(netdev, pflags,
1689 MLX5E_PFLAG_TX_CQE_BASED_MODER,
1690 set_pflag_tx_cqe_based_moder);
1691 if (err)
1692 goto out;
1693
9bcc8606
SD		 1694 err = mlx5e_handle_pflag(netdev, pflags,
1695 MLX5E_PFLAG_RX_CQE_COMPRESS,
1696 set_pflag_rx_cqe_compress);
2ccb0a79
TT		 1697 if (err)
1698 goto out;
1699
1700 err = mlx5e_handle_pflag(netdev, pflags,
1701 MLX5E_PFLAG_RX_STRIDING_RQ,
1702 set_pflag_rx_striding_rq);
b856df28
OG		 1703 if (err)
1704 goto out;
1705
1706 err = mlx5e_handle_pflag(netdev, pflags,
1707 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
1708 set_pflag_rx_no_csum_complete);
9bcc8606
SD		 1709
1710out:
4e59e288 1711 mutex_unlock(&priv->state_lock);
6c3a823e
TT		 1712
1713 /* Need to fix some features.. */
1714 netdev_update_features(netdev);
1715
9bcc8606 1716 return err;
4e59e288
GP		 1717}
1718
1719static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1720{
1721 struct mlx5e_priv *priv = netdev_priv(netdev);
1722
6a9764ef 1723 return priv->channels.params.pflags;
4e59e288
GP		 1724}
1725
3ffaabec
OG		 1726int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1727 struct ethtool_flash *flash)
1728{
1729 struct mlx5_core_dev *mdev = priv->mdev;
1730 struct net_device *dev = priv->netdev;
1731 const struct firmware *fw;
1732 int err;
1733
1734 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1735 return -EOPNOTSUPP;
1736
1737 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1738 if (err)
1739 return err;
1740
1741 dev_hold(dev);
1742 rtnl_unlock();
1743
1744 err = mlx5_firmware_flash(mdev, fw);
1745 release_firmware(fw);
1746
1747 rtnl_lock();
1748 dev_put(dev);
1749 return err;
1750}
1751
1752static int mlx5e_flash_device(struct net_device *dev,
1753 struct ethtool_flash *flash)
1754{
1755 struct mlx5e_priv *priv = netdev_priv(dev);
1756
1757 return mlx5e_ethtool_flash_device(priv, flash);
1758}
1759
f62b8bb8
AV		 1760const struct ethtool_ops mlx5e_ethtool_ops = {
1761 .get_drvinfo = mlx5e_get_drvinfo,
1762 .get_link = ethtool_op_get_link,
1763 .get_strings = mlx5e_get_strings,
1764 .get_sset_count = mlx5e_get_sset_count,
1765 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1766 .get_ringparam = mlx5e_get_ringparam,
1767 .set_ringparam = mlx5e_set_ringparam,
1768 .get_channels = mlx5e_get_channels,
1769 .set_channels = mlx5e_set_channels,
1770 .get_coalesce = mlx5e_get_coalesce,
1771 .set_coalesce = mlx5e_set_coalesce,
665bc539
GP		 1772 .get_link_ksettings = mlx5e_get_link_ksettings,
1773 .set_link_ksettings = mlx5e_set_link_ksettings,
2d75b2bc
AS		 1774 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1775 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2be6967c
SM		 1776 .get_rxfh = mlx5e_get_rxfh,
1777 .set_rxfh = mlx5e_set_rxfh,
fe6d86b3 1778#ifdef CONFIG_MLX5_EN_RXNFC
2d75b2bc 1779 .get_rxnfc = mlx5e_get_rxnfc,
6dc6071c 1780 .set_rxnfc = mlx5e_set_rxnfc,
fe6d86b3 1781#endif
3ffaabec 1782 .flash_device = mlx5e_flash_device,
58d52291
AS		 1783 .get_tunable = mlx5e_get_tunable,
1784 .set_tunable = mlx5e_set_tunable,
3c2d18ef
AS		 1785 .get_pauseparam = mlx5e_get_pauseparam,
1786 .set_pauseparam = mlx5e_set_pauseparam,
ef9814de 1787 .get_ts_info = mlx5e_get_ts_info,
da54d24e 1788 .set_phys_id = mlx5e_set_phys_id,
928cfe87
TT		 1789 .get_wol = mlx5e_get_wol,
1790 .set_wol = mlx5e_set_wol,
bb64143e
GP		 1791 .get_module_info = mlx5e_get_module_info,
1792 .get_module_eeprom = mlx5e_get_module_eeprom,
4e59e288 1793 .get_priv_flags = mlx5e_get_priv_flags,
d605d668
KH		 1794 .set_priv_flags = mlx5e_set_priv_flags,
1795 .self_test = mlx5e_self_test,
79c48764
GP		 1796 .get_msglevel = mlx5e_get_msglevel,
1797 .set_msglevel = mlx5e_set_msglevel,
6cfa9460
SA		 1798 .get_fecparam = mlx5e_get_fecparam,
1799 .set_fecparam = mlx5e_set_fecparam,
f62b8bb8 1800};
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