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[thirdparty/kernel/stable.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
60bbf7ee 38#include <net/page_pool.h>
1d447a39 39#include "eswitch.h"
f62b8bb8 40#include "en.h"
e8f887ac 41#include "en_tc.h"
1d447a39 42#include "en_rep.h"
547eede0 43#include "en_accel/ipsec.h"
899a59d3 44#include "en_accel/ipsec_rxtx.h"
c83294b9 45#include "en_accel/tls.h"
899a59d3 46#include "accel/ipsec.h"
c83294b9 47#include "accel/tls.h"
358aa5ce 48#include "lib/vxlan.h"
6dbc80ca 49#include "lib/clock.h"
2c81bfd5 50#include "en/port.h"
159d2131 51#include "en/xdp.h"
f62b8bb8
AV		 52
53struct mlx5e_rq_param {
cb3c7fd4
GR		 54 u32 rqc[MLX5_ST_SZ_DW(rqc)];
55 struct mlx5_wq_param wq;
069d1146 56 struct mlx5e_rq_frags_info frags_info;
f62b8bb8
AV		 57};
58
59struct mlx5e_sq_param {
60 u32 sqc[MLX5_ST_SZ_DW(sqc)];
61 struct mlx5_wq_param wq;
62};
63
64struct mlx5e_cq_param {
65 u32 cqc[MLX5_ST_SZ_DW(cqc)];
66 struct mlx5_wq_param wq;
67 u16 eq_ix;
9908aa29 68 u8 cq_period_mode;
f62b8bb8
AV		 69};
70
71struct mlx5e_channel_param {
72 struct mlx5e_rq_param rq;
73 struct mlx5e_sq_param sq;
b5503b99 74 struct mlx5e_sq_param xdp_sq;
d3c9bc27 75 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 76 struct mlx5e_cq_param rx_cq;
77 struct mlx5e_cq_param tx_cq;
d3c9bc27 78 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 79};
80
2ccb0a79 81bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2fc4bfb7 82{
ea3886ca 83 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
2fc4bfb7
SM		 84 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
85 MLX5_CAP_ETH(mdev, reg_umr_sq);
ea3886ca
TT		 86 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
87 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
88
89 if (!striding_rq_umr)
90 return false;
91 if (!inline_umr) {
92 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
93 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
94 return false;
95 }
96 return true;
2fc4bfb7
SM		 97}
98
069d1146 99static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
73281b78 100{
a26a5bdf
TT		 101 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
102 u16 linear_rq_headroom = params->xdp_prog ?
103 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
104 u32 frag_sz;
73281b78 105
a26a5bdf 106 linear_rq_headroom += NET_IP_ALIGN;
619a8f2a 107
a26a5bdf
TT		 108 frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu);
109
110 if (params->xdp_prog && frag_sz < PAGE_SIZE)
111 frag_sz = PAGE_SIZE;
112
113 return frag_sz;
73281b78
TT		 114}
115
116static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
117{
069d1146 118 u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
73281b78
TT		 119
120 return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
121}
122
069d1146
TT		 123static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
124 struct mlx5e_params *params)
125{
126 u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
127
128 return !params->lro_en && frag_sz <= PAGE_SIZE;
129}
130
619a8f2a
TT		 131static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
132 struct mlx5e_params *params)
133{
069d1146 134 u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
619a8f2a
TT		 135 s8 signed_log_num_strides_param;
136 u8 log_num_strides;
137
069d1146 138 if (!mlx5e_rx_is_linear_skb(mdev, params))
619a8f2a
TT		 139 return false;
140
141 if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
142 return true;
143
144 log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
145 signed_log_num_strides_param =
146 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
147
148 return signed_log_num_strides_param >= 0;
149}
150
73281b78
TT		 151static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
152{
153 if (params->log_rq_mtu_frames <
154 mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
155 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
156
157 return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
158}
159
160static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
161 struct mlx5e_params *params)
f1e4fc9b 162{
619a8f2a 163 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
069d1146 164 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
619a8f2a 165
f1e4fc9b
TT		 166 return MLX5E_MPWQE_STRIDE_SZ(mdev,
167 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
168}
169
73281b78
TT		 170static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
171 struct mlx5e_params *params)
f1e4fc9b
TT		 172{
173 return MLX5_MPWRQ_LOG_WQE_SZ -
174 mlx5e_mpwqe_get_log_stride_size(mdev, params);
175}
176
619a8f2a
TT		 177static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
178 struct mlx5e_params *params)
b0cedc84
TT		 179{
180 u16 linear_rq_headroom = params->xdp_prog ?
181 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
069d1146 182 bool is_linear_skb;
b0cedc84
TT		 183
184 linear_rq_headroom += NET_IP_ALIGN;
185
069d1146
TT		 186 is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
187 mlx5e_rx_is_linear_skb(mdev, params) :
188 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
b0cedc84 189
069d1146 190 return is_linear_skb ? linear_rq_headroom : 0;
b0cedc84
TT		 191}
192
696a97cf 193void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
2a0f561b 194 struct mlx5e_params *params)
2fc4bfb7 195{
6a9764ef 196 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
73281b78
TT		 197 params->log_rq_mtu_frames = is_kdump_kernel() ?
198 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
199 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2fc4bfb7 200
6a9764ef
SM		 201 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
202 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
619a8f2a
TT		 203 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
204 BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
73281b78 205 BIT(params->log_rq_mtu_frames),
f1e4fc9b 206 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
6a9764ef 207 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 208}
209
2ccb0a79
TT		 210bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
211 struct mlx5e_params *params)
212{
213 return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
22f45398
TT		 214 !MLX5_IPSEC_DEV(mdev) &&
215 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
2ccb0a79 216}
291f445e 217
2ccb0a79 218void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
2fc4bfb7 219{
2ccb0a79
TT		 220 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
221 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
291f445e 222 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
99cbfa93 223 MLX5_WQ_TYPE_CYCLIC;
2fc4bfb7
SM		 224}
225
f62b8bb8
AV		 226static void mlx5e_update_carrier(struct mlx5e_priv *priv)
227{
228 struct mlx5_core_dev *mdev = priv->mdev;
229 u8 port_state;
230
231 port_state = mlx5_query_vport_state(mdev,
cc9c82a8 232 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
e53eef63 233 0);
f62b8bb8 234
87424ad5
SD		 235 if (port_state == VPORT_STATE_UP) {
236 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 237 netif_carrier_on(priv->netdev);
87424ad5
SD		 238 } else {
239 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 240 netif_carrier_off(priv->netdev);
87424ad5 241 }
f62b8bb8
AV		 242}
243
244static void mlx5e_update_carrier_work(struct work_struct *work)
245{
246 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
247 update_carrier_work);
248
249 mutex_lock(&priv->state_lock);
250 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
7ca42c80
ES		 251 if (priv->profile->update_carrier)
252 priv->profile->update_carrier(priv);
f62b8bb8
AV		 253 mutex_unlock(&priv->state_lock);
254}
255
19386177 256void mlx5e_update_stats(struct mlx5e_priv *priv)
f62b8bb8 257{
19386177 258 int i;
f62b8bb8 259
19386177
KH		 260 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
261 if (mlx5e_stats_grps[i].update_stats)
262 mlx5e_stats_grps[i].update_stats(priv);
f62b8bb8
AV		 263}
264
3834a5e6
GP		 265static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
266{
19386177
KH		 267 int i;
268
269 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
270 if (mlx5e_stats_grps[i].update_stats_mask &
271 MLX5E_NDO_UPDATE_STATS)
272 mlx5e_stats_grps[i].update_stats(priv);
3834a5e6
GP		 273}
274
303211b4 275static void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8 276{
cdeef2b1 277 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
f62b8bb8 278 update_stats_work);
ed56c519 279
f62b8bb8 280 mutex_lock(&priv->state_lock);
ed56c519 281 priv->profile->update_stats(priv);
f62b8bb8
AV		 282 mutex_unlock(&priv->state_lock);
283}
284
cdeef2b1
SM		 285void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
286{
287 if (!priv->profile->update_stats)
288 return;
289
290 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
291 return;
292
293 queue_work(priv->wq, &priv->update_stats_work);
294}
295
daa21560
TT		 296static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
297 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 298{
daa21560
TT		 299 struct mlx5e_priv *priv = vpriv;
300
e0f46eb9 301 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 302 return;
303
f62b8bb8
AV		 304 switch (event) {
305 case MLX5_DEV_EVENT_PORT_UP:
306 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 307 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 308 break;
f62b8bb8
AV		 309 default:
310 break;
311 }
312}
313
f62b8bb8
AV		 314static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
315{
e0f46eb9 316 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 317}
318
319static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
320{
e0f46eb9 321 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
78249c42 322 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 323}
324
31391048
SM		 325static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
326 struct mlx5e_icosq *sq,
b8a98a4c 327 struct mlx5e_umr_wqe *wqe)
7e426671
TT		 328{
329 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
330 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
ea3886ca 331 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
7e426671
TT		 332
333 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
334 ds_cnt);
335 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
336 cseg->imm = rq->mkey_be;
337
ea3886ca 338 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
31616255 339 ucseg->xlt_octowords =
7e426671 340 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
7e426671 341 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
7e426671
TT		 342}
343
422d4c40
TT		 344static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
345{
346 switch (rq->wq_type) {
347 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
348 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
349 default:
99cbfa93 350 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
422d4c40
TT		 351 }
352}
353
354static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
355{
356 switch (rq->wq_type) {
357 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
358 return rq->mpwqe.wq.cur_sz;
359 default:
360 return rq->wqe.wq.cur_sz;
361 }
362}
363
7e426671
TT		 364static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
365 struct mlx5e_channel *c)
366{
422d4c40 367 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
7e426671 368
eec4edc9
KC		 369 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
370 sizeof(*rq->mpwqe.info)),
ca11b798 371 GFP_KERNEL, cpu_to_node(c->cpu));
21c59685 372 if (!rq->mpwqe.info)
ea3886ca 373 return -ENOMEM;
7e426671 374
b8a98a4c 375 mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
7e426671
TT		 376
377 return 0;
7e426671
TT		 378}
379
a43b25da 380static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
ec8b9981
TT		 381 u64 npages, u8 page_shift,
382 struct mlx5_core_mkey *umr_mkey)
3608ae77 383{
3608ae77
TT		 384 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
385 void *mkc;
386 u32 *in;
387 int err;
388
1b9a07ee 389 in = kvzalloc(inlen, GFP_KERNEL);
3608ae77
TT		 390 if (!in)
391 return -ENOMEM;
392
393 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
394
3608ae77
TT		 395 MLX5_SET(mkc, mkc, free, 1);
396 MLX5_SET(mkc, mkc, umr_en, 1);
397 MLX5_SET(mkc, mkc, lw, 1);
398 MLX5_SET(mkc, mkc, lr, 1);
cdbd0d2b 399 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
3608ae77
TT		 400
401 MLX5_SET(mkc, mkc, qpn, 0xffffff);
402 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 403 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 404 MLX5_SET(mkc, mkc, translations_octword_size,
405 MLX5_MTT_OCTW(npages));
ec8b9981 406 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 407
ec8b9981 408 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 409
410 kvfree(in);
411 return err;
412}
413
a43b25da 414static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
ec8b9981 415{
422d4c40 416 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
ec8b9981 417
a43b25da 418 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
ec8b9981
TT		 419}
420
b8a98a4c
TT		 421static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
422{
423 return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
424}
425
069d1146
TT		 426static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
427{
428 struct mlx5e_wqe_frag_info next_frag, *prev;
429 int i;
430
431 next_frag.di = &rq->wqe.di[0];
432 next_frag.offset = 0;
433 prev = NULL;
434
435 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
436 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
437 struct mlx5e_wqe_frag_info *frag =
438 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
439 int f;
440
441 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
442 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
443 next_frag.di++;
444 next_frag.offset = 0;
445 if (prev)
446 prev->last_in_page = true;
447 }
448 *frag = next_frag;
449
450 /* prepare next */
451 next_frag.offset += frag_info[f].frag_stride;
452 prev = frag;
453 }
454 }
455
456 if (prev)
457 prev->last_in_page = true;
458}
459
460static int mlx5e_init_di_list(struct mlx5e_rq *rq,
461 struct mlx5e_params *params,
462 int wq_sz, int cpu)
463{
464 int len = wq_sz << rq->wqe.info.log_num_frags;
465
84ca176b 466 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
069d1146
TT		 467 GFP_KERNEL, cpu_to_node(cpu));
468 if (!rq->wqe.di)
469 return -ENOMEM;
470
471 mlx5e_init_frags_partition(rq);
472
473 return 0;
474}
475
476static void mlx5e_free_di_list(struct mlx5e_rq *rq)
477{
478 kvfree(rq->wqe.di);
479}
480
3b77235b 481static int mlx5e_alloc_rq(struct mlx5e_channel *c,
6a9764ef
SM		 482 struct mlx5e_params *params,
483 struct mlx5e_rq_param *rqp,
3b77235b 484 struct mlx5e_rq *rq)
f62b8bb8 485{
60bbf7ee 486 struct page_pool_params pp_params = { 0 };
a43b25da 487 struct mlx5_core_dev *mdev = c->mdev;
6a9764ef 488 void *rqc = rqp->rqc;
f62b8bb8 489 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
069d1146 490 u32 pool_size;
f62b8bb8
AV		 491 int wq_sz;
492 int err;
493 int i;
494
231243c8 495 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
311c7c71 496
6a9764ef 497 rq->wq_type = params->rq_wq_type;
7e426671
TT		 498 rq->pdev = c->pdev;
499 rq->netdev = c->netdev;
a43b25da 500 rq->tstamp = c->tstamp;
7c39afb3 501 rq->clock = &mdev->clock;
7e426671
TT		 502 rq->channel = c;
503 rq->ix = c->ix;
a43b25da 504 rq->mdev = mdev;
05909bab 505 rq->stats = &c->priv->channel_stats[c->ix].rq;
97bc402d 506
6a9764ef 507 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
97bc402d
DB		 508 if (IS_ERR(rq->xdp_prog)) {
509 err = PTR_ERR(rq->xdp_prog);
510 rq->xdp_prog = NULL;
511 goto err_rq_wq_destroy;
512 }
7e426671 513
e213f5b6
WY		 514 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
515 if (err < 0)
0ddf5432
JDB		 516 goto err_rq_wq_destroy;
517
bce2b2bf 518 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
619a8f2a 519 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
60bbf7ee 520 pool_size = 1 << params->log_rq_mtu_frames;
b5503b99 521
6a9764ef 522 switch (rq->wq_type) {
461017cb 523 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
422d4c40
TT		 524 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
525 &rq->wq_ctrl);
526 if (err)
527 return err;
528
529 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
530
531 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
60bbf7ee
JDB		 532
533 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
422d4c40 534
7cc6d77b 535 rq->post_wqes = mlx5e_post_rx_mpwqes;
6cd392a0 536 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 537
20fd0c19 538 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
899a59d3
IT		 539#ifdef CONFIG_MLX5_EN_IPSEC
540 if (MLX5_IPSEC_DEV(mdev)) {
541 err = -EINVAL;
542 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
543 goto err_rq_wq_destroy;
544 }
545#endif
20fd0c19
SM		 546 if (!rq->handle_rx_cqe) {
547 err = -EINVAL;
548 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
549 goto err_rq_wq_destroy;
550 }
551
619a8f2a
TT		 552 rq->mpwqe.skb_from_cqe_mpwrq =
553 mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
554 mlx5e_skb_from_cqe_mpwrq_linear :
555 mlx5e_skb_from_cqe_mpwrq_nonlinear;
f1e4fc9b
TT		 556 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
557 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
1bfecfca 558
a43b25da 559 err = mlx5e_create_rq_umr_mkey(mdev, rq);
7e426671
TT		 560 if (err)
561 goto err_rq_wq_destroy;
ec8b9981
TT		 562 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
563
564 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
565 if (err)
069d1146 566 goto err_free;
461017cb 567 break;
99cbfa93
TT		 568 default: /* MLX5_WQ_TYPE_CYCLIC */
569 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
570 &rq->wq_ctrl);
422d4c40
TT		 571 if (err)
572 return err;
573
574 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
575
99cbfa93 576 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
422d4c40 577
069d1146
TT		 578 rq->wqe.info = rqp->frags_info;
579 rq->wqe.frags =
84ca176b
KC		 580 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
581 (wq_sz << rq->wqe.info.log_num_frags)),
069d1146 582 GFP_KERNEL, cpu_to_node(c->cpu));
47a6ca3f
WY		 583 if (!rq->wqe.frags) {
584 err = -ENOMEM;
069d1146 585 goto err_free;
47a6ca3f 586 }
069d1146
TT		 587
588 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
589 if (err)
590 goto err_free;
7cc6d77b 591 rq->post_wqes = mlx5e_post_rx_wqes;
6cd392a0 592 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 593
899a59d3
IT		 594#ifdef CONFIG_MLX5_EN_IPSEC
595 if (c->priv->ipsec)
596 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
597 else
598#endif
599 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
20fd0c19 600 if (!rq->handle_rx_cqe) {
20fd0c19
SM		 601 err = -EINVAL;
602 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
069d1146 603 goto err_free;
20fd0c19
SM		 604 }
605
069d1146
TT		 606 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
607 mlx5e_skb_from_cqe_linear :
608 mlx5e_skb_from_cqe_nonlinear;
7e426671 609 rq->mkey_be = c->mkey_be;
461017cb 610 }
f62b8bb8 611
60bbf7ee 612 /* Create a page_pool and register it with rxq */
069d1146 613 pp_params.order = 0;
60bbf7ee
JDB		 614 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
615 pp_params.pool_size = pool_size;
616 pp_params.nid = cpu_to_node(c->cpu);
617 pp_params.dev = c->pdev;
618 pp_params.dma_dir = rq->buff.map_dir;
619
620 /* page_pool can be used even when there is no rq->xdp_prog,
621 * given page_pool does not handle DMA mapping there is no
622 * required state to clear. And page_pool gracefully handle
623 * elevated refcnt.
624 */
625 rq->page_pool = page_pool_create(&pp_params);
626 if (IS_ERR(rq->page_pool)) {
60bbf7ee
JDB		 627 err = PTR_ERR(rq->page_pool);
628 rq->page_pool = NULL;
069d1146 629 goto err_free;
84f5e3fb 630 }
60bbf7ee
JDB		 631 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
632 MEM_TYPE_PAGE_POOL, rq->page_pool);
633 if (err)
069d1146 634 goto err_free;
84f5e3fb 635
f62b8bb8 636 for (i = 0; i < wq_sz; i++) {
4c2af5cc 637 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
99cbfa93 638 struct mlx5e_rx_wqe_ll *wqe =
422d4c40 639 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
069d1146
TT		 640 u32 byte_count =
641 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
b8a98a4c 642 u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
4c2af5cc 643
99cbfa93
TT		 644 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
645 wqe->data[0].byte_count = cpu_to_be32(byte_count);
646 wqe->data[0].lkey = rq->mkey_be;
422d4c40 647 } else {
99cbfa93
TT		 648 struct mlx5e_rx_wqe_cyc *wqe =
649 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
069d1146
TT		 650 int f;
651
652 for (f = 0; f < rq->wqe.info.num_frags; f++) {
653 u32 frag_size = rq->wqe.info.arr[f].frag_size |
654 MLX5_HW_START_PADDING;
655
656 wqe->data[f].byte_count = cpu_to_be32(frag_size);
657 wqe->data[f].lkey = rq->mkey_be;
658 }
659 /* check if num_frags is not a pow of two */
660 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
661 wqe->data[f].byte_count = 0;
662 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
663 wqe->data[f].addr = 0;
664 }
422d4c40 665 }
f62b8bb8
AV		 666 }
667
9a317425
AG		 668 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
669
670 switch (params->rx_cq_moderation.cq_period_mode) {
671 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
672 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
673 break;
674 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
675 default:
676 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
677 }
678
4415a031
TT		 679 rq->page_cache.head = 0;
680 rq->page_cache.tail = 0;
681
f62b8bb8
AV		 682 return 0;
683
069d1146
TT		 684err_free:
685 switch (rq->wq_type) {
686 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
ca11b798 687 kvfree(rq->mpwqe.info);
069d1146
TT		 688 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
689 break;
690 default: /* MLX5_WQ_TYPE_CYCLIC */
691 kvfree(rq->wqe.frags);
692 mlx5e_free_di_list(rq);
693 }
ec8b9981 694
f62b8bb8 695err_rq_wq_destroy:
97bc402d
DB		 696 if (rq->xdp_prog)
697 bpf_prog_put(rq->xdp_prog);
0ddf5432 698 xdp_rxq_info_unreg(&rq->xdp_rxq);
60bbf7ee
JDB		 699 if (rq->page_pool)
700 page_pool_destroy(rq->page_pool);
f62b8bb8
AV		 701 mlx5_wq_destroy(&rq->wq_ctrl);
702
703 return err;
704}
705
3b77235b 706static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 707{
4415a031
TT		 708 int i;
709
86994156
RS		 710 if (rq->xdp_prog)
711 bpf_prog_put(rq->xdp_prog);
712
0ddf5432 713 xdp_rxq_info_unreg(&rq->xdp_rxq);
60bbf7ee
JDB		 714 if (rq->page_pool)
715 page_pool_destroy(rq->page_pool);
0ddf5432 716
461017cb
TT		 717 switch (rq->wq_type) {
718 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
ca11b798 719 kvfree(rq->mpwqe.info);
a43b25da 720 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
461017cb 721 break;
99cbfa93 722 default: /* MLX5_WQ_TYPE_CYCLIC */
069d1146
TT		 723 kvfree(rq->wqe.frags);
724 mlx5e_free_di_list(rq);
461017cb
TT		 725 }
726
4415a031
TT		 727 for (i = rq->page_cache.head; i != rq->page_cache.tail;
728 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
729 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
730
731 mlx5e_page_release(rq, dma_info, false);
732 }
f62b8bb8
AV		 733 mlx5_wq_destroy(&rq->wq_ctrl);
734}
735
6a9764ef
SM		 736static int mlx5e_create_rq(struct mlx5e_rq *rq,
737 struct mlx5e_rq_param *param)
f62b8bb8 738{
a43b25da 739 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 740
741 void *in;
742 void *rqc;
743 void *wq;
744 int inlen;
745 int err;
746
747 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
748 sizeof(u64) * rq->wq_ctrl.buf.npages;
1b9a07ee 749 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 750 if (!in)
751 return -ENOMEM;
752
753 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
754 wq = MLX5_ADDR_OF(rqc, rqc, wq);
755
756 memcpy(rqc, param->rqc, sizeof(param->rqc));
757
97de9f31 758 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 759 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
f62b8bb8 760 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 761 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 762 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
763
3a2f7033
TT		 764 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
765 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 766
7db22ffb 767 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 768
769 kvfree(in);
770
771 return err;
772}
773
36350114
GP		 774static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
775 int next_state)
f62b8bb8 776{
7cbaf9a3 777 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 778
779 void *in;
780 void *rqc;
781 int inlen;
782 int err;
783
784 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 785 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 786 if (!in)
787 return -ENOMEM;
788
789 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
790
791 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
792 MLX5_SET(rqc, rqc, state, next_state);
793
7db22ffb 794 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 795
796 kvfree(in);
797
798 return err;
799}
800
102722fc
GE		 801static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
802{
803 struct mlx5e_channel *c = rq->channel;
804 struct mlx5e_priv *priv = c->priv;
805 struct mlx5_core_dev *mdev = priv->mdev;
806
807 void *in;
808 void *rqc;
809 int inlen;
810 int err;
811
812 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 813 in = kvzalloc(inlen, GFP_KERNEL);
102722fc
GE		 814 if (!in)
815 return -ENOMEM;
816
817 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
818
819 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
820 MLX5_SET64(modify_rq_in, in, modify_bitmask,
821 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
822 MLX5_SET(rqc, rqc, scatter_fcs, enable);
823 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
824
825 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
826
827 kvfree(in);
828
829 return err;
830}
831
36350114
GP		 832static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
833{
834 struct mlx5e_channel *c = rq->channel;
a43b25da 835 struct mlx5_core_dev *mdev = c->mdev;
36350114
GP		 836 void *in;
837 void *rqc;
838 int inlen;
839 int err;
840
841 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 842 in = kvzalloc(inlen, GFP_KERNEL);
36350114
GP		 843 if (!in)
844 return -ENOMEM;
845
846 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
847
848 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 849 MLX5_SET64(modify_rq_in, in, modify_bitmask,
850 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 851 MLX5_SET(rqc, rqc, vsd, vsd);
852 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
853
854 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
855
856 kvfree(in);
857
858 return err;
859}
860
3b77235b 861static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 862{
a43b25da 863 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
f62b8bb8
AV		 864}
865
1e7477ae 866static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
f62b8bb8 867{
1e7477ae 868 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
f62b8bb8 869 struct mlx5e_channel *c = rq->channel;
a43b25da 870
422d4c40 871 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
f62b8bb8 872
1e7477ae 873 do {
422d4c40 874 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
f62b8bb8
AV		 875 return 0;
876
877 msleep(20);
1e7477ae
EBE		 878 } while (time_before(jiffies, exp_time));
879
880 netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
422d4c40 881 c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
f62b8bb8
AV		 882
883 return -ETIMEDOUT;
884}
885
f2fde18c
SM		 886static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
887{
f2fde18c
SM		 888 __be16 wqe_ix_be;
889 u16 wqe_ix;
890
422d4c40
TT		 891 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
892 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
893
99cbfa93 894 /* UMR WQE (if in progress) is always at wq->head */
422d4c40 895 if (rq->mpwqe.umr_in_progress)
afab995e 896 rq->dealloc_wqe(rq, wq->head);
422d4c40
TT		 897
898 while (!mlx5_wq_ll_is_empty(wq)) {
99cbfa93 899 struct mlx5e_rx_wqe_ll *wqe;
422d4c40
TT		 900
901 wqe_ix_be = *wq->tail_next;
902 wqe_ix = be16_to_cpu(wqe_ix_be);
903 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
904 rq->dealloc_wqe(rq, wqe_ix);
905 mlx5_wq_ll_pop(wq, wqe_ix_be,
906 &wqe->next.next_wqe_index);
907 }
908 } else {
99cbfa93 909 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
422d4c40 910
99cbfa93
TT		 911 while (!mlx5_wq_cyc_is_empty(wq)) {
912 wqe_ix = mlx5_wq_cyc_get_tail(wq);
422d4c40 913 rq->dealloc_wqe(rq, wqe_ix);
99cbfa93 914 mlx5_wq_cyc_pop(wq);
422d4c40 915 }
accd5883 916 }
069d1146 917
f2fde18c
SM		 918}
919
f62b8bb8 920static int mlx5e_open_rq(struct mlx5e_channel *c,
6a9764ef 921 struct mlx5e_params *params,
f62b8bb8
AV		 922 struct mlx5e_rq_param *param,
923 struct mlx5e_rq *rq)
924{
925 int err;
926
6a9764ef 927 err = mlx5e_alloc_rq(c, params, param, rq);
f62b8bb8
AV		 928 if (err)
929 return err;
930
3b77235b 931 err = mlx5e_create_rq(rq, param);
f62b8bb8 932 if (err)
3b77235b 933 goto err_free_rq;
f62b8bb8 934
36350114 935 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 936 if (err)
3b77235b 937 goto err_destroy_rq;
f62b8bb8 938
9a317425 939 if (params->rx_dim_enabled)
af5a6c93 940 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
cb3c7fd4 941
b856df28
OG		 942 if (params->pflags & MLX5E_PFLAG_RX_NO_CSUM_COMPLETE)
943 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
944
f62b8bb8
AV		 945 return 0;
946
f62b8bb8
AV		 947err_destroy_rq:
948 mlx5e_destroy_rq(rq);
3b77235b
SM		 949err_free_rq:
950 mlx5e_free_rq(rq);
f62b8bb8
AV		 951
952 return err;
953}
954
acc6c595
SM		 955static void mlx5e_activate_rq(struct mlx5e_rq *rq)
956{
957 struct mlx5e_icosq *sq = &rq->channel->icosq;
ddf385e3 958 struct mlx5_wq_cyc *wq = &sq->wq;
acc6c595
SM		 959 struct mlx5e_tx_wqe *nopwqe;
960
ddf385e3
TT		 961 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
962
acc6c595
SM		 963 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
964 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
ddf385e3
TT		 965 nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
966 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
acc6c595
SM		 967}
968
969static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
f62b8bb8 970{
c0f1147d 971 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 972 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
acc6c595 973}
cb3c7fd4 974
acc6c595
SM		 975static void mlx5e_close_rq(struct mlx5e_rq *rq)
976{
9a317425 977 cancel_work_sync(&rq->dim.work);
f62b8bb8 978 mlx5e_destroy_rq(rq);
3b77235b
SM		 979 mlx5e_free_rx_descs(rq);
980 mlx5e_free_rq(rq);
f62b8bb8
AV		 981}
982
31391048 983static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
b5503b99 984{
c94e4f11 985 kvfree(sq->db.xdpi);
b5503b99
SM		 986}
987
31391048 988static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
b5503b99
SM		 989{
990 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
991
c94e4f11
TT		 992 sq->db.xdpi = kvzalloc_node(array_size(wq_sz, sizeof(*sq->db.xdpi)),
993 GFP_KERNEL, numa);
994 if (!sq->db.xdpi) {
31391048 995 mlx5e_free_xdpsq_db(sq);
b5503b99
SM		 996 return -ENOMEM;
997 }
998
999 return 0;
1000}
1001
31391048 1002static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
6a9764ef 1003 struct mlx5e_params *params,
31391048 1004 struct mlx5e_sq_param *param,
58b99ee3
TT		 1005 struct mlx5e_xdpsq *sq,
1006 bool is_redirect)
31391048
SM		 1007{
1008 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1009 struct mlx5_core_dev *mdev = c->mdev;
ddf385e3 1010 struct mlx5_wq_cyc *wq = &sq->wq;
31391048
SM		 1011 int err;
1012
1013 sq->pdev = c->pdev;
1014 sq->mkey_be = c->mkey_be;
1015 sq->channel = c;
1016 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 1017 sq->min_inline_mode = params->tx_min_inline_mode;
c94e4f11 1018 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
58b99ee3
TT		 1019 sq->stats = is_redirect ?
1020 &c->priv->channel_stats[c->ix].xdpsq :
1021 &c->priv->channel_stats[c->ix].rq_xdpsq;
31391048 1022
231243c8 1023 param->wq.db_numa_node = cpu_to_node(c->cpu);
ddf385e3 1024 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
31391048
SM		 1025 if (err)
1026 return err;
ddf385e3 1027 wq->db = &wq->db[MLX5_SND_DBR];
31391048 1028
231243c8 1029 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
31391048
SM		 1030 if (err)
1031 goto err_sq_wq_destroy;
1032
1033 return 0;
1034
1035err_sq_wq_destroy:
1036 mlx5_wq_destroy(&sq->wq_ctrl);
1037
1038 return err;
1039}
1040
1041static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1042{
1043 mlx5e_free_xdpsq_db(sq);
1044 mlx5_wq_destroy(&sq->wq_ctrl);
1045}
1046
1047static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
f62b8bb8 1048{
ca11b798 1049 kvfree(sq->db.ico_wqe);
f62b8bb8
AV		 1050}
1051
31391048 1052static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
f10b7cc7
SM		 1053{
1054 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1055
eec4edc9
KC		 1056 sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1057 sizeof(*sq->db.ico_wqe)),
ca11b798 1058 GFP_KERNEL, numa);
f10b7cc7
SM		 1059 if (!sq->db.ico_wqe)
1060 return -ENOMEM;
1061
1062 return 0;
1063}
1064
31391048 1065static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
31391048
SM		 1066 struct mlx5e_sq_param *param,
1067 struct mlx5e_icosq *sq)
f10b7cc7 1068{
31391048 1069 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1070 struct mlx5_core_dev *mdev = c->mdev;
ddf385e3 1071 struct mlx5_wq_cyc *wq = &sq->wq;
31391048 1072 int err;
f10b7cc7 1073
31391048
SM		 1074 sq->channel = c;
1075 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f62b8bb8 1076
231243c8 1077 param->wq.db_numa_node = cpu_to_node(c->cpu);
ddf385e3 1078 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
31391048
SM		 1079 if (err)
1080 return err;
ddf385e3 1081 wq->db = &wq->db[MLX5_SND_DBR];
f62b8bb8 1082
231243c8 1083 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
31391048
SM		 1084 if (err)
1085 goto err_sq_wq_destroy;
1086
f62b8bb8 1087 return 0;
31391048
SM		 1088
1089err_sq_wq_destroy:
1090 mlx5_wq_destroy(&sq->wq_ctrl);
1091
1092 return err;
f62b8bb8
AV		 1093}
1094
31391048 1095static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
f10b7cc7 1096{
31391048
SM		 1097 mlx5e_free_icosq_db(sq);
1098 mlx5_wq_destroy(&sq->wq_ctrl);
f10b7cc7
SM		 1099}
1100
31391048 1101static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
f10b7cc7 1102{
ca11b798
TT		 1103 kvfree(sq->db.wqe_info);
1104 kvfree(sq->db.dma_fifo);
f10b7cc7
SM		 1105}
1106
31391048 1107static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
b5503b99 1108{
31391048
SM		 1109 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1110 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1111
eec4edc9
KC		 1112 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1113 sizeof(*sq->db.dma_fifo)),
ca11b798 1114 GFP_KERNEL, numa);
eec4edc9
KC		 1115 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1116 sizeof(*sq->db.wqe_info)),
ca11b798 1117 GFP_KERNEL, numa);
77bdf895 1118 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
31391048
SM		 1119 mlx5e_free_txqsq_db(sq);
1120 return -ENOMEM;
b5503b99 1121 }
31391048
SM		 1122
1123 sq->dma_fifo_mask = df_sz - 1;
1124
1125 return 0;
b5503b99
SM		 1126}
1127
db75373c 1128static void mlx5e_sq_recover(struct work_struct *work);
31391048 1129static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
acc6c595 1130 int txq_ix,
6a9764ef 1131 struct mlx5e_params *params,
31391048 1132 struct mlx5e_sq_param *param,
05909bab
EBE		 1133 struct mlx5e_txqsq *sq,
1134 int tc)
f62b8bb8 1135{
31391048 1136 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1137 struct mlx5_core_dev *mdev = c->mdev;
ddf385e3 1138 struct mlx5_wq_cyc *wq = &sq->wq;
f62b8bb8
AV		 1139 int err;
1140
f10b7cc7 1141 sq->pdev = c->pdev;
a43b25da 1142 sq->tstamp = c->tstamp;
7c39afb3 1143 sq->clock = &mdev->clock;
f10b7cc7
SM		 1144 sq->mkey_be = c->mkey_be;
1145 sq->channel = c;
acc6c595 1146 sq->txq_ix = txq_ix;
aff26157 1147 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 1148 sq->min_inline_mode = params->tx_min_inline_mode;
05909bab 1149 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
db75373c 1150 INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
2ac9cfe7
IT		 1151 if (MLX5_IPSEC_DEV(c->priv->mdev))
1152 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
bf239741
IL		 1153 if (mlx5_accel_is_tls_device(c->priv->mdev))
1154 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
f10b7cc7 1155
231243c8 1156 param->wq.db_numa_node = cpu_to_node(c->cpu);
ddf385e3 1157 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
f62b8bb8 1158 if (err)
aff26157 1159 return err;
ddf385e3 1160 wq->db = &wq->db[MLX5_SND_DBR];
f62b8bb8 1161
231243c8 1162 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
7ec0bb22 1163 if (err)
f62b8bb8
AV		 1164 goto err_sq_wq_destroy;
1165
cbce4f44
TG		 1166 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1167 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1168
f62b8bb8
AV		 1169 return 0;
1170
1171err_sq_wq_destroy:
1172 mlx5_wq_destroy(&sq->wq_ctrl);
1173
f62b8bb8
AV		 1174 return err;
1175}
1176
31391048 1177static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1178{
31391048 1179 mlx5e_free_txqsq_db(sq);
f62b8bb8 1180 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1181}
1182
33ad9711
SM		 1183struct mlx5e_create_sq_param {
1184 struct mlx5_wq_ctrl *wq_ctrl;
1185 u32 cqn;
1186 u32 tisn;
1187 u8 tis_lst_sz;
1188 u8 min_inline_mode;
1189};
1190
a43b25da 1191static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
33ad9711
SM		 1192 struct mlx5e_sq_param *param,
1193 struct mlx5e_create_sq_param *csp,
1194 u32 *sqn)
f62b8bb8 1195{
f62b8bb8
AV		 1196 void *in;
1197 void *sqc;
1198 void *wq;
1199 int inlen;
1200 int err;
1201
1202 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
33ad9711 1203 sizeof(u64) * csp->wq_ctrl->buf.npages;
1b9a07ee 1204 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1205 if (!in)
1206 return -ENOMEM;
1207
1208 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1209 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1210
1211 memcpy(sqc, param->sqc, sizeof(param->sqc));
33ad9711
SM		 1212 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1213 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1214 MLX5_SET(sqc, sqc, cqn, csp->cqn);
a6f402e4
SM		 1215
1216 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
33ad9711 1217 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
a6f402e4 1218
33ad9711 1219 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
db75373c 1220 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
f62b8bb8
AV		 1221
1222 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
a43b25da 1223 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
33ad9711 1224 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
68cdf5d6 1225 MLX5_ADAPTER_PAGE_SHIFT);
33ad9711 1226 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
f62b8bb8 1227
3a2f7033
TT		 1228 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1229 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 1230
33ad9711 1231 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
f62b8bb8
AV		 1232
1233 kvfree(in);
1234
1235 return err;
1236}
1237
33ad9711
SM		 1238struct mlx5e_modify_sq_param {
1239 int curr_state;
1240 int next_state;
1241 bool rl_update;
1242 int rl_index;
1243};
1244
a43b25da 1245static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
33ad9711 1246 struct mlx5e_modify_sq_param *p)
f62b8bb8 1247{
f62b8bb8
AV		 1248 void *in;
1249 void *sqc;
1250 int inlen;
1251 int err;
1252
1253 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 1254 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1255 if (!in)
1256 return -ENOMEM;
1257
1258 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1259
33ad9711
SM		 1260 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1261 MLX5_SET(sqc, sqc, state, p->next_state);
1262 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
507f0c81 1263 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
33ad9711 1264 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
507f0c81 1265 }
f62b8bb8 1266
33ad9711 1267 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
f62b8bb8
AV		 1268
1269 kvfree(in);
1270
1271 return err;
1272}
1273
a43b25da 1274static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
33ad9711 1275{
a43b25da 1276 mlx5_core_destroy_sq(mdev, sqn);
f62b8bb8
AV		 1277}
1278
a43b25da 1279static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
31391048
SM		 1280 struct mlx5e_sq_param *param,
1281 struct mlx5e_create_sq_param *csp,
1282 u32 *sqn)
f62b8bb8 1283{
33ad9711 1284 struct mlx5e_modify_sq_param msp = {0};
31391048
SM		 1285 int err;
1286
a43b25da 1287 err = mlx5e_create_sq(mdev, param, csp, sqn);
31391048
SM		 1288 if (err)
1289 return err;
1290
1291 msp.curr_state = MLX5_SQC_STATE_RST;
1292 msp.next_state = MLX5_SQC_STATE_RDY;
a43b25da 1293 err = mlx5e_modify_sq(mdev, *sqn, &msp);
31391048 1294 if (err)
a43b25da 1295 mlx5e_destroy_sq(mdev, *sqn);
31391048
SM		 1296
1297 return err;
1298}
1299
7f859ecf
SM		 1300static int mlx5e_set_sq_maxrate(struct net_device *dev,
1301 struct mlx5e_txqsq *sq, u32 rate);
1302
31391048 1303static int mlx5e_open_txqsq(struct mlx5e_channel *c,
a43b25da 1304 u32 tisn,
acc6c595 1305 int txq_ix,
6a9764ef 1306 struct mlx5e_params *params,
31391048 1307 struct mlx5e_sq_param *param,
05909bab
EBE		 1308 struct mlx5e_txqsq *sq,
1309 int tc)
31391048
SM		 1310{
1311 struct mlx5e_create_sq_param csp = {};
7f859ecf 1312 u32 tx_rate;
f62b8bb8
AV		 1313 int err;
1314
05909bab 1315 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
f62b8bb8
AV		 1316 if (err)
1317 return err;
1318
a43b25da 1319 csp.tisn = tisn;
31391048 1320 csp.tis_lst_sz = 1;
33ad9711
SM		 1321 csp.cqn = sq->cq.mcq.cqn;
1322 csp.wq_ctrl = &sq->wq_ctrl;
1323 csp.min_inline_mode = sq->min_inline_mode;
a43b25da 1324 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
f62b8bb8 1325 if (err)
31391048 1326 goto err_free_txqsq;
f62b8bb8 1327
a43b25da 1328 tx_rate = c->priv->tx_rates[sq->txq_ix];
7f859ecf 1329 if (tx_rate)
a43b25da 1330 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
7f859ecf 1331
cbce4f44
TG		 1332 if (params->tx_dim_enabled)
1333 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1334
f62b8bb8
AV		 1335 return 0;
1336
31391048 1337err_free_txqsq:
3b77235b 1338 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
31391048 1339 mlx5e_free_txqsq(sq);
f62b8bb8
AV		 1340
1341 return err;
1342}
1343
db75373c
EBE		 1344static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1345{
1346 WARN_ONCE(sq->cc != sq->pc,
1347 "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1348 sq->sqn, sq->cc, sq->pc);
1349 sq->cc = 0;
1350 sq->dma_fifo_cc = 0;
1351 sq->pc = 0;
1352}
1353
acc6c595
SM		 1354static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1355{
a43b25da 1356 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
db75373c 1357 clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
acc6c595
SM		 1358 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1359 netdev_tx_reset_queue(sq->txq);
1360 netif_tx_start_queue(sq->txq);
1361}
1362
f62b8bb8
AV		 1363static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1364{
1365 __netif_tx_lock_bh(txq);
1366 netif_tx_stop_queue(txq);
1367 __netif_tx_unlock_bh(txq);
1368}
1369
acc6c595 1370static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1371{
33ad9711 1372 struct mlx5e_channel *c = sq->channel;
ddf385e3 1373 struct mlx5_wq_cyc *wq = &sq->wq;
33ad9711 1374
c0f1147d 1375 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6 1376 /* prevent netif_tx_wake_queue */
33ad9711 1377 napi_synchronize(&c->napi);
29429f33 1378
31391048 1379 netif_tx_disable_queue(sq->txq);
f62b8bb8 1380
31391048 1381 /* last doorbell out, godspeed .. */
ddf385e3
TT		 1382 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1383 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
31391048 1384 struct mlx5e_tx_wqe *nop;
864b2d71 1385
ddf385e3
TT		 1386 sq->db.wqe_info[pi].skb = NULL;
1387 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1388 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
29429f33 1389 }
acc6c595
SM		 1390}
1391
1392static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1393{
1394 struct mlx5e_channel *c = sq->channel;
a43b25da 1395 struct mlx5_core_dev *mdev = c->mdev;
05d3ac97 1396 struct mlx5_rate_limit rl = {0};
f62b8bb8 1397
a43b25da 1398 mlx5e_destroy_sq(mdev, sq->sqn);
05d3ac97
BW		 1399 if (sq->rate_limit) {
1400 rl.rate = sq->rate_limit;
1401 mlx5_rl_remove_rate(mdev, &rl);
1402 }
31391048
SM		 1403 mlx5e_free_txqsq_descs(sq);
1404 mlx5e_free_txqsq(sq);
1405}
1406
db75373c
EBE		 1407static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1408{
1409 unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1410
1411 while (time_before(jiffies, exp_time)) {
1412 if (sq->cc == sq->pc)
1413 return 0;
1414
1415 msleep(20);
1416 }
1417
1418 netdev_err(sq->channel->netdev,
1419 "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1420 sq->sqn, sq->cc, sq->pc);
1421
1422 return -ETIMEDOUT;
1423}
1424
1425static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1426{
1427 struct mlx5_core_dev *mdev = sq->channel->mdev;
1428 struct net_device *dev = sq->channel->netdev;
1429 struct mlx5e_modify_sq_param msp = {0};
1430 int err;
1431
1432 msp.curr_state = curr_state;
1433 msp.next_state = MLX5_SQC_STATE_RST;
1434
1435 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1436 if (err) {
1437 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1438 return err;
1439 }
1440
1441 memset(&msp, 0, sizeof(msp));
1442 msp.curr_state = MLX5_SQC_STATE_RST;
1443 msp.next_state = MLX5_SQC_STATE_RDY;
1444
1445 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1446 if (err) {
1447 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1448 return err;
1449 }
1450
1451 return 0;
1452}
1453
1454static void mlx5e_sq_recover(struct work_struct *work)
1455{
1456 struct mlx5e_txqsq_recover *recover =
1457 container_of(work, struct mlx5e_txqsq_recover,
1458 recover_work);
1459 struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1460 recover);
1461 struct mlx5_core_dev *mdev = sq->channel->mdev;
1462 struct net_device *dev = sq->channel->netdev;
1463 u8 state;
1464 int err;
1465
1466 err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1467 if (err) {
1468 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1469 sq->sqn, err);
1470 return;
1471 }
1472
1473 if (state != MLX5_RQC_STATE_ERR) {
1474 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1475 return;
1476 }
1477
1478 netif_tx_disable_queue(sq->txq);
1479
1480 if (mlx5e_wait_for_sq_flush(sq))
1481 return;
1482
1483 /* If the interval between two consecutive recovers per SQ is too
1484 * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1485 * If we reached this state, there is probably a bug that needs to be
1486 * fixed. let's keep the queue close and let tx timeout cleanup.
1487 */
1488 if (jiffies_to_msecs(jiffies - recover->last_recover) <
1489 MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1490 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1491 sq->sqn);
1492 return;
1493 }
1494
1495 /* At this point, no new packets will arrive from the stack as TXQ is
1496 * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1497 * pending WQEs. SQ can safely reset the SQ.
1498 */
1499 if (mlx5e_sq_to_ready(sq, state))
1500 return;
1501
1502 mlx5e_reset_txqsq_cc_pc(sq);
05909bab 1503 sq->stats->recover++;
db75373c
EBE		 1504 recover->last_recover = jiffies;
1505 mlx5e_activate_txqsq(sq);
1506}
1507
31391048 1508static int mlx5e_open_icosq(struct mlx5e_channel *c,
6a9764ef 1509 struct mlx5e_params *params,
31391048
SM		 1510 struct mlx5e_sq_param *param,
1511 struct mlx5e_icosq *sq)
1512{
1513 struct mlx5e_create_sq_param csp = {};
1514 int err;
1515
6a9764ef 1516 err = mlx5e_alloc_icosq(c, param, sq);
31391048
SM		 1517 if (err)
1518 return err;
1519
1520 csp.cqn = sq->cq.mcq.cqn;
1521 csp.wq_ctrl = &sq->wq_ctrl;
6a9764ef 1522 csp.min_inline_mode = params->tx_min_inline_mode;
31391048 1523 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1524 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1525 if (err)
1526 goto err_free_icosq;
1527
1528 return 0;
1529
1530err_free_icosq:
1531 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1532 mlx5e_free_icosq(sq);
1533
1534 return err;
1535}
1536
1537static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1538{
1539 struct mlx5e_channel *c = sq->channel;
1540
1541 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1542 napi_synchronize(&c->napi);
1543
a43b25da 1544 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1545 mlx5e_free_icosq(sq);
1546}
1547
1548static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
6a9764ef 1549 struct mlx5e_params *params,
31391048 1550 struct mlx5e_sq_param *param,
58b99ee3
TT		 1551 struct mlx5e_xdpsq *sq,
1552 bool is_redirect)
31391048
SM		 1553{
1554 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1555 struct mlx5e_create_sq_param csp = {};
31391048
SM		 1556 unsigned int inline_hdr_sz = 0;
1557 int err;
1558 int i;
1559
58b99ee3 1560 err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
31391048
SM		 1561 if (err)
1562 return err;
1563
1564 csp.tis_lst_sz = 1;
a43b25da 1565 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
31391048
SM		 1566 csp.cqn = sq->cq.mcq.cqn;
1567 csp.wq_ctrl = &sq->wq_ctrl;
1568 csp.min_inline_mode = sq->min_inline_mode;
58b99ee3
TT		 1569 if (is_redirect)
1570 set_bit(MLX5E_SQ_STATE_REDIRECT, &sq->state);
31391048 1571 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1572 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1573 if (err)
1574 goto err_free_xdpsq;
1575
1576 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1577 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1578 ds_cnt++;
1579 }
1580
1581 /* Pre initialize fixed WQE fields */
1582 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1583 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1584 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1585 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1586 struct mlx5_wqe_data_seg *dseg;
1587
1588 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1589 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1590
1591 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1592 dseg->lkey = sq->mkey_be;
1593 }
1594
1595 return 0;
1596
1597err_free_xdpsq:
1598 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1599 mlx5e_free_xdpsq(sq);
1600
1601 return err;
1602}
1603
1604static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1605{
1606 struct mlx5e_channel *c = sq->channel;
1607
1608 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1609 napi_synchronize(&c->napi);
1610
a43b25da 1611 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1612 mlx5e_free_xdpsq_descs(sq);
1613 mlx5e_free_xdpsq(sq);
f62b8bb8
AV		 1614}
1615
95b6c6a5
EBE		 1616static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1617 struct mlx5e_cq_param *param,
1618 struct mlx5e_cq *cq)
f62b8bb8 1619{
f62b8bb8
AV		 1620 struct mlx5_core_cq *mcq = &cq->mcq;
1621 int eqn_not_used;
0b6e26ce 1622 unsigned int irqn;
f62b8bb8
AV		 1623 int err;
1624 u32 i;
1625
f62b8bb8
AV		 1626 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1627 &cq->wq_ctrl);
1628 if (err)
1629 return err;
1630
1631 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1632
f62b8bb8
AV		 1633 mcq->cqe_sz = 64;
1634 mcq->set_ci_db = cq->wq_ctrl.db.db;
1635 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1636 *mcq->set_ci_db = 0;
1637 *mcq->arm_db = 0;
1638 mcq->vector = param->eq_ix;
1639 mcq->comp = mlx5e_completion_event;
1640 mcq->event = mlx5e_cq_error_event;
1641 mcq->irqn = irqn;
f62b8bb8
AV		 1642
1643 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1644 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1645
1646 cqe->op_own = 0xf1;
1647 }
1648
a43b25da 1649 cq->mdev = mdev;
f62b8bb8
AV		 1650
1651 return 0;
1652}
1653
95b6c6a5
EBE		 1654static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1655 struct mlx5e_cq_param *param,
1656 struct mlx5e_cq *cq)
1657{
1658 struct mlx5_core_dev *mdev = c->priv->mdev;
1659 int err;
1660
231243c8
SM		 1661 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1662 param->wq.db_numa_node = cpu_to_node(c->cpu);
95b6c6a5
EBE		 1663 param->eq_ix = c->ix;
1664
1665 err = mlx5e_alloc_cq_common(mdev, param, cq);
1666
1667 cq->napi = &c->napi;
1668 cq->channel = c;
1669
1670 return err;
1671}
1672
3b77235b 1673static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1674{
3a2f7033 1675 mlx5_wq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1676}
1677
3b77235b 1678static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1679{
a43b25da 1680 struct mlx5_core_dev *mdev = cq->mdev;
f62b8bb8
AV		 1681 struct mlx5_core_cq *mcq = &cq->mcq;
1682
1683 void *in;
1684 void *cqc;
1685 int inlen;
0b6e26ce 1686 unsigned int irqn_not_used;
f62b8bb8
AV		 1687 int eqn;
1688 int err;
1689
1690 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
3a2f7033 1691 sizeof(u64) * cq->wq_ctrl.buf.npages;
1b9a07ee 1692 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1693 if (!in)
1694 return -ENOMEM;
1695
1696 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1697
1698 memcpy(cqc, param->cqc, sizeof(param->cqc));
1699
3a2f7033 1700 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1c1b5228 1701 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1702
1703 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1704
9908aa29 1705 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1706 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1707 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
3a2f7033 1708 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 1709 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1710 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1711
1712 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1713
1714 kvfree(in);
1715
1716 if (err)
1717 return err;
1718
1719 mlx5e_cq_arm(cq);
1720
1721 return 0;
1722}
1723
3b77235b 1724static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1725{
a43b25da 1726 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
f62b8bb8
AV		 1727}
1728
1729static int mlx5e_open_cq(struct mlx5e_channel *c,
9a317425 1730 struct net_dim_cq_moder moder,
f62b8bb8 1731 struct mlx5e_cq_param *param,
6a9764ef 1732 struct mlx5e_cq *cq)
f62b8bb8 1733{
a43b25da 1734 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1735 int err;
f62b8bb8 1736
3b77235b 1737 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1738 if (err)
1739 return err;
1740
3b77235b 1741 err = mlx5e_create_cq(cq, param);
f62b8bb8 1742 if (err)
3b77235b 1743 goto err_free_cq;
f62b8bb8 1744
7524a5d8 1745 if (MLX5_CAP_GEN(mdev, cq_moderation))
6a9764ef 1746 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
f62b8bb8
AV		 1747 return 0;
1748
3b77235b
SM		 1749err_free_cq:
1750 mlx5e_free_cq(cq);
f62b8bb8
AV		 1751
1752 return err;
1753}
1754
1755static void mlx5e_close_cq(struct mlx5e_cq *cq)
1756{
f62b8bb8 1757 mlx5e_destroy_cq(cq);
3b77235b 1758 mlx5e_free_cq(cq);
f62b8bb8
AV		 1759}
1760
231243c8
SM		 1761static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1762{
1e86ace4 1763 return cpumask_first(priv->mdev->priv.irq_info[ix + MLX5_EQ_VEC_COMP_BASE].mask);
231243c8
SM		 1764}
1765
f62b8bb8 1766static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
6a9764ef 1767 struct mlx5e_params *params,
f62b8bb8
AV		 1768 struct mlx5e_channel_param *cparam)
1769{
f62b8bb8
AV		 1770 int err;
1771 int tc;
1772
1773 for (tc = 0; tc < c->num_tc; tc++) {
6a9764ef
SM		 1774 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1775 &cparam->tx_cq, &c->sq[tc].cq);
f62b8bb8
AV		 1776 if (err)
1777 goto err_close_tx_cqs;
f62b8bb8
AV		 1778 }
1779
1780 return 0;
1781
1782err_close_tx_cqs:
1783 for (tc--; tc >= 0; tc--)
1784 mlx5e_close_cq(&c->sq[tc].cq);
1785
1786 return err;
1787}
1788
1789static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1790{
1791 int tc;
1792
1793 for (tc = 0; tc < c->num_tc; tc++)
1794 mlx5e_close_cq(&c->sq[tc].cq);
1795}
1796
1797static int mlx5e_open_sqs(struct mlx5e_channel *c,
6a9764ef 1798 struct mlx5e_params *params,
f62b8bb8
AV		 1799 struct mlx5e_channel_param *cparam)
1800{
05909bab 1801 struct mlx5e_priv *priv = c->priv;
779d986d 1802 int err, tc, max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
f62b8bb8 1803
6a9764ef 1804 for (tc = 0; tc < params->num_tc; tc++) {
05909bab 1805 int txq_ix = c->ix + tc * max_nch;
acc6c595 1806
a43b25da 1807 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
05909bab 1808 params, &cparam->sq, &c->sq[tc], tc);
f62b8bb8
AV		 1809 if (err)
1810 goto err_close_sqs;
1811 }
1812
1813 return 0;
1814
1815err_close_sqs:
1816 for (tc--; tc >= 0; tc--)
31391048 1817 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1818
1819 return err;
1820}
1821
1822static void mlx5e_close_sqs(struct mlx5e_channel *c)
1823{
1824 int tc;
1825
1826 for (tc = 0; tc < c->num_tc; tc++)
31391048 1827 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1828}
1829
507f0c81 1830static int mlx5e_set_sq_maxrate(struct net_device *dev,
31391048 1831 struct mlx5e_txqsq *sq, u32 rate)
507f0c81
YP		 1832{
1833 struct mlx5e_priv *priv = netdev_priv(dev);
1834 struct mlx5_core_dev *mdev = priv->mdev;
33ad9711 1835 struct mlx5e_modify_sq_param msp = {0};
05d3ac97 1836 struct mlx5_rate_limit rl = {0};
507f0c81
YP		 1837 u16 rl_index = 0;
1838 int err;
1839
1840 if (rate == sq->rate_limit)
1841 /* nothing to do */
1842 return 0;
1843
05d3ac97
BW		 1844 if (sq->rate_limit) {
1845 rl.rate = sq->rate_limit;
507f0c81 1846 /* remove current rl index to free space to next ones */
05d3ac97
BW		 1847 mlx5_rl_remove_rate(mdev, &rl);
1848 }
507f0c81
YP		 1849
1850 sq->rate_limit = 0;
1851
1852 if (rate) {
05d3ac97
BW		 1853 rl.rate = rate;
1854 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
507f0c81
YP		 1855 if (err) {
1856 netdev_err(dev, "Failed configuring rate %u: %d\n",
1857 rate, err);
1858 return err;
1859 }
1860 }
1861
33ad9711
SM		 1862 msp.curr_state = MLX5_SQC_STATE_RDY;
1863 msp.next_state = MLX5_SQC_STATE_RDY;
1864 msp.rl_index = rl_index;
1865 msp.rl_update = true;
a43b25da 1866 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
507f0c81
YP		 1867 if (err) {
1868 netdev_err(dev, "Failed configuring rate %u: %d\n",
1869 rate, err);
1870 /* remove the rate from the table */
1871 if (rate)
05d3ac97 1872 mlx5_rl_remove_rate(mdev, &rl);
507f0c81
YP		 1873 return err;
1874 }
1875
1876 sq->rate_limit = rate;
1877 return 0;
1878}
1879
1880static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1881{
1882 struct mlx5e_priv *priv = netdev_priv(dev);
1883 struct mlx5_core_dev *mdev = priv->mdev;
acc6c595 1884 struct mlx5e_txqsq *sq = priv->txq2sq[index];
507f0c81
YP		 1885 int err = 0;
1886
1887 if (!mlx5_rl_is_supported(mdev)) {
1888 netdev_err(dev, "Rate limiting is not supported on this device\n");
1889 return -EINVAL;
1890 }
1891
1892 /* rate is given in Mb/sec, HW config is in Kb/sec */
1893 rate = rate << 10;
1894
1895 /* Check whether rate in valid range, 0 is always valid */
1896 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1897 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1898 return -ERANGE;
1899 }
1900
1901 mutex_lock(&priv->state_lock);
1902 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1903 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1904 if (!err)
1905 priv->tx_rates[index] = rate;
1906 mutex_unlock(&priv->state_lock);
1907
1908 return err;
1909}
1910
f62b8bb8 1911static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
6a9764ef 1912 struct mlx5e_params *params,
f62b8bb8
AV		 1913 struct mlx5e_channel_param *cparam,
1914 struct mlx5e_channel **cp)
1915{
9a317425 1916 struct net_dim_cq_moder icocq_moder = {0, 0};
f62b8bb8 1917 struct net_device *netdev = priv->netdev;
231243c8 1918 int cpu = mlx5e_get_cpu(priv, ix);
f62b8bb8 1919 struct mlx5e_channel *c;
a8c2eb15 1920 unsigned int irq;
f62b8bb8 1921 int err;
a8c2eb15 1922 int eqn;
f62b8bb8 1923
ca11b798 1924 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
f62b8bb8
AV		 1925 if (!c)
1926 return -ENOMEM;
1927
1928 c->priv = priv;
a43b25da
SM		 1929 c->mdev = priv->mdev;
1930 c->tstamp = &priv->tstamp;
f62b8bb8 1931 c->ix = ix;
231243c8 1932 c->cpu = cpu;
f62b8bb8
AV		 1933 c->pdev = &priv->mdev->pdev->dev;
1934 c->netdev = priv->netdev;
b50d292b 1935 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
6a9764ef
SM		 1936 c->num_tc = params->num_tc;
1937 c->xdp = !!params->xdp_prog;
05909bab 1938 c->stats = &priv->channel_stats[ix].ch;
cb3c7fd4 1939
a8c2eb15
TT		 1940 mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1941 c->irq_desc = irq_to_desc(irq);
1942
f62b8bb8
AV		 1943 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1944
6a9764ef 1945 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
f62b8bb8
AV		 1946 if (err)
1947 goto err_napi_del;
1948
6a9764ef 1949 err = mlx5e_open_tx_cqs(c, params, cparam);
d3c9bc27
TT		 1950 if (err)
1951 goto err_close_icosq_cq;
1952
58b99ee3 1953 err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
f62b8bb8
AV		 1954 if (err)
1955 goto err_close_tx_cqs;
f62b8bb8 1956
58b99ee3
TT		 1957 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1958 if (err)
1959 goto err_close_xdp_tx_cqs;
1960
d7a0ecab 1961 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
6a9764ef
SM		 1962 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1963 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
d7a0ecab
SM		 1964 if (err)
1965 goto err_close_rx_cq;
1966
f62b8bb8
AV		 1967 napi_enable(&c->napi);
1968
6a9764ef 1969 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1970 if (err)
1971 goto err_disable_napi;
1972
6a9764ef 1973 err = mlx5e_open_sqs(c, params, cparam);
d3c9bc27
TT		 1974 if (err)
1975 goto err_close_icosq;
1976
58b99ee3 1977 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
d7a0ecab
SM		 1978 if (err)
1979 goto err_close_sqs;
b5503b99 1980
6a9764ef 1981 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
f62b8bb8 1982 if (err)
b5503b99 1983 goto err_close_xdp_sq;
f62b8bb8 1984
58b99ee3
TT		 1985 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
1986 if (err)
1987 goto err_close_rq;
1988
f62b8bb8
AV		 1989 *cp = c;
1990
1991 return 0;
58b99ee3
TT		 1992
1993err_close_rq:
1994 mlx5e_close_rq(&c->rq);
1995
b5503b99 1996err_close_xdp_sq:
d7a0ecab 1997 if (c->xdp)
31391048 1998 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8
AV		 1999
2000err_close_sqs:
2001 mlx5e_close_sqs(c);
2002
d3c9bc27 2003err_close_icosq:
31391048 2004 mlx5e_close_icosq(&c->icosq);
d3c9bc27 2005
f62b8bb8
AV		 2006err_disable_napi:
2007 napi_disable(&c->napi);
d7a0ecab 2008 if (c->xdp)
31871f87 2009 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 2010
2011err_close_rx_cq:
f62b8bb8
AV		 2012 mlx5e_close_cq(&c->rq.cq);
2013
58b99ee3
TT		 2014err_close_xdp_tx_cqs:
2015 mlx5e_close_cq(&c->xdpsq.cq);
2016
f62b8bb8
AV		 2017err_close_tx_cqs:
2018 mlx5e_close_tx_cqs(c);
2019
d3c9bc27
TT		 2020err_close_icosq_cq:
2021 mlx5e_close_cq(&c->icosq.cq);
2022
f62b8bb8
AV		 2023err_napi_del:
2024 netif_napi_del(&c->napi);
ca11b798 2025 kvfree(c);
f62b8bb8
AV		 2026
2027 return err;
2028}
2029
acc6c595
SM		 2030static void mlx5e_activate_channel(struct mlx5e_channel *c)
2031{
2032 int tc;
2033
2034 for (tc = 0; tc < c->num_tc; tc++)
2035 mlx5e_activate_txqsq(&c->sq[tc]);
2036 mlx5e_activate_rq(&c->rq);
231243c8 2037 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
acc6c595
SM		 2038}
2039
2040static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2041{
2042 int tc;
2043
2044 mlx5e_deactivate_rq(&c->rq);
2045 for (tc = 0; tc < c->num_tc; tc++)
2046 mlx5e_deactivate_txqsq(&c->sq[tc]);
2047}
2048
f62b8bb8
AV		 2049static void mlx5e_close_channel(struct mlx5e_channel *c)
2050{
58b99ee3 2051 mlx5e_close_xdpsq(&c->xdpsq);
f62b8bb8 2052 mlx5e_close_rq(&c->rq);
b5503b99 2053 if (c->xdp)
31391048 2054 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8 2055 mlx5e_close_sqs(c);
31391048 2056 mlx5e_close_icosq(&c->icosq);
f62b8bb8 2057 napi_disable(&c->napi);
b5503b99 2058 if (c->xdp)
31871f87 2059 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8 2060 mlx5e_close_cq(&c->rq.cq);
58b99ee3 2061 mlx5e_close_cq(&c->xdpsq.cq);
f62b8bb8 2062 mlx5e_close_tx_cqs(c);
d3c9bc27 2063 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 2064 netif_napi_del(&c->napi);
7ae92ae5 2065
ca11b798 2066 kvfree(c);
f62b8bb8
AV		 2067}
2068
069d1146
TT		 2069#define DEFAULT_FRAG_SIZE (2048)
2070
2071static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2072 struct mlx5e_params *params,
2073 struct mlx5e_rq_frags_info *info)
2074{
2075 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2076 int frag_size_max = DEFAULT_FRAG_SIZE;
2077 u32 buf_size = 0;
2078 int i;
2079
2080#ifdef CONFIG_MLX5_EN_IPSEC
2081 if (MLX5_IPSEC_DEV(mdev))
2082 byte_count += MLX5E_METADATA_ETHER_LEN;
2083#endif
2084
2085 if (mlx5e_rx_is_linear_skb(mdev, params)) {
2086 int frag_stride;
2087
2088 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2089 frag_stride = roundup_pow_of_two(frag_stride);
2090
2091 info->arr[0].frag_size = byte_count;
2092 info->arr[0].frag_stride = frag_stride;
2093 info->num_frags = 1;
2094 info->wqe_bulk = PAGE_SIZE / frag_stride;
2095 goto out;
2096 }
2097
2098 if (byte_count > PAGE_SIZE +
2099 (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2100 frag_size_max = PAGE_SIZE;
2101
2102 i = 0;
2103 while (buf_size < byte_count) {
2104 int frag_size = byte_count - buf_size;
2105
2106 if (i < MLX5E_MAX_RX_FRAGS - 1)
2107 frag_size = min(frag_size, frag_size_max);
2108
2109 info->arr[i].frag_size = frag_size;
2110 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2111
2112 buf_size += frag_size;
2113 i++;
2114 }
2115 info->num_frags = i;
2116 /* number of different wqes sharing a page */
2117 info->wqe_bulk = 1 + (info->num_frags % 2);
2118
2119out:
2120 info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2121 info->log_num_frags = order_base_2(info->num_frags);
2122}
2123
99cbfa93
TT		 2124static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2125{
2126 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2127
2128 switch (wq_type) {
2129 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2130 sz += sizeof(struct mlx5e_rx_wqe_ll);
2131 break;
2132 default: /* MLX5_WQ_TYPE_CYCLIC */
2133 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2134 }
2135
2136 return order_base_2(sz);
2137}
2138
f62b8bb8 2139static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
6a9764ef 2140 struct mlx5e_params *params,
f62b8bb8
AV		 2141 struct mlx5e_rq_param *param)
2142{
f1e4fc9b 2143 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2144 void *rqc = param->rqc;
2145 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
99cbfa93 2146 int ndsegs = 1;
f62b8bb8 2147
6a9764ef 2148 switch (params->rq_wq_type) {
461017cb 2149 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f1e4fc9b 2150 MLX5_SET(wq, wq, log_wqe_num_of_strides,
619a8f2a
TT		 2151 mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2152 MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
f1e4fc9b 2153 MLX5_SET(wq, wq, log_wqe_stride_size,
619a8f2a
TT		 2154 mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2155 MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
73281b78 2156 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
461017cb 2157 break;
99cbfa93 2158 default: /* MLX5_WQ_TYPE_CYCLIC */
73281b78 2159 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
069d1146
TT		 2160 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2161 ndsegs = param->frags_info.num_frags;
461017cb
TT		 2162 }
2163
99cbfa93 2164 MLX5_SET(wq, wq, wq_type, params->rq_wq_type);
f62b8bb8 2165 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
99cbfa93
TT		 2166 MLX5_SET(wq, wq, log_wq_stride,
2167 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
f1e4fc9b 2168 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn);
593cf338 2169 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
6a9764ef 2170 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
102722fc 2171 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
f62b8bb8 2172
f1e4fc9b 2173 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
f62b8bb8
AV		 2174}
2175
7cbaf9a3 2176static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2f0db879 2177 struct mlx5e_rq_param *param)
556dd1b9 2178{
7cbaf9a3 2179 struct mlx5_core_dev *mdev = priv->mdev;
556dd1b9
TT		 2180 void *rqc = param->rqc;
2181 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2182
99cbfa93
TT		 2183 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2184 MLX5_SET(wq, wq, log_wq_stride,
2185 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
7cbaf9a3 2186 MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2f0db879
GP		 2187
2188 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
556dd1b9
TT		 2189}
2190
d3c9bc27
TT		 2191static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2192 struct mlx5e_sq_param *param)
f62b8bb8
AV		 2193{
2194 void *sqc = param->sqc;
2195 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2196
f62b8bb8 2197 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 2198 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 2199
311c7c71 2200 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 2201}
2202
2203static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
6a9764ef 2204 struct mlx5e_params *params,
d3c9bc27
TT		 2205 struct mlx5e_sq_param *param)
2206{
2207 void *sqc = param->sqc;
2208 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2209
2210 mlx5e_build_sq_param_common(priv, param);
6a9764ef 2211 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2ac9cfe7 2212 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
f62b8bb8
AV		 2213}
2214
2215static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2216 struct mlx5e_cq_param *param)
2217{
2218 void *cqc = param->cqc;
2219
30aa60b3 2220 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 2221}
2222
2223static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
6a9764ef 2224 struct mlx5e_params *params,
f62b8bb8
AV		 2225 struct mlx5e_cq_param *param)
2226{
73281b78 2227 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8 2228 void *cqc = param->cqc;
461017cb 2229 u8 log_cq_size;
f62b8bb8 2230
6a9764ef 2231 switch (params->rq_wq_type) {
461017cb 2232 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
73281b78
TT		 2233 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2234 mlx5e_mpwqe_get_log_num_strides(mdev, params);
461017cb 2235 break;
99cbfa93 2236 default: /* MLX5_WQ_TYPE_CYCLIC */
73281b78 2237 log_cq_size = params->log_rq_mtu_frames;
461017cb
TT		 2238 }
2239
2240 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
6a9764ef 2241 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 2242 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2243 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2244 }
f62b8bb8
AV		 2245
2246 mlx5e_build_common_cq_param(priv, param);
0088cbbc 2247 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 2248}
2249
2250static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
6a9764ef 2251 struct mlx5e_params *params,
f62b8bb8
AV		 2252 struct mlx5e_cq_param *param)
2253{
2254 void *cqc = param->cqc;
2255
6a9764ef 2256 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
f62b8bb8
AV		 2257
2258 mlx5e_build_common_cq_param(priv, param);
0088cbbc 2259 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 2260}
2261
d3c9bc27 2262static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 2263 u8 log_wq_size,
2264 struct mlx5e_cq_param *param)
d3c9bc27
TT		 2265{
2266 void *cqc = param->cqc;
2267
2268 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2269
2270 mlx5e_build_common_cq_param(priv, param);
9908aa29 2271
9a317425 2272 param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 2273}
2274
2275static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 2276 u8 log_wq_size,
2277 struct mlx5e_sq_param *param)
d3c9bc27
TT		 2278{
2279 void *sqc = param->sqc;
2280 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2281
2282 mlx5e_build_sq_param_common(priv, param);
2283
2284 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 2285 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 2286}
2287
b5503b99 2288static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
6a9764ef 2289 struct mlx5e_params *params,
b5503b99
SM		 2290 struct mlx5e_sq_param *param)
2291{
2292 void *sqc = param->sqc;
2293 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2294
2295 mlx5e_build_sq_param_common(priv, param);
6a9764ef 2296 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
b5503b99
SM		 2297}
2298
6a9764ef
SM		 2299static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2300 struct mlx5e_params *params,
2301 struct mlx5e_channel_param *cparam)
f62b8bb8 2302{
bc77b240 2303 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 2304
6a9764ef
SM		 2305 mlx5e_build_rq_param(priv, params, &cparam->rq);
2306 mlx5e_build_sq_param(priv, params, &cparam->sq);
2307 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2308 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2309 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2310 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2311 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
f62b8bb8
AV		 2312}
2313
55c2503d
SM		 2314int mlx5e_open_channels(struct mlx5e_priv *priv,
2315 struct mlx5e_channels *chs)
f62b8bb8 2316{
6b87663f 2317 struct mlx5e_channel_param *cparam;
03289b88 2318 int err = -ENOMEM;
f62b8bb8 2319 int i;
f62b8bb8 2320
6a9764ef 2321 chs->num = chs->params.num_channels;
03289b88 2322
ff9c852f 2323 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
ca11b798 2324 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
acc6c595
SM		 2325 if (!chs->c || !cparam)
2326 goto err_free;
f62b8bb8 2327
6a9764ef 2328 mlx5e_build_channel_param(priv, &chs->params, cparam);
ff9c852f 2329 for (i = 0; i < chs->num; i++) {
6a9764ef 2330 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
f62b8bb8
AV		 2331 if (err)
2332 goto err_close_channels;
2333 }
2334
ca11b798 2335 kvfree(cparam);
f62b8bb8
AV		 2336 return 0;
2337
2338err_close_channels:
2339 for (i--; i >= 0; i--)
ff9c852f 2340 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2341
acc6c595 2342err_free:
ff9c852f 2343 kfree(chs->c);
ca11b798 2344 kvfree(cparam);
ff9c852f 2345 chs->num = 0;
f62b8bb8
AV		 2346 return err;
2347}
2348
acc6c595 2349static void mlx5e_activate_channels(struct mlx5e_channels *chs)
f62b8bb8
AV		 2350{
2351 int i;
2352
acc6c595
SM		 2353 for (i = 0; i < chs->num; i++)
2354 mlx5e_activate_channel(chs->c[i]);
2355}
2356
2357static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2358{
2359 int err = 0;
2360 int i;
2361
1e7477ae
EBE		 2362 for (i = 0; i < chs->num; i++)
2363 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2364 err ? 0 : 20000);
acc6c595 2365
1e7477ae 2366 return err ? -ETIMEDOUT : 0;
acc6c595
SM		 2367}
2368
2369static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2370{
2371 int i;
2372
2373 for (i = 0; i < chs->num; i++)
2374 mlx5e_deactivate_channel(chs->c[i]);
2375}
2376
55c2503d 2377void mlx5e_close_channels(struct mlx5e_channels *chs)
acc6c595
SM		 2378{
2379 int i;
c3b7c5c9 2380
ff9c852f
SM		 2381 for (i = 0; i < chs->num; i++)
2382 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2383
ff9c852f
SM		 2384 kfree(chs->c);
2385 chs->num = 0;
f62b8bb8
AV		 2386}
2387
a5f97fee
SM		 2388static int
2389mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 2390{
2391 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2392 void *rqtc;
2393 int inlen;
2394 int err;
1da36696 2395 u32 *in;
a5f97fee 2396 int i;
f62b8bb8 2397
f62b8bb8 2398 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2399 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2400 if (!in)
2401 return -ENOMEM;
2402
2403 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2404
2405 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2406 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2407
a5f97fee
SM		 2408 for (i = 0; i < sz; i++)
2409 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2be6967c 2410
398f3351
HHZ		 2411 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2412 if (!err)
2413 rqt->enabled = true;
f62b8bb8
AV		 2414
2415 kvfree(in);
1da36696
TT		 2416 return err;
2417}
2418
cb67b832 2419void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2420{
398f3351
HHZ		 2421 rqt->enabled = false;
2422 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2423}
2424
8f493ffd 2425int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2426{
2427 struct mlx5e_rqt *rqt = &priv->indir_rqt;
8f493ffd 2428 int err;
6bfd390b 2429
8f493ffd
SM		 2430 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2431 if (err)
2432 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2433 return err;
6bfd390b
HHZ		 2434}
2435
cb67b832 2436int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2437{
398f3351 2438 struct mlx5e_rqt *rqt;
1da36696
TT		 2439 int err;
2440 int ix;
2441
779d986d 2442 for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
398f3351 2443 rqt = &priv->direct_tir[ix].rqt;
a5f97fee 2444 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
1da36696
TT		 2445 if (err)
2446 goto err_destroy_rqts;
2447 }
2448
2449 return 0;
2450
2451err_destroy_rqts:
8f493ffd 2452 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
1da36696 2453 for (ix--; ix >= 0; ix--)
398f3351 2454 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2455
f62b8bb8
AV		 2456 return err;
2457}
2458
8f493ffd
SM		 2459void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2460{
2461 int i;
2462
779d986d 2463 for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++)
8f493ffd
SM		 2464 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2465}
2466
a5f97fee
SM		 2467static int mlx5e_rx_hash_fn(int hfunc)
2468{
2469 return (hfunc == ETH_RSS_HASH_TOP) ?
2470 MLX5_RX_HASH_FN_TOEPLITZ :
2471 MLX5_RX_HASH_FN_INVERTED_XOR8;
2472}
2473
3f6d08d1 2474int mlx5e_bits_invert(unsigned long a, int size)
a5f97fee
SM		 2475{
2476 int inv = 0;
2477 int i;
2478
2479 for (i = 0; i < size; i++)
2480 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2481
2482 return inv;
2483}
2484
2485static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2486 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2487{
2488 int i;
2489
2490 for (i = 0; i < sz; i++) {
2491 u32 rqn;
2492
2493 if (rrp.is_rss) {
2494 int ix = i;
2495
2496 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2497 ix = mlx5e_bits_invert(i, ilog2(sz));
2498
6a9764ef 2499 ix = priv->channels.params.indirection_rqt[ix];
a5f97fee
SM		 2500 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2501 } else {
2502 rqn = rrp.rqn;
2503 }
2504 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2505 }
2506}
2507
2508int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2509 struct mlx5e_redirect_rqt_param rrp)
5c50368f
AS		 2510{
2511 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2512 void *rqtc;
2513 int inlen;
1da36696 2514 u32 *in;
5c50368f
AS		 2515 int err;
2516
5c50368f 2517 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2518 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2519 if (!in)
2520 return -ENOMEM;
2521
2522 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2523
2524 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5c50368f 2525 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
a5f97fee 2526 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
1da36696 2527 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2528
2529 kvfree(in);
5c50368f
AS		 2530 return err;
2531}
2532
a5f97fee
SM		 2533static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2534 struct mlx5e_redirect_rqt_param rrp)
2535{
2536 if (!rrp.is_rss)
2537 return rrp.rqn;
2538
2539 if (ix >= rrp.rss.channels->num)
2540 return priv->drop_rq.rqn;
2541
2542 return rrp.rss.channels->c[ix]->rq.rqn;
2543}
2544
2545static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2546 struct mlx5e_redirect_rqt_param rrp)
40ab6a6e 2547{
1da36696
TT		 2548 u32 rqtn;
2549 int ix;
2550
398f3351 2551 if (priv->indir_rqt.enabled) {
a5f97fee 2552 /* RSS RQ table */
398f3351 2553 rqtn = priv->indir_rqt.rqtn;
a5f97fee 2554 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
398f3351
HHZ		 2555 }
2556
779d986d 2557 for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
a5f97fee
SM		 2558 struct mlx5e_redirect_rqt_param direct_rrp = {
2559 .is_rss = false,
95632791
AM		 2560 {
2561 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2562 },
a5f97fee
SM		 2563 };
2564
2565 /* Direct RQ Tables */
398f3351
HHZ		 2566 if (!priv->direct_tir[ix].rqt.enabled)
2567 continue;
a5f97fee 2568
398f3351 2569 rqtn = priv->direct_tir[ix].rqt.rqtn;
a5f97fee 2570 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
1da36696 2571 }
40ab6a6e
AS		 2572}
2573
a5f97fee
SM		 2574static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2575 struct mlx5e_channels *chs)
2576{
2577 struct mlx5e_redirect_rqt_param rrp = {
2578 .is_rss = true,
95632791
AM		 2579 {
2580 .rss = {
2581 .channels = chs,
2582 .hfunc = chs->params.rss_hfunc,
2583 }
2584 },
a5f97fee
SM		 2585 };
2586
2587 mlx5e_redirect_rqts(priv, rrp);
2588}
2589
2590static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2591{
2592 struct mlx5e_redirect_rqt_param drop_rrp = {
2593 .is_rss = false,
95632791
AM		 2594 {
2595 .rqn = priv->drop_rq.rqn,
2596 },
a5f97fee
SM		 2597 };
2598
2599 mlx5e_redirect_rqts(priv, drop_rrp);
2600}
2601
6a9764ef 2602static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
5c50368f 2603{
6a9764ef 2604 if (!params->lro_en)
5c50368f
AS		 2605 return;
2606
2607#define ROUGH_MAX_L2_L3_HDR_SZ 256
2608
2609 MLX5_SET(tirc, tirc, lro_enable_mask,
2610 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2611 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2612 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
6a9764ef
SM		 2613 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2614 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
5c50368f
AS		 2615}
2616
6a9764ef
SM		 2617void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2618 enum mlx5e_traffic_types tt,
7b3722fa 2619 void *tirc, bool inner)
bdfc028d 2620{
7b3722fa
GP		 2621 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2622 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
a100ff3e
GP		 2623
2624#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2625 MLX5_HASH_FIELD_SEL_DST_IP)
2626
2627#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2628 MLX5_HASH_FIELD_SEL_DST_IP |\
2629 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2630 MLX5_HASH_FIELD_SEL_L4_DPORT)
2631
2632#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2633 MLX5_HASH_FIELD_SEL_DST_IP |\
2634 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2635
6a9764ef
SM		 2636 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2637 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
bdfc028d
TT		 2638 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2639 rx_hash_toeplitz_key);
2640 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2641 rx_hash_toeplitz_key);
2642
2643 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
6a9764ef 2644 memcpy(rss_key, params->toeplitz_hash_key, len);
bdfc028d 2645 }
a100ff3e
GP		 2646
2647 switch (tt) {
2648 case MLX5E_TT_IPV4_TCP:
2649 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2650 MLX5_L3_PROT_TYPE_IPV4);
2651 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2652 MLX5_L4_PROT_TYPE_TCP);
2653 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2654 MLX5_HASH_IP_L4PORTS);
2655 break;
2656
2657 case MLX5E_TT_IPV6_TCP:
2658 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2659 MLX5_L3_PROT_TYPE_IPV6);
2660 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2661 MLX5_L4_PROT_TYPE_TCP);
2662 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2663 MLX5_HASH_IP_L4PORTS);
2664 break;
2665
2666 case MLX5E_TT_IPV4_UDP:
2667 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2668 MLX5_L3_PROT_TYPE_IPV4);
2669 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2670 MLX5_L4_PROT_TYPE_UDP);
2671 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2672 MLX5_HASH_IP_L4PORTS);
2673 break;
2674
2675 case MLX5E_TT_IPV6_UDP:
2676 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2677 MLX5_L3_PROT_TYPE_IPV6);
2678 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2679 MLX5_L4_PROT_TYPE_UDP);
2680 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2681 MLX5_HASH_IP_L4PORTS);
2682 break;
2683
2684 case MLX5E_TT_IPV4_IPSEC_AH:
2685 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2686 MLX5_L3_PROT_TYPE_IPV4);
2687 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2688 MLX5_HASH_IP_IPSEC_SPI);
2689 break;
2690
2691 case MLX5E_TT_IPV6_IPSEC_AH:
2692 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2693 MLX5_L3_PROT_TYPE_IPV6);
2694 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2695 MLX5_HASH_IP_IPSEC_SPI);
2696 break;
2697
2698 case MLX5E_TT_IPV4_IPSEC_ESP:
2699 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2700 MLX5_L3_PROT_TYPE_IPV4);
2701 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2702 MLX5_HASH_IP_IPSEC_SPI);
2703 break;
2704
2705 case MLX5E_TT_IPV6_IPSEC_ESP:
2706 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2707 MLX5_L3_PROT_TYPE_IPV6);
2708 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2709 MLX5_HASH_IP_IPSEC_SPI);
2710 break;
2711
2712 case MLX5E_TT_IPV4:
2713 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2714 MLX5_L3_PROT_TYPE_IPV4);
2715 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2716 MLX5_HASH_IP);
2717 break;
2718
2719 case MLX5E_TT_IPV6:
2720 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2721 MLX5_L3_PROT_TYPE_IPV6);
2722 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2723 MLX5_HASH_IP);
2724 break;
2725 default:
2726 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2727 }
bdfc028d
TT		 2728}
2729
ab0394fe 2730static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2731{
2732 struct mlx5_core_dev *mdev = priv->mdev;
2733
2734 void *in;
2735 void *tirc;
2736 int inlen;
2737 int err;
ab0394fe 2738 int tt;
1da36696 2739 int ix;
5c50368f
AS		 2740
2741 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1b9a07ee 2742 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2743 if (!in)
2744 return -ENOMEM;
2745
2746 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2747 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2748
6a9764ef 2749 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
5c50368f 2750
1da36696 2751 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2752 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2753 inlen);
ab0394fe 2754 if (err)
1da36696 2755 goto free_in;
ab0394fe 2756 }
5c50368f 2757
779d986d 2758 for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
1da36696
TT		 2759 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2760 in, inlen);
2761 if (err)
2762 goto free_in;
2763 }
2764
2765free_in:
5c50368f
AS		 2766 kvfree(in);
2767
2768 return err;
2769}
2770
7b3722fa
GP		 2771static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2772 enum mlx5e_traffic_types tt,
2773 u32 *tirc)
2774{
2775 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2776
2777 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2778
2779 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2780 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2781 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2782
2783 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2784}
2785
472a1e44
TT		 2786static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2787 struct mlx5e_params *params, u16 mtu)
40ab6a6e 2788{
472a1e44 2789 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
40ab6a6e
AS		 2790 int err;
2791
cd255eff 2792 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2793 if (err)
2794 return err;
2795
cd255eff
SM		 2796 /* Update vport context MTU */
2797 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2798 return 0;
2799}
40ab6a6e 2800
472a1e44
TT		 2801static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2802 struct mlx5e_params *params, u16 *mtu)
cd255eff 2803{
cd255eff
SM		 2804 u16 hw_mtu = 0;
2805 int err;
40ab6a6e 2806
cd255eff
SM		 2807 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2808 if (err || !hw_mtu) /* fallback to port oper mtu */
2809 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2810
472a1e44 2811 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
cd255eff
SM		 2812}
2813
2e20a151 2814static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
cd255eff 2815{
472a1e44 2816 struct mlx5e_params *params = &priv->channels.params;
2e20a151 2817 struct net_device *netdev = priv->netdev;
472a1e44 2818 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff
SM		 2819 u16 mtu;
2820 int err;
2821
472a1e44 2822 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
cd255eff
SM		 2823 if (err)
2824 return err;
40ab6a6e 2825
472a1e44
TT		 2826 mlx5e_query_mtu(mdev, params, &mtu);
2827 if (mtu != params->sw_mtu)
cd255eff 2828 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
472a1e44 2829 __func__, mtu, params->sw_mtu);
40ab6a6e 2830
472a1e44 2831 params->sw_mtu = mtu;
40ab6a6e
AS		 2832 return 0;
2833}
2834
08fb1dac
SM		 2835static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2836{
2837 struct mlx5e_priv *priv = netdev_priv(netdev);
6a9764ef
SM		 2838 int nch = priv->channels.params.num_channels;
2839 int ntc = priv->channels.params.num_tc;
08fb1dac
SM		 2840 int tc;
2841
2842 netdev_reset_tc(netdev);
2843
2844 if (ntc == 1)
2845 return;
2846
2847 netdev_set_num_tc(netdev, ntc);
2848
7ccdd084
RS		 2849 /* Map netdev TCs to offset 0
2850 * We have our own UP to TXQ mapping for QoS
2851 */
08fb1dac 2852 for (tc = 0; tc < ntc; tc++)
7ccdd084 2853 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2854}
2855
8bfaf07f 2856static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
acc6c595 2857{
779d986d 2858 int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
acc6c595
SM		 2859 int i, tc;
2860
8bfaf07f 2861 for (i = 0; i < max_nch; i++)
acc6c595 2862 for (tc = 0; tc < priv->profile->max_tc; tc++)
8bfaf07f
EBE		 2863 priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2864}
2865
2866static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2867{
2868 struct mlx5e_channel *c;
2869 struct mlx5e_txqsq *sq;
2870 int i, tc;
acc6c595
SM		 2871
2872 for (i = 0; i < priv->channels.num; i++) {
2873 c = priv->channels.c[i];
2874 for (tc = 0; tc < c->num_tc; tc++) {
2875 sq = &c->sq[tc];
2876 priv->txq2sq[sq->txq_ix] = sq;
2877 }
2878 }
2879}
2880
603f4a45 2881void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2882{
9008ae07
SM		 2883 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2884 struct net_device *netdev = priv->netdev;
2885
2886 mlx5e_netdev_set_tcs(netdev);
053ee0a7
TR		 2887 netif_set_real_num_tx_queues(netdev, num_txqs);
2888 netif_set_real_num_rx_queues(netdev, priv->channels.num);
9008ae07 2889
8bfaf07f 2890 mlx5e_build_tx2sq_maps(priv);
acc6c595
SM		 2891 mlx5e_activate_channels(&priv->channels);
2892 netif_tx_start_all_queues(priv->netdev);
9008ae07 2893
733d3e54 2894 if (MLX5_ESWITCH_MANAGER(priv->mdev))
9008ae07
SM		 2895 mlx5e_add_sqs_fwd_rules(priv);
2896
acc6c595 2897 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
9008ae07 2898 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
acc6c595
SM		 2899}
2900
603f4a45 2901void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2902{
9008ae07
SM		 2903 mlx5e_redirect_rqts_to_drop(priv);
2904
733d3e54 2905 if (MLX5_ESWITCH_MANAGER(priv->mdev))
9008ae07
SM		 2906 mlx5e_remove_sqs_fwd_rules(priv);
2907
acc6c595
SM		 2908 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2909 * polling for inactive tx queues.
2910 */
2911 netif_tx_stop_all_queues(priv->netdev);
2912 netif_tx_disable(priv->netdev);
2913 mlx5e_deactivate_channels(&priv->channels);
2914}
2915
55c2503d 2916void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2e20a151
SM		 2917 struct mlx5e_channels *new_chs,
2918 mlx5e_fp_hw_modify hw_modify)
55c2503d
SM		 2919{
2920 struct net_device *netdev = priv->netdev;
2921 int new_num_txqs;
7ca42c80 2922 int carrier_ok;
55c2503d
SM		 2923 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2924
7ca42c80 2925 carrier_ok = netif_carrier_ok(netdev);
55c2503d
SM		 2926 netif_carrier_off(netdev);
2927
2928 if (new_num_txqs < netdev->real_num_tx_queues)
2929 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2930
2931 mlx5e_deactivate_priv_channels(priv);
2932 mlx5e_close_channels(&priv->channels);
2933
2934 priv->channels = *new_chs;
2935
2e20a151
SM		 2936 /* New channels are ready to roll, modify HW settings if needed */
2937 if (hw_modify)
2938 hw_modify(priv);
2939
55c2503d
SM		 2940 mlx5e_refresh_tirs(priv, false);
2941 mlx5e_activate_priv_channels(priv);
2942
7ca42c80
ES		 2943 /* return carrier back if needed */
2944 if (carrier_ok)
2945 netif_carrier_on(netdev);
55c2503d
SM		 2946}
2947
237f258c 2948void mlx5e_timestamp_init(struct mlx5e_priv *priv)
7c39afb3
FD		 2949{
2950 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2951 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2952}
2953
40ab6a6e
AS		 2954int mlx5e_open_locked(struct net_device *netdev)
2955{
2956 struct mlx5e_priv *priv = netdev_priv(netdev);
40ab6a6e
AS		 2957 int err;
2958
2959 set_bit(MLX5E_STATE_OPENED, &priv->state);
2960
ff9c852f 2961 err = mlx5e_open_channels(priv, &priv->channels);
acc6c595 2962 if (err)
343b29f3 2963 goto err_clear_state_opened_flag;
40ab6a6e 2964
b676f653 2965 mlx5e_refresh_tirs(priv, false);
acc6c595 2966 mlx5e_activate_priv_channels(priv);
7ca42c80
ES		 2967 if (priv->profile->update_carrier)
2968 priv->profile->update_carrier(priv);
be4891af 2969
cdeef2b1 2970 mlx5e_queue_update_stats(priv);
9b37b07f 2971 return 0;
343b29f3
AS		 2972
2973err_clear_state_opened_flag:
2974 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2975 return err;
40ab6a6e
AS		 2976}
2977
cb67b832 2978int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2979{
2980 struct mlx5e_priv *priv = netdev_priv(netdev);
2981 int err;
2982
2983 mutex_lock(&priv->state_lock);
2984 err = mlx5e_open_locked(netdev);
63bfd399
EBE		 2985 if (!err)
2986 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
40ab6a6e
AS		 2987 mutex_unlock(&priv->state_lock);
2988
358aa5ce 2989 if (mlx5_vxlan_allowed(priv->mdev->vxlan))
a117f73d
SK		 2990 udp_tunnel_get_rx_info(netdev);
2991
40ab6a6e
AS		 2992 return err;
2993}
2994
2995int mlx5e_close_locked(struct net_device *netdev)
2996{
2997 struct mlx5e_priv *priv = netdev_priv(netdev);
2998
a1985740
AS		 2999 /* May already be CLOSED in case a previous configuration operation
3000 * (e.g RX/TX queue size change) that involves close&open failed.
3001 */
3002 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3003 return 0;
3004
40ab6a6e
AS		 3005 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3006
40ab6a6e 3007 netif_carrier_off(priv->netdev);
acc6c595
SM		 3008 mlx5e_deactivate_priv_channels(priv);
3009 mlx5e_close_channels(&priv->channels);
40ab6a6e
AS		 3010
3011 return 0;
3012}
3013
cb67b832 3014int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 3015{
3016 struct mlx5e_priv *priv = netdev_priv(netdev);
3017 int err;
3018
26e59d80
MHY		 3019 if (!netif_device_present(netdev))
3020 return -ENODEV;
3021
40ab6a6e 3022 mutex_lock(&priv->state_lock);
63bfd399 3023 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
40ab6a6e
AS		 3024 err = mlx5e_close_locked(netdev);
3025 mutex_unlock(&priv->state_lock);
3026
3027 return err;
3028}
3029
a43b25da 3030static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3b77235b
SM		 3031 struct mlx5e_rq *rq,
3032 struct mlx5e_rq_param *param)
40ab6a6e 3033{
40ab6a6e
AS		 3034 void *rqc = param->rqc;
3035 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3036 int err;
3037
3038 param->wq.db_numa_node = param->wq.buf_numa_node;
3039
99cbfa93
TT		 3040 err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3041 &rq->wq_ctrl);
40ab6a6e
AS		 3042 if (err)
3043 return err;
3044
0ddf5432
JDB		 3045 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3046 xdp_rxq_info_unused(&rq->xdp_rxq);
3047
a43b25da 3048 rq->mdev = mdev;
40ab6a6e
AS		 3049
3050 return 0;
3051}
3052
a43b25da 3053static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3b77235b
SM		 3054 struct mlx5e_cq *cq,
3055 struct mlx5e_cq_param *param)
40ab6a6e 3056{
2f0db879
GP		 3057 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3058 param->wq.db_numa_node = dev_to_node(&mdev->pdev->dev);
3059
95b6c6a5 3060 return mlx5e_alloc_cq_common(mdev, param, cq);
40ab6a6e
AS		 3061}
3062
1462e48d
RD		 3063int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3064 struct mlx5e_rq *drop_rq)
40ab6a6e 3065{
7cbaf9a3 3066 struct mlx5_core_dev *mdev = priv->mdev;
a43b25da
SM		 3067 struct mlx5e_cq_param cq_param = {};
3068 struct mlx5e_rq_param rq_param = {};
3069 struct mlx5e_cq *cq = &drop_rq->cq;
40ab6a6e
AS		 3070 int err;
3071
7cbaf9a3 3072 mlx5e_build_drop_rq_param(priv, &rq_param);
40ab6a6e 3073
a43b25da 3074 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
40ab6a6e
AS		 3075 if (err)
3076 return err;
3077
3b77235b 3078 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 3079 if (err)
3b77235b 3080 goto err_free_cq;
40ab6a6e 3081
a43b25da 3082 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
40ab6a6e 3083 if (err)
3b77235b 3084 goto err_destroy_cq;
40ab6a6e 3085
a43b25da 3086 err = mlx5e_create_rq(drop_rq, &rq_param);
40ab6a6e 3087 if (err)
3b77235b 3088 goto err_free_rq;
40ab6a6e 3089
7cbaf9a3
MS		 3090 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3091 if (err)
3092 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3093
40ab6a6e
AS		 3094 return 0;
3095
3b77235b 3096err_free_rq:
a43b25da 3097 mlx5e_free_rq(drop_rq);
40ab6a6e
AS		 3098
3099err_destroy_cq:
a43b25da 3100 mlx5e_destroy_cq(cq);
40ab6a6e 3101
3b77235b 3102err_free_cq:
a43b25da 3103 mlx5e_free_cq(cq);
3b77235b 3104
40ab6a6e
AS		 3105 return err;
3106}
3107
1462e48d 3108void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
40ab6a6e 3109{
a43b25da
SM		 3110 mlx5e_destroy_rq(drop_rq);
3111 mlx5e_free_rq(drop_rq);
3112 mlx5e_destroy_cq(&drop_rq->cq);
3113 mlx5e_free_cq(&drop_rq->cq);
40ab6a6e
AS		 3114}
3115
5426a0b2
SM		 3116int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3117 u32 underlay_qpn, u32 *tisn)
40ab6a6e 3118{
c4f287c4 3119 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 3120 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3121
08fb1dac 3122 MLX5_SET(tisc, tisc, prio, tc << 1);
5426a0b2 3123 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
b50d292b 3124 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 3125
3126 if (mlx5_lag_is_lacp_owner(mdev))
3127 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3128
5426a0b2 3129 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
40ab6a6e
AS		 3130}
3131
5426a0b2 3132void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
40ab6a6e 3133{
5426a0b2 3134 mlx5_core_destroy_tis(mdev, tisn);
40ab6a6e
AS		 3135}
3136
cb67b832 3137int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 3138{
3139 int err;
3140 int tc;
3141
6bfd390b 3142 for (tc = 0; tc < priv->profile->max_tc; tc++) {
5426a0b2 3143 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
40ab6a6e
AS		 3144 if (err)
3145 goto err_close_tises;
3146 }
3147
3148 return 0;
3149
3150err_close_tises:
3151 for (tc--; tc >= 0; tc--)
5426a0b2 3152 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 3153
3154 return err;
3155}
3156
cb67b832 3157void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 3158{
3159 int tc;
3160
6bfd390b 3161 for (tc = 0; tc < priv->profile->max_tc; tc++)
5426a0b2 3162 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 3163}
3164
6a9764ef
SM		 3165static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3166 enum mlx5e_traffic_types tt,
3167 u32 *tirc)
f62b8bb8 3168{
b50d292b 3169 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 3170
6a9764ef 3171 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
f62b8bb8 3172
4cbeaff5 3173 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 3174 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
7b3722fa 3175 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
f62b8bb8
AV		 3176}
3177
6a9764ef 3178static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
f62b8bb8 3179{
b50d292b 3180 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696 3181
6a9764ef 3182 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
1da36696
TT		 3183
3184 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3185 MLX5_SET(tirc, tirc, indirect_table, rqtn);
3186 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3187}
3188
46dc933c 3189int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
1da36696 3190{
724b2aa1 3191 struct mlx5e_tir *tir;
f62b8bb8
AV		 3192 void *tirc;
3193 int inlen;
7b3722fa 3194 int i = 0;
f62b8bb8 3195 int err;
1da36696 3196 u32 *in;
1da36696 3197 int tt;
f62b8bb8
AV		 3198
3199 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 3200 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 3201 if (!in)
3202 return -ENOMEM;
3203
1da36696
TT		 3204 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3205 memset(in, 0, inlen);
724b2aa1 3206 tir = &priv->indir_tir[tt];
1da36696 3207 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 3208 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
724b2aa1 3209 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
7b3722fa
GP		 3210 if (err) {
3211 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3212 goto err_destroy_inner_tirs;
3213 }
f62b8bb8
AV		 3214 }
3215
46dc933c 3216 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
7b3722fa
GP		 3217 goto out;
3218
3219 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3220 memset(in, 0, inlen);
3221 tir = &priv->inner_indir_tir[i];
3222 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3223 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3224 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3225 if (err) {
3226 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3227 goto err_destroy_inner_tirs;
3228 }
3229 }
3230
3231out:
6bfd390b
HHZ		 3232 kvfree(in);
3233
3234 return 0;
3235
7b3722fa
GP		 3236err_destroy_inner_tirs:
3237 for (i--; i >= 0; i--)
3238 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3239
6bfd390b
HHZ		 3240 for (tt--; tt >= 0; tt--)
3241 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3242
3243 kvfree(in);
3244
3245 return err;
3246}
3247
cb67b832 3248int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b 3249{
779d986d 3250 int nch = mlx5e_get_netdev_max_channels(priv->netdev);
6bfd390b
HHZ		 3251 struct mlx5e_tir *tir;
3252 void *tirc;
3253 int inlen;
3254 int err;
3255 u32 *in;
3256 int ix;
3257
3258 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 3259 in = kvzalloc(inlen, GFP_KERNEL);
6bfd390b
HHZ		 3260 if (!in)
3261 return -ENOMEM;
3262
1da36696
TT		 3263 for (ix = 0; ix < nch; ix++) {
3264 memset(in, 0, inlen);
724b2aa1 3265 tir = &priv->direct_tir[ix];
1da36696 3266 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 3267 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
724b2aa1 3268 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 3269 if (err)
3270 goto err_destroy_ch_tirs;
3271 }
3272
3273 kvfree(in);
3274
f62b8bb8
AV		 3275 return 0;
3276
1da36696 3277err_destroy_ch_tirs:
8f493ffd 3278 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
1da36696 3279 for (ix--; ix >= 0; ix--)
724b2aa1 3280 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 3281
1da36696 3282 kvfree(in);
f62b8bb8
AV		 3283
3284 return err;
3285}
3286
46dc933c 3287void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
f62b8bb8
AV		 3288{
3289 int i;
3290
1da36696 3291 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 3292 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
7b3722fa 3293
46dc933c 3294 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
7b3722fa
GP		 3295 return;
3296
3297 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3298 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
f62b8bb8
AV		 3299}
3300
cb67b832 3301void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b 3302{
779d986d 3303 int nch = mlx5e_get_netdev_max_channels(priv->netdev);
6bfd390b
HHZ		 3304 int i;
3305
3306 for (i = 0; i < nch; i++)
3307 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3308}
3309
102722fc
GE		 3310static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3311{
3312 int err = 0;
3313 int i;
3314
3315 for (i = 0; i < chs->num; i++) {
3316 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3317 if (err)
3318 return err;
3319 }
3320
3321 return 0;
3322}
3323
f6d96a20 3324static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
36350114
GP		 3325{
3326 int err = 0;
3327 int i;
3328
ff9c852f
SM		 3329 for (i = 0; i < chs->num; i++) {
3330 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
36350114
GP		 3331 if (err)
3332 return err;
3333 }
3334
3335 return 0;
3336}
3337
0cf0f6d3
JP		 3338static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3339 struct tc_mqprio_qopt *mqprio)
08fb1dac
SM		 3340{
3341 struct mlx5e_priv *priv = netdev_priv(netdev);
6f9485af 3342 struct mlx5e_channels new_channels = {};
0cf0f6d3 3343 u8 tc = mqprio->num_tc;
08fb1dac
SM		 3344 int err = 0;
3345
0cf0f6d3
JP		 3346 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3347
08fb1dac
SM		 3348 if (tc && tc != MLX5E_MAX_NUM_TC)
3349 return -EINVAL;
3350
3351 mutex_lock(&priv->state_lock);
3352
6f9485af
SM		 3353 new_channels.params = priv->channels.params;
3354 new_channels.params.num_tc = tc ? tc : 1;
08fb1dac 3355
20b6a1c7 3356 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6f9485af
SM		 3357 priv->channels.params = new_channels.params;
3358 goto out;
3359 }
08fb1dac 3360
6f9485af
SM		 3361 err = mlx5e_open_channels(priv, &new_channels);
3362 if (err)
3363 goto out;
08fb1dac 3364
05909bab
EBE		 3365 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3366 new_channels.params.num_tc);
2e20a151 3367 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
6f9485af 3368out:
08fb1dac 3369 mutex_unlock(&priv->state_lock);
08fb1dac
SM		 3370 return err;
3371}
3372
e80541ec 3373#ifdef CONFIG_MLX5_ESWITCH
d6c862ba 3374static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
60bd4af8
OG		 3375 struct tc_cls_flower_offload *cls_flower,
3376 int flags)
08fb1dac 3377{
0cf0f6d3
JP		 3378 switch (cls_flower->command) {
3379 case TC_CLSFLOWER_REPLACE:
60bd4af8 3380 return mlx5e_configure_flower(priv, cls_flower, flags);
0cf0f6d3 3381 case TC_CLSFLOWER_DESTROY:
60bd4af8 3382 return mlx5e_delete_flower(priv, cls_flower, flags);
0cf0f6d3 3383 case TC_CLSFLOWER_STATS:
60bd4af8 3384 return mlx5e_stats_flower(priv, cls_flower, flags);
0cf0f6d3 3385 default:
a5fcf8a6 3386 return -EOPNOTSUPP;
0cf0f6d3
JP		 3387 }
3388}
d6c862ba 3389
60bd4af8
OG		 3390static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3391 void *cb_priv)
d6c862ba
JP		 3392{
3393 struct mlx5e_priv *priv = cb_priv;
3394
3395 switch (type) {
3396 case TC_SETUP_CLSFLOWER:
60bd4af8 3397 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS);
d6c862ba
JP		 3398 default:
3399 return -EOPNOTSUPP;
3400 }
3401}
3402
3403static int mlx5e_setup_tc_block(struct net_device *dev,
3404 struct tc_block_offload *f)
3405{
3406 struct mlx5e_priv *priv = netdev_priv(dev);
3407
3408 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3409 return -EOPNOTSUPP;
3410
3411 switch (f->command) {
3412 case TC_BLOCK_BIND:
3413 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
60513bd8 3414 priv, priv, f->extack);
d6c862ba
JP		 3415 case TC_BLOCK_UNBIND:
3416 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3417 priv);
3418 return 0;
3419 default:
3420 return -EOPNOTSUPP;
3421 }
3422}
e80541ec 3423#endif
a5fcf8a6 3424
9afe9a53
OG		 3425static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3426 void *type_data)
0cf0f6d3 3427{
2572ac53 3428 switch (type) {
fde6af47 3429#ifdef CONFIG_MLX5_ESWITCH
d6c862ba
JP		 3430 case TC_SETUP_BLOCK:
3431 return mlx5e_setup_tc_block(dev, type_data);
fde6af47 3432#endif
575ed7d3 3433 case TC_SETUP_QDISC_MQPRIO:
de4784ca 3434 return mlx5e_setup_tc_mqprio(dev, type_data);
e8f887ac
AV		 3435 default:
3436 return -EOPNOTSUPP;
3437 }
08fb1dac
SM		 3438}
3439
bc1f4470 3440static void
f62b8bb8
AV		 3441mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3442{
3443 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 3444 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 3445 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 3446 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 3447
ed56c519 3448 /* update HW stats in background for next time */
cdeef2b1 3449 mlx5e_queue_update_stats(priv);
ed56c519 3450
370bad0f
OG		 3451 if (mlx5e_is_uplink_rep(priv)) {
3452 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3453 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3454 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3455 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3456 } else {
868a01a2 3457 mlx5e_grp_sw_update_stats(priv);
370bad0f
OG		 3458 stats->rx_packets = sstats->rx_packets;
3459 stats->rx_bytes = sstats->rx_bytes;
3460 stats->tx_packets = sstats->tx_packets;
3461 stats->tx_bytes = sstats->tx_bytes;
3462 stats->tx_dropped = sstats->tx_queue_dropped;
3463 }
269e6b3a
GP		 3464
3465 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 3466
3467 stats->rx_length_errors =
9218b44d
GP		 3468 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3469 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3470 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 3471 stats->rx_crc_errors =
9218b44d
GP		 3472 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3473 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3474 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a
GP		 3475 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3476 stats->rx_frame_errors;
3477 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3478
3479 /* vport multicast also counts packets that are dropped due to steering
3480 * or rx out of buffer
3481 */
9218b44d
GP		 3482 stats->multicast =
3483 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 3484}
3485
3486static void mlx5e_set_rx_mode(struct net_device *dev)
3487{
3488 struct mlx5e_priv *priv = netdev_priv(dev);
3489
7bb29755 3490 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3491}
3492
3493static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3494{
3495 struct mlx5e_priv *priv = netdev_priv(netdev);
3496 struct sockaddr *saddr = addr;
3497
3498 if (!is_valid_ether_addr(saddr->sa_data))
3499 return -EADDRNOTAVAIL;
3500
3501 netif_addr_lock_bh(netdev);
3502 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3503 netif_addr_unlock_bh(netdev);
3504
7bb29755 3505 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3506
3507 return 0;
3508}
3509
75b81ce7 3510#define MLX5E_SET_FEATURE(features, feature, enable) \
0e405443
GP		 3511 do { \
3512 if (enable) \
75b81ce7 3513 *features |= feature; \
0e405443 3514 else \
75b81ce7 3515 *features &= ~feature; \
0e405443
GP		 3516 } while (0)
3517
3518typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3519
3520static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 3521{
3522 struct mlx5e_priv *priv = netdev_priv(netdev);
619a8f2a 3523 struct mlx5_core_dev *mdev = priv->mdev;
2e20a151 3524 struct mlx5e_channels new_channels = {};
619a8f2a 3525 struct mlx5e_params *old_params;
2e20a151
SM		 3526 int err = 0;
3527 bool reset;
f62b8bb8
AV		 3528
3529 mutex_lock(&priv->state_lock);
f62b8bb8 3530
619a8f2a 3531 old_params = &priv->channels.params;
6c3a823e
TT		 3532 if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3533 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3534 err = -EINVAL;
3535 goto out;
3536 }
3537
619a8f2a 3538 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3539
619a8f2a 3540 new_channels.params = *old_params;
2e20a151
SM		 3541 new_channels.params.lro_en = enable;
3542
99cbfa93 3543 if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
619a8f2a
TT		 3544 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3545 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3546 reset = false;
3547 }
3548
2e20a151 3549 if (!reset) {
619a8f2a 3550 *old_params = new_channels.params;
2e20a151
SM		 3551 err = mlx5e_modify_tirs_lro(priv);
3552 goto out;
98e81b0a 3553 }
f62b8bb8 3554
2e20a151
SM		 3555 err = mlx5e_open_channels(priv, &new_channels);
3556 if (err)
3557 goto out;
0e405443 3558
2e20a151
SM		 3559 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3560out:
9b37b07f 3561 mutex_unlock(&priv->state_lock);
0e405443
GP		 3562 return err;
3563}
3564
2b52a283 3565static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
0e405443
GP		 3566{
3567 struct mlx5e_priv *priv = netdev_priv(netdev);
3568
3569 if (enable)
2b52a283 3570 mlx5e_enable_cvlan_filter(priv);
0e405443 3571 else
2b52a283 3572 mlx5e_disable_cvlan_filter(priv);
0e405443
GP		 3573
3574 return 0;
3575}
3576
3577static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3578{
3579 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 3580
0e405443 3581 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 3582 netdev_err(netdev,
3583 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3584 return -EINVAL;
3585 }
3586
0e405443
GP		 3587 return 0;
3588}
3589
94cb1ebb
EBE		 3590static int set_feature_rx_all(struct net_device *netdev, bool enable)
3591{
3592 struct mlx5e_priv *priv = netdev_priv(netdev);
3593 struct mlx5_core_dev *mdev = priv->mdev;
3594
3595 return mlx5_set_port_fcs(mdev, !enable);
3596}
3597
102722fc
GE		 3598static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3599{
3600 struct mlx5e_priv *priv = netdev_priv(netdev);
3601 int err;
3602
3603 mutex_lock(&priv->state_lock);
3604
3605 priv->channels.params.scatter_fcs_en = enable;
3606 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3607 if (err)
3608 priv->channels.params.scatter_fcs_en = !enable;
3609
3610 mutex_unlock(&priv->state_lock);
3611
3612 return err;
3613}
3614
36350114
GP		 3615static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3616{
3617 struct mlx5e_priv *priv = netdev_priv(netdev);
ff9c852f 3618 int err = 0;
36350114
GP		 3619
3620 mutex_lock(&priv->state_lock);
3621
6a9764ef 3622 priv->channels.params.vlan_strip_disable = !enable;
ff9c852f
SM		 3623 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3624 goto unlock;
3625
3626 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
36350114 3627 if (err)
6a9764ef 3628 priv->channels.params.vlan_strip_disable = enable;
36350114 3629
ff9c852f 3630unlock:
36350114
GP		 3631 mutex_unlock(&priv->state_lock);
3632
3633 return err;
3634}
3635
ec080045 3636#ifdef CONFIG_MLX5_EN_ARFS
45bf454a
MG		 3637static int set_feature_arfs(struct net_device *netdev, bool enable)
3638{
3639 struct mlx5e_priv *priv = netdev_priv(netdev);
3640 int err;
3641
3642 if (enable)
3643 err = mlx5e_arfs_enable(priv);
3644 else
3645 err = mlx5e_arfs_disable(priv);
3646
3647 return err;
3648}
3649#endif
3650
0e405443 3651static int mlx5e_handle_feature(struct net_device *netdev,
75b81ce7 3652 netdev_features_t *features,
0e405443
GP		 3653 netdev_features_t wanted_features,
3654 netdev_features_t feature,
3655 mlx5e_feature_handler feature_handler)
3656{
3657 netdev_features_t changes = wanted_features ^ netdev->features;
3658 bool enable = !!(wanted_features & feature);
3659 int err;
3660
3661 if (!(changes & feature))
3662 return 0;
3663
3664 err = feature_handler(netdev, enable);
3665 if (err) {
b20eab15
GP		 3666 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3667 enable ? "Enable" : "Disable", &feature, err);
0e405443
GP		 3668 return err;
3669 }
3670
75b81ce7 3671 MLX5E_SET_FEATURE(features, feature, enable);
0e405443
GP		 3672 return 0;
3673}
3674
3675static int mlx5e_set_features(struct net_device *netdev,
3676 netdev_features_t features)
3677{
75b81ce7 3678 netdev_features_t oper_features = netdev->features;
be0f780b
GP		 3679 int err = 0;
3680
3681#define MLX5E_HANDLE_FEATURE(feature, handler) \
3682 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
0e405443 3683
be0f780b
GP		 3684 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3685 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
2b52a283 3686 set_feature_cvlan_filter);
be0f780b
GP		 3687 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3688 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3689 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3690 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
ec080045 3691#ifdef CONFIG_MLX5_EN_ARFS
be0f780b 3692 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
45bf454a 3693#endif
0e405443 3694
75b81ce7
GP		 3695 if (err) {
3696 netdev->features = oper_features;
3697 return -EINVAL;
3698 }
3699
3700 return 0;
f62b8bb8
AV		 3701}
3702
7d92d580
GP		 3703static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3704 netdev_features_t features)
3705{
3706 struct mlx5e_priv *priv = netdev_priv(netdev);
6c3a823e 3707 struct mlx5e_params *params;
7d92d580
GP		 3708
3709 mutex_lock(&priv->state_lock);
6c3a823e 3710 params = &priv->channels.params;
7d92d580
GP		 3711 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3712 /* HW strips the outer C-tag header, this is a problem
3713 * for S-tag traffic.
3714 */
3715 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
6c3a823e 3716 if (!params->vlan_strip_disable)
7d92d580
GP		 3717 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3718 }
6c3a823e
TT		 3719 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3720 features &= ~NETIF_F_LRO;
3721 if (params->lro_en)
3722 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3723 }
3724
7d92d580
GP		 3725 mutex_unlock(&priv->state_lock);
3726
3727 return features;
3728}
3729
250a42b6
AN		 3730int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3731 change_hw_mtu_cb set_mtu_cb)
f62b8bb8
AV		 3732{
3733 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151 3734 struct mlx5e_channels new_channels = {};
472a1e44 3735 struct mlx5e_params *params;
98e81b0a 3736 int err = 0;
506753b0 3737 bool reset;
f62b8bb8 3738
f62b8bb8 3739 mutex_lock(&priv->state_lock);
98e81b0a 3740
472a1e44 3741 params = &priv->channels.params;
506753b0 3742
73281b78 3743 reset = !params->lro_en;
2e20a151 3744 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3745
73281b78
TT		 3746 new_channels.params = *params;
3747 new_channels.params.sw_mtu = new_mtu;
3748
a26a5bdf
TT		 3749 if (params->xdp_prog &&
3750 !mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
3751 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3752 new_mtu, MLX5E_XDP_MAX_MTU);
3753 err = -EINVAL;
3754 goto out;
3755 }
3756
99cbfa93 3757 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
73281b78
TT		 3758 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3759 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3760
3761 reset = reset && (ppw_old != ppw_new);
3762 }
3763
2e20a151 3764 if (!reset) {
472a1e44 3765 params->sw_mtu = new_mtu;
eacecf27
AN		 3766 if (set_mtu_cb)
3767 set_mtu_cb(priv);
472a1e44 3768 netdev->mtu = params->sw_mtu;
2e20a151
SM		 3769 goto out;
3770 }
98e81b0a 3771
2e20a151 3772 err = mlx5e_open_channels(priv, &new_channels);
472a1e44 3773 if (err)
2e20a151 3774 goto out;
2e20a151 3775
250a42b6 3776 mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb);
472a1e44 3777 netdev->mtu = new_channels.params.sw_mtu;
f62b8bb8 3778
2e20a151
SM		 3779out:
3780 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 3781 return err;
3782}
3783
250a42b6
AN		 3784static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3785{
3786 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3787}
3788
7c39afb3
FD		 3789int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3790{
3791 struct hwtstamp_config config;
3792 int err;
3793
6dbc80ca
MS		 3794 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3795 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
7c39afb3
FD		 3796 return -EOPNOTSUPP;
3797
3798 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3799 return -EFAULT;
3800
3801 /* TX HW timestamp */
3802 switch (config.tx_type) {
3803 case HWTSTAMP_TX_OFF:
3804 case HWTSTAMP_TX_ON:
3805 break;
3806 default:
3807 return -ERANGE;
3808 }
3809
3810 mutex_lock(&priv->state_lock);
3811 /* RX HW timestamp */
3812 switch (config.rx_filter) {
3813 case HWTSTAMP_FILTER_NONE:
3814 /* Reset CQE compression to Admin default */
3815 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3816 break;
3817 case HWTSTAMP_FILTER_ALL:
3818 case HWTSTAMP_FILTER_SOME:
3819 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3820 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3821 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3822 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3823 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3824 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3825 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3826 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3827 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3828 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3829 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3830 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3831 case HWTSTAMP_FILTER_NTP_ALL:
3832 /* Disable CQE compression */
3833 netdev_warn(priv->netdev, "Disabling cqe compression");
3834 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3835 if (err) {
3836 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3837 mutex_unlock(&priv->state_lock);
3838 return err;
3839 }
3840 config.rx_filter = HWTSTAMP_FILTER_ALL;
3841 break;
3842 default:
3843 mutex_unlock(&priv->state_lock);
3844 return -ERANGE;
3845 }
3846
3847 memcpy(&priv->tstamp, &config, sizeof(config));
3848 mutex_unlock(&priv->state_lock);
3849
3850 return copy_to_user(ifr->ifr_data, &config,
3851 sizeof(config)) ? -EFAULT : 0;
3852}
3853
3854int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3855{
3856 struct hwtstamp_config *cfg = &priv->tstamp;
3857
3858 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3859 return -EOPNOTSUPP;
3860
3861 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3862}
3863
ef9814de
EBE		 3864static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3865{
1170fbd8
FD		 3866 struct mlx5e_priv *priv = netdev_priv(dev);
3867
ef9814de
EBE		 3868 switch (cmd) {
3869 case SIOCSHWTSTAMP:
1170fbd8 3870 return mlx5e_hwstamp_set(priv, ifr);
ef9814de 3871 case SIOCGHWTSTAMP:
1170fbd8 3872 return mlx5e_hwstamp_get(priv, ifr);
ef9814de
EBE		 3873 default:
3874 return -EOPNOTSUPP;
3875 }
3876}
3877
e80541ec 3878#ifdef CONFIG_MLX5_ESWITCH
66e49ded
SM		 3879static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3880{
3881 struct mlx5e_priv *priv = netdev_priv(dev);
3882 struct mlx5_core_dev *mdev = priv->mdev;
3883
3884 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3885}
3886
79aab093
MS		 3887static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3888 __be16 vlan_proto)
66e49ded
SM		 3889{
3890 struct mlx5e_priv *priv = netdev_priv(dev);
3891 struct mlx5_core_dev *mdev = priv->mdev;
3892
79aab093
MS		 3893 if (vlan_proto != htons(ETH_P_8021Q))
3894 return -EPROTONOSUPPORT;
3895
66e49ded
SM		 3896 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3897 vlan, qos);
3898}
3899
f942380c
MHY		 3900static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3901{
3902 struct mlx5e_priv *priv = netdev_priv(dev);
3903 struct mlx5_core_dev *mdev = priv->mdev;
3904
3905 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3906}
3907
1edc57e2
MHY		 3908static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3909{
3910 struct mlx5e_priv *priv = netdev_priv(dev);
3911 struct mlx5_core_dev *mdev = priv->mdev;
3912
3913 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3914}
bd77bf1c
MHY		 3915
3916static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3917 int max_tx_rate)
3918{
3919 struct mlx5e_priv *priv = netdev_priv(dev);
3920 struct mlx5_core_dev *mdev = priv->mdev;
3921
bd77bf1c 3922 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3923 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3924}
3925
66e49ded
SM		 3926static int mlx5_vport_link2ifla(u8 esw_link)
3927{
3928 switch (esw_link) {
cc9c82a8 3929 case MLX5_VPORT_ADMIN_STATE_DOWN:
66e49ded 3930 return IFLA_VF_LINK_STATE_DISABLE;
cc9c82a8 3931 case MLX5_VPORT_ADMIN_STATE_UP:
66e49ded
SM		 3932 return IFLA_VF_LINK_STATE_ENABLE;
3933 }
3934 return IFLA_VF_LINK_STATE_AUTO;
3935}
3936
3937static int mlx5_ifla_link2vport(u8 ifla_link)
3938{
3939 switch (ifla_link) {
3940 case IFLA_VF_LINK_STATE_DISABLE:
cc9c82a8 3941 return MLX5_VPORT_ADMIN_STATE_DOWN;
66e49ded 3942 case IFLA_VF_LINK_STATE_ENABLE:
cc9c82a8 3943 return MLX5_VPORT_ADMIN_STATE_UP;
66e49ded 3944 }
cc9c82a8 3945 return MLX5_VPORT_ADMIN_STATE_AUTO;
66e49ded
SM		 3946}
3947
3948static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3949 int link_state)
3950{
3951 struct mlx5e_priv *priv = netdev_priv(dev);
3952 struct mlx5_core_dev *mdev = priv->mdev;
3953
3954 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3955 mlx5_ifla_link2vport(link_state));
3956}
3957
3958static int mlx5e_get_vf_config(struct net_device *dev,
3959 int vf, struct ifla_vf_info *ivi)
3960{
3961 struct mlx5e_priv *priv = netdev_priv(dev);
3962 struct mlx5_core_dev *mdev = priv->mdev;
3963 int err;
3964
3965 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3966 if (err)
3967 return err;
3968 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3969 return 0;
3970}
3971
3972static int mlx5e_get_vf_stats(struct net_device *dev,
3973 int vf, struct ifla_vf_stats *vf_stats)
3974{
3975 struct mlx5e_priv *priv = netdev_priv(dev);
3976 struct mlx5_core_dev *mdev = priv->mdev;
3977
3978 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3979 vf_stats);
3980}
e80541ec 3981#endif
66e49ded 3982
dccea6bf
SM		 3983struct mlx5e_vxlan_work {
3984 struct work_struct work;
3985 struct mlx5e_priv *priv;
3986 u16 port;
3987};
3988
3989static void mlx5e_vxlan_add_work(struct work_struct *work)
3990{
3991 struct mlx5e_vxlan_work *vxlan_work =
3992 container_of(work, struct mlx5e_vxlan_work, work);
3993 struct mlx5e_priv *priv = vxlan_work->priv;
3994 u16 port = vxlan_work->port;
3995
3996 mutex_lock(&priv->state_lock);
358aa5ce 3997 mlx5_vxlan_add_port(priv->mdev->vxlan, port);
dccea6bf
SM		 3998 mutex_unlock(&priv->state_lock);
3999
4000 kfree(vxlan_work);
4001}
4002
4003static void mlx5e_vxlan_del_work(struct work_struct *work)
4004{
4005 struct mlx5e_vxlan_work *vxlan_work =
4006 container_of(work, struct mlx5e_vxlan_work, work);
4007 struct mlx5e_priv *priv = vxlan_work->priv;
4008 u16 port = vxlan_work->port;
4009
4010 mutex_lock(&priv->state_lock);
358aa5ce 4011 mlx5_vxlan_del_port(priv->mdev->vxlan, port);
dccea6bf
SM		 4012 mutex_unlock(&priv->state_lock);
4013 kfree(vxlan_work);
4014}
4015
4016static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4017{
4018 struct mlx5e_vxlan_work *vxlan_work;
4019
4020 vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4021 if (!vxlan_work)
4022 return;
4023
4024 if (add)
4025 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4026 else
4027 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4028
4029 vxlan_work->priv = priv;
4030 vxlan_work->port = port;
4031 queue_work(priv->wq, &vxlan_work->work);
4032}
4033
1ad9a00a
PB		 4034static void mlx5e_add_vxlan_port(struct net_device *netdev,
4035 struct udp_tunnel_info *ti)
b3f63c3d
MF		 4036{
4037 struct mlx5e_priv *priv = netdev_priv(netdev);
4038
974c3f30
AD		 4039 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4040 return;
4041
358aa5ce 4042 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
b3f63c3d
MF		 4043 return;
4044
278d7f3d 4045 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 4046}
4047
1ad9a00a
PB		 4048static void mlx5e_del_vxlan_port(struct net_device *netdev,
4049 struct udp_tunnel_info *ti)
b3f63c3d
MF		 4050{
4051 struct mlx5e_priv *priv = netdev_priv(netdev);
4052
974c3f30
AD		 4053 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4054 return;
4055
358aa5ce 4056 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
b3f63c3d
MF		 4057 return;
4058
278d7f3d 4059 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 4060}
4061
27299841
GP		 4062static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4063 struct sk_buff *skb,
4064 netdev_features_t features)
b3f63c3d 4065{
2989ad1e 4066 unsigned int offset = 0;
b3f63c3d 4067 struct udphdr *udph;
27299841
GP		 4068 u8 proto;
4069 u16 port;
b3f63c3d
MF		 4070
4071 switch (vlan_get_protocol(skb)) {
4072 case htons(ETH_P_IP):
4073 proto = ip_hdr(skb)->protocol;
4074 break;
4075 case htons(ETH_P_IPV6):
2989ad1e 4076 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
b3f63c3d
MF		 4077 break;
4078 default:
4079 goto out;
4080 }
4081
27299841
GP		 4082 switch (proto) {
4083 case IPPROTO_GRE:
4084 return features;
4085 case IPPROTO_UDP:
b3f63c3d
MF		 4086 udph = udp_hdr(skb);
4087 port = be16_to_cpu(udph->dest);
b3f63c3d 4088
27299841 4089 /* Verify if UDP port is being offloaded by HW */
358aa5ce 4090 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
27299841
GP		 4091 return features;
4092 }
b3f63c3d
MF		 4093
4094out:
4095 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4096 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4097}
4098
4099static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4100 struct net_device *netdev,
4101 netdev_features_t features)
4102{
4103 struct mlx5e_priv *priv = netdev_priv(netdev);
4104
4105 features = vlan_features_check(skb, features);
4106 features = vxlan_features_check(skb, features);
4107
2ac9cfe7
IT		 4108#ifdef CONFIG_MLX5_EN_IPSEC
4109 if (mlx5e_ipsec_feature_check(skb, netdev, features))
4110 return features;
4111#endif
4112
b3f63c3d
MF		 4113 /* Validate if the tunneled packet is being offloaded by HW */
4114 if (skb->encapsulation &&
4115 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
27299841 4116 return mlx5e_tunnel_features_check(priv, skb, features);
b3f63c3d
MF		 4117
4118 return features;
4119}
4120
7ca560b5
EBE		 4121static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
4122 struct mlx5e_txqsq *sq)
4123{
7b2117bb 4124 struct mlx5_eq *eq = sq->cq.mcq.eq;
7ca560b5
EBE		 4125 u32 eqe_count;
4126
7ca560b5 4127 netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
7b2117bb 4128 eq->eqn, eq->cons_index, eq->irqn);
7ca560b5
EBE		 4129
4130 eqe_count = mlx5_eq_poll_irq_disabled(eq);
4131 if (!eqe_count)
4132 return false;
4133
4134 netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
05909bab 4135 sq->channel->stats->eq_rearm++;
7ca560b5
EBE		 4136 return true;
4137}
4138
bfc647d5 4139static void mlx5e_tx_timeout_work(struct work_struct *work)
3947ca18 4140{
bfc647d5
EBE		 4141 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4142 tx_timeout_work);
4143 struct net_device *dev = priv->netdev;
7ca560b5 4144 bool reopen_channels = false;
bfc647d5 4145 int i, err;
3947ca18 4146
bfc647d5
EBE		 4147 rtnl_lock();
4148 mutex_lock(&priv->state_lock);
4149
4150 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4151 goto unlock;
3947ca18 4152
6a9764ef 4153 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
84990945 4154 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
acc6c595 4155 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3947ca18 4156
84990945 4157 if (!netif_xmit_stopped(dev_queue))
3947ca18 4158 continue;
bfc647d5
EBE		 4159
4160 netdev_err(dev,
4161 "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
84990945
EBE		 4162 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
4163 jiffies_to_usecs(jiffies - dev_queue->trans_start));
3a32b26a 4164
7ca560b5
EBE		 4165 /* If we recover a lost interrupt, most likely TX timeout will
4166 * be resolved, skip reopening channels
4167 */
4168 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
4169 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
4170 reopen_channels = true;
4171 }
3947ca18
DJ		 4172 }
4173
bfc647d5
EBE		 4174 if (!reopen_channels)
4175 goto unlock;
4176
4177 mlx5e_close_locked(dev);
4178 err = mlx5e_open_locked(dev);
4179 if (err)
4180 netdev_err(priv->netdev,
4181 "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
4182 err);
4183
4184unlock:
4185 mutex_unlock(&priv->state_lock);
4186 rtnl_unlock();
4187}
4188
4189static void mlx5e_tx_timeout(struct net_device *dev)
4190{
4191 struct mlx5e_priv *priv = netdev_priv(dev);
4192
4193 netdev_err(dev, "TX timeout detected\n");
4194 queue_work(priv->wq, &priv->tx_timeout_work);
3947ca18
DJ		 4195}
4196
a26a5bdf 4197static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
0ec13877
TT		 4198{
4199 struct net_device *netdev = priv->netdev;
a26a5bdf 4200 struct mlx5e_channels new_channels = {};
0ec13877
TT		 4201
4202 if (priv->channels.params.lro_en) {
4203 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4204 return -EINVAL;
4205 }
4206
4207 if (MLX5_IPSEC_DEV(priv->mdev)) {
4208 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4209 return -EINVAL;
4210 }
4211
a26a5bdf
TT		 4212 new_channels.params = priv->channels.params;
4213 new_channels.params.xdp_prog = prog;
4214
4215 if (!mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
4216 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4217 new_channels.params.sw_mtu, MLX5E_XDP_MAX_MTU);
4218 return -EINVAL;
4219 }
4220
0ec13877
TT		 4221 return 0;
4222}
4223
86994156
RS		 4224static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4225{
4226 struct mlx5e_priv *priv = netdev_priv(netdev);
4227 struct bpf_prog *old_prog;
86994156 4228 bool reset, was_opened;
96d39502 4229 int err = 0;
86994156
RS		 4230 int i;
4231
4232 mutex_lock(&priv->state_lock);
4233
0ec13877 4234 if (prog) {
a26a5bdf 4235 err = mlx5e_xdp_allowed(priv, prog);
0ec13877
TT		 4236 if (err)
4237 goto unlock;
547eede0
IT		 4238 }
4239
86994156
RS		 4240 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4241 /* no need for full reset when exchanging programs */
6a9764ef 4242 reset = (!priv->channels.params.xdp_prog || !prog);
86994156
RS		 4243
4244 if (was_opened && reset)
4245 mlx5e_close_locked(netdev);
c54c0629
DB		 4246 if (was_opened && !reset) {
4247 /* num_channels is invariant here, so we can take the
4248 * batched reference right upfront.
4249 */
6a9764ef 4250 prog = bpf_prog_add(prog, priv->channels.num);
c54c0629
DB		 4251 if (IS_ERR(prog)) {
4252 err = PTR_ERR(prog);
4253 goto unlock;
4254 }
4255 }
86994156 4256
c54c0629
DB		 4257 /* exchange programs, extra prog reference we got from caller
4258 * as long as we don't fail from this point onwards.
4259 */
6a9764ef 4260 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
86994156
RS		 4261 if (old_prog)
4262 bpf_prog_put(old_prog);
4263
4264 if (reset) /* change RQ type according to priv->xdp_prog */
2a0f561b 4265 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
86994156
RS		 4266
4267 if (was_opened && reset)
4268 mlx5e_open_locked(netdev);
4269
4270 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4271 goto unlock;
4272
4273 /* exchanging programs w/o reset, we update ref counts on behalf
4274 * of the channels RQs here.
4275 */
ff9c852f
SM		 4276 for (i = 0; i < priv->channels.num; i++) {
4277 struct mlx5e_channel *c = priv->channels.c[i];
86994156 4278
c0f1147d 4279 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 4280 napi_synchronize(&c->napi);
4281 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4282
4283 old_prog = xchg(&c->rq.xdp_prog, prog);
4284
c0f1147d 4285 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156 4286 /* napi_schedule in case we have missed anything */
86994156
RS		 4287 napi_schedule(&c->napi);
4288
4289 if (old_prog)
4290 bpf_prog_put(old_prog);
4291 }
4292
4293unlock:
4294 mutex_unlock(&priv->state_lock);
4295 return err;
4296}
4297
821b2e29 4298static u32 mlx5e_xdp_query(struct net_device *dev)
86994156
RS		 4299{
4300 struct mlx5e_priv *priv = netdev_priv(dev);
821b2e29
MKL		 4301 const struct bpf_prog *xdp_prog;
4302 u32 prog_id = 0;
86994156 4303
821b2e29
MKL		 4304 mutex_lock(&priv->state_lock);
4305 xdp_prog = priv->channels.params.xdp_prog;
4306 if (xdp_prog)
4307 prog_id = xdp_prog->aux->id;
4308 mutex_unlock(&priv->state_lock);
4309
4310 return prog_id;
86994156
RS		 4311}
4312
f4e63525 4313static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
86994156
RS		 4314{
4315 switch (xdp->command) {
4316 case XDP_SETUP_PROG:
4317 return mlx5e_xdp_set(dev, xdp->prog);
4318 case XDP_QUERY_PROG:
821b2e29 4319 xdp->prog_id = mlx5e_xdp_query(dev);
86994156
RS		 4320 return 0;
4321 default:
4322 return -EINVAL;
4323 }
4324}
4325
4d8fcf21 4326const struct net_device_ops mlx5e_netdev_ops = {
f62b8bb8
AV		 4327 .ndo_open = mlx5e_open,
4328 .ndo_stop = mlx5e_close,
4329 .ndo_start_xmit = mlx5e_xmit,
0cf0f6d3 4330 .ndo_setup_tc = mlx5e_setup_tc,
08fb1dac 4331 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 4332 .ndo_get_stats64 = mlx5e_get_stats,
4333 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4334 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 4335 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4336 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 4337 .ndo_set_features = mlx5e_set_features,
7d92d580 4338 .ndo_fix_features = mlx5e_fix_features,
250a42b6 4339 .ndo_change_mtu = mlx5e_change_nic_mtu,
b0eed40e 4340 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 4341 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
706b3583
SM		 4342 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
4343 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
4344 .ndo_features_check = mlx5e_features_check,
3947ca18 4345 .ndo_tx_timeout = mlx5e_tx_timeout,
f4e63525 4346 .ndo_bpf = mlx5e_xdp,
58b99ee3 4347 .ndo_xdp_xmit = mlx5e_xdp_xmit,
ec080045
SM		 4348#ifdef CONFIG_MLX5_EN_ARFS
4349 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4350#endif
e80541ec 4351#ifdef CONFIG_MLX5_ESWITCH
706b3583 4352 /* SRIOV E-Switch NDOs */
b0eed40e
SM		 4353 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4354 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 4355 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 4356 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 4357 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 4358 .ndo_get_vf_config = mlx5e_get_vf_config,
4359 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4360 .ndo_get_vf_stats = mlx5e_get_vf_stats,
370bad0f
OG		 4361 .ndo_has_offload_stats = mlx5e_has_offload_stats,
4362 .ndo_get_offload_stats = mlx5e_get_offload_stats,
e80541ec 4363#endif
f62b8bb8
AV		 4364};
4365
4366static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4367{
4368 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 4369 return -EOPNOTSUPP;
f62b8bb8
AV		 4370 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4371 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4372 !MLX5_CAP_ETH(mdev, csum_cap) ||
4373 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4374 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 4375 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4376 MLX5_CAP_FLOWTABLE(mdev,
4377 flow_table_properties_nic_receive.max_ft_level)
4378 < 3) {
f62b8bb8
AV		 4379 mlx5_core_warn(mdev,
4380 "Not creating net device, some required device capabilities are missing\n");
9eb78923 4381 return -EOPNOTSUPP;
f62b8bb8 4382 }
66189961
TT		 4383 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4384 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8 4385 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3e432ab6 4386 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
66189961 4387
f62b8bb8
AV		 4388 return 0;
4389}
4390
d4b6c488 4391void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
85082dba
TT		 4392 int num_channels)
4393{
4394 int i;
4395
4396 for (i = 0; i < len; i++)
4397 indirection_rqt[i] = i % num_channels;
4398}
4399
0608d4db 4400static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
b797a684 4401{
0608d4db
TT		 4402 u32 link_speed = 0;
4403 u32 pci_bw = 0;
b797a684 4404
2c81bfd5 4405 mlx5e_port_max_linkspeed(mdev, &link_speed);
3c0d551e 4406 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
0608d4db
TT		 4407 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4408 link_speed, pci_bw);
4409
4410#define MLX5E_SLOW_PCI_RATIO (2)
4411
4412 return link_speed && pci_bw &&
4413 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
0f6e4cf6
EBE		 4414}
4415
cbce4f44 4416static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
0088cbbc 4417{
cbce4f44
TG		 4418 struct net_dim_cq_moder moder;
4419
4420 moder.cq_period_mode = cq_period_mode;
4421 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4422 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4423 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4424 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4425
4426 return moder;
4427}
0088cbbc 4428
cbce4f44
TG		 4429static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4430{
4431 struct net_dim_cq_moder moder;
0088cbbc 4432
cbce4f44
TG		 4433 moder.cq_period_mode = cq_period_mode;
4434 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4435 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
0088cbbc 4436 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
cbce4f44
TG		 4437 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4438
4439 return moder;
4440}
4441
4442static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4443{
4444 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4445 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4446 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4447}
4448
4449void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4450{
4451 if (params->tx_dim_enabled) {
4452 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4453
4454 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4455 } else {
4456 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4457 }
0088cbbc
TG		 4458
4459 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4460 params->tx_cq_moderation.cq_period_mode ==
4461 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4462}
4463
9908aa29
TT		 4464void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4465{
9a317425 4466 if (params->rx_dim_enabled) {
cbce4f44
TG		 4467 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4468
4469 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4470 } else {
4471 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
9a317425 4472 }
457fcd8a 4473
6a9764ef 4474 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
0088cbbc
TG		 4475 params->rx_cq_moderation.cq_period_mode ==
4476 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29
TT		 4477}
4478
707129dc 4479static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
2b029556
SM		 4480{
4481 int i;
4482
4483 /* The supported periods are organized in ascending order */
4484 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4485 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4486 break;
4487
4488 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4489}
4490
749359f4
GT		 4491void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4492 struct mlx5e_params *params)
4493{
4494 /* Prefer Striding RQ, unless any of the following holds:
4495 * - Striding RQ configuration is not possible/supported.
4496 * - Slow PCI heuristic.
4497 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4498 */
4499 if (!slow_pci_heuristic(mdev) &&
4500 mlx5e_striding_rq_possible(mdev, params) &&
4501 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4502 !mlx5e_rx_is_linear_skb(mdev, params)))
4503 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4504 mlx5e_set_rq_type(mdev, params);
4505 mlx5e_init_rq_type_params(mdev, params);
4506}
4507
3edc0159
GT		 4508void mlx5e_build_rss_params(struct mlx5e_params *params)
4509{
4510 params->rss_hfunc = ETH_RSS_HASH_XOR;
4511 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4512 mlx5e_build_default_indir_rqt(params->indirection_rqt,
4513 MLX5E_INDIR_RQT_SIZE, params->num_channels);
4514}
4515
8f493ffd
SM		 4516void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4517 struct mlx5e_params *params,
472a1e44 4518 u16 max_channels, u16 mtu)
f62b8bb8 4519{
48bfc397 4520 u8 rx_cq_period_mode;
2fc4bfb7 4521
472a1e44
TT		 4522 params->sw_mtu = mtu;
4523 params->hard_mtu = MLX5E_ETH_HARD_MTU;
6a9764ef
SM		 4524 params->num_channels = max_channels;
4525 params->num_tc = 1;
2b029556 4526
6a9764ef
SM		 4527 /* SQ */
4528 params->log_sq_size = is_kdump_kernel() ?
b4e029da
KH		 4529 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4530 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 4531
b797a684 4532 /* set CQE compression */
6a9764ef 4533 params->rx_cqe_compress_def = false;
b797a684 4534 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
e53eef63 4535 MLX5_CAP_GEN(mdev, vport_group_manager))
0608d4db 4536 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
0f6e4cf6 4537
6a9764ef 4538 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
b856df28 4539 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
6a9764ef
SM		 4540
4541 /* RQ */
749359f4 4542 mlx5e_build_rq_params(mdev, params);
b797a684 4543
6a9764ef 4544 /* HW LRO */
c139dbfd 4545
5426a0b2 4546 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
6a9764ef 4547 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
619a8f2a
TT		 4548 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4549 params->lro_en = !slow_pci_heuristic(mdev);
6a9764ef 4550 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
b0d4660b 4551
6a9764ef 4552 /* CQ moderation params */
48bfc397 4553 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
6a9764ef
SM		 4554 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4555 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
9a317425 4556 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
cbce4f44 4557 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
48bfc397
TG		 4558 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4559 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
9908aa29 4560
6a9764ef 4561 /* TX inline */
fbcb127e 4562 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
a6f402e4 4563
6a9764ef 4564 /* RSS */
3edc0159 4565 mlx5e_build_rss_params(params);
6a9764ef 4566}
f62b8bb8 4567
f62b8bb8
AV		 4568static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4569{
4570 struct mlx5e_priv *priv = netdev_priv(netdev);
4571
e1d7d349 4572 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 4573 if (is_zero_ether_addr(netdev->dev_addr) &&
4574 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4575 eth_hw_addr_random(netdev);
4576 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4577 }
f62b8bb8
AV		 4578}
4579
f125376b 4580#if IS_ENABLED(CONFIG_MLX5_ESWITCH)
cb67b832
HHZ		 4581static const struct switchdev_ops mlx5e_switchdev_ops = {
4582 .switchdev_port_attr_get = mlx5e_attr_get,
4583};
e80541ec 4584#endif
cb67b832 4585
6bfd390b 4586static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 4587{
4588 struct mlx5e_priv *priv = netdev_priv(netdev);
4589 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 4590 bool fcs_supported;
4591 bool fcs_enabled;
f62b8bb8
AV		 4592
4593 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4594
e80541ec
SM		 4595 netdev->netdev_ops = &mlx5e_netdev_ops;
4596
08fb1dac 4597#ifdef CONFIG_MLX5_CORE_EN_DCB
e80541ec
SM		 4598 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4599 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac 4600#endif
66e49ded 4601
f62b8bb8
AV		 4602 netdev->watchdog_timeo = 15 * HZ;
4603
4604 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4605
12be4b21 4606 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 4607 netdev->vlan_features |= NETIF_F_IP_CSUM;
4608 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4609 netdev->vlan_features |= NETIF_F_GRO;
4610 netdev->vlan_features |= NETIF_F_TSO;
4611 netdev->vlan_features |= NETIF_F_TSO6;
4612 netdev->vlan_features |= NETIF_F_RXCSUM;
4613 netdev->vlan_features |= NETIF_F_RXHASH;
4614
71186172
AH		 4615 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4616 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4617
6c3a823e
TT		 4618 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4619 mlx5e_check_fragmented_striding_rq_cap(mdev))
f62b8bb8
AV		 4620 netdev->vlan_features |= NETIF_F_LRO;
4621
4622 netdev->hw_features = netdev->vlan_features;
e4cf27bd 4623 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 4624 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4625 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4382c7b9 4626 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
f62b8bb8 4627
358aa5ce 4628 if (mlx5_vxlan_allowed(mdev->vxlan) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
b3f63c3d 4629 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 4630 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 4631 netdev->hw_enc_features |= NETIF_F_TSO;
4632 netdev->hw_enc_features |= NETIF_F_TSO6;
27299841
GP		 4633 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4634 }
4635
358aa5ce 4636 if (mlx5_vxlan_allowed(mdev->vxlan)) {
27299841
GP		 4637 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4638 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4639 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4640 NETIF_F_GSO_UDP_TUNNEL_CSUM;
b49663c8 4641 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 4642 }
4643
27299841
GP		 4644 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4645 netdev->hw_features |= NETIF_F_GSO_GRE |
4646 NETIF_F_GSO_GRE_CSUM;
4647 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4648 NETIF_F_GSO_GRE_CSUM;
4649 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4650 NETIF_F_GSO_GRE_CSUM;
4651 }
4652
3f44899e
BP		 4653 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4654 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
4655 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
4656 netdev->features |= NETIF_F_GSO_UDP_L4;
4657
94cb1ebb
EBE		 4658 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4659
4660 if (fcs_supported)
4661 netdev->hw_features |= NETIF_F_RXALL;
4662
102722fc
GE		 4663 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4664 netdev->hw_features |= NETIF_F_RXFCS;
4665
f62b8bb8 4666 netdev->features = netdev->hw_features;
6a9764ef 4667 if (!priv->channels.params.lro_en)
f62b8bb8
AV		 4668 netdev->features &= ~NETIF_F_LRO;
4669
94cb1ebb
EBE		 4670 if (fcs_enabled)
4671 netdev->features &= ~NETIF_F_RXALL;
4672
102722fc
GE		 4673 if (!priv->channels.params.scatter_fcs_en)
4674 netdev->features &= ~NETIF_F_RXFCS;
4675
e8f887ac
AV		 4676#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4677 if (FT_CAP(flow_modify_en) &&
4678 FT_CAP(modify_root) &&
4679 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 4680 FT_CAP(flow_table_modify)) {
4681 netdev->hw_features |= NETIF_F_HW_TC;
ec080045 4682#ifdef CONFIG_MLX5_EN_ARFS
1cabe6b0
MG		 4683 netdev->hw_features |= NETIF_F_NTUPLE;
4684#endif
4685 }
e8f887ac 4686
f62b8bb8 4687 netdev->features |= NETIF_F_HIGHDMA;
7d92d580 4688 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
f62b8bb8
AV		 4689
4690 netdev->priv_flags |= IFF_UNICAST_FLT;
4691
4692 mlx5e_set_netdev_dev_addr(netdev);
cb67b832 4693
f125376b 4694#if IS_ENABLED(CONFIG_MLX5_ESWITCH)
733d3e54 4695 if (MLX5_ESWITCH_MANAGER(mdev))
cb67b832
HHZ		 4696 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4697#endif
547eede0
IT		 4698
4699 mlx5e_ipsec_build_netdev(priv);
c83294b9 4700 mlx5e_tls_build_netdev(priv);
f62b8bb8
AV		 4701}
4702
1462e48d 4703void mlx5e_create_q_counters(struct mlx5e_priv *priv)
593cf338
RS		 4704{
4705 struct mlx5_core_dev *mdev = priv->mdev;
4706 int err;
4707
4708 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4709 if (err) {
4710 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4711 priv->q_counter = 0;
4712 }
7cbaf9a3
MS		 4713
4714 err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4715 if (err) {
4716 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4717 priv->drop_rq_q_counter = 0;
4718 }
593cf338
RS		 4719}
4720
1462e48d 4721void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
593cf338 4722{
7cbaf9a3
MS		 4723 if (priv->q_counter)
4724 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
593cf338 4725
7cbaf9a3
MS		 4726 if (priv->drop_rq_q_counter)
4727 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
593cf338
RS		 4728}
4729
182570b2
FD		 4730static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4731 struct net_device *netdev,
4732 const struct mlx5e_profile *profile,
4733 void *ppriv)
6bfd390b
HHZ		 4734{
4735 struct mlx5e_priv *priv = netdev_priv(netdev);
547eede0 4736 int err;
6bfd390b 4737
519a0bf5 4738 err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
182570b2
FD		 4739 if (err)
4740 return err;
4741
519a0bf5 4742 mlx5e_build_nic_params(mdev, &priv->channels.params,
779d986d 4743 mlx5e_get_netdev_max_channels(netdev), netdev->mtu);
519a0bf5
SM		 4744
4745 mlx5e_timestamp_init(priv);
4746
547eede0
IT		 4747 err = mlx5e_ipsec_init(priv);
4748 if (err)
4749 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
43585a41
IL		 4750 err = mlx5e_tls_init(priv);
4751 if (err)
4752 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
6bfd390b 4753 mlx5e_build_nic_netdev(netdev);
8bfaf07f 4754 mlx5e_build_tc2txq_maps(priv);
182570b2
FD		 4755
4756 return 0;
6bfd390b
HHZ		 4757}
4758
4759static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4760{
43585a41 4761 mlx5e_tls_cleanup(priv);
547eede0 4762 mlx5e_ipsec_cleanup(priv);
182570b2 4763 mlx5e_netdev_cleanup(priv->netdev, priv);
6bfd390b
HHZ		 4764}
4765
4766static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4767{
4768 struct mlx5_core_dev *mdev = priv->mdev;
4769 int err;
6bfd390b 4770
1462e48d
RD		 4771 mlx5e_create_q_counters(priv);
4772
4773 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4774 if (err) {
4775 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4776 goto err_destroy_q_counters;
4777 }
4778
8f493ffd
SM		 4779 err = mlx5e_create_indirect_rqt(priv);
4780 if (err)
1462e48d 4781 goto err_close_drop_rq;
6bfd390b
HHZ		 4782
4783 err = mlx5e_create_direct_rqts(priv);
8f493ffd 4784 if (err)
6bfd390b 4785 goto err_destroy_indirect_rqts;
6bfd390b 4786
46dc933c 4787 err = mlx5e_create_indirect_tirs(priv, true);
8f493ffd 4788 if (err)
6bfd390b 4789 goto err_destroy_direct_rqts;
6bfd390b
HHZ		 4790
4791 err = mlx5e_create_direct_tirs(priv);
8f493ffd 4792 if (err)
6bfd390b 4793 goto err_destroy_indirect_tirs;
6bfd390b
HHZ		 4794
4795 err = mlx5e_create_flow_steering(priv);
4796 if (err) {
4797 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4798 goto err_destroy_direct_tirs;
4799 }
4800
655dc3d2 4801 err = mlx5e_tc_nic_init(priv);
6bfd390b
HHZ		 4802 if (err)
4803 goto err_destroy_flow_steering;
4804
4805 return 0;
4806
4807err_destroy_flow_steering:
4808 mlx5e_destroy_flow_steering(priv);
4809err_destroy_direct_tirs:
4810 mlx5e_destroy_direct_tirs(priv);
4811err_destroy_indirect_tirs:
46dc933c 4812 mlx5e_destroy_indirect_tirs(priv, true);
6bfd390b 4813err_destroy_direct_rqts:
8f493ffd 4814 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4815err_destroy_indirect_rqts:
4816 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
1462e48d
RD		 4817err_close_drop_rq:
4818 mlx5e_close_drop_rq(&priv->drop_rq);
4819err_destroy_q_counters:
4820 mlx5e_destroy_q_counters(priv);
6bfd390b
HHZ		 4821 return err;
4822}
4823
4824static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4825{
655dc3d2 4826 mlx5e_tc_nic_cleanup(priv);
6bfd390b
HHZ		 4827 mlx5e_destroy_flow_steering(priv);
4828 mlx5e_destroy_direct_tirs(priv);
46dc933c 4829 mlx5e_destroy_indirect_tirs(priv, true);
8f493ffd 4830 mlx5e_destroy_direct_rqts(priv);
6bfd390b 4831 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
1462e48d
RD		 4832 mlx5e_close_drop_rq(&priv->drop_rq);
4833 mlx5e_destroy_q_counters(priv);
6bfd390b
HHZ		 4834}
4835
4836static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4837{
4838 int err;
4839
4840 err = mlx5e_create_tises(priv);
4841 if (err) {
4842 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4843 return err;
4844 }
4845
4846#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 4847 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 4848#endif
4849 return 0;
4850}
4851
4852static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4853{
4854 struct net_device *netdev = priv->netdev;
4855 struct mlx5_core_dev *mdev = priv->mdev;
2c3b5bee
SM		 4856 u16 max_mtu;
4857
4858 mlx5e_init_l2_addr(priv);
4859
63bfd399
EBE		 4860 /* Marking the link as currently not needed by the Driver */
4861 if (!netif_running(netdev))
4862 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4863
2c3b5bee
SM		 4864 /* MTU range: 68 - hw-specific max */
4865 netdev->min_mtu = ETH_MIN_MTU;
4866 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
472a1e44 4867 netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
2c3b5bee 4868 mlx5e_set_dev_port_mtu(priv);
6bfd390b 4869
7907f23a
AH		 4870 mlx5_lag_add(mdev, netdev);
4871
6bfd390b 4872 mlx5e_enable_async_events(priv);
127ea380 4873
733d3e54 4874 if (MLX5_ESWITCH_MANAGER(priv->mdev))
1d447a39 4875 mlx5e_register_vport_reps(priv);
2c3b5bee 4876
610e89e0
SM		 4877 if (netdev->reg_state != NETREG_REGISTERED)
4878 return;
2a5e7a13
HN		 4879#ifdef CONFIG_MLX5_CORE_EN_DCB
4880 mlx5e_dcbnl_init_app(priv);
4881#endif
610e89e0
SM		 4882
4883 queue_work(priv->wq, &priv->set_rx_mode_work);
2c3b5bee
SM		 4884
4885 rtnl_lock();
4886 if (netif_running(netdev))
4887 mlx5e_open(netdev);
4888 netif_device_attach(netdev);
4889 rtnl_unlock();
6bfd390b
HHZ		 4890}
4891
4892static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4893{
3deef8ce 4894 struct mlx5_core_dev *mdev = priv->mdev;
3deef8ce 4895
2a5e7a13
HN		 4896#ifdef CONFIG_MLX5_CORE_EN_DCB
4897 if (priv->netdev->reg_state == NETREG_REGISTERED)
4898 mlx5e_dcbnl_delete_app(priv);
4899#endif
4900
2c3b5bee
SM		 4901 rtnl_lock();
4902 if (netif_running(priv->netdev))
4903 mlx5e_close(priv->netdev);
4904 netif_device_detach(priv->netdev);
4905 rtnl_unlock();
4906
6bfd390b 4907 queue_work(priv->wq, &priv->set_rx_mode_work);
1d447a39 4908
733d3e54 4909 if (MLX5_ESWITCH_MANAGER(priv->mdev))
1d447a39
SM		 4910 mlx5e_unregister_vport_reps(priv);
4911
6bfd390b 4912 mlx5e_disable_async_events(priv);
3deef8ce 4913 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 4914}
4915
4916static const struct mlx5e_profile mlx5e_nic_profile = {
4917 .init = mlx5e_nic_init,
4918 .cleanup = mlx5e_nic_cleanup,
4919 .init_rx = mlx5e_init_nic_rx,
4920 .cleanup_rx = mlx5e_cleanup_nic_rx,
4921 .init_tx = mlx5e_init_nic_tx,
4922 .cleanup_tx = mlx5e_cleanup_nic_tx,
4923 .enable = mlx5e_nic_enable,
4924 .disable = mlx5e_nic_disable,
3834a5e6 4925 .update_stats = mlx5e_update_ndo_stats,
7ca42c80 4926 .update_carrier = mlx5e_update_carrier,
20fd0c19
SM		 4927 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4928 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
6bfd390b
HHZ		 4929 .max_tc = MLX5E_MAX_NUM_TC,
4930};
4931
2c3b5bee
SM		 4932/* mlx5e generic netdev management API (move to en_common.c) */
4933
182570b2 4934/* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
519a0bf5
SM		 4935int mlx5e_netdev_init(struct net_device *netdev,
4936 struct mlx5e_priv *priv,
4937 struct mlx5_core_dev *mdev,
4938 const struct mlx5e_profile *profile,
4939 void *ppriv)
182570b2 4940{
519a0bf5
SM		 4941 /* priv init */
4942 priv->mdev = mdev;
4943 priv->netdev = netdev;
4944 priv->profile = profile;
4945 priv->ppriv = ppriv;
4946 priv->msglevel = MLX5E_MSG_LEVEL;
4947 priv->max_opened_tc = 1;
182570b2 4948
519a0bf5
SM		 4949 mutex_init(&priv->state_lock);
4950 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4951 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4952 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
cdeef2b1 4953 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
303211b4 4954
182570b2
FD		 4955 priv->wq = create_singlethread_workqueue("mlx5e");
4956 if (!priv->wq)
4957 return -ENOMEM;
4958
519a0bf5
SM		 4959 /* netdev init */
4960 netif_carrier_off(netdev);
4961
4962#ifdef CONFIG_MLX5_EN_ARFS
4963 netdev->rx_cpu_rmap = mdev->rmap;
4964#endif
4965
182570b2
FD		 4966 return 0;
4967}
4968
4969void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
4970{
4971 destroy_workqueue(priv->wq);
4972}
4973
26e59d80
MHY		 4974struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4975 const struct mlx5e_profile *profile,
779d986d 4976 int nch,
26e59d80 4977 void *ppriv)
f62b8bb8
AV		 4978{
4979 struct net_device *netdev;
182570b2 4980 int err;
f62b8bb8 4981
08fb1dac 4982 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 4983 nch * profile->max_tc,
08fb1dac 4984 nch);
f62b8bb8
AV		 4985 if (!netdev) {
4986 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4987 return NULL;
4988 }
4989
182570b2
FD		 4990 err = profile->init(mdev, netdev, profile, ppriv);
4991 if (err) {
4992 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
4993 goto err_free_netdev;
4994 }
26e59d80
MHY		 4995
4996 return netdev;
4997
182570b2 4998err_free_netdev:
26e59d80
MHY		 4999 free_netdev(netdev);
5000
5001 return NULL;
5002}
5003
2c3b5bee 5004int mlx5e_attach_netdev(struct mlx5e_priv *priv)
26e59d80
MHY		 5005{
5006 const struct mlx5e_profile *profile;
26e59d80
MHY		 5007 int err;
5008
26e59d80
MHY		 5009 profile = priv->profile;
5010 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 5011
6bfd390b
HHZ		 5012 err = profile->init_tx(priv);
5013 if (err)
ec8b9981 5014 goto out;
5c50368f 5015
6bfd390b
HHZ		 5016 err = profile->init_rx(priv);
5017 if (err)
1462e48d 5018 goto err_cleanup_tx;
5c50368f 5019
6bfd390b
HHZ		 5020 if (profile->enable)
5021 profile->enable(priv);
f62b8bb8 5022
26e59d80 5023 return 0;
5c50368f 5024
1462e48d 5025err_cleanup_tx:
6bfd390b 5026 profile->cleanup_tx(priv);
5c50368f 5027
26e59d80
MHY		 5028out:
5029 return err;
f62b8bb8
AV		 5030}
5031
2c3b5bee 5032void mlx5e_detach_netdev(struct mlx5e_priv *priv)
26e59d80 5033{
26e59d80
MHY		 5034 const struct mlx5e_profile *profile = priv->profile;
5035
5036 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80 5037
37f304d1
SM		 5038 if (profile->disable)
5039 profile->disable(priv);
5040 flush_workqueue(priv->wq);
5041
26e59d80 5042 profile->cleanup_rx(priv);
26e59d80 5043 profile->cleanup_tx(priv);
cdeef2b1 5044 cancel_work_sync(&priv->update_stats_work);
26e59d80
MHY		 5045}
5046
2c3b5bee
SM		 5047void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5048{
5049 const struct mlx5e_profile *profile = priv->profile;
5050 struct net_device *netdev = priv->netdev;
5051
2c3b5bee
SM		 5052 if (profile->cleanup)
5053 profile->cleanup(priv);
5054 free_netdev(netdev);
5055}
5056
26e59d80
MHY		 5057/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5058 * hardware contexts and to connect it to the current netdev.
5059 */
5060static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5061{
5062 struct mlx5e_priv *priv = vpriv;
5063 struct net_device *netdev = priv->netdev;
5064 int err;
5065
5066 if (netif_device_present(netdev))
5067 return 0;
5068
5069 err = mlx5e_create_mdev_resources(mdev);
5070 if (err)
5071 return err;
5072
2c3b5bee 5073 err = mlx5e_attach_netdev(priv);
26e59d80
MHY		 5074 if (err) {
5075 mlx5e_destroy_mdev_resources(mdev);
5076 return err;
5077 }
5078
5079 return 0;
5080}
5081
5082static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5083{
5084 struct mlx5e_priv *priv = vpriv;
5085 struct net_device *netdev = priv->netdev;
5086
5087 if (!netif_device_present(netdev))
5088 return;
5089
2c3b5bee 5090 mlx5e_detach_netdev(priv);
26e59d80
MHY		 5091 mlx5e_destroy_mdev_resources(mdev);
5092}
5093
b50d292b
HHZ		 5094static void *mlx5e_add(struct mlx5_core_dev *mdev)
5095{
07c9f1e5
SM		 5096 struct net_device *netdev;
5097 void *rpriv = NULL;
26e59d80 5098 void *priv;
26e59d80 5099 int err;
779d986d 5100 int nch;
b50d292b 5101
26e59d80
MHY		 5102 err = mlx5e_check_required_hca_cap(mdev);
5103 if (err)
b50d292b
HHZ		 5104 return NULL;
5105
e80541ec 5106#ifdef CONFIG_MLX5_ESWITCH
733d3e54 5107 if (MLX5_ESWITCH_MANAGER(mdev)) {
07c9f1e5 5108 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
1d447a39 5109 if (!rpriv) {
07c9f1e5 5110 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
1d447a39
SM		 5111 return NULL;
5112 }
1d447a39 5113 }
e80541ec 5114#endif
127ea380 5115
779d986d
FD		 5116 nch = mlx5e_get_max_num_channels(mdev);
5117 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, rpriv);
26e59d80
MHY		 5118 if (!netdev) {
5119 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
07c9f1e5 5120 goto err_free_rpriv;
26e59d80
MHY		 5121 }
5122
5123 priv = netdev_priv(netdev);
5124
5125 err = mlx5e_attach(mdev, priv);
5126 if (err) {
5127 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5128 goto err_destroy_netdev;
5129 }
5130
5131 err = register_netdev(netdev);
5132 if (err) {
5133 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5134 goto err_detach;
b50d292b 5135 }
26e59d80 5136
2a5e7a13
HN		 5137#ifdef CONFIG_MLX5_CORE_EN_DCB
5138 mlx5e_dcbnl_init_app(priv);
5139#endif
26e59d80
MHY		 5140 return priv;
5141
5142err_detach:
5143 mlx5e_detach(mdev, priv);
26e59d80 5144err_destroy_netdev:
2c3b5bee 5145 mlx5e_destroy_netdev(priv);
07c9f1e5 5146err_free_rpriv:
1d447a39 5147 kfree(rpriv);
26e59d80 5148 return NULL;
b50d292b
HHZ		 5149}
5150
b50d292b
HHZ		 5151static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5152{
5153 struct mlx5e_priv *priv = vpriv;
1d447a39 5154 void *ppriv = priv->ppriv;
127ea380 5155
2a5e7a13
HN		 5156#ifdef CONFIG_MLX5_CORE_EN_DCB
5157 mlx5e_dcbnl_delete_app(priv);
5158#endif
5e1e93c7 5159 unregister_netdev(priv->netdev);
26e59d80 5160 mlx5e_detach(mdev, vpriv);
2c3b5bee 5161 mlx5e_destroy_netdev(priv);
1d447a39 5162 kfree(ppriv);
b50d292b
HHZ		 5163}
5164
f62b8bb8
AV		 5165static void *mlx5e_get_netdev(void *vpriv)
5166{
5167 struct mlx5e_priv *priv = vpriv;
5168
5169 return priv->netdev;
5170}
5171
5172static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 5173 .add = mlx5e_add,
5174 .remove = mlx5e_remove,
26e59d80
MHY		 5175 .attach = mlx5e_attach,
5176 .detach = mlx5e_detach,
f62b8bb8
AV		 5177 .event = mlx5e_async_event,
5178 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
5179 .get_dev = mlx5e_get_netdev,
5180};
5181
5182void mlx5e_init(void)
5183{
2ac9cfe7 5184 mlx5e_ipsec_build_inverse_table();
665bc539 5185 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 5186 mlx5_register_interface(&mlx5e_interface);
5187}
5188
5189void mlx5e_cleanup(void)
5190{
5191 mlx5_unregister_interface(&mlx5e_interface);
5192}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git