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net/mlx5e: Use no-offset function in skb header copy
[thirdparty/kernel/stable.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
1d447a39 38#include "eswitch.h"
f62b8bb8 39#include "en.h"
e8f887ac 40#include "en_tc.h"
1d447a39 41#include "en_rep.h"
547eede0 42#include "en_accel/ipsec.h"
899a59d3
IT		 43#include "en_accel/ipsec_rxtx.h"
44#include "accel/ipsec.h"
b3f63c3d 45#include "vxlan.h"
f62b8bb8
AV		 46
47struct mlx5e_rq_param {
cb3c7fd4
GR		 48 u32 rqc[MLX5_ST_SZ_DW(rqc)];
49 struct mlx5_wq_param wq;
f62b8bb8
AV		 50};
51
52struct mlx5e_sq_param {
53 u32 sqc[MLX5_ST_SZ_DW(sqc)];
54 struct mlx5_wq_param wq;
55};
56
57struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
9908aa29 61 u8 cq_period_mode;
f62b8bb8
AV		 62};
63
64struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
b5503b99 67 struct mlx5e_sq_param xdp_sq;
d3c9bc27 68 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
d3c9bc27 71 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 72};
73
2fc4bfb7
SM		 74static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75{
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
79}
80
696a97cf
EE		 81void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
82 struct mlx5e_params *params, u8 rq_type)
2fc4bfb7 83{
6a9764ef
SM		 84 params->rq_wq_type = rq_type;
85 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
86 switch (params->rq_wq_type) {
2fc4bfb7 87 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 88 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 89 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
90 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
696a97cf
EE		 91 params->mpwqe_log_stride_sz = MLX5E_MPWQE_STRIDE_SZ(mdev,
92 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
6a9764ef
SM		 93 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
94 params->mpwqe_log_stride_sz;
2fc4bfb7
SM		 95 break;
96 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 97 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 98 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
99 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
bce2b2bf
TT		 100 params->rq_headroom = params->xdp_prog ?
101 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
102 params->rq_headroom += NET_IP_ALIGN;
4078e637
TT		 103
104 /* Extra room needed for build_skb */
bce2b2bf 105 params->lro_wqe_sz -= params->rq_headroom +
4078e637 106 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2fc4bfb7 107 }
2fc4bfb7 108
6a9764ef
SM		 109 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
110 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
111 BIT(params->log_rq_size),
112 BIT(params->mpwqe_log_stride_sz),
113 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 114}
115
291f445e
TT		 116static bool slow_pci_heuristic(struct mlx5_core_dev *mdev);
117
696a97cf
EE		 118static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev,
119 struct mlx5e_params *params)
2fc4bfb7 120{
6a9764ef 121 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
291f445e
TT		 122 !slow_pci_heuristic(mdev) &&
123 !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
124 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
125 MLX5_WQ_TYPE_LINKED_LIST;
696a97cf 126 mlx5e_init_rq_type_params(mdev, params, rq_type);
2fc4bfb7
SM		 127}
128
f62b8bb8
AV		 129static void mlx5e_update_carrier(struct mlx5e_priv *priv)
130{
131 struct mlx5_core_dev *mdev = priv->mdev;
132 u8 port_state;
133
134 port_state = mlx5_query_vport_state(mdev,
e53eef63
OG		 135 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
136 0);
f62b8bb8 137
87424ad5
SD		 138 if (port_state == VPORT_STATE_UP) {
139 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 140 netif_carrier_on(priv->netdev);
87424ad5
SD		 141 } else {
142 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 143 netif_carrier_off(priv->netdev);
87424ad5 144 }
f62b8bb8
AV		 145}
146
147static void mlx5e_update_carrier_work(struct work_struct *work)
148{
149 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
150 update_carrier_work);
151
152 mutex_lock(&priv->state_lock);
153 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
7ca42c80
ES		 154 if (priv->profile->update_carrier)
155 priv->profile->update_carrier(priv);
f62b8bb8
AV		 156 mutex_unlock(&priv->state_lock);
157}
158
3947ca18
DJ		 159static void mlx5e_tx_timeout_work(struct work_struct *work)
160{
161 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
162 tx_timeout_work);
163 int err;
164
165 rtnl_lock();
166 mutex_lock(&priv->state_lock);
167 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
168 goto unlock;
169 mlx5e_close_locked(priv->netdev);
170 err = mlx5e_open_locked(priv->netdev);
171 if (err)
172 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
173 err);
174unlock:
175 mutex_unlock(&priv->state_lock);
176 rtnl_unlock();
177}
178
19386177 179void mlx5e_update_stats(struct mlx5e_priv *priv)
f62b8bb8 180{
19386177 181 int i;
f62b8bb8 182
19386177
KH		 183 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
184 if (mlx5e_stats_grps[i].update_stats)
185 mlx5e_stats_grps[i].update_stats(priv);
f62b8bb8
AV		 186}
187
3834a5e6
GP		 188static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
189{
19386177
KH		 190 int i;
191
192 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
193 if (mlx5e_stats_grps[i].update_stats_mask &
194 MLX5E_NDO_UPDATE_STATS)
195 mlx5e_stats_grps[i].update_stats(priv);
3834a5e6
GP		 196}
197
cb67b832 198void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 199{
200 struct delayed_work *dwork = to_delayed_work(work);
201 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
202 update_stats_work);
203 mutex_lock(&priv->state_lock);
204 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 205 priv->profile->update_stats(priv);
7bb29755
MF		 206 queue_delayed_work(priv->wq, dwork,
207 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 208 }
209 mutex_unlock(&priv->state_lock);
210}
211
daa21560
TT		 212static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
213 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 214{
daa21560
TT		 215 struct mlx5e_priv *priv = vpriv;
216
e0f46eb9 217 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 218 return;
219
f62b8bb8
AV		 220 switch (event) {
221 case MLX5_DEV_EVENT_PORT_UP:
222 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 223 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 224 break;
f62b8bb8
AV		 225 default:
226 break;
227 }
228}
229
f62b8bb8
AV		 230static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
231{
e0f46eb9 232 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 233}
234
235static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
236{
e0f46eb9 237 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
78249c42 238 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 239}
240
7e426671
TT		 241static inline int mlx5e_get_wqe_mtt_sz(void)
242{
243 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
244 * To avoid copying garbage after the mtt array, we allocate
245 * a little more.
246 */
247 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
248 MLX5_UMR_MTT_ALIGNMENT);
249}
250
31391048
SM		 251static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
252 struct mlx5e_icosq *sq,
253 struct mlx5e_umr_wqe *wqe,
254 u16 ix)
7e426671
TT		 255{
256 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
257 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
258 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 259 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 260 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
261 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
262
263 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
264 ds_cnt);
265 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
266 cseg->imm = rq->mkey_be;
267
268 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
31616255 269 ucseg->xlt_octowords =
7e426671
TT		 270 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
271 ucseg->bsf_octowords =
272 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
273 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
274
275 dseg->lkey = sq->mkey_be;
276 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
277}
278
279static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
280 struct mlx5e_channel *c)
281{
282 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
283 int mtt_sz = mlx5e_get_wqe_mtt_sz();
284 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
285 int i;
286
21c59685 287 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
231243c8 288 GFP_KERNEL, cpu_to_node(c->cpu));
21c59685 289 if (!rq->mpwqe.info)
7e426671
TT		 290 goto err_out;
291
292 /* We allocate more than mtt_sz as we will align the pointer */
231243c8
SM		 293 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
294 cpu_to_node(c->cpu));
21c59685 295 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 296 goto err_free_wqe_info;
297
298 for (i = 0; i < wq_sz; i++) {
21c59685 299 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 300
21c59685 301 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 302 MLX5_UMR_ALIGN);
303 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
304 PCI_DMA_TODEVICE);
305 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
306 goto err_unmap_mtts;
307
308 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
309 }
310
311 return 0;
312
313err_unmap_mtts:
314 while (--i >= 0) {
21c59685 315 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 316
317 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
318 PCI_DMA_TODEVICE);
319 }
21c59685 320 kfree(rq->mpwqe.mtt_no_align);
7e426671 321err_free_wqe_info:
21c59685 322 kfree(rq->mpwqe.info);
7e426671
TT		 323
324err_out:
325 return -ENOMEM;
326}
327
328static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
329{
330 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
331 int mtt_sz = mlx5e_get_wqe_mtt_sz();
332 int i;
333
334 for (i = 0; i < wq_sz; i++) {
21c59685 335 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 336
337 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
338 PCI_DMA_TODEVICE);
339 }
21c59685
SM		 340 kfree(rq->mpwqe.mtt_no_align);
341 kfree(rq->mpwqe.info);
7e426671
TT		 342}
343
a43b25da 344static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
ec8b9981
TT		 345 u64 npages, u8 page_shift,
346 struct mlx5_core_mkey *umr_mkey)
3608ae77 347{
3608ae77
TT		 348 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
349 void *mkc;
350 u32 *in;
351 int err;
352
ec8b9981
TT		 353 if (!MLX5E_VALID_NUM_MTTS(npages))
354 return -EINVAL;
355
1b9a07ee 356 in = kvzalloc(inlen, GFP_KERNEL);
3608ae77
TT		 357 if (!in)
358 return -ENOMEM;
359
360 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
361
3608ae77
TT		 362 MLX5_SET(mkc, mkc, free, 1);
363 MLX5_SET(mkc, mkc, umr_en, 1);
364 MLX5_SET(mkc, mkc, lw, 1);
365 MLX5_SET(mkc, mkc, lr, 1);
366 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
367
368 MLX5_SET(mkc, mkc, qpn, 0xffffff);
369 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 370 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 371 MLX5_SET(mkc, mkc, translations_octword_size,
372 MLX5_MTT_OCTW(npages));
ec8b9981 373 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 374
ec8b9981 375 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 376
377 kvfree(in);
378 return err;
379}
380
a43b25da 381static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
ec8b9981 382{
6a9764ef 383 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
ec8b9981 384
a43b25da 385 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
ec8b9981
TT		 386}
387
3b77235b 388static int mlx5e_alloc_rq(struct mlx5e_channel *c,
6a9764ef
SM		 389 struct mlx5e_params *params,
390 struct mlx5e_rq_param *rqp,
3b77235b 391 struct mlx5e_rq *rq)
f62b8bb8 392{
a43b25da 393 struct mlx5_core_dev *mdev = c->mdev;
6a9764ef 394 void *rqc = rqp->rqc;
f62b8bb8 395 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 396 u32 byte_count;
1bfecfca 397 int npages;
f62b8bb8
AV		 398 int wq_sz;
399 int err;
400 int i;
401
231243c8 402 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
311c7c71 403
6a9764ef 404 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
f62b8bb8
AV		 405 &rq->wq_ctrl);
406 if (err)
407 return err;
408
409 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
410
411 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 412
6a9764ef 413 rq->wq_type = params->rq_wq_type;
7e426671
TT		 414 rq->pdev = c->pdev;
415 rq->netdev = c->netdev;
a43b25da 416 rq->tstamp = c->tstamp;
7c39afb3 417 rq->clock = &mdev->clock;
7e426671
TT		 418 rq->channel = c;
419 rq->ix = c->ix;
a43b25da 420 rq->mdev = mdev;
97bc402d 421
6a9764ef 422 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
97bc402d
DB		 423 if (IS_ERR(rq->xdp_prog)) {
424 err = PTR_ERR(rq->xdp_prog);
425 rq->xdp_prog = NULL;
426 goto err_rq_wq_destroy;
427 }
7e426671 428
e213f5b6
WY		 429 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
430 if (err < 0)
0ddf5432
JDB		 431 goto err_rq_wq_destroy;
432
bce2b2bf 433 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
b45d8b50 434 rq->buff.headroom = params->rq_headroom;
b5503b99 435
6a9764ef 436 switch (rq->wq_type) {
461017cb 437 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476 438
7cc6d77b 439 rq->post_wqes = mlx5e_post_rx_mpwqes;
6cd392a0 440 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 441
20fd0c19 442 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
899a59d3
IT		 443#ifdef CONFIG_MLX5_EN_IPSEC
444 if (MLX5_IPSEC_DEV(mdev)) {
445 err = -EINVAL;
446 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
447 goto err_rq_wq_destroy;
448 }
449#endif
20fd0c19
SM		 450 if (!rq->handle_rx_cqe) {
451 err = -EINVAL;
452 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
453 goto err_rq_wq_destroy;
454 }
455
89e89f7a 456 rq->mpwqe.log_stride_sz = params->mpwqe_log_stride_sz;
b45d8b50 457 rq->mpwqe.num_strides = BIT(params->mpwqe_log_num_strides);
1bfecfca 458
b681c481 459 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
ec8b9981 460
a43b25da 461 err = mlx5e_create_rq_umr_mkey(mdev, rq);
7e426671
TT		 462 if (err)
463 goto err_rq_wq_destroy;
ec8b9981
TT		 464 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
465
466 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
467 if (err)
468 goto err_destroy_umr_mkey;
461017cb
TT		 469 break;
470 default: /* MLX5_WQ_TYPE_LINKED_LIST */
accd5883
TT		 471 rq->wqe.frag_info =
472 kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
231243c8 473 GFP_KERNEL, cpu_to_node(c->cpu));
accd5883 474 if (!rq->wqe.frag_info) {
461017cb
TT		 475 err = -ENOMEM;
476 goto err_rq_wq_destroy;
477 }
7cc6d77b 478 rq->post_wqes = mlx5e_post_rx_wqes;
6cd392a0 479 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 480
899a59d3
IT		 481#ifdef CONFIG_MLX5_EN_IPSEC
482 if (c->priv->ipsec)
483 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
484 else
485#endif
486 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
20fd0c19 487 if (!rq->handle_rx_cqe) {
accd5883 488 kfree(rq->wqe.frag_info);
20fd0c19
SM		 489 err = -EINVAL;
490 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
491 goto err_rq_wq_destroy;
492 }
493
b681c481 494 byte_count = params->lro_en ?
6a9764ef 495 params->lro_wqe_sz :
c139dbfd 496 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
899a59d3
IT		 497#ifdef CONFIG_MLX5_EN_IPSEC
498 if (MLX5_IPSEC_DEV(mdev))
b681c481 499 byte_count += MLX5E_METADATA_ETHER_LEN;
899a59d3 500#endif
accd5883 501 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
1bfecfca
SM		 502
503 /* calc the required page order */
b45d8b50 504 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
accd5883 505 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
1bfecfca
SM		 506 rq->buff.page_order = order_base_2(npages);
507
461017cb 508 byte_count |= MLX5_HW_START_PADDING;
7e426671 509 rq->mkey_be = c->mkey_be;
461017cb 510 }
f62b8bb8
AV		 511
512 for (i = 0; i < wq_sz; i++) {
513 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
514
4c2af5cc
TT		 515 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
516 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT;
517
518 wqe->data.addr = cpu_to_be64(dma_offset);
519 }
520
461017cb 521 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 522 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 523 }
524
9a317425
AG		 525 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
526
527 switch (params->rx_cq_moderation.cq_period_mode) {
528 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
529 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
530 break;
531 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
532 default:
533 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
534 }
535
4415a031
TT		 536 rq->page_cache.head = 0;
537 rq->page_cache.tail = 0;
538
f62b8bb8
AV		 539 return 0;
540
ec8b9981
TT		 541err_destroy_umr_mkey:
542 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
543
f62b8bb8 544err_rq_wq_destroy:
97bc402d
DB		 545 if (rq->xdp_prog)
546 bpf_prog_put(rq->xdp_prog);
0ddf5432 547 xdp_rxq_info_unreg(&rq->xdp_rxq);
f62b8bb8
AV		 548 mlx5_wq_destroy(&rq->wq_ctrl);
549
550 return err;
551}
552
3b77235b 553static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 554{
4415a031
TT		 555 int i;
556
86994156
RS		 557 if (rq->xdp_prog)
558 bpf_prog_put(rq->xdp_prog);
559
0ddf5432
JDB		 560 xdp_rxq_info_unreg(&rq->xdp_rxq);
561
461017cb
TT		 562 switch (rq->wq_type) {
563 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 564 mlx5e_rq_free_mpwqe_info(rq);
a43b25da 565 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
461017cb
TT		 566 break;
567 default: /* MLX5_WQ_TYPE_LINKED_LIST */
accd5883 568 kfree(rq->wqe.frag_info);
461017cb
TT		 569 }
570
4415a031
TT		 571 for (i = rq->page_cache.head; i != rq->page_cache.tail;
572 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
573 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
574
575 mlx5e_page_release(rq, dma_info, false);
576 }
f62b8bb8
AV		 577 mlx5_wq_destroy(&rq->wq_ctrl);
578}
579
6a9764ef
SM		 580static int mlx5e_create_rq(struct mlx5e_rq *rq,
581 struct mlx5e_rq_param *param)
f62b8bb8 582{
a43b25da 583 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 584
585 void *in;
586 void *rqc;
587 void *wq;
588 int inlen;
589 int err;
590
591 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
592 sizeof(u64) * rq->wq_ctrl.buf.npages;
1b9a07ee 593 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 594 if (!in)
595 return -ENOMEM;
596
597 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
598 wq = MLX5_ADDR_OF(rqc, rqc, wq);
599
600 memcpy(rqc, param->rqc, sizeof(param->rqc));
601
97de9f31 602 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 603 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
f62b8bb8 604 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 605 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 606 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
607
608 mlx5_fill_page_array(&rq->wq_ctrl.buf,
609 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
610
7db22ffb 611 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 612
613 kvfree(in);
614
615 return err;
616}
617
36350114
GP		 618static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
619 int next_state)
f62b8bb8 620{
7cbaf9a3 621 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 622
623 void *in;
624 void *rqc;
625 int inlen;
626 int err;
627
628 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 629 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 630 if (!in)
631 return -ENOMEM;
632
633 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
634
635 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
636 MLX5_SET(rqc, rqc, state, next_state);
637
7db22ffb 638 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 639
640 kvfree(in);
641
642 return err;
643}
644
102722fc
GE		 645static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
646{
647 struct mlx5e_channel *c = rq->channel;
648 struct mlx5e_priv *priv = c->priv;
649 struct mlx5_core_dev *mdev = priv->mdev;
650
651 void *in;
652 void *rqc;
653 int inlen;
654 int err;
655
656 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 657 in = kvzalloc(inlen, GFP_KERNEL);
102722fc
GE		 658 if (!in)
659 return -ENOMEM;
660
661 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
662
663 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
664 MLX5_SET64(modify_rq_in, in, modify_bitmask,
665 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
666 MLX5_SET(rqc, rqc, scatter_fcs, enable);
667 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
668
669 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
670
671 kvfree(in);
672
673 return err;
674}
675
36350114
GP		 676static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
677{
678 struct mlx5e_channel *c = rq->channel;
a43b25da 679 struct mlx5_core_dev *mdev = c->mdev;
36350114
GP		 680 void *in;
681 void *rqc;
682 int inlen;
683 int err;
684
685 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 686 in = kvzalloc(inlen, GFP_KERNEL);
36350114
GP		 687 if (!in)
688 return -ENOMEM;
689
690 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
691
692 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 693 MLX5_SET64(modify_rq_in, in, modify_bitmask,
694 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 695 MLX5_SET(rqc, rqc, vsd, vsd);
696 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
697
698 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
699
700 kvfree(in);
701
702 return err;
703}
704
3b77235b 705static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 706{
a43b25da 707 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
f62b8bb8
AV		 708}
709
710static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
711{
01c196a2 712 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8 713 struct mlx5e_channel *c = rq->channel;
a43b25da 714
f62b8bb8 715 struct mlx5_wq_ll *wq = &rq->wq;
6a9764ef 716 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
f62b8bb8 717
01c196a2 718 while (time_before(jiffies, exp_time)) {
6a9764ef 719 if (wq->cur_sz >= min_wqes)
f62b8bb8
AV		 720 return 0;
721
722 msleep(20);
723 }
724
a43b25da 725 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
6a9764ef 726 rq->rqn, wq->cur_sz, min_wqes);
f62b8bb8
AV		 727 return -ETIMEDOUT;
728}
729
f2fde18c
SM		 730static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
731{
732 struct mlx5_wq_ll *wq = &rq->wq;
733 struct mlx5e_rx_wqe *wqe;
734 __be16 wqe_ix_be;
735 u16 wqe_ix;
736
8484f9ed 737 /* UMR WQE (if in progress) is always at wq->head */
a071cb9f
TT		 738 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
739 rq->mpwqe.umr_in_progress)
21c59685 740 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 741
f2fde18c
SM		 742 while (!mlx5_wq_ll_is_empty(wq)) {
743 wqe_ix_be = *wq->tail_next;
744 wqe_ix = be16_to_cpu(wqe_ix_be);
745 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
746 rq->dealloc_wqe(rq, wqe_ix);
747 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
748 &wqe->next.next_wqe_index);
749 }
accd5883
TT		 750
751 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
752 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
753 * but yet to be re-posted.
754 */
755 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
756
757 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
758 rq->dealloc_wqe(rq, wqe_ix);
759 }
f2fde18c
SM		 760}
761
f62b8bb8 762static int mlx5e_open_rq(struct mlx5e_channel *c,
6a9764ef 763 struct mlx5e_params *params,
f62b8bb8
AV		 764 struct mlx5e_rq_param *param,
765 struct mlx5e_rq *rq)
766{
767 int err;
768
6a9764ef 769 err = mlx5e_alloc_rq(c, params, param, rq);
f62b8bb8
AV		 770 if (err)
771 return err;
772
3b77235b 773 err = mlx5e_create_rq(rq, param);
f62b8bb8 774 if (err)
3b77235b 775 goto err_free_rq;
f62b8bb8 776
36350114 777 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 778 if (err)
3b77235b 779 goto err_destroy_rq;
f62b8bb8 780
9a317425 781 if (params->rx_dim_enabled)
a1eaba4c 782 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
cb3c7fd4 783
f62b8bb8
AV		 784 return 0;
785
f62b8bb8
AV		 786err_destroy_rq:
787 mlx5e_destroy_rq(rq);
3b77235b
SM		 788err_free_rq:
789 mlx5e_free_rq(rq);
f62b8bb8
AV		 790
791 return err;
792}
793
acc6c595
SM		 794static void mlx5e_activate_rq(struct mlx5e_rq *rq)
795{
796 struct mlx5e_icosq *sq = &rq->channel->icosq;
797 u16 pi = sq->pc & sq->wq.sz_m1;
798 struct mlx5e_tx_wqe *nopwqe;
799
800 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
801 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
acc6c595
SM		 802 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
803 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
804}
805
806static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
f62b8bb8 807{
c0f1147d 808 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 809 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
acc6c595 810}
cb3c7fd4 811
acc6c595
SM		 812static void mlx5e_close_rq(struct mlx5e_rq *rq)
813{
9a317425 814 cancel_work_sync(&rq->dim.work);
f62b8bb8 815 mlx5e_destroy_rq(rq);
3b77235b
SM		 816 mlx5e_free_rx_descs(rq);
817 mlx5e_free_rq(rq);
f62b8bb8
AV		 818}
819
31391048 820static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
b5503b99 821{
31391048 822 kfree(sq->db.di);
b5503b99
SM		 823}
824
31391048 825static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
b5503b99
SM		 826{
827 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
828
31391048 829 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
b5503b99 830 GFP_KERNEL, numa);
31391048
SM		 831 if (!sq->db.di) {
832 mlx5e_free_xdpsq_db(sq);
b5503b99
SM		 833 return -ENOMEM;
834 }
835
836 return 0;
837}
838
31391048 839static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
6a9764ef 840 struct mlx5e_params *params,
31391048
SM		 841 struct mlx5e_sq_param *param,
842 struct mlx5e_xdpsq *sq)
843{
844 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 845 struct mlx5_core_dev *mdev = c->mdev;
31391048
SM		 846 int err;
847
848 sq->pdev = c->pdev;
849 sq->mkey_be = c->mkey_be;
850 sq->channel = c;
851 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 852 sq->min_inline_mode = params->tx_min_inline_mode;
31391048 853
231243c8 854 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048
SM		 855 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
856 if (err)
857 return err;
858 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
859
231243c8 860 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
31391048
SM		 861 if (err)
862 goto err_sq_wq_destroy;
863
864 return 0;
865
866err_sq_wq_destroy:
867 mlx5_wq_destroy(&sq->wq_ctrl);
868
869 return err;
870}
871
872static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
873{
874 mlx5e_free_xdpsq_db(sq);
875 mlx5_wq_destroy(&sq->wq_ctrl);
876}
877
878static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
f62b8bb8 879{
f10b7cc7 880 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 881}
882
31391048 883static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
f10b7cc7
SM		 884{
885 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
886
887 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
888 GFP_KERNEL, numa);
889 if (!sq->db.ico_wqe)
890 return -ENOMEM;
891
892 return 0;
893}
894
31391048 895static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
31391048
SM		 896 struct mlx5e_sq_param *param,
897 struct mlx5e_icosq *sq)
f10b7cc7 898{
31391048 899 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 900 struct mlx5_core_dev *mdev = c->mdev;
31391048 901 int err;
f10b7cc7 902
31391048
SM		 903 sq->mkey_be = c->mkey_be;
904 sq->channel = c;
905 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f62b8bb8 906
231243c8 907 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048
SM		 908 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
909 if (err)
910 return err;
911 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 912
231243c8 913 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
31391048
SM		 914 if (err)
915 goto err_sq_wq_destroy;
916
917 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
f62b8bb8
AV		 918
919 return 0;
31391048
SM		 920
921err_sq_wq_destroy:
922 mlx5_wq_destroy(&sq->wq_ctrl);
923
924 return err;
f62b8bb8
AV		 925}
926
31391048 927static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
f10b7cc7 928{
31391048
SM		 929 mlx5e_free_icosq_db(sq);
930 mlx5_wq_destroy(&sq->wq_ctrl);
f10b7cc7
SM		 931}
932
31391048 933static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
f10b7cc7 934{
31391048
SM		 935 kfree(sq->db.wqe_info);
936 kfree(sq->db.dma_fifo);
f10b7cc7
SM		 937}
938
31391048 939static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
b5503b99 940{
31391048
SM		 941 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
942 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
943
31391048
SM		 944 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
945 GFP_KERNEL, numa);
946 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
947 GFP_KERNEL, numa);
77bdf895 948 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
31391048
SM		 949 mlx5e_free_txqsq_db(sq);
950 return -ENOMEM;
b5503b99 951 }
31391048
SM		 952
953 sq->dma_fifo_mask = df_sz - 1;
954
955 return 0;
b5503b99
SM		 956}
957
31391048 958static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
acc6c595 959 int txq_ix,
6a9764ef 960 struct mlx5e_params *params,
31391048
SM		 961 struct mlx5e_sq_param *param,
962 struct mlx5e_txqsq *sq)
f62b8bb8 963{
31391048 964 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 965 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 966 int err;
967
f10b7cc7 968 sq->pdev = c->pdev;
a43b25da 969 sq->tstamp = c->tstamp;
7c39afb3 970 sq->clock = &mdev->clock;
f10b7cc7
SM		 971 sq->mkey_be = c->mkey_be;
972 sq->channel = c;
acc6c595 973 sq->txq_ix = txq_ix;
aff26157 974 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef
SM		 975 sq->max_inline = params->tx_max_inline;
976 sq->min_inline_mode = params->tx_min_inline_mode;
2ac9cfe7
IT		 977 if (MLX5_IPSEC_DEV(c->priv->mdev))
978 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
f10b7cc7 979
231243c8 980 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048 981 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
f62b8bb8 982 if (err)
aff26157 983 return err;
31391048 984 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 985
231243c8 986 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
7ec0bb22 987 if (err)
f62b8bb8
AV		 988 goto err_sq_wq_destroy;
989
31391048 990 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
f62b8bb8
AV		 991
992 return 0;
993
994err_sq_wq_destroy:
995 mlx5_wq_destroy(&sq->wq_ctrl);
996
f62b8bb8
AV		 997 return err;
998}
999
31391048 1000static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1001{
31391048 1002 mlx5e_free_txqsq_db(sq);
f62b8bb8 1003 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1004}
1005
33ad9711
SM		 1006struct mlx5e_create_sq_param {
1007 struct mlx5_wq_ctrl *wq_ctrl;
1008 u32 cqn;
1009 u32 tisn;
1010 u8 tis_lst_sz;
1011 u8 min_inline_mode;
1012};
1013
a43b25da 1014static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
33ad9711
SM		 1015 struct mlx5e_sq_param *param,
1016 struct mlx5e_create_sq_param *csp,
1017 u32 *sqn)
f62b8bb8 1018{
f62b8bb8
AV		 1019 void *in;
1020 void *sqc;
1021 void *wq;
1022 int inlen;
1023 int err;
1024
1025 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
33ad9711 1026 sizeof(u64) * csp->wq_ctrl->buf.npages;
1b9a07ee 1027 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1028 if (!in)
1029 return -ENOMEM;
1030
1031 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1032 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1033
1034 memcpy(sqc, param->sqc, sizeof(param->sqc));
33ad9711
SM		 1035 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1036 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1037 MLX5_SET(sqc, sqc, cqn, csp->cqn);
a6f402e4
SM		 1038
1039 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
33ad9711 1040 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
a6f402e4 1041
33ad9711 1042 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f62b8bb8
AV		 1043
1044 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
a43b25da 1045 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
33ad9711 1046 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
68cdf5d6 1047 MLX5_ADAPTER_PAGE_SHIFT);
33ad9711 1048 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
f62b8bb8 1049
33ad9711 1050 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 1051
33ad9711 1052 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
f62b8bb8
AV		 1053
1054 kvfree(in);
1055
1056 return err;
1057}
1058
33ad9711
SM		 1059struct mlx5e_modify_sq_param {
1060 int curr_state;
1061 int next_state;
1062 bool rl_update;
1063 int rl_index;
1064};
1065
a43b25da 1066static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
33ad9711 1067 struct mlx5e_modify_sq_param *p)
f62b8bb8 1068{
f62b8bb8
AV		 1069 void *in;
1070 void *sqc;
1071 int inlen;
1072 int err;
1073
1074 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 1075 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1076 if (!in)
1077 return -ENOMEM;
1078
1079 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1080
33ad9711
SM		 1081 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1082 MLX5_SET(sqc, sqc, state, p->next_state);
1083 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
507f0c81 1084 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
33ad9711 1085 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
507f0c81 1086 }
f62b8bb8 1087
33ad9711 1088 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
f62b8bb8
AV		 1089
1090 kvfree(in);
1091
1092 return err;
1093}
1094
a43b25da 1095static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
33ad9711 1096{
a43b25da 1097 mlx5_core_destroy_sq(mdev, sqn);
f62b8bb8
AV		 1098}
1099
a43b25da 1100static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
31391048
SM		 1101 struct mlx5e_sq_param *param,
1102 struct mlx5e_create_sq_param *csp,
1103 u32 *sqn)
f62b8bb8 1104{
33ad9711 1105 struct mlx5e_modify_sq_param msp = {0};
31391048
SM		 1106 int err;
1107
a43b25da 1108 err = mlx5e_create_sq(mdev, param, csp, sqn);
31391048
SM		 1109 if (err)
1110 return err;
1111
1112 msp.curr_state = MLX5_SQC_STATE_RST;
1113 msp.next_state = MLX5_SQC_STATE_RDY;
a43b25da 1114 err = mlx5e_modify_sq(mdev, *sqn, &msp);
31391048 1115 if (err)
a43b25da 1116 mlx5e_destroy_sq(mdev, *sqn);
31391048
SM		 1117
1118 return err;
1119}
1120
7f859ecf
SM		 1121static int mlx5e_set_sq_maxrate(struct net_device *dev,
1122 struct mlx5e_txqsq *sq, u32 rate);
1123
31391048 1124static int mlx5e_open_txqsq(struct mlx5e_channel *c,
a43b25da 1125 u32 tisn,
acc6c595 1126 int txq_ix,
6a9764ef 1127 struct mlx5e_params *params,
31391048
SM		 1128 struct mlx5e_sq_param *param,
1129 struct mlx5e_txqsq *sq)
1130{
1131 struct mlx5e_create_sq_param csp = {};
7f859ecf 1132 u32 tx_rate;
f62b8bb8
AV		 1133 int err;
1134
6a9764ef 1135 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
f62b8bb8
AV		 1136 if (err)
1137 return err;
1138
a43b25da 1139 csp.tisn = tisn;
31391048 1140 csp.tis_lst_sz = 1;
33ad9711
SM		 1141 csp.cqn = sq->cq.mcq.cqn;
1142 csp.wq_ctrl = &sq->wq_ctrl;
1143 csp.min_inline_mode = sq->min_inline_mode;
a43b25da 1144 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
f62b8bb8 1145 if (err)
31391048 1146 goto err_free_txqsq;
f62b8bb8 1147
a43b25da 1148 tx_rate = c->priv->tx_rates[sq->txq_ix];
7f859ecf 1149 if (tx_rate)
a43b25da 1150 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
7f859ecf 1151
f62b8bb8
AV		 1152 return 0;
1153
31391048 1154err_free_txqsq:
3b77235b 1155 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
31391048 1156 mlx5e_free_txqsq(sq);
f62b8bb8
AV		 1157
1158 return err;
1159}
1160
acc6c595
SM		 1161static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1162{
a43b25da 1163 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
acc6c595
SM		 1164 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1165 netdev_tx_reset_queue(sq->txq);
1166 netif_tx_start_queue(sq->txq);
1167}
1168
f62b8bb8
AV		 1169static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1170{
1171 __netif_tx_lock_bh(txq);
1172 netif_tx_stop_queue(txq);
1173 __netif_tx_unlock_bh(txq);
1174}
1175
acc6c595 1176static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1177{
33ad9711 1178 struct mlx5e_channel *c = sq->channel;
33ad9711 1179
c0f1147d 1180 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6 1181 /* prevent netif_tx_wake_queue */
33ad9711 1182 napi_synchronize(&c->napi);
29429f33 1183
31391048 1184 netif_tx_disable_queue(sq->txq);
f62b8bb8 1185
31391048
SM		 1186 /* last doorbell out, godspeed .. */
1187 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1188 struct mlx5e_tx_wqe *nop;
864b2d71 1189
77bdf895 1190 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
31391048
SM		 1191 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1192 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
29429f33 1193 }
acc6c595
SM		 1194}
1195
1196static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1197{
1198 struct mlx5e_channel *c = sq->channel;
a43b25da 1199 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1200
a43b25da 1201 mlx5e_destroy_sq(mdev, sq->sqn);
33ad9711
SM		 1202 if (sq->rate_limit)
1203 mlx5_rl_remove_rate(mdev, sq->rate_limit);
31391048
SM		 1204 mlx5e_free_txqsq_descs(sq);
1205 mlx5e_free_txqsq(sq);
1206}
1207
1208static int mlx5e_open_icosq(struct mlx5e_channel *c,
6a9764ef 1209 struct mlx5e_params *params,
31391048
SM		 1210 struct mlx5e_sq_param *param,
1211 struct mlx5e_icosq *sq)
1212{
1213 struct mlx5e_create_sq_param csp = {};
1214 int err;
1215
6a9764ef 1216 err = mlx5e_alloc_icosq(c, param, sq);
31391048
SM		 1217 if (err)
1218 return err;
1219
1220 csp.cqn = sq->cq.mcq.cqn;
1221 csp.wq_ctrl = &sq->wq_ctrl;
6a9764ef 1222 csp.min_inline_mode = params->tx_min_inline_mode;
31391048 1223 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1224 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1225 if (err)
1226 goto err_free_icosq;
1227
1228 return 0;
1229
1230err_free_icosq:
1231 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1232 mlx5e_free_icosq(sq);
1233
1234 return err;
1235}
1236
1237static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1238{
1239 struct mlx5e_channel *c = sq->channel;
1240
1241 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1242 napi_synchronize(&c->napi);
1243
a43b25da 1244 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1245 mlx5e_free_icosq(sq);
1246}
1247
1248static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
6a9764ef 1249 struct mlx5e_params *params,
31391048
SM		 1250 struct mlx5e_sq_param *param,
1251 struct mlx5e_xdpsq *sq)
1252{
1253 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1254 struct mlx5e_create_sq_param csp = {};
31391048
SM		 1255 unsigned int inline_hdr_sz = 0;
1256 int err;
1257 int i;
1258
6a9764ef 1259 err = mlx5e_alloc_xdpsq(c, params, param, sq);
31391048
SM		 1260 if (err)
1261 return err;
1262
1263 csp.tis_lst_sz = 1;
a43b25da 1264 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
31391048
SM		 1265 csp.cqn = sq->cq.mcq.cqn;
1266 csp.wq_ctrl = &sq->wq_ctrl;
1267 csp.min_inline_mode = sq->min_inline_mode;
1268 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1269 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1270 if (err)
1271 goto err_free_xdpsq;
1272
1273 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1274 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1275 ds_cnt++;
1276 }
1277
1278 /* Pre initialize fixed WQE fields */
1279 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1280 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1281 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1282 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1283 struct mlx5_wqe_data_seg *dseg;
1284
1285 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1286 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1287
1288 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1289 dseg->lkey = sq->mkey_be;
1290 }
1291
1292 return 0;
1293
1294err_free_xdpsq:
1295 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1296 mlx5e_free_xdpsq(sq);
1297
1298 return err;
1299}
1300
1301static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1302{
1303 struct mlx5e_channel *c = sq->channel;
1304
1305 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1306 napi_synchronize(&c->napi);
1307
a43b25da 1308 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1309 mlx5e_free_xdpsq_descs(sq);
1310 mlx5e_free_xdpsq(sq);
f62b8bb8
AV		 1311}
1312
95b6c6a5
EBE		 1313static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1314 struct mlx5e_cq_param *param,
1315 struct mlx5e_cq *cq)
f62b8bb8 1316{
f62b8bb8
AV		 1317 struct mlx5_core_cq *mcq = &cq->mcq;
1318 int eqn_not_used;
0b6e26ce 1319 unsigned int irqn;
f62b8bb8
AV		 1320 int err;
1321 u32 i;
1322
f62b8bb8
AV		 1323 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1324 &cq->wq_ctrl);
1325 if (err)
1326 return err;
1327
1328 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1329
f62b8bb8
AV		 1330 mcq->cqe_sz = 64;
1331 mcq->set_ci_db = cq->wq_ctrl.db.db;
1332 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1333 *mcq->set_ci_db = 0;
1334 *mcq->arm_db = 0;
1335 mcq->vector = param->eq_ix;
1336 mcq->comp = mlx5e_completion_event;
1337 mcq->event = mlx5e_cq_error_event;
1338 mcq->irqn = irqn;
f62b8bb8
AV		 1339
1340 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1341 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1342
1343 cqe->op_own = 0xf1;
1344 }
1345
a43b25da 1346 cq->mdev = mdev;
f62b8bb8
AV		 1347
1348 return 0;
1349}
1350
95b6c6a5
EBE		 1351static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1352 struct mlx5e_cq_param *param,
1353 struct mlx5e_cq *cq)
1354{
1355 struct mlx5_core_dev *mdev = c->priv->mdev;
1356 int err;
1357
231243c8
SM		 1358 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1359 param->wq.db_numa_node = cpu_to_node(c->cpu);
95b6c6a5
EBE		 1360 param->eq_ix = c->ix;
1361
1362 err = mlx5e_alloc_cq_common(mdev, param, cq);
1363
1364 cq->napi = &c->napi;
1365 cq->channel = c;
1366
1367 return err;
1368}
1369
3b77235b 1370static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1371{
1c1b5228 1372 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1373}
1374
3b77235b 1375static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1376{
a43b25da 1377 struct mlx5_core_dev *mdev = cq->mdev;
f62b8bb8
AV		 1378 struct mlx5_core_cq *mcq = &cq->mcq;
1379
1380 void *in;
1381 void *cqc;
1382 int inlen;
0b6e26ce 1383 unsigned int irqn_not_used;
f62b8bb8
AV		 1384 int eqn;
1385 int err;
1386
1387 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1388 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1b9a07ee 1389 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1390 if (!in)
1391 return -ENOMEM;
1392
1393 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1394
1395 memcpy(cqc, param->cqc, sizeof(param->cqc));
1396
1c1b5228
TT		 1397 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1398 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1399
1400 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1401
9908aa29 1402 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1403 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1404 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1c1b5228 1405 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1406 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1407 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1408
1409 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1410
1411 kvfree(in);
1412
1413 if (err)
1414 return err;
1415
1416 mlx5e_cq_arm(cq);
1417
1418 return 0;
1419}
1420
3b77235b 1421static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1422{
a43b25da 1423 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
f62b8bb8
AV		 1424}
1425
1426static int mlx5e_open_cq(struct mlx5e_channel *c,
9a317425 1427 struct net_dim_cq_moder moder,
f62b8bb8 1428 struct mlx5e_cq_param *param,
6a9764ef 1429 struct mlx5e_cq *cq)
f62b8bb8 1430{
a43b25da 1431 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1432 int err;
f62b8bb8 1433
3b77235b 1434 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1435 if (err)
1436 return err;
1437
3b77235b 1438 err = mlx5e_create_cq(cq, param);
f62b8bb8 1439 if (err)
3b77235b 1440 goto err_free_cq;
f62b8bb8 1441
7524a5d8 1442 if (MLX5_CAP_GEN(mdev, cq_moderation))
6a9764ef 1443 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
f62b8bb8
AV		 1444 return 0;
1445
3b77235b
SM		 1446err_free_cq:
1447 mlx5e_free_cq(cq);
f62b8bb8
AV		 1448
1449 return err;
1450}
1451
1452static void mlx5e_close_cq(struct mlx5e_cq *cq)
1453{
f62b8bb8 1454 mlx5e_destroy_cq(cq);
3b77235b 1455 mlx5e_free_cq(cq);
f62b8bb8
AV		 1456}
1457
231243c8
SM		 1458static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1459{
1460 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1461}
1462
f62b8bb8 1463static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
6a9764ef 1464 struct mlx5e_params *params,
f62b8bb8
AV		 1465 struct mlx5e_channel_param *cparam)
1466{
f62b8bb8
AV		 1467 int err;
1468 int tc;
1469
1470 for (tc = 0; tc < c->num_tc; tc++) {
6a9764ef
SM		 1471 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1472 &cparam->tx_cq, &c->sq[tc].cq);
f62b8bb8
AV		 1473 if (err)
1474 goto err_close_tx_cqs;
f62b8bb8
AV		 1475 }
1476
1477 return 0;
1478
1479err_close_tx_cqs:
1480 for (tc--; tc >= 0; tc--)
1481 mlx5e_close_cq(&c->sq[tc].cq);
1482
1483 return err;
1484}
1485
1486static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1487{
1488 int tc;
1489
1490 for (tc = 0; tc < c->num_tc; tc++)
1491 mlx5e_close_cq(&c->sq[tc].cq);
1492}
1493
1494static int mlx5e_open_sqs(struct mlx5e_channel *c,
6a9764ef 1495 struct mlx5e_params *params,
f62b8bb8
AV		 1496 struct mlx5e_channel_param *cparam)
1497{
1498 int err;
1499 int tc;
1500
6a9764ef
SM		 1501 for (tc = 0; tc < params->num_tc; tc++) {
1502 int txq_ix = c->ix + tc * params->num_channels;
acc6c595 1503
a43b25da
SM		 1504 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1505 params, &cparam->sq, &c->sq[tc]);
f62b8bb8
AV		 1506 if (err)
1507 goto err_close_sqs;
1508 }
1509
1510 return 0;
1511
1512err_close_sqs:
1513 for (tc--; tc >= 0; tc--)
31391048 1514 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1515
1516 return err;
1517}
1518
1519static void mlx5e_close_sqs(struct mlx5e_channel *c)
1520{
1521 int tc;
1522
1523 for (tc = 0; tc < c->num_tc; tc++)
31391048 1524 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1525}
1526
507f0c81 1527static int mlx5e_set_sq_maxrate(struct net_device *dev,
31391048 1528 struct mlx5e_txqsq *sq, u32 rate)
507f0c81
YP		 1529{
1530 struct mlx5e_priv *priv = netdev_priv(dev);
1531 struct mlx5_core_dev *mdev = priv->mdev;
33ad9711 1532 struct mlx5e_modify_sq_param msp = {0};
507f0c81
YP		 1533 u16 rl_index = 0;
1534 int err;
1535
1536 if (rate == sq->rate_limit)
1537 /* nothing to do */
1538 return 0;
1539
1540 if (sq->rate_limit)
1541 /* remove current rl index to free space to next ones */
1542 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1543
1544 sq->rate_limit = 0;
1545
1546 if (rate) {
1547 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1548 if (err) {
1549 netdev_err(dev, "Failed configuring rate %u: %d\n",
1550 rate, err);
1551 return err;
1552 }
1553 }
1554
33ad9711
SM		 1555 msp.curr_state = MLX5_SQC_STATE_RDY;
1556 msp.next_state = MLX5_SQC_STATE_RDY;
1557 msp.rl_index = rl_index;
1558 msp.rl_update = true;
a43b25da 1559 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
507f0c81
YP		 1560 if (err) {
1561 netdev_err(dev, "Failed configuring rate %u: %d\n",
1562 rate, err);
1563 /* remove the rate from the table */
1564 if (rate)
1565 mlx5_rl_remove_rate(mdev, rate);
1566 return err;
1567 }
1568
1569 sq->rate_limit = rate;
1570 return 0;
1571}
1572
1573static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1574{
1575 struct mlx5e_priv *priv = netdev_priv(dev);
1576 struct mlx5_core_dev *mdev = priv->mdev;
acc6c595 1577 struct mlx5e_txqsq *sq = priv->txq2sq[index];
507f0c81
YP		 1578 int err = 0;
1579
1580 if (!mlx5_rl_is_supported(mdev)) {
1581 netdev_err(dev, "Rate limiting is not supported on this device\n");
1582 return -EINVAL;
1583 }
1584
1585 /* rate is given in Mb/sec, HW config is in Kb/sec */
1586 rate = rate << 10;
1587
1588 /* Check whether rate in valid range, 0 is always valid */
1589 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1590 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1591 return -ERANGE;
1592 }
1593
1594 mutex_lock(&priv->state_lock);
1595 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1596 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1597 if (!err)
1598 priv->tx_rates[index] = rate;
1599 mutex_unlock(&priv->state_lock);
1600
1601 return err;
1602}
1603
f62b8bb8 1604static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
6a9764ef 1605 struct mlx5e_params *params,
f62b8bb8
AV		 1606 struct mlx5e_channel_param *cparam,
1607 struct mlx5e_channel **cp)
1608{
9a317425 1609 struct net_dim_cq_moder icocq_moder = {0, 0};
f62b8bb8 1610 struct net_device *netdev = priv->netdev;
231243c8 1611 int cpu = mlx5e_get_cpu(priv, ix);
f62b8bb8 1612 struct mlx5e_channel *c;
a8c2eb15 1613 unsigned int irq;
f62b8bb8 1614 int err;
a8c2eb15 1615 int eqn;
f62b8bb8 1616
231243c8 1617 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
f62b8bb8
AV		 1618 if (!c)
1619 return -ENOMEM;
1620
1621 c->priv = priv;
a43b25da
SM		 1622 c->mdev = priv->mdev;
1623 c->tstamp = &priv->tstamp;
f62b8bb8 1624 c->ix = ix;
231243c8 1625 c->cpu = cpu;
f62b8bb8
AV		 1626 c->pdev = &priv->mdev->pdev->dev;
1627 c->netdev = priv->netdev;
b50d292b 1628 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
6a9764ef
SM		 1629 c->num_tc = params->num_tc;
1630 c->xdp = !!params->xdp_prog;
cb3c7fd4 1631
a8c2eb15
TT		 1632 mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1633 c->irq_desc = irq_to_desc(irq);
1634
f62b8bb8
AV		 1635 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1636
6a9764ef 1637 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
f62b8bb8
AV		 1638 if (err)
1639 goto err_napi_del;
1640
6a9764ef 1641 err = mlx5e_open_tx_cqs(c, params, cparam);
d3c9bc27
TT		 1642 if (err)
1643 goto err_close_icosq_cq;
1644
6a9764ef 1645 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
f62b8bb8
AV		 1646 if (err)
1647 goto err_close_tx_cqs;
f62b8bb8 1648
d7a0ecab 1649 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
6a9764ef
SM		 1650 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1651 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
d7a0ecab
SM		 1652 if (err)
1653 goto err_close_rx_cq;
1654
f62b8bb8
AV		 1655 napi_enable(&c->napi);
1656
6a9764ef 1657 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1658 if (err)
1659 goto err_disable_napi;
1660
6a9764ef 1661 err = mlx5e_open_sqs(c, params, cparam);
d3c9bc27
TT		 1662 if (err)
1663 goto err_close_icosq;
1664
6a9764ef 1665 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
d7a0ecab
SM		 1666 if (err)
1667 goto err_close_sqs;
b5503b99 1668
6a9764ef 1669 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
f62b8bb8 1670 if (err)
b5503b99 1671 goto err_close_xdp_sq;
f62b8bb8 1672
f62b8bb8
AV		 1673 *cp = c;
1674
1675 return 0;
b5503b99 1676err_close_xdp_sq:
d7a0ecab 1677 if (c->xdp)
31391048 1678 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8
AV		 1679
1680err_close_sqs:
1681 mlx5e_close_sqs(c);
1682
d3c9bc27 1683err_close_icosq:
31391048 1684 mlx5e_close_icosq(&c->icosq);
d3c9bc27 1685
f62b8bb8
AV		 1686err_disable_napi:
1687 napi_disable(&c->napi);
d7a0ecab 1688 if (c->xdp)
31871f87 1689 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 1690
1691err_close_rx_cq:
f62b8bb8
AV		 1692 mlx5e_close_cq(&c->rq.cq);
1693
1694err_close_tx_cqs:
1695 mlx5e_close_tx_cqs(c);
1696
d3c9bc27
TT		 1697err_close_icosq_cq:
1698 mlx5e_close_cq(&c->icosq.cq);
1699
f62b8bb8
AV		 1700err_napi_del:
1701 netif_napi_del(&c->napi);
1702 kfree(c);
1703
1704 return err;
1705}
1706
acc6c595
SM		 1707static void mlx5e_activate_channel(struct mlx5e_channel *c)
1708{
1709 int tc;
1710
1711 for (tc = 0; tc < c->num_tc; tc++)
1712 mlx5e_activate_txqsq(&c->sq[tc]);
1713 mlx5e_activate_rq(&c->rq);
231243c8 1714 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
acc6c595
SM		 1715}
1716
1717static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1718{
1719 int tc;
1720
1721 mlx5e_deactivate_rq(&c->rq);
1722 for (tc = 0; tc < c->num_tc; tc++)
1723 mlx5e_deactivate_txqsq(&c->sq[tc]);
1724}
1725
f62b8bb8
AV		 1726static void mlx5e_close_channel(struct mlx5e_channel *c)
1727{
1728 mlx5e_close_rq(&c->rq);
b5503b99 1729 if (c->xdp)
31391048 1730 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8 1731 mlx5e_close_sqs(c);
31391048 1732 mlx5e_close_icosq(&c->icosq);
f62b8bb8 1733 napi_disable(&c->napi);
b5503b99 1734 if (c->xdp)
31871f87 1735 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8
AV		 1736 mlx5e_close_cq(&c->rq.cq);
1737 mlx5e_close_tx_cqs(c);
d3c9bc27 1738 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1739 netif_napi_del(&c->napi);
7ae92ae5 1740
f62b8bb8
AV		 1741 kfree(c);
1742}
1743
1744static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
6a9764ef 1745 struct mlx5e_params *params,
f62b8bb8
AV		 1746 struct mlx5e_rq_param *param)
1747{
1748 void *rqc = param->rqc;
1749 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1750
6a9764ef 1751 switch (params->rq_wq_type) {
461017cb 1752 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef
SM		 1753 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1754 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
461017cb
TT		 1755 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1756 break;
1757 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1758 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1759 }
1760
f62b8bb8
AV		 1761 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1762 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
6a9764ef 1763 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
b50d292b 1764 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1765 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
6a9764ef 1766 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
102722fc 1767 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
f62b8bb8 1768
311c7c71 1769 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1770 param->wq.linear = 1;
1771}
1772
7cbaf9a3 1773static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2f0db879 1774 struct mlx5e_rq_param *param)
556dd1b9 1775{
7cbaf9a3 1776 struct mlx5_core_dev *mdev = priv->mdev;
556dd1b9
TT		 1777 void *rqc = param->rqc;
1778 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1779
1780 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1781 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
7cbaf9a3 1782 MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2f0db879
GP		 1783
1784 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
556dd1b9
TT		 1785}
1786
d3c9bc27
TT		 1787static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1788 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1789{
1790 void *sqc = param->sqc;
1791 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1792
f62b8bb8 1793 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1794 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1795
311c7c71 1796 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1797}
1798
1799static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
6a9764ef 1800 struct mlx5e_params *params,
d3c9bc27
TT		 1801 struct mlx5e_sq_param *param)
1802{
1803 void *sqc = param->sqc;
1804 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1805
1806 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1807 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2ac9cfe7 1808 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
f62b8bb8
AV		 1809}
1810
1811static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1812 struct mlx5e_cq_param *param)
1813{
1814 void *cqc = param->cqc;
1815
30aa60b3 1816 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 1817}
1818
1819static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1820 struct mlx5e_params *params,
f62b8bb8
AV		 1821 struct mlx5e_cq_param *param)
1822{
1823 void *cqc = param->cqc;
461017cb 1824 u8 log_cq_size;
f62b8bb8 1825
6a9764ef 1826 switch (params->rq_wq_type) {
461017cb 1827 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 1828 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
461017cb
TT		 1829 break;
1830 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 1831 log_cq_size = params->log_rq_size;
461017cb
TT		 1832 }
1833
1834 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
6a9764ef 1835 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1836 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1837 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1838 }
f62b8bb8
AV		 1839
1840 mlx5e_build_common_cq_param(priv, param);
0088cbbc 1841 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 1842}
1843
1844static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1845 struct mlx5e_params *params,
f62b8bb8
AV		 1846 struct mlx5e_cq_param *param)
1847{
1848 void *cqc = param->cqc;
1849
6a9764ef 1850 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
f62b8bb8
AV		 1851
1852 mlx5e_build_common_cq_param(priv, param);
0088cbbc 1853 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 1854}
1855
d3c9bc27 1856static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1857 u8 log_wq_size,
1858 struct mlx5e_cq_param *param)
d3c9bc27
TT		 1859{
1860 void *cqc = param->cqc;
1861
1862 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1863
1864 mlx5e_build_common_cq_param(priv, param);
9908aa29 1865
9a317425 1866 param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1867}
1868
1869static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1870 u8 log_wq_size,
1871 struct mlx5e_sq_param *param)
d3c9bc27
TT		 1872{
1873 void *sqc = param->sqc;
1874 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1875
1876 mlx5e_build_sq_param_common(priv, param);
1877
1878 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1879 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1880}
1881
b5503b99 1882static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
6a9764ef 1883 struct mlx5e_params *params,
b5503b99
SM		 1884 struct mlx5e_sq_param *param)
1885{
1886 void *sqc = param->sqc;
1887 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1888
1889 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1890 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
b5503b99
SM		 1891}
1892
6a9764ef
SM		 1893static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1894 struct mlx5e_params *params,
1895 struct mlx5e_channel_param *cparam)
f62b8bb8 1896{
bc77b240 1897 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1898
6a9764ef
SM		 1899 mlx5e_build_rq_param(priv, params, &cparam->rq);
1900 mlx5e_build_sq_param(priv, params, &cparam->sq);
1901 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
1902 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
1903 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
1904 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
1905 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
f62b8bb8
AV		 1906}
1907
55c2503d
SM		 1908int mlx5e_open_channels(struct mlx5e_priv *priv,
1909 struct mlx5e_channels *chs)
f62b8bb8 1910{
6b87663f 1911 struct mlx5e_channel_param *cparam;
03289b88 1912 int err = -ENOMEM;
f62b8bb8 1913 int i;
f62b8bb8 1914
6a9764ef 1915 chs->num = chs->params.num_channels;
03289b88 1916
ff9c852f 1917 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
6b87663f 1918 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
acc6c595
SM		 1919 if (!chs->c || !cparam)
1920 goto err_free;
f62b8bb8 1921
6a9764ef 1922 mlx5e_build_channel_param(priv, &chs->params, cparam);
ff9c852f 1923 for (i = 0; i < chs->num; i++) {
6a9764ef 1924 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
f62b8bb8
AV		 1925 if (err)
1926 goto err_close_channels;
1927 }
1928
6b87663f 1929 kfree(cparam);
f62b8bb8
AV		 1930 return 0;
1931
1932err_close_channels:
1933 for (i--; i >= 0; i--)
ff9c852f 1934 mlx5e_close_channel(chs->c[i]);
f62b8bb8 1935
acc6c595 1936err_free:
ff9c852f 1937 kfree(chs->c);
6b87663f 1938 kfree(cparam);
ff9c852f 1939 chs->num = 0;
f62b8bb8
AV		 1940 return err;
1941}
1942
acc6c595 1943static void mlx5e_activate_channels(struct mlx5e_channels *chs)
f62b8bb8
AV		 1944{
1945 int i;
1946
acc6c595
SM		 1947 for (i = 0; i < chs->num; i++)
1948 mlx5e_activate_channel(chs->c[i]);
1949}
1950
1951static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
1952{
1953 int err = 0;
1954 int i;
1955
1956 for (i = 0; i < chs->num; i++) {
1957 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
1958 if (err)
1959 break;
1960 }
1961
1962 return err;
1963}
1964
1965static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
1966{
1967 int i;
1968
1969 for (i = 0; i < chs->num; i++)
1970 mlx5e_deactivate_channel(chs->c[i]);
1971}
1972
55c2503d 1973void mlx5e_close_channels(struct mlx5e_channels *chs)
acc6c595
SM		 1974{
1975 int i;
c3b7c5c9 1976
ff9c852f
SM		 1977 for (i = 0; i < chs->num; i++)
1978 mlx5e_close_channel(chs->c[i]);
f62b8bb8 1979
ff9c852f
SM		 1980 kfree(chs->c);
1981 chs->num = 0;
f62b8bb8
AV		 1982}
1983
a5f97fee
SM		 1984static int
1985mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 1986{
1987 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1988 void *rqtc;
1989 int inlen;
1990 int err;
1da36696 1991 u32 *in;
a5f97fee 1992 int i;
f62b8bb8 1993
f62b8bb8 1994 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 1995 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1996 if (!in)
1997 return -ENOMEM;
1998
1999 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2000
2001 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2002 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2003
a5f97fee
SM		 2004 for (i = 0; i < sz; i++)
2005 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2be6967c 2006
398f3351
HHZ		 2007 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2008 if (!err)
2009 rqt->enabled = true;
f62b8bb8
AV		 2010
2011 kvfree(in);
1da36696
TT		 2012 return err;
2013}
2014
cb67b832 2015void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2016{
398f3351
HHZ		 2017 rqt->enabled = false;
2018 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2019}
2020
8f493ffd 2021int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2022{
2023 struct mlx5e_rqt *rqt = &priv->indir_rqt;
8f493ffd 2024 int err;
6bfd390b 2025
8f493ffd
SM		 2026 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2027 if (err)
2028 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2029 return err;
6bfd390b
HHZ		 2030}
2031
cb67b832 2032int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2033{
398f3351 2034 struct mlx5e_rqt *rqt;
1da36696
TT		 2035 int err;
2036 int ix;
2037
6bfd390b 2038 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351 2039 rqt = &priv->direct_tir[ix].rqt;
a5f97fee 2040 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
1da36696
TT		 2041 if (err)
2042 goto err_destroy_rqts;
2043 }
2044
2045 return 0;
2046
2047err_destroy_rqts:
8f493ffd 2048 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
1da36696 2049 for (ix--; ix >= 0; ix--)
398f3351 2050 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2051
f62b8bb8
AV		 2052 return err;
2053}
2054
8f493ffd
SM		 2055void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2056{
2057 int i;
2058
2059 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2060 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2061}
2062
a5f97fee
SM		 2063static int mlx5e_rx_hash_fn(int hfunc)
2064{
2065 return (hfunc == ETH_RSS_HASH_TOP) ?
2066 MLX5_RX_HASH_FN_TOEPLITZ :
2067 MLX5_RX_HASH_FN_INVERTED_XOR8;
2068}
2069
3f6d08d1 2070int mlx5e_bits_invert(unsigned long a, int size)
a5f97fee
SM		 2071{
2072 int inv = 0;
2073 int i;
2074
2075 for (i = 0; i < size; i++)
2076 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2077
2078 return inv;
2079}
2080
2081static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2082 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2083{
2084 int i;
2085
2086 for (i = 0; i < sz; i++) {
2087 u32 rqn;
2088
2089 if (rrp.is_rss) {
2090 int ix = i;
2091
2092 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2093 ix = mlx5e_bits_invert(i, ilog2(sz));
2094
6a9764ef 2095 ix = priv->channels.params.indirection_rqt[ix];
a5f97fee
SM		 2096 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2097 } else {
2098 rqn = rrp.rqn;
2099 }
2100 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2101 }
2102}
2103
2104int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2105 struct mlx5e_redirect_rqt_param rrp)
5c50368f
AS		 2106{
2107 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2108 void *rqtc;
2109 int inlen;
1da36696 2110 u32 *in;
5c50368f
AS		 2111 int err;
2112
5c50368f 2113 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2114 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2115 if (!in)
2116 return -ENOMEM;
2117
2118 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2119
2120 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5c50368f 2121 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
a5f97fee 2122 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
1da36696 2123 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2124
2125 kvfree(in);
5c50368f
AS		 2126 return err;
2127}
2128
a5f97fee
SM		 2129static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2130 struct mlx5e_redirect_rqt_param rrp)
2131{
2132 if (!rrp.is_rss)
2133 return rrp.rqn;
2134
2135 if (ix >= rrp.rss.channels->num)
2136 return priv->drop_rq.rqn;
2137
2138 return rrp.rss.channels->c[ix]->rq.rqn;
2139}
2140
2141static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2142 struct mlx5e_redirect_rqt_param rrp)
40ab6a6e 2143{
1da36696
TT		 2144 u32 rqtn;
2145 int ix;
2146
398f3351 2147 if (priv->indir_rqt.enabled) {
a5f97fee 2148 /* RSS RQ table */
398f3351 2149 rqtn = priv->indir_rqt.rqtn;
a5f97fee 2150 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
398f3351
HHZ		 2151 }
2152
a5f97fee
SM		 2153 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2154 struct mlx5e_redirect_rqt_param direct_rrp = {
2155 .is_rss = false,
95632791
AM		 2156 {
2157 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2158 },
a5f97fee
SM		 2159 };
2160
2161 /* Direct RQ Tables */
398f3351
HHZ		 2162 if (!priv->direct_tir[ix].rqt.enabled)
2163 continue;
a5f97fee 2164
398f3351 2165 rqtn = priv->direct_tir[ix].rqt.rqtn;
a5f97fee 2166 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
1da36696 2167 }
40ab6a6e
AS		 2168}
2169
a5f97fee
SM		 2170static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2171 struct mlx5e_channels *chs)
2172{
2173 struct mlx5e_redirect_rqt_param rrp = {
2174 .is_rss = true,
95632791
AM		 2175 {
2176 .rss = {
2177 .channels = chs,
2178 .hfunc = chs->params.rss_hfunc,
2179 }
2180 },
a5f97fee
SM		 2181 };
2182
2183 mlx5e_redirect_rqts(priv, rrp);
2184}
2185
2186static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2187{
2188 struct mlx5e_redirect_rqt_param drop_rrp = {
2189 .is_rss = false,
95632791
AM		 2190 {
2191 .rqn = priv->drop_rq.rqn,
2192 },
a5f97fee
SM		 2193 };
2194
2195 mlx5e_redirect_rqts(priv, drop_rrp);
2196}
2197
6a9764ef 2198static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
5c50368f 2199{
6a9764ef 2200 if (!params->lro_en)
5c50368f
AS		 2201 return;
2202
2203#define ROUGH_MAX_L2_L3_HDR_SZ 256
2204
2205 MLX5_SET(tirc, tirc, lro_enable_mask,
2206 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2207 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2208 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
6a9764ef
SM		 2209 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2210 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
5c50368f
AS		 2211}
2212
6a9764ef
SM		 2213void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2214 enum mlx5e_traffic_types tt,
7b3722fa 2215 void *tirc, bool inner)
bdfc028d 2216{
7b3722fa
GP		 2217 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2218 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
a100ff3e
GP		 2219
2220#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2221 MLX5_HASH_FIELD_SEL_DST_IP)
2222
2223#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2224 MLX5_HASH_FIELD_SEL_DST_IP |\
2225 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2226 MLX5_HASH_FIELD_SEL_L4_DPORT)
2227
2228#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2229 MLX5_HASH_FIELD_SEL_DST_IP |\
2230 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2231
6a9764ef
SM		 2232 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2233 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
bdfc028d
TT		 2234 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2235 rx_hash_toeplitz_key);
2236 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2237 rx_hash_toeplitz_key);
2238
2239 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
6a9764ef 2240 memcpy(rss_key, params->toeplitz_hash_key, len);
bdfc028d 2241 }
a100ff3e
GP		 2242
2243 switch (tt) {
2244 case MLX5E_TT_IPV4_TCP:
2245 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2246 MLX5_L3_PROT_TYPE_IPV4);
2247 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2248 MLX5_L4_PROT_TYPE_TCP);
2249 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2250 MLX5_HASH_IP_L4PORTS);
2251 break;
2252
2253 case MLX5E_TT_IPV6_TCP:
2254 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2255 MLX5_L3_PROT_TYPE_IPV6);
2256 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2257 MLX5_L4_PROT_TYPE_TCP);
2258 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2259 MLX5_HASH_IP_L4PORTS);
2260 break;
2261
2262 case MLX5E_TT_IPV4_UDP:
2263 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2264 MLX5_L3_PROT_TYPE_IPV4);
2265 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2266 MLX5_L4_PROT_TYPE_UDP);
2267 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2268 MLX5_HASH_IP_L4PORTS);
2269 break;
2270
2271 case MLX5E_TT_IPV6_UDP:
2272 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2273 MLX5_L3_PROT_TYPE_IPV6);
2274 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2275 MLX5_L4_PROT_TYPE_UDP);
2276 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2277 MLX5_HASH_IP_L4PORTS);
2278 break;
2279
2280 case MLX5E_TT_IPV4_IPSEC_AH:
2281 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2282 MLX5_L3_PROT_TYPE_IPV4);
2283 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2284 MLX5_HASH_IP_IPSEC_SPI);
2285 break;
2286
2287 case MLX5E_TT_IPV6_IPSEC_AH:
2288 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2289 MLX5_L3_PROT_TYPE_IPV6);
2290 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2291 MLX5_HASH_IP_IPSEC_SPI);
2292 break;
2293
2294 case MLX5E_TT_IPV4_IPSEC_ESP:
2295 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2296 MLX5_L3_PROT_TYPE_IPV4);
2297 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2298 MLX5_HASH_IP_IPSEC_SPI);
2299 break;
2300
2301 case MLX5E_TT_IPV6_IPSEC_ESP:
2302 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2303 MLX5_L3_PROT_TYPE_IPV6);
2304 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2305 MLX5_HASH_IP_IPSEC_SPI);
2306 break;
2307
2308 case MLX5E_TT_IPV4:
2309 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2310 MLX5_L3_PROT_TYPE_IPV4);
2311 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2312 MLX5_HASH_IP);
2313 break;
2314
2315 case MLX5E_TT_IPV6:
2316 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2317 MLX5_L3_PROT_TYPE_IPV6);
2318 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2319 MLX5_HASH_IP);
2320 break;
2321 default:
2322 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2323 }
bdfc028d
TT		 2324}
2325
ab0394fe 2326static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2327{
2328 struct mlx5_core_dev *mdev = priv->mdev;
2329
2330 void *in;
2331 void *tirc;
2332 int inlen;
2333 int err;
ab0394fe 2334 int tt;
1da36696 2335 int ix;
5c50368f
AS		 2336
2337 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1b9a07ee 2338 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2339 if (!in)
2340 return -ENOMEM;
2341
2342 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2343 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2344
6a9764ef 2345 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
5c50368f 2346
1da36696 2347 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2348 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2349 inlen);
ab0394fe 2350 if (err)
1da36696 2351 goto free_in;
ab0394fe 2352 }
5c50368f 2353
6bfd390b 2354 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2355 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2356 in, inlen);
2357 if (err)
2358 goto free_in;
2359 }
2360
2361free_in:
5c50368f
AS		 2362 kvfree(in);
2363
2364 return err;
2365}
2366
7b3722fa
GP		 2367static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2368 enum mlx5e_traffic_types tt,
2369 u32 *tirc)
2370{
2371 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2372
2373 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2374
2375 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2376 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2377 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2378
2379 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2380}
2381
cd255eff 2382static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2383{
40ab6a6e 2384 struct mlx5_core_dev *mdev = priv->mdev;
c139dbfd 2385 u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
40ab6a6e
AS		 2386 int err;
2387
cd255eff 2388 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2389 if (err)
2390 return err;
2391
cd255eff
SM		 2392 /* Update vport context MTU */
2393 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2394 return 0;
2395}
40ab6a6e 2396
cd255eff
SM		 2397static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2398{
2399 struct mlx5_core_dev *mdev = priv->mdev;
2400 u16 hw_mtu = 0;
2401 int err;
40ab6a6e 2402
cd255eff
SM		 2403 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2404 if (err || !hw_mtu) /* fallback to port oper mtu */
2405 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2406
c139dbfd 2407 *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
cd255eff
SM		 2408}
2409
2e20a151 2410static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
cd255eff 2411{
2e20a151 2412 struct net_device *netdev = priv->netdev;
cd255eff
SM		 2413 u16 mtu;
2414 int err;
2415
2416 err = mlx5e_set_mtu(priv, netdev->mtu);
2417 if (err)
2418 return err;
40ab6a6e 2419
cd255eff
SM		 2420 mlx5e_query_mtu(priv, &mtu);
2421 if (mtu != netdev->mtu)
2422 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2423 __func__, mtu, netdev->mtu);
40ab6a6e 2424
cd255eff 2425 netdev->mtu = mtu;
40ab6a6e
AS		 2426 return 0;
2427}
2428
08fb1dac
SM		 2429static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2430{
2431 struct mlx5e_priv *priv = netdev_priv(netdev);
6a9764ef
SM		 2432 int nch = priv->channels.params.num_channels;
2433 int ntc = priv->channels.params.num_tc;
08fb1dac
SM		 2434 int tc;
2435
2436 netdev_reset_tc(netdev);
2437
2438 if (ntc == 1)
2439 return;
2440
2441 netdev_set_num_tc(netdev, ntc);
2442
7ccdd084
RS		 2443 /* Map netdev TCs to offset 0
2444 * We have our own UP to TXQ mapping for QoS
2445 */
08fb1dac 2446 for (tc = 0; tc < ntc; tc++)
7ccdd084 2447 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2448}
2449
acc6c595
SM		 2450static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2451{
2452 struct mlx5e_channel *c;
2453 struct mlx5e_txqsq *sq;
2454 int i, tc;
2455
2456 for (i = 0; i < priv->channels.num; i++)
2457 for (tc = 0; tc < priv->profile->max_tc; tc++)
2458 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2459
2460 for (i = 0; i < priv->channels.num; i++) {
2461 c = priv->channels.c[i];
2462 for (tc = 0; tc < c->num_tc; tc++) {
2463 sq = &c->sq[tc];
2464 priv->txq2sq[sq->txq_ix] = sq;
2465 }
2466 }
2467}
2468
603f4a45 2469void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2470{
9008ae07
SM		 2471 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2472 struct net_device *netdev = priv->netdev;
2473
2474 mlx5e_netdev_set_tcs(netdev);
053ee0a7
TR		 2475 netif_set_real_num_tx_queues(netdev, num_txqs);
2476 netif_set_real_num_rx_queues(netdev, priv->channels.num);
9008ae07 2477
acc6c595
SM		 2478 mlx5e_build_channels_tx_maps(priv);
2479 mlx5e_activate_channels(&priv->channels);
2480 netif_tx_start_all_queues(priv->netdev);
9008ae07 2481
a9f7705f 2482 if (MLX5_VPORT_MANAGER(priv->mdev))
9008ae07
SM		 2483 mlx5e_add_sqs_fwd_rules(priv);
2484
acc6c595 2485 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
9008ae07 2486 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
acc6c595
SM		 2487}
2488
603f4a45 2489void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2490{
9008ae07
SM		 2491 mlx5e_redirect_rqts_to_drop(priv);
2492
a9f7705f 2493 if (MLX5_VPORT_MANAGER(priv->mdev))
9008ae07
SM		 2494 mlx5e_remove_sqs_fwd_rules(priv);
2495
acc6c595
SM		 2496 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2497 * polling for inactive tx queues.
2498 */
2499 netif_tx_stop_all_queues(priv->netdev);
2500 netif_tx_disable(priv->netdev);
2501 mlx5e_deactivate_channels(&priv->channels);
2502}
2503
55c2503d 2504void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2e20a151
SM		 2505 struct mlx5e_channels *new_chs,
2506 mlx5e_fp_hw_modify hw_modify)
55c2503d
SM		 2507{
2508 struct net_device *netdev = priv->netdev;
2509 int new_num_txqs;
7ca42c80 2510 int carrier_ok;
55c2503d
SM		 2511 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2512
7ca42c80 2513 carrier_ok = netif_carrier_ok(netdev);
55c2503d
SM		 2514 netif_carrier_off(netdev);
2515
2516 if (new_num_txqs < netdev->real_num_tx_queues)
2517 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2518
2519 mlx5e_deactivate_priv_channels(priv);
2520 mlx5e_close_channels(&priv->channels);
2521
2522 priv->channels = *new_chs;
2523
2e20a151
SM		 2524 /* New channels are ready to roll, modify HW settings if needed */
2525 if (hw_modify)
2526 hw_modify(priv);
2527
55c2503d
SM		 2528 mlx5e_refresh_tirs(priv, false);
2529 mlx5e_activate_priv_channels(priv);
2530
7ca42c80
ES		 2531 /* return carrier back if needed */
2532 if (carrier_ok)
2533 netif_carrier_on(netdev);
55c2503d
SM		 2534}
2535
237f258c 2536void mlx5e_timestamp_init(struct mlx5e_priv *priv)
7c39afb3
FD		 2537{
2538 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2539 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2540}
2541
40ab6a6e
AS		 2542int mlx5e_open_locked(struct net_device *netdev)
2543{
2544 struct mlx5e_priv *priv = netdev_priv(netdev);
40ab6a6e
AS		 2545 int err;
2546
2547 set_bit(MLX5E_STATE_OPENED, &priv->state);
2548
ff9c852f 2549 err = mlx5e_open_channels(priv, &priv->channels);
acc6c595 2550 if (err)
343b29f3 2551 goto err_clear_state_opened_flag;
40ab6a6e 2552
b676f653 2553 mlx5e_refresh_tirs(priv, false);
acc6c595 2554 mlx5e_activate_priv_channels(priv);
7ca42c80
ES		 2555 if (priv->profile->update_carrier)
2556 priv->profile->update_carrier(priv);
be4891af 2557
cb67b832
HHZ		 2558 if (priv->profile->update_stats)
2559 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2560
9b37b07f 2561 return 0;
343b29f3
AS		 2562
2563err_clear_state_opened_flag:
2564 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2565 return err;
40ab6a6e
AS		 2566}
2567
cb67b832 2568int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2569{
2570 struct mlx5e_priv *priv = netdev_priv(netdev);
2571 int err;
2572
2573 mutex_lock(&priv->state_lock);
2574 err = mlx5e_open_locked(netdev);
63bfd399
EBE		 2575 if (!err)
2576 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
40ab6a6e
AS		 2577 mutex_unlock(&priv->state_lock);
2578
2579 return err;
2580}
2581
2582int mlx5e_close_locked(struct net_device *netdev)
2583{
2584 struct mlx5e_priv *priv = netdev_priv(netdev);
2585
a1985740
AS		 2586 /* May already be CLOSED in case a previous configuration operation
2587 * (e.g RX/TX queue size change) that involves close&open failed.
2588 */
2589 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2590 return 0;
2591
40ab6a6e
AS		 2592 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2593
40ab6a6e 2594 netif_carrier_off(priv->netdev);
acc6c595
SM		 2595 mlx5e_deactivate_priv_channels(priv);
2596 mlx5e_close_channels(&priv->channels);
40ab6a6e
AS		 2597
2598 return 0;
2599}
2600
cb67b832 2601int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2602{
2603 struct mlx5e_priv *priv = netdev_priv(netdev);
2604 int err;
2605
26e59d80
MHY		 2606 if (!netif_device_present(netdev))
2607 return -ENODEV;
2608
40ab6a6e 2609 mutex_lock(&priv->state_lock);
63bfd399 2610 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
40ab6a6e
AS		 2611 err = mlx5e_close_locked(netdev);
2612 mutex_unlock(&priv->state_lock);
2613
2614 return err;
2615}
2616
a43b25da 2617static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2618 struct mlx5e_rq *rq,
2619 struct mlx5e_rq_param *param)
40ab6a6e 2620{
40ab6a6e
AS		 2621 void *rqc = param->rqc;
2622 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2623 int err;
2624
2625 param->wq.db_numa_node = param->wq.buf_numa_node;
2626
2627 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2628 &rq->wq_ctrl);
2629 if (err)
2630 return err;
2631
0ddf5432
JDB		 2632 /* Mark as unused given "Drop-RQ" packets never reach XDP */
2633 xdp_rxq_info_unused(&rq->xdp_rxq);
2634
a43b25da 2635 rq->mdev = mdev;
40ab6a6e
AS		 2636
2637 return 0;
2638}
2639
a43b25da 2640static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2641 struct mlx5e_cq *cq,
2642 struct mlx5e_cq_param *param)
40ab6a6e 2643{
2f0db879
GP		 2644 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2645 param->wq.db_numa_node = dev_to_node(&mdev->pdev->dev);
2646
95b6c6a5 2647 return mlx5e_alloc_cq_common(mdev, param, cq);
40ab6a6e
AS		 2648}
2649
7cbaf9a3 2650static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
a43b25da 2651 struct mlx5e_rq *drop_rq)
40ab6a6e 2652{
7cbaf9a3 2653 struct mlx5_core_dev *mdev = priv->mdev;
a43b25da
SM		 2654 struct mlx5e_cq_param cq_param = {};
2655 struct mlx5e_rq_param rq_param = {};
2656 struct mlx5e_cq *cq = &drop_rq->cq;
40ab6a6e
AS		 2657 int err;
2658
7cbaf9a3 2659 mlx5e_build_drop_rq_param(priv, &rq_param);
40ab6a6e 2660
a43b25da 2661 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
40ab6a6e
AS		 2662 if (err)
2663 return err;
2664
3b77235b 2665 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 2666 if (err)
3b77235b 2667 goto err_free_cq;
40ab6a6e 2668
a43b25da 2669 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
40ab6a6e 2670 if (err)
3b77235b 2671 goto err_destroy_cq;
40ab6a6e 2672
a43b25da 2673 err = mlx5e_create_rq(drop_rq, &rq_param);
40ab6a6e 2674 if (err)
3b77235b 2675 goto err_free_rq;
40ab6a6e 2676
7cbaf9a3
MS		 2677 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
2678 if (err)
2679 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
2680
40ab6a6e
AS		 2681 return 0;
2682
3b77235b 2683err_free_rq:
a43b25da 2684 mlx5e_free_rq(drop_rq);
40ab6a6e
AS		 2685
2686err_destroy_cq:
a43b25da 2687 mlx5e_destroy_cq(cq);
40ab6a6e 2688
3b77235b 2689err_free_cq:
a43b25da 2690 mlx5e_free_cq(cq);
3b77235b 2691
40ab6a6e
AS		 2692 return err;
2693}
2694
a43b25da 2695static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
40ab6a6e 2696{
a43b25da
SM		 2697 mlx5e_destroy_rq(drop_rq);
2698 mlx5e_free_rq(drop_rq);
2699 mlx5e_destroy_cq(&drop_rq->cq);
2700 mlx5e_free_cq(&drop_rq->cq);
40ab6a6e
AS		 2701}
2702
5426a0b2
SM		 2703int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2704 u32 underlay_qpn, u32 *tisn)
40ab6a6e 2705{
c4f287c4 2706 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2707 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2708
08fb1dac 2709 MLX5_SET(tisc, tisc, prio, tc << 1);
5426a0b2 2710 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
b50d292b 2711 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2712
2713 if (mlx5_lag_is_lacp_owner(mdev))
2714 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2715
5426a0b2 2716 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
40ab6a6e
AS		 2717}
2718
5426a0b2 2719void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
40ab6a6e 2720{
5426a0b2 2721 mlx5_core_destroy_tis(mdev, tisn);
40ab6a6e
AS		 2722}
2723
cb67b832 2724int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2725{
2726 int err;
2727 int tc;
2728
6bfd390b 2729 for (tc = 0; tc < priv->profile->max_tc; tc++) {
5426a0b2 2730 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
40ab6a6e
AS		 2731 if (err)
2732 goto err_close_tises;
2733 }
2734
2735 return 0;
2736
2737err_close_tises:
2738 for (tc--; tc >= 0; tc--)
5426a0b2 2739 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2740
2741 return err;
2742}
2743
cb67b832 2744void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2745{
2746 int tc;
2747
6bfd390b 2748 for (tc = 0; tc < priv->profile->max_tc; tc++)
5426a0b2 2749 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2750}
2751
6a9764ef
SM		 2752static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2753 enum mlx5e_traffic_types tt,
2754 u32 *tirc)
f62b8bb8 2755{
b50d292b 2756 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2757
6a9764ef 2758 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
f62b8bb8 2759
4cbeaff5 2760 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2761 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
7b3722fa 2762 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
f62b8bb8
AV		 2763}
2764
6a9764ef 2765static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
f62b8bb8 2766{
b50d292b 2767 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696 2768
6a9764ef 2769 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
1da36696
TT		 2770
2771 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2772 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2773 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2774}
2775
8f493ffd 2776int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2777{
724b2aa1 2778 struct mlx5e_tir *tir;
f62b8bb8
AV		 2779 void *tirc;
2780 int inlen;
7b3722fa 2781 int i = 0;
f62b8bb8 2782 int err;
1da36696 2783 u32 *in;
1da36696 2784 int tt;
f62b8bb8
AV		 2785
2786 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2787 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2788 if (!in)
2789 return -ENOMEM;
2790
1da36696
TT		 2791 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2792 memset(in, 0, inlen);
724b2aa1 2793 tir = &priv->indir_tir[tt];
1da36696 2794 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2795 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
724b2aa1 2796 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
7b3722fa
GP		 2797 if (err) {
2798 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2799 goto err_destroy_inner_tirs;
2800 }
f62b8bb8
AV		 2801 }
2802
7b3722fa
GP		 2803 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2804 goto out;
2805
2806 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2807 memset(in, 0, inlen);
2808 tir = &priv->inner_indir_tir[i];
2809 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2810 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2811 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2812 if (err) {
2813 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2814 goto err_destroy_inner_tirs;
2815 }
2816 }
2817
2818out:
6bfd390b
HHZ		 2819 kvfree(in);
2820
2821 return 0;
2822
7b3722fa
GP		 2823err_destroy_inner_tirs:
2824 for (i--; i >= 0; i--)
2825 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2826
6bfd390b
HHZ		 2827 for (tt--; tt >= 0; tt--)
2828 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2829
2830 kvfree(in);
2831
2832 return err;
2833}
2834
cb67b832 2835int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2836{
2837 int nch = priv->profile->max_nch(priv->mdev);
2838 struct mlx5e_tir *tir;
2839 void *tirc;
2840 int inlen;
2841 int err;
2842 u32 *in;
2843 int ix;
2844
2845 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2846 in = kvzalloc(inlen, GFP_KERNEL);
6bfd390b
HHZ		 2847 if (!in)
2848 return -ENOMEM;
2849
1da36696
TT		 2850 for (ix = 0; ix < nch; ix++) {
2851 memset(in, 0, inlen);
724b2aa1 2852 tir = &priv->direct_tir[ix];
1da36696 2853 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2854 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
724b2aa1 2855 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2856 if (err)
2857 goto err_destroy_ch_tirs;
2858 }
2859
2860 kvfree(in);
2861
f62b8bb8
AV		 2862 return 0;
2863
1da36696 2864err_destroy_ch_tirs:
8f493ffd 2865 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
1da36696 2866 for (ix--; ix >= 0; ix--)
724b2aa1 2867 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2868
1da36696 2869 kvfree(in);
f62b8bb8
AV		 2870
2871 return err;
2872}
2873
8f493ffd 2874void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2875{
2876 int i;
2877
1da36696 2878 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2879 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
7b3722fa
GP		 2880
2881 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2882 return;
2883
2884 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2885 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
f62b8bb8
AV		 2886}
2887
cb67b832 2888void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2889{
2890 int nch = priv->profile->max_nch(priv->mdev);
2891 int i;
2892
2893 for (i = 0; i < nch; i++)
2894 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2895}
2896
102722fc
GE		 2897static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2898{
2899 int err = 0;
2900 int i;
2901
2902 for (i = 0; i < chs->num; i++) {
2903 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2904 if (err)
2905 return err;
2906 }
2907
2908 return 0;
2909}
2910
f6d96a20 2911static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
36350114
GP		 2912{
2913 int err = 0;
2914 int i;
2915
ff9c852f
SM		 2916 for (i = 0; i < chs->num; i++) {
2917 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
36350114
GP		 2918 if (err)
2919 return err;
2920 }
2921
2922 return 0;
2923}
2924
0cf0f6d3
JP		 2925static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
2926 struct tc_mqprio_qopt *mqprio)
08fb1dac
SM		 2927{
2928 struct mlx5e_priv *priv = netdev_priv(netdev);
6f9485af 2929 struct mlx5e_channels new_channels = {};
0cf0f6d3 2930 u8 tc = mqprio->num_tc;
08fb1dac
SM		 2931 int err = 0;
2932
0cf0f6d3
JP		 2933 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2934
08fb1dac
SM		 2935 if (tc && tc != MLX5E_MAX_NUM_TC)
2936 return -EINVAL;
2937
2938 mutex_lock(&priv->state_lock);
2939
6f9485af
SM		 2940 new_channels.params = priv->channels.params;
2941 new_channels.params.num_tc = tc ? tc : 1;
08fb1dac 2942
20b6a1c7 2943 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6f9485af
SM		 2944 priv->channels.params = new_channels.params;
2945 goto out;
2946 }
08fb1dac 2947
6f9485af
SM		 2948 err = mlx5e_open_channels(priv, &new_channels);
2949 if (err)
2950 goto out;
08fb1dac 2951
2e20a151 2952 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
6f9485af 2953out:
08fb1dac 2954 mutex_unlock(&priv->state_lock);
08fb1dac
SM		 2955 return err;
2956}
2957
e80541ec 2958#ifdef CONFIG_MLX5_ESWITCH
d6c862ba 2959static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
0cf0f6d3 2960 struct tc_cls_flower_offload *cls_flower)
08fb1dac 2961{
0cf0f6d3
JP		 2962 switch (cls_flower->command) {
2963 case TC_CLSFLOWER_REPLACE:
5fd9fc4e 2964 return mlx5e_configure_flower(priv, cls_flower);
0cf0f6d3
JP		 2965 case TC_CLSFLOWER_DESTROY:
2966 return mlx5e_delete_flower(priv, cls_flower);
2967 case TC_CLSFLOWER_STATS:
2968 return mlx5e_stats_flower(priv, cls_flower);
2969 default:
a5fcf8a6 2970 return -EOPNOTSUPP;
0cf0f6d3
JP		 2971 }
2972}
d6c862ba
JP		 2973
2974int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2975 void *cb_priv)
2976{
2977 struct mlx5e_priv *priv = cb_priv;
2978
9ab88e83 2979 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
44ae12a7
JP		 2980 return -EOPNOTSUPP;
2981
d6c862ba
JP		 2982 switch (type) {
2983 case TC_SETUP_CLSFLOWER:
2984 return mlx5e_setup_tc_cls_flower(priv, type_data);
2985 default:
2986 return -EOPNOTSUPP;
2987 }
2988}
2989
2990static int mlx5e_setup_tc_block(struct net_device *dev,
2991 struct tc_block_offload *f)
2992{
2993 struct mlx5e_priv *priv = netdev_priv(dev);
2994
2995 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
2996 return -EOPNOTSUPP;
2997
2998 switch (f->command) {
2999 case TC_BLOCK_BIND:
3000 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3001 priv, priv);
3002 case TC_BLOCK_UNBIND:
3003 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3004 priv);
3005 return 0;
3006 default:
3007 return -EOPNOTSUPP;
3008 }
3009}
e80541ec 3010#endif
a5fcf8a6 3011
9afe9a53
OG		 3012static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3013 void *type_data)
0cf0f6d3 3014{
2572ac53 3015 switch (type) {
fde6af47 3016#ifdef CONFIG_MLX5_ESWITCH
d6c862ba
JP		 3017 case TC_SETUP_BLOCK:
3018 return mlx5e_setup_tc_block(dev, type_data);
fde6af47 3019#endif
575ed7d3 3020 case TC_SETUP_QDISC_MQPRIO:
de4784ca 3021 return mlx5e_setup_tc_mqprio(dev, type_data);
e8f887ac
AV		 3022 default:
3023 return -EOPNOTSUPP;
3024 }
08fb1dac
SM		 3025}
3026
bc1f4470 3027static void
f62b8bb8
AV		 3028mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3029{
3030 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 3031 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 3032 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 3033 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 3034
370bad0f
OG		 3035 if (mlx5e_is_uplink_rep(priv)) {
3036 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3037 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3038 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3039 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3040 } else {
3041 stats->rx_packets = sstats->rx_packets;
3042 stats->rx_bytes = sstats->rx_bytes;
3043 stats->tx_packets = sstats->tx_packets;
3044 stats->tx_bytes = sstats->tx_bytes;
3045 stats->tx_dropped = sstats->tx_queue_dropped;
3046 }
269e6b3a
GP		 3047
3048 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 3049
3050 stats->rx_length_errors =
9218b44d
GP		 3051 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3052 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3053 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 3054 stats->rx_crc_errors =
9218b44d
GP		 3055 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3056 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3057 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a
GP		 3058 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3059 stats->rx_frame_errors;
3060 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3061
3062 /* vport multicast also counts packets that are dropped due to steering
3063 * or rx out of buffer
3064 */
9218b44d
GP		 3065 stats->multicast =
3066 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 3067}
3068
3069static void mlx5e_set_rx_mode(struct net_device *dev)
3070{
3071 struct mlx5e_priv *priv = netdev_priv(dev);
3072
7bb29755 3073 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3074}
3075
3076static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3077{
3078 struct mlx5e_priv *priv = netdev_priv(netdev);
3079 struct sockaddr *saddr = addr;
3080
3081 if (!is_valid_ether_addr(saddr->sa_data))
3082 return -EADDRNOTAVAIL;
3083
3084 netif_addr_lock_bh(netdev);
3085 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3086 netif_addr_unlock_bh(netdev);
3087
7bb29755 3088 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3089
3090 return 0;
3091}
3092
75b81ce7 3093#define MLX5E_SET_FEATURE(features, feature, enable) \
0e405443
GP		 3094 do { \
3095 if (enable) \
75b81ce7 3096 *features |= feature; \
0e405443 3097 else \
75b81ce7 3098 *features &= ~feature; \
0e405443
GP		 3099 } while (0)
3100
3101typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3102
3103static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 3104{
3105 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3106 struct mlx5e_channels new_channels = {};
3107 int err = 0;
3108 bool reset;
f62b8bb8
AV		 3109
3110 mutex_lock(&priv->state_lock);
f62b8bb8 3111
2e20a151
SM		 3112 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3113 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3114
2e20a151
SM		 3115 new_channels.params = priv->channels.params;
3116 new_channels.params.lro_en = enable;
3117
3118 if (!reset) {
3119 priv->channels.params = new_channels.params;
3120 err = mlx5e_modify_tirs_lro(priv);
3121 goto out;
98e81b0a 3122 }
f62b8bb8 3123
2e20a151
SM		 3124 err = mlx5e_open_channels(priv, &new_channels);
3125 if (err)
3126 goto out;
0e405443 3127
2e20a151
SM		 3128 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3129out:
9b37b07f 3130 mutex_unlock(&priv->state_lock);
0e405443
GP		 3131 return err;
3132}
3133
2b52a283 3134static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
0e405443
GP		 3135{
3136 struct mlx5e_priv *priv = netdev_priv(netdev);
3137
3138 if (enable)
2b52a283 3139 mlx5e_enable_cvlan_filter(priv);
0e405443 3140 else
2b52a283 3141 mlx5e_disable_cvlan_filter(priv);
0e405443
GP		 3142
3143 return 0;
3144}
3145
3146static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3147{
3148 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 3149
0e405443 3150 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 3151 netdev_err(netdev,
3152 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3153 return -EINVAL;
3154 }
3155
0e405443
GP		 3156 return 0;
3157}
3158
94cb1ebb
EBE		 3159static int set_feature_rx_all(struct net_device *netdev, bool enable)
3160{
3161 struct mlx5e_priv *priv = netdev_priv(netdev);
3162 struct mlx5_core_dev *mdev = priv->mdev;
3163
3164 return mlx5_set_port_fcs(mdev, !enable);
3165}
3166
102722fc
GE		 3167static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3168{
3169 struct mlx5e_priv *priv = netdev_priv(netdev);
3170 int err;
3171
3172 mutex_lock(&priv->state_lock);
3173
3174 priv->channels.params.scatter_fcs_en = enable;
3175 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3176 if (err)
3177 priv->channels.params.scatter_fcs_en = !enable;
3178
3179 mutex_unlock(&priv->state_lock);
3180
3181 return err;
3182}
3183
36350114
GP		 3184static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3185{
3186 struct mlx5e_priv *priv = netdev_priv(netdev);
ff9c852f 3187 int err = 0;
36350114
GP		 3188
3189 mutex_lock(&priv->state_lock);
3190
6a9764ef 3191 priv->channels.params.vlan_strip_disable = !enable;
ff9c852f
SM		 3192 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3193 goto unlock;
3194
3195 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
36350114 3196 if (err)
6a9764ef 3197 priv->channels.params.vlan_strip_disable = enable;
36350114 3198
ff9c852f 3199unlock:
36350114
GP		 3200 mutex_unlock(&priv->state_lock);
3201
3202 return err;
3203}
3204
45bf454a
MG		 3205#ifdef CONFIG_RFS_ACCEL
3206static int set_feature_arfs(struct net_device *netdev, bool enable)
3207{
3208 struct mlx5e_priv *priv = netdev_priv(netdev);
3209 int err;
3210
3211 if (enable)
3212 err = mlx5e_arfs_enable(priv);
3213 else
3214 err = mlx5e_arfs_disable(priv);
3215
3216 return err;
3217}
3218#endif
3219
0e405443 3220static int mlx5e_handle_feature(struct net_device *netdev,
75b81ce7 3221 netdev_features_t *features,
0e405443
GP		 3222 netdev_features_t wanted_features,
3223 netdev_features_t feature,
3224 mlx5e_feature_handler feature_handler)
3225{
3226 netdev_features_t changes = wanted_features ^ netdev->features;
3227 bool enable = !!(wanted_features & feature);
3228 int err;
3229
3230 if (!(changes & feature))
3231 return 0;
3232
3233 err = feature_handler(netdev, enable);
3234 if (err) {
b20eab15
GP		 3235 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3236 enable ? "Enable" : "Disable", &feature, err);
0e405443
GP		 3237 return err;
3238 }
3239
75b81ce7 3240 MLX5E_SET_FEATURE(features, feature, enable);
0e405443
GP		 3241 return 0;
3242}
3243
3244static int mlx5e_set_features(struct net_device *netdev,
3245 netdev_features_t features)
3246{
75b81ce7 3247 netdev_features_t oper_features = netdev->features;
be0f780b
GP		 3248 int err = 0;
3249
3250#define MLX5E_HANDLE_FEATURE(feature, handler) \
3251 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
0e405443 3252
be0f780b
GP		 3253 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3254 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
2b52a283 3255 set_feature_cvlan_filter);
be0f780b
GP		 3256 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3257 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3258 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3259 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
45bf454a 3260#ifdef CONFIG_RFS_ACCEL
be0f780b 3261 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
45bf454a 3262#endif
0e405443 3263
75b81ce7
GP		 3264 if (err) {
3265 netdev->features = oper_features;
3266 return -EINVAL;
3267 }
3268
3269 return 0;
f62b8bb8
AV		 3270}
3271
7d92d580
GP		 3272static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3273 netdev_features_t features)
3274{
3275 struct mlx5e_priv *priv = netdev_priv(netdev);
3276
3277 mutex_lock(&priv->state_lock);
3278 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3279 /* HW strips the outer C-tag header, this is a problem
3280 * for S-tag traffic.
3281 */
3282 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3283 if (!priv->channels.params.vlan_strip_disable)
3284 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3285 }
3286 mutex_unlock(&priv->state_lock);
3287
3288 return features;
3289}
3290
f62b8bb8
AV		 3291static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3292{
3293 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3294 struct mlx5e_channels new_channels = {};
3295 int curr_mtu;
98e81b0a 3296 int err = 0;
506753b0 3297 bool reset;
f62b8bb8 3298
f62b8bb8 3299 mutex_lock(&priv->state_lock);
98e81b0a 3300
6a9764ef
SM		 3301 reset = !priv->channels.params.lro_en &&
3302 (priv->channels.params.rq_wq_type !=
506753b0
TT		 3303 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3304
2e20a151 3305 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3306
2e20a151 3307 curr_mtu = netdev->mtu;
f62b8bb8 3308 netdev->mtu = new_mtu;
98e81b0a 3309
2e20a151
SM		 3310 if (!reset) {
3311 mlx5e_set_dev_port_mtu(priv);
3312 goto out;
3313 }
98e81b0a 3314
2e20a151
SM		 3315 new_channels.params = priv->channels.params;
3316 err = mlx5e_open_channels(priv, &new_channels);
3317 if (err) {
3318 netdev->mtu = curr_mtu;
3319 goto out;
3320 }
3321
3322 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
f62b8bb8 3323
2e20a151
SM		 3324out:
3325 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 3326 return err;
3327}
3328
7c39afb3
FD		 3329int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3330{
3331 struct hwtstamp_config config;
3332 int err;
3333
3334 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3335 return -EOPNOTSUPP;
3336
3337 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3338 return -EFAULT;
3339
3340 /* TX HW timestamp */
3341 switch (config.tx_type) {
3342 case HWTSTAMP_TX_OFF:
3343 case HWTSTAMP_TX_ON:
3344 break;
3345 default:
3346 return -ERANGE;
3347 }
3348
3349 mutex_lock(&priv->state_lock);
3350 /* RX HW timestamp */
3351 switch (config.rx_filter) {
3352 case HWTSTAMP_FILTER_NONE:
3353 /* Reset CQE compression to Admin default */
3354 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3355 break;
3356 case HWTSTAMP_FILTER_ALL:
3357 case HWTSTAMP_FILTER_SOME:
3358 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3359 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3360 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3361 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3362 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3363 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3364 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3365 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3366 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3367 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3368 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3369 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3370 case HWTSTAMP_FILTER_NTP_ALL:
3371 /* Disable CQE compression */
3372 netdev_warn(priv->netdev, "Disabling cqe compression");
3373 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3374 if (err) {
3375 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3376 mutex_unlock(&priv->state_lock);
3377 return err;
3378 }
3379 config.rx_filter = HWTSTAMP_FILTER_ALL;
3380 break;
3381 default:
3382 mutex_unlock(&priv->state_lock);
3383 return -ERANGE;
3384 }
3385
3386 memcpy(&priv->tstamp, &config, sizeof(config));
3387 mutex_unlock(&priv->state_lock);
3388
3389 return copy_to_user(ifr->ifr_data, &config,
3390 sizeof(config)) ? -EFAULT : 0;
3391}
3392
3393int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3394{
3395 struct hwtstamp_config *cfg = &priv->tstamp;
3396
3397 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3398 return -EOPNOTSUPP;
3399
3400 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3401}
3402
ef9814de
EBE		 3403static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3404{
1170fbd8
FD		 3405 struct mlx5e_priv *priv = netdev_priv(dev);
3406
ef9814de
EBE		 3407 switch (cmd) {
3408 case SIOCSHWTSTAMP:
1170fbd8 3409 return mlx5e_hwstamp_set(priv, ifr);
ef9814de 3410 case SIOCGHWTSTAMP:
1170fbd8 3411 return mlx5e_hwstamp_get(priv, ifr);
ef9814de
EBE		 3412 default:
3413 return -EOPNOTSUPP;
3414 }
3415}
3416
e80541ec 3417#ifdef CONFIG_MLX5_ESWITCH
66e49ded
SM		 3418static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3419{
3420 struct mlx5e_priv *priv = netdev_priv(dev);
3421 struct mlx5_core_dev *mdev = priv->mdev;
3422
3423 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3424}
3425
79aab093
MS		 3426static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3427 __be16 vlan_proto)
66e49ded
SM		 3428{
3429 struct mlx5e_priv *priv = netdev_priv(dev);
3430 struct mlx5_core_dev *mdev = priv->mdev;
3431
79aab093
MS		 3432 if (vlan_proto != htons(ETH_P_8021Q))
3433 return -EPROTONOSUPPORT;
3434
66e49ded
SM		 3435 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3436 vlan, qos);
3437}
3438
f942380c
MHY		 3439static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3440{
3441 struct mlx5e_priv *priv = netdev_priv(dev);
3442 struct mlx5_core_dev *mdev = priv->mdev;
3443
3444 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3445}
3446
1edc57e2
MHY		 3447static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3448{
3449 struct mlx5e_priv *priv = netdev_priv(dev);
3450 struct mlx5_core_dev *mdev = priv->mdev;
3451
3452 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3453}
bd77bf1c
MHY		 3454
3455static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3456 int max_tx_rate)
3457{
3458 struct mlx5e_priv *priv = netdev_priv(dev);
3459 struct mlx5_core_dev *mdev = priv->mdev;
3460
bd77bf1c 3461 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3462 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3463}
3464
66e49ded
SM		 3465static int mlx5_vport_link2ifla(u8 esw_link)
3466{
3467 switch (esw_link) {
3468 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3469 return IFLA_VF_LINK_STATE_DISABLE;
3470 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3471 return IFLA_VF_LINK_STATE_ENABLE;
3472 }
3473 return IFLA_VF_LINK_STATE_AUTO;
3474}
3475
3476static int mlx5_ifla_link2vport(u8 ifla_link)
3477{
3478 switch (ifla_link) {
3479 case IFLA_VF_LINK_STATE_DISABLE:
3480 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3481 case IFLA_VF_LINK_STATE_ENABLE:
3482 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3483 }
3484 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3485}
3486
3487static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3488 int link_state)
3489{
3490 struct mlx5e_priv *priv = netdev_priv(dev);
3491 struct mlx5_core_dev *mdev = priv->mdev;
3492
3493 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3494 mlx5_ifla_link2vport(link_state));
3495}
3496
3497static int mlx5e_get_vf_config(struct net_device *dev,
3498 int vf, struct ifla_vf_info *ivi)
3499{
3500 struct mlx5e_priv *priv = netdev_priv(dev);
3501 struct mlx5_core_dev *mdev = priv->mdev;
3502 int err;
3503
3504 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3505 if (err)
3506 return err;
3507 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3508 return 0;
3509}
3510
3511static int mlx5e_get_vf_stats(struct net_device *dev,
3512 int vf, struct ifla_vf_stats *vf_stats)
3513{
3514 struct mlx5e_priv *priv = netdev_priv(dev);
3515 struct mlx5_core_dev *mdev = priv->mdev;
3516
3517 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3518 vf_stats);
3519}
e80541ec 3520#endif
66e49ded 3521
1ad9a00a
PB		 3522static void mlx5e_add_vxlan_port(struct net_device *netdev,
3523 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3524{
3525 struct mlx5e_priv *priv = netdev_priv(netdev);
3526
974c3f30
AD		 3527 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3528 return;
3529
b3f63c3d
MF		 3530 if (!mlx5e_vxlan_allowed(priv->mdev))
3531 return;
3532
974c3f30 3533 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3534}
3535
1ad9a00a
PB		 3536static void mlx5e_del_vxlan_port(struct net_device *netdev,
3537 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3538{
3539 struct mlx5e_priv *priv = netdev_priv(netdev);
3540
974c3f30
AD		 3541 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3542 return;
3543
b3f63c3d
MF		 3544 if (!mlx5e_vxlan_allowed(priv->mdev))
3545 return;
3546
974c3f30 3547 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3548}
3549
27299841
GP		 3550static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3551 struct sk_buff *skb,
3552 netdev_features_t features)
b3f63c3d 3553{
2989ad1e 3554 unsigned int offset = 0;
b3f63c3d 3555 struct udphdr *udph;
27299841
GP		 3556 u8 proto;
3557 u16 port;
b3f63c3d
MF		 3558
3559 switch (vlan_get_protocol(skb)) {
3560 case htons(ETH_P_IP):
3561 proto = ip_hdr(skb)->protocol;
3562 break;
3563 case htons(ETH_P_IPV6):
2989ad1e 3564 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
b3f63c3d
MF		 3565 break;
3566 default:
3567 goto out;
3568 }
3569
27299841
GP		 3570 switch (proto) {
3571 case IPPROTO_GRE:
3572 return features;
3573 case IPPROTO_UDP:
b3f63c3d
MF		 3574 udph = udp_hdr(skb);
3575 port = be16_to_cpu(udph->dest);
b3f63c3d 3576
27299841
GP		 3577 /* Verify if UDP port is being offloaded by HW */
3578 if (mlx5e_vxlan_lookup_port(priv, port))
3579 return features;
3580 }
b3f63c3d
MF		 3581
3582out:
3583 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3584 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3585}
3586
3587static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3588 struct net_device *netdev,
3589 netdev_features_t features)
3590{
3591 struct mlx5e_priv *priv = netdev_priv(netdev);
3592
3593 features = vlan_features_check(skb, features);
3594 features = vxlan_features_check(skb, features);
3595
2ac9cfe7
IT		 3596#ifdef CONFIG_MLX5_EN_IPSEC
3597 if (mlx5e_ipsec_feature_check(skb, netdev, features))
3598 return features;
3599#endif
3600
b3f63c3d
MF		 3601 /* Validate if the tunneled packet is being offloaded by HW */
3602 if (skb->encapsulation &&
3603 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
27299841 3604 return mlx5e_tunnel_features_check(priv, skb, features);
b3f63c3d
MF		 3605
3606 return features;
3607}
3608
7ca560b5
EBE		 3609static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
3610 struct mlx5e_txqsq *sq)
3611{
3612 struct mlx5e_priv *priv = netdev_priv(dev);
3613 struct mlx5_core_dev *mdev = priv->mdev;
3614 int irqn_not_used, eqn;
3615 struct mlx5_eq *eq;
3616 u32 eqe_count;
3617
3618 if (mlx5_vector2eqn(mdev, sq->cq.mcq.vector, &eqn, &irqn_not_used))
3619 return false;
3620
3621 eq = mlx5_eqn2eq(mdev, eqn);
3622 if (IS_ERR(eq))
3623 return false;
3624
3625 netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
3626 eqn, eq->cons_index, eq->irqn);
3627
3628 eqe_count = mlx5_eq_poll_irq_disabled(eq);
3629 if (!eqe_count)
3630 return false;
3631
3632 netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
57d689a8 3633 sq->channel->stats.eq_rearm++;
7ca560b5
EBE		 3634 return true;
3635}
3636
3947ca18
DJ		 3637static void mlx5e_tx_timeout(struct net_device *dev)
3638{
3639 struct mlx5e_priv *priv = netdev_priv(dev);
7ca560b5 3640 bool reopen_channels = false;
3947ca18
DJ		 3641 int i;
3642
3643 netdev_err(dev, "TX timeout detected\n");
3644
6a9764ef 3645 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
84990945 3646 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
acc6c595 3647 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3947ca18 3648
84990945 3649 if (!netif_xmit_stopped(dev_queue))
3947ca18 3650 continue;
84990945
EBE		 3651 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
3652 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
3653 jiffies_to_usecs(jiffies - dev_queue->trans_start));
3a32b26a 3654
7ca560b5
EBE		 3655 /* If we recover a lost interrupt, most likely TX timeout will
3656 * be resolved, skip reopening channels
3657 */
3658 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
3659 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3660 reopen_channels = true;
3661 }
3947ca18
DJ		 3662 }
3663
7ca560b5 3664 if (reopen_channels && test_bit(MLX5E_STATE_OPENED, &priv->state))
3947ca18
DJ		 3665 schedule_work(&priv->tx_timeout_work);
3666}
3667
86994156
RS		 3668static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3669{
3670 struct mlx5e_priv *priv = netdev_priv(netdev);
3671 struct bpf_prog *old_prog;
3672 int err = 0;
3673 bool reset, was_opened;
3674 int i;
3675
3676 mutex_lock(&priv->state_lock);
3677
3678 if ((netdev->features & NETIF_F_LRO) && prog) {
3679 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3680 err = -EINVAL;
3681 goto unlock;
3682 }
3683
547eede0
IT		 3684 if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3685 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3686 err = -EINVAL;
3687 goto unlock;
3688 }
3689
86994156
RS		 3690 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3691 /* no need for full reset when exchanging programs */
6a9764ef 3692 reset = (!priv->channels.params.xdp_prog || !prog);
86994156
RS		 3693
3694 if (was_opened && reset)
3695 mlx5e_close_locked(netdev);
c54c0629
DB		 3696 if (was_opened && !reset) {
3697 /* num_channels is invariant here, so we can take the
3698 * batched reference right upfront.
3699 */
6a9764ef 3700 prog = bpf_prog_add(prog, priv->channels.num);
c54c0629
DB		 3701 if (IS_ERR(prog)) {
3702 err = PTR_ERR(prog);
3703 goto unlock;
3704 }
3705 }
86994156 3706
c54c0629
DB		 3707 /* exchange programs, extra prog reference we got from caller
3708 * as long as we don't fail from this point onwards.
3709 */
6a9764ef 3710 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
86994156
RS		 3711 if (old_prog)
3712 bpf_prog_put(old_prog);
3713
3714 if (reset) /* change RQ type according to priv->xdp_prog */
6a9764ef 3715 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
86994156
RS		 3716
3717 if (was_opened && reset)
3718 mlx5e_open_locked(netdev);
3719
3720 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3721 goto unlock;
3722
3723 /* exchanging programs w/o reset, we update ref counts on behalf
3724 * of the channels RQs here.
3725 */
ff9c852f
SM		 3726 for (i = 0; i < priv->channels.num; i++) {
3727 struct mlx5e_channel *c = priv->channels.c[i];
86994156 3728
c0f1147d 3729 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3730 napi_synchronize(&c->napi);
3731 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3732
3733 old_prog = xchg(&c->rq.xdp_prog, prog);
3734
c0f1147d 3735 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156 3736 /* napi_schedule in case we have missed anything */
86994156
RS		 3737 napi_schedule(&c->napi);
3738
3739 if (old_prog)
3740 bpf_prog_put(old_prog);
3741 }
3742
3743unlock:
3744 mutex_unlock(&priv->state_lock);
3745 return err;
3746}
3747
821b2e29 3748static u32 mlx5e_xdp_query(struct net_device *dev)
86994156
RS		 3749{
3750 struct mlx5e_priv *priv = netdev_priv(dev);
821b2e29
MKL		 3751 const struct bpf_prog *xdp_prog;
3752 u32 prog_id = 0;
86994156 3753
821b2e29
MKL		 3754 mutex_lock(&priv->state_lock);
3755 xdp_prog = priv->channels.params.xdp_prog;
3756 if (xdp_prog)
3757 prog_id = xdp_prog->aux->id;
3758 mutex_unlock(&priv->state_lock);
3759
3760 return prog_id;
86994156
RS		 3761}
3762
f4e63525 3763static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
86994156
RS		 3764{
3765 switch (xdp->command) {
3766 case XDP_SETUP_PROG:
3767 return mlx5e_xdp_set(dev, xdp->prog);
3768 case XDP_QUERY_PROG:
821b2e29
MKL		 3769 xdp->prog_id = mlx5e_xdp_query(dev);
3770 xdp->prog_attached = !!xdp->prog_id;
86994156
RS		 3771 return 0;
3772 default:
3773 return -EINVAL;
3774 }
3775}
3776
80378384
CO		 3777#ifdef CONFIG_NET_POLL_CONTROLLER
3778/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3779 * reenabling interrupts.
3780 */
3781static void mlx5e_netpoll(struct net_device *dev)
3782{
3783 struct mlx5e_priv *priv = netdev_priv(dev);
ff9c852f
SM		 3784 struct mlx5e_channels *chs = &priv->channels;
3785
80378384
CO		 3786 int i;
3787
ff9c852f
SM		 3788 for (i = 0; i < chs->num; i++)
3789 napi_schedule(&chs->c[i]->napi);
80378384
CO		 3790}
3791#endif
3792
e80541ec 3793static const struct net_device_ops mlx5e_netdev_ops = {
f62b8bb8
AV		 3794 .ndo_open = mlx5e_open,
3795 .ndo_stop = mlx5e_close,
3796 .ndo_start_xmit = mlx5e_xmit,
0cf0f6d3 3797 .ndo_setup_tc = mlx5e_setup_tc,
08fb1dac 3798 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3799 .ndo_get_stats64 = mlx5e_get_stats,
3800 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3801 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3802 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3803 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3804 .ndo_set_features = mlx5e_set_features,
7d92d580 3805 .ndo_fix_features = mlx5e_fix_features,
b0eed40e
SM		 3806 .ndo_change_mtu = mlx5e_change_mtu,
3807 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3808 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
706b3583
SM		 3809 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3810 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3811 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3812#ifdef CONFIG_RFS_ACCEL
3813 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3814#endif
3947ca18 3815 .ndo_tx_timeout = mlx5e_tx_timeout,
f4e63525 3816 .ndo_bpf = mlx5e_xdp,
80378384
CO		 3817#ifdef CONFIG_NET_POLL_CONTROLLER
3818 .ndo_poll_controller = mlx5e_netpoll,
3819#endif
e80541ec 3820#ifdef CONFIG_MLX5_ESWITCH
706b3583 3821 /* SRIOV E-Switch NDOs */
b0eed40e
SM		 3822 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3823 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3824 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3825 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3826 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3827 .ndo_get_vf_config = mlx5e_get_vf_config,
3828 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3829 .ndo_get_vf_stats = mlx5e_get_vf_stats,
370bad0f
OG		 3830 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3831 .ndo_get_offload_stats = mlx5e_get_offload_stats,
e80541ec 3832#endif
f62b8bb8
AV		 3833};
3834
3835static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3836{
3837 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 3838 return -EOPNOTSUPP;
f62b8bb8
AV		 3839 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3840 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3841 !MLX5_CAP_ETH(mdev, csum_cap) ||
3842 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3843 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3844 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3845 MLX5_CAP_FLOWTABLE(mdev,
3846 flow_table_properties_nic_receive.max_ft_level)
3847 < 3) {
f62b8bb8
AV		 3848 mlx5_core_warn(mdev,
3849 "Not creating net device, some required device capabilities are missing\n");
9eb78923 3850 return -EOPNOTSUPP;
f62b8bb8 3851 }
66189961
TT		 3852 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3853 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8 3854 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3e432ab6 3855 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
66189961 3856
f62b8bb8
AV		 3857 return 0;
3858}
3859
58d52291
AS		 3860u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3861{
3862 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3863
3864 return bf_buf_size -
3865 sizeof(struct mlx5e_tx_wqe) +
3866 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3867}
3868
d4b6c488 3869void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
85082dba
TT		 3870 int num_channels)
3871{
3872 int i;
3873
3874 for (i = 0; i < len; i++)
3875 indirection_rqt[i] = i % num_channels;
3876}
3877
b797a684
SM		 3878static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3879{
3880 enum pcie_link_width width;
3881 enum pci_bus_speed speed;
3882 int err = 0;
3883
3884 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3885 if (err)
3886 return err;
3887
3888 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3889 return -EINVAL;
3890
3891 switch (speed) {
3892 case PCIE_SPEED_2_5GT:
3893 *pci_bw = 2500 * width;
3894 break;
3895 case PCIE_SPEED_5_0GT:
3896 *pci_bw = 5000 * width;
3897 break;
3898 case PCIE_SPEED_8_0GT:
3899 *pci_bw = 8000 * width;
3900 break;
3901 default:
3902 return -EINVAL;
3903 }
3904
3905 return 0;
3906}
3907
0608d4db 3908static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
b797a684 3909{
0608d4db
TT		 3910 u32 link_speed = 0;
3911 u32 pci_bw = 0;
b797a684 3912
0608d4db
TT		 3913 mlx5e_get_max_linkspeed(mdev, &link_speed);
3914 mlx5e_get_pci_bw(mdev, &pci_bw);
3915 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
3916 link_speed, pci_bw);
3917
3918#define MLX5E_SLOW_PCI_RATIO (2)
3919
3920 return link_speed && pci_bw &&
3921 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
0f6e4cf6
EBE		 3922}
3923
0088cbbc
TG		 3924void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3925{
3926 params->tx_cq_moderation.cq_period_mode = cq_period_mode;
3927
3928 params->tx_cq_moderation.pkts =
3929 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3930 params->tx_cq_moderation.usec =
3931 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3932
3933 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3934 params->tx_cq_moderation.usec =
3935 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
3936
3937 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
3938 params->tx_cq_moderation.cq_period_mode ==
3939 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3940}
3941
9908aa29
TT		 3942void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3943{
0088cbbc 3944 params->rx_cq_moderation.cq_period_mode = cq_period_mode;
9908aa29
TT		 3945
3946 params->rx_cq_moderation.pkts =
3947 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3948 params->rx_cq_moderation.usec =
0088cbbc 3949 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
9908aa29
TT		 3950
3951 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3952 params->rx_cq_moderation.usec =
3953 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
6a9764ef 3954
9a317425
AG		 3955 if (params->rx_dim_enabled) {
3956 switch (cq_period_mode) {
3957 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
3958 params->rx_cq_moderation =
3959 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE);
3960 break;
3961 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
3962 default:
3963 params->rx_cq_moderation =
3964 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE);
3965 }
3966 }
457fcd8a 3967
6a9764ef 3968 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
0088cbbc
TG		 3969 params->rx_cq_moderation.cq_period_mode ==
3970 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29
TT		 3971}
3972
707129dc 3973static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
2b029556
SM		 3974{
3975 int i;
3976
3977 /* The supported periods are organized in ascending order */
3978 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3979 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3980 break;
3981
3982 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3983}
3984
8f493ffd
SM		 3985void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3986 struct mlx5e_params *params,
3987 u16 max_channels)
f62b8bb8 3988{
6a9764ef 3989 u8 cq_period_mode = 0;
2fc4bfb7 3990
6a9764ef
SM		 3991 params->num_channels = max_channels;
3992 params->num_tc = 1;
2b029556 3993
6a9764ef
SM		 3994 /* SQ */
3995 params->log_sq_size = is_kdump_kernel() ?
b4e029da
KH		 3996 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3997 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3998
b797a684 3999 /* set CQE compression */
6a9764ef 4000 params->rx_cqe_compress_def = false;
b797a684 4001 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
e53eef63 4002 MLX5_CAP_GEN(mdev, vport_group_manager))
0608d4db 4003 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
0f6e4cf6 4004
6a9764ef
SM		 4005 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4006
4007 /* RQ */
4008 mlx5e_set_rq_params(mdev, params);
b797a684 4009
6a9764ef 4010 /* HW LRO */
c139dbfd 4011
5426a0b2 4012 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
6a9764ef 4013 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
0608d4db 4014 params->lro_en = !slow_pci_heuristic(mdev);
6a9764ef 4015 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
b0d4660b 4016
6a9764ef
SM		 4017 /* CQ moderation params */
4018 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4019 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4020 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
9a317425 4021 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
6a9764ef 4022 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
0088cbbc 4023 mlx5e_set_tx_cq_mode_params(params, cq_period_mode);
9908aa29 4024
6a9764ef
SM		 4025 /* TX inline */
4026 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
fbcb127e 4027 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
a6f402e4 4028
6a9764ef
SM		 4029 /* RSS */
4030 params->rss_hfunc = ETH_RSS_HASH_XOR;
4031 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
d4b6c488 4032 mlx5e_build_default_indir_rqt(params->indirection_rqt,
6a9764ef
SM		 4033 MLX5E_INDIR_RQT_SIZE, max_channels);
4034}
f62b8bb8 4035
6a9764ef
SM		 4036static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4037 struct net_device *netdev,
4038 const struct mlx5e_profile *profile,
4039 void *ppriv)
4040{
4041 struct mlx5e_priv *priv = netdev_priv(netdev);
57afead5 4042
6a9764ef
SM		 4043 priv->mdev = mdev;
4044 priv->netdev = netdev;
4045 priv->profile = profile;
4046 priv->ppriv = ppriv;
79c48764 4047 priv->msglevel = MLX5E_MSG_LEVEL;
c139dbfd 4048 priv->hard_mtu = MLX5E_ETH_HARD_MTU;
2d75b2bc 4049
6a9764ef 4050 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
9908aa29 4051
f62b8bb8
AV		 4052 mutex_init(&priv->state_lock);
4053
4054 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4055 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 4056 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8 4057 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
237f258c
FD		 4058
4059 mlx5e_timestamp_init(priv);
f62b8bb8
AV		 4060}
4061
4062static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4063{
4064 struct mlx5e_priv *priv = netdev_priv(netdev);
4065
e1d7d349 4066 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 4067 if (is_zero_ether_addr(netdev->dev_addr) &&
4068 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4069 eth_hw_addr_random(netdev);
4070 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4071 }
f62b8bb8
AV		 4072}
4073
e80541ec 4074#if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
cb67b832
HHZ		 4075static const struct switchdev_ops mlx5e_switchdev_ops = {
4076 .switchdev_port_attr_get = mlx5e_attr_get,
4077};
e80541ec 4078#endif
cb67b832 4079
6bfd390b 4080static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 4081{
4082 struct mlx5e_priv *priv = netdev_priv(netdev);
4083 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 4084 bool fcs_supported;
4085 bool fcs_enabled;
f62b8bb8
AV		 4086
4087 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4088
e80541ec
SM		 4089 netdev->netdev_ops = &mlx5e_netdev_ops;
4090
08fb1dac 4091#ifdef CONFIG_MLX5_CORE_EN_DCB
e80541ec
SM		 4092 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4093 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac 4094#endif
66e49ded 4095
f62b8bb8
AV		 4096 netdev->watchdog_timeo = 15 * HZ;
4097
4098 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4099
12be4b21 4100 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 4101 netdev->vlan_features |= NETIF_F_IP_CSUM;
4102 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4103 netdev->vlan_features |= NETIF_F_GRO;
4104 netdev->vlan_features |= NETIF_F_TSO;
4105 netdev->vlan_features |= NETIF_F_TSO6;
4106 netdev->vlan_features |= NETIF_F_RXCSUM;
4107 netdev->vlan_features |= NETIF_F_RXHASH;
4108
71186172
AH		 4109 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4110 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4111
f62b8bb8
AV		 4112 if (!!MLX5_CAP_ETH(mdev, lro_cap))
4113 netdev->vlan_features |= NETIF_F_LRO;
4114
4115 netdev->hw_features = netdev->vlan_features;
e4cf27bd 4116 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 4117 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4118 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4382c7b9 4119 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
f62b8bb8 4120
27299841
GP		 4121 if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4122 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
b3f63c3d 4123 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 4124 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 4125 netdev->hw_enc_features |= NETIF_F_TSO;
4126 netdev->hw_enc_features |= NETIF_F_TSO6;
27299841
GP		 4127 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4128 }
4129
4130 if (mlx5e_vxlan_allowed(mdev)) {
4131 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4132 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4133 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4134 NETIF_F_GSO_UDP_TUNNEL_CSUM;
b49663c8 4135 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 4136 }
4137
27299841
GP		 4138 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4139 netdev->hw_features |= NETIF_F_GSO_GRE |
4140 NETIF_F_GSO_GRE_CSUM;
4141 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4142 NETIF_F_GSO_GRE_CSUM;
4143 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4144 NETIF_F_GSO_GRE_CSUM;
4145 }
4146
94cb1ebb
EBE		 4147 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4148
4149 if (fcs_supported)
4150 netdev->hw_features |= NETIF_F_RXALL;
4151
102722fc
GE		 4152 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4153 netdev->hw_features |= NETIF_F_RXFCS;
4154
f62b8bb8 4155 netdev->features = netdev->hw_features;
6a9764ef 4156 if (!priv->channels.params.lro_en)
f62b8bb8
AV		 4157 netdev->features &= ~NETIF_F_LRO;
4158
94cb1ebb
EBE		 4159 if (fcs_enabled)
4160 netdev->features &= ~NETIF_F_RXALL;
4161
102722fc
GE		 4162 if (!priv->channels.params.scatter_fcs_en)
4163 netdev->features &= ~NETIF_F_RXFCS;
4164
e8f887ac
AV		 4165#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4166 if (FT_CAP(flow_modify_en) &&
4167 FT_CAP(modify_root) &&
4168 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 4169 FT_CAP(flow_table_modify)) {
4170 netdev->hw_features |= NETIF_F_HW_TC;
4171#ifdef CONFIG_RFS_ACCEL
4172 netdev->hw_features |= NETIF_F_NTUPLE;
4173#endif
4174 }
e8f887ac 4175
f62b8bb8 4176 netdev->features |= NETIF_F_HIGHDMA;
7d92d580 4177 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
f62b8bb8
AV		 4178
4179 netdev->priv_flags |= IFF_UNICAST_FLT;
4180
4181 mlx5e_set_netdev_dev_addr(netdev);
cb67b832 4182
e80541ec 4183#if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
a9f7705f 4184 if (MLX5_VPORT_MANAGER(mdev))
cb67b832
HHZ		 4185 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4186#endif
547eede0
IT		 4187
4188 mlx5e_ipsec_build_netdev(priv);
f62b8bb8
AV		 4189}
4190
7cbaf9a3 4191static void mlx5e_create_q_counters(struct mlx5e_priv *priv)
593cf338
RS		 4192{
4193 struct mlx5_core_dev *mdev = priv->mdev;
4194 int err;
4195
4196 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4197 if (err) {
4198 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4199 priv->q_counter = 0;
4200 }
7cbaf9a3
MS		 4201
4202 err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4203 if (err) {
4204 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4205 priv->drop_rq_q_counter = 0;
4206 }
593cf338
RS		 4207}
4208
7cbaf9a3 4209static void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
593cf338 4210{
7cbaf9a3
MS		 4211 if (priv->q_counter)
4212 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
593cf338 4213
7cbaf9a3
MS		 4214 if (priv->drop_rq_q_counter)
4215 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
593cf338
RS		 4216}
4217
6bfd390b
HHZ		 4218static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4219 struct net_device *netdev,
127ea380
HHZ		 4220 const struct mlx5e_profile *profile,
4221 void *ppriv)
6bfd390b
HHZ		 4222{
4223 struct mlx5e_priv *priv = netdev_priv(netdev);
547eede0 4224 int err;
6bfd390b 4225
127ea380 4226 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
547eede0
IT		 4227 err = mlx5e_ipsec_init(priv);
4228 if (err)
4229 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
6bfd390b
HHZ		 4230 mlx5e_build_nic_netdev(netdev);
4231 mlx5e_vxlan_init(priv);
4232}
4233
4234static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4235{
547eede0 4236 mlx5e_ipsec_cleanup(priv);
6bfd390b
HHZ		 4237 mlx5e_vxlan_cleanup(priv);
4238}
4239
4240static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4241{
4242 struct mlx5_core_dev *mdev = priv->mdev;
4243 int err;
6bfd390b 4244
8f493ffd
SM		 4245 err = mlx5e_create_indirect_rqt(priv);
4246 if (err)
6bfd390b 4247 return err;
6bfd390b
HHZ		 4248
4249 err = mlx5e_create_direct_rqts(priv);
8f493ffd 4250 if (err)
6bfd390b 4251 goto err_destroy_indirect_rqts;
6bfd390b
HHZ		 4252
4253 err = mlx5e_create_indirect_tirs(priv);
8f493ffd 4254 if (err)
6bfd390b 4255 goto err_destroy_direct_rqts;
6bfd390b
HHZ		 4256
4257 err = mlx5e_create_direct_tirs(priv);
8f493ffd 4258 if (err)
6bfd390b 4259 goto err_destroy_indirect_tirs;
6bfd390b
HHZ		 4260
4261 err = mlx5e_create_flow_steering(priv);
4262 if (err) {
4263 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4264 goto err_destroy_direct_tirs;
4265 }
4266
4267 err = mlx5e_tc_init(priv);
4268 if (err)
4269 goto err_destroy_flow_steering;
4270
4271 return 0;
4272
4273err_destroy_flow_steering:
4274 mlx5e_destroy_flow_steering(priv);
4275err_destroy_direct_tirs:
4276 mlx5e_destroy_direct_tirs(priv);
4277err_destroy_indirect_tirs:
4278 mlx5e_destroy_indirect_tirs(priv);
4279err_destroy_direct_rqts:
8f493ffd 4280 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4281err_destroy_indirect_rqts:
4282 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4283 return err;
4284}
4285
4286static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4287{
6bfd390b
HHZ		 4288 mlx5e_tc_cleanup(priv);
4289 mlx5e_destroy_flow_steering(priv);
4290 mlx5e_destroy_direct_tirs(priv);
4291 mlx5e_destroy_indirect_tirs(priv);
8f493ffd 4292 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4293 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4294}
4295
4296static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4297{
4298 int err;
4299
4300 err = mlx5e_create_tises(priv);
4301 if (err) {
4302 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4303 return err;
4304 }
4305
4306#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 4307 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 4308#endif
4309 return 0;
4310}
4311
4312static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4313{
4314 struct net_device *netdev = priv->netdev;
4315 struct mlx5_core_dev *mdev = priv->mdev;
2c3b5bee
SM		 4316 u16 max_mtu;
4317
4318 mlx5e_init_l2_addr(priv);
4319
63bfd399
EBE		 4320 /* Marking the link as currently not needed by the Driver */
4321 if (!netif_running(netdev))
4322 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4323
2c3b5bee
SM		 4324 /* MTU range: 68 - hw-specific max */
4325 netdev->min_mtu = ETH_MIN_MTU;
4326 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
c139dbfd 4327 netdev->max_mtu = MLX5E_HW2SW_MTU(priv, max_mtu);
2c3b5bee 4328 mlx5e_set_dev_port_mtu(priv);
6bfd390b 4329
7907f23a
AH		 4330 mlx5_lag_add(mdev, netdev);
4331
6bfd390b 4332 mlx5e_enable_async_events(priv);
127ea380 4333
a9f7705f 4334 if (MLX5_VPORT_MANAGER(priv->mdev))
1d447a39 4335 mlx5e_register_vport_reps(priv);
2c3b5bee 4336
610e89e0
SM		 4337 if (netdev->reg_state != NETREG_REGISTERED)
4338 return;
2a5e7a13
HN		 4339#ifdef CONFIG_MLX5_CORE_EN_DCB
4340 mlx5e_dcbnl_init_app(priv);
4341#endif
610e89e0
SM		 4342 /* Device already registered: sync netdev system state */
4343 if (mlx5e_vxlan_allowed(mdev)) {
4344 rtnl_lock();
4345 udp_tunnel_get_rx_info(netdev);
4346 rtnl_unlock();
4347 }
4348
4349 queue_work(priv->wq, &priv->set_rx_mode_work);
2c3b5bee
SM		 4350
4351 rtnl_lock();
4352 if (netif_running(netdev))
4353 mlx5e_open(netdev);
4354 netif_device_attach(netdev);
4355 rtnl_unlock();
6bfd390b
HHZ		 4356}
4357
4358static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4359{
3deef8ce 4360 struct mlx5_core_dev *mdev = priv->mdev;
3deef8ce 4361
2a5e7a13
HN		 4362#ifdef CONFIG_MLX5_CORE_EN_DCB
4363 if (priv->netdev->reg_state == NETREG_REGISTERED)
4364 mlx5e_dcbnl_delete_app(priv);
4365#endif
4366
2c3b5bee
SM		 4367 rtnl_lock();
4368 if (netif_running(priv->netdev))
4369 mlx5e_close(priv->netdev);
4370 netif_device_detach(priv->netdev);
4371 rtnl_unlock();
4372
6bfd390b 4373 queue_work(priv->wq, &priv->set_rx_mode_work);
1d447a39 4374
a9f7705f 4375 if (MLX5_VPORT_MANAGER(priv->mdev))
1d447a39
SM		 4376 mlx5e_unregister_vport_reps(priv);
4377
6bfd390b 4378 mlx5e_disable_async_events(priv);
3deef8ce 4379 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 4380}
4381
4382static const struct mlx5e_profile mlx5e_nic_profile = {
4383 .init = mlx5e_nic_init,
4384 .cleanup = mlx5e_nic_cleanup,
4385 .init_rx = mlx5e_init_nic_rx,
4386 .cleanup_rx = mlx5e_cleanup_nic_rx,
4387 .init_tx = mlx5e_init_nic_tx,
4388 .cleanup_tx = mlx5e_cleanup_nic_tx,
4389 .enable = mlx5e_nic_enable,
4390 .disable = mlx5e_nic_disable,
3834a5e6 4391 .update_stats = mlx5e_update_ndo_stats,
6bfd390b 4392 .max_nch = mlx5e_get_max_num_channels,
7ca42c80 4393 .update_carrier = mlx5e_update_carrier,
20fd0c19
SM		 4394 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4395 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
6bfd390b
HHZ		 4396 .max_tc = MLX5E_MAX_NUM_TC,
4397};
4398
2c3b5bee
SM		 4399/* mlx5e generic netdev management API (move to en_common.c) */
4400
26e59d80
MHY		 4401struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4402 const struct mlx5e_profile *profile,
4403 void *ppriv)
f62b8bb8 4404{
26e59d80 4405 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 4406 struct net_device *netdev;
4407 struct mlx5e_priv *priv;
f62b8bb8 4408
08fb1dac 4409 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 4410 nch * profile->max_tc,
08fb1dac 4411 nch);
f62b8bb8
AV		 4412 if (!netdev) {
4413 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4414 return NULL;
4415 }
4416
be4891af
SM		 4417#ifdef CONFIG_RFS_ACCEL
4418 netdev->rx_cpu_rmap = mdev->rmap;
4419#endif
4420
127ea380 4421 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 4422
4423 netif_carrier_off(netdev);
4424
4425 priv = netdev_priv(netdev);
4426
7bb29755
MF		 4427 priv->wq = create_singlethread_workqueue("mlx5e");
4428 if (!priv->wq)
26e59d80
MHY		 4429 goto err_cleanup_nic;
4430
4431 return netdev;
4432
4433err_cleanup_nic:
31ac9338
OG		 4434 if (profile->cleanup)
4435 profile->cleanup(priv);
26e59d80
MHY		 4436 free_netdev(netdev);
4437
4438 return NULL;
4439}
4440
2c3b5bee 4441int mlx5e_attach_netdev(struct mlx5e_priv *priv)
26e59d80 4442{
2c3b5bee 4443 struct mlx5_core_dev *mdev = priv->mdev;
26e59d80 4444 const struct mlx5e_profile *profile;
26e59d80
MHY		 4445 int err;
4446
26e59d80
MHY		 4447 profile = priv->profile;
4448 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 4449
6bfd390b
HHZ		 4450 err = profile->init_tx(priv);
4451 if (err)
ec8b9981 4452 goto out;
5c50368f 4453
7cbaf9a3
MS		 4454 mlx5e_create_q_counters(priv);
4455
4456 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5c50368f
AS		 4457 if (err) {
4458 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
7cbaf9a3 4459 goto err_destroy_q_counters;
5c50368f
AS		 4460 }
4461
6bfd390b
HHZ		 4462 err = profile->init_rx(priv);
4463 if (err)
5c50368f 4464 goto err_close_drop_rq;
5c50368f 4465
6bfd390b
HHZ		 4466 if (profile->enable)
4467 profile->enable(priv);
f62b8bb8 4468
26e59d80 4469 return 0;
5c50368f
AS		 4470
4471err_close_drop_rq:
a43b25da 4472 mlx5e_close_drop_rq(&priv->drop_rq);
5c50368f 4473
7cbaf9a3
MS		 4474err_destroy_q_counters:
4475 mlx5e_destroy_q_counters(priv);
6bfd390b 4476 profile->cleanup_tx(priv);
5c50368f 4477
26e59d80
MHY		 4478out:
4479 return err;
f62b8bb8
AV		 4480}
4481
2c3b5bee 4482void mlx5e_detach_netdev(struct mlx5e_priv *priv)
26e59d80 4483{
26e59d80
MHY		 4484 const struct mlx5e_profile *profile = priv->profile;
4485
4486 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80 4487
37f304d1
SM		 4488 if (profile->disable)
4489 profile->disable(priv);
4490 flush_workqueue(priv->wq);
4491
26e59d80 4492 profile->cleanup_rx(priv);
a43b25da 4493 mlx5e_close_drop_rq(&priv->drop_rq);
7cbaf9a3 4494 mlx5e_destroy_q_counters(priv);
26e59d80 4495 profile->cleanup_tx(priv);
26e59d80
MHY		 4496 cancel_delayed_work_sync(&priv->update_stats_work);
4497}
4498
2c3b5bee
SM		 4499void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4500{
4501 const struct mlx5e_profile *profile = priv->profile;
4502 struct net_device *netdev = priv->netdev;
4503
4504 destroy_workqueue(priv->wq);
4505 if (profile->cleanup)
4506 profile->cleanup(priv);
4507 free_netdev(netdev);
4508}
4509
26e59d80
MHY		 4510/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4511 * hardware contexts and to connect it to the current netdev.
4512 */
4513static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4514{
4515 struct mlx5e_priv *priv = vpriv;
4516 struct net_device *netdev = priv->netdev;
4517 int err;
4518
4519 if (netif_device_present(netdev))
4520 return 0;
4521
4522 err = mlx5e_create_mdev_resources(mdev);
4523 if (err)
4524 return err;
4525
2c3b5bee 4526 err = mlx5e_attach_netdev(priv);
26e59d80
MHY		 4527 if (err) {
4528 mlx5e_destroy_mdev_resources(mdev);
4529 return err;
4530 }
4531
4532 return 0;
4533}
4534
4535static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4536{
4537 struct mlx5e_priv *priv = vpriv;
4538 struct net_device *netdev = priv->netdev;
4539
4540 if (!netif_device_present(netdev))
4541 return;
4542
2c3b5bee 4543 mlx5e_detach_netdev(priv);
26e59d80
MHY		 4544 mlx5e_destroy_mdev_resources(mdev);
4545}
4546
b50d292b
HHZ		 4547static void *mlx5e_add(struct mlx5_core_dev *mdev)
4548{
07c9f1e5
SM		 4549 struct net_device *netdev;
4550 void *rpriv = NULL;
26e59d80 4551 void *priv;
26e59d80 4552 int err;
b50d292b 4553
26e59d80
MHY		 4554 err = mlx5e_check_required_hca_cap(mdev);
4555 if (err)
b50d292b
HHZ		 4556 return NULL;
4557
e80541ec 4558#ifdef CONFIG_MLX5_ESWITCH
a9f7705f 4559 if (MLX5_VPORT_MANAGER(mdev)) {
07c9f1e5 4560 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
1d447a39 4561 if (!rpriv) {
07c9f1e5 4562 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
1d447a39
SM		 4563 return NULL;
4564 }
1d447a39 4565 }
e80541ec 4566#endif
127ea380 4567
1d447a39 4568 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
26e59d80
MHY		 4569 if (!netdev) {
4570 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
07c9f1e5 4571 goto err_free_rpriv;
26e59d80
MHY		 4572 }
4573
4574 priv = netdev_priv(netdev);
4575
4576 err = mlx5e_attach(mdev, priv);
4577 if (err) {
4578 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4579 goto err_destroy_netdev;
4580 }
4581
4582 err = register_netdev(netdev);
4583 if (err) {
4584 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4585 goto err_detach;
b50d292b 4586 }
26e59d80 4587
2a5e7a13
HN		 4588#ifdef CONFIG_MLX5_CORE_EN_DCB
4589 mlx5e_dcbnl_init_app(priv);
4590#endif
26e59d80
MHY		 4591 return priv;
4592
4593err_detach:
4594 mlx5e_detach(mdev, priv);
26e59d80 4595err_destroy_netdev:
2c3b5bee 4596 mlx5e_destroy_netdev(priv);
07c9f1e5 4597err_free_rpriv:
1d447a39 4598 kfree(rpriv);
26e59d80 4599 return NULL;
b50d292b
HHZ		 4600}
4601
b50d292b
HHZ		 4602static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4603{
4604 struct mlx5e_priv *priv = vpriv;
1d447a39 4605 void *ppriv = priv->ppriv;
127ea380 4606
2a5e7a13
HN		 4607#ifdef CONFIG_MLX5_CORE_EN_DCB
4608 mlx5e_dcbnl_delete_app(priv);
4609#endif
5e1e93c7 4610 unregister_netdev(priv->netdev);
26e59d80 4611 mlx5e_detach(mdev, vpriv);
2c3b5bee 4612 mlx5e_destroy_netdev(priv);
1d447a39 4613 kfree(ppriv);
b50d292b
HHZ		 4614}
4615
f62b8bb8
AV		 4616static void *mlx5e_get_netdev(void *vpriv)
4617{
4618 struct mlx5e_priv *priv = vpriv;
4619
4620 return priv->netdev;
4621}
4622
4623static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4624 .add = mlx5e_add,
4625 .remove = mlx5e_remove,
26e59d80
MHY		 4626 .attach = mlx5e_attach,
4627 .detach = mlx5e_detach,
f62b8bb8
AV		 4628 .event = mlx5e_async_event,
4629 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4630 .get_dev = mlx5e_get_netdev,
4631};
4632
4633void mlx5e_init(void)
4634{
2ac9cfe7 4635 mlx5e_ipsec_build_inverse_table();
665bc539 4636 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4637 mlx5_register_interface(&mlx5e_interface);
4638}
4639
4640void mlx5e_cleanup(void)
4641{
4642 mlx5_unregister_interface(&mlx5e_interface);
4643}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git