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f62b8bb8 | 1 | /* |
b3f63c3d | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
e8f887ac AV |
33 | #include <net/tc_act/tc_gact.h> |
34 | #include <net/pkt_cls.h> | |
86d722ad | 35 | #include <linux/mlx5/fs.h> |
b3f63c3d | 36 | #include <net/vxlan.h> |
86994156 | 37 | #include <linux/bpf.h> |
60bbf7ee | 38 | #include <net/page_pool.h> |
1d447a39 | 39 | #include "eswitch.h" |
f62b8bb8 | 40 | #include "en.h" |
e8f887ac | 41 | #include "en_tc.h" |
1d447a39 | 42 | #include "en_rep.h" |
547eede0 | 43 | #include "en_accel/ipsec.h" |
899a59d3 | 44 | #include "en_accel/ipsec_rxtx.h" |
c83294b9 | 45 | #include "en_accel/tls.h" |
899a59d3 | 46 | #include "accel/ipsec.h" |
c83294b9 | 47 | #include "accel/tls.h" |
358aa5ce | 48 | #include "lib/vxlan.h" |
6dbc80ca | 49 | #include "lib/clock.h" |
2c81bfd5 | 50 | #include "en/port.h" |
159d2131 | 51 | #include "en/xdp.h" |
f62b8bb8 AV |
52 | |
53 | struct mlx5e_rq_param { | |
cb3c7fd4 GR |
54 | u32 rqc[MLX5_ST_SZ_DW(rqc)]; |
55 | struct mlx5_wq_param wq; | |
069d1146 | 56 | struct mlx5e_rq_frags_info frags_info; |
f62b8bb8 AV |
57 | }; |
58 | ||
59 | struct mlx5e_sq_param { | |
60 | u32 sqc[MLX5_ST_SZ_DW(sqc)]; | |
61 | struct mlx5_wq_param wq; | |
62 | }; | |
63 | ||
64 | struct mlx5e_cq_param { | |
65 | u32 cqc[MLX5_ST_SZ_DW(cqc)]; | |
66 | struct mlx5_wq_param wq; | |
67 | u16 eq_ix; | |
9908aa29 | 68 | u8 cq_period_mode; |
f62b8bb8 AV |
69 | }; |
70 | ||
71 | struct mlx5e_channel_param { | |
72 | struct mlx5e_rq_param rq; | |
73 | struct mlx5e_sq_param sq; | |
b5503b99 | 74 | struct mlx5e_sq_param xdp_sq; |
d3c9bc27 | 75 | struct mlx5e_sq_param icosq; |
f62b8bb8 AV |
76 | struct mlx5e_cq_param rx_cq; |
77 | struct mlx5e_cq_param tx_cq; | |
d3c9bc27 | 78 | struct mlx5e_cq_param icosq_cq; |
f62b8bb8 AV |
79 | }; |
80 | ||
2ccb0a79 | 81 | bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev) |
2fc4bfb7 | 82 | { |
ea3886ca | 83 | bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && |
2fc4bfb7 SM |
84 | MLX5_CAP_GEN(mdev, umr_ptr_rlky) && |
85 | MLX5_CAP_ETH(mdev, reg_umr_sq); | |
ea3886ca TT |
86 | u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq); |
87 | bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap; | |
88 | ||
89 | if (!striding_rq_umr) | |
90 | return false; | |
91 | if (!inline_umr) { | |
92 | mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n", | |
93 | (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap); | |
94 | return false; | |
95 | } | |
96 | return true; | |
2fc4bfb7 SM |
97 | } |
98 | ||
069d1146 | 99 | static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params) |
73281b78 | 100 | { |
a26a5bdf TT |
101 | u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); |
102 | u16 linear_rq_headroom = params->xdp_prog ? | |
103 | XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM; | |
104 | u32 frag_sz; | |
73281b78 | 105 | |
a26a5bdf | 106 | linear_rq_headroom += NET_IP_ALIGN; |
619a8f2a | 107 | |
a26a5bdf TT |
108 | frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu); |
109 | ||
110 | if (params->xdp_prog && frag_sz < PAGE_SIZE) | |
111 | frag_sz = PAGE_SIZE; | |
112 | ||
113 | return frag_sz; | |
73281b78 TT |
114 | } |
115 | ||
116 | static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params) | |
117 | { | |
069d1146 | 118 | u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params); |
73281b78 TT |
119 | |
120 | return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz); | |
121 | } | |
122 | ||
069d1146 TT |
123 | static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev, |
124 | struct mlx5e_params *params) | |
125 | { | |
126 | u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params); | |
127 | ||
128 | return !params->lro_en && frag_sz <= PAGE_SIZE; | |
129 | } | |
130 | ||
619a8f2a TT |
131 | static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev, |
132 | struct mlx5e_params *params) | |
133 | { | |
069d1146 | 134 | u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params); |
619a8f2a TT |
135 | s8 signed_log_num_strides_param; |
136 | u8 log_num_strides; | |
137 | ||
069d1146 | 138 | if (!mlx5e_rx_is_linear_skb(mdev, params)) |
619a8f2a TT |
139 | return false; |
140 | ||
141 | if (MLX5_CAP_GEN(mdev, ext_stride_num_range)) | |
142 | return true; | |
143 | ||
144 | log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz); | |
145 | signed_log_num_strides_param = | |
146 | (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE; | |
147 | ||
148 | return signed_log_num_strides_param >= 0; | |
149 | } | |
150 | ||
73281b78 TT |
151 | static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params) |
152 | { | |
153 | if (params->log_rq_mtu_frames < | |
154 | mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW) | |
155 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
156 | ||
157 | return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params); | |
158 | } | |
159 | ||
160 | static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev, | |
161 | struct mlx5e_params *params) | |
f1e4fc9b | 162 | { |
619a8f2a | 163 | if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params)) |
069d1146 | 164 | return order_base_2(mlx5e_rx_get_linear_frag_sz(params)); |
619a8f2a | 165 | |
f1e4fc9b TT |
166 | return MLX5E_MPWQE_STRIDE_SZ(mdev, |
167 | MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)); | |
168 | } | |
169 | ||
73281b78 TT |
170 | static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev, |
171 | struct mlx5e_params *params) | |
f1e4fc9b TT |
172 | { |
173 | return MLX5_MPWRQ_LOG_WQE_SZ - | |
174 | mlx5e_mpwqe_get_log_stride_size(mdev, params); | |
175 | } | |
176 | ||
619a8f2a TT |
177 | static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev, |
178 | struct mlx5e_params *params) | |
b0cedc84 TT |
179 | { |
180 | u16 linear_rq_headroom = params->xdp_prog ? | |
181 | XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM; | |
069d1146 | 182 | bool is_linear_skb; |
b0cedc84 TT |
183 | |
184 | linear_rq_headroom += NET_IP_ALIGN; | |
185 | ||
069d1146 TT |
186 | is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ? |
187 | mlx5e_rx_is_linear_skb(mdev, params) : | |
188 | mlx5e_rx_mpwqe_is_linear_skb(mdev, params); | |
b0cedc84 | 189 | |
069d1146 | 190 | return is_linear_skb ? linear_rq_headroom : 0; |
b0cedc84 TT |
191 | } |
192 | ||
696a97cf | 193 | void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, |
2a0f561b | 194 | struct mlx5e_params *params) |
2fc4bfb7 | 195 | { |
6a9764ef | 196 | params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; |
73281b78 TT |
197 | params->log_rq_mtu_frames = is_kdump_kernel() ? |
198 | MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE : | |
199 | MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; | |
2fc4bfb7 | 200 | |
6a9764ef SM |
201 | mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n", |
202 | params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ, | |
619a8f2a TT |
203 | params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ? |
204 | BIT(mlx5e_mpwqe_get_log_rq_size(params)) : | |
73281b78 | 205 | BIT(params->log_rq_mtu_frames), |
f1e4fc9b | 206 | BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)), |
6a9764ef | 207 | MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)); |
2fc4bfb7 SM |
208 | } |
209 | ||
2ccb0a79 TT |
210 | bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev, |
211 | struct mlx5e_params *params) | |
212 | { | |
213 | return mlx5e_check_fragmented_striding_rq_cap(mdev) && | |
22f45398 TT |
214 | !MLX5_IPSEC_DEV(mdev) && |
215 | !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params)); | |
2ccb0a79 | 216 | } |
291f445e | 217 | |
2ccb0a79 | 218 | void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params) |
2fc4bfb7 | 219 | { |
2ccb0a79 TT |
220 | params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) && |
221 | MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ? | |
291f445e | 222 | MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ : |
99cbfa93 | 223 | MLX5_WQ_TYPE_CYCLIC; |
2fc4bfb7 SM |
224 | } |
225 | ||
f62b8bb8 AV |
226 | static void mlx5e_update_carrier(struct mlx5e_priv *priv) |
227 | { | |
228 | struct mlx5_core_dev *mdev = priv->mdev; | |
229 | u8 port_state; | |
230 | ||
231 | port_state = mlx5_query_vport_state(mdev, | |
cc9c82a8 | 232 | MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT, |
e53eef63 | 233 | 0); |
f62b8bb8 | 234 | |
87424ad5 SD |
235 | if (port_state == VPORT_STATE_UP) { |
236 | netdev_info(priv->netdev, "Link up\n"); | |
f62b8bb8 | 237 | netif_carrier_on(priv->netdev); |
87424ad5 SD |
238 | } else { |
239 | netdev_info(priv->netdev, "Link down\n"); | |
f62b8bb8 | 240 | netif_carrier_off(priv->netdev); |
87424ad5 | 241 | } |
f62b8bb8 AV |
242 | } |
243 | ||
244 | static void mlx5e_update_carrier_work(struct work_struct *work) | |
245 | { | |
246 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, | |
247 | update_carrier_work); | |
248 | ||
249 | mutex_lock(&priv->state_lock); | |
250 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
7ca42c80 ES |
251 | if (priv->profile->update_carrier) |
252 | priv->profile->update_carrier(priv); | |
f62b8bb8 AV |
253 | mutex_unlock(&priv->state_lock); |
254 | } | |
255 | ||
19386177 | 256 | void mlx5e_update_stats(struct mlx5e_priv *priv) |
f62b8bb8 | 257 | { |
19386177 | 258 | int i; |
f62b8bb8 | 259 | |
19386177 KH |
260 | for (i = mlx5e_num_stats_grps - 1; i >= 0; i--) |
261 | if (mlx5e_stats_grps[i].update_stats) | |
262 | mlx5e_stats_grps[i].update_stats(priv); | |
f62b8bb8 AV |
263 | } |
264 | ||
3834a5e6 GP |
265 | static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv) |
266 | { | |
19386177 KH |
267 | int i; |
268 | ||
269 | for (i = mlx5e_num_stats_grps - 1; i >= 0; i--) | |
270 | if (mlx5e_stats_grps[i].update_stats_mask & | |
271 | MLX5E_NDO_UPDATE_STATS) | |
272 | mlx5e_stats_grps[i].update_stats(priv); | |
3834a5e6 GP |
273 | } |
274 | ||
303211b4 | 275 | static void mlx5e_update_stats_work(struct work_struct *work) |
f62b8bb8 AV |
276 | { |
277 | struct delayed_work *dwork = to_delayed_work(work); | |
278 | struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv, | |
279 | update_stats_work); | |
ed56c519 | 280 | |
f62b8bb8 | 281 | mutex_lock(&priv->state_lock); |
ed56c519 | 282 | priv->profile->update_stats(priv); |
f62b8bb8 AV |
283 | mutex_unlock(&priv->state_lock); |
284 | } | |
285 | ||
daa21560 TT |
286 | static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, |
287 | enum mlx5_dev_event event, unsigned long param) | |
f62b8bb8 | 288 | { |
daa21560 TT |
289 | struct mlx5e_priv *priv = vpriv; |
290 | ||
e0f46eb9 | 291 | if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state)) |
daa21560 TT |
292 | return; |
293 | ||
f62b8bb8 AV |
294 | switch (event) { |
295 | case MLX5_DEV_EVENT_PORT_UP: | |
296 | case MLX5_DEV_EVENT_PORT_DOWN: | |
7bb29755 | 297 | queue_work(priv->wq, &priv->update_carrier_work); |
f62b8bb8 | 298 | break; |
f62b8bb8 AV |
299 | default: |
300 | break; | |
301 | } | |
302 | } | |
303 | ||
f62b8bb8 AV |
304 | static void mlx5e_enable_async_events(struct mlx5e_priv *priv) |
305 | { | |
e0f46eb9 | 306 | set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state); |
f62b8bb8 AV |
307 | } |
308 | ||
309 | static void mlx5e_disable_async_events(struct mlx5e_priv *priv) | |
310 | { | |
e0f46eb9 | 311 | clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state); |
78249c42 | 312 | synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC)); |
f62b8bb8 AV |
313 | } |
314 | ||
31391048 SM |
315 | static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, |
316 | struct mlx5e_icosq *sq, | |
b8a98a4c | 317 | struct mlx5e_umr_wqe *wqe) |
7e426671 TT |
318 | { |
319 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
320 | struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl; | |
ea3886ca | 321 | u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS); |
7e426671 TT |
322 | |
323 | cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) | | |
324 | ds_cnt); | |
325 | cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; | |
326 | cseg->imm = rq->mkey_be; | |
327 | ||
ea3886ca | 328 | ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE; |
31616255 | 329 | ucseg->xlt_octowords = |
7e426671 | 330 | cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE)); |
7e426671 | 331 | ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); |
7e426671 TT |
332 | } |
333 | ||
422d4c40 TT |
334 | static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq) |
335 | { | |
336 | switch (rq->wq_type) { | |
337 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
338 | return mlx5_wq_ll_get_size(&rq->mpwqe.wq); | |
339 | default: | |
99cbfa93 | 340 | return mlx5_wq_cyc_get_size(&rq->wqe.wq); |
422d4c40 TT |
341 | } |
342 | } | |
343 | ||
344 | static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq) | |
345 | { | |
346 | switch (rq->wq_type) { | |
347 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
348 | return rq->mpwqe.wq.cur_sz; | |
349 | default: | |
350 | return rq->wqe.wq.cur_sz; | |
351 | } | |
352 | } | |
353 | ||
7e426671 TT |
354 | static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, |
355 | struct mlx5e_channel *c) | |
356 | { | |
422d4c40 | 357 | int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq); |
7e426671 | 358 | |
eec4edc9 KC |
359 | rq->mpwqe.info = kvzalloc_node(array_size(wq_sz, |
360 | sizeof(*rq->mpwqe.info)), | |
ca11b798 | 361 | GFP_KERNEL, cpu_to_node(c->cpu)); |
21c59685 | 362 | if (!rq->mpwqe.info) |
ea3886ca | 363 | return -ENOMEM; |
7e426671 | 364 | |
b8a98a4c | 365 | mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe); |
7e426671 TT |
366 | |
367 | return 0; | |
7e426671 TT |
368 | } |
369 | ||
a43b25da | 370 | static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev, |
ec8b9981 TT |
371 | u64 npages, u8 page_shift, |
372 | struct mlx5_core_mkey *umr_mkey) | |
3608ae77 | 373 | { |
3608ae77 TT |
374 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
375 | void *mkc; | |
376 | u32 *in; | |
377 | int err; | |
378 | ||
1b9a07ee | 379 | in = kvzalloc(inlen, GFP_KERNEL); |
3608ae77 TT |
380 | if (!in) |
381 | return -ENOMEM; | |
382 | ||
383 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
384 | ||
3608ae77 TT |
385 | MLX5_SET(mkc, mkc, free, 1); |
386 | MLX5_SET(mkc, mkc, umr_en, 1); | |
387 | MLX5_SET(mkc, mkc, lw, 1); | |
388 | MLX5_SET(mkc, mkc, lr, 1); | |
cdbd0d2b | 389 | MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); |
3608ae77 TT |
390 | |
391 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
392 | MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn); | |
ec8b9981 | 393 | MLX5_SET64(mkc, mkc, len, npages << page_shift); |
3608ae77 TT |
394 | MLX5_SET(mkc, mkc, translations_octword_size, |
395 | MLX5_MTT_OCTW(npages)); | |
ec8b9981 | 396 | MLX5_SET(mkc, mkc, log_page_size, page_shift); |
3608ae77 | 397 | |
ec8b9981 | 398 | err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen); |
3608ae77 TT |
399 | |
400 | kvfree(in); | |
401 | return err; | |
402 | } | |
403 | ||
a43b25da | 404 | static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq) |
ec8b9981 | 405 | { |
422d4c40 | 406 | u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq)); |
ec8b9981 | 407 | |
a43b25da | 408 | return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey); |
ec8b9981 TT |
409 | } |
410 | ||
b8a98a4c TT |
411 | static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix) |
412 | { | |
413 | return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT; | |
414 | } | |
415 | ||
069d1146 TT |
416 | static void mlx5e_init_frags_partition(struct mlx5e_rq *rq) |
417 | { | |
418 | struct mlx5e_wqe_frag_info next_frag, *prev; | |
419 | int i; | |
420 | ||
421 | next_frag.di = &rq->wqe.di[0]; | |
422 | next_frag.offset = 0; | |
423 | prev = NULL; | |
424 | ||
425 | for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) { | |
426 | struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0]; | |
427 | struct mlx5e_wqe_frag_info *frag = | |
428 | &rq->wqe.frags[i << rq->wqe.info.log_num_frags]; | |
429 | int f; | |
430 | ||
431 | for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) { | |
432 | if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) { | |
433 | next_frag.di++; | |
434 | next_frag.offset = 0; | |
435 | if (prev) | |
436 | prev->last_in_page = true; | |
437 | } | |
438 | *frag = next_frag; | |
439 | ||
440 | /* prepare next */ | |
441 | next_frag.offset += frag_info[f].frag_stride; | |
442 | prev = frag; | |
443 | } | |
444 | } | |
445 | ||
446 | if (prev) | |
447 | prev->last_in_page = true; | |
448 | } | |
449 | ||
450 | static int mlx5e_init_di_list(struct mlx5e_rq *rq, | |
451 | struct mlx5e_params *params, | |
452 | int wq_sz, int cpu) | |
453 | { | |
454 | int len = wq_sz << rq->wqe.info.log_num_frags; | |
455 | ||
84ca176b | 456 | rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), |
069d1146 TT |
457 | GFP_KERNEL, cpu_to_node(cpu)); |
458 | if (!rq->wqe.di) | |
459 | return -ENOMEM; | |
460 | ||
461 | mlx5e_init_frags_partition(rq); | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
466 | static void mlx5e_free_di_list(struct mlx5e_rq *rq) | |
467 | { | |
468 | kvfree(rq->wqe.di); | |
469 | } | |
470 | ||
3b77235b | 471 | static int mlx5e_alloc_rq(struct mlx5e_channel *c, |
6a9764ef SM |
472 | struct mlx5e_params *params, |
473 | struct mlx5e_rq_param *rqp, | |
3b77235b | 474 | struct mlx5e_rq *rq) |
f62b8bb8 | 475 | { |
60bbf7ee | 476 | struct page_pool_params pp_params = { 0 }; |
a43b25da | 477 | struct mlx5_core_dev *mdev = c->mdev; |
6a9764ef | 478 | void *rqc = rqp->rqc; |
f62b8bb8 | 479 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); |
069d1146 | 480 | u32 pool_size; |
f62b8bb8 AV |
481 | int wq_sz; |
482 | int err; | |
483 | int i; | |
484 | ||
231243c8 | 485 | rqp->wq.db_numa_node = cpu_to_node(c->cpu); |
311c7c71 | 486 | |
6a9764ef | 487 | rq->wq_type = params->rq_wq_type; |
7e426671 TT |
488 | rq->pdev = c->pdev; |
489 | rq->netdev = c->netdev; | |
a43b25da | 490 | rq->tstamp = c->tstamp; |
7c39afb3 | 491 | rq->clock = &mdev->clock; |
7e426671 TT |
492 | rq->channel = c; |
493 | rq->ix = c->ix; | |
a43b25da | 494 | rq->mdev = mdev; |
05909bab | 495 | rq->stats = &c->priv->channel_stats[c->ix].rq; |
97bc402d | 496 | |
6a9764ef | 497 | rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL; |
97bc402d DB |
498 | if (IS_ERR(rq->xdp_prog)) { |
499 | err = PTR_ERR(rq->xdp_prog); | |
500 | rq->xdp_prog = NULL; | |
501 | goto err_rq_wq_destroy; | |
502 | } | |
7e426671 | 503 | |
e213f5b6 WY |
504 | err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix); |
505 | if (err < 0) | |
0ddf5432 JDB |
506 | goto err_rq_wq_destroy; |
507 | ||
bce2b2bf | 508 | rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; |
619a8f2a | 509 | rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params); |
60bbf7ee | 510 | pool_size = 1 << params->log_rq_mtu_frames; |
b5503b99 | 511 | |
6a9764ef | 512 | switch (rq->wq_type) { |
461017cb | 513 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: |
422d4c40 TT |
514 | err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq, |
515 | &rq->wq_ctrl); | |
516 | if (err) | |
517 | return err; | |
518 | ||
519 | rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR]; | |
520 | ||
521 | wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq); | |
60bbf7ee JDB |
522 | |
523 | pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params); | |
422d4c40 | 524 | |
7cc6d77b | 525 | rq->post_wqes = mlx5e_post_rx_mpwqes; |
6cd392a0 | 526 | rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe; |
461017cb | 527 | |
20fd0c19 | 528 | rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe; |
899a59d3 IT |
529 | #ifdef CONFIG_MLX5_EN_IPSEC |
530 | if (MLX5_IPSEC_DEV(mdev)) { | |
531 | err = -EINVAL; | |
532 | netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n"); | |
533 | goto err_rq_wq_destroy; | |
534 | } | |
535 | #endif | |
20fd0c19 SM |
536 | if (!rq->handle_rx_cqe) { |
537 | err = -EINVAL; | |
538 | netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err); | |
539 | goto err_rq_wq_destroy; | |
540 | } | |
541 | ||
619a8f2a TT |
542 | rq->mpwqe.skb_from_cqe_mpwrq = |
543 | mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ? | |
544 | mlx5e_skb_from_cqe_mpwrq_linear : | |
545 | mlx5e_skb_from_cqe_mpwrq_nonlinear; | |
f1e4fc9b TT |
546 | rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params); |
547 | rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params)); | |
1bfecfca | 548 | |
a43b25da | 549 | err = mlx5e_create_rq_umr_mkey(mdev, rq); |
7e426671 TT |
550 | if (err) |
551 | goto err_rq_wq_destroy; | |
ec8b9981 TT |
552 | rq->mkey_be = cpu_to_be32(rq->umr_mkey.key); |
553 | ||
554 | err = mlx5e_rq_alloc_mpwqe_info(rq, c); | |
555 | if (err) | |
069d1146 | 556 | goto err_free; |
461017cb | 557 | break; |
99cbfa93 TT |
558 | default: /* MLX5_WQ_TYPE_CYCLIC */ |
559 | err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq, | |
560 | &rq->wq_ctrl); | |
422d4c40 TT |
561 | if (err) |
562 | return err; | |
563 | ||
564 | rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR]; | |
565 | ||
99cbfa93 | 566 | wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq); |
422d4c40 | 567 | |
069d1146 TT |
568 | rq->wqe.info = rqp->frags_info; |
569 | rq->wqe.frags = | |
84ca176b KC |
570 | kvzalloc_node(array_size(sizeof(*rq->wqe.frags), |
571 | (wq_sz << rq->wqe.info.log_num_frags)), | |
069d1146 | 572 | GFP_KERNEL, cpu_to_node(c->cpu)); |
47a6ca3f WY |
573 | if (!rq->wqe.frags) { |
574 | err = -ENOMEM; | |
069d1146 | 575 | goto err_free; |
47a6ca3f | 576 | } |
069d1146 TT |
577 | |
578 | err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu); | |
579 | if (err) | |
580 | goto err_free; | |
7cc6d77b | 581 | rq->post_wqes = mlx5e_post_rx_wqes; |
6cd392a0 | 582 | rq->dealloc_wqe = mlx5e_dealloc_rx_wqe; |
461017cb | 583 | |
899a59d3 IT |
584 | #ifdef CONFIG_MLX5_EN_IPSEC |
585 | if (c->priv->ipsec) | |
586 | rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe; | |
587 | else | |
588 | #endif | |
589 | rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe; | |
20fd0c19 | 590 | if (!rq->handle_rx_cqe) { |
20fd0c19 SM |
591 | err = -EINVAL; |
592 | netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err); | |
069d1146 | 593 | goto err_free; |
20fd0c19 SM |
594 | } |
595 | ||
069d1146 TT |
596 | rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ? |
597 | mlx5e_skb_from_cqe_linear : | |
598 | mlx5e_skb_from_cqe_nonlinear; | |
7e426671 | 599 | rq->mkey_be = c->mkey_be; |
461017cb | 600 | } |
f62b8bb8 | 601 | |
60bbf7ee | 602 | /* Create a page_pool and register it with rxq */ |
069d1146 | 603 | pp_params.order = 0; |
60bbf7ee JDB |
604 | pp_params.flags = 0; /* No-internal DMA mapping in page_pool */ |
605 | pp_params.pool_size = pool_size; | |
606 | pp_params.nid = cpu_to_node(c->cpu); | |
607 | pp_params.dev = c->pdev; | |
608 | pp_params.dma_dir = rq->buff.map_dir; | |
609 | ||
610 | /* page_pool can be used even when there is no rq->xdp_prog, | |
611 | * given page_pool does not handle DMA mapping there is no | |
612 | * required state to clear. And page_pool gracefully handle | |
613 | * elevated refcnt. | |
614 | */ | |
615 | rq->page_pool = page_pool_create(&pp_params); | |
616 | if (IS_ERR(rq->page_pool)) { | |
60bbf7ee JDB |
617 | err = PTR_ERR(rq->page_pool); |
618 | rq->page_pool = NULL; | |
069d1146 | 619 | goto err_free; |
84f5e3fb | 620 | } |
60bbf7ee JDB |
621 | err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq, |
622 | MEM_TYPE_PAGE_POOL, rq->page_pool); | |
623 | if (err) | |
069d1146 | 624 | goto err_free; |
84f5e3fb | 625 | |
f62b8bb8 | 626 | for (i = 0; i < wq_sz; i++) { |
4c2af5cc | 627 | if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { |
99cbfa93 | 628 | struct mlx5e_rx_wqe_ll *wqe = |
422d4c40 | 629 | mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i); |
069d1146 TT |
630 | u32 byte_count = |
631 | rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz; | |
b8a98a4c | 632 | u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i); |
4c2af5cc | 633 | |
99cbfa93 TT |
634 | wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom); |
635 | wqe->data[0].byte_count = cpu_to_be32(byte_count); | |
636 | wqe->data[0].lkey = rq->mkey_be; | |
422d4c40 | 637 | } else { |
99cbfa93 TT |
638 | struct mlx5e_rx_wqe_cyc *wqe = |
639 | mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i); | |
069d1146 TT |
640 | int f; |
641 | ||
642 | for (f = 0; f < rq->wqe.info.num_frags; f++) { | |
643 | u32 frag_size = rq->wqe.info.arr[f].frag_size | | |
644 | MLX5_HW_START_PADDING; | |
645 | ||
646 | wqe->data[f].byte_count = cpu_to_be32(frag_size); | |
647 | wqe->data[f].lkey = rq->mkey_be; | |
648 | } | |
649 | /* check if num_frags is not a pow of two */ | |
650 | if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) { | |
651 | wqe->data[f].byte_count = 0; | |
652 | wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY); | |
653 | wqe->data[f].addr = 0; | |
654 | } | |
422d4c40 | 655 | } |
f62b8bb8 AV |
656 | } |
657 | ||
9a317425 AG |
658 | INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work); |
659 | ||
660 | switch (params->rx_cq_moderation.cq_period_mode) { | |
661 | case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: | |
662 | rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; | |
663 | break; | |
664 | case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: | |
665 | default: | |
666 | rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; | |
667 | } | |
668 | ||
4415a031 TT |
669 | rq->page_cache.head = 0; |
670 | rq->page_cache.tail = 0; | |
671 | ||
f62b8bb8 AV |
672 | return 0; |
673 | ||
069d1146 TT |
674 | err_free: |
675 | switch (rq->wq_type) { | |
676 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
ca11b798 | 677 | kvfree(rq->mpwqe.info); |
069d1146 TT |
678 | mlx5_core_destroy_mkey(mdev, &rq->umr_mkey); |
679 | break; | |
680 | default: /* MLX5_WQ_TYPE_CYCLIC */ | |
681 | kvfree(rq->wqe.frags); | |
682 | mlx5e_free_di_list(rq); | |
683 | } | |
ec8b9981 | 684 | |
f62b8bb8 | 685 | err_rq_wq_destroy: |
97bc402d DB |
686 | if (rq->xdp_prog) |
687 | bpf_prog_put(rq->xdp_prog); | |
0ddf5432 | 688 | xdp_rxq_info_unreg(&rq->xdp_rxq); |
60bbf7ee JDB |
689 | if (rq->page_pool) |
690 | page_pool_destroy(rq->page_pool); | |
f62b8bb8 AV |
691 | mlx5_wq_destroy(&rq->wq_ctrl); |
692 | ||
693 | return err; | |
694 | } | |
695 | ||
3b77235b | 696 | static void mlx5e_free_rq(struct mlx5e_rq *rq) |
f62b8bb8 | 697 | { |
4415a031 TT |
698 | int i; |
699 | ||
86994156 RS |
700 | if (rq->xdp_prog) |
701 | bpf_prog_put(rq->xdp_prog); | |
702 | ||
0ddf5432 | 703 | xdp_rxq_info_unreg(&rq->xdp_rxq); |
60bbf7ee JDB |
704 | if (rq->page_pool) |
705 | page_pool_destroy(rq->page_pool); | |
0ddf5432 | 706 | |
461017cb TT |
707 | switch (rq->wq_type) { |
708 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
ca11b798 | 709 | kvfree(rq->mpwqe.info); |
a43b25da | 710 | mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey); |
461017cb | 711 | break; |
99cbfa93 | 712 | default: /* MLX5_WQ_TYPE_CYCLIC */ |
069d1146 TT |
713 | kvfree(rq->wqe.frags); |
714 | mlx5e_free_di_list(rq); | |
461017cb TT |
715 | } |
716 | ||
4415a031 TT |
717 | for (i = rq->page_cache.head; i != rq->page_cache.tail; |
718 | i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) { | |
719 | struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i]; | |
720 | ||
721 | mlx5e_page_release(rq, dma_info, false); | |
722 | } | |
f62b8bb8 AV |
723 | mlx5_wq_destroy(&rq->wq_ctrl); |
724 | } | |
725 | ||
6a9764ef SM |
726 | static int mlx5e_create_rq(struct mlx5e_rq *rq, |
727 | struct mlx5e_rq_param *param) | |
f62b8bb8 | 728 | { |
a43b25da | 729 | struct mlx5_core_dev *mdev = rq->mdev; |
f62b8bb8 AV |
730 | |
731 | void *in; | |
732 | void *rqc; | |
733 | void *wq; | |
734 | int inlen; | |
735 | int err; | |
736 | ||
737 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + | |
738 | sizeof(u64) * rq->wq_ctrl.buf.npages; | |
1b9a07ee | 739 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
740 | if (!in) |
741 | return -ENOMEM; | |
742 | ||
743 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); | |
744 | wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
745 | ||
746 | memcpy(rqc, param->rqc, sizeof(param->rqc)); | |
747 | ||
97de9f31 | 748 | MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn); |
f62b8bb8 | 749 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); |
f62b8bb8 | 750 | MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - |
68cdf5d6 | 751 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
752 | MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); |
753 | ||
3a2f7033 TT |
754 | mlx5_fill_page_frag_array(&rq->wq_ctrl.buf, |
755 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
f62b8bb8 | 756 | |
7db22ffb | 757 | err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); |
f62b8bb8 AV |
758 | |
759 | kvfree(in); | |
760 | ||
761 | return err; | |
762 | } | |
763 | ||
36350114 GP |
764 | static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, |
765 | int next_state) | |
f62b8bb8 | 766 | { |
7cbaf9a3 | 767 | struct mlx5_core_dev *mdev = rq->mdev; |
f62b8bb8 AV |
768 | |
769 | void *in; | |
770 | void *rqc; | |
771 | int inlen; | |
772 | int err; | |
773 | ||
774 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 775 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
776 | if (!in) |
777 | return -ENOMEM; | |
778 | ||
779 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
780 | ||
781 | MLX5_SET(modify_rq_in, in, rq_state, curr_state); | |
782 | MLX5_SET(rqc, rqc, state, next_state); | |
783 | ||
7db22ffb | 784 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); |
f62b8bb8 AV |
785 | |
786 | kvfree(in); | |
787 | ||
788 | return err; | |
789 | } | |
790 | ||
102722fc GE |
791 | static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable) |
792 | { | |
793 | struct mlx5e_channel *c = rq->channel; | |
794 | struct mlx5e_priv *priv = c->priv; | |
795 | struct mlx5_core_dev *mdev = priv->mdev; | |
796 | ||
797 | void *in; | |
798 | void *rqc; | |
799 | int inlen; | |
800 | int err; | |
801 | ||
802 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 803 | in = kvzalloc(inlen, GFP_KERNEL); |
102722fc GE |
804 | if (!in) |
805 | return -ENOMEM; | |
806 | ||
807 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
808 | ||
809 | MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); | |
810 | MLX5_SET64(modify_rq_in, in, modify_bitmask, | |
811 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS); | |
812 | MLX5_SET(rqc, rqc, scatter_fcs, enable); | |
813 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); | |
814 | ||
815 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); | |
816 | ||
817 | kvfree(in); | |
818 | ||
819 | return err; | |
820 | } | |
821 | ||
36350114 GP |
822 | static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd) |
823 | { | |
824 | struct mlx5e_channel *c = rq->channel; | |
a43b25da | 825 | struct mlx5_core_dev *mdev = c->mdev; |
36350114 GP |
826 | void *in; |
827 | void *rqc; | |
828 | int inlen; | |
829 | int err; | |
830 | ||
831 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 832 | in = kvzalloc(inlen, GFP_KERNEL); |
36350114 GP |
833 | if (!in) |
834 | return -ENOMEM; | |
835 | ||
836 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
837 | ||
838 | MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); | |
83b502a1 AV |
839 | MLX5_SET64(modify_rq_in, in, modify_bitmask, |
840 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); | |
36350114 GP |
841 | MLX5_SET(rqc, rqc, vsd, vsd); |
842 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); | |
843 | ||
844 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); | |
845 | ||
846 | kvfree(in); | |
847 | ||
848 | return err; | |
849 | } | |
850 | ||
3b77235b | 851 | static void mlx5e_destroy_rq(struct mlx5e_rq *rq) |
f62b8bb8 | 852 | { |
a43b25da | 853 | mlx5_core_destroy_rq(rq->mdev, rq->rqn); |
f62b8bb8 AV |
854 | } |
855 | ||
1e7477ae | 856 | static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time) |
f62b8bb8 | 857 | { |
1e7477ae | 858 | unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time); |
f62b8bb8 | 859 | struct mlx5e_channel *c = rq->channel; |
a43b25da | 860 | |
422d4c40 | 861 | u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq)); |
f62b8bb8 | 862 | |
1e7477ae | 863 | do { |
422d4c40 | 864 | if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes) |
f62b8bb8 AV |
865 | return 0; |
866 | ||
867 | msleep(20); | |
1e7477ae EBE |
868 | } while (time_before(jiffies, exp_time)); |
869 | ||
870 | netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n", | |
422d4c40 | 871 | c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes); |
f62b8bb8 AV |
872 | |
873 | return -ETIMEDOUT; | |
874 | } | |
875 | ||
f2fde18c SM |
876 | static void mlx5e_free_rx_descs(struct mlx5e_rq *rq) |
877 | { | |
f2fde18c SM |
878 | __be16 wqe_ix_be; |
879 | u16 wqe_ix; | |
880 | ||
422d4c40 TT |
881 | if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { |
882 | struct mlx5_wq_ll *wq = &rq->mpwqe.wq; | |
883 | ||
99cbfa93 | 884 | /* UMR WQE (if in progress) is always at wq->head */ |
422d4c40 | 885 | if (rq->mpwqe.umr_in_progress) |
afab995e | 886 | rq->dealloc_wqe(rq, wq->head); |
422d4c40 TT |
887 | |
888 | while (!mlx5_wq_ll_is_empty(wq)) { | |
99cbfa93 | 889 | struct mlx5e_rx_wqe_ll *wqe; |
422d4c40 TT |
890 | |
891 | wqe_ix_be = *wq->tail_next; | |
892 | wqe_ix = be16_to_cpu(wqe_ix_be); | |
893 | wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix); | |
894 | rq->dealloc_wqe(rq, wqe_ix); | |
895 | mlx5_wq_ll_pop(wq, wqe_ix_be, | |
896 | &wqe->next.next_wqe_index); | |
897 | } | |
898 | } else { | |
99cbfa93 | 899 | struct mlx5_wq_cyc *wq = &rq->wqe.wq; |
422d4c40 | 900 | |
99cbfa93 TT |
901 | while (!mlx5_wq_cyc_is_empty(wq)) { |
902 | wqe_ix = mlx5_wq_cyc_get_tail(wq); | |
422d4c40 | 903 | rq->dealloc_wqe(rq, wqe_ix); |
99cbfa93 | 904 | mlx5_wq_cyc_pop(wq); |
422d4c40 | 905 | } |
accd5883 | 906 | } |
069d1146 | 907 | |
f2fde18c SM |
908 | } |
909 | ||
f62b8bb8 | 910 | static int mlx5e_open_rq(struct mlx5e_channel *c, |
6a9764ef | 911 | struct mlx5e_params *params, |
f62b8bb8 AV |
912 | struct mlx5e_rq_param *param, |
913 | struct mlx5e_rq *rq) | |
914 | { | |
915 | int err; | |
916 | ||
6a9764ef | 917 | err = mlx5e_alloc_rq(c, params, param, rq); |
f62b8bb8 AV |
918 | if (err) |
919 | return err; | |
920 | ||
3b77235b | 921 | err = mlx5e_create_rq(rq, param); |
f62b8bb8 | 922 | if (err) |
3b77235b | 923 | goto err_free_rq; |
f62b8bb8 | 924 | |
36350114 | 925 | err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); |
f62b8bb8 | 926 | if (err) |
3b77235b | 927 | goto err_destroy_rq; |
f62b8bb8 | 928 | |
9a317425 | 929 | if (params->rx_dim_enabled) |
af5a6c93 | 930 | __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state); |
cb3c7fd4 | 931 | |
b856df28 OG |
932 | if (params->pflags & MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) |
933 | __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state); | |
934 | ||
f62b8bb8 AV |
935 | return 0; |
936 | ||
f62b8bb8 AV |
937 | err_destroy_rq: |
938 | mlx5e_destroy_rq(rq); | |
3b77235b SM |
939 | err_free_rq: |
940 | mlx5e_free_rq(rq); | |
f62b8bb8 AV |
941 | |
942 | return err; | |
943 | } | |
944 | ||
acc6c595 SM |
945 | static void mlx5e_activate_rq(struct mlx5e_rq *rq) |
946 | { | |
947 | struct mlx5e_icosq *sq = &rq->channel->icosq; | |
ddf385e3 | 948 | struct mlx5_wq_cyc *wq = &sq->wq; |
acc6c595 SM |
949 | struct mlx5e_tx_wqe *nopwqe; |
950 | ||
ddf385e3 TT |
951 | u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); |
952 | ||
acc6c595 SM |
953 | set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); |
954 | sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; | |
ddf385e3 TT |
955 | nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc); |
956 | mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl); | |
acc6c595 SM |
957 | } |
958 | ||
959 | static void mlx5e_deactivate_rq(struct mlx5e_rq *rq) | |
f62b8bb8 | 960 | { |
c0f1147d | 961 | clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); |
f62b8bb8 | 962 | napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */ |
acc6c595 | 963 | } |
cb3c7fd4 | 964 | |
acc6c595 SM |
965 | static void mlx5e_close_rq(struct mlx5e_rq *rq) |
966 | { | |
9a317425 | 967 | cancel_work_sync(&rq->dim.work); |
f62b8bb8 | 968 | mlx5e_destroy_rq(rq); |
3b77235b SM |
969 | mlx5e_free_rx_descs(rq); |
970 | mlx5e_free_rq(rq); | |
f62b8bb8 AV |
971 | } |
972 | ||
31391048 | 973 | static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq) |
b5503b99 | 974 | { |
c94e4f11 | 975 | kvfree(sq->db.xdpi); |
b5503b99 SM |
976 | } |
977 | ||
31391048 | 978 | static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa) |
b5503b99 SM |
979 | { |
980 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
981 | ||
c94e4f11 TT |
982 | sq->db.xdpi = kvzalloc_node(array_size(wq_sz, sizeof(*sq->db.xdpi)), |
983 | GFP_KERNEL, numa); | |
984 | if (!sq->db.xdpi) { | |
31391048 | 985 | mlx5e_free_xdpsq_db(sq); |
b5503b99 SM |
986 | return -ENOMEM; |
987 | } | |
988 | ||
989 | return 0; | |
990 | } | |
991 | ||
31391048 | 992 | static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c, |
6a9764ef | 993 | struct mlx5e_params *params, |
31391048 | 994 | struct mlx5e_sq_param *param, |
58b99ee3 TT |
995 | struct mlx5e_xdpsq *sq, |
996 | bool is_redirect) | |
31391048 SM |
997 | { |
998 | void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); | |
a43b25da | 999 | struct mlx5_core_dev *mdev = c->mdev; |
ddf385e3 | 1000 | struct mlx5_wq_cyc *wq = &sq->wq; |
31391048 SM |
1001 | int err; |
1002 | ||
1003 | sq->pdev = c->pdev; | |
1004 | sq->mkey_be = c->mkey_be; | |
1005 | sq->channel = c; | |
1006 | sq->uar_map = mdev->mlx5e_res.bfreg.map; | |
6a9764ef | 1007 | sq->min_inline_mode = params->tx_min_inline_mode; |
c94e4f11 | 1008 | sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); |
58b99ee3 TT |
1009 | sq->stats = is_redirect ? |
1010 | &c->priv->channel_stats[c->ix].xdpsq : | |
1011 | &c->priv->channel_stats[c->ix].rq_xdpsq; | |
31391048 | 1012 | |
231243c8 | 1013 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
ddf385e3 | 1014 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); |
31391048 SM |
1015 | if (err) |
1016 | return err; | |
ddf385e3 | 1017 | wq->db = &wq->db[MLX5_SND_DBR]; |
31391048 | 1018 | |
231243c8 | 1019 | err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu)); |
31391048 SM |
1020 | if (err) |
1021 | goto err_sq_wq_destroy; | |
1022 | ||
1023 | return 0; | |
1024 | ||
1025 | err_sq_wq_destroy: | |
1026 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1027 | ||
1028 | return err; | |
1029 | } | |
1030 | ||
1031 | static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq) | |
1032 | { | |
1033 | mlx5e_free_xdpsq_db(sq); | |
1034 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1035 | } | |
1036 | ||
1037 | static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq) | |
f62b8bb8 | 1038 | { |
ca11b798 | 1039 | kvfree(sq->db.ico_wqe); |
f62b8bb8 AV |
1040 | } |
1041 | ||
31391048 | 1042 | static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa) |
f10b7cc7 SM |
1043 | { |
1044 | u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
1045 | ||
eec4edc9 KC |
1046 | sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz, |
1047 | sizeof(*sq->db.ico_wqe)), | |
ca11b798 | 1048 | GFP_KERNEL, numa); |
f10b7cc7 SM |
1049 | if (!sq->db.ico_wqe) |
1050 | return -ENOMEM; | |
1051 | ||
1052 | return 0; | |
1053 | } | |
1054 | ||
31391048 | 1055 | static int mlx5e_alloc_icosq(struct mlx5e_channel *c, |
31391048 SM |
1056 | struct mlx5e_sq_param *param, |
1057 | struct mlx5e_icosq *sq) | |
f10b7cc7 | 1058 | { |
31391048 | 1059 | void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); |
a43b25da | 1060 | struct mlx5_core_dev *mdev = c->mdev; |
ddf385e3 | 1061 | struct mlx5_wq_cyc *wq = &sq->wq; |
31391048 | 1062 | int err; |
f10b7cc7 | 1063 | |
31391048 SM |
1064 | sq->channel = c; |
1065 | sq->uar_map = mdev->mlx5e_res.bfreg.map; | |
f62b8bb8 | 1066 | |
231243c8 | 1067 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
ddf385e3 | 1068 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); |
31391048 SM |
1069 | if (err) |
1070 | return err; | |
ddf385e3 | 1071 | wq->db = &wq->db[MLX5_SND_DBR]; |
f62b8bb8 | 1072 | |
231243c8 | 1073 | err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu)); |
31391048 SM |
1074 | if (err) |
1075 | goto err_sq_wq_destroy; | |
1076 | ||
f62b8bb8 | 1077 | return 0; |
31391048 SM |
1078 | |
1079 | err_sq_wq_destroy: | |
1080 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1081 | ||
1082 | return err; | |
f62b8bb8 AV |
1083 | } |
1084 | ||
31391048 | 1085 | static void mlx5e_free_icosq(struct mlx5e_icosq *sq) |
f10b7cc7 | 1086 | { |
31391048 SM |
1087 | mlx5e_free_icosq_db(sq); |
1088 | mlx5_wq_destroy(&sq->wq_ctrl); | |
f10b7cc7 SM |
1089 | } |
1090 | ||
31391048 | 1091 | static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq) |
f10b7cc7 | 1092 | { |
ca11b798 TT |
1093 | kvfree(sq->db.wqe_info); |
1094 | kvfree(sq->db.dma_fifo); | |
f10b7cc7 SM |
1095 | } |
1096 | ||
31391048 | 1097 | static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa) |
b5503b99 | 1098 | { |
31391048 SM |
1099 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); |
1100 | int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS; | |
1101 | ||
eec4edc9 KC |
1102 | sq->db.dma_fifo = kvzalloc_node(array_size(df_sz, |
1103 | sizeof(*sq->db.dma_fifo)), | |
ca11b798 | 1104 | GFP_KERNEL, numa); |
eec4edc9 KC |
1105 | sq->db.wqe_info = kvzalloc_node(array_size(wq_sz, |
1106 | sizeof(*sq->db.wqe_info)), | |
ca11b798 | 1107 | GFP_KERNEL, numa); |
77bdf895 | 1108 | if (!sq->db.dma_fifo || !sq->db.wqe_info) { |
31391048 SM |
1109 | mlx5e_free_txqsq_db(sq); |
1110 | return -ENOMEM; | |
b5503b99 | 1111 | } |
31391048 SM |
1112 | |
1113 | sq->dma_fifo_mask = df_sz - 1; | |
1114 | ||
1115 | return 0; | |
b5503b99 SM |
1116 | } |
1117 | ||
db75373c | 1118 | static void mlx5e_sq_recover(struct work_struct *work); |
31391048 | 1119 | static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, |
acc6c595 | 1120 | int txq_ix, |
6a9764ef | 1121 | struct mlx5e_params *params, |
31391048 | 1122 | struct mlx5e_sq_param *param, |
05909bab EBE |
1123 | struct mlx5e_txqsq *sq, |
1124 | int tc) | |
f62b8bb8 | 1125 | { |
31391048 | 1126 | void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); |
a43b25da | 1127 | struct mlx5_core_dev *mdev = c->mdev; |
ddf385e3 | 1128 | struct mlx5_wq_cyc *wq = &sq->wq; |
f62b8bb8 AV |
1129 | int err; |
1130 | ||
f10b7cc7 | 1131 | sq->pdev = c->pdev; |
a43b25da | 1132 | sq->tstamp = c->tstamp; |
7c39afb3 | 1133 | sq->clock = &mdev->clock; |
f10b7cc7 SM |
1134 | sq->mkey_be = c->mkey_be; |
1135 | sq->channel = c; | |
acc6c595 | 1136 | sq->txq_ix = txq_ix; |
aff26157 | 1137 | sq->uar_map = mdev->mlx5e_res.bfreg.map; |
6a9764ef | 1138 | sq->min_inline_mode = params->tx_min_inline_mode; |
05909bab | 1139 | sq->stats = &c->priv->channel_stats[c->ix].sq[tc]; |
db75373c | 1140 | INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover); |
2ac9cfe7 IT |
1141 | if (MLX5_IPSEC_DEV(c->priv->mdev)) |
1142 | set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state); | |
bf239741 IL |
1143 | if (mlx5_accel_is_tls_device(c->priv->mdev)) |
1144 | set_bit(MLX5E_SQ_STATE_TLS, &sq->state); | |
f10b7cc7 | 1145 | |
231243c8 | 1146 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
ddf385e3 | 1147 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); |
f62b8bb8 | 1148 | if (err) |
aff26157 | 1149 | return err; |
ddf385e3 | 1150 | wq->db = &wq->db[MLX5_SND_DBR]; |
f62b8bb8 | 1151 | |
231243c8 | 1152 | err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu)); |
7ec0bb22 | 1153 | if (err) |
f62b8bb8 AV |
1154 | goto err_sq_wq_destroy; |
1155 | ||
cbce4f44 TG |
1156 | INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work); |
1157 | sq->dim.mode = params->tx_cq_moderation.cq_period_mode; | |
1158 | ||
f62b8bb8 AV |
1159 | return 0; |
1160 | ||
1161 | err_sq_wq_destroy: | |
1162 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1163 | ||
f62b8bb8 AV |
1164 | return err; |
1165 | } | |
1166 | ||
31391048 | 1167 | static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq) |
f62b8bb8 | 1168 | { |
31391048 | 1169 | mlx5e_free_txqsq_db(sq); |
f62b8bb8 | 1170 | mlx5_wq_destroy(&sq->wq_ctrl); |
f62b8bb8 AV |
1171 | } |
1172 | ||
33ad9711 SM |
1173 | struct mlx5e_create_sq_param { |
1174 | struct mlx5_wq_ctrl *wq_ctrl; | |
1175 | u32 cqn; | |
1176 | u32 tisn; | |
1177 | u8 tis_lst_sz; | |
1178 | u8 min_inline_mode; | |
1179 | }; | |
1180 | ||
a43b25da | 1181 | static int mlx5e_create_sq(struct mlx5_core_dev *mdev, |
33ad9711 SM |
1182 | struct mlx5e_sq_param *param, |
1183 | struct mlx5e_create_sq_param *csp, | |
1184 | u32 *sqn) | |
f62b8bb8 | 1185 | { |
f62b8bb8 AV |
1186 | void *in; |
1187 | void *sqc; | |
1188 | void *wq; | |
1189 | int inlen; | |
1190 | int err; | |
1191 | ||
1192 | inlen = MLX5_ST_SZ_BYTES(create_sq_in) + | |
33ad9711 | 1193 | sizeof(u64) * csp->wq_ctrl->buf.npages; |
1b9a07ee | 1194 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
1195 | if (!in) |
1196 | return -ENOMEM; | |
1197 | ||
1198 | sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); | |
1199 | wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1200 | ||
1201 | memcpy(sqc, param->sqc, sizeof(param->sqc)); | |
33ad9711 SM |
1202 | MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz); |
1203 | MLX5_SET(sqc, sqc, tis_num_0, csp->tisn); | |
1204 | MLX5_SET(sqc, sqc, cqn, csp->cqn); | |
a6f402e4 SM |
1205 | |
1206 | if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) | |
33ad9711 | 1207 | MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode); |
a6f402e4 | 1208 | |
33ad9711 | 1209 | MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); |
db75373c | 1210 | MLX5_SET(sqc, sqc, flush_in_error_en, 1); |
f62b8bb8 AV |
1211 | |
1212 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
a43b25da | 1213 | MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index); |
33ad9711 | 1214 | MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift - |
68cdf5d6 | 1215 | MLX5_ADAPTER_PAGE_SHIFT); |
33ad9711 | 1216 | MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma); |
f62b8bb8 | 1217 | |
3a2f7033 TT |
1218 | mlx5_fill_page_frag_array(&csp->wq_ctrl->buf, |
1219 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
f62b8bb8 | 1220 | |
33ad9711 | 1221 | err = mlx5_core_create_sq(mdev, in, inlen, sqn); |
f62b8bb8 AV |
1222 | |
1223 | kvfree(in); | |
1224 | ||
1225 | return err; | |
1226 | } | |
1227 | ||
33ad9711 SM |
1228 | struct mlx5e_modify_sq_param { |
1229 | int curr_state; | |
1230 | int next_state; | |
1231 | bool rl_update; | |
1232 | int rl_index; | |
1233 | }; | |
1234 | ||
a43b25da | 1235 | static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, |
33ad9711 | 1236 | struct mlx5e_modify_sq_param *p) |
f62b8bb8 | 1237 | { |
f62b8bb8 AV |
1238 | void *in; |
1239 | void *sqc; | |
1240 | int inlen; | |
1241 | int err; | |
1242 | ||
1243 | inlen = MLX5_ST_SZ_BYTES(modify_sq_in); | |
1b9a07ee | 1244 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
1245 | if (!in) |
1246 | return -ENOMEM; | |
1247 | ||
1248 | sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); | |
1249 | ||
33ad9711 SM |
1250 | MLX5_SET(modify_sq_in, in, sq_state, p->curr_state); |
1251 | MLX5_SET(sqc, sqc, state, p->next_state); | |
1252 | if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) { | |
507f0c81 | 1253 | MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); |
33ad9711 | 1254 | MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index); |
507f0c81 | 1255 | } |
f62b8bb8 | 1256 | |
33ad9711 | 1257 | err = mlx5_core_modify_sq(mdev, sqn, in, inlen); |
f62b8bb8 AV |
1258 | |
1259 | kvfree(in); | |
1260 | ||
1261 | return err; | |
1262 | } | |
1263 | ||
a43b25da | 1264 | static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn) |
33ad9711 | 1265 | { |
a43b25da | 1266 | mlx5_core_destroy_sq(mdev, sqn); |
f62b8bb8 AV |
1267 | } |
1268 | ||
a43b25da | 1269 | static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, |
31391048 SM |
1270 | struct mlx5e_sq_param *param, |
1271 | struct mlx5e_create_sq_param *csp, | |
1272 | u32 *sqn) | |
f62b8bb8 | 1273 | { |
33ad9711 | 1274 | struct mlx5e_modify_sq_param msp = {0}; |
31391048 SM |
1275 | int err; |
1276 | ||
a43b25da | 1277 | err = mlx5e_create_sq(mdev, param, csp, sqn); |
31391048 SM |
1278 | if (err) |
1279 | return err; | |
1280 | ||
1281 | msp.curr_state = MLX5_SQC_STATE_RST; | |
1282 | msp.next_state = MLX5_SQC_STATE_RDY; | |
a43b25da | 1283 | err = mlx5e_modify_sq(mdev, *sqn, &msp); |
31391048 | 1284 | if (err) |
a43b25da | 1285 | mlx5e_destroy_sq(mdev, *sqn); |
31391048 SM |
1286 | |
1287 | return err; | |
1288 | } | |
1289 | ||
7f859ecf SM |
1290 | static int mlx5e_set_sq_maxrate(struct net_device *dev, |
1291 | struct mlx5e_txqsq *sq, u32 rate); | |
1292 | ||
31391048 | 1293 | static int mlx5e_open_txqsq(struct mlx5e_channel *c, |
a43b25da | 1294 | u32 tisn, |
acc6c595 | 1295 | int txq_ix, |
6a9764ef | 1296 | struct mlx5e_params *params, |
31391048 | 1297 | struct mlx5e_sq_param *param, |
05909bab EBE |
1298 | struct mlx5e_txqsq *sq, |
1299 | int tc) | |
31391048 SM |
1300 | { |
1301 | struct mlx5e_create_sq_param csp = {}; | |
7f859ecf | 1302 | u32 tx_rate; |
f62b8bb8 AV |
1303 | int err; |
1304 | ||
05909bab | 1305 | err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc); |
f62b8bb8 AV |
1306 | if (err) |
1307 | return err; | |
1308 | ||
a43b25da | 1309 | csp.tisn = tisn; |
31391048 | 1310 | csp.tis_lst_sz = 1; |
33ad9711 SM |
1311 | csp.cqn = sq->cq.mcq.cqn; |
1312 | csp.wq_ctrl = &sq->wq_ctrl; | |
1313 | csp.min_inline_mode = sq->min_inline_mode; | |
a43b25da | 1314 | err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn); |
f62b8bb8 | 1315 | if (err) |
31391048 | 1316 | goto err_free_txqsq; |
f62b8bb8 | 1317 | |
a43b25da | 1318 | tx_rate = c->priv->tx_rates[sq->txq_ix]; |
7f859ecf | 1319 | if (tx_rate) |
a43b25da | 1320 | mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate); |
7f859ecf | 1321 | |
cbce4f44 TG |
1322 | if (params->tx_dim_enabled) |
1323 | sq->state |= BIT(MLX5E_SQ_STATE_AM); | |
1324 | ||
f62b8bb8 AV |
1325 | return 0; |
1326 | ||
31391048 | 1327 | err_free_txqsq: |
3b77235b | 1328 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
31391048 | 1329 | mlx5e_free_txqsq(sq); |
f62b8bb8 AV |
1330 | |
1331 | return err; | |
1332 | } | |
1333 | ||
db75373c EBE |
1334 | static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq) |
1335 | { | |
1336 | WARN_ONCE(sq->cc != sq->pc, | |
1337 | "SQ 0x%x: cc (0x%x) != pc (0x%x)\n", | |
1338 | sq->sqn, sq->cc, sq->pc); | |
1339 | sq->cc = 0; | |
1340 | sq->dma_fifo_cc = 0; | |
1341 | sq->pc = 0; | |
1342 | } | |
1343 | ||
acc6c595 SM |
1344 | static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq) |
1345 | { | |
a43b25da | 1346 | sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix); |
db75373c | 1347 | clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state); |
acc6c595 SM |
1348 | set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
1349 | netdev_tx_reset_queue(sq->txq); | |
1350 | netif_tx_start_queue(sq->txq); | |
1351 | } | |
1352 | ||
f62b8bb8 AV |
1353 | static inline void netif_tx_disable_queue(struct netdev_queue *txq) |
1354 | { | |
1355 | __netif_tx_lock_bh(txq); | |
1356 | netif_tx_stop_queue(txq); | |
1357 | __netif_tx_unlock_bh(txq); | |
1358 | } | |
1359 | ||
acc6c595 | 1360 | static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq) |
f62b8bb8 | 1361 | { |
33ad9711 | 1362 | struct mlx5e_channel *c = sq->channel; |
ddf385e3 | 1363 | struct mlx5_wq_cyc *wq = &sq->wq; |
33ad9711 | 1364 | |
c0f1147d | 1365 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
6e8dd6d6 | 1366 | /* prevent netif_tx_wake_queue */ |
33ad9711 | 1367 | napi_synchronize(&c->napi); |
29429f33 | 1368 | |
31391048 | 1369 | netif_tx_disable_queue(sq->txq); |
f62b8bb8 | 1370 | |
31391048 | 1371 | /* last doorbell out, godspeed .. */ |
ddf385e3 TT |
1372 | if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) { |
1373 | u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); | |
31391048 | 1374 | struct mlx5e_tx_wqe *nop; |
864b2d71 | 1375 | |
ddf385e3 TT |
1376 | sq->db.wqe_info[pi].skb = NULL; |
1377 | nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc); | |
1378 | mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl); | |
29429f33 | 1379 | } |
acc6c595 SM |
1380 | } |
1381 | ||
1382 | static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq) | |
1383 | { | |
1384 | struct mlx5e_channel *c = sq->channel; | |
a43b25da | 1385 | struct mlx5_core_dev *mdev = c->mdev; |
05d3ac97 | 1386 | struct mlx5_rate_limit rl = {0}; |
f62b8bb8 | 1387 | |
a43b25da | 1388 | mlx5e_destroy_sq(mdev, sq->sqn); |
05d3ac97 BW |
1389 | if (sq->rate_limit) { |
1390 | rl.rate = sq->rate_limit; | |
1391 | mlx5_rl_remove_rate(mdev, &rl); | |
1392 | } | |
31391048 SM |
1393 | mlx5e_free_txqsq_descs(sq); |
1394 | mlx5e_free_txqsq(sq); | |
1395 | } | |
1396 | ||
db75373c EBE |
1397 | static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq) |
1398 | { | |
1399 | unsigned long exp_time = jiffies + msecs_to_jiffies(2000); | |
1400 | ||
1401 | while (time_before(jiffies, exp_time)) { | |
1402 | if (sq->cc == sq->pc) | |
1403 | return 0; | |
1404 | ||
1405 | msleep(20); | |
1406 | } | |
1407 | ||
1408 | netdev_err(sq->channel->netdev, | |
1409 | "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n", | |
1410 | sq->sqn, sq->cc, sq->pc); | |
1411 | ||
1412 | return -ETIMEDOUT; | |
1413 | } | |
1414 | ||
1415 | static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state) | |
1416 | { | |
1417 | struct mlx5_core_dev *mdev = sq->channel->mdev; | |
1418 | struct net_device *dev = sq->channel->netdev; | |
1419 | struct mlx5e_modify_sq_param msp = {0}; | |
1420 | int err; | |
1421 | ||
1422 | msp.curr_state = curr_state; | |
1423 | msp.next_state = MLX5_SQC_STATE_RST; | |
1424 | ||
1425 | err = mlx5e_modify_sq(mdev, sq->sqn, &msp); | |
1426 | if (err) { | |
1427 | netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn); | |
1428 | return err; | |
1429 | } | |
1430 | ||
1431 | memset(&msp, 0, sizeof(msp)); | |
1432 | msp.curr_state = MLX5_SQC_STATE_RST; | |
1433 | msp.next_state = MLX5_SQC_STATE_RDY; | |
1434 | ||
1435 | err = mlx5e_modify_sq(mdev, sq->sqn, &msp); | |
1436 | if (err) { | |
1437 | netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn); | |
1438 | return err; | |
1439 | } | |
1440 | ||
1441 | return 0; | |
1442 | } | |
1443 | ||
1444 | static void mlx5e_sq_recover(struct work_struct *work) | |
1445 | { | |
1446 | struct mlx5e_txqsq_recover *recover = | |
1447 | container_of(work, struct mlx5e_txqsq_recover, | |
1448 | recover_work); | |
1449 | struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq, | |
1450 | recover); | |
1451 | struct mlx5_core_dev *mdev = sq->channel->mdev; | |
1452 | struct net_device *dev = sq->channel->netdev; | |
1453 | u8 state; | |
1454 | int err; | |
1455 | ||
1456 | err = mlx5_core_query_sq_state(mdev, sq->sqn, &state); | |
1457 | if (err) { | |
1458 | netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n", | |
1459 | sq->sqn, err); | |
1460 | return; | |
1461 | } | |
1462 | ||
1463 | if (state != MLX5_RQC_STATE_ERR) { | |
1464 | netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn); | |
1465 | return; | |
1466 | } | |
1467 | ||
1468 | netif_tx_disable_queue(sq->txq); | |
1469 | ||
1470 | if (mlx5e_wait_for_sq_flush(sq)) | |
1471 | return; | |
1472 | ||
1473 | /* If the interval between two consecutive recovers per SQ is too | |
1474 | * short, don't recover to avoid infinite loop of ERR_CQE -> recover. | |
1475 | * If we reached this state, there is probably a bug that needs to be | |
1476 | * fixed. let's keep the queue close and let tx timeout cleanup. | |
1477 | */ | |
1478 | if (jiffies_to_msecs(jiffies - recover->last_recover) < | |
1479 | MLX5E_SQ_RECOVER_MIN_INTERVAL) { | |
1480 | netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n", | |
1481 | sq->sqn); | |
1482 | return; | |
1483 | } | |
1484 | ||
1485 | /* At this point, no new packets will arrive from the stack as TXQ is | |
1486 | * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all | |
1487 | * pending WQEs. SQ can safely reset the SQ. | |
1488 | */ | |
1489 | if (mlx5e_sq_to_ready(sq, state)) | |
1490 | return; | |
1491 | ||
1492 | mlx5e_reset_txqsq_cc_pc(sq); | |
05909bab | 1493 | sq->stats->recover++; |
db75373c EBE |
1494 | recover->last_recover = jiffies; |
1495 | mlx5e_activate_txqsq(sq); | |
1496 | } | |
1497 | ||
31391048 | 1498 | static int mlx5e_open_icosq(struct mlx5e_channel *c, |
6a9764ef | 1499 | struct mlx5e_params *params, |
31391048 SM |
1500 | struct mlx5e_sq_param *param, |
1501 | struct mlx5e_icosq *sq) | |
1502 | { | |
1503 | struct mlx5e_create_sq_param csp = {}; | |
1504 | int err; | |
1505 | ||
6a9764ef | 1506 | err = mlx5e_alloc_icosq(c, param, sq); |
31391048 SM |
1507 | if (err) |
1508 | return err; | |
1509 | ||
1510 | csp.cqn = sq->cq.mcq.cqn; | |
1511 | csp.wq_ctrl = &sq->wq_ctrl; | |
6a9764ef | 1512 | csp.min_inline_mode = params->tx_min_inline_mode; |
31391048 | 1513 | set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
a43b25da | 1514 | err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn); |
31391048 SM |
1515 | if (err) |
1516 | goto err_free_icosq; | |
1517 | ||
1518 | return 0; | |
1519 | ||
1520 | err_free_icosq: | |
1521 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1522 | mlx5e_free_icosq(sq); | |
1523 | ||
1524 | return err; | |
1525 | } | |
1526 | ||
1527 | static void mlx5e_close_icosq(struct mlx5e_icosq *sq) | |
1528 | { | |
1529 | struct mlx5e_channel *c = sq->channel; | |
1530 | ||
1531 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1532 | napi_synchronize(&c->napi); | |
1533 | ||
a43b25da | 1534 | mlx5e_destroy_sq(c->mdev, sq->sqn); |
31391048 SM |
1535 | mlx5e_free_icosq(sq); |
1536 | } | |
1537 | ||
1538 | static int mlx5e_open_xdpsq(struct mlx5e_channel *c, | |
6a9764ef | 1539 | struct mlx5e_params *params, |
31391048 | 1540 | struct mlx5e_sq_param *param, |
58b99ee3 TT |
1541 | struct mlx5e_xdpsq *sq, |
1542 | bool is_redirect) | |
31391048 SM |
1543 | { |
1544 | unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT; | |
1545 | struct mlx5e_create_sq_param csp = {}; | |
31391048 SM |
1546 | unsigned int inline_hdr_sz = 0; |
1547 | int err; | |
1548 | int i; | |
1549 | ||
58b99ee3 | 1550 | err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect); |
31391048 SM |
1551 | if (err) |
1552 | return err; | |
1553 | ||
1554 | csp.tis_lst_sz = 1; | |
a43b25da | 1555 | csp.tisn = c->priv->tisn[0]; /* tc = 0 */ |
31391048 SM |
1556 | csp.cqn = sq->cq.mcq.cqn; |
1557 | csp.wq_ctrl = &sq->wq_ctrl; | |
1558 | csp.min_inline_mode = sq->min_inline_mode; | |
58b99ee3 TT |
1559 | if (is_redirect) |
1560 | set_bit(MLX5E_SQ_STATE_REDIRECT, &sq->state); | |
31391048 | 1561 | set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
a43b25da | 1562 | err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn); |
31391048 SM |
1563 | if (err) |
1564 | goto err_free_xdpsq; | |
1565 | ||
1566 | if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { | |
1567 | inline_hdr_sz = MLX5E_XDP_MIN_INLINE; | |
1568 | ds_cnt++; | |
1569 | } | |
1570 | ||
1571 | /* Pre initialize fixed WQE fields */ | |
1572 | for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) { | |
1573 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i); | |
1574 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
1575 | struct mlx5_wqe_eth_seg *eseg = &wqe->eth; | |
1576 | struct mlx5_wqe_data_seg *dseg; | |
1577 | ||
1578 | cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt); | |
1579 | eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz); | |
1580 | ||
1581 | dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1); | |
1582 | dseg->lkey = sq->mkey_be; | |
1583 | } | |
1584 | ||
1585 | return 0; | |
1586 | ||
1587 | err_free_xdpsq: | |
1588 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1589 | mlx5e_free_xdpsq(sq); | |
1590 | ||
1591 | return err; | |
1592 | } | |
1593 | ||
1594 | static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq) | |
1595 | { | |
1596 | struct mlx5e_channel *c = sq->channel; | |
1597 | ||
1598 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1599 | napi_synchronize(&c->napi); | |
1600 | ||
a43b25da | 1601 | mlx5e_destroy_sq(c->mdev, sq->sqn); |
31391048 SM |
1602 | mlx5e_free_xdpsq_descs(sq); |
1603 | mlx5e_free_xdpsq(sq); | |
f62b8bb8 AV |
1604 | } |
1605 | ||
95b6c6a5 EBE |
1606 | static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev, |
1607 | struct mlx5e_cq_param *param, | |
1608 | struct mlx5e_cq *cq) | |
f62b8bb8 | 1609 | { |
f62b8bb8 AV |
1610 | struct mlx5_core_cq *mcq = &cq->mcq; |
1611 | int eqn_not_used; | |
0b6e26ce | 1612 | unsigned int irqn; |
f62b8bb8 AV |
1613 | int err; |
1614 | u32 i; | |
1615 | ||
f62b8bb8 AV |
1616 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, |
1617 | &cq->wq_ctrl); | |
1618 | if (err) | |
1619 | return err; | |
1620 | ||
1621 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); | |
1622 | ||
f62b8bb8 AV |
1623 | mcq->cqe_sz = 64; |
1624 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
1625 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
1626 | *mcq->set_ci_db = 0; | |
1627 | *mcq->arm_db = 0; | |
1628 | mcq->vector = param->eq_ix; | |
1629 | mcq->comp = mlx5e_completion_event; | |
1630 | mcq->event = mlx5e_cq_error_event; | |
1631 | mcq->irqn = irqn; | |
f62b8bb8 AV |
1632 | |
1633 | for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { | |
1634 | struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); | |
1635 | ||
1636 | cqe->op_own = 0xf1; | |
1637 | } | |
1638 | ||
a43b25da | 1639 | cq->mdev = mdev; |
f62b8bb8 AV |
1640 | |
1641 | return 0; | |
1642 | } | |
1643 | ||
95b6c6a5 EBE |
1644 | static int mlx5e_alloc_cq(struct mlx5e_channel *c, |
1645 | struct mlx5e_cq_param *param, | |
1646 | struct mlx5e_cq *cq) | |
1647 | { | |
1648 | struct mlx5_core_dev *mdev = c->priv->mdev; | |
1649 | int err; | |
1650 | ||
231243c8 SM |
1651 | param->wq.buf_numa_node = cpu_to_node(c->cpu); |
1652 | param->wq.db_numa_node = cpu_to_node(c->cpu); | |
95b6c6a5 EBE |
1653 | param->eq_ix = c->ix; |
1654 | ||
1655 | err = mlx5e_alloc_cq_common(mdev, param, cq); | |
1656 | ||
1657 | cq->napi = &c->napi; | |
1658 | cq->channel = c; | |
1659 | ||
1660 | return err; | |
1661 | } | |
1662 | ||
3b77235b | 1663 | static void mlx5e_free_cq(struct mlx5e_cq *cq) |
f62b8bb8 | 1664 | { |
3a2f7033 | 1665 | mlx5_wq_destroy(&cq->wq_ctrl); |
f62b8bb8 AV |
1666 | } |
1667 | ||
3b77235b | 1668 | static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) |
f62b8bb8 | 1669 | { |
a43b25da | 1670 | struct mlx5_core_dev *mdev = cq->mdev; |
f62b8bb8 AV |
1671 | struct mlx5_core_cq *mcq = &cq->mcq; |
1672 | ||
1673 | void *in; | |
1674 | void *cqc; | |
1675 | int inlen; | |
0b6e26ce | 1676 | unsigned int irqn_not_used; |
f62b8bb8 AV |
1677 | int eqn; |
1678 | int err; | |
1679 | ||
1680 | inlen = MLX5_ST_SZ_BYTES(create_cq_in) + | |
3a2f7033 | 1681 | sizeof(u64) * cq->wq_ctrl.buf.npages; |
1b9a07ee | 1682 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
1683 | if (!in) |
1684 | return -ENOMEM; | |
1685 | ||
1686 | cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); | |
1687 | ||
1688 | memcpy(cqc, param->cqc, sizeof(param->cqc)); | |
1689 | ||
3a2f7033 | 1690 | mlx5_fill_page_frag_array(&cq->wq_ctrl.buf, |
1c1b5228 | 1691 | (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas)); |
f62b8bb8 AV |
1692 | |
1693 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used); | |
1694 | ||
9908aa29 | 1695 | MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode); |
f62b8bb8 | 1696 | MLX5_SET(cqc, cqc, c_eqn, eqn); |
30aa60b3 | 1697 | MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index); |
3a2f7033 | 1698 | MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - |
68cdf5d6 | 1699 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
1700 | MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); |
1701 | ||
1702 | err = mlx5_core_create_cq(mdev, mcq, in, inlen); | |
1703 | ||
1704 | kvfree(in); | |
1705 | ||
1706 | if (err) | |
1707 | return err; | |
1708 | ||
1709 | mlx5e_cq_arm(cq); | |
1710 | ||
1711 | return 0; | |
1712 | } | |
1713 | ||
3b77235b | 1714 | static void mlx5e_destroy_cq(struct mlx5e_cq *cq) |
f62b8bb8 | 1715 | { |
a43b25da | 1716 | mlx5_core_destroy_cq(cq->mdev, &cq->mcq); |
f62b8bb8 AV |
1717 | } |
1718 | ||
1719 | static int mlx5e_open_cq(struct mlx5e_channel *c, | |
9a317425 | 1720 | struct net_dim_cq_moder moder, |
f62b8bb8 | 1721 | struct mlx5e_cq_param *param, |
6a9764ef | 1722 | struct mlx5e_cq *cq) |
f62b8bb8 | 1723 | { |
a43b25da | 1724 | struct mlx5_core_dev *mdev = c->mdev; |
f62b8bb8 | 1725 | int err; |
f62b8bb8 | 1726 | |
3b77235b | 1727 | err = mlx5e_alloc_cq(c, param, cq); |
f62b8bb8 AV |
1728 | if (err) |
1729 | return err; | |
1730 | ||
3b77235b | 1731 | err = mlx5e_create_cq(cq, param); |
f62b8bb8 | 1732 | if (err) |
3b77235b | 1733 | goto err_free_cq; |
f62b8bb8 | 1734 | |
7524a5d8 | 1735 | if (MLX5_CAP_GEN(mdev, cq_moderation)) |
6a9764ef | 1736 | mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts); |
f62b8bb8 AV |
1737 | return 0; |
1738 | ||
3b77235b SM |
1739 | err_free_cq: |
1740 | mlx5e_free_cq(cq); | |
f62b8bb8 AV |
1741 | |
1742 | return err; | |
1743 | } | |
1744 | ||
1745 | static void mlx5e_close_cq(struct mlx5e_cq *cq) | |
1746 | { | |
f62b8bb8 | 1747 | mlx5e_destroy_cq(cq); |
3b77235b | 1748 | mlx5e_free_cq(cq); |
f62b8bb8 AV |
1749 | } |
1750 | ||
231243c8 SM |
1751 | static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix) |
1752 | { | |
1753 | return cpumask_first(priv->mdev->priv.irq_info[ix].mask); | |
1754 | } | |
1755 | ||
f62b8bb8 | 1756 | static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, |
6a9764ef | 1757 | struct mlx5e_params *params, |
f62b8bb8 AV |
1758 | struct mlx5e_channel_param *cparam) |
1759 | { | |
f62b8bb8 AV |
1760 | int err; |
1761 | int tc; | |
1762 | ||
1763 | for (tc = 0; tc < c->num_tc; tc++) { | |
6a9764ef SM |
1764 | err = mlx5e_open_cq(c, params->tx_cq_moderation, |
1765 | &cparam->tx_cq, &c->sq[tc].cq); | |
f62b8bb8 AV |
1766 | if (err) |
1767 | goto err_close_tx_cqs; | |
f62b8bb8 AV |
1768 | } |
1769 | ||
1770 | return 0; | |
1771 | ||
1772 | err_close_tx_cqs: | |
1773 | for (tc--; tc >= 0; tc--) | |
1774 | mlx5e_close_cq(&c->sq[tc].cq); | |
1775 | ||
1776 | return err; | |
1777 | } | |
1778 | ||
1779 | static void mlx5e_close_tx_cqs(struct mlx5e_channel *c) | |
1780 | { | |
1781 | int tc; | |
1782 | ||
1783 | for (tc = 0; tc < c->num_tc; tc++) | |
1784 | mlx5e_close_cq(&c->sq[tc].cq); | |
1785 | } | |
1786 | ||
1787 | static int mlx5e_open_sqs(struct mlx5e_channel *c, | |
6a9764ef | 1788 | struct mlx5e_params *params, |
f62b8bb8 AV |
1789 | struct mlx5e_channel_param *cparam) |
1790 | { | |
05909bab EBE |
1791 | struct mlx5e_priv *priv = c->priv; |
1792 | int err, tc, max_nch = priv->profile->max_nch(priv->mdev); | |
f62b8bb8 | 1793 | |
6a9764ef | 1794 | for (tc = 0; tc < params->num_tc; tc++) { |
05909bab | 1795 | int txq_ix = c->ix + tc * max_nch; |
acc6c595 | 1796 | |
a43b25da | 1797 | err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix, |
05909bab | 1798 | params, &cparam->sq, &c->sq[tc], tc); |
f62b8bb8 AV |
1799 | if (err) |
1800 | goto err_close_sqs; | |
1801 | } | |
1802 | ||
1803 | return 0; | |
1804 | ||
1805 | err_close_sqs: | |
1806 | for (tc--; tc >= 0; tc--) | |
31391048 | 1807 | mlx5e_close_txqsq(&c->sq[tc]); |
f62b8bb8 AV |
1808 | |
1809 | return err; | |
1810 | } | |
1811 | ||
1812 | static void mlx5e_close_sqs(struct mlx5e_channel *c) | |
1813 | { | |
1814 | int tc; | |
1815 | ||
1816 | for (tc = 0; tc < c->num_tc; tc++) | |
31391048 | 1817 | mlx5e_close_txqsq(&c->sq[tc]); |
f62b8bb8 AV |
1818 | } |
1819 | ||
507f0c81 | 1820 | static int mlx5e_set_sq_maxrate(struct net_device *dev, |
31391048 | 1821 | struct mlx5e_txqsq *sq, u32 rate) |
507f0c81 YP |
1822 | { |
1823 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1824 | struct mlx5_core_dev *mdev = priv->mdev; | |
33ad9711 | 1825 | struct mlx5e_modify_sq_param msp = {0}; |
05d3ac97 | 1826 | struct mlx5_rate_limit rl = {0}; |
507f0c81 YP |
1827 | u16 rl_index = 0; |
1828 | int err; | |
1829 | ||
1830 | if (rate == sq->rate_limit) | |
1831 | /* nothing to do */ | |
1832 | return 0; | |
1833 | ||
05d3ac97 BW |
1834 | if (sq->rate_limit) { |
1835 | rl.rate = sq->rate_limit; | |
507f0c81 | 1836 | /* remove current rl index to free space to next ones */ |
05d3ac97 BW |
1837 | mlx5_rl_remove_rate(mdev, &rl); |
1838 | } | |
507f0c81 YP |
1839 | |
1840 | sq->rate_limit = 0; | |
1841 | ||
1842 | if (rate) { | |
05d3ac97 BW |
1843 | rl.rate = rate; |
1844 | err = mlx5_rl_add_rate(mdev, &rl_index, &rl); | |
507f0c81 YP |
1845 | if (err) { |
1846 | netdev_err(dev, "Failed configuring rate %u: %d\n", | |
1847 | rate, err); | |
1848 | return err; | |
1849 | } | |
1850 | } | |
1851 | ||
33ad9711 SM |
1852 | msp.curr_state = MLX5_SQC_STATE_RDY; |
1853 | msp.next_state = MLX5_SQC_STATE_RDY; | |
1854 | msp.rl_index = rl_index; | |
1855 | msp.rl_update = true; | |
a43b25da | 1856 | err = mlx5e_modify_sq(mdev, sq->sqn, &msp); |
507f0c81 YP |
1857 | if (err) { |
1858 | netdev_err(dev, "Failed configuring rate %u: %d\n", | |
1859 | rate, err); | |
1860 | /* remove the rate from the table */ | |
1861 | if (rate) | |
05d3ac97 | 1862 | mlx5_rl_remove_rate(mdev, &rl); |
507f0c81 YP |
1863 | return err; |
1864 | } | |
1865 | ||
1866 | sq->rate_limit = rate; | |
1867 | return 0; | |
1868 | } | |
1869 | ||
1870 | static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate) | |
1871 | { | |
1872 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1873 | struct mlx5_core_dev *mdev = priv->mdev; | |
acc6c595 | 1874 | struct mlx5e_txqsq *sq = priv->txq2sq[index]; |
507f0c81 YP |
1875 | int err = 0; |
1876 | ||
1877 | if (!mlx5_rl_is_supported(mdev)) { | |
1878 | netdev_err(dev, "Rate limiting is not supported on this device\n"); | |
1879 | return -EINVAL; | |
1880 | } | |
1881 | ||
1882 | /* rate is given in Mb/sec, HW config is in Kb/sec */ | |
1883 | rate = rate << 10; | |
1884 | ||
1885 | /* Check whether rate in valid range, 0 is always valid */ | |
1886 | if (rate && !mlx5_rl_is_in_range(mdev, rate)) { | |
1887 | netdev_err(dev, "TX rate %u, is not in range\n", rate); | |
1888 | return -ERANGE; | |
1889 | } | |
1890 | ||
1891 | mutex_lock(&priv->state_lock); | |
1892 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
1893 | err = mlx5e_set_sq_maxrate(dev, sq, rate); | |
1894 | if (!err) | |
1895 | priv->tx_rates[index] = rate; | |
1896 | mutex_unlock(&priv->state_lock); | |
1897 | ||
1898 | return err; | |
1899 | } | |
1900 | ||
f62b8bb8 | 1901 | static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, |
6a9764ef | 1902 | struct mlx5e_params *params, |
f62b8bb8 AV |
1903 | struct mlx5e_channel_param *cparam, |
1904 | struct mlx5e_channel **cp) | |
1905 | { | |
9a317425 | 1906 | struct net_dim_cq_moder icocq_moder = {0, 0}; |
f62b8bb8 | 1907 | struct net_device *netdev = priv->netdev; |
231243c8 | 1908 | int cpu = mlx5e_get_cpu(priv, ix); |
f62b8bb8 | 1909 | struct mlx5e_channel *c; |
a8c2eb15 | 1910 | unsigned int irq; |
f62b8bb8 | 1911 | int err; |
a8c2eb15 | 1912 | int eqn; |
f62b8bb8 | 1913 | |
ca11b798 | 1914 | c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu)); |
f62b8bb8 AV |
1915 | if (!c) |
1916 | return -ENOMEM; | |
1917 | ||
1918 | c->priv = priv; | |
a43b25da SM |
1919 | c->mdev = priv->mdev; |
1920 | c->tstamp = &priv->tstamp; | |
f62b8bb8 | 1921 | c->ix = ix; |
231243c8 | 1922 | c->cpu = cpu; |
f62b8bb8 AV |
1923 | c->pdev = &priv->mdev->pdev->dev; |
1924 | c->netdev = priv->netdev; | |
b50d292b | 1925 | c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key); |
6a9764ef SM |
1926 | c->num_tc = params->num_tc; |
1927 | c->xdp = !!params->xdp_prog; | |
05909bab | 1928 | c->stats = &priv->channel_stats[ix].ch; |
cb3c7fd4 | 1929 | |
a8c2eb15 TT |
1930 | mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq); |
1931 | c->irq_desc = irq_to_desc(irq); | |
1932 | ||
f62b8bb8 AV |
1933 | netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64); |
1934 | ||
6a9764ef | 1935 | err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq); |
f62b8bb8 AV |
1936 | if (err) |
1937 | goto err_napi_del; | |
1938 | ||
6a9764ef | 1939 | err = mlx5e_open_tx_cqs(c, params, cparam); |
d3c9bc27 TT |
1940 | if (err) |
1941 | goto err_close_icosq_cq; | |
1942 | ||
58b99ee3 | 1943 | err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq); |
f62b8bb8 AV |
1944 | if (err) |
1945 | goto err_close_tx_cqs; | |
f62b8bb8 | 1946 | |
58b99ee3 TT |
1947 | err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq); |
1948 | if (err) | |
1949 | goto err_close_xdp_tx_cqs; | |
1950 | ||
d7a0ecab | 1951 | /* XDP SQ CQ params are same as normal TXQ sq CQ params */ |
6a9764ef SM |
1952 | err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation, |
1953 | &cparam->tx_cq, &c->rq.xdpsq.cq) : 0; | |
d7a0ecab SM |
1954 | if (err) |
1955 | goto err_close_rx_cq; | |
1956 | ||
f62b8bb8 AV |
1957 | napi_enable(&c->napi); |
1958 | ||
6a9764ef | 1959 | err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq); |
f62b8bb8 AV |
1960 | if (err) |
1961 | goto err_disable_napi; | |
1962 | ||
6a9764ef | 1963 | err = mlx5e_open_sqs(c, params, cparam); |
d3c9bc27 TT |
1964 | if (err) |
1965 | goto err_close_icosq; | |
1966 | ||
58b99ee3 | 1967 | err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0; |
d7a0ecab SM |
1968 | if (err) |
1969 | goto err_close_sqs; | |
b5503b99 | 1970 | |
6a9764ef | 1971 | err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq); |
f62b8bb8 | 1972 | if (err) |
b5503b99 | 1973 | goto err_close_xdp_sq; |
f62b8bb8 | 1974 | |
58b99ee3 TT |
1975 | err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true); |
1976 | if (err) | |
1977 | goto err_close_rq; | |
1978 | ||
f62b8bb8 AV |
1979 | *cp = c; |
1980 | ||
1981 | return 0; | |
58b99ee3 TT |
1982 | |
1983 | err_close_rq: | |
1984 | mlx5e_close_rq(&c->rq); | |
1985 | ||
b5503b99 | 1986 | err_close_xdp_sq: |
d7a0ecab | 1987 | if (c->xdp) |
31391048 | 1988 | mlx5e_close_xdpsq(&c->rq.xdpsq); |
f62b8bb8 AV |
1989 | |
1990 | err_close_sqs: | |
1991 | mlx5e_close_sqs(c); | |
1992 | ||
d3c9bc27 | 1993 | err_close_icosq: |
31391048 | 1994 | mlx5e_close_icosq(&c->icosq); |
d3c9bc27 | 1995 | |
f62b8bb8 AV |
1996 | err_disable_napi: |
1997 | napi_disable(&c->napi); | |
d7a0ecab | 1998 | if (c->xdp) |
31871f87 | 1999 | mlx5e_close_cq(&c->rq.xdpsq.cq); |
d7a0ecab SM |
2000 | |
2001 | err_close_rx_cq: | |
f62b8bb8 AV |
2002 | mlx5e_close_cq(&c->rq.cq); |
2003 | ||
58b99ee3 TT |
2004 | err_close_xdp_tx_cqs: |
2005 | mlx5e_close_cq(&c->xdpsq.cq); | |
2006 | ||
f62b8bb8 AV |
2007 | err_close_tx_cqs: |
2008 | mlx5e_close_tx_cqs(c); | |
2009 | ||
d3c9bc27 TT |
2010 | err_close_icosq_cq: |
2011 | mlx5e_close_cq(&c->icosq.cq); | |
2012 | ||
f62b8bb8 AV |
2013 | err_napi_del: |
2014 | netif_napi_del(&c->napi); | |
ca11b798 | 2015 | kvfree(c); |
f62b8bb8 AV |
2016 | |
2017 | return err; | |
2018 | } | |
2019 | ||
acc6c595 SM |
2020 | static void mlx5e_activate_channel(struct mlx5e_channel *c) |
2021 | { | |
2022 | int tc; | |
2023 | ||
2024 | for (tc = 0; tc < c->num_tc; tc++) | |
2025 | mlx5e_activate_txqsq(&c->sq[tc]); | |
2026 | mlx5e_activate_rq(&c->rq); | |
231243c8 | 2027 | netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix); |
acc6c595 SM |
2028 | } |
2029 | ||
2030 | static void mlx5e_deactivate_channel(struct mlx5e_channel *c) | |
2031 | { | |
2032 | int tc; | |
2033 | ||
2034 | mlx5e_deactivate_rq(&c->rq); | |
2035 | for (tc = 0; tc < c->num_tc; tc++) | |
2036 | mlx5e_deactivate_txqsq(&c->sq[tc]); | |
2037 | } | |
2038 | ||
f62b8bb8 AV |
2039 | static void mlx5e_close_channel(struct mlx5e_channel *c) |
2040 | { | |
58b99ee3 | 2041 | mlx5e_close_xdpsq(&c->xdpsq); |
f62b8bb8 | 2042 | mlx5e_close_rq(&c->rq); |
b5503b99 | 2043 | if (c->xdp) |
31391048 | 2044 | mlx5e_close_xdpsq(&c->rq.xdpsq); |
f62b8bb8 | 2045 | mlx5e_close_sqs(c); |
31391048 | 2046 | mlx5e_close_icosq(&c->icosq); |
f62b8bb8 | 2047 | napi_disable(&c->napi); |
b5503b99 | 2048 | if (c->xdp) |
31871f87 | 2049 | mlx5e_close_cq(&c->rq.xdpsq.cq); |
f62b8bb8 | 2050 | mlx5e_close_cq(&c->rq.cq); |
58b99ee3 | 2051 | mlx5e_close_cq(&c->xdpsq.cq); |
f62b8bb8 | 2052 | mlx5e_close_tx_cqs(c); |
d3c9bc27 | 2053 | mlx5e_close_cq(&c->icosq.cq); |
f62b8bb8 | 2054 | netif_napi_del(&c->napi); |
7ae92ae5 | 2055 | |
ca11b798 | 2056 | kvfree(c); |
f62b8bb8 AV |
2057 | } |
2058 | ||
069d1146 TT |
2059 | #define DEFAULT_FRAG_SIZE (2048) |
2060 | ||
2061 | static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev, | |
2062 | struct mlx5e_params *params, | |
2063 | struct mlx5e_rq_frags_info *info) | |
2064 | { | |
2065 | u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu); | |
2066 | int frag_size_max = DEFAULT_FRAG_SIZE; | |
2067 | u32 buf_size = 0; | |
2068 | int i; | |
2069 | ||
2070 | #ifdef CONFIG_MLX5_EN_IPSEC | |
2071 | if (MLX5_IPSEC_DEV(mdev)) | |
2072 | byte_count += MLX5E_METADATA_ETHER_LEN; | |
2073 | #endif | |
2074 | ||
2075 | if (mlx5e_rx_is_linear_skb(mdev, params)) { | |
2076 | int frag_stride; | |
2077 | ||
2078 | frag_stride = mlx5e_rx_get_linear_frag_sz(params); | |
2079 | frag_stride = roundup_pow_of_two(frag_stride); | |
2080 | ||
2081 | info->arr[0].frag_size = byte_count; | |
2082 | info->arr[0].frag_stride = frag_stride; | |
2083 | info->num_frags = 1; | |
2084 | info->wqe_bulk = PAGE_SIZE / frag_stride; | |
2085 | goto out; | |
2086 | } | |
2087 | ||
2088 | if (byte_count > PAGE_SIZE + | |
2089 | (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max) | |
2090 | frag_size_max = PAGE_SIZE; | |
2091 | ||
2092 | i = 0; | |
2093 | while (buf_size < byte_count) { | |
2094 | int frag_size = byte_count - buf_size; | |
2095 | ||
2096 | if (i < MLX5E_MAX_RX_FRAGS - 1) | |
2097 | frag_size = min(frag_size, frag_size_max); | |
2098 | ||
2099 | info->arr[i].frag_size = frag_size; | |
2100 | info->arr[i].frag_stride = roundup_pow_of_two(frag_size); | |
2101 | ||
2102 | buf_size += frag_size; | |
2103 | i++; | |
2104 | } | |
2105 | info->num_frags = i; | |
2106 | /* number of different wqes sharing a page */ | |
2107 | info->wqe_bulk = 1 + (info->num_frags % 2); | |
2108 | ||
2109 | out: | |
2110 | info->wqe_bulk = max_t(u8, info->wqe_bulk, 8); | |
2111 | info->log_num_frags = order_base_2(info->num_frags); | |
2112 | } | |
2113 | ||
99cbfa93 TT |
2114 | static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs) |
2115 | { | |
2116 | int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs; | |
2117 | ||
2118 | switch (wq_type) { | |
2119 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
2120 | sz += sizeof(struct mlx5e_rx_wqe_ll); | |
2121 | break; | |
2122 | default: /* MLX5_WQ_TYPE_CYCLIC */ | |
2123 | sz += sizeof(struct mlx5e_rx_wqe_cyc); | |
2124 | } | |
2125 | ||
2126 | return order_base_2(sz); | |
2127 | } | |
2128 | ||
f62b8bb8 | 2129 | static void mlx5e_build_rq_param(struct mlx5e_priv *priv, |
6a9764ef | 2130 | struct mlx5e_params *params, |
f62b8bb8 AV |
2131 | struct mlx5e_rq_param *param) |
2132 | { | |
f1e4fc9b | 2133 | struct mlx5_core_dev *mdev = priv->mdev; |
f62b8bb8 AV |
2134 | void *rqc = param->rqc; |
2135 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
99cbfa93 | 2136 | int ndsegs = 1; |
f62b8bb8 | 2137 | |
6a9764ef | 2138 | switch (params->rq_wq_type) { |
461017cb | 2139 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: |
f1e4fc9b | 2140 | MLX5_SET(wq, wq, log_wqe_num_of_strides, |
619a8f2a TT |
2141 | mlx5e_mpwqe_get_log_num_strides(mdev, params) - |
2142 | MLX5_MPWQE_LOG_NUM_STRIDES_BASE); | |
f1e4fc9b | 2143 | MLX5_SET(wq, wq, log_wqe_stride_size, |
619a8f2a TT |
2144 | mlx5e_mpwqe_get_log_stride_size(mdev, params) - |
2145 | MLX5_MPWQE_LOG_STRIDE_SZ_BASE); | |
73281b78 | 2146 | MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params)); |
461017cb | 2147 | break; |
99cbfa93 | 2148 | default: /* MLX5_WQ_TYPE_CYCLIC */ |
73281b78 | 2149 | MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames); |
069d1146 TT |
2150 | mlx5e_build_rq_frags_info(mdev, params, ¶m->frags_info); |
2151 | ndsegs = param->frags_info.num_frags; | |
461017cb TT |
2152 | } |
2153 | ||
99cbfa93 | 2154 | MLX5_SET(wq, wq, wq_type, params->rq_wq_type); |
f62b8bb8 | 2155 | MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); |
99cbfa93 TT |
2156 | MLX5_SET(wq, wq, log_wq_stride, |
2157 | mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs)); | |
f1e4fc9b | 2158 | MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn); |
593cf338 | 2159 | MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter); |
6a9764ef | 2160 | MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable); |
102722fc | 2161 | MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en); |
f62b8bb8 | 2162 | |
f1e4fc9b | 2163 | param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev); |
f62b8bb8 AV |
2164 | } |
2165 | ||
7cbaf9a3 | 2166 | static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv, |
2f0db879 | 2167 | struct mlx5e_rq_param *param) |
556dd1b9 | 2168 | { |
7cbaf9a3 | 2169 | struct mlx5_core_dev *mdev = priv->mdev; |
556dd1b9 TT |
2170 | void *rqc = param->rqc; |
2171 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
2172 | ||
99cbfa93 TT |
2173 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); |
2174 | MLX5_SET(wq, wq, log_wq_stride, | |
2175 | mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1)); | |
7cbaf9a3 | 2176 | MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter); |
2f0db879 GP |
2177 | |
2178 | param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev); | |
556dd1b9 TT |
2179 | } |
2180 | ||
d3c9bc27 TT |
2181 | static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv, |
2182 | struct mlx5e_sq_param *param) | |
f62b8bb8 AV |
2183 | { |
2184 | void *sqc = param->sqc; | |
2185 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
2186 | ||
f62b8bb8 | 2187 | MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); |
b50d292b | 2188 | MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn); |
f62b8bb8 | 2189 | |
311c7c71 | 2190 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); |
d3c9bc27 TT |
2191 | } |
2192 | ||
2193 | static void mlx5e_build_sq_param(struct mlx5e_priv *priv, | |
6a9764ef | 2194 | struct mlx5e_params *params, |
d3c9bc27 TT |
2195 | struct mlx5e_sq_param *param) |
2196 | { | |
2197 | void *sqc = param->sqc; | |
2198 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
2199 | ||
2200 | mlx5e_build_sq_param_common(priv, param); | |
6a9764ef | 2201 | MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size); |
2ac9cfe7 | 2202 | MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev)); |
f62b8bb8 AV |
2203 | } |
2204 | ||
2205 | static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv, | |
2206 | struct mlx5e_cq_param *param) | |
2207 | { | |
2208 | void *cqc = param->cqc; | |
2209 | ||
30aa60b3 | 2210 | MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index); |
f62b8bb8 AV |
2211 | } |
2212 | ||
2213 | static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, | |
6a9764ef | 2214 | struct mlx5e_params *params, |
f62b8bb8 AV |
2215 | struct mlx5e_cq_param *param) |
2216 | { | |
73281b78 | 2217 | struct mlx5_core_dev *mdev = priv->mdev; |
f62b8bb8 | 2218 | void *cqc = param->cqc; |
461017cb | 2219 | u8 log_cq_size; |
f62b8bb8 | 2220 | |
6a9764ef | 2221 | switch (params->rq_wq_type) { |
461017cb | 2222 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: |
73281b78 TT |
2223 | log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) + |
2224 | mlx5e_mpwqe_get_log_num_strides(mdev, params); | |
461017cb | 2225 | break; |
99cbfa93 | 2226 | default: /* MLX5_WQ_TYPE_CYCLIC */ |
73281b78 | 2227 | log_cq_size = params->log_rq_mtu_frames; |
461017cb TT |
2228 | } |
2229 | ||
2230 | MLX5_SET(cqc, cqc, log_cq_size, log_cq_size); | |
6a9764ef | 2231 | if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) { |
7219ab34 TT |
2232 | MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM); |
2233 | MLX5_SET(cqc, cqc, cqe_comp_en, 1); | |
2234 | } | |
f62b8bb8 AV |
2235 | |
2236 | mlx5e_build_common_cq_param(priv, param); | |
0088cbbc | 2237 | param->cq_period_mode = params->rx_cq_moderation.cq_period_mode; |
f62b8bb8 AV |
2238 | } |
2239 | ||
2240 | static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, | |
6a9764ef | 2241 | struct mlx5e_params *params, |
f62b8bb8 AV |
2242 | struct mlx5e_cq_param *param) |
2243 | { | |
2244 | void *cqc = param->cqc; | |
2245 | ||
6a9764ef | 2246 | MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size); |
f62b8bb8 AV |
2247 | |
2248 | mlx5e_build_common_cq_param(priv, param); | |
0088cbbc | 2249 | param->cq_period_mode = params->tx_cq_moderation.cq_period_mode; |
f62b8bb8 AV |
2250 | } |
2251 | ||
d3c9bc27 | 2252 | static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv, |
6a9764ef SM |
2253 | u8 log_wq_size, |
2254 | struct mlx5e_cq_param *param) | |
d3c9bc27 TT |
2255 | { |
2256 | void *cqc = param->cqc; | |
2257 | ||
2258 | MLX5_SET(cqc, cqc, log_cq_size, log_wq_size); | |
2259 | ||
2260 | mlx5e_build_common_cq_param(priv, param); | |
9908aa29 | 2261 | |
9a317425 | 2262 | param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; |
d3c9bc27 TT |
2263 | } |
2264 | ||
2265 | static void mlx5e_build_icosq_param(struct mlx5e_priv *priv, | |
6a9764ef SM |
2266 | u8 log_wq_size, |
2267 | struct mlx5e_sq_param *param) | |
d3c9bc27 TT |
2268 | { |
2269 | void *sqc = param->sqc; | |
2270 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
2271 | ||
2272 | mlx5e_build_sq_param_common(priv, param); | |
2273 | ||
2274 | MLX5_SET(wq, wq, log_wq_sz, log_wq_size); | |
bc77b240 | 2275 | MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq)); |
d3c9bc27 TT |
2276 | } |
2277 | ||
b5503b99 | 2278 | static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv, |
6a9764ef | 2279 | struct mlx5e_params *params, |
b5503b99 SM |
2280 | struct mlx5e_sq_param *param) |
2281 | { | |
2282 | void *sqc = param->sqc; | |
2283 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
2284 | ||
2285 | mlx5e_build_sq_param_common(priv, param); | |
6a9764ef | 2286 | MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size); |
b5503b99 SM |
2287 | } |
2288 | ||
6a9764ef SM |
2289 | static void mlx5e_build_channel_param(struct mlx5e_priv *priv, |
2290 | struct mlx5e_params *params, | |
2291 | struct mlx5e_channel_param *cparam) | |
f62b8bb8 | 2292 | { |
bc77b240 | 2293 | u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; |
d3c9bc27 | 2294 | |
6a9764ef SM |
2295 | mlx5e_build_rq_param(priv, params, &cparam->rq); |
2296 | mlx5e_build_sq_param(priv, params, &cparam->sq); | |
2297 | mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq); | |
2298 | mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq); | |
2299 | mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq); | |
2300 | mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq); | |
2301 | mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq); | |
f62b8bb8 AV |
2302 | } |
2303 | ||
55c2503d SM |
2304 | int mlx5e_open_channels(struct mlx5e_priv *priv, |
2305 | struct mlx5e_channels *chs) | |
f62b8bb8 | 2306 | { |
6b87663f | 2307 | struct mlx5e_channel_param *cparam; |
03289b88 | 2308 | int err = -ENOMEM; |
f62b8bb8 | 2309 | int i; |
f62b8bb8 | 2310 | |
6a9764ef | 2311 | chs->num = chs->params.num_channels; |
03289b88 | 2312 | |
ff9c852f | 2313 | chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL); |
ca11b798 | 2314 | cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL); |
acc6c595 SM |
2315 | if (!chs->c || !cparam) |
2316 | goto err_free; | |
f62b8bb8 | 2317 | |
6a9764ef | 2318 | mlx5e_build_channel_param(priv, &chs->params, cparam); |
ff9c852f | 2319 | for (i = 0; i < chs->num; i++) { |
6a9764ef | 2320 | err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]); |
f62b8bb8 AV |
2321 | if (err) |
2322 | goto err_close_channels; | |
2323 | } | |
2324 | ||
ca11b798 | 2325 | kvfree(cparam); |
f62b8bb8 AV |
2326 | return 0; |
2327 | ||
2328 | err_close_channels: | |
2329 | for (i--; i >= 0; i--) | |
ff9c852f | 2330 | mlx5e_close_channel(chs->c[i]); |
f62b8bb8 | 2331 | |
acc6c595 | 2332 | err_free: |
ff9c852f | 2333 | kfree(chs->c); |
ca11b798 | 2334 | kvfree(cparam); |
ff9c852f | 2335 | chs->num = 0; |
f62b8bb8 AV |
2336 | return err; |
2337 | } | |
2338 | ||
acc6c595 | 2339 | static void mlx5e_activate_channels(struct mlx5e_channels *chs) |
f62b8bb8 AV |
2340 | { |
2341 | int i; | |
2342 | ||
acc6c595 SM |
2343 | for (i = 0; i < chs->num; i++) |
2344 | mlx5e_activate_channel(chs->c[i]); | |
2345 | } | |
2346 | ||
2347 | static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs) | |
2348 | { | |
2349 | int err = 0; | |
2350 | int i; | |
2351 | ||
1e7477ae EBE |
2352 | for (i = 0; i < chs->num; i++) |
2353 | err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, | |
2354 | err ? 0 : 20000); | |
acc6c595 | 2355 | |
1e7477ae | 2356 | return err ? -ETIMEDOUT : 0; |
acc6c595 SM |
2357 | } |
2358 | ||
2359 | static void mlx5e_deactivate_channels(struct mlx5e_channels *chs) | |
2360 | { | |
2361 | int i; | |
2362 | ||
2363 | for (i = 0; i < chs->num; i++) | |
2364 | mlx5e_deactivate_channel(chs->c[i]); | |
2365 | } | |
2366 | ||
55c2503d | 2367 | void mlx5e_close_channels(struct mlx5e_channels *chs) |
acc6c595 SM |
2368 | { |
2369 | int i; | |
c3b7c5c9 | 2370 | |
ff9c852f SM |
2371 | for (i = 0; i < chs->num; i++) |
2372 | mlx5e_close_channel(chs->c[i]); | |
f62b8bb8 | 2373 | |
ff9c852f SM |
2374 | kfree(chs->c); |
2375 | chs->num = 0; | |
f62b8bb8 AV |
2376 | } |
2377 | ||
a5f97fee SM |
2378 | static int |
2379 | mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt) | |
f62b8bb8 AV |
2380 | { |
2381 | struct mlx5_core_dev *mdev = priv->mdev; | |
f62b8bb8 AV |
2382 | void *rqtc; |
2383 | int inlen; | |
2384 | int err; | |
1da36696 | 2385 | u32 *in; |
a5f97fee | 2386 | int i; |
f62b8bb8 | 2387 | |
f62b8bb8 | 2388 | inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; |
1b9a07ee | 2389 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
2390 | if (!in) |
2391 | return -ENOMEM; | |
2392 | ||
2393 | rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); | |
2394 | ||
2395 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
2396 | MLX5_SET(rqtc, rqtc, rqt_max_size, sz); | |
2397 | ||
a5f97fee SM |
2398 | for (i = 0; i < sz; i++) |
2399 | MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn); | |
2be6967c | 2400 | |
398f3351 HHZ |
2401 | err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn); |
2402 | if (!err) | |
2403 | rqt->enabled = true; | |
f62b8bb8 AV |
2404 | |
2405 | kvfree(in); | |
1da36696 TT |
2406 | return err; |
2407 | } | |
2408 | ||
cb67b832 | 2409 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt) |
1da36696 | 2410 | { |
398f3351 HHZ |
2411 | rqt->enabled = false; |
2412 | mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn); | |
1da36696 TT |
2413 | } |
2414 | ||
8f493ffd | 2415 | int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv) |
6bfd390b HHZ |
2416 | { |
2417 | struct mlx5e_rqt *rqt = &priv->indir_rqt; | |
8f493ffd | 2418 | int err; |
6bfd390b | 2419 | |
8f493ffd SM |
2420 | err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt); |
2421 | if (err) | |
2422 | mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err); | |
2423 | return err; | |
6bfd390b HHZ |
2424 | } |
2425 | ||
cb67b832 | 2426 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv) |
1da36696 | 2427 | { |
398f3351 | 2428 | struct mlx5e_rqt *rqt; |
1da36696 TT |
2429 | int err; |
2430 | int ix; | |
2431 | ||
6bfd390b | 2432 | for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) { |
398f3351 | 2433 | rqt = &priv->direct_tir[ix].rqt; |
a5f97fee | 2434 | err = mlx5e_create_rqt(priv, 1 /*size */, rqt); |
1da36696 TT |
2435 | if (err) |
2436 | goto err_destroy_rqts; | |
2437 | } | |
2438 | ||
2439 | return 0; | |
2440 | ||
2441 | err_destroy_rqts: | |
8f493ffd | 2442 | mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err); |
1da36696 | 2443 | for (ix--; ix >= 0; ix--) |
398f3351 | 2444 | mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt); |
1da36696 | 2445 | |
f62b8bb8 AV |
2446 | return err; |
2447 | } | |
2448 | ||
8f493ffd SM |
2449 | void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv) |
2450 | { | |
2451 | int i; | |
2452 | ||
2453 | for (i = 0; i < priv->profile->max_nch(priv->mdev); i++) | |
2454 | mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt); | |
2455 | } | |
2456 | ||
a5f97fee SM |
2457 | static int mlx5e_rx_hash_fn(int hfunc) |
2458 | { | |
2459 | return (hfunc == ETH_RSS_HASH_TOP) ? | |
2460 | MLX5_RX_HASH_FN_TOEPLITZ : | |
2461 | MLX5_RX_HASH_FN_INVERTED_XOR8; | |
2462 | } | |
2463 | ||
3f6d08d1 | 2464 | int mlx5e_bits_invert(unsigned long a, int size) |
a5f97fee SM |
2465 | { |
2466 | int inv = 0; | |
2467 | int i; | |
2468 | ||
2469 | for (i = 0; i < size; i++) | |
2470 | inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i; | |
2471 | ||
2472 | return inv; | |
2473 | } | |
2474 | ||
2475 | static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz, | |
2476 | struct mlx5e_redirect_rqt_param rrp, void *rqtc) | |
2477 | { | |
2478 | int i; | |
2479 | ||
2480 | for (i = 0; i < sz; i++) { | |
2481 | u32 rqn; | |
2482 | ||
2483 | if (rrp.is_rss) { | |
2484 | int ix = i; | |
2485 | ||
2486 | if (rrp.rss.hfunc == ETH_RSS_HASH_XOR) | |
2487 | ix = mlx5e_bits_invert(i, ilog2(sz)); | |
2488 | ||
6a9764ef | 2489 | ix = priv->channels.params.indirection_rqt[ix]; |
a5f97fee SM |
2490 | rqn = rrp.rss.channels->c[ix]->rq.rqn; |
2491 | } else { | |
2492 | rqn = rrp.rqn; | |
2493 | } | |
2494 | MLX5_SET(rqtc, rqtc, rq_num[i], rqn); | |
2495 | } | |
2496 | } | |
2497 | ||
2498 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, | |
2499 | struct mlx5e_redirect_rqt_param rrp) | |
5c50368f AS |
2500 | { |
2501 | struct mlx5_core_dev *mdev = priv->mdev; | |
5c50368f AS |
2502 | void *rqtc; |
2503 | int inlen; | |
1da36696 | 2504 | u32 *in; |
5c50368f AS |
2505 | int err; |
2506 | ||
5c50368f | 2507 | inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; |
1b9a07ee | 2508 | in = kvzalloc(inlen, GFP_KERNEL); |
5c50368f AS |
2509 | if (!in) |
2510 | return -ENOMEM; | |
2511 | ||
2512 | rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); | |
2513 | ||
2514 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
5c50368f | 2515 | MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); |
a5f97fee | 2516 | mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc); |
1da36696 | 2517 | err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen); |
5c50368f AS |
2518 | |
2519 | kvfree(in); | |
5c50368f AS |
2520 | return err; |
2521 | } | |
2522 | ||
a5f97fee SM |
2523 | static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix, |
2524 | struct mlx5e_redirect_rqt_param rrp) | |
2525 | { | |
2526 | if (!rrp.is_rss) | |
2527 | return rrp.rqn; | |
2528 | ||
2529 | if (ix >= rrp.rss.channels->num) | |
2530 | return priv->drop_rq.rqn; | |
2531 | ||
2532 | return rrp.rss.channels->c[ix]->rq.rqn; | |
2533 | } | |
2534 | ||
2535 | static void mlx5e_redirect_rqts(struct mlx5e_priv *priv, | |
2536 | struct mlx5e_redirect_rqt_param rrp) | |
40ab6a6e | 2537 | { |
1da36696 TT |
2538 | u32 rqtn; |
2539 | int ix; | |
2540 | ||
398f3351 | 2541 | if (priv->indir_rqt.enabled) { |
a5f97fee | 2542 | /* RSS RQ table */ |
398f3351 | 2543 | rqtn = priv->indir_rqt.rqtn; |
a5f97fee | 2544 | mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp); |
398f3351 HHZ |
2545 | } |
2546 | ||
a5f97fee SM |
2547 | for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) { |
2548 | struct mlx5e_redirect_rqt_param direct_rrp = { | |
2549 | .is_rss = false, | |
95632791 AM |
2550 | { |
2551 | .rqn = mlx5e_get_direct_rqn(priv, ix, rrp) | |
2552 | }, | |
a5f97fee SM |
2553 | }; |
2554 | ||
2555 | /* Direct RQ Tables */ | |
398f3351 HHZ |
2556 | if (!priv->direct_tir[ix].rqt.enabled) |
2557 | continue; | |
a5f97fee | 2558 | |
398f3351 | 2559 | rqtn = priv->direct_tir[ix].rqt.rqtn; |
a5f97fee | 2560 | mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp); |
1da36696 | 2561 | } |
40ab6a6e AS |
2562 | } |
2563 | ||
a5f97fee SM |
2564 | static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv, |
2565 | struct mlx5e_channels *chs) | |
2566 | { | |
2567 | struct mlx5e_redirect_rqt_param rrp = { | |
2568 | .is_rss = true, | |
95632791 AM |
2569 | { |
2570 | .rss = { | |
2571 | .channels = chs, | |
2572 | .hfunc = chs->params.rss_hfunc, | |
2573 | } | |
2574 | }, | |
a5f97fee SM |
2575 | }; |
2576 | ||
2577 | mlx5e_redirect_rqts(priv, rrp); | |
2578 | } | |
2579 | ||
2580 | static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv) | |
2581 | { | |
2582 | struct mlx5e_redirect_rqt_param drop_rrp = { | |
2583 | .is_rss = false, | |
95632791 AM |
2584 | { |
2585 | .rqn = priv->drop_rq.rqn, | |
2586 | }, | |
a5f97fee SM |
2587 | }; |
2588 | ||
2589 | mlx5e_redirect_rqts(priv, drop_rrp); | |
2590 | } | |
2591 | ||
6a9764ef | 2592 | static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc) |
5c50368f | 2593 | { |
6a9764ef | 2594 | if (!params->lro_en) |
5c50368f AS |
2595 | return; |
2596 | ||
2597 | #define ROUGH_MAX_L2_L3_HDR_SZ 256 | |
2598 | ||
2599 | MLX5_SET(tirc, tirc, lro_enable_mask, | |
2600 | MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | | |
2601 | MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); | |
2602 | MLX5_SET(tirc, tirc, lro_max_ip_payload_size, | |
6a9764ef SM |
2603 | (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8); |
2604 | MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout); | |
5c50368f AS |
2605 | } |
2606 | ||
6a9764ef SM |
2607 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params, |
2608 | enum mlx5e_traffic_types tt, | |
7b3722fa | 2609 | void *tirc, bool inner) |
bdfc028d | 2610 | { |
7b3722fa GP |
2611 | void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) : |
2612 | MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | |
a100ff3e GP |
2613 | |
2614 | #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ | |
2615 | MLX5_HASH_FIELD_SEL_DST_IP) | |
2616 | ||
2617 | #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\ | |
2618 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
2619 | MLX5_HASH_FIELD_SEL_L4_SPORT |\ | |
2620 | MLX5_HASH_FIELD_SEL_L4_DPORT) | |
2621 | ||
2622 | #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ | |
2623 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
2624 | MLX5_HASH_FIELD_SEL_IPSEC_SPI) | |
2625 | ||
6a9764ef SM |
2626 | MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc)); |
2627 | if (params->rss_hfunc == ETH_RSS_HASH_TOP) { | |
bdfc028d TT |
2628 | void *rss_key = MLX5_ADDR_OF(tirc, tirc, |
2629 | rx_hash_toeplitz_key); | |
2630 | size_t len = MLX5_FLD_SZ_BYTES(tirc, | |
2631 | rx_hash_toeplitz_key); | |
2632 | ||
2633 | MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); | |
6a9764ef | 2634 | memcpy(rss_key, params->toeplitz_hash_key, len); |
bdfc028d | 2635 | } |
a100ff3e GP |
2636 | |
2637 | switch (tt) { | |
2638 | case MLX5E_TT_IPV4_TCP: | |
2639 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2640 | MLX5_L3_PROT_TYPE_IPV4); | |
2641 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2642 | MLX5_L4_PROT_TYPE_TCP); | |
2643 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2644 | MLX5_HASH_IP_L4PORTS); | |
2645 | break; | |
2646 | ||
2647 | case MLX5E_TT_IPV6_TCP: | |
2648 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2649 | MLX5_L3_PROT_TYPE_IPV6); | |
2650 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2651 | MLX5_L4_PROT_TYPE_TCP); | |
2652 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2653 | MLX5_HASH_IP_L4PORTS); | |
2654 | break; | |
2655 | ||
2656 | case MLX5E_TT_IPV4_UDP: | |
2657 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2658 | MLX5_L3_PROT_TYPE_IPV4); | |
2659 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2660 | MLX5_L4_PROT_TYPE_UDP); | |
2661 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2662 | MLX5_HASH_IP_L4PORTS); | |
2663 | break; | |
2664 | ||
2665 | case MLX5E_TT_IPV6_UDP: | |
2666 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2667 | MLX5_L3_PROT_TYPE_IPV6); | |
2668 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2669 | MLX5_L4_PROT_TYPE_UDP); | |
2670 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2671 | MLX5_HASH_IP_L4PORTS); | |
2672 | break; | |
2673 | ||
2674 | case MLX5E_TT_IPV4_IPSEC_AH: | |
2675 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2676 | MLX5_L3_PROT_TYPE_IPV4); | |
2677 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2678 | MLX5_HASH_IP_IPSEC_SPI); | |
2679 | break; | |
2680 | ||
2681 | case MLX5E_TT_IPV6_IPSEC_AH: | |
2682 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2683 | MLX5_L3_PROT_TYPE_IPV6); | |
2684 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2685 | MLX5_HASH_IP_IPSEC_SPI); | |
2686 | break; | |
2687 | ||
2688 | case MLX5E_TT_IPV4_IPSEC_ESP: | |
2689 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2690 | MLX5_L3_PROT_TYPE_IPV4); | |
2691 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2692 | MLX5_HASH_IP_IPSEC_SPI); | |
2693 | break; | |
2694 | ||
2695 | case MLX5E_TT_IPV6_IPSEC_ESP: | |
2696 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2697 | MLX5_L3_PROT_TYPE_IPV6); | |
2698 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2699 | MLX5_HASH_IP_IPSEC_SPI); | |
2700 | break; | |
2701 | ||
2702 | case MLX5E_TT_IPV4: | |
2703 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2704 | MLX5_L3_PROT_TYPE_IPV4); | |
2705 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2706 | MLX5_HASH_IP); | |
2707 | break; | |
2708 | ||
2709 | case MLX5E_TT_IPV6: | |
2710 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2711 | MLX5_L3_PROT_TYPE_IPV6); | |
2712 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2713 | MLX5_HASH_IP); | |
2714 | break; | |
2715 | default: | |
2716 | WARN_ONCE(true, "%s: bad traffic type!\n", __func__); | |
2717 | } | |
bdfc028d TT |
2718 | } |
2719 | ||
ab0394fe | 2720 | static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv) |
5c50368f AS |
2721 | { |
2722 | struct mlx5_core_dev *mdev = priv->mdev; | |
2723 | ||
2724 | void *in; | |
2725 | void *tirc; | |
2726 | int inlen; | |
2727 | int err; | |
ab0394fe | 2728 | int tt; |
1da36696 | 2729 | int ix; |
5c50368f AS |
2730 | |
2731 | inlen = MLX5_ST_SZ_BYTES(modify_tir_in); | |
1b9a07ee | 2732 | in = kvzalloc(inlen, GFP_KERNEL); |
5c50368f AS |
2733 | if (!in) |
2734 | return -ENOMEM; | |
2735 | ||
2736 | MLX5_SET(modify_tir_in, in, bitmask.lro, 1); | |
2737 | tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx); | |
2738 | ||
6a9764ef | 2739 | mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); |
5c50368f | 2740 | |
1da36696 | 2741 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { |
724b2aa1 | 2742 | err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, |
1da36696 | 2743 | inlen); |
ab0394fe | 2744 | if (err) |
1da36696 | 2745 | goto free_in; |
ab0394fe | 2746 | } |
5c50368f | 2747 | |
6bfd390b | 2748 | for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) { |
1da36696 TT |
2749 | err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, |
2750 | in, inlen); | |
2751 | if (err) | |
2752 | goto free_in; | |
2753 | } | |
2754 | ||
2755 | free_in: | |
5c50368f AS |
2756 | kvfree(in); |
2757 | ||
2758 | return err; | |
2759 | } | |
2760 | ||
7b3722fa GP |
2761 | static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv, |
2762 | enum mlx5e_traffic_types tt, | |
2763 | u32 *tirc) | |
2764 | { | |
2765 | MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); | |
2766 | ||
2767 | mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); | |
2768 | ||
2769 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | |
2770 | MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn); | |
2771 | MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1); | |
2772 | ||
2773 | mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true); | |
2774 | } | |
2775 | ||
472a1e44 TT |
2776 | static int mlx5e_set_mtu(struct mlx5_core_dev *mdev, |
2777 | struct mlx5e_params *params, u16 mtu) | |
40ab6a6e | 2778 | { |
472a1e44 | 2779 | u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu); |
40ab6a6e AS |
2780 | int err; |
2781 | ||
cd255eff | 2782 | err = mlx5_set_port_mtu(mdev, hw_mtu, 1); |
40ab6a6e AS |
2783 | if (err) |
2784 | return err; | |
2785 | ||
cd255eff SM |
2786 | /* Update vport context MTU */ |
2787 | mlx5_modify_nic_vport_mtu(mdev, hw_mtu); | |
2788 | return 0; | |
2789 | } | |
40ab6a6e | 2790 | |
472a1e44 TT |
2791 | static void mlx5e_query_mtu(struct mlx5_core_dev *mdev, |
2792 | struct mlx5e_params *params, u16 *mtu) | |
cd255eff | 2793 | { |
cd255eff SM |
2794 | u16 hw_mtu = 0; |
2795 | int err; | |
40ab6a6e | 2796 | |
cd255eff SM |
2797 | err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu); |
2798 | if (err || !hw_mtu) /* fallback to port oper mtu */ | |
2799 | mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1); | |
2800 | ||
472a1e44 | 2801 | *mtu = MLX5E_HW2SW_MTU(params, hw_mtu); |
cd255eff SM |
2802 | } |
2803 | ||
2e20a151 | 2804 | static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv) |
cd255eff | 2805 | { |
472a1e44 | 2806 | struct mlx5e_params *params = &priv->channels.params; |
2e20a151 | 2807 | struct net_device *netdev = priv->netdev; |
472a1e44 | 2808 | struct mlx5_core_dev *mdev = priv->mdev; |
cd255eff SM |
2809 | u16 mtu; |
2810 | int err; | |
2811 | ||
472a1e44 | 2812 | err = mlx5e_set_mtu(mdev, params, params->sw_mtu); |
cd255eff SM |
2813 | if (err) |
2814 | return err; | |
40ab6a6e | 2815 | |
472a1e44 TT |
2816 | mlx5e_query_mtu(mdev, params, &mtu); |
2817 | if (mtu != params->sw_mtu) | |
cd255eff | 2818 | netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n", |
472a1e44 | 2819 | __func__, mtu, params->sw_mtu); |
40ab6a6e | 2820 | |
472a1e44 | 2821 | params->sw_mtu = mtu; |
40ab6a6e AS |
2822 | return 0; |
2823 | } | |
2824 | ||
08fb1dac SM |
2825 | static void mlx5e_netdev_set_tcs(struct net_device *netdev) |
2826 | { | |
2827 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
6a9764ef SM |
2828 | int nch = priv->channels.params.num_channels; |
2829 | int ntc = priv->channels.params.num_tc; | |
08fb1dac SM |
2830 | int tc; |
2831 | ||
2832 | netdev_reset_tc(netdev); | |
2833 | ||
2834 | if (ntc == 1) | |
2835 | return; | |
2836 | ||
2837 | netdev_set_num_tc(netdev, ntc); | |
2838 | ||
7ccdd084 RS |
2839 | /* Map netdev TCs to offset 0 |
2840 | * We have our own UP to TXQ mapping for QoS | |
2841 | */ | |
08fb1dac | 2842 | for (tc = 0; tc < ntc; tc++) |
7ccdd084 | 2843 | netdev_set_tc_queue(netdev, tc, nch, 0); |
08fb1dac SM |
2844 | } |
2845 | ||
8bfaf07f | 2846 | static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv) |
acc6c595 | 2847 | { |
8bfaf07f | 2848 | int max_nch = priv->profile->max_nch(priv->mdev); |
acc6c595 SM |
2849 | int i, tc; |
2850 | ||
8bfaf07f | 2851 | for (i = 0; i < max_nch; i++) |
acc6c595 | 2852 | for (tc = 0; tc < priv->profile->max_tc; tc++) |
8bfaf07f EBE |
2853 | priv->channel_tc2txq[i][tc] = i + tc * max_nch; |
2854 | } | |
2855 | ||
2856 | static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv) | |
2857 | { | |
2858 | struct mlx5e_channel *c; | |
2859 | struct mlx5e_txqsq *sq; | |
2860 | int i, tc; | |
acc6c595 SM |
2861 | |
2862 | for (i = 0; i < priv->channels.num; i++) { | |
2863 | c = priv->channels.c[i]; | |
2864 | for (tc = 0; tc < c->num_tc; tc++) { | |
2865 | sq = &c->sq[tc]; | |
2866 | priv->txq2sq[sq->txq_ix] = sq; | |
2867 | } | |
2868 | } | |
2869 | } | |
2870 | ||
603f4a45 | 2871 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv) |
acc6c595 | 2872 | { |
9008ae07 SM |
2873 | int num_txqs = priv->channels.num * priv->channels.params.num_tc; |
2874 | struct net_device *netdev = priv->netdev; | |
2875 | ||
2876 | mlx5e_netdev_set_tcs(netdev); | |
053ee0a7 TR |
2877 | netif_set_real_num_tx_queues(netdev, num_txqs); |
2878 | netif_set_real_num_rx_queues(netdev, priv->channels.num); | |
9008ae07 | 2879 | |
8bfaf07f | 2880 | mlx5e_build_tx2sq_maps(priv); |
acc6c595 SM |
2881 | mlx5e_activate_channels(&priv->channels); |
2882 | netif_tx_start_all_queues(priv->netdev); | |
9008ae07 | 2883 | |
733d3e54 | 2884 | if (MLX5_ESWITCH_MANAGER(priv->mdev)) |
9008ae07 SM |
2885 | mlx5e_add_sqs_fwd_rules(priv); |
2886 | ||
acc6c595 | 2887 | mlx5e_wait_channels_min_rx_wqes(&priv->channels); |
9008ae07 | 2888 | mlx5e_redirect_rqts_to_channels(priv, &priv->channels); |
acc6c595 SM |
2889 | } |
2890 | ||
603f4a45 | 2891 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv) |
acc6c595 | 2892 | { |
9008ae07 SM |
2893 | mlx5e_redirect_rqts_to_drop(priv); |
2894 | ||
733d3e54 | 2895 | if (MLX5_ESWITCH_MANAGER(priv->mdev)) |
9008ae07 SM |
2896 | mlx5e_remove_sqs_fwd_rules(priv); |
2897 | ||
acc6c595 SM |
2898 | /* FIXME: This is a W/A only for tx timeout watch dog false alarm when |
2899 | * polling for inactive tx queues. | |
2900 | */ | |
2901 | netif_tx_stop_all_queues(priv->netdev); | |
2902 | netif_tx_disable(priv->netdev); | |
2903 | mlx5e_deactivate_channels(&priv->channels); | |
2904 | } | |
2905 | ||
55c2503d | 2906 | void mlx5e_switch_priv_channels(struct mlx5e_priv *priv, |
2e20a151 SM |
2907 | struct mlx5e_channels *new_chs, |
2908 | mlx5e_fp_hw_modify hw_modify) | |
55c2503d SM |
2909 | { |
2910 | struct net_device *netdev = priv->netdev; | |
2911 | int new_num_txqs; | |
7ca42c80 | 2912 | int carrier_ok; |
55c2503d SM |
2913 | new_num_txqs = new_chs->num * new_chs->params.num_tc; |
2914 | ||
7ca42c80 | 2915 | carrier_ok = netif_carrier_ok(netdev); |
55c2503d SM |
2916 | netif_carrier_off(netdev); |
2917 | ||
2918 | if (new_num_txqs < netdev->real_num_tx_queues) | |
2919 | netif_set_real_num_tx_queues(netdev, new_num_txqs); | |
2920 | ||
2921 | mlx5e_deactivate_priv_channels(priv); | |
2922 | mlx5e_close_channels(&priv->channels); | |
2923 | ||
2924 | priv->channels = *new_chs; | |
2925 | ||
2e20a151 SM |
2926 | /* New channels are ready to roll, modify HW settings if needed */ |
2927 | if (hw_modify) | |
2928 | hw_modify(priv); | |
2929 | ||
55c2503d SM |
2930 | mlx5e_refresh_tirs(priv, false); |
2931 | mlx5e_activate_priv_channels(priv); | |
2932 | ||
7ca42c80 ES |
2933 | /* return carrier back if needed */ |
2934 | if (carrier_ok) | |
2935 | netif_carrier_on(netdev); | |
55c2503d SM |
2936 | } |
2937 | ||
237f258c | 2938 | void mlx5e_timestamp_init(struct mlx5e_priv *priv) |
7c39afb3 FD |
2939 | { |
2940 | priv->tstamp.tx_type = HWTSTAMP_TX_OFF; | |
2941 | priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE; | |
2942 | } | |
2943 | ||
40ab6a6e AS |
2944 | int mlx5e_open_locked(struct net_device *netdev) |
2945 | { | |
2946 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
40ab6a6e AS |
2947 | int err; |
2948 | ||
2949 | set_bit(MLX5E_STATE_OPENED, &priv->state); | |
2950 | ||
ff9c852f | 2951 | err = mlx5e_open_channels(priv, &priv->channels); |
acc6c595 | 2952 | if (err) |
343b29f3 | 2953 | goto err_clear_state_opened_flag; |
40ab6a6e | 2954 | |
b676f653 | 2955 | mlx5e_refresh_tirs(priv, false); |
acc6c595 | 2956 | mlx5e_activate_priv_channels(priv); |
7ca42c80 ES |
2957 | if (priv->profile->update_carrier) |
2958 | priv->profile->update_carrier(priv); | |
be4891af | 2959 | |
cb67b832 HHZ |
2960 | if (priv->profile->update_stats) |
2961 | queue_delayed_work(priv->wq, &priv->update_stats_work, 0); | |
40ab6a6e | 2962 | |
9b37b07f | 2963 | return 0; |
343b29f3 AS |
2964 | |
2965 | err_clear_state_opened_flag: | |
2966 | clear_bit(MLX5E_STATE_OPENED, &priv->state); | |
2967 | return err; | |
40ab6a6e AS |
2968 | } |
2969 | ||
cb67b832 | 2970 | int mlx5e_open(struct net_device *netdev) |
40ab6a6e AS |
2971 | { |
2972 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2973 | int err; | |
2974 | ||
2975 | mutex_lock(&priv->state_lock); | |
2976 | err = mlx5e_open_locked(netdev); | |
63bfd399 EBE |
2977 | if (!err) |
2978 | mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP); | |
40ab6a6e AS |
2979 | mutex_unlock(&priv->state_lock); |
2980 | ||
358aa5ce | 2981 | if (mlx5_vxlan_allowed(priv->mdev->vxlan)) |
a117f73d SK |
2982 | udp_tunnel_get_rx_info(netdev); |
2983 | ||
40ab6a6e AS |
2984 | return err; |
2985 | } | |
2986 | ||
2987 | int mlx5e_close_locked(struct net_device *netdev) | |
2988 | { | |
2989 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2990 | ||
a1985740 AS |
2991 | /* May already be CLOSED in case a previous configuration operation |
2992 | * (e.g RX/TX queue size change) that involves close&open failed. | |
2993 | */ | |
2994 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
2995 | return 0; | |
2996 | ||
40ab6a6e AS |
2997 | clear_bit(MLX5E_STATE_OPENED, &priv->state); |
2998 | ||
40ab6a6e | 2999 | netif_carrier_off(priv->netdev); |
acc6c595 SM |
3000 | mlx5e_deactivate_priv_channels(priv); |
3001 | mlx5e_close_channels(&priv->channels); | |
40ab6a6e AS |
3002 | |
3003 | return 0; | |
3004 | } | |
3005 | ||
cb67b832 | 3006 | int mlx5e_close(struct net_device *netdev) |
40ab6a6e AS |
3007 | { |
3008 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3009 | int err; | |
3010 | ||
26e59d80 MHY |
3011 | if (!netif_device_present(netdev)) |
3012 | return -ENODEV; | |
3013 | ||
40ab6a6e | 3014 | mutex_lock(&priv->state_lock); |
63bfd399 | 3015 | mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN); |
40ab6a6e AS |
3016 | err = mlx5e_close_locked(netdev); |
3017 | mutex_unlock(&priv->state_lock); | |
3018 | ||
3019 | return err; | |
3020 | } | |
3021 | ||
a43b25da | 3022 | static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev, |
3b77235b SM |
3023 | struct mlx5e_rq *rq, |
3024 | struct mlx5e_rq_param *param) | |
40ab6a6e | 3025 | { |
40ab6a6e AS |
3026 | void *rqc = param->rqc; |
3027 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
3028 | int err; | |
3029 | ||
3030 | param->wq.db_numa_node = param->wq.buf_numa_node; | |
3031 | ||
99cbfa93 TT |
3032 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq, |
3033 | &rq->wq_ctrl); | |
40ab6a6e AS |
3034 | if (err) |
3035 | return err; | |
3036 | ||
0ddf5432 JDB |
3037 | /* Mark as unused given "Drop-RQ" packets never reach XDP */ |
3038 | xdp_rxq_info_unused(&rq->xdp_rxq); | |
3039 | ||
a43b25da | 3040 | rq->mdev = mdev; |
40ab6a6e AS |
3041 | |
3042 | return 0; | |
3043 | } | |
3044 | ||
a43b25da | 3045 | static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev, |
3b77235b SM |
3046 | struct mlx5e_cq *cq, |
3047 | struct mlx5e_cq_param *param) | |
40ab6a6e | 3048 | { |
2f0db879 GP |
3049 | param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev); |
3050 | param->wq.db_numa_node = dev_to_node(&mdev->pdev->dev); | |
3051 | ||
95b6c6a5 | 3052 | return mlx5e_alloc_cq_common(mdev, param, cq); |
40ab6a6e AS |
3053 | } |
3054 | ||
1462e48d RD |
3055 | int mlx5e_open_drop_rq(struct mlx5e_priv *priv, |
3056 | struct mlx5e_rq *drop_rq) | |
40ab6a6e | 3057 | { |
7cbaf9a3 | 3058 | struct mlx5_core_dev *mdev = priv->mdev; |
a43b25da SM |
3059 | struct mlx5e_cq_param cq_param = {}; |
3060 | struct mlx5e_rq_param rq_param = {}; | |
3061 | struct mlx5e_cq *cq = &drop_rq->cq; | |
40ab6a6e AS |
3062 | int err; |
3063 | ||
7cbaf9a3 | 3064 | mlx5e_build_drop_rq_param(priv, &rq_param); |
40ab6a6e | 3065 | |
a43b25da | 3066 | err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param); |
40ab6a6e AS |
3067 | if (err) |
3068 | return err; | |
3069 | ||
3b77235b | 3070 | err = mlx5e_create_cq(cq, &cq_param); |
40ab6a6e | 3071 | if (err) |
3b77235b | 3072 | goto err_free_cq; |
40ab6a6e | 3073 | |
a43b25da | 3074 | err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param); |
40ab6a6e | 3075 | if (err) |
3b77235b | 3076 | goto err_destroy_cq; |
40ab6a6e | 3077 | |
a43b25da | 3078 | err = mlx5e_create_rq(drop_rq, &rq_param); |
40ab6a6e | 3079 | if (err) |
3b77235b | 3080 | goto err_free_rq; |
40ab6a6e | 3081 | |
7cbaf9a3 MS |
3082 | err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); |
3083 | if (err) | |
3084 | mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err); | |
3085 | ||
40ab6a6e AS |
3086 | return 0; |
3087 | ||
3b77235b | 3088 | err_free_rq: |
a43b25da | 3089 | mlx5e_free_rq(drop_rq); |
40ab6a6e AS |
3090 | |
3091 | err_destroy_cq: | |
a43b25da | 3092 | mlx5e_destroy_cq(cq); |
40ab6a6e | 3093 | |
3b77235b | 3094 | err_free_cq: |
a43b25da | 3095 | mlx5e_free_cq(cq); |
3b77235b | 3096 | |
40ab6a6e AS |
3097 | return err; |
3098 | } | |
3099 | ||
1462e48d | 3100 | void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq) |
40ab6a6e | 3101 | { |
a43b25da SM |
3102 | mlx5e_destroy_rq(drop_rq); |
3103 | mlx5e_free_rq(drop_rq); | |
3104 | mlx5e_destroy_cq(&drop_rq->cq); | |
3105 | mlx5e_free_cq(&drop_rq->cq); | |
40ab6a6e AS |
3106 | } |
3107 | ||
5426a0b2 SM |
3108 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc, |
3109 | u32 underlay_qpn, u32 *tisn) | |
40ab6a6e | 3110 | { |
c4f287c4 | 3111 | u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; |
40ab6a6e AS |
3112 | void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); |
3113 | ||
08fb1dac | 3114 | MLX5_SET(tisc, tisc, prio, tc << 1); |
5426a0b2 | 3115 | MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn); |
b50d292b | 3116 | MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn); |
db60b802 AH |
3117 | |
3118 | if (mlx5_lag_is_lacp_owner(mdev)) | |
3119 | MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1); | |
3120 | ||
5426a0b2 | 3121 | return mlx5_core_create_tis(mdev, in, sizeof(in), tisn); |
40ab6a6e AS |
3122 | } |
3123 | ||
5426a0b2 | 3124 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn) |
40ab6a6e | 3125 | { |
5426a0b2 | 3126 | mlx5_core_destroy_tis(mdev, tisn); |
40ab6a6e AS |
3127 | } |
3128 | ||
cb67b832 | 3129 | int mlx5e_create_tises(struct mlx5e_priv *priv) |
40ab6a6e AS |
3130 | { |
3131 | int err; | |
3132 | int tc; | |
3133 | ||
6bfd390b | 3134 | for (tc = 0; tc < priv->profile->max_tc; tc++) { |
5426a0b2 | 3135 | err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]); |
40ab6a6e AS |
3136 | if (err) |
3137 | goto err_close_tises; | |
3138 | } | |
3139 | ||
3140 | return 0; | |
3141 | ||
3142 | err_close_tises: | |
3143 | for (tc--; tc >= 0; tc--) | |
5426a0b2 | 3144 | mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]); |
40ab6a6e AS |
3145 | |
3146 | return err; | |
3147 | } | |
3148 | ||
cb67b832 | 3149 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv) |
40ab6a6e AS |
3150 | { |
3151 | int tc; | |
3152 | ||
6bfd390b | 3153 | for (tc = 0; tc < priv->profile->max_tc; tc++) |
5426a0b2 | 3154 | mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]); |
40ab6a6e AS |
3155 | } |
3156 | ||
6a9764ef SM |
3157 | static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, |
3158 | enum mlx5e_traffic_types tt, | |
3159 | u32 *tirc) | |
f62b8bb8 | 3160 | { |
b50d292b | 3161 | MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); |
3191e05f | 3162 | |
6a9764ef | 3163 | mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); |
f62b8bb8 | 3164 | |
4cbeaff5 | 3165 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); |
398f3351 | 3166 | MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn); |
7b3722fa | 3167 | mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false); |
f62b8bb8 AV |
3168 | } |
3169 | ||
6a9764ef | 3170 | static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc) |
f62b8bb8 | 3171 | { |
b50d292b | 3172 | MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); |
1da36696 | 3173 | |
6a9764ef | 3174 | mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); |
1da36696 TT |
3175 | |
3176 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | |
3177 | MLX5_SET(tirc, tirc, indirect_table, rqtn); | |
3178 | MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8); | |
3179 | } | |
3180 | ||
46dc933c | 3181 | int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc) |
1da36696 | 3182 | { |
724b2aa1 | 3183 | struct mlx5e_tir *tir; |
f62b8bb8 AV |
3184 | void *tirc; |
3185 | int inlen; | |
7b3722fa | 3186 | int i = 0; |
f62b8bb8 | 3187 | int err; |
1da36696 | 3188 | u32 *in; |
1da36696 | 3189 | int tt; |
f62b8bb8 AV |
3190 | |
3191 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
1b9a07ee | 3192 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
3193 | if (!in) |
3194 | return -ENOMEM; | |
3195 | ||
1da36696 TT |
3196 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { |
3197 | memset(in, 0, inlen); | |
724b2aa1 | 3198 | tir = &priv->indir_tir[tt]; |
1da36696 | 3199 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); |
6a9764ef | 3200 | mlx5e_build_indir_tir_ctx(priv, tt, tirc); |
724b2aa1 | 3201 | err = mlx5e_create_tir(priv->mdev, tir, in, inlen); |
7b3722fa GP |
3202 | if (err) { |
3203 | mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err); | |
3204 | goto err_destroy_inner_tirs; | |
3205 | } | |
f62b8bb8 AV |
3206 | } |
3207 | ||
46dc933c | 3208 | if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev)) |
7b3722fa GP |
3209 | goto out; |
3210 | ||
3211 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) { | |
3212 | memset(in, 0, inlen); | |
3213 | tir = &priv->inner_indir_tir[i]; | |
3214 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
3215 | mlx5e_build_inner_indir_tir_ctx(priv, i, tirc); | |
3216 | err = mlx5e_create_tir(priv->mdev, tir, in, inlen); | |
3217 | if (err) { | |
3218 | mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err); | |
3219 | goto err_destroy_inner_tirs; | |
3220 | } | |
3221 | } | |
3222 | ||
3223 | out: | |
6bfd390b HHZ |
3224 | kvfree(in); |
3225 | ||
3226 | return 0; | |
3227 | ||
7b3722fa GP |
3228 | err_destroy_inner_tirs: |
3229 | for (i--; i >= 0; i--) | |
3230 | mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]); | |
3231 | ||
6bfd390b HHZ |
3232 | for (tt--; tt >= 0; tt--) |
3233 | mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]); | |
3234 | ||
3235 | kvfree(in); | |
3236 | ||
3237 | return err; | |
3238 | } | |
3239 | ||
cb67b832 | 3240 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv) |
6bfd390b HHZ |
3241 | { |
3242 | int nch = priv->profile->max_nch(priv->mdev); | |
3243 | struct mlx5e_tir *tir; | |
3244 | void *tirc; | |
3245 | int inlen; | |
3246 | int err; | |
3247 | u32 *in; | |
3248 | int ix; | |
3249 | ||
3250 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
1b9a07ee | 3251 | in = kvzalloc(inlen, GFP_KERNEL); |
6bfd390b HHZ |
3252 | if (!in) |
3253 | return -ENOMEM; | |
3254 | ||
1da36696 TT |
3255 | for (ix = 0; ix < nch; ix++) { |
3256 | memset(in, 0, inlen); | |
724b2aa1 | 3257 | tir = &priv->direct_tir[ix]; |
1da36696 | 3258 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); |
6a9764ef | 3259 | mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc); |
724b2aa1 | 3260 | err = mlx5e_create_tir(priv->mdev, tir, in, inlen); |
1da36696 TT |
3261 | if (err) |
3262 | goto err_destroy_ch_tirs; | |
3263 | } | |
3264 | ||
3265 | kvfree(in); | |
3266 | ||
f62b8bb8 AV |
3267 | return 0; |
3268 | ||
1da36696 | 3269 | err_destroy_ch_tirs: |
8f493ffd | 3270 | mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err); |
1da36696 | 3271 | for (ix--; ix >= 0; ix--) |
724b2aa1 | 3272 | mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]); |
1da36696 | 3273 | |
1da36696 | 3274 | kvfree(in); |
f62b8bb8 AV |
3275 | |
3276 | return err; | |
3277 | } | |
3278 | ||
46dc933c | 3279 | void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc) |
f62b8bb8 AV |
3280 | { |
3281 | int i; | |
3282 | ||
1da36696 | 3283 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) |
724b2aa1 | 3284 | mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]); |
7b3722fa | 3285 | |
46dc933c | 3286 | if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev)) |
7b3722fa GP |
3287 | return; |
3288 | ||
3289 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) | |
3290 | mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]); | |
f62b8bb8 AV |
3291 | } |
3292 | ||
cb67b832 | 3293 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv) |
6bfd390b HHZ |
3294 | { |
3295 | int nch = priv->profile->max_nch(priv->mdev); | |
3296 | int i; | |
3297 | ||
3298 | for (i = 0; i < nch; i++) | |
3299 | mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]); | |
3300 | } | |
3301 | ||
102722fc GE |
3302 | static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable) |
3303 | { | |
3304 | int err = 0; | |
3305 | int i; | |
3306 | ||
3307 | for (i = 0; i < chs->num; i++) { | |
3308 | err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable); | |
3309 | if (err) | |
3310 | return err; | |
3311 | } | |
3312 | ||
3313 | return 0; | |
3314 | } | |
3315 | ||
f6d96a20 | 3316 | static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd) |
36350114 GP |
3317 | { |
3318 | int err = 0; | |
3319 | int i; | |
3320 | ||
ff9c852f SM |
3321 | for (i = 0; i < chs->num; i++) { |
3322 | err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd); | |
36350114 GP |
3323 | if (err) |
3324 | return err; | |
3325 | } | |
3326 | ||
3327 | return 0; | |
3328 | } | |
3329 | ||
0cf0f6d3 JP |
3330 | static int mlx5e_setup_tc_mqprio(struct net_device *netdev, |
3331 | struct tc_mqprio_qopt *mqprio) | |
08fb1dac SM |
3332 | { |
3333 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
6f9485af | 3334 | struct mlx5e_channels new_channels = {}; |
0cf0f6d3 | 3335 | u8 tc = mqprio->num_tc; |
08fb1dac SM |
3336 | int err = 0; |
3337 | ||
0cf0f6d3 JP |
3338 | mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; |
3339 | ||
08fb1dac SM |
3340 | if (tc && tc != MLX5E_MAX_NUM_TC) |
3341 | return -EINVAL; | |
3342 | ||
3343 | mutex_lock(&priv->state_lock); | |
3344 | ||
6f9485af SM |
3345 | new_channels.params = priv->channels.params; |
3346 | new_channels.params.num_tc = tc ? tc : 1; | |
08fb1dac | 3347 | |
20b6a1c7 | 3348 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { |
6f9485af SM |
3349 | priv->channels.params = new_channels.params; |
3350 | goto out; | |
3351 | } | |
08fb1dac | 3352 | |
6f9485af SM |
3353 | err = mlx5e_open_channels(priv, &new_channels); |
3354 | if (err) | |
3355 | goto out; | |
08fb1dac | 3356 | |
05909bab EBE |
3357 | priv->max_opened_tc = max_t(u8, priv->max_opened_tc, |
3358 | new_channels.params.num_tc); | |
2e20a151 | 3359 | mlx5e_switch_priv_channels(priv, &new_channels, NULL); |
6f9485af | 3360 | out: |
08fb1dac | 3361 | mutex_unlock(&priv->state_lock); |
08fb1dac SM |
3362 | return err; |
3363 | } | |
3364 | ||
e80541ec | 3365 | #ifdef CONFIG_MLX5_ESWITCH |
d6c862ba | 3366 | static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv, |
60bd4af8 OG |
3367 | struct tc_cls_flower_offload *cls_flower, |
3368 | int flags) | |
08fb1dac | 3369 | { |
0cf0f6d3 JP |
3370 | switch (cls_flower->command) { |
3371 | case TC_CLSFLOWER_REPLACE: | |
60bd4af8 | 3372 | return mlx5e_configure_flower(priv, cls_flower, flags); |
0cf0f6d3 | 3373 | case TC_CLSFLOWER_DESTROY: |
60bd4af8 | 3374 | return mlx5e_delete_flower(priv, cls_flower, flags); |
0cf0f6d3 | 3375 | case TC_CLSFLOWER_STATS: |
60bd4af8 | 3376 | return mlx5e_stats_flower(priv, cls_flower, flags); |
0cf0f6d3 | 3377 | default: |
a5fcf8a6 | 3378 | return -EOPNOTSUPP; |
0cf0f6d3 JP |
3379 | } |
3380 | } | |
d6c862ba | 3381 | |
60bd4af8 OG |
3382 | static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, |
3383 | void *cb_priv) | |
d6c862ba JP |
3384 | { |
3385 | struct mlx5e_priv *priv = cb_priv; | |
3386 | ||
9ab88e83 | 3387 | if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data)) |
44ae12a7 JP |
3388 | return -EOPNOTSUPP; |
3389 | ||
d6c862ba JP |
3390 | switch (type) { |
3391 | case TC_SETUP_CLSFLOWER: | |
60bd4af8 | 3392 | return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS); |
d6c862ba JP |
3393 | default: |
3394 | return -EOPNOTSUPP; | |
3395 | } | |
3396 | } | |
3397 | ||
3398 | static int mlx5e_setup_tc_block(struct net_device *dev, | |
3399 | struct tc_block_offload *f) | |
3400 | { | |
3401 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3402 | ||
3403 | if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) | |
3404 | return -EOPNOTSUPP; | |
3405 | ||
3406 | switch (f->command) { | |
3407 | case TC_BLOCK_BIND: | |
3408 | return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb, | |
60513bd8 | 3409 | priv, priv, f->extack); |
d6c862ba JP |
3410 | case TC_BLOCK_UNBIND: |
3411 | tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb, | |
3412 | priv); | |
3413 | return 0; | |
3414 | default: | |
3415 | return -EOPNOTSUPP; | |
3416 | } | |
3417 | } | |
e80541ec | 3418 | #endif |
a5fcf8a6 | 3419 | |
9afe9a53 OG |
3420 | static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type, |
3421 | void *type_data) | |
0cf0f6d3 | 3422 | { |
2572ac53 | 3423 | switch (type) { |
fde6af47 | 3424 | #ifdef CONFIG_MLX5_ESWITCH |
d6c862ba JP |
3425 | case TC_SETUP_BLOCK: |
3426 | return mlx5e_setup_tc_block(dev, type_data); | |
fde6af47 | 3427 | #endif |
575ed7d3 | 3428 | case TC_SETUP_QDISC_MQPRIO: |
de4784ca | 3429 | return mlx5e_setup_tc_mqprio(dev, type_data); |
e8f887ac AV |
3430 | default: |
3431 | return -EOPNOTSUPP; | |
3432 | } | |
08fb1dac SM |
3433 | } |
3434 | ||
bc1f4470 | 3435 | static void |
f62b8bb8 AV |
3436 | mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) |
3437 | { | |
3438 | struct mlx5e_priv *priv = netdev_priv(dev); | |
9218b44d | 3439 | struct mlx5e_sw_stats *sstats = &priv->stats.sw; |
f62b8bb8 | 3440 | struct mlx5e_vport_stats *vstats = &priv->stats.vport; |
269e6b3a | 3441 | struct mlx5e_pport_stats *pstats = &priv->stats.pport; |
f62b8bb8 | 3442 | |
ed56c519 SM |
3443 | /* update HW stats in background for next time */ |
3444 | queue_delayed_work(priv->wq, &priv->update_stats_work, 0); | |
3445 | ||
370bad0f OG |
3446 | if (mlx5e_is_uplink_rep(priv)) { |
3447 | stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok); | |
3448 | stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok); | |
3449 | stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok); | |
3450 | stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok); | |
3451 | } else { | |
868a01a2 | 3452 | mlx5e_grp_sw_update_stats(priv); |
370bad0f OG |
3453 | stats->rx_packets = sstats->rx_packets; |
3454 | stats->rx_bytes = sstats->rx_bytes; | |
3455 | stats->tx_packets = sstats->tx_packets; | |
3456 | stats->tx_bytes = sstats->tx_bytes; | |
3457 | stats->tx_dropped = sstats->tx_queue_dropped; | |
3458 | } | |
269e6b3a GP |
3459 | |
3460 | stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer; | |
269e6b3a GP |
3461 | |
3462 | stats->rx_length_errors = | |
9218b44d GP |
3463 | PPORT_802_3_GET(pstats, a_in_range_length_errors) + |
3464 | PPORT_802_3_GET(pstats, a_out_of_range_length_field) + | |
3465 | PPORT_802_3_GET(pstats, a_frame_too_long_errors); | |
269e6b3a | 3466 | stats->rx_crc_errors = |
9218b44d GP |
3467 | PPORT_802_3_GET(pstats, a_frame_check_sequence_errors); |
3468 | stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors); | |
3469 | stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards); | |
269e6b3a GP |
3470 | stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + |
3471 | stats->rx_frame_errors; | |
3472 | stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors; | |
3473 | ||
3474 | /* vport multicast also counts packets that are dropped due to steering | |
3475 | * or rx out of buffer | |
3476 | */ | |
9218b44d GP |
3477 | stats->multicast = |
3478 | VPORT_COUNTER_GET(vstats, received_eth_multicast.packets); | |
f62b8bb8 AV |
3479 | } |
3480 | ||
3481 | static void mlx5e_set_rx_mode(struct net_device *dev) | |
3482 | { | |
3483 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3484 | ||
7bb29755 | 3485 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
3486 | } |
3487 | ||
3488 | static int mlx5e_set_mac(struct net_device *netdev, void *addr) | |
3489 | { | |
3490 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3491 | struct sockaddr *saddr = addr; | |
3492 | ||
3493 | if (!is_valid_ether_addr(saddr->sa_data)) | |
3494 | return -EADDRNOTAVAIL; | |
3495 | ||
3496 | netif_addr_lock_bh(netdev); | |
3497 | ether_addr_copy(netdev->dev_addr, saddr->sa_data); | |
3498 | netif_addr_unlock_bh(netdev); | |
3499 | ||
7bb29755 | 3500 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
3501 | |
3502 | return 0; | |
3503 | } | |
3504 | ||
75b81ce7 | 3505 | #define MLX5E_SET_FEATURE(features, feature, enable) \ |
0e405443 GP |
3506 | do { \ |
3507 | if (enable) \ | |
75b81ce7 | 3508 | *features |= feature; \ |
0e405443 | 3509 | else \ |
75b81ce7 | 3510 | *features &= ~feature; \ |
0e405443 GP |
3511 | } while (0) |
3512 | ||
3513 | typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable); | |
3514 | ||
3515 | static int set_feature_lro(struct net_device *netdev, bool enable) | |
f62b8bb8 AV |
3516 | { |
3517 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
619a8f2a | 3518 | struct mlx5_core_dev *mdev = priv->mdev; |
2e20a151 | 3519 | struct mlx5e_channels new_channels = {}; |
619a8f2a | 3520 | struct mlx5e_params *old_params; |
2e20a151 SM |
3521 | int err = 0; |
3522 | bool reset; | |
f62b8bb8 AV |
3523 | |
3524 | mutex_lock(&priv->state_lock); | |
f62b8bb8 | 3525 | |
619a8f2a | 3526 | old_params = &priv->channels.params; |
6c3a823e TT |
3527 | if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) { |
3528 | netdev_warn(netdev, "can't set LRO with legacy RQ\n"); | |
3529 | err = -EINVAL; | |
3530 | goto out; | |
3531 | } | |
3532 | ||
619a8f2a | 3533 | reset = test_bit(MLX5E_STATE_OPENED, &priv->state); |
98e81b0a | 3534 | |
619a8f2a | 3535 | new_channels.params = *old_params; |
2e20a151 SM |
3536 | new_channels.params.lro_en = enable; |
3537 | ||
99cbfa93 | 3538 | if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) { |
619a8f2a TT |
3539 | if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) == |
3540 | mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params)) | |
3541 | reset = false; | |
3542 | } | |
3543 | ||
2e20a151 | 3544 | if (!reset) { |
619a8f2a | 3545 | *old_params = new_channels.params; |
2e20a151 SM |
3546 | err = mlx5e_modify_tirs_lro(priv); |
3547 | goto out; | |
98e81b0a | 3548 | } |
f62b8bb8 | 3549 | |
2e20a151 SM |
3550 | err = mlx5e_open_channels(priv, &new_channels); |
3551 | if (err) | |
3552 | goto out; | |
0e405443 | 3553 | |
2e20a151 SM |
3554 | mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro); |
3555 | out: | |
9b37b07f | 3556 | mutex_unlock(&priv->state_lock); |
0e405443 GP |
3557 | return err; |
3558 | } | |
3559 | ||
2b52a283 | 3560 | static int set_feature_cvlan_filter(struct net_device *netdev, bool enable) |
0e405443 GP |
3561 | { |
3562 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3563 | ||
3564 | if (enable) | |
2b52a283 | 3565 | mlx5e_enable_cvlan_filter(priv); |
0e405443 | 3566 | else |
2b52a283 | 3567 | mlx5e_disable_cvlan_filter(priv); |
0e405443 GP |
3568 | |
3569 | return 0; | |
3570 | } | |
3571 | ||
3572 | static int set_feature_tc_num_filters(struct net_device *netdev, bool enable) | |
3573 | { | |
3574 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
f62b8bb8 | 3575 | |
0e405443 | 3576 | if (!enable && mlx5e_tc_num_filters(priv)) { |
e8f887ac AV |
3577 | netdev_err(netdev, |
3578 | "Active offloaded tc filters, can't turn hw_tc_offload off\n"); | |
3579 | return -EINVAL; | |
3580 | } | |
3581 | ||
0e405443 GP |
3582 | return 0; |
3583 | } | |
3584 | ||
94cb1ebb EBE |
3585 | static int set_feature_rx_all(struct net_device *netdev, bool enable) |
3586 | { | |
3587 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3588 | struct mlx5_core_dev *mdev = priv->mdev; | |
3589 | ||
3590 | return mlx5_set_port_fcs(mdev, !enable); | |
3591 | } | |
3592 | ||
102722fc GE |
3593 | static int set_feature_rx_fcs(struct net_device *netdev, bool enable) |
3594 | { | |
3595 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3596 | int err; | |
3597 | ||
3598 | mutex_lock(&priv->state_lock); | |
3599 | ||
3600 | priv->channels.params.scatter_fcs_en = enable; | |
3601 | err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable); | |
3602 | if (err) | |
3603 | priv->channels.params.scatter_fcs_en = !enable; | |
3604 | ||
3605 | mutex_unlock(&priv->state_lock); | |
3606 | ||
3607 | return err; | |
3608 | } | |
3609 | ||
36350114 GP |
3610 | static int set_feature_rx_vlan(struct net_device *netdev, bool enable) |
3611 | { | |
3612 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
ff9c852f | 3613 | int err = 0; |
36350114 GP |
3614 | |
3615 | mutex_lock(&priv->state_lock); | |
3616 | ||
6a9764ef | 3617 | priv->channels.params.vlan_strip_disable = !enable; |
ff9c852f SM |
3618 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) |
3619 | goto unlock; | |
3620 | ||
3621 | err = mlx5e_modify_channels_vsd(&priv->channels, !enable); | |
36350114 | 3622 | if (err) |
6a9764ef | 3623 | priv->channels.params.vlan_strip_disable = enable; |
36350114 | 3624 | |
ff9c852f | 3625 | unlock: |
36350114 GP |
3626 | mutex_unlock(&priv->state_lock); |
3627 | ||
3628 | return err; | |
3629 | } | |
3630 | ||
ec080045 | 3631 | #ifdef CONFIG_MLX5_EN_ARFS |
45bf454a MG |
3632 | static int set_feature_arfs(struct net_device *netdev, bool enable) |
3633 | { | |
3634 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3635 | int err; | |
3636 | ||
3637 | if (enable) | |
3638 | err = mlx5e_arfs_enable(priv); | |
3639 | else | |
3640 | err = mlx5e_arfs_disable(priv); | |
3641 | ||
3642 | return err; | |
3643 | } | |
3644 | #endif | |
3645 | ||
0e405443 | 3646 | static int mlx5e_handle_feature(struct net_device *netdev, |
75b81ce7 | 3647 | netdev_features_t *features, |
0e405443 GP |
3648 | netdev_features_t wanted_features, |
3649 | netdev_features_t feature, | |
3650 | mlx5e_feature_handler feature_handler) | |
3651 | { | |
3652 | netdev_features_t changes = wanted_features ^ netdev->features; | |
3653 | bool enable = !!(wanted_features & feature); | |
3654 | int err; | |
3655 | ||
3656 | if (!(changes & feature)) | |
3657 | return 0; | |
3658 | ||
3659 | err = feature_handler(netdev, enable); | |
3660 | if (err) { | |
b20eab15 GP |
3661 | netdev_err(netdev, "%s feature %pNF failed, err %d\n", |
3662 | enable ? "Enable" : "Disable", &feature, err); | |
0e405443 GP |
3663 | return err; |
3664 | } | |
3665 | ||
75b81ce7 | 3666 | MLX5E_SET_FEATURE(features, feature, enable); |
0e405443 GP |
3667 | return 0; |
3668 | } | |
3669 | ||
3670 | static int mlx5e_set_features(struct net_device *netdev, | |
3671 | netdev_features_t features) | |
3672 | { | |
75b81ce7 | 3673 | netdev_features_t oper_features = netdev->features; |
be0f780b GP |
3674 | int err = 0; |
3675 | ||
3676 | #define MLX5E_HANDLE_FEATURE(feature, handler) \ | |
3677 | mlx5e_handle_feature(netdev, &oper_features, features, feature, handler) | |
0e405443 | 3678 | |
be0f780b GP |
3679 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro); |
3680 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER, | |
2b52a283 | 3681 | set_feature_cvlan_filter); |
be0f780b GP |
3682 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters); |
3683 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all); | |
3684 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs); | |
3685 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan); | |
ec080045 | 3686 | #ifdef CONFIG_MLX5_EN_ARFS |
be0f780b | 3687 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs); |
45bf454a | 3688 | #endif |
0e405443 | 3689 | |
75b81ce7 GP |
3690 | if (err) { |
3691 | netdev->features = oper_features; | |
3692 | return -EINVAL; | |
3693 | } | |
3694 | ||
3695 | return 0; | |
f62b8bb8 AV |
3696 | } |
3697 | ||
7d92d580 GP |
3698 | static netdev_features_t mlx5e_fix_features(struct net_device *netdev, |
3699 | netdev_features_t features) | |
3700 | { | |
3701 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
6c3a823e | 3702 | struct mlx5e_params *params; |
7d92d580 GP |
3703 | |
3704 | mutex_lock(&priv->state_lock); | |
6c3a823e | 3705 | params = &priv->channels.params; |
7d92d580 GP |
3706 | if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) { |
3707 | /* HW strips the outer C-tag header, this is a problem | |
3708 | * for S-tag traffic. | |
3709 | */ | |
3710 | features &= ~NETIF_F_HW_VLAN_CTAG_RX; | |
6c3a823e | 3711 | if (!params->vlan_strip_disable) |
7d92d580 GP |
3712 | netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n"); |
3713 | } | |
6c3a823e TT |
3714 | if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) { |
3715 | features &= ~NETIF_F_LRO; | |
3716 | if (params->lro_en) | |
3717 | netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n"); | |
3718 | } | |
3719 | ||
7d92d580 GP |
3720 | mutex_unlock(&priv->state_lock); |
3721 | ||
3722 | return features; | |
3723 | } | |
3724 | ||
250a42b6 AN |
3725 | int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, |
3726 | change_hw_mtu_cb set_mtu_cb) | |
f62b8bb8 AV |
3727 | { |
3728 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2e20a151 | 3729 | struct mlx5e_channels new_channels = {}; |
472a1e44 | 3730 | struct mlx5e_params *params; |
98e81b0a | 3731 | int err = 0; |
506753b0 | 3732 | bool reset; |
f62b8bb8 | 3733 | |
f62b8bb8 | 3734 | mutex_lock(&priv->state_lock); |
98e81b0a | 3735 | |
472a1e44 | 3736 | params = &priv->channels.params; |
506753b0 | 3737 | |
73281b78 | 3738 | reset = !params->lro_en; |
2e20a151 | 3739 | reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state); |
98e81b0a | 3740 | |
73281b78 TT |
3741 | new_channels.params = *params; |
3742 | new_channels.params.sw_mtu = new_mtu; | |
3743 | ||
a26a5bdf TT |
3744 | if (params->xdp_prog && |
3745 | !mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) { | |
3746 | netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n", | |
3747 | new_mtu, MLX5E_XDP_MAX_MTU); | |
3748 | err = -EINVAL; | |
3749 | goto out; | |
3750 | } | |
3751 | ||
99cbfa93 | 3752 | if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { |
73281b78 TT |
3753 | u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params); |
3754 | u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params); | |
3755 | ||
3756 | reset = reset && (ppw_old != ppw_new); | |
3757 | } | |
3758 | ||
2e20a151 | 3759 | if (!reset) { |
472a1e44 | 3760 | params->sw_mtu = new_mtu; |
eacecf27 AN |
3761 | if (set_mtu_cb) |
3762 | set_mtu_cb(priv); | |
472a1e44 | 3763 | netdev->mtu = params->sw_mtu; |
2e20a151 SM |
3764 | goto out; |
3765 | } | |
98e81b0a | 3766 | |
2e20a151 | 3767 | err = mlx5e_open_channels(priv, &new_channels); |
472a1e44 | 3768 | if (err) |
2e20a151 | 3769 | goto out; |
2e20a151 | 3770 | |
250a42b6 | 3771 | mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb); |
472a1e44 | 3772 | netdev->mtu = new_channels.params.sw_mtu; |
f62b8bb8 | 3773 | |
2e20a151 SM |
3774 | out: |
3775 | mutex_unlock(&priv->state_lock); | |
f62b8bb8 AV |
3776 | return err; |
3777 | } | |
3778 | ||
250a42b6 AN |
3779 | static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu) |
3780 | { | |
3781 | return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu); | |
3782 | } | |
3783 | ||
7c39afb3 FD |
3784 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr) |
3785 | { | |
3786 | struct hwtstamp_config config; | |
3787 | int err; | |
3788 | ||
6dbc80ca MS |
3789 | if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) || |
3790 | (mlx5_clock_get_ptp_index(priv->mdev) == -1)) | |
7c39afb3 FD |
3791 | return -EOPNOTSUPP; |
3792 | ||
3793 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
3794 | return -EFAULT; | |
3795 | ||
3796 | /* TX HW timestamp */ | |
3797 | switch (config.tx_type) { | |
3798 | case HWTSTAMP_TX_OFF: | |
3799 | case HWTSTAMP_TX_ON: | |
3800 | break; | |
3801 | default: | |
3802 | return -ERANGE; | |
3803 | } | |
3804 | ||
3805 | mutex_lock(&priv->state_lock); | |
3806 | /* RX HW timestamp */ | |
3807 | switch (config.rx_filter) { | |
3808 | case HWTSTAMP_FILTER_NONE: | |
3809 | /* Reset CQE compression to Admin default */ | |
3810 | mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def); | |
3811 | break; | |
3812 | case HWTSTAMP_FILTER_ALL: | |
3813 | case HWTSTAMP_FILTER_SOME: | |
3814 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
3815 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
3816 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
3817 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
3818 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
3819 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
3820 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
3821 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
3822 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
3823 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
3824 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
3825 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
3826 | case HWTSTAMP_FILTER_NTP_ALL: | |
3827 | /* Disable CQE compression */ | |
3828 | netdev_warn(priv->netdev, "Disabling cqe compression"); | |
3829 | err = mlx5e_modify_rx_cqe_compression_locked(priv, false); | |
3830 | if (err) { | |
3831 | netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err); | |
3832 | mutex_unlock(&priv->state_lock); | |
3833 | return err; | |
3834 | } | |
3835 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
3836 | break; | |
3837 | default: | |
3838 | mutex_unlock(&priv->state_lock); | |
3839 | return -ERANGE; | |
3840 | } | |
3841 | ||
3842 | memcpy(&priv->tstamp, &config, sizeof(config)); | |
3843 | mutex_unlock(&priv->state_lock); | |
3844 | ||
3845 | return copy_to_user(ifr->ifr_data, &config, | |
3846 | sizeof(config)) ? -EFAULT : 0; | |
3847 | } | |
3848 | ||
3849 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr) | |
3850 | { | |
3851 | struct hwtstamp_config *cfg = &priv->tstamp; | |
3852 | ||
3853 | if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz)) | |
3854 | return -EOPNOTSUPP; | |
3855 | ||
3856 | return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0; | |
3857 | } | |
3858 | ||
ef9814de EBE |
3859 | static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
3860 | { | |
1170fbd8 FD |
3861 | struct mlx5e_priv *priv = netdev_priv(dev); |
3862 | ||
ef9814de EBE |
3863 | switch (cmd) { |
3864 | case SIOCSHWTSTAMP: | |
1170fbd8 | 3865 | return mlx5e_hwstamp_set(priv, ifr); |
ef9814de | 3866 | case SIOCGHWTSTAMP: |
1170fbd8 | 3867 | return mlx5e_hwstamp_get(priv, ifr); |
ef9814de EBE |
3868 | default: |
3869 | return -EOPNOTSUPP; | |
3870 | } | |
3871 | } | |
3872 | ||
e80541ec | 3873 | #ifdef CONFIG_MLX5_ESWITCH |
66e49ded SM |
3874 | static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac) |
3875 | { | |
3876 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3877 | struct mlx5_core_dev *mdev = priv->mdev; | |
3878 | ||
3879 | return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac); | |
3880 | } | |
3881 | ||
79aab093 MS |
3882 | static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos, |
3883 | __be16 vlan_proto) | |
66e49ded SM |
3884 | { |
3885 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3886 | struct mlx5_core_dev *mdev = priv->mdev; | |
3887 | ||
79aab093 MS |
3888 | if (vlan_proto != htons(ETH_P_8021Q)) |
3889 | return -EPROTONOSUPPORT; | |
3890 | ||
66e49ded SM |
3891 | return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1, |
3892 | vlan, qos); | |
3893 | } | |
3894 | ||
f942380c MHY |
3895 | static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting) |
3896 | { | |
3897 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3898 | struct mlx5_core_dev *mdev = priv->mdev; | |
3899 | ||
3900 | return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting); | |
3901 | } | |
3902 | ||
1edc57e2 MHY |
3903 | static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting) |
3904 | { | |
3905 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3906 | struct mlx5_core_dev *mdev = priv->mdev; | |
3907 | ||
3908 | return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting); | |
3909 | } | |
bd77bf1c MHY |
3910 | |
3911 | static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, | |
3912 | int max_tx_rate) | |
3913 | { | |
3914 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3915 | struct mlx5_core_dev *mdev = priv->mdev; | |
3916 | ||
bd77bf1c | 3917 | return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1, |
c9497c98 | 3918 | max_tx_rate, min_tx_rate); |
bd77bf1c MHY |
3919 | } |
3920 | ||
66e49ded SM |
3921 | static int mlx5_vport_link2ifla(u8 esw_link) |
3922 | { | |
3923 | switch (esw_link) { | |
cc9c82a8 | 3924 | case MLX5_VPORT_ADMIN_STATE_DOWN: |
66e49ded | 3925 | return IFLA_VF_LINK_STATE_DISABLE; |
cc9c82a8 | 3926 | case MLX5_VPORT_ADMIN_STATE_UP: |
66e49ded SM |
3927 | return IFLA_VF_LINK_STATE_ENABLE; |
3928 | } | |
3929 | return IFLA_VF_LINK_STATE_AUTO; | |
3930 | } | |
3931 | ||
3932 | static int mlx5_ifla_link2vport(u8 ifla_link) | |
3933 | { | |
3934 | switch (ifla_link) { | |
3935 | case IFLA_VF_LINK_STATE_DISABLE: | |
cc9c82a8 | 3936 | return MLX5_VPORT_ADMIN_STATE_DOWN; |
66e49ded | 3937 | case IFLA_VF_LINK_STATE_ENABLE: |
cc9c82a8 | 3938 | return MLX5_VPORT_ADMIN_STATE_UP; |
66e49ded | 3939 | } |
cc9c82a8 | 3940 | return MLX5_VPORT_ADMIN_STATE_AUTO; |
66e49ded SM |
3941 | } |
3942 | ||
3943 | static int mlx5e_set_vf_link_state(struct net_device *dev, int vf, | |
3944 | int link_state) | |
3945 | { | |
3946 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3947 | struct mlx5_core_dev *mdev = priv->mdev; | |
3948 | ||
3949 | return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1, | |
3950 | mlx5_ifla_link2vport(link_state)); | |
3951 | } | |
3952 | ||
3953 | static int mlx5e_get_vf_config(struct net_device *dev, | |
3954 | int vf, struct ifla_vf_info *ivi) | |
3955 | { | |
3956 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3957 | struct mlx5_core_dev *mdev = priv->mdev; | |
3958 | int err; | |
3959 | ||
3960 | err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi); | |
3961 | if (err) | |
3962 | return err; | |
3963 | ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate); | |
3964 | return 0; | |
3965 | } | |
3966 | ||
3967 | static int mlx5e_get_vf_stats(struct net_device *dev, | |
3968 | int vf, struct ifla_vf_stats *vf_stats) | |
3969 | { | |
3970 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3971 | struct mlx5_core_dev *mdev = priv->mdev; | |
3972 | ||
3973 | return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1, | |
3974 | vf_stats); | |
3975 | } | |
e80541ec | 3976 | #endif |
66e49ded | 3977 | |
dccea6bf SM |
3978 | struct mlx5e_vxlan_work { |
3979 | struct work_struct work; | |
3980 | struct mlx5e_priv *priv; | |
3981 | u16 port; | |
3982 | }; | |
3983 | ||
3984 | static void mlx5e_vxlan_add_work(struct work_struct *work) | |
3985 | { | |
3986 | struct mlx5e_vxlan_work *vxlan_work = | |
3987 | container_of(work, struct mlx5e_vxlan_work, work); | |
3988 | struct mlx5e_priv *priv = vxlan_work->priv; | |
3989 | u16 port = vxlan_work->port; | |
3990 | ||
3991 | mutex_lock(&priv->state_lock); | |
358aa5ce | 3992 | mlx5_vxlan_add_port(priv->mdev->vxlan, port); |
dccea6bf SM |
3993 | mutex_unlock(&priv->state_lock); |
3994 | ||
3995 | kfree(vxlan_work); | |
3996 | } | |
3997 | ||
3998 | static void mlx5e_vxlan_del_work(struct work_struct *work) | |
3999 | { | |
4000 | struct mlx5e_vxlan_work *vxlan_work = | |
4001 | container_of(work, struct mlx5e_vxlan_work, work); | |
4002 | struct mlx5e_priv *priv = vxlan_work->priv; | |
4003 | u16 port = vxlan_work->port; | |
4004 | ||
4005 | mutex_lock(&priv->state_lock); | |
358aa5ce | 4006 | mlx5_vxlan_del_port(priv->mdev->vxlan, port); |
dccea6bf SM |
4007 | mutex_unlock(&priv->state_lock); |
4008 | kfree(vxlan_work); | |
4009 | } | |
4010 | ||
4011 | static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add) | |
4012 | { | |
4013 | struct mlx5e_vxlan_work *vxlan_work; | |
4014 | ||
4015 | vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC); | |
4016 | if (!vxlan_work) | |
4017 | return; | |
4018 | ||
4019 | if (add) | |
4020 | INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work); | |
4021 | else | |
4022 | INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work); | |
4023 | ||
4024 | vxlan_work->priv = priv; | |
4025 | vxlan_work->port = port; | |
4026 | queue_work(priv->wq, &vxlan_work->work); | |
4027 | } | |
4028 | ||
1ad9a00a PB |
4029 | static void mlx5e_add_vxlan_port(struct net_device *netdev, |
4030 | struct udp_tunnel_info *ti) | |
b3f63c3d MF |
4031 | { |
4032 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
4033 | ||
974c3f30 AD |
4034 | if (ti->type != UDP_TUNNEL_TYPE_VXLAN) |
4035 | return; | |
4036 | ||
358aa5ce | 4037 | if (!mlx5_vxlan_allowed(priv->mdev->vxlan)) |
b3f63c3d MF |
4038 | return; |
4039 | ||
278d7f3d | 4040 | mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1); |
b3f63c3d MF |
4041 | } |
4042 | ||
1ad9a00a PB |
4043 | static void mlx5e_del_vxlan_port(struct net_device *netdev, |
4044 | struct udp_tunnel_info *ti) | |
b3f63c3d MF |
4045 | { |
4046 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
4047 | ||
974c3f30 AD |
4048 | if (ti->type != UDP_TUNNEL_TYPE_VXLAN) |
4049 | return; | |
4050 | ||
358aa5ce | 4051 | if (!mlx5_vxlan_allowed(priv->mdev->vxlan)) |
b3f63c3d MF |
4052 | return; |
4053 | ||
278d7f3d | 4054 | mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0); |
b3f63c3d MF |
4055 | } |
4056 | ||
27299841 GP |
4057 | static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv, |
4058 | struct sk_buff *skb, | |
4059 | netdev_features_t features) | |
b3f63c3d | 4060 | { |
2989ad1e | 4061 | unsigned int offset = 0; |
b3f63c3d | 4062 | struct udphdr *udph; |
27299841 GP |
4063 | u8 proto; |
4064 | u16 port; | |
b3f63c3d MF |
4065 | |
4066 | switch (vlan_get_protocol(skb)) { | |
4067 | case htons(ETH_P_IP): | |
4068 | proto = ip_hdr(skb)->protocol; | |
4069 | break; | |
4070 | case htons(ETH_P_IPV6): | |
2989ad1e | 4071 | proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL); |
b3f63c3d MF |
4072 | break; |
4073 | default: | |
4074 | goto out; | |
4075 | } | |
4076 | ||
27299841 GP |
4077 | switch (proto) { |
4078 | case IPPROTO_GRE: | |
4079 | return features; | |
4080 | case IPPROTO_UDP: | |
b3f63c3d MF |
4081 | udph = udp_hdr(skb); |
4082 | port = be16_to_cpu(udph->dest); | |
b3f63c3d | 4083 | |
27299841 | 4084 | /* Verify if UDP port is being offloaded by HW */ |
358aa5ce | 4085 | if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port)) |
27299841 GP |
4086 | return features; |
4087 | } | |
b3f63c3d MF |
4088 | |
4089 | out: | |
4090 | /* Disable CSUM and GSO if the udp dport is not offloaded by HW */ | |
4091 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
4092 | } | |
4093 | ||
4094 | static netdev_features_t mlx5e_features_check(struct sk_buff *skb, | |
4095 | struct net_device *netdev, | |
4096 | netdev_features_t features) | |
4097 | { | |
4098 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
4099 | ||
4100 | features = vlan_features_check(skb, features); | |
4101 | features = vxlan_features_check(skb, features); | |
4102 | ||
2ac9cfe7 IT |
4103 | #ifdef CONFIG_MLX5_EN_IPSEC |
4104 | if (mlx5e_ipsec_feature_check(skb, netdev, features)) | |
4105 | return features; | |
4106 | #endif | |
4107 | ||
b3f63c3d MF |
4108 | /* Validate if the tunneled packet is being offloaded by HW */ |
4109 | if (skb->encapsulation && | |
4110 | (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK)) | |
27299841 | 4111 | return mlx5e_tunnel_features_check(priv, skb, features); |
b3f63c3d MF |
4112 | |
4113 | return features; | |
4114 | } | |
4115 | ||
7ca560b5 EBE |
4116 | static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev, |
4117 | struct mlx5e_txqsq *sq) | |
4118 | { | |
7b2117bb | 4119 | struct mlx5_eq *eq = sq->cq.mcq.eq; |
7ca560b5 EBE |
4120 | u32 eqe_count; |
4121 | ||
7ca560b5 | 4122 | netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n", |
7b2117bb | 4123 | eq->eqn, eq->cons_index, eq->irqn); |
7ca560b5 EBE |
4124 | |
4125 | eqe_count = mlx5_eq_poll_irq_disabled(eq); | |
4126 | if (!eqe_count) | |
4127 | return false; | |
4128 | ||
4129 | netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn); | |
05909bab | 4130 | sq->channel->stats->eq_rearm++; |
7ca560b5 EBE |
4131 | return true; |
4132 | } | |
4133 | ||
bfc647d5 | 4134 | static void mlx5e_tx_timeout_work(struct work_struct *work) |
3947ca18 | 4135 | { |
bfc647d5 EBE |
4136 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, |
4137 | tx_timeout_work); | |
4138 | struct net_device *dev = priv->netdev; | |
7ca560b5 | 4139 | bool reopen_channels = false; |
bfc647d5 | 4140 | int i, err; |
3947ca18 | 4141 | |
bfc647d5 EBE |
4142 | rtnl_lock(); |
4143 | mutex_lock(&priv->state_lock); | |
4144 | ||
4145 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
4146 | goto unlock; | |
3947ca18 | 4147 | |
6a9764ef | 4148 | for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) { |
84990945 | 4149 | struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i); |
acc6c595 | 4150 | struct mlx5e_txqsq *sq = priv->txq2sq[i]; |
3947ca18 | 4151 | |
84990945 | 4152 | if (!netif_xmit_stopped(dev_queue)) |
3947ca18 | 4153 | continue; |
bfc647d5 EBE |
4154 | |
4155 | netdev_err(dev, | |
4156 | "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n", | |
84990945 EBE |
4157 | i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc, |
4158 | jiffies_to_usecs(jiffies - dev_queue->trans_start)); | |
3a32b26a | 4159 | |
7ca560b5 EBE |
4160 | /* If we recover a lost interrupt, most likely TX timeout will |
4161 | * be resolved, skip reopening channels | |
4162 | */ | |
4163 | if (!mlx5e_tx_timeout_eq_recover(dev, sq)) { | |
4164 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
4165 | reopen_channels = true; | |
4166 | } | |
3947ca18 DJ |
4167 | } |
4168 | ||
bfc647d5 EBE |
4169 | if (!reopen_channels) |
4170 | goto unlock; | |
4171 | ||
4172 | mlx5e_close_locked(dev); | |
4173 | err = mlx5e_open_locked(dev); | |
4174 | if (err) | |
4175 | netdev_err(priv->netdev, | |
4176 | "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n", | |
4177 | err); | |
4178 | ||
4179 | unlock: | |
4180 | mutex_unlock(&priv->state_lock); | |
4181 | rtnl_unlock(); | |
4182 | } | |
4183 | ||
4184 | static void mlx5e_tx_timeout(struct net_device *dev) | |
4185 | { | |
4186 | struct mlx5e_priv *priv = netdev_priv(dev); | |
4187 | ||
4188 | netdev_err(dev, "TX timeout detected\n"); | |
4189 | queue_work(priv->wq, &priv->tx_timeout_work); | |
3947ca18 DJ |
4190 | } |
4191 | ||
a26a5bdf | 4192 | static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog) |
0ec13877 TT |
4193 | { |
4194 | struct net_device *netdev = priv->netdev; | |
a26a5bdf | 4195 | struct mlx5e_channels new_channels = {}; |
0ec13877 TT |
4196 | |
4197 | if (priv->channels.params.lro_en) { | |
4198 | netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n"); | |
4199 | return -EINVAL; | |
4200 | } | |
4201 | ||
4202 | if (MLX5_IPSEC_DEV(priv->mdev)) { | |
4203 | netdev_warn(netdev, "can't set XDP with IPSec offload\n"); | |
4204 | return -EINVAL; | |
4205 | } | |
4206 | ||
a26a5bdf TT |
4207 | new_channels.params = priv->channels.params; |
4208 | new_channels.params.xdp_prog = prog; | |
4209 | ||
4210 | if (!mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) { | |
4211 | netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n", | |
4212 | new_channels.params.sw_mtu, MLX5E_XDP_MAX_MTU); | |
4213 | return -EINVAL; | |
4214 | } | |
4215 | ||
0ec13877 TT |
4216 | return 0; |
4217 | } | |
4218 | ||
86994156 RS |
4219 | static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog) |
4220 | { | |
4221 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
4222 | struct bpf_prog *old_prog; | |
86994156 | 4223 | bool reset, was_opened; |
96d39502 | 4224 | int err = 0; |
86994156 RS |
4225 | int i; |
4226 | ||
4227 | mutex_lock(&priv->state_lock); | |
4228 | ||
0ec13877 | 4229 | if (prog) { |
a26a5bdf | 4230 | err = mlx5e_xdp_allowed(priv, prog); |
0ec13877 TT |
4231 | if (err) |
4232 | goto unlock; | |
547eede0 IT |
4233 | } |
4234 | ||
86994156 RS |
4235 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); |
4236 | /* no need for full reset when exchanging programs */ | |
6a9764ef | 4237 | reset = (!priv->channels.params.xdp_prog || !prog); |
86994156 RS |
4238 | |
4239 | if (was_opened && reset) | |
4240 | mlx5e_close_locked(netdev); | |
c54c0629 DB |
4241 | if (was_opened && !reset) { |
4242 | /* num_channels is invariant here, so we can take the | |
4243 | * batched reference right upfront. | |
4244 | */ | |
6a9764ef | 4245 | prog = bpf_prog_add(prog, priv->channels.num); |
c54c0629 DB |
4246 | if (IS_ERR(prog)) { |
4247 | err = PTR_ERR(prog); | |
4248 | goto unlock; | |
4249 | } | |
4250 | } | |
86994156 | 4251 | |
c54c0629 DB |
4252 | /* exchange programs, extra prog reference we got from caller |
4253 | * as long as we don't fail from this point onwards. | |
4254 | */ | |
6a9764ef | 4255 | old_prog = xchg(&priv->channels.params.xdp_prog, prog); |
86994156 RS |
4256 | if (old_prog) |
4257 | bpf_prog_put(old_prog); | |
4258 | ||
4259 | if (reset) /* change RQ type according to priv->xdp_prog */ | |
2a0f561b | 4260 | mlx5e_set_rq_type(priv->mdev, &priv->channels.params); |
86994156 RS |
4261 | |
4262 | if (was_opened && reset) | |
4263 | mlx5e_open_locked(netdev); | |
4264 | ||
4265 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset) | |
4266 | goto unlock; | |
4267 | ||
4268 | /* exchanging programs w/o reset, we update ref counts on behalf | |
4269 | * of the channels RQs here. | |
4270 | */ | |
ff9c852f SM |
4271 | for (i = 0; i < priv->channels.num; i++) { |
4272 | struct mlx5e_channel *c = priv->channels.c[i]; | |
86994156 | 4273 | |
c0f1147d | 4274 | clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state); |
86994156 RS |
4275 | napi_synchronize(&c->napi); |
4276 | /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */ | |
4277 | ||
4278 | old_prog = xchg(&c->rq.xdp_prog, prog); | |
4279 | ||
c0f1147d | 4280 | set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state); |
86994156 | 4281 | /* napi_schedule in case we have missed anything */ |
86994156 RS |
4282 | napi_schedule(&c->napi); |
4283 | ||
4284 | if (old_prog) | |
4285 | bpf_prog_put(old_prog); | |
4286 | } | |
4287 | ||
4288 | unlock: | |
4289 | mutex_unlock(&priv->state_lock); | |
4290 | return err; | |
4291 | } | |
4292 | ||
821b2e29 | 4293 | static u32 mlx5e_xdp_query(struct net_device *dev) |
86994156 RS |
4294 | { |
4295 | struct mlx5e_priv *priv = netdev_priv(dev); | |
821b2e29 MKL |
4296 | const struct bpf_prog *xdp_prog; |
4297 | u32 prog_id = 0; | |
86994156 | 4298 | |
821b2e29 MKL |
4299 | mutex_lock(&priv->state_lock); |
4300 | xdp_prog = priv->channels.params.xdp_prog; | |
4301 | if (xdp_prog) | |
4302 | prog_id = xdp_prog->aux->id; | |
4303 | mutex_unlock(&priv->state_lock); | |
4304 | ||
4305 | return prog_id; | |
86994156 RS |
4306 | } |
4307 | ||
f4e63525 | 4308 | static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp) |
86994156 RS |
4309 | { |
4310 | switch (xdp->command) { | |
4311 | case XDP_SETUP_PROG: | |
4312 | return mlx5e_xdp_set(dev, xdp->prog); | |
4313 | case XDP_QUERY_PROG: | |
821b2e29 | 4314 | xdp->prog_id = mlx5e_xdp_query(dev); |
86994156 RS |
4315 | return 0; |
4316 | default: | |
4317 | return -EINVAL; | |
4318 | } | |
4319 | } | |
4320 | ||
4d8fcf21 | 4321 | const struct net_device_ops mlx5e_netdev_ops = { |
f62b8bb8 AV |
4322 | .ndo_open = mlx5e_open, |
4323 | .ndo_stop = mlx5e_close, | |
4324 | .ndo_start_xmit = mlx5e_xmit, | |
0cf0f6d3 | 4325 | .ndo_setup_tc = mlx5e_setup_tc, |
08fb1dac | 4326 | .ndo_select_queue = mlx5e_select_queue, |
f62b8bb8 AV |
4327 | .ndo_get_stats64 = mlx5e_get_stats, |
4328 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
4329 | .ndo_set_mac_address = mlx5e_set_mac, | |
b0eed40e SM |
4330 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, |
4331 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
f62b8bb8 | 4332 | .ndo_set_features = mlx5e_set_features, |
7d92d580 | 4333 | .ndo_fix_features = mlx5e_fix_features, |
250a42b6 | 4334 | .ndo_change_mtu = mlx5e_change_nic_mtu, |
b0eed40e | 4335 | .ndo_do_ioctl = mlx5e_ioctl, |
507f0c81 | 4336 | .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate, |
706b3583 SM |
4337 | .ndo_udp_tunnel_add = mlx5e_add_vxlan_port, |
4338 | .ndo_udp_tunnel_del = mlx5e_del_vxlan_port, | |
4339 | .ndo_features_check = mlx5e_features_check, | |
3947ca18 | 4340 | .ndo_tx_timeout = mlx5e_tx_timeout, |
f4e63525 | 4341 | .ndo_bpf = mlx5e_xdp, |
58b99ee3 | 4342 | .ndo_xdp_xmit = mlx5e_xdp_xmit, |
ec080045 SM |
4343 | #ifdef CONFIG_MLX5_EN_ARFS |
4344 | .ndo_rx_flow_steer = mlx5e_rx_flow_steer, | |
4345 | #endif | |
e80541ec | 4346 | #ifdef CONFIG_MLX5_ESWITCH |
706b3583 | 4347 | /* SRIOV E-Switch NDOs */ |
b0eed40e SM |
4348 | .ndo_set_vf_mac = mlx5e_set_vf_mac, |
4349 | .ndo_set_vf_vlan = mlx5e_set_vf_vlan, | |
f942380c | 4350 | .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk, |
1edc57e2 | 4351 | .ndo_set_vf_trust = mlx5e_set_vf_trust, |
bd77bf1c | 4352 | .ndo_set_vf_rate = mlx5e_set_vf_rate, |
b0eed40e SM |
4353 | .ndo_get_vf_config = mlx5e_get_vf_config, |
4354 | .ndo_set_vf_link_state = mlx5e_set_vf_link_state, | |
4355 | .ndo_get_vf_stats = mlx5e_get_vf_stats, | |
370bad0f OG |
4356 | .ndo_has_offload_stats = mlx5e_has_offload_stats, |
4357 | .ndo_get_offload_stats = mlx5e_get_offload_stats, | |
e80541ec | 4358 | #endif |
f62b8bb8 AV |
4359 | }; |
4360 | ||
4361 | static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) | |
4362 | { | |
4363 | if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
9eb78923 | 4364 | return -EOPNOTSUPP; |
f62b8bb8 AV |
4365 | if (!MLX5_CAP_GEN(mdev, eth_net_offloads) || |
4366 | !MLX5_CAP_GEN(mdev, nic_flow_table) || | |
4367 | !MLX5_CAP_ETH(mdev, csum_cap) || | |
4368 | !MLX5_CAP_ETH(mdev, max_lso_cap) || | |
4369 | !MLX5_CAP_ETH(mdev, vlan_cap) || | |
796a27ec GP |
4370 | !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) || |
4371 | MLX5_CAP_FLOWTABLE(mdev, | |
4372 | flow_table_properties_nic_receive.max_ft_level) | |
4373 | < 3) { | |
f62b8bb8 AV |
4374 | mlx5_core_warn(mdev, |
4375 | "Not creating net device, some required device capabilities are missing\n"); | |
9eb78923 | 4376 | return -EOPNOTSUPP; |
f62b8bb8 | 4377 | } |
66189961 TT |
4378 | if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable)) |
4379 | mlx5_core_warn(mdev, "Self loop back prevention is not supported\n"); | |
7524a5d8 | 4380 | if (!MLX5_CAP_GEN(mdev, cq_moderation)) |
3e432ab6 | 4381 | mlx5_core_warn(mdev, "CQ moderation is not supported\n"); |
66189961 | 4382 | |
f62b8bb8 AV |
4383 | return 0; |
4384 | } | |
4385 | ||
d4b6c488 | 4386 | void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, |
85082dba TT |
4387 | int num_channels) |
4388 | { | |
4389 | int i; | |
4390 | ||
4391 | for (i = 0; i < len; i++) | |
4392 | indirection_rqt[i] = i % num_channels; | |
4393 | } | |
4394 | ||
0608d4db | 4395 | static bool slow_pci_heuristic(struct mlx5_core_dev *mdev) |
b797a684 | 4396 | { |
0608d4db TT |
4397 | u32 link_speed = 0; |
4398 | u32 pci_bw = 0; | |
b797a684 | 4399 | |
2c81bfd5 | 4400 | mlx5e_port_max_linkspeed(mdev, &link_speed); |
3c0d551e | 4401 | pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL); |
0608d4db TT |
4402 | mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n", |
4403 | link_speed, pci_bw); | |
4404 | ||
4405 | #define MLX5E_SLOW_PCI_RATIO (2) | |
4406 | ||
4407 | return link_speed && pci_bw && | |
4408 | link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw; | |
0f6e4cf6 EBE |
4409 | } |
4410 | ||
cbce4f44 | 4411 | static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode) |
0088cbbc | 4412 | { |
cbce4f44 TG |
4413 | struct net_dim_cq_moder moder; |
4414 | ||
4415 | moder.cq_period_mode = cq_period_mode; | |
4416 | moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; | |
4417 | moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; | |
4418 | if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) | |
4419 | moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE; | |
4420 | ||
4421 | return moder; | |
4422 | } | |
0088cbbc | 4423 | |
cbce4f44 TG |
4424 | static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode) |
4425 | { | |
4426 | struct net_dim_cq_moder moder; | |
0088cbbc | 4427 | |
cbce4f44 TG |
4428 | moder.cq_period_mode = cq_period_mode; |
4429 | moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; | |
4430 | moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; | |
0088cbbc | 4431 | if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) |
cbce4f44 TG |
4432 | moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE; |
4433 | ||
4434 | return moder; | |
4435 | } | |
4436 | ||
4437 | static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode) | |
4438 | { | |
4439 | return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ? | |
4440 | NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE : | |
4441 | NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; | |
4442 | } | |
4443 | ||
4444 | void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) | |
4445 | { | |
4446 | if (params->tx_dim_enabled) { | |
4447 | u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); | |
4448 | ||
4449 | params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode); | |
4450 | } else { | |
4451 | params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode); | |
4452 | } | |
0088cbbc TG |
4453 | |
4454 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER, | |
4455 | params->tx_cq_moderation.cq_period_mode == | |
4456 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE); | |
4457 | } | |
4458 | ||
9908aa29 TT |
4459 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) |
4460 | { | |
9a317425 | 4461 | if (params->rx_dim_enabled) { |
cbce4f44 TG |
4462 | u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); |
4463 | ||
4464 | params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode); | |
4465 | } else { | |
4466 | params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode); | |
9a317425 | 4467 | } |
457fcd8a | 4468 | |
6a9764ef | 4469 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER, |
0088cbbc TG |
4470 | params->rx_cq_moderation.cq_period_mode == |
4471 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE); | |
9908aa29 TT |
4472 | } |
4473 | ||
707129dc | 4474 | static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout) |
2b029556 SM |
4475 | { |
4476 | int i; | |
4477 | ||
4478 | /* The supported periods are organized in ascending order */ | |
4479 | for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++) | |
4480 | if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout) | |
4481 | break; | |
4482 | ||
4483 | return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]); | |
4484 | } | |
4485 | ||
749359f4 GT |
4486 | void mlx5e_build_rq_params(struct mlx5_core_dev *mdev, |
4487 | struct mlx5e_params *params) | |
4488 | { | |
4489 | /* Prefer Striding RQ, unless any of the following holds: | |
4490 | * - Striding RQ configuration is not possible/supported. | |
4491 | * - Slow PCI heuristic. | |
4492 | * - Legacy RQ would use linear SKB while Striding RQ would use non-linear. | |
4493 | */ | |
4494 | if (!slow_pci_heuristic(mdev) && | |
4495 | mlx5e_striding_rq_possible(mdev, params) && | |
4496 | (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) || | |
4497 | !mlx5e_rx_is_linear_skb(mdev, params))) | |
4498 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true); | |
4499 | mlx5e_set_rq_type(mdev, params); | |
4500 | mlx5e_init_rq_type_params(mdev, params); | |
4501 | } | |
4502 | ||
3edc0159 GT |
4503 | void mlx5e_build_rss_params(struct mlx5e_params *params) |
4504 | { | |
4505 | params->rss_hfunc = ETH_RSS_HASH_XOR; | |
4506 | netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key)); | |
4507 | mlx5e_build_default_indir_rqt(params->indirection_rqt, | |
4508 | MLX5E_INDIR_RQT_SIZE, params->num_channels); | |
4509 | } | |
4510 | ||
8f493ffd SM |
4511 | void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, |
4512 | struct mlx5e_params *params, | |
472a1e44 | 4513 | u16 max_channels, u16 mtu) |
f62b8bb8 | 4514 | { |
48bfc397 | 4515 | u8 rx_cq_period_mode; |
2fc4bfb7 | 4516 | |
472a1e44 TT |
4517 | params->sw_mtu = mtu; |
4518 | params->hard_mtu = MLX5E_ETH_HARD_MTU; | |
6a9764ef SM |
4519 | params->num_channels = max_channels; |
4520 | params->num_tc = 1; | |
2b029556 | 4521 | |
6a9764ef SM |
4522 | /* SQ */ |
4523 | params->log_sq_size = is_kdump_kernel() ? | |
b4e029da KH |
4524 | MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE : |
4525 | MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; | |
461017cb | 4526 | |
b797a684 | 4527 | /* set CQE compression */ |
6a9764ef | 4528 | params->rx_cqe_compress_def = false; |
b797a684 | 4529 | if (MLX5_CAP_GEN(mdev, cqe_compression) && |
e53eef63 | 4530 | MLX5_CAP_GEN(mdev, vport_group_manager)) |
0608d4db | 4531 | params->rx_cqe_compress_def = slow_pci_heuristic(mdev); |
0f6e4cf6 | 4532 | |
6a9764ef | 4533 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def); |
b856df28 | 4534 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false); |
6a9764ef SM |
4535 | |
4536 | /* RQ */ | |
749359f4 | 4537 | mlx5e_build_rq_params(mdev, params); |
b797a684 | 4538 | |
6a9764ef | 4539 | /* HW LRO */ |
c139dbfd | 4540 | |
5426a0b2 | 4541 | /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */ |
6a9764ef | 4542 | if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) |
619a8f2a TT |
4543 | if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params)) |
4544 | params->lro_en = !slow_pci_heuristic(mdev); | |
6a9764ef | 4545 | params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT); |
b0d4660b | 4546 | |
6a9764ef | 4547 | /* CQ moderation params */ |
48bfc397 | 4548 | rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? |
6a9764ef SM |
4549 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE : |
4550 | MLX5_CQ_PERIOD_MODE_START_FROM_EQE; | |
9a317425 | 4551 | params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation); |
cbce4f44 | 4552 | params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation); |
48bfc397 TG |
4553 | mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode); |
4554 | mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); | |
9908aa29 | 4555 | |
6a9764ef | 4556 | /* TX inline */ |
fbcb127e | 4557 | params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev); |
a6f402e4 | 4558 | |
6a9764ef | 4559 | /* RSS */ |
3edc0159 | 4560 | mlx5e_build_rss_params(params); |
6a9764ef | 4561 | } |
f62b8bb8 | 4562 | |
6a9764ef SM |
4563 | static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev, |
4564 | struct net_device *netdev, | |
4565 | const struct mlx5e_profile *profile, | |
4566 | void *ppriv) | |
4567 | { | |
4568 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
57afead5 | 4569 | |
6a9764ef SM |
4570 | priv->mdev = mdev; |
4571 | priv->netdev = netdev; | |
4572 | priv->profile = profile; | |
4573 | priv->ppriv = ppriv; | |
79c48764 | 4574 | priv->msglevel = MLX5E_MSG_LEVEL; |
05909bab | 4575 | priv->max_opened_tc = 1; |
2d75b2bc | 4576 | |
472a1e44 TT |
4577 | mlx5e_build_nic_params(mdev, &priv->channels.params, |
4578 | profile->max_nch(mdev), netdev->mtu); | |
9908aa29 | 4579 | |
f62b8bb8 AV |
4580 | mutex_init(&priv->state_lock); |
4581 | ||
4582 | INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); | |
4583 | INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); | |
3947ca18 | 4584 | INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work); |
237f258c FD |
4585 | |
4586 | mlx5e_timestamp_init(priv); | |
f62b8bb8 AV |
4587 | } |
4588 | ||
4589 | static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) | |
4590 | { | |
4591 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
4592 | ||
e1d7d349 | 4593 | mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr); |
108805fc SM |
4594 | if (is_zero_ether_addr(netdev->dev_addr) && |
4595 | !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) { | |
4596 | eth_hw_addr_random(netdev); | |
4597 | mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr); | |
4598 | } | |
f62b8bb8 AV |
4599 | } |
4600 | ||
f125376b | 4601 | #if IS_ENABLED(CONFIG_MLX5_ESWITCH) |
cb67b832 HHZ |
4602 | static const struct switchdev_ops mlx5e_switchdev_ops = { |
4603 | .switchdev_port_attr_get = mlx5e_attr_get, | |
4604 | }; | |
e80541ec | 4605 | #endif |
cb67b832 | 4606 | |
6bfd390b | 4607 | static void mlx5e_build_nic_netdev(struct net_device *netdev) |
f62b8bb8 AV |
4608 | { |
4609 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
4610 | struct mlx5_core_dev *mdev = priv->mdev; | |
94cb1ebb EBE |
4611 | bool fcs_supported; |
4612 | bool fcs_enabled; | |
f62b8bb8 AV |
4613 | |
4614 | SET_NETDEV_DEV(netdev, &mdev->pdev->dev); | |
4615 | ||
e80541ec SM |
4616 | netdev->netdev_ops = &mlx5e_netdev_ops; |
4617 | ||
08fb1dac | 4618 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
e80541ec SM |
4619 | if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos)) |
4620 | netdev->dcbnl_ops = &mlx5e_dcbnl_ops; | |
08fb1dac | 4621 | #endif |
66e49ded | 4622 | |
f62b8bb8 AV |
4623 | netdev->watchdog_timeo = 15 * HZ; |
4624 | ||
4625 | netdev->ethtool_ops = &mlx5e_ethtool_ops; | |
4626 | ||
12be4b21 | 4627 | netdev->vlan_features |= NETIF_F_SG; |
f62b8bb8 AV |
4628 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
4629 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; | |
4630 | netdev->vlan_features |= NETIF_F_GRO; | |
4631 | netdev->vlan_features |= NETIF_F_TSO; | |
4632 | netdev->vlan_features |= NETIF_F_TSO6; | |
4633 | netdev->vlan_features |= NETIF_F_RXCSUM; | |
4634 | netdev->vlan_features |= NETIF_F_RXHASH; | |
4635 | ||
71186172 AH |
4636 | netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX; |
4637 | netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX; | |
4638 | ||
6c3a823e TT |
4639 | if (!!MLX5_CAP_ETH(mdev, lro_cap) && |
4640 | mlx5e_check_fragmented_striding_rq_cap(mdev)) | |
f62b8bb8 AV |
4641 | netdev->vlan_features |= NETIF_F_LRO; |
4642 | ||
4643 | netdev->hw_features = netdev->vlan_features; | |
e4cf27bd | 4644 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; |
f62b8bb8 AV |
4645 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; |
4646 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
4382c7b9 | 4647 | netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX; |
f62b8bb8 | 4648 | |
358aa5ce | 4649 | if (mlx5_vxlan_allowed(mdev->vxlan) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) { |
b3f63c3d | 4650 | netdev->hw_enc_features |= NETIF_F_IP_CSUM; |
f3ed653c | 4651 | netdev->hw_enc_features |= NETIF_F_IPV6_CSUM; |
b3f63c3d MF |
4652 | netdev->hw_enc_features |= NETIF_F_TSO; |
4653 | netdev->hw_enc_features |= NETIF_F_TSO6; | |
27299841 GP |
4654 | netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL; |
4655 | } | |
4656 | ||
358aa5ce | 4657 | if (mlx5_vxlan_allowed(mdev->vxlan)) { |
27299841 GP |
4658 | netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | |
4659 | NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
4660 | netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL | | |
4661 | NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
b49663c8 | 4662 | netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM; |
b3f63c3d MF |
4663 | } |
4664 | ||
27299841 GP |
4665 | if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) { |
4666 | netdev->hw_features |= NETIF_F_GSO_GRE | | |
4667 | NETIF_F_GSO_GRE_CSUM; | |
4668 | netdev->hw_enc_features |= NETIF_F_GSO_GRE | | |
4669 | NETIF_F_GSO_GRE_CSUM; | |
4670 | netdev->gso_partial_features |= NETIF_F_GSO_GRE | | |
4671 | NETIF_F_GSO_GRE_CSUM; | |
4672 | } | |
4673 | ||
3f44899e BP |
4674 | netdev->hw_features |= NETIF_F_GSO_PARTIAL; |
4675 | netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4; | |
4676 | netdev->hw_features |= NETIF_F_GSO_UDP_L4; | |
4677 | netdev->features |= NETIF_F_GSO_UDP_L4; | |
4678 | ||
94cb1ebb EBE |
4679 | mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled); |
4680 | ||
4681 | if (fcs_supported) | |
4682 | netdev->hw_features |= NETIF_F_RXALL; | |
4683 | ||
102722fc GE |
4684 | if (MLX5_CAP_ETH(mdev, scatter_fcs)) |
4685 | netdev->hw_features |= NETIF_F_RXFCS; | |
4686 | ||
f62b8bb8 | 4687 | netdev->features = netdev->hw_features; |
6a9764ef | 4688 | if (!priv->channels.params.lro_en) |
f62b8bb8 AV |
4689 | netdev->features &= ~NETIF_F_LRO; |
4690 | ||
94cb1ebb EBE |
4691 | if (fcs_enabled) |
4692 | netdev->features &= ~NETIF_F_RXALL; | |
4693 | ||
102722fc GE |
4694 | if (!priv->channels.params.scatter_fcs_en) |
4695 | netdev->features &= ~NETIF_F_RXFCS; | |
4696 | ||
e8f887ac AV |
4697 | #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f) |
4698 | if (FT_CAP(flow_modify_en) && | |
4699 | FT_CAP(modify_root) && | |
4700 | FT_CAP(identified_miss_table_mode) && | |
1cabe6b0 MG |
4701 | FT_CAP(flow_table_modify)) { |
4702 | netdev->hw_features |= NETIF_F_HW_TC; | |
ec080045 | 4703 | #ifdef CONFIG_MLX5_EN_ARFS |
1cabe6b0 MG |
4704 | netdev->hw_features |= NETIF_F_NTUPLE; |
4705 | #endif | |
4706 | } | |
e8f887ac | 4707 | |
f62b8bb8 | 4708 | netdev->features |= NETIF_F_HIGHDMA; |
7d92d580 | 4709 | netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER; |
f62b8bb8 AV |
4710 | |
4711 | netdev->priv_flags |= IFF_UNICAST_FLT; | |
4712 | ||
4713 | mlx5e_set_netdev_dev_addr(netdev); | |
cb67b832 | 4714 | |
f125376b | 4715 | #if IS_ENABLED(CONFIG_MLX5_ESWITCH) |
733d3e54 | 4716 | if (MLX5_ESWITCH_MANAGER(mdev)) |
cb67b832 HHZ |
4717 | netdev->switchdev_ops = &mlx5e_switchdev_ops; |
4718 | #endif | |
547eede0 IT |
4719 | |
4720 | mlx5e_ipsec_build_netdev(priv); | |
c83294b9 | 4721 | mlx5e_tls_build_netdev(priv); |
f62b8bb8 AV |
4722 | } |
4723 | ||
1462e48d | 4724 | void mlx5e_create_q_counters(struct mlx5e_priv *priv) |
593cf338 RS |
4725 | { |
4726 | struct mlx5_core_dev *mdev = priv->mdev; | |
4727 | int err; | |
4728 | ||
4729 | err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter); | |
4730 | if (err) { | |
4731 | mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err); | |
4732 | priv->q_counter = 0; | |
4733 | } | |
7cbaf9a3 MS |
4734 | |
4735 | err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter); | |
4736 | if (err) { | |
4737 | mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err); | |
4738 | priv->drop_rq_q_counter = 0; | |
4739 | } | |
593cf338 RS |
4740 | } |
4741 | ||
1462e48d | 4742 | void mlx5e_destroy_q_counters(struct mlx5e_priv *priv) |
593cf338 | 4743 | { |
7cbaf9a3 MS |
4744 | if (priv->q_counter) |
4745 | mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter); | |
593cf338 | 4746 | |
7cbaf9a3 MS |
4747 | if (priv->drop_rq_q_counter) |
4748 | mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter); | |
593cf338 RS |
4749 | } |
4750 | ||
182570b2 FD |
4751 | static int mlx5e_nic_init(struct mlx5_core_dev *mdev, |
4752 | struct net_device *netdev, | |
4753 | const struct mlx5e_profile *profile, | |
4754 | void *ppriv) | |
6bfd390b HHZ |
4755 | { |
4756 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
547eede0 | 4757 | int err; |
6bfd390b | 4758 | |
182570b2 FD |
4759 | err = mlx5e_netdev_init(netdev, priv); |
4760 | if (err) | |
4761 | return err; | |
4762 | ||
127ea380 | 4763 | mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv); |
547eede0 IT |
4764 | err = mlx5e_ipsec_init(priv); |
4765 | if (err) | |
4766 | mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err); | |
43585a41 IL |
4767 | err = mlx5e_tls_init(priv); |
4768 | if (err) | |
4769 | mlx5_core_err(mdev, "TLS initialization failed, %d\n", err); | |
6bfd390b | 4770 | mlx5e_build_nic_netdev(netdev); |
8bfaf07f | 4771 | mlx5e_build_tc2txq_maps(priv); |
182570b2 FD |
4772 | |
4773 | return 0; | |
6bfd390b HHZ |
4774 | } |
4775 | ||
4776 | static void mlx5e_nic_cleanup(struct mlx5e_priv *priv) | |
4777 | { | |
43585a41 | 4778 | mlx5e_tls_cleanup(priv); |
547eede0 | 4779 | mlx5e_ipsec_cleanup(priv); |
182570b2 | 4780 | mlx5e_netdev_cleanup(priv->netdev, priv); |
6bfd390b HHZ |
4781 | } |
4782 | ||
4783 | static int mlx5e_init_nic_rx(struct mlx5e_priv *priv) | |
4784 | { | |
4785 | struct mlx5_core_dev *mdev = priv->mdev; | |
4786 | int err; | |
6bfd390b | 4787 | |
1462e48d RD |
4788 | mlx5e_create_q_counters(priv); |
4789 | ||
4790 | err = mlx5e_open_drop_rq(priv, &priv->drop_rq); | |
4791 | if (err) { | |
4792 | mlx5_core_err(mdev, "open drop rq failed, %d\n", err); | |
4793 | goto err_destroy_q_counters; | |
4794 | } | |
4795 | ||
8f493ffd SM |
4796 | err = mlx5e_create_indirect_rqt(priv); |
4797 | if (err) | |
1462e48d | 4798 | goto err_close_drop_rq; |
6bfd390b HHZ |
4799 | |
4800 | err = mlx5e_create_direct_rqts(priv); | |
8f493ffd | 4801 | if (err) |
6bfd390b | 4802 | goto err_destroy_indirect_rqts; |
6bfd390b | 4803 | |
46dc933c | 4804 | err = mlx5e_create_indirect_tirs(priv, true); |
8f493ffd | 4805 | if (err) |
6bfd390b | 4806 | goto err_destroy_direct_rqts; |
6bfd390b HHZ |
4807 | |
4808 | err = mlx5e_create_direct_tirs(priv); | |
8f493ffd | 4809 | if (err) |
6bfd390b | 4810 | goto err_destroy_indirect_tirs; |
6bfd390b HHZ |
4811 | |
4812 | err = mlx5e_create_flow_steering(priv); | |
4813 | if (err) { | |
4814 | mlx5_core_warn(mdev, "create flow steering failed, %d\n", err); | |
4815 | goto err_destroy_direct_tirs; | |
4816 | } | |
4817 | ||
655dc3d2 | 4818 | err = mlx5e_tc_nic_init(priv); |
6bfd390b HHZ |
4819 | if (err) |
4820 | goto err_destroy_flow_steering; | |
4821 | ||
4822 | return 0; | |
4823 | ||
4824 | err_destroy_flow_steering: | |
4825 | mlx5e_destroy_flow_steering(priv); | |
4826 | err_destroy_direct_tirs: | |
4827 | mlx5e_destroy_direct_tirs(priv); | |
4828 | err_destroy_indirect_tirs: | |
46dc933c | 4829 | mlx5e_destroy_indirect_tirs(priv, true); |
6bfd390b | 4830 | err_destroy_direct_rqts: |
8f493ffd | 4831 | mlx5e_destroy_direct_rqts(priv); |
6bfd390b HHZ |
4832 | err_destroy_indirect_rqts: |
4833 | mlx5e_destroy_rqt(priv, &priv->indir_rqt); | |
1462e48d RD |
4834 | err_close_drop_rq: |
4835 | mlx5e_close_drop_rq(&priv->drop_rq); | |
4836 | err_destroy_q_counters: | |
4837 | mlx5e_destroy_q_counters(priv); | |
6bfd390b HHZ |
4838 | return err; |
4839 | } | |
4840 | ||
4841 | static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv) | |
4842 | { | |
655dc3d2 | 4843 | mlx5e_tc_nic_cleanup(priv); |
6bfd390b HHZ |
4844 | mlx5e_destroy_flow_steering(priv); |
4845 | mlx5e_destroy_direct_tirs(priv); | |
46dc933c | 4846 | mlx5e_destroy_indirect_tirs(priv, true); |
8f493ffd | 4847 | mlx5e_destroy_direct_rqts(priv); |
6bfd390b | 4848 | mlx5e_destroy_rqt(priv, &priv->indir_rqt); |
1462e48d RD |
4849 | mlx5e_close_drop_rq(&priv->drop_rq); |
4850 | mlx5e_destroy_q_counters(priv); | |
6bfd390b HHZ |
4851 | } |
4852 | ||
4853 | static int mlx5e_init_nic_tx(struct mlx5e_priv *priv) | |
4854 | { | |
4855 | int err; | |
4856 | ||
4857 | err = mlx5e_create_tises(priv); | |
4858 | if (err) { | |
4859 | mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err); | |
4860 | return err; | |
4861 | } | |
4862 | ||
4863 | #ifdef CONFIG_MLX5_CORE_EN_DCB | |
e207b7e9 | 4864 | mlx5e_dcbnl_initialize(priv); |
6bfd390b HHZ |
4865 | #endif |
4866 | return 0; | |
4867 | } | |
4868 | ||
4869 | static void mlx5e_nic_enable(struct mlx5e_priv *priv) | |
4870 | { | |
4871 | struct net_device *netdev = priv->netdev; | |
4872 | struct mlx5_core_dev *mdev = priv->mdev; | |
2c3b5bee SM |
4873 | u16 max_mtu; |
4874 | ||
4875 | mlx5e_init_l2_addr(priv); | |
4876 | ||
63bfd399 EBE |
4877 | /* Marking the link as currently not needed by the Driver */ |
4878 | if (!netif_running(netdev)) | |
4879 | mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN); | |
4880 | ||
2c3b5bee SM |
4881 | /* MTU range: 68 - hw-specific max */ |
4882 | netdev->min_mtu = ETH_MIN_MTU; | |
4883 | mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1); | |
472a1e44 | 4884 | netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu); |
2c3b5bee | 4885 | mlx5e_set_dev_port_mtu(priv); |
6bfd390b | 4886 | |
7907f23a AH |
4887 | mlx5_lag_add(mdev, netdev); |
4888 | ||
6bfd390b | 4889 | mlx5e_enable_async_events(priv); |
127ea380 | 4890 | |
733d3e54 | 4891 | if (MLX5_ESWITCH_MANAGER(priv->mdev)) |
1d447a39 | 4892 | mlx5e_register_vport_reps(priv); |
2c3b5bee | 4893 | |
610e89e0 SM |
4894 | if (netdev->reg_state != NETREG_REGISTERED) |
4895 | return; | |
2a5e7a13 HN |
4896 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
4897 | mlx5e_dcbnl_init_app(priv); | |
4898 | #endif | |
610e89e0 SM |
4899 | |
4900 | queue_work(priv->wq, &priv->set_rx_mode_work); | |
2c3b5bee SM |
4901 | |
4902 | rtnl_lock(); | |
4903 | if (netif_running(netdev)) | |
4904 | mlx5e_open(netdev); | |
4905 | netif_device_attach(netdev); | |
4906 | rtnl_unlock(); | |
6bfd390b HHZ |
4907 | } |
4908 | ||
4909 | static void mlx5e_nic_disable(struct mlx5e_priv *priv) | |
4910 | { | |
3deef8ce | 4911 | struct mlx5_core_dev *mdev = priv->mdev; |
3deef8ce | 4912 | |
2a5e7a13 HN |
4913 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
4914 | if (priv->netdev->reg_state == NETREG_REGISTERED) | |
4915 | mlx5e_dcbnl_delete_app(priv); | |
4916 | #endif | |
4917 | ||
2c3b5bee SM |
4918 | rtnl_lock(); |
4919 | if (netif_running(priv->netdev)) | |
4920 | mlx5e_close(priv->netdev); | |
4921 | netif_device_detach(priv->netdev); | |
4922 | rtnl_unlock(); | |
4923 | ||
6bfd390b | 4924 | queue_work(priv->wq, &priv->set_rx_mode_work); |
1d447a39 | 4925 | |
733d3e54 | 4926 | if (MLX5_ESWITCH_MANAGER(priv->mdev)) |
1d447a39 SM |
4927 | mlx5e_unregister_vport_reps(priv); |
4928 | ||
6bfd390b | 4929 | mlx5e_disable_async_events(priv); |
3deef8ce | 4930 | mlx5_lag_remove(mdev); |
6bfd390b HHZ |
4931 | } |
4932 | ||
4933 | static const struct mlx5e_profile mlx5e_nic_profile = { | |
4934 | .init = mlx5e_nic_init, | |
4935 | .cleanup = mlx5e_nic_cleanup, | |
4936 | .init_rx = mlx5e_init_nic_rx, | |
4937 | .cleanup_rx = mlx5e_cleanup_nic_rx, | |
4938 | .init_tx = mlx5e_init_nic_tx, | |
4939 | .cleanup_tx = mlx5e_cleanup_nic_tx, | |
4940 | .enable = mlx5e_nic_enable, | |
4941 | .disable = mlx5e_nic_disable, | |
3834a5e6 | 4942 | .update_stats = mlx5e_update_ndo_stats, |
6bfd390b | 4943 | .max_nch = mlx5e_get_max_num_channels, |
7ca42c80 | 4944 | .update_carrier = mlx5e_update_carrier, |
20fd0c19 SM |
4945 | .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe, |
4946 | .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq, | |
6bfd390b HHZ |
4947 | .max_tc = MLX5E_MAX_NUM_TC, |
4948 | }; | |
4949 | ||
2c3b5bee SM |
4950 | /* mlx5e generic netdev management API (move to en_common.c) */ |
4951 | ||
182570b2 FD |
4952 | /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */ |
4953 | int mlx5e_netdev_init(struct net_device *netdev, struct mlx5e_priv *priv) | |
4954 | { | |
4955 | netif_carrier_off(netdev); | |
4956 | ||
303211b4 FD |
4957 | INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work); |
4958 | ||
182570b2 FD |
4959 | priv->wq = create_singlethread_workqueue("mlx5e"); |
4960 | if (!priv->wq) | |
4961 | return -ENOMEM; | |
4962 | ||
4963 | return 0; | |
4964 | } | |
4965 | ||
4966 | void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv) | |
4967 | { | |
4968 | destroy_workqueue(priv->wq); | |
4969 | } | |
4970 | ||
26e59d80 MHY |
4971 | struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev, |
4972 | const struct mlx5e_profile *profile, | |
4973 | void *ppriv) | |
f62b8bb8 | 4974 | { |
26e59d80 | 4975 | int nch = profile->max_nch(mdev); |
f62b8bb8 | 4976 | struct net_device *netdev; |
182570b2 | 4977 | int err; |
f62b8bb8 | 4978 | |
08fb1dac | 4979 | netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), |
6bfd390b | 4980 | nch * profile->max_tc, |
08fb1dac | 4981 | nch); |
f62b8bb8 AV |
4982 | if (!netdev) { |
4983 | mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n"); | |
4984 | return NULL; | |
4985 | } | |
4986 | ||
ec080045 | 4987 | #ifdef CONFIG_MLX5_EN_ARFS |
be4891af SM |
4988 | netdev->rx_cpu_rmap = mdev->rmap; |
4989 | #endif | |
4990 | ||
182570b2 FD |
4991 | err = profile->init(mdev, netdev, profile, ppriv); |
4992 | if (err) { | |
4993 | mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err); | |
4994 | goto err_free_netdev; | |
4995 | } | |
26e59d80 MHY |
4996 | |
4997 | return netdev; | |
4998 | ||
182570b2 | 4999 | err_free_netdev: |
26e59d80 MHY |
5000 | free_netdev(netdev); |
5001 | ||
5002 | return NULL; | |
5003 | } | |
5004 | ||
2c3b5bee | 5005 | int mlx5e_attach_netdev(struct mlx5e_priv *priv) |
26e59d80 MHY |
5006 | { |
5007 | const struct mlx5e_profile *profile; | |
26e59d80 MHY |
5008 | int err; |
5009 | ||
26e59d80 MHY |
5010 | profile = priv->profile; |
5011 | clear_bit(MLX5E_STATE_DESTROYING, &priv->state); | |
7bb29755 | 5012 | |
6bfd390b HHZ |
5013 | err = profile->init_tx(priv); |
5014 | if (err) | |
ec8b9981 | 5015 | goto out; |
5c50368f | 5016 | |
6bfd390b HHZ |
5017 | err = profile->init_rx(priv); |
5018 | if (err) | |
1462e48d | 5019 | goto err_cleanup_tx; |
5c50368f | 5020 | |
6bfd390b HHZ |
5021 | if (profile->enable) |
5022 | profile->enable(priv); | |
f62b8bb8 | 5023 | |
26e59d80 | 5024 | return 0; |
5c50368f | 5025 | |
1462e48d | 5026 | err_cleanup_tx: |
6bfd390b | 5027 | profile->cleanup_tx(priv); |
5c50368f | 5028 | |
26e59d80 MHY |
5029 | out: |
5030 | return err; | |
f62b8bb8 AV |
5031 | } |
5032 | ||
2c3b5bee | 5033 | void mlx5e_detach_netdev(struct mlx5e_priv *priv) |
26e59d80 | 5034 | { |
26e59d80 MHY |
5035 | const struct mlx5e_profile *profile = priv->profile; |
5036 | ||
5037 | set_bit(MLX5E_STATE_DESTROYING, &priv->state); | |
26e59d80 | 5038 | |
37f304d1 SM |
5039 | if (profile->disable) |
5040 | profile->disable(priv); | |
5041 | flush_workqueue(priv->wq); | |
5042 | ||
26e59d80 | 5043 | profile->cleanup_rx(priv); |
26e59d80 | 5044 | profile->cleanup_tx(priv); |
26e59d80 MHY |
5045 | cancel_delayed_work_sync(&priv->update_stats_work); |
5046 | } | |
5047 | ||
2c3b5bee SM |
5048 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv) |
5049 | { | |
5050 | const struct mlx5e_profile *profile = priv->profile; | |
5051 | struct net_device *netdev = priv->netdev; | |
5052 | ||
2c3b5bee SM |
5053 | if (profile->cleanup) |
5054 | profile->cleanup(priv); | |
5055 | free_netdev(netdev); | |
5056 | } | |
5057 | ||
26e59d80 MHY |
5058 | /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying |
5059 | * hardware contexts and to connect it to the current netdev. | |
5060 | */ | |
5061 | static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv) | |
5062 | { | |
5063 | struct mlx5e_priv *priv = vpriv; | |
5064 | struct net_device *netdev = priv->netdev; | |
5065 | int err; | |
5066 | ||
5067 | if (netif_device_present(netdev)) | |
5068 | return 0; | |
5069 | ||
5070 | err = mlx5e_create_mdev_resources(mdev); | |
5071 | if (err) | |
5072 | return err; | |
5073 | ||
2c3b5bee | 5074 | err = mlx5e_attach_netdev(priv); |
26e59d80 MHY |
5075 | if (err) { |
5076 | mlx5e_destroy_mdev_resources(mdev); | |
5077 | return err; | |
5078 | } | |
5079 | ||
5080 | return 0; | |
5081 | } | |
5082 | ||
5083 | static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv) | |
5084 | { | |
5085 | struct mlx5e_priv *priv = vpriv; | |
5086 | struct net_device *netdev = priv->netdev; | |
5087 | ||
5088 | if (!netif_device_present(netdev)) | |
5089 | return; | |
5090 | ||
2c3b5bee | 5091 | mlx5e_detach_netdev(priv); |
26e59d80 MHY |
5092 | mlx5e_destroy_mdev_resources(mdev); |
5093 | } | |
5094 | ||
b50d292b HHZ |
5095 | static void *mlx5e_add(struct mlx5_core_dev *mdev) |
5096 | { | |
07c9f1e5 SM |
5097 | struct net_device *netdev; |
5098 | void *rpriv = NULL; | |
26e59d80 | 5099 | void *priv; |
26e59d80 | 5100 | int err; |
b50d292b | 5101 | |
26e59d80 MHY |
5102 | err = mlx5e_check_required_hca_cap(mdev); |
5103 | if (err) | |
b50d292b HHZ |
5104 | return NULL; |
5105 | ||
e80541ec | 5106 | #ifdef CONFIG_MLX5_ESWITCH |
733d3e54 | 5107 | if (MLX5_ESWITCH_MANAGER(mdev)) { |
07c9f1e5 | 5108 | rpriv = mlx5e_alloc_nic_rep_priv(mdev); |
1d447a39 | 5109 | if (!rpriv) { |
07c9f1e5 | 5110 | mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n"); |
1d447a39 SM |
5111 | return NULL; |
5112 | } | |
1d447a39 | 5113 | } |
e80541ec | 5114 | #endif |
127ea380 | 5115 | |
1d447a39 | 5116 | netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv); |
26e59d80 MHY |
5117 | if (!netdev) { |
5118 | mlx5_core_err(mdev, "mlx5e_create_netdev failed\n"); | |
07c9f1e5 | 5119 | goto err_free_rpriv; |
26e59d80 MHY |
5120 | } |
5121 | ||
5122 | priv = netdev_priv(netdev); | |
5123 | ||
5124 | err = mlx5e_attach(mdev, priv); | |
5125 | if (err) { | |
5126 | mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err); | |
5127 | goto err_destroy_netdev; | |
5128 | } | |
5129 | ||
5130 | err = register_netdev(netdev); | |
5131 | if (err) { | |
5132 | mlx5_core_err(mdev, "register_netdev failed, %d\n", err); | |
5133 | goto err_detach; | |
b50d292b | 5134 | } |
26e59d80 | 5135 | |
2a5e7a13 HN |
5136 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
5137 | mlx5e_dcbnl_init_app(priv); | |
5138 | #endif | |
26e59d80 MHY |
5139 | return priv; |
5140 | ||
5141 | err_detach: | |
5142 | mlx5e_detach(mdev, priv); | |
26e59d80 | 5143 | err_destroy_netdev: |
2c3b5bee | 5144 | mlx5e_destroy_netdev(priv); |
07c9f1e5 | 5145 | err_free_rpriv: |
1d447a39 | 5146 | kfree(rpriv); |
26e59d80 | 5147 | return NULL; |
b50d292b HHZ |
5148 | } |
5149 | ||
b50d292b HHZ |
5150 | static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv) |
5151 | { | |
5152 | struct mlx5e_priv *priv = vpriv; | |
1d447a39 | 5153 | void *ppriv = priv->ppriv; |
127ea380 | 5154 | |
2a5e7a13 HN |
5155 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
5156 | mlx5e_dcbnl_delete_app(priv); | |
5157 | #endif | |
5e1e93c7 | 5158 | unregister_netdev(priv->netdev); |
26e59d80 | 5159 | mlx5e_detach(mdev, vpriv); |
2c3b5bee | 5160 | mlx5e_destroy_netdev(priv); |
1d447a39 | 5161 | kfree(ppriv); |
b50d292b HHZ |
5162 | } |
5163 | ||
f62b8bb8 AV |
5164 | static void *mlx5e_get_netdev(void *vpriv) |
5165 | { | |
5166 | struct mlx5e_priv *priv = vpriv; | |
5167 | ||
5168 | return priv->netdev; | |
5169 | } | |
5170 | ||
5171 | static struct mlx5_interface mlx5e_interface = { | |
b50d292b HHZ |
5172 | .add = mlx5e_add, |
5173 | .remove = mlx5e_remove, | |
26e59d80 MHY |
5174 | .attach = mlx5e_attach, |
5175 | .detach = mlx5e_detach, | |
f62b8bb8 AV |
5176 | .event = mlx5e_async_event, |
5177 | .protocol = MLX5_INTERFACE_PROTOCOL_ETH, | |
5178 | .get_dev = mlx5e_get_netdev, | |
5179 | }; | |
5180 | ||
5181 | void mlx5e_init(void) | |
5182 | { | |
2ac9cfe7 | 5183 | mlx5e_ipsec_build_inverse_table(); |
665bc539 | 5184 | mlx5e_build_ptys2ethtool_map(); |
f62b8bb8 AV |
5185 | mlx5_register_interface(&mlx5e_interface); |
5186 | } | |
5187 | ||
5188 | void mlx5e_cleanup(void) | |
5189 | { | |
5190 | mlx5_unregister_interface(&mlx5e_interface); | |
5191 | } |