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net/mlx5: Add DCBX firmware commands support
[thirdparty/kernel/stable.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
f62b8bb8 38#include "en.h"
e8f887ac 39#include "en_tc.h"
66e49ded 40#include "eswitch.h"
b3f63c3d 41#include "vxlan.h"
f62b8bb8
AV		 42
43struct mlx5e_rq_param {
cb3c7fd4
GR		 44 u32 rqc[MLX5_ST_SZ_DW(rqc)];
45 struct mlx5_wq_param wq;
46 bool am_enabled;
f62b8bb8
AV		 47};
48
49struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
58d52291 52 u16 max_inline;
cff92d7c 53 u8 min_inline_mode;
f10b7cc7 54 enum mlx5e_sq_type type;
f62b8bb8
AV		 55};
56
57struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
9908aa29 61 u8 cq_period_mode;
f62b8bb8
AV		 62};
63
64struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
b5503b99 67 struct mlx5e_sq_param xdp_sq;
d3c9bc27 68 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
d3c9bc27 71 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 72};
73
2fc4bfb7
SM		 74static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75{
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
79}
80
81static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
82{
83 priv->params.rq_wq_type = rq_type;
84 switch (priv->params.rq_wq_type) {
85 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
86 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
87 priv->params.mpwqe_log_stride_sz = priv->params.rx_cqe_compress ?
88 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
89 MLX5_MPWRQ_LOG_STRIDE_SIZE;
90 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
91 priv->params.mpwqe_log_stride_sz;
92 break;
93 default: /* MLX5_WQ_TYPE_LINKED_LIST */
94 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
95 }
96 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
97 BIT(priv->params.log_rq_size));
98
99 mlx5_core_info(priv->mdev,
100 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
101 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
102 BIT(priv->params.log_rq_size),
103 BIT(priv->params.mpwqe_log_stride_sz),
104 priv->params.rx_cqe_compress_admin);
105}
106
107static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
108{
86994156
RS		 109 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
110 !priv->xdp_prog ?
2fc4bfb7
SM		 111 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
112 MLX5_WQ_TYPE_LINKED_LIST;
113 mlx5e_set_rq_type_params(priv, rq_type);
114}
115
f62b8bb8
AV		 116static void mlx5e_update_carrier(struct mlx5e_priv *priv)
117{
118 struct mlx5_core_dev *mdev = priv->mdev;
119 u8 port_state;
120
121 port_state = mlx5_query_vport_state(mdev,
e7546514 122 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8 123
87424ad5
SD		 124 if (port_state == VPORT_STATE_UP) {
125 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 126 netif_carrier_on(priv->netdev);
87424ad5
SD		 127 } else {
128 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 129 netif_carrier_off(priv->netdev);
87424ad5 130 }
f62b8bb8
AV		 131}
132
133static void mlx5e_update_carrier_work(struct work_struct *work)
134{
135 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
136 update_carrier_work);
137
138 mutex_lock(&priv->state_lock);
139 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
140 mlx5e_update_carrier(priv);
141 mutex_unlock(&priv->state_lock);
142}
143
3947ca18
DJ		 144static void mlx5e_tx_timeout_work(struct work_struct *work)
145{
146 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
147 tx_timeout_work);
148 int err;
149
150 rtnl_lock();
151 mutex_lock(&priv->state_lock);
152 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
153 goto unlock;
154 mlx5e_close_locked(priv->netdev);
155 err = mlx5e_open_locked(priv->netdev);
156 if (err)
157 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
158 err);
159unlock:
160 mutex_unlock(&priv->state_lock);
161 rtnl_unlock();
162}
163
9218b44d 164static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 165{
9218b44d 166 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 167 struct mlx5e_rq_stats *rq_stats;
168 struct mlx5e_sq_stats *sq_stats;
9218b44d 169 u64 tx_offload_none = 0;
f62b8bb8
AV		 170 int i, j;
171
9218b44d 172 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 173 for (i = 0; i < priv->params.num_channels; i++) {
174 rq_stats = &priv->channel[i]->rq.stats;
175
faf4478b
GP		 176 s->rx_packets += rq_stats->packets;
177 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 178 s->rx_lro_packets += rq_stats->lro_packets;
179 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 180 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 181 s->rx_csum_complete += rq_stats->csum_complete;
182 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 183 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 184 s->rx_xdp_tx += rq_stats->xdp_tx;
185 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 186 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 187 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 188 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 189 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
190 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
4415a031
TT		 191 s->rx_cache_reuse += rq_stats->cache_reuse;
192 s->rx_cache_full += rq_stats->cache_full;
193 s->rx_cache_empty += rq_stats->cache_empty;
194 s->rx_cache_busy += rq_stats->cache_busy;
f62b8bb8 195
a4418a6c 196 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 197 sq_stats = &priv->channel[i]->sq[j].stats;
198
faf4478b
GP		 199 s->tx_packets += sq_stats->packets;
200 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 201 s->tx_tso_packets += sq_stats->tso_packets;
202 s->tx_tso_bytes += sq_stats->tso_bytes;
203 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
204 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 205 s->tx_queue_stopped += sq_stats->stopped;
206 s->tx_queue_wake += sq_stats->wake;
207 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 208 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1
GP		 209 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
210 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 211 }
212 }
213
9218b44d 214 /* Update calculated offload counters */
bfe6d8d1
GP		 215 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
216 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 217
bfe6d8d1 218 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 219 priv->stats.pport.phy_counters,
220 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 221}
222
223static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
224{
225 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
226 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 227 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 228 struct mlx5_core_dev *mdev = priv->mdev;
229
f62b8bb8
AV		 230 MLX5_SET(query_vport_counter_in, in, opcode,
231 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
232 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
233 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
234
235 memset(out, 0, outlen);
9218b44d
GP		 236 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
237}
238
239static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
240{
241 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
242 struct mlx5_core_dev *mdev = priv->mdev;
243 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 244 int prio;
9218b44d
GP		 245 void *out;
246 u32 *in;
247
248 in = mlx5_vzalloc(sz);
249 if (!in)
f62b8bb8
AV		 250 goto free_out;
251
9218b44d 252 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 253
9218b44d
GP		 254 out = pstats->IEEE_802_3_counters;
255 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
256 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 257
9218b44d
GP		 258 out = pstats->RFC_2863_counters;
259 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
260 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
261
262 out = pstats->RFC_2819_counters;
263 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
264 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 265
121fcdc8
GP		 266 out = pstats->phy_counters;
267 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
268 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
269
cf678570
GP		 270 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
271 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
272 out = pstats->per_prio_counters[prio];
273 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
274 mlx5_core_access_reg(mdev, in, sz, out, sz,
275 MLX5_REG_PPCNT, 0, 0);
276 }
277
f62b8bb8 278free_out:
9218b44d
GP		 279 kvfree(in);
280}
281
282static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
283{
284 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
285
286 if (!priv->q_counter)
287 return;
288
289 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
290 &qcnt->rx_out_of_buffer);
291}
292
9c726239
GP		 293static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
294{
295 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
296 struct mlx5_core_dev *mdev = priv->mdev;
297 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
298 void *out;
299 u32 *in;
300
301 in = mlx5_vzalloc(sz);
302 if (!in)
303 return;
304
305 out = pcie_stats->pcie_perf_counters;
306 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
307 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
308
309 out = pcie_stats->pcie_tas_counters;
310 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
311 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
312
313 kvfree(in);
314}
315
9218b44d
GP		 316void mlx5e_update_stats(struct mlx5e_priv *priv)
317{
9218b44d
GP		 318 mlx5e_update_q_counter(priv);
319 mlx5e_update_vport_counters(priv);
320 mlx5e_update_pport_counters(priv);
121fcdc8 321 mlx5e_update_sw_counters(priv);
9c726239 322 mlx5e_update_pcie_counters(priv);
f62b8bb8
AV		 323}
324
cb67b832 325void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 326{
327 struct delayed_work *dwork = to_delayed_work(work);
328 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
329 update_stats_work);
330 mutex_lock(&priv->state_lock);
331 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 332 priv->profile->update_stats(priv);
7bb29755
MF		 333 queue_delayed_work(priv->wq, dwork,
334 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 335 }
336 mutex_unlock(&priv->state_lock);
337}
338
daa21560
TT		 339static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
340 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 341{
daa21560
TT		 342 struct mlx5e_priv *priv = vpriv;
343
e0f46eb9 344 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 345 return;
346
f62b8bb8
AV		 347 switch (event) {
348 case MLX5_DEV_EVENT_PORT_UP:
349 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 350 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8
AV		 351 break;
352
353 default:
354 break;
355 }
356}
357
f62b8bb8
AV		 358static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
359{
e0f46eb9 360 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 361}
362
363static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
364{
e0f46eb9 365 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 366 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 367}
368
facc9699
SM		 369#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
370#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
371
7e426671
TT		 372static inline int mlx5e_get_wqe_mtt_sz(void)
373{
374 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
375 * To avoid copying garbage after the mtt array, we allocate
376 * a little more.
377 */
378 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
379 MLX5_UMR_MTT_ALIGNMENT);
380}
381
382static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
383 struct mlx5e_umr_wqe *wqe, u16 ix)
384{
385 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
386 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
387 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 388 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 389 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
390 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
391
392 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
393 ds_cnt);
394 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
395 cseg->imm = rq->mkey_be;
396
397 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
398 ucseg->klm_octowords =
399 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
400 ucseg->bsf_octowords =
401 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
402 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
403
404 dseg->lkey = sq->mkey_be;
405 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
406}
407
408static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
409 struct mlx5e_channel *c)
410{
411 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
412 int mtt_sz = mlx5e_get_wqe_mtt_sz();
413 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
414 int i;
415
21c59685
SM		 416 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
417 GFP_KERNEL, cpu_to_node(c->cpu));
418 if (!rq->mpwqe.info)
7e426671
TT		 419 goto err_out;
420
421 /* We allocate more than mtt_sz as we will align the pointer */
21c59685 422 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
7e426671 423 cpu_to_node(c->cpu));
21c59685 424 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 425 goto err_free_wqe_info;
426
427 for (i = 0; i < wq_sz; i++) {
21c59685 428 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 429
21c59685 430 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 431 MLX5_UMR_ALIGN);
432 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
433 PCI_DMA_TODEVICE);
434 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
435 goto err_unmap_mtts;
436
437 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
438 }
439
440 return 0;
441
442err_unmap_mtts:
443 while (--i >= 0) {
21c59685 444 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 445
446 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
447 PCI_DMA_TODEVICE);
448 }
21c59685 449 kfree(rq->mpwqe.mtt_no_align);
7e426671 450err_free_wqe_info:
21c59685 451 kfree(rq->mpwqe.info);
7e426671
TT		 452
453err_out:
454 return -ENOMEM;
455}
456
457static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
458{
459 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
460 int mtt_sz = mlx5e_get_wqe_mtt_sz();
461 int i;
462
463 for (i = 0; i < wq_sz; i++) {
21c59685 464 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 465
466 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
467 PCI_DMA_TODEVICE);
468 }
21c59685
SM		 469 kfree(rq->mpwqe.mtt_no_align);
470 kfree(rq->mpwqe.info);
7e426671
TT		 471}
472
f62b8bb8
AV		 473static int mlx5e_create_rq(struct mlx5e_channel *c,
474 struct mlx5e_rq_param *param,
475 struct mlx5e_rq *rq)
476{
477 struct mlx5e_priv *priv = c->priv;
478 struct mlx5_core_dev *mdev = priv->mdev;
479 void *rqc = param->rqc;
480 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 481 u32 byte_count;
1bfecfca
SM		 482 u32 frag_sz;
483 int npages;
f62b8bb8
AV		 484 int wq_sz;
485 int err;
486 int i;
487
311c7c71
SM		 488 param->wq.db_numa_node = cpu_to_node(c->cpu);
489
f62b8bb8
AV		 490 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
491 &rq->wq_ctrl);
492 if (err)
493 return err;
494
495 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
496
497 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 498
7e426671
TT		 499 rq->wq_type = priv->params.rq_wq_type;
500 rq->pdev = c->pdev;
501 rq->netdev = c->netdev;
502 rq->tstamp = &priv->tstamp;
503 rq->channel = c;
504 rq->ix = c->ix;
505 rq->priv = c->priv;
97bc402d
DB		 506
507 rq->xdp_prog = priv->xdp_prog ? bpf_prog_inc(priv->xdp_prog) : NULL;
508 if (IS_ERR(rq->xdp_prog)) {
509 err = PTR_ERR(rq->xdp_prog);
510 rq->xdp_prog = NULL;
511 goto err_rq_wq_destroy;
512 }
7e426671 513
b5503b99
SM		 514 rq->buff.map_dir = DMA_FROM_DEVICE;
515 if (rq->xdp_prog)
516 rq->buff.map_dir = DMA_BIDIRECTIONAL;
517
461017cb
TT		 518 switch (priv->params.rq_wq_type) {
519 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476
OG		 520 if (mlx5e_is_vf_vport_rep(priv)) {
521 err = -EINVAL;
522 goto err_rq_wq_destroy;
523 }
524
461017cb
TT		 525 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
526 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 527 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 528
21c59685 529 rq->mpwqe.mtt_offset = c->ix *
fe4c988b
SM		 530 MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
531
d9d9f156
TT		 532 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
533 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
1bfecfca
SM		 534
535 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
536 byte_count = rq->buff.wqe_sz;
7e426671
TT		 537 rq->mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
538 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
539 if (err)
540 goto err_rq_wq_destroy;
461017cb
TT		 541 break;
542 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca
SM		 543 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
544 GFP_KERNEL, cpu_to_node(c->cpu));
545 if (!rq->dma_info) {
461017cb
TT		 546 err = -ENOMEM;
547 goto err_rq_wq_destroy;
548 }
1bfecfca 549
f5f82476
OG		 550 if (mlx5e_is_vf_vport_rep(priv))
551 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
552 else
553 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
554
461017cb 555 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 556 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 557
1bfecfca 558 rq->buff.wqe_sz = (priv->params.lro_en) ?
461017cb
TT		 559 priv->params.lro_wqe_sz :
560 MLX5E_SW2HW_MTU(priv->netdev->mtu);
1bfecfca
SM		 561 byte_count = rq->buff.wqe_sz;
562
563 /* calc the required page order */
564 frag_sz = MLX5_RX_HEADROOM +
565 byte_count /* packet data */ +
566 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
567 frag_sz = SKB_DATA_ALIGN(frag_sz);
568
569 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
570 rq->buff.page_order = order_base_2(npages);
571
461017cb 572 byte_count |= MLX5_HW_START_PADDING;
7e426671 573 rq->mkey_be = c->mkey_be;
461017cb 574 }
f62b8bb8
AV		 575
576 for (i = 0; i < wq_sz; i++) {
577 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
578
461017cb 579 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 580 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 581 }
582
cb3c7fd4
GR		 583 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
584 rq->am.mode = priv->params.rx_cq_period_mode;
585
4415a031
TT		 586 rq->page_cache.head = 0;
587 rq->page_cache.tail = 0;
588
f62b8bb8
AV		 589 return 0;
590
591err_rq_wq_destroy:
97bc402d
DB		 592 if (rq->xdp_prog)
593 bpf_prog_put(rq->xdp_prog);
f62b8bb8
AV		 594 mlx5_wq_destroy(&rq->wq_ctrl);
595
596 return err;
597}
598
599static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
600{
4415a031
TT		 601 int i;
602
86994156
RS		 603 if (rq->xdp_prog)
604 bpf_prog_put(rq->xdp_prog);
605
461017cb
TT		 606 switch (rq->wq_type) {
607 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 608 mlx5e_rq_free_mpwqe_info(rq);
461017cb
TT		 609 break;
610 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca 611 kfree(rq->dma_info);
461017cb
TT		 612 }
613
4415a031
TT		 614 for (i = rq->page_cache.head; i != rq->page_cache.tail;
615 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
616 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
617
618 mlx5e_page_release(rq, dma_info, false);
619 }
f62b8bb8
AV		 620 mlx5_wq_destroy(&rq->wq_ctrl);
621}
622
623static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
624{
50cfa25a 625 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 626 struct mlx5_core_dev *mdev = priv->mdev;
627
628 void *in;
629 void *rqc;
630 void *wq;
631 int inlen;
632 int err;
633
634 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
635 sizeof(u64) * rq->wq_ctrl.buf.npages;
636 in = mlx5_vzalloc(inlen);
637 if (!in)
638 return -ENOMEM;
639
640 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
641 wq = MLX5_ADDR_OF(rqc, rqc, wq);
642
643 memcpy(rqc, param->rqc, sizeof(param->rqc));
644
97de9f31 645 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 646 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
36350114 647 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
f62b8bb8 648 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 649 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 650 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
651
652 mlx5_fill_page_array(&rq->wq_ctrl.buf,
653 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
654
7db22ffb 655 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 656
657 kvfree(in);
658
659 return err;
660}
661
36350114
GP		 662static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
663 int next_state)
f62b8bb8
AV		 664{
665 struct mlx5e_channel *c = rq->channel;
666 struct mlx5e_priv *priv = c->priv;
667 struct mlx5_core_dev *mdev = priv->mdev;
668
669 void *in;
670 void *rqc;
671 int inlen;
672 int err;
673
674 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
675 in = mlx5_vzalloc(inlen);
676 if (!in)
677 return -ENOMEM;
678
679 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
680
681 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
682 MLX5_SET(rqc, rqc, state, next_state);
683
7db22ffb 684 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 685
686 kvfree(in);
687
688 return err;
689}
690
36350114
GP		 691static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
692{
693 struct mlx5e_channel *c = rq->channel;
694 struct mlx5e_priv *priv = c->priv;
695 struct mlx5_core_dev *mdev = priv->mdev;
696
697 void *in;
698 void *rqc;
699 int inlen;
700 int err;
701
702 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
703 in = mlx5_vzalloc(inlen);
704 if (!in)
705 return -ENOMEM;
706
707 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
708
709 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 710 MLX5_SET64(modify_rq_in, in, modify_bitmask,
711 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 712 MLX5_SET(rqc, rqc, vsd, vsd);
713 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
714
715 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
716
717 kvfree(in);
718
719 return err;
720}
721
f62b8bb8
AV		 722static void mlx5e_disable_rq(struct mlx5e_rq *rq)
723{
50cfa25a 724 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 725}
726
727static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
728{
01c196a2 729 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 730 struct mlx5e_channel *c = rq->channel;
731 struct mlx5e_priv *priv = c->priv;
732 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 733
01c196a2 734 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 735 if (wq->cur_sz >= priv->params.min_rx_wqes)
736 return 0;
737
738 msleep(20);
739 }
740
741 return -ETIMEDOUT;
742}
743
f2fde18c
SM		 744static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
745{
746 struct mlx5_wq_ll *wq = &rq->wq;
747 struct mlx5e_rx_wqe *wqe;
748 __be16 wqe_ix_be;
749 u16 wqe_ix;
750
8484f9ed
SM		 751 /* UMR WQE (if in progress) is always at wq->head */
752 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
21c59685 753 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 754
f2fde18c
SM		 755 while (!mlx5_wq_ll_is_empty(wq)) {
756 wqe_ix_be = *wq->tail_next;
757 wqe_ix = be16_to_cpu(wqe_ix_be);
758 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
759 rq->dealloc_wqe(rq, wqe_ix);
760 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
761 &wqe->next.next_wqe_index);
762 }
763}
764
f62b8bb8
AV		 765static int mlx5e_open_rq(struct mlx5e_channel *c,
766 struct mlx5e_rq_param *param,
767 struct mlx5e_rq *rq)
768{
d3c9bc27
TT		 769 struct mlx5e_sq *sq = &c->icosq;
770 u16 pi = sq->pc & sq->wq.sz_m1;
f62b8bb8
AV		 771 int err;
772
773 err = mlx5e_create_rq(c, param, rq);
774 if (err)
775 return err;
776
777 err = mlx5e_enable_rq(rq, param);
778 if (err)
779 goto err_destroy_rq;
780
36350114 781 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8
AV		 782 if (err)
783 goto err_disable_rq;
784
cb3c7fd4
GR		 785 if (param->am_enabled)
786 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
787
f10b7cc7
SM		 788 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
789 sq->db.ico_wqe[pi].num_wqebbs = 1;
d3c9bc27 790 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 791
792 return 0;
793
794err_disable_rq:
795 mlx5e_disable_rq(rq);
796err_destroy_rq:
797 mlx5e_destroy_rq(rq);
798
799 return err;
800}
801
802static void mlx5e_close_rq(struct mlx5e_rq *rq)
803{
f2fde18c 804 set_bit(MLX5E_RQ_STATE_FLUSH, &rq->state);
f62b8bb8 805 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
cb3c7fd4
GR		 806 cancel_work_sync(&rq->am.work);
807
f62b8bb8 808 mlx5e_disable_rq(rq);
6cd392a0 809 mlx5e_free_rx_descs(rq);
f62b8bb8
AV		 810 mlx5e_destroy_rq(rq);
811}
812
b5503b99
SM		 813static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
814{
815 kfree(sq->db.xdp.di);
816 kfree(sq->db.xdp.wqe_info);
817}
818
819static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
820{
821 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
822
823 sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
824 GFP_KERNEL, numa);
825 sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
826 GFP_KERNEL, numa);
827 if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
828 mlx5e_free_sq_xdp_db(sq);
829 return -ENOMEM;
830 }
831
832 return 0;
833}
834
f10b7cc7 835static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
f62b8bb8 836{
f10b7cc7 837 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 838}
839
f10b7cc7
SM		 840static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
841{
842 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
843
844 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
845 GFP_KERNEL, numa);
846 if (!sq->db.ico_wqe)
847 return -ENOMEM;
848
849 return 0;
850}
851
852static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
853{
854 kfree(sq->db.txq.wqe_info);
855 kfree(sq->db.txq.dma_fifo);
856 kfree(sq->db.txq.skb);
857}
858
859static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
f62b8bb8
AV		 860{
861 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
862 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
863
f10b7cc7
SM		 864 sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
865 GFP_KERNEL, numa);
866 sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
867 GFP_KERNEL, numa);
868 sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
869 GFP_KERNEL, numa);
870 if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
871 mlx5e_free_sq_txq_db(sq);
f62b8bb8
AV		 872 return -ENOMEM;
873 }
874
875 sq->dma_fifo_mask = df_sz - 1;
876
877 return 0;
878}
879
f10b7cc7
SM		 880static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
881{
882 switch (sq->type) {
883 case MLX5E_SQ_TXQ:
884 mlx5e_free_sq_txq_db(sq);
885 break;
886 case MLX5E_SQ_ICO:
887 mlx5e_free_sq_ico_db(sq);
888 break;
b5503b99
SM		 889 case MLX5E_SQ_XDP:
890 mlx5e_free_sq_xdp_db(sq);
891 break;
f10b7cc7
SM		 892 }
893}
894
895static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
896{
897 switch (sq->type) {
898 case MLX5E_SQ_TXQ:
899 return mlx5e_alloc_sq_txq_db(sq, numa);
900 case MLX5E_SQ_ICO:
901 return mlx5e_alloc_sq_ico_db(sq, numa);
b5503b99
SM		 902 case MLX5E_SQ_XDP:
903 return mlx5e_alloc_sq_xdp_db(sq, numa);
f10b7cc7
SM		 904 }
905
906 return 0;
907}
908
b5503b99
SM		 909static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
910{
911 switch (sq_type) {
912 case MLX5E_SQ_ICO:
913 return MLX5E_ICOSQ_MAX_WQEBBS;
914 case MLX5E_SQ_XDP:
915 return MLX5E_XDP_TX_WQEBBS;
916 }
917 return MLX5_SEND_WQE_MAX_WQEBBS;
918}
919
f62b8bb8
AV		 920static int mlx5e_create_sq(struct mlx5e_channel *c,
921 int tc,
922 struct mlx5e_sq_param *param,
923 struct mlx5e_sq *sq)
924{
925 struct mlx5e_priv *priv = c->priv;
926 struct mlx5_core_dev *mdev = priv->mdev;
927
928 void *sqc = param->sqc;
929 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
930 int err;
931
f10b7cc7
SM		 932 sq->type = param->type;
933 sq->pdev = c->pdev;
934 sq->tstamp = &priv->tstamp;
935 sq->mkey_be = c->mkey_be;
936 sq->channel = c;
937 sq->tc = tc;
938
fd4782c2 939 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
f62b8bb8
AV		 940 if (err)
941 return err;
942
311c7c71
SM		 943 param->wq.db_numa_node = cpu_to_node(c->cpu);
944
f62b8bb8
AV		 945 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
946 &sq->wq_ctrl);
947 if (err)
948 goto err_unmap_free_uar;
949
950 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
0ba42241
ML		 951 if (sq->uar.bf_map) {
952 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
953 sq->uar_map = sq->uar.bf_map;
954 } else {
955 sq->uar_map = sq->uar.map;
956 }
f62b8bb8 957 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 958 sq->max_inline = param->max_inline;
cff92d7c 959 sq->min_inline_mode =
34e4e990 960 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT ?
cff92d7c 961 param->min_inline_mode : 0;
f62b8bb8 962
7ec0bb22
DC		 963 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
964 if (err)
f62b8bb8
AV		 965 goto err_sq_wq_destroy;
966
f10b7cc7 967 if (sq->type == MLX5E_SQ_TXQ) {
d3c9bc27
TT		 968 int txq_ix;
969
970 txq_ix = c->ix + tc * priv->params.num_channels;
971 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
972 priv->txq_to_sq_map[txq_ix] = sq;
973 }
f62b8bb8 974
b5503b99 975 sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
88a85f99 976 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
f62b8bb8
AV		 977
978 return 0;
979
980err_sq_wq_destroy:
981 mlx5_wq_destroy(&sq->wq_ctrl);
982
983err_unmap_free_uar:
984 mlx5_unmap_free_uar(mdev, &sq->uar);
985
986 return err;
987}
988
989static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
990{
991 struct mlx5e_channel *c = sq->channel;
992 struct mlx5e_priv *priv = c->priv;
993
994 mlx5e_free_sq_db(sq);
995 mlx5_wq_destroy(&sq->wq_ctrl);
996 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
997}
998
999static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1000{
1001 struct mlx5e_channel *c = sq->channel;
1002 struct mlx5e_priv *priv = c->priv;
1003 struct mlx5_core_dev *mdev = priv->mdev;
1004
1005 void *in;
1006 void *sqc;
1007 void *wq;
1008 int inlen;
1009 int err;
1010
1011 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1012 sizeof(u64) * sq->wq_ctrl.buf.npages;
1013 in = mlx5_vzalloc(inlen);
1014 if (!in)
1015 return -ENOMEM;
1016
1017 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1018 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1019
1020 memcpy(sqc, param->sqc, sizeof(param->sqc));
1021
f10b7cc7
SM		 1022 MLX5_SET(sqc, sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1023 0 : priv->tisn[sq->tc]);
d3c9bc27 1024 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
cff92d7c 1025 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
f62b8bb8 1026 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f10b7cc7 1027 MLX5_SET(sqc, sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
f62b8bb8
AV		 1028 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1029
1030 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1031 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1032 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 1033 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1034 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1035
1036 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1037 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1038
7db22ffb 1039 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 1040
1041 kvfree(in);
1042
1043 return err;
1044}
1045
507f0c81
YP		 1046static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1047 int next_state, bool update_rl, int rl_index)
f62b8bb8
AV		 1048{
1049 struct mlx5e_channel *c = sq->channel;
1050 struct mlx5e_priv *priv = c->priv;
1051 struct mlx5_core_dev *mdev = priv->mdev;
1052
1053 void *in;
1054 void *sqc;
1055 int inlen;
1056 int err;
1057
1058 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1059 in = mlx5_vzalloc(inlen);
1060 if (!in)
1061 return -ENOMEM;
1062
1063 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1064
1065 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1066 MLX5_SET(sqc, sqc, state, next_state);
507f0c81
YP		 1067 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1068 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1069 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
1070 }
f62b8bb8 1071
7db22ffb 1072 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 1073
1074 kvfree(in);
1075
1076 return err;
1077}
1078
1079static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1080{
1081 struct mlx5e_channel *c = sq->channel;
1082 struct mlx5e_priv *priv = c->priv;
1083 struct mlx5_core_dev *mdev = priv->mdev;
1084
7db22ffb 1085 mlx5_core_destroy_sq(mdev, sq->sqn);
507f0c81
YP		 1086 if (sq->rate_limit)
1087 mlx5_rl_remove_rate(mdev, sq->rate_limit);
f62b8bb8
AV		 1088}
1089
1090static int mlx5e_open_sq(struct mlx5e_channel *c,
1091 int tc,
1092 struct mlx5e_sq_param *param,
1093 struct mlx5e_sq *sq)
1094{
1095 int err;
1096
1097 err = mlx5e_create_sq(c, tc, param, sq);
1098 if (err)
1099 return err;
1100
1101 err = mlx5e_enable_sq(sq, param);
1102 if (err)
1103 goto err_destroy_sq;
1104
507f0c81
YP		 1105 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1106 false, 0);
f62b8bb8
AV		 1107 if (err)
1108 goto err_disable_sq;
1109
d3c9bc27 1110 if (sq->txq) {
d3c9bc27
TT		 1111 netdev_tx_reset_queue(sq->txq);
1112 netif_tx_start_queue(sq->txq);
1113 }
f62b8bb8
AV		 1114
1115 return 0;
1116
1117err_disable_sq:
1118 mlx5e_disable_sq(sq);
1119err_destroy_sq:
1120 mlx5e_destroy_sq(sq);
1121
1122 return err;
1123}
1124
1125static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1126{
1127 __netif_tx_lock_bh(txq);
1128 netif_tx_stop_queue(txq);
1129 __netif_tx_unlock_bh(txq);
1130}
1131
1132static void mlx5e_close_sq(struct mlx5e_sq *sq)
1133{
6e8dd6d6
SM		 1134 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
1135 /* prevent netif_tx_wake_queue */
1136 napi_synchronize(&sq->channel->napi);
29429f33 1137
d3c9bc27 1138 if (sq->txq) {
d3c9bc27 1139 netif_tx_disable_queue(sq->txq);
f62b8bb8 1140
6e8dd6d6 1141 /* last doorbell out, godspeed .. */
f10b7cc7
SM		 1142 if (mlx5e_sq_has_room_for(sq, 1)) {
1143 sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
d3c9bc27 1144 mlx5e_send_nop(sq, true);
f10b7cc7 1145 }
29429f33 1146 }
f62b8bb8 1147
f62b8bb8 1148 mlx5e_disable_sq(sq);
b5503b99 1149 mlx5e_free_sq_descs(sq);
f62b8bb8
AV		 1150 mlx5e_destroy_sq(sq);
1151}
1152
1153static int mlx5e_create_cq(struct mlx5e_channel *c,
1154 struct mlx5e_cq_param *param,
1155 struct mlx5e_cq *cq)
1156{
1157 struct mlx5e_priv *priv = c->priv;
1158 struct mlx5_core_dev *mdev = priv->mdev;
1159 struct mlx5_core_cq *mcq = &cq->mcq;
1160 int eqn_not_used;
0b6e26ce 1161 unsigned int irqn;
f62b8bb8
AV		 1162 int err;
1163 u32 i;
1164
311c7c71
SM		 1165 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1166 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 1167 param->eq_ix = c->ix;
1168
1169 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1170 &cq->wq_ctrl);
1171 if (err)
1172 return err;
1173
1174 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1175
1176 cq->napi = &c->napi;
1177
1178 mcq->cqe_sz = 64;
1179 mcq->set_ci_db = cq->wq_ctrl.db.db;
1180 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1181 *mcq->set_ci_db = 0;
1182 *mcq->arm_db = 0;
1183 mcq->vector = param->eq_ix;
1184 mcq->comp = mlx5e_completion_event;
1185 mcq->event = mlx5e_cq_error_event;
1186 mcq->irqn = irqn;
b50d292b 1187 mcq->uar = &mdev->mlx5e_res.cq_uar;
f62b8bb8
AV		 1188
1189 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1190 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1191
1192 cqe->op_own = 0xf1;
1193 }
1194
1195 cq->channel = c;
50cfa25a 1196 cq->priv = priv;
f62b8bb8
AV		 1197
1198 return 0;
1199}
1200
1201static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1202{
1203 mlx5_wq_destroy(&cq->wq_ctrl);
1204}
1205
1206static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1207{
50cfa25a 1208 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 1209 struct mlx5_core_dev *mdev = priv->mdev;
1210 struct mlx5_core_cq *mcq = &cq->mcq;
1211
1212 void *in;
1213 void *cqc;
1214 int inlen;
0b6e26ce 1215 unsigned int irqn_not_used;
f62b8bb8
AV		 1216 int eqn;
1217 int err;
1218
1219 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1220 sizeof(u64) * cq->wq_ctrl.buf.npages;
1221 in = mlx5_vzalloc(inlen);
1222 if (!in)
1223 return -ENOMEM;
1224
1225 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1226
1227 memcpy(cqc, param->cqc, sizeof(param->cqc));
1228
1229 mlx5_fill_page_array(&cq->wq_ctrl.buf,
1230 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1231
1232 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1233
9908aa29 1234 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8
AV		 1235 MLX5_SET(cqc, cqc, c_eqn, eqn);
1236 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1237 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 1238 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1239 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1240
1241 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1242
1243 kvfree(in);
1244
1245 if (err)
1246 return err;
1247
1248 mlx5e_cq_arm(cq);
1249
1250 return 0;
1251}
1252
1253static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1254{
50cfa25a 1255 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 1256 struct mlx5_core_dev *mdev = priv->mdev;
1257
1258 mlx5_core_destroy_cq(mdev, &cq->mcq);
1259}
1260
1261static int mlx5e_open_cq(struct mlx5e_channel *c,
1262 struct mlx5e_cq_param *param,
1263 struct mlx5e_cq *cq,
9908aa29 1264 struct mlx5e_cq_moder moderation)
f62b8bb8
AV		 1265{
1266 int err;
1267 struct mlx5e_priv *priv = c->priv;
1268 struct mlx5_core_dev *mdev = priv->mdev;
1269
1270 err = mlx5e_create_cq(c, param, cq);
1271 if (err)
1272 return err;
1273
1274 err = mlx5e_enable_cq(cq, param);
1275 if (err)
1276 goto err_destroy_cq;
1277
7524a5d8
GP		 1278 if (MLX5_CAP_GEN(mdev, cq_moderation))
1279 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
9908aa29
TT		 1280 moderation.usec,
1281 moderation.pkts);
f62b8bb8
AV		 1282 return 0;
1283
1284err_destroy_cq:
1285 mlx5e_destroy_cq(cq);
1286
1287 return err;
1288}
1289
1290static void mlx5e_close_cq(struct mlx5e_cq *cq)
1291{
1292 mlx5e_disable_cq(cq);
1293 mlx5e_destroy_cq(cq);
1294}
1295
1296static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1297{
1298 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1299}
1300
1301static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1302 struct mlx5e_channel_param *cparam)
1303{
1304 struct mlx5e_priv *priv = c->priv;
1305 int err;
1306 int tc;
1307
1308 for (tc = 0; tc < c->num_tc; tc++) {
1309 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
9908aa29 1310 priv->params.tx_cq_moderation);
f62b8bb8
AV		 1311 if (err)
1312 goto err_close_tx_cqs;
f62b8bb8
AV		 1313 }
1314
1315 return 0;
1316
1317err_close_tx_cqs:
1318 for (tc--; tc >= 0; tc--)
1319 mlx5e_close_cq(&c->sq[tc].cq);
1320
1321 return err;
1322}
1323
1324static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1325{
1326 int tc;
1327
1328 for (tc = 0; tc < c->num_tc; tc++)
1329 mlx5e_close_cq(&c->sq[tc].cq);
1330}
1331
1332static int mlx5e_open_sqs(struct mlx5e_channel *c,
1333 struct mlx5e_channel_param *cparam)
1334{
1335 int err;
1336 int tc;
1337
1338 for (tc = 0; tc < c->num_tc; tc++) {
1339 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1340 if (err)
1341 goto err_close_sqs;
1342 }
1343
1344 return 0;
1345
1346err_close_sqs:
1347 for (tc--; tc >= 0; tc--)
1348 mlx5e_close_sq(&c->sq[tc]);
1349
1350 return err;
1351}
1352
1353static void mlx5e_close_sqs(struct mlx5e_channel *c)
1354{
1355 int tc;
1356
1357 for (tc = 0; tc < c->num_tc; tc++)
1358 mlx5e_close_sq(&c->sq[tc]);
1359}
1360
5283af89 1361static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 1362{
1363 int i;
1364
6bfd390b 1365 for (i = 0; i < priv->profile->max_tc; i++)
5283af89
RS		 1366 priv->channeltc_to_txq_map[ix][i] =
1367 ix + i * priv->params.num_channels;
03289b88
SM		 1368}
1369
507f0c81
YP		 1370static int mlx5e_set_sq_maxrate(struct net_device *dev,
1371 struct mlx5e_sq *sq, u32 rate)
1372{
1373 struct mlx5e_priv *priv = netdev_priv(dev);
1374 struct mlx5_core_dev *mdev = priv->mdev;
1375 u16 rl_index = 0;
1376 int err;
1377
1378 if (rate == sq->rate_limit)
1379 /* nothing to do */
1380 return 0;
1381
1382 if (sq->rate_limit)
1383 /* remove current rl index to free space to next ones */
1384 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1385
1386 sq->rate_limit = 0;
1387
1388 if (rate) {
1389 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1390 if (err) {
1391 netdev_err(dev, "Failed configuring rate %u: %d\n",
1392 rate, err);
1393 return err;
1394 }
1395 }
1396
1397 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1398 MLX5_SQC_STATE_RDY, true, rl_index);
1399 if (err) {
1400 netdev_err(dev, "Failed configuring rate %u: %d\n",
1401 rate, err);
1402 /* remove the rate from the table */
1403 if (rate)
1404 mlx5_rl_remove_rate(mdev, rate);
1405 return err;
1406 }
1407
1408 sq->rate_limit = rate;
1409 return 0;
1410}
1411
1412static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1413{
1414 struct mlx5e_priv *priv = netdev_priv(dev);
1415 struct mlx5_core_dev *mdev = priv->mdev;
1416 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1417 int err = 0;
1418
1419 if (!mlx5_rl_is_supported(mdev)) {
1420 netdev_err(dev, "Rate limiting is not supported on this device\n");
1421 return -EINVAL;
1422 }
1423
1424 /* rate is given in Mb/sec, HW config is in Kb/sec */
1425 rate = rate << 10;
1426
1427 /* Check whether rate in valid range, 0 is always valid */
1428 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1429 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1430 return -ERANGE;
1431 }
1432
1433 mutex_lock(&priv->state_lock);
1434 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1435 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1436 if (!err)
1437 priv->tx_rates[index] = rate;
1438 mutex_unlock(&priv->state_lock);
1439
1440 return err;
1441}
1442
f62b8bb8
AV		 1443static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1444 struct mlx5e_channel_param *cparam,
1445 struct mlx5e_channel **cp)
1446{
9908aa29 1447 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
f62b8bb8 1448 struct net_device *netdev = priv->netdev;
cb3c7fd4 1449 struct mlx5e_cq_moder rx_cq_profile;
f62b8bb8
AV		 1450 int cpu = mlx5e_get_cpu(priv, ix);
1451 struct mlx5e_channel *c;
507f0c81 1452 struct mlx5e_sq *sq;
f62b8bb8 1453 int err;
507f0c81 1454 int i;
f62b8bb8
AV		 1455
1456 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1457 if (!c)
1458 return -ENOMEM;
1459
1460 c->priv = priv;
1461 c->ix = ix;
1462 c->cpu = cpu;
1463 c->pdev = &priv->mdev->pdev->dev;
1464 c->netdev = priv->netdev;
b50d292b 1465 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
a4418a6c 1466 c->num_tc = priv->params.num_tc;
d7a0ecab 1467 c->xdp = !!priv->xdp_prog;
f62b8bb8 1468
cb3c7fd4
GR		 1469 if (priv->params.rx_am_enabled)
1470 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1471 else
1472 rx_cq_profile = priv->params.rx_cq_moderation;
1473
5283af89 1474 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1475
f62b8bb8
AV		 1476 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1477
9908aa29 1478 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
f62b8bb8
AV		 1479 if (err)
1480 goto err_napi_del;
1481
d3c9bc27
TT		 1482 err = mlx5e_open_tx_cqs(c, cparam);
1483 if (err)
1484 goto err_close_icosq_cq;
1485
f62b8bb8 1486 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
cb3c7fd4 1487 rx_cq_profile);
f62b8bb8
AV		 1488 if (err)
1489 goto err_close_tx_cqs;
f62b8bb8 1490
d7a0ecab
SM		 1491 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1492 err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1493 priv->params.tx_cq_moderation) : 0;
1494 if (err)
1495 goto err_close_rx_cq;
1496
f62b8bb8
AV		 1497 napi_enable(&c->napi);
1498
d3c9bc27 1499 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1500 if (err)
1501 goto err_disable_napi;
1502
d3c9bc27
TT		 1503 err = mlx5e_open_sqs(c, cparam);
1504 if (err)
1505 goto err_close_icosq;
1506
507f0c81
YP		 1507 for (i = 0; i < priv->params.num_tc; i++) {
1508 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1509
1510 if (priv->tx_rates[txq_ix]) {
1511 sq = priv->txq_to_sq_map[txq_ix];
1512 mlx5e_set_sq_maxrate(priv->netdev, sq,
1513 priv->tx_rates[txq_ix]);
1514 }
1515 }
1516
d7a0ecab
SM		 1517 err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0;
1518 if (err)
1519 goto err_close_sqs;
b5503b99 1520
f62b8bb8
AV		 1521 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1522 if (err)
b5503b99 1523 goto err_close_xdp_sq;
f62b8bb8
AV		 1524
1525 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1526 *cp = c;
1527
1528 return 0;
b5503b99 1529err_close_xdp_sq:
d7a0ecab 1530 if (c->xdp)
87dc0255 1531 mlx5e_close_sq(&c->xdp_sq);
f62b8bb8
AV		 1532
1533err_close_sqs:
1534 mlx5e_close_sqs(c);
1535
d3c9bc27
TT		 1536err_close_icosq:
1537 mlx5e_close_sq(&c->icosq);
1538
f62b8bb8
AV		 1539err_disable_napi:
1540 napi_disable(&c->napi);
d7a0ecab
SM		 1541 if (c->xdp)
1542 mlx5e_close_cq(&c->xdp_sq.cq);
1543
1544err_close_rx_cq:
f62b8bb8
AV		 1545 mlx5e_close_cq(&c->rq.cq);
1546
1547err_close_tx_cqs:
1548 mlx5e_close_tx_cqs(c);
1549
d3c9bc27
TT		 1550err_close_icosq_cq:
1551 mlx5e_close_cq(&c->icosq.cq);
1552
f62b8bb8
AV		 1553err_napi_del:
1554 netif_napi_del(&c->napi);
1555 kfree(c);
1556
1557 return err;
1558}
1559
1560static void mlx5e_close_channel(struct mlx5e_channel *c)
1561{
1562 mlx5e_close_rq(&c->rq);
b5503b99
SM		 1563 if (c->xdp)
1564 mlx5e_close_sq(&c->xdp_sq);
f62b8bb8 1565 mlx5e_close_sqs(c);
d3c9bc27 1566 mlx5e_close_sq(&c->icosq);
f62b8bb8 1567 napi_disable(&c->napi);
b5503b99
SM		 1568 if (c->xdp)
1569 mlx5e_close_cq(&c->xdp_sq.cq);
f62b8bb8
AV		 1570 mlx5e_close_cq(&c->rq.cq);
1571 mlx5e_close_tx_cqs(c);
d3c9bc27 1572 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1573 netif_napi_del(&c->napi);
7ae92ae5 1574
f62b8bb8
AV		 1575 kfree(c);
1576}
1577
1578static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1579 struct mlx5e_rq_param *param)
1580{
1581 void *rqc = param->rqc;
1582 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1583
461017cb
TT		 1584 switch (priv->params.rq_wq_type) {
1585 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1586 MLX5_SET(wq, wq, log_wqe_num_of_strides,
d9d9f156 1587 priv->params.mpwqe_log_num_strides - 9);
461017cb 1588 MLX5_SET(wq, wq, log_wqe_stride_size,
d9d9f156 1589 priv->params.mpwqe_log_stride_sz - 6);
461017cb
TT		 1590 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1591 break;
1592 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1593 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1594 }
1595
f62b8bb8
AV		 1596 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1597 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1598 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
b50d292b 1599 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1600 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1601
311c7c71 1602 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8 1603 param->wq.linear = 1;
cb3c7fd4
GR		 1604
1605 param->am_enabled = priv->params.rx_am_enabled;
f62b8bb8
AV		 1606}
1607
556dd1b9
TT		 1608static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1609{
1610 void *rqc = param->rqc;
1611 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1612
1613 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1614 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1615}
1616
d3c9bc27
TT		 1617static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1618 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1619{
1620 void *sqc = param->sqc;
1621 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1622
f62b8bb8 1623 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1624 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1625
311c7c71 1626 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1627}
1628
1629static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1630 struct mlx5e_sq_param *param)
1631{
1632 void *sqc = param->sqc;
1633 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1634
1635 mlx5e_build_sq_param_common(priv, param);
1636 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1637
58d52291 1638 param->max_inline = priv->params.tx_max_inline;
cff92d7c 1639 param->min_inline_mode = priv->params.tx_min_inline_mode;
f10b7cc7 1640 param->type = MLX5E_SQ_TXQ;
f62b8bb8
AV		 1641}
1642
1643static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1644 struct mlx5e_cq_param *param)
1645{
1646 void *cqc = param->cqc;
1647
b50d292b 1648 MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
f62b8bb8
AV		 1649}
1650
1651static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1652 struct mlx5e_cq_param *param)
1653{
1654 void *cqc = param->cqc;
461017cb 1655 u8 log_cq_size;
f62b8bb8 1656
461017cb
TT		 1657 switch (priv->params.rq_wq_type) {
1658 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1659 log_cq_size = priv->params.log_rq_size +
d9d9f156 1660 priv->params.mpwqe_log_num_strides;
461017cb
TT		 1661 break;
1662 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1663 log_cq_size = priv->params.log_rq_size;
1664 }
1665
1666 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
7219ab34
TT		 1667 if (priv->params.rx_cqe_compress) {
1668 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1669 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1670 }
f62b8bb8
AV		 1671
1672 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1673
1674 param->cq_period_mode = priv->params.rx_cq_period_mode;
f62b8bb8
AV		 1675}
1676
1677static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1678 struct mlx5e_cq_param *param)
1679{
1680 void *cqc = param->cqc;
1681
d3c9bc27 1682 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1683
1684 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1685
1686 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1687}
1688
d3c9bc27
TT		 1689static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1690 struct mlx5e_cq_param *param,
1691 u8 log_wq_size)
1692{
1693 void *cqc = param->cqc;
1694
1695 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1696
1697 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1698
1699 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1700}
1701
1702static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1703 struct mlx5e_sq_param *param,
1704 u8 log_wq_size)
1705{
1706 void *sqc = param->sqc;
1707 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1708
1709 mlx5e_build_sq_param_common(priv, param);
1710
1711 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1712 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27 1713
f10b7cc7 1714 param->type = MLX5E_SQ_ICO;
d3c9bc27
TT		 1715}
1716
b5503b99
SM		 1717static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1718 struct mlx5e_sq_param *param)
1719{
1720 void *sqc = param->sqc;
1721 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1722
1723 mlx5e_build_sq_param_common(priv, param);
1724 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1725
1726 param->max_inline = priv->params.tx_max_inline;
1727 /* FOR XDP SQs will support only L2 inline mode */
1728 param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1729 param->type = MLX5E_SQ_XDP;
1730}
1731
6b87663f 1732static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
f62b8bb8 1733{
bc77b240 1734 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1735
f62b8bb8
AV		 1736 mlx5e_build_rq_param(priv, &cparam->rq);
1737 mlx5e_build_sq_param(priv, &cparam->sq);
b5503b99 1738 mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
d3c9bc27 1739 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1740 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1741 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1742 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1743}
1744
1745static int mlx5e_open_channels(struct mlx5e_priv *priv)
1746{
6b87663f 1747 struct mlx5e_channel_param *cparam;
a4418a6c 1748 int nch = priv->params.num_channels;
03289b88 1749 int err = -ENOMEM;
f62b8bb8
AV		 1750 int i;
1751 int j;
1752
a4418a6c
AS		 1753 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1754 GFP_KERNEL);
03289b88 1755
a4418a6c 1756 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1757 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1758
6b87663f
AB		 1759 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1760
1761 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
03289b88 1762 goto err_free_txq_to_sq_map;
f62b8bb8 1763
6b87663f
AB		 1764 mlx5e_build_channel_param(priv, cparam);
1765
a4418a6c 1766 for (i = 0; i < nch; i++) {
6b87663f 1767 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
f62b8bb8
AV		 1768 if (err)
1769 goto err_close_channels;
1770 }
1771
a4418a6c 1772 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1773 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1774 if (err)
1775 goto err_close_channels;
1776 }
1777
c3b7c5c9
MHY		 1778 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1779 * polling for inactive tx queues.
1780 */
1781 netif_tx_start_all_queues(priv->netdev);
1782
6b87663f 1783 kfree(cparam);
f62b8bb8
AV		 1784 return 0;
1785
1786err_close_channels:
1787 for (i--; i >= 0; i--)
1788 mlx5e_close_channel(priv->channel[i]);
1789
03289b88
SM		 1790err_free_txq_to_sq_map:
1791 kfree(priv->txq_to_sq_map);
f62b8bb8 1792 kfree(priv->channel);
6b87663f 1793 kfree(cparam);
f62b8bb8
AV		 1794
1795 return err;
1796}
1797
1798static void mlx5e_close_channels(struct mlx5e_priv *priv)
1799{
1800 int i;
1801
c3b7c5c9
MHY		 1802 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1803 * polling for inactive tx queues.
1804 */
1805 netif_tx_stop_all_queues(priv->netdev);
1806 netif_tx_disable(priv->netdev);
1807
f62b8bb8
AV		 1808 for (i = 0; i < priv->params.num_channels; i++)
1809 mlx5e_close_channel(priv->channel[i]);
1810
03289b88 1811 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1812 kfree(priv->channel);
1813}
1814
2be6967c
SM		 1815static int mlx5e_rx_hash_fn(int hfunc)
1816{
1817 return (hfunc == ETH_RSS_HASH_TOP) ?
1818 MLX5_RX_HASH_FN_TOEPLITZ :
1819 MLX5_RX_HASH_FN_INVERTED_XOR8;
1820}
1821
1822static int mlx5e_bits_invert(unsigned long a, int size)
1823{
1824 int inv = 0;
1825 int i;
1826
1827 for (i = 0; i < size; i++)
1828 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1829
1830 return inv;
1831}
1832
936896e9
AS		 1833static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1834{
1835 int i;
1836
1837 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1838 int ix = i;
1da36696 1839 u32 rqn;
936896e9
AS		 1840
1841 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1842 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1843
2d75b2bc 1844 ix = priv->params.indirection_rqt[ix];
1da36696
TT		 1845 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1846 priv->channel[ix]->rq.rqn :
1847 priv->drop_rq.rqn;
1848 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
936896e9
AS		 1849 }
1850}
1851
1da36696
TT		 1852static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1853 int ix)
4cbeaff5 1854{
1da36696
TT		 1855 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1856 priv->channel[ix]->rq.rqn :
1857 priv->drop_rq.rqn;
4cbeaff5 1858
1da36696 1859 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
4cbeaff5
AS		 1860}
1861
398f3351
HHZ		 1862static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1863 int ix, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 1864{
1865 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1866 void *rqtc;
1867 int inlen;
1868 int err;
1da36696 1869 u32 *in;
f62b8bb8 1870
f62b8bb8
AV		 1871 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1872 in = mlx5_vzalloc(inlen);
1873 if (!in)
1874 return -ENOMEM;
1875
1876 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1877
1878 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1879 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1880
1da36696
TT		 1881 if (sz > 1) /* RSS */
1882 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1883 else
1884 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2be6967c 1885
398f3351
HHZ		 1886 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1887 if (!err)
1888 rqt->enabled = true;
f62b8bb8
AV		 1889
1890 kvfree(in);
1da36696
TT		 1891 return err;
1892}
1893
cb67b832 1894void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 1895{
398f3351
HHZ		 1896 rqt->enabled = false;
1897 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 1898}
1899
6bfd390b
HHZ		 1900static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1901{
1902 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1903
1904 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1905}
1906
cb67b832 1907int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 1908{
398f3351 1909 struct mlx5e_rqt *rqt;
1da36696
TT		 1910 int err;
1911 int ix;
1912
6bfd390b 1913 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351
HHZ		 1914 rqt = &priv->direct_tir[ix].rqt;
1915 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1da36696
TT		 1916 if (err)
1917 goto err_destroy_rqts;
1918 }
1919
1920 return 0;
1921
1922err_destroy_rqts:
1923 for (ix--; ix >= 0; ix--)
398f3351 1924 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 1925
f62b8bb8
AV		 1926 return err;
1927}
1928
1da36696 1929int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
5c50368f
AS		 1930{
1931 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 1932 void *rqtc;
1933 int inlen;
1da36696 1934 u32 *in;
5c50368f
AS		 1935 int err;
1936
5c50368f
AS		 1937 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1938 in = mlx5_vzalloc(inlen);
1939 if (!in)
1940 return -ENOMEM;
1941
1942 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1943
1944 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1da36696
TT		 1945 if (sz > 1) /* RSS */
1946 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1947 else
1948 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
5c50368f
AS		 1949
1950 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1951
1da36696 1952 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 1953
1954 kvfree(in);
1955
1956 return err;
1957}
1958
40ab6a6e
AS		 1959static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1960{
1da36696
TT		 1961 u32 rqtn;
1962 int ix;
1963
398f3351
HHZ		 1964 if (priv->indir_rqt.enabled) {
1965 rqtn = priv->indir_rqt.rqtn;
1966 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1967 }
1968
1da36696 1969 for (ix = 0; ix < priv->params.num_channels; ix++) {
398f3351
HHZ		 1970 if (!priv->direct_tir[ix].rqt.enabled)
1971 continue;
1972 rqtn = priv->direct_tir[ix].rqt.rqtn;
1da36696
TT		 1973 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1974 }
40ab6a6e
AS		 1975}
1976
5c50368f
AS		 1977static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1978{
1979 if (!priv->params.lro_en)
1980 return;
1981
1982#define ROUGH_MAX_L2_L3_HDR_SZ 256
1983
1984 MLX5_SET(tirc, tirc, lro_enable_mask,
1985 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1986 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1987 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1988 (priv->params.lro_wqe_sz -
1989 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2b029556 1990 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
5c50368f
AS		 1991}
1992
bdfc028d
TT		 1993void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1994{
1995 MLX5_SET(tirc, tirc, rx_hash_fn,
1996 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1997 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1998 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1999 rx_hash_toeplitz_key);
2000 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2001 rx_hash_toeplitz_key);
2002
2003 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2004 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2005 }
2006}
2007
ab0394fe 2008static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2009{
2010 struct mlx5_core_dev *mdev = priv->mdev;
2011
2012 void *in;
2013 void *tirc;
2014 int inlen;
2015 int err;
ab0394fe 2016 int tt;
1da36696 2017 int ix;
5c50368f
AS		 2018
2019 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2020 in = mlx5_vzalloc(inlen);
2021 if (!in)
2022 return -ENOMEM;
2023
2024 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2025 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2026
2027 mlx5e_build_tir_ctx_lro(tirc, priv);
2028
1da36696 2029 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2030 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2031 inlen);
ab0394fe 2032 if (err)
1da36696 2033 goto free_in;
ab0394fe 2034 }
5c50368f 2035
6bfd390b 2036 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2037 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2038 in, inlen);
2039 if (err)
2040 goto free_in;
2041 }
2042
2043free_in:
5c50368f
AS		 2044 kvfree(in);
2045
2046 return err;
2047}
2048
cd255eff 2049static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2050{
40ab6a6e 2051 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 2052 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 2053 int err;
2054
cd255eff 2055 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2056 if (err)
2057 return err;
2058
cd255eff
SM		 2059 /* Update vport context MTU */
2060 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2061 return 0;
2062}
40ab6a6e 2063
cd255eff
SM		 2064static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2065{
2066 struct mlx5_core_dev *mdev = priv->mdev;
2067 u16 hw_mtu = 0;
2068 int err;
40ab6a6e 2069
cd255eff
SM		 2070 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2071 if (err || !hw_mtu) /* fallback to port oper mtu */
2072 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2073
2074 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2075}
2076
2077static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2078{
2079 struct mlx5e_priv *priv = netdev_priv(netdev);
2080 u16 mtu;
2081 int err;
2082
2083 err = mlx5e_set_mtu(priv, netdev->mtu);
2084 if (err)
2085 return err;
40ab6a6e 2086
cd255eff
SM		 2087 mlx5e_query_mtu(priv, &mtu);
2088 if (mtu != netdev->mtu)
2089 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2090 __func__, mtu, netdev->mtu);
40ab6a6e 2091
cd255eff 2092 netdev->mtu = mtu;
40ab6a6e
AS		 2093 return 0;
2094}
2095
08fb1dac
SM		 2096static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2097{
2098 struct mlx5e_priv *priv = netdev_priv(netdev);
2099 int nch = priv->params.num_channels;
2100 int ntc = priv->params.num_tc;
2101 int tc;
2102
2103 netdev_reset_tc(netdev);
2104
2105 if (ntc == 1)
2106 return;
2107
2108 netdev_set_num_tc(netdev, ntc);
2109
7ccdd084
RS		 2110 /* Map netdev TCs to offset 0
2111 * We have our own UP to TXQ mapping for QoS
2112 */
08fb1dac 2113 for (tc = 0; tc < ntc; tc++)
7ccdd084 2114 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2115}
2116
40ab6a6e
AS		 2117int mlx5e_open_locked(struct net_device *netdev)
2118{
2119 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 2120 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e
AS		 2121 int num_txqs;
2122 int err;
2123
2124 set_bit(MLX5E_STATE_OPENED, &priv->state);
2125
08fb1dac
SM		 2126 mlx5e_netdev_set_tcs(netdev);
2127
40ab6a6e
AS		 2128 num_txqs = priv->params.num_channels * priv->params.num_tc;
2129 netif_set_real_num_tx_queues(netdev, num_txqs);
2130 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2131
40ab6a6e
AS		 2132 err = mlx5e_open_channels(priv);
2133 if (err) {
2134 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2135 __func__, err);
343b29f3 2136 goto err_clear_state_opened_flag;
40ab6a6e
AS		 2137 }
2138
724b2aa1 2139 err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
66189961
TT		 2140 if (err) {
2141 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2142 __func__, err);
2143 goto err_close_channels;
2144 }
2145
40ab6a6e 2146 mlx5e_redirect_rqts(priv);
ce89ef36 2147 mlx5e_update_carrier(priv);
ef9814de 2148 mlx5e_timestamp_init(priv);
5a7b27eb
MG		 2149#ifdef CONFIG_RFS_ACCEL
2150 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2151#endif
cb67b832
HHZ		 2152 if (priv->profile->update_stats)
2153 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2154
cb67b832
HHZ		 2155 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2156 err = mlx5e_add_sqs_fwd_rules(priv);
2157 if (err)
2158 goto err_close_channels;
2159 }
9b37b07f 2160 return 0;
343b29f3 2161
66189961
TT		 2162err_close_channels:
2163 mlx5e_close_channels(priv);
343b29f3
AS		 2164err_clear_state_opened_flag:
2165 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2166 return err;
40ab6a6e
AS		 2167}
2168
cb67b832 2169int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2170{
2171 struct mlx5e_priv *priv = netdev_priv(netdev);
2172 int err;
2173
2174 mutex_lock(&priv->state_lock);
2175 err = mlx5e_open_locked(netdev);
2176 mutex_unlock(&priv->state_lock);
2177
2178 return err;
2179}
2180
2181int mlx5e_close_locked(struct net_device *netdev)
2182{
2183 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 2184 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e 2185
a1985740
AS		 2186 /* May already be CLOSED in case a previous configuration operation
2187 * (e.g RX/TX queue size change) that involves close&open failed.
2188 */
2189 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2190 return 0;
2191
40ab6a6e
AS		 2192 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2193
cb67b832
HHZ		 2194 if (MLX5_CAP_GEN(mdev, vport_group_manager))
2195 mlx5e_remove_sqs_fwd_rules(priv);
2196
ef9814de 2197 mlx5e_timestamp_cleanup(priv);
40ab6a6e 2198 netif_carrier_off(priv->netdev);
ce89ef36 2199 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 2200 mlx5e_close_channels(priv);
2201
2202 return 0;
2203}
2204
cb67b832 2205int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2206{
2207 struct mlx5e_priv *priv = netdev_priv(netdev);
2208 int err;
2209
26e59d80
MHY		 2210 if (!netif_device_present(netdev))
2211 return -ENODEV;
2212
40ab6a6e
AS		 2213 mutex_lock(&priv->state_lock);
2214 err = mlx5e_close_locked(netdev);
2215 mutex_unlock(&priv->state_lock);
2216
2217 return err;
2218}
2219
2220static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2221 struct mlx5e_rq *rq,
2222 struct mlx5e_rq_param *param)
2223{
2224 struct mlx5_core_dev *mdev = priv->mdev;
2225 void *rqc = param->rqc;
2226 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2227 int err;
2228
2229 param->wq.db_numa_node = param->wq.buf_numa_node;
2230
2231 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2232 &rq->wq_ctrl);
2233 if (err)
2234 return err;
2235
2236 rq->priv = priv;
2237
2238 return 0;
2239}
2240
2241static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2242 struct mlx5e_cq *cq,
2243 struct mlx5e_cq_param *param)
2244{
2245 struct mlx5_core_dev *mdev = priv->mdev;
2246 struct mlx5_core_cq *mcq = &cq->mcq;
2247 int eqn_not_used;
0b6e26ce 2248 unsigned int irqn;
40ab6a6e
AS		 2249 int err;
2250
2251 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2252 &cq->wq_ctrl);
2253 if (err)
2254 return err;
2255
2256 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2257
2258 mcq->cqe_sz = 64;
2259 mcq->set_ci_db = cq->wq_ctrl.db.db;
2260 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2261 *mcq->set_ci_db = 0;
2262 *mcq->arm_db = 0;
2263 mcq->vector = param->eq_ix;
2264 mcq->comp = mlx5e_completion_event;
2265 mcq->event = mlx5e_cq_error_event;
2266 mcq->irqn = irqn;
b50d292b 2267 mcq->uar = &mdev->mlx5e_res.cq_uar;
40ab6a6e
AS		 2268
2269 cq->priv = priv;
2270
2271 return 0;
2272}
2273
2274static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2275{
2276 struct mlx5e_cq_param cq_param;
2277 struct mlx5e_rq_param rq_param;
2278 struct mlx5e_rq *rq = &priv->drop_rq;
2279 struct mlx5e_cq *cq = &priv->drop_rq.cq;
2280 int err;
2281
2282 memset(&cq_param, 0, sizeof(cq_param));
2283 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 2284 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 2285
2286 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2287 if (err)
2288 return err;
2289
2290 err = mlx5e_enable_cq(cq, &cq_param);
2291 if (err)
2292 goto err_destroy_cq;
2293
2294 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2295 if (err)
2296 goto err_disable_cq;
2297
2298 err = mlx5e_enable_rq(rq, &rq_param);
2299 if (err)
2300 goto err_destroy_rq;
2301
2302 return 0;
2303
2304err_destroy_rq:
2305 mlx5e_destroy_rq(&priv->drop_rq);
2306
2307err_disable_cq:
2308 mlx5e_disable_cq(&priv->drop_rq.cq);
2309
2310err_destroy_cq:
2311 mlx5e_destroy_cq(&priv->drop_rq.cq);
2312
2313 return err;
2314}
2315
2316static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2317{
2318 mlx5e_disable_rq(&priv->drop_rq);
2319 mlx5e_destroy_rq(&priv->drop_rq);
2320 mlx5e_disable_cq(&priv->drop_rq.cq);
2321 mlx5e_destroy_cq(&priv->drop_rq.cq);
2322}
2323
2324static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2325{
2326 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 2327 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2328 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2329
08fb1dac 2330 MLX5_SET(tisc, tisc, prio, tc << 1);
b50d292b 2331 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2332
2333 if (mlx5_lag_is_lacp_owner(mdev))
2334 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2335
40ab6a6e
AS		 2336 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2337}
2338
2339static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2340{
2341 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2342}
2343
cb67b832 2344int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2345{
2346 int err;
2347 int tc;
2348
6bfd390b 2349 for (tc = 0; tc < priv->profile->max_tc; tc++) {
40ab6a6e
AS		 2350 err = mlx5e_create_tis(priv, tc);
2351 if (err)
2352 goto err_close_tises;
2353 }
2354
2355 return 0;
2356
2357err_close_tises:
2358 for (tc--; tc >= 0; tc--)
2359 mlx5e_destroy_tis(priv, tc);
2360
2361 return err;
2362}
2363
cb67b832 2364void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2365{
2366 int tc;
2367
6bfd390b 2368 for (tc = 0; tc < priv->profile->max_tc; tc++)
40ab6a6e
AS		 2369 mlx5e_destroy_tis(priv, tc);
2370}
2371
1da36696
TT		 2372static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2373 enum mlx5e_traffic_types tt)
f62b8bb8
AV		 2374{
2375 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2376
b50d292b 2377 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2378
5a6f8aef
AS		 2379#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2380 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 2381
5a6f8aef
AS		 2382#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2383 MLX5_HASH_FIELD_SEL_DST_IP |\
2384 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2385 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 2386
a741749f
AS		 2387#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2388 MLX5_HASH_FIELD_SEL_DST_IP |\
2389 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2390
5c50368f 2391 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 2392
4cbeaff5 2393 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2394 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
1da36696 2395 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 2396
2397 switch (tt) {
2398 case MLX5E_TT_IPV4_TCP:
2399 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2400 MLX5_L3_PROT_TYPE_IPV4);
2401 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2402 MLX5_L4_PROT_TYPE_TCP);
2403 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2404 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2405 break;
2406
2407 case MLX5E_TT_IPV6_TCP:
2408 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2409 MLX5_L3_PROT_TYPE_IPV6);
2410 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2411 MLX5_L4_PROT_TYPE_TCP);
2412 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2413 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2414 break;
2415
2416 case MLX5E_TT_IPV4_UDP:
2417 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2418 MLX5_L3_PROT_TYPE_IPV4);
2419 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2420 MLX5_L4_PROT_TYPE_UDP);
2421 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2422 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2423 break;
2424
2425 case MLX5E_TT_IPV6_UDP:
2426 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2427 MLX5_L3_PROT_TYPE_IPV6);
2428 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2429 MLX5_L4_PROT_TYPE_UDP);
2430 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2431 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2432 break;
2433
a741749f
AS		 2434 case MLX5E_TT_IPV4_IPSEC_AH:
2435 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2436 MLX5_L3_PROT_TYPE_IPV4);
2437 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2438 MLX5_HASH_IP_IPSEC_SPI);
2439 break;
2440
2441 case MLX5E_TT_IPV6_IPSEC_AH:
2442 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2443 MLX5_L3_PROT_TYPE_IPV6);
2444 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2445 MLX5_HASH_IP_IPSEC_SPI);
2446 break;
2447
2448 case MLX5E_TT_IPV4_IPSEC_ESP:
2449 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2450 MLX5_L3_PROT_TYPE_IPV4);
2451 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2452 MLX5_HASH_IP_IPSEC_SPI);
2453 break;
2454
2455 case MLX5E_TT_IPV6_IPSEC_ESP:
2456 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2457 MLX5_L3_PROT_TYPE_IPV6);
2458 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2459 MLX5_HASH_IP_IPSEC_SPI);
2460 break;
2461
f62b8bb8
AV		 2462 case MLX5E_TT_IPV4:
2463 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2464 MLX5_L3_PROT_TYPE_IPV4);
2465 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2466 MLX5_HASH_IP);
2467 break;
2468
2469 case MLX5E_TT_IPV6:
2470 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2471 MLX5_L3_PROT_TYPE_IPV6);
2472 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2473 MLX5_HASH_IP);
2474 break;
1da36696
TT		 2475 default:
2476 WARN_ONCE(true,
2477 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
f62b8bb8
AV		 2478 }
2479}
2480
1da36696
TT		 2481static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2482 u32 rqtn)
f62b8bb8 2483{
b50d292b 2484 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696
TT		 2485
2486 mlx5e_build_tir_ctx_lro(tirc, priv);
2487
2488 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2489 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2490 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2491}
2492
6bfd390b 2493static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2494{
724b2aa1 2495 struct mlx5e_tir *tir;
f62b8bb8
AV		 2496 void *tirc;
2497 int inlen;
2498 int err;
1da36696 2499 u32 *in;
1da36696 2500 int tt;
f62b8bb8
AV		 2501
2502 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2503 in = mlx5_vzalloc(inlen);
2504 if (!in)
2505 return -ENOMEM;
2506
1da36696
TT		 2507 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2508 memset(in, 0, inlen);
724b2aa1 2509 tir = &priv->indir_tir[tt];
1da36696
TT		 2510 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2511 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
724b2aa1 2512 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2513 if (err)
40ab6a6e 2514 goto err_destroy_tirs;
f62b8bb8
AV		 2515 }
2516
6bfd390b
HHZ		 2517 kvfree(in);
2518
2519 return 0;
2520
2521err_destroy_tirs:
2522 for (tt--; tt >= 0; tt--)
2523 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2524
2525 kvfree(in);
2526
2527 return err;
2528}
2529
cb67b832 2530int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2531{
2532 int nch = priv->profile->max_nch(priv->mdev);
2533 struct mlx5e_tir *tir;
2534 void *tirc;
2535 int inlen;
2536 int err;
2537 u32 *in;
2538 int ix;
2539
2540 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2541 in = mlx5_vzalloc(inlen);
2542 if (!in)
2543 return -ENOMEM;
2544
1da36696
TT		 2545 for (ix = 0; ix < nch; ix++) {
2546 memset(in, 0, inlen);
724b2aa1 2547 tir = &priv->direct_tir[ix];
1da36696
TT		 2548 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2549 mlx5e_build_direct_tir_ctx(priv, tirc,
398f3351 2550 priv->direct_tir[ix].rqt.rqtn);
724b2aa1 2551 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2552 if (err)
2553 goto err_destroy_ch_tirs;
2554 }
2555
2556 kvfree(in);
2557
f62b8bb8
AV		 2558 return 0;
2559
1da36696
TT		 2560err_destroy_ch_tirs:
2561 for (ix--; ix >= 0; ix--)
724b2aa1 2562 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2563
1da36696 2564 kvfree(in);
f62b8bb8
AV		 2565
2566 return err;
2567}
2568
6bfd390b 2569static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2570{
2571 int i;
2572
1da36696 2573 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2574 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2575}
2576
cb67b832 2577void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2578{
2579 int nch = priv->profile->max_nch(priv->mdev);
2580 int i;
2581
2582 for (i = 0; i < nch; i++)
2583 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2584}
2585
36350114
GP		 2586int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2587{
2588 int err = 0;
2589 int i;
2590
2591 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2592 return 0;
2593
2594 for (i = 0; i < priv->params.num_channels; i++) {
2595 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2596 if (err)
2597 return err;
2598 }
2599
2600 return 0;
2601}
2602
08fb1dac
SM		 2603static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2604{
2605 struct mlx5e_priv *priv = netdev_priv(netdev);
2606 bool was_opened;
2607 int err = 0;
2608
2609 if (tc && tc != MLX5E_MAX_NUM_TC)
2610 return -EINVAL;
2611
2612 mutex_lock(&priv->state_lock);
2613
2614 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2615 if (was_opened)
2616 mlx5e_close_locked(priv->netdev);
2617
2618 priv->params.num_tc = tc ? tc : 1;
2619
2620 if (was_opened)
2621 err = mlx5e_open_locked(priv->netdev);
2622
2623 mutex_unlock(&priv->state_lock);
2624
2625 return err;
2626}
2627
2628static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2629 __be16 proto, struct tc_to_netdev *tc)
2630{
e8f887ac
AV		 2631 struct mlx5e_priv *priv = netdev_priv(dev);
2632
2633 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2634 goto mqprio;
2635
2636 switch (tc->type) {
e3a2b7ed
AV		 2637 case TC_SETUP_CLSFLOWER:
2638 switch (tc->cls_flower->command) {
2639 case TC_CLSFLOWER_REPLACE:
2640 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2641 case TC_CLSFLOWER_DESTROY:
2642 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 2643 case TC_CLSFLOWER_STATS:
2644 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 2645 }
e8f887ac
AV		 2646 default:
2647 return -EOPNOTSUPP;
2648 }
2649
2650mqprio:
67ba422e 2651 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2652 return -EINVAL;
2653
2654 return mlx5e_setup_tc(dev, tc->tc);
2655}
2656
370bad0f 2657static struct rtnl_link_stats64 *
f62b8bb8
AV		 2658mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2659{
2660 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2661 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2662 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2663 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2664
370bad0f
OG		 2665 if (mlx5e_is_uplink_rep(priv)) {
2666 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
2667 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
2668 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
2669 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
2670 } else {
2671 stats->rx_packets = sstats->rx_packets;
2672 stats->rx_bytes = sstats->rx_bytes;
2673 stats->tx_packets = sstats->tx_packets;
2674 stats->tx_bytes = sstats->tx_bytes;
2675 stats->tx_dropped = sstats->tx_queue_dropped;
2676 }
269e6b3a
GP		 2677
2678 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 2679
2680 stats->rx_length_errors =
9218b44d
GP		 2681 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2682 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2683 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2684 stats->rx_crc_errors =
9218b44d
GP		 2685 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2686 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2687 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2688 stats->tx_carrier_errors =
9218b44d 2689 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2690 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2691 stats->rx_frame_errors;
2692 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2693
2694 /* vport multicast also counts packets that are dropped due to steering
2695 * or rx out of buffer
2696 */
9218b44d
GP		 2697 stats->multicast =
2698 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 2699
2700 return stats;
2701}
2702
2703static void mlx5e_set_rx_mode(struct net_device *dev)
2704{
2705 struct mlx5e_priv *priv = netdev_priv(dev);
2706
7bb29755 2707 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2708}
2709
2710static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2711{
2712 struct mlx5e_priv *priv = netdev_priv(netdev);
2713 struct sockaddr *saddr = addr;
2714
2715 if (!is_valid_ether_addr(saddr->sa_data))
2716 return -EADDRNOTAVAIL;
2717
2718 netif_addr_lock_bh(netdev);
2719 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2720 netif_addr_unlock_bh(netdev);
2721
7bb29755 2722 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2723
2724 return 0;
2725}
2726
0e405443
GP		 2727#define MLX5E_SET_FEATURE(netdev, feature, enable) \
2728 do { \
2729 if (enable) \
2730 netdev->features |= feature; \
2731 else \
2732 netdev->features &= ~feature; \
2733 } while (0)
2734
2735typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2736
2737static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 2738{
2739 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 2740 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2741 int err;
f62b8bb8
AV		 2742
2743 mutex_lock(&priv->state_lock);
f62b8bb8 2744
0e405443
GP		 2745 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2746 mlx5e_close_locked(priv->netdev);
98e81b0a 2747
0e405443
GP		 2748 priv->params.lro_en = enable;
2749 err = mlx5e_modify_tirs_lro(priv);
2750 if (err) {
2751 netdev_err(netdev, "lro modify failed, %d\n", err);
2752 priv->params.lro_en = !enable;
98e81b0a 2753 }
f62b8bb8 2754
0e405443
GP		 2755 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2756 mlx5e_open_locked(priv->netdev);
2757
9b37b07f
AS		 2758 mutex_unlock(&priv->state_lock);
2759
0e405443
GP		 2760 return err;
2761}
2762
2763static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2764{
2765 struct mlx5e_priv *priv = netdev_priv(netdev);
2766
2767 if (enable)
2768 mlx5e_enable_vlan_filter(priv);
2769 else
2770 mlx5e_disable_vlan_filter(priv);
2771
2772 return 0;
2773}
2774
2775static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2776{
2777 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 2778
0e405443 2779 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 2780 netdev_err(netdev,
2781 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2782 return -EINVAL;
2783 }
2784
0e405443
GP		 2785 return 0;
2786}
2787
94cb1ebb
EBE		 2788static int set_feature_rx_all(struct net_device *netdev, bool enable)
2789{
2790 struct mlx5e_priv *priv = netdev_priv(netdev);
2791 struct mlx5_core_dev *mdev = priv->mdev;
2792
2793 return mlx5_set_port_fcs(mdev, !enable);
2794}
2795
36350114
GP		 2796static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2797{
2798 struct mlx5e_priv *priv = netdev_priv(netdev);
2799 int err;
2800
2801 mutex_lock(&priv->state_lock);
2802
2803 priv->params.vlan_strip_disable = !enable;
2804 err = mlx5e_modify_rqs_vsd(priv, !enable);
2805 if (err)
2806 priv->params.vlan_strip_disable = enable;
2807
2808 mutex_unlock(&priv->state_lock);
2809
2810 return err;
2811}
2812
45bf454a
MG		 2813#ifdef CONFIG_RFS_ACCEL
2814static int set_feature_arfs(struct net_device *netdev, bool enable)
2815{
2816 struct mlx5e_priv *priv = netdev_priv(netdev);
2817 int err;
2818
2819 if (enable)
2820 err = mlx5e_arfs_enable(priv);
2821 else
2822 err = mlx5e_arfs_disable(priv);
2823
2824 return err;
2825}
2826#endif
2827
0e405443
GP		 2828static int mlx5e_handle_feature(struct net_device *netdev,
2829 netdev_features_t wanted_features,
2830 netdev_features_t feature,
2831 mlx5e_feature_handler feature_handler)
2832{
2833 netdev_features_t changes = wanted_features ^ netdev->features;
2834 bool enable = !!(wanted_features & feature);
2835 int err;
2836
2837 if (!(changes & feature))
2838 return 0;
2839
2840 err = feature_handler(netdev, enable);
2841 if (err) {
2842 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2843 enable ? "Enable" : "Disable", feature, err);
2844 return err;
2845 }
2846
2847 MLX5E_SET_FEATURE(netdev, feature, enable);
2848 return 0;
2849}
2850
2851static int mlx5e_set_features(struct net_device *netdev,
2852 netdev_features_t features)
2853{
2854 int err;
2855
2856 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2857 set_feature_lro);
2858 err |= mlx5e_handle_feature(netdev, features,
2859 NETIF_F_HW_VLAN_CTAG_FILTER,
2860 set_feature_vlan_filter);
2861 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2862 set_feature_tc_num_filters);
94cb1ebb
EBE		 2863 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2864 set_feature_rx_all);
36350114
GP		 2865 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2866 set_feature_rx_vlan);
45bf454a
MG		 2867#ifdef CONFIG_RFS_ACCEL
2868 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2869 set_feature_arfs);
2870#endif
0e405443
GP		 2871
2872 return err ? -EINVAL : 0;
f62b8bb8
AV		 2873}
2874
2875static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2876{
2877 struct mlx5e_priv *priv = netdev_priv(netdev);
98e81b0a 2878 bool was_opened;
98e81b0a 2879 int err = 0;
506753b0 2880 bool reset;
f62b8bb8 2881
f62b8bb8 2882 mutex_lock(&priv->state_lock);
98e81b0a 2883
506753b0
TT		 2884 reset = !priv->params.lro_en &&
2885 (priv->params.rq_wq_type !=
2886 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2887
98e81b0a 2888 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
506753b0 2889 if (was_opened && reset)
98e81b0a
AS		 2890 mlx5e_close_locked(netdev);
2891
f62b8bb8 2892 netdev->mtu = new_mtu;
13f9bba7 2893 mlx5e_set_dev_port_mtu(netdev);
98e81b0a 2894
506753b0 2895 if (was_opened && reset)
98e81b0a
AS		 2896 err = mlx5e_open_locked(netdev);
2897
f62b8bb8
AV		 2898 mutex_unlock(&priv->state_lock);
2899
2900 return err;
2901}
2902
ef9814de
EBE		 2903static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2904{
2905 switch (cmd) {
2906 case SIOCSHWTSTAMP:
2907 return mlx5e_hwstamp_set(dev, ifr);
2908 case SIOCGHWTSTAMP:
2909 return mlx5e_hwstamp_get(dev, ifr);
2910 default:
2911 return -EOPNOTSUPP;
2912 }
2913}
2914
66e49ded
SM		 2915static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2916{
2917 struct mlx5e_priv *priv = netdev_priv(dev);
2918 struct mlx5_core_dev *mdev = priv->mdev;
2919
2920 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2921}
2922
79aab093
MS		 2923static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2924 __be16 vlan_proto)
66e49ded
SM		 2925{
2926 struct mlx5e_priv *priv = netdev_priv(dev);
2927 struct mlx5_core_dev *mdev = priv->mdev;
2928
79aab093
MS		 2929 if (vlan_proto != htons(ETH_P_8021Q))
2930 return -EPROTONOSUPPORT;
2931
66e49ded
SM		 2932 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2933 vlan, qos);
2934}
2935
f942380c
MHY		 2936static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2937{
2938 struct mlx5e_priv *priv = netdev_priv(dev);
2939 struct mlx5_core_dev *mdev = priv->mdev;
2940
2941 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2942}
2943
1edc57e2
MHY		 2944static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2945{
2946 struct mlx5e_priv *priv = netdev_priv(dev);
2947 struct mlx5_core_dev *mdev = priv->mdev;
2948
2949 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2950}
bd77bf1c
MHY		 2951
2952static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2953 int max_tx_rate)
2954{
2955 struct mlx5e_priv *priv = netdev_priv(dev);
2956 struct mlx5_core_dev *mdev = priv->mdev;
2957
2958 if (min_tx_rate)
2959 return -EOPNOTSUPP;
2960
2961 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
2962 max_tx_rate);
2963}
2964
66e49ded
SM		 2965static int mlx5_vport_link2ifla(u8 esw_link)
2966{
2967 switch (esw_link) {
2968 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2969 return IFLA_VF_LINK_STATE_DISABLE;
2970 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2971 return IFLA_VF_LINK_STATE_ENABLE;
2972 }
2973 return IFLA_VF_LINK_STATE_AUTO;
2974}
2975
2976static int mlx5_ifla_link2vport(u8 ifla_link)
2977{
2978 switch (ifla_link) {
2979 case IFLA_VF_LINK_STATE_DISABLE:
2980 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2981 case IFLA_VF_LINK_STATE_ENABLE:
2982 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2983 }
2984 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2985}
2986
2987static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2988 int link_state)
2989{
2990 struct mlx5e_priv *priv = netdev_priv(dev);
2991 struct mlx5_core_dev *mdev = priv->mdev;
2992
2993 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2994 mlx5_ifla_link2vport(link_state));
2995}
2996
2997static int mlx5e_get_vf_config(struct net_device *dev,
2998 int vf, struct ifla_vf_info *ivi)
2999{
3000 struct mlx5e_priv *priv = netdev_priv(dev);
3001 struct mlx5_core_dev *mdev = priv->mdev;
3002 int err;
3003
3004 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3005 if (err)
3006 return err;
3007 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3008 return 0;
3009}
3010
3011static int mlx5e_get_vf_stats(struct net_device *dev,
3012 int vf, struct ifla_vf_stats *vf_stats)
3013{
3014 struct mlx5e_priv *priv = netdev_priv(dev);
3015 struct mlx5_core_dev *mdev = priv->mdev;
3016
3017 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3018 vf_stats);
3019}
3020
4a25730e
HHZ		 3021void mlx5e_add_vxlan_port(struct net_device *netdev,
3022 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3023{
3024 struct mlx5e_priv *priv = netdev_priv(netdev);
3025
974c3f30
AD		 3026 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3027 return;
3028
b3f63c3d
MF		 3029 if (!mlx5e_vxlan_allowed(priv->mdev))
3030 return;
3031
974c3f30 3032 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3033}
3034
4a25730e
HHZ		 3035void mlx5e_del_vxlan_port(struct net_device *netdev,
3036 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3037{
3038 struct mlx5e_priv *priv = netdev_priv(netdev);
3039
974c3f30
AD		 3040 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3041 return;
3042
b3f63c3d
MF		 3043 if (!mlx5e_vxlan_allowed(priv->mdev))
3044 return;
3045
974c3f30 3046 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3047}
3048
3049static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3050 struct sk_buff *skb,
3051 netdev_features_t features)
3052{
3053 struct udphdr *udph;
3054 u16 proto;
3055 u16 port = 0;
3056
3057 switch (vlan_get_protocol(skb)) {
3058 case htons(ETH_P_IP):
3059 proto = ip_hdr(skb)->protocol;
3060 break;
3061 case htons(ETH_P_IPV6):
3062 proto = ipv6_hdr(skb)->nexthdr;
3063 break;
3064 default:
3065 goto out;
3066 }
3067
3068 if (proto == IPPROTO_UDP) {
3069 udph = udp_hdr(skb);
3070 port = be16_to_cpu(udph->dest);
3071 }
3072
3073 /* Verify if UDP port is being offloaded by HW */
3074 if (port && mlx5e_vxlan_lookup_port(priv, port))
3075 return features;
3076
3077out:
3078 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3079 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3080}
3081
3082static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3083 struct net_device *netdev,
3084 netdev_features_t features)
3085{
3086 struct mlx5e_priv *priv = netdev_priv(netdev);
3087
3088 features = vlan_features_check(skb, features);
3089 features = vxlan_features_check(skb, features);
3090
3091 /* Validate if the tunneled packet is being offloaded by HW */
3092 if (skb->encapsulation &&
3093 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3094 return mlx5e_vxlan_features_check(priv, skb, features);
3095
3096 return features;
3097}
3098
3947ca18
DJ		 3099static void mlx5e_tx_timeout(struct net_device *dev)
3100{
3101 struct mlx5e_priv *priv = netdev_priv(dev);
3102 bool sched_work = false;
3103 int i;
3104
3105 netdev_err(dev, "TX timeout detected\n");
3106
3107 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3108 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3109
2c1ccc99 3110 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3111 continue;
3112 sched_work = true;
6e8dd6d6 3113 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
3947ca18
DJ		 3114 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3115 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3116 }
3117
3118 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3119 schedule_work(&priv->tx_timeout_work);
3120}
3121
86994156
RS		 3122static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3123{
3124 struct mlx5e_priv *priv = netdev_priv(netdev);
3125 struct bpf_prog *old_prog;
3126 int err = 0;
3127 bool reset, was_opened;
3128 int i;
3129
3130 mutex_lock(&priv->state_lock);
3131
3132 if ((netdev->features & NETIF_F_LRO) && prog) {
3133 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3134 err = -EINVAL;
3135 goto unlock;
3136 }
3137
3138 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3139 /* no need for full reset when exchanging programs */
3140 reset = (!priv->xdp_prog || !prog);
3141
3142 if (was_opened && reset)
3143 mlx5e_close_locked(netdev);
c54c0629
DB		 3144 if (was_opened && !reset) {
3145 /* num_channels is invariant here, so we can take the
3146 * batched reference right upfront.
3147 */
3148 prog = bpf_prog_add(prog, priv->params.num_channels);
3149 if (IS_ERR(prog)) {
3150 err = PTR_ERR(prog);
3151 goto unlock;
3152 }
3153 }
86994156 3154
c54c0629
DB		 3155 /* exchange programs, extra prog reference we got from caller
3156 * as long as we don't fail from this point onwards.
3157 */
86994156 3158 old_prog = xchg(&priv->xdp_prog, prog);
86994156
RS		 3159 if (old_prog)
3160 bpf_prog_put(old_prog);
3161
3162 if (reset) /* change RQ type according to priv->xdp_prog */
3163 mlx5e_set_rq_priv_params(priv);
3164
3165 if (was_opened && reset)
3166 mlx5e_open_locked(netdev);
3167
3168 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3169 goto unlock;
3170
3171 /* exchanging programs w/o reset, we update ref counts on behalf
3172 * of the channels RQs here.
3173 */
86994156
RS		 3174 for (i = 0; i < priv->params.num_channels; i++) {
3175 struct mlx5e_channel *c = priv->channel[i];
3176
3177 set_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3178 napi_synchronize(&c->napi);
3179 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3180
3181 old_prog = xchg(&c->rq.xdp_prog, prog);
3182
3183 clear_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3184 /* napi_schedule in case we have missed anything */
3185 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3186 napi_schedule(&c->napi);
3187
3188 if (old_prog)
3189 bpf_prog_put(old_prog);
3190 }
3191
3192unlock:
3193 mutex_unlock(&priv->state_lock);
3194 return err;
3195}
3196
3197static bool mlx5e_xdp_attached(struct net_device *dev)
3198{
3199 struct mlx5e_priv *priv = netdev_priv(dev);
3200
3201 return !!priv->xdp_prog;
3202}
3203
3204static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3205{
3206 switch (xdp->command) {
3207 case XDP_SETUP_PROG:
3208 return mlx5e_xdp_set(dev, xdp->prog);
3209 case XDP_QUERY_PROG:
3210 xdp->prog_attached = mlx5e_xdp_attached(dev);
3211 return 0;
3212 default:
3213 return -EINVAL;
3214 }
3215}
3216
80378384
CO		 3217#ifdef CONFIG_NET_POLL_CONTROLLER
3218/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3219 * reenabling interrupts.
3220 */
3221static void mlx5e_netpoll(struct net_device *dev)
3222{
3223 struct mlx5e_priv *priv = netdev_priv(dev);
3224 int i;
3225
3226 for (i = 0; i < priv->params.num_channels; i++)
3227 napi_schedule(&priv->channel[i]->napi);
3228}
3229#endif
3230
b0eed40e 3231static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 3232 .ndo_open = mlx5e_open,
3233 .ndo_stop = mlx5e_close,
3234 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3235 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3236 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3237 .ndo_get_stats64 = mlx5e_get_stats,
3238 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3239 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3240 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3241 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3242 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 3243 .ndo_change_mtu = mlx5e_change_mtu,
3244 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3245 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 3246#ifdef CONFIG_RFS_ACCEL
3247 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3248#endif
3947ca18 3249 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3250 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3251#ifdef CONFIG_NET_POLL_CONTROLLER
3252 .ndo_poll_controller = mlx5e_netpoll,
3253#endif
b0eed40e
SM		 3254};
3255
3256static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3257 .ndo_open = mlx5e_open,
3258 .ndo_stop = mlx5e_close,
3259 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3260 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3261 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 3262 .ndo_get_stats64 = mlx5e_get_stats,
3263 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3264 .ndo_set_mac_address = mlx5e_set_mac,
3265 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3266 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3267 .ndo_set_features = mlx5e_set_features,
3268 .ndo_change_mtu = mlx5e_change_mtu,
3269 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 3270 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3271 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 3272 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 3273 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3274#ifdef CONFIG_RFS_ACCEL
3275 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3276#endif
b0eed40e
SM		 3277 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3278 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3279 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3280 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3281 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3282 .ndo_get_vf_config = mlx5e_get_vf_config,
3283 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3284 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 3285 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3286 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3287#ifdef CONFIG_NET_POLL_CONTROLLER
3288 .ndo_poll_controller = mlx5e_netpoll,
3289#endif
370bad0f
OG		 3290 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3291 .ndo_get_offload_stats = mlx5e_get_offload_stats,
f62b8bb8
AV		 3292};
3293
3294static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3295{
3296 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3297 return -ENOTSUPP;
3298 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3299 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3300 !MLX5_CAP_ETH(mdev, csum_cap) ||
3301 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3302 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3303 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3304 MLX5_CAP_FLOWTABLE(mdev,
3305 flow_table_properties_nic_receive.max_ft_level)
3306 < 3) {
f62b8bb8
AV		 3307 mlx5_core_warn(mdev,
3308 "Not creating net device, some required device capabilities are missing\n");
3309 return -ENOTSUPP;
3310 }
66189961
TT		 3311 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3312 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 3313 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3314 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 3315
f62b8bb8
AV		 3316 return 0;
3317}
3318
58d52291
AS		 3319u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3320{
3321 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3322
3323 return bf_buf_size -
3324 sizeof(struct mlx5e_tx_wqe) +
3325 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3326}
3327
08fb1dac
SM		 3328#ifdef CONFIG_MLX5_CORE_EN_DCB
3329static void mlx5e_ets_init(struct mlx5e_priv *priv)
3330{
820c2c5e 3331 struct ieee_ets ets;
08fb1dac
SM		 3332 int i;
3333
820c2c5e
HN		 3334 if (!MLX5_CAP_GEN(priv->mdev, ets))
3335 return;
3336
3337 memset(&ets, 0, sizeof(ets));
3338 ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
3339 for (i = 0; i < ets.ets_cap; i++) {
3340 ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
3341 ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
3342 ets.prio_tc[i] = i;
08fb1dac
SM		 3343 }
3344
820c2c5e
HN		 3345 memcpy(priv->dcbx.tc_tsa, ets.tc_tsa, sizeof(ets.tc_tsa));
3346
08fb1dac 3347 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
820c2c5e
HN		 3348 ets.prio_tc[0] = 1;
3349 ets.prio_tc[1] = 0;
3350
3351 mlx5e_dcbnl_ieee_setets_core(priv, &ets);
08fb1dac
SM		 3352}
3353#endif
3354
d8c9660d
TT		 3355void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3356 u32 *indirection_rqt, int len,
85082dba
TT		 3357 int num_channels)
3358{
d8c9660d
TT		 3359 int node = mdev->priv.numa_node;
3360 int node_num_of_cores;
85082dba
TT		 3361 int i;
3362
d8c9660d
TT		 3363 if (node == -1)
3364 node = first_online_node;
3365
3366 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3367
3368 if (node_num_of_cores)
3369 num_channels = min_t(int, num_channels, node_num_of_cores);
3370
85082dba
TT		 3371 for (i = 0; i < len; i++)
3372 indirection_rqt[i] = i % num_channels;
3373}
3374
b797a684
SM		 3375static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3376{
3377 enum pcie_link_width width;
3378 enum pci_bus_speed speed;
3379 int err = 0;
3380
3381 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3382 if (err)
3383 return err;
3384
3385 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3386 return -EINVAL;
3387
3388 switch (speed) {
3389 case PCIE_SPEED_2_5GT:
3390 *pci_bw = 2500 * width;
3391 break;
3392 case PCIE_SPEED_5_0GT:
3393 *pci_bw = 5000 * width;
3394 break;
3395 case PCIE_SPEED_8_0GT:
3396 *pci_bw = 8000 * width;
3397 break;
3398 default:
3399 return -EINVAL;
3400 }
3401
3402 return 0;
3403}
3404
3405static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3406{
3407 return (link_speed && pci_bw &&
3408 (pci_bw < 40000) && (pci_bw < link_speed));
3409}
3410
9908aa29
TT		 3411void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3412{
3413 params->rx_cq_period_mode = cq_period_mode;
3414
3415 params->rx_cq_moderation.pkts =
3416 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3417 params->rx_cq_moderation.usec =
3418 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3419
3420 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3421 params->rx_cq_moderation.usec =
3422 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3423}
3424
cff92d7c
HHZ		 3425static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3426 u8 *min_inline_mode)
3427{
3428 switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
34e4e990 3429 case MLX5_CAP_INLINE_MODE_L2:
cff92d7c
HHZ		 3430 *min_inline_mode = MLX5_INLINE_MODE_L2;
3431 break;
34e4e990
RD		 3432 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3433 mlx5_query_nic_vport_min_inline(mdev, 0, min_inline_mode);
cff92d7c 3434 break;
34e4e990 3435 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
cff92d7c
HHZ		 3436 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3437 break;
3438 }
3439}
3440
2b029556
SM		 3441u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3442{
3443 int i;
3444
3445 /* The supported periods are organized in ascending order */
3446 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3447 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3448 break;
3449
3450 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3451}
3452
6bfd390b
HHZ		 3453static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3454 struct net_device *netdev,
127ea380
HHZ		 3455 const struct mlx5e_profile *profile,
3456 void *ppriv)
f62b8bb8
AV		 3457{
3458 struct mlx5e_priv *priv = netdev_priv(netdev);
b797a684
SM		 3459 u32 link_speed = 0;
3460 u32 pci_bw = 0;
cb3c7fd4
GR		 3461 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3462 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3463 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8 3464
2fc4bfb7
SM		 3465 priv->mdev = mdev;
3466 priv->netdev = netdev;
3467 priv->params.num_channels = profile->max_nch(mdev);
3468 priv->profile = profile;
3469 priv->ppriv = ppriv;
3470
2b029556
SM		 3471 priv->params.lro_timeout =
3472 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3473
2fc4bfb7 3474 priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3475
b797a684
SM		 3476 /* set CQE compression */
3477 priv->params.rx_cqe_compress_admin = false;
3478 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3479 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3480 mlx5e_get_max_linkspeed(mdev, &link_speed);
3481 mlx5e_get_pci_bw(mdev, &pci_bw);
3482 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3483 link_speed, pci_bw);
3484 priv->params.rx_cqe_compress_admin =
3485 cqe_compress_heuristic(link_speed, pci_bw);
3486 }
b797a684
SM		 3487 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3488
2fc4bfb7
SM		 3489 mlx5e_set_rq_priv_params(priv);
3490 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
461017cb 3491 priv->params.lro_en = true;
9908aa29 3492
cb3c7fd4
GR		 3493 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3494 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
9908aa29
TT		 3495
3496 priv->params.tx_cq_moderation.usec =
f62b8bb8 3497 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
9908aa29 3498 priv->params.tx_cq_moderation.pkts =
f62b8bb8 3499 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 3500 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
cff92d7c 3501 mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
f62b8bb8 3502 priv->params.num_tc = 1;
2be6967c 3503 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 3504
57afead5
AS		 3505 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3506 sizeof(priv->params.toeplitz_hash_key));
3507
d8c9660d 3508 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
6bfd390b 3509 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
2d75b2bc 3510
e4b85508
SM		 3511 priv->params.lro_wqe_sz =
3512 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3513 /* Extra room needed for build_skb */
3514 MLX5_RX_HEADROOM -
3515 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
f62b8bb8 3516
9908aa29
TT		 3517 /* Initialize pflags */
3518 MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3519 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3520
f62b8bb8
AV		 3521 mutex_init(&priv->state_lock);
3522
3523 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3524 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3525 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3526 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3527}
3528
3529static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3530{
3531 struct mlx5e_priv *priv = netdev_priv(netdev);
3532
e1d7d349 3533 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3534 if (is_zero_ether_addr(netdev->dev_addr) &&
3535 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3536 eth_hw_addr_random(netdev);
3537 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3538 }
f62b8bb8
AV		 3539}
3540
cb67b832
HHZ		 3541static const struct switchdev_ops mlx5e_switchdev_ops = {
3542 .switchdev_port_attr_get = mlx5e_attr_get,
3543};
3544
6bfd390b 3545static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3546{
3547 struct mlx5e_priv *priv = netdev_priv(netdev);
3548 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3549 bool fcs_supported;
3550 bool fcs_enabled;
f62b8bb8
AV		 3551
3552 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3553
08fb1dac 3554 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3555 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac 3556#ifdef CONFIG_MLX5_CORE_EN_DCB
80653f73
HN		 3557 if (MLX5_CAP_GEN(mdev, qos))
3558 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac
SM		 3559#endif
3560 } else {
b0eed40e 3561 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3562 }
66e49ded 3563
f62b8bb8
AV		 3564 netdev->watchdog_timeo = 15 * HZ;
3565
3566 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3567
12be4b21 3568 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3569 netdev->vlan_features |= NETIF_F_IP_CSUM;
3570 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3571 netdev->vlan_features |= NETIF_F_GRO;
3572 netdev->vlan_features |= NETIF_F_TSO;
3573 netdev->vlan_features |= NETIF_F_TSO6;
3574 netdev->vlan_features |= NETIF_F_RXCSUM;
3575 netdev->vlan_features |= NETIF_F_RXHASH;
3576
3577 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3578 netdev->vlan_features |= NETIF_F_LRO;
3579
3580 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3581 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3582 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3583 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3584
b3f63c3d 3585 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3586 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3587 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3588 NETIF_F_GSO_PARTIAL;
b3f63c3d 3589 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3590 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3591 netdev->hw_enc_features |= NETIF_F_TSO;
3592 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3593 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3594 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3595 NETIF_F_GSO_PARTIAL;
3596 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3597 }
3598
94cb1ebb
EBE		 3599 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3600
3601 if (fcs_supported)
3602 netdev->hw_features |= NETIF_F_RXALL;
3603
f62b8bb8
AV		 3604 netdev->features = netdev->hw_features;
3605 if (!priv->params.lro_en)
3606 netdev->features &= ~NETIF_F_LRO;
3607
94cb1ebb
EBE		 3608 if (fcs_enabled)
3609 netdev->features &= ~NETIF_F_RXALL;
3610
e8f887ac
AV		 3611#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3612 if (FT_CAP(flow_modify_en) &&
3613 FT_CAP(modify_root) &&
3614 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3615 FT_CAP(flow_table_modify)) {
3616 netdev->hw_features |= NETIF_F_HW_TC;
3617#ifdef CONFIG_RFS_ACCEL
3618 netdev->hw_features |= NETIF_F_NTUPLE;
3619#endif
3620 }
e8f887ac 3621
f62b8bb8
AV		 3622 netdev->features |= NETIF_F_HIGHDMA;
3623
3624 netdev->priv_flags |= IFF_UNICAST_FLT;
3625
3626 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 3627
3628#ifdef CONFIG_NET_SWITCHDEV
3629 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3630 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3631#endif
f62b8bb8
AV		 3632}
3633
593cf338
RS		 3634static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3635{
3636 struct mlx5_core_dev *mdev = priv->mdev;
3637 int err;
3638
3639 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3640 if (err) {
3641 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3642 priv->q_counter = 0;
3643 }
3644}
3645
3646static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3647{
3648 if (!priv->q_counter)
3649 return;
3650
3651 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3652}
3653
bc77b240
TT		 3654static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3655{
3656 struct mlx5_core_dev *mdev = priv->mdev;
fe4c988b
SM		 3657 u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3658 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
ec22eb53
SM		 3659 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3660 void *mkc;
3661 u32 *in;
bc77b240
TT		 3662 int err;
3663
3664 in = mlx5_vzalloc(inlen);
3665 if (!in)
3666 return -ENOMEM;
3667
ec22eb53 3668 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
bc77b240 3669
fe4c988b
SM		 3670 npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3671
ec22eb53
SM		 3672 MLX5_SET(mkc, mkc, free, 1);
3673 MLX5_SET(mkc, mkc, umr_en, 1);
3674 MLX5_SET(mkc, mkc, lw, 1);
3675 MLX5_SET(mkc, mkc, lr, 1);
3676 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
bc77b240 3677
ec22eb53
SM		 3678 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3679 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3680 MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3681 MLX5_SET(mkc, mkc, translations_octword_size,
6abdd5f5 3682 MLX5_MTT_OCTW(npages));
ec22eb53 3683 MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
bc77b240 3684
ec22eb53 3685 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
bc77b240 3686
ec22eb53 3687 kvfree(in);
bc77b240
TT		 3688 return err;
3689}
3690
6bfd390b
HHZ		 3691static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3692 struct net_device *netdev,
127ea380
HHZ		 3693 const struct mlx5e_profile *profile,
3694 void *ppriv)
6bfd390b
HHZ		 3695{
3696 struct mlx5e_priv *priv = netdev_priv(netdev);
3697
127ea380 3698 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 3699 mlx5e_build_nic_netdev(netdev);
3700 mlx5e_vxlan_init(priv);
3701}
3702
3703static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3704{
127ea380
HHZ		 3705 struct mlx5_core_dev *mdev = priv->mdev;
3706 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3707
6bfd390b 3708 mlx5e_vxlan_cleanup(priv);
127ea380
HHZ		 3709
3710 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3711 mlx5_eswitch_unregister_vport_rep(esw, 0);
a055c19b
DB		 3712
3713 if (priv->xdp_prog)
3714 bpf_prog_put(priv->xdp_prog);
6bfd390b
HHZ		 3715}
3716
3717static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3718{
3719 struct mlx5_core_dev *mdev = priv->mdev;
3720 int err;
3721 int i;
3722
3723 err = mlx5e_create_indirect_rqts(priv);
3724 if (err) {
3725 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3726 return err;
3727 }
3728
3729 err = mlx5e_create_direct_rqts(priv);
3730 if (err) {
3731 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3732 goto err_destroy_indirect_rqts;
3733 }
3734
3735 err = mlx5e_create_indirect_tirs(priv);
3736 if (err) {
3737 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3738 goto err_destroy_direct_rqts;
3739 }
3740
3741 err = mlx5e_create_direct_tirs(priv);
3742 if (err) {
3743 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3744 goto err_destroy_indirect_tirs;
3745 }
3746
3747 err = mlx5e_create_flow_steering(priv);
3748 if (err) {
3749 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3750 goto err_destroy_direct_tirs;
3751 }
3752
3753 err = mlx5e_tc_init(priv);
3754 if (err)
3755 goto err_destroy_flow_steering;
3756
3757 return 0;
3758
3759err_destroy_flow_steering:
3760 mlx5e_destroy_flow_steering(priv);
3761err_destroy_direct_tirs:
3762 mlx5e_destroy_direct_tirs(priv);
3763err_destroy_indirect_tirs:
3764 mlx5e_destroy_indirect_tirs(priv);
3765err_destroy_direct_rqts:
3766 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3767 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3768err_destroy_indirect_rqts:
3769 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3770 return err;
3771}
3772
3773static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3774{
3775 int i;
3776
3777 mlx5e_tc_cleanup(priv);
3778 mlx5e_destroy_flow_steering(priv);
3779 mlx5e_destroy_direct_tirs(priv);
3780 mlx5e_destroy_indirect_tirs(priv);
3781 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3782 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3783 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3784}
3785
3786static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3787{
3788 int err;
3789
3790 err = mlx5e_create_tises(priv);
3791 if (err) {
3792 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3793 return err;
3794 }
3795
3796#ifdef CONFIG_MLX5_CORE_EN_DCB
820c2c5e 3797 mlx5e_ets_init(priv);
6bfd390b
HHZ		 3798#endif
3799 return 0;
3800}
3801
3802static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3803{
3804 struct net_device *netdev = priv->netdev;
3805 struct mlx5_core_dev *mdev = priv->mdev;
127ea380
HHZ		 3806 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3807 struct mlx5_eswitch_rep rep;
6bfd390b 3808
7907f23a
AH		 3809 mlx5_lag_add(mdev, netdev);
3810
6bfd390b
HHZ		 3811 if (mlx5e_vxlan_allowed(mdev)) {
3812 rtnl_lock();
3813 udp_tunnel_get_rx_info(netdev);
3814 rtnl_unlock();
3815 }
3816
3817 mlx5e_enable_async_events(priv);
3818 queue_work(priv->wq, &priv->set_rx_mode_work);
127ea380
HHZ		 3819
3820 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
dbe413e3 3821 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
cb67b832
HHZ		 3822 rep.load = mlx5e_nic_rep_load;
3823 rep.unload = mlx5e_nic_rep_unload;
9deb2241 3824 rep.vport = FDB_UPLINK_VPORT;
127ea380 3825 rep.priv_data = priv;
9deb2241 3826 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
127ea380 3827 }
6bfd390b
HHZ		 3828}
3829
3830static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3831{
3832 queue_work(priv->wq, &priv->set_rx_mode_work);
3833 mlx5e_disable_async_events(priv);
7907f23a 3834 mlx5_lag_remove(priv->mdev);
6bfd390b
HHZ		 3835}
3836
3837static const struct mlx5e_profile mlx5e_nic_profile = {
3838 .init = mlx5e_nic_init,
3839 .cleanup = mlx5e_nic_cleanup,
3840 .init_rx = mlx5e_init_nic_rx,
3841 .cleanup_rx = mlx5e_cleanup_nic_rx,
3842 .init_tx = mlx5e_init_nic_tx,
3843 .cleanup_tx = mlx5e_cleanup_nic_tx,
3844 .enable = mlx5e_nic_enable,
3845 .disable = mlx5e_nic_disable,
3846 .update_stats = mlx5e_update_stats,
3847 .max_nch = mlx5e_get_max_num_channels,
3848 .max_tc = MLX5E_MAX_NUM_TC,
3849};
3850
26e59d80
MHY		 3851struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3852 const struct mlx5e_profile *profile,
3853 void *ppriv)
f62b8bb8 3854{
26e59d80 3855 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 3856 struct net_device *netdev;
3857 struct mlx5e_priv *priv;
f62b8bb8 3858
08fb1dac 3859 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 3860 nch * profile->max_tc,
08fb1dac 3861 nch);
f62b8bb8
AV		 3862 if (!netdev) {
3863 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3864 return NULL;
3865 }
3866
127ea380 3867 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 3868
3869 netif_carrier_off(netdev);
3870
3871 priv = netdev_priv(netdev);
3872
7bb29755
MF		 3873 priv->wq = create_singlethread_workqueue("mlx5e");
3874 if (!priv->wq)
26e59d80
MHY		 3875 goto err_cleanup_nic;
3876
3877 return netdev;
3878
3879err_cleanup_nic:
3880 profile->cleanup(priv);
3881 free_netdev(netdev);
3882
3883 return NULL;
3884}
3885
3886int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3887{
3888 const struct mlx5e_profile *profile;
3889 struct mlx5e_priv *priv;
b80f71f5 3890 u16 max_mtu;
26e59d80
MHY		 3891 int err;
3892
3893 priv = netdev_priv(netdev);
3894 profile = priv->profile;
3895 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 3896
bc77b240
TT		 3897 err = mlx5e_create_umr_mkey(priv);
3898 if (err) {
3899 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
26e59d80 3900 goto out;
bc77b240
TT		 3901 }
3902
6bfd390b
HHZ		 3903 err = profile->init_tx(priv);
3904 if (err)
bc77b240 3905 goto err_destroy_umr_mkey;
5c50368f
AS		 3906
3907 err = mlx5e_open_drop_rq(priv);
3908 if (err) {
3909 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 3910 goto err_cleanup_tx;
5c50368f
AS		 3911 }
3912
6bfd390b
HHZ		 3913 err = profile->init_rx(priv);
3914 if (err)
5c50368f 3915 goto err_close_drop_rq;
5c50368f 3916
593cf338
RS		 3917 mlx5e_create_q_counter(priv);
3918
33cfaaa8 3919 mlx5e_init_l2_addr(priv);
5c50368f 3920
b80f71f5
JW		 3921 /* MTU range: 68 - hw-specific max */
3922 netdev->min_mtu = ETH_MIN_MTU;
3923 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
3924 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
3925
13f9bba7
SM		 3926 mlx5e_set_dev_port_mtu(netdev);
3927
6bfd390b
HHZ		 3928 if (profile->enable)
3929 profile->enable(priv);
f62b8bb8 3930
26e59d80
MHY		 3931 rtnl_lock();
3932 if (netif_running(netdev))
3933 mlx5e_open(netdev);
3934 netif_device_attach(netdev);
3935 rtnl_unlock();
f62b8bb8 3936
26e59d80 3937 return 0;
5c50368f
AS		 3938
3939err_close_drop_rq:
3940 mlx5e_close_drop_rq(priv);
3941
6bfd390b
HHZ		 3942err_cleanup_tx:
3943 profile->cleanup_tx(priv);
5c50368f 3944
bc77b240
TT		 3945err_destroy_umr_mkey:
3946 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3947
26e59d80
MHY		 3948out:
3949 return err;
f62b8bb8
AV		 3950}
3951
127ea380
HHZ		 3952static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3953{
3954 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3955 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3956 int vport;
dbe413e3 3957 u8 mac[ETH_ALEN];
127ea380
HHZ		 3958
3959 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3960 return;
3961
dbe413e3
HHZ		 3962 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3963
127ea380
HHZ		 3964 for (vport = 1; vport < total_vfs; vport++) {
3965 struct mlx5_eswitch_rep rep;
3966
cb67b832
HHZ		 3967 rep.load = mlx5e_vport_rep_load;
3968 rep.unload = mlx5e_vport_rep_unload;
127ea380 3969 rep.vport = vport;
dbe413e3 3970 ether_addr_copy(rep.hw_id, mac);
9deb2241 3971 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
127ea380
HHZ		 3972 }
3973}
3974
26e59d80
MHY		 3975void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3976{
3977 struct mlx5e_priv *priv = netdev_priv(netdev);
3978 const struct mlx5e_profile *profile = priv->profile;
3979
3980 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3981 if (profile->disable)
3982 profile->disable(priv);
3983
3984 flush_workqueue(priv->wq);
3985
3986 rtnl_lock();
3987 if (netif_running(netdev))
3988 mlx5e_close(netdev);
3989 netif_device_detach(netdev);
3990 rtnl_unlock();
3991
3992 mlx5e_destroy_q_counter(priv);
3993 profile->cleanup_rx(priv);
3994 mlx5e_close_drop_rq(priv);
3995 profile->cleanup_tx(priv);
3996 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3997 cancel_delayed_work_sync(&priv->update_stats_work);
3998}
3999
4000/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4001 * hardware contexts and to connect it to the current netdev.
4002 */
4003static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4004{
4005 struct mlx5e_priv *priv = vpriv;
4006 struct net_device *netdev = priv->netdev;
4007 int err;
4008
4009 if (netif_device_present(netdev))
4010 return 0;
4011
4012 err = mlx5e_create_mdev_resources(mdev);
4013 if (err)
4014 return err;
4015
4016 err = mlx5e_attach_netdev(mdev, netdev);
4017 if (err) {
4018 mlx5e_destroy_mdev_resources(mdev);
4019 return err;
4020 }
4021
4022 return 0;
4023}
4024
4025static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4026{
4027 struct mlx5e_priv *priv = vpriv;
4028 struct net_device *netdev = priv->netdev;
4029
4030 if (!netif_device_present(netdev))
4031 return;
4032
4033 mlx5e_detach_netdev(mdev, netdev);
4034 mlx5e_destroy_mdev_resources(mdev);
4035}
4036
b50d292b
HHZ		 4037static void *mlx5e_add(struct mlx5_core_dev *mdev)
4038{
127ea380 4039 struct mlx5_eswitch *esw = mdev->priv.eswitch;
26e59d80 4040 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
127ea380 4041 void *ppriv = NULL;
26e59d80
MHY		 4042 void *priv;
4043 int vport;
4044 int err;
4045 struct net_device *netdev;
b50d292b 4046
26e59d80
MHY		 4047 err = mlx5e_check_required_hca_cap(mdev);
4048 if (err)
b50d292b
HHZ		 4049 return NULL;
4050
127ea380
HHZ		 4051 mlx5e_register_vport_rep(mdev);
4052
4053 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4054 ppriv = &esw->offloads.vport_reps[0];
4055
26e59d80
MHY		 4056 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4057 if (!netdev) {
4058 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4059 goto err_unregister_reps;
4060 }
4061
4062 priv = netdev_priv(netdev);
4063
4064 err = mlx5e_attach(mdev, priv);
4065 if (err) {
4066 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4067 goto err_destroy_netdev;
4068 }
4069
4070 err = register_netdev(netdev);
4071 if (err) {
4072 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4073 goto err_detach;
b50d292b 4074 }
26e59d80
MHY		 4075
4076 return priv;
4077
4078err_detach:
4079 mlx5e_detach(mdev, priv);
4080
4081err_destroy_netdev:
4082 mlx5e_destroy_netdev(mdev, priv);
4083
4084err_unregister_reps:
4085 for (vport = 1; vport < total_vfs; vport++)
4086 mlx5_eswitch_unregister_vport_rep(esw, vport);
4087
4088 return NULL;
b50d292b
HHZ		 4089}
4090
cb67b832 4091void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
f62b8bb8 4092{
6bfd390b 4093 const struct mlx5e_profile *profile = priv->profile;
f62b8bb8
AV		 4094 struct net_device *netdev = priv->netdev;
4095
7bb29755 4096 destroy_workqueue(priv->wq);
6bfd390b
HHZ		 4097 if (profile->cleanup)
4098 profile->cleanup(priv);
26e59d80 4099 free_netdev(netdev);
f62b8bb8
AV		 4100}
4101
b50d292b
HHZ		 4102static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4103{
127ea380
HHZ		 4104 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4105 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
b50d292b 4106 struct mlx5e_priv *priv = vpriv;
127ea380 4107 int vport;
b50d292b 4108
127ea380
HHZ		 4109 for (vport = 1; vport < total_vfs; vport++)
4110 mlx5_eswitch_unregister_vport_rep(esw, vport);
4111
5e1e93c7 4112 unregister_netdev(priv->netdev);
26e59d80
MHY		 4113 mlx5e_detach(mdev, vpriv);
4114 mlx5e_destroy_netdev(mdev, priv);
b50d292b
HHZ		 4115}
4116
f62b8bb8
AV		 4117static void *mlx5e_get_netdev(void *vpriv)
4118{
4119 struct mlx5e_priv *priv = vpriv;
4120
4121 return priv->netdev;
4122}
4123
4124static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4125 .add = mlx5e_add,
4126 .remove = mlx5e_remove,
26e59d80
MHY		 4127 .attach = mlx5e_attach,
4128 .detach = mlx5e_detach,
f62b8bb8
AV		 4129 .event = mlx5e_async_event,
4130 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4131 .get_dev = mlx5e_get_netdev,
4132};
4133
4134void mlx5e_init(void)
4135{
665bc539 4136 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4137 mlx5_register_interface(&mlx5e_interface);
4138}
4139
4140void mlx5e_cleanup(void)
4141{
4142 mlx5_unregister_interface(&mlx5e_interface);
4143}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git