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net/mlx5e: Implement ndo_tx_timeout callback
[thirdparty/kernel/stable.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
f62b8bb8 37#include "en.h"
e8f887ac 38#include "en_tc.h"
66e49ded 39#include "eswitch.h"
b3f63c3d 40#include "vxlan.h"
f62b8bb8 41
29429f33
DJ		 42enum {
43 MLX5_EN_QP_FLUSH_TIMEOUT_MS = 5000,
44 MLX5_EN_QP_FLUSH_MSLEEP_QUANT = 20,
45 MLX5_EN_QP_FLUSH_MAX_ITER = MLX5_EN_QP_FLUSH_TIMEOUT_MS /
46 MLX5_EN_QP_FLUSH_MSLEEP_QUANT,
47};
48
f62b8bb8
AV		 49struct mlx5e_rq_param {
50 u32 rqc[MLX5_ST_SZ_DW(rqc)];
51 struct mlx5_wq_param wq;
52};
53
54struct mlx5e_sq_param {
55 u32 sqc[MLX5_ST_SZ_DW(sqc)];
56 struct mlx5_wq_param wq;
58d52291 57 u16 max_inline;
d3c9bc27 58 bool icosq;
f62b8bb8
AV		 59};
60
61struct mlx5e_cq_param {
62 u32 cqc[MLX5_ST_SZ_DW(cqc)];
63 struct mlx5_wq_param wq;
64 u16 eq_ix;
65};
66
67struct mlx5e_channel_param {
68 struct mlx5e_rq_param rq;
69 struct mlx5e_sq_param sq;
d3c9bc27 70 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 71 struct mlx5e_cq_param rx_cq;
72 struct mlx5e_cq_param tx_cq;
d3c9bc27 73 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 74};
75
76static void mlx5e_update_carrier(struct mlx5e_priv *priv)
77{
78 struct mlx5_core_dev *mdev = priv->mdev;
79 u8 port_state;
80
81 port_state = mlx5_query_vport_state(mdev,
e7546514 82 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8
AV		 83
84 if (port_state == VPORT_STATE_UP)
85 netif_carrier_on(priv->netdev);
86 else
87 netif_carrier_off(priv->netdev);
88}
89
90static void mlx5e_update_carrier_work(struct work_struct *work)
91{
92 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
93 update_carrier_work);
94
95 mutex_lock(&priv->state_lock);
96 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
97 mlx5e_update_carrier(priv);
98 mutex_unlock(&priv->state_lock);
99}
100
3947ca18
DJ		 101static void mlx5e_tx_timeout_work(struct work_struct *work)
102{
103 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
104 tx_timeout_work);
105 int err;
106
107 rtnl_lock();
108 mutex_lock(&priv->state_lock);
109 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
110 goto unlock;
111 mlx5e_close_locked(priv->netdev);
112 err = mlx5e_open_locked(priv->netdev);
113 if (err)
114 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
115 err);
116unlock:
117 mutex_unlock(&priv->state_lock);
118 rtnl_unlock();
119}
120
9218b44d 121static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 122{
9218b44d 123 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 124 struct mlx5e_rq_stats *rq_stats;
125 struct mlx5e_sq_stats *sq_stats;
9218b44d 126 u64 tx_offload_none = 0;
f62b8bb8
AV		 127 int i, j;
128
9218b44d 129 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 130 for (i = 0; i < priv->params.num_channels; i++) {
131 rq_stats = &priv->channel[i]->rq.stats;
132
faf4478b
GP		 133 s->rx_packets += rq_stats->packets;
134 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 135 s->rx_lro_packets += rq_stats->lro_packets;
136 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 137 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 138 s->rx_csum_complete += rq_stats->csum_complete;
139 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
f62b8bb8 140 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 141 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
bc77b240 142 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
54984407 143 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 144 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
145 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
f62b8bb8 146
a4418a6c 147 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 148 sq_stats = &priv->channel[i]->sq[j].stats;
149
faf4478b
GP		 150 s->tx_packets += sq_stats->packets;
151 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 152 s->tx_tso_packets += sq_stats->tso_packets;
153 s->tx_tso_bytes += sq_stats->tso_bytes;
154 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
155 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 156 s->tx_queue_stopped += sq_stats->stopped;
157 s->tx_queue_wake += sq_stats->wake;
158 s->tx_queue_dropped += sq_stats->dropped;
bfe6d8d1
GP		 159 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
160 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 161 }
162 }
163
9218b44d 164 /* Update calculated offload counters */
bfe6d8d1
GP		 165 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
166 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 167
bfe6d8d1 168 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 169 priv->stats.pport.phy_counters,
170 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 171}
172
173static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
174{
175 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
176 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
177 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
178 struct mlx5_core_dev *mdev = priv->mdev;
179
f62b8bb8
AV		 180 memset(in, 0, sizeof(in));
181
182 MLX5_SET(query_vport_counter_in, in, opcode,
183 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
184 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
185 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
186
187 memset(out, 0, outlen);
188
9218b44d
GP		 189 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
190}
191
192static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
193{
194 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
195 struct mlx5_core_dev *mdev = priv->mdev;
196 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 197 int prio;
9218b44d
GP		 198 void *out;
199 u32 *in;
200
201 in = mlx5_vzalloc(sz);
202 if (!in)
f62b8bb8
AV		 203 goto free_out;
204
9218b44d 205 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 206
9218b44d
GP		 207 out = pstats->IEEE_802_3_counters;
208 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
209 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 210
9218b44d
GP		 211 out = pstats->RFC_2863_counters;
212 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
213 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
214
215 out = pstats->RFC_2819_counters;
216 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
217 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 218
121fcdc8
GP		 219 out = pstats->phy_counters;
220 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
221 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
222
cf678570
GP		 223 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
224 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
225 out = pstats->per_prio_counters[prio];
226 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
227 mlx5_core_access_reg(mdev, in, sz, out, sz,
228 MLX5_REG_PPCNT, 0, 0);
229 }
230
f62b8bb8 231free_out:
9218b44d
GP		 232 kvfree(in);
233}
234
235static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
236{
237 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
238
239 if (!priv->q_counter)
240 return;
241
242 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
243 &qcnt->rx_out_of_buffer);
244}
245
246void mlx5e_update_stats(struct mlx5e_priv *priv)
247{
9218b44d
GP		 248 mlx5e_update_q_counter(priv);
249 mlx5e_update_vport_counters(priv);
250 mlx5e_update_pport_counters(priv);
121fcdc8 251 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 252}
253
254static void mlx5e_update_stats_work(struct work_struct *work)
255{
256 struct delayed_work *dwork = to_delayed_work(work);
257 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
258 update_stats_work);
259 mutex_lock(&priv->state_lock);
260 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
261 mlx5e_update_stats(priv);
7bb29755
MF		 262 queue_delayed_work(priv->wq, dwork,
263 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 264 }
265 mutex_unlock(&priv->state_lock);
266}
267
daa21560
TT		 268static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
269 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 270{
daa21560
TT		 271 struct mlx5e_priv *priv = vpriv;
272
e0f46eb9 273 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 274 return;
275
f62b8bb8
AV		 276 switch (event) {
277 case MLX5_DEV_EVENT_PORT_UP:
278 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 279 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8
AV		 280 break;
281
282 default:
283 break;
284 }
285}
286
f62b8bb8
AV		 287static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
288{
e0f46eb9 289 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 290}
291
292static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
293{
e0f46eb9 294 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 295 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 296}
297
facc9699
SM		 298#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
299#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
300
f62b8bb8
AV		 301static int mlx5e_create_rq(struct mlx5e_channel *c,
302 struct mlx5e_rq_param *param,
303 struct mlx5e_rq *rq)
304{
305 struct mlx5e_priv *priv = c->priv;
306 struct mlx5_core_dev *mdev = priv->mdev;
307 void *rqc = param->rqc;
308 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 309 u32 byte_count;
f62b8bb8
AV		 310 int wq_sz;
311 int err;
312 int i;
313
311c7c71
SM		 314 param->wq.db_numa_node = cpu_to_node(c->cpu);
315
f62b8bb8
AV		 316 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
317 &rq->wq_ctrl);
318 if (err)
319 return err;
320
321 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
322
323 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 324
461017cb
TT		 325 switch (priv->params.rq_wq_type) {
326 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
327 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
328 GFP_KERNEL, cpu_to_node(c->cpu));
329 if (!rq->wqe_info) {
330 err = -ENOMEM;
331 goto err_rq_wq_destroy;
332 }
333 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
334 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
335
d9d9f156
TT		 336 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
337 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
338 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
461017cb
TT		 339 byte_count = rq->wqe_sz;
340 break;
341 default: /* MLX5_WQ_TYPE_LINKED_LIST */
342 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
343 cpu_to_node(c->cpu));
344 if (!rq->skb) {
345 err = -ENOMEM;
346 goto err_rq_wq_destroy;
347 }
348 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
349 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
350
351 rq->wqe_sz = (priv->params.lro_en) ?
352 priv->params.lro_wqe_sz :
353 MLX5E_SW2HW_MTU(priv->netdev->mtu);
c5adb96f
TT		 354 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
355 byte_count = rq->wqe_sz;
461017cb
TT		 356 byte_count |= MLX5_HW_START_PADDING;
357 }
f62b8bb8
AV		 358
359 for (i = 0; i < wq_sz; i++) {
360 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
361
461017cb 362 wqe->data.byte_count = cpu_to_be32(byte_count);
f62b8bb8
AV		 363 }
364
461017cb 365 rq->wq_type = priv->params.rq_wq_type;
f62b8bb8
AV		 366 rq->pdev = c->pdev;
367 rq->netdev = c->netdev;
ef9814de 368 rq->tstamp = &priv->tstamp;
f62b8bb8
AV		 369 rq->channel = c;
370 rq->ix = c->ix;
50cfa25a 371 rq->priv = c->priv;
bc77b240
TT		 372 rq->mkey_be = c->mkey_be;
373 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
f62b8bb8
AV		 374
375 return 0;
376
377err_rq_wq_destroy:
378 mlx5_wq_destroy(&rq->wq_ctrl);
379
380 return err;
381}
382
383static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
384{
461017cb
TT		 385 switch (rq->wq_type) {
386 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
387 kfree(rq->wqe_info);
388 break;
389 default: /* MLX5_WQ_TYPE_LINKED_LIST */
390 kfree(rq->skb);
391 }
392
f62b8bb8
AV		 393 mlx5_wq_destroy(&rq->wq_ctrl);
394}
395
396static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
397{
50cfa25a 398 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 399 struct mlx5_core_dev *mdev = priv->mdev;
400
401 void *in;
402 void *rqc;
403 void *wq;
404 int inlen;
405 int err;
406
407 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
408 sizeof(u64) * rq->wq_ctrl.buf.npages;
409 in = mlx5_vzalloc(inlen);
410 if (!in)
411 return -ENOMEM;
412
413 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
414 wq = MLX5_ADDR_OF(rqc, rqc, wq);
415
416 memcpy(rqc, param->rqc, sizeof(param->rqc));
417
97de9f31 418 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8
AV		 419 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
420 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
36350114 421 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
f62b8bb8 422 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 423 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 424 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
425
426 mlx5_fill_page_array(&rq->wq_ctrl.buf,
427 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
428
7db22ffb 429 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 430
431 kvfree(in);
432
433 return err;
434}
435
36350114
GP		 436static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
437 int next_state)
f62b8bb8
AV		 438{
439 struct mlx5e_channel *c = rq->channel;
440 struct mlx5e_priv *priv = c->priv;
441 struct mlx5_core_dev *mdev = priv->mdev;
442
443 void *in;
444 void *rqc;
445 int inlen;
446 int err;
447
448 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
449 in = mlx5_vzalloc(inlen);
450 if (!in)
451 return -ENOMEM;
452
453 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
454
455 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
456 MLX5_SET(rqc, rqc, state, next_state);
457
7db22ffb 458 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 459
460 kvfree(in);
461
462 return err;
463}
464
36350114
GP		 465static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
466{
467 struct mlx5e_channel *c = rq->channel;
468 struct mlx5e_priv *priv = c->priv;
469 struct mlx5_core_dev *mdev = priv->mdev;
470
471 void *in;
472 void *rqc;
473 int inlen;
474 int err;
475
476 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
477 in = mlx5_vzalloc(inlen);
478 if (!in)
479 return -ENOMEM;
480
481 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
482
483 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
484 MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
485 MLX5_SET(rqc, rqc, vsd, vsd);
486 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
487
488 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
489
490 kvfree(in);
491
492 return err;
493}
494
f62b8bb8
AV		 495static void mlx5e_disable_rq(struct mlx5e_rq *rq)
496{
50cfa25a 497 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 498}
499
500static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
501{
01c196a2 502 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 503 struct mlx5e_channel *c = rq->channel;
504 struct mlx5e_priv *priv = c->priv;
505 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 506
01c196a2 507 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 508 if (wq->cur_sz >= priv->params.min_rx_wqes)
509 return 0;
510
511 msleep(20);
512 }
513
514 return -ETIMEDOUT;
515}
516
517static int mlx5e_open_rq(struct mlx5e_channel *c,
518 struct mlx5e_rq_param *param,
519 struct mlx5e_rq *rq)
520{
d3c9bc27
TT		 521 struct mlx5e_sq *sq = &c->icosq;
522 u16 pi = sq->pc & sq->wq.sz_m1;
f62b8bb8
AV		 523 int err;
524
525 err = mlx5e_create_rq(c, param, rq);
526 if (err)
527 return err;
528
529 err = mlx5e_enable_rq(rq, param);
530 if (err)
531 goto err_destroy_rq;
532
36350114 533 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8
AV		 534 if (err)
535 goto err_disable_rq;
536
537 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
d3c9bc27
TT		 538
539 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
540 sq->ico_wqe_info[pi].num_wqebbs = 1;
541 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 542
543 return 0;
544
545err_disable_rq:
546 mlx5e_disable_rq(rq);
547err_destroy_rq:
548 mlx5e_destroy_rq(rq);
549
550 return err;
551}
552
553static void mlx5e_close_rq(struct mlx5e_rq *rq)
554{
555 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
556 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
557
36350114 558 mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
f62b8bb8
AV		 559 while (!mlx5_wq_ll_is_empty(&rq->wq))
560 msleep(20);
561
562 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
563 napi_synchronize(&rq->channel->napi);
564
565 mlx5e_disable_rq(rq);
566 mlx5e_destroy_rq(rq);
567}
568
569static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
570{
34802a42 571 kfree(sq->wqe_info);
f62b8bb8
AV		 572 kfree(sq->dma_fifo);
573 kfree(sq->skb);
574}
575
576static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
577{
578 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
579 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
580
581 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
582 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
583 numa);
34802a42
AS		 584 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
585 numa);
f62b8bb8 586
34802a42 587 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
f62b8bb8
AV		 588 mlx5e_free_sq_db(sq);
589 return -ENOMEM;
590 }
591
592 sq->dma_fifo_mask = df_sz - 1;
593
594 return 0;
595}
596
597static int mlx5e_create_sq(struct mlx5e_channel *c,
598 int tc,
599 struct mlx5e_sq_param *param,
600 struct mlx5e_sq *sq)
601{
602 struct mlx5e_priv *priv = c->priv;
603 struct mlx5_core_dev *mdev = priv->mdev;
604
605 void *sqc = param->sqc;
606 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
607 int err;
608
fd4782c2 609 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
f62b8bb8
AV		 610 if (err)
611 return err;
612
311c7c71
SM		 613 param->wq.db_numa_node = cpu_to_node(c->cpu);
614
f62b8bb8
AV		 615 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
616 &sq->wq_ctrl);
617 if (err)
618 goto err_unmap_free_uar;
619
620 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
0ba42241
ML		 621 if (sq->uar.bf_map) {
622 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
623 sq->uar_map = sq->uar.bf_map;
624 } else {
625 sq->uar_map = sq->uar.map;
626 }
f62b8bb8 627 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 628 sq->max_inline = param->max_inline;
f62b8bb8 629
7ec0bb22
DC		 630 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
631 if (err)
f62b8bb8
AV		 632 goto err_sq_wq_destroy;
633
d3c9bc27
TT		 634 if (param->icosq) {
635 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
636
637 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
638 wq_sz,
639 GFP_KERNEL,
640 cpu_to_node(c->cpu));
641 if (!sq->ico_wqe_info) {
642 err = -ENOMEM;
643 goto err_free_sq_db;
644 }
645 } else {
646 int txq_ix;
647
648 txq_ix = c->ix + tc * priv->params.num_channels;
649 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
650 priv->txq_to_sq_map[txq_ix] = sq;
651 }
f62b8bb8 652
88a85f99 653 sq->pdev = c->pdev;
ef9814de 654 sq->tstamp = &priv->tstamp;
88a85f99
AS		 655 sq->mkey_be = c->mkey_be;
656 sq->channel = c;
657 sq->tc = tc;
658 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
659 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
f62b8bb8
AV		 660
661 return 0;
662
d3c9bc27
TT		 663err_free_sq_db:
664 mlx5e_free_sq_db(sq);
665
f62b8bb8
AV		 666err_sq_wq_destroy:
667 mlx5_wq_destroy(&sq->wq_ctrl);
668
669err_unmap_free_uar:
670 mlx5_unmap_free_uar(mdev, &sq->uar);
671
672 return err;
673}
674
675static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
676{
677 struct mlx5e_channel *c = sq->channel;
678 struct mlx5e_priv *priv = c->priv;
679
d3c9bc27 680 kfree(sq->ico_wqe_info);
f62b8bb8
AV		 681 mlx5e_free_sq_db(sq);
682 mlx5_wq_destroy(&sq->wq_ctrl);
683 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
684}
685
686static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
687{
688 struct mlx5e_channel *c = sq->channel;
689 struct mlx5e_priv *priv = c->priv;
690 struct mlx5_core_dev *mdev = priv->mdev;
691
692 void *in;
693 void *sqc;
694 void *wq;
695 int inlen;
696 int err;
697
698 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
699 sizeof(u64) * sq->wq_ctrl.buf.npages;
700 in = mlx5_vzalloc(inlen);
701 if (!in)
702 return -ENOMEM;
703
704 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
705 wq = MLX5_ADDR_OF(sqc, sqc, wq);
706
707 memcpy(sqc, param->sqc, sizeof(param->sqc));
708
d3c9bc27
TT		 709 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
710 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
f62b8bb8 711 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
d3c9bc27 712 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
f62b8bb8
AV		 713 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
714
715 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
716 MLX5_SET(wq, wq, uar_page, sq->uar.index);
717 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 718 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 719 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
720
721 mlx5_fill_page_array(&sq->wq_ctrl.buf,
722 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
723
7db22ffb 724 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 725
726 kvfree(in);
727
728 return err;
729}
730
731static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
732{
733 struct mlx5e_channel *c = sq->channel;
734 struct mlx5e_priv *priv = c->priv;
735 struct mlx5_core_dev *mdev = priv->mdev;
736
737 void *in;
738 void *sqc;
739 int inlen;
740 int err;
741
742 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
743 in = mlx5_vzalloc(inlen);
744 if (!in)
745 return -ENOMEM;
746
747 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
748
749 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
750 MLX5_SET(sqc, sqc, state, next_state);
751
7db22ffb 752 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 753
754 kvfree(in);
755
756 return err;
757}
758
759static void mlx5e_disable_sq(struct mlx5e_sq *sq)
760{
761 struct mlx5e_channel *c = sq->channel;
762 struct mlx5e_priv *priv = c->priv;
763 struct mlx5_core_dev *mdev = priv->mdev;
764
7db22ffb 765 mlx5_core_destroy_sq(mdev, sq->sqn);
f62b8bb8
AV		 766}
767
768static int mlx5e_open_sq(struct mlx5e_channel *c,
769 int tc,
770 struct mlx5e_sq_param *param,
771 struct mlx5e_sq *sq)
772{
773 int err;
774
775 err = mlx5e_create_sq(c, tc, param, sq);
776 if (err)
777 return err;
778
779 err = mlx5e_enable_sq(sq, param);
780 if (err)
781 goto err_destroy_sq;
782
783 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
784 if (err)
785 goto err_disable_sq;
786
d3c9bc27
TT		 787 if (sq->txq) {
788 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
789 netdev_tx_reset_queue(sq->txq);
790 netif_tx_start_queue(sq->txq);
791 }
f62b8bb8
AV		 792
793 return 0;
794
795err_disable_sq:
796 mlx5e_disable_sq(sq);
797err_destroy_sq:
798 mlx5e_destroy_sq(sq);
799
800 return err;
801}
802
803static inline void netif_tx_disable_queue(struct netdev_queue *txq)
804{
805 __netif_tx_lock_bh(txq);
806 netif_tx_stop_queue(txq);
807 __netif_tx_unlock_bh(txq);
808}
809
810static void mlx5e_close_sq(struct mlx5e_sq *sq)
811{
29429f33
DJ		 812 int tout = 0;
813 int err;
814
d3c9bc27
TT		 815 if (sq->txq) {
816 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
817 /* prevent netif_tx_wake_queue */
818 napi_synchronize(&sq->channel->napi);
819 netif_tx_disable_queue(sq->txq);
f62b8bb8 820
d3c9bc27
TT		 821 /* ensure hw is notified of all pending wqes */
822 if (mlx5e_sq_has_room_for(sq, 1))
823 mlx5e_send_nop(sq, true);
824
29429f33
DJ		 825 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
826 MLX5_SQC_STATE_ERR);
827 if (err)
828 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
d3c9bc27 829 }
f62b8bb8 830
29429f33
DJ		 831 /* wait till sq is empty, unless a TX timeout occurred on this SQ */
832 while (sq->cc != sq->pc &&
833 !test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)) {
834 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
835 if (tout++ > MLX5_EN_QP_FLUSH_MAX_ITER)
836 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
837 }
f62b8bb8
AV		 838
839 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
840 napi_synchronize(&sq->channel->napi);
841
29429f33 842 mlx5e_free_tx_descs(sq);
f62b8bb8
AV		 843 mlx5e_disable_sq(sq);
844 mlx5e_destroy_sq(sq);
845}
846
847static int mlx5e_create_cq(struct mlx5e_channel *c,
848 struct mlx5e_cq_param *param,
849 struct mlx5e_cq *cq)
850{
851 struct mlx5e_priv *priv = c->priv;
852 struct mlx5_core_dev *mdev = priv->mdev;
853 struct mlx5_core_cq *mcq = &cq->mcq;
854 int eqn_not_used;
0b6e26ce 855 unsigned int irqn;
f62b8bb8
AV		 856 int err;
857 u32 i;
858
311c7c71
SM		 859 param->wq.buf_numa_node = cpu_to_node(c->cpu);
860 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 861 param->eq_ix = c->ix;
862
863 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
864 &cq->wq_ctrl);
865 if (err)
866 return err;
867
868 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
869
870 cq->napi = &c->napi;
871
872 mcq->cqe_sz = 64;
873 mcq->set_ci_db = cq->wq_ctrl.db.db;
874 mcq->arm_db = cq->wq_ctrl.db.db + 1;
875 *mcq->set_ci_db = 0;
876 *mcq->arm_db = 0;
877 mcq->vector = param->eq_ix;
878 mcq->comp = mlx5e_completion_event;
879 mcq->event = mlx5e_cq_error_event;
880 mcq->irqn = irqn;
881 mcq->uar = &priv->cq_uar;
882
883 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
884 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
885
886 cqe->op_own = 0xf1;
887 }
888
889 cq->channel = c;
50cfa25a 890 cq->priv = priv;
f62b8bb8
AV		 891
892 return 0;
893}
894
895static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
896{
897 mlx5_wq_destroy(&cq->wq_ctrl);
898}
899
900static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
901{
50cfa25a 902 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 903 struct mlx5_core_dev *mdev = priv->mdev;
904 struct mlx5_core_cq *mcq = &cq->mcq;
905
906 void *in;
907 void *cqc;
908 int inlen;
0b6e26ce 909 unsigned int irqn_not_used;
f62b8bb8
AV		 910 int eqn;
911 int err;
912
913 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
914 sizeof(u64) * cq->wq_ctrl.buf.npages;
915 in = mlx5_vzalloc(inlen);
916 if (!in)
917 return -ENOMEM;
918
919 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
920
921 memcpy(cqc, param->cqc, sizeof(param->cqc));
922
923 mlx5_fill_page_array(&cq->wq_ctrl.buf,
924 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
925
926 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
927
928 MLX5_SET(cqc, cqc, c_eqn, eqn);
929 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
930 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 931 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 932 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
933
934 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
935
936 kvfree(in);
937
938 if (err)
939 return err;
940
941 mlx5e_cq_arm(cq);
942
943 return 0;
944}
945
946static void mlx5e_disable_cq(struct mlx5e_cq *cq)
947{
50cfa25a 948 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 949 struct mlx5_core_dev *mdev = priv->mdev;
950
951 mlx5_core_destroy_cq(mdev, &cq->mcq);
952}
953
954static int mlx5e_open_cq(struct mlx5e_channel *c,
955 struct mlx5e_cq_param *param,
956 struct mlx5e_cq *cq,
957 u16 moderation_usecs,
958 u16 moderation_frames)
959{
960 int err;
961 struct mlx5e_priv *priv = c->priv;
962 struct mlx5_core_dev *mdev = priv->mdev;
963
964 err = mlx5e_create_cq(c, param, cq);
965 if (err)
966 return err;
967
968 err = mlx5e_enable_cq(cq, param);
969 if (err)
970 goto err_destroy_cq;
971
7524a5d8
GP		 972 if (MLX5_CAP_GEN(mdev, cq_moderation))
973 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
974 moderation_usecs,
975 moderation_frames);
f62b8bb8
AV		 976 return 0;
977
978err_destroy_cq:
979 mlx5e_destroy_cq(cq);
980
981 return err;
982}
983
984static void mlx5e_close_cq(struct mlx5e_cq *cq)
985{
986 mlx5e_disable_cq(cq);
987 mlx5e_destroy_cq(cq);
988}
989
990static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
991{
992 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
993}
994
995static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
996 struct mlx5e_channel_param *cparam)
997{
998 struct mlx5e_priv *priv = c->priv;
999 int err;
1000 int tc;
1001
1002 for (tc = 0; tc < c->num_tc; tc++) {
1003 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1004 priv->params.tx_cq_moderation_usec,
1005 priv->params.tx_cq_moderation_pkts);
1006 if (err)
1007 goto err_close_tx_cqs;
f62b8bb8
AV		 1008 }
1009
1010 return 0;
1011
1012err_close_tx_cqs:
1013 for (tc--; tc >= 0; tc--)
1014 mlx5e_close_cq(&c->sq[tc].cq);
1015
1016 return err;
1017}
1018
1019static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1020{
1021 int tc;
1022
1023 for (tc = 0; tc < c->num_tc; tc++)
1024 mlx5e_close_cq(&c->sq[tc].cq);
1025}
1026
1027static int mlx5e_open_sqs(struct mlx5e_channel *c,
1028 struct mlx5e_channel_param *cparam)
1029{
1030 int err;
1031 int tc;
1032
1033 for (tc = 0; tc < c->num_tc; tc++) {
1034 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1035 if (err)
1036 goto err_close_sqs;
1037 }
1038
1039 return 0;
1040
1041err_close_sqs:
1042 for (tc--; tc >= 0; tc--)
1043 mlx5e_close_sq(&c->sq[tc]);
1044
1045 return err;
1046}
1047
1048static void mlx5e_close_sqs(struct mlx5e_channel *c)
1049{
1050 int tc;
1051
1052 for (tc = 0; tc < c->num_tc; tc++)
1053 mlx5e_close_sq(&c->sq[tc]);
1054}
1055
5283af89 1056static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 1057{
1058 int i;
1059
1060 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
5283af89
RS		 1061 priv->channeltc_to_txq_map[ix][i] =
1062 ix + i * priv->params.num_channels;
03289b88
SM		 1063}
1064
f62b8bb8
AV		 1065static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1066 struct mlx5e_channel_param *cparam,
1067 struct mlx5e_channel **cp)
1068{
1069 struct net_device *netdev = priv->netdev;
1070 int cpu = mlx5e_get_cpu(priv, ix);
1071 struct mlx5e_channel *c;
1072 int err;
1073
1074 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1075 if (!c)
1076 return -ENOMEM;
1077
1078 c->priv = priv;
1079 c->ix = ix;
1080 c->cpu = cpu;
1081 c->pdev = &priv->mdev->pdev->dev;
1082 c->netdev = priv->netdev;
a606b0f6 1083 c->mkey_be = cpu_to_be32(priv->mkey.key);
a4418a6c 1084 c->num_tc = priv->params.num_tc;
f62b8bb8 1085
5283af89 1086 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1087
f62b8bb8
AV		 1088 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1089
d3c9bc27 1090 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
f62b8bb8
AV		 1091 if (err)
1092 goto err_napi_del;
1093
d3c9bc27
TT		 1094 err = mlx5e_open_tx_cqs(c, cparam);
1095 if (err)
1096 goto err_close_icosq_cq;
1097
f62b8bb8
AV		 1098 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1099 priv->params.rx_cq_moderation_usec,
1100 priv->params.rx_cq_moderation_pkts);
1101 if (err)
1102 goto err_close_tx_cqs;
f62b8bb8
AV		 1103
1104 napi_enable(&c->napi);
1105
d3c9bc27 1106 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1107 if (err)
1108 goto err_disable_napi;
1109
d3c9bc27
TT		 1110 err = mlx5e_open_sqs(c, cparam);
1111 if (err)
1112 goto err_close_icosq;
1113
f62b8bb8
AV		 1114 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1115 if (err)
1116 goto err_close_sqs;
1117
1118 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1119 *cp = c;
1120
1121 return 0;
1122
1123err_close_sqs:
1124 mlx5e_close_sqs(c);
1125
d3c9bc27
TT		 1126err_close_icosq:
1127 mlx5e_close_sq(&c->icosq);
1128
f62b8bb8
AV		 1129err_disable_napi:
1130 napi_disable(&c->napi);
1131 mlx5e_close_cq(&c->rq.cq);
1132
1133err_close_tx_cqs:
1134 mlx5e_close_tx_cqs(c);
1135
d3c9bc27
TT		 1136err_close_icosq_cq:
1137 mlx5e_close_cq(&c->icosq.cq);
1138
f62b8bb8
AV		 1139err_napi_del:
1140 netif_napi_del(&c->napi);
7ae92ae5 1141 napi_hash_del(&c->napi);
f62b8bb8
AV		 1142 kfree(c);
1143
1144 return err;
1145}
1146
1147static void mlx5e_close_channel(struct mlx5e_channel *c)
1148{
1149 mlx5e_close_rq(&c->rq);
1150 mlx5e_close_sqs(c);
d3c9bc27 1151 mlx5e_close_sq(&c->icosq);
f62b8bb8
AV		 1152 napi_disable(&c->napi);
1153 mlx5e_close_cq(&c->rq.cq);
1154 mlx5e_close_tx_cqs(c);
d3c9bc27 1155 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1156 netif_napi_del(&c->napi);
7ae92ae5
ED		 1157
1158 napi_hash_del(&c->napi);
1159 synchronize_rcu();
1160
f62b8bb8
AV		 1161 kfree(c);
1162}
1163
1164static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1165 struct mlx5e_rq_param *param)
1166{
1167 void *rqc = param->rqc;
1168 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1169
461017cb
TT		 1170 switch (priv->params.rq_wq_type) {
1171 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1172 MLX5_SET(wq, wq, log_wqe_num_of_strides,
d9d9f156 1173 priv->params.mpwqe_log_num_strides - 9);
461017cb 1174 MLX5_SET(wq, wq, log_wqe_stride_size,
d9d9f156 1175 priv->params.mpwqe_log_stride_sz - 6);
461017cb
TT		 1176 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1177 break;
1178 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1179 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1180 }
1181
f62b8bb8
AV		 1182 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1183 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1184 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1185 MLX5_SET(wq, wq, pd, priv->pdn);
593cf338 1186 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1187
311c7c71 1188 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1189 param->wq.linear = 1;
1190}
1191
556dd1b9
TT		 1192static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1193{
1194 void *rqc = param->rqc;
1195 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1196
1197 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1198 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1199}
1200
d3c9bc27
TT		 1201static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1202 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1203{
1204 void *sqc = param->sqc;
1205 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1206
f62b8bb8
AV		 1207 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1208 MLX5_SET(wq, wq, pd, priv->pdn);
1209
311c7c71 1210 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1211}
1212
1213static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1214 struct mlx5e_sq_param *param)
1215{
1216 void *sqc = param->sqc;
1217 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1218
1219 mlx5e_build_sq_param_common(priv, param);
1220 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1221
58d52291 1222 param->max_inline = priv->params.tx_max_inline;
f62b8bb8
AV		 1223}
1224
1225static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1226 struct mlx5e_cq_param *param)
1227{
1228 void *cqc = param->cqc;
1229
1230 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1231}
1232
1233static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1234 struct mlx5e_cq_param *param)
1235{
1236 void *cqc = param->cqc;
461017cb 1237 u8 log_cq_size;
f62b8bb8 1238
461017cb
TT		 1239 switch (priv->params.rq_wq_type) {
1240 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1241 log_cq_size = priv->params.log_rq_size +
d9d9f156 1242 priv->params.mpwqe_log_num_strides;
461017cb
TT		 1243 break;
1244 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1245 log_cq_size = priv->params.log_rq_size;
1246 }
1247
1248 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
7219ab34
TT		 1249 if (priv->params.rx_cqe_compress) {
1250 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1251 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1252 }
f62b8bb8
AV		 1253
1254 mlx5e_build_common_cq_param(priv, param);
1255}
1256
1257static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1258 struct mlx5e_cq_param *param)
1259{
1260 void *cqc = param->cqc;
1261
d3c9bc27 1262 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1263
1264 mlx5e_build_common_cq_param(priv, param);
1265}
1266
d3c9bc27
TT		 1267static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1268 struct mlx5e_cq_param *param,
1269 u8 log_wq_size)
1270{
1271 void *cqc = param->cqc;
1272
1273 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1274
1275 mlx5e_build_common_cq_param(priv, param);
1276}
1277
1278static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1279 struct mlx5e_sq_param *param,
1280 u8 log_wq_size)
1281{
1282 void *sqc = param->sqc;
1283 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1284
1285 mlx5e_build_sq_param_common(priv, param);
1286
1287 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1288 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1289
1290 param->icosq = true;
1291}
1292
6b87663f 1293static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
f62b8bb8 1294{
bc77b240 1295 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1296
f62b8bb8
AV		 1297 mlx5e_build_rq_param(priv, &cparam->rq);
1298 mlx5e_build_sq_param(priv, &cparam->sq);
d3c9bc27 1299 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1300 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1301 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1302 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1303}
1304
1305static int mlx5e_open_channels(struct mlx5e_priv *priv)
1306{
6b87663f 1307 struct mlx5e_channel_param *cparam;
a4418a6c 1308 int nch = priv->params.num_channels;
03289b88 1309 int err = -ENOMEM;
f62b8bb8
AV		 1310 int i;
1311 int j;
1312
a4418a6c
AS		 1313 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1314 GFP_KERNEL);
03289b88 1315
a4418a6c 1316 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1317 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1318
6b87663f
AB		 1319 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1320
1321 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
03289b88 1322 goto err_free_txq_to_sq_map;
f62b8bb8 1323
6b87663f
AB		 1324 mlx5e_build_channel_param(priv, cparam);
1325
a4418a6c 1326 for (i = 0; i < nch; i++) {
6b87663f 1327 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
f62b8bb8
AV		 1328 if (err)
1329 goto err_close_channels;
1330 }
1331
a4418a6c 1332 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1333 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1334 if (err)
1335 goto err_close_channels;
1336 }
1337
6b87663f 1338 kfree(cparam);
f62b8bb8
AV		 1339 return 0;
1340
1341err_close_channels:
1342 for (i--; i >= 0; i--)
1343 mlx5e_close_channel(priv->channel[i]);
1344
03289b88
SM		 1345err_free_txq_to_sq_map:
1346 kfree(priv->txq_to_sq_map);
f62b8bb8 1347 kfree(priv->channel);
6b87663f 1348 kfree(cparam);
f62b8bb8
AV		 1349
1350 return err;
1351}
1352
1353static void mlx5e_close_channels(struct mlx5e_priv *priv)
1354{
1355 int i;
1356
1357 for (i = 0; i < priv->params.num_channels; i++)
1358 mlx5e_close_channel(priv->channel[i]);
1359
03289b88 1360 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1361 kfree(priv->channel);
1362}
1363
2be6967c
SM		 1364static int mlx5e_rx_hash_fn(int hfunc)
1365{
1366 return (hfunc == ETH_RSS_HASH_TOP) ?
1367 MLX5_RX_HASH_FN_TOEPLITZ :
1368 MLX5_RX_HASH_FN_INVERTED_XOR8;
1369}
1370
1371static int mlx5e_bits_invert(unsigned long a, int size)
1372{
1373 int inv = 0;
1374 int i;
1375
1376 for (i = 0; i < size; i++)
1377 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1378
1379 return inv;
1380}
1381
936896e9
AS		 1382static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1383{
1384 int i;
1385
1386 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1387 int ix = i;
1da36696 1388 u32 rqn;
936896e9
AS		 1389
1390 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1391 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1392
2d75b2bc 1393 ix = priv->params.indirection_rqt[ix];
1da36696
TT		 1394 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1395 priv->channel[ix]->rq.rqn :
1396 priv->drop_rq.rqn;
1397 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
936896e9
AS		 1398 }
1399}
1400
1da36696
TT		 1401static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1402 int ix)
4cbeaff5 1403{
1da36696
TT		 1404 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1405 priv->channel[ix]->rq.rqn :
1406 priv->drop_rq.rqn;
4cbeaff5 1407
1da36696 1408 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
4cbeaff5
AS		 1409}
1410
1da36696 1411static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn)
f62b8bb8
AV		 1412{
1413 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1414 void *rqtc;
1415 int inlen;
1416 int err;
1da36696 1417 u32 *in;
f62b8bb8 1418
f62b8bb8
AV		 1419 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1420 in = mlx5_vzalloc(inlen);
1421 if (!in)
1422 return -ENOMEM;
1423
1424 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1425
1426 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1427 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1428
1da36696
TT		 1429 if (sz > 1) /* RSS */
1430 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1431 else
1432 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2be6967c 1433
1da36696 1434 err = mlx5_core_create_rqt(mdev, in, inlen, rqtn);
f62b8bb8
AV		 1435
1436 kvfree(in);
1da36696
TT		 1437 return err;
1438}
1439
1440static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn)
1441{
1442 mlx5_core_destroy_rqt(priv->mdev, rqtn);
1443}
1444
1445static int mlx5e_create_rqts(struct mlx5e_priv *priv)
1446{
1447 int nch = mlx5e_get_max_num_channels(priv->mdev);
1448 u32 *rqtn;
1449 int err;
1450 int ix;
1451
1452 /* Indirect RQT */
1453 rqtn = &priv->indir_rqtn;
1454 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn);
1455 if (err)
1456 return err;
1457
1458 /* Direct RQTs */
1459 for (ix = 0; ix < nch; ix++) {
1460 rqtn = &priv->direct_tir[ix].rqtn;
1461 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn);
1462 if (err)
1463 goto err_destroy_rqts;
1464 }
1465
1466 return 0;
1467
1468err_destroy_rqts:
1469 for (ix--; ix >= 0; ix--)
1470 mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn);
1471
1472 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
f62b8bb8
AV		 1473
1474 return err;
1475}
1476
1da36696
TT		 1477static void mlx5e_destroy_rqts(struct mlx5e_priv *priv)
1478{
1479 int nch = mlx5e_get_max_num_channels(priv->mdev);
1480 int i;
1481
1482 for (i = 0; i < nch; i++)
1483 mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn);
1484
1485 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1486}
1487
1488int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
5c50368f
AS		 1489{
1490 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 1491 void *rqtc;
1492 int inlen;
1da36696 1493 u32 *in;
5c50368f
AS		 1494 int err;
1495
5c50368f
AS		 1496 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1497 in = mlx5_vzalloc(inlen);
1498 if (!in)
1499 return -ENOMEM;
1500
1501 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1502
1503 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1da36696
TT		 1504 if (sz > 1) /* RSS */
1505 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1506 else
1507 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
5c50368f
AS		 1508
1509 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1510
1da36696 1511 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 1512
1513 kvfree(in);
1514
1515 return err;
1516}
1517
40ab6a6e
AS		 1518static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1519{
1da36696
TT		 1520 u32 rqtn;
1521 int ix;
1522
1523 rqtn = priv->indir_rqtn;
1524 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1525 for (ix = 0; ix < priv->params.num_channels; ix++) {
1526 rqtn = priv->direct_tir[ix].rqtn;
1527 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1528 }
40ab6a6e
AS		 1529}
1530
5c50368f
AS		 1531static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1532{
1533 if (!priv->params.lro_en)
1534 return;
1535
1536#define ROUGH_MAX_L2_L3_HDR_SZ 256
1537
1538 MLX5_SET(tirc, tirc, lro_enable_mask,
1539 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1540 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1541 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1542 (priv->params.lro_wqe_sz -
1543 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1544 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1545 MLX5_CAP_ETH(priv->mdev,
d9a40271 1546 lro_timer_supported_periods[2]));
5c50368f
AS		 1547}
1548
bdfc028d
TT		 1549void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1550{
1551 MLX5_SET(tirc, tirc, rx_hash_fn,
1552 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1553 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1554 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1555 rx_hash_toeplitz_key);
1556 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1557 rx_hash_toeplitz_key);
1558
1559 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1560 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1561 }
1562}
1563
ab0394fe 1564static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 1565{
1566 struct mlx5_core_dev *mdev = priv->mdev;
1567
1568 void *in;
1569 void *tirc;
1570 int inlen;
1571 int err;
ab0394fe 1572 int tt;
1da36696 1573 int ix;
5c50368f
AS		 1574
1575 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1576 in = mlx5_vzalloc(inlen);
1577 if (!in)
1578 return -ENOMEM;
1579
1580 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1581 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1582
1583 mlx5e_build_tir_ctx_lro(tirc, priv);
1584
1da36696
TT		 1585 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1586 err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in,
1587 inlen);
ab0394fe 1588 if (err)
1da36696 1589 goto free_in;
ab0394fe 1590 }
5c50368f 1591
1da36696
TT		 1592 for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) {
1593 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1594 in, inlen);
1595 if (err)
1596 goto free_in;
1597 }
1598
1599free_in:
5c50368f
AS		 1600 kvfree(in);
1601
1602 return err;
1603}
1604
1da36696 1605static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
66189961
TT		 1606{
1607 void *in;
1608 int inlen;
1609 int err;
1da36696 1610 int i;
66189961
TT		 1611
1612 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1613 in = mlx5_vzalloc(inlen);
1614 if (!in)
1615 return -ENOMEM;
1616
1617 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1618
1da36696
TT		 1619 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
1620 err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in,
1621 inlen);
1622 if (err)
1623 return err;
1624 }
66189961 1625
1da36696
TT		 1626 for (i = 0; i < priv->params.num_channels; i++) {
1627 err = mlx5_core_modify_tir(priv->mdev,
1628 priv->direct_tir[i].tirn, in,
1629 inlen);
66189961
TT		 1630 if (err)
1631 return err;
1632 }
1633
1da36696
TT		 1634 kvfree(in);
1635
66189961
TT		 1636 return 0;
1637}
1638
cd255eff 1639static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 1640{
40ab6a6e 1641 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 1642 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 1643 int err;
1644
cd255eff 1645 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 1646 if (err)
1647 return err;
1648
cd255eff
SM		 1649 /* Update vport context MTU */
1650 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1651 return 0;
1652}
40ab6a6e 1653
cd255eff
SM		 1654static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1655{
1656 struct mlx5_core_dev *mdev = priv->mdev;
1657 u16 hw_mtu = 0;
1658 int err;
40ab6a6e 1659
cd255eff
SM		 1660 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1661 if (err || !hw_mtu) /* fallback to port oper mtu */
1662 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1663
1664 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1665}
1666
1667static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1668{
1669 struct mlx5e_priv *priv = netdev_priv(netdev);
1670 u16 mtu;
1671 int err;
1672
1673 err = mlx5e_set_mtu(priv, netdev->mtu);
1674 if (err)
1675 return err;
40ab6a6e 1676
cd255eff
SM		 1677 mlx5e_query_mtu(priv, &mtu);
1678 if (mtu != netdev->mtu)
1679 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1680 __func__, mtu, netdev->mtu);
40ab6a6e 1681
cd255eff 1682 netdev->mtu = mtu;
40ab6a6e
AS		 1683 return 0;
1684}
1685
08fb1dac
SM		 1686static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1687{
1688 struct mlx5e_priv *priv = netdev_priv(netdev);
1689 int nch = priv->params.num_channels;
1690 int ntc = priv->params.num_tc;
1691 int tc;
1692
1693 netdev_reset_tc(netdev);
1694
1695 if (ntc == 1)
1696 return;
1697
1698 netdev_set_num_tc(netdev, ntc);
1699
1700 for (tc = 0; tc < ntc; tc++)
1701 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1702}
1703
40ab6a6e
AS		 1704int mlx5e_open_locked(struct net_device *netdev)
1705{
1706 struct mlx5e_priv *priv = netdev_priv(netdev);
1707 int num_txqs;
1708 int err;
1709
1710 set_bit(MLX5E_STATE_OPENED, &priv->state);
1711
08fb1dac
SM		 1712 mlx5e_netdev_set_tcs(netdev);
1713
40ab6a6e
AS		 1714 num_txqs = priv->params.num_channels * priv->params.num_tc;
1715 netif_set_real_num_tx_queues(netdev, num_txqs);
1716 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1717
1718 err = mlx5e_set_dev_port_mtu(netdev);
1719 if (err)
343b29f3 1720 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1721
1722 err = mlx5e_open_channels(priv);
1723 if (err) {
1724 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1725 __func__, err);
343b29f3 1726 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1727 }
1728
66189961
TT		 1729 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1730 if (err) {
1731 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1732 __func__, err);
1733 goto err_close_channels;
1734 }
1735
40ab6a6e 1736 mlx5e_redirect_rqts(priv);
ce89ef36 1737 mlx5e_update_carrier(priv);
ef9814de 1738 mlx5e_timestamp_init(priv);
5a7b27eb
MG		 1739#ifdef CONFIG_RFS_ACCEL
1740 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1741#endif
40ab6a6e 1742
7bb29755 1743 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 1744
9b37b07f 1745 return 0;
343b29f3 1746
66189961
TT		 1747err_close_channels:
1748 mlx5e_close_channels(priv);
343b29f3
AS		 1749err_clear_state_opened_flag:
1750 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1751 return err;
40ab6a6e
AS		 1752}
1753
1754static int mlx5e_open(struct net_device *netdev)
1755{
1756 struct mlx5e_priv *priv = netdev_priv(netdev);
1757 int err;
1758
1759 mutex_lock(&priv->state_lock);
1760 err = mlx5e_open_locked(netdev);
1761 mutex_unlock(&priv->state_lock);
1762
1763 return err;
1764}
1765
1766int mlx5e_close_locked(struct net_device *netdev)
1767{
1768 struct mlx5e_priv *priv = netdev_priv(netdev);
1769
a1985740
AS		 1770 /* May already be CLOSED in case a previous configuration operation
1771 * (e.g RX/TX queue size change) that involves close&open failed.
1772 */
1773 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1774 return 0;
1775
40ab6a6e
AS		 1776 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1777
ef9814de 1778 mlx5e_timestamp_cleanup(priv);
40ab6a6e 1779 netif_carrier_off(priv->netdev);
ce89ef36 1780 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 1781 mlx5e_close_channels(priv);
1782
1783 return 0;
1784}
1785
1786static int mlx5e_close(struct net_device *netdev)
1787{
1788 struct mlx5e_priv *priv = netdev_priv(netdev);
1789 int err;
1790
1791 mutex_lock(&priv->state_lock);
1792 err = mlx5e_close_locked(netdev);
1793 mutex_unlock(&priv->state_lock);
1794
1795 return err;
1796}
1797
1798static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1799 struct mlx5e_rq *rq,
1800 struct mlx5e_rq_param *param)
1801{
1802 struct mlx5_core_dev *mdev = priv->mdev;
1803 void *rqc = param->rqc;
1804 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1805 int err;
1806
1807 param->wq.db_numa_node = param->wq.buf_numa_node;
1808
1809 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1810 &rq->wq_ctrl);
1811 if (err)
1812 return err;
1813
1814 rq->priv = priv;
1815
1816 return 0;
1817}
1818
1819static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1820 struct mlx5e_cq *cq,
1821 struct mlx5e_cq_param *param)
1822{
1823 struct mlx5_core_dev *mdev = priv->mdev;
1824 struct mlx5_core_cq *mcq = &cq->mcq;
1825 int eqn_not_used;
0b6e26ce 1826 unsigned int irqn;
40ab6a6e
AS		 1827 int err;
1828
1829 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1830 &cq->wq_ctrl);
1831 if (err)
1832 return err;
1833
1834 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1835
1836 mcq->cqe_sz = 64;
1837 mcq->set_ci_db = cq->wq_ctrl.db.db;
1838 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1839 *mcq->set_ci_db = 0;
1840 *mcq->arm_db = 0;
1841 mcq->vector = param->eq_ix;
1842 mcq->comp = mlx5e_completion_event;
1843 mcq->event = mlx5e_cq_error_event;
1844 mcq->irqn = irqn;
1845 mcq->uar = &priv->cq_uar;
1846
1847 cq->priv = priv;
1848
1849 return 0;
1850}
1851
1852static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1853{
1854 struct mlx5e_cq_param cq_param;
1855 struct mlx5e_rq_param rq_param;
1856 struct mlx5e_rq *rq = &priv->drop_rq;
1857 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1858 int err;
1859
1860 memset(&cq_param, 0, sizeof(cq_param));
1861 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 1862 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 1863
1864 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1865 if (err)
1866 return err;
1867
1868 err = mlx5e_enable_cq(cq, &cq_param);
1869 if (err)
1870 goto err_destroy_cq;
1871
1872 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1873 if (err)
1874 goto err_disable_cq;
1875
1876 err = mlx5e_enable_rq(rq, &rq_param);
1877 if (err)
1878 goto err_destroy_rq;
1879
1880 return 0;
1881
1882err_destroy_rq:
1883 mlx5e_destroy_rq(&priv->drop_rq);
1884
1885err_disable_cq:
1886 mlx5e_disable_cq(&priv->drop_rq.cq);
1887
1888err_destroy_cq:
1889 mlx5e_destroy_cq(&priv->drop_rq.cq);
1890
1891 return err;
1892}
1893
1894static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1895{
1896 mlx5e_disable_rq(&priv->drop_rq);
1897 mlx5e_destroy_rq(&priv->drop_rq);
1898 mlx5e_disable_cq(&priv->drop_rq.cq);
1899 mlx5e_destroy_cq(&priv->drop_rq.cq);
1900}
1901
1902static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1903{
1904 struct mlx5_core_dev *mdev = priv->mdev;
1905 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1906 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1907
1908 memset(in, 0, sizeof(in));
1909
08fb1dac 1910 MLX5_SET(tisc, tisc, prio, tc << 1);
40ab6a6e
AS		 1911 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1912
1913 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1914}
1915
1916static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1917{
1918 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1919}
1920
1921static int mlx5e_create_tises(struct mlx5e_priv *priv)
1922{
1923 int err;
1924 int tc;
1925
08fb1dac 1926 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
40ab6a6e
AS		 1927 err = mlx5e_create_tis(priv, tc);
1928 if (err)
1929 goto err_close_tises;
1930 }
1931
1932 return 0;
1933
1934err_close_tises:
1935 for (tc--; tc >= 0; tc--)
1936 mlx5e_destroy_tis(priv, tc);
1937
1938 return err;
1939}
1940
1941static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1942{
1943 int tc;
1944
08fb1dac 1945 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
40ab6a6e
AS		 1946 mlx5e_destroy_tis(priv, tc);
1947}
1948
1da36696
TT		 1949static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
1950 enum mlx5e_traffic_types tt)
f62b8bb8
AV		 1951{
1952 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1953
3191e05f
AS		 1954 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1955
5a6f8aef
AS		 1956#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1957 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 1958
5a6f8aef
AS		 1959#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1960 MLX5_HASH_FIELD_SEL_DST_IP |\
1961 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1962 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 1963
a741749f
AS		 1964#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1965 MLX5_HASH_FIELD_SEL_DST_IP |\
1966 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1967
5c50368f 1968 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 1969
4cbeaff5 1970 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1da36696
TT		 1971 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn);
1972 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 1973
1974 switch (tt) {
1975 case MLX5E_TT_IPV4_TCP:
1976 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1977 MLX5_L3_PROT_TYPE_IPV4);
1978 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1979 MLX5_L4_PROT_TYPE_TCP);
1980 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1981 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1982 break;
1983
1984 case MLX5E_TT_IPV6_TCP:
1985 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1986 MLX5_L3_PROT_TYPE_IPV6);
1987 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1988 MLX5_L4_PROT_TYPE_TCP);
1989 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1990 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1991 break;
1992
1993 case MLX5E_TT_IPV4_UDP:
1994 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1995 MLX5_L3_PROT_TYPE_IPV4);
1996 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1997 MLX5_L4_PROT_TYPE_UDP);
1998 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1999 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2000 break;
2001
2002 case MLX5E_TT_IPV6_UDP:
2003 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2004 MLX5_L3_PROT_TYPE_IPV6);
2005 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2006 MLX5_L4_PROT_TYPE_UDP);
2007 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2008 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2009 break;
2010
a741749f
AS		 2011 case MLX5E_TT_IPV4_IPSEC_AH:
2012 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2013 MLX5_L3_PROT_TYPE_IPV4);
2014 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2015 MLX5_HASH_IP_IPSEC_SPI);
2016 break;
2017
2018 case MLX5E_TT_IPV6_IPSEC_AH:
2019 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2020 MLX5_L3_PROT_TYPE_IPV6);
2021 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2022 MLX5_HASH_IP_IPSEC_SPI);
2023 break;
2024
2025 case MLX5E_TT_IPV4_IPSEC_ESP:
2026 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2027 MLX5_L3_PROT_TYPE_IPV4);
2028 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2029 MLX5_HASH_IP_IPSEC_SPI);
2030 break;
2031
2032 case MLX5E_TT_IPV6_IPSEC_ESP:
2033 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2034 MLX5_L3_PROT_TYPE_IPV6);
2035 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2036 MLX5_HASH_IP_IPSEC_SPI);
2037 break;
2038
f62b8bb8
AV		 2039 case MLX5E_TT_IPV4:
2040 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2041 MLX5_L3_PROT_TYPE_IPV4);
2042 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2043 MLX5_HASH_IP);
2044 break;
2045
2046 case MLX5E_TT_IPV6:
2047 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2048 MLX5_L3_PROT_TYPE_IPV6);
2049 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2050 MLX5_HASH_IP);
2051 break;
1da36696
TT		 2052 default:
2053 WARN_ONCE(true,
2054 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
f62b8bb8
AV		 2055 }
2056}
2057
1da36696
TT		 2058static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2059 u32 rqtn)
f62b8bb8 2060{
1da36696
TT		 2061 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2062
2063 mlx5e_build_tir_ctx_lro(tirc, priv);
2064
2065 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2066 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2067 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2068}
2069
2070static int mlx5e_create_tirs(struct mlx5e_priv *priv)
2071{
2072 int nch = mlx5e_get_max_num_channels(priv->mdev);
f62b8bb8
AV		 2073 void *tirc;
2074 int inlen;
1da36696 2075 u32 *tirn;
f62b8bb8 2076 int err;
1da36696
TT		 2077 u32 *in;
2078 int ix;
2079 int tt;
f62b8bb8
AV		 2080
2081 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2082 in = mlx5_vzalloc(inlen);
2083 if (!in)
2084 return -ENOMEM;
2085
1da36696
TT		 2086 /* indirect tirs */
2087 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2088 memset(in, 0, inlen);
2089 tirn = &priv->indir_tirn[tt];
2090 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2091 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2092 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
f62b8bb8 2093 if (err)
40ab6a6e 2094 goto err_destroy_tirs;
f62b8bb8
AV		 2095 }
2096
1da36696
TT		 2097 /* direct tirs */
2098 for (ix = 0; ix < nch; ix++) {
2099 memset(in, 0, inlen);
2100 tirn = &priv->direct_tir[ix].tirn;
2101 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2102 mlx5e_build_direct_tir_ctx(priv, tirc,
2103 priv->direct_tir[ix].rqtn);
2104 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2105 if (err)
2106 goto err_destroy_ch_tirs;
2107 }
2108
2109 kvfree(in);
2110
f62b8bb8
AV		 2111 return 0;
2112
1da36696
TT		 2113err_destroy_ch_tirs:
2114 for (ix--; ix >= 0; ix--)
2115 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn);
2116
40ab6a6e 2117err_destroy_tirs:
1da36696
TT		 2118 for (tt--; tt >= 0; tt--)
2119 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]);
2120
2121 kvfree(in);
f62b8bb8
AV		 2122
2123 return err;
2124}
2125
40ab6a6e 2126static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
f62b8bb8 2127{
1da36696 2128 int nch = mlx5e_get_max_num_channels(priv->mdev);
f62b8bb8
AV		 2129 int i;
2130
1da36696
TT		 2131 for (i = 0; i < nch; i++)
2132 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn);
2133
2134 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2135 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]);
f62b8bb8
AV		 2136}
2137
36350114
GP		 2138int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2139{
2140 int err = 0;
2141 int i;
2142
2143 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2144 return 0;
2145
2146 for (i = 0; i < priv->params.num_channels; i++) {
2147 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2148 if (err)
2149 return err;
2150 }
2151
2152 return 0;
2153}
2154
08fb1dac
SM		 2155static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2156{
2157 struct mlx5e_priv *priv = netdev_priv(netdev);
2158 bool was_opened;
2159 int err = 0;
2160
2161 if (tc && tc != MLX5E_MAX_NUM_TC)
2162 return -EINVAL;
2163
2164 mutex_lock(&priv->state_lock);
2165
2166 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2167 if (was_opened)
2168 mlx5e_close_locked(priv->netdev);
2169
2170 priv->params.num_tc = tc ? tc : 1;
2171
2172 if (was_opened)
2173 err = mlx5e_open_locked(priv->netdev);
2174
2175 mutex_unlock(&priv->state_lock);
2176
2177 return err;
2178}
2179
2180static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2181 __be16 proto, struct tc_to_netdev *tc)
2182{
e8f887ac
AV		 2183 struct mlx5e_priv *priv = netdev_priv(dev);
2184
2185 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2186 goto mqprio;
2187
2188 switch (tc->type) {
e3a2b7ed
AV		 2189 case TC_SETUP_CLSFLOWER:
2190 switch (tc->cls_flower->command) {
2191 case TC_CLSFLOWER_REPLACE:
2192 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2193 case TC_CLSFLOWER_DESTROY:
2194 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 2195 case TC_CLSFLOWER_STATS:
2196 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 2197 }
e8f887ac
AV		 2198 default:
2199 return -EOPNOTSUPP;
2200 }
2201
2202mqprio:
67ba422e 2203 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2204 return -EINVAL;
2205
2206 return mlx5e_setup_tc(dev, tc->tc);
2207}
2208
f62b8bb8
AV		 2209static struct rtnl_link_stats64 *
2210mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2211{
2212 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2213 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2214 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2215 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2216
9218b44d
GP		 2217 stats->rx_packets = sstats->rx_packets;
2218 stats->rx_bytes = sstats->rx_bytes;
2219 stats->tx_packets = sstats->tx_packets;
2220 stats->tx_bytes = sstats->tx_bytes;
269e6b3a
GP		 2221
2222 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
9218b44d 2223 stats->tx_dropped = sstats->tx_queue_dropped;
269e6b3a
GP		 2224
2225 stats->rx_length_errors =
9218b44d
GP		 2226 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2227 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2228 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2229 stats->rx_crc_errors =
9218b44d
GP		 2230 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2231 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2232 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2233 stats->tx_carrier_errors =
9218b44d 2234 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2235 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2236 stats->rx_frame_errors;
2237 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2238
2239 /* vport multicast also counts packets that are dropped due to steering
2240 * or rx out of buffer
2241 */
9218b44d
GP		 2242 stats->multicast =
2243 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 2244
2245 return stats;
2246}
2247
2248static void mlx5e_set_rx_mode(struct net_device *dev)
2249{
2250 struct mlx5e_priv *priv = netdev_priv(dev);
2251
7bb29755 2252 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2253}
2254
2255static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2256{
2257 struct mlx5e_priv *priv = netdev_priv(netdev);
2258 struct sockaddr *saddr = addr;
2259
2260 if (!is_valid_ether_addr(saddr->sa_data))
2261 return -EADDRNOTAVAIL;
2262
2263 netif_addr_lock_bh(netdev);
2264 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2265 netif_addr_unlock_bh(netdev);
2266
7bb29755 2267 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2268
2269 return 0;
2270}
2271
0e405443
GP		 2272#define MLX5E_SET_FEATURE(netdev, feature, enable) \
2273 do { \
2274 if (enable) \
2275 netdev->features |= feature; \
2276 else \
2277 netdev->features &= ~feature; \
2278 } while (0)
2279
2280typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2281
2282static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 2283{
2284 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 2285 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2286 int err;
f62b8bb8
AV		 2287
2288 mutex_lock(&priv->state_lock);
f62b8bb8 2289
0e405443
GP		 2290 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2291 mlx5e_close_locked(priv->netdev);
98e81b0a 2292
0e405443
GP		 2293 priv->params.lro_en = enable;
2294 err = mlx5e_modify_tirs_lro(priv);
2295 if (err) {
2296 netdev_err(netdev, "lro modify failed, %d\n", err);
2297 priv->params.lro_en = !enable;
98e81b0a 2298 }
f62b8bb8 2299
0e405443
GP		 2300 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2301 mlx5e_open_locked(priv->netdev);
2302
9b37b07f
AS		 2303 mutex_unlock(&priv->state_lock);
2304
0e405443
GP		 2305 return err;
2306}
2307
2308static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2309{
2310 struct mlx5e_priv *priv = netdev_priv(netdev);
2311
2312 if (enable)
2313 mlx5e_enable_vlan_filter(priv);
2314 else
2315 mlx5e_disable_vlan_filter(priv);
2316
2317 return 0;
2318}
2319
2320static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2321{
2322 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 2323
0e405443 2324 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 2325 netdev_err(netdev,
2326 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2327 return -EINVAL;
2328 }
2329
0e405443
GP		 2330 return 0;
2331}
2332
94cb1ebb
EBE		 2333static int set_feature_rx_all(struct net_device *netdev, bool enable)
2334{
2335 struct mlx5e_priv *priv = netdev_priv(netdev);
2336 struct mlx5_core_dev *mdev = priv->mdev;
2337
2338 return mlx5_set_port_fcs(mdev, !enable);
2339}
2340
36350114
GP		 2341static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2342{
2343 struct mlx5e_priv *priv = netdev_priv(netdev);
2344 int err;
2345
2346 mutex_lock(&priv->state_lock);
2347
2348 priv->params.vlan_strip_disable = !enable;
2349 err = mlx5e_modify_rqs_vsd(priv, !enable);
2350 if (err)
2351 priv->params.vlan_strip_disable = enable;
2352
2353 mutex_unlock(&priv->state_lock);
2354
2355 return err;
2356}
2357
45bf454a
MG		 2358#ifdef CONFIG_RFS_ACCEL
2359static int set_feature_arfs(struct net_device *netdev, bool enable)
2360{
2361 struct mlx5e_priv *priv = netdev_priv(netdev);
2362 int err;
2363
2364 if (enable)
2365 err = mlx5e_arfs_enable(priv);
2366 else
2367 err = mlx5e_arfs_disable(priv);
2368
2369 return err;
2370}
2371#endif
2372
0e405443
GP		 2373static int mlx5e_handle_feature(struct net_device *netdev,
2374 netdev_features_t wanted_features,
2375 netdev_features_t feature,
2376 mlx5e_feature_handler feature_handler)
2377{
2378 netdev_features_t changes = wanted_features ^ netdev->features;
2379 bool enable = !!(wanted_features & feature);
2380 int err;
2381
2382 if (!(changes & feature))
2383 return 0;
2384
2385 err = feature_handler(netdev, enable);
2386 if (err) {
2387 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2388 enable ? "Enable" : "Disable", feature, err);
2389 return err;
2390 }
2391
2392 MLX5E_SET_FEATURE(netdev, feature, enable);
2393 return 0;
2394}
2395
2396static int mlx5e_set_features(struct net_device *netdev,
2397 netdev_features_t features)
2398{
2399 int err;
2400
2401 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2402 set_feature_lro);
2403 err |= mlx5e_handle_feature(netdev, features,
2404 NETIF_F_HW_VLAN_CTAG_FILTER,
2405 set_feature_vlan_filter);
2406 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2407 set_feature_tc_num_filters);
94cb1ebb
EBE		 2408 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2409 set_feature_rx_all);
36350114
GP		 2410 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2411 set_feature_rx_vlan);
45bf454a
MG		 2412#ifdef CONFIG_RFS_ACCEL
2413 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2414 set_feature_arfs);
2415#endif
0e405443
GP		 2416
2417 return err ? -EINVAL : 0;
f62b8bb8
AV		 2418}
2419
d8edd246
SM		 2420#define MXL5_HW_MIN_MTU 64
2421#define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2422
f62b8bb8
AV		 2423static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2424{
2425 struct mlx5e_priv *priv = netdev_priv(netdev);
2426 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 2427 bool was_opened;
046339ea 2428 u16 max_mtu;
d8edd246 2429 u16 min_mtu;
98e81b0a 2430 int err = 0;
f62b8bb8 2431
facc9699 2432 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 2433
50a9eea6 2434 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
d8edd246 2435 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
50a9eea6 2436
d8edd246 2437 if (new_mtu > max_mtu || new_mtu < min_mtu) {
facc9699 2438 netdev_err(netdev,
d8edd246
SM		 2439 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2440 __func__, new_mtu, min_mtu, max_mtu);
f62b8bb8
AV		 2441 return -EINVAL;
2442 }
2443
2444 mutex_lock(&priv->state_lock);
98e81b0a
AS		 2445
2446 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2447 if (was_opened)
2448 mlx5e_close_locked(netdev);
2449
f62b8bb8 2450 netdev->mtu = new_mtu;
98e81b0a
AS		 2451
2452 if (was_opened)
2453 err = mlx5e_open_locked(netdev);
2454
f62b8bb8
AV		 2455 mutex_unlock(&priv->state_lock);
2456
2457 return err;
2458}
2459
ef9814de
EBE		 2460static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2461{
2462 switch (cmd) {
2463 case SIOCSHWTSTAMP:
2464 return mlx5e_hwstamp_set(dev, ifr);
2465 case SIOCGHWTSTAMP:
2466 return mlx5e_hwstamp_get(dev, ifr);
2467 default:
2468 return -EOPNOTSUPP;
2469 }
2470}
2471
66e49ded
SM		 2472static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2473{
2474 struct mlx5e_priv *priv = netdev_priv(dev);
2475 struct mlx5_core_dev *mdev = priv->mdev;
2476
2477 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2478}
2479
2480static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2481{
2482 struct mlx5e_priv *priv = netdev_priv(dev);
2483 struct mlx5_core_dev *mdev = priv->mdev;
2484
2485 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2486 vlan, qos);
2487}
2488
f942380c
MHY		 2489static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2490{
2491 struct mlx5e_priv *priv = netdev_priv(dev);
2492 struct mlx5_core_dev *mdev = priv->mdev;
2493
2494 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2495}
2496
1edc57e2
MHY		 2497static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2498{
2499 struct mlx5e_priv *priv = netdev_priv(dev);
2500 struct mlx5_core_dev *mdev = priv->mdev;
2501
2502 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2503}
66e49ded
SM		 2504static int mlx5_vport_link2ifla(u8 esw_link)
2505{
2506 switch (esw_link) {
2507 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2508 return IFLA_VF_LINK_STATE_DISABLE;
2509 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2510 return IFLA_VF_LINK_STATE_ENABLE;
2511 }
2512 return IFLA_VF_LINK_STATE_AUTO;
2513}
2514
2515static int mlx5_ifla_link2vport(u8 ifla_link)
2516{
2517 switch (ifla_link) {
2518 case IFLA_VF_LINK_STATE_DISABLE:
2519 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2520 case IFLA_VF_LINK_STATE_ENABLE:
2521 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2522 }
2523 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2524}
2525
2526static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2527 int link_state)
2528{
2529 struct mlx5e_priv *priv = netdev_priv(dev);
2530 struct mlx5_core_dev *mdev = priv->mdev;
2531
2532 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2533 mlx5_ifla_link2vport(link_state));
2534}
2535
2536static int mlx5e_get_vf_config(struct net_device *dev,
2537 int vf, struct ifla_vf_info *ivi)
2538{
2539 struct mlx5e_priv *priv = netdev_priv(dev);
2540 struct mlx5_core_dev *mdev = priv->mdev;
2541 int err;
2542
2543 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2544 if (err)
2545 return err;
2546 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2547 return 0;
2548}
2549
2550static int mlx5e_get_vf_stats(struct net_device *dev,
2551 int vf, struct ifla_vf_stats *vf_stats)
2552{
2553 struct mlx5e_priv *priv = netdev_priv(dev);
2554 struct mlx5_core_dev *mdev = priv->mdev;
2555
2556 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2557 vf_stats);
2558}
2559
b3f63c3d
MF		 2560static void mlx5e_add_vxlan_port(struct net_device *netdev,
2561 sa_family_t sa_family, __be16 port)
2562{
2563 struct mlx5e_priv *priv = netdev_priv(netdev);
2564
2565 if (!mlx5e_vxlan_allowed(priv->mdev))
2566 return;
2567
d8cf2dda 2568 mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 1);
b3f63c3d
MF		 2569}
2570
2571static void mlx5e_del_vxlan_port(struct net_device *netdev,
2572 sa_family_t sa_family, __be16 port)
2573{
2574 struct mlx5e_priv *priv = netdev_priv(netdev);
2575
2576 if (!mlx5e_vxlan_allowed(priv->mdev))
2577 return;
2578
d8cf2dda 2579 mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 0);
b3f63c3d
MF		 2580}
2581
2582static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2583 struct sk_buff *skb,
2584 netdev_features_t features)
2585{
2586 struct udphdr *udph;
2587 u16 proto;
2588 u16 port = 0;
2589
2590 switch (vlan_get_protocol(skb)) {
2591 case htons(ETH_P_IP):
2592 proto = ip_hdr(skb)->protocol;
2593 break;
2594 case htons(ETH_P_IPV6):
2595 proto = ipv6_hdr(skb)->nexthdr;
2596 break;
2597 default:
2598 goto out;
2599 }
2600
2601 if (proto == IPPROTO_UDP) {
2602 udph = udp_hdr(skb);
2603 port = be16_to_cpu(udph->dest);
2604 }
2605
2606 /* Verify if UDP port is being offloaded by HW */
2607 if (port && mlx5e_vxlan_lookup_port(priv, port))
2608 return features;
2609
2610out:
2611 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2612 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2613}
2614
2615static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2616 struct net_device *netdev,
2617 netdev_features_t features)
2618{
2619 struct mlx5e_priv *priv = netdev_priv(netdev);
2620
2621 features = vlan_features_check(skb, features);
2622 features = vxlan_features_check(skb, features);
2623
2624 /* Validate if the tunneled packet is being offloaded by HW */
2625 if (skb->encapsulation &&
2626 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2627 return mlx5e_vxlan_features_check(priv, skb, features);
2628
2629 return features;
2630}
2631
3947ca18
DJ		 2632static void mlx5e_tx_timeout(struct net_device *dev)
2633{
2634 struct mlx5e_priv *priv = netdev_priv(dev);
2635 bool sched_work = false;
2636 int i;
2637
2638 netdev_err(dev, "TX timeout detected\n");
2639
2640 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2641 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2642
2643 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
2644 continue;
2645 sched_work = true;
2646 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
2647 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2648 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2649 }
2650
2651 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2652 schedule_work(&priv->tx_timeout_work);
2653}
2654
b0eed40e 2655static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 2656 .ndo_open = mlx5e_open,
2657 .ndo_stop = mlx5e_close,
2658 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2659 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2660 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 2661 .ndo_get_stats64 = mlx5e_get_stats,
2662 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2663 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 2664 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2665 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 2666 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 2667 .ndo_change_mtu = mlx5e_change_mtu,
2668 .ndo_do_ioctl = mlx5e_ioctl,
45bf454a
MG		 2669#ifdef CONFIG_RFS_ACCEL
2670 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2671#endif
3947ca18 2672 .ndo_tx_timeout = mlx5e_tx_timeout,
b0eed40e
SM		 2673};
2674
2675static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2676 .ndo_open = mlx5e_open,
2677 .ndo_stop = mlx5e_close,
2678 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2679 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2680 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 2681 .ndo_get_stats64 = mlx5e_get_stats,
2682 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2683 .ndo_set_mac_address = mlx5e_set_mac,
2684 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2685 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2686 .ndo_set_features = mlx5e_set_features,
2687 .ndo_change_mtu = mlx5e_change_mtu,
2688 .ndo_do_ioctl = mlx5e_ioctl,
b3f63c3d
MF		 2689 .ndo_add_vxlan_port = mlx5e_add_vxlan_port,
2690 .ndo_del_vxlan_port = mlx5e_del_vxlan_port,
2691 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 2692#ifdef CONFIG_RFS_ACCEL
2693 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2694#endif
b0eed40e
SM		 2695 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2696 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 2697 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 2698 .ndo_set_vf_trust = mlx5e_set_vf_trust,
b0eed40e
SM		 2699 .ndo_get_vf_config = mlx5e_get_vf_config,
2700 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2701 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 2702 .ndo_tx_timeout = mlx5e_tx_timeout,
f62b8bb8
AV		 2703};
2704
2705static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2706{
2707 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2708 return -ENOTSUPP;
2709 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2710 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2711 !MLX5_CAP_ETH(mdev, csum_cap) ||
2712 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2713 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 2714 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2715 MLX5_CAP_FLOWTABLE(mdev,
2716 flow_table_properties_nic_receive.max_ft_level)
2717 < 3) {
f62b8bb8
AV		 2718 mlx5_core_warn(mdev,
2719 "Not creating net device, some required device capabilities are missing\n");
2720 return -ENOTSUPP;
2721 }
66189961
TT		 2722 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2723 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 2724 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2725 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 2726
f62b8bb8
AV		 2727 return 0;
2728}
2729
58d52291
AS		 2730u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2731{
2732 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2733
2734 return bf_buf_size -
2735 sizeof(struct mlx5e_tx_wqe) +
2736 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2737}
2738
08fb1dac
SM		 2739#ifdef CONFIG_MLX5_CORE_EN_DCB
2740static void mlx5e_ets_init(struct mlx5e_priv *priv)
2741{
2742 int i;
2743
2744 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2745 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2746 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2747 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2748 priv->params.ets.prio_tc[i] = i;
2749 }
2750
2751 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2752 priv->params.ets.prio_tc[0] = 1;
2753 priv->params.ets.prio_tc[1] = 0;
2754}
2755#endif
2756
d8c9660d
TT		 2757void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2758 u32 *indirection_rqt, int len,
85082dba
TT		 2759 int num_channels)
2760{
d8c9660d
TT		 2761 int node = mdev->priv.numa_node;
2762 int node_num_of_cores;
85082dba
TT		 2763 int i;
2764
d8c9660d
TT		 2765 if (node == -1)
2766 node = first_online_node;
2767
2768 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2769
2770 if (node_num_of_cores)
2771 num_channels = min_t(int, num_channels, node_num_of_cores);
2772
85082dba
TT		 2773 for (i = 0; i < len; i++)
2774 indirection_rqt[i] = i % num_channels;
2775}
2776
bc77b240
TT		 2777static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2778{
2779 return MLX5_CAP_GEN(mdev, striding_rq) &&
2780 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2781 MLX5_CAP_ETH(mdev, reg_umr_sq);
2782}
2783
b797a684
SM		 2784static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2785{
2786 enum pcie_link_width width;
2787 enum pci_bus_speed speed;
2788 int err = 0;
2789
2790 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2791 if (err)
2792 return err;
2793
2794 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2795 return -EINVAL;
2796
2797 switch (speed) {
2798 case PCIE_SPEED_2_5GT:
2799 *pci_bw = 2500 * width;
2800 break;
2801 case PCIE_SPEED_5_0GT:
2802 *pci_bw = 5000 * width;
2803 break;
2804 case PCIE_SPEED_8_0GT:
2805 *pci_bw = 8000 * width;
2806 break;
2807 default:
2808 return -EINVAL;
2809 }
2810
2811 return 0;
2812}
2813
2814static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2815{
2816 return (link_speed && pci_bw &&
2817 (pci_bw < 40000) && (pci_bw < link_speed));
2818}
2819
f62b8bb8
AV		 2820static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2821 struct net_device *netdev,
936896e9 2822 int num_channels)
f62b8bb8
AV		 2823{
2824 struct mlx5e_priv *priv = netdev_priv(netdev);
b797a684
SM		 2825 u32 link_speed = 0;
2826 u32 pci_bw = 0;
f62b8bb8
AV		 2827
2828 priv->params.log_sq_size =
2829 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
bc77b240 2830 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
461017cb
TT		 2831 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2832 MLX5_WQ_TYPE_LINKED_LIST;
2833
b797a684
SM		 2834 /* set CQE compression */
2835 priv->params.rx_cqe_compress_admin = false;
2836 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
2837 MLX5_CAP_GEN(mdev, vport_group_manager)) {
2838 mlx5e_get_max_linkspeed(mdev, &link_speed);
2839 mlx5e_get_pci_bw(mdev, &pci_bw);
2840 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
2841 link_speed, pci_bw);
2842 priv->params.rx_cqe_compress_admin =
2843 cqe_compress_heuristic(link_speed, pci_bw);
2844 }
2845
2846 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
2847
461017cb
TT		 2848 switch (priv->params.rq_wq_type) {
2849 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2850 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
d9d9f156
TT		 2851 priv->params.mpwqe_log_stride_sz =
2852 priv->params.rx_cqe_compress ?
2853 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
2854 MLX5_MPWRQ_LOG_STRIDE_SIZE;
2855 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
2856 priv->params.mpwqe_log_stride_sz;
461017cb
TT		 2857 priv->params.lro_en = true;
2858 break;
2859 default: /* MLX5_WQ_TYPE_LINKED_LIST */
2860 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2861 }
2862
d9d9f156
TT		 2863 mlx5_core_info(mdev,
2864 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
2865 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
2866 BIT(priv->params.log_rq_size),
2867 BIT(priv->params.mpwqe_log_stride_sz),
2868 priv->params.rx_cqe_compress_admin);
2869
461017cb
TT		 2870 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2871 BIT(priv->params.log_rq_size));
f62b8bb8
AV		 2872 priv->params.rx_cq_moderation_usec =
2873 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2874 priv->params.rx_cq_moderation_pkts =
2875 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2876 priv->params.tx_cq_moderation_usec =
2877 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2878 priv->params.tx_cq_moderation_pkts =
2879 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 2880 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
f62b8bb8 2881 priv->params.num_tc = 1;
2be6967c 2882 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 2883
57afead5
AS		 2884 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2885 sizeof(priv->params.toeplitz_hash_key));
2886
d8c9660d 2887 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
85082dba 2888 MLX5E_INDIR_RQT_SIZE, num_channels);
2d75b2bc 2889
f62b8bb8
AV		 2890 priv->params.lro_wqe_sz =
2891 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2892
2893 priv->mdev = mdev;
2894 priv->netdev = netdev;
936896e9 2895 priv->params.num_channels = num_channels;
f62b8bb8 2896
08fb1dac
SM		 2897#ifdef CONFIG_MLX5_CORE_EN_DCB
2898 mlx5e_ets_init(priv);
2899#endif
f62b8bb8 2900
f62b8bb8
AV		 2901 mutex_init(&priv->state_lock);
2902
2903 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2904 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 2905 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 2906 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2907}
2908
2909static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2910{
2911 struct mlx5e_priv *priv = netdev_priv(netdev);
2912
e1d7d349 2913 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 2914 if (is_zero_ether_addr(netdev->dev_addr) &&
2915 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2916 eth_hw_addr_random(netdev);
2917 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2918 }
f62b8bb8
AV		 2919}
2920
2921static void mlx5e_build_netdev(struct net_device *netdev)
2922{
2923 struct mlx5e_priv *priv = netdev_priv(netdev);
2924 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 2925 bool fcs_supported;
2926 bool fcs_enabled;
f62b8bb8
AV		 2927
2928 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2929
08fb1dac 2930 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 2931 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac
SM		 2932#ifdef CONFIG_MLX5_CORE_EN_DCB
2933 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2934#endif
2935 } else {
b0eed40e 2936 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 2937 }
66e49ded 2938
f62b8bb8
AV		 2939 netdev->watchdog_timeo = 15 * HZ;
2940
2941 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2942
12be4b21 2943 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 2944 netdev->vlan_features |= NETIF_F_IP_CSUM;
2945 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2946 netdev->vlan_features |= NETIF_F_GRO;
2947 netdev->vlan_features |= NETIF_F_TSO;
2948 netdev->vlan_features |= NETIF_F_TSO6;
2949 netdev->vlan_features |= NETIF_F_RXCSUM;
2950 netdev->vlan_features |= NETIF_F_RXHASH;
2951
2952 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2953 netdev->vlan_features |= NETIF_F_LRO;
2954
2955 netdev->hw_features = netdev->vlan_features;
e4cf27bd 2956 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 2957 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2958 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2959
b3f63c3d 2960 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 2961 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
2962 NETIF_F_GSO_UDP_TUNNEL_CSUM |
2963 NETIF_F_GSO_PARTIAL;
b3f63c3d 2964 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 2965 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 2966 netdev->hw_enc_features |= NETIF_F_TSO;
2967 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 2968 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 2969 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
2970 NETIF_F_GSO_PARTIAL;
2971 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 2972 }
2973
94cb1ebb
EBE		 2974 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
2975
2976 if (fcs_supported)
2977 netdev->hw_features |= NETIF_F_RXALL;
2978
f62b8bb8
AV		 2979 netdev->features = netdev->hw_features;
2980 if (!priv->params.lro_en)
2981 netdev->features &= ~NETIF_F_LRO;
2982
94cb1ebb
EBE		 2983 if (fcs_enabled)
2984 netdev->features &= ~NETIF_F_RXALL;
2985
e8f887ac
AV		 2986#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2987 if (FT_CAP(flow_modify_en) &&
2988 FT_CAP(modify_root) &&
2989 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 2990 FT_CAP(flow_table_modify)) {
2991 netdev->hw_features |= NETIF_F_HW_TC;
2992#ifdef CONFIG_RFS_ACCEL
2993 netdev->hw_features |= NETIF_F_NTUPLE;
2994#endif
2995 }
e8f887ac 2996
f62b8bb8
AV		 2997 netdev->features |= NETIF_F_HIGHDMA;
2998
2999 netdev->priv_flags |= IFF_UNICAST_FLT;
3000
3001 mlx5e_set_netdev_dev_addr(netdev);
3002}
3003
3004static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
a606b0f6 3005 struct mlx5_core_mkey *mkey)
f62b8bb8
AV		 3006{
3007 struct mlx5_core_dev *mdev = priv->mdev;
3008 struct mlx5_create_mkey_mbox_in *in;
3009 int err;
3010
3011 in = mlx5_vzalloc(sizeof(*in));
3012 if (!in)
3013 return -ENOMEM;
3014
3015 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
3016 MLX5_PERM_LOCAL_READ |
3017 MLX5_ACCESS_MODE_PA;
3018 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
3019 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3020
a606b0f6 3021 err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
f62b8bb8
AV		 3022 NULL);
3023
3024 kvfree(in);
3025
3026 return err;
3027}
3028
593cf338
RS		 3029static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3030{
3031 struct mlx5_core_dev *mdev = priv->mdev;
3032 int err;
3033
3034 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3035 if (err) {
3036 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3037 priv->q_counter = 0;
3038 }
3039}
3040
3041static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3042{
3043 if (!priv->q_counter)
3044 return;
3045
3046 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3047}
3048
bc77b240
TT		 3049static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3050{
3051 struct mlx5_core_dev *mdev = priv->mdev;
3052 struct mlx5_create_mkey_mbox_in *in;
3053 struct mlx5_mkey_seg *mkc;
3054 int inlen = sizeof(*in);
3055 u64 npages =
3056 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
3057 int err;
3058
3059 in = mlx5_vzalloc(inlen);
3060 if (!in)
3061 return -ENOMEM;
3062
3063 mkc = &in->seg;
3064 mkc->status = MLX5_MKEY_STATUS_FREE;
3065 mkc->flags = MLX5_PERM_UMR_EN |
3066 MLX5_PERM_LOCAL_READ |
3067 MLX5_PERM_LOCAL_WRITE |
3068 MLX5_ACCESS_MODE_MTT;
3069
3070 mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3071 mkc->flags_pd = cpu_to_be32(priv->pdn);
3072 mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3073 mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
3074 mkc->log2_page_size = PAGE_SHIFT;
3075
3076 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3077 NULL, NULL);
3078
3079 kvfree(in);
3080
3081 return err;
3082}
3083
f62b8bb8
AV		 3084static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
3085{
3086 struct net_device *netdev;
3087 struct mlx5e_priv *priv;
3435ab59 3088 int nch = mlx5e_get_max_num_channels(mdev);
f62b8bb8
AV		 3089 int err;
3090
3091 if (mlx5e_check_required_hca_cap(mdev))
3092 return NULL;
3093
08fb1dac
SM		 3094 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3095 nch * MLX5E_MAX_NUM_TC,
3096 nch);
f62b8bb8
AV		 3097 if (!netdev) {
3098 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3099 return NULL;
3100 }
3101
936896e9 3102 mlx5e_build_netdev_priv(mdev, netdev, nch);
f62b8bb8
AV		 3103 mlx5e_build_netdev(netdev);
3104
3105 netif_carrier_off(netdev);
3106
3107 priv = netdev_priv(netdev);
3108
7bb29755
MF		 3109 priv->wq = create_singlethread_workqueue("mlx5e");
3110 if (!priv->wq)
3111 goto err_free_netdev;
3112
0ba42241 3113 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
f62b8bb8 3114 if (err) {
1f2a3003 3115 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
7bb29755 3116 goto err_destroy_wq;
f62b8bb8
AV		 3117 }
3118
3119 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3120 if (err) {
1f2a3003 3121 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
f62b8bb8
AV		 3122 goto err_unmap_free_uar;
3123 }
3124
8d7f9ecb 3125 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3191e05f 3126 if (err) {
1f2a3003 3127 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3191e05f
AS		 3128 goto err_dealloc_pd;
3129 }
3130
a606b0f6 3131 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
f62b8bb8 3132 if (err) {
1f2a3003 3133 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3191e05f 3134 goto err_dealloc_transport_domain;
f62b8bb8
AV		 3135 }
3136
bc77b240
TT		 3137 err = mlx5e_create_umr_mkey(priv);
3138 if (err) {
3139 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3140 goto err_destroy_mkey;
3141 }
3142
40ab6a6e 3143 err = mlx5e_create_tises(priv);
5c50368f 3144 if (err) {
40ab6a6e 3145 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
bc77b240 3146 goto err_destroy_umr_mkey;
5c50368f
AS		 3147 }
3148
3149 err = mlx5e_open_drop_rq(priv);
3150 if (err) {
3151 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
40ab6a6e 3152 goto err_destroy_tises;
5c50368f
AS		 3153 }
3154
1da36696 3155 err = mlx5e_create_rqts(priv);
5c50368f 3156 if (err) {
1da36696 3157 mlx5_core_warn(mdev, "create rqts failed, %d\n", err);
5c50368f
AS		 3158 goto err_close_drop_rq;
3159 }
3160
40ab6a6e 3161 err = mlx5e_create_tirs(priv);
5c50368f 3162 if (err) {
40ab6a6e 3163 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
1da36696 3164 goto err_destroy_rqts;
5c50368f
AS		 3165 }
3166
acff797c 3167 err = mlx5e_create_flow_steering(priv);
5c50368f 3168 if (err) {
acff797c 3169 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
40ab6a6e 3170 goto err_destroy_tirs;
5c50368f
AS		 3171 }
3172
593cf338
RS		 3173 mlx5e_create_q_counter(priv);
3174
33cfaaa8 3175 mlx5e_init_l2_addr(priv);
5c50368f 3176
b3f63c3d
MF		 3177 mlx5e_vxlan_init(priv);
3178
e8f887ac
AV		 3179 err = mlx5e_tc_init(priv);
3180 if (err)
593cf338 3181 goto err_dealloc_q_counters;
e8f887ac 3182
08fb1dac
SM		 3183#ifdef CONFIG_MLX5_CORE_EN_DCB
3184 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3185#endif
3186
f62b8bb8
AV		 3187 err = register_netdev(netdev);
3188 if (err) {
1f2a3003 3189 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
e8f887ac 3190 goto err_tc_cleanup;
f62b8bb8
AV		 3191 }
3192
01a14098
MF		 3193 if (mlx5e_vxlan_allowed(mdev)) {
3194 rtnl_lock();
b3f63c3d 3195 vxlan_get_rx_port(netdev);
01a14098
MF		 3196 rtnl_unlock();
3197 }
b3f63c3d 3198
f62b8bb8 3199 mlx5e_enable_async_events(priv);
7bb29755 3200 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3201
3202 return priv;
3203
e8f887ac
AV		 3204err_tc_cleanup:
3205 mlx5e_tc_cleanup(priv);
3206
593cf338
RS		 3207err_dealloc_q_counters:
3208 mlx5e_destroy_q_counter(priv);
acff797c 3209 mlx5e_destroy_flow_steering(priv);
5c50368f 3210
40ab6a6e
AS		 3211err_destroy_tirs:
3212 mlx5e_destroy_tirs(priv);
5c50368f 3213
1da36696
TT		 3214err_destroy_rqts:
3215 mlx5e_destroy_rqts(priv);
5c50368f
AS		 3216
3217err_close_drop_rq:
3218 mlx5e_close_drop_rq(priv);
3219
40ab6a6e
AS		 3220err_destroy_tises:
3221 mlx5e_destroy_tises(priv);
5c50368f 3222
bc77b240
TT		 3223err_destroy_umr_mkey:
3224 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3225
f62b8bb8 3226err_destroy_mkey:
a606b0f6 3227 mlx5_core_destroy_mkey(mdev, &priv->mkey);
f62b8bb8 3228
3191e05f 3229err_dealloc_transport_domain:
8d7f9ecb 3230 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3191e05f 3231
f62b8bb8
AV		 3232err_dealloc_pd:
3233 mlx5_core_dealloc_pd(mdev, priv->pdn);
3234
3235err_unmap_free_uar:
3236 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3237
7bb29755
MF		 3238err_destroy_wq:
3239 destroy_workqueue(priv->wq);
3240
f62b8bb8
AV		 3241err_free_netdev:
3242 free_netdev(netdev);
3243
3244 return NULL;
3245}
3246
3247static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
3248{
3249 struct mlx5e_priv *priv = vpriv;
3250 struct net_device *netdev = priv->netdev;
3251
9b37b07f
AS		 3252 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3253
7bb29755 3254 queue_work(priv->wq, &priv->set_rx_mode_work);
1cefa326 3255 mlx5e_disable_async_events(priv);
7bb29755 3256 flush_workqueue(priv->wq);
5fc7197d
MD		 3257 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3258 netif_device_detach(netdev);
811afeaa 3259 mlx5e_close(netdev);
5fc7197d
MD		 3260 } else {
3261 unregister_netdev(netdev);
3262 }
3263
e8f887ac 3264 mlx5e_tc_cleanup(priv);
b3f63c3d 3265 mlx5e_vxlan_cleanup(priv);
593cf338 3266 mlx5e_destroy_q_counter(priv);
acff797c 3267 mlx5e_destroy_flow_steering(priv);
40ab6a6e 3268 mlx5e_destroy_tirs(priv);
1da36696 3269 mlx5e_destroy_rqts(priv);
5c50368f 3270 mlx5e_close_drop_rq(priv);
40ab6a6e 3271 mlx5e_destroy_tises(priv);
bc77b240 3272 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
a606b0f6 3273 mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
8d7f9ecb 3274 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
f62b8bb8
AV		 3275 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3276 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
7bb29755
MF		 3277 cancel_delayed_work_sync(&priv->update_stats_work);
3278 destroy_workqueue(priv->wq);
5fc7197d
MD		 3279
3280 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3281 free_netdev(netdev);
f62b8bb8
AV		 3282}
3283
3284static void *mlx5e_get_netdev(void *vpriv)
3285{
3286 struct mlx5e_priv *priv = vpriv;
3287
3288 return priv->netdev;
3289}
3290
3291static struct mlx5_interface mlx5e_interface = {
3292 .add = mlx5e_create_netdev,
3293 .remove = mlx5e_destroy_netdev,
3294 .event = mlx5e_async_event,
3295 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3296 .get_dev = mlx5e_get_netdev,
3297};
3298
3299void mlx5e_init(void)
3300{
3301 mlx5_register_interface(&mlx5e_interface);
3302}
3303
3304void mlx5e_cleanup(void)
3305{
3306 mlx5_unregister_interface(&mlx5e_interface);
3307}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git