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net: Add net-device param to the get offloaded stats ndo
[thirdparty/kernel/stable.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
f62b8bb8 38#include "en.h"
e8f887ac 39#include "en_tc.h"
66e49ded 40#include "eswitch.h"
b3f63c3d 41#include "vxlan.h"
f62b8bb8
AV		 42
43struct mlx5e_rq_param {
cb3c7fd4
GR		 44 u32 rqc[MLX5_ST_SZ_DW(rqc)];
45 struct mlx5_wq_param wq;
46 bool am_enabled;
f62b8bb8
AV		 47};
48
49struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
58d52291 52 u16 max_inline;
cff92d7c 53 u8 min_inline_mode;
f10b7cc7 54 enum mlx5e_sq_type type;
f62b8bb8
AV		 55};
56
57struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
9908aa29 61 u8 cq_period_mode;
f62b8bb8
AV		 62};
63
64struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
b5503b99 67 struct mlx5e_sq_param xdp_sq;
d3c9bc27 68 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
d3c9bc27 71 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 72};
73
2fc4bfb7
SM		 74static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75{
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
79}
80
81static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
82{
83 priv->params.rq_wq_type = rq_type;
84 switch (priv->params.rq_wq_type) {
85 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
86 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
87 priv->params.mpwqe_log_stride_sz = priv->params.rx_cqe_compress ?
88 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
89 MLX5_MPWRQ_LOG_STRIDE_SIZE;
90 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
91 priv->params.mpwqe_log_stride_sz;
92 break;
93 default: /* MLX5_WQ_TYPE_LINKED_LIST */
94 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
95 }
96 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
97 BIT(priv->params.log_rq_size));
98
99 mlx5_core_info(priv->mdev,
100 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
101 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
102 BIT(priv->params.log_rq_size),
103 BIT(priv->params.mpwqe_log_stride_sz),
104 priv->params.rx_cqe_compress_admin);
105}
106
107static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
108{
86994156
RS		 109 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
110 !priv->xdp_prog ?
2fc4bfb7
SM		 111 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
112 MLX5_WQ_TYPE_LINKED_LIST;
113 mlx5e_set_rq_type_params(priv, rq_type);
114}
115
f62b8bb8
AV		 116static void mlx5e_update_carrier(struct mlx5e_priv *priv)
117{
118 struct mlx5_core_dev *mdev = priv->mdev;
119 u8 port_state;
120
121 port_state = mlx5_query_vport_state(mdev,
e7546514 122 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8 123
87424ad5
SD		 124 if (port_state == VPORT_STATE_UP) {
125 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 126 netif_carrier_on(priv->netdev);
87424ad5
SD		 127 } else {
128 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 129 netif_carrier_off(priv->netdev);
87424ad5 130 }
f62b8bb8
AV		 131}
132
133static void mlx5e_update_carrier_work(struct work_struct *work)
134{
135 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
136 update_carrier_work);
137
138 mutex_lock(&priv->state_lock);
139 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
140 mlx5e_update_carrier(priv);
141 mutex_unlock(&priv->state_lock);
142}
143
3947ca18
DJ		 144static void mlx5e_tx_timeout_work(struct work_struct *work)
145{
146 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
147 tx_timeout_work);
148 int err;
149
150 rtnl_lock();
151 mutex_lock(&priv->state_lock);
152 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
153 goto unlock;
154 mlx5e_close_locked(priv->netdev);
155 err = mlx5e_open_locked(priv->netdev);
156 if (err)
157 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
158 err);
159unlock:
160 mutex_unlock(&priv->state_lock);
161 rtnl_unlock();
162}
163
9218b44d 164static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 165{
9218b44d 166 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 167 struct mlx5e_rq_stats *rq_stats;
168 struct mlx5e_sq_stats *sq_stats;
9218b44d 169 u64 tx_offload_none = 0;
f62b8bb8
AV		 170 int i, j;
171
9218b44d 172 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 173 for (i = 0; i < priv->params.num_channels; i++) {
174 rq_stats = &priv->channel[i]->rq.stats;
175
faf4478b
GP		 176 s->rx_packets += rq_stats->packets;
177 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 178 s->rx_lro_packets += rq_stats->lro_packets;
179 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 180 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 181 s->rx_csum_complete += rq_stats->csum_complete;
182 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 183 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 184 s->rx_xdp_tx += rq_stats->xdp_tx;
185 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 186 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 187 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 188 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 189 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
190 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
4415a031
TT		 191 s->rx_cache_reuse += rq_stats->cache_reuse;
192 s->rx_cache_full += rq_stats->cache_full;
193 s->rx_cache_empty += rq_stats->cache_empty;
194 s->rx_cache_busy += rq_stats->cache_busy;
f62b8bb8 195
a4418a6c 196 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 197 sq_stats = &priv->channel[i]->sq[j].stats;
198
faf4478b
GP		 199 s->tx_packets += sq_stats->packets;
200 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 201 s->tx_tso_packets += sq_stats->tso_packets;
202 s->tx_tso_bytes += sq_stats->tso_bytes;
203 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
204 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 205 s->tx_queue_stopped += sq_stats->stopped;
206 s->tx_queue_wake += sq_stats->wake;
207 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 208 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1
GP		 209 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
210 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 211 }
212 }
213
9218b44d 214 /* Update calculated offload counters */
bfe6d8d1
GP		 215 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
216 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 217
bfe6d8d1 218 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 219 priv->stats.pport.phy_counters,
220 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 221}
222
223static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
224{
225 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
226 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 227 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 228 struct mlx5_core_dev *mdev = priv->mdev;
229
f62b8bb8
AV		 230 MLX5_SET(query_vport_counter_in, in, opcode,
231 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
232 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
233 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
234
235 memset(out, 0, outlen);
9218b44d
GP		 236 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
237}
238
239static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
240{
241 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
242 struct mlx5_core_dev *mdev = priv->mdev;
243 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 244 int prio;
9218b44d
GP		 245 void *out;
246 u32 *in;
247
248 in = mlx5_vzalloc(sz);
249 if (!in)
f62b8bb8
AV		 250 goto free_out;
251
9218b44d 252 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 253
9218b44d
GP		 254 out = pstats->IEEE_802_3_counters;
255 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
256 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 257
9218b44d
GP		 258 out = pstats->RFC_2863_counters;
259 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
260 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
261
262 out = pstats->RFC_2819_counters;
263 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
264 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 265
121fcdc8
GP		 266 out = pstats->phy_counters;
267 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
268 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
269
cf678570
GP		 270 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
271 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
272 out = pstats->per_prio_counters[prio];
273 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
274 mlx5_core_access_reg(mdev, in, sz, out, sz,
275 MLX5_REG_PPCNT, 0, 0);
276 }
277
f62b8bb8 278free_out:
9218b44d
GP		 279 kvfree(in);
280}
281
282static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
283{
284 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
285
286 if (!priv->q_counter)
287 return;
288
289 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
290 &qcnt->rx_out_of_buffer);
291}
292
9c726239
GP		 293static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
294{
295 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
296 struct mlx5_core_dev *mdev = priv->mdev;
297 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
298 void *out;
299 u32 *in;
300
301 in = mlx5_vzalloc(sz);
302 if (!in)
303 return;
304
305 out = pcie_stats->pcie_perf_counters;
306 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
307 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
308
309 out = pcie_stats->pcie_tas_counters;
310 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
311 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
312
313 kvfree(in);
314}
315
9218b44d
GP		 316void mlx5e_update_stats(struct mlx5e_priv *priv)
317{
9218b44d
GP		 318 mlx5e_update_q_counter(priv);
319 mlx5e_update_vport_counters(priv);
320 mlx5e_update_pport_counters(priv);
121fcdc8 321 mlx5e_update_sw_counters(priv);
9c726239 322 mlx5e_update_pcie_counters(priv);
f62b8bb8
AV		 323}
324
cb67b832 325void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 326{
327 struct delayed_work *dwork = to_delayed_work(work);
328 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
329 update_stats_work);
330 mutex_lock(&priv->state_lock);
331 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 332 priv->profile->update_stats(priv);
7bb29755
MF		 333 queue_delayed_work(priv->wq, dwork,
334 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 335 }
336 mutex_unlock(&priv->state_lock);
337}
338
daa21560
TT		 339static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
340 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 341{
daa21560
TT		 342 struct mlx5e_priv *priv = vpriv;
343
e0f46eb9 344 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 345 return;
346
f62b8bb8
AV		 347 switch (event) {
348 case MLX5_DEV_EVENT_PORT_UP:
349 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 350 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8
AV		 351 break;
352
353 default:
354 break;
355 }
356}
357
f62b8bb8
AV		 358static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
359{
e0f46eb9 360 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 361}
362
363static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
364{
e0f46eb9 365 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 366 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 367}
368
facc9699
SM		 369#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
370#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
371
7e426671
TT		 372static inline int mlx5e_get_wqe_mtt_sz(void)
373{
374 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
375 * To avoid copying garbage after the mtt array, we allocate
376 * a little more.
377 */
378 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
379 MLX5_UMR_MTT_ALIGNMENT);
380}
381
382static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
383 struct mlx5e_umr_wqe *wqe, u16 ix)
384{
385 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
386 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
387 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 388 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 389 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
390 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
391
392 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
393 ds_cnt);
394 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
395 cseg->imm = rq->mkey_be;
396
397 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
398 ucseg->klm_octowords =
399 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
400 ucseg->bsf_octowords =
401 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
402 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
403
404 dseg->lkey = sq->mkey_be;
405 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
406}
407
408static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
409 struct mlx5e_channel *c)
410{
411 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
412 int mtt_sz = mlx5e_get_wqe_mtt_sz();
413 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
414 int i;
415
21c59685
SM		 416 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
417 GFP_KERNEL, cpu_to_node(c->cpu));
418 if (!rq->mpwqe.info)
7e426671
TT		 419 goto err_out;
420
421 /* We allocate more than mtt_sz as we will align the pointer */
21c59685 422 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
7e426671 423 cpu_to_node(c->cpu));
21c59685 424 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 425 goto err_free_wqe_info;
426
427 for (i = 0; i < wq_sz; i++) {
21c59685 428 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 429
21c59685 430 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 431 MLX5_UMR_ALIGN);
432 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
433 PCI_DMA_TODEVICE);
434 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
435 goto err_unmap_mtts;
436
437 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
438 }
439
440 return 0;
441
442err_unmap_mtts:
443 while (--i >= 0) {
21c59685 444 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 445
446 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
447 PCI_DMA_TODEVICE);
448 }
21c59685 449 kfree(rq->mpwqe.mtt_no_align);
7e426671 450err_free_wqe_info:
21c59685 451 kfree(rq->mpwqe.info);
7e426671
TT		 452
453err_out:
454 return -ENOMEM;
455}
456
457static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
458{
459 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
460 int mtt_sz = mlx5e_get_wqe_mtt_sz();
461 int i;
462
463 for (i = 0; i < wq_sz; i++) {
21c59685 464 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 465
466 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
467 PCI_DMA_TODEVICE);
468 }
21c59685
SM		 469 kfree(rq->mpwqe.mtt_no_align);
470 kfree(rq->mpwqe.info);
7e426671
TT		 471}
472
f5f82476
OG		 473static bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv)
474{
475 struct mlx5_eswitch_rep *rep = (struct mlx5_eswitch_rep *)priv->ppriv;
476
477 if (rep && rep->vport != FDB_UPLINK_VPORT)
478 return true;
479
480 return false;
481}
482
f62b8bb8
AV		 483static int mlx5e_create_rq(struct mlx5e_channel *c,
484 struct mlx5e_rq_param *param,
485 struct mlx5e_rq *rq)
486{
487 struct mlx5e_priv *priv = c->priv;
488 struct mlx5_core_dev *mdev = priv->mdev;
489 void *rqc = param->rqc;
490 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 491 u32 byte_count;
1bfecfca
SM		 492 u32 frag_sz;
493 int npages;
f62b8bb8
AV		 494 int wq_sz;
495 int err;
496 int i;
497
311c7c71
SM		 498 param->wq.db_numa_node = cpu_to_node(c->cpu);
499
f62b8bb8
AV		 500 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
501 &rq->wq_ctrl);
502 if (err)
503 return err;
504
505 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
506
507 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 508
7e426671
TT		 509 rq->wq_type = priv->params.rq_wq_type;
510 rq->pdev = c->pdev;
511 rq->netdev = c->netdev;
512 rq->tstamp = &priv->tstamp;
513 rq->channel = c;
514 rq->ix = c->ix;
515 rq->priv = c->priv;
97bc402d
DB		 516
517 rq->xdp_prog = priv->xdp_prog ? bpf_prog_inc(priv->xdp_prog) : NULL;
518 if (IS_ERR(rq->xdp_prog)) {
519 err = PTR_ERR(rq->xdp_prog);
520 rq->xdp_prog = NULL;
521 goto err_rq_wq_destroy;
522 }
7e426671 523
b5503b99
SM		 524 rq->buff.map_dir = DMA_FROM_DEVICE;
525 if (rq->xdp_prog)
526 rq->buff.map_dir = DMA_BIDIRECTIONAL;
527
461017cb
TT		 528 switch (priv->params.rq_wq_type) {
529 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476
OG		 530 if (mlx5e_is_vf_vport_rep(priv)) {
531 err = -EINVAL;
532 goto err_rq_wq_destroy;
533 }
534
461017cb
TT		 535 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
536 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 537 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 538
21c59685 539 rq->mpwqe.mtt_offset = c->ix *
fe4c988b
SM		 540 MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
541
d9d9f156
TT		 542 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
543 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
1bfecfca
SM		 544
545 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
546 byte_count = rq->buff.wqe_sz;
7e426671
TT		 547 rq->mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
548 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
549 if (err)
550 goto err_rq_wq_destroy;
461017cb
TT		 551 break;
552 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca
SM		 553 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
554 GFP_KERNEL, cpu_to_node(c->cpu));
555 if (!rq->dma_info) {
461017cb
TT		 556 err = -ENOMEM;
557 goto err_rq_wq_destroy;
558 }
1bfecfca 559
f5f82476
OG		 560 if (mlx5e_is_vf_vport_rep(priv))
561 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
562 else
563 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
564
461017cb 565 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 566 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 567
1bfecfca 568 rq->buff.wqe_sz = (priv->params.lro_en) ?
461017cb
TT		 569 priv->params.lro_wqe_sz :
570 MLX5E_SW2HW_MTU(priv->netdev->mtu);
1bfecfca
SM		 571 byte_count = rq->buff.wqe_sz;
572
573 /* calc the required page order */
574 frag_sz = MLX5_RX_HEADROOM +
575 byte_count /* packet data */ +
576 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
577 frag_sz = SKB_DATA_ALIGN(frag_sz);
578
579 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
580 rq->buff.page_order = order_base_2(npages);
581
461017cb 582 byte_count |= MLX5_HW_START_PADDING;
7e426671 583 rq->mkey_be = c->mkey_be;
461017cb 584 }
f62b8bb8
AV		 585
586 for (i = 0; i < wq_sz; i++) {
587 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
588
461017cb 589 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 590 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 591 }
592
cb3c7fd4
GR		 593 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
594 rq->am.mode = priv->params.rx_cq_period_mode;
595
4415a031
TT		 596 rq->page_cache.head = 0;
597 rq->page_cache.tail = 0;
598
f62b8bb8
AV		 599 return 0;
600
601err_rq_wq_destroy:
97bc402d
DB		 602 if (rq->xdp_prog)
603 bpf_prog_put(rq->xdp_prog);
f62b8bb8
AV		 604 mlx5_wq_destroy(&rq->wq_ctrl);
605
606 return err;
607}
608
609static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
610{
4415a031
TT		 611 int i;
612
86994156
RS		 613 if (rq->xdp_prog)
614 bpf_prog_put(rq->xdp_prog);
615
461017cb
TT		 616 switch (rq->wq_type) {
617 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 618 mlx5e_rq_free_mpwqe_info(rq);
461017cb
TT		 619 break;
620 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca 621 kfree(rq->dma_info);
461017cb
TT		 622 }
623
4415a031
TT		 624 for (i = rq->page_cache.head; i != rq->page_cache.tail;
625 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
626 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
627
628 mlx5e_page_release(rq, dma_info, false);
629 }
f62b8bb8
AV		 630 mlx5_wq_destroy(&rq->wq_ctrl);
631}
632
633static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
634{
50cfa25a 635 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 636 struct mlx5_core_dev *mdev = priv->mdev;
637
638 void *in;
639 void *rqc;
640 void *wq;
641 int inlen;
642 int err;
643
644 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
645 sizeof(u64) * rq->wq_ctrl.buf.npages;
646 in = mlx5_vzalloc(inlen);
647 if (!in)
648 return -ENOMEM;
649
650 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
651 wq = MLX5_ADDR_OF(rqc, rqc, wq);
652
653 memcpy(rqc, param->rqc, sizeof(param->rqc));
654
97de9f31 655 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 656 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
36350114 657 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
f62b8bb8 658 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 659 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 660 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
661
662 mlx5_fill_page_array(&rq->wq_ctrl.buf,
663 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
664
7db22ffb 665 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 666
667 kvfree(in);
668
669 return err;
670}
671
36350114
GP		 672static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
673 int next_state)
f62b8bb8
AV		 674{
675 struct mlx5e_channel *c = rq->channel;
676 struct mlx5e_priv *priv = c->priv;
677 struct mlx5_core_dev *mdev = priv->mdev;
678
679 void *in;
680 void *rqc;
681 int inlen;
682 int err;
683
684 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
685 in = mlx5_vzalloc(inlen);
686 if (!in)
687 return -ENOMEM;
688
689 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
690
691 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
692 MLX5_SET(rqc, rqc, state, next_state);
693
7db22ffb 694 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 695
696 kvfree(in);
697
698 return err;
699}
700
36350114
GP		 701static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
702{
703 struct mlx5e_channel *c = rq->channel;
704 struct mlx5e_priv *priv = c->priv;
705 struct mlx5_core_dev *mdev = priv->mdev;
706
707 void *in;
708 void *rqc;
709 int inlen;
710 int err;
711
712 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
713 in = mlx5_vzalloc(inlen);
714 if (!in)
715 return -ENOMEM;
716
717 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
718
719 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 720 MLX5_SET64(modify_rq_in, in, modify_bitmask,
721 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 722 MLX5_SET(rqc, rqc, vsd, vsd);
723 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
724
725 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
726
727 kvfree(in);
728
729 return err;
730}
731
f62b8bb8
AV		 732static void mlx5e_disable_rq(struct mlx5e_rq *rq)
733{
50cfa25a 734 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 735}
736
737static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
738{
01c196a2 739 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 740 struct mlx5e_channel *c = rq->channel;
741 struct mlx5e_priv *priv = c->priv;
742 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 743
01c196a2 744 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 745 if (wq->cur_sz >= priv->params.min_rx_wqes)
746 return 0;
747
748 msleep(20);
749 }
750
751 return -ETIMEDOUT;
752}
753
f2fde18c
SM		 754static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
755{
756 struct mlx5_wq_ll *wq = &rq->wq;
757 struct mlx5e_rx_wqe *wqe;
758 __be16 wqe_ix_be;
759 u16 wqe_ix;
760
8484f9ed
SM		 761 /* UMR WQE (if in progress) is always at wq->head */
762 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
21c59685 763 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 764
f2fde18c
SM		 765 while (!mlx5_wq_ll_is_empty(wq)) {
766 wqe_ix_be = *wq->tail_next;
767 wqe_ix = be16_to_cpu(wqe_ix_be);
768 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
769 rq->dealloc_wqe(rq, wqe_ix);
770 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
771 &wqe->next.next_wqe_index);
772 }
773}
774
f62b8bb8
AV		 775static int mlx5e_open_rq(struct mlx5e_channel *c,
776 struct mlx5e_rq_param *param,
777 struct mlx5e_rq *rq)
778{
d3c9bc27
TT		 779 struct mlx5e_sq *sq = &c->icosq;
780 u16 pi = sq->pc & sq->wq.sz_m1;
f62b8bb8
AV		 781 int err;
782
783 err = mlx5e_create_rq(c, param, rq);
784 if (err)
785 return err;
786
787 err = mlx5e_enable_rq(rq, param);
788 if (err)
789 goto err_destroy_rq;
790
36350114 791 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8
AV		 792 if (err)
793 goto err_disable_rq;
794
cb3c7fd4
GR		 795 if (param->am_enabled)
796 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
797
f10b7cc7
SM		 798 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
799 sq->db.ico_wqe[pi].num_wqebbs = 1;
d3c9bc27 800 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 801
802 return 0;
803
804err_disable_rq:
805 mlx5e_disable_rq(rq);
806err_destroy_rq:
807 mlx5e_destroy_rq(rq);
808
809 return err;
810}
811
812static void mlx5e_close_rq(struct mlx5e_rq *rq)
813{
f2fde18c 814 set_bit(MLX5E_RQ_STATE_FLUSH, &rq->state);
f62b8bb8 815 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
cb3c7fd4
GR		 816 cancel_work_sync(&rq->am.work);
817
f62b8bb8 818 mlx5e_disable_rq(rq);
6cd392a0 819 mlx5e_free_rx_descs(rq);
f62b8bb8
AV		 820 mlx5e_destroy_rq(rq);
821}
822
b5503b99
SM		 823static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
824{
825 kfree(sq->db.xdp.di);
826 kfree(sq->db.xdp.wqe_info);
827}
828
829static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
830{
831 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
832
833 sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
834 GFP_KERNEL, numa);
835 sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
836 GFP_KERNEL, numa);
837 if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
838 mlx5e_free_sq_xdp_db(sq);
839 return -ENOMEM;
840 }
841
842 return 0;
843}
844
f10b7cc7 845static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
f62b8bb8 846{
f10b7cc7 847 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 848}
849
f10b7cc7
SM		 850static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
851{
852 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
853
854 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
855 GFP_KERNEL, numa);
856 if (!sq->db.ico_wqe)
857 return -ENOMEM;
858
859 return 0;
860}
861
862static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
863{
864 kfree(sq->db.txq.wqe_info);
865 kfree(sq->db.txq.dma_fifo);
866 kfree(sq->db.txq.skb);
867}
868
869static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
f62b8bb8
AV		 870{
871 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
872 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
873
f10b7cc7
SM		 874 sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
875 GFP_KERNEL, numa);
876 sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
877 GFP_KERNEL, numa);
878 sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
879 GFP_KERNEL, numa);
880 if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
881 mlx5e_free_sq_txq_db(sq);
f62b8bb8
AV		 882 return -ENOMEM;
883 }
884
885 sq->dma_fifo_mask = df_sz - 1;
886
887 return 0;
888}
889
f10b7cc7
SM		 890static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
891{
892 switch (sq->type) {
893 case MLX5E_SQ_TXQ:
894 mlx5e_free_sq_txq_db(sq);
895 break;
896 case MLX5E_SQ_ICO:
897 mlx5e_free_sq_ico_db(sq);
898 break;
b5503b99
SM		 899 case MLX5E_SQ_XDP:
900 mlx5e_free_sq_xdp_db(sq);
901 break;
f10b7cc7
SM		 902 }
903}
904
905static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
906{
907 switch (sq->type) {
908 case MLX5E_SQ_TXQ:
909 return mlx5e_alloc_sq_txq_db(sq, numa);
910 case MLX5E_SQ_ICO:
911 return mlx5e_alloc_sq_ico_db(sq, numa);
b5503b99
SM		 912 case MLX5E_SQ_XDP:
913 return mlx5e_alloc_sq_xdp_db(sq, numa);
f10b7cc7
SM		 914 }
915
916 return 0;
917}
918
b5503b99
SM		 919static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
920{
921 switch (sq_type) {
922 case MLX5E_SQ_ICO:
923 return MLX5E_ICOSQ_MAX_WQEBBS;
924 case MLX5E_SQ_XDP:
925 return MLX5E_XDP_TX_WQEBBS;
926 }
927 return MLX5_SEND_WQE_MAX_WQEBBS;
928}
929
f62b8bb8
AV		 930static int mlx5e_create_sq(struct mlx5e_channel *c,
931 int tc,
932 struct mlx5e_sq_param *param,
933 struct mlx5e_sq *sq)
934{
935 struct mlx5e_priv *priv = c->priv;
936 struct mlx5_core_dev *mdev = priv->mdev;
937
938 void *sqc = param->sqc;
939 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
940 int err;
941
f10b7cc7
SM		 942 sq->type = param->type;
943 sq->pdev = c->pdev;
944 sq->tstamp = &priv->tstamp;
945 sq->mkey_be = c->mkey_be;
946 sq->channel = c;
947 sq->tc = tc;
948
fd4782c2 949 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
f62b8bb8
AV		 950 if (err)
951 return err;
952
311c7c71
SM		 953 param->wq.db_numa_node = cpu_to_node(c->cpu);
954
f62b8bb8
AV		 955 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
956 &sq->wq_ctrl);
957 if (err)
958 goto err_unmap_free_uar;
959
960 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
0ba42241
ML		 961 if (sq->uar.bf_map) {
962 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
963 sq->uar_map = sq->uar.bf_map;
964 } else {
965 sq->uar_map = sq->uar.map;
966 }
f62b8bb8 967 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 968 sq->max_inline = param->max_inline;
cff92d7c
HHZ		 969 sq->min_inline_mode =
970 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
971 param->min_inline_mode : 0;
f62b8bb8 972
7ec0bb22
DC		 973 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
974 if (err)
f62b8bb8
AV		 975 goto err_sq_wq_destroy;
976
f10b7cc7 977 if (sq->type == MLX5E_SQ_TXQ) {
d3c9bc27
TT		 978 int txq_ix;
979
980 txq_ix = c->ix + tc * priv->params.num_channels;
981 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
982 priv->txq_to_sq_map[txq_ix] = sq;
983 }
f62b8bb8 984
b5503b99 985 sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
88a85f99 986 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
f62b8bb8
AV		 987
988 return 0;
989
990err_sq_wq_destroy:
991 mlx5_wq_destroy(&sq->wq_ctrl);
992
993err_unmap_free_uar:
994 mlx5_unmap_free_uar(mdev, &sq->uar);
995
996 return err;
997}
998
999static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
1000{
1001 struct mlx5e_channel *c = sq->channel;
1002 struct mlx5e_priv *priv = c->priv;
1003
1004 mlx5e_free_sq_db(sq);
1005 mlx5_wq_destroy(&sq->wq_ctrl);
1006 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
1007}
1008
1009static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1010{
1011 struct mlx5e_channel *c = sq->channel;
1012 struct mlx5e_priv *priv = c->priv;
1013 struct mlx5_core_dev *mdev = priv->mdev;
1014
1015 void *in;
1016 void *sqc;
1017 void *wq;
1018 int inlen;
1019 int err;
1020
1021 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1022 sizeof(u64) * sq->wq_ctrl.buf.npages;
1023 in = mlx5_vzalloc(inlen);
1024 if (!in)
1025 return -ENOMEM;
1026
1027 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1028 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1029
1030 memcpy(sqc, param->sqc, sizeof(param->sqc));
1031
f10b7cc7
SM		 1032 MLX5_SET(sqc, sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1033 0 : priv->tisn[sq->tc]);
d3c9bc27 1034 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
cff92d7c 1035 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
f62b8bb8 1036 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f10b7cc7 1037 MLX5_SET(sqc, sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
f62b8bb8
AV		 1038 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1039
1040 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1041 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1042 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 1043 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1044 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1045
1046 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1047 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1048
7db22ffb 1049 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 1050
1051 kvfree(in);
1052
1053 return err;
1054}
1055
507f0c81
YP		 1056static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1057 int next_state, bool update_rl, int rl_index)
f62b8bb8
AV		 1058{
1059 struct mlx5e_channel *c = sq->channel;
1060 struct mlx5e_priv *priv = c->priv;
1061 struct mlx5_core_dev *mdev = priv->mdev;
1062
1063 void *in;
1064 void *sqc;
1065 int inlen;
1066 int err;
1067
1068 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1069 in = mlx5_vzalloc(inlen);
1070 if (!in)
1071 return -ENOMEM;
1072
1073 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1074
1075 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1076 MLX5_SET(sqc, sqc, state, next_state);
507f0c81
YP		 1077 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1078 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1079 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
1080 }
f62b8bb8 1081
7db22ffb 1082 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 1083
1084 kvfree(in);
1085
1086 return err;
1087}
1088
1089static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1090{
1091 struct mlx5e_channel *c = sq->channel;
1092 struct mlx5e_priv *priv = c->priv;
1093 struct mlx5_core_dev *mdev = priv->mdev;
1094
7db22ffb 1095 mlx5_core_destroy_sq(mdev, sq->sqn);
507f0c81
YP		 1096 if (sq->rate_limit)
1097 mlx5_rl_remove_rate(mdev, sq->rate_limit);
f62b8bb8
AV		 1098}
1099
1100static int mlx5e_open_sq(struct mlx5e_channel *c,
1101 int tc,
1102 struct mlx5e_sq_param *param,
1103 struct mlx5e_sq *sq)
1104{
1105 int err;
1106
1107 err = mlx5e_create_sq(c, tc, param, sq);
1108 if (err)
1109 return err;
1110
1111 err = mlx5e_enable_sq(sq, param);
1112 if (err)
1113 goto err_destroy_sq;
1114
507f0c81
YP		 1115 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1116 false, 0);
f62b8bb8
AV		 1117 if (err)
1118 goto err_disable_sq;
1119
d3c9bc27 1120 if (sq->txq) {
d3c9bc27
TT		 1121 netdev_tx_reset_queue(sq->txq);
1122 netif_tx_start_queue(sq->txq);
1123 }
f62b8bb8
AV		 1124
1125 return 0;
1126
1127err_disable_sq:
1128 mlx5e_disable_sq(sq);
1129err_destroy_sq:
1130 mlx5e_destroy_sq(sq);
1131
1132 return err;
1133}
1134
1135static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1136{
1137 __netif_tx_lock_bh(txq);
1138 netif_tx_stop_queue(txq);
1139 __netif_tx_unlock_bh(txq);
1140}
1141
1142static void mlx5e_close_sq(struct mlx5e_sq *sq)
1143{
6e8dd6d6
SM		 1144 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
1145 /* prevent netif_tx_wake_queue */
1146 napi_synchronize(&sq->channel->napi);
29429f33 1147
d3c9bc27 1148 if (sq->txq) {
d3c9bc27 1149 netif_tx_disable_queue(sq->txq);
f62b8bb8 1150
6e8dd6d6 1151 /* last doorbell out, godspeed .. */
f10b7cc7
SM		 1152 if (mlx5e_sq_has_room_for(sq, 1)) {
1153 sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
d3c9bc27 1154 mlx5e_send_nop(sq, true);
f10b7cc7 1155 }
29429f33 1156 }
f62b8bb8 1157
f62b8bb8 1158 mlx5e_disable_sq(sq);
b5503b99 1159 mlx5e_free_sq_descs(sq);
f62b8bb8
AV		 1160 mlx5e_destroy_sq(sq);
1161}
1162
1163static int mlx5e_create_cq(struct mlx5e_channel *c,
1164 struct mlx5e_cq_param *param,
1165 struct mlx5e_cq *cq)
1166{
1167 struct mlx5e_priv *priv = c->priv;
1168 struct mlx5_core_dev *mdev = priv->mdev;
1169 struct mlx5_core_cq *mcq = &cq->mcq;
1170 int eqn_not_used;
0b6e26ce 1171 unsigned int irqn;
f62b8bb8
AV		 1172 int err;
1173 u32 i;
1174
311c7c71
SM		 1175 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1176 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 1177 param->eq_ix = c->ix;
1178
1179 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1180 &cq->wq_ctrl);
1181 if (err)
1182 return err;
1183
1184 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1185
1186 cq->napi = &c->napi;
1187
1188 mcq->cqe_sz = 64;
1189 mcq->set_ci_db = cq->wq_ctrl.db.db;
1190 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1191 *mcq->set_ci_db = 0;
1192 *mcq->arm_db = 0;
1193 mcq->vector = param->eq_ix;
1194 mcq->comp = mlx5e_completion_event;
1195 mcq->event = mlx5e_cq_error_event;
1196 mcq->irqn = irqn;
b50d292b 1197 mcq->uar = &mdev->mlx5e_res.cq_uar;
f62b8bb8
AV		 1198
1199 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1200 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1201
1202 cqe->op_own = 0xf1;
1203 }
1204
1205 cq->channel = c;
50cfa25a 1206 cq->priv = priv;
f62b8bb8
AV		 1207
1208 return 0;
1209}
1210
1211static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1212{
1213 mlx5_wq_destroy(&cq->wq_ctrl);
1214}
1215
1216static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1217{
50cfa25a 1218 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 1219 struct mlx5_core_dev *mdev = priv->mdev;
1220 struct mlx5_core_cq *mcq = &cq->mcq;
1221
1222 void *in;
1223 void *cqc;
1224 int inlen;
0b6e26ce 1225 unsigned int irqn_not_used;
f62b8bb8
AV		 1226 int eqn;
1227 int err;
1228
1229 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1230 sizeof(u64) * cq->wq_ctrl.buf.npages;
1231 in = mlx5_vzalloc(inlen);
1232 if (!in)
1233 return -ENOMEM;
1234
1235 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1236
1237 memcpy(cqc, param->cqc, sizeof(param->cqc));
1238
1239 mlx5_fill_page_array(&cq->wq_ctrl.buf,
1240 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1241
1242 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1243
9908aa29 1244 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8
AV		 1245 MLX5_SET(cqc, cqc, c_eqn, eqn);
1246 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1247 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 1248 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1249 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1250
1251 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1252
1253 kvfree(in);
1254
1255 if (err)
1256 return err;
1257
1258 mlx5e_cq_arm(cq);
1259
1260 return 0;
1261}
1262
1263static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1264{
50cfa25a 1265 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 1266 struct mlx5_core_dev *mdev = priv->mdev;
1267
1268 mlx5_core_destroy_cq(mdev, &cq->mcq);
1269}
1270
1271static int mlx5e_open_cq(struct mlx5e_channel *c,
1272 struct mlx5e_cq_param *param,
1273 struct mlx5e_cq *cq,
9908aa29 1274 struct mlx5e_cq_moder moderation)
f62b8bb8
AV		 1275{
1276 int err;
1277 struct mlx5e_priv *priv = c->priv;
1278 struct mlx5_core_dev *mdev = priv->mdev;
1279
1280 err = mlx5e_create_cq(c, param, cq);
1281 if (err)
1282 return err;
1283
1284 err = mlx5e_enable_cq(cq, param);
1285 if (err)
1286 goto err_destroy_cq;
1287
7524a5d8
GP		 1288 if (MLX5_CAP_GEN(mdev, cq_moderation))
1289 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
9908aa29
TT		 1290 moderation.usec,
1291 moderation.pkts);
f62b8bb8
AV		 1292 return 0;
1293
1294err_destroy_cq:
1295 mlx5e_destroy_cq(cq);
1296
1297 return err;
1298}
1299
1300static void mlx5e_close_cq(struct mlx5e_cq *cq)
1301{
1302 mlx5e_disable_cq(cq);
1303 mlx5e_destroy_cq(cq);
1304}
1305
1306static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1307{
1308 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1309}
1310
1311static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1312 struct mlx5e_channel_param *cparam)
1313{
1314 struct mlx5e_priv *priv = c->priv;
1315 int err;
1316 int tc;
1317
1318 for (tc = 0; tc < c->num_tc; tc++) {
1319 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
9908aa29 1320 priv->params.tx_cq_moderation);
f62b8bb8
AV		 1321 if (err)
1322 goto err_close_tx_cqs;
f62b8bb8
AV		 1323 }
1324
1325 return 0;
1326
1327err_close_tx_cqs:
1328 for (tc--; tc >= 0; tc--)
1329 mlx5e_close_cq(&c->sq[tc].cq);
1330
1331 return err;
1332}
1333
1334static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1335{
1336 int tc;
1337
1338 for (tc = 0; tc < c->num_tc; tc++)
1339 mlx5e_close_cq(&c->sq[tc].cq);
1340}
1341
1342static int mlx5e_open_sqs(struct mlx5e_channel *c,
1343 struct mlx5e_channel_param *cparam)
1344{
1345 int err;
1346 int tc;
1347
1348 for (tc = 0; tc < c->num_tc; tc++) {
1349 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1350 if (err)
1351 goto err_close_sqs;
1352 }
1353
1354 return 0;
1355
1356err_close_sqs:
1357 for (tc--; tc >= 0; tc--)
1358 mlx5e_close_sq(&c->sq[tc]);
1359
1360 return err;
1361}
1362
1363static void mlx5e_close_sqs(struct mlx5e_channel *c)
1364{
1365 int tc;
1366
1367 for (tc = 0; tc < c->num_tc; tc++)
1368 mlx5e_close_sq(&c->sq[tc]);
1369}
1370
5283af89 1371static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 1372{
1373 int i;
1374
6bfd390b 1375 for (i = 0; i < priv->profile->max_tc; i++)
5283af89
RS		 1376 priv->channeltc_to_txq_map[ix][i] =
1377 ix + i * priv->params.num_channels;
03289b88
SM		 1378}
1379
507f0c81
YP		 1380static int mlx5e_set_sq_maxrate(struct net_device *dev,
1381 struct mlx5e_sq *sq, u32 rate)
1382{
1383 struct mlx5e_priv *priv = netdev_priv(dev);
1384 struct mlx5_core_dev *mdev = priv->mdev;
1385 u16 rl_index = 0;
1386 int err;
1387
1388 if (rate == sq->rate_limit)
1389 /* nothing to do */
1390 return 0;
1391
1392 if (sq->rate_limit)
1393 /* remove current rl index to free space to next ones */
1394 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1395
1396 sq->rate_limit = 0;
1397
1398 if (rate) {
1399 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1400 if (err) {
1401 netdev_err(dev, "Failed configuring rate %u: %d\n",
1402 rate, err);
1403 return err;
1404 }
1405 }
1406
1407 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1408 MLX5_SQC_STATE_RDY, true, rl_index);
1409 if (err) {
1410 netdev_err(dev, "Failed configuring rate %u: %d\n",
1411 rate, err);
1412 /* remove the rate from the table */
1413 if (rate)
1414 mlx5_rl_remove_rate(mdev, rate);
1415 return err;
1416 }
1417
1418 sq->rate_limit = rate;
1419 return 0;
1420}
1421
1422static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1423{
1424 struct mlx5e_priv *priv = netdev_priv(dev);
1425 struct mlx5_core_dev *mdev = priv->mdev;
1426 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1427 int err = 0;
1428
1429 if (!mlx5_rl_is_supported(mdev)) {
1430 netdev_err(dev, "Rate limiting is not supported on this device\n");
1431 return -EINVAL;
1432 }
1433
1434 /* rate is given in Mb/sec, HW config is in Kb/sec */
1435 rate = rate << 10;
1436
1437 /* Check whether rate in valid range, 0 is always valid */
1438 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1439 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1440 return -ERANGE;
1441 }
1442
1443 mutex_lock(&priv->state_lock);
1444 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1445 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1446 if (!err)
1447 priv->tx_rates[index] = rate;
1448 mutex_unlock(&priv->state_lock);
1449
1450 return err;
1451}
1452
f62b8bb8
AV		 1453static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1454 struct mlx5e_channel_param *cparam,
1455 struct mlx5e_channel **cp)
1456{
9908aa29 1457 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
f62b8bb8 1458 struct net_device *netdev = priv->netdev;
cb3c7fd4 1459 struct mlx5e_cq_moder rx_cq_profile;
f62b8bb8
AV		 1460 int cpu = mlx5e_get_cpu(priv, ix);
1461 struct mlx5e_channel *c;
507f0c81 1462 struct mlx5e_sq *sq;
f62b8bb8 1463 int err;
507f0c81 1464 int i;
f62b8bb8
AV		 1465
1466 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1467 if (!c)
1468 return -ENOMEM;
1469
1470 c->priv = priv;
1471 c->ix = ix;
1472 c->cpu = cpu;
1473 c->pdev = &priv->mdev->pdev->dev;
1474 c->netdev = priv->netdev;
b50d292b 1475 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
a4418a6c 1476 c->num_tc = priv->params.num_tc;
d7a0ecab 1477 c->xdp = !!priv->xdp_prog;
f62b8bb8 1478
cb3c7fd4
GR		 1479 if (priv->params.rx_am_enabled)
1480 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1481 else
1482 rx_cq_profile = priv->params.rx_cq_moderation;
1483
5283af89 1484 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1485
f62b8bb8
AV		 1486 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1487
9908aa29 1488 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
f62b8bb8
AV		 1489 if (err)
1490 goto err_napi_del;
1491
d3c9bc27
TT		 1492 err = mlx5e_open_tx_cqs(c, cparam);
1493 if (err)
1494 goto err_close_icosq_cq;
1495
f62b8bb8 1496 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
cb3c7fd4 1497 rx_cq_profile);
f62b8bb8
AV		 1498 if (err)
1499 goto err_close_tx_cqs;
f62b8bb8 1500
d7a0ecab
SM		 1501 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1502 err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1503 priv->params.tx_cq_moderation) : 0;
1504 if (err)
1505 goto err_close_rx_cq;
1506
f62b8bb8
AV		 1507 napi_enable(&c->napi);
1508
d3c9bc27 1509 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1510 if (err)
1511 goto err_disable_napi;
1512
d3c9bc27
TT		 1513 err = mlx5e_open_sqs(c, cparam);
1514 if (err)
1515 goto err_close_icosq;
1516
507f0c81
YP		 1517 for (i = 0; i < priv->params.num_tc; i++) {
1518 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1519
1520 if (priv->tx_rates[txq_ix]) {
1521 sq = priv->txq_to_sq_map[txq_ix];
1522 mlx5e_set_sq_maxrate(priv->netdev, sq,
1523 priv->tx_rates[txq_ix]);
1524 }
1525 }
1526
d7a0ecab
SM		 1527 err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0;
1528 if (err)
1529 goto err_close_sqs;
b5503b99 1530
f62b8bb8
AV		 1531 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1532 if (err)
b5503b99 1533 goto err_close_xdp_sq;
f62b8bb8
AV		 1534
1535 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1536 *cp = c;
1537
1538 return 0;
b5503b99 1539err_close_xdp_sq:
d7a0ecab 1540 if (c->xdp)
87dc0255 1541 mlx5e_close_sq(&c->xdp_sq);
f62b8bb8
AV		 1542
1543err_close_sqs:
1544 mlx5e_close_sqs(c);
1545
d3c9bc27
TT		 1546err_close_icosq:
1547 mlx5e_close_sq(&c->icosq);
1548
f62b8bb8
AV		 1549err_disable_napi:
1550 napi_disable(&c->napi);
d7a0ecab
SM		 1551 if (c->xdp)
1552 mlx5e_close_cq(&c->xdp_sq.cq);
1553
1554err_close_rx_cq:
f62b8bb8
AV		 1555 mlx5e_close_cq(&c->rq.cq);
1556
1557err_close_tx_cqs:
1558 mlx5e_close_tx_cqs(c);
1559
d3c9bc27
TT		 1560err_close_icosq_cq:
1561 mlx5e_close_cq(&c->icosq.cq);
1562
f62b8bb8
AV		 1563err_napi_del:
1564 netif_napi_del(&c->napi);
1565 kfree(c);
1566
1567 return err;
1568}
1569
1570static void mlx5e_close_channel(struct mlx5e_channel *c)
1571{
1572 mlx5e_close_rq(&c->rq);
b5503b99
SM		 1573 if (c->xdp)
1574 mlx5e_close_sq(&c->xdp_sq);
f62b8bb8 1575 mlx5e_close_sqs(c);
d3c9bc27 1576 mlx5e_close_sq(&c->icosq);
f62b8bb8 1577 napi_disable(&c->napi);
b5503b99
SM		 1578 if (c->xdp)
1579 mlx5e_close_cq(&c->xdp_sq.cq);
f62b8bb8
AV		 1580 mlx5e_close_cq(&c->rq.cq);
1581 mlx5e_close_tx_cqs(c);
d3c9bc27 1582 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1583 netif_napi_del(&c->napi);
7ae92ae5 1584
f62b8bb8
AV		 1585 kfree(c);
1586}
1587
1588static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1589 struct mlx5e_rq_param *param)
1590{
1591 void *rqc = param->rqc;
1592 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1593
461017cb
TT		 1594 switch (priv->params.rq_wq_type) {
1595 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1596 MLX5_SET(wq, wq, log_wqe_num_of_strides,
d9d9f156 1597 priv->params.mpwqe_log_num_strides - 9);
461017cb 1598 MLX5_SET(wq, wq, log_wqe_stride_size,
d9d9f156 1599 priv->params.mpwqe_log_stride_sz - 6);
461017cb
TT		 1600 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1601 break;
1602 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1603 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1604 }
1605
f62b8bb8
AV		 1606 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1607 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1608 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
b50d292b 1609 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1610 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1611
311c7c71 1612 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8 1613 param->wq.linear = 1;
cb3c7fd4
GR		 1614
1615 param->am_enabled = priv->params.rx_am_enabled;
f62b8bb8
AV		 1616}
1617
556dd1b9
TT		 1618static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1619{
1620 void *rqc = param->rqc;
1621 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1622
1623 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1624 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1625}
1626
d3c9bc27
TT		 1627static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1628 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1629{
1630 void *sqc = param->sqc;
1631 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1632
f62b8bb8 1633 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1634 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1635
311c7c71 1636 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1637}
1638
1639static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1640 struct mlx5e_sq_param *param)
1641{
1642 void *sqc = param->sqc;
1643 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1644
1645 mlx5e_build_sq_param_common(priv, param);
1646 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1647
58d52291 1648 param->max_inline = priv->params.tx_max_inline;
cff92d7c 1649 param->min_inline_mode = priv->params.tx_min_inline_mode;
f10b7cc7 1650 param->type = MLX5E_SQ_TXQ;
f62b8bb8
AV		 1651}
1652
1653static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1654 struct mlx5e_cq_param *param)
1655{
1656 void *cqc = param->cqc;
1657
b50d292b 1658 MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
f62b8bb8
AV		 1659}
1660
1661static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1662 struct mlx5e_cq_param *param)
1663{
1664 void *cqc = param->cqc;
461017cb 1665 u8 log_cq_size;
f62b8bb8 1666
461017cb
TT		 1667 switch (priv->params.rq_wq_type) {
1668 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1669 log_cq_size = priv->params.log_rq_size +
d9d9f156 1670 priv->params.mpwqe_log_num_strides;
461017cb
TT		 1671 break;
1672 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1673 log_cq_size = priv->params.log_rq_size;
1674 }
1675
1676 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
7219ab34
TT		 1677 if (priv->params.rx_cqe_compress) {
1678 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1679 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1680 }
f62b8bb8
AV		 1681
1682 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1683
1684 param->cq_period_mode = priv->params.rx_cq_period_mode;
f62b8bb8
AV		 1685}
1686
1687static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1688 struct mlx5e_cq_param *param)
1689{
1690 void *cqc = param->cqc;
1691
d3c9bc27 1692 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1693
1694 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1695
1696 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1697}
1698
d3c9bc27
TT		 1699static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1700 struct mlx5e_cq_param *param,
1701 u8 log_wq_size)
1702{
1703 void *cqc = param->cqc;
1704
1705 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1706
1707 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1708
1709 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1710}
1711
1712static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1713 struct mlx5e_sq_param *param,
1714 u8 log_wq_size)
1715{
1716 void *sqc = param->sqc;
1717 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1718
1719 mlx5e_build_sq_param_common(priv, param);
1720
1721 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1722 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27 1723
f10b7cc7 1724 param->type = MLX5E_SQ_ICO;
d3c9bc27
TT		 1725}
1726
b5503b99
SM		 1727static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1728 struct mlx5e_sq_param *param)
1729{
1730 void *sqc = param->sqc;
1731 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1732
1733 mlx5e_build_sq_param_common(priv, param);
1734 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1735
1736 param->max_inline = priv->params.tx_max_inline;
1737 /* FOR XDP SQs will support only L2 inline mode */
1738 param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1739 param->type = MLX5E_SQ_XDP;
1740}
1741
6b87663f 1742static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
f62b8bb8 1743{
bc77b240 1744 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1745
f62b8bb8
AV		 1746 mlx5e_build_rq_param(priv, &cparam->rq);
1747 mlx5e_build_sq_param(priv, &cparam->sq);
b5503b99 1748 mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
d3c9bc27 1749 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1750 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1751 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1752 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1753}
1754
1755static int mlx5e_open_channels(struct mlx5e_priv *priv)
1756{
6b87663f 1757 struct mlx5e_channel_param *cparam;
a4418a6c 1758 int nch = priv->params.num_channels;
03289b88 1759 int err = -ENOMEM;
f62b8bb8
AV		 1760 int i;
1761 int j;
1762
a4418a6c
AS		 1763 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1764 GFP_KERNEL);
03289b88 1765
a4418a6c 1766 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1767 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1768
6b87663f
AB		 1769 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1770
1771 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
03289b88 1772 goto err_free_txq_to_sq_map;
f62b8bb8 1773
6b87663f
AB		 1774 mlx5e_build_channel_param(priv, cparam);
1775
a4418a6c 1776 for (i = 0; i < nch; i++) {
6b87663f 1777 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
f62b8bb8
AV		 1778 if (err)
1779 goto err_close_channels;
1780 }
1781
a4418a6c 1782 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1783 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1784 if (err)
1785 goto err_close_channels;
1786 }
1787
c3b7c5c9
MHY		 1788 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1789 * polling for inactive tx queues.
1790 */
1791 netif_tx_start_all_queues(priv->netdev);
1792
6b87663f 1793 kfree(cparam);
f62b8bb8
AV		 1794 return 0;
1795
1796err_close_channels:
1797 for (i--; i >= 0; i--)
1798 mlx5e_close_channel(priv->channel[i]);
1799
03289b88
SM		 1800err_free_txq_to_sq_map:
1801 kfree(priv->txq_to_sq_map);
f62b8bb8 1802 kfree(priv->channel);
6b87663f 1803 kfree(cparam);
f62b8bb8
AV		 1804
1805 return err;
1806}
1807
1808static void mlx5e_close_channels(struct mlx5e_priv *priv)
1809{
1810 int i;
1811
c3b7c5c9
MHY		 1812 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1813 * polling for inactive tx queues.
1814 */
1815 netif_tx_stop_all_queues(priv->netdev);
1816 netif_tx_disable(priv->netdev);
1817
f62b8bb8
AV		 1818 for (i = 0; i < priv->params.num_channels; i++)
1819 mlx5e_close_channel(priv->channel[i]);
1820
03289b88 1821 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1822 kfree(priv->channel);
1823}
1824
2be6967c
SM		 1825static int mlx5e_rx_hash_fn(int hfunc)
1826{
1827 return (hfunc == ETH_RSS_HASH_TOP) ?
1828 MLX5_RX_HASH_FN_TOEPLITZ :
1829 MLX5_RX_HASH_FN_INVERTED_XOR8;
1830}
1831
1832static int mlx5e_bits_invert(unsigned long a, int size)
1833{
1834 int inv = 0;
1835 int i;
1836
1837 for (i = 0; i < size; i++)
1838 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1839
1840 return inv;
1841}
1842
936896e9
AS		 1843static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1844{
1845 int i;
1846
1847 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1848 int ix = i;
1da36696 1849 u32 rqn;
936896e9
AS		 1850
1851 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1852 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1853
2d75b2bc 1854 ix = priv->params.indirection_rqt[ix];
1da36696
TT		 1855 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1856 priv->channel[ix]->rq.rqn :
1857 priv->drop_rq.rqn;
1858 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
936896e9
AS		 1859 }
1860}
1861
1da36696
TT		 1862static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1863 int ix)
4cbeaff5 1864{
1da36696
TT		 1865 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1866 priv->channel[ix]->rq.rqn :
1867 priv->drop_rq.rqn;
4cbeaff5 1868
1da36696 1869 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
4cbeaff5
AS		 1870}
1871
398f3351
HHZ		 1872static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1873 int ix, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 1874{
1875 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1876 void *rqtc;
1877 int inlen;
1878 int err;
1da36696 1879 u32 *in;
f62b8bb8 1880
f62b8bb8
AV		 1881 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1882 in = mlx5_vzalloc(inlen);
1883 if (!in)
1884 return -ENOMEM;
1885
1886 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1887
1888 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1889 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1890
1da36696
TT		 1891 if (sz > 1) /* RSS */
1892 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1893 else
1894 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2be6967c 1895
398f3351
HHZ		 1896 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1897 if (!err)
1898 rqt->enabled = true;
f62b8bb8
AV		 1899
1900 kvfree(in);
1da36696
TT		 1901 return err;
1902}
1903
cb67b832 1904void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 1905{
398f3351
HHZ		 1906 rqt->enabled = false;
1907 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 1908}
1909
6bfd390b
HHZ		 1910static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1911{
1912 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1913
1914 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1915}
1916
cb67b832 1917int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 1918{
398f3351 1919 struct mlx5e_rqt *rqt;
1da36696
TT		 1920 int err;
1921 int ix;
1922
6bfd390b 1923 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351
HHZ		 1924 rqt = &priv->direct_tir[ix].rqt;
1925 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1da36696
TT		 1926 if (err)
1927 goto err_destroy_rqts;
1928 }
1929
1930 return 0;
1931
1932err_destroy_rqts:
1933 for (ix--; ix >= 0; ix--)
398f3351 1934 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 1935
f62b8bb8
AV		 1936 return err;
1937}
1938
1da36696 1939int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
5c50368f
AS		 1940{
1941 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 1942 void *rqtc;
1943 int inlen;
1da36696 1944 u32 *in;
5c50368f
AS		 1945 int err;
1946
5c50368f
AS		 1947 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1948 in = mlx5_vzalloc(inlen);
1949 if (!in)
1950 return -ENOMEM;
1951
1952 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1953
1954 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1da36696
TT		 1955 if (sz > 1) /* RSS */
1956 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1957 else
1958 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
5c50368f
AS		 1959
1960 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1961
1da36696 1962 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 1963
1964 kvfree(in);
1965
1966 return err;
1967}
1968
40ab6a6e
AS		 1969static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1970{
1da36696
TT		 1971 u32 rqtn;
1972 int ix;
1973
398f3351
HHZ		 1974 if (priv->indir_rqt.enabled) {
1975 rqtn = priv->indir_rqt.rqtn;
1976 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1977 }
1978
1da36696 1979 for (ix = 0; ix < priv->params.num_channels; ix++) {
398f3351
HHZ		 1980 if (!priv->direct_tir[ix].rqt.enabled)
1981 continue;
1982 rqtn = priv->direct_tir[ix].rqt.rqtn;
1da36696
TT		 1983 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1984 }
40ab6a6e
AS		 1985}
1986
5c50368f
AS		 1987static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1988{
1989 if (!priv->params.lro_en)
1990 return;
1991
1992#define ROUGH_MAX_L2_L3_HDR_SZ 256
1993
1994 MLX5_SET(tirc, tirc, lro_enable_mask,
1995 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1996 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1997 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1998 (priv->params.lro_wqe_sz -
1999 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2b029556 2000 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
5c50368f
AS		 2001}
2002
bdfc028d
TT		 2003void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
2004{
2005 MLX5_SET(tirc, tirc, rx_hash_fn,
2006 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
2007 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
2008 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2009 rx_hash_toeplitz_key);
2010 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2011 rx_hash_toeplitz_key);
2012
2013 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2014 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2015 }
2016}
2017
ab0394fe 2018static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2019{
2020 struct mlx5_core_dev *mdev = priv->mdev;
2021
2022 void *in;
2023 void *tirc;
2024 int inlen;
2025 int err;
ab0394fe 2026 int tt;
1da36696 2027 int ix;
5c50368f
AS		 2028
2029 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2030 in = mlx5_vzalloc(inlen);
2031 if (!in)
2032 return -ENOMEM;
2033
2034 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2035 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2036
2037 mlx5e_build_tir_ctx_lro(tirc, priv);
2038
1da36696 2039 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2040 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2041 inlen);
ab0394fe 2042 if (err)
1da36696 2043 goto free_in;
ab0394fe 2044 }
5c50368f 2045
6bfd390b 2046 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2047 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2048 in, inlen);
2049 if (err)
2050 goto free_in;
2051 }
2052
2053free_in:
5c50368f
AS		 2054 kvfree(in);
2055
2056 return err;
2057}
2058
cd255eff 2059static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2060{
40ab6a6e 2061 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 2062 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 2063 int err;
2064
cd255eff 2065 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2066 if (err)
2067 return err;
2068
cd255eff
SM		 2069 /* Update vport context MTU */
2070 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2071 return 0;
2072}
40ab6a6e 2073
cd255eff
SM		 2074static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2075{
2076 struct mlx5_core_dev *mdev = priv->mdev;
2077 u16 hw_mtu = 0;
2078 int err;
40ab6a6e 2079
cd255eff
SM		 2080 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2081 if (err || !hw_mtu) /* fallback to port oper mtu */
2082 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2083
2084 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2085}
2086
2087static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2088{
2089 struct mlx5e_priv *priv = netdev_priv(netdev);
2090 u16 mtu;
2091 int err;
2092
2093 err = mlx5e_set_mtu(priv, netdev->mtu);
2094 if (err)
2095 return err;
40ab6a6e 2096
cd255eff
SM		 2097 mlx5e_query_mtu(priv, &mtu);
2098 if (mtu != netdev->mtu)
2099 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2100 __func__, mtu, netdev->mtu);
40ab6a6e 2101
cd255eff 2102 netdev->mtu = mtu;
40ab6a6e
AS		 2103 return 0;
2104}
2105
08fb1dac
SM		 2106static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2107{
2108 struct mlx5e_priv *priv = netdev_priv(netdev);
2109 int nch = priv->params.num_channels;
2110 int ntc = priv->params.num_tc;
2111 int tc;
2112
2113 netdev_reset_tc(netdev);
2114
2115 if (ntc == 1)
2116 return;
2117
2118 netdev_set_num_tc(netdev, ntc);
2119
7ccdd084
RS		 2120 /* Map netdev TCs to offset 0
2121 * We have our own UP to TXQ mapping for QoS
2122 */
08fb1dac 2123 for (tc = 0; tc < ntc; tc++)
7ccdd084 2124 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2125}
2126
40ab6a6e
AS		 2127int mlx5e_open_locked(struct net_device *netdev)
2128{
2129 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 2130 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e
AS		 2131 int num_txqs;
2132 int err;
2133
2134 set_bit(MLX5E_STATE_OPENED, &priv->state);
2135
08fb1dac
SM		 2136 mlx5e_netdev_set_tcs(netdev);
2137
40ab6a6e
AS		 2138 num_txqs = priv->params.num_channels * priv->params.num_tc;
2139 netif_set_real_num_tx_queues(netdev, num_txqs);
2140 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2141
40ab6a6e
AS		 2142 err = mlx5e_open_channels(priv);
2143 if (err) {
2144 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2145 __func__, err);
343b29f3 2146 goto err_clear_state_opened_flag;
40ab6a6e
AS		 2147 }
2148
724b2aa1 2149 err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
66189961
TT		 2150 if (err) {
2151 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2152 __func__, err);
2153 goto err_close_channels;
2154 }
2155
40ab6a6e 2156 mlx5e_redirect_rqts(priv);
ce89ef36 2157 mlx5e_update_carrier(priv);
ef9814de 2158 mlx5e_timestamp_init(priv);
5a7b27eb
MG		 2159#ifdef CONFIG_RFS_ACCEL
2160 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2161#endif
cb67b832
HHZ		 2162 if (priv->profile->update_stats)
2163 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2164
cb67b832
HHZ		 2165 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2166 err = mlx5e_add_sqs_fwd_rules(priv);
2167 if (err)
2168 goto err_close_channels;
2169 }
9b37b07f 2170 return 0;
343b29f3 2171
66189961
TT		 2172err_close_channels:
2173 mlx5e_close_channels(priv);
343b29f3
AS		 2174err_clear_state_opened_flag:
2175 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2176 return err;
40ab6a6e
AS		 2177}
2178
cb67b832 2179int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2180{
2181 struct mlx5e_priv *priv = netdev_priv(netdev);
2182 int err;
2183
2184 mutex_lock(&priv->state_lock);
2185 err = mlx5e_open_locked(netdev);
2186 mutex_unlock(&priv->state_lock);
2187
2188 return err;
2189}
2190
2191int mlx5e_close_locked(struct net_device *netdev)
2192{
2193 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 2194 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e 2195
a1985740
AS		 2196 /* May already be CLOSED in case a previous configuration operation
2197 * (e.g RX/TX queue size change) that involves close&open failed.
2198 */
2199 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2200 return 0;
2201
40ab6a6e
AS		 2202 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2203
cb67b832
HHZ		 2204 if (MLX5_CAP_GEN(mdev, vport_group_manager))
2205 mlx5e_remove_sqs_fwd_rules(priv);
2206
ef9814de 2207 mlx5e_timestamp_cleanup(priv);
40ab6a6e 2208 netif_carrier_off(priv->netdev);
ce89ef36 2209 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 2210 mlx5e_close_channels(priv);
2211
2212 return 0;
2213}
2214
cb67b832 2215int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2216{
2217 struct mlx5e_priv *priv = netdev_priv(netdev);
2218 int err;
2219
26e59d80
MHY		 2220 if (!netif_device_present(netdev))
2221 return -ENODEV;
2222
40ab6a6e
AS		 2223 mutex_lock(&priv->state_lock);
2224 err = mlx5e_close_locked(netdev);
2225 mutex_unlock(&priv->state_lock);
2226
2227 return err;
2228}
2229
2230static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2231 struct mlx5e_rq *rq,
2232 struct mlx5e_rq_param *param)
2233{
2234 struct mlx5_core_dev *mdev = priv->mdev;
2235 void *rqc = param->rqc;
2236 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2237 int err;
2238
2239 param->wq.db_numa_node = param->wq.buf_numa_node;
2240
2241 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2242 &rq->wq_ctrl);
2243 if (err)
2244 return err;
2245
2246 rq->priv = priv;
2247
2248 return 0;
2249}
2250
2251static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2252 struct mlx5e_cq *cq,
2253 struct mlx5e_cq_param *param)
2254{
2255 struct mlx5_core_dev *mdev = priv->mdev;
2256 struct mlx5_core_cq *mcq = &cq->mcq;
2257 int eqn_not_used;
0b6e26ce 2258 unsigned int irqn;
40ab6a6e
AS		 2259 int err;
2260
2261 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2262 &cq->wq_ctrl);
2263 if (err)
2264 return err;
2265
2266 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2267
2268 mcq->cqe_sz = 64;
2269 mcq->set_ci_db = cq->wq_ctrl.db.db;
2270 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2271 *mcq->set_ci_db = 0;
2272 *mcq->arm_db = 0;
2273 mcq->vector = param->eq_ix;
2274 mcq->comp = mlx5e_completion_event;
2275 mcq->event = mlx5e_cq_error_event;
2276 mcq->irqn = irqn;
b50d292b 2277 mcq->uar = &mdev->mlx5e_res.cq_uar;
40ab6a6e
AS		 2278
2279 cq->priv = priv;
2280
2281 return 0;
2282}
2283
2284static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2285{
2286 struct mlx5e_cq_param cq_param;
2287 struct mlx5e_rq_param rq_param;
2288 struct mlx5e_rq *rq = &priv->drop_rq;
2289 struct mlx5e_cq *cq = &priv->drop_rq.cq;
2290 int err;
2291
2292 memset(&cq_param, 0, sizeof(cq_param));
2293 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 2294 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 2295
2296 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2297 if (err)
2298 return err;
2299
2300 err = mlx5e_enable_cq(cq, &cq_param);
2301 if (err)
2302 goto err_destroy_cq;
2303
2304 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2305 if (err)
2306 goto err_disable_cq;
2307
2308 err = mlx5e_enable_rq(rq, &rq_param);
2309 if (err)
2310 goto err_destroy_rq;
2311
2312 return 0;
2313
2314err_destroy_rq:
2315 mlx5e_destroy_rq(&priv->drop_rq);
2316
2317err_disable_cq:
2318 mlx5e_disable_cq(&priv->drop_rq.cq);
2319
2320err_destroy_cq:
2321 mlx5e_destroy_cq(&priv->drop_rq.cq);
2322
2323 return err;
2324}
2325
2326static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2327{
2328 mlx5e_disable_rq(&priv->drop_rq);
2329 mlx5e_destroy_rq(&priv->drop_rq);
2330 mlx5e_disable_cq(&priv->drop_rq.cq);
2331 mlx5e_destroy_cq(&priv->drop_rq.cq);
2332}
2333
2334static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2335{
2336 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 2337 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2338 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2339
08fb1dac 2340 MLX5_SET(tisc, tisc, prio, tc << 1);
b50d292b 2341 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2342
2343 if (mlx5_lag_is_lacp_owner(mdev))
2344 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2345
40ab6a6e
AS		 2346 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2347}
2348
2349static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2350{
2351 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2352}
2353
cb67b832 2354int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2355{
2356 int err;
2357 int tc;
2358
6bfd390b 2359 for (tc = 0; tc < priv->profile->max_tc; tc++) {
40ab6a6e
AS		 2360 err = mlx5e_create_tis(priv, tc);
2361 if (err)
2362 goto err_close_tises;
2363 }
2364
2365 return 0;
2366
2367err_close_tises:
2368 for (tc--; tc >= 0; tc--)
2369 mlx5e_destroy_tis(priv, tc);
2370
2371 return err;
2372}
2373
cb67b832 2374void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2375{
2376 int tc;
2377
6bfd390b 2378 for (tc = 0; tc < priv->profile->max_tc; tc++)
40ab6a6e
AS		 2379 mlx5e_destroy_tis(priv, tc);
2380}
2381
1da36696
TT		 2382static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2383 enum mlx5e_traffic_types tt)
f62b8bb8
AV		 2384{
2385 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2386
b50d292b 2387 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2388
5a6f8aef
AS		 2389#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2390 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 2391
5a6f8aef
AS		 2392#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2393 MLX5_HASH_FIELD_SEL_DST_IP |\
2394 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2395 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 2396
a741749f
AS		 2397#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2398 MLX5_HASH_FIELD_SEL_DST_IP |\
2399 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2400
5c50368f 2401 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 2402
4cbeaff5 2403 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2404 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
1da36696 2405 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 2406
2407 switch (tt) {
2408 case MLX5E_TT_IPV4_TCP:
2409 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2410 MLX5_L3_PROT_TYPE_IPV4);
2411 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2412 MLX5_L4_PROT_TYPE_TCP);
2413 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2414 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2415 break;
2416
2417 case MLX5E_TT_IPV6_TCP:
2418 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2419 MLX5_L3_PROT_TYPE_IPV6);
2420 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2421 MLX5_L4_PROT_TYPE_TCP);
2422 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2423 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2424 break;
2425
2426 case MLX5E_TT_IPV4_UDP:
2427 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2428 MLX5_L3_PROT_TYPE_IPV4);
2429 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2430 MLX5_L4_PROT_TYPE_UDP);
2431 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2432 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2433 break;
2434
2435 case MLX5E_TT_IPV6_UDP:
2436 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2437 MLX5_L3_PROT_TYPE_IPV6);
2438 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2439 MLX5_L4_PROT_TYPE_UDP);
2440 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2441 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2442 break;
2443
a741749f
AS		 2444 case MLX5E_TT_IPV4_IPSEC_AH:
2445 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2446 MLX5_L3_PROT_TYPE_IPV4);
2447 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2448 MLX5_HASH_IP_IPSEC_SPI);
2449 break;
2450
2451 case MLX5E_TT_IPV6_IPSEC_AH:
2452 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2453 MLX5_L3_PROT_TYPE_IPV6);
2454 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2455 MLX5_HASH_IP_IPSEC_SPI);
2456 break;
2457
2458 case MLX5E_TT_IPV4_IPSEC_ESP:
2459 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2460 MLX5_L3_PROT_TYPE_IPV4);
2461 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2462 MLX5_HASH_IP_IPSEC_SPI);
2463 break;
2464
2465 case MLX5E_TT_IPV6_IPSEC_ESP:
2466 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2467 MLX5_L3_PROT_TYPE_IPV6);
2468 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2469 MLX5_HASH_IP_IPSEC_SPI);
2470 break;
2471
f62b8bb8
AV		 2472 case MLX5E_TT_IPV4:
2473 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2474 MLX5_L3_PROT_TYPE_IPV4);
2475 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2476 MLX5_HASH_IP);
2477 break;
2478
2479 case MLX5E_TT_IPV6:
2480 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2481 MLX5_L3_PROT_TYPE_IPV6);
2482 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2483 MLX5_HASH_IP);
2484 break;
1da36696
TT		 2485 default:
2486 WARN_ONCE(true,
2487 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
f62b8bb8
AV		 2488 }
2489}
2490
1da36696
TT		 2491static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2492 u32 rqtn)
f62b8bb8 2493{
b50d292b 2494 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696
TT		 2495
2496 mlx5e_build_tir_ctx_lro(tirc, priv);
2497
2498 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2499 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2500 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2501}
2502
6bfd390b 2503static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2504{
724b2aa1 2505 struct mlx5e_tir *tir;
f62b8bb8
AV		 2506 void *tirc;
2507 int inlen;
2508 int err;
1da36696 2509 u32 *in;
1da36696 2510 int tt;
f62b8bb8
AV		 2511
2512 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2513 in = mlx5_vzalloc(inlen);
2514 if (!in)
2515 return -ENOMEM;
2516
1da36696
TT		 2517 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2518 memset(in, 0, inlen);
724b2aa1 2519 tir = &priv->indir_tir[tt];
1da36696
TT		 2520 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2521 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
724b2aa1 2522 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2523 if (err)
40ab6a6e 2524 goto err_destroy_tirs;
f62b8bb8
AV		 2525 }
2526
6bfd390b
HHZ		 2527 kvfree(in);
2528
2529 return 0;
2530
2531err_destroy_tirs:
2532 for (tt--; tt >= 0; tt--)
2533 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2534
2535 kvfree(in);
2536
2537 return err;
2538}
2539
cb67b832 2540int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2541{
2542 int nch = priv->profile->max_nch(priv->mdev);
2543 struct mlx5e_tir *tir;
2544 void *tirc;
2545 int inlen;
2546 int err;
2547 u32 *in;
2548 int ix;
2549
2550 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2551 in = mlx5_vzalloc(inlen);
2552 if (!in)
2553 return -ENOMEM;
2554
1da36696
TT		 2555 for (ix = 0; ix < nch; ix++) {
2556 memset(in, 0, inlen);
724b2aa1 2557 tir = &priv->direct_tir[ix];
1da36696
TT		 2558 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2559 mlx5e_build_direct_tir_ctx(priv, tirc,
398f3351 2560 priv->direct_tir[ix].rqt.rqtn);
724b2aa1 2561 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2562 if (err)
2563 goto err_destroy_ch_tirs;
2564 }
2565
2566 kvfree(in);
2567
f62b8bb8
AV		 2568 return 0;
2569
1da36696
TT		 2570err_destroy_ch_tirs:
2571 for (ix--; ix >= 0; ix--)
724b2aa1 2572 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2573
1da36696 2574 kvfree(in);
f62b8bb8
AV		 2575
2576 return err;
2577}
2578
6bfd390b 2579static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2580{
2581 int i;
2582
1da36696 2583 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2584 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2585}
2586
cb67b832 2587void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2588{
2589 int nch = priv->profile->max_nch(priv->mdev);
2590 int i;
2591
2592 for (i = 0; i < nch; i++)
2593 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2594}
2595
36350114
GP		 2596int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2597{
2598 int err = 0;
2599 int i;
2600
2601 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2602 return 0;
2603
2604 for (i = 0; i < priv->params.num_channels; i++) {
2605 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2606 if (err)
2607 return err;
2608 }
2609
2610 return 0;
2611}
2612
08fb1dac
SM		 2613static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2614{
2615 struct mlx5e_priv *priv = netdev_priv(netdev);
2616 bool was_opened;
2617 int err = 0;
2618
2619 if (tc && tc != MLX5E_MAX_NUM_TC)
2620 return -EINVAL;
2621
2622 mutex_lock(&priv->state_lock);
2623
2624 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2625 if (was_opened)
2626 mlx5e_close_locked(priv->netdev);
2627
2628 priv->params.num_tc = tc ? tc : 1;
2629
2630 if (was_opened)
2631 err = mlx5e_open_locked(priv->netdev);
2632
2633 mutex_unlock(&priv->state_lock);
2634
2635 return err;
2636}
2637
2638static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2639 __be16 proto, struct tc_to_netdev *tc)
2640{
e8f887ac
AV		 2641 struct mlx5e_priv *priv = netdev_priv(dev);
2642
2643 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2644 goto mqprio;
2645
2646 switch (tc->type) {
e3a2b7ed
AV		 2647 case TC_SETUP_CLSFLOWER:
2648 switch (tc->cls_flower->command) {
2649 case TC_CLSFLOWER_REPLACE:
2650 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2651 case TC_CLSFLOWER_DESTROY:
2652 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 2653 case TC_CLSFLOWER_STATS:
2654 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 2655 }
e8f887ac
AV		 2656 default:
2657 return -EOPNOTSUPP;
2658 }
2659
2660mqprio:
67ba422e 2661 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2662 return -EINVAL;
2663
2664 return mlx5e_setup_tc(dev, tc->tc);
2665}
2666
cb67b832 2667struct rtnl_link_stats64 *
f62b8bb8
AV		 2668mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2669{
2670 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2671 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2672 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2673 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2674
9218b44d
GP		 2675 stats->rx_packets = sstats->rx_packets;
2676 stats->rx_bytes = sstats->rx_bytes;
2677 stats->tx_packets = sstats->tx_packets;
2678 stats->tx_bytes = sstats->tx_bytes;
269e6b3a
GP		 2679
2680 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
9218b44d 2681 stats->tx_dropped = sstats->tx_queue_dropped;
269e6b3a
GP		 2682
2683 stats->rx_length_errors =
9218b44d
GP		 2684 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2685 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2686 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2687 stats->rx_crc_errors =
9218b44d
GP		 2688 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2689 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2690 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2691 stats->tx_carrier_errors =
9218b44d 2692 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2693 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2694 stats->rx_frame_errors;
2695 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2696
2697 /* vport multicast also counts packets that are dropped due to steering
2698 * or rx out of buffer
2699 */
9218b44d
GP		 2700 stats->multicast =
2701 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 2702
2703 return stats;
2704}
2705
2706static void mlx5e_set_rx_mode(struct net_device *dev)
2707{
2708 struct mlx5e_priv *priv = netdev_priv(dev);
2709
7bb29755 2710 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2711}
2712
2713static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2714{
2715 struct mlx5e_priv *priv = netdev_priv(netdev);
2716 struct sockaddr *saddr = addr;
2717
2718 if (!is_valid_ether_addr(saddr->sa_data))
2719 return -EADDRNOTAVAIL;
2720
2721 netif_addr_lock_bh(netdev);
2722 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2723 netif_addr_unlock_bh(netdev);
2724
7bb29755 2725 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2726
2727 return 0;
2728}
2729
0e405443
GP		 2730#define MLX5E_SET_FEATURE(netdev, feature, enable) \
2731 do { \
2732 if (enable) \
2733 netdev->features |= feature; \
2734 else \
2735 netdev->features &= ~feature; \
2736 } while (0)
2737
2738typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2739
2740static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 2741{
2742 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 2743 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2744 int err;
f62b8bb8
AV		 2745
2746 mutex_lock(&priv->state_lock);
f62b8bb8 2747
0e405443
GP		 2748 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2749 mlx5e_close_locked(priv->netdev);
98e81b0a 2750
0e405443
GP		 2751 priv->params.lro_en = enable;
2752 err = mlx5e_modify_tirs_lro(priv);
2753 if (err) {
2754 netdev_err(netdev, "lro modify failed, %d\n", err);
2755 priv->params.lro_en = !enable;
98e81b0a 2756 }
f62b8bb8 2757
0e405443
GP		 2758 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2759 mlx5e_open_locked(priv->netdev);
2760
9b37b07f
AS		 2761 mutex_unlock(&priv->state_lock);
2762
0e405443
GP		 2763 return err;
2764}
2765
2766static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2767{
2768 struct mlx5e_priv *priv = netdev_priv(netdev);
2769
2770 if (enable)
2771 mlx5e_enable_vlan_filter(priv);
2772 else
2773 mlx5e_disable_vlan_filter(priv);
2774
2775 return 0;
2776}
2777
2778static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2779{
2780 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 2781
0e405443 2782 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 2783 netdev_err(netdev,
2784 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2785 return -EINVAL;
2786 }
2787
0e405443
GP		 2788 return 0;
2789}
2790
94cb1ebb
EBE		 2791static int set_feature_rx_all(struct net_device *netdev, bool enable)
2792{
2793 struct mlx5e_priv *priv = netdev_priv(netdev);
2794 struct mlx5_core_dev *mdev = priv->mdev;
2795
2796 return mlx5_set_port_fcs(mdev, !enable);
2797}
2798
36350114
GP		 2799static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2800{
2801 struct mlx5e_priv *priv = netdev_priv(netdev);
2802 int err;
2803
2804 mutex_lock(&priv->state_lock);
2805
2806 priv->params.vlan_strip_disable = !enable;
2807 err = mlx5e_modify_rqs_vsd(priv, !enable);
2808 if (err)
2809 priv->params.vlan_strip_disable = enable;
2810
2811 mutex_unlock(&priv->state_lock);
2812
2813 return err;
2814}
2815
45bf454a
MG		 2816#ifdef CONFIG_RFS_ACCEL
2817static int set_feature_arfs(struct net_device *netdev, bool enable)
2818{
2819 struct mlx5e_priv *priv = netdev_priv(netdev);
2820 int err;
2821
2822 if (enable)
2823 err = mlx5e_arfs_enable(priv);
2824 else
2825 err = mlx5e_arfs_disable(priv);
2826
2827 return err;
2828}
2829#endif
2830
0e405443
GP		 2831static int mlx5e_handle_feature(struct net_device *netdev,
2832 netdev_features_t wanted_features,
2833 netdev_features_t feature,
2834 mlx5e_feature_handler feature_handler)
2835{
2836 netdev_features_t changes = wanted_features ^ netdev->features;
2837 bool enable = !!(wanted_features & feature);
2838 int err;
2839
2840 if (!(changes & feature))
2841 return 0;
2842
2843 err = feature_handler(netdev, enable);
2844 if (err) {
2845 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2846 enable ? "Enable" : "Disable", feature, err);
2847 return err;
2848 }
2849
2850 MLX5E_SET_FEATURE(netdev, feature, enable);
2851 return 0;
2852}
2853
2854static int mlx5e_set_features(struct net_device *netdev,
2855 netdev_features_t features)
2856{
2857 int err;
2858
2859 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2860 set_feature_lro);
2861 err |= mlx5e_handle_feature(netdev, features,
2862 NETIF_F_HW_VLAN_CTAG_FILTER,
2863 set_feature_vlan_filter);
2864 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2865 set_feature_tc_num_filters);
94cb1ebb
EBE		 2866 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2867 set_feature_rx_all);
36350114
GP		 2868 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2869 set_feature_rx_vlan);
45bf454a
MG		 2870#ifdef CONFIG_RFS_ACCEL
2871 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2872 set_feature_arfs);
2873#endif
0e405443
GP		 2874
2875 return err ? -EINVAL : 0;
f62b8bb8
AV		 2876}
2877
2878static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2879{
2880 struct mlx5e_priv *priv = netdev_priv(netdev);
98e81b0a 2881 bool was_opened;
98e81b0a 2882 int err = 0;
506753b0 2883 bool reset;
f62b8bb8 2884
f62b8bb8 2885 mutex_lock(&priv->state_lock);
98e81b0a 2886
506753b0
TT		 2887 reset = !priv->params.lro_en &&
2888 (priv->params.rq_wq_type !=
2889 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2890
98e81b0a 2891 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
506753b0 2892 if (was_opened && reset)
98e81b0a
AS		 2893 mlx5e_close_locked(netdev);
2894
f62b8bb8 2895 netdev->mtu = new_mtu;
13f9bba7 2896 mlx5e_set_dev_port_mtu(netdev);
98e81b0a 2897
506753b0 2898 if (was_opened && reset)
98e81b0a
AS		 2899 err = mlx5e_open_locked(netdev);
2900
f62b8bb8
AV		 2901 mutex_unlock(&priv->state_lock);
2902
2903 return err;
2904}
2905
ef9814de
EBE		 2906static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2907{
2908 switch (cmd) {
2909 case SIOCSHWTSTAMP:
2910 return mlx5e_hwstamp_set(dev, ifr);
2911 case SIOCGHWTSTAMP:
2912 return mlx5e_hwstamp_get(dev, ifr);
2913 default:
2914 return -EOPNOTSUPP;
2915 }
2916}
2917
66e49ded
SM		 2918static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2919{
2920 struct mlx5e_priv *priv = netdev_priv(dev);
2921 struct mlx5_core_dev *mdev = priv->mdev;
2922
2923 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2924}
2925
79aab093
MS		 2926static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2927 __be16 vlan_proto)
66e49ded
SM		 2928{
2929 struct mlx5e_priv *priv = netdev_priv(dev);
2930 struct mlx5_core_dev *mdev = priv->mdev;
2931
79aab093
MS		 2932 if (vlan_proto != htons(ETH_P_8021Q))
2933 return -EPROTONOSUPPORT;
2934
66e49ded
SM		 2935 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2936 vlan, qos);
2937}
2938
f942380c
MHY		 2939static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2940{
2941 struct mlx5e_priv *priv = netdev_priv(dev);
2942 struct mlx5_core_dev *mdev = priv->mdev;
2943
2944 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2945}
2946
1edc57e2
MHY		 2947static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2948{
2949 struct mlx5e_priv *priv = netdev_priv(dev);
2950 struct mlx5_core_dev *mdev = priv->mdev;
2951
2952 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2953}
bd77bf1c
MHY		 2954
2955static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2956 int max_tx_rate)
2957{
2958 struct mlx5e_priv *priv = netdev_priv(dev);
2959 struct mlx5_core_dev *mdev = priv->mdev;
2960
2961 if (min_tx_rate)
2962 return -EOPNOTSUPP;
2963
2964 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
2965 max_tx_rate);
2966}
2967
66e49ded
SM		 2968static int mlx5_vport_link2ifla(u8 esw_link)
2969{
2970 switch (esw_link) {
2971 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2972 return IFLA_VF_LINK_STATE_DISABLE;
2973 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2974 return IFLA_VF_LINK_STATE_ENABLE;
2975 }
2976 return IFLA_VF_LINK_STATE_AUTO;
2977}
2978
2979static int mlx5_ifla_link2vport(u8 ifla_link)
2980{
2981 switch (ifla_link) {
2982 case IFLA_VF_LINK_STATE_DISABLE:
2983 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2984 case IFLA_VF_LINK_STATE_ENABLE:
2985 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2986 }
2987 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2988}
2989
2990static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2991 int link_state)
2992{
2993 struct mlx5e_priv *priv = netdev_priv(dev);
2994 struct mlx5_core_dev *mdev = priv->mdev;
2995
2996 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2997 mlx5_ifla_link2vport(link_state));
2998}
2999
3000static int mlx5e_get_vf_config(struct net_device *dev,
3001 int vf, struct ifla_vf_info *ivi)
3002{
3003 struct mlx5e_priv *priv = netdev_priv(dev);
3004 struct mlx5_core_dev *mdev = priv->mdev;
3005 int err;
3006
3007 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3008 if (err)
3009 return err;
3010 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3011 return 0;
3012}
3013
3014static int mlx5e_get_vf_stats(struct net_device *dev,
3015 int vf, struct ifla_vf_stats *vf_stats)
3016{
3017 struct mlx5e_priv *priv = netdev_priv(dev);
3018 struct mlx5_core_dev *mdev = priv->mdev;
3019
3020 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3021 vf_stats);
3022}
3023
4a25730e
HHZ		 3024void mlx5e_add_vxlan_port(struct net_device *netdev,
3025 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3026{
3027 struct mlx5e_priv *priv = netdev_priv(netdev);
3028
974c3f30
AD		 3029 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3030 return;
3031
b3f63c3d
MF		 3032 if (!mlx5e_vxlan_allowed(priv->mdev))
3033 return;
3034
974c3f30 3035 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3036}
3037
4a25730e
HHZ		 3038void mlx5e_del_vxlan_port(struct net_device *netdev,
3039 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3040{
3041 struct mlx5e_priv *priv = netdev_priv(netdev);
3042
974c3f30
AD		 3043 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3044 return;
3045
b3f63c3d
MF		 3046 if (!mlx5e_vxlan_allowed(priv->mdev))
3047 return;
3048
974c3f30 3049 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3050}
3051
3052static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3053 struct sk_buff *skb,
3054 netdev_features_t features)
3055{
3056 struct udphdr *udph;
3057 u16 proto;
3058 u16 port = 0;
3059
3060 switch (vlan_get_protocol(skb)) {
3061 case htons(ETH_P_IP):
3062 proto = ip_hdr(skb)->protocol;
3063 break;
3064 case htons(ETH_P_IPV6):
3065 proto = ipv6_hdr(skb)->nexthdr;
3066 break;
3067 default:
3068 goto out;
3069 }
3070
3071 if (proto == IPPROTO_UDP) {
3072 udph = udp_hdr(skb);
3073 port = be16_to_cpu(udph->dest);
3074 }
3075
3076 /* Verify if UDP port is being offloaded by HW */
3077 if (port && mlx5e_vxlan_lookup_port(priv, port))
3078 return features;
3079
3080out:
3081 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3082 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3083}
3084
3085static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3086 struct net_device *netdev,
3087 netdev_features_t features)
3088{
3089 struct mlx5e_priv *priv = netdev_priv(netdev);
3090
3091 features = vlan_features_check(skb, features);
3092 features = vxlan_features_check(skb, features);
3093
3094 /* Validate if the tunneled packet is being offloaded by HW */
3095 if (skb->encapsulation &&
3096 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3097 return mlx5e_vxlan_features_check(priv, skb, features);
3098
3099 return features;
3100}
3101
3947ca18
DJ		 3102static void mlx5e_tx_timeout(struct net_device *dev)
3103{
3104 struct mlx5e_priv *priv = netdev_priv(dev);
3105 bool sched_work = false;
3106 int i;
3107
3108 netdev_err(dev, "TX timeout detected\n");
3109
3110 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3111 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3112
2c1ccc99 3113 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3114 continue;
3115 sched_work = true;
6e8dd6d6 3116 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
3947ca18
DJ		 3117 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3118 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3119 }
3120
3121 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3122 schedule_work(&priv->tx_timeout_work);
3123}
3124
86994156
RS		 3125static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3126{
3127 struct mlx5e_priv *priv = netdev_priv(netdev);
3128 struct bpf_prog *old_prog;
3129 int err = 0;
3130 bool reset, was_opened;
3131 int i;
3132
3133 mutex_lock(&priv->state_lock);
3134
3135 if ((netdev->features & NETIF_F_LRO) && prog) {
3136 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3137 err = -EINVAL;
3138 goto unlock;
3139 }
3140
3141 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3142 /* no need for full reset when exchanging programs */
3143 reset = (!priv->xdp_prog || !prog);
3144
3145 if (was_opened && reset)
3146 mlx5e_close_locked(netdev);
c54c0629
DB		 3147 if (was_opened && !reset) {
3148 /* num_channels is invariant here, so we can take the
3149 * batched reference right upfront.
3150 */
3151 prog = bpf_prog_add(prog, priv->params.num_channels);
3152 if (IS_ERR(prog)) {
3153 err = PTR_ERR(prog);
3154 goto unlock;
3155 }
3156 }
86994156 3157
c54c0629
DB		 3158 /* exchange programs, extra prog reference we got from caller
3159 * as long as we don't fail from this point onwards.
3160 */
86994156 3161 old_prog = xchg(&priv->xdp_prog, prog);
86994156
RS		 3162 if (old_prog)
3163 bpf_prog_put(old_prog);
3164
3165 if (reset) /* change RQ type according to priv->xdp_prog */
3166 mlx5e_set_rq_priv_params(priv);
3167
3168 if (was_opened && reset)
3169 mlx5e_open_locked(netdev);
3170
3171 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3172 goto unlock;
3173
3174 /* exchanging programs w/o reset, we update ref counts on behalf
3175 * of the channels RQs here.
3176 */
86994156
RS		 3177 for (i = 0; i < priv->params.num_channels; i++) {
3178 struct mlx5e_channel *c = priv->channel[i];
3179
3180 set_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3181 napi_synchronize(&c->napi);
3182 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3183
3184 old_prog = xchg(&c->rq.xdp_prog, prog);
3185
3186 clear_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3187 /* napi_schedule in case we have missed anything */
3188 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3189 napi_schedule(&c->napi);
3190
3191 if (old_prog)
3192 bpf_prog_put(old_prog);
3193 }
3194
3195unlock:
3196 mutex_unlock(&priv->state_lock);
3197 return err;
3198}
3199
3200static bool mlx5e_xdp_attached(struct net_device *dev)
3201{
3202 struct mlx5e_priv *priv = netdev_priv(dev);
3203
3204 return !!priv->xdp_prog;
3205}
3206
3207static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3208{
3209 switch (xdp->command) {
3210 case XDP_SETUP_PROG:
3211 return mlx5e_xdp_set(dev, xdp->prog);
3212 case XDP_QUERY_PROG:
3213 xdp->prog_attached = mlx5e_xdp_attached(dev);
3214 return 0;
3215 default:
3216 return -EINVAL;
3217 }
3218}
3219
80378384
CO		 3220#ifdef CONFIG_NET_POLL_CONTROLLER
3221/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3222 * reenabling interrupts.
3223 */
3224static void mlx5e_netpoll(struct net_device *dev)
3225{
3226 struct mlx5e_priv *priv = netdev_priv(dev);
3227 int i;
3228
3229 for (i = 0; i < priv->params.num_channels; i++)
3230 napi_schedule(&priv->channel[i]->napi);
3231}
3232#endif
3233
b0eed40e 3234static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 3235 .ndo_open = mlx5e_open,
3236 .ndo_stop = mlx5e_close,
3237 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3238 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3239 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3240 .ndo_get_stats64 = mlx5e_get_stats,
3241 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3242 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3243 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3244 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3245 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 3246 .ndo_change_mtu = mlx5e_change_mtu,
3247 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3248 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 3249#ifdef CONFIG_RFS_ACCEL
3250 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3251#endif
3947ca18 3252 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3253 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3254#ifdef CONFIG_NET_POLL_CONTROLLER
3255 .ndo_poll_controller = mlx5e_netpoll,
3256#endif
b0eed40e
SM		 3257};
3258
3259static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3260 .ndo_open = mlx5e_open,
3261 .ndo_stop = mlx5e_close,
3262 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3263 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3264 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 3265 .ndo_get_stats64 = mlx5e_get_stats,
3266 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3267 .ndo_set_mac_address = mlx5e_set_mac,
3268 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3269 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3270 .ndo_set_features = mlx5e_set_features,
3271 .ndo_change_mtu = mlx5e_change_mtu,
3272 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 3273 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3274 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 3275 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 3276 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3277#ifdef CONFIG_RFS_ACCEL
3278 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3279#endif
b0eed40e
SM		 3280 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3281 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3282 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3283 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3284 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3285 .ndo_get_vf_config = mlx5e_get_vf_config,
3286 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3287 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 3288 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3289 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3290#ifdef CONFIG_NET_POLL_CONTROLLER
3291 .ndo_poll_controller = mlx5e_netpoll,
3292#endif
f62b8bb8
AV		 3293};
3294
3295static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3296{
3297 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3298 return -ENOTSUPP;
3299 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3300 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3301 !MLX5_CAP_ETH(mdev, csum_cap) ||
3302 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3303 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3304 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3305 MLX5_CAP_FLOWTABLE(mdev,
3306 flow_table_properties_nic_receive.max_ft_level)
3307 < 3) {
f62b8bb8
AV		 3308 mlx5_core_warn(mdev,
3309 "Not creating net device, some required device capabilities are missing\n");
3310 return -ENOTSUPP;
3311 }
66189961
TT		 3312 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3313 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 3314 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3315 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 3316
f62b8bb8
AV		 3317 return 0;
3318}
3319
58d52291
AS		 3320u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3321{
3322 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3323
3324 return bf_buf_size -
3325 sizeof(struct mlx5e_tx_wqe) +
3326 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3327}
3328
08fb1dac
SM		 3329#ifdef CONFIG_MLX5_CORE_EN_DCB
3330static void mlx5e_ets_init(struct mlx5e_priv *priv)
3331{
3332 int i;
3333
3334 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
3335 for (i = 0; i < priv->params.ets.ets_cap; i++) {
3336 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
3337 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
3338 priv->params.ets.prio_tc[i] = i;
3339 }
3340
3341 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
3342 priv->params.ets.prio_tc[0] = 1;
3343 priv->params.ets.prio_tc[1] = 0;
3344}
3345#endif
3346
d8c9660d
TT		 3347void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3348 u32 *indirection_rqt, int len,
85082dba
TT		 3349 int num_channels)
3350{
d8c9660d
TT		 3351 int node = mdev->priv.numa_node;
3352 int node_num_of_cores;
85082dba
TT		 3353 int i;
3354
d8c9660d
TT		 3355 if (node == -1)
3356 node = first_online_node;
3357
3358 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3359
3360 if (node_num_of_cores)
3361 num_channels = min_t(int, num_channels, node_num_of_cores);
3362
85082dba
TT		 3363 for (i = 0; i < len; i++)
3364 indirection_rqt[i] = i % num_channels;
3365}
3366
b797a684
SM		 3367static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3368{
3369 enum pcie_link_width width;
3370 enum pci_bus_speed speed;
3371 int err = 0;
3372
3373 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3374 if (err)
3375 return err;
3376
3377 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3378 return -EINVAL;
3379
3380 switch (speed) {
3381 case PCIE_SPEED_2_5GT:
3382 *pci_bw = 2500 * width;
3383 break;
3384 case PCIE_SPEED_5_0GT:
3385 *pci_bw = 5000 * width;
3386 break;
3387 case PCIE_SPEED_8_0GT:
3388 *pci_bw = 8000 * width;
3389 break;
3390 default:
3391 return -EINVAL;
3392 }
3393
3394 return 0;
3395}
3396
3397static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3398{
3399 return (link_speed && pci_bw &&
3400 (pci_bw < 40000) && (pci_bw < link_speed));
3401}
3402
9908aa29
TT		 3403void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3404{
3405 params->rx_cq_period_mode = cq_period_mode;
3406
3407 params->rx_cq_moderation.pkts =
3408 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3409 params->rx_cq_moderation.usec =
3410 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3411
3412 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3413 params->rx_cq_moderation.usec =
3414 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3415}
3416
cff92d7c
HHZ		 3417static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3418 u8 *min_inline_mode)
3419{
3420 switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
3421 case MLX5E_INLINE_MODE_L2:
3422 *min_inline_mode = MLX5_INLINE_MODE_L2;
3423 break;
3424 case MLX5E_INLINE_MODE_VPORT_CONTEXT:
3425 mlx5_query_nic_vport_min_inline(mdev,
3426 min_inline_mode);
3427 break;
3428 case MLX5_INLINE_MODE_NOT_REQUIRED:
3429 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3430 break;
3431 }
3432}
3433
2b029556
SM		 3434u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3435{
3436 int i;
3437
3438 /* The supported periods are organized in ascending order */
3439 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3440 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3441 break;
3442
3443 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3444}
3445
6bfd390b
HHZ		 3446static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3447 struct net_device *netdev,
127ea380
HHZ		 3448 const struct mlx5e_profile *profile,
3449 void *ppriv)
f62b8bb8
AV		 3450{
3451 struct mlx5e_priv *priv = netdev_priv(netdev);
b797a684
SM		 3452 u32 link_speed = 0;
3453 u32 pci_bw = 0;
cb3c7fd4
GR		 3454 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3455 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3456 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8 3457
2fc4bfb7
SM		 3458 priv->mdev = mdev;
3459 priv->netdev = netdev;
3460 priv->params.num_channels = profile->max_nch(mdev);
3461 priv->profile = profile;
3462 priv->ppriv = ppriv;
3463
2b029556
SM		 3464 priv->params.lro_timeout =
3465 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3466
2fc4bfb7 3467 priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3468
b797a684
SM		 3469 /* set CQE compression */
3470 priv->params.rx_cqe_compress_admin = false;
3471 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3472 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3473 mlx5e_get_max_linkspeed(mdev, &link_speed);
3474 mlx5e_get_pci_bw(mdev, &pci_bw);
3475 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3476 link_speed, pci_bw);
3477 priv->params.rx_cqe_compress_admin =
3478 cqe_compress_heuristic(link_speed, pci_bw);
3479 }
b797a684
SM		 3480 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3481
2fc4bfb7
SM		 3482 mlx5e_set_rq_priv_params(priv);
3483 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
461017cb 3484 priv->params.lro_en = true;
9908aa29 3485
cb3c7fd4
GR		 3486 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3487 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
9908aa29
TT		 3488
3489 priv->params.tx_cq_moderation.usec =
f62b8bb8 3490 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
9908aa29 3491 priv->params.tx_cq_moderation.pkts =
f62b8bb8 3492 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 3493 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
cff92d7c 3494 mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
f62b8bb8 3495 priv->params.num_tc = 1;
2be6967c 3496 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 3497
57afead5
AS		 3498 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3499 sizeof(priv->params.toeplitz_hash_key));
3500
d8c9660d 3501 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
6bfd390b 3502 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
2d75b2bc 3503
e4b85508
SM		 3504 priv->params.lro_wqe_sz =
3505 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3506 /* Extra room needed for build_skb */
3507 MLX5_RX_HEADROOM -
3508 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
f62b8bb8 3509
9908aa29
TT		 3510 /* Initialize pflags */
3511 MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3512 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3513
08fb1dac
SM		 3514#ifdef CONFIG_MLX5_CORE_EN_DCB
3515 mlx5e_ets_init(priv);
3516#endif
f62b8bb8 3517
f62b8bb8
AV		 3518 mutex_init(&priv->state_lock);
3519
3520 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3521 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3522 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3523 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3524}
3525
3526static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3527{
3528 struct mlx5e_priv *priv = netdev_priv(netdev);
3529
e1d7d349 3530 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3531 if (is_zero_ether_addr(netdev->dev_addr) &&
3532 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3533 eth_hw_addr_random(netdev);
3534 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3535 }
f62b8bb8
AV		 3536}
3537
cb67b832
HHZ		 3538static const struct switchdev_ops mlx5e_switchdev_ops = {
3539 .switchdev_port_attr_get = mlx5e_attr_get,
3540};
3541
6bfd390b 3542static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3543{
3544 struct mlx5e_priv *priv = netdev_priv(netdev);
3545 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3546 bool fcs_supported;
3547 bool fcs_enabled;
f62b8bb8
AV		 3548
3549 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3550
08fb1dac 3551 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3552 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac
SM		 3553#ifdef CONFIG_MLX5_CORE_EN_DCB
3554 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3555#endif
3556 } else {
b0eed40e 3557 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3558 }
66e49ded 3559
f62b8bb8
AV		 3560 netdev->watchdog_timeo = 15 * HZ;
3561
3562 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3563
12be4b21 3564 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3565 netdev->vlan_features |= NETIF_F_IP_CSUM;
3566 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3567 netdev->vlan_features |= NETIF_F_GRO;
3568 netdev->vlan_features |= NETIF_F_TSO;
3569 netdev->vlan_features |= NETIF_F_TSO6;
3570 netdev->vlan_features |= NETIF_F_RXCSUM;
3571 netdev->vlan_features |= NETIF_F_RXHASH;
3572
3573 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3574 netdev->vlan_features |= NETIF_F_LRO;
3575
3576 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3577 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3578 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3579 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3580
b3f63c3d 3581 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3582 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3583 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3584 NETIF_F_GSO_PARTIAL;
b3f63c3d 3585 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3586 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3587 netdev->hw_enc_features |= NETIF_F_TSO;
3588 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3589 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3590 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3591 NETIF_F_GSO_PARTIAL;
3592 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3593 }
3594
94cb1ebb
EBE		 3595 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3596
3597 if (fcs_supported)
3598 netdev->hw_features |= NETIF_F_RXALL;
3599
f62b8bb8
AV		 3600 netdev->features = netdev->hw_features;
3601 if (!priv->params.lro_en)
3602 netdev->features &= ~NETIF_F_LRO;
3603
94cb1ebb
EBE		 3604 if (fcs_enabled)
3605 netdev->features &= ~NETIF_F_RXALL;
3606
e8f887ac
AV		 3607#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3608 if (FT_CAP(flow_modify_en) &&
3609 FT_CAP(modify_root) &&
3610 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3611 FT_CAP(flow_table_modify)) {
3612 netdev->hw_features |= NETIF_F_HW_TC;
3613#ifdef CONFIG_RFS_ACCEL
3614 netdev->hw_features |= NETIF_F_NTUPLE;
3615#endif
3616 }
e8f887ac 3617
f62b8bb8
AV		 3618 netdev->features |= NETIF_F_HIGHDMA;
3619
3620 netdev->priv_flags |= IFF_UNICAST_FLT;
3621
3622 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 3623
3624#ifdef CONFIG_NET_SWITCHDEV
3625 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3626 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3627#endif
f62b8bb8
AV		 3628}
3629
593cf338
RS		 3630static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3631{
3632 struct mlx5_core_dev *mdev = priv->mdev;
3633 int err;
3634
3635 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3636 if (err) {
3637 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3638 priv->q_counter = 0;
3639 }
3640}
3641
3642static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3643{
3644 if (!priv->q_counter)
3645 return;
3646
3647 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3648}
3649
bc77b240
TT		 3650static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3651{
3652 struct mlx5_core_dev *mdev = priv->mdev;
fe4c988b
SM		 3653 u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3654 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
ec22eb53
SM		 3655 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3656 void *mkc;
3657 u32 *in;
bc77b240
TT		 3658 int err;
3659
3660 in = mlx5_vzalloc(inlen);
3661 if (!in)
3662 return -ENOMEM;
3663
ec22eb53 3664 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
bc77b240 3665
fe4c988b
SM		 3666 npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3667
ec22eb53
SM		 3668 MLX5_SET(mkc, mkc, free, 1);
3669 MLX5_SET(mkc, mkc, umr_en, 1);
3670 MLX5_SET(mkc, mkc, lw, 1);
3671 MLX5_SET(mkc, mkc, lr, 1);
3672 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
bc77b240 3673
ec22eb53
SM		 3674 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3675 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3676 MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3677 MLX5_SET(mkc, mkc, translations_octword_size,
6abdd5f5 3678 MLX5_MTT_OCTW(npages));
ec22eb53 3679 MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
bc77b240 3680
ec22eb53 3681 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
bc77b240 3682
ec22eb53 3683 kvfree(in);
bc77b240
TT		 3684 return err;
3685}
3686
6bfd390b
HHZ		 3687static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3688 struct net_device *netdev,
127ea380
HHZ		 3689 const struct mlx5e_profile *profile,
3690 void *ppriv)
6bfd390b
HHZ		 3691{
3692 struct mlx5e_priv *priv = netdev_priv(netdev);
3693
127ea380 3694 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 3695 mlx5e_build_nic_netdev(netdev);
3696 mlx5e_vxlan_init(priv);
3697}
3698
3699static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3700{
127ea380
HHZ		 3701 struct mlx5_core_dev *mdev = priv->mdev;
3702 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3703
6bfd390b 3704 mlx5e_vxlan_cleanup(priv);
127ea380
HHZ		 3705
3706 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3707 mlx5_eswitch_unregister_vport_rep(esw, 0);
a055c19b
DB		 3708
3709 if (priv->xdp_prog)
3710 bpf_prog_put(priv->xdp_prog);
6bfd390b
HHZ		 3711}
3712
3713static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3714{
3715 struct mlx5_core_dev *mdev = priv->mdev;
3716 int err;
3717 int i;
3718
3719 err = mlx5e_create_indirect_rqts(priv);
3720 if (err) {
3721 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3722 return err;
3723 }
3724
3725 err = mlx5e_create_direct_rqts(priv);
3726 if (err) {
3727 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3728 goto err_destroy_indirect_rqts;
3729 }
3730
3731 err = mlx5e_create_indirect_tirs(priv);
3732 if (err) {
3733 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3734 goto err_destroy_direct_rqts;
3735 }
3736
3737 err = mlx5e_create_direct_tirs(priv);
3738 if (err) {
3739 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3740 goto err_destroy_indirect_tirs;
3741 }
3742
3743 err = mlx5e_create_flow_steering(priv);
3744 if (err) {
3745 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3746 goto err_destroy_direct_tirs;
3747 }
3748
3749 err = mlx5e_tc_init(priv);
3750 if (err)
3751 goto err_destroy_flow_steering;
3752
3753 return 0;
3754
3755err_destroy_flow_steering:
3756 mlx5e_destroy_flow_steering(priv);
3757err_destroy_direct_tirs:
3758 mlx5e_destroy_direct_tirs(priv);
3759err_destroy_indirect_tirs:
3760 mlx5e_destroy_indirect_tirs(priv);
3761err_destroy_direct_rqts:
3762 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3763 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3764err_destroy_indirect_rqts:
3765 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3766 return err;
3767}
3768
3769static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3770{
3771 int i;
3772
3773 mlx5e_tc_cleanup(priv);
3774 mlx5e_destroy_flow_steering(priv);
3775 mlx5e_destroy_direct_tirs(priv);
3776 mlx5e_destroy_indirect_tirs(priv);
3777 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3778 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3779 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3780}
3781
3782static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3783{
3784 int err;
3785
3786 err = mlx5e_create_tises(priv);
3787 if (err) {
3788 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3789 return err;
3790 }
3791
3792#ifdef CONFIG_MLX5_CORE_EN_DCB
3793 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3794#endif
3795 return 0;
3796}
3797
3798static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3799{
3800 struct net_device *netdev = priv->netdev;
3801 struct mlx5_core_dev *mdev = priv->mdev;
127ea380
HHZ		 3802 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3803 struct mlx5_eswitch_rep rep;
6bfd390b 3804
7907f23a
AH		 3805 mlx5_lag_add(mdev, netdev);
3806
6bfd390b
HHZ		 3807 if (mlx5e_vxlan_allowed(mdev)) {
3808 rtnl_lock();
3809 udp_tunnel_get_rx_info(netdev);
3810 rtnl_unlock();
3811 }
3812
3813 mlx5e_enable_async_events(priv);
3814 queue_work(priv->wq, &priv->set_rx_mode_work);
127ea380
HHZ		 3815
3816 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
dbe413e3 3817 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
cb67b832
HHZ		 3818 rep.load = mlx5e_nic_rep_load;
3819 rep.unload = mlx5e_nic_rep_unload;
9deb2241 3820 rep.vport = FDB_UPLINK_VPORT;
127ea380 3821 rep.priv_data = priv;
9deb2241 3822 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
127ea380 3823 }
6bfd390b
HHZ		 3824}
3825
3826static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3827{
3828 queue_work(priv->wq, &priv->set_rx_mode_work);
3829 mlx5e_disable_async_events(priv);
7907f23a 3830 mlx5_lag_remove(priv->mdev);
6bfd390b
HHZ		 3831}
3832
3833static const struct mlx5e_profile mlx5e_nic_profile = {
3834 .init = mlx5e_nic_init,
3835 .cleanup = mlx5e_nic_cleanup,
3836 .init_rx = mlx5e_init_nic_rx,
3837 .cleanup_rx = mlx5e_cleanup_nic_rx,
3838 .init_tx = mlx5e_init_nic_tx,
3839 .cleanup_tx = mlx5e_cleanup_nic_tx,
3840 .enable = mlx5e_nic_enable,
3841 .disable = mlx5e_nic_disable,
3842 .update_stats = mlx5e_update_stats,
3843 .max_nch = mlx5e_get_max_num_channels,
3844 .max_tc = MLX5E_MAX_NUM_TC,
3845};
3846
26e59d80
MHY		 3847struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3848 const struct mlx5e_profile *profile,
3849 void *ppriv)
f62b8bb8 3850{
26e59d80 3851 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 3852 struct net_device *netdev;
3853 struct mlx5e_priv *priv;
f62b8bb8 3854
08fb1dac 3855 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 3856 nch * profile->max_tc,
08fb1dac 3857 nch);
f62b8bb8
AV		 3858 if (!netdev) {
3859 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3860 return NULL;
3861 }
3862
127ea380 3863 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 3864
3865 netif_carrier_off(netdev);
3866
3867 priv = netdev_priv(netdev);
3868
7bb29755
MF		 3869 priv->wq = create_singlethread_workqueue("mlx5e");
3870 if (!priv->wq)
26e59d80
MHY		 3871 goto err_cleanup_nic;
3872
3873 return netdev;
3874
3875err_cleanup_nic:
3876 profile->cleanup(priv);
3877 free_netdev(netdev);
3878
3879 return NULL;
3880}
3881
3882int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3883{
3884 const struct mlx5e_profile *profile;
3885 struct mlx5e_priv *priv;
b80f71f5 3886 u16 max_mtu;
26e59d80
MHY		 3887 int err;
3888
3889 priv = netdev_priv(netdev);
3890 profile = priv->profile;
3891 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 3892
bc77b240
TT		 3893 err = mlx5e_create_umr_mkey(priv);
3894 if (err) {
3895 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
26e59d80 3896 goto out;
bc77b240
TT		 3897 }
3898
6bfd390b
HHZ		 3899 err = profile->init_tx(priv);
3900 if (err)
bc77b240 3901 goto err_destroy_umr_mkey;
5c50368f
AS		 3902
3903 err = mlx5e_open_drop_rq(priv);
3904 if (err) {
3905 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 3906 goto err_cleanup_tx;
5c50368f
AS		 3907 }
3908
6bfd390b
HHZ		 3909 err = profile->init_rx(priv);
3910 if (err)
5c50368f 3911 goto err_close_drop_rq;
5c50368f 3912
593cf338
RS		 3913 mlx5e_create_q_counter(priv);
3914
33cfaaa8 3915 mlx5e_init_l2_addr(priv);
5c50368f 3916
b80f71f5
JW		 3917 /* MTU range: 68 - hw-specific max */
3918 netdev->min_mtu = ETH_MIN_MTU;
3919 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
3920 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
3921
13f9bba7
SM		 3922 mlx5e_set_dev_port_mtu(netdev);
3923
6bfd390b
HHZ		 3924 if (profile->enable)
3925 profile->enable(priv);
f62b8bb8 3926
26e59d80
MHY		 3927 rtnl_lock();
3928 if (netif_running(netdev))
3929 mlx5e_open(netdev);
3930 netif_device_attach(netdev);
3931 rtnl_unlock();
f62b8bb8 3932
26e59d80 3933 return 0;
5c50368f
AS		 3934
3935err_close_drop_rq:
3936 mlx5e_close_drop_rq(priv);
3937
6bfd390b
HHZ		 3938err_cleanup_tx:
3939 profile->cleanup_tx(priv);
5c50368f 3940
bc77b240
TT		 3941err_destroy_umr_mkey:
3942 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3943
26e59d80
MHY		 3944out:
3945 return err;
f62b8bb8
AV		 3946}
3947
127ea380
HHZ		 3948static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3949{
3950 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3951 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3952 int vport;
dbe413e3 3953 u8 mac[ETH_ALEN];
127ea380
HHZ		 3954
3955 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3956 return;
3957
dbe413e3
HHZ		 3958 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3959
127ea380
HHZ		 3960 for (vport = 1; vport < total_vfs; vport++) {
3961 struct mlx5_eswitch_rep rep;
3962
cb67b832
HHZ		 3963 rep.load = mlx5e_vport_rep_load;
3964 rep.unload = mlx5e_vport_rep_unload;
127ea380 3965 rep.vport = vport;
dbe413e3 3966 ether_addr_copy(rep.hw_id, mac);
9deb2241 3967 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
127ea380
HHZ		 3968 }
3969}
3970
26e59d80
MHY		 3971void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3972{
3973 struct mlx5e_priv *priv = netdev_priv(netdev);
3974 const struct mlx5e_profile *profile = priv->profile;
3975
3976 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3977 if (profile->disable)
3978 profile->disable(priv);
3979
3980 flush_workqueue(priv->wq);
3981
3982 rtnl_lock();
3983 if (netif_running(netdev))
3984 mlx5e_close(netdev);
3985 netif_device_detach(netdev);
3986 rtnl_unlock();
3987
3988 mlx5e_destroy_q_counter(priv);
3989 profile->cleanup_rx(priv);
3990 mlx5e_close_drop_rq(priv);
3991 profile->cleanup_tx(priv);
3992 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3993 cancel_delayed_work_sync(&priv->update_stats_work);
3994}
3995
3996/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3997 * hardware contexts and to connect it to the current netdev.
3998 */
3999static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4000{
4001 struct mlx5e_priv *priv = vpriv;
4002 struct net_device *netdev = priv->netdev;
4003 int err;
4004
4005 if (netif_device_present(netdev))
4006 return 0;
4007
4008 err = mlx5e_create_mdev_resources(mdev);
4009 if (err)
4010 return err;
4011
4012 err = mlx5e_attach_netdev(mdev, netdev);
4013 if (err) {
4014 mlx5e_destroy_mdev_resources(mdev);
4015 return err;
4016 }
4017
4018 return 0;
4019}
4020
4021static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4022{
4023 struct mlx5e_priv *priv = vpriv;
4024 struct net_device *netdev = priv->netdev;
4025
4026 if (!netif_device_present(netdev))
4027 return;
4028
4029 mlx5e_detach_netdev(mdev, netdev);
4030 mlx5e_destroy_mdev_resources(mdev);
4031}
4032
b50d292b
HHZ		 4033static void *mlx5e_add(struct mlx5_core_dev *mdev)
4034{
127ea380 4035 struct mlx5_eswitch *esw = mdev->priv.eswitch;
26e59d80 4036 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
127ea380 4037 void *ppriv = NULL;
26e59d80
MHY		 4038 void *priv;
4039 int vport;
4040 int err;
4041 struct net_device *netdev;
b50d292b 4042
26e59d80
MHY		 4043 err = mlx5e_check_required_hca_cap(mdev);
4044 if (err)
b50d292b
HHZ		 4045 return NULL;
4046
127ea380
HHZ		 4047 mlx5e_register_vport_rep(mdev);
4048
4049 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4050 ppriv = &esw->offloads.vport_reps[0];
4051
26e59d80
MHY		 4052 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4053 if (!netdev) {
4054 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4055 goto err_unregister_reps;
4056 }
4057
4058 priv = netdev_priv(netdev);
4059
4060 err = mlx5e_attach(mdev, priv);
4061 if (err) {
4062 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4063 goto err_destroy_netdev;
4064 }
4065
4066 err = register_netdev(netdev);
4067 if (err) {
4068 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4069 goto err_detach;
b50d292b 4070 }
26e59d80
MHY		 4071
4072 return priv;
4073
4074err_detach:
4075 mlx5e_detach(mdev, priv);
4076
4077err_destroy_netdev:
4078 mlx5e_destroy_netdev(mdev, priv);
4079
4080err_unregister_reps:
4081 for (vport = 1; vport < total_vfs; vport++)
4082 mlx5_eswitch_unregister_vport_rep(esw, vport);
4083
4084 return NULL;
b50d292b
HHZ		 4085}
4086
cb67b832 4087void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
f62b8bb8 4088{
6bfd390b 4089 const struct mlx5e_profile *profile = priv->profile;
f62b8bb8
AV		 4090 struct net_device *netdev = priv->netdev;
4091
7bb29755 4092 destroy_workqueue(priv->wq);
6bfd390b
HHZ		 4093 if (profile->cleanup)
4094 profile->cleanup(priv);
26e59d80 4095 free_netdev(netdev);
f62b8bb8
AV		 4096}
4097
b50d292b
HHZ		 4098static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4099{
127ea380
HHZ		 4100 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4101 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
b50d292b 4102 struct mlx5e_priv *priv = vpriv;
127ea380 4103 int vport;
b50d292b 4104
127ea380
HHZ		 4105 for (vport = 1; vport < total_vfs; vport++)
4106 mlx5_eswitch_unregister_vport_rep(esw, vport);
4107
5e1e93c7 4108 unregister_netdev(priv->netdev);
26e59d80
MHY		 4109 mlx5e_detach(mdev, vpriv);
4110 mlx5e_destroy_netdev(mdev, priv);
b50d292b
HHZ		 4111}
4112
f62b8bb8
AV		 4113static void *mlx5e_get_netdev(void *vpriv)
4114{
4115 struct mlx5e_priv *priv = vpriv;
4116
4117 return priv->netdev;
4118}
4119
4120static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4121 .add = mlx5e_add,
4122 .remove = mlx5e_remove,
26e59d80
MHY		 4123 .attach = mlx5e_attach,
4124 .detach = mlx5e_detach,
f62b8bb8
AV		 4125 .event = mlx5e_async_event,
4126 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4127 .get_dev = mlx5e_get_netdev,
4128};
4129
4130void mlx5e_init(void)
4131{
665bc539 4132 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4133 mlx5_register_interface(&mlx5e_interface);
4134}
4135
4136void mlx5e_cleanup(void)
4137{
4138 mlx5_unregister_interface(&mlx5e_interface);
4139}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git