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[thirdparty/kernel/stable.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
f62b8bb8 37#include "en.h"
e8f887ac 38#include "en_tc.h"
66e49ded 39#include "eswitch.h"
b3f63c3d 40#include "vxlan.h"
f62b8bb8
AV		 41
42struct mlx5e_rq_param {
43 u32 rqc[MLX5_ST_SZ_DW(rqc)];
44 struct mlx5_wq_param wq;
45};
46
47struct mlx5e_sq_param {
48 u32 sqc[MLX5_ST_SZ_DW(sqc)];
49 struct mlx5_wq_param wq;
58d52291 50 u16 max_inline;
d3c9bc27 51 bool icosq;
f62b8bb8
AV		 52};
53
54struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
57 u16 eq_ix;
58};
59
60struct mlx5e_channel_param {
61 struct mlx5e_rq_param rq;
62 struct mlx5e_sq_param sq;
d3c9bc27 63 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 64 struct mlx5e_cq_param rx_cq;
65 struct mlx5e_cq_param tx_cq;
d3c9bc27 66 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 67};
68
69static void mlx5e_update_carrier(struct mlx5e_priv *priv)
70{
71 struct mlx5_core_dev *mdev = priv->mdev;
72 u8 port_state;
73
74 port_state = mlx5_query_vport_state(mdev,
e7546514 75 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8
AV		 76
77 if (port_state == VPORT_STATE_UP)
78 netif_carrier_on(priv->netdev);
79 else
80 netif_carrier_off(priv->netdev);
81}
82
83static void mlx5e_update_carrier_work(struct work_struct *work)
84{
85 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
86 update_carrier_work);
87
88 mutex_lock(&priv->state_lock);
89 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
90 mlx5e_update_carrier(priv);
91 mutex_unlock(&priv->state_lock);
92}
93
9218b44d 94static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 95{
9218b44d 96 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 97 struct mlx5e_rq_stats *rq_stats;
98 struct mlx5e_sq_stats *sq_stats;
9218b44d 99 u64 tx_offload_none = 0;
f62b8bb8
AV		 100 int i, j;
101
9218b44d 102 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 103 for (i = 0; i < priv->params.num_channels; i++) {
104 rq_stats = &priv->channel[i]->rq.stats;
105
faf4478b
GP		 106 s->rx_packets += rq_stats->packets;
107 s->rx_bytes += rq_stats->bytes;
f62b8bb8
AV		 108 s->lro_packets += rq_stats->lro_packets;
109 s->lro_bytes += rq_stats->lro_bytes;
110 s->rx_csum_none += rq_stats->csum_none;
bbceefce 111 s->rx_csum_sw += rq_stats->csum_sw;
1b223dd3 112 s->rx_csum_inner += rq_stats->csum_inner;
f62b8bb8 113 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 114 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
bc77b240 115 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
54984407 116 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
f62b8bb8 117
a4418a6c 118 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 119 sq_stats = &priv->channel[i]->sq[j].stats;
120
faf4478b
GP		 121 s->tx_packets += sq_stats->packets;
122 s->tx_bytes += sq_stats->bytes;
f62b8bb8
AV		 123 s->tso_packets += sq_stats->tso_packets;
124 s->tso_bytes += sq_stats->tso_bytes;
89db09eb
MF		 125 s->tso_inner_packets += sq_stats->tso_inner_packets;
126 s->tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 127 s->tx_queue_stopped += sq_stats->stopped;
128 s->tx_queue_wake += sq_stats->wake;
129 s->tx_queue_dropped += sq_stats->dropped;
89db09eb 130 s->tx_csum_inner += sq_stats->csum_offload_inner;
f62b8bb8
AV		 131 tx_offload_none += sq_stats->csum_offload_none;
132 }
133 }
134
9218b44d
GP		 135 /* Update calculated offload counters */
136 s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
137 s->rx_csum_good = s->rx_packets - s->rx_csum_none -
138 s->rx_csum_sw;
121fcdc8
GP		 139
140 s->link_down_events = MLX5_GET(ppcnt_reg,
141 priv->stats.pport.phy_counters,
142 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 143}
144
145static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
146{
147 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
148 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
149 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
150 struct mlx5_core_dev *mdev = priv->mdev;
151
f62b8bb8
AV		 152 memset(in, 0, sizeof(in));
153
154 MLX5_SET(query_vport_counter_in, in, opcode,
155 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
156 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
157 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
158
159 memset(out, 0, outlen);
160
9218b44d
GP		 161 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
162}
163
164static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
165{
166 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
167 struct mlx5_core_dev *mdev = priv->mdev;
168 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 169 int prio;
9218b44d
GP		 170 void *out;
171 u32 *in;
172
173 in = mlx5_vzalloc(sz);
174 if (!in)
f62b8bb8
AV		 175 goto free_out;
176
9218b44d 177 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 178
9218b44d
GP		 179 out = pstats->IEEE_802_3_counters;
180 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
181 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 182
9218b44d
GP		 183 out = pstats->RFC_2863_counters;
184 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
185 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
186
187 out = pstats->RFC_2819_counters;
188 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
189 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 190
121fcdc8
GP		 191 out = pstats->phy_counters;
192 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
193 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
194
cf678570
GP		 195 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
196 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
197 out = pstats->per_prio_counters[prio];
198 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
199 mlx5_core_access_reg(mdev, in, sz, out, sz,
200 MLX5_REG_PPCNT, 0, 0);
201 }
202
f62b8bb8 203free_out:
9218b44d
GP		 204 kvfree(in);
205}
206
207static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
208{
209 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
210
211 if (!priv->q_counter)
212 return;
213
214 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
215 &qcnt->rx_out_of_buffer);
216}
217
218void mlx5e_update_stats(struct mlx5e_priv *priv)
219{
9218b44d
GP		 220 mlx5e_update_q_counter(priv);
221 mlx5e_update_vport_counters(priv);
222 mlx5e_update_pport_counters(priv);
121fcdc8 223 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 224}
225
226static void mlx5e_update_stats_work(struct work_struct *work)
227{
228 struct delayed_work *dwork = to_delayed_work(work);
229 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
230 update_stats_work);
231 mutex_lock(&priv->state_lock);
232 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
233 mlx5e_update_stats(priv);
234 schedule_delayed_work(dwork,
235 msecs_to_jiffies(
236 MLX5E_UPDATE_STATS_INTERVAL));
237 }
238 mutex_unlock(&priv->state_lock);
239}
240
daa21560
TT		 241static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
242 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 243{
daa21560
TT		 244 struct mlx5e_priv *priv = vpriv;
245
246 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
247 return;
248
f62b8bb8
AV		 249 switch (event) {
250 case MLX5_DEV_EVENT_PORT_UP:
251 case MLX5_DEV_EVENT_PORT_DOWN:
252 schedule_work(&priv->update_carrier_work);
253 break;
254
255 default:
256 break;
257 }
258}
259
f62b8bb8
AV		 260static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
261{
262 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
263}
264
265static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
266{
f62b8bb8 267 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
daa21560 268 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 269}
270
facc9699
SM		 271#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
272#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
273
f62b8bb8
AV		 274static int mlx5e_create_rq(struct mlx5e_channel *c,
275 struct mlx5e_rq_param *param,
276 struct mlx5e_rq *rq)
277{
278 struct mlx5e_priv *priv = c->priv;
279 struct mlx5_core_dev *mdev = priv->mdev;
280 void *rqc = param->rqc;
281 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 282 u32 byte_count;
f62b8bb8
AV		 283 int wq_sz;
284 int err;
285 int i;
286
311c7c71
SM		 287 param->wq.db_numa_node = cpu_to_node(c->cpu);
288
f62b8bb8
AV		 289 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
290 &rq->wq_ctrl);
291 if (err)
292 return err;
293
294 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
295
296 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 297
461017cb
TT		 298 switch (priv->params.rq_wq_type) {
299 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
300 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
301 GFP_KERNEL, cpu_to_node(c->cpu));
302 if (!rq->wqe_info) {
303 err = -ENOMEM;
304 goto err_rq_wq_destroy;
305 }
306 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
307 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
308
309 rq->wqe_sz = MLX5_MPWRQ_NUM_STRIDES * MLX5_MPWRQ_STRIDE_SIZE;
310 byte_count = rq->wqe_sz;
311 break;
312 default: /* MLX5_WQ_TYPE_LINKED_LIST */
313 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
314 cpu_to_node(c->cpu));
315 if (!rq->skb) {
316 err = -ENOMEM;
317 goto err_rq_wq_destroy;
318 }
319 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
320 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
321
322 rq->wqe_sz = (priv->params.lro_en) ?
323 priv->params.lro_wqe_sz :
324 MLX5E_SW2HW_MTU(priv->netdev->mtu);
c5adb96f
TT		 325 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
326 byte_count = rq->wqe_sz;
461017cb
TT		 327 byte_count |= MLX5_HW_START_PADDING;
328 }
f62b8bb8
AV		 329
330 for (i = 0; i < wq_sz; i++) {
331 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
332
461017cb 333 wqe->data.byte_count = cpu_to_be32(byte_count);
f62b8bb8
AV		 334 }
335
461017cb 336 rq->wq_type = priv->params.rq_wq_type;
f62b8bb8
AV		 337 rq->pdev = c->pdev;
338 rq->netdev = c->netdev;
ef9814de 339 rq->tstamp = &priv->tstamp;
f62b8bb8
AV		 340 rq->channel = c;
341 rq->ix = c->ix;
50cfa25a 342 rq->priv = c->priv;
bc77b240
TT		 343 rq->mkey_be = c->mkey_be;
344 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
f62b8bb8
AV		 345
346 return 0;
347
348err_rq_wq_destroy:
349 mlx5_wq_destroy(&rq->wq_ctrl);
350
351 return err;
352}
353
354static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
355{
461017cb
TT		 356 switch (rq->wq_type) {
357 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
358 kfree(rq->wqe_info);
359 break;
360 default: /* MLX5_WQ_TYPE_LINKED_LIST */
361 kfree(rq->skb);
362 }
363
f62b8bb8
AV		 364 mlx5_wq_destroy(&rq->wq_ctrl);
365}
366
367static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
368{
50cfa25a 369 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 370 struct mlx5_core_dev *mdev = priv->mdev;
371
372 void *in;
373 void *rqc;
374 void *wq;
375 int inlen;
376 int err;
377
378 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
379 sizeof(u64) * rq->wq_ctrl.buf.npages;
380 in = mlx5_vzalloc(inlen);
381 if (!in)
382 return -ENOMEM;
383
384 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
385 wq = MLX5_ADDR_OF(rqc, rqc, wq);
386
387 memcpy(rqc, param->rqc, sizeof(param->rqc));
388
97de9f31 389 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8
AV		 390 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
391 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
36350114 392 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
f62b8bb8 393 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 394 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 395 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
396
397 mlx5_fill_page_array(&rq->wq_ctrl.buf,
398 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
399
7db22ffb 400 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 401
402 kvfree(in);
403
404 return err;
405}
406
36350114
GP		 407static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
408 int next_state)
f62b8bb8
AV		 409{
410 struct mlx5e_channel *c = rq->channel;
411 struct mlx5e_priv *priv = c->priv;
412 struct mlx5_core_dev *mdev = priv->mdev;
413
414 void *in;
415 void *rqc;
416 int inlen;
417 int err;
418
419 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
420 in = mlx5_vzalloc(inlen);
421 if (!in)
422 return -ENOMEM;
423
424 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
425
426 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
427 MLX5_SET(rqc, rqc, state, next_state);
428
7db22ffb 429 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 430
431 kvfree(in);
432
433 return err;
434}
435
36350114
GP		 436static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
437{
438 struct mlx5e_channel *c = rq->channel;
439 struct mlx5e_priv *priv = c->priv;
440 struct mlx5_core_dev *mdev = priv->mdev;
441
442 void *in;
443 void *rqc;
444 int inlen;
445 int err;
446
447 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
448 in = mlx5_vzalloc(inlen);
449 if (!in)
450 return -ENOMEM;
451
452 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
453
454 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
455 MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
456 MLX5_SET(rqc, rqc, vsd, vsd);
457 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
458
459 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
460
461 kvfree(in);
462
463 return err;
464}
465
f62b8bb8
AV		 466static void mlx5e_disable_rq(struct mlx5e_rq *rq)
467{
50cfa25a 468 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 469}
470
471static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
472{
01c196a2 473 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 474 struct mlx5e_channel *c = rq->channel;
475 struct mlx5e_priv *priv = c->priv;
476 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 477
01c196a2 478 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 479 if (wq->cur_sz >= priv->params.min_rx_wqes)
480 return 0;
481
482 msleep(20);
483 }
484
485 return -ETIMEDOUT;
486}
487
488static int mlx5e_open_rq(struct mlx5e_channel *c,
489 struct mlx5e_rq_param *param,
490 struct mlx5e_rq *rq)
491{
d3c9bc27
TT		 492 struct mlx5e_sq *sq = &c->icosq;
493 u16 pi = sq->pc & sq->wq.sz_m1;
f62b8bb8
AV		 494 int err;
495
496 err = mlx5e_create_rq(c, param, rq);
497 if (err)
498 return err;
499
500 err = mlx5e_enable_rq(rq, param);
501 if (err)
502 goto err_destroy_rq;
503
36350114 504 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8
AV		 505 if (err)
506 goto err_disable_rq;
507
508 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
d3c9bc27
TT		 509
510 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
511 sq->ico_wqe_info[pi].num_wqebbs = 1;
512 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 513
514 return 0;
515
516err_disable_rq:
517 mlx5e_disable_rq(rq);
518err_destroy_rq:
519 mlx5e_destroy_rq(rq);
520
521 return err;
522}
523
524static void mlx5e_close_rq(struct mlx5e_rq *rq)
525{
526 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
527 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
528
36350114 529 mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
f62b8bb8
AV		 530 while (!mlx5_wq_ll_is_empty(&rq->wq))
531 msleep(20);
532
533 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
534 napi_synchronize(&rq->channel->napi);
535
536 mlx5e_disable_rq(rq);
537 mlx5e_destroy_rq(rq);
538}
539
540static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
541{
34802a42 542 kfree(sq->wqe_info);
f62b8bb8
AV		 543 kfree(sq->dma_fifo);
544 kfree(sq->skb);
545}
546
547static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
548{
549 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
550 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
551
552 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
553 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
554 numa);
34802a42
AS		 555 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
556 numa);
f62b8bb8 557
34802a42 558 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
f62b8bb8
AV		 559 mlx5e_free_sq_db(sq);
560 return -ENOMEM;
561 }
562
563 sq->dma_fifo_mask = df_sz - 1;
564
565 return 0;
566}
567
568static int mlx5e_create_sq(struct mlx5e_channel *c,
569 int tc,
570 struct mlx5e_sq_param *param,
571 struct mlx5e_sq *sq)
572{
573 struct mlx5e_priv *priv = c->priv;
574 struct mlx5_core_dev *mdev = priv->mdev;
575
576 void *sqc = param->sqc;
577 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
578 int err;
579
0ba42241 580 err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
f62b8bb8
AV		 581 if (err)
582 return err;
583
311c7c71
SM		 584 param->wq.db_numa_node = cpu_to_node(c->cpu);
585
f62b8bb8
AV		 586 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
587 &sq->wq_ctrl);
588 if (err)
589 goto err_unmap_free_uar;
590
591 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
0ba42241
ML		 592 if (sq->uar.bf_map) {
593 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
594 sq->uar_map = sq->uar.bf_map;
595 } else {
596 sq->uar_map = sq->uar.map;
597 }
f62b8bb8 598 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 599 sq->max_inline = param->max_inline;
f62b8bb8 600
7ec0bb22
DC		 601 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
602 if (err)
f62b8bb8
AV		 603 goto err_sq_wq_destroy;
604
d3c9bc27
TT		 605 if (param->icosq) {
606 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
607
608 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
609 wq_sz,
610 GFP_KERNEL,
611 cpu_to_node(c->cpu));
612 if (!sq->ico_wqe_info) {
613 err = -ENOMEM;
614 goto err_free_sq_db;
615 }
616 } else {
617 int txq_ix;
618
619 txq_ix = c->ix + tc * priv->params.num_channels;
620 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
621 priv->txq_to_sq_map[txq_ix] = sq;
622 }
f62b8bb8 623
88a85f99 624 sq->pdev = c->pdev;
ef9814de 625 sq->tstamp = &priv->tstamp;
88a85f99
AS		 626 sq->mkey_be = c->mkey_be;
627 sq->channel = c;
628 sq->tc = tc;
629 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
630 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
f62b8bb8
AV		 631
632 return 0;
633
d3c9bc27
TT		 634err_free_sq_db:
635 mlx5e_free_sq_db(sq);
636
f62b8bb8
AV		 637err_sq_wq_destroy:
638 mlx5_wq_destroy(&sq->wq_ctrl);
639
640err_unmap_free_uar:
641 mlx5_unmap_free_uar(mdev, &sq->uar);
642
643 return err;
644}
645
646static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
647{
648 struct mlx5e_channel *c = sq->channel;
649 struct mlx5e_priv *priv = c->priv;
650
d3c9bc27 651 kfree(sq->ico_wqe_info);
f62b8bb8
AV		 652 mlx5e_free_sq_db(sq);
653 mlx5_wq_destroy(&sq->wq_ctrl);
654 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
655}
656
657static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
658{
659 struct mlx5e_channel *c = sq->channel;
660 struct mlx5e_priv *priv = c->priv;
661 struct mlx5_core_dev *mdev = priv->mdev;
662
663 void *in;
664 void *sqc;
665 void *wq;
666 int inlen;
667 int err;
668
669 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
670 sizeof(u64) * sq->wq_ctrl.buf.npages;
671 in = mlx5_vzalloc(inlen);
672 if (!in)
673 return -ENOMEM;
674
675 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
676 wq = MLX5_ADDR_OF(sqc, sqc, wq);
677
678 memcpy(sqc, param->sqc, sizeof(param->sqc));
679
d3c9bc27
TT		 680 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
681 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
f62b8bb8 682 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
d3c9bc27 683 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
f62b8bb8
AV		 684 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
685
686 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
687 MLX5_SET(wq, wq, uar_page, sq->uar.index);
688 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 689 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 690 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
691
692 mlx5_fill_page_array(&sq->wq_ctrl.buf,
693 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
694
7db22ffb 695 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 696
697 kvfree(in);
698
699 return err;
700}
701
702static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
703{
704 struct mlx5e_channel *c = sq->channel;
705 struct mlx5e_priv *priv = c->priv;
706 struct mlx5_core_dev *mdev = priv->mdev;
707
708 void *in;
709 void *sqc;
710 int inlen;
711 int err;
712
713 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
714 in = mlx5_vzalloc(inlen);
715 if (!in)
716 return -ENOMEM;
717
718 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
719
720 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
721 MLX5_SET(sqc, sqc, state, next_state);
722
7db22ffb 723 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 724
725 kvfree(in);
726
727 return err;
728}
729
730static void mlx5e_disable_sq(struct mlx5e_sq *sq)
731{
732 struct mlx5e_channel *c = sq->channel;
733 struct mlx5e_priv *priv = c->priv;
734 struct mlx5_core_dev *mdev = priv->mdev;
735
7db22ffb 736 mlx5_core_destroy_sq(mdev, sq->sqn);
f62b8bb8
AV		 737}
738
739static int mlx5e_open_sq(struct mlx5e_channel *c,
740 int tc,
741 struct mlx5e_sq_param *param,
742 struct mlx5e_sq *sq)
743{
744 int err;
745
746 err = mlx5e_create_sq(c, tc, param, sq);
747 if (err)
748 return err;
749
750 err = mlx5e_enable_sq(sq, param);
751 if (err)
752 goto err_destroy_sq;
753
754 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
755 if (err)
756 goto err_disable_sq;
757
d3c9bc27
TT		 758 if (sq->txq) {
759 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
760 netdev_tx_reset_queue(sq->txq);
761 netif_tx_start_queue(sq->txq);
762 }
f62b8bb8
AV		 763
764 return 0;
765
766err_disable_sq:
767 mlx5e_disable_sq(sq);
768err_destroy_sq:
769 mlx5e_destroy_sq(sq);
770
771 return err;
772}
773
774static inline void netif_tx_disable_queue(struct netdev_queue *txq)
775{
776 __netif_tx_lock_bh(txq);
777 netif_tx_stop_queue(txq);
778 __netif_tx_unlock_bh(txq);
779}
780
781static void mlx5e_close_sq(struct mlx5e_sq *sq)
782{
d3c9bc27
TT		 783 if (sq->txq) {
784 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
785 /* prevent netif_tx_wake_queue */
786 napi_synchronize(&sq->channel->napi);
787 netif_tx_disable_queue(sq->txq);
f62b8bb8 788
d3c9bc27
TT		 789 /* ensure hw is notified of all pending wqes */
790 if (mlx5e_sq_has_room_for(sq, 1))
791 mlx5e_send_nop(sq, true);
792
793 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
794 }
f62b8bb8 795
f62b8bb8
AV		 796 while (sq->cc != sq->pc) /* wait till sq is empty */
797 msleep(20);
798
799 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
800 napi_synchronize(&sq->channel->napi);
801
802 mlx5e_disable_sq(sq);
803 mlx5e_destroy_sq(sq);
804}
805
806static int mlx5e_create_cq(struct mlx5e_channel *c,
807 struct mlx5e_cq_param *param,
808 struct mlx5e_cq *cq)
809{
810 struct mlx5e_priv *priv = c->priv;
811 struct mlx5_core_dev *mdev = priv->mdev;
812 struct mlx5_core_cq *mcq = &cq->mcq;
813 int eqn_not_used;
0b6e26ce 814 unsigned int irqn;
f62b8bb8
AV		 815 int err;
816 u32 i;
817
311c7c71
SM		 818 param->wq.buf_numa_node = cpu_to_node(c->cpu);
819 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 820 param->eq_ix = c->ix;
821
822 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
823 &cq->wq_ctrl);
824 if (err)
825 return err;
826
827 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
828
829 cq->napi = &c->napi;
830
831 mcq->cqe_sz = 64;
832 mcq->set_ci_db = cq->wq_ctrl.db.db;
833 mcq->arm_db = cq->wq_ctrl.db.db + 1;
834 *mcq->set_ci_db = 0;
835 *mcq->arm_db = 0;
836 mcq->vector = param->eq_ix;
837 mcq->comp = mlx5e_completion_event;
838 mcq->event = mlx5e_cq_error_event;
839 mcq->irqn = irqn;
840 mcq->uar = &priv->cq_uar;
841
842 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
843 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
844
845 cqe->op_own = 0xf1;
846 }
847
848 cq->channel = c;
50cfa25a 849 cq->priv = priv;
f62b8bb8
AV		 850
851 return 0;
852}
853
854static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
855{
856 mlx5_wq_destroy(&cq->wq_ctrl);
857}
858
859static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
860{
50cfa25a 861 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 862 struct mlx5_core_dev *mdev = priv->mdev;
863 struct mlx5_core_cq *mcq = &cq->mcq;
864
865 void *in;
866 void *cqc;
867 int inlen;
0b6e26ce 868 unsigned int irqn_not_used;
f62b8bb8
AV		 869 int eqn;
870 int err;
871
872 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
873 sizeof(u64) * cq->wq_ctrl.buf.npages;
874 in = mlx5_vzalloc(inlen);
875 if (!in)
876 return -ENOMEM;
877
878 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
879
880 memcpy(cqc, param->cqc, sizeof(param->cqc));
881
882 mlx5_fill_page_array(&cq->wq_ctrl.buf,
883 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
884
885 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
886
887 MLX5_SET(cqc, cqc, c_eqn, eqn);
888 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
889 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 890 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 891 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
892
893 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
894
895 kvfree(in);
896
897 if (err)
898 return err;
899
900 mlx5e_cq_arm(cq);
901
902 return 0;
903}
904
905static void mlx5e_disable_cq(struct mlx5e_cq *cq)
906{
50cfa25a 907 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 908 struct mlx5_core_dev *mdev = priv->mdev;
909
910 mlx5_core_destroy_cq(mdev, &cq->mcq);
911}
912
913static int mlx5e_open_cq(struct mlx5e_channel *c,
914 struct mlx5e_cq_param *param,
915 struct mlx5e_cq *cq,
916 u16 moderation_usecs,
917 u16 moderation_frames)
918{
919 int err;
920 struct mlx5e_priv *priv = c->priv;
921 struct mlx5_core_dev *mdev = priv->mdev;
922
923 err = mlx5e_create_cq(c, param, cq);
924 if (err)
925 return err;
926
927 err = mlx5e_enable_cq(cq, param);
928 if (err)
929 goto err_destroy_cq;
930
7524a5d8
GP		 931 if (MLX5_CAP_GEN(mdev, cq_moderation))
932 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
933 moderation_usecs,
934 moderation_frames);
f62b8bb8
AV		 935 return 0;
936
937err_destroy_cq:
938 mlx5e_destroy_cq(cq);
939
940 return err;
941}
942
943static void mlx5e_close_cq(struct mlx5e_cq *cq)
944{
945 mlx5e_disable_cq(cq);
946 mlx5e_destroy_cq(cq);
947}
948
949static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
950{
951 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
952}
953
954static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
955 struct mlx5e_channel_param *cparam)
956{
957 struct mlx5e_priv *priv = c->priv;
958 int err;
959 int tc;
960
961 for (tc = 0; tc < c->num_tc; tc++) {
962 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
963 priv->params.tx_cq_moderation_usec,
964 priv->params.tx_cq_moderation_pkts);
965 if (err)
966 goto err_close_tx_cqs;
f62b8bb8
AV		 967 }
968
969 return 0;
970
971err_close_tx_cqs:
972 for (tc--; tc >= 0; tc--)
973 mlx5e_close_cq(&c->sq[tc].cq);
974
975 return err;
976}
977
978static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
979{
980 int tc;
981
982 for (tc = 0; tc < c->num_tc; tc++)
983 mlx5e_close_cq(&c->sq[tc].cq);
984}
985
986static int mlx5e_open_sqs(struct mlx5e_channel *c,
987 struct mlx5e_channel_param *cparam)
988{
989 int err;
990 int tc;
991
992 for (tc = 0; tc < c->num_tc; tc++) {
993 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
994 if (err)
995 goto err_close_sqs;
996 }
997
998 return 0;
999
1000err_close_sqs:
1001 for (tc--; tc >= 0; tc--)
1002 mlx5e_close_sq(&c->sq[tc]);
1003
1004 return err;
1005}
1006
1007static void mlx5e_close_sqs(struct mlx5e_channel *c)
1008{
1009 int tc;
1010
1011 for (tc = 0; tc < c->num_tc; tc++)
1012 mlx5e_close_sq(&c->sq[tc]);
1013}
1014
5283af89 1015static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 1016{
1017 int i;
1018
1019 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
5283af89
RS		 1020 priv->channeltc_to_txq_map[ix][i] =
1021 ix + i * priv->params.num_channels;
03289b88
SM		 1022}
1023
f62b8bb8
AV		 1024static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1025 struct mlx5e_channel_param *cparam,
1026 struct mlx5e_channel **cp)
1027{
1028 struct net_device *netdev = priv->netdev;
1029 int cpu = mlx5e_get_cpu(priv, ix);
1030 struct mlx5e_channel *c;
1031 int err;
1032
1033 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1034 if (!c)
1035 return -ENOMEM;
1036
1037 c->priv = priv;
1038 c->ix = ix;
1039 c->cpu = cpu;
1040 c->pdev = &priv->mdev->pdev->dev;
1041 c->netdev = priv->netdev;
a606b0f6 1042 c->mkey_be = cpu_to_be32(priv->mkey.key);
a4418a6c 1043 c->num_tc = priv->params.num_tc;
f62b8bb8 1044
5283af89 1045 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1046
f62b8bb8
AV		 1047 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1048
d3c9bc27 1049 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
f62b8bb8
AV		 1050 if (err)
1051 goto err_napi_del;
1052
d3c9bc27
TT		 1053 err = mlx5e_open_tx_cqs(c, cparam);
1054 if (err)
1055 goto err_close_icosq_cq;
1056
f62b8bb8
AV		 1057 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1058 priv->params.rx_cq_moderation_usec,
1059 priv->params.rx_cq_moderation_pkts);
1060 if (err)
1061 goto err_close_tx_cqs;
f62b8bb8
AV		 1062
1063 napi_enable(&c->napi);
1064
d3c9bc27 1065 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1066 if (err)
1067 goto err_disable_napi;
1068
d3c9bc27
TT		 1069 err = mlx5e_open_sqs(c, cparam);
1070 if (err)
1071 goto err_close_icosq;
1072
f62b8bb8
AV		 1073 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1074 if (err)
1075 goto err_close_sqs;
1076
1077 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1078 *cp = c;
1079
1080 return 0;
1081
1082err_close_sqs:
1083 mlx5e_close_sqs(c);
1084
d3c9bc27
TT		 1085err_close_icosq:
1086 mlx5e_close_sq(&c->icosq);
1087
f62b8bb8
AV		 1088err_disable_napi:
1089 napi_disable(&c->napi);
1090 mlx5e_close_cq(&c->rq.cq);
1091
1092err_close_tx_cqs:
1093 mlx5e_close_tx_cqs(c);
1094
d3c9bc27
TT		 1095err_close_icosq_cq:
1096 mlx5e_close_cq(&c->icosq.cq);
1097
f62b8bb8
AV		 1098err_napi_del:
1099 netif_napi_del(&c->napi);
7ae92ae5 1100 napi_hash_del(&c->napi);
f62b8bb8
AV		 1101 kfree(c);
1102
1103 return err;
1104}
1105
1106static void mlx5e_close_channel(struct mlx5e_channel *c)
1107{
1108 mlx5e_close_rq(&c->rq);
1109 mlx5e_close_sqs(c);
d3c9bc27 1110 mlx5e_close_sq(&c->icosq);
f62b8bb8
AV		 1111 napi_disable(&c->napi);
1112 mlx5e_close_cq(&c->rq.cq);
1113 mlx5e_close_tx_cqs(c);
d3c9bc27 1114 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1115 netif_napi_del(&c->napi);
7ae92ae5
ED		 1116
1117 napi_hash_del(&c->napi);
1118 synchronize_rcu();
1119
f62b8bb8
AV		 1120 kfree(c);
1121}
1122
1123static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1124 struct mlx5e_rq_param *param)
1125{
1126 void *rqc = param->rqc;
1127 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1128
461017cb
TT		 1129 switch (priv->params.rq_wq_type) {
1130 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1131 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1132 MLX5_MPWRQ_LOG_NUM_STRIDES - 9);
1133 MLX5_SET(wq, wq, log_wqe_stride_size,
1134 MLX5_MPWRQ_LOG_STRIDE_SIZE - 6);
1135 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1136 break;
1137 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1138 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1139 }
1140
f62b8bb8
AV		 1141 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1142 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1143 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1144 MLX5_SET(wq, wq, pd, priv->pdn);
593cf338 1145 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1146
311c7c71 1147 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1148 param->wq.linear = 1;
1149}
1150
556dd1b9
TT		 1151static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1152{
1153 void *rqc = param->rqc;
1154 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1155
1156 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1157 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1158}
1159
d3c9bc27
TT		 1160static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1161 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1162{
1163 void *sqc = param->sqc;
1164 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1165
f62b8bb8
AV		 1166 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1167 MLX5_SET(wq, wq, pd, priv->pdn);
1168
311c7c71 1169 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1170}
1171
1172static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1173 struct mlx5e_sq_param *param)
1174{
1175 void *sqc = param->sqc;
1176 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1177
1178 mlx5e_build_sq_param_common(priv, param);
1179 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1180
58d52291 1181 param->max_inline = priv->params.tx_max_inline;
f62b8bb8
AV		 1182}
1183
1184static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1185 struct mlx5e_cq_param *param)
1186{
1187 void *cqc = param->cqc;
1188
1189 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1190}
1191
1192static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1193 struct mlx5e_cq_param *param)
1194{
1195 void *cqc = param->cqc;
461017cb 1196 u8 log_cq_size;
f62b8bb8 1197
461017cb
TT		 1198 switch (priv->params.rq_wq_type) {
1199 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1200 log_cq_size = priv->params.log_rq_size +
1201 MLX5_MPWRQ_LOG_NUM_STRIDES;
1202 break;
1203 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1204 log_cq_size = priv->params.log_rq_size;
1205 }
1206
1207 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
f62b8bb8
AV		 1208
1209 mlx5e_build_common_cq_param(priv, param);
1210}
1211
1212static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1213 struct mlx5e_cq_param *param)
1214{
1215 void *cqc = param->cqc;
1216
d3c9bc27 1217 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1218
1219 mlx5e_build_common_cq_param(priv, param);
1220}
1221
d3c9bc27
TT		 1222static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1223 struct mlx5e_cq_param *param,
1224 u8 log_wq_size)
1225{
1226 void *cqc = param->cqc;
1227
1228 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1229
1230 mlx5e_build_common_cq_param(priv, param);
1231}
1232
1233static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1234 struct mlx5e_sq_param *param,
1235 u8 log_wq_size)
1236{
1237 void *sqc = param->sqc;
1238 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1239
1240 mlx5e_build_sq_param_common(priv, param);
1241
1242 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1243 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1244
1245 param->icosq = true;
1246}
1247
f62b8bb8
AV		 1248static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1249 struct mlx5e_channel_param *cparam)
1250{
bc77b240 1251 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1252
f62b8bb8
AV		 1253 memset(cparam, 0, sizeof(*cparam));
1254
1255 mlx5e_build_rq_param(priv, &cparam->rq);
1256 mlx5e_build_sq_param(priv, &cparam->sq);
d3c9bc27 1257 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1258 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1259 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1260 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1261}
1262
1263static int mlx5e_open_channels(struct mlx5e_priv *priv)
1264{
1265 struct mlx5e_channel_param cparam;
a4418a6c 1266 int nch = priv->params.num_channels;
03289b88 1267 int err = -ENOMEM;
f62b8bb8
AV		 1268 int i;
1269 int j;
1270
a4418a6c
AS		 1271 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1272 GFP_KERNEL);
03289b88 1273
a4418a6c 1274 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1275 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1276
1277 if (!priv->channel || !priv->txq_to_sq_map)
1278 goto err_free_txq_to_sq_map;
f62b8bb8
AV		 1279
1280 mlx5e_build_channel_param(priv, &cparam);
a4418a6c 1281 for (i = 0; i < nch; i++) {
f62b8bb8
AV		 1282 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1283 if (err)
1284 goto err_close_channels;
1285 }
1286
a4418a6c 1287 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1288 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1289 if (err)
1290 goto err_close_channels;
1291 }
1292
1293 return 0;
1294
1295err_close_channels:
1296 for (i--; i >= 0; i--)
1297 mlx5e_close_channel(priv->channel[i]);
1298
03289b88
SM		 1299err_free_txq_to_sq_map:
1300 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1301 kfree(priv->channel);
1302
1303 return err;
1304}
1305
1306static void mlx5e_close_channels(struct mlx5e_priv *priv)
1307{
1308 int i;
1309
1310 for (i = 0; i < priv->params.num_channels; i++)
1311 mlx5e_close_channel(priv->channel[i]);
1312
03289b88 1313 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1314 kfree(priv->channel);
1315}
1316
2be6967c
SM		 1317static int mlx5e_rx_hash_fn(int hfunc)
1318{
1319 return (hfunc == ETH_RSS_HASH_TOP) ?
1320 MLX5_RX_HASH_FN_TOEPLITZ :
1321 MLX5_RX_HASH_FN_INVERTED_XOR8;
1322}
1323
1324static int mlx5e_bits_invert(unsigned long a, int size)
1325{
1326 int inv = 0;
1327 int i;
1328
1329 for (i = 0; i < size; i++)
1330 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1331
1332 return inv;
1333}
1334
936896e9
AS		 1335static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1336{
1337 int i;
1338
1339 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1340 int ix = i;
1341
1342 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1343 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1344
2d75b2bc 1345 ix = priv->params.indirection_rqt[ix];
936896e9
AS		 1346 MLX5_SET(rqtc, rqtc, rq_num[i],
1347 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1348 priv->channel[ix]->rq.rqn :
1349 priv->drop_rq.rqn);
1350 }
1351}
1352
4cbeaff5
AS		 1353static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1354 enum mlx5e_rqt_ix rqt_ix)
1355{
4cbeaff5
AS		 1356
1357 switch (rqt_ix) {
1358 case MLX5E_INDIRECTION_RQT:
936896e9 1359 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
4cbeaff5
AS		 1360
1361 break;
1362
1363 default: /* MLX5E_SINGLE_RQ_RQT */
1364 MLX5_SET(rqtc, rqtc, rq_num[0],
5c50368f
AS		 1365 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1366 priv->channel[0]->rq.rqn :
1367 priv->drop_rq.rqn);
4cbeaff5
AS		 1368
1369 break;
1370 }
1371}
1372
40ab6a6e 1373static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
f62b8bb8
AV		 1374{
1375 struct mlx5_core_dev *mdev = priv->mdev;
1376 u32 *in;
f62b8bb8
AV		 1377 void *rqtc;
1378 int inlen;
4cbeaff5 1379 int sz;
f62b8bb8 1380 int err;
4cbeaff5 1381
936896e9 1382 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
f62b8bb8 1383
f62b8bb8
AV		 1384 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1385 in = mlx5_vzalloc(inlen);
1386 if (!in)
1387 return -ENOMEM;
1388
1389 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1390
1391 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1392 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1393
4cbeaff5 1394 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
2be6967c 1395
4cbeaff5 1396 err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
f62b8bb8
AV		 1397
1398 kvfree(in);
1399
1400 return err;
1401}
1402
2d75b2bc 1403int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
5c50368f
AS		 1404{
1405 struct mlx5_core_dev *mdev = priv->mdev;
1406 u32 *in;
1407 void *rqtc;
1408 int inlen;
5c50368f
AS		 1409 int sz;
1410 int err;
1411
936896e9 1412 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
5c50368f
AS		 1413
1414 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1415 in = mlx5_vzalloc(inlen);
1416 if (!in)
1417 return -ENOMEM;
1418
1419 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1420
1421 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1422
1423 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1424
1425 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1426
1427 err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1428
1429 kvfree(in);
1430
1431 return err;
1432}
1433
40ab6a6e 1434static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
f62b8bb8 1435{
4cbeaff5 1436 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
f62b8bb8
AV		 1437}
1438
40ab6a6e
AS		 1439static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1440{
1441 mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1442 mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1443}
1444
5c50368f
AS		 1445static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1446{
1447 if (!priv->params.lro_en)
1448 return;
1449
1450#define ROUGH_MAX_L2_L3_HDR_SZ 256
1451
1452 MLX5_SET(tirc, tirc, lro_enable_mask,
1453 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1454 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1455 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1456 (priv->params.lro_wqe_sz -
1457 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1458 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1459 MLX5_CAP_ETH(priv->mdev,
d9a40271 1460 lro_timer_supported_periods[2]));
5c50368f
AS		 1461}
1462
bdfc028d
TT		 1463void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1464{
1465 MLX5_SET(tirc, tirc, rx_hash_fn,
1466 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1467 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1468 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1469 rx_hash_toeplitz_key);
1470 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1471 rx_hash_toeplitz_key);
1472
1473 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1474 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1475 }
1476}
1477
ab0394fe 1478static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 1479{
1480 struct mlx5_core_dev *mdev = priv->mdev;
1481
1482 void *in;
1483 void *tirc;
1484 int inlen;
1485 int err;
ab0394fe 1486 int tt;
5c50368f
AS		 1487
1488 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1489 in = mlx5_vzalloc(inlen);
1490 if (!in)
1491 return -ENOMEM;
1492
1493 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1494 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1495
1496 mlx5e_build_tir_ctx_lro(tirc, priv);
1497
ab0394fe
TT		 1498 for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1499 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1500 if (err)
1501 break;
1502 }
5c50368f
AS		 1503
1504 kvfree(in);
1505
1506 return err;
1507}
1508
66189961
TT		 1509static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1510 u32 tirn)
1511{
1512 void *in;
1513 int inlen;
1514 int err;
1515
1516 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1517 in = mlx5_vzalloc(inlen);
1518 if (!in)
1519 return -ENOMEM;
1520
1521 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1522
1523 err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1524
1525 kvfree(in);
1526
1527 return err;
1528}
1529
1530static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1531{
1532 int err;
1533 int i;
1534
1535 for (i = 0; i < MLX5E_NUM_TT; i++) {
1536 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1537 priv->tirn[i]);
1538 if (err)
1539 return err;
1540 }
1541
1542 return 0;
1543}
1544
cd255eff 1545static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 1546{
40ab6a6e 1547 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 1548 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 1549 int err;
1550
cd255eff 1551 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 1552 if (err)
1553 return err;
1554
cd255eff
SM		 1555 /* Update vport context MTU */
1556 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1557 return 0;
1558}
40ab6a6e 1559
cd255eff
SM		 1560static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1561{
1562 struct mlx5_core_dev *mdev = priv->mdev;
1563 u16 hw_mtu = 0;
1564 int err;
40ab6a6e 1565
cd255eff
SM		 1566 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1567 if (err || !hw_mtu) /* fallback to port oper mtu */
1568 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1569
1570 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1571}
1572
1573static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1574{
1575 struct mlx5e_priv *priv = netdev_priv(netdev);
1576 u16 mtu;
1577 int err;
1578
1579 err = mlx5e_set_mtu(priv, netdev->mtu);
1580 if (err)
1581 return err;
40ab6a6e 1582
cd255eff
SM		 1583 mlx5e_query_mtu(priv, &mtu);
1584 if (mtu != netdev->mtu)
1585 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1586 __func__, mtu, netdev->mtu);
40ab6a6e 1587
cd255eff 1588 netdev->mtu = mtu;
40ab6a6e
AS		 1589 return 0;
1590}
1591
08fb1dac
SM		 1592static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1593{
1594 struct mlx5e_priv *priv = netdev_priv(netdev);
1595 int nch = priv->params.num_channels;
1596 int ntc = priv->params.num_tc;
1597 int tc;
1598
1599 netdev_reset_tc(netdev);
1600
1601 if (ntc == 1)
1602 return;
1603
1604 netdev_set_num_tc(netdev, ntc);
1605
1606 for (tc = 0; tc < ntc; tc++)
1607 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1608}
1609
40ab6a6e
AS		 1610int mlx5e_open_locked(struct net_device *netdev)
1611{
1612 struct mlx5e_priv *priv = netdev_priv(netdev);
1613 int num_txqs;
1614 int err;
1615
1616 set_bit(MLX5E_STATE_OPENED, &priv->state);
1617
08fb1dac
SM		 1618 mlx5e_netdev_set_tcs(netdev);
1619
40ab6a6e
AS		 1620 num_txqs = priv->params.num_channels * priv->params.num_tc;
1621 netif_set_real_num_tx_queues(netdev, num_txqs);
1622 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1623
1624 err = mlx5e_set_dev_port_mtu(netdev);
1625 if (err)
343b29f3 1626 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1627
1628 err = mlx5e_open_channels(priv);
1629 if (err) {
1630 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1631 __func__, err);
343b29f3 1632 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1633 }
1634
66189961
TT		 1635 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1636 if (err) {
1637 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1638 __func__, err);
1639 goto err_close_channels;
1640 }
1641
40ab6a6e 1642 mlx5e_redirect_rqts(priv);
ce89ef36 1643 mlx5e_update_carrier(priv);
ef9814de 1644 mlx5e_timestamp_init(priv);
40ab6a6e
AS		 1645
1646 schedule_delayed_work(&priv->update_stats_work, 0);
40ab6a6e 1647
9b37b07f 1648 return 0;
343b29f3 1649
66189961
TT		 1650err_close_channels:
1651 mlx5e_close_channels(priv);
343b29f3
AS		 1652err_clear_state_opened_flag:
1653 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1654 return err;
40ab6a6e
AS		 1655}
1656
1657static int mlx5e_open(struct net_device *netdev)
1658{
1659 struct mlx5e_priv *priv = netdev_priv(netdev);
1660 int err;
1661
1662 mutex_lock(&priv->state_lock);
1663 err = mlx5e_open_locked(netdev);
1664 mutex_unlock(&priv->state_lock);
1665
1666 return err;
1667}
1668
1669int mlx5e_close_locked(struct net_device *netdev)
1670{
1671 struct mlx5e_priv *priv = netdev_priv(netdev);
1672
a1985740
AS		 1673 /* May already be CLOSED in case a previous configuration operation
1674 * (e.g RX/TX queue size change) that involves close&open failed.
1675 */
1676 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1677 return 0;
1678
40ab6a6e
AS		 1679 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1680
ef9814de 1681 mlx5e_timestamp_cleanup(priv);
40ab6a6e 1682 netif_carrier_off(priv->netdev);
ce89ef36 1683 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 1684 mlx5e_close_channels(priv);
1685
1686 return 0;
1687}
1688
1689static int mlx5e_close(struct net_device *netdev)
1690{
1691 struct mlx5e_priv *priv = netdev_priv(netdev);
1692 int err;
1693
1694 mutex_lock(&priv->state_lock);
1695 err = mlx5e_close_locked(netdev);
1696 mutex_unlock(&priv->state_lock);
1697
1698 return err;
1699}
1700
1701static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1702 struct mlx5e_rq *rq,
1703 struct mlx5e_rq_param *param)
1704{
1705 struct mlx5_core_dev *mdev = priv->mdev;
1706 void *rqc = param->rqc;
1707 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1708 int err;
1709
1710 param->wq.db_numa_node = param->wq.buf_numa_node;
1711
1712 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1713 &rq->wq_ctrl);
1714 if (err)
1715 return err;
1716
1717 rq->priv = priv;
1718
1719 return 0;
1720}
1721
1722static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1723 struct mlx5e_cq *cq,
1724 struct mlx5e_cq_param *param)
1725{
1726 struct mlx5_core_dev *mdev = priv->mdev;
1727 struct mlx5_core_cq *mcq = &cq->mcq;
1728 int eqn_not_used;
0b6e26ce 1729 unsigned int irqn;
40ab6a6e
AS		 1730 int err;
1731
1732 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1733 &cq->wq_ctrl);
1734 if (err)
1735 return err;
1736
1737 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1738
1739 mcq->cqe_sz = 64;
1740 mcq->set_ci_db = cq->wq_ctrl.db.db;
1741 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1742 *mcq->set_ci_db = 0;
1743 *mcq->arm_db = 0;
1744 mcq->vector = param->eq_ix;
1745 mcq->comp = mlx5e_completion_event;
1746 mcq->event = mlx5e_cq_error_event;
1747 mcq->irqn = irqn;
1748 mcq->uar = &priv->cq_uar;
1749
1750 cq->priv = priv;
1751
1752 return 0;
1753}
1754
1755static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1756{
1757 struct mlx5e_cq_param cq_param;
1758 struct mlx5e_rq_param rq_param;
1759 struct mlx5e_rq *rq = &priv->drop_rq;
1760 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1761 int err;
1762
1763 memset(&cq_param, 0, sizeof(cq_param));
1764 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 1765 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 1766
1767 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1768 if (err)
1769 return err;
1770
1771 err = mlx5e_enable_cq(cq, &cq_param);
1772 if (err)
1773 goto err_destroy_cq;
1774
1775 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1776 if (err)
1777 goto err_disable_cq;
1778
1779 err = mlx5e_enable_rq(rq, &rq_param);
1780 if (err)
1781 goto err_destroy_rq;
1782
1783 return 0;
1784
1785err_destroy_rq:
1786 mlx5e_destroy_rq(&priv->drop_rq);
1787
1788err_disable_cq:
1789 mlx5e_disable_cq(&priv->drop_rq.cq);
1790
1791err_destroy_cq:
1792 mlx5e_destroy_cq(&priv->drop_rq.cq);
1793
1794 return err;
1795}
1796
1797static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1798{
1799 mlx5e_disable_rq(&priv->drop_rq);
1800 mlx5e_destroy_rq(&priv->drop_rq);
1801 mlx5e_disable_cq(&priv->drop_rq.cq);
1802 mlx5e_destroy_cq(&priv->drop_rq.cq);
1803}
1804
1805static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1806{
1807 struct mlx5_core_dev *mdev = priv->mdev;
1808 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1809 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1810
1811 memset(in, 0, sizeof(in));
1812
08fb1dac 1813 MLX5_SET(tisc, tisc, prio, tc << 1);
40ab6a6e
AS		 1814 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1815
1816 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1817}
1818
1819static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1820{
1821 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1822}
1823
1824static int mlx5e_create_tises(struct mlx5e_priv *priv)
1825{
1826 int err;
1827 int tc;
1828
08fb1dac 1829 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
40ab6a6e
AS		 1830 err = mlx5e_create_tis(priv, tc);
1831 if (err)
1832 goto err_close_tises;
1833 }
1834
1835 return 0;
1836
1837err_close_tises:
1838 for (tc--; tc >= 0; tc--)
1839 mlx5e_destroy_tis(priv, tc);
1840
1841 return err;
1842}
1843
1844static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1845{
1846 int tc;
1847
08fb1dac 1848 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
40ab6a6e
AS		 1849 mlx5e_destroy_tis(priv, tc);
1850}
1851
f62b8bb8
AV		 1852static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1853{
1854 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1855
3191e05f
AS		 1856 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1857
5a6f8aef
AS		 1858#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1859 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 1860
5a6f8aef
AS		 1861#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1862 MLX5_HASH_FIELD_SEL_DST_IP |\
1863 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1864 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 1865
a741749f
AS		 1866#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1867 MLX5_HASH_FIELD_SEL_DST_IP |\
1868 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1869
5c50368f 1870 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 1871
4cbeaff5
AS		 1872 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1873
f62b8bb8
AV		 1874 switch (tt) {
1875 case MLX5E_TT_ANY:
4cbeaff5
AS		 1876 MLX5_SET(tirc, tirc, indirect_table,
1877 priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1878 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
f62b8bb8
AV		 1879 break;
1880 default:
f62b8bb8 1881 MLX5_SET(tirc, tirc, indirect_table,
4cbeaff5 1882 priv->rqtn[MLX5E_INDIRECTION_RQT]);
bdfc028d 1883 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 1884 break;
1885 }
1886
1887 switch (tt) {
1888 case MLX5E_TT_IPV4_TCP:
1889 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1890 MLX5_L3_PROT_TYPE_IPV4);
1891 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1892 MLX5_L4_PROT_TYPE_TCP);
1893 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1894 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1895 break;
1896
1897 case MLX5E_TT_IPV6_TCP:
1898 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1899 MLX5_L3_PROT_TYPE_IPV6);
1900 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1901 MLX5_L4_PROT_TYPE_TCP);
1902 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1903 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1904 break;
1905
1906 case MLX5E_TT_IPV4_UDP:
1907 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1908 MLX5_L3_PROT_TYPE_IPV4);
1909 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1910 MLX5_L4_PROT_TYPE_UDP);
1911 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1912 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1913 break;
1914
1915 case MLX5E_TT_IPV6_UDP:
1916 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1917 MLX5_L3_PROT_TYPE_IPV6);
1918 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1919 MLX5_L4_PROT_TYPE_UDP);
1920 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1921 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1922 break;
1923
a741749f
AS		 1924 case MLX5E_TT_IPV4_IPSEC_AH:
1925 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1926 MLX5_L3_PROT_TYPE_IPV4);
1927 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1928 MLX5_HASH_IP_IPSEC_SPI);
1929 break;
1930
1931 case MLX5E_TT_IPV6_IPSEC_AH:
1932 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1933 MLX5_L3_PROT_TYPE_IPV6);
1934 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1935 MLX5_HASH_IP_IPSEC_SPI);
1936 break;
1937
1938 case MLX5E_TT_IPV4_IPSEC_ESP:
1939 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1940 MLX5_L3_PROT_TYPE_IPV4);
1941 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1942 MLX5_HASH_IP_IPSEC_SPI);
1943 break;
1944
1945 case MLX5E_TT_IPV6_IPSEC_ESP:
1946 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1947 MLX5_L3_PROT_TYPE_IPV6);
1948 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1949 MLX5_HASH_IP_IPSEC_SPI);
1950 break;
1951
f62b8bb8
AV		 1952 case MLX5E_TT_IPV4:
1953 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1954 MLX5_L3_PROT_TYPE_IPV4);
1955 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1956 MLX5_HASH_IP);
1957 break;
1958
1959 case MLX5E_TT_IPV6:
1960 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1961 MLX5_L3_PROT_TYPE_IPV6);
1962 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1963 MLX5_HASH_IP);
1964 break;
1965 }
1966}
1967
40ab6a6e 1968static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
f62b8bb8
AV		 1969{
1970 struct mlx5_core_dev *mdev = priv->mdev;
1971 u32 *in;
1972 void *tirc;
1973 int inlen;
1974 int err;
1975
1976 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1977 in = mlx5_vzalloc(inlen);
1978 if (!in)
1979 return -ENOMEM;
1980
1981 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1982
1983 mlx5e_build_tir_ctx(priv, tirc, tt);
1984
7db22ffb 1985 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
f62b8bb8
AV		 1986
1987 kvfree(in);
1988
1989 return err;
1990}
1991
40ab6a6e 1992static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
f62b8bb8 1993{
7db22ffb 1994 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
f62b8bb8
AV		 1995}
1996
40ab6a6e 1997static int mlx5e_create_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 1998{
1999 int err;
2000 int i;
2001
2002 for (i = 0; i < MLX5E_NUM_TT; i++) {
40ab6a6e 2003 err = mlx5e_create_tir(priv, i);
f62b8bb8 2004 if (err)
40ab6a6e 2005 goto err_destroy_tirs;
f62b8bb8
AV		 2006 }
2007
2008 return 0;
2009
40ab6a6e 2010err_destroy_tirs:
f62b8bb8 2011 for (i--; i >= 0; i--)
40ab6a6e 2012 mlx5e_destroy_tir(priv, i);
f62b8bb8
AV		 2013
2014 return err;
2015}
2016
40ab6a6e 2017static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2018{
2019 int i;
2020
2021 for (i = 0; i < MLX5E_NUM_TT; i++)
40ab6a6e 2022 mlx5e_destroy_tir(priv, i);
f62b8bb8
AV		 2023}
2024
36350114
GP		 2025int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2026{
2027 int err = 0;
2028 int i;
2029
2030 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2031 return 0;
2032
2033 for (i = 0; i < priv->params.num_channels; i++) {
2034 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2035 if (err)
2036 return err;
2037 }
2038
2039 return 0;
2040}
2041
08fb1dac
SM		 2042static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2043{
2044 struct mlx5e_priv *priv = netdev_priv(netdev);
2045 bool was_opened;
2046 int err = 0;
2047
2048 if (tc && tc != MLX5E_MAX_NUM_TC)
2049 return -EINVAL;
2050
2051 mutex_lock(&priv->state_lock);
2052
2053 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2054 if (was_opened)
2055 mlx5e_close_locked(priv->netdev);
2056
2057 priv->params.num_tc = tc ? tc : 1;
2058
2059 if (was_opened)
2060 err = mlx5e_open_locked(priv->netdev);
2061
2062 mutex_unlock(&priv->state_lock);
2063
2064 return err;
2065}
2066
2067static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2068 __be16 proto, struct tc_to_netdev *tc)
2069{
e8f887ac
AV		 2070 struct mlx5e_priv *priv = netdev_priv(dev);
2071
2072 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2073 goto mqprio;
2074
2075 switch (tc->type) {
e3a2b7ed
AV		 2076 case TC_SETUP_CLSFLOWER:
2077 switch (tc->cls_flower->command) {
2078 case TC_CLSFLOWER_REPLACE:
2079 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2080 case TC_CLSFLOWER_DESTROY:
2081 return mlx5e_delete_flower(priv, tc->cls_flower);
2082 }
e8f887ac
AV		 2083 default:
2084 return -EOPNOTSUPP;
2085 }
2086
2087mqprio:
67ba422e 2088 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2089 return -EINVAL;
2090
2091 return mlx5e_setup_tc(dev, tc->tc);
2092}
2093
f62b8bb8
AV		 2094static struct rtnl_link_stats64 *
2095mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2096{
2097 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2098 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2099 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2100 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2101
9218b44d
GP		 2102 stats->rx_packets = sstats->rx_packets;
2103 stats->rx_bytes = sstats->rx_bytes;
2104 stats->tx_packets = sstats->tx_packets;
2105 stats->tx_bytes = sstats->tx_bytes;
269e6b3a
GP		 2106
2107 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
9218b44d 2108 stats->tx_dropped = sstats->tx_queue_dropped;
269e6b3a
GP		 2109
2110 stats->rx_length_errors =
9218b44d
GP		 2111 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2112 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2113 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2114 stats->rx_crc_errors =
9218b44d
GP		 2115 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2116 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2117 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2118 stats->tx_carrier_errors =
9218b44d 2119 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2120 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2121 stats->rx_frame_errors;
2122 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2123
2124 /* vport multicast also counts packets that are dropped due to steering
2125 * or rx out of buffer
2126 */
9218b44d
GP		 2127 stats->multicast =
2128 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 2129
2130 return stats;
2131}
2132
2133static void mlx5e_set_rx_mode(struct net_device *dev)
2134{
2135 struct mlx5e_priv *priv = netdev_priv(dev);
2136
2137 schedule_work(&priv->set_rx_mode_work);
2138}
2139
2140static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2141{
2142 struct mlx5e_priv *priv = netdev_priv(netdev);
2143 struct sockaddr *saddr = addr;
2144
2145 if (!is_valid_ether_addr(saddr->sa_data))
2146 return -EADDRNOTAVAIL;
2147
2148 netif_addr_lock_bh(netdev);
2149 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2150 netif_addr_unlock_bh(netdev);
2151
2152 schedule_work(&priv->set_rx_mode_work);
2153
2154 return 0;
2155}
2156
0e405443
GP		 2157#define MLX5E_SET_FEATURE(netdev, feature, enable) \
2158 do { \
2159 if (enable) \
2160 netdev->features |= feature; \
2161 else \
2162 netdev->features &= ~feature; \
2163 } while (0)
2164
2165typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2166
2167static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 2168{
2169 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 2170 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2171 int err;
f62b8bb8
AV		 2172
2173 mutex_lock(&priv->state_lock);
f62b8bb8 2174
0e405443
GP		 2175 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2176 mlx5e_close_locked(priv->netdev);
98e81b0a 2177
0e405443
GP		 2178 priv->params.lro_en = enable;
2179 err = mlx5e_modify_tirs_lro(priv);
2180 if (err) {
2181 netdev_err(netdev, "lro modify failed, %d\n", err);
2182 priv->params.lro_en = !enable;
98e81b0a 2183 }
f62b8bb8 2184
0e405443
GP		 2185 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2186 mlx5e_open_locked(priv->netdev);
2187
9b37b07f
AS		 2188 mutex_unlock(&priv->state_lock);
2189
0e405443
GP		 2190 return err;
2191}
2192
2193static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2194{
2195 struct mlx5e_priv *priv = netdev_priv(netdev);
2196
2197 if (enable)
2198 mlx5e_enable_vlan_filter(priv);
2199 else
2200 mlx5e_disable_vlan_filter(priv);
2201
2202 return 0;
2203}
2204
2205static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2206{
2207 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 2208
0e405443 2209 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 2210 netdev_err(netdev,
2211 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2212 return -EINVAL;
2213 }
2214
0e405443
GP		 2215 return 0;
2216}
2217
94cb1ebb
EBE		 2218static int set_feature_rx_all(struct net_device *netdev, bool enable)
2219{
2220 struct mlx5e_priv *priv = netdev_priv(netdev);
2221 struct mlx5_core_dev *mdev = priv->mdev;
2222
2223 return mlx5_set_port_fcs(mdev, !enable);
2224}
2225
36350114
GP		 2226static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2227{
2228 struct mlx5e_priv *priv = netdev_priv(netdev);
2229 int err;
2230
2231 mutex_lock(&priv->state_lock);
2232
2233 priv->params.vlan_strip_disable = !enable;
2234 err = mlx5e_modify_rqs_vsd(priv, !enable);
2235 if (err)
2236 priv->params.vlan_strip_disable = enable;
2237
2238 mutex_unlock(&priv->state_lock);
2239
2240 return err;
2241}
2242
0e405443
GP		 2243static int mlx5e_handle_feature(struct net_device *netdev,
2244 netdev_features_t wanted_features,
2245 netdev_features_t feature,
2246 mlx5e_feature_handler feature_handler)
2247{
2248 netdev_features_t changes = wanted_features ^ netdev->features;
2249 bool enable = !!(wanted_features & feature);
2250 int err;
2251
2252 if (!(changes & feature))
2253 return 0;
2254
2255 err = feature_handler(netdev, enable);
2256 if (err) {
2257 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2258 enable ? "Enable" : "Disable", feature, err);
2259 return err;
2260 }
2261
2262 MLX5E_SET_FEATURE(netdev, feature, enable);
2263 return 0;
2264}
2265
2266static int mlx5e_set_features(struct net_device *netdev,
2267 netdev_features_t features)
2268{
2269 int err;
2270
2271 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2272 set_feature_lro);
2273 err |= mlx5e_handle_feature(netdev, features,
2274 NETIF_F_HW_VLAN_CTAG_FILTER,
2275 set_feature_vlan_filter);
2276 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2277 set_feature_tc_num_filters);
94cb1ebb
EBE		 2278 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2279 set_feature_rx_all);
36350114
GP		 2280 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2281 set_feature_rx_vlan);
0e405443
GP		 2282
2283 return err ? -EINVAL : 0;
f62b8bb8
AV		 2284}
2285
d8edd246
SM		 2286#define MXL5_HW_MIN_MTU 64
2287#define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2288
f62b8bb8
AV		 2289static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2290{
2291 struct mlx5e_priv *priv = netdev_priv(netdev);
2292 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 2293 bool was_opened;
046339ea 2294 u16 max_mtu;
d8edd246 2295 u16 min_mtu;
98e81b0a 2296 int err = 0;
f62b8bb8 2297
facc9699 2298 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 2299
50a9eea6 2300 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
d8edd246 2301 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
50a9eea6 2302
d8edd246 2303 if (new_mtu > max_mtu || new_mtu < min_mtu) {
facc9699 2304 netdev_err(netdev,
d8edd246
SM		 2305 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2306 __func__, new_mtu, min_mtu, max_mtu);
f62b8bb8
AV		 2307 return -EINVAL;
2308 }
2309
2310 mutex_lock(&priv->state_lock);
98e81b0a
AS		 2311
2312 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2313 if (was_opened)
2314 mlx5e_close_locked(netdev);
2315
f62b8bb8 2316 netdev->mtu = new_mtu;
98e81b0a
AS		 2317
2318 if (was_opened)
2319 err = mlx5e_open_locked(netdev);
2320
f62b8bb8
AV		 2321 mutex_unlock(&priv->state_lock);
2322
2323 return err;
2324}
2325
ef9814de
EBE		 2326static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2327{
2328 switch (cmd) {
2329 case SIOCSHWTSTAMP:
2330 return mlx5e_hwstamp_set(dev, ifr);
2331 case SIOCGHWTSTAMP:
2332 return mlx5e_hwstamp_get(dev, ifr);
2333 default:
2334 return -EOPNOTSUPP;
2335 }
2336}
2337
66e49ded
SM		 2338static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2339{
2340 struct mlx5e_priv *priv = netdev_priv(dev);
2341 struct mlx5_core_dev *mdev = priv->mdev;
2342
2343 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2344}
2345
2346static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2347{
2348 struct mlx5e_priv *priv = netdev_priv(dev);
2349 struct mlx5_core_dev *mdev = priv->mdev;
2350
2351 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2352 vlan, qos);
2353}
2354
2355static int mlx5_vport_link2ifla(u8 esw_link)
2356{
2357 switch (esw_link) {
2358 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2359 return IFLA_VF_LINK_STATE_DISABLE;
2360 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2361 return IFLA_VF_LINK_STATE_ENABLE;
2362 }
2363 return IFLA_VF_LINK_STATE_AUTO;
2364}
2365
2366static int mlx5_ifla_link2vport(u8 ifla_link)
2367{
2368 switch (ifla_link) {
2369 case IFLA_VF_LINK_STATE_DISABLE:
2370 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2371 case IFLA_VF_LINK_STATE_ENABLE:
2372 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2373 }
2374 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2375}
2376
2377static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2378 int link_state)
2379{
2380 struct mlx5e_priv *priv = netdev_priv(dev);
2381 struct mlx5_core_dev *mdev = priv->mdev;
2382
2383 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2384 mlx5_ifla_link2vport(link_state));
2385}
2386
2387static int mlx5e_get_vf_config(struct net_device *dev,
2388 int vf, struct ifla_vf_info *ivi)
2389{
2390 struct mlx5e_priv *priv = netdev_priv(dev);
2391 struct mlx5_core_dev *mdev = priv->mdev;
2392 int err;
2393
2394 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2395 if (err)
2396 return err;
2397 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2398 return 0;
2399}
2400
2401static int mlx5e_get_vf_stats(struct net_device *dev,
2402 int vf, struct ifla_vf_stats *vf_stats)
2403{
2404 struct mlx5e_priv *priv = netdev_priv(dev);
2405 struct mlx5_core_dev *mdev = priv->mdev;
2406
2407 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2408 vf_stats);
2409}
2410
b3f63c3d
MF		 2411static void mlx5e_add_vxlan_port(struct net_device *netdev,
2412 sa_family_t sa_family, __be16 port)
2413{
2414 struct mlx5e_priv *priv = netdev_priv(netdev);
2415
2416 if (!mlx5e_vxlan_allowed(priv->mdev))
2417 return;
2418
2419 mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2420}
2421
2422static void mlx5e_del_vxlan_port(struct net_device *netdev,
2423 sa_family_t sa_family, __be16 port)
2424{
2425 struct mlx5e_priv *priv = netdev_priv(netdev);
2426
2427 if (!mlx5e_vxlan_allowed(priv->mdev))
2428 return;
2429
2430 mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2431}
2432
2433static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2434 struct sk_buff *skb,
2435 netdev_features_t features)
2436{
2437 struct udphdr *udph;
2438 u16 proto;
2439 u16 port = 0;
2440
2441 switch (vlan_get_protocol(skb)) {
2442 case htons(ETH_P_IP):
2443 proto = ip_hdr(skb)->protocol;
2444 break;
2445 case htons(ETH_P_IPV6):
2446 proto = ipv6_hdr(skb)->nexthdr;
2447 break;
2448 default:
2449 goto out;
2450 }
2451
2452 if (proto == IPPROTO_UDP) {
2453 udph = udp_hdr(skb);
2454 port = be16_to_cpu(udph->dest);
2455 }
2456
2457 /* Verify if UDP port is being offloaded by HW */
2458 if (port && mlx5e_vxlan_lookup_port(priv, port))
2459 return features;
2460
2461out:
2462 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2463 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2464}
2465
2466static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2467 struct net_device *netdev,
2468 netdev_features_t features)
2469{
2470 struct mlx5e_priv *priv = netdev_priv(netdev);
2471
2472 features = vlan_features_check(skb, features);
2473 features = vxlan_features_check(skb, features);
2474
2475 /* Validate if the tunneled packet is being offloaded by HW */
2476 if (skb->encapsulation &&
2477 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2478 return mlx5e_vxlan_features_check(priv, skb, features);
2479
2480 return features;
2481}
2482
b0eed40e 2483static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 2484 .ndo_open = mlx5e_open,
2485 .ndo_stop = mlx5e_close,
2486 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2487 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2488 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 2489 .ndo_get_stats64 = mlx5e_get_stats,
2490 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2491 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 2492 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2493 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 2494 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 2495 .ndo_change_mtu = mlx5e_change_mtu,
2496 .ndo_do_ioctl = mlx5e_ioctl,
2497};
2498
2499static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2500 .ndo_open = mlx5e_open,
2501 .ndo_stop = mlx5e_close,
2502 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2503 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2504 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 2505 .ndo_get_stats64 = mlx5e_get_stats,
2506 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2507 .ndo_set_mac_address = mlx5e_set_mac,
2508 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2509 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2510 .ndo_set_features = mlx5e_set_features,
2511 .ndo_change_mtu = mlx5e_change_mtu,
2512 .ndo_do_ioctl = mlx5e_ioctl,
b3f63c3d
MF		 2513 .ndo_add_vxlan_port = mlx5e_add_vxlan_port,
2514 .ndo_del_vxlan_port = mlx5e_del_vxlan_port,
2515 .ndo_features_check = mlx5e_features_check,
b0eed40e
SM		 2516 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2517 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2518 .ndo_get_vf_config = mlx5e_get_vf_config,
2519 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2520 .ndo_get_vf_stats = mlx5e_get_vf_stats,
f62b8bb8
AV		 2521};
2522
2523static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2524{
2525 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2526 return -ENOTSUPP;
2527 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2528 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2529 !MLX5_CAP_ETH(mdev, csum_cap) ||
2530 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2531 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 2532 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2533 MLX5_CAP_FLOWTABLE(mdev,
2534 flow_table_properties_nic_receive.max_ft_level)
2535 < 3) {
f62b8bb8
AV		 2536 mlx5_core_warn(mdev,
2537 "Not creating net device, some required device capabilities are missing\n");
2538 return -ENOTSUPP;
2539 }
66189961
TT		 2540 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2541 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 2542 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2543 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 2544
f62b8bb8
AV		 2545 return 0;
2546}
2547
58d52291
AS		 2548u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2549{
2550 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2551
2552 return bf_buf_size -
2553 sizeof(struct mlx5e_tx_wqe) +
2554 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2555}
2556
08fb1dac
SM		 2557#ifdef CONFIG_MLX5_CORE_EN_DCB
2558static void mlx5e_ets_init(struct mlx5e_priv *priv)
2559{
2560 int i;
2561
2562 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2563 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2564 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2565 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2566 priv->params.ets.prio_tc[i] = i;
2567 }
2568
2569 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2570 priv->params.ets.prio_tc[0] = 1;
2571 priv->params.ets.prio_tc[1] = 0;
2572}
2573#endif
2574
d8c9660d
TT		 2575void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2576 u32 *indirection_rqt, int len,
85082dba
TT		 2577 int num_channels)
2578{
d8c9660d
TT		 2579 int node = mdev->priv.numa_node;
2580 int node_num_of_cores;
85082dba
TT		 2581 int i;
2582
d8c9660d
TT		 2583 if (node == -1)
2584 node = first_online_node;
2585
2586 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2587
2588 if (node_num_of_cores)
2589 num_channels = min_t(int, num_channels, node_num_of_cores);
2590
85082dba
TT		 2591 for (i = 0; i < len; i++)
2592 indirection_rqt[i] = i % num_channels;
2593}
2594
bc77b240
TT		 2595static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2596{
2597 return MLX5_CAP_GEN(mdev, striding_rq) &&
2598 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2599 MLX5_CAP_ETH(mdev, reg_umr_sq);
2600}
2601
f62b8bb8
AV		 2602static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2603 struct net_device *netdev,
936896e9 2604 int num_channels)
f62b8bb8
AV		 2605{
2606 struct mlx5e_priv *priv = netdev_priv(netdev);
2607
2608 priv->params.log_sq_size =
2609 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
bc77b240 2610 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
461017cb
TT		 2611 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2612 MLX5_WQ_TYPE_LINKED_LIST;
2613
2614 switch (priv->params.rq_wq_type) {
2615 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2616 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2617 priv->params.lro_en = true;
2618 break;
2619 default: /* MLX5_WQ_TYPE_LINKED_LIST */
2620 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2621 }
2622
2623 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2624 BIT(priv->params.log_rq_size));
f62b8bb8
AV		 2625 priv->params.rx_cq_moderation_usec =
2626 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2627 priv->params.rx_cq_moderation_pkts =
2628 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2629 priv->params.tx_cq_moderation_usec =
2630 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2631 priv->params.tx_cq_moderation_pkts =
2632 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 2633 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
f62b8bb8 2634 priv->params.num_tc = 1;
2be6967c 2635 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 2636
57afead5
AS		 2637 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2638 sizeof(priv->params.toeplitz_hash_key));
2639
d8c9660d 2640 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
85082dba 2641 MLX5E_INDIR_RQT_SIZE, num_channels);
2d75b2bc 2642
f62b8bb8
AV		 2643 priv->params.lro_wqe_sz =
2644 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2645
2646 priv->mdev = mdev;
2647 priv->netdev = netdev;
936896e9 2648 priv->params.num_channels = num_channels;
f62b8bb8 2649
08fb1dac
SM		 2650#ifdef CONFIG_MLX5_CORE_EN_DCB
2651 mlx5e_ets_init(priv);
2652#endif
f62b8bb8 2653
f62b8bb8
AV		 2654 mutex_init(&priv->state_lock);
2655
2656 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2657 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2658 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2659}
2660
2661static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2662{
2663 struct mlx5e_priv *priv = netdev_priv(netdev);
2664
e1d7d349 2665 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 2666 if (is_zero_ether_addr(netdev->dev_addr) &&
2667 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2668 eth_hw_addr_random(netdev);
2669 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2670 }
f62b8bb8
AV		 2671}
2672
2673static void mlx5e_build_netdev(struct net_device *netdev)
2674{
2675 struct mlx5e_priv *priv = netdev_priv(netdev);
2676 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 2677 bool fcs_supported;
2678 bool fcs_enabled;
f62b8bb8
AV		 2679
2680 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2681
08fb1dac 2682 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 2683 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac
SM		 2684#ifdef CONFIG_MLX5_CORE_EN_DCB
2685 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2686#endif
2687 } else {
b0eed40e 2688 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 2689 }
66e49ded 2690
f62b8bb8
AV		 2691 netdev->watchdog_timeo = 15 * HZ;
2692
2693 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2694
12be4b21 2695 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 2696 netdev->vlan_features |= NETIF_F_IP_CSUM;
2697 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2698 netdev->vlan_features |= NETIF_F_GRO;
2699 netdev->vlan_features |= NETIF_F_TSO;
2700 netdev->vlan_features |= NETIF_F_TSO6;
2701 netdev->vlan_features |= NETIF_F_RXCSUM;
2702 netdev->vlan_features |= NETIF_F_RXHASH;
2703
2704 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2705 netdev->vlan_features |= NETIF_F_LRO;
2706
2707 netdev->hw_features = netdev->vlan_features;
e4cf27bd 2708 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 2709 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2710 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2711
b3f63c3d
MF		 2712 if (mlx5e_vxlan_allowed(mdev)) {
2713 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2714 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2715 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2716 netdev->hw_enc_features |= NETIF_F_TSO;
2717 netdev->hw_enc_features |= NETIF_F_TSO6;
2718 netdev->hw_enc_features |= NETIF_F_RXHASH;
2719 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2720 }
2721
94cb1ebb
EBE		 2722 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
2723
2724 if (fcs_supported)
2725 netdev->hw_features |= NETIF_F_RXALL;
2726
f62b8bb8
AV		 2727 netdev->features = netdev->hw_features;
2728 if (!priv->params.lro_en)
2729 netdev->features &= ~NETIF_F_LRO;
2730
94cb1ebb
EBE		 2731 if (fcs_enabled)
2732 netdev->features &= ~NETIF_F_RXALL;
2733
e8f887ac
AV		 2734#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2735 if (FT_CAP(flow_modify_en) &&
2736 FT_CAP(modify_root) &&
2737 FT_CAP(identified_miss_table_mode) &&
2738 FT_CAP(flow_table_modify))
2739 priv->netdev->hw_features |= NETIF_F_HW_TC;
2740
f62b8bb8
AV		 2741 netdev->features |= NETIF_F_HIGHDMA;
2742
2743 netdev->priv_flags |= IFF_UNICAST_FLT;
2744
2745 mlx5e_set_netdev_dev_addr(netdev);
2746}
2747
2748static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
a606b0f6 2749 struct mlx5_core_mkey *mkey)
f62b8bb8
AV		 2750{
2751 struct mlx5_core_dev *mdev = priv->mdev;
2752 struct mlx5_create_mkey_mbox_in *in;
2753 int err;
2754
2755 in = mlx5_vzalloc(sizeof(*in));
2756 if (!in)
2757 return -ENOMEM;
2758
2759 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2760 MLX5_PERM_LOCAL_READ |
2761 MLX5_ACCESS_MODE_PA;
2762 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2763 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2764
a606b0f6 2765 err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
f62b8bb8
AV		 2766 NULL);
2767
2768 kvfree(in);
2769
2770 return err;
2771}
2772
593cf338
RS		 2773static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2774{
2775 struct mlx5_core_dev *mdev = priv->mdev;
2776 int err;
2777
2778 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2779 if (err) {
2780 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2781 priv->q_counter = 0;
2782 }
2783}
2784
2785static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2786{
2787 if (!priv->q_counter)
2788 return;
2789
2790 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2791}
2792
bc77b240
TT		 2793static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
2794{
2795 struct mlx5_core_dev *mdev = priv->mdev;
2796 struct mlx5_create_mkey_mbox_in *in;
2797 struct mlx5_mkey_seg *mkc;
2798 int inlen = sizeof(*in);
2799 u64 npages =
2800 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
2801 int err;
2802
2803 in = mlx5_vzalloc(inlen);
2804 if (!in)
2805 return -ENOMEM;
2806
2807 mkc = &in->seg;
2808 mkc->status = MLX5_MKEY_STATUS_FREE;
2809 mkc->flags = MLX5_PERM_UMR_EN |
2810 MLX5_PERM_LOCAL_READ |
2811 MLX5_PERM_LOCAL_WRITE |
2812 MLX5_ACCESS_MODE_MTT;
2813
2814 mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2815 mkc->flags_pd = cpu_to_be32(priv->pdn);
2816 mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
2817 mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
2818 mkc->log2_page_size = PAGE_SHIFT;
2819
2820 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
2821 NULL, NULL);
2822
2823 kvfree(in);
2824
2825 return err;
2826}
2827
f62b8bb8
AV		 2828static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2829{
2830 struct net_device *netdev;
2831 struct mlx5e_priv *priv;
3435ab59 2832 int nch = mlx5e_get_max_num_channels(mdev);
f62b8bb8
AV		 2833 int err;
2834
2835 if (mlx5e_check_required_hca_cap(mdev))
2836 return NULL;
2837
08fb1dac
SM		 2838 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2839 nch * MLX5E_MAX_NUM_TC,
2840 nch);
f62b8bb8
AV		 2841 if (!netdev) {
2842 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2843 return NULL;
2844 }
2845
936896e9 2846 mlx5e_build_netdev_priv(mdev, netdev, nch);
f62b8bb8
AV		 2847 mlx5e_build_netdev(netdev);
2848
2849 netif_carrier_off(netdev);
2850
2851 priv = netdev_priv(netdev);
2852
0ba42241 2853 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
f62b8bb8 2854 if (err) {
1f2a3003 2855 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
f62b8bb8
AV		 2856 goto err_free_netdev;
2857 }
2858
2859 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2860 if (err) {
1f2a3003 2861 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
f62b8bb8
AV		 2862 goto err_unmap_free_uar;
2863 }
2864
8d7f9ecb 2865 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3191e05f 2866 if (err) {
1f2a3003 2867 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3191e05f
AS		 2868 goto err_dealloc_pd;
2869 }
2870
a606b0f6 2871 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
f62b8bb8 2872 if (err) {
1f2a3003 2873 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3191e05f 2874 goto err_dealloc_transport_domain;
f62b8bb8
AV		 2875 }
2876
bc77b240
TT		 2877 err = mlx5e_create_umr_mkey(priv);
2878 if (err) {
2879 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
2880 goto err_destroy_mkey;
2881 }
2882
40ab6a6e 2883 err = mlx5e_create_tises(priv);
5c50368f 2884 if (err) {
40ab6a6e 2885 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
bc77b240 2886 goto err_destroy_umr_mkey;
5c50368f
AS		 2887 }
2888
2889 err = mlx5e_open_drop_rq(priv);
2890 if (err) {
2891 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
40ab6a6e 2892 goto err_destroy_tises;
5c50368f
AS		 2893 }
2894
40ab6a6e 2895 err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f 2896 if (err) {
40ab6a6e 2897 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
5c50368f
AS		 2898 goto err_close_drop_rq;
2899 }
2900
40ab6a6e 2901 err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
5c50368f 2902 if (err) {
40ab6a6e
AS		 2903 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2904 goto err_destroy_rqt_indir;
5c50368f
AS		 2905 }
2906
40ab6a6e 2907 err = mlx5e_create_tirs(priv);
5c50368f 2908 if (err) {
40ab6a6e
AS		 2909 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2910 goto err_destroy_rqt_single;
5c50368f
AS		 2911 }
2912
40ab6a6e 2913 err = mlx5e_create_flow_tables(priv);
5c50368f 2914 if (err) {
40ab6a6e
AS		 2915 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2916 goto err_destroy_tirs;
5c50368f
AS		 2917 }
2918
593cf338
RS		 2919 mlx5e_create_q_counter(priv);
2920
5c50368f
AS		 2921 mlx5e_init_eth_addr(priv);
2922
b3f63c3d
MF		 2923 mlx5e_vxlan_init(priv);
2924
e8f887ac
AV		 2925 err = mlx5e_tc_init(priv);
2926 if (err)
593cf338 2927 goto err_dealloc_q_counters;
e8f887ac 2928
08fb1dac
SM		 2929#ifdef CONFIG_MLX5_CORE_EN_DCB
2930 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2931#endif
2932
f62b8bb8
AV		 2933 err = register_netdev(netdev);
2934 if (err) {
1f2a3003 2935 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
e8f887ac 2936 goto err_tc_cleanup;
f62b8bb8
AV		 2937 }
2938
b3f63c3d
MF		 2939 if (mlx5e_vxlan_allowed(mdev))
2940 vxlan_get_rx_port(netdev);
2941
f62b8bb8 2942 mlx5e_enable_async_events(priv);
9b37b07f 2943 schedule_work(&priv->set_rx_mode_work);
f62b8bb8
AV		 2944
2945 return priv;
2946
e8f887ac
AV		 2947err_tc_cleanup:
2948 mlx5e_tc_cleanup(priv);
2949
593cf338
RS		 2950err_dealloc_q_counters:
2951 mlx5e_destroy_q_counter(priv);
40ab6a6e 2952 mlx5e_destroy_flow_tables(priv);
5c50368f 2953
40ab6a6e
AS		 2954err_destroy_tirs:
2955 mlx5e_destroy_tirs(priv);
5c50368f 2956
40ab6a6e
AS		 2957err_destroy_rqt_single:
2958 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
5c50368f 2959
40ab6a6e
AS		 2960err_destroy_rqt_indir:
2961 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f
AS		 2962
2963err_close_drop_rq:
2964 mlx5e_close_drop_rq(priv);
2965
40ab6a6e
AS		 2966err_destroy_tises:
2967 mlx5e_destroy_tises(priv);
5c50368f 2968
bc77b240
TT		 2969err_destroy_umr_mkey:
2970 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
2971
f62b8bb8 2972err_destroy_mkey:
a606b0f6 2973 mlx5_core_destroy_mkey(mdev, &priv->mkey);
f62b8bb8 2974
3191e05f 2975err_dealloc_transport_domain:
8d7f9ecb 2976 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3191e05f 2977
f62b8bb8
AV		 2978err_dealloc_pd:
2979 mlx5_core_dealloc_pd(mdev, priv->pdn);
2980
2981err_unmap_free_uar:
2982 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2983
2984err_free_netdev:
2985 free_netdev(netdev);
2986
2987 return NULL;
2988}
2989
2990static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2991{
2992 struct mlx5e_priv *priv = vpriv;
2993 struct net_device *netdev = priv->netdev;
2994
9b37b07f
AS		 2995 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2996
2997 schedule_work(&priv->set_rx_mode_work);
1cefa326
AS		 2998 mlx5e_disable_async_events(priv);
2999 flush_scheduled_work();
5fc7197d
MD		 3000 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3001 netif_device_detach(netdev);
3002 mutex_lock(&priv->state_lock);
3003 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
3004 mlx5e_close_locked(netdev);
3005 mutex_unlock(&priv->state_lock);
3006 } else {
3007 unregister_netdev(netdev);
3008 }
3009
e8f887ac 3010 mlx5e_tc_cleanup(priv);
b3f63c3d 3011 mlx5e_vxlan_cleanup(priv);
593cf338 3012 mlx5e_destroy_q_counter(priv);
40ab6a6e
AS		 3013 mlx5e_destroy_flow_tables(priv);
3014 mlx5e_destroy_tirs(priv);
3015 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
3016 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f 3017 mlx5e_close_drop_rq(priv);
40ab6a6e 3018 mlx5e_destroy_tises(priv);
bc77b240 3019 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
a606b0f6 3020 mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
8d7f9ecb 3021 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
f62b8bb8
AV		 3022 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3023 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
5fc7197d
MD		 3024
3025 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3026 free_netdev(netdev);
f62b8bb8
AV		 3027}
3028
3029static void *mlx5e_get_netdev(void *vpriv)
3030{
3031 struct mlx5e_priv *priv = vpriv;
3032
3033 return priv->netdev;
3034}
3035
3036static struct mlx5_interface mlx5e_interface = {
3037 .add = mlx5e_create_netdev,
3038 .remove = mlx5e_destroy_netdev,
3039 .event = mlx5e_async_event,
3040 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3041 .get_dev = mlx5e_get_netdev,
3042};
3043
3044void mlx5e_init(void)
3045{
3046 mlx5_register_interface(&mlx5e_interface);
3047}
3048
3049void mlx5e_cleanup(void)
3050{
3051 mlx5_unregister_interface(&mlx5e_interface);
3052}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git