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f62b8bb8 | 1 | /* |
b3f63c3d | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
e8f887ac AV |
33 | #include <net/tc_act/tc_gact.h> |
34 | #include <net/pkt_cls.h> | |
86d722ad | 35 | #include <linux/mlx5/fs.h> |
b3f63c3d | 36 | #include <net/vxlan.h> |
86994156 | 37 | #include <linux/bpf.h> |
60bbf7ee | 38 | #include <net/page_pool.h> |
1d447a39 | 39 | #include "eswitch.h" |
f62b8bb8 | 40 | #include "en.h" |
e8f887ac | 41 | #include "en_tc.h" |
1d447a39 | 42 | #include "en_rep.h" |
547eede0 | 43 | #include "en_accel/ipsec.h" |
899a59d3 | 44 | #include "en_accel/ipsec_rxtx.h" |
c83294b9 | 45 | #include "en_accel/tls.h" |
899a59d3 | 46 | #include "accel/ipsec.h" |
c83294b9 | 47 | #include "accel/tls.h" |
b3f63c3d | 48 | #include "vxlan.h" |
2c81bfd5 | 49 | #include "en/port.h" |
f62b8bb8 AV |
50 | |
51 | struct mlx5e_rq_param { | |
cb3c7fd4 GR |
52 | u32 rqc[MLX5_ST_SZ_DW(rqc)]; |
53 | struct mlx5_wq_param wq; | |
f62b8bb8 AV |
54 | }; |
55 | ||
56 | struct mlx5e_sq_param { | |
57 | u32 sqc[MLX5_ST_SZ_DW(sqc)]; | |
58 | struct mlx5_wq_param wq; | |
59 | }; | |
60 | ||
61 | struct mlx5e_cq_param { | |
62 | u32 cqc[MLX5_ST_SZ_DW(cqc)]; | |
63 | struct mlx5_wq_param wq; | |
64 | u16 eq_ix; | |
9908aa29 | 65 | u8 cq_period_mode; |
f62b8bb8 AV |
66 | }; |
67 | ||
68 | struct mlx5e_channel_param { | |
69 | struct mlx5e_rq_param rq; | |
70 | struct mlx5e_sq_param sq; | |
b5503b99 | 71 | struct mlx5e_sq_param xdp_sq; |
d3c9bc27 | 72 | struct mlx5e_sq_param icosq; |
f62b8bb8 AV |
73 | struct mlx5e_cq_param rx_cq; |
74 | struct mlx5e_cq_param tx_cq; | |
d3c9bc27 | 75 | struct mlx5e_cq_param icosq_cq; |
f62b8bb8 AV |
76 | }; |
77 | ||
2ccb0a79 | 78 | bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev) |
2fc4bfb7 | 79 | { |
ea3886ca | 80 | bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && |
2fc4bfb7 SM |
81 | MLX5_CAP_GEN(mdev, umr_ptr_rlky) && |
82 | MLX5_CAP_ETH(mdev, reg_umr_sq); | |
ea3886ca TT |
83 | u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq); |
84 | bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap; | |
85 | ||
86 | if (!striding_rq_umr) | |
87 | return false; | |
88 | if (!inline_umr) { | |
89 | mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n", | |
90 | (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap); | |
91 | return false; | |
92 | } | |
93 | return true; | |
2fc4bfb7 SM |
94 | } |
95 | ||
73281b78 TT |
96 | static u32 mlx5e_mpwqe_get_linear_frag_sz(struct mlx5e_params *params) |
97 | { | |
619a8f2a TT |
98 | if (!params->xdp_prog) { |
99 | u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); | |
100 | u16 rq_headroom = MLX5_RX_HEADROOM + NET_IP_ALIGN; | |
73281b78 | 101 | |
619a8f2a TT |
102 | return MLX5_SKB_FRAG_SZ(rq_headroom + hw_mtu); |
103 | } | |
104 | ||
105 | return PAGE_SIZE; | |
73281b78 TT |
106 | } |
107 | ||
108 | static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params) | |
109 | { | |
110 | u32 linear_frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params); | |
111 | ||
112 | return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz); | |
113 | } | |
114 | ||
619a8f2a TT |
115 | static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev, |
116 | struct mlx5e_params *params) | |
117 | { | |
118 | u32 frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params); | |
119 | s8 signed_log_num_strides_param; | |
120 | u8 log_num_strides; | |
121 | ||
122 | if (params->lro_en || frag_sz > PAGE_SIZE) | |
123 | return false; | |
124 | ||
125 | if (MLX5_CAP_GEN(mdev, ext_stride_num_range)) | |
126 | return true; | |
127 | ||
128 | log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz); | |
129 | signed_log_num_strides_param = | |
130 | (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE; | |
131 | ||
132 | return signed_log_num_strides_param >= 0; | |
133 | } | |
134 | ||
73281b78 TT |
135 | static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params) |
136 | { | |
137 | if (params->log_rq_mtu_frames < | |
138 | mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW) | |
139 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
140 | ||
141 | return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params); | |
142 | } | |
143 | ||
144 | static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev, | |
145 | struct mlx5e_params *params) | |
f1e4fc9b | 146 | { |
619a8f2a TT |
147 | if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params)) |
148 | return order_base_2(mlx5e_mpwqe_get_linear_frag_sz(params)); | |
149 | ||
f1e4fc9b TT |
150 | return MLX5E_MPWQE_STRIDE_SZ(mdev, |
151 | MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)); | |
152 | } | |
153 | ||
73281b78 TT |
154 | static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev, |
155 | struct mlx5e_params *params) | |
f1e4fc9b TT |
156 | { |
157 | return MLX5_MPWRQ_LOG_WQE_SZ - | |
158 | mlx5e_mpwqe_get_log_stride_size(mdev, params); | |
159 | } | |
160 | ||
619a8f2a TT |
161 | static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev, |
162 | struct mlx5e_params *params) | |
b0cedc84 TT |
163 | { |
164 | u16 linear_rq_headroom = params->xdp_prog ? | |
165 | XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM; | |
166 | ||
167 | linear_rq_headroom += NET_IP_ALIGN; | |
168 | ||
169 | if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST) | |
170 | return linear_rq_headroom; | |
171 | ||
619a8f2a TT |
172 | if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params)) |
173 | return linear_rq_headroom; | |
174 | ||
b0cedc84 TT |
175 | return 0; |
176 | } | |
177 | ||
696a97cf | 178 | void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, |
2a0f561b | 179 | struct mlx5e_params *params) |
2fc4bfb7 | 180 | { |
6a9764ef | 181 | params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; |
73281b78 TT |
182 | params->log_rq_mtu_frames = is_kdump_kernel() ? |
183 | MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE : | |
184 | MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; | |
2fc4bfb7 | 185 | |
6a9764ef SM |
186 | mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n", |
187 | params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ, | |
619a8f2a TT |
188 | params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ? |
189 | BIT(mlx5e_mpwqe_get_log_rq_size(params)) : | |
73281b78 | 190 | BIT(params->log_rq_mtu_frames), |
f1e4fc9b | 191 | BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)), |
6a9764ef | 192 | MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)); |
2fc4bfb7 SM |
193 | } |
194 | ||
2ccb0a79 TT |
195 | bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev, |
196 | struct mlx5e_params *params) | |
197 | { | |
198 | return mlx5e_check_fragmented_striding_rq_cap(mdev) && | |
22f45398 TT |
199 | !MLX5_IPSEC_DEV(mdev) && |
200 | !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params)); | |
2ccb0a79 | 201 | } |
291f445e | 202 | |
2ccb0a79 | 203 | void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params) |
2fc4bfb7 | 204 | { |
2ccb0a79 TT |
205 | params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) && |
206 | MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ? | |
291f445e TT |
207 | MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ : |
208 | MLX5_WQ_TYPE_LINKED_LIST; | |
2fc4bfb7 SM |
209 | } |
210 | ||
f62b8bb8 AV |
211 | static void mlx5e_update_carrier(struct mlx5e_priv *priv) |
212 | { | |
213 | struct mlx5_core_dev *mdev = priv->mdev; | |
214 | u8 port_state; | |
215 | ||
216 | port_state = mlx5_query_vport_state(mdev, | |
e53eef63 OG |
217 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, |
218 | 0); | |
f62b8bb8 | 219 | |
87424ad5 SD |
220 | if (port_state == VPORT_STATE_UP) { |
221 | netdev_info(priv->netdev, "Link up\n"); | |
f62b8bb8 | 222 | netif_carrier_on(priv->netdev); |
87424ad5 SD |
223 | } else { |
224 | netdev_info(priv->netdev, "Link down\n"); | |
f62b8bb8 | 225 | netif_carrier_off(priv->netdev); |
87424ad5 | 226 | } |
f62b8bb8 AV |
227 | } |
228 | ||
229 | static void mlx5e_update_carrier_work(struct work_struct *work) | |
230 | { | |
231 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, | |
232 | update_carrier_work); | |
233 | ||
234 | mutex_lock(&priv->state_lock); | |
235 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
7ca42c80 ES |
236 | if (priv->profile->update_carrier) |
237 | priv->profile->update_carrier(priv); | |
f62b8bb8 AV |
238 | mutex_unlock(&priv->state_lock); |
239 | } | |
240 | ||
19386177 | 241 | void mlx5e_update_stats(struct mlx5e_priv *priv) |
f62b8bb8 | 242 | { |
19386177 | 243 | int i; |
f62b8bb8 | 244 | |
19386177 KH |
245 | for (i = mlx5e_num_stats_grps - 1; i >= 0; i--) |
246 | if (mlx5e_stats_grps[i].update_stats) | |
247 | mlx5e_stats_grps[i].update_stats(priv); | |
f62b8bb8 AV |
248 | } |
249 | ||
3834a5e6 GP |
250 | static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv) |
251 | { | |
19386177 KH |
252 | int i; |
253 | ||
254 | for (i = mlx5e_num_stats_grps - 1; i >= 0; i--) | |
255 | if (mlx5e_stats_grps[i].update_stats_mask & | |
256 | MLX5E_NDO_UPDATE_STATS) | |
257 | mlx5e_stats_grps[i].update_stats(priv); | |
3834a5e6 GP |
258 | } |
259 | ||
cb67b832 | 260 | void mlx5e_update_stats_work(struct work_struct *work) |
f62b8bb8 AV |
261 | { |
262 | struct delayed_work *dwork = to_delayed_work(work); | |
263 | struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv, | |
264 | update_stats_work); | |
265 | mutex_lock(&priv->state_lock); | |
266 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
6bfd390b | 267 | priv->profile->update_stats(priv); |
7bb29755 MF |
268 | queue_delayed_work(priv->wq, dwork, |
269 | msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL)); | |
f62b8bb8 AV |
270 | } |
271 | mutex_unlock(&priv->state_lock); | |
272 | } | |
273 | ||
daa21560 TT |
274 | static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, |
275 | enum mlx5_dev_event event, unsigned long param) | |
f62b8bb8 | 276 | { |
daa21560 TT |
277 | struct mlx5e_priv *priv = vpriv; |
278 | ||
e0f46eb9 | 279 | if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state)) |
daa21560 TT |
280 | return; |
281 | ||
f62b8bb8 AV |
282 | switch (event) { |
283 | case MLX5_DEV_EVENT_PORT_UP: | |
284 | case MLX5_DEV_EVENT_PORT_DOWN: | |
7bb29755 | 285 | queue_work(priv->wq, &priv->update_carrier_work); |
f62b8bb8 | 286 | break; |
f62b8bb8 AV |
287 | default: |
288 | break; | |
289 | } | |
290 | } | |
291 | ||
f62b8bb8 AV |
292 | static void mlx5e_enable_async_events(struct mlx5e_priv *priv) |
293 | { | |
e0f46eb9 | 294 | set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state); |
f62b8bb8 AV |
295 | } |
296 | ||
297 | static void mlx5e_disable_async_events(struct mlx5e_priv *priv) | |
298 | { | |
e0f46eb9 | 299 | clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state); |
78249c42 | 300 | synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC)); |
f62b8bb8 AV |
301 | } |
302 | ||
31391048 SM |
303 | static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, |
304 | struct mlx5e_icosq *sq, | |
b8a98a4c | 305 | struct mlx5e_umr_wqe *wqe) |
7e426671 TT |
306 | { |
307 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
308 | struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl; | |
ea3886ca | 309 | u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS); |
7e426671 TT |
310 | |
311 | cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) | | |
312 | ds_cnt); | |
313 | cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; | |
314 | cseg->imm = rq->mkey_be; | |
315 | ||
ea3886ca | 316 | ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE; |
31616255 | 317 | ucseg->xlt_octowords = |
7e426671 | 318 | cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE)); |
7e426671 | 319 | ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); |
7e426671 TT |
320 | } |
321 | ||
422d4c40 TT |
322 | static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq) |
323 | { | |
324 | switch (rq->wq_type) { | |
325 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
326 | return mlx5_wq_ll_get_size(&rq->mpwqe.wq); | |
327 | default: | |
328 | return mlx5_wq_ll_get_size(&rq->wqe.wq); | |
329 | } | |
330 | } | |
331 | ||
332 | static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq) | |
333 | { | |
334 | switch (rq->wq_type) { | |
335 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
336 | return rq->mpwqe.wq.cur_sz; | |
337 | default: | |
338 | return rq->wqe.wq.cur_sz; | |
339 | } | |
340 | } | |
341 | ||
7e426671 TT |
342 | static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, |
343 | struct mlx5e_channel *c) | |
344 | { | |
422d4c40 | 345 | int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq); |
7e426671 | 346 | |
21c59685 | 347 | rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info), |
231243c8 | 348 | GFP_KERNEL, cpu_to_node(c->cpu)); |
21c59685 | 349 | if (!rq->mpwqe.info) |
ea3886ca | 350 | return -ENOMEM; |
7e426671 | 351 | |
b8a98a4c | 352 | mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe); |
7e426671 TT |
353 | |
354 | return 0; | |
7e426671 TT |
355 | } |
356 | ||
a43b25da | 357 | static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev, |
ec8b9981 TT |
358 | u64 npages, u8 page_shift, |
359 | struct mlx5_core_mkey *umr_mkey) | |
3608ae77 | 360 | { |
3608ae77 TT |
361 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
362 | void *mkc; | |
363 | u32 *in; | |
364 | int err; | |
365 | ||
1b9a07ee | 366 | in = kvzalloc(inlen, GFP_KERNEL); |
3608ae77 TT |
367 | if (!in) |
368 | return -ENOMEM; | |
369 | ||
370 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
371 | ||
3608ae77 TT |
372 | MLX5_SET(mkc, mkc, free, 1); |
373 | MLX5_SET(mkc, mkc, umr_en, 1); | |
374 | MLX5_SET(mkc, mkc, lw, 1); | |
375 | MLX5_SET(mkc, mkc, lr, 1); | |
cdbd0d2b | 376 | MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); |
3608ae77 TT |
377 | |
378 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
379 | MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn); | |
ec8b9981 | 380 | MLX5_SET64(mkc, mkc, len, npages << page_shift); |
3608ae77 TT |
381 | MLX5_SET(mkc, mkc, translations_octword_size, |
382 | MLX5_MTT_OCTW(npages)); | |
ec8b9981 | 383 | MLX5_SET(mkc, mkc, log_page_size, page_shift); |
3608ae77 | 384 | |
ec8b9981 | 385 | err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen); |
3608ae77 TT |
386 | |
387 | kvfree(in); | |
388 | return err; | |
389 | } | |
390 | ||
a43b25da | 391 | static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq) |
ec8b9981 | 392 | { |
422d4c40 | 393 | u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq)); |
ec8b9981 | 394 | |
a43b25da | 395 | return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey); |
ec8b9981 TT |
396 | } |
397 | ||
b8a98a4c TT |
398 | static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix) |
399 | { | |
400 | return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT; | |
401 | } | |
402 | ||
3b77235b | 403 | static int mlx5e_alloc_rq(struct mlx5e_channel *c, |
6a9764ef SM |
404 | struct mlx5e_params *params, |
405 | struct mlx5e_rq_param *rqp, | |
3b77235b | 406 | struct mlx5e_rq *rq) |
f62b8bb8 | 407 | { |
60bbf7ee | 408 | struct page_pool_params pp_params = { 0 }; |
a43b25da | 409 | struct mlx5_core_dev *mdev = c->mdev; |
6a9764ef | 410 | void *rqc = rqp->rqc; |
f62b8bb8 | 411 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); |
60bbf7ee | 412 | u32 byte_count, pool_size; |
1bfecfca | 413 | int npages; |
f62b8bb8 AV |
414 | int wq_sz; |
415 | int err; | |
416 | int i; | |
417 | ||
231243c8 | 418 | rqp->wq.db_numa_node = cpu_to_node(c->cpu); |
311c7c71 | 419 | |
6a9764ef | 420 | rq->wq_type = params->rq_wq_type; |
7e426671 TT |
421 | rq->pdev = c->pdev; |
422 | rq->netdev = c->netdev; | |
a43b25da | 423 | rq->tstamp = c->tstamp; |
7c39afb3 | 424 | rq->clock = &mdev->clock; |
7e426671 TT |
425 | rq->channel = c; |
426 | rq->ix = c->ix; | |
a43b25da | 427 | rq->mdev = mdev; |
472a1e44 | 428 | rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); |
05909bab | 429 | rq->stats = &c->priv->channel_stats[c->ix].rq; |
97bc402d | 430 | |
6a9764ef | 431 | rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL; |
97bc402d DB |
432 | if (IS_ERR(rq->xdp_prog)) { |
433 | err = PTR_ERR(rq->xdp_prog); | |
434 | rq->xdp_prog = NULL; | |
435 | goto err_rq_wq_destroy; | |
436 | } | |
7e426671 | 437 | |
e213f5b6 WY |
438 | err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix); |
439 | if (err < 0) | |
0ddf5432 JDB |
440 | goto err_rq_wq_destroy; |
441 | ||
bce2b2bf | 442 | rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; |
619a8f2a | 443 | rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params); |
60bbf7ee | 444 | pool_size = 1 << params->log_rq_mtu_frames; |
b5503b99 | 445 | |
6a9764ef | 446 | switch (rq->wq_type) { |
461017cb | 447 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: |
422d4c40 TT |
448 | err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq, |
449 | &rq->wq_ctrl); | |
450 | if (err) | |
451 | return err; | |
452 | ||
453 | rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR]; | |
454 | ||
455 | wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq); | |
60bbf7ee JDB |
456 | |
457 | pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params); | |
422d4c40 | 458 | |
7cc6d77b | 459 | rq->post_wqes = mlx5e_post_rx_mpwqes; |
6cd392a0 | 460 | rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe; |
461017cb | 461 | |
20fd0c19 | 462 | rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe; |
899a59d3 IT |
463 | #ifdef CONFIG_MLX5_EN_IPSEC |
464 | if (MLX5_IPSEC_DEV(mdev)) { | |
465 | err = -EINVAL; | |
466 | netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n"); | |
467 | goto err_rq_wq_destroy; | |
468 | } | |
469 | #endif | |
20fd0c19 SM |
470 | if (!rq->handle_rx_cqe) { |
471 | err = -EINVAL; | |
472 | netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err); | |
473 | goto err_rq_wq_destroy; | |
474 | } | |
475 | ||
619a8f2a TT |
476 | rq->mpwqe.skb_from_cqe_mpwrq = |
477 | mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ? | |
478 | mlx5e_skb_from_cqe_mpwrq_linear : | |
479 | mlx5e_skb_from_cqe_mpwrq_nonlinear; | |
f1e4fc9b TT |
480 | rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params); |
481 | rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params)); | |
1bfecfca | 482 | |
b681c481 | 483 | byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz; |
ec8b9981 | 484 | |
a43b25da | 485 | err = mlx5e_create_rq_umr_mkey(mdev, rq); |
7e426671 TT |
486 | if (err) |
487 | goto err_rq_wq_destroy; | |
ec8b9981 TT |
488 | rq->mkey_be = cpu_to_be32(rq->umr_mkey.key); |
489 | ||
490 | err = mlx5e_rq_alloc_mpwqe_info(rq, c); | |
491 | if (err) | |
492 | goto err_destroy_umr_mkey; | |
461017cb TT |
493 | break; |
494 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
422d4c40 TT |
495 | err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq, |
496 | &rq->wq_ctrl); | |
497 | if (err) | |
498 | return err; | |
499 | ||
500 | rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR]; | |
501 | ||
502 | wq_sz = mlx5_wq_ll_get_size(&rq->wqe.wq); | |
503 | ||
accd5883 TT |
504 | rq->wqe.frag_info = |
505 | kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info), | |
231243c8 | 506 | GFP_KERNEL, cpu_to_node(c->cpu)); |
accd5883 | 507 | if (!rq->wqe.frag_info) { |
461017cb TT |
508 | err = -ENOMEM; |
509 | goto err_rq_wq_destroy; | |
510 | } | |
7cc6d77b | 511 | rq->post_wqes = mlx5e_post_rx_wqes; |
6cd392a0 | 512 | rq->dealloc_wqe = mlx5e_dealloc_rx_wqe; |
461017cb | 513 | |
899a59d3 IT |
514 | #ifdef CONFIG_MLX5_EN_IPSEC |
515 | if (c->priv->ipsec) | |
516 | rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe; | |
517 | else | |
518 | #endif | |
519 | rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe; | |
20fd0c19 | 520 | if (!rq->handle_rx_cqe) { |
accd5883 | 521 | kfree(rq->wqe.frag_info); |
20fd0c19 SM |
522 | err = -EINVAL; |
523 | netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err); | |
524 | goto err_rq_wq_destroy; | |
525 | } | |
526 | ||
6c3a823e | 527 | byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu); |
899a59d3 IT |
528 | #ifdef CONFIG_MLX5_EN_IPSEC |
529 | if (MLX5_IPSEC_DEV(mdev)) | |
b681c481 | 530 | byte_count += MLX5E_METADATA_ETHER_LEN; |
899a59d3 | 531 | #endif |
6c3a823e | 532 | rq->wqe.page_reuse = !params->xdp_prog; |
1bfecfca SM |
533 | |
534 | /* calc the required page order */ | |
b45d8b50 | 535 | rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count); |
accd5883 | 536 | npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE); |
1bfecfca SM |
537 | rq->buff.page_order = order_base_2(npages); |
538 | ||
461017cb | 539 | byte_count |= MLX5_HW_START_PADDING; |
7e426671 | 540 | rq->mkey_be = c->mkey_be; |
461017cb | 541 | } |
f62b8bb8 | 542 | |
60bbf7ee JDB |
543 | /* Create a page_pool and register it with rxq */ |
544 | pp_params.order = rq->buff.page_order; | |
545 | pp_params.flags = 0; /* No-internal DMA mapping in page_pool */ | |
546 | pp_params.pool_size = pool_size; | |
547 | pp_params.nid = cpu_to_node(c->cpu); | |
548 | pp_params.dev = c->pdev; | |
549 | pp_params.dma_dir = rq->buff.map_dir; | |
550 | ||
551 | /* page_pool can be used even when there is no rq->xdp_prog, | |
552 | * given page_pool does not handle DMA mapping there is no | |
553 | * required state to clear. And page_pool gracefully handle | |
554 | * elevated refcnt. | |
555 | */ | |
556 | rq->page_pool = page_pool_create(&pp_params); | |
557 | if (IS_ERR(rq->page_pool)) { | |
558 | if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) | |
559 | kfree(rq->wqe.frag_info); | |
560 | err = PTR_ERR(rq->page_pool); | |
561 | rq->page_pool = NULL; | |
562 | goto err_rq_wq_destroy; | |
84f5e3fb | 563 | } |
60bbf7ee JDB |
564 | err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq, |
565 | MEM_TYPE_PAGE_POOL, rq->page_pool); | |
566 | if (err) | |
567 | goto err_rq_wq_destroy; | |
84f5e3fb | 568 | |
f62b8bb8 | 569 | for (i = 0; i < wq_sz; i++) { |
4c2af5cc | 570 | if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { |
422d4c40 TT |
571 | struct mlx5e_rx_wqe *wqe = |
572 | mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i); | |
b8a98a4c | 573 | u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i); |
4c2af5cc | 574 | |
619a8f2a | 575 | wqe->data.addr = cpu_to_be64(dma_offset + rq->buff.headroom); |
422d4c40 TT |
576 | wqe->data.byte_count = cpu_to_be32(byte_count); |
577 | wqe->data.lkey = rq->mkey_be; | |
578 | } else { | |
579 | struct mlx5e_rx_wqe *wqe = | |
580 | mlx5_wq_ll_get_wqe(&rq->wqe.wq, i); | |
4c2af5cc | 581 | |
422d4c40 TT |
582 | wqe->data.byte_count = cpu_to_be32(byte_count); |
583 | wqe->data.lkey = rq->mkey_be; | |
584 | } | |
f62b8bb8 AV |
585 | } |
586 | ||
9a317425 AG |
587 | INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work); |
588 | ||
589 | switch (params->rx_cq_moderation.cq_period_mode) { | |
590 | case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: | |
591 | rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; | |
592 | break; | |
593 | case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: | |
594 | default: | |
595 | rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; | |
596 | } | |
597 | ||
4415a031 TT |
598 | rq->page_cache.head = 0; |
599 | rq->page_cache.tail = 0; | |
600 | ||
f62b8bb8 AV |
601 | return 0; |
602 | ||
ec8b9981 TT |
603 | err_destroy_umr_mkey: |
604 | mlx5_core_destroy_mkey(mdev, &rq->umr_mkey); | |
605 | ||
f62b8bb8 | 606 | err_rq_wq_destroy: |
97bc402d DB |
607 | if (rq->xdp_prog) |
608 | bpf_prog_put(rq->xdp_prog); | |
0ddf5432 | 609 | xdp_rxq_info_unreg(&rq->xdp_rxq); |
60bbf7ee JDB |
610 | if (rq->page_pool) |
611 | page_pool_destroy(rq->page_pool); | |
f62b8bb8 AV |
612 | mlx5_wq_destroy(&rq->wq_ctrl); |
613 | ||
614 | return err; | |
615 | } | |
616 | ||
3b77235b | 617 | static void mlx5e_free_rq(struct mlx5e_rq *rq) |
f62b8bb8 | 618 | { |
4415a031 TT |
619 | int i; |
620 | ||
86994156 RS |
621 | if (rq->xdp_prog) |
622 | bpf_prog_put(rq->xdp_prog); | |
623 | ||
0ddf5432 | 624 | xdp_rxq_info_unreg(&rq->xdp_rxq); |
60bbf7ee JDB |
625 | if (rq->page_pool) |
626 | page_pool_destroy(rq->page_pool); | |
0ddf5432 | 627 | |
461017cb TT |
628 | switch (rq->wq_type) { |
629 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
ea3886ca | 630 | kfree(rq->mpwqe.info); |
a43b25da | 631 | mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey); |
461017cb TT |
632 | break; |
633 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
accd5883 | 634 | kfree(rq->wqe.frag_info); |
461017cb TT |
635 | } |
636 | ||
4415a031 TT |
637 | for (i = rq->page_cache.head; i != rq->page_cache.tail; |
638 | i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) { | |
639 | struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i]; | |
640 | ||
641 | mlx5e_page_release(rq, dma_info, false); | |
642 | } | |
f62b8bb8 AV |
643 | mlx5_wq_destroy(&rq->wq_ctrl); |
644 | } | |
645 | ||
6a9764ef SM |
646 | static int mlx5e_create_rq(struct mlx5e_rq *rq, |
647 | struct mlx5e_rq_param *param) | |
f62b8bb8 | 648 | { |
a43b25da | 649 | struct mlx5_core_dev *mdev = rq->mdev; |
f62b8bb8 AV |
650 | |
651 | void *in; | |
652 | void *rqc; | |
653 | void *wq; | |
654 | int inlen; | |
655 | int err; | |
656 | ||
657 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + | |
658 | sizeof(u64) * rq->wq_ctrl.buf.npages; | |
1b9a07ee | 659 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
660 | if (!in) |
661 | return -ENOMEM; | |
662 | ||
663 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); | |
664 | wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
665 | ||
666 | memcpy(rqc, param->rqc, sizeof(param->rqc)); | |
667 | ||
97de9f31 | 668 | MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn); |
f62b8bb8 | 669 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); |
f62b8bb8 | 670 | MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - |
68cdf5d6 | 671 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
672 | MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); |
673 | ||
3a2f7033 TT |
674 | mlx5_fill_page_frag_array(&rq->wq_ctrl.buf, |
675 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
f62b8bb8 | 676 | |
7db22ffb | 677 | err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); |
f62b8bb8 AV |
678 | |
679 | kvfree(in); | |
680 | ||
681 | return err; | |
682 | } | |
683 | ||
36350114 GP |
684 | static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, |
685 | int next_state) | |
f62b8bb8 | 686 | { |
7cbaf9a3 | 687 | struct mlx5_core_dev *mdev = rq->mdev; |
f62b8bb8 AV |
688 | |
689 | void *in; | |
690 | void *rqc; | |
691 | int inlen; | |
692 | int err; | |
693 | ||
694 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 695 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
696 | if (!in) |
697 | return -ENOMEM; | |
698 | ||
699 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
700 | ||
701 | MLX5_SET(modify_rq_in, in, rq_state, curr_state); | |
702 | MLX5_SET(rqc, rqc, state, next_state); | |
703 | ||
7db22ffb | 704 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); |
f62b8bb8 AV |
705 | |
706 | kvfree(in); | |
707 | ||
708 | return err; | |
709 | } | |
710 | ||
102722fc GE |
711 | static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable) |
712 | { | |
713 | struct mlx5e_channel *c = rq->channel; | |
714 | struct mlx5e_priv *priv = c->priv; | |
715 | struct mlx5_core_dev *mdev = priv->mdev; | |
716 | ||
717 | void *in; | |
718 | void *rqc; | |
719 | int inlen; | |
720 | int err; | |
721 | ||
722 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 723 | in = kvzalloc(inlen, GFP_KERNEL); |
102722fc GE |
724 | if (!in) |
725 | return -ENOMEM; | |
726 | ||
727 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
728 | ||
729 | MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); | |
730 | MLX5_SET64(modify_rq_in, in, modify_bitmask, | |
731 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS); | |
732 | MLX5_SET(rqc, rqc, scatter_fcs, enable); | |
733 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); | |
734 | ||
735 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); | |
736 | ||
737 | kvfree(in); | |
738 | ||
739 | return err; | |
740 | } | |
741 | ||
36350114 GP |
742 | static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd) |
743 | { | |
744 | struct mlx5e_channel *c = rq->channel; | |
a43b25da | 745 | struct mlx5_core_dev *mdev = c->mdev; |
36350114 GP |
746 | void *in; |
747 | void *rqc; | |
748 | int inlen; | |
749 | int err; | |
750 | ||
751 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 752 | in = kvzalloc(inlen, GFP_KERNEL); |
36350114 GP |
753 | if (!in) |
754 | return -ENOMEM; | |
755 | ||
756 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
757 | ||
758 | MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); | |
83b502a1 AV |
759 | MLX5_SET64(modify_rq_in, in, modify_bitmask, |
760 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); | |
36350114 GP |
761 | MLX5_SET(rqc, rqc, vsd, vsd); |
762 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); | |
763 | ||
764 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); | |
765 | ||
766 | kvfree(in); | |
767 | ||
768 | return err; | |
769 | } | |
770 | ||
3b77235b | 771 | static void mlx5e_destroy_rq(struct mlx5e_rq *rq) |
f62b8bb8 | 772 | { |
a43b25da | 773 | mlx5_core_destroy_rq(rq->mdev, rq->rqn); |
f62b8bb8 AV |
774 | } |
775 | ||
1e7477ae | 776 | static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time) |
f62b8bb8 | 777 | { |
1e7477ae | 778 | unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time); |
f62b8bb8 | 779 | struct mlx5e_channel *c = rq->channel; |
a43b25da | 780 | |
422d4c40 | 781 | u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq)); |
f62b8bb8 | 782 | |
1e7477ae | 783 | do { |
422d4c40 | 784 | if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes) |
f62b8bb8 AV |
785 | return 0; |
786 | ||
787 | msleep(20); | |
1e7477ae EBE |
788 | } while (time_before(jiffies, exp_time)); |
789 | ||
790 | netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n", | |
422d4c40 | 791 | c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes); |
f62b8bb8 AV |
792 | |
793 | return -ETIMEDOUT; | |
794 | } | |
795 | ||
f2fde18c SM |
796 | static void mlx5e_free_rx_descs(struct mlx5e_rq *rq) |
797 | { | |
f2fde18c SM |
798 | __be16 wqe_ix_be; |
799 | u16 wqe_ix; | |
800 | ||
422d4c40 TT |
801 | if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { |
802 | struct mlx5_wq_ll *wq = &rq->mpwqe.wq; | |
803 | ||
804 | if (rq->mpwqe.umr_in_progress) | |
805 | mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]); | |
806 | ||
807 | while (!mlx5_wq_ll_is_empty(wq)) { | |
808 | struct mlx5e_rx_wqe *wqe; | |
809 | ||
810 | wqe_ix_be = *wq->tail_next; | |
811 | wqe_ix = be16_to_cpu(wqe_ix_be); | |
812 | wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix); | |
813 | rq->dealloc_wqe(rq, wqe_ix); | |
814 | mlx5_wq_ll_pop(wq, wqe_ix_be, | |
815 | &wqe->next.next_wqe_index); | |
816 | } | |
817 | } else { | |
818 | struct mlx5_wq_ll *wq = &rq->wqe.wq; | |
819 | ||
820 | while (!mlx5_wq_ll_is_empty(wq)) { | |
821 | struct mlx5e_rx_wqe *wqe; | |
822 | ||
823 | wqe_ix_be = *wq->tail_next; | |
824 | wqe_ix = be16_to_cpu(wqe_ix_be); | |
825 | wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix); | |
826 | rq->dealloc_wqe(rq, wqe_ix); | |
827 | mlx5_wq_ll_pop(wq, wqe_ix_be, | |
828 | &wqe->next.next_wqe_index); | |
829 | } | |
accd5883 | 830 | |
accd5883 TT |
831 | /* Clean outstanding pages on handled WQEs that decided to do page-reuse, |
832 | * but yet to be re-posted. | |
833 | */ | |
422d4c40 TT |
834 | if (rq->wqe.page_reuse) { |
835 | int wq_sz = mlx5_wq_ll_get_size(wq); | |
accd5883 | 836 | |
422d4c40 TT |
837 | for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++) |
838 | rq->dealloc_wqe(rq, wqe_ix); | |
839 | } | |
accd5883 | 840 | } |
f2fde18c SM |
841 | } |
842 | ||
f62b8bb8 | 843 | static int mlx5e_open_rq(struct mlx5e_channel *c, |
6a9764ef | 844 | struct mlx5e_params *params, |
f62b8bb8 AV |
845 | struct mlx5e_rq_param *param, |
846 | struct mlx5e_rq *rq) | |
847 | { | |
848 | int err; | |
849 | ||
6a9764ef | 850 | err = mlx5e_alloc_rq(c, params, param, rq); |
f62b8bb8 AV |
851 | if (err) |
852 | return err; | |
853 | ||
3b77235b | 854 | err = mlx5e_create_rq(rq, param); |
f62b8bb8 | 855 | if (err) |
3b77235b | 856 | goto err_free_rq; |
f62b8bb8 | 857 | |
36350114 | 858 | err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); |
f62b8bb8 | 859 | if (err) |
3b77235b | 860 | goto err_destroy_rq; |
f62b8bb8 | 861 | |
9a317425 | 862 | if (params->rx_dim_enabled) |
af5a6c93 | 863 | __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state); |
cb3c7fd4 | 864 | |
f62b8bb8 AV |
865 | return 0; |
866 | ||
f62b8bb8 AV |
867 | err_destroy_rq: |
868 | mlx5e_destroy_rq(rq); | |
3b77235b SM |
869 | err_free_rq: |
870 | mlx5e_free_rq(rq); | |
f62b8bb8 AV |
871 | |
872 | return err; | |
873 | } | |
874 | ||
acc6c595 SM |
875 | static void mlx5e_activate_rq(struct mlx5e_rq *rq) |
876 | { | |
877 | struct mlx5e_icosq *sq = &rq->channel->icosq; | |
ddf385e3 | 878 | struct mlx5_wq_cyc *wq = &sq->wq; |
acc6c595 SM |
879 | struct mlx5e_tx_wqe *nopwqe; |
880 | ||
ddf385e3 TT |
881 | u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); |
882 | ||
acc6c595 SM |
883 | set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); |
884 | sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; | |
ddf385e3 TT |
885 | nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc); |
886 | mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl); | |
acc6c595 SM |
887 | } |
888 | ||
889 | static void mlx5e_deactivate_rq(struct mlx5e_rq *rq) | |
f62b8bb8 | 890 | { |
c0f1147d | 891 | clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); |
f62b8bb8 | 892 | napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */ |
acc6c595 | 893 | } |
cb3c7fd4 | 894 | |
acc6c595 SM |
895 | static void mlx5e_close_rq(struct mlx5e_rq *rq) |
896 | { | |
9a317425 | 897 | cancel_work_sync(&rq->dim.work); |
f62b8bb8 | 898 | mlx5e_destroy_rq(rq); |
3b77235b SM |
899 | mlx5e_free_rx_descs(rq); |
900 | mlx5e_free_rq(rq); | |
f62b8bb8 AV |
901 | } |
902 | ||
31391048 | 903 | static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq) |
b5503b99 | 904 | { |
31391048 | 905 | kfree(sq->db.di); |
b5503b99 SM |
906 | } |
907 | ||
31391048 | 908 | static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa) |
b5503b99 SM |
909 | { |
910 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
911 | ||
31391048 | 912 | sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz, |
b5503b99 | 913 | GFP_KERNEL, numa); |
31391048 SM |
914 | if (!sq->db.di) { |
915 | mlx5e_free_xdpsq_db(sq); | |
b5503b99 SM |
916 | return -ENOMEM; |
917 | } | |
918 | ||
919 | return 0; | |
920 | } | |
921 | ||
31391048 | 922 | static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c, |
6a9764ef | 923 | struct mlx5e_params *params, |
31391048 SM |
924 | struct mlx5e_sq_param *param, |
925 | struct mlx5e_xdpsq *sq) | |
926 | { | |
927 | void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); | |
a43b25da | 928 | struct mlx5_core_dev *mdev = c->mdev; |
ddf385e3 | 929 | struct mlx5_wq_cyc *wq = &sq->wq; |
31391048 SM |
930 | int err; |
931 | ||
932 | sq->pdev = c->pdev; | |
933 | sq->mkey_be = c->mkey_be; | |
934 | sq->channel = c; | |
935 | sq->uar_map = mdev->mlx5e_res.bfreg.map; | |
6a9764ef | 936 | sq->min_inline_mode = params->tx_min_inline_mode; |
31391048 | 937 | |
231243c8 | 938 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
ddf385e3 | 939 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); |
31391048 SM |
940 | if (err) |
941 | return err; | |
ddf385e3 | 942 | wq->db = &wq->db[MLX5_SND_DBR]; |
31391048 | 943 | |
231243c8 | 944 | err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu)); |
31391048 SM |
945 | if (err) |
946 | goto err_sq_wq_destroy; | |
947 | ||
948 | return 0; | |
949 | ||
950 | err_sq_wq_destroy: | |
951 | mlx5_wq_destroy(&sq->wq_ctrl); | |
952 | ||
953 | return err; | |
954 | } | |
955 | ||
956 | static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq) | |
957 | { | |
958 | mlx5e_free_xdpsq_db(sq); | |
959 | mlx5_wq_destroy(&sq->wq_ctrl); | |
960 | } | |
961 | ||
962 | static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq) | |
f62b8bb8 | 963 | { |
f10b7cc7 | 964 | kfree(sq->db.ico_wqe); |
f62b8bb8 AV |
965 | } |
966 | ||
31391048 | 967 | static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa) |
f10b7cc7 SM |
968 | { |
969 | u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
970 | ||
971 | sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz, | |
972 | GFP_KERNEL, numa); | |
973 | if (!sq->db.ico_wqe) | |
974 | return -ENOMEM; | |
975 | ||
976 | return 0; | |
977 | } | |
978 | ||
31391048 | 979 | static int mlx5e_alloc_icosq(struct mlx5e_channel *c, |
31391048 SM |
980 | struct mlx5e_sq_param *param, |
981 | struct mlx5e_icosq *sq) | |
f10b7cc7 | 982 | { |
31391048 | 983 | void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); |
a43b25da | 984 | struct mlx5_core_dev *mdev = c->mdev; |
ddf385e3 | 985 | struct mlx5_wq_cyc *wq = &sq->wq; |
31391048 | 986 | int err; |
f10b7cc7 | 987 | |
31391048 SM |
988 | sq->channel = c; |
989 | sq->uar_map = mdev->mlx5e_res.bfreg.map; | |
f62b8bb8 | 990 | |
231243c8 | 991 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
ddf385e3 | 992 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); |
31391048 SM |
993 | if (err) |
994 | return err; | |
ddf385e3 | 995 | wq->db = &wq->db[MLX5_SND_DBR]; |
f62b8bb8 | 996 | |
231243c8 | 997 | err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu)); |
31391048 SM |
998 | if (err) |
999 | goto err_sq_wq_destroy; | |
1000 | ||
f62b8bb8 | 1001 | return 0; |
31391048 SM |
1002 | |
1003 | err_sq_wq_destroy: | |
1004 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1005 | ||
1006 | return err; | |
f62b8bb8 AV |
1007 | } |
1008 | ||
31391048 | 1009 | static void mlx5e_free_icosq(struct mlx5e_icosq *sq) |
f10b7cc7 | 1010 | { |
31391048 SM |
1011 | mlx5e_free_icosq_db(sq); |
1012 | mlx5_wq_destroy(&sq->wq_ctrl); | |
f10b7cc7 SM |
1013 | } |
1014 | ||
31391048 | 1015 | static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq) |
f10b7cc7 | 1016 | { |
31391048 SM |
1017 | kfree(sq->db.wqe_info); |
1018 | kfree(sq->db.dma_fifo); | |
f10b7cc7 SM |
1019 | } |
1020 | ||
31391048 | 1021 | static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa) |
b5503b99 | 1022 | { |
31391048 SM |
1023 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); |
1024 | int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS; | |
1025 | ||
31391048 SM |
1026 | sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo), |
1027 | GFP_KERNEL, numa); | |
1028 | sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info), | |
1029 | GFP_KERNEL, numa); | |
77bdf895 | 1030 | if (!sq->db.dma_fifo || !sq->db.wqe_info) { |
31391048 SM |
1031 | mlx5e_free_txqsq_db(sq); |
1032 | return -ENOMEM; | |
b5503b99 | 1033 | } |
31391048 SM |
1034 | |
1035 | sq->dma_fifo_mask = df_sz - 1; | |
1036 | ||
1037 | return 0; | |
b5503b99 SM |
1038 | } |
1039 | ||
db75373c | 1040 | static void mlx5e_sq_recover(struct work_struct *work); |
31391048 | 1041 | static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, |
acc6c595 | 1042 | int txq_ix, |
6a9764ef | 1043 | struct mlx5e_params *params, |
31391048 | 1044 | struct mlx5e_sq_param *param, |
05909bab EBE |
1045 | struct mlx5e_txqsq *sq, |
1046 | int tc) | |
f62b8bb8 | 1047 | { |
31391048 | 1048 | void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); |
a43b25da | 1049 | struct mlx5_core_dev *mdev = c->mdev; |
ddf385e3 | 1050 | struct mlx5_wq_cyc *wq = &sq->wq; |
f62b8bb8 AV |
1051 | int err; |
1052 | ||
f10b7cc7 | 1053 | sq->pdev = c->pdev; |
a43b25da | 1054 | sq->tstamp = c->tstamp; |
7c39afb3 | 1055 | sq->clock = &mdev->clock; |
f10b7cc7 SM |
1056 | sq->mkey_be = c->mkey_be; |
1057 | sq->channel = c; | |
acc6c595 | 1058 | sq->txq_ix = txq_ix; |
aff26157 | 1059 | sq->uar_map = mdev->mlx5e_res.bfreg.map; |
6a9764ef | 1060 | sq->min_inline_mode = params->tx_min_inline_mode; |
05909bab | 1061 | sq->stats = &c->priv->channel_stats[c->ix].sq[tc]; |
db75373c | 1062 | INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover); |
2ac9cfe7 IT |
1063 | if (MLX5_IPSEC_DEV(c->priv->mdev)) |
1064 | set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state); | |
bf239741 IL |
1065 | if (mlx5_accel_is_tls_device(c->priv->mdev)) |
1066 | set_bit(MLX5E_SQ_STATE_TLS, &sq->state); | |
f10b7cc7 | 1067 | |
231243c8 | 1068 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
ddf385e3 | 1069 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); |
f62b8bb8 | 1070 | if (err) |
aff26157 | 1071 | return err; |
ddf385e3 | 1072 | wq->db = &wq->db[MLX5_SND_DBR]; |
f62b8bb8 | 1073 | |
231243c8 | 1074 | err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu)); |
7ec0bb22 | 1075 | if (err) |
f62b8bb8 AV |
1076 | goto err_sq_wq_destroy; |
1077 | ||
cbce4f44 TG |
1078 | INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work); |
1079 | sq->dim.mode = params->tx_cq_moderation.cq_period_mode; | |
1080 | ||
f62b8bb8 AV |
1081 | return 0; |
1082 | ||
1083 | err_sq_wq_destroy: | |
1084 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1085 | ||
f62b8bb8 AV |
1086 | return err; |
1087 | } | |
1088 | ||
31391048 | 1089 | static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq) |
f62b8bb8 | 1090 | { |
31391048 | 1091 | mlx5e_free_txqsq_db(sq); |
f62b8bb8 | 1092 | mlx5_wq_destroy(&sq->wq_ctrl); |
f62b8bb8 AV |
1093 | } |
1094 | ||
33ad9711 SM |
1095 | struct mlx5e_create_sq_param { |
1096 | struct mlx5_wq_ctrl *wq_ctrl; | |
1097 | u32 cqn; | |
1098 | u32 tisn; | |
1099 | u8 tis_lst_sz; | |
1100 | u8 min_inline_mode; | |
1101 | }; | |
1102 | ||
a43b25da | 1103 | static int mlx5e_create_sq(struct mlx5_core_dev *mdev, |
33ad9711 SM |
1104 | struct mlx5e_sq_param *param, |
1105 | struct mlx5e_create_sq_param *csp, | |
1106 | u32 *sqn) | |
f62b8bb8 | 1107 | { |
f62b8bb8 AV |
1108 | void *in; |
1109 | void *sqc; | |
1110 | void *wq; | |
1111 | int inlen; | |
1112 | int err; | |
1113 | ||
1114 | inlen = MLX5_ST_SZ_BYTES(create_sq_in) + | |
33ad9711 | 1115 | sizeof(u64) * csp->wq_ctrl->buf.npages; |
1b9a07ee | 1116 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
1117 | if (!in) |
1118 | return -ENOMEM; | |
1119 | ||
1120 | sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); | |
1121 | wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1122 | ||
1123 | memcpy(sqc, param->sqc, sizeof(param->sqc)); | |
33ad9711 SM |
1124 | MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz); |
1125 | MLX5_SET(sqc, sqc, tis_num_0, csp->tisn); | |
1126 | MLX5_SET(sqc, sqc, cqn, csp->cqn); | |
a6f402e4 SM |
1127 | |
1128 | if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) | |
33ad9711 | 1129 | MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode); |
a6f402e4 | 1130 | |
33ad9711 | 1131 | MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); |
db75373c | 1132 | MLX5_SET(sqc, sqc, flush_in_error_en, 1); |
f62b8bb8 AV |
1133 | |
1134 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
a43b25da | 1135 | MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index); |
33ad9711 | 1136 | MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift - |
68cdf5d6 | 1137 | MLX5_ADAPTER_PAGE_SHIFT); |
33ad9711 | 1138 | MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma); |
f62b8bb8 | 1139 | |
3a2f7033 TT |
1140 | mlx5_fill_page_frag_array(&csp->wq_ctrl->buf, |
1141 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
f62b8bb8 | 1142 | |
33ad9711 | 1143 | err = mlx5_core_create_sq(mdev, in, inlen, sqn); |
f62b8bb8 AV |
1144 | |
1145 | kvfree(in); | |
1146 | ||
1147 | return err; | |
1148 | } | |
1149 | ||
33ad9711 SM |
1150 | struct mlx5e_modify_sq_param { |
1151 | int curr_state; | |
1152 | int next_state; | |
1153 | bool rl_update; | |
1154 | int rl_index; | |
1155 | }; | |
1156 | ||
a43b25da | 1157 | static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, |
33ad9711 | 1158 | struct mlx5e_modify_sq_param *p) |
f62b8bb8 | 1159 | { |
f62b8bb8 AV |
1160 | void *in; |
1161 | void *sqc; | |
1162 | int inlen; | |
1163 | int err; | |
1164 | ||
1165 | inlen = MLX5_ST_SZ_BYTES(modify_sq_in); | |
1b9a07ee | 1166 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
1167 | if (!in) |
1168 | return -ENOMEM; | |
1169 | ||
1170 | sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); | |
1171 | ||
33ad9711 SM |
1172 | MLX5_SET(modify_sq_in, in, sq_state, p->curr_state); |
1173 | MLX5_SET(sqc, sqc, state, p->next_state); | |
1174 | if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) { | |
507f0c81 | 1175 | MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); |
33ad9711 | 1176 | MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index); |
507f0c81 | 1177 | } |
f62b8bb8 | 1178 | |
33ad9711 | 1179 | err = mlx5_core_modify_sq(mdev, sqn, in, inlen); |
f62b8bb8 AV |
1180 | |
1181 | kvfree(in); | |
1182 | ||
1183 | return err; | |
1184 | } | |
1185 | ||
a43b25da | 1186 | static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn) |
33ad9711 | 1187 | { |
a43b25da | 1188 | mlx5_core_destroy_sq(mdev, sqn); |
f62b8bb8 AV |
1189 | } |
1190 | ||
a43b25da | 1191 | static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, |
31391048 SM |
1192 | struct mlx5e_sq_param *param, |
1193 | struct mlx5e_create_sq_param *csp, | |
1194 | u32 *sqn) | |
f62b8bb8 | 1195 | { |
33ad9711 | 1196 | struct mlx5e_modify_sq_param msp = {0}; |
31391048 SM |
1197 | int err; |
1198 | ||
a43b25da | 1199 | err = mlx5e_create_sq(mdev, param, csp, sqn); |
31391048 SM |
1200 | if (err) |
1201 | return err; | |
1202 | ||
1203 | msp.curr_state = MLX5_SQC_STATE_RST; | |
1204 | msp.next_state = MLX5_SQC_STATE_RDY; | |
a43b25da | 1205 | err = mlx5e_modify_sq(mdev, *sqn, &msp); |
31391048 | 1206 | if (err) |
a43b25da | 1207 | mlx5e_destroy_sq(mdev, *sqn); |
31391048 SM |
1208 | |
1209 | return err; | |
1210 | } | |
1211 | ||
7f859ecf SM |
1212 | static int mlx5e_set_sq_maxrate(struct net_device *dev, |
1213 | struct mlx5e_txqsq *sq, u32 rate); | |
1214 | ||
31391048 | 1215 | static int mlx5e_open_txqsq(struct mlx5e_channel *c, |
a43b25da | 1216 | u32 tisn, |
acc6c595 | 1217 | int txq_ix, |
6a9764ef | 1218 | struct mlx5e_params *params, |
31391048 | 1219 | struct mlx5e_sq_param *param, |
05909bab EBE |
1220 | struct mlx5e_txqsq *sq, |
1221 | int tc) | |
31391048 SM |
1222 | { |
1223 | struct mlx5e_create_sq_param csp = {}; | |
7f859ecf | 1224 | u32 tx_rate; |
f62b8bb8 AV |
1225 | int err; |
1226 | ||
05909bab | 1227 | err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc); |
f62b8bb8 AV |
1228 | if (err) |
1229 | return err; | |
1230 | ||
a43b25da | 1231 | csp.tisn = tisn; |
31391048 | 1232 | csp.tis_lst_sz = 1; |
33ad9711 SM |
1233 | csp.cqn = sq->cq.mcq.cqn; |
1234 | csp.wq_ctrl = &sq->wq_ctrl; | |
1235 | csp.min_inline_mode = sq->min_inline_mode; | |
a43b25da | 1236 | err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn); |
f62b8bb8 | 1237 | if (err) |
31391048 | 1238 | goto err_free_txqsq; |
f62b8bb8 | 1239 | |
a43b25da | 1240 | tx_rate = c->priv->tx_rates[sq->txq_ix]; |
7f859ecf | 1241 | if (tx_rate) |
a43b25da | 1242 | mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate); |
7f859ecf | 1243 | |
cbce4f44 TG |
1244 | if (params->tx_dim_enabled) |
1245 | sq->state |= BIT(MLX5E_SQ_STATE_AM); | |
1246 | ||
f62b8bb8 AV |
1247 | return 0; |
1248 | ||
31391048 | 1249 | err_free_txqsq: |
3b77235b | 1250 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
31391048 | 1251 | mlx5e_free_txqsq(sq); |
f62b8bb8 AV |
1252 | |
1253 | return err; | |
1254 | } | |
1255 | ||
db75373c EBE |
1256 | static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq) |
1257 | { | |
1258 | WARN_ONCE(sq->cc != sq->pc, | |
1259 | "SQ 0x%x: cc (0x%x) != pc (0x%x)\n", | |
1260 | sq->sqn, sq->cc, sq->pc); | |
1261 | sq->cc = 0; | |
1262 | sq->dma_fifo_cc = 0; | |
1263 | sq->pc = 0; | |
1264 | } | |
1265 | ||
acc6c595 SM |
1266 | static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq) |
1267 | { | |
a43b25da | 1268 | sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix); |
db75373c | 1269 | clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state); |
acc6c595 SM |
1270 | set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
1271 | netdev_tx_reset_queue(sq->txq); | |
1272 | netif_tx_start_queue(sq->txq); | |
1273 | } | |
1274 | ||
f62b8bb8 AV |
1275 | static inline void netif_tx_disable_queue(struct netdev_queue *txq) |
1276 | { | |
1277 | __netif_tx_lock_bh(txq); | |
1278 | netif_tx_stop_queue(txq); | |
1279 | __netif_tx_unlock_bh(txq); | |
1280 | } | |
1281 | ||
acc6c595 | 1282 | static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq) |
f62b8bb8 | 1283 | { |
33ad9711 | 1284 | struct mlx5e_channel *c = sq->channel; |
ddf385e3 | 1285 | struct mlx5_wq_cyc *wq = &sq->wq; |
33ad9711 | 1286 | |
c0f1147d | 1287 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
6e8dd6d6 | 1288 | /* prevent netif_tx_wake_queue */ |
33ad9711 | 1289 | napi_synchronize(&c->napi); |
29429f33 | 1290 | |
31391048 | 1291 | netif_tx_disable_queue(sq->txq); |
f62b8bb8 | 1292 | |
31391048 | 1293 | /* last doorbell out, godspeed .. */ |
ddf385e3 TT |
1294 | if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) { |
1295 | u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); | |
31391048 | 1296 | struct mlx5e_tx_wqe *nop; |
864b2d71 | 1297 | |
ddf385e3 TT |
1298 | sq->db.wqe_info[pi].skb = NULL; |
1299 | nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc); | |
1300 | mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl); | |
29429f33 | 1301 | } |
acc6c595 SM |
1302 | } |
1303 | ||
1304 | static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq) | |
1305 | { | |
1306 | struct mlx5e_channel *c = sq->channel; | |
a43b25da | 1307 | struct mlx5_core_dev *mdev = c->mdev; |
05d3ac97 | 1308 | struct mlx5_rate_limit rl = {0}; |
f62b8bb8 | 1309 | |
a43b25da | 1310 | mlx5e_destroy_sq(mdev, sq->sqn); |
05d3ac97 BW |
1311 | if (sq->rate_limit) { |
1312 | rl.rate = sq->rate_limit; | |
1313 | mlx5_rl_remove_rate(mdev, &rl); | |
1314 | } | |
31391048 SM |
1315 | mlx5e_free_txqsq_descs(sq); |
1316 | mlx5e_free_txqsq(sq); | |
1317 | } | |
1318 | ||
db75373c EBE |
1319 | static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq) |
1320 | { | |
1321 | unsigned long exp_time = jiffies + msecs_to_jiffies(2000); | |
1322 | ||
1323 | while (time_before(jiffies, exp_time)) { | |
1324 | if (sq->cc == sq->pc) | |
1325 | return 0; | |
1326 | ||
1327 | msleep(20); | |
1328 | } | |
1329 | ||
1330 | netdev_err(sq->channel->netdev, | |
1331 | "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n", | |
1332 | sq->sqn, sq->cc, sq->pc); | |
1333 | ||
1334 | return -ETIMEDOUT; | |
1335 | } | |
1336 | ||
1337 | static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state) | |
1338 | { | |
1339 | struct mlx5_core_dev *mdev = sq->channel->mdev; | |
1340 | struct net_device *dev = sq->channel->netdev; | |
1341 | struct mlx5e_modify_sq_param msp = {0}; | |
1342 | int err; | |
1343 | ||
1344 | msp.curr_state = curr_state; | |
1345 | msp.next_state = MLX5_SQC_STATE_RST; | |
1346 | ||
1347 | err = mlx5e_modify_sq(mdev, sq->sqn, &msp); | |
1348 | if (err) { | |
1349 | netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn); | |
1350 | return err; | |
1351 | } | |
1352 | ||
1353 | memset(&msp, 0, sizeof(msp)); | |
1354 | msp.curr_state = MLX5_SQC_STATE_RST; | |
1355 | msp.next_state = MLX5_SQC_STATE_RDY; | |
1356 | ||
1357 | err = mlx5e_modify_sq(mdev, sq->sqn, &msp); | |
1358 | if (err) { | |
1359 | netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn); | |
1360 | return err; | |
1361 | } | |
1362 | ||
1363 | return 0; | |
1364 | } | |
1365 | ||
1366 | static void mlx5e_sq_recover(struct work_struct *work) | |
1367 | { | |
1368 | struct mlx5e_txqsq_recover *recover = | |
1369 | container_of(work, struct mlx5e_txqsq_recover, | |
1370 | recover_work); | |
1371 | struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq, | |
1372 | recover); | |
1373 | struct mlx5_core_dev *mdev = sq->channel->mdev; | |
1374 | struct net_device *dev = sq->channel->netdev; | |
1375 | u8 state; | |
1376 | int err; | |
1377 | ||
1378 | err = mlx5_core_query_sq_state(mdev, sq->sqn, &state); | |
1379 | if (err) { | |
1380 | netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n", | |
1381 | sq->sqn, err); | |
1382 | return; | |
1383 | } | |
1384 | ||
1385 | if (state != MLX5_RQC_STATE_ERR) { | |
1386 | netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn); | |
1387 | return; | |
1388 | } | |
1389 | ||
1390 | netif_tx_disable_queue(sq->txq); | |
1391 | ||
1392 | if (mlx5e_wait_for_sq_flush(sq)) | |
1393 | return; | |
1394 | ||
1395 | /* If the interval between two consecutive recovers per SQ is too | |
1396 | * short, don't recover to avoid infinite loop of ERR_CQE -> recover. | |
1397 | * If we reached this state, there is probably a bug that needs to be | |
1398 | * fixed. let's keep the queue close and let tx timeout cleanup. | |
1399 | */ | |
1400 | if (jiffies_to_msecs(jiffies - recover->last_recover) < | |
1401 | MLX5E_SQ_RECOVER_MIN_INTERVAL) { | |
1402 | netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n", | |
1403 | sq->sqn); | |
1404 | return; | |
1405 | } | |
1406 | ||
1407 | /* At this point, no new packets will arrive from the stack as TXQ is | |
1408 | * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all | |
1409 | * pending WQEs. SQ can safely reset the SQ. | |
1410 | */ | |
1411 | if (mlx5e_sq_to_ready(sq, state)) | |
1412 | return; | |
1413 | ||
1414 | mlx5e_reset_txqsq_cc_pc(sq); | |
05909bab | 1415 | sq->stats->recover++; |
db75373c EBE |
1416 | recover->last_recover = jiffies; |
1417 | mlx5e_activate_txqsq(sq); | |
1418 | } | |
1419 | ||
31391048 | 1420 | static int mlx5e_open_icosq(struct mlx5e_channel *c, |
6a9764ef | 1421 | struct mlx5e_params *params, |
31391048 SM |
1422 | struct mlx5e_sq_param *param, |
1423 | struct mlx5e_icosq *sq) | |
1424 | { | |
1425 | struct mlx5e_create_sq_param csp = {}; | |
1426 | int err; | |
1427 | ||
6a9764ef | 1428 | err = mlx5e_alloc_icosq(c, param, sq); |
31391048 SM |
1429 | if (err) |
1430 | return err; | |
1431 | ||
1432 | csp.cqn = sq->cq.mcq.cqn; | |
1433 | csp.wq_ctrl = &sq->wq_ctrl; | |
6a9764ef | 1434 | csp.min_inline_mode = params->tx_min_inline_mode; |
31391048 | 1435 | set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
a43b25da | 1436 | err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn); |
31391048 SM |
1437 | if (err) |
1438 | goto err_free_icosq; | |
1439 | ||
1440 | return 0; | |
1441 | ||
1442 | err_free_icosq: | |
1443 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1444 | mlx5e_free_icosq(sq); | |
1445 | ||
1446 | return err; | |
1447 | } | |
1448 | ||
1449 | static void mlx5e_close_icosq(struct mlx5e_icosq *sq) | |
1450 | { | |
1451 | struct mlx5e_channel *c = sq->channel; | |
1452 | ||
1453 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1454 | napi_synchronize(&c->napi); | |
1455 | ||
a43b25da | 1456 | mlx5e_destroy_sq(c->mdev, sq->sqn); |
31391048 SM |
1457 | mlx5e_free_icosq(sq); |
1458 | } | |
1459 | ||
1460 | static int mlx5e_open_xdpsq(struct mlx5e_channel *c, | |
6a9764ef | 1461 | struct mlx5e_params *params, |
31391048 SM |
1462 | struct mlx5e_sq_param *param, |
1463 | struct mlx5e_xdpsq *sq) | |
1464 | { | |
1465 | unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT; | |
1466 | struct mlx5e_create_sq_param csp = {}; | |
31391048 SM |
1467 | unsigned int inline_hdr_sz = 0; |
1468 | int err; | |
1469 | int i; | |
1470 | ||
6a9764ef | 1471 | err = mlx5e_alloc_xdpsq(c, params, param, sq); |
31391048 SM |
1472 | if (err) |
1473 | return err; | |
1474 | ||
1475 | csp.tis_lst_sz = 1; | |
a43b25da | 1476 | csp.tisn = c->priv->tisn[0]; /* tc = 0 */ |
31391048 SM |
1477 | csp.cqn = sq->cq.mcq.cqn; |
1478 | csp.wq_ctrl = &sq->wq_ctrl; | |
1479 | csp.min_inline_mode = sq->min_inline_mode; | |
1480 | set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
a43b25da | 1481 | err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn); |
31391048 SM |
1482 | if (err) |
1483 | goto err_free_xdpsq; | |
1484 | ||
1485 | if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { | |
1486 | inline_hdr_sz = MLX5E_XDP_MIN_INLINE; | |
1487 | ds_cnt++; | |
1488 | } | |
1489 | ||
1490 | /* Pre initialize fixed WQE fields */ | |
1491 | for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) { | |
1492 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i); | |
1493 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
1494 | struct mlx5_wqe_eth_seg *eseg = &wqe->eth; | |
1495 | struct mlx5_wqe_data_seg *dseg; | |
1496 | ||
1497 | cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt); | |
1498 | eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz); | |
1499 | ||
1500 | dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1); | |
1501 | dseg->lkey = sq->mkey_be; | |
1502 | } | |
1503 | ||
1504 | return 0; | |
1505 | ||
1506 | err_free_xdpsq: | |
1507 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1508 | mlx5e_free_xdpsq(sq); | |
1509 | ||
1510 | return err; | |
1511 | } | |
1512 | ||
1513 | static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq) | |
1514 | { | |
1515 | struct mlx5e_channel *c = sq->channel; | |
1516 | ||
1517 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1518 | napi_synchronize(&c->napi); | |
1519 | ||
a43b25da | 1520 | mlx5e_destroy_sq(c->mdev, sq->sqn); |
31391048 SM |
1521 | mlx5e_free_xdpsq_descs(sq); |
1522 | mlx5e_free_xdpsq(sq); | |
f62b8bb8 AV |
1523 | } |
1524 | ||
95b6c6a5 EBE |
1525 | static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev, |
1526 | struct mlx5e_cq_param *param, | |
1527 | struct mlx5e_cq *cq) | |
f62b8bb8 | 1528 | { |
f62b8bb8 AV |
1529 | struct mlx5_core_cq *mcq = &cq->mcq; |
1530 | int eqn_not_used; | |
0b6e26ce | 1531 | unsigned int irqn; |
f62b8bb8 AV |
1532 | int err; |
1533 | u32 i; | |
1534 | ||
f62b8bb8 AV |
1535 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, |
1536 | &cq->wq_ctrl); | |
1537 | if (err) | |
1538 | return err; | |
1539 | ||
1540 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); | |
1541 | ||
f62b8bb8 AV |
1542 | mcq->cqe_sz = 64; |
1543 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
1544 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
1545 | *mcq->set_ci_db = 0; | |
1546 | *mcq->arm_db = 0; | |
1547 | mcq->vector = param->eq_ix; | |
1548 | mcq->comp = mlx5e_completion_event; | |
1549 | mcq->event = mlx5e_cq_error_event; | |
1550 | mcq->irqn = irqn; | |
f62b8bb8 AV |
1551 | |
1552 | for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { | |
1553 | struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); | |
1554 | ||
1555 | cqe->op_own = 0xf1; | |
1556 | } | |
1557 | ||
a43b25da | 1558 | cq->mdev = mdev; |
f62b8bb8 AV |
1559 | |
1560 | return 0; | |
1561 | } | |
1562 | ||
95b6c6a5 EBE |
1563 | static int mlx5e_alloc_cq(struct mlx5e_channel *c, |
1564 | struct mlx5e_cq_param *param, | |
1565 | struct mlx5e_cq *cq) | |
1566 | { | |
1567 | struct mlx5_core_dev *mdev = c->priv->mdev; | |
1568 | int err; | |
1569 | ||
231243c8 SM |
1570 | param->wq.buf_numa_node = cpu_to_node(c->cpu); |
1571 | param->wq.db_numa_node = cpu_to_node(c->cpu); | |
95b6c6a5 EBE |
1572 | param->eq_ix = c->ix; |
1573 | ||
1574 | err = mlx5e_alloc_cq_common(mdev, param, cq); | |
1575 | ||
1576 | cq->napi = &c->napi; | |
1577 | cq->channel = c; | |
1578 | ||
1579 | return err; | |
1580 | } | |
1581 | ||
3b77235b | 1582 | static void mlx5e_free_cq(struct mlx5e_cq *cq) |
f62b8bb8 | 1583 | { |
3a2f7033 | 1584 | mlx5_wq_destroy(&cq->wq_ctrl); |
f62b8bb8 AV |
1585 | } |
1586 | ||
3b77235b | 1587 | static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) |
f62b8bb8 | 1588 | { |
a43b25da | 1589 | struct mlx5_core_dev *mdev = cq->mdev; |
f62b8bb8 AV |
1590 | struct mlx5_core_cq *mcq = &cq->mcq; |
1591 | ||
1592 | void *in; | |
1593 | void *cqc; | |
1594 | int inlen; | |
0b6e26ce | 1595 | unsigned int irqn_not_used; |
f62b8bb8 AV |
1596 | int eqn; |
1597 | int err; | |
1598 | ||
1599 | inlen = MLX5_ST_SZ_BYTES(create_cq_in) + | |
3a2f7033 | 1600 | sizeof(u64) * cq->wq_ctrl.buf.npages; |
1b9a07ee | 1601 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
1602 | if (!in) |
1603 | return -ENOMEM; | |
1604 | ||
1605 | cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); | |
1606 | ||
1607 | memcpy(cqc, param->cqc, sizeof(param->cqc)); | |
1608 | ||
3a2f7033 | 1609 | mlx5_fill_page_frag_array(&cq->wq_ctrl.buf, |
1c1b5228 | 1610 | (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas)); |
f62b8bb8 AV |
1611 | |
1612 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used); | |
1613 | ||
9908aa29 | 1614 | MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode); |
f62b8bb8 | 1615 | MLX5_SET(cqc, cqc, c_eqn, eqn); |
30aa60b3 | 1616 | MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index); |
3a2f7033 | 1617 | MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - |
68cdf5d6 | 1618 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
1619 | MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); |
1620 | ||
1621 | err = mlx5_core_create_cq(mdev, mcq, in, inlen); | |
1622 | ||
1623 | kvfree(in); | |
1624 | ||
1625 | if (err) | |
1626 | return err; | |
1627 | ||
1628 | mlx5e_cq_arm(cq); | |
1629 | ||
1630 | return 0; | |
1631 | } | |
1632 | ||
3b77235b | 1633 | static void mlx5e_destroy_cq(struct mlx5e_cq *cq) |
f62b8bb8 | 1634 | { |
a43b25da | 1635 | mlx5_core_destroy_cq(cq->mdev, &cq->mcq); |
f62b8bb8 AV |
1636 | } |
1637 | ||
1638 | static int mlx5e_open_cq(struct mlx5e_channel *c, | |
9a317425 | 1639 | struct net_dim_cq_moder moder, |
f62b8bb8 | 1640 | struct mlx5e_cq_param *param, |
6a9764ef | 1641 | struct mlx5e_cq *cq) |
f62b8bb8 | 1642 | { |
a43b25da | 1643 | struct mlx5_core_dev *mdev = c->mdev; |
f62b8bb8 | 1644 | int err; |
f62b8bb8 | 1645 | |
3b77235b | 1646 | err = mlx5e_alloc_cq(c, param, cq); |
f62b8bb8 AV |
1647 | if (err) |
1648 | return err; | |
1649 | ||
3b77235b | 1650 | err = mlx5e_create_cq(cq, param); |
f62b8bb8 | 1651 | if (err) |
3b77235b | 1652 | goto err_free_cq; |
f62b8bb8 | 1653 | |
7524a5d8 | 1654 | if (MLX5_CAP_GEN(mdev, cq_moderation)) |
6a9764ef | 1655 | mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts); |
f62b8bb8 AV |
1656 | return 0; |
1657 | ||
3b77235b SM |
1658 | err_free_cq: |
1659 | mlx5e_free_cq(cq); | |
f62b8bb8 AV |
1660 | |
1661 | return err; | |
1662 | } | |
1663 | ||
1664 | static void mlx5e_close_cq(struct mlx5e_cq *cq) | |
1665 | { | |
f62b8bb8 | 1666 | mlx5e_destroy_cq(cq); |
3b77235b | 1667 | mlx5e_free_cq(cq); |
f62b8bb8 AV |
1668 | } |
1669 | ||
231243c8 SM |
1670 | static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix) |
1671 | { | |
1672 | return cpumask_first(priv->mdev->priv.irq_info[ix].mask); | |
1673 | } | |
1674 | ||
f62b8bb8 | 1675 | static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, |
6a9764ef | 1676 | struct mlx5e_params *params, |
f62b8bb8 AV |
1677 | struct mlx5e_channel_param *cparam) |
1678 | { | |
f62b8bb8 AV |
1679 | int err; |
1680 | int tc; | |
1681 | ||
1682 | for (tc = 0; tc < c->num_tc; tc++) { | |
6a9764ef SM |
1683 | err = mlx5e_open_cq(c, params->tx_cq_moderation, |
1684 | &cparam->tx_cq, &c->sq[tc].cq); | |
f62b8bb8 AV |
1685 | if (err) |
1686 | goto err_close_tx_cqs; | |
f62b8bb8 AV |
1687 | } |
1688 | ||
1689 | return 0; | |
1690 | ||
1691 | err_close_tx_cqs: | |
1692 | for (tc--; tc >= 0; tc--) | |
1693 | mlx5e_close_cq(&c->sq[tc].cq); | |
1694 | ||
1695 | return err; | |
1696 | } | |
1697 | ||
1698 | static void mlx5e_close_tx_cqs(struct mlx5e_channel *c) | |
1699 | { | |
1700 | int tc; | |
1701 | ||
1702 | for (tc = 0; tc < c->num_tc; tc++) | |
1703 | mlx5e_close_cq(&c->sq[tc].cq); | |
1704 | } | |
1705 | ||
1706 | static int mlx5e_open_sqs(struct mlx5e_channel *c, | |
6a9764ef | 1707 | struct mlx5e_params *params, |
f62b8bb8 AV |
1708 | struct mlx5e_channel_param *cparam) |
1709 | { | |
05909bab EBE |
1710 | struct mlx5e_priv *priv = c->priv; |
1711 | int err, tc, max_nch = priv->profile->max_nch(priv->mdev); | |
f62b8bb8 | 1712 | |
6a9764ef | 1713 | for (tc = 0; tc < params->num_tc; tc++) { |
05909bab | 1714 | int txq_ix = c->ix + tc * max_nch; |
acc6c595 | 1715 | |
a43b25da | 1716 | err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix, |
05909bab | 1717 | params, &cparam->sq, &c->sq[tc], tc); |
f62b8bb8 AV |
1718 | if (err) |
1719 | goto err_close_sqs; | |
1720 | } | |
1721 | ||
1722 | return 0; | |
1723 | ||
1724 | err_close_sqs: | |
1725 | for (tc--; tc >= 0; tc--) | |
31391048 | 1726 | mlx5e_close_txqsq(&c->sq[tc]); |
f62b8bb8 AV |
1727 | |
1728 | return err; | |
1729 | } | |
1730 | ||
1731 | static void mlx5e_close_sqs(struct mlx5e_channel *c) | |
1732 | { | |
1733 | int tc; | |
1734 | ||
1735 | for (tc = 0; tc < c->num_tc; tc++) | |
31391048 | 1736 | mlx5e_close_txqsq(&c->sq[tc]); |
f62b8bb8 AV |
1737 | } |
1738 | ||
507f0c81 | 1739 | static int mlx5e_set_sq_maxrate(struct net_device *dev, |
31391048 | 1740 | struct mlx5e_txqsq *sq, u32 rate) |
507f0c81 YP |
1741 | { |
1742 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1743 | struct mlx5_core_dev *mdev = priv->mdev; | |
33ad9711 | 1744 | struct mlx5e_modify_sq_param msp = {0}; |
05d3ac97 | 1745 | struct mlx5_rate_limit rl = {0}; |
507f0c81 YP |
1746 | u16 rl_index = 0; |
1747 | int err; | |
1748 | ||
1749 | if (rate == sq->rate_limit) | |
1750 | /* nothing to do */ | |
1751 | return 0; | |
1752 | ||
05d3ac97 BW |
1753 | if (sq->rate_limit) { |
1754 | rl.rate = sq->rate_limit; | |
507f0c81 | 1755 | /* remove current rl index to free space to next ones */ |
05d3ac97 BW |
1756 | mlx5_rl_remove_rate(mdev, &rl); |
1757 | } | |
507f0c81 YP |
1758 | |
1759 | sq->rate_limit = 0; | |
1760 | ||
1761 | if (rate) { | |
05d3ac97 BW |
1762 | rl.rate = rate; |
1763 | err = mlx5_rl_add_rate(mdev, &rl_index, &rl); | |
507f0c81 YP |
1764 | if (err) { |
1765 | netdev_err(dev, "Failed configuring rate %u: %d\n", | |
1766 | rate, err); | |
1767 | return err; | |
1768 | } | |
1769 | } | |
1770 | ||
33ad9711 SM |
1771 | msp.curr_state = MLX5_SQC_STATE_RDY; |
1772 | msp.next_state = MLX5_SQC_STATE_RDY; | |
1773 | msp.rl_index = rl_index; | |
1774 | msp.rl_update = true; | |
a43b25da | 1775 | err = mlx5e_modify_sq(mdev, sq->sqn, &msp); |
507f0c81 YP |
1776 | if (err) { |
1777 | netdev_err(dev, "Failed configuring rate %u: %d\n", | |
1778 | rate, err); | |
1779 | /* remove the rate from the table */ | |
1780 | if (rate) | |
05d3ac97 | 1781 | mlx5_rl_remove_rate(mdev, &rl); |
507f0c81 YP |
1782 | return err; |
1783 | } | |
1784 | ||
1785 | sq->rate_limit = rate; | |
1786 | return 0; | |
1787 | } | |
1788 | ||
1789 | static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate) | |
1790 | { | |
1791 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1792 | struct mlx5_core_dev *mdev = priv->mdev; | |
acc6c595 | 1793 | struct mlx5e_txqsq *sq = priv->txq2sq[index]; |
507f0c81 YP |
1794 | int err = 0; |
1795 | ||
1796 | if (!mlx5_rl_is_supported(mdev)) { | |
1797 | netdev_err(dev, "Rate limiting is not supported on this device\n"); | |
1798 | return -EINVAL; | |
1799 | } | |
1800 | ||
1801 | /* rate is given in Mb/sec, HW config is in Kb/sec */ | |
1802 | rate = rate << 10; | |
1803 | ||
1804 | /* Check whether rate in valid range, 0 is always valid */ | |
1805 | if (rate && !mlx5_rl_is_in_range(mdev, rate)) { | |
1806 | netdev_err(dev, "TX rate %u, is not in range\n", rate); | |
1807 | return -ERANGE; | |
1808 | } | |
1809 | ||
1810 | mutex_lock(&priv->state_lock); | |
1811 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
1812 | err = mlx5e_set_sq_maxrate(dev, sq, rate); | |
1813 | if (!err) | |
1814 | priv->tx_rates[index] = rate; | |
1815 | mutex_unlock(&priv->state_lock); | |
1816 | ||
1817 | return err; | |
1818 | } | |
1819 | ||
f62b8bb8 | 1820 | static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, |
6a9764ef | 1821 | struct mlx5e_params *params, |
f62b8bb8 AV |
1822 | struct mlx5e_channel_param *cparam, |
1823 | struct mlx5e_channel **cp) | |
1824 | { | |
9a317425 | 1825 | struct net_dim_cq_moder icocq_moder = {0, 0}; |
f62b8bb8 | 1826 | struct net_device *netdev = priv->netdev; |
231243c8 | 1827 | int cpu = mlx5e_get_cpu(priv, ix); |
f62b8bb8 | 1828 | struct mlx5e_channel *c; |
a8c2eb15 | 1829 | unsigned int irq; |
f62b8bb8 | 1830 | int err; |
a8c2eb15 | 1831 | int eqn; |
f62b8bb8 | 1832 | |
231243c8 | 1833 | c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu)); |
f62b8bb8 AV |
1834 | if (!c) |
1835 | return -ENOMEM; | |
1836 | ||
1837 | c->priv = priv; | |
a43b25da SM |
1838 | c->mdev = priv->mdev; |
1839 | c->tstamp = &priv->tstamp; | |
f62b8bb8 | 1840 | c->ix = ix; |
231243c8 | 1841 | c->cpu = cpu; |
f62b8bb8 AV |
1842 | c->pdev = &priv->mdev->pdev->dev; |
1843 | c->netdev = priv->netdev; | |
b50d292b | 1844 | c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key); |
6a9764ef SM |
1845 | c->num_tc = params->num_tc; |
1846 | c->xdp = !!params->xdp_prog; | |
05909bab | 1847 | c->stats = &priv->channel_stats[ix].ch; |
cb3c7fd4 | 1848 | |
a8c2eb15 TT |
1849 | mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq); |
1850 | c->irq_desc = irq_to_desc(irq); | |
1851 | ||
f62b8bb8 AV |
1852 | netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64); |
1853 | ||
6a9764ef | 1854 | err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq); |
f62b8bb8 AV |
1855 | if (err) |
1856 | goto err_napi_del; | |
1857 | ||
6a9764ef | 1858 | err = mlx5e_open_tx_cqs(c, params, cparam); |
d3c9bc27 TT |
1859 | if (err) |
1860 | goto err_close_icosq_cq; | |
1861 | ||
6a9764ef | 1862 | err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq); |
f62b8bb8 AV |
1863 | if (err) |
1864 | goto err_close_tx_cqs; | |
f62b8bb8 | 1865 | |
d7a0ecab | 1866 | /* XDP SQ CQ params are same as normal TXQ sq CQ params */ |
6a9764ef SM |
1867 | err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation, |
1868 | &cparam->tx_cq, &c->rq.xdpsq.cq) : 0; | |
d7a0ecab SM |
1869 | if (err) |
1870 | goto err_close_rx_cq; | |
1871 | ||
f62b8bb8 AV |
1872 | napi_enable(&c->napi); |
1873 | ||
6a9764ef | 1874 | err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq); |
f62b8bb8 AV |
1875 | if (err) |
1876 | goto err_disable_napi; | |
1877 | ||
6a9764ef | 1878 | err = mlx5e_open_sqs(c, params, cparam); |
d3c9bc27 TT |
1879 | if (err) |
1880 | goto err_close_icosq; | |
1881 | ||
6a9764ef | 1882 | err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0; |
d7a0ecab SM |
1883 | if (err) |
1884 | goto err_close_sqs; | |
b5503b99 | 1885 | |
6a9764ef | 1886 | err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq); |
f62b8bb8 | 1887 | if (err) |
b5503b99 | 1888 | goto err_close_xdp_sq; |
f62b8bb8 | 1889 | |
f62b8bb8 AV |
1890 | *cp = c; |
1891 | ||
1892 | return 0; | |
b5503b99 | 1893 | err_close_xdp_sq: |
d7a0ecab | 1894 | if (c->xdp) |
31391048 | 1895 | mlx5e_close_xdpsq(&c->rq.xdpsq); |
f62b8bb8 AV |
1896 | |
1897 | err_close_sqs: | |
1898 | mlx5e_close_sqs(c); | |
1899 | ||
d3c9bc27 | 1900 | err_close_icosq: |
31391048 | 1901 | mlx5e_close_icosq(&c->icosq); |
d3c9bc27 | 1902 | |
f62b8bb8 AV |
1903 | err_disable_napi: |
1904 | napi_disable(&c->napi); | |
d7a0ecab | 1905 | if (c->xdp) |
31871f87 | 1906 | mlx5e_close_cq(&c->rq.xdpsq.cq); |
d7a0ecab SM |
1907 | |
1908 | err_close_rx_cq: | |
f62b8bb8 AV |
1909 | mlx5e_close_cq(&c->rq.cq); |
1910 | ||
1911 | err_close_tx_cqs: | |
1912 | mlx5e_close_tx_cqs(c); | |
1913 | ||
d3c9bc27 TT |
1914 | err_close_icosq_cq: |
1915 | mlx5e_close_cq(&c->icosq.cq); | |
1916 | ||
f62b8bb8 AV |
1917 | err_napi_del: |
1918 | netif_napi_del(&c->napi); | |
1919 | kfree(c); | |
1920 | ||
1921 | return err; | |
1922 | } | |
1923 | ||
acc6c595 SM |
1924 | static void mlx5e_activate_channel(struct mlx5e_channel *c) |
1925 | { | |
1926 | int tc; | |
1927 | ||
1928 | for (tc = 0; tc < c->num_tc; tc++) | |
1929 | mlx5e_activate_txqsq(&c->sq[tc]); | |
1930 | mlx5e_activate_rq(&c->rq); | |
231243c8 | 1931 | netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix); |
acc6c595 SM |
1932 | } |
1933 | ||
1934 | static void mlx5e_deactivate_channel(struct mlx5e_channel *c) | |
1935 | { | |
1936 | int tc; | |
1937 | ||
1938 | mlx5e_deactivate_rq(&c->rq); | |
1939 | for (tc = 0; tc < c->num_tc; tc++) | |
1940 | mlx5e_deactivate_txqsq(&c->sq[tc]); | |
1941 | } | |
1942 | ||
f62b8bb8 AV |
1943 | static void mlx5e_close_channel(struct mlx5e_channel *c) |
1944 | { | |
1945 | mlx5e_close_rq(&c->rq); | |
b5503b99 | 1946 | if (c->xdp) |
31391048 | 1947 | mlx5e_close_xdpsq(&c->rq.xdpsq); |
f62b8bb8 | 1948 | mlx5e_close_sqs(c); |
31391048 | 1949 | mlx5e_close_icosq(&c->icosq); |
f62b8bb8 | 1950 | napi_disable(&c->napi); |
b5503b99 | 1951 | if (c->xdp) |
31871f87 | 1952 | mlx5e_close_cq(&c->rq.xdpsq.cq); |
f62b8bb8 AV |
1953 | mlx5e_close_cq(&c->rq.cq); |
1954 | mlx5e_close_tx_cqs(c); | |
d3c9bc27 | 1955 | mlx5e_close_cq(&c->icosq.cq); |
f62b8bb8 | 1956 | netif_napi_del(&c->napi); |
7ae92ae5 | 1957 | |
f62b8bb8 AV |
1958 | kfree(c); |
1959 | } | |
1960 | ||
1961 | static void mlx5e_build_rq_param(struct mlx5e_priv *priv, | |
6a9764ef | 1962 | struct mlx5e_params *params, |
f62b8bb8 AV |
1963 | struct mlx5e_rq_param *param) |
1964 | { | |
f1e4fc9b | 1965 | struct mlx5_core_dev *mdev = priv->mdev; |
f62b8bb8 AV |
1966 | void *rqc = param->rqc; |
1967 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1968 | ||
6a9764ef | 1969 | switch (params->rq_wq_type) { |
461017cb | 1970 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: |
f1e4fc9b | 1971 | MLX5_SET(wq, wq, log_wqe_num_of_strides, |
619a8f2a TT |
1972 | mlx5e_mpwqe_get_log_num_strides(mdev, params) - |
1973 | MLX5_MPWQE_LOG_NUM_STRIDES_BASE); | |
f1e4fc9b | 1974 | MLX5_SET(wq, wq, log_wqe_stride_size, |
619a8f2a TT |
1975 | mlx5e_mpwqe_get_log_stride_size(mdev, params) - |
1976 | MLX5_MPWQE_LOG_STRIDE_SZ_BASE); | |
461017cb | 1977 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ); |
73281b78 | 1978 | MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params)); |
461017cb TT |
1979 | break; |
1980 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
1981 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
73281b78 | 1982 | MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames); |
461017cb TT |
1983 | } |
1984 | ||
f62b8bb8 AV |
1985 | MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); |
1986 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
f1e4fc9b | 1987 | MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn); |
593cf338 | 1988 | MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter); |
6a9764ef | 1989 | MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable); |
102722fc | 1990 | MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en); |
f62b8bb8 | 1991 | |
f1e4fc9b | 1992 | param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev); |
f62b8bb8 AV |
1993 | } |
1994 | ||
7cbaf9a3 | 1995 | static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv, |
2f0db879 | 1996 | struct mlx5e_rq_param *param) |
556dd1b9 | 1997 | { |
7cbaf9a3 | 1998 | struct mlx5_core_dev *mdev = priv->mdev; |
556dd1b9 TT |
1999 | void *rqc = param->rqc; |
2000 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
2001 | ||
2002 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
2003 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
7cbaf9a3 | 2004 | MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter); |
2f0db879 GP |
2005 | |
2006 | param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev); | |
556dd1b9 TT |
2007 | } |
2008 | ||
d3c9bc27 TT |
2009 | static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv, |
2010 | struct mlx5e_sq_param *param) | |
f62b8bb8 AV |
2011 | { |
2012 | void *sqc = param->sqc; | |
2013 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
2014 | ||
f62b8bb8 | 2015 | MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); |
b50d292b | 2016 | MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn); |
f62b8bb8 | 2017 | |
311c7c71 | 2018 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); |
d3c9bc27 TT |
2019 | } |
2020 | ||
2021 | static void mlx5e_build_sq_param(struct mlx5e_priv *priv, | |
6a9764ef | 2022 | struct mlx5e_params *params, |
d3c9bc27 TT |
2023 | struct mlx5e_sq_param *param) |
2024 | { | |
2025 | void *sqc = param->sqc; | |
2026 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
2027 | ||
2028 | mlx5e_build_sq_param_common(priv, param); | |
6a9764ef | 2029 | MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size); |
2ac9cfe7 | 2030 | MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev)); |
f62b8bb8 AV |
2031 | } |
2032 | ||
2033 | static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv, | |
2034 | struct mlx5e_cq_param *param) | |
2035 | { | |
2036 | void *cqc = param->cqc; | |
2037 | ||
30aa60b3 | 2038 | MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index); |
f62b8bb8 AV |
2039 | } |
2040 | ||
2041 | static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, | |
6a9764ef | 2042 | struct mlx5e_params *params, |
f62b8bb8 AV |
2043 | struct mlx5e_cq_param *param) |
2044 | { | |
73281b78 | 2045 | struct mlx5_core_dev *mdev = priv->mdev; |
f62b8bb8 | 2046 | void *cqc = param->cqc; |
461017cb | 2047 | u8 log_cq_size; |
f62b8bb8 | 2048 | |
6a9764ef | 2049 | switch (params->rq_wq_type) { |
461017cb | 2050 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: |
73281b78 TT |
2051 | log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) + |
2052 | mlx5e_mpwqe_get_log_num_strides(mdev, params); | |
461017cb TT |
2053 | break; |
2054 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
73281b78 | 2055 | log_cq_size = params->log_rq_mtu_frames; |
461017cb TT |
2056 | } |
2057 | ||
2058 | MLX5_SET(cqc, cqc, log_cq_size, log_cq_size); | |
6a9764ef | 2059 | if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) { |
7219ab34 TT |
2060 | MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM); |
2061 | MLX5_SET(cqc, cqc, cqe_comp_en, 1); | |
2062 | } | |
f62b8bb8 AV |
2063 | |
2064 | mlx5e_build_common_cq_param(priv, param); | |
0088cbbc | 2065 | param->cq_period_mode = params->rx_cq_moderation.cq_period_mode; |
f62b8bb8 AV |
2066 | } |
2067 | ||
2068 | static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, | |
6a9764ef | 2069 | struct mlx5e_params *params, |
f62b8bb8 AV |
2070 | struct mlx5e_cq_param *param) |
2071 | { | |
2072 | void *cqc = param->cqc; | |
2073 | ||
6a9764ef | 2074 | MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size); |
f62b8bb8 AV |
2075 | |
2076 | mlx5e_build_common_cq_param(priv, param); | |
0088cbbc | 2077 | param->cq_period_mode = params->tx_cq_moderation.cq_period_mode; |
f62b8bb8 AV |
2078 | } |
2079 | ||
d3c9bc27 | 2080 | static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv, |
6a9764ef SM |
2081 | u8 log_wq_size, |
2082 | struct mlx5e_cq_param *param) | |
d3c9bc27 TT |
2083 | { |
2084 | void *cqc = param->cqc; | |
2085 | ||
2086 | MLX5_SET(cqc, cqc, log_cq_size, log_wq_size); | |
2087 | ||
2088 | mlx5e_build_common_cq_param(priv, param); | |
9908aa29 | 2089 | |
9a317425 | 2090 | param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; |
d3c9bc27 TT |
2091 | } |
2092 | ||
2093 | static void mlx5e_build_icosq_param(struct mlx5e_priv *priv, | |
6a9764ef SM |
2094 | u8 log_wq_size, |
2095 | struct mlx5e_sq_param *param) | |
d3c9bc27 TT |
2096 | { |
2097 | void *sqc = param->sqc; | |
2098 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
2099 | ||
2100 | mlx5e_build_sq_param_common(priv, param); | |
2101 | ||
2102 | MLX5_SET(wq, wq, log_wq_sz, log_wq_size); | |
bc77b240 | 2103 | MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq)); |
d3c9bc27 TT |
2104 | } |
2105 | ||
b5503b99 | 2106 | static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv, |
6a9764ef | 2107 | struct mlx5e_params *params, |
b5503b99 SM |
2108 | struct mlx5e_sq_param *param) |
2109 | { | |
2110 | void *sqc = param->sqc; | |
2111 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
2112 | ||
2113 | mlx5e_build_sq_param_common(priv, param); | |
6a9764ef | 2114 | MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size); |
b5503b99 SM |
2115 | } |
2116 | ||
6a9764ef SM |
2117 | static void mlx5e_build_channel_param(struct mlx5e_priv *priv, |
2118 | struct mlx5e_params *params, | |
2119 | struct mlx5e_channel_param *cparam) | |
f62b8bb8 | 2120 | { |
bc77b240 | 2121 | u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; |
d3c9bc27 | 2122 | |
6a9764ef SM |
2123 | mlx5e_build_rq_param(priv, params, &cparam->rq); |
2124 | mlx5e_build_sq_param(priv, params, &cparam->sq); | |
2125 | mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq); | |
2126 | mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq); | |
2127 | mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq); | |
2128 | mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq); | |
2129 | mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq); | |
f62b8bb8 AV |
2130 | } |
2131 | ||
55c2503d SM |
2132 | int mlx5e_open_channels(struct mlx5e_priv *priv, |
2133 | struct mlx5e_channels *chs) | |
f62b8bb8 | 2134 | { |
6b87663f | 2135 | struct mlx5e_channel_param *cparam; |
03289b88 | 2136 | int err = -ENOMEM; |
f62b8bb8 | 2137 | int i; |
f62b8bb8 | 2138 | |
6a9764ef | 2139 | chs->num = chs->params.num_channels; |
03289b88 | 2140 | |
ff9c852f | 2141 | chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL); |
6b87663f | 2142 | cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL); |
acc6c595 SM |
2143 | if (!chs->c || !cparam) |
2144 | goto err_free; | |
f62b8bb8 | 2145 | |
6a9764ef | 2146 | mlx5e_build_channel_param(priv, &chs->params, cparam); |
ff9c852f | 2147 | for (i = 0; i < chs->num; i++) { |
6a9764ef | 2148 | err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]); |
f62b8bb8 AV |
2149 | if (err) |
2150 | goto err_close_channels; | |
2151 | } | |
2152 | ||
6b87663f | 2153 | kfree(cparam); |
f62b8bb8 AV |
2154 | return 0; |
2155 | ||
2156 | err_close_channels: | |
2157 | for (i--; i >= 0; i--) | |
ff9c852f | 2158 | mlx5e_close_channel(chs->c[i]); |
f62b8bb8 | 2159 | |
acc6c595 | 2160 | err_free: |
ff9c852f | 2161 | kfree(chs->c); |
6b87663f | 2162 | kfree(cparam); |
ff9c852f | 2163 | chs->num = 0; |
f62b8bb8 AV |
2164 | return err; |
2165 | } | |
2166 | ||
acc6c595 | 2167 | static void mlx5e_activate_channels(struct mlx5e_channels *chs) |
f62b8bb8 AV |
2168 | { |
2169 | int i; | |
2170 | ||
acc6c595 SM |
2171 | for (i = 0; i < chs->num; i++) |
2172 | mlx5e_activate_channel(chs->c[i]); | |
2173 | } | |
2174 | ||
2175 | static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs) | |
2176 | { | |
2177 | int err = 0; | |
2178 | int i; | |
2179 | ||
1e7477ae EBE |
2180 | for (i = 0; i < chs->num; i++) |
2181 | err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, | |
2182 | err ? 0 : 20000); | |
acc6c595 | 2183 | |
1e7477ae | 2184 | return err ? -ETIMEDOUT : 0; |
acc6c595 SM |
2185 | } |
2186 | ||
2187 | static void mlx5e_deactivate_channels(struct mlx5e_channels *chs) | |
2188 | { | |
2189 | int i; | |
2190 | ||
2191 | for (i = 0; i < chs->num; i++) | |
2192 | mlx5e_deactivate_channel(chs->c[i]); | |
2193 | } | |
2194 | ||
55c2503d | 2195 | void mlx5e_close_channels(struct mlx5e_channels *chs) |
acc6c595 SM |
2196 | { |
2197 | int i; | |
c3b7c5c9 | 2198 | |
ff9c852f SM |
2199 | for (i = 0; i < chs->num; i++) |
2200 | mlx5e_close_channel(chs->c[i]); | |
f62b8bb8 | 2201 | |
ff9c852f SM |
2202 | kfree(chs->c); |
2203 | chs->num = 0; | |
f62b8bb8 AV |
2204 | } |
2205 | ||
a5f97fee SM |
2206 | static int |
2207 | mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt) | |
f62b8bb8 AV |
2208 | { |
2209 | struct mlx5_core_dev *mdev = priv->mdev; | |
f62b8bb8 AV |
2210 | void *rqtc; |
2211 | int inlen; | |
2212 | int err; | |
1da36696 | 2213 | u32 *in; |
a5f97fee | 2214 | int i; |
f62b8bb8 | 2215 | |
f62b8bb8 | 2216 | inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; |
1b9a07ee | 2217 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
2218 | if (!in) |
2219 | return -ENOMEM; | |
2220 | ||
2221 | rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); | |
2222 | ||
2223 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
2224 | MLX5_SET(rqtc, rqtc, rqt_max_size, sz); | |
2225 | ||
a5f97fee SM |
2226 | for (i = 0; i < sz; i++) |
2227 | MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn); | |
2be6967c | 2228 | |
398f3351 HHZ |
2229 | err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn); |
2230 | if (!err) | |
2231 | rqt->enabled = true; | |
f62b8bb8 AV |
2232 | |
2233 | kvfree(in); | |
1da36696 TT |
2234 | return err; |
2235 | } | |
2236 | ||
cb67b832 | 2237 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt) |
1da36696 | 2238 | { |
398f3351 HHZ |
2239 | rqt->enabled = false; |
2240 | mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn); | |
1da36696 TT |
2241 | } |
2242 | ||
8f493ffd | 2243 | int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv) |
6bfd390b HHZ |
2244 | { |
2245 | struct mlx5e_rqt *rqt = &priv->indir_rqt; | |
8f493ffd | 2246 | int err; |
6bfd390b | 2247 | |
8f493ffd SM |
2248 | err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt); |
2249 | if (err) | |
2250 | mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err); | |
2251 | return err; | |
6bfd390b HHZ |
2252 | } |
2253 | ||
cb67b832 | 2254 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv) |
1da36696 | 2255 | { |
398f3351 | 2256 | struct mlx5e_rqt *rqt; |
1da36696 TT |
2257 | int err; |
2258 | int ix; | |
2259 | ||
6bfd390b | 2260 | for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) { |
398f3351 | 2261 | rqt = &priv->direct_tir[ix].rqt; |
a5f97fee | 2262 | err = mlx5e_create_rqt(priv, 1 /*size */, rqt); |
1da36696 TT |
2263 | if (err) |
2264 | goto err_destroy_rqts; | |
2265 | } | |
2266 | ||
2267 | return 0; | |
2268 | ||
2269 | err_destroy_rqts: | |
8f493ffd | 2270 | mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err); |
1da36696 | 2271 | for (ix--; ix >= 0; ix--) |
398f3351 | 2272 | mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt); |
1da36696 | 2273 | |
f62b8bb8 AV |
2274 | return err; |
2275 | } | |
2276 | ||
8f493ffd SM |
2277 | void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv) |
2278 | { | |
2279 | int i; | |
2280 | ||
2281 | for (i = 0; i < priv->profile->max_nch(priv->mdev); i++) | |
2282 | mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt); | |
2283 | } | |
2284 | ||
a5f97fee SM |
2285 | static int mlx5e_rx_hash_fn(int hfunc) |
2286 | { | |
2287 | return (hfunc == ETH_RSS_HASH_TOP) ? | |
2288 | MLX5_RX_HASH_FN_TOEPLITZ : | |
2289 | MLX5_RX_HASH_FN_INVERTED_XOR8; | |
2290 | } | |
2291 | ||
3f6d08d1 | 2292 | int mlx5e_bits_invert(unsigned long a, int size) |
a5f97fee SM |
2293 | { |
2294 | int inv = 0; | |
2295 | int i; | |
2296 | ||
2297 | for (i = 0; i < size; i++) | |
2298 | inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i; | |
2299 | ||
2300 | return inv; | |
2301 | } | |
2302 | ||
2303 | static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz, | |
2304 | struct mlx5e_redirect_rqt_param rrp, void *rqtc) | |
2305 | { | |
2306 | int i; | |
2307 | ||
2308 | for (i = 0; i < sz; i++) { | |
2309 | u32 rqn; | |
2310 | ||
2311 | if (rrp.is_rss) { | |
2312 | int ix = i; | |
2313 | ||
2314 | if (rrp.rss.hfunc == ETH_RSS_HASH_XOR) | |
2315 | ix = mlx5e_bits_invert(i, ilog2(sz)); | |
2316 | ||
6a9764ef | 2317 | ix = priv->channels.params.indirection_rqt[ix]; |
a5f97fee SM |
2318 | rqn = rrp.rss.channels->c[ix]->rq.rqn; |
2319 | } else { | |
2320 | rqn = rrp.rqn; | |
2321 | } | |
2322 | MLX5_SET(rqtc, rqtc, rq_num[i], rqn); | |
2323 | } | |
2324 | } | |
2325 | ||
2326 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, | |
2327 | struct mlx5e_redirect_rqt_param rrp) | |
5c50368f AS |
2328 | { |
2329 | struct mlx5_core_dev *mdev = priv->mdev; | |
5c50368f AS |
2330 | void *rqtc; |
2331 | int inlen; | |
1da36696 | 2332 | u32 *in; |
5c50368f AS |
2333 | int err; |
2334 | ||
5c50368f | 2335 | inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; |
1b9a07ee | 2336 | in = kvzalloc(inlen, GFP_KERNEL); |
5c50368f AS |
2337 | if (!in) |
2338 | return -ENOMEM; | |
2339 | ||
2340 | rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); | |
2341 | ||
2342 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
5c50368f | 2343 | MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); |
a5f97fee | 2344 | mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc); |
1da36696 | 2345 | err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen); |
5c50368f AS |
2346 | |
2347 | kvfree(in); | |
5c50368f AS |
2348 | return err; |
2349 | } | |
2350 | ||
a5f97fee SM |
2351 | static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix, |
2352 | struct mlx5e_redirect_rqt_param rrp) | |
2353 | { | |
2354 | if (!rrp.is_rss) | |
2355 | return rrp.rqn; | |
2356 | ||
2357 | if (ix >= rrp.rss.channels->num) | |
2358 | return priv->drop_rq.rqn; | |
2359 | ||
2360 | return rrp.rss.channels->c[ix]->rq.rqn; | |
2361 | } | |
2362 | ||
2363 | static void mlx5e_redirect_rqts(struct mlx5e_priv *priv, | |
2364 | struct mlx5e_redirect_rqt_param rrp) | |
40ab6a6e | 2365 | { |
1da36696 TT |
2366 | u32 rqtn; |
2367 | int ix; | |
2368 | ||
398f3351 | 2369 | if (priv->indir_rqt.enabled) { |
a5f97fee | 2370 | /* RSS RQ table */ |
398f3351 | 2371 | rqtn = priv->indir_rqt.rqtn; |
a5f97fee | 2372 | mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp); |
398f3351 HHZ |
2373 | } |
2374 | ||
a5f97fee SM |
2375 | for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) { |
2376 | struct mlx5e_redirect_rqt_param direct_rrp = { | |
2377 | .is_rss = false, | |
95632791 AM |
2378 | { |
2379 | .rqn = mlx5e_get_direct_rqn(priv, ix, rrp) | |
2380 | }, | |
a5f97fee SM |
2381 | }; |
2382 | ||
2383 | /* Direct RQ Tables */ | |
398f3351 HHZ |
2384 | if (!priv->direct_tir[ix].rqt.enabled) |
2385 | continue; | |
a5f97fee | 2386 | |
398f3351 | 2387 | rqtn = priv->direct_tir[ix].rqt.rqtn; |
a5f97fee | 2388 | mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp); |
1da36696 | 2389 | } |
40ab6a6e AS |
2390 | } |
2391 | ||
a5f97fee SM |
2392 | static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv, |
2393 | struct mlx5e_channels *chs) | |
2394 | { | |
2395 | struct mlx5e_redirect_rqt_param rrp = { | |
2396 | .is_rss = true, | |
95632791 AM |
2397 | { |
2398 | .rss = { | |
2399 | .channels = chs, | |
2400 | .hfunc = chs->params.rss_hfunc, | |
2401 | } | |
2402 | }, | |
a5f97fee SM |
2403 | }; |
2404 | ||
2405 | mlx5e_redirect_rqts(priv, rrp); | |
2406 | } | |
2407 | ||
2408 | static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv) | |
2409 | { | |
2410 | struct mlx5e_redirect_rqt_param drop_rrp = { | |
2411 | .is_rss = false, | |
95632791 AM |
2412 | { |
2413 | .rqn = priv->drop_rq.rqn, | |
2414 | }, | |
a5f97fee SM |
2415 | }; |
2416 | ||
2417 | mlx5e_redirect_rqts(priv, drop_rrp); | |
2418 | } | |
2419 | ||
6a9764ef | 2420 | static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc) |
5c50368f | 2421 | { |
6a9764ef | 2422 | if (!params->lro_en) |
5c50368f AS |
2423 | return; |
2424 | ||
2425 | #define ROUGH_MAX_L2_L3_HDR_SZ 256 | |
2426 | ||
2427 | MLX5_SET(tirc, tirc, lro_enable_mask, | |
2428 | MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | | |
2429 | MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); | |
2430 | MLX5_SET(tirc, tirc, lro_max_ip_payload_size, | |
6a9764ef SM |
2431 | (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8); |
2432 | MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout); | |
5c50368f AS |
2433 | } |
2434 | ||
6a9764ef SM |
2435 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params, |
2436 | enum mlx5e_traffic_types tt, | |
7b3722fa | 2437 | void *tirc, bool inner) |
bdfc028d | 2438 | { |
7b3722fa GP |
2439 | void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) : |
2440 | MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | |
a100ff3e GP |
2441 | |
2442 | #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ | |
2443 | MLX5_HASH_FIELD_SEL_DST_IP) | |
2444 | ||
2445 | #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\ | |
2446 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
2447 | MLX5_HASH_FIELD_SEL_L4_SPORT |\ | |
2448 | MLX5_HASH_FIELD_SEL_L4_DPORT) | |
2449 | ||
2450 | #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ | |
2451 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
2452 | MLX5_HASH_FIELD_SEL_IPSEC_SPI) | |
2453 | ||
6a9764ef SM |
2454 | MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc)); |
2455 | if (params->rss_hfunc == ETH_RSS_HASH_TOP) { | |
bdfc028d TT |
2456 | void *rss_key = MLX5_ADDR_OF(tirc, tirc, |
2457 | rx_hash_toeplitz_key); | |
2458 | size_t len = MLX5_FLD_SZ_BYTES(tirc, | |
2459 | rx_hash_toeplitz_key); | |
2460 | ||
2461 | MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); | |
6a9764ef | 2462 | memcpy(rss_key, params->toeplitz_hash_key, len); |
bdfc028d | 2463 | } |
a100ff3e GP |
2464 | |
2465 | switch (tt) { | |
2466 | case MLX5E_TT_IPV4_TCP: | |
2467 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2468 | MLX5_L3_PROT_TYPE_IPV4); | |
2469 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2470 | MLX5_L4_PROT_TYPE_TCP); | |
2471 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2472 | MLX5_HASH_IP_L4PORTS); | |
2473 | break; | |
2474 | ||
2475 | case MLX5E_TT_IPV6_TCP: | |
2476 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2477 | MLX5_L3_PROT_TYPE_IPV6); | |
2478 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2479 | MLX5_L4_PROT_TYPE_TCP); | |
2480 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2481 | MLX5_HASH_IP_L4PORTS); | |
2482 | break; | |
2483 | ||
2484 | case MLX5E_TT_IPV4_UDP: | |
2485 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2486 | MLX5_L3_PROT_TYPE_IPV4); | |
2487 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2488 | MLX5_L4_PROT_TYPE_UDP); | |
2489 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2490 | MLX5_HASH_IP_L4PORTS); | |
2491 | break; | |
2492 | ||
2493 | case MLX5E_TT_IPV6_UDP: | |
2494 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2495 | MLX5_L3_PROT_TYPE_IPV6); | |
2496 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2497 | MLX5_L4_PROT_TYPE_UDP); | |
2498 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2499 | MLX5_HASH_IP_L4PORTS); | |
2500 | break; | |
2501 | ||
2502 | case MLX5E_TT_IPV4_IPSEC_AH: | |
2503 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2504 | MLX5_L3_PROT_TYPE_IPV4); | |
2505 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2506 | MLX5_HASH_IP_IPSEC_SPI); | |
2507 | break; | |
2508 | ||
2509 | case MLX5E_TT_IPV6_IPSEC_AH: | |
2510 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2511 | MLX5_L3_PROT_TYPE_IPV6); | |
2512 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2513 | MLX5_HASH_IP_IPSEC_SPI); | |
2514 | break; | |
2515 | ||
2516 | case MLX5E_TT_IPV4_IPSEC_ESP: | |
2517 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2518 | MLX5_L3_PROT_TYPE_IPV4); | |
2519 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2520 | MLX5_HASH_IP_IPSEC_SPI); | |
2521 | break; | |
2522 | ||
2523 | case MLX5E_TT_IPV6_IPSEC_ESP: | |
2524 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2525 | MLX5_L3_PROT_TYPE_IPV6); | |
2526 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2527 | MLX5_HASH_IP_IPSEC_SPI); | |
2528 | break; | |
2529 | ||
2530 | case MLX5E_TT_IPV4: | |
2531 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2532 | MLX5_L3_PROT_TYPE_IPV4); | |
2533 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2534 | MLX5_HASH_IP); | |
2535 | break; | |
2536 | ||
2537 | case MLX5E_TT_IPV6: | |
2538 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2539 | MLX5_L3_PROT_TYPE_IPV6); | |
2540 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2541 | MLX5_HASH_IP); | |
2542 | break; | |
2543 | default: | |
2544 | WARN_ONCE(true, "%s: bad traffic type!\n", __func__); | |
2545 | } | |
bdfc028d TT |
2546 | } |
2547 | ||
ab0394fe | 2548 | static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv) |
5c50368f AS |
2549 | { |
2550 | struct mlx5_core_dev *mdev = priv->mdev; | |
2551 | ||
2552 | void *in; | |
2553 | void *tirc; | |
2554 | int inlen; | |
2555 | int err; | |
ab0394fe | 2556 | int tt; |
1da36696 | 2557 | int ix; |
5c50368f AS |
2558 | |
2559 | inlen = MLX5_ST_SZ_BYTES(modify_tir_in); | |
1b9a07ee | 2560 | in = kvzalloc(inlen, GFP_KERNEL); |
5c50368f AS |
2561 | if (!in) |
2562 | return -ENOMEM; | |
2563 | ||
2564 | MLX5_SET(modify_tir_in, in, bitmask.lro, 1); | |
2565 | tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx); | |
2566 | ||
6a9764ef | 2567 | mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); |
5c50368f | 2568 | |
1da36696 | 2569 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { |
724b2aa1 | 2570 | err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, |
1da36696 | 2571 | inlen); |
ab0394fe | 2572 | if (err) |
1da36696 | 2573 | goto free_in; |
ab0394fe | 2574 | } |
5c50368f | 2575 | |
6bfd390b | 2576 | for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) { |
1da36696 TT |
2577 | err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, |
2578 | in, inlen); | |
2579 | if (err) | |
2580 | goto free_in; | |
2581 | } | |
2582 | ||
2583 | free_in: | |
5c50368f AS |
2584 | kvfree(in); |
2585 | ||
2586 | return err; | |
2587 | } | |
2588 | ||
7b3722fa GP |
2589 | static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv, |
2590 | enum mlx5e_traffic_types tt, | |
2591 | u32 *tirc) | |
2592 | { | |
2593 | MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); | |
2594 | ||
2595 | mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); | |
2596 | ||
2597 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | |
2598 | MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn); | |
2599 | MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1); | |
2600 | ||
2601 | mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true); | |
2602 | } | |
2603 | ||
472a1e44 TT |
2604 | static int mlx5e_set_mtu(struct mlx5_core_dev *mdev, |
2605 | struct mlx5e_params *params, u16 mtu) | |
40ab6a6e | 2606 | { |
472a1e44 | 2607 | u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu); |
40ab6a6e AS |
2608 | int err; |
2609 | ||
cd255eff | 2610 | err = mlx5_set_port_mtu(mdev, hw_mtu, 1); |
40ab6a6e AS |
2611 | if (err) |
2612 | return err; | |
2613 | ||
cd255eff SM |
2614 | /* Update vport context MTU */ |
2615 | mlx5_modify_nic_vport_mtu(mdev, hw_mtu); | |
2616 | return 0; | |
2617 | } | |
40ab6a6e | 2618 | |
472a1e44 TT |
2619 | static void mlx5e_query_mtu(struct mlx5_core_dev *mdev, |
2620 | struct mlx5e_params *params, u16 *mtu) | |
cd255eff | 2621 | { |
cd255eff SM |
2622 | u16 hw_mtu = 0; |
2623 | int err; | |
40ab6a6e | 2624 | |
cd255eff SM |
2625 | err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu); |
2626 | if (err || !hw_mtu) /* fallback to port oper mtu */ | |
2627 | mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1); | |
2628 | ||
472a1e44 | 2629 | *mtu = MLX5E_HW2SW_MTU(params, hw_mtu); |
cd255eff SM |
2630 | } |
2631 | ||
2e20a151 | 2632 | static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv) |
cd255eff | 2633 | { |
472a1e44 | 2634 | struct mlx5e_params *params = &priv->channels.params; |
2e20a151 | 2635 | struct net_device *netdev = priv->netdev; |
472a1e44 | 2636 | struct mlx5_core_dev *mdev = priv->mdev; |
cd255eff SM |
2637 | u16 mtu; |
2638 | int err; | |
2639 | ||
472a1e44 | 2640 | err = mlx5e_set_mtu(mdev, params, params->sw_mtu); |
cd255eff SM |
2641 | if (err) |
2642 | return err; | |
40ab6a6e | 2643 | |
472a1e44 TT |
2644 | mlx5e_query_mtu(mdev, params, &mtu); |
2645 | if (mtu != params->sw_mtu) | |
cd255eff | 2646 | netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n", |
472a1e44 | 2647 | __func__, mtu, params->sw_mtu); |
40ab6a6e | 2648 | |
472a1e44 | 2649 | params->sw_mtu = mtu; |
40ab6a6e AS |
2650 | return 0; |
2651 | } | |
2652 | ||
08fb1dac SM |
2653 | static void mlx5e_netdev_set_tcs(struct net_device *netdev) |
2654 | { | |
2655 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
6a9764ef SM |
2656 | int nch = priv->channels.params.num_channels; |
2657 | int ntc = priv->channels.params.num_tc; | |
08fb1dac SM |
2658 | int tc; |
2659 | ||
2660 | netdev_reset_tc(netdev); | |
2661 | ||
2662 | if (ntc == 1) | |
2663 | return; | |
2664 | ||
2665 | netdev_set_num_tc(netdev, ntc); | |
2666 | ||
7ccdd084 RS |
2667 | /* Map netdev TCs to offset 0 |
2668 | * We have our own UP to TXQ mapping for QoS | |
2669 | */ | |
08fb1dac | 2670 | for (tc = 0; tc < ntc; tc++) |
7ccdd084 | 2671 | netdev_set_tc_queue(netdev, tc, nch, 0); |
08fb1dac SM |
2672 | } |
2673 | ||
8bfaf07f | 2674 | static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv) |
acc6c595 | 2675 | { |
8bfaf07f | 2676 | int max_nch = priv->profile->max_nch(priv->mdev); |
acc6c595 SM |
2677 | int i, tc; |
2678 | ||
8bfaf07f | 2679 | for (i = 0; i < max_nch; i++) |
acc6c595 | 2680 | for (tc = 0; tc < priv->profile->max_tc; tc++) |
8bfaf07f EBE |
2681 | priv->channel_tc2txq[i][tc] = i + tc * max_nch; |
2682 | } | |
2683 | ||
2684 | static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv) | |
2685 | { | |
2686 | struct mlx5e_channel *c; | |
2687 | struct mlx5e_txqsq *sq; | |
2688 | int i, tc; | |
acc6c595 SM |
2689 | |
2690 | for (i = 0; i < priv->channels.num; i++) { | |
2691 | c = priv->channels.c[i]; | |
2692 | for (tc = 0; tc < c->num_tc; tc++) { | |
2693 | sq = &c->sq[tc]; | |
2694 | priv->txq2sq[sq->txq_ix] = sq; | |
2695 | } | |
2696 | } | |
2697 | } | |
2698 | ||
603f4a45 | 2699 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv) |
acc6c595 | 2700 | { |
9008ae07 SM |
2701 | int num_txqs = priv->channels.num * priv->channels.params.num_tc; |
2702 | struct net_device *netdev = priv->netdev; | |
2703 | ||
2704 | mlx5e_netdev_set_tcs(netdev); | |
053ee0a7 TR |
2705 | netif_set_real_num_tx_queues(netdev, num_txqs); |
2706 | netif_set_real_num_rx_queues(netdev, priv->channels.num); | |
9008ae07 | 2707 | |
8bfaf07f | 2708 | mlx5e_build_tx2sq_maps(priv); |
acc6c595 SM |
2709 | mlx5e_activate_channels(&priv->channels); |
2710 | netif_tx_start_all_queues(priv->netdev); | |
9008ae07 | 2711 | |
a9f7705f | 2712 | if (MLX5_VPORT_MANAGER(priv->mdev)) |
9008ae07 SM |
2713 | mlx5e_add_sqs_fwd_rules(priv); |
2714 | ||
acc6c595 | 2715 | mlx5e_wait_channels_min_rx_wqes(&priv->channels); |
9008ae07 | 2716 | mlx5e_redirect_rqts_to_channels(priv, &priv->channels); |
acc6c595 SM |
2717 | } |
2718 | ||
603f4a45 | 2719 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv) |
acc6c595 | 2720 | { |
9008ae07 SM |
2721 | mlx5e_redirect_rqts_to_drop(priv); |
2722 | ||
a9f7705f | 2723 | if (MLX5_VPORT_MANAGER(priv->mdev)) |
9008ae07 SM |
2724 | mlx5e_remove_sqs_fwd_rules(priv); |
2725 | ||
acc6c595 SM |
2726 | /* FIXME: This is a W/A only for tx timeout watch dog false alarm when |
2727 | * polling for inactive tx queues. | |
2728 | */ | |
2729 | netif_tx_stop_all_queues(priv->netdev); | |
2730 | netif_tx_disable(priv->netdev); | |
2731 | mlx5e_deactivate_channels(&priv->channels); | |
2732 | } | |
2733 | ||
55c2503d | 2734 | void mlx5e_switch_priv_channels(struct mlx5e_priv *priv, |
2e20a151 SM |
2735 | struct mlx5e_channels *new_chs, |
2736 | mlx5e_fp_hw_modify hw_modify) | |
55c2503d SM |
2737 | { |
2738 | struct net_device *netdev = priv->netdev; | |
2739 | int new_num_txqs; | |
7ca42c80 | 2740 | int carrier_ok; |
55c2503d SM |
2741 | new_num_txqs = new_chs->num * new_chs->params.num_tc; |
2742 | ||
7ca42c80 | 2743 | carrier_ok = netif_carrier_ok(netdev); |
55c2503d SM |
2744 | netif_carrier_off(netdev); |
2745 | ||
2746 | if (new_num_txqs < netdev->real_num_tx_queues) | |
2747 | netif_set_real_num_tx_queues(netdev, new_num_txqs); | |
2748 | ||
2749 | mlx5e_deactivate_priv_channels(priv); | |
2750 | mlx5e_close_channels(&priv->channels); | |
2751 | ||
2752 | priv->channels = *new_chs; | |
2753 | ||
2e20a151 SM |
2754 | /* New channels are ready to roll, modify HW settings if needed */ |
2755 | if (hw_modify) | |
2756 | hw_modify(priv); | |
2757 | ||
55c2503d SM |
2758 | mlx5e_refresh_tirs(priv, false); |
2759 | mlx5e_activate_priv_channels(priv); | |
2760 | ||
7ca42c80 ES |
2761 | /* return carrier back if needed */ |
2762 | if (carrier_ok) | |
2763 | netif_carrier_on(netdev); | |
55c2503d SM |
2764 | } |
2765 | ||
237f258c | 2766 | void mlx5e_timestamp_init(struct mlx5e_priv *priv) |
7c39afb3 FD |
2767 | { |
2768 | priv->tstamp.tx_type = HWTSTAMP_TX_OFF; | |
2769 | priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE; | |
2770 | } | |
2771 | ||
40ab6a6e AS |
2772 | int mlx5e_open_locked(struct net_device *netdev) |
2773 | { | |
2774 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
40ab6a6e AS |
2775 | int err; |
2776 | ||
2777 | set_bit(MLX5E_STATE_OPENED, &priv->state); | |
2778 | ||
ff9c852f | 2779 | err = mlx5e_open_channels(priv, &priv->channels); |
acc6c595 | 2780 | if (err) |
343b29f3 | 2781 | goto err_clear_state_opened_flag; |
40ab6a6e | 2782 | |
b676f653 | 2783 | mlx5e_refresh_tirs(priv, false); |
acc6c595 | 2784 | mlx5e_activate_priv_channels(priv); |
7ca42c80 ES |
2785 | if (priv->profile->update_carrier) |
2786 | priv->profile->update_carrier(priv); | |
be4891af | 2787 | |
cb67b832 HHZ |
2788 | if (priv->profile->update_stats) |
2789 | queue_delayed_work(priv->wq, &priv->update_stats_work, 0); | |
40ab6a6e | 2790 | |
9b37b07f | 2791 | return 0; |
343b29f3 AS |
2792 | |
2793 | err_clear_state_opened_flag: | |
2794 | clear_bit(MLX5E_STATE_OPENED, &priv->state); | |
2795 | return err; | |
40ab6a6e AS |
2796 | } |
2797 | ||
cb67b832 | 2798 | int mlx5e_open(struct net_device *netdev) |
40ab6a6e AS |
2799 | { |
2800 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2801 | int err; | |
2802 | ||
2803 | mutex_lock(&priv->state_lock); | |
2804 | err = mlx5e_open_locked(netdev); | |
63bfd399 EBE |
2805 | if (!err) |
2806 | mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP); | |
40ab6a6e AS |
2807 | mutex_unlock(&priv->state_lock); |
2808 | ||
a117f73d SK |
2809 | if (mlx5e_vxlan_allowed(priv->mdev)) |
2810 | udp_tunnel_get_rx_info(netdev); | |
2811 | ||
40ab6a6e AS |
2812 | return err; |
2813 | } | |
2814 | ||
2815 | int mlx5e_close_locked(struct net_device *netdev) | |
2816 | { | |
2817 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2818 | ||
a1985740 AS |
2819 | /* May already be CLOSED in case a previous configuration operation |
2820 | * (e.g RX/TX queue size change) that involves close&open failed. | |
2821 | */ | |
2822 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
2823 | return 0; | |
2824 | ||
40ab6a6e AS |
2825 | clear_bit(MLX5E_STATE_OPENED, &priv->state); |
2826 | ||
40ab6a6e | 2827 | netif_carrier_off(priv->netdev); |
acc6c595 SM |
2828 | mlx5e_deactivate_priv_channels(priv); |
2829 | mlx5e_close_channels(&priv->channels); | |
40ab6a6e AS |
2830 | |
2831 | return 0; | |
2832 | } | |
2833 | ||
cb67b832 | 2834 | int mlx5e_close(struct net_device *netdev) |
40ab6a6e AS |
2835 | { |
2836 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2837 | int err; | |
2838 | ||
26e59d80 MHY |
2839 | if (!netif_device_present(netdev)) |
2840 | return -ENODEV; | |
2841 | ||
40ab6a6e | 2842 | mutex_lock(&priv->state_lock); |
63bfd399 | 2843 | mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN); |
40ab6a6e AS |
2844 | err = mlx5e_close_locked(netdev); |
2845 | mutex_unlock(&priv->state_lock); | |
2846 | ||
2847 | return err; | |
2848 | } | |
2849 | ||
a43b25da | 2850 | static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev, |
3b77235b SM |
2851 | struct mlx5e_rq *rq, |
2852 | struct mlx5e_rq_param *param) | |
40ab6a6e | 2853 | { |
40ab6a6e AS |
2854 | void *rqc = param->rqc; |
2855 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
2856 | int err; | |
2857 | ||
2858 | param->wq.db_numa_node = param->wq.buf_numa_node; | |
2859 | ||
422d4c40 | 2860 | err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq, |
40ab6a6e AS |
2861 | &rq->wq_ctrl); |
2862 | if (err) | |
2863 | return err; | |
2864 | ||
0ddf5432 JDB |
2865 | /* Mark as unused given "Drop-RQ" packets never reach XDP */ |
2866 | xdp_rxq_info_unused(&rq->xdp_rxq); | |
2867 | ||
a43b25da | 2868 | rq->mdev = mdev; |
40ab6a6e AS |
2869 | |
2870 | return 0; | |
2871 | } | |
2872 | ||
a43b25da | 2873 | static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev, |
3b77235b SM |
2874 | struct mlx5e_cq *cq, |
2875 | struct mlx5e_cq_param *param) | |
40ab6a6e | 2876 | { |
2f0db879 GP |
2877 | param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev); |
2878 | param->wq.db_numa_node = dev_to_node(&mdev->pdev->dev); | |
2879 | ||
95b6c6a5 | 2880 | return mlx5e_alloc_cq_common(mdev, param, cq); |
40ab6a6e AS |
2881 | } |
2882 | ||
7cbaf9a3 | 2883 | static int mlx5e_open_drop_rq(struct mlx5e_priv *priv, |
a43b25da | 2884 | struct mlx5e_rq *drop_rq) |
40ab6a6e | 2885 | { |
7cbaf9a3 | 2886 | struct mlx5_core_dev *mdev = priv->mdev; |
a43b25da SM |
2887 | struct mlx5e_cq_param cq_param = {}; |
2888 | struct mlx5e_rq_param rq_param = {}; | |
2889 | struct mlx5e_cq *cq = &drop_rq->cq; | |
40ab6a6e AS |
2890 | int err; |
2891 | ||
7cbaf9a3 | 2892 | mlx5e_build_drop_rq_param(priv, &rq_param); |
40ab6a6e | 2893 | |
a43b25da | 2894 | err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param); |
40ab6a6e AS |
2895 | if (err) |
2896 | return err; | |
2897 | ||
3b77235b | 2898 | err = mlx5e_create_cq(cq, &cq_param); |
40ab6a6e | 2899 | if (err) |
3b77235b | 2900 | goto err_free_cq; |
40ab6a6e | 2901 | |
a43b25da | 2902 | err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param); |
40ab6a6e | 2903 | if (err) |
3b77235b | 2904 | goto err_destroy_cq; |
40ab6a6e | 2905 | |
a43b25da | 2906 | err = mlx5e_create_rq(drop_rq, &rq_param); |
40ab6a6e | 2907 | if (err) |
3b77235b | 2908 | goto err_free_rq; |
40ab6a6e | 2909 | |
7cbaf9a3 MS |
2910 | err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); |
2911 | if (err) | |
2912 | mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err); | |
2913 | ||
40ab6a6e AS |
2914 | return 0; |
2915 | ||
3b77235b | 2916 | err_free_rq: |
a43b25da | 2917 | mlx5e_free_rq(drop_rq); |
40ab6a6e AS |
2918 | |
2919 | err_destroy_cq: | |
a43b25da | 2920 | mlx5e_destroy_cq(cq); |
40ab6a6e | 2921 | |
3b77235b | 2922 | err_free_cq: |
a43b25da | 2923 | mlx5e_free_cq(cq); |
3b77235b | 2924 | |
40ab6a6e AS |
2925 | return err; |
2926 | } | |
2927 | ||
a43b25da | 2928 | static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq) |
40ab6a6e | 2929 | { |
a43b25da SM |
2930 | mlx5e_destroy_rq(drop_rq); |
2931 | mlx5e_free_rq(drop_rq); | |
2932 | mlx5e_destroy_cq(&drop_rq->cq); | |
2933 | mlx5e_free_cq(&drop_rq->cq); | |
40ab6a6e AS |
2934 | } |
2935 | ||
5426a0b2 SM |
2936 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc, |
2937 | u32 underlay_qpn, u32 *tisn) | |
40ab6a6e | 2938 | { |
c4f287c4 | 2939 | u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; |
40ab6a6e AS |
2940 | void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); |
2941 | ||
08fb1dac | 2942 | MLX5_SET(tisc, tisc, prio, tc << 1); |
5426a0b2 | 2943 | MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn); |
b50d292b | 2944 | MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn); |
db60b802 AH |
2945 | |
2946 | if (mlx5_lag_is_lacp_owner(mdev)) | |
2947 | MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1); | |
2948 | ||
5426a0b2 | 2949 | return mlx5_core_create_tis(mdev, in, sizeof(in), tisn); |
40ab6a6e AS |
2950 | } |
2951 | ||
5426a0b2 | 2952 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn) |
40ab6a6e | 2953 | { |
5426a0b2 | 2954 | mlx5_core_destroy_tis(mdev, tisn); |
40ab6a6e AS |
2955 | } |
2956 | ||
cb67b832 | 2957 | int mlx5e_create_tises(struct mlx5e_priv *priv) |
40ab6a6e AS |
2958 | { |
2959 | int err; | |
2960 | int tc; | |
2961 | ||
6bfd390b | 2962 | for (tc = 0; tc < priv->profile->max_tc; tc++) { |
5426a0b2 | 2963 | err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]); |
40ab6a6e AS |
2964 | if (err) |
2965 | goto err_close_tises; | |
2966 | } | |
2967 | ||
2968 | return 0; | |
2969 | ||
2970 | err_close_tises: | |
2971 | for (tc--; tc >= 0; tc--) | |
5426a0b2 | 2972 | mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]); |
40ab6a6e AS |
2973 | |
2974 | return err; | |
2975 | } | |
2976 | ||
cb67b832 | 2977 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv) |
40ab6a6e AS |
2978 | { |
2979 | int tc; | |
2980 | ||
6bfd390b | 2981 | for (tc = 0; tc < priv->profile->max_tc; tc++) |
5426a0b2 | 2982 | mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]); |
40ab6a6e AS |
2983 | } |
2984 | ||
6a9764ef SM |
2985 | static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, |
2986 | enum mlx5e_traffic_types tt, | |
2987 | u32 *tirc) | |
f62b8bb8 | 2988 | { |
b50d292b | 2989 | MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); |
3191e05f | 2990 | |
6a9764ef | 2991 | mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); |
f62b8bb8 | 2992 | |
4cbeaff5 | 2993 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); |
398f3351 | 2994 | MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn); |
7b3722fa | 2995 | mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false); |
f62b8bb8 AV |
2996 | } |
2997 | ||
6a9764ef | 2998 | static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc) |
f62b8bb8 | 2999 | { |
b50d292b | 3000 | MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); |
1da36696 | 3001 | |
6a9764ef | 3002 | mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); |
1da36696 TT |
3003 | |
3004 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | |
3005 | MLX5_SET(tirc, tirc, indirect_table, rqtn); | |
3006 | MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8); | |
3007 | } | |
3008 | ||
8f493ffd | 3009 | int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv) |
1da36696 | 3010 | { |
724b2aa1 | 3011 | struct mlx5e_tir *tir; |
f62b8bb8 AV |
3012 | void *tirc; |
3013 | int inlen; | |
7b3722fa | 3014 | int i = 0; |
f62b8bb8 | 3015 | int err; |
1da36696 | 3016 | u32 *in; |
1da36696 | 3017 | int tt; |
f62b8bb8 AV |
3018 | |
3019 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
1b9a07ee | 3020 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
3021 | if (!in) |
3022 | return -ENOMEM; | |
3023 | ||
1da36696 TT |
3024 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { |
3025 | memset(in, 0, inlen); | |
724b2aa1 | 3026 | tir = &priv->indir_tir[tt]; |
1da36696 | 3027 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); |
6a9764ef | 3028 | mlx5e_build_indir_tir_ctx(priv, tt, tirc); |
724b2aa1 | 3029 | err = mlx5e_create_tir(priv->mdev, tir, in, inlen); |
7b3722fa GP |
3030 | if (err) { |
3031 | mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err); | |
3032 | goto err_destroy_inner_tirs; | |
3033 | } | |
f62b8bb8 AV |
3034 | } |
3035 | ||
7b3722fa GP |
3036 | if (!mlx5e_tunnel_inner_ft_supported(priv->mdev)) |
3037 | goto out; | |
3038 | ||
3039 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) { | |
3040 | memset(in, 0, inlen); | |
3041 | tir = &priv->inner_indir_tir[i]; | |
3042 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
3043 | mlx5e_build_inner_indir_tir_ctx(priv, i, tirc); | |
3044 | err = mlx5e_create_tir(priv->mdev, tir, in, inlen); | |
3045 | if (err) { | |
3046 | mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err); | |
3047 | goto err_destroy_inner_tirs; | |
3048 | } | |
3049 | } | |
3050 | ||
3051 | out: | |
6bfd390b HHZ |
3052 | kvfree(in); |
3053 | ||
3054 | return 0; | |
3055 | ||
7b3722fa GP |
3056 | err_destroy_inner_tirs: |
3057 | for (i--; i >= 0; i--) | |
3058 | mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]); | |
3059 | ||
6bfd390b HHZ |
3060 | for (tt--; tt >= 0; tt--) |
3061 | mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]); | |
3062 | ||
3063 | kvfree(in); | |
3064 | ||
3065 | return err; | |
3066 | } | |
3067 | ||
cb67b832 | 3068 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv) |
6bfd390b HHZ |
3069 | { |
3070 | int nch = priv->profile->max_nch(priv->mdev); | |
3071 | struct mlx5e_tir *tir; | |
3072 | void *tirc; | |
3073 | int inlen; | |
3074 | int err; | |
3075 | u32 *in; | |
3076 | int ix; | |
3077 | ||
3078 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
1b9a07ee | 3079 | in = kvzalloc(inlen, GFP_KERNEL); |
6bfd390b HHZ |
3080 | if (!in) |
3081 | return -ENOMEM; | |
3082 | ||
1da36696 TT |
3083 | for (ix = 0; ix < nch; ix++) { |
3084 | memset(in, 0, inlen); | |
724b2aa1 | 3085 | tir = &priv->direct_tir[ix]; |
1da36696 | 3086 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); |
6a9764ef | 3087 | mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc); |
724b2aa1 | 3088 | err = mlx5e_create_tir(priv->mdev, tir, in, inlen); |
1da36696 TT |
3089 | if (err) |
3090 | goto err_destroy_ch_tirs; | |
3091 | } | |
3092 | ||
3093 | kvfree(in); | |
3094 | ||
f62b8bb8 AV |
3095 | return 0; |
3096 | ||
1da36696 | 3097 | err_destroy_ch_tirs: |
8f493ffd | 3098 | mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err); |
1da36696 | 3099 | for (ix--; ix >= 0; ix--) |
724b2aa1 | 3100 | mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]); |
1da36696 | 3101 | |
1da36696 | 3102 | kvfree(in); |
f62b8bb8 AV |
3103 | |
3104 | return err; | |
3105 | } | |
3106 | ||
8f493ffd | 3107 | void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv) |
f62b8bb8 AV |
3108 | { |
3109 | int i; | |
3110 | ||
1da36696 | 3111 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) |
724b2aa1 | 3112 | mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]); |
7b3722fa GP |
3113 | |
3114 | if (!mlx5e_tunnel_inner_ft_supported(priv->mdev)) | |
3115 | return; | |
3116 | ||
3117 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) | |
3118 | mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]); | |
f62b8bb8 AV |
3119 | } |
3120 | ||
cb67b832 | 3121 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv) |
6bfd390b HHZ |
3122 | { |
3123 | int nch = priv->profile->max_nch(priv->mdev); | |
3124 | int i; | |
3125 | ||
3126 | for (i = 0; i < nch; i++) | |
3127 | mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]); | |
3128 | } | |
3129 | ||
102722fc GE |
3130 | static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable) |
3131 | { | |
3132 | int err = 0; | |
3133 | int i; | |
3134 | ||
3135 | for (i = 0; i < chs->num; i++) { | |
3136 | err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable); | |
3137 | if (err) | |
3138 | return err; | |
3139 | } | |
3140 | ||
3141 | return 0; | |
3142 | } | |
3143 | ||
f6d96a20 | 3144 | static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd) |
36350114 GP |
3145 | { |
3146 | int err = 0; | |
3147 | int i; | |
3148 | ||
ff9c852f SM |
3149 | for (i = 0; i < chs->num; i++) { |
3150 | err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd); | |
36350114 GP |
3151 | if (err) |
3152 | return err; | |
3153 | } | |
3154 | ||
3155 | return 0; | |
3156 | } | |
3157 | ||
0cf0f6d3 JP |
3158 | static int mlx5e_setup_tc_mqprio(struct net_device *netdev, |
3159 | struct tc_mqprio_qopt *mqprio) | |
08fb1dac SM |
3160 | { |
3161 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
6f9485af | 3162 | struct mlx5e_channels new_channels = {}; |
0cf0f6d3 | 3163 | u8 tc = mqprio->num_tc; |
08fb1dac SM |
3164 | int err = 0; |
3165 | ||
0cf0f6d3 JP |
3166 | mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; |
3167 | ||
08fb1dac SM |
3168 | if (tc && tc != MLX5E_MAX_NUM_TC) |
3169 | return -EINVAL; | |
3170 | ||
3171 | mutex_lock(&priv->state_lock); | |
3172 | ||
6f9485af SM |
3173 | new_channels.params = priv->channels.params; |
3174 | new_channels.params.num_tc = tc ? tc : 1; | |
08fb1dac | 3175 | |
20b6a1c7 | 3176 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { |
6f9485af SM |
3177 | priv->channels.params = new_channels.params; |
3178 | goto out; | |
3179 | } | |
08fb1dac | 3180 | |
6f9485af SM |
3181 | err = mlx5e_open_channels(priv, &new_channels); |
3182 | if (err) | |
3183 | goto out; | |
08fb1dac | 3184 | |
05909bab EBE |
3185 | priv->max_opened_tc = max_t(u8, priv->max_opened_tc, |
3186 | new_channels.params.num_tc); | |
2e20a151 | 3187 | mlx5e_switch_priv_channels(priv, &new_channels, NULL); |
6f9485af | 3188 | out: |
08fb1dac | 3189 | mutex_unlock(&priv->state_lock); |
08fb1dac SM |
3190 | return err; |
3191 | } | |
3192 | ||
e80541ec | 3193 | #ifdef CONFIG_MLX5_ESWITCH |
d6c862ba | 3194 | static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv, |
60bd4af8 OG |
3195 | struct tc_cls_flower_offload *cls_flower, |
3196 | int flags) | |
08fb1dac | 3197 | { |
0cf0f6d3 JP |
3198 | switch (cls_flower->command) { |
3199 | case TC_CLSFLOWER_REPLACE: | |
60bd4af8 | 3200 | return mlx5e_configure_flower(priv, cls_flower, flags); |
0cf0f6d3 | 3201 | case TC_CLSFLOWER_DESTROY: |
60bd4af8 | 3202 | return mlx5e_delete_flower(priv, cls_flower, flags); |
0cf0f6d3 | 3203 | case TC_CLSFLOWER_STATS: |
60bd4af8 | 3204 | return mlx5e_stats_flower(priv, cls_flower, flags); |
0cf0f6d3 | 3205 | default: |
a5fcf8a6 | 3206 | return -EOPNOTSUPP; |
0cf0f6d3 JP |
3207 | } |
3208 | } | |
d6c862ba | 3209 | |
60bd4af8 OG |
3210 | static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, |
3211 | void *cb_priv) | |
d6c862ba JP |
3212 | { |
3213 | struct mlx5e_priv *priv = cb_priv; | |
3214 | ||
9ab88e83 | 3215 | if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data)) |
44ae12a7 JP |
3216 | return -EOPNOTSUPP; |
3217 | ||
d6c862ba JP |
3218 | switch (type) { |
3219 | case TC_SETUP_CLSFLOWER: | |
60bd4af8 | 3220 | return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS); |
d6c862ba JP |
3221 | default: |
3222 | return -EOPNOTSUPP; | |
3223 | } | |
3224 | } | |
3225 | ||
3226 | static int mlx5e_setup_tc_block(struct net_device *dev, | |
3227 | struct tc_block_offload *f) | |
3228 | { | |
3229 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3230 | ||
3231 | if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) | |
3232 | return -EOPNOTSUPP; | |
3233 | ||
3234 | switch (f->command) { | |
3235 | case TC_BLOCK_BIND: | |
3236 | return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb, | |
3237 | priv, priv); | |
3238 | case TC_BLOCK_UNBIND: | |
3239 | tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb, | |
3240 | priv); | |
3241 | return 0; | |
3242 | default: | |
3243 | return -EOPNOTSUPP; | |
3244 | } | |
3245 | } | |
e80541ec | 3246 | #endif |
a5fcf8a6 | 3247 | |
9afe9a53 OG |
3248 | static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type, |
3249 | void *type_data) | |
0cf0f6d3 | 3250 | { |
2572ac53 | 3251 | switch (type) { |
fde6af47 | 3252 | #ifdef CONFIG_MLX5_ESWITCH |
d6c862ba JP |
3253 | case TC_SETUP_BLOCK: |
3254 | return mlx5e_setup_tc_block(dev, type_data); | |
fde6af47 | 3255 | #endif |
575ed7d3 | 3256 | case TC_SETUP_QDISC_MQPRIO: |
de4784ca | 3257 | return mlx5e_setup_tc_mqprio(dev, type_data); |
e8f887ac AV |
3258 | default: |
3259 | return -EOPNOTSUPP; | |
3260 | } | |
08fb1dac SM |
3261 | } |
3262 | ||
bc1f4470 | 3263 | static void |
f62b8bb8 AV |
3264 | mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) |
3265 | { | |
3266 | struct mlx5e_priv *priv = netdev_priv(dev); | |
9218b44d | 3267 | struct mlx5e_sw_stats *sstats = &priv->stats.sw; |
f62b8bb8 | 3268 | struct mlx5e_vport_stats *vstats = &priv->stats.vport; |
269e6b3a | 3269 | struct mlx5e_pport_stats *pstats = &priv->stats.pport; |
f62b8bb8 | 3270 | |
370bad0f OG |
3271 | if (mlx5e_is_uplink_rep(priv)) { |
3272 | stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok); | |
3273 | stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok); | |
3274 | stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok); | |
3275 | stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok); | |
3276 | } else { | |
868a01a2 | 3277 | mlx5e_grp_sw_update_stats(priv); |
370bad0f OG |
3278 | stats->rx_packets = sstats->rx_packets; |
3279 | stats->rx_bytes = sstats->rx_bytes; | |
3280 | stats->tx_packets = sstats->tx_packets; | |
3281 | stats->tx_bytes = sstats->tx_bytes; | |
3282 | stats->tx_dropped = sstats->tx_queue_dropped; | |
3283 | } | |
269e6b3a GP |
3284 | |
3285 | stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer; | |
269e6b3a GP |
3286 | |
3287 | stats->rx_length_errors = | |
9218b44d GP |
3288 | PPORT_802_3_GET(pstats, a_in_range_length_errors) + |
3289 | PPORT_802_3_GET(pstats, a_out_of_range_length_field) + | |
3290 | PPORT_802_3_GET(pstats, a_frame_too_long_errors); | |
269e6b3a | 3291 | stats->rx_crc_errors = |
9218b44d GP |
3292 | PPORT_802_3_GET(pstats, a_frame_check_sequence_errors); |
3293 | stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors); | |
3294 | stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards); | |
269e6b3a GP |
3295 | stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + |
3296 | stats->rx_frame_errors; | |
3297 | stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors; | |
3298 | ||
3299 | /* vport multicast also counts packets that are dropped due to steering | |
3300 | * or rx out of buffer | |
3301 | */ | |
9218b44d GP |
3302 | stats->multicast = |
3303 | VPORT_COUNTER_GET(vstats, received_eth_multicast.packets); | |
f62b8bb8 AV |
3304 | } |
3305 | ||
3306 | static void mlx5e_set_rx_mode(struct net_device *dev) | |
3307 | { | |
3308 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3309 | ||
7bb29755 | 3310 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
3311 | } |
3312 | ||
3313 | static int mlx5e_set_mac(struct net_device *netdev, void *addr) | |
3314 | { | |
3315 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3316 | struct sockaddr *saddr = addr; | |
3317 | ||
3318 | if (!is_valid_ether_addr(saddr->sa_data)) | |
3319 | return -EADDRNOTAVAIL; | |
3320 | ||
3321 | netif_addr_lock_bh(netdev); | |
3322 | ether_addr_copy(netdev->dev_addr, saddr->sa_data); | |
3323 | netif_addr_unlock_bh(netdev); | |
3324 | ||
7bb29755 | 3325 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
3326 | |
3327 | return 0; | |
3328 | } | |
3329 | ||
75b81ce7 | 3330 | #define MLX5E_SET_FEATURE(features, feature, enable) \ |
0e405443 GP |
3331 | do { \ |
3332 | if (enable) \ | |
75b81ce7 | 3333 | *features |= feature; \ |
0e405443 | 3334 | else \ |
75b81ce7 | 3335 | *features &= ~feature; \ |
0e405443 GP |
3336 | } while (0) |
3337 | ||
3338 | typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable); | |
3339 | ||
3340 | static int set_feature_lro(struct net_device *netdev, bool enable) | |
f62b8bb8 AV |
3341 | { |
3342 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
619a8f2a | 3343 | struct mlx5_core_dev *mdev = priv->mdev; |
2e20a151 | 3344 | struct mlx5e_channels new_channels = {}; |
619a8f2a | 3345 | struct mlx5e_params *old_params; |
2e20a151 SM |
3346 | int err = 0; |
3347 | bool reset; | |
f62b8bb8 AV |
3348 | |
3349 | mutex_lock(&priv->state_lock); | |
f62b8bb8 | 3350 | |
619a8f2a | 3351 | old_params = &priv->channels.params; |
6c3a823e TT |
3352 | if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) { |
3353 | netdev_warn(netdev, "can't set LRO with legacy RQ\n"); | |
3354 | err = -EINVAL; | |
3355 | goto out; | |
3356 | } | |
3357 | ||
619a8f2a | 3358 | reset = test_bit(MLX5E_STATE_OPENED, &priv->state); |
98e81b0a | 3359 | |
619a8f2a | 3360 | new_channels.params = *old_params; |
2e20a151 SM |
3361 | new_channels.params.lro_en = enable; |
3362 | ||
619a8f2a TT |
3363 | if (old_params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST) { |
3364 | if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) == | |
3365 | mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params)) | |
3366 | reset = false; | |
3367 | } | |
3368 | ||
2e20a151 | 3369 | if (!reset) { |
619a8f2a | 3370 | *old_params = new_channels.params; |
2e20a151 SM |
3371 | err = mlx5e_modify_tirs_lro(priv); |
3372 | goto out; | |
98e81b0a | 3373 | } |
f62b8bb8 | 3374 | |
2e20a151 SM |
3375 | err = mlx5e_open_channels(priv, &new_channels); |
3376 | if (err) | |
3377 | goto out; | |
0e405443 | 3378 | |
2e20a151 SM |
3379 | mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro); |
3380 | out: | |
9b37b07f | 3381 | mutex_unlock(&priv->state_lock); |
0e405443 GP |
3382 | return err; |
3383 | } | |
3384 | ||
2b52a283 | 3385 | static int set_feature_cvlan_filter(struct net_device *netdev, bool enable) |
0e405443 GP |
3386 | { |
3387 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3388 | ||
3389 | if (enable) | |
2b52a283 | 3390 | mlx5e_enable_cvlan_filter(priv); |
0e405443 | 3391 | else |
2b52a283 | 3392 | mlx5e_disable_cvlan_filter(priv); |
0e405443 GP |
3393 | |
3394 | return 0; | |
3395 | } | |
3396 | ||
3397 | static int set_feature_tc_num_filters(struct net_device *netdev, bool enable) | |
3398 | { | |
3399 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
f62b8bb8 | 3400 | |
0e405443 | 3401 | if (!enable && mlx5e_tc_num_filters(priv)) { |
e8f887ac AV |
3402 | netdev_err(netdev, |
3403 | "Active offloaded tc filters, can't turn hw_tc_offload off\n"); | |
3404 | return -EINVAL; | |
3405 | } | |
3406 | ||
0e405443 GP |
3407 | return 0; |
3408 | } | |
3409 | ||
94cb1ebb EBE |
3410 | static int set_feature_rx_all(struct net_device *netdev, bool enable) |
3411 | { | |
3412 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3413 | struct mlx5_core_dev *mdev = priv->mdev; | |
3414 | ||
3415 | return mlx5_set_port_fcs(mdev, !enable); | |
3416 | } | |
3417 | ||
102722fc GE |
3418 | static int set_feature_rx_fcs(struct net_device *netdev, bool enable) |
3419 | { | |
3420 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3421 | int err; | |
3422 | ||
3423 | mutex_lock(&priv->state_lock); | |
3424 | ||
3425 | priv->channels.params.scatter_fcs_en = enable; | |
3426 | err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable); | |
3427 | if (err) | |
3428 | priv->channels.params.scatter_fcs_en = !enable; | |
3429 | ||
3430 | mutex_unlock(&priv->state_lock); | |
3431 | ||
3432 | return err; | |
3433 | } | |
3434 | ||
36350114 GP |
3435 | static int set_feature_rx_vlan(struct net_device *netdev, bool enable) |
3436 | { | |
3437 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
ff9c852f | 3438 | int err = 0; |
36350114 GP |
3439 | |
3440 | mutex_lock(&priv->state_lock); | |
3441 | ||
6a9764ef | 3442 | priv->channels.params.vlan_strip_disable = !enable; |
ff9c852f SM |
3443 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) |
3444 | goto unlock; | |
3445 | ||
3446 | err = mlx5e_modify_channels_vsd(&priv->channels, !enable); | |
36350114 | 3447 | if (err) |
6a9764ef | 3448 | priv->channels.params.vlan_strip_disable = enable; |
36350114 | 3449 | |
ff9c852f | 3450 | unlock: |
36350114 GP |
3451 | mutex_unlock(&priv->state_lock); |
3452 | ||
3453 | return err; | |
3454 | } | |
3455 | ||
45bf454a MG |
3456 | #ifdef CONFIG_RFS_ACCEL |
3457 | static int set_feature_arfs(struct net_device *netdev, bool enable) | |
3458 | { | |
3459 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3460 | int err; | |
3461 | ||
3462 | if (enable) | |
3463 | err = mlx5e_arfs_enable(priv); | |
3464 | else | |
3465 | err = mlx5e_arfs_disable(priv); | |
3466 | ||
3467 | return err; | |
3468 | } | |
3469 | #endif | |
3470 | ||
0e405443 | 3471 | static int mlx5e_handle_feature(struct net_device *netdev, |
75b81ce7 | 3472 | netdev_features_t *features, |
0e405443 GP |
3473 | netdev_features_t wanted_features, |
3474 | netdev_features_t feature, | |
3475 | mlx5e_feature_handler feature_handler) | |
3476 | { | |
3477 | netdev_features_t changes = wanted_features ^ netdev->features; | |
3478 | bool enable = !!(wanted_features & feature); | |
3479 | int err; | |
3480 | ||
3481 | if (!(changes & feature)) | |
3482 | return 0; | |
3483 | ||
3484 | err = feature_handler(netdev, enable); | |
3485 | if (err) { | |
b20eab15 GP |
3486 | netdev_err(netdev, "%s feature %pNF failed, err %d\n", |
3487 | enable ? "Enable" : "Disable", &feature, err); | |
0e405443 GP |
3488 | return err; |
3489 | } | |
3490 | ||
75b81ce7 | 3491 | MLX5E_SET_FEATURE(features, feature, enable); |
0e405443 GP |
3492 | return 0; |
3493 | } | |
3494 | ||
3495 | static int mlx5e_set_features(struct net_device *netdev, | |
3496 | netdev_features_t features) | |
3497 | { | |
75b81ce7 | 3498 | netdev_features_t oper_features = netdev->features; |
be0f780b GP |
3499 | int err = 0; |
3500 | ||
3501 | #define MLX5E_HANDLE_FEATURE(feature, handler) \ | |
3502 | mlx5e_handle_feature(netdev, &oper_features, features, feature, handler) | |
0e405443 | 3503 | |
be0f780b GP |
3504 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro); |
3505 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER, | |
2b52a283 | 3506 | set_feature_cvlan_filter); |
be0f780b GP |
3507 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters); |
3508 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all); | |
3509 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs); | |
3510 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan); | |
45bf454a | 3511 | #ifdef CONFIG_RFS_ACCEL |
be0f780b | 3512 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs); |
45bf454a | 3513 | #endif |
0e405443 | 3514 | |
75b81ce7 GP |
3515 | if (err) { |
3516 | netdev->features = oper_features; | |
3517 | return -EINVAL; | |
3518 | } | |
3519 | ||
3520 | return 0; | |
f62b8bb8 AV |
3521 | } |
3522 | ||
7d92d580 GP |
3523 | static netdev_features_t mlx5e_fix_features(struct net_device *netdev, |
3524 | netdev_features_t features) | |
3525 | { | |
3526 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
6c3a823e | 3527 | struct mlx5e_params *params; |
7d92d580 GP |
3528 | |
3529 | mutex_lock(&priv->state_lock); | |
6c3a823e | 3530 | params = &priv->channels.params; |
7d92d580 GP |
3531 | if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) { |
3532 | /* HW strips the outer C-tag header, this is a problem | |
3533 | * for S-tag traffic. | |
3534 | */ | |
3535 | features &= ~NETIF_F_HW_VLAN_CTAG_RX; | |
6c3a823e | 3536 | if (!params->vlan_strip_disable) |
7d92d580 GP |
3537 | netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n"); |
3538 | } | |
6c3a823e TT |
3539 | if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) { |
3540 | features &= ~NETIF_F_LRO; | |
3541 | if (params->lro_en) | |
3542 | netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n"); | |
3543 | } | |
3544 | ||
7d92d580 GP |
3545 | mutex_unlock(&priv->state_lock); |
3546 | ||
3547 | return features; | |
3548 | } | |
3549 | ||
250a42b6 AN |
3550 | int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, |
3551 | change_hw_mtu_cb set_mtu_cb) | |
f62b8bb8 AV |
3552 | { |
3553 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2e20a151 | 3554 | struct mlx5e_channels new_channels = {}; |
472a1e44 | 3555 | struct mlx5e_params *params; |
98e81b0a | 3556 | int err = 0; |
506753b0 | 3557 | bool reset; |
f62b8bb8 | 3558 | |
f62b8bb8 | 3559 | mutex_lock(&priv->state_lock); |
98e81b0a | 3560 | |
472a1e44 | 3561 | params = &priv->channels.params; |
506753b0 | 3562 | |
73281b78 | 3563 | reset = !params->lro_en; |
2e20a151 | 3564 | reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state); |
98e81b0a | 3565 | |
73281b78 TT |
3566 | new_channels.params = *params; |
3567 | new_channels.params.sw_mtu = new_mtu; | |
3568 | ||
3569 | if (params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST) { | |
3570 | u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params); | |
3571 | u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params); | |
3572 | ||
3573 | reset = reset && (ppw_old != ppw_new); | |
3574 | } | |
3575 | ||
2e20a151 | 3576 | if (!reset) { |
472a1e44 | 3577 | params->sw_mtu = new_mtu; |
250a42b6 | 3578 | set_mtu_cb(priv); |
472a1e44 | 3579 | netdev->mtu = params->sw_mtu; |
2e20a151 SM |
3580 | goto out; |
3581 | } | |
98e81b0a | 3582 | |
2e20a151 | 3583 | err = mlx5e_open_channels(priv, &new_channels); |
472a1e44 | 3584 | if (err) |
2e20a151 | 3585 | goto out; |
2e20a151 | 3586 | |
250a42b6 | 3587 | mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb); |
472a1e44 | 3588 | netdev->mtu = new_channels.params.sw_mtu; |
f62b8bb8 | 3589 | |
2e20a151 SM |
3590 | out: |
3591 | mutex_unlock(&priv->state_lock); | |
f62b8bb8 AV |
3592 | return err; |
3593 | } | |
3594 | ||
250a42b6 AN |
3595 | static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu) |
3596 | { | |
3597 | return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu); | |
3598 | } | |
3599 | ||
7c39afb3 FD |
3600 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr) |
3601 | { | |
3602 | struct hwtstamp_config config; | |
3603 | int err; | |
3604 | ||
3605 | if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz)) | |
3606 | return -EOPNOTSUPP; | |
3607 | ||
3608 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
3609 | return -EFAULT; | |
3610 | ||
3611 | /* TX HW timestamp */ | |
3612 | switch (config.tx_type) { | |
3613 | case HWTSTAMP_TX_OFF: | |
3614 | case HWTSTAMP_TX_ON: | |
3615 | break; | |
3616 | default: | |
3617 | return -ERANGE; | |
3618 | } | |
3619 | ||
3620 | mutex_lock(&priv->state_lock); | |
3621 | /* RX HW timestamp */ | |
3622 | switch (config.rx_filter) { | |
3623 | case HWTSTAMP_FILTER_NONE: | |
3624 | /* Reset CQE compression to Admin default */ | |
3625 | mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def); | |
3626 | break; | |
3627 | case HWTSTAMP_FILTER_ALL: | |
3628 | case HWTSTAMP_FILTER_SOME: | |
3629 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
3630 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
3631 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
3632 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
3633 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
3634 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
3635 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
3636 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
3637 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
3638 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
3639 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
3640 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
3641 | case HWTSTAMP_FILTER_NTP_ALL: | |
3642 | /* Disable CQE compression */ | |
3643 | netdev_warn(priv->netdev, "Disabling cqe compression"); | |
3644 | err = mlx5e_modify_rx_cqe_compression_locked(priv, false); | |
3645 | if (err) { | |
3646 | netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err); | |
3647 | mutex_unlock(&priv->state_lock); | |
3648 | return err; | |
3649 | } | |
3650 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
3651 | break; | |
3652 | default: | |
3653 | mutex_unlock(&priv->state_lock); | |
3654 | return -ERANGE; | |
3655 | } | |
3656 | ||
3657 | memcpy(&priv->tstamp, &config, sizeof(config)); | |
3658 | mutex_unlock(&priv->state_lock); | |
3659 | ||
3660 | return copy_to_user(ifr->ifr_data, &config, | |
3661 | sizeof(config)) ? -EFAULT : 0; | |
3662 | } | |
3663 | ||
3664 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr) | |
3665 | { | |
3666 | struct hwtstamp_config *cfg = &priv->tstamp; | |
3667 | ||
3668 | if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz)) | |
3669 | return -EOPNOTSUPP; | |
3670 | ||
3671 | return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0; | |
3672 | } | |
3673 | ||
ef9814de EBE |
3674 | static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
3675 | { | |
1170fbd8 FD |
3676 | struct mlx5e_priv *priv = netdev_priv(dev); |
3677 | ||
ef9814de EBE |
3678 | switch (cmd) { |
3679 | case SIOCSHWTSTAMP: | |
1170fbd8 | 3680 | return mlx5e_hwstamp_set(priv, ifr); |
ef9814de | 3681 | case SIOCGHWTSTAMP: |
1170fbd8 | 3682 | return mlx5e_hwstamp_get(priv, ifr); |
ef9814de EBE |
3683 | default: |
3684 | return -EOPNOTSUPP; | |
3685 | } | |
3686 | } | |
3687 | ||
e80541ec | 3688 | #ifdef CONFIG_MLX5_ESWITCH |
66e49ded SM |
3689 | static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac) |
3690 | { | |
3691 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3692 | struct mlx5_core_dev *mdev = priv->mdev; | |
3693 | ||
3694 | return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac); | |
3695 | } | |
3696 | ||
79aab093 MS |
3697 | static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos, |
3698 | __be16 vlan_proto) | |
66e49ded SM |
3699 | { |
3700 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3701 | struct mlx5_core_dev *mdev = priv->mdev; | |
3702 | ||
79aab093 MS |
3703 | if (vlan_proto != htons(ETH_P_8021Q)) |
3704 | return -EPROTONOSUPPORT; | |
3705 | ||
66e49ded SM |
3706 | return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1, |
3707 | vlan, qos); | |
3708 | } | |
3709 | ||
f942380c MHY |
3710 | static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting) |
3711 | { | |
3712 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3713 | struct mlx5_core_dev *mdev = priv->mdev; | |
3714 | ||
3715 | return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting); | |
3716 | } | |
3717 | ||
1edc57e2 MHY |
3718 | static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting) |
3719 | { | |
3720 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3721 | struct mlx5_core_dev *mdev = priv->mdev; | |
3722 | ||
3723 | return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting); | |
3724 | } | |
bd77bf1c MHY |
3725 | |
3726 | static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, | |
3727 | int max_tx_rate) | |
3728 | { | |
3729 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3730 | struct mlx5_core_dev *mdev = priv->mdev; | |
3731 | ||
bd77bf1c | 3732 | return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1, |
c9497c98 | 3733 | max_tx_rate, min_tx_rate); |
bd77bf1c MHY |
3734 | } |
3735 | ||
66e49ded SM |
3736 | static int mlx5_vport_link2ifla(u8 esw_link) |
3737 | { | |
3738 | switch (esw_link) { | |
3739 | case MLX5_ESW_VPORT_ADMIN_STATE_DOWN: | |
3740 | return IFLA_VF_LINK_STATE_DISABLE; | |
3741 | case MLX5_ESW_VPORT_ADMIN_STATE_UP: | |
3742 | return IFLA_VF_LINK_STATE_ENABLE; | |
3743 | } | |
3744 | return IFLA_VF_LINK_STATE_AUTO; | |
3745 | } | |
3746 | ||
3747 | static int mlx5_ifla_link2vport(u8 ifla_link) | |
3748 | { | |
3749 | switch (ifla_link) { | |
3750 | case IFLA_VF_LINK_STATE_DISABLE: | |
3751 | return MLX5_ESW_VPORT_ADMIN_STATE_DOWN; | |
3752 | case IFLA_VF_LINK_STATE_ENABLE: | |
3753 | return MLX5_ESW_VPORT_ADMIN_STATE_UP; | |
3754 | } | |
3755 | return MLX5_ESW_VPORT_ADMIN_STATE_AUTO; | |
3756 | } | |
3757 | ||
3758 | static int mlx5e_set_vf_link_state(struct net_device *dev, int vf, | |
3759 | int link_state) | |
3760 | { | |
3761 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3762 | struct mlx5_core_dev *mdev = priv->mdev; | |
3763 | ||
3764 | return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1, | |
3765 | mlx5_ifla_link2vport(link_state)); | |
3766 | } | |
3767 | ||
3768 | static int mlx5e_get_vf_config(struct net_device *dev, | |
3769 | int vf, struct ifla_vf_info *ivi) | |
3770 | { | |
3771 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3772 | struct mlx5_core_dev *mdev = priv->mdev; | |
3773 | int err; | |
3774 | ||
3775 | err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi); | |
3776 | if (err) | |
3777 | return err; | |
3778 | ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate); | |
3779 | return 0; | |
3780 | } | |
3781 | ||
3782 | static int mlx5e_get_vf_stats(struct net_device *dev, | |
3783 | int vf, struct ifla_vf_stats *vf_stats) | |
3784 | { | |
3785 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3786 | struct mlx5_core_dev *mdev = priv->mdev; | |
3787 | ||
3788 | return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1, | |
3789 | vf_stats); | |
3790 | } | |
e80541ec | 3791 | #endif |
66e49ded | 3792 | |
1ad9a00a PB |
3793 | static void mlx5e_add_vxlan_port(struct net_device *netdev, |
3794 | struct udp_tunnel_info *ti) | |
b3f63c3d MF |
3795 | { |
3796 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3797 | ||
974c3f30 AD |
3798 | if (ti->type != UDP_TUNNEL_TYPE_VXLAN) |
3799 | return; | |
3800 | ||
b3f63c3d MF |
3801 | if (!mlx5e_vxlan_allowed(priv->mdev)) |
3802 | return; | |
3803 | ||
974c3f30 | 3804 | mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1); |
b3f63c3d MF |
3805 | } |
3806 | ||
1ad9a00a PB |
3807 | static void mlx5e_del_vxlan_port(struct net_device *netdev, |
3808 | struct udp_tunnel_info *ti) | |
b3f63c3d MF |
3809 | { |
3810 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3811 | ||
974c3f30 AD |
3812 | if (ti->type != UDP_TUNNEL_TYPE_VXLAN) |
3813 | return; | |
3814 | ||
b3f63c3d MF |
3815 | if (!mlx5e_vxlan_allowed(priv->mdev)) |
3816 | return; | |
3817 | ||
974c3f30 | 3818 | mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0); |
b3f63c3d MF |
3819 | } |
3820 | ||
27299841 GP |
3821 | static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv, |
3822 | struct sk_buff *skb, | |
3823 | netdev_features_t features) | |
b3f63c3d | 3824 | { |
2989ad1e | 3825 | unsigned int offset = 0; |
b3f63c3d | 3826 | struct udphdr *udph; |
27299841 GP |
3827 | u8 proto; |
3828 | u16 port; | |
b3f63c3d MF |
3829 | |
3830 | switch (vlan_get_protocol(skb)) { | |
3831 | case htons(ETH_P_IP): | |
3832 | proto = ip_hdr(skb)->protocol; | |
3833 | break; | |
3834 | case htons(ETH_P_IPV6): | |
2989ad1e | 3835 | proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL); |
b3f63c3d MF |
3836 | break; |
3837 | default: | |
3838 | goto out; | |
3839 | } | |
3840 | ||
27299841 GP |
3841 | switch (proto) { |
3842 | case IPPROTO_GRE: | |
3843 | return features; | |
3844 | case IPPROTO_UDP: | |
b3f63c3d MF |
3845 | udph = udp_hdr(skb); |
3846 | port = be16_to_cpu(udph->dest); | |
b3f63c3d | 3847 | |
27299841 GP |
3848 | /* Verify if UDP port is being offloaded by HW */ |
3849 | if (mlx5e_vxlan_lookup_port(priv, port)) | |
3850 | return features; | |
3851 | } | |
b3f63c3d MF |
3852 | |
3853 | out: | |
3854 | /* Disable CSUM and GSO if the udp dport is not offloaded by HW */ | |
3855 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
3856 | } | |
3857 | ||
3858 | static netdev_features_t mlx5e_features_check(struct sk_buff *skb, | |
3859 | struct net_device *netdev, | |
3860 | netdev_features_t features) | |
3861 | { | |
3862 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3863 | ||
3864 | features = vlan_features_check(skb, features); | |
3865 | features = vxlan_features_check(skb, features); | |
3866 | ||
2ac9cfe7 IT |
3867 | #ifdef CONFIG_MLX5_EN_IPSEC |
3868 | if (mlx5e_ipsec_feature_check(skb, netdev, features)) | |
3869 | return features; | |
3870 | #endif | |
3871 | ||
b3f63c3d MF |
3872 | /* Validate if the tunneled packet is being offloaded by HW */ |
3873 | if (skb->encapsulation && | |
3874 | (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK)) | |
27299841 | 3875 | return mlx5e_tunnel_features_check(priv, skb, features); |
b3f63c3d MF |
3876 | |
3877 | return features; | |
3878 | } | |
3879 | ||
7ca560b5 EBE |
3880 | static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev, |
3881 | struct mlx5e_txqsq *sq) | |
3882 | { | |
7b2117bb | 3883 | struct mlx5_eq *eq = sq->cq.mcq.eq; |
7ca560b5 EBE |
3884 | u32 eqe_count; |
3885 | ||
7ca560b5 | 3886 | netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n", |
7b2117bb | 3887 | eq->eqn, eq->cons_index, eq->irqn); |
7ca560b5 EBE |
3888 | |
3889 | eqe_count = mlx5_eq_poll_irq_disabled(eq); | |
3890 | if (!eqe_count) | |
3891 | return false; | |
3892 | ||
3893 | netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn); | |
05909bab | 3894 | sq->channel->stats->eq_rearm++; |
7ca560b5 EBE |
3895 | return true; |
3896 | } | |
3897 | ||
bfc647d5 | 3898 | static void mlx5e_tx_timeout_work(struct work_struct *work) |
3947ca18 | 3899 | { |
bfc647d5 EBE |
3900 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, |
3901 | tx_timeout_work); | |
3902 | struct net_device *dev = priv->netdev; | |
7ca560b5 | 3903 | bool reopen_channels = false; |
bfc647d5 | 3904 | int i, err; |
3947ca18 | 3905 | |
bfc647d5 EBE |
3906 | rtnl_lock(); |
3907 | mutex_lock(&priv->state_lock); | |
3908 | ||
3909 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
3910 | goto unlock; | |
3947ca18 | 3911 | |
6a9764ef | 3912 | for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) { |
84990945 | 3913 | struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i); |
acc6c595 | 3914 | struct mlx5e_txqsq *sq = priv->txq2sq[i]; |
3947ca18 | 3915 | |
84990945 | 3916 | if (!netif_xmit_stopped(dev_queue)) |
3947ca18 | 3917 | continue; |
bfc647d5 EBE |
3918 | |
3919 | netdev_err(dev, | |
3920 | "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n", | |
84990945 EBE |
3921 | i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc, |
3922 | jiffies_to_usecs(jiffies - dev_queue->trans_start)); | |
3a32b26a | 3923 | |
7ca560b5 EBE |
3924 | /* If we recover a lost interrupt, most likely TX timeout will |
3925 | * be resolved, skip reopening channels | |
3926 | */ | |
3927 | if (!mlx5e_tx_timeout_eq_recover(dev, sq)) { | |
3928 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
3929 | reopen_channels = true; | |
3930 | } | |
3947ca18 DJ |
3931 | } |
3932 | ||
bfc647d5 EBE |
3933 | if (!reopen_channels) |
3934 | goto unlock; | |
3935 | ||
3936 | mlx5e_close_locked(dev); | |
3937 | err = mlx5e_open_locked(dev); | |
3938 | if (err) | |
3939 | netdev_err(priv->netdev, | |
3940 | "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n", | |
3941 | err); | |
3942 | ||
3943 | unlock: | |
3944 | mutex_unlock(&priv->state_lock); | |
3945 | rtnl_unlock(); | |
3946 | } | |
3947 | ||
3948 | static void mlx5e_tx_timeout(struct net_device *dev) | |
3949 | { | |
3950 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3951 | ||
3952 | netdev_err(dev, "TX timeout detected\n"); | |
3953 | queue_work(priv->wq, &priv->tx_timeout_work); | |
3947ca18 DJ |
3954 | } |
3955 | ||
86994156 RS |
3956 | static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog) |
3957 | { | |
3958 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3959 | struct bpf_prog *old_prog; | |
3960 | int err = 0; | |
3961 | bool reset, was_opened; | |
3962 | int i; | |
3963 | ||
3964 | mutex_lock(&priv->state_lock); | |
3965 | ||
3966 | if ((netdev->features & NETIF_F_LRO) && prog) { | |
3967 | netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n"); | |
3968 | err = -EINVAL; | |
3969 | goto unlock; | |
3970 | } | |
3971 | ||
547eede0 IT |
3972 | if ((netdev->features & NETIF_F_HW_ESP) && prog) { |
3973 | netdev_warn(netdev, "can't set XDP with IPSec offload\n"); | |
3974 | err = -EINVAL; | |
3975 | goto unlock; | |
3976 | } | |
3977 | ||
86994156 RS |
3978 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); |
3979 | /* no need for full reset when exchanging programs */ | |
6a9764ef | 3980 | reset = (!priv->channels.params.xdp_prog || !prog); |
86994156 RS |
3981 | |
3982 | if (was_opened && reset) | |
3983 | mlx5e_close_locked(netdev); | |
c54c0629 DB |
3984 | if (was_opened && !reset) { |
3985 | /* num_channels is invariant here, so we can take the | |
3986 | * batched reference right upfront. | |
3987 | */ | |
6a9764ef | 3988 | prog = bpf_prog_add(prog, priv->channels.num); |
c54c0629 DB |
3989 | if (IS_ERR(prog)) { |
3990 | err = PTR_ERR(prog); | |
3991 | goto unlock; | |
3992 | } | |
3993 | } | |
86994156 | 3994 | |
c54c0629 DB |
3995 | /* exchange programs, extra prog reference we got from caller |
3996 | * as long as we don't fail from this point onwards. | |
3997 | */ | |
6a9764ef | 3998 | old_prog = xchg(&priv->channels.params.xdp_prog, prog); |
86994156 RS |
3999 | if (old_prog) |
4000 | bpf_prog_put(old_prog); | |
4001 | ||
4002 | if (reset) /* change RQ type according to priv->xdp_prog */ | |
2a0f561b | 4003 | mlx5e_set_rq_type(priv->mdev, &priv->channels.params); |
86994156 RS |
4004 | |
4005 | if (was_opened && reset) | |
4006 | mlx5e_open_locked(netdev); | |
4007 | ||
4008 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset) | |
4009 | goto unlock; | |
4010 | ||
4011 | /* exchanging programs w/o reset, we update ref counts on behalf | |
4012 | * of the channels RQs here. | |
4013 | */ | |
ff9c852f SM |
4014 | for (i = 0; i < priv->channels.num; i++) { |
4015 | struct mlx5e_channel *c = priv->channels.c[i]; | |
86994156 | 4016 | |
c0f1147d | 4017 | clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state); |
86994156 RS |
4018 | napi_synchronize(&c->napi); |
4019 | /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */ | |
4020 | ||
4021 | old_prog = xchg(&c->rq.xdp_prog, prog); | |
4022 | ||
c0f1147d | 4023 | set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state); |
86994156 | 4024 | /* napi_schedule in case we have missed anything */ |
86994156 RS |
4025 | napi_schedule(&c->napi); |
4026 | ||
4027 | if (old_prog) | |
4028 | bpf_prog_put(old_prog); | |
4029 | } | |
4030 | ||
4031 | unlock: | |
4032 | mutex_unlock(&priv->state_lock); | |
4033 | return err; | |
4034 | } | |
4035 | ||
821b2e29 | 4036 | static u32 mlx5e_xdp_query(struct net_device *dev) |
86994156 RS |
4037 | { |
4038 | struct mlx5e_priv *priv = netdev_priv(dev); | |
821b2e29 MKL |
4039 | const struct bpf_prog *xdp_prog; |
4040 | u32 prog_id = 0; | |
86994156 | 4041 | |
821b2e29 MKL |
4042 | mutex_lock(&priv->state_lock); |
4043 | xdp_prog = priv->channels.params.xdp_prog; | |
4044 | if (xdp_prog) | |
4045 | prog_id = xdp_prog->aux->id; | |
4046 | mutex_unlock(&priv->state_lock); | |
4047 | ||
4048 | return prog_id; | |
86994156 RS |
4049 | } |
4050 | ||
f4e63525 | 4051 | static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp) |
86994156 RS |
4052 | { |
4053 | switch (xdp->command) { | |
4054 | case XDP_SETUP_PROG: | |
4055 | return mlx5e_xdp_set(dev, xdp->prog); | |
4056 | case XDP_QUERY_PROG: | |
821b2e29 MKL |
4057 | xdp->prog_id = mlx5e_xdp_query(dev); |
4058 | xdp->prog_attached = !!xdp->prog_id; | |
86994156 RS |
4059 | return 0; |
4060 | default: | |
4061 | return -EINVAL; | |
4062 | } | |
4063 | } | |
4064 | ||
80378384 CO |
4065 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4066 | /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without | |
4067 | * reenabling interrupts. | |
4068 | */ | |
4069 | static void mlx5e_netpoll(struct net_device *dev) | |
4070 | { | |
4071 | struct mlx5e_priv *priv = netdev_priv(dev); | |
ff9c852f SM |
4072 | struct mlx5e_channels *chs = &priv->channels; |
4073 | ||
80378384 CO |
4074 | int i; |
4075 | ||
ff9c852f SM |
4076 | for (i = 0; i < chs->num; i++) |
4077 | napi_schedule(&chs->c[i]->napi); | |
80378384 CO |
4078 | } |
4079 | #endif | |
4080 | ||
e80541ec | 4081 | static const struct net_device_ops mlx5e_netdev_ops = { |
f62b8bb8 AV |
4082 | .ndo_open = mlx5e_open, |
4083 | .ndo_stop = mlx5e_close, | |
4084 | .ndo_start_xmit = mlx5e_xmit, | |
0cf0f6d3 | 4085 | .ndo_setup_tc = mlx5e_setup_tc, |
08fb1dac | 4086 | .ndo_select_queue = mlx5e_select_queue, |
f62b8bb8 AV |
4087 | .ndo_get_stats64 = mlx5e_get_stats, |
4088 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
4089 | .ndo_set_mac_address = mlx5e_set_mac, | |
b0eed40e SM |
4090 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, |
4091 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
f62b8bb8 | 4092 | .ndo_set_features = mlx5e_set_features, |
7d92d580 | 4093 | .ndo_fix_features = mlx5e_fix_features, |
250a42b6 | 4094 | .ndo_change_mtu = mlx5e_change_nic_mtu, |
b0eed40e | 4095 | .ndo_do_ioctl = mlx5e_ioctl, |
507f0c81 | 4096 | .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate, |
706b3583 SM |
4097 | .ndo_udp_tunnel_add = mlx5e_add_vxlan_port, |
4098 | .ndo_udp_tunnel_del = mlx5e_del_vxlan_port, | |
4099 | .ndo_features_check = mlx5e_features_check, | |
45bf454a MG |
4100 | #ifdef CONFIG_RFS_ACCEL |
4101 | .ndo_rx_flow_steer = mlx5e_rx_flow_steer, | |
4102 | #endif | |
3947ca18 | 4103 | .ndo_tx_timeout = mlx5e_tx_timeout, |
f4e63525 | 4104 | .ndo_bpf = mlx5e_xdp, |
80378384 CO |
4105 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4106 | .ndo_poll_controller = mlx5e_netpoll, | |
4107 | #endif | |
e80541ec | 4108 | #ifdef CONFIG_MLX5_ESWITCH |
706b3583 | 4109 | /* SRIOV E-Switch NDOs */ |
b0eed40e SM |
4110 | .ndo_set_vf_mac = mlx5e_set_vf_mac, |
4111 | .ndo_set_vf_vlan = mlx5e_set_vf_vlan, | |
f942380c | 4112 | .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk, |
1edc57e2 | 4113 | .ndo_set_vf_trust = mlx5e_set_vf_trust, |
bd77bf1c | 4114 | .ndo_set_vf_rate = mlx5e_set_vf_rate, |
b0eed40e SM |
4115 | .ndo_get_vf_config = mlx5e_get_vf_config, |
4116 | .ndo_set_vf_link_state = mlx5e_set_vf_link_state, | |
4117 | .ndo_get_vf_stats = mlx5e_get_vf_stats, | |
370bad0f OG |
4118 | .ndo_has_offload_stats = mlx5e_has_offload_stats, |
4119 | .ndo_get_offload_stats = mlx5e_get_offload_stats, | |
e80541ec | 4120 | #endif |
f62b8bb8 AV |
4121 | }; |
4122 | ||
4123 | static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) | |
4124 | { | |
4125 | if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
9eb78923 | 4126 | return -EOPNOTSUPP; |
f62b8bb8 AV |
4127 | if (!MLX5_CAP_GEN(mdev, eth_net_offloads) || |
4128 | !MLX5_CAP_GEN(mdev, nic_flow_table) || | |
4129 | !MLX5_CAP_ETH(mdev, csum_cap) || | |
4130 | !MLX5_CAP_ETH(mdev, max_lso_cap) || | |
4131 | !MLX5_CAP_ETH(mdev, vlan_cap) || | |
796a27ec GP |
4132 | !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) || |
4133 | MLX5_CAP_FLOWTABLE(mdev, | |
4134 | flow_table_properties_nic_receive.max_ft_level) | |
4135 | < 3) { | |
f62b8bb8 AV |
4136 | mlx5_core_warn(mdev, |
4137 | "Not creating net device, some required device capabilities are missing\n"); | |
9eb78923 | 4138 | return -EOPNOTSUPP; |
f62b8bb8 | 4139 | } |
66189961 TT |
4140 | if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable)) |
4141 | mlx5_core_warn(mdev, "Self loop back prevention is not supported\n"); | |
7524a5d8 | 4142 | if (!MLX5_CAP_GEN(mdev, cq_moderation)) |
3e432ab6 | 4143 | mlx5_core_warn(mdev, "CQ moderation is not supported\n"); |
66189961 | 4144 | |
f62b8bb8 AV |
4145 | return 0; |
4146 | } | |
4147 | ||
d4b6c488 | 4148 | void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, |
85082dba TT |
4149 | int num_channels) |
4150 | { | |
4151 | int i; | |
4152 | ||
4153 | for (i = 0; i < len; i++) | |
4154 | indirection_rqt[i] = i % num_channels; | |
4155 | } | |
4156 | ||
0608d4db | 4157 | static bool slow_pci_heuristic(struct mlx5_core_dev *mdev) |
b797a684 | 4158 | { |
0608d4db TT |
4159 | u32 link_speed = 0; |
4160 | u32 pci_bw = 0; | |
b797a684 | 4161 | |
2c81bfd5 | 4162 | mlx5e_port_max_linkspeed(mdev, &link_speed); |
3c0d551e | 4163 | pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL); |
0608d4db TT |
4164 | mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n", |
4165 | link_speed, pci_bw); | |
4166 | ||
4167 | #define MLX5E_SLOW_PCI_RATIO (2) | |
4168 | ||
4169 | return link_speed && pci_bw && | |
4170 | link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw; | |
0f6e4cf6 EBE |
4171 | } |
4172 | ||
cbce4f44 | 4173 | static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode) |
0088cbbc | 4174 | { |
cbce4f44 TG |
4175 | struct net_dim_cq_moder moder; |
4176 | ||
4177 | moder.cq_period_mode = cq_period_mode; | |
4178 | moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; | |
4179 | moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; | |
4180 | if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) | |
4181 | moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE; | |
4182 | ||
4183 | return moder; | |
4184 | } | |
0088cbbc | 4185 | |
cbce4f44 TG |
4186 | static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode) |
4187 | { | |
4188 | struct net_dim_cq_moder moder; | |
0088cbbc | 4189 | |
cbce4f44 TG |
4190 | moder.cq_period_mode = cq_period_mode; |
4191 | moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; | |
4192 | moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; | |
0088cbbc | 4193 | if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) |
cbce4f44 TG |
4194 | moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE; |
4195 | ||
4196 | return moder; | |
4197 | } | |
4198 | ||
4199 | static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode) | |
4200 | { | |
4201 | return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ? | |
4202 | NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE : | |
4203 | NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; | |
4204 | } | |
4205 | ||
4206 | void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) | |
4207 | { | |
4208 | if (params->tx_dim_enabled) { | |
4209 | u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); | |
4210 | ||
4211 | params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode); | |
4212 | } else { | |
4213 | params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode); | |
4214 | } | |
0088cbbc TG |
4215 | |
4216 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER, | |
4217 | params->tx_cq_moderation.cq_period_mode == | |
4218 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE); | |
4219 | } | |
4220 | ||
9908aa29 TT |
4221 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) |
4222 | { | |
9a317425 | 4223 | if (params->rx_dim_enabled) { |
cbce4f44 TG |
4224 | u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); |
4225 | ||
4226 | params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode); | |
4227 | } else { | |
4228 | params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode); | |
9a317425 | 4229 | } |
457fcd8a | 4230 | |
6a9764ef | 4231 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER, |
0088cbbc TG |
4232 | params->rx_cq_moderation.cq_period_mode == |
4233 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE); | |
9908aa29 TT |
4234 | } |
4235 | ||
707129dc | 4236 | static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout) |
2b029556 SM |
4237 | { |
4238 | int i; | |
4239 | ||
4240 | /* The supported periods are organized in ascending order */ | |
4241 | for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++) | |
4242 | if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout) | |
4243 | break; | |
4244 | ||
4245 | return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]); | |
4246 | } | |
4247 | ||
8f493ffd SM |
4248 | void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, |
4249 | struct mlx5e_params *params, | |
472a1e44 | 4250 | u16 max_channels, u16 mtu) |
f62b8bb8 | 4251 | { |
48bfc397 | 4252 | u8 rx_cq_period_mode; |
2fc4bfb7 | 4253 | |
472a1e44 TT |
4254 | params->sw_mtu = mtu; |
4255 | params->hard_mtu = MLX5E_ETH_HARD_MTU; | |
6a9764ef SM |
4256 | params->num_channels = max_channels; |
4257 | params->num_tc = 1; | |
2b029556 | 4258 | |
6a9764ef SM |
4259 | /* SQ */ |
4260 | params->log_sq_size = is_kdump_kernel() ? | |
b4e029da KH |
4261 | MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE : |
4262 | MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; | |
461017cb | 4263 | |
b797a684 | 4264 | /* set CQE compression */ |
6a9764ef | 4265 | params->rx_cqe_compress_def = false; |
b797a684 | 4266 | if (MLX5_CAP_GEN(mdev, cqe_compression) && |
e53eef63 | 4267 | MLX5_CAP_GEN(mdev, vport_group_manager)) |
0608d4db | 4268 | params->rx_cqe_compress_def = slow_pci_heuristic(mdev); |
0f6e4cf6 | 4269 | |
6a9764ef SM |
4270 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def); |
4271 | ||
4272 | /* RQ */ | |
2ccb0a79 TT |
4273 | if (mlx5e_striding_rq_possible(mdev, params)) |
4274 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, | |
4275 | !slow_pci_heuristic(mdev)); | |
2a0f561b TT |
4276 | mlx5e_set_rq_type(mdev, params); |
4277 | mlx5e_init_rq_type_params(mdev, params); | |
b797a684 | 4278 | |
6a9764ef | 4279 | /* HW LRO */ |
c139dbfd | 4280 | |
5426a0b2 | 4281 | /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */ |
6a9764ef | 4282 | if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) |
619a8f2a TT |
4283 | if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params)) |
4284 | params->lro_en = !slow_pci_heuristic(mdev); | |
6a9764ef | 4285 | params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT); |
b0d4660b | 4286 | |
6a9764ef | 4287 | /* CQ moderation params */ |
48bfc397 | 4288 | rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? |
6a9764ef SM |
4289 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE : |
4290 | MLX5_CQ_PERIOD_MODE_START_FROM_EQE; | |
9a317425 | 4291 | params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation); |
cbce4f44 | 4292 | params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation); |
48bfc397 TG |
4293 | mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode); |
4294 | mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); | |
9908aa29 | 4295 | |
6a9764ef | 4296 | /* TX inline */ |
fbcb127e | 4297 | params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev); |
a6f402e4 | 4298 | |
6a9764ef SM |
4299 | /* RSS */ |
4300 | params->rss_hfunc = ETH_RSS_HASH_XOR; | |
4301 | netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key)); | |
d4b6c488 | 4302 | mlx5e_build_default_indir_rqt(params->indirection_rqt, |
6a9764ef SM |
4303 | MLX5E_INDIR_RQT_SIZE, max_channels); |
4304 | } | |
f62b8bb8 | 4305 | |
6a9764ef SM |
4306 | static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev, |
4307 | struct net_device *netdev, | |
4308 | const struct mlx5e_profile *profile, | |
4309 | void *ppriv) | |
4310 | { | |
4311 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
57afead5 | 4312 | |
6a9764ef SM |
4313 | priv->mdev = mdev; |
4314 | priv->netdev = netdev; | |
4315 | priv->profile = profile; | |
4316 | priv->ppriv = ppriv; | |
79c48764 | 4317 | priv->msglevel = MLX5E_MSG_LEVEL; |
05909bab | 4318 | priv->max_opened_tc = 1; |
2d75b2bc | 4319 | |
472a1e44 TT |
4320 | mlx5e_build_nic_params(mdev, &priv->channels.params, |
4321 | profile->max_nch(mdev), netdev->mtu); | |
9908aa29 | 4322 | |
f62b8bb8 AV |
4323 | mutex_init(&priv->state_lock); |
4324 | ||
4325 | INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); | |
4326 | INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); | |
3947ca18 | 4327 | INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work); |
f62b8bb8 | 4328 | INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work); |
237f258c FD |
4329 | |
4330 | mlx5e_timestamp_init(priv); | |
f62b8bb8 AV |
4331 | } |
4332 | ||
4333 | static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) | |
4334 | { | |
4335 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
4336 | ||
e1d7d349 | 4337 | mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr); |
108805fc SM |
4338 | if (is_zero_ether_addr(netdev->dev_addr) && |
4339 | !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) { | |
4340 | eth_hw_addr_random(netdev); | |
4341 | mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr); | |
4342 | } | |
f62b8bb8 AV |
4343 | } |
4344 | ||
f125376b | 4345 | #if IS_ENABLED(CONFIG_MLX5_ESWITCH) |
cb67b832 HHZ |
4346 | static const struct switchdev_ops mlx5e_switchdev_ops = { |
4347 | .switchdev_port_attr_get = mlx5e_attr_get, | |
4348 | }; | |
e80541ec | 4349 | #endif |
cb67b832 | 4350 | |
6bfd390b | 4351 | static void mlx5e_build_nic_netdev(struct net_device *netdev) |
f62b8bb8 AV |
4352 | { |
4353 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
4354 | struct mlx5_core_dev *mdev = priv->mdev; | |
94cb1ebb EBE |
4355 | bool fcs_supported; |
4356 | bool fcs_enabled; | |
f62b8bb8 AV |
4357 | |
4358 | SET_NETDEV_DEV(netdev, &mdev->pdev->dev); | |
4359 | ||
e80541ec SM |
4360 | netdev->netdev_ops = &mlx5e_netdev_ops; |
4361 | ||
08fb1dac | 4362 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
e80541ec SM |
4363 | if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos)) |
4364 | netdev->dcbnl_ops = &mlx5e_dcbnl_ops; | |
08fb1dac | 4365 | #endif |
66e49ded | 4366 | |
f62b8bb8 AV |
4367 | netdev->watchdog_timeo = 15 * HZ; |
4368 | ||
4369 | netdev->ethtool_ops = &mlx5e_ethtool_ops; | |
4370 | ||
12be4b21 | 4371 | netdev->vlan_features |= NETIF_F_SG; |
f62b8bb8 AV |
4372 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
4373 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; | |
4374 | netdev->vlan_features |= NETIF_F_GRO; | |
4375 | netdev->vlan_features |= NETIF_F_TSO; | |
4376 | netdev->vlan_features |= NETIF_F_TSO6; | |
4377 | netdev->vlan_features |= NETIF_F_RXCSUM; | |
4378 | netdev->vlan_features |= NETIF_F_RXHASH; | |
4379 | ||
71186172 AH |
4380 | netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX; |
4381 | netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX; | |
4382 | ||
6c3a823e TT |
4383 | if (!!MLX5_CAP_ETH(mdev, lro_cap) && |
4384 | mlx5e_check_fragmented_striding_rq_cap(mdev)) | |
f62b8bb8 AV |
4385 | netdev->vlan_features |= NETIF_F_LRO; |
4386 | ||
4387 | netdev->hw_features = netdev->vlan_features; | |
e4cf27bd | 4388 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; |
f62b8bb8 AV |
4389 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; |
4390 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
4382c7b9 | 4391 | netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX; |
f62b8bb8 | 4392 | |
27299841 GP |
4393 | if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) { |
4394 | netdev->hw_features |= NETIF_F_GSO_PARTIAL; | |
b3f63c3d | 4395 | netdev->hw_enc_features |= NETIF_F_IP_CSUM; |
f3ed653c | 4396 | netdev->hw_enc_features |= NETIF_F_IPV6_CSUM; |
b3f63c3d MF |
4397 | netdev->hw_enc_features |= NETIF_F_TSO; |
4398 | netdev->hw_enc_features |= NETIF_F_TSO6; | |
27299841 GP |
4399 | netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL; |
4400 | } | |
4401 | ||
4402 | if (mlx5e_vxlan_allowed(mdev)) { | |
4403 | netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | | |
4404 | NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
4405 | netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL | | |
4406 | NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
b49663c8 | 4407 | netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM; |
b3f63c3d MF |
4408 | } |
4409 | ||
27299841 GP |
4410 | if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) { |
4411 | netdev->hw_features |= NETIF_F_GSO_GRE | | |
4412 | NETIF_F_GSO_GRE_CSUM; | |
4413 | netdev->hw_enc_features |= NETIF_F_GSO_GRE | | |
4414 | NETIF_F_GSO_GRE_CSUM; | |
4415 | netdev->gso_partial_features |= NETIF_F_GSO_GRE | | |
4416 | NETIF_F_GSO_GRE_CSUM; | |
4417 | } | |
4418 | ||
94cb1ebb EBE |
4419 | mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled); |
4420 | ||
4421 | if (fcs_supported) | |
4422 | netdev->hw_features |= NETIF_F_RXALL; | |
4423 | ||
102722fc GE |
4424 | if (MLX5_CAP_ETH(mdev, scatter_fcs)) |
4425 | netdev->hw_features |= NETIF_F_RXFCS; | |
4426 | ||
f62b8bb8 | 4427 | netdev->features = netdev->hw_features; |
6a9764ef | 4428 | if (!priv->channels.params.lro_en) |
f62b8bb8 AV |
4429 | netdev->features &= ~NETIF_F_LRO; |
4430 | ||
94cb1ebb EBE |
4431 | if (fcs_enabled) |
4432 | netdev->features &= ~NETIF_F_RXALL; | |
4433 | ||
102722fc GE |
4434 | if (!priv->channels.params.scatter_fcs_en) |
4435 | netdev->features &= ~NETIF_F_RXFCS; | |
4436 | ||
e8f887ac AV |
4437 | #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f) |
4438 | if (FT_CAP(flow_modify_en) && | |
4439 | FT_CAP(modify_root) && | |
4440 | FT_CAP(identified_miss_table_mode) && | |
1cabe6b0 MG |
4441 | FT_CAP(flow_table_modify)) { |
4442 | netdev->hw_features |= NETIF_F_HW_TC; | |
4443 | #ifdef CONFIG_RFS_ACCEL | |
4444 | netdev->hw_features |= NETIF_F_NTUPLE; | |
4445 | #endif | |
4446 | } | |
e8f887ac | 4447 | |
f62b8bb8 | 4448 | netdev->features |= NETIF_F_HIGHDMA; |
7d92d580 | 4449 | netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER; |
f62b8bb8 AV |
4450 | |
4451 | netdev->priv_flags |= IFF_UNICAST_FLT; | |
4452 | ||
4453 | mlx5e_set_netdev_dev_addr(netdev); | |
cb67b832 | 4454 | |
f125376b | 4455 | #if IS_ENABLED(CONFIG_MLX5_ESWITCH) |
a9f7705f | 4456 | if (MLX5_VPORT_MANAGER(mdev)) |
cb67b832 HHZ |
4457 | netdev->switchdev_ops = &mlx5e_switchdev_ops; |
4458 | #endif | |
547eede0 IT |
4459 | |
4460 | mlx5e_ipsec_build_netdev(priv); | |
c83294b9 | 4461 | mlx5e_tls_build_netdev(priv); |
f62b8bb8 AV |
4462 | } |
4463 | ||
7cbaf9a3 | 4464 | static void mlx5e_create_q_counters(struct mlx5e_priv *priv) |
593cf338 RS |
4465 | { |
4466 | struct mlx5_core_dev *mdev = priv->mdev; | |
4467 | int err; | |
4468 | ||
4469 | err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter); | |
4470 | if (err) { | |
4471 | mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err); | |
4472 | priv->q_counter = 0; | |
4473 | } | |
7cbaf9a3 MS |
4474 | |
4475 | err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter); | |
4476 | if (err) { | |
4477 | mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err); | |
4478 | priv->drop_rq_q_counter = 0; | |
4479 | } | |
593cf338 RS |
4480 | } |
4481 | ||
7cbaf9a3 | 4482 | static void mlx5e_destroy_q_counters(struct mlx5e_priv *priv) |
593cf338 | 4483 | { |
7cbaf9a3 MS |
4484 | if (priv->q_counter) |
4485 | mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter); | |
593cf338 | 4486 | |
7cbaf9a3 MS |
4487 | if (priv->drop_rq_q_counter) |
4488 | mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter); | |
593cf338 RS |
4489 | } |
4490 | ||
6bfd390b HHZ |
4491 | static void mlx5e_nic_init(struct mlx5_core_dev *mdev, |
4492 | struct net_device *netdev, | |
127ea380 HHZ |
4493 | const struct mlx5e_profile *profile, |
4494 | void *ppriv) | |
6bfd390b HHZ |
4495 | { |
4496 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
547eede0 | 4497 | int err; |
6bfd390b | 4498 | |
127ea380 | 4499 | mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv); |
547eede0 IT |
4500 | err = mlx5e_ipsec_init(priv); |
4501 | if (err) | |
4502 | mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err); | |
43585a41 IL |
4503 | err = mlx5e_tls_init(priv); |
4504 | if (err) | |
4505 | mlx5_core_err(mdev, "TLS initialization failed, %d\n", err); | |
6bfd390b | 4506 | mlx5e_build_nic_netdev(netdev); |
8bfaf07f | 4507 | mlx5e_build_tc2txq_maps(priv); |
6bfd390b HHZ |
4508 | mlx5e_vxlan_init(priv); |
4509 | } | |
4510 | ||
4511 | static void mlx5e_nic_cleanup(struct mlx5e_priv *priv) | |
4512 | { | |
43585a41 | 4513 | mlx5e_tls_cleanup(priv); |
547eede0 | 4514 | mlx5e_ipsec_cleanup(priv); |
6bfd390b HHZ |
4515 | mlx5e_vxlan_cleanup(priv); |
4516 | } | |
4517 | ||
4518 | static int mlx5e_init_nic_rx(struct mlx5e_priv *priv) | |
4519 | { | |
4520 | struct mlx5_core_dev *mdev = priv->mdev; | |
4521 | int err; | |
6bfd390b | 4522 | |
8f493ffd SM |
4523 | err = mlx5e_create_indirect_rqt(priv); |
4524 | if (err) | |
6bfd390b | 4525 | return err; |
6bfd390b HHZ |
4526 | |
4527 | err = mlx5e_create_direct_rqts(priv); | |
8f493ffd | 4528 | if (err) |
6bfd390b | 4529 | goto err_destroy_indirect_rqts; |
6bfd390b HHZ |
4530 | |
4531 | err = mlx5e_create_indirect_tirs(priv); | |
8f493ffd | 4532 | if (err) |
6bfd390b | 4533 | goto err_destroy_direct_rqts; |
6bfd390b HHZ |
4534 | |
4535 | err = mlx5e_create_direct_tirs(priv); | |
8f493ffd | 4536 | if (err) |
6bfd390b | 4537 | goto err_destroy_indirect_tirs; |
6bfd390b HHZ |
4538 | |
4539 | err = mlx5e_create_flow_steering(priv); | |
4540 | if (err) { | |
4541 | mlx5_core_warn(mdev, "create flow steering failed, %d\n", err); | |
4542 | goto err_destroy_direct_tirs; | |
4543 | } | |
4544 | ||
655dc3d2 | 4545 | err = mlx5e_tc_nic_init(priv); |
6bfd390b HHZ |
4546 | if (err) |
4547 | goto err_destroy_flow_steering; | |
4548 | ||
4549 | return 0; | |
4550 | ||
4551 | err_destroy_flow_steering: | |
4552 | mlx5e_destroy_flow_steering(priv); | |
4553 | err_destroy_direct_tirs: | |
4554 | mlx5e_destroy_direct_tirs(priv); | |
4555 | err_destroy_indirect_tirs: | |
4556 | mlx5e_destroy_indirect_tirs(priv); | |
4557 | err_destroy_direct_rqts: | |
8f493ffd | 4558 | mlx5e_destroy_direct_rqts(priv); |
6bfd390b HHZ |
4559 | err_destroy_indirect_rqts: |
4560 | mlx5e_destroy_rqt(priv, &priv->indir_rqt); | |
4561 | return err; | |
4562 | } | |
4563 | ||
4564 | static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv) | |
4565 | { | |
655dc3d2 | 4566 | mlx5e_tc_nic_cleanup(priv); |
6bfd390b HHZ |
4567 | mlx5e_destroy_flow_steering(priv); |
4568 | mlx5e_destroy_direct_tirs(priv); | |
4569 | mlx5e_destroy_indirect_tirs(priv); | |
8f493ffd | 4570 | mlx5e_destroy_direct_rqts(priv); |
6bfd390b HHZ |
4571 | mlx5e_destroy_rqt(priv, &priv->indir_rqt); |
4572 | } | |
4573 | ||
4574 | static int mlx5e_init_nic_tx(struct mlx5e_priv *priv) | |
4575 | { | |
4576 | int err; | |
4577 | ||
4578 | err = mlx5e_create_tises(priv); | |
4579 | if (err) { | |
4580 | mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err); | |
4581 | return err; | |
4582 | } | |
4583 | ||
4584 | #ifdef CONFIG_MLX5_CORE_EN_DCB | |
e207b7e9 | 4585 | mlx5e_dcbnl_initialize(priv); |
6bfd390b HHZ |
4586 | #endif |
4587 | return 0; | |
4588 | } | |
4589 | ||
4590 | static void mlx5e_nic_enable(struct mlx5e_priv *priv) | |
4591 | { | |
4592 | struct net_device *netdev = priv->netdev; | |
4593 | struct mlx5_core_dev *mdev = priv->mdev; | |
2c3b5bee SM |
4594 | u16 max_mtu; |
4595 | ||
4596 | mlx5e_init_l2_addr(priv); | |
4597 | ||
63bfd399 EBE |
4598 | /* Marking the link as currently not needed by the Driver */ |
4599 | if (!netif_running(netdev)) | |
4600 | mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN); | |
4601 | ||
2c3b5bee SM |
4602 | /* MTU range: 68 - hw-specific max */ |
4603 | netdev->min_mtu = ETH_MIN_MTU; | |
4604 | mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1); | |
472a1e44 | 4605 | netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu); |
2c3b5bee | 4606 | mlx5e_set_dev_port_mtu(priv); |
6bfd390b | 4607 | |
7907f23a AH |
4608 | mlx5_lag_add(mdev, netdev); |
4609 | ||
6bfd390b | 4610 | mlx5e_enable_async_events(priv); |
127ea380 | 4611 | |
a9f7705f | 4612 | if (MLX5_VPORT_MANAGER(priv->mdev)) |
1d447a39 | 4613 | mlx5e_register_vport_reps(priv); |
2c3b5bee | 4614 | |
610e89e0 SM |
4615 | if (netdev->reg_state != NETREG_REGISTERED) |
4616 | return; | |
2a5e7a13 HN |
4617 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
4618 | mlx5e_dcbnl_init_app(priv); | |
4619 | #endif | |
610e89e0 SM |
4620 | |
4621 | queue_work(priv->wq, &priv->set_rx_mode_work); | |
2c3b5bee SM |
4622 | |
4623 | rtnl_lock(); | |
4624 | if (netif_running(netdev)) | |
4625 | mlx5e_open(netdev); | |
4626 | netif_device_attach(netdev); | |
4627 | rtnl_unlock(); | |
6bfd390b HHZ |
4628 | } |
4629 | ||
4630 | static void mlx5e_nic_disable(struct mlx5e_priv *priv) | |
4631 | { | |
3deef8ce | 4632 | struct mlx5_core_dev *mdev = priv->mdev; |
3deef8ce | 4633 | |
2a5e7a13 HN |
4634 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
4635 | if (priv->netdev->reg_state == NETREG_REGISTERED) | |
4636 | mlx5e_dcbnl_delete_app(priv); | |
4637 | #endif | |
4638 | ||
2c3b5bee SM |
4639 | rtnl_lock(); |
4640 | if (netif_running(priv->netdev)) | |
4641 | mlx5e_close(priv->netdev); | |
4642 | netif_device_detach(priv->netdev); | |
4643 | rtnl_unlock(); | |
4644 | ||
6bfd390b | 4645 | queue_work(priv->wq, &priv->set_rx_mode_work); |
1d447a39 | 4646 | |
a9f7705f | 4647 | if (MLX5_VPORT_MANAGER(priv->mdev)) |
1d447a39 SM |
4648 | mlx5e_unregister_vport_reps(priv); |
4649 | ||
6bfd390b | 4650 | mlx5e_disable_async_events(priv); |
3deef8ce | 4651 | mlx5_lag_remove(mdev); |
6bfd390b HHZ |
4652 | } |
4653 | ||
4654 | static const struct mlx5e_profile mlx5e_nic_profile = { | |
4655 | .init = mlx5e_nic_init, | |
4656 | .cleanup = mlx5e_nic_cleanup, | |
4657 | .init_rx = mlx5e_init_nic_rx, | |
4658 | .cleanup_rx = mlx5e_cleanup_nic_rx, | |
4659 | .init_tx = mlx5e_init_nic_tx, | |
4660 | .cleanup_tx = mlx5e_cleanup_nic_tx, | |
4661 | .enable = mlx5e_nic_enable, | |
4662 | .disable = mlx5e_nic_disable, | |
3834a5e6 | 4663 | .update_stats = mlx5e_update_ndo_stats, |
6bfd390b | 4664 | .max_nch = mlx5e_get_max_num_channels, |
7ca42c80 | 4665 | .update_carrier = mlx5e_update_carrier, |
20fd0c19 SM |
4666 | .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe, |
4667 | .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq, | |
6bfd390b HHZ |
4668 | .max_tc = MLX5E_MAX_NUM_TC, |
4669 | }; | |
4670 | ||
2c3b5bee SM |
4671 | /* mlx5e generic netdev management API (move to en_common.c) */ |
4672 | ||
26e59d80 MHY |
4673 | struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev, |
4674 | const struct mlx5e_profile *profile, | |
4675 | void *ppriv) | |
f62b8bb8 | 4676 | { |
26e59d80 | 4677 | int nch = profile->max_nch(mdev); |
f62b8bb8 AV |
4678 | struct net_device *netdev; |
4679 | struct mlx5e_priv *priv; | |
f62b8bb8 | 4680 | |
08fb1dac | 4681 | netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), |
6bfd390b | 4682 | nch * profile->max_tc, |
08fb1dac | 4683 | nch); |
f62b8bb8 AV |
4684 | if (!netdev) { |
4685 | mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n"); | |
4686 | return NULL; | |
4687 | } | |
4688 | ||
be4891af SM |
4689 | #ifdef CONFIG_RFS_ACCEL |
4690 | netdev->rx_cpu_rmap = mdev->rmap; | |
4691 | #endif | |
4692 | ||
127ea380 | 4693 | profile->init(mdev, netdev, profile, ppriv); |
f62b8bb8 AV |
4694 | |
4695 | netif_carrier_off(netdev); | |
4696 | ||
4697 | priv = netdev_priv(netdev); | |
4698 | ||
7bb29755 MF |
4699 | priv->wq = create_singlethread_workqueue("mlx5e"); |
4700 | if (!priv->wq) | |
26e59d80 MHY |
4701 | goto err_cleanup_nic; |
4702 | ||
4703 | return netdev; | |
4704 | ||
4705 | err_cleanup_nic: | |
31ac9338 OG |
4706 | if (profile->cleanup) |
4707 | profile->cleanup(priv); | |
26e59d80 MHY |
4708 | free_netdev(netdev); |
4709 | ||
4710 | return NULL; | |
4711 | } | |
4712 | ||
2c3b5bee | 4713 | int mlx5e_attach_netdev(struct mlx5e_priv *priv) |
26e59d80 | 4714 | { |
2c3b5bee | 4715 | struct mlx5_core_dev *mdev = priv->mdev; |
26e59d80 | 4716 | const struct mlx5e_profile *profile; |
26e59d80 MHY |
4717 | int err; |
4718 | ||
26e59d80 MHY |
4719 | profile = priv->profile; |
4720 | clear_bit(MLX5E_STATE_DESTROYING, &priv->state); | |
7bb29755 | 4721 | |
6bfd390b HHZ |
4722 | err = profile->init_tx(priv); |
4723 | if (err) | |
ec8b9981 | 4724 | goto out; |
5c50368f | 4725 | |
7cbaf9a3 MS |
4726 | mlx5e_create_q_counters(priv); |
4727 | ||
4728 | err = mlx5e_open_drop_rq(priv, &priv->drop_rq); | |
5c50368f AS |
4729 | if (err) { |
4730 | mlx5_core_err(mdev, "open drop rq failed, %d\n", err); | |
7cbaf9a3 | 4731 | goto err_destroy_q_counters; |
5c50368f AS |
4732 | } |
4733 | ||
6bfd390b HHZ |
4734 | err = profile->init_rx(priv); |
4735 | if (err) | |
5c50368f | 4736 | goto err_close_drop_rq; |
5c50368f | 4737 | |
6bfd390b HHZ |
4738 | if (profile->enable) |
4739 | profile->enable(priv); | |
f62b8bb8 | 4740 | |
26e59d80 | 4741 | return 0; |
5c50368f AS |
4742 | |
4743 | err_close_drop_rq: | |
a43b25da | 4744 | mlx5e_close_drop_rq(&priv->drop_rq); |
5c50368f | 4745 | |
7cbaf9a3 MS |
4746 | err_destroy_q_counters: |
4747 | mlx5e_destroy_q_counters(priv); | |
6bfd390b | 4748 | profile->cleanup_tx(priv); |
5c50368f | 4749 | |
26e59d80 MHY |
4750 | out: |
4751 | return err; | |
f62b8bb8 AV |
4752 | } |
4753 | ||
2c3b5bee | 4754 | void mlx5e_detach_netdev(struct mlx5e_priv *priv) |
26e59d80 | 4755 | { |
26e59d80 MHY |
4756 | const struct mlx5e_profile *profile = priv->profile; |
4757 | ||
4758 | set_bit(MLX5E_STATE_DESTROYING, &priv->state); | |
26e59d80 | 4759 | |
37f304d1 SM |
4760 | if (profile->disable) |
4761 | profile->disable(priv); | |
4762 | flush_workqueue(priv->wq); | |
4763 | ||
26e59d80 | 4764 | profile->cleanup_rx(priv); |
a43b25da | 4765 | mlx5e_close_drop_rq(&priv->drop_rq); |
7cbaf9a3 | 4766 | mlx5e_destroy_q_counters(priv); |
26e59d80 | 4767 | profile->cleanup_tx(priv); |
26e59d80 MHY |
4768 | cancel_delayed_work_sync(&priv->update_stats_work); |
4769 | } | |
4770 | ||
2c3b5bee SM |
4771 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv) |
4772 | { | |
4773 | const struct mlx5e_profile *profile = priv->profile; | |
4774 | struct net_device *netdev = priv->netdev; | |
4775 | ||
4776 | destroy_workqueue(priv->wq); | |
4777 | if (profile->cleanup) | |
4778 | profile->cleanup(priv); | |
4779 | free_netdev(netdev); | |
4780 | } | |
4781 | ||
26e59d80 MHY |
4782 | /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying |
4783 | * hardware contexts and to connect it to the current netdev. | |
4784 | */ | |
4785 | static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv) | |
4786 | { | |
4787 | struct mlx5e_priv *priv = vpriv; | |
4788 | struct net_device *netdev = priv->netdev; | |
4789 | int err; | |
4790 | ||
4791 | if (netif_device_present(netdev)) | |
4792 | return 0; | |
4793 | ||
4794 | err = mlx5e_create_mdev_resources(mdev); | |
4795 | if (err) | |
4796 | return err; | |
4797 | ||
2c3b5bee | 4798 | err = mlx5e_attach_netdev(priv); |
26e59d80 MHY |
4799 | if (err) { |
4800 | mlx5e_destroy_mdev_resources(mdev); | |
4801 | return err; | |
4802 | } | |
4803 | ||
4804 | return 0; | |
4805 | } | |
4806 | ||
4807 | static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv) | |
4808 | { | |
4809 | struct mlx5e_priv *priv = vpriv; | |
4810 | struct net_device *netdev = priv->netdev; | |
4811 | ||
4812 | if (!netif_device_present(netdev)) | |
4813 | return; | |
4814 | ||
2c3b5bee | 4815 | mlx5e_detach_netdev(priv); |
26e59d80 MHY |
4816 | mlx5e_destroy_mdev_resources(mdev); |
4817 | } | |
4818 | ||
b50d292b HHZ |
4819 | static void *mlx5e_add(struct mlx5_core_dev *mdev) |
4820 | { | |
07c9f1e5 SM |
4821 | struct net_device *netdev; |
4822 | void *rpriv = NULL; | |
26e59d80 | 4823 | void *priv; |
26e59d80 | 4824 | int err; |
b50d292b | 4825 | |
26e59d80 MHY |
4826 | err = mlx5e_check_required_hca_cap(mdev); |
4827 | if (err) | |
b50d292b HHZ |
4828 | return NULL; |
4829 | ||
e80541ec | 4830 | #ifdef CONFIG_MLX5_ESWITCH |
a9f7705f | 4831 | if (MLX5_VPORT_MANAGER(mdev)) { |
07c9f1e5 | 4832 | rpriv = mlx5e_alloc_nic_rep_priv(mdev); |
1d447a39 | 4833 | if (!rpriv) { |
07c9f1e5 | 4834 | mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n"); |
1d447a39 SM |
4835 | return NULL; |
4836 | } | |
1d447a39 | 4837 | } |
e80541ec | 4838 | #endif |
127ea380 | 4839 | |
1d447a39 | 4840 | netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv); |
26e59d80 MHY |
4841 | if (!netdev) { |
4842 | mlx5_core_err(mdev, "mlx5e_create_netdev failed\n"); | |
07c9f1e5 | 4843 | goto err_free_rpriv; |
26e59d80 MHY |
4844 | } |
4845 | ||
4846 | priv = netdev_priv(netdev); | |
4847 | ||
4848 | err = mlx5e_attach(mdev, priv); | |
4849 | if (err) { | |
4850 | mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err); | |
4851 | goto err_destroy_netdev; | |
4852 | } | |
4853 | ||
4854 | err = register_netdev(netdev); | |
4855 | if (err) { | |
4856 | mlx5_core_err(mdev, "register_netdev failed, %d\n", err); | |
4857 | goto err_detach; | |
b50d292b | 4858 | } |
26e59d80 | 4859 | |
2a5e7a13 HN |
4860 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
4861 | mlx5e_dcbnl_init_app(priv); | |
4862 | #endif | |
26e59d80 MHY |
4863 | return priv; |
4864 | ||
4865 | err_detach: | |
4866 | mlx5e_detach(mdev, priv); | |
26e59d80 | 4867 | err_destroy_netdev: |
2c3b5bee | 4868 | mlx5e_destroy_netdev(priv); |
07c9f1e5 | 4869 | err_free_rpriv: |
1d447a39 | 4870 | kfree(rpriv); |
26e59d80 | 4871 | return NULL; |
b50d292b HHZ |
4872 | } |
4873 | ||
b50d292b HHZ |
4874 | static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv) |
4875 | { | |
4876 | struct mlx5e_priv *priv = vpriv; | |
1d447a39 | 4877 | void *ppriv = priv->ppriv; |
127ea380 | 4878 | |
2a5e7a13 HN |
4879 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
4880 | mlx5e_dcbnl_delete_app(priv); | |
4881 | #endif | |
5e1e93c7 | 4882 | unregister_netdev(priv->netdev); |
26e59d80 | 4883 | mlx5e_detach(mdev, vpriv); |
2c3b5bee | 4884 | mlx5e_destroy_netdev(priv); |
1d447a39 | 4885 | kfree(ppriv); |
b50d292b HHZ |
4886 | } |
4887 | ||
f62b8bb8 AV |
4888 | static void *mlx5e_get_netdev(void *vpriv) |
4889 | { | |
4890 | struct mlx5e_priv *priv = vpriv; | |
4891 | ||
4892 | return priv->netdev; | |
4893 | } | |
4894 | ||
4895 | static struct mlx5_interface mlx5e_interface = { | |
b50d292b HHZ |
4896 | .add = mlx5e_add, |
4897 | .remove = mlx5e_remove, | |
26e59d80 MHY |
4898 | .attach = mlx5e_attach, |
4899 | .detach = mlx5e_detach, | |
f62b8bb8 AV |
4900 | .event = mlx5e_async_event, |
4901 | .protocol = MLX5_INTERFACE_PROTOCOL_ETH, | |
4902 | .get_dev = mlx5e_get_netdev, | |
4903 | }; | |
4904 | ||
4905 | void mlx5e_init(void) | |
4906 | { | |
2ac9cfe7 | 4907 | mlx5e_ipsec_build_inverse_table(); |
665bc539 | 4908 | mlx5e_build_ptys2ethtool_map(); |
f62b8bb8 AV |
4909 | mlx5_register_interface(&mlx5e_interface); |
4910 | } | |
4911 | ||
4912 | void mlx5e_cleanup(void) | |
4913 | { | |
4914 | mlx5_unregister_interface(&mlx5e_interface); | |
4915 | } |