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net/mlx5e: Avoid using the ipv6 stub in the TC offload neigh update path
[thirdparty/kernel/stable.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
1d447a39 38#include "eswitch.h"
f62b8bb8 39#include "en.h"
e8f887ac 40#include "en_tc.h"
1d447a39 41#include "en_rep.h"
547eede0 42#include "en_accel/ipsec.h"
899a59d3
IT		 43#include "en_accel/ipsec_rxtx.h"
44#include "accel/ipsec.h"
b3f63c3d 45#include "vxlan.h"
f62b8bb8
AV		 46
47struct mlx5e_rq_param {
cb3c7fd4
GR		 48 u32 rqc[MLX5_ST_SZ_DW(rqc)];
49 struct mlx5_wq_param wq;
f62b8bb8
AV		 50};
51
52struct mlx5e_sq_param {
53 u32 sqc[MLX5_ST_SZ_DW(sqc)];
54 struct mlx5_wq_param wq;
55};
56
57struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
9908aa29 61 u8 cq_period_mode;
f62b8bb8
AV		 62};
63
64struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
b5503b99 67 struct mlx5e_sq_param xdp_sq;
d3c9bc27 68 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
d3c9bc27 71 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 72};
73
2fc4bfb7
SM		 74static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75{
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
79}
80
696a97cf
EE		 81void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
82 struct mlx5e_params *params, u8 rq_type)
2fc4bfb7 83{
6a9764ef
SM		 84 params->rq_wq_type = rq_type;
85 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
86 switch (params->rq_wq_type) {
2fc4bfb7 87 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 88 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 89 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
90 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
696a97cf
EE		 91 params->mpwqe_log_stride_sz = MLX5E_MPWQE_STRIDE_SZ(mdev,
92 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
6a9764ef
SM		 93 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
94 params->mpwqe_log_stride_sz;
2fc4bfb7
SM		 95 break;
96 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 97 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 98 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
99 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
bce2b2bf
TT		 100 params->rq_headroom = params->xdp_prog ?
101 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
102 params->rq_headroom += NET_IP_ALIGN;
4078e637
TT		 103
104 /* Extra room needed for build_skb */
bce2b2bf 105 params->lro_wqe_sz -= params->rq_headroom +
4078e637 106 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2fc4bfb7 107 }
2fc4bfb7 108
6a9764ef
SM		 109 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
110 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
111 BIT(params->log_rq_size),
112 BIT(params->mpwqe_log_stride_sz),
113 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 114}
115
696a97cf
EE		 116static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev,
117 struct mlx5e_params *params)
2fc4bfb7 118{
6a9764ef 119 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
899a59d3 120 !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
2fc4bfb7
SM		 121 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
122 MLX5_WQ_TYPE_LINKED_LIST;
696a97cf 123 mlx5e_init_rq_type_params(mdev, params, rq_type);
2fc4bfb7
SM		 124}
125
f62b8bb8
AV		 126static void mlx5e_update_carrier(struct mlx5e_priv *priv)
127{
128 struct mlx5_core_dev *mdev = priv->mdev;
129 u8 port_state;
130
131 port_state = mlx5_query_vport_state(mdev,
e53eef63
OG		 132 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
133 0);
f62b8bb8 134
87424ad5
SD		 135 if (port_state == VPORT_STATE_UP) {
136 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 137 netif_carrier_on(priv->netdev);
87424ad5
SD		 138 } else {
139 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 140 netif_carrier_off(priv->netdev);
87424ad5 141 }
f62b8bb8
AV		 142}
143
144static void mlx5e_update_carrier_work(struct work_struct *work)
145{
146 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
147 update_carrier_work);
148
149 mutex_lock(&priv->state_lock);
150 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
7ca42c80
ES		 151 if (priv->profile->update_carrier)
152 priv->profile->update_carrier(priv);
f62b8bb8
AV		 153 mutex_unlock(&priv->state_lock);
154}
155
3947ca18
DJ		 156static void mlx5e_tx_timeout_work(struct work_struct *work)
157{
158 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
159 tx_timeout_work);
160 int err;
161
162 rtnl_lock();
163 mutex_lock(&priv->state_lock);
164 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
165 goto unlock;
166 mlx5e_close_locked(priv->netdev);
167 err = mlx5e_open_locked(priv->netdev);
168 if (err)
169 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
170 err);
171unlock:
172 mutex_unlock(&priv->state_lock);
173 rtnl_unlock();
174}
175
19386177 176void mlx5e_update_stats(struct mlx5e_priv *priv)
f62b8bb8 177{
19386177 178 int i;
f62b8bb8 179
19386177
KH		 180 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
181 if (mlx5e_stats_grps[i].update_stats)
182 mlx5e_stats_grps[i].update_stats(priv);
f62b8bb8
AV		 183}
184
3834a5e6
GP		 185static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
186{
19386177
KH		 187 int i;
188
189 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
190 if (mlx5e_stats_grps[i].update_stats_mask &
191 MLX5E_NDO_UPDATE_STATS)
192 mlx5e_stats_grps[i].update_stats(priv);
3834a5e6
GP		 193}
194
cb67b832 195void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 196{
197 struct delayed_work *dwork = to_delayed_work(work);
198 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
199 update_stats_work);
200 mutex_lock(&priv->state_lock);
201 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 202 priv->profile->update_stats(priv);
7bb29755
MF		 203 queue_delayed_work(priv->wq, dwork,
204 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 205 }
206 mutex_unlock(&priv->state_lock);
207}
208
daa21560
TT		 209static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
210 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 211{
daa21560
TT		 212 struct mlx5e_priv *priv = vpriv;
213
e0f46eb9 214 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 215 return;
216
f62b8bb8
AV		 217 switch (event) {
218 case MLX5_DEV_EVENT_PORT_UP:
219 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 220 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 221 break;
f62b8bb8
AV		 222 default:
223 break;
224 }
225}
226
f62b8bb8
AV		 227static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
228{
e0f46eb9 229 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 230}
231
232static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
233{
e0f46eb9 234 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
78249c42 235 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 236}
237
7e426671
TT		 238static inline int mlx5e_get_wqe_mtt_sz(void)
239{
240 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
241 * To avoid copying garbage after the mtt array, we allocate
242 * a little more.
243 */
244 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
245 MLX5_UMR_MTT_ALIGNMENT);
246}
247
31391048
SM		 248static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
249 struct mlx5e_icosq *sq,
250 struct mlx5e_umr_wqe *wqe,
251 u16 ix)
7e426671
TT		 252{
253 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
254 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
255 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 256 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 257 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
258 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
259
260 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
261 ds_cnt);
262 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
263 cseg->imm = rq->mkey_be;
264
265 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
31616255 266 ucseg->xlt_octowords =
7e426671
TT		 267 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
268 ucseg->bsf_octowords =
269 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
270 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
271
272 dseg->lkey = sq->mkey_be;
273 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
274}
275
276static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
277 struct mlx5e_channel *c)
278{
279 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
280 int mtt_sz = mlx5e_get_wqe_mtt_sz();
281 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
282 int i;
283
21c59685 284 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
231243c8 285 GFP_KERNEL, cpu_to_node(c->cpu));
21c59685 286 if (!rq->mpwqe.info)
7e426671
TT		 287 goto err_out;
288
289 /* We allocate more than mtt_sz as we will align the pointer */
231243c8
SM		 290 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
291 cpu_to_node(c->cpu));
21c59685 292 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 293 goto err_free_wqe_info;
294
295 for (i = 0; i < wq_sz; i++) {
21c59685 296 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 297
21c59685 298 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 299 MLX5_UMR_ALIGN);
300 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
301 PCI_DMA_TODEVICE);
302 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
303 goto err_unmap_mtts;
304
305 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
306 }
307
308 return 0;
309
310err_unmap_mtts:
311 while (--i >= 0) {
21c59685 312 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 313
314 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
315 PCI_DMA_TODEVICE);
316 }
21c59685 317 kfree(rq->mpwqe.mtt_no_align);
7e426671 318err_free_wqe_info:
21c59685 319 kfree(rq->mpwqe.info);
7e426671
TT		 320
321err_out:
322 return -ENOMEM;
323}
324
325static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
326{
327 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
328 int mtt_sz = mlx5e_get_wqe_mtt_sz();
329 int i;
330
331 for (i = 0; i < wq_sz; i++) {
21c59685 332 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 333
334 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
335 PCI_DMA_TODEVICE);
336 }
21c59685
SM		 337 kfree(rq->mpwqe.mtt_no_align);
338 kfree(rq->mpwqe.info);
7e426671
TT		 339}
340
a43b25da 341static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
ec8b9981
TT		 342 u64 npages, u8 page_shift,
343 struct mlx5_core_mkey *umr_mkey)
3608ae77 344{
3608ae77
TT		 345 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
346 void *mkc;
347 u32 *in;
348 int err;
349
ec8b9981
TT		 350 if (!MLX5E_VALID_NUM_MTTS(npages))
351 return -EINVAL;
352
1b9a07ee 353 in = kvzalloc(inlen, GFP_KERNEL);
3608ae77
TT		 354 if (!in)
355 return -ENOMEM;
356
357 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
358
3608ae77
TT		 359 MLX5_SET(mkc, mkc, free, 1);
360 MLX5_SET(mkc, mkc, umr_en, 1);
361 MLX5_SET(mkc, mkc, lw, 1);
362 MLX5_SET(mkc, mkc, lr, 1);
363 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
364
365 MLX5_SET(mkc, mkc, qpn, 0xffffff);
366 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 367 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 368 MLX5_SET(mkc, mkc, translations_octword_size,
369 MLX5_MTT_OCTW(npages));
ec8b9981 370 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 371
ec8b9981 372 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 373
374 kvfree(in);
375 return err;
376}
377
a43b25da 378static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
ec8b9981 379{
6a9764ef 380 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
ec8b9981 381
a43b25da 382 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
ec8b9981
TT		 383}
384
3b77235b 385static int mlx5e_alloc_rq(struct mlx5e_channel *c,
6a9764ef
SM		 386 struct mlx5e_params *params,
387 struct mlx5e_rq_param *rqp,
3b77235b 388 struct mlx5e_rq *rq)
f62b8bb8 389{
a43b25da 390 struct mlx5_core_dev *mdev = c->mdev;
6a9764ef 391 void *rqc = rqp->rqc;
f62b8bb8 392 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 393 u32 byte_count;
1bfecfca 394 int npages;
f62b8bb8
AV		 395 int wq_sz;
396 int err;
397 int i;
398
231243c8 399 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
311c7c71 400
6a9764ef 401 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
f62b8bb8
AV		 402 &rq->wq_ctrl);
403 if (err)
404 return err;
405
406 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
407
408 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 409
6a9764ef 410 rq->wq_type = params->rq_wq_type;
7e426671
TT		 411 rq->pdev = c->pdev;
412 rq->netdev = c->netdev;
a43b25da 413 rq->tstamp = c->tstamp;
7c39afb3 414 rq->clock = &mdev->clock;
7e426671
TT		 415 rq->channel = c;
416 rq->ix = c->ix;
a43b25da 417 rq->mdev = mdev;
97bc402d 418
6a9764ef 419 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
97bc402d
DB		 420 if (IS_ERR(rq->xdp_prog)) {
421 err = PTR_ERR(rq->xdp_prog);
422 rq->xdp_prog = NULL;
423 goto err_rq_wq_destroy;
424 }
7e426671 425
e213f5b6
WY		 426 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
427 if (err < 0)
0ddf5432
JDB		 428 goto err_rq_wq_destroy;
429
bce2b2bf 430 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
b45d8b50 431 rq->buff.headroom = params->rq_headroom;
b5503b99 432
6a9764ef 433 switch (rq->wq_type) {
461017cb 434 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476 435
7cc6d77b 436 rq->post_wqes = mlx5e_post_rx_mpwqes;
6cd392a0 437 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 438
20fd0c19 439 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
899a59d3
IT		 440#ifdef CONFIG_MLX5_EN_IPSEC
441 if (MLX5_IPSEC_DEV(mdev)) {
442 err = -EINVAL;
443 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
444 goto err_rq_wq_destroy;
445 }
446#endif
20fd0c19
SM		 447 if (!rq->handle_rx_cqe) {
448 err = -EINVAL;
449 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
450 goto err_rq_wq_destroy;
451 }
452
89e89f7a 453 rq->mpwqe.log_stride_sz = params->mpwqe_log_stride_sz;
b45d8b50 454 rq->mpwqe.num_strides = BIT(params->mpwqe_log_num_strides);
1bfecfca 455
b681c481 456 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
ec8b9981 457
a43b25da 458 err = mlx5e_create_rq_umr_mkey(mdev, rq);
7e426671
TT		 459 if (err)
460 goto err_rq_wq_destroy;
ec8b9981
TT		 461 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
462
463 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
464 if (err)
465 goto err_destroy_umr_mkey;
461017cb
TT		 466 break;
467 default: /* MLX5_WQ_TYPE_LINKED_LIST */
accd5883
TT		 468 rq->wqe.frag_info =
469 kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
231243c8 470 GFP_KERNEL, cpu_to_node(c->cpu));
accd5883 471 if (!rq->wqe.frag_info) {
461017cb
TT		 472 err = -ENOMEM;
473 goto err_rq_wq_destroy;
474 }
7cc6d77b 475 rq->post_wqes = mlx5e_post_rx_wqes;
6cd392a0 476 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 477
899a59d3
IT		 478#ifdef CONFIG_MLX5_EN_IPSEC
479 if (c->priv->ipsec)
480 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
481 else
482#endif
483 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
20fd0c19 484 if (!rq->handle_rx_cqe) {
accd5883 485 kfree(rq->wqe.frag_info);
20fd0c19
SM		 486 err = -EINVAL;
487 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
488 goto err_rq_wq_destroy;
489 }
490
b681c481 491 byte_count = params->lro_en ?
6a9764ef 492 params->lro_wqe_sz :
c139dbfd 493 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
899a59d3
IT		 494#ifdef CONFIG_MLX5_EN_IPSEC
495 if (MLX5_IPSEC_DEV(mdev))
b681c481 496 byte_count += MLX5E_METADATA_ETHER_LEN;
899a59d3 497#endif
accd5883 498 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
1bfecfca
SM		 499
500 /* calc the required page order */
b45d8b50 501 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
accd5883 502 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
1bfecfca
SM		 503 rq->buff.page_order = order_base_2(npages);
504
461017cb 505 byte_count |= MLX5_HW_START_PADDING;
7e426671 506 rq->mkey_be = c->mkey_be;
461017cb 507 }
f62b8bb8
AV		 508
509 for (i = 0; i < wq_sz; i++) {
510 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
511
4c2af5cc
TT		 512 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
513 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT;
514
515 wqe->data.addr = cpu_to_be64(dma_offset);
516 }
517
461017cb 518 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 519 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 520 }
521
9a317425
AG		 522 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
523
524 switch (params->rx_cq_moderation.cq_period_mode) {
525 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
526 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
527 break;
528 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
529 default:
530 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
531 }
532
4415a031
TT		 533 rq->page_cache.head = 0;
534 rq->page_cache.tail = 0;
535
f62b8bb8
AV		 536 return 0;
537
ec8b9981
TT		 538err_destroy_umr_mkey:
539 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
540
f62b8bb8 541err_rq_wq_destroy:
97bc402d
DB		 542 if (rq->xdp_prog)
543 bpf_prog_put(rq->xdp_prog);
0ddf5432 544 xdp_rxq_info_unreg(&rq->xdp_rxq);
f62b8bb8
AV		 545 mlx5_wq_destroy(&rq->wq_ctrl);
546
547 return err;
548}
549
3b77235b 550static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 551{
4415a031
TT		 552 int i;
553
86994156
RS		 554 if (rq->xdp_prog)
555 bpf_prog_put(rq->xdp_prog);
556
0ddf5432
JDB		 557 xdp_rxq_info_unreg(&rq->xdp_rxq);
558
461017cb
TT		 559 switch (rq->wq_type) {
560 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 561 mlx5e_rq_free_mpwqe_info(rq);
a43b25da 562 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
461017cb
TT		 563 break;
564 default: /* MLX5_WQ_TYPE_LINKED_LIST */
accd5883 565 kfree(rq->wqe.frag_info);
461017cb
TT		 566 }
567
4415a031
TT		 568 for (i = rq->page_cache.head; i != rq->page_cache.tail;
569 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
570 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
571
572 mlx5e_page_release(rq, dma_info, false);
573 }
f62b8bb8
AV		 574 mlx5_wq_destroy(&rq->wq_ctrl);
575}
576
6a9764ef
SM		 577static int mlx5e_create_rq(struct mlx5e_rq *rq,
578 struct mlx5e_rq_param *param)
f62b8bb8 579{
a43b25da 580 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 581
582 void *in;
583 void *rqc;
584 void *wq;
585 int inlen;
586 int err;
587
588 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
589 sizeof(u64) * rq->wq_ctrl.buf.npages;
1b9a07ee 590 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 591 if (!in)
592 return -ENOMEM;
593
594 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
595 wq = MLX5_ADDR_OF(rqc, rqc, wq);
596
597 memcpy(rqc, param->rqc, sizeof(param->rqc));
598
97de9f31 599 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 600 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
f62b8bb8 601 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 602 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 603 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
604
605 mlx5_fill_page_array(&rq->wq_ctrl.buf,
606 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
607
7db22ffb 608 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 609
610 kvfree(in);
611
612 return err;
613}
614
36350114
GP		 615static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
616 int next_state)
f62b8bb8
AV		 617{
618 struct mlx5e_channel *c = rq->channel;
a43b25da 619 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 620
621 void *in;
622 void *rqc;
623 int inlen;
624 int err;
625
626 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 627 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 628 if (!in)
629 return -ENOMEM;
630
631 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
632
633 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
634 MLX5_SET(rqc, rqc, state, next_state);
635
7db22ffb 636 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 637
638 kvfree(in);
639
640 return err;
641}
642
102722fc
GE		 643static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
644{
645 struct mlx5e_channel *c = rq->channel;
646 struct mlx5e_priv *priv = c->priv;
647 struct mlx5_core_dev *mdev = priv->mdev;
648
649 void *in;
650 void *rqc;
651 int inlen;
652 int err;
653
654 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 655 in = kvzalloc(inlen, GFP_KERNEL);
102722fc
GE		 656 if (!in)
657 return -ENOMEM;
658
659 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
660
661 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
662 MLX5_SET64(modify_rq_in, in, modify_bitmask,
663 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
664 MLX5_SET(rqc, rqc, scatter_fcs, enable);
665 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
666
667 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
668
669 kvfree(in);
670
671 return err;
672}
673
36350114
GP		 674static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
675{
676 struct mlx5e_channel *c = rq->channel;
a43b25da 677 struct mlx5_core_dev *mdev = c->mdev;
36350114
GP		 678 void *in;
679 void *rqc;
680 int inlen;
681 int err;
682
683 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 684 in = kvzalloc(inlen, GFP_KERNEL);
36350114
GP		 685 if (!in)
686 return -ENOMEM;
687
688 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
689
690 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 691 MLX5_SET64(modify_rq_in, in, modify_bitmask,
692 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 693 MLX5_SET(rqc, rqc, vsd, vsd);
694 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
695
696 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
697
698 kvfree(in);
699
700 return err;
701}
702
3b77235b 703static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 704{
a43b25da 705 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
f62b8bb8
AV		 706}
707
708static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
709{
01c196a2 710 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8 711 struct mlx5e_channel *c = rq->channel;
a43b25da 712
f62b8bb8 713 struct mlx5_wq_ll *wq = &rq->wq;
6a9764ef 714 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
f62b8bb8 715
01c196a2 716 while (time_before(jiffies, exp_time)) {
6a9764ef 717 if (wq->cur_sz >= min_wqes)
f62b8bb8
AV		 718 return 0;
719
720 msleep(20);
721 }
722
a43b25da 723 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
6a9764ef 724 rq->rqn, wq->cur_sz, min_wqes);
f62b8bb8
AV		 725 return -ETIMEDOUT;
726}
727
f2fde18c
SM		 728static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
729{
730 struct mlx5_wq_ll *wq = &rq->wq;
731 struct mlx5e_rx_wqe *wqe;
732 __be16 wqe_ix_be;
733 u16 wqe_ix;
734
8484f9ed 735 /* UMR WQE (if in progress) is always at wq->head */
a071cb9f
TT		 736 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
737 rq->mpwqe.umr_in_progress)
21c59685 738 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 739
f2fde18c
SM		 740 while (!mlx5_wq_ll_is_empty(wq)) {
741 wqe_ix_be = *wq->tail_next;
742 wqe_ix = be16_to_cpu(wqe_ix_be);
743 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
744 rq->dealloc_wqe(rq, wqe_ix);
745 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
746 &wqe->next.next_wqe_index);
747 }
accd5883
TT		 748
749 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
750 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
751 * but yet to be re-posted.
752 */
753 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
754
755 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
756 rq->dealloc_wqe(rq, wqe_ix);
757 }
f2fde18c
SM		 758}
759
f62b8bb8 760static int mlx5e_open_rq(struct mlx5e_channel *c,
6a9764ef 761 struct mlx5e_params *params,
f62b8bb8
AV		 762 struct mlx5e_rq_param *param,
763 struct mlx5e_rq *rq)
764{
765 int err;
766
6a9764ef 767 err = mlx5e_alloc_rq(c, params, param, rq);
f62b8bb8
AV		 768 if (err)
769 return err;
770
3b77235b 771 err = mlx5e_create_rq(rq, param);
f62b8bb8 772 if (err)
3b77235b 773 goto err_free_rq;
f62b8bb8 774
36350114 775 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 776 if (err)
3b77235b 777 goto err_destroy_rq;
f62b8bb8 778
9a317425 779 if (params->rx_dim_enabled)
a1eaba4c 780 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
cb3c7fd4 781
f62b8bb8
AV		 782 return 0;
783
f62b8bb8
AV		 784err_destroy_rq:
785 mlx5e_destroy_rq(rq);
3b77235b
SM		 786err_free_rq:
787 mlx5e_free_rq(rq);
f62b8bb8
AV		 788
789 return err;
790}
791
acc6c595
SM		 792static void mlx5e_activate_rq(struct mlx5e_rq *rq)
793{
794 struct mlx5e_icosq *sq = &rq->channel->icosq;
795 u16 pi = sq->pc & sq->wq.sz_m1;
796 struct mlx5e_tx_wqe *nopwqe;
797
798 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
799 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
acc6c595
SM		 800 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
801 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
802}
803
804static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
f62b8bb8 805{
c0f1147d 806 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 807 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
acc6c595 808}
cb3c7fd4 809
acc6c595
SM		 810static void mlx5e_close_rq(struct mlx5e_rq *rq)
811{
9a317425 812 cancel_work_sync(&rq->dim.work);
f62b8bb8 813 mlx5e_destroy_rq(rq);
3b77235b
SM		 814 mlx5e_free_rx_descs(rq);
815 mlx5e_free_rq(rq);
f62b8bb8
AV		 816}
817
31391048 818static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
b5503b99 819{
31391048 820 kfree(sq->db.di);
b5503b99
SM		 821}
822
31391048 823static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
b5503b99
SM		 824{
825 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
826
31391048 827 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
b5503b99 828 GFP_KERNEL, numa);
31391048
SM		 829 if (!sq->db.di) {
830 mlx5e_free_xdpsq_db(sq);
b5503b99
SM		 831 return -ENOMEM;
832 }
833
834 return 0;
835}
836
31391048 837static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
6a9764ef 838 struct mlx5e_params *params,
31391048
SM		 839 struct mlx5e_sq_param *param,
840 struct mlx5e_xdpsq *sq)
841{
842 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 843 struct mlx5_core_dev *mdev = c->mdev;
31391048
SM		 844 int err;
845
846 sq->pdev = c->pdev;
847 sq->mkey_be = c->mkey_be;
848 sq->channel = c;
849 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 850 sq->min_inline_mode = params->tx_min_inline_mode;
31391048 851
231243c8 852 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048
SM		 853 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
854 if (err)
855 return err;
856 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
857
231243c8 858 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
31391048
SM		 859 if (err)
860 goto err_sq_wq_destroy;
861
862 return 0;
863
864err_sq_wq_destroy:
865 mlx5_wq_destroy(&sq->wq_ctrl);
866
867 return err;
868}
869
870static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
871{
872 mlx5e_free_xdpsq_db(sq);
873 mlx5_wq_destroy(&sq->wq_ctrl);
874}
875
876static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
f62b8bb8 877{
f10b7cc7 878 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 879}
880
31391048 881static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
f10b7cc7
SM		 882{
883 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
884
885 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
886 GFP_KERNEL, numa);
887 if (!sq->db.ico_wqe)
888 return -ENOMEM;
889
890 return 0;
891}
892
31391048 893static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
31391048
SM		 894 struct mlx5e_sq_param *param,
895 struct mlx5e_icosq *sq)
f10b7cc7 896{
31391048 897 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 898 struct mlx5_core_dev *mdev = c->mdev;
31391048 899 int err;
f10b7cc7 900
31391048
SM		 901 sq->mkey_be = c->mkey_be;
902 sq->channel = c;
903 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f62b8bb8 904
231243c8 905 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048
SM		 906 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
907 if (err)
908 return err;
909 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 910
231243c8 911 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
31391048
SM		 912 if (err)
913 goto err_sq_wq_destroy;
914
915 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
f62b8bb8
AV		 916
917 return 0;
31391048
SM		 918
919err_sq_wq_destroy:
920 mlx5_wq_destroy(&sq->wq_ctrl);
921
922 return err;
f62b8bb8
AV		 923}
924
31391048 925static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
f10b7cc7 926{
31391048
SM		 927 mlx5e_free_icosq_db(sq);
928 mlx5_wq_destroy(&sq->wq_ctrl);
f10b7cc7
SM		 929}
930
31391048 931static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
f10b7cc7 932{
31391048
SM		 933 kfree(sq->db.wqe_info);
934 kfree(sq->db.dma_fifo);
f10b7cc7
SM		 935}
936
31391048 937static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
b5503b99 938{
31391048
SM		 939 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
940 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
941
31391048
SM		 942 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
943 GFP_KERNEL, numa);
944 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
945 GFP_KERNEL, numa);
77bdf895 946 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
31391048
SM		 947 mlx5e_free_txqsq_db(sq);
948 return -ENOMEM;
b5503b99 949 }
31391048
SM		 950
951 sq->dma_fifo_mask = df_sz - 1;
952
953 return 0;
b5503b99
SM		 954}
955
31391048 956static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
acc6c595 957 int txq_ix,
6a9764ef 958 struct mlx5e_params *params,
31391048
SM		 959 struct mlx5e_sq_param *param,
960 struct mlx5e_txqsq *sq)
f62b8bb8 961{
31391048 962 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 963 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 964 int err;
965
f10b7cc7 966 sq->pdev = c->pdev;
a43b25da 967 sq->tstamp = c->tstamp;
7c39afb3 968 sq->clock = &mdev->clock;
f10b7cc7
SM		 969 sq->mkey_be = c->mkey_be;
970 sq->channel = c;
acc6c595 971 sq->txq_ix = txq_ix;
aff26157 972 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef
SM		 973 sq->max_inline = params->tx_max_inline;
974 sq->min_inline_mode = params->tx_min_inline_mode;
2ac9cfe7
IT		 975 if (MLX5_IPSEC_DEV(c->priv->mdev))
976 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
f10b7cc7 977
231243c8 978 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048 979 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
f62b8bb8 980 if (err)
aff26157 981 return err;
31391048 982 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 983
231243c8 984 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
7ec0bb22 985 if (err)
f62b8bb8
AV		 986 goto err_sq_wq_destroy;
987
31391048 988 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
f62b8bb8
AV		 989
990 return 0;
991
992err_sq_wq_destroy:
993 mlx5_wq_destroy(&sq->wq_ctrl);
994
f62b8bb8
AV		 995 return err;
996}
997
31391048 998static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 999{
31391048 1000 mlx5e_free_txqsq_db(sq);
f62b8bb8 1001 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1002}
1003
33ad9711
SM		 1004struct mlx5e_create_sq_param {
1005 struct mlx5_wq_ctrl *wq_ctrl;
1006 u32 cqn;
1007 u32 tisn;
1008 u8 tis_lst_sz;
1009 u8 min_inline_mode;
1010};
1011
a43b25da 1012static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
33ad9711
SM		 1013 struct mlx5e_sq_param *param,
1014 struct mlx5e_create_sq_param *csp,
1015 u32 *sqn)
f62b8bb8 1016{
f62b8bb8
AV		 1017 void *in;
1018 void *sqc;
1019 void *wq;
1020 int inlen;
1021 int err;
1022
1023 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
33ad9711 1024 sizeof(u64) * csp->wq_ctrl->buf.npages;
1b9a07ee 1025 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1026 if (!in)
1027 return -ENOMEM;
1028
1029 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1030 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1031
1032 memcpy(sqc, param->sqc, sizeof(param->sqc));
33ad9711
SM		 1033 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1034 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1035 MLX5_SET(sqc, sqc, cqn, csp->cqn);
a6f402e4
SM		 1036
1037 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
33ad9711 1038 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
a6f402e4 1039
33ad9711 1040 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f62b8bb8
AV		 1041
1042 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
a43b25da 1043 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
33ad9711 1044 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
68cdf5d6 1045 MLX5_ADAPTER_PAGE_SHIFT);
33ad9711 1046 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
f62b8bb8 1047
33ad9711 1048 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 1049
33ad9711 1050 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
f62b8bb8
AV		 1051
1052 kvfree(in);
1053
1054 return err;
1055}
1056
33ad9711
SM		 1057struct mlx5e_modify_sq_param {
1058 int curr_state;
1059 int next_state;
1060 bool rl_update;
1061 int rl_index;
1062};
1063
a43b25da 1064static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
33ad9711 1065 struct mlx5e_modify_sq_param *p)
f62b8bb8 1066{
f62b8bb8
AV		 1067 void *in;
1068 void *sqc;
1069 int inlen;
1070 int err;
1071
1072 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 1073 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1074 if (!in)
1075 return -ENOMEM;
1076
1077 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1078
33ad9711
SM		 1079 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1080 MLX5_SET(sqc, sqc, state, p->next_state);
1081 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
507f0c81 1082 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
33ad9711 1083 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
507f0c81 1084 }
f62b8bb8 1085
33ad9711 1086 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
f62b8bb8
AV		 1087
1088 kvfree(in);
1089
1090 return err;
1091}
1092
a43b25da 1093static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
33ad9711 1094{
a43b25da 1095 mlx5_core_destroy_sq(mdev, sqn);
f62b8bb8
AV		 1096}
1097
a43b25da 1098static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
31391048
SM		 1099 struct mlx5e_sq_param *param,
1100 struct mlx5e_create_sq_param *csp,
1101 u32 *sqn)
f62b8bb8 1102{
33ad9711 1103 struct mlx5e_modify_sq_param msp = {0};
31391048
SM		 1104 int err;
1105
a43b25da 1106 err = mlx5e_create_sq(mdev, param, csp, sqn);
31391048
SM		 1107 if (err)
1108 return err;
1109
1110 msp.curr_state = MLX5_SQC_STATE_RST;
1111 msp.next_state = MLX5_SQC_STATE_RDY;
a43b25da 1112 err = mlx5e_modify_sq(mdev, *sqn, &msp);
31391048 1113 if (err)
a43b25da 1114 mlx5e_destroy_sq(mdev, *sqn);
31391048
SM		 1115
1116 return err;
1117}
1118
7f859ecf
SM		 1119static int mlx5e_set_sq_maxrate(struct net_device *dev,
1120 struct mlx5e_txqsq *sq, u32 rate);
1121
31391048 1122static int mlx5e_open_txqsq(struct mlx5e_channel *c,
a43b25da 1123 u32 tisn,
acc6c595 1124 int txq_ix,
6a9764ef 1125 struct mlx5e_params *params,
31391048
SM		 1126 struct mlx5e_sq_param *param,
1127 struct mlx5e_txqsq *sq)
1128{
1129 struct mlx5e_create_sq_param csp = {};
7f859ecf 1130 u32 tx_rate;
f62b8bb8
AV		 1131 int err;
1132
6a9764ef 1133 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
f62b8bb8
AV		 1134 if (err)
1135 return err;
1136
a43b25da 1137 csp.tisn = tisn;
31391048 1138 csp.tis_lst_sz = 1;
33ad9711
SM		 1139 csp.cqn = sq->cq.mcq.cqn;
1140 csp.wq_ctrl = &sq->wq_ctrl;
1141 csp.min_inline_mode = sq->min_inline_mode;
a43b25da 1142 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
f62b8bb8 1143 if (err)
31391048 1144 goto err_free_txqsq;
f62b8bb8 1145
a43b25da 1146 tx_rate = c->priv->tx_rates[sq->txq_ix];
7f859ecf 1147 if (tx_rate)
a43b25da 1148 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
7f859ecf 1149
f62b8bb8
AV		 1150 return 0;
1151
31391048 1152err_free_txqsq:
3b77235b 1153 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
31391048 1154 mlx5e_free_txqsq(sq);
f62b8bb8
AV		 1155
1156 return err;
1157}
1158
acc6c595
SM		 1159static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1160{
a43b25da 1161 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
acc6c595
SM		 1162 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1163 netdev_tx_reset_queue(sq->txq);
1164 netif_tx_start_queue(sq->txq);
1165}
1166
f62b8bb8
AV		 1167static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1168{
1169 __netif_tx_lock_bh(txq);
1170 netif_tx_stop_queue(txq);
1171 __netif_tx_unlock_bh(txq);
1172}
1173
acc6c595 1174static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1175{
33ad9711 1176 struct mlx5e_channel *c = sq->channel;
33ad9711 1177
c0f1147d 1178 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6 1179 /* prevent netif_tx_wake_queue */
33ad9711 1180 napi_synchronize(&c->napi);
29429f33 1181
31391048 1182 netif_tx_disable_queue(sq->txq);
f62b8bb8 1183
31391048
SM		 1184 /* last doorbell out, godspeed .. */
1185 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1186 struct mlx5e_tx_wqe *nop;
864b2d71 1187
77bdf895 1188 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
31391048
SM		 1189 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1190 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
29429f33 1191 }
acc6c595
SM		 1192}
1193
1194static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1195{
1196 struct mlx5e_channel *c = sq->channel;
a43b25da 1197 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1198
a43b25da 1199 mlx5e_destroy_sq(mdev, sq->sqn);
33ad9711
SM		 1200 if (sq->rate_limit)
1201 mlx5_rl_remove_rate(mdev, sq->rate_limit);
31391048
SM		 1202 mlx5e_free_txqsq_descs(sq);
1203 mlx5e_free_txqsq(sq);
1204}
1205
1206static int mlx5e_open_icosq(struct mlx5e_channel *c,
6a9764ef 1207 struct mlx5e_params *params,
31391048
SM		 1208 struct mlx5e_sq_param *param,
1209 struct mlx5e_icosq *sq)
1210{
1211 struct mlx5e_create_sq_param csp = {};
1212 int err;
1213
6a9764ef 1214 err = mlx5e_alloc_icosq(c, param, sq);
31391048
SM		 1215 if (err)
1216 return err;
1217
1218 csp.cqn = sq->cq.mcq.cqn;
1219 csp.wq_ctrl = &sq->wq_ctrl;
6a9764ef 1220 csp.min_inline_mode = params->tx_min_inline_mode;
31391048 1221 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1222 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1223 if (err)
1224 goto err_free_icosq;
1225
1226 return 0;
1227
1228err_free_icosq:
1229 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1230 mlx5e_free_icosq(sq);
1231
1232 return err;
1233}
1234
1235static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1236{
1237 struct mlx5e_channel *c = sq->channel;
1238
1239 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1240 napi_synchronize(&c->napi);
1241
a43b25da 1242 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1243 mlx5e_free_icosq(sq);
1244}
1245
1246static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
6a9764ef 1247 struct mlx5e_params *params,
31391048
SM		 1248 struct mlx5e_sq_param *param,
1249 struct mlx5e_xdpsq *sq)
1250{
1251 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1252 struct mlx5e_create_sq_param csp = {};
31391048
SM		 1253 unsigned int inline_hdr_sz = 0;
1254 int err;
1255 int i;
1256
6a9764ef 1257 err = mlx5e_alloc_xdpsq(c, params, param, sq);
31391048
SM		 1258 if (err)
1259 return err;
1260
1261 csp.tis_lst_sz = 1;
a43b25da 1262 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
31391048
SM		 1263 csp.cqn = sq->cq.mcq.cqn;
1264 csp.wq_ctrl = &sq->wq_ctrl;
1265 csp.min_inline_mode = sq->min_inline_mode;
1266 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1267 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1268 if (err)
1269 goto err_free_xdpsq;
1270
1271 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1272 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1273 ds_cnt++;
1274 }
1275
1276 /* Pre initialize fixed WQE fields */
1277 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1278 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1279 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1280 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1281 struct mlx5_wqe_data_seg *dseg;
1282
1283 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1284 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1285
1286 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1287 dseg->lkey = sq->mkey_be;
1288 }
1289
1290 return 0;
1291
1292err_free_xdpsq:
1293 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1294 mlx5e_free_xdpsq(sq);
1295
1296 return err;
1297}
1298
1299static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1300{
1301 struct mlx5e_channel *c = sq->channel;
1302
1303 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1304 napi_synchronize(&c->napi);
1305
a43b25da 1306 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1307 mlx5e_free_xdpsq_descs(sq);
1308 mlx5e_free_xdpsq(sq);
f62b8bb8
AV		 1309}
1310
95b6c6a5
EBE		 1311static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1312 struct mlx5e_cq_param *param,
1313 struct mlx5e_cq *cq)
f62b8bb8 1314{
f62b8bb8
AV		 1315 struct mlx5_core_cq *mcq = &cq->mcq;
1316 int eqn_not_used;
0b6e26ce 1317 unsigned int irqn;
f62b8bb8
AV		 1318 int err;
1319 u32 i;
1320
f62b8bb8
AV		 1321 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1322 &cq->wq_ctrl);
1323 if (err)
1324 return err;
1325
1326 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1327
f62b8bb8
AV		 1328 mcq->cqe_sz = 64;
1329 mcq->set_ci_db = cq->wq_ctrl.db.db;
1330 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1331 *mcq->set_ci_db = 0;
1332 *mcq->arm_db = 0;
1333 mcq->vector = param->eq_ix;
1334 mcq->comp = mlx5e_completion_event;
1335 mcq->event = mlx5e_cq_error_event;
1336 mcq->irqn = irqn;
f62b8bb8
AV		 1337
1338 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1339 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1340
1341 cqe->op_own = 0xf1;
1342 }
1343
a43b25da 1344 cq->mdev = mdev;
f62b8bb8
AV		 1345
1346 return 0;
1347}
1348
95b6c6a5
EBE		 1349static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1350 struct mlx5e_cq_param *param,
1351 struct mlx5e_cq *cq)
1352{
1353 struct mlx5_core_dev *mdev = c->priv->mdev;
1354 int err;
1355
231243c8
SM		 1356 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1357 param->wq.db_numa_node = cpu_to_node(c->cpu);
95b6c6a5
EBE		 1358 param->eq_ix = c->ix;
1359
1360 err = mlx5e_alloc_cq_common(mdev, param, cq);
1361
1362 cq->napi = &c->napi;
1363 cq->channel = c;
1364
1365 return err;
1366}
1367
3b77235b 1368static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1369{
1c1b5228 1370 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1371}
1372
3b77235b 1373static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1374{
a43b25da 1375 struct mlx5_core_dev *mdev = cq->mdev;
f62b8bb8
AV		 1376 struct mlx5_core_cq *mcq = &cq->mcq;
1377
1378 void *in;
1379 void *cqc;
1380 int inlen;
0b6e26ce 1381 unsigned int irqn_not_used;
f62b8bb8
AV		 1382 int eqn;
1383 int err;
1384
1385 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1386 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1b9a07ee 1387 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1388 if (!in)
1389 return -ENOMEM;
1390
1391 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1392
1393 memcpy(cqc, param->cqc, sizeof(param->cqc));
1394
1c1b5228
TT		 1395 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1396 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1397
1398 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1399
9908aa29 1400 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1401 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1402 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1c1b5228 1403 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1404 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1405 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1406
1407 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1408
1409 kvfree(in);
1410
1411 if (err)
1412 return err;
1413
1414 mlx5e_cq_arm(cq);
1415
1416 return 0;
1417}
1418
3b77235b 1419static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1420{
a43b25da 1421 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
f62b8bb8
AV		 1422}
1423
1424static int mlx5e_open_cq(struct mlx5e_channel *c,
9a317425 1425 struct net_dim_cq_moder moder,
f62b8bb8 1426 struct mlx5e_cq_param *param,
6a9764ef 1427 struct mlx5e_cq *cq)
f62b8bb8 1428{
a43b25da 1429 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1430 int err;
f62b8bb8 1431
3b77235b 1432 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1433 if (err)
1434 return err;
1435
3b77235b 1436 err = mlx5e_create_cq(cq, param);
f62b8bb8 1437 if (err)
3b77235b 1438 goto err_free_cq;
f62b8bb8 1439
7524a5d8 1440 if (MLX5_CAP_GEN(mdev, cq_moderation))
6a9764ef 1441 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
f62b8bb8
AV		 1442 return 0;
1443
3b77235b
SM		 1444err_free_cq:
1445 mlx5e_free_cq(cq);
f62b8bb8
AV		 1446
1447 return err;
1448}
1449
1450static void mlx5e_close_cq(struct mlx5e_cq *cq)
1451{
f62b8bb8 1452 mlx5e_destroy_cq(cq);
3b77235b 1453 mlx5e_free_cq(cq);
f62b8bb8
AV		 1454}
1455
231243c8
SM		 1456static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1457{
1458 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1459}
1460
f62b8bb8 1461static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
6a9764ef 1462 struct mlx5e_params *params,
f62b8bb8
AV		 1463 struct mlx5e_channel_param *cparam)
1464{
f62b8bb8
AV		 1465 int err;
1466 int tc;
1467
1468 for (tc = 0; tc < c->num_tc; tc++) {
6a9764ef
SM		 1469 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1470 &cparam->tx_cq, &c->sq[tc].cq);
f62b8bb8
AV		 1471 if (err)
1472 goto err_close_tx_cqs;
f62b8bb8
AV		 1473 }
1474
1475 return 0;
1476
1477err_close_tx_cqs:
1478 for (tc--; tc >= 0; tc--)
1479 mlx5e_close_cq(&c->sq[tc].cq);
1480
1481 return err;
1482}
1483
1484static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1485{
1486 int tc;
1487
1488 for (tc = 0; tc < c->num_tc; tc++)
1489 mlx5e_close_cq(&c->sq[tc].cq);
1490}
1491
1492static int mlx5e_open_sqs(struct mlx5e_channel *c,
6a9764ef 1493 struct mlx5e_params *params,
f62b8bb8
AV		 1494 struct mlx5e_channel_param *cparam)
1495{
1496 int err;
1497 int tc;
1498
6a9764ef
SM		 1499 for (tc = 0; tc < params->num_tc; tc++) {
1500 int txq_ix = c->ix + tc * params->num_channels;
acc6c595 1501
a43b25da
SM		 1502 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1503 params, &cparam->sq, &c->sq[tc]);
f62b8bb8
AV		 1504 if (err)
1505 goto err_close_sqs;
1506 }
1507
1508 return 0;
1509
1510err_close_sqs:
1511 for (tc--; tc >= 0; tc--)
31391048 1512 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1513
1514 return err;
1515}
1516
1517static void mlx5e_close_sqs(struct mlx5e_channel *c)
1518{
1519 int tc;
1520
1521 for (tc = 0; tc < c->num_tc; tc++)
31391048 1522 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1523}
1524
507f0c81 1525static int mlx5e_set_sq_maxrate(struct net_device *dev,
31391048 1526 struct mlx5e_txqsq *sq, u32 rate)
507f0c81
YP		 1527{
1528 struct mlx5e_priv *priv = netdev_priv(dev);
1529 struct mlx5_core_dev *mdev = priv->mdev;
33ad9711 1530 struct mlx5e_modify_sq_param msp = {0};
507f0c81
YP		 1531 u16 rl_index = 0;
1532 int err;
1533
1534 if (rate == sq->rate_limit)
1535 /* nothing to do */
1536 return 0;
1537
1538 if (sq->rate_limit)
1539 /* remove current rl index to free space to next ones */
1540 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1541
1542 sq->rate_limit = 0;
1543
1544 if (rate) {
1545 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1546 if (err) {
1547 netdev_err(dev, "Failed configuring rate %u: %d\n",
1548 rate, err);
1549 return err;
1550 }
1551 }
1552
33ad9711
SM		 1553 msp.curr_state = MLX5_SQC_STATE_RDY;
1554 msp.next_state = MLX5_SQC_STATE_RDY;
1555 msp.rl_index = rl_index;
1556 msp.rl_update = true;
a43b25da 1557 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
507f0c81
YP		 1558 if (err) {
1559 netdev_err(dev, "Failed configuring rate %u: %d\n",
1560 rate, err);
1561 /* remove the rate from the table */
1562 if (rate)
1563 mlx5_rl_remove_rate(mdev, rate);
1564 return err;
1565 }
1566
1567 sq->rate_limit = rate;
1568 return 0;
1569}
1570
1571static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1572{
1573 struct mlx5e_priv *priv = netdev_priv(dev);
1574 struct mlx5_core_dev *mdev = priv->mdev;
acc6c595 1575 struct mlx5e_txqsq *sq = priv->txq2sq[index];
507f0c81
YP		 1576 int err = 0;
1577
1578 if (!mlx5_rl_is_supported(mdev)) {
1579 netdev_err(dev, "Rate limiting is not supported on this device\n");
1580 return -EINVAL;
1581 }
1582
1583 /* rate is given in Mb/sec, HW config is in Kb/sec */
1584 rate = rate << 10;
1585
1586 /* Check whether rate in valid range, 0 is always valid */
1587 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1588 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1589 return -ERANGE;
1590 }
1591
1592 mutex_lock(&priv->state_lock);
1593 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1594 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1595 if (!err)
1596 priv->tx_rates[index] = rate;
1597 mutex_unlock(&priv->state_lock);
1598
1599 return err;
1600}
1601
f62b8bb8 1602static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
6a9764ef 1603 struct mlx5e_params *params,
f62b8bb8
AV		 1604 struct mlx5e_channel_param *cparam,
1605 struct mlx5e_channel **cp)
1606{
9a317425 1607 struct net_dim_cq_moder icocq_moder = {0, 0};
f62b8bb8 1608 struct net_device *netdev = priv->netdev;
231243c8 1609 int cpu = mlx5e_get_cpu(priv, ix);
f62b8bb8 1610 struct mlx5e_channel *c;
a8c2eb15 1611 unsigned int irq;
f62b8bb8 1612 int err;
a8c2eb15 1613 int eqn;
f62b8bb8 1614
231243c8 1615 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
f62b8bb8
AV		 1616 if (!c)
1617 return -ENOMEM;
1618
1619 c->priv = priv;
a43b25da
SM		 1620 c->mdev = priv->mdev;
1621 c->tstamp = &priv->tstamp;
f62b8bb8 1622 c->ix = ix;
231243c8 1623 c->cpu = cpu;
f62b8bb8
AV		 1624 c->pdev = &priv->mdev->pdev->dev;
1625 c->netdev = priv->netdev;
b50d292b 1626 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
6a9764ef
SM		 1627 c->num_tc = params->num_tc;
1628 c->xdp = !!params->xdp_prog;
cb3c7fd4 1629
a8c2eb15
TT		 1630 mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1631 c->irq_desc = irq_to_desc(irq);
1632
f62b8bb8
AV		 1633 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1634
6a9764ef 1635 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
f62b8bb8
AV		 1636 if (err)
1637 goto err_napi_del;
1638
6a9764ef 1639 err = mlx5e_open_tx_cqs(c, params, cparam);
d3c9bc27
TT		 1640 if (err)
1641 goto err_close_icosq_cq;
1642
6a9764ef 1643 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
f62b8bb8
AV		 1644 if (err)
1645 goto err_close_tx_cqs;
f62b8bb8 1646
d7a0ecab 1647 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
6a9764ef
SM		 1648 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1649 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
d7a0ecab
SM		 1650 if (err)
1651 goto err_close_rx_cq;
1652
f62b8bb8
AV		 1653 napi_enable(&c->napi);
1654
6a9764ef 1655 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1656 if (err)
1657 goto err_disable_napi;
1658
6a9764ef 1659 err = mlx5e_open_sqs(c, params, cparam);
d3c9bc27
TT		 1660 if (err)
1661 goto err_close_icosq;
1662
6a9764ef 1663 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
d7a0ecab
SM		 1664 if (err)
1665 goto err_close_sqs;
b5503b99 1666
6a9764ef 1667 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
f62b8bb8 1668 if (err)
b5503b99 1669 goto err_close_xdp_sq;
f62b8bb8 1670
f62b8bb8
AV		 1671 *cp = c;
1672
1673 return 0;
b5503b99 1674err_close_xdp_sq:
d7a0ecab 1675 if (c->xdp)
31391048 1676 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8
AV		 1677
1678err_close_sqs:
1679 mlx5e_close_sqs(c);
1680
d3c9bc27 1681err_close_icosq:
31391048 1682 mlx5e_close_icosq(&c->icosq);
d3c9bc27 1683
f62b8bb8
AV		 1684err_disable_napi:
1685 napi_disable(&c->napi);
d7a0ecab 1686 if (c->xdp)
31871f87 1687 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 1688
1689err_close_rx_cq:
f62b8bb8
AV		 1690 mlx5e_close_cq(&c->rq.cq);
1691
1692err_close_tx_cqs:
1693 mlx5e_close_tx_cqs(c);
1694
d3c9bc27
TT		 1695err_close_icosq_cq:
1696 mlx5e_close_cq(&c->icosq.cq);
1697
f62b8bb8
AV		 1698err_napi_del:
1699 netif_napi_del(&c->napi);
1700 kfree(c);
1701
1702 return err;
1703}
1704
acc6c595
SM		 1705static void mlx5e_activate_channel(struct mlx5e_channel *c)
1706{
1707 int tc;
1708
1709 for (tc = 0; tc < c->num_tc; tc++)
1710 mlx5e_activate_txqsq(&c->sq[tc]);
1711 mlx5e_activate_rq(&c->rq);
231243c8 1712 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
acc6c595
SM		 1713}
1714
1715static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1716{
1717 int tc;
1718
1719 mlx5e_deactivate_rq(&c->rq);
1720 for (tc = 0; tc < c->num_tc; tc++)
1721 mlx5e_deactivate_txqsq(&c->sq[tc]);
1722}
1723
f62b8bb8
AV		 1724static void mlx5e_close_channel(struct mlx5e_channel *c)
1725{
1726 mlx5e_close_rq(&c->rq);
b5503b99 1727 if (c->xdp)
31391048 1728 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8 1729 mlx5e_close_sqs(c);
31391048 1730 mlx5e_close_icosq(&c->icosq);
f62b8bb8 1731 napi_disable(&c->napi);
b5503b99 1732 if (c->xdp)
31871f87 1733 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8
AV		 1734 mlx5e_close_cq(&c->rq.cq);
1735 mlx5e_close_tx_cqs(c);
d3c9bc27 1736 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1737 netif_napi_del(&c->napi);
7ae92ae5 1738
f62b8bb8
AV		 1739 kfree(c);
1740}
1741
1742static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
6a9764ef 1743 struct mlx5e_params *params,
f62b8bb8
AV		 1744 struct mlx5e_rq_param *param)
1745{
1746 void *rqc = param->rqc;
1747 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1748
6a9764ef 1749 switch (params->rq_wq_type) {
461017cb 1750 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef
SM		 1751 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1752 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
461017cb
TT		 1753 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1754 break;
1755 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1756 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1757 }
1758
f62b8bb8
AV		 1759 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1760 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
6a9764ef 1761 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
b50d292b 1762 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1763 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
6a9764ef 1764 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
102722fc 1765 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
f62b8bb8 1766
311c7c71 1767 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1768 param->wq.linear = 1;
1769}
1770
2f0db879
GP		 1771static void mlx5e_build_drop_rq_param(struct mlx5_core_dev *mdev,
1772 struct mlx5e_rq_param *param)
556dd1b9
TT		 1773{
1774 void *rqc = param->rqc;
1775 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1776
1777 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1778 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
2f0db879
GP		 1779
1780 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
556dd1b9
TT		 1781}
1782
d3c9bc27
TT		 1783static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1784 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1785{
1786 void *sqc = param->sqc;
1787 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1788
f62b8bb8 1789 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1790 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1791
311c7c71 1792 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1793}
1794
1795static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
6a9764ef 1796 struct mlx5e_params *params,
d3c9bc27
TT		 1797 struct mlx5e_sq_param *param)
1798{
1799 void *sqc = param->sqc;
1800 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1801
1802 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1803 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2ac9cfe7 1804 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
f62b8bb8
AV		 1805}
1806
1807static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1808 struct mlx5e_cq_param *param)
1809{
1810 void *cqc = param->cqc;
1811
30aa60b3 1812 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 1813}
1814
1815static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1816 struct mlx5e_params *params,
f62b8bb8
AV		 1817 struct mlx5e_cq_param *param)
1818{
1819 void *cqc = param->cqc;
461017cb 1820 u8 log_cq_size;
f62b8bb8 1821
6a9764ef 1822 switch (params->rq_wq_type) {
461017cb 1823 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 1824 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
461017cb
TT		 1825 break;
1826 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 1827 log_cq_size = params->log_rq_size;
461017cb
TT		 1828 }
1829
1830 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
6a9764ef 1831 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1832 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1833 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1834 }
f62b8bb8
AV		 1835
1836 mlx5e_build_common_cq_param(priv, param);
0088cbbc 1837 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 1838}
1839
1840static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1841 struct mlx5e_params *params,
f62b8bb8
AV		 1842 struct mlx5e_cq_param *param)
1843{
1844 void *cqc = param->cqc;
1845
6a9764ef 1846 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
f62b8bb8
AV		 1847
1848 mlx5e_build_common_cq_param(priv, param);
0088cbbc 1849 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 1850}
1851
d3c9bc27 1852static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1853 u8 log_wq_size,
1854 struct mlx5e_cq_param *param)
d3c9bc27
TT		 1855{
1856 void *cqc = param->cqc;
1857
1858 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1859
1860 mlx5e_build_common_cq_param(priv, param);
9908aa29 1861
9a317425 1862 param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1863}
1864
1865static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1866 u8 log_wq_size,
1867 struct mlx5e_sq_param *param)
d3c9bc27
TT		 1868{
1869 void *sqc = param->sqc;
1870 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1871
1872 mlx5e_build_sq_param_common(priv, param);
1873
1874 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1875 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1876}
1877
b5503b99 1878static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
6a9764ef 1879 struct mlx5e_params *params,
b5503b99
SM		 1880 struct mlx5e_sq_param *param)
1881{
1882 void *sqc = param->sqc;
1883 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1884
1885 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1886 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
b5503b99
SM		 1887}
1888
6a9764ef
SM		 1889static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1890 struct mlx5e_params *params,
1891 struct mlx5e_channel_param *cparam)
f62b8bb8 1892{
bc77b240 1893 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1894
6a9764ef
SM		 1895 mlx5e_build_rq_param(priv, params, &cparam->rq);
1896 mlx5e_build_sq_param(priv, params, &cparam->sq);
1897 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
1898 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
1899 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
1900 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
1901 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
f62b8bb8
AV		 1902}
1903
55c2503d
SM		 1904int mlx5e_open_channels(struct mlx5e_priv *priv,
1905 struct mlx5e_channels *chs)
f62b8bb8 1906{
6b87663f 1907 struct mlx5e_channel_param *cparam;
03289b88 1908 int err = -ENOMEM;
f62b8bb8 1909 int i;
f62b8bb8 1910
6a9764ef 1911 chs->num = chs->params.num_channels;
03289b88 1912
ff9c852f 1913 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
6b87663f 1914 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
acc6c595
SM		 1915 if (!chs->c || !cparam)
1916 goto err_free;
f62b8bb8 1917
6a9764ef 1918 mlx5e_build_channel_param(priv, &chs->params, cparam);
ff9c852f 1919 for (i = 0; i < chs->num; i++) {
6a9764ef 1920 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
f62b8bb8
AV		 1921 if (err)
1922 goto err_close_channels;
1923 }
1924
6b87663f 1925 kfree(cparam);
f62b8bb8
AV		 1926 return 0;
1927
1928err_close_channels:
1929 for (i--; i >= 0; i--)
ff9c852f 1930 mlx5e_close_channel(chs->c[i]);
f62b8bb8 1931
acc6c595 1932err_free:
ff9c852f 1933 kfree(chs->c);
6b87663f 1934 kfree(cparam);
ff9c852f 1935 chs->num = 0;
f62b8bb8
AV		 1936 return err;
1937}
1938
acc6c595 1939static void mlx5e_activate_channels(struct mlx5e_channels *chs)
f62b8bb8
AV		 1940{
1941 int i;
1942
acc6c595
SM		 1943 for (i = 0; i < chs->num; i++)
1944 mlx5e_activate_channel(chs->c[i]);
1945}
1946
1947static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
1948{
1949 int err = 0;
1950 int i;
1951
1952 for (i = 0; i < chs->num; i++) {
1953 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
1954 if (err)
1955 break;
1956 }
1957
1958 return err;
1959}
1960
1961static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
1962{
1963 int i;
1964
1965 for (i = 0; i < chs->num; i++)
1966 mlx5e_deactivate_channel(chs->c[i]);
1967}
1968
55c2503d 1969void mlx5e_close_channels(struct mlx5e_channels *chs)
acc6c595
SM		 1970{
1971 int i;
c3b7c5c9 1972
ff9c852f
SM		 1973 for (i = 0; i < chs->num; i++)
1974 mlx5e_close_channel(chs->c[i]);
f62b8bb8 1975
ff9c852f
SM		 1976 kfree(chs->c);
1977 chs->num = 0;
f62b8bb8
AV		 1978}
1979
a5f97fee
SM		 1980static int
1981mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 1982{
1983 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1984 void *rqtc;
1985 int inlen;
1986 int err;
1da36696 1987 u32 *in;
a5f97fee 1988 int i;
f62b8bb8 1989
f62b8bb8 1990 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 1991 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1992 if (!in)
1993 return -ENOMEM;
1994
1995 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1996
1997 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1998 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1999
a5f97fee
SM		 2000 for (i = 0; i < sz; i++)
2001 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2be6967c 2002
398f3351
HHZ		 2003 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2004 if (!err)
2005 rqt->enabled = true;
f62b8bb8
AV		 2006
2007 kvfree(in);
1da36696
TT		 2008 return err;
2009}
2010
cb67b832 2011void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2012{
398f3351
HHZ		 2013 rqt->enabled = false;
2014 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2015}
2016
8f493ffd 2017int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2018{
2019 struct mlx5e_rqt *rqt = &priv->indir_rqt;
8f493ffd 2020 int err;
6bfd390b 2021
8f493ffd
SM		 2022 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2023 if (err)
2024 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2025 return err;
6bfd390b
HHZ		 2026}
2027
cb67b832 2028int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2029{
398f3351 2030 struct mlx5e_rqt *rqt;
1da36696
TT		 2031 int err;
2032 int ix;
2033
6bfd390b 2034 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351 2035 rqt = &priv->direct_tir[ix].rqt;
a5f97fee 2036 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
1da36696
TT		 2037 if (err)
2038 goto err_destroy_rqts;
2039 }
2040
2041 return 0;
2042
2043err_destroy_rqts:
8f493ffd 2044 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
1da36696 2045 for (ix--; ix >= 0; ix--)
398f3351 2046 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2047
f62b8bb8
AV		 2048 return err;
2049}
2050
8f493ffd
SM		 2051void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2052{
2053 int i;
2054
2055 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2056 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2057}
2058
a5f97fee
SM		 2059static int mlx5e_rx_hash_fn(int hfunc)
2060{
2061 return (hfunc == ETH_RSS_HASH_TOP) ?
2062 MLX5_RX_HASH_FN_TOEPLITZ :
2063 MLX5_RX_HASH_FN_INVERTED_XOR8;
2064}
2065
3f6d08d1 2066int mlx5e_bits_invert(unsigned long a, int size)
a5f97fee
SM		 2067{
2068 int inv = 0;
2069 int i;
2070
2071 for (i = 0; i < size; i++)
2072 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2073
2074 return inv;
2075}
2076
2077static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2078 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2079{
2080 int i;
2081
2082 for (i = 0; i < sz; i++) {
2083 u32 rqn;
2084
2085 if (rrp.is_rss) {
2086 int ix = i;
2087
2088 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2089 ix = mlx5e_bits_invert(i, ilog2(sz));
2090
6a9764ef 2091 ix = priv->channels.params.indirection_rqt[ix];
a5f97fee
SM		 2092 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2093 } else {
2094 rqn = rrp.rqn;
2095 }
2096 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2097 }
2098}
2099
2100int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2101 struct mlx5e_redirect_rqt_param rrp)
5c50368f
AS		 2102{
2103 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2104 void *rqtc;
2105 int inlen;
1da36696 2106 u32 *in;
5c50368f
AS		 2107 int err;
2108
5c50368f 2109 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2110 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2111 if (!in)
2112 return -ENOMEM;
2113
2114 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2115
2116 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5c50368f 2117 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
a5f97fee 2118 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
1da36696 2119 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2120
2121 kvfree(in);
5c50368f
AS		 2122 return err;
2123}
2124
a5f97fee
SM		 2125static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2126 struct mlx5e_redirect_rqt_param rrp)
2127{
2128 if (!rrp.is_rss)
2129 return rrp.rqn;
2130
2131 if (ix >= rrp.rss.channels->num)
2132 return priv->drop_rq.rqn;
2133
2134 return rrp.rss.channels->c[ix]->rq.rqn;
2135}
2136
2137static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2138 struct mlx5e_redirect_rqt_param rrp)
40ab6a6e 2139{
1da36696
TT		 2140 u32 rqtn;
2141 int ix;
2142
398f3351 2143 if (priv->indir_rqt.enabled) {
a5f97fee 2144 /* RSS RQ table */
398f3351 2145 rqtn = priv->indir_rqt.rqtn;
a5f97fee 2146 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
398f3351
HHZ		 2147 }
2148
a5f97fee
SM		 2149 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2150 struct mlx5e_redirect_rqt_param direct_rrp = {
2151 .is_rss = false,
95632791
AM		 2152 {
2153 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2154 },
a5f97fee
SM		 2155 };
2156
2157 /* Direct RQ Tables */
398f3351
HHZ		 2158 if (!priv->direct_tir[ix].rqt.enabled)
2159 continue;
a5f97fee 2160
398f3351 2161 rqtn = priv->direct_tir[ix].rqt.rqtn;
a5f97fee 2162 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
1da36696 2163 }
40ab6a6e
AS		 2164}
2165
a5f97fee
SM		 2166static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2167 struct mlx5e_channels *chs)
2168{
2169 struct mlx5e_redirect_rqt_param rrp = {
2170 .is_rss = true,
95632791
AM		 2171 {
2172 .rss = {
2173 .channels = chs,
2174 .hfunc = chs->params.rss_hfunc,
2175 }
2176 },
a5f97fee
SM		 2177 };
2178
2179 mlx5e_redirect_rqts(priv, rrp);
2180}
2181
2182static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2183{
2184 struct mlx5e_redirect_rqt_param drop_rrp = {
2185 .is_rss = false,
95632791
AM		 2186 {
2187 .rqn = priv->drop_rq.rqn,
2188 },
a5f97fee
SM		 2189 };
2190
2191 mlx5e_redirect_rqts(priv, drop_rrp);
2192}
2193
6a9764ef 2194static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
5c50368f 2195{
6a9764ef 2196 if (!params->lro_en)
5c50368f
AS		 2197 return;
2198
2199#define ROUGH_MAX_L2_L3_HDR_SZ 256
2200
2201 MLX5_SET(tirc, tirc, lro_enable_mask,
2202 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2203 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2204 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
6a9764ef
SM		 2205 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2206 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
5c50368f
AS		 2207}
2208
6a9764ef
SM		 2209void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2210 enum mlx5e_traffic_types tt,
7b3722fa 2211 void *tirc, bool inner)
bdfc028d 2212{
7b3722fa
GP		 2213 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2214 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
a100ff3e
GP		 2215
2216#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2217 MLX5_HASH_FIELD_SEL_DST_IP)
2218
2219#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2220 MLX5_HASH_FIELD_SEL_DST_IP |\
2221 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2222 MLX5_HASH_FIELD_SEL_L4_DPORT)
2223
2224#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2225 MLX5_HASH_FIELD_SEL_DST_IP |\
2226 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2227
6a9764ef
SM		 2228 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2229 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
bdfc028d
TT		 2230 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2231 rx_hash_toeplitz_key);
2232 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2233 rx_hash_toeplitz_key);
2234
2235 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
6a9764ef 2236 memcpy(rss_key, params->toeplitz_hash_key, len);
bdfc028d 2237 }
a100ff3e
GP		 2238
2239 switch (tt) {
2240 case MLX5E_TT_IPV4_TCP:
2241 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2242 MLX5_L3_PROT_TYPE_IPV4);
2243 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2244 MLX5_L4_PROT_TYPE_TCP);
2245 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2246 MLX5_HASH_IP_L4PORTS);
2247 break;
2248
2249 case MLX5E_TT_IPV6_TCP:
2250 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2251 MLX5_L3_PROT_TYPE_IPV6);
2252 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2253 MLX5_L4_PROT_TYPE_TCP);
2254 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2255 MLX5_HASH_IP_L4PORTS);
2256 break;
2257
2258 case MLX5E_TT_IPV4_UDP:
2259 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2260 MLX5_L3_PROT_TYPE_IPV4);
2261 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2262 MLX5_L4_PROT_TYPE_UDP);
2263 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2264 MLX5_HASH_IP_L4PORTS);
2265 break;
2266
2267 case MLX5E_TT_IPV6_UDP:
2268 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2269 MLX5_L3_PROT_TYPE_IPV6);
2270 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2271 MLX5_L4_PROT_TYPE_UDP);
2272 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2273 MLX5_HASH_IP_L4PORTS);
2274 break;
2275
2276 case MLX5E_TT_IPV4_IPSEC_AH:
2277 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2278 MLX5_L3_PROT_TYPE_IPV4);
2279 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2280 MLX5_HASH_IP_IPSEC_SPI);
2281 break;
2282
2283 case MLX5E_TT_IPV6_IPSEC_AH:
2284 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2285 MLX5_L3_PROT_TYPE_IPV6);
2286 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2287 MLX5_HASH_IP_IPSEC_SPI);
2288 break;
2289
2290 case MLX5E_TT_IPV4_IPSEC_ESP:
2291 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2292 MLX5_L3_PROT_TYPE_IPV4);
2293 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2294 MLX5_HASH_IP_IPSEC_SPI);
2295 break;
2296
2297 case MLX5E_TT_IPV6_IPSEC_ESP:
2298 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2299 MLX5_L3_PROT_TYPE_IPV6);
2300 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2301 MLX5_HASH_IP_IPSEC_SPI);
2302 break;
2303
2304 case MLX5E_TT_IPV4:
2305 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2306 MLX5_L3_PROT_TYPE_IPV4);
2307 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2308 MLX5_HASH_IP);
2309 break;
2310
2311 case MLX5E_TT_IPV6:
2312 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2313 MLX5_L3_PROT_TYPE_IPV6);
2314 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2315 MLX5_HASH_IP);
2316 break;
2317 default:
2318 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2319 }
bdfc028d
TT		 2320}
2321
ab0394fe 2322static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2323{
2324 struct mlx5_core_dev *mdev = priv->mdev;
2325
2326 void *in;
2327 void *tirc;
2328 int inlen;
2329 int err;
ab0394fe 2330 int tt;
1da36696 2331 int ix;
5c50368f
AS		 2332
2333 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1b9a07ee 2334 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2335 if (!in)
2336 return -ENOMEM;
2337
2338 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2339 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2340
6a9764ef 2341 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
5c50368f 2342
1da36696 2343 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2344 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2345 inlen);
ab0394fe 2346 if (err)
1da36696 2347 goto free_in;
ab0394fe 2348 }
5c50368f 2349
6bfd390b 2350 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2351 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2352 in, inlen);
2353 if (err)
2354 goto free_in;
2355 }
2356
2357free_in:
5c50368f
AS		 2358 kvfree(in);
2359
2360 return err;
2361}
2362
7b3722fa
GP		 2363static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2364 enum mlx5e_traffic_types tt,
2365 u32 *tirc)
2366{
2367 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2368
2369 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2370
2371 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2372 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2373 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2374
2375 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2376}
2377
cd255eff 2378static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2379{
40ab6a6e 2380 struct mlx5_core_dev *mdev = priv->mdev;
c139dbfd 2381 u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
40ab6a6e
AS		 2382 int err;
2383
cd255eff 2384 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2385 if (err)
2386 return err;
2387
cd255eff
SM		 2388 /* Update vport context MTU */
2389 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2390 return 0;
2391}
40ab6a6e 2392
cd255eff
SM		 2393static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2394{
2395 struct mlx5_core_dev *mdev = priv->mdev;
2396 u16 hw_mtu = 0;
2397 int err;
40ab6a6e 2398
cd255eff
SM		 2399 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2400 if (err || !hw_mtu) /* fallback to port oper mtu */
2401 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2402
c139dbfd 2403 *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
cd255eff
SM		 2404}
2405
2e20a151 2406static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
cd255eff 2407{
2e20a151 2408 struct net_device *netdev = priv->netdev;
cd255eff
SM		 2409 u16 mtu;
2410 int err;
2411
2412 err = mlx5e_set_mtu(priv, netdev->mtu);
2413 if (err)
2414 return err;
40ab6a6e 2415
cd255eff
SM		 2416 mlx5e_query_mtu(priv, &mtu);
2417 if (mtu != netdev->mtu)
2418 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2419 __func__, mtu, netdev->mtu);
40ab6a6e 2420
cd255eff 2421 netdev->mtu = mtu;
40ab6a6e
AS		 2422 return 0;
2423}
2424
08fb1dac
SM		 2425static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2426{
2427 struct mlx5e_priv *priv = netdev_priv(netdev);
6a9764ef
SM		 2428 int nch = priv->channels.params.num_channels;
2429 int ntc = priv->channels.params.num_tc;
08fb1dac
SM		 2430 int tc;
2431
2432 netdev_reset_tc(netdev);
2433
2434 if (ntc == 1)
2435 return;
2436
2437 netdev_set_num_tc(netdev, ntc);
2438
7ccdd084
RS		 2439 /* Map netdev TCs to offset 0
2440 * We have our own UP to TXQ mapping for QoS
2441 */
08fb1dac 2442 for (tc = 0; tc < ntc; tc++)
7ccdd084 2443 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2444}
2445
acc6c595
SM		 2446static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2447{
2448 struct mlx5e_channel *c;
2449 struct mlx5e_txqsq *sq;
2450 int i, tc;
2451
2452 for (i = 0; i < priv->channels.num; i++)
2453 for (tc = 0; tc < priv->profile->max_tc; tc++)
2454 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2455
2456 for (i = 0; i < priv->channels.num; i++) {
2457 c = priv->channels.c[i];
2458 for (tc = 0; tc < c->num_tc; tc++) {
2459 sq = &c->sq[tc];
2460 priv->txq2sq[sq->txq_ix] = sq;
2461 }
2462 }
2463}
2464
603f4a45 2465void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2466{
9008ae07
SM		 2467 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2468 struct net_device *netdev = priv->netdev;
2469
2470 mlx5e_netdev_set_tcs(netdev);
053ee0a7
TR		 2471 netif_set_real_num_tx_queues(netdev, num_txqs);
2472 netif_set_real_num_rx_queues(netdev, priv->channels.num);
9008ae07 2473
acc6c595
SM		 2474 mlx5e_build_channels_tx_maps(priv);
2475 mlx5e_activate_channels(&priv->channels);
2476 netif_tx_start_all_queues(priv->netdev);
9008ae07 2477
a9f7705f 2478 if (MLX5_VPORT_MANAGER(priv->mdev))
9008ae07
SM		 2479 mlx5e_add_sqs_fwd_rules(priv);
2480
acc6c595 2481 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
9008ae07 2482 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
acc6c595
SM		 2483}
2484
603f4a45 2485void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2486{
9008ae07
SM		 2487 mlx5e_redirect_rqts_to_drop(priv);
2488
a9f7705f 2489 if (MLX5_VPORT_MANAGER(priv->mdev))
9008ae07
SM		 2490 mlx5e_remove_sqs_fwd_rules(priv);
2491
acc6c595
SM		 2492 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2493 * polling for inactive tx queues.
2494 */
2495 netif_tx_stop_all_queues(priv->netdev);
2496 netif_tx_disable(priv->netdev);
2497 mlx5e_deactivate_channels(&priv->channels);
2498}
2499
55c2503d 2500void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2e20a151
SM		 2501 struct mlx5e_channels *new_chs,
2502 mlx5e_fp_hw_modify hw_modify)
55c2503d
SM		 2503{
2504 struct net_device *netdev = priv->netdev;
2505 int new_num_txqs;
7ca42c80 2506 int carrier_ok;
55c2503d
SM		 2507 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2508
7ca42c80 2509 carrier_ok = netif_carrier_ok(netdev);
55c2503d
SM		 2510 netif_carrier_off(netdev);
2511
2512 if (new_num_txqs < netdev->real_num_tx_queues)
2513 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2514
2515 mlx5e_deactivate_priv_channels(priv);
2516 mlx5e_close_channels(&priv->channels);
2517
2518 priv->channels = *new_chs;
2519
2e20a151
SM		 2520 /* New channels are ready to roll, modify HW settings if needed */
2521 if (hw_modify)
2522 hw_modify(priv);
2523
55c2503d
SM		 2524 mlx5e_refresh_tirs(priv, false);
2525 mlx5e_activate_priv_channels(priv);
2526
7ca42c80
ES		 2527 /* return carrier back if needed */
2528 if (carrier_ok)
2529 netif_carrier_on(netdev);
55c2503d
SM		 2530}
2531
237f258c 2532void mlx5e_timestamp_init(struct mlx5e_priv *priv)
7c39afb3
FD		 2533{
2534 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2535 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2536}
2537
40ab6a6e
AS		 2538int mlx5e_open_locked(struct net_device *netdev)
2539{
2540 struct mlx5e_priv *priv = netdev_priv(netdev);
40ab6a6e
AS		 2541 int err;
2542
2543 set_bit(MLX5E_STATE_OPENED, &priv->state);
2544
ff9c852f 2545 err = mlx5e_open_channels(priv, &priv->channels);
acc6c595 2546 if (err)
343b29f3 2547 goto err_clear_state_opened_flag;
40ab6a6e 2548
b676f653 2549 mlx5e_refresh_tirs(priv, false);
acc6c595 2550 mlx5e_activate_priv_channels(priv);
7ca42c80
ES		 2551 if (priv->profile->update_carrier)
2552 priv->profile->update_carrier(priv);
be4891af 2553
cb67b832
HHZ		 2554 if (priv->profile->update_stats)
2555 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2556
9b37b07f 2557 return 0;
343b29f3
AS		 2558
2559err_clear_state_opened_flag:
2560 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2561 return err;
40ab6a6e
AS		 2562}
2563
cb67b832 2564int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2565{
2566 struct mlx5e_priv *priv = netdev_priv(netdev);
2567 int err;
2568
2569 mutex_lock(&priv->state_lock);
2570 err = mlx5e_open_locked(netdev);
63bfd399
EBE		 2571 if (!err)
2572 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
40ab6a6e
AS		 2573 mutex_unlock(&priv->state_lock);
2574
2575 return err;
2576}
2577
2578int mlx5e_close_locked(struct net_device *netdev)
2579{
2580 struct mlx5e_priv *priv = netdev_priv(netdev);
2581
a1985740
AS		 2582 /* May already be CLOSED in case a previous configuration operation
2583 * (e.g RX/TX queue size change) that involves close&open failed.
2584 */
2585 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2586 return 0;
2587
40ab6a6e
AS		 2588 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2589
40ab6a6e 2590 netif_carrier_off(priv->netdev);
acc6c595
SM		 2591 mlx5e_deactivate_priv_channels(priv);
2592 mlx5e_close_channels(&priv->channels);
40ab6a6e
AS		 2593
2594 return 0;
2595}
2596
cb67b832 2597int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2598{
2599 struct mlx5e_priv *priv = netdev_priv(netdev);
2600 int err;
2601
26e59d80
MHY		 2602 if (!netif_device_present(netdev))
2603 return -ENODEV;
2604
40ab6a6e 2605 mutex_lock(&priv->state_lock);
63bfd399 2606 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
40ab6a6e
AS		 2607 err = mlx5e_close_locked(netdev);
2608 mutex_unlock(&priv->state_lock);
2609
2610 return err;
2611}
2612
a43b25da 2613static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2614 struct mlx5e_rq *rq,
2615 struct mlx5e_rq_param *param)
40ab6a6e 2616{
40ab6a6e
AS		 2617 void *rqc = param->rqc;
2618 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2619 int err;
2620
2621 param->wq.db_numa_node = param->wq.buf_numa_node;
2622
2623 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2624 &rq->wq_ctrl);
2625 if (err)
2626 return err;
2627
0ddf5432
JDB		 2628 /* Mark as unused given "Drop-RQ" packets never reach XDP */
2629 xdp_rxq_info_unused(&rq->xdp_rxq);
2630
a43b25da 2631 rq->mdev = mdev;
40ab6a6e
AS		 2632
2633 return 0;
2634}
2635
a43b25da 2636static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2637 struct mlx5e_cq *cq,
2638 struct mlx5e_cq_param *param)
40ab6a6e 2639{
2f0db879
GP		 2640 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2641 param->wq.db_numa_node = dev_to_node(&mdev->pdev->dev);
2642
95b6c6a5 2643 return mlx5e_alloc_cq_common(mdev, param, cq);
40ab6a6e
AS		 2644}
2645
a43b25da
SM		 2646static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2647 struct mlx5e_rq *drop_rq)
40ab6a6e 2648{
a43b25da
SM		 2649 struct mlx5e_cq_param cq_param = {};
2650 struct mlx5e_rq_param rq_param = {};
2651 struct mlx5e_cq *cq = &drop_rq->cq;
40ab6a6e
AS		 2652 int err;
2653
2f0db879 2654 mlx5e_build_drop_rq_param(mdev, &rq_param);
40ab6a6e 2655
a43b25da 2656 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
40ab6a6e
AS		 2657 if (err)
2658 return err;
2659
3b77235b 2660 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 2661 if (err)
3b77235b 2662 goto err_free_cq;
40ab6a6e 2663
a43b25da 2664 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
40ab6a6e 2665 if (err)
3b77235b 2666 goto err_destroy_cq;
40ab6a6e 2667
a43b25da 2668 err = mlx5e_create_rq(drop_rq, &rq_param);
40ab6a6e 2669 if (err)
3b77235b 2670 goto err_free_rq;
40ab6a6e
AS		 2671
2672 return 0;
2673
3b77235b 2674err_free_rq:
a43b25da 2675 mlx5e_free_rq(drop_rq);
40ab6a6e
AS		 2676
2677err_destroy_cq:
a43b25da 2678 mlx5e_destroy_cq(cq);
40ab6a6e 2679
3b77235b 2680err_free_cq:
a43b25da 2681 mlx5e_free_cq(cq);
3b77235b 2682
40ab6a6e
AS		 2683 return err;
2684}
2685
a43b25da 2686static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
40ab6a6e 2687{
a43b25da
SM		 2688 mlx5e_destroy_rq(drop_rq);
2689 mlx5e_free_rq(drop_rq);
2690 mlx5e_destroy_cq(&drop_rq->cq);
2691 mlx5e_free_cq(&drop_rq->cq);
40ab6a6e
AS		 2692}
2693
5426a0b2
SM		 2694int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2695 u32 underlay_qpn, u32 *tisn)
40ab6a6e 2696{
c4f287c4 2697 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2698 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2699
08fb1dac 2700 MLX5_SET(tisc, tisc, prio, tc << 1);
5426a0b2 2701 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
b50d292b 2702 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2703
2704 if (mlx5_lag_is_lacp_owner(mdev))
2705 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2706
5426a0b2 2707 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
40ab6a6e
AS		 2708}
2709
5426a0b2 2710void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
40ab6a6e 2711{
5426a0b2 2712 mlx5_core_destroy_tis(mdev, tisn);
40ab6a6e
AS		 2713}
2714
cb67b832 2715int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2716{
2717 int err;
2718 int tc;
2719
6bfd390b 2720 for (tc = 0; tc < priv->profile->max_tc; tc++) {
5426a0b2 2721 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
40ab6a6e
AS		 2722 if (err)
2723 goto err_close_tises;
2724 }
2725
2726 return 0;
2727
2728err_close_tises:
2729 for (tc--; tc >= 0; tc--)
5426a0b2 2730 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2731
2732 return err;
2733}
2734
cb67b832 2735void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2736{
2737 int tc;
2738
6bfd390b 2739 for (tc = 0; tc < priv->profile->max_tc; tc++)
5426a0b2 2740 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2741}
2742
6a9764ef
SM		 2743static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2744 enum mlx5e_traffic_types tt,
2745 u32 *tirc)
f62b8bb8 2746{
b50d292b 2747 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2748
6a9764ef 2749 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
f62b8bb8 2750
4cbeaff5 2751 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2752 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
7b3722fa 2753 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
f62b8bb8
AV		 2754}
2755
6a9764ef 2756static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
f62b8bb8 2757{
b50d292b 2758 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696 2759
6a9764ef 2760 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
1da36696
TT		 2761
2762 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2763 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2764 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2765}
2766
8f493ffd 2767int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2768{
724b2aa1 2769 struct mlx5e_tir *tir;
f62b8bb8
AV		 2770 void *tirc;
2771 int inlen;
7b3722fa 2772 int i = 0;
f62b8bb8 2773 int err;
1da36696 2774 u32 *in;
1da36696 2775 int tt;
f62b8bb8
AV		 2776
2777 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2778 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2779 if (!in)
2780 return -ENOMEM;
2781
1da36696
TT		 2782 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2783 memset(in, 0, inlen);
724b2aa1 2784 tir = &priv->indir_tir[tt];
1da36696 2785 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2786 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
724b2aa1 2787 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
7b3722fa
GP		 2788 if (err) {
2789 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2790 goto err_destroy_inner_tirs;
2791 }
f62b8bb8
AV		 2792 }
2793
7b3722fa
GP		 2794 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2795 goto out;
2796
2797 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2798 memset(in, 0, inlen);
2799 tir = &priv->inner_indir_tir[i];
2800 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2801 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2802 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2803 if (err) {
2804 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2805 goto err_destroy_inner_tirs;
2806 }
2807 }
2808
2809out:
6bfd390b
HHZ		 2810 kvfree(in);
2811
2812 return 0;
2813
7b3722fa
GP		 2814err_destroy_inner_tirs:
2815 for (i--; i >= 0; i--)
2816 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2817
6bfd390b
HHZ		 2818 for (tt--; tt >= 0; tt--)
2819 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2820
2821 kvfree(in);
2822
2823 return err;
2824}
2825
cb67b832 2826int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2827{
2828 int nch = priv->profile->max_nch(priv->mdev);
2829 struct mlx5e_tir *tir;
2830 void *tirc;
2831 int inlen;
2832 int err;
2833 u32 *in;
2834 int ix;
2835
2836 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2837 in = kvzalloc(inlen, GFP_KERNEL);
6bfd390b
HHZ		 2838 if (!in)
2839 return -ENOMEM;
2840
1da36696
TT		 2841 for (ix = 0; ix < nch; ix++) {
2842 memset(in, 0, inlen);
724b2aa1 2843 tir = &priv->direct_tir[ix];
1da36696 2844 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2845 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
724b2aa1 2846 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2847 if (err)
2848 goto err_destroy_ch_tirs;
2849 }
2850
2851 kvfree(in);
2852
f62b8bb8
AV		 2853 return 0;
2854
1da36696 2855err_destroy_ch_tirs:
8f493ffd 2856 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
1da36696 2857 for (ix--; ix >= 0; ix--)
724b2aa1 2858 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2859
1da36696 2860 kvfree(in);
f62b8bb8
AV		 2861
2862 return err;
2863}
2864
8f493ffd 2865void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2866{
2867 int i;
2868
1da36696 2869 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2870 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
7b3722fa
GP		 2871
2872 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2873 return;
2874
2875 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2876 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
f62b8bb8
AV		 2877}
2878
cb67b832 2879void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2880{
2881 int nch = priv->profile->max_nch(priv->mdev);
2882 int i;
2883
2884 for (i = 0; i < nch; i++)
2885 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2886}
2887
102722fc
GE		 2888static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2889{
2890 int err = 0;
2891 int i;
2892
2893 for (i = 0; i < chs->num; i++) {
2894 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2895 if (err)
2896 return err;
2897 }
2898
2899 return 0;
2900}
2901
f6d96a20 2902static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
36350114
GP		 2903{
2904 int err = 0;
2905 int i;
2906
ff9c852f
SM		 2907 for (i = 0; i < chs->num; i++) {
2908 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
36350114
GP		 2909 if (err)
2910 return err;
2911 }
2912
2913 return 0;
2914}
2915
0cf0f6d3
JP		 2916static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
2917 struct tc_mqprio_qopt *mqprio)
08fb1dac
SM		 2918{
2919 struct mlx5e_priv *priv = netdev_priv(netdev);
6f9485af 2920 struct mlx5e_channels new_channels = {};
0cf0f6d3 2921 u8 tc = mqprio->num_tc;
08fb1dac
SM		 2922 int err = 0;
2923
0cf0f6d3
JP		 2924 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2925
08fb1dac
SM		 2926 if (tc && tc != MLX5E_MAX_NUM_TC)
2927 return -EINVAL;
2928
2929 mutex_lock(&priv->state_lock);
2930
6f9485af
SM		 2931 new_channels.params = priv->channels.params;
2932 new_channels.params.num_tc = tc ? tc : 1;
08fb1dac 2933
20b6a1c7 2934 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6f9485af
SM		 2935 priv->channels.params = new_channels.params;
2936 goto out;
2937 }
08fb1dac 2938
6f9485af
SM		 2939 err = mlx5e_open_channels(priv, &new_channels);
2940 if (err)
2941 goto out;
08fb1dac 2942
2e20a151 2943 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
6f9485af 2944out:
08fb1dac 2945 mutex_unlock(&priv->state_lock);
08fb1dac
SM		 2946 return err;
2947}
2948
e80541ec 2949#ifdef CONFIG_MLX5_ESWITCH
d6c862ba 2950static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
0cf0f6d3 2951 struct tc_cls_flower_offload *cls_flower)
08fb1dac 2952{
0cf0f6d3
JP		 2953 switch (cls_flower->command) {
2954 case TC_CLSFLOWER_REPLACE:
5fd9fc4e 2955 return mlx5e_configure_flower(priv, cls_flower);
0cf0f6d3
JP		 2956 case TC_CLSFLOWER_DESTROY:
2957 return mlx5e_delete_flower(priv, cls_flower);
2958 case TC_CLSFLOWER_STATS:
2959 return mlx5e_stats_flower(priv, cls_flower);
2960 default:
a5fcf8a6 2961 return -EOPNOTSUPP;
0cf0f6d3
JP		 2962 }
2963}
d6c862ba
JP		 2964
2965int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2966 void *cb_priv)
2967{
2968 struct mlx5e_priv *priv = cb_priv;
2969
9ab88e83 2970 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
44ae12a7
JP		 2971 return -EOPNOTSUPP;
2972
d6c862ba
JP		 2973 switch (type) {
2974 case TC_SETUP_CLSFLOWER:
2975 return mlx5e_setup_tc_cls_flower(priv, type_data);
2976 default:
2977 return -EOPNOTSUPP;
2978 }
2979}
2980
2981static int mlx5e_setup_tc_block(struct net_device *dev,
2982 struct tc_block_offload *f)
2983{
2984 struct mlx5e_priv *priv = netdev_priv(dev);
2985
2986 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
2987 return -EOPNOTSUPP;
2988
2989 switch (f->command) {
2990 case TC_BLOCK_BIND:
2991 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
2992 priv, priv);
2993 case TC_BLOCK_UNBIND:
2994 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
2995 priv);
2996 return 0;
2997 default:
2998 return -EOPNOTSUPP;
2999 }
3000}
e80541ec 3001#endif
a5fcf8a6 3002
9afe9a53
OG		 3003static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3004 void *type_data)
0cf0f6d3 3005{
2572ac53 3006 switch (type) {
fde6af47 3007#ifdef CONFIG_MLX5_ESWITCH
d6c862ba
JP		 3008 case TC_SETUP_BLOCK:
3009 return mlx5e_setup_tc_block(dev, type_data);
fde6af47 3010#endif
575ed7d3 3011 case TC_SETUP_QDISC_MQPRIO:
de4784ca 3012 return mlx5e_setup_tc_mqprio(dev, type_data);
e8f887ac
AV		 3013 default:
3014 return -EOPNOTSUPP;
3015 }
08fb1dac
SM		 3016}
3017
bc1f4470 3018static void
f62b8bb8
AV		 3019mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3020{
3021 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 3022 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 3023 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 3024 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 3025
370bad0f
OG		 3026 if (mlx5e_is_uplink_rep(priv)) {
3027 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3028 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3029 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3030 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3031 } else {
3032 stats->rx_packets = sstats->rx_packets;
3033 stats->rx_bytes = sstats->rx_bytes;
3034 stats->tx_packets = sstats->tx_packets;
3035 stats->tx_bytes = sstats->tx_bytes;
3036 stats->tx_dropped = sstats->tx_queue_dropped;
3037 }
269e6b3a
GP		 3038
3039 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 3040
3041 stats->rx_length_errors =
9218b44d
GP		 3042 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3043 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3044 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 3045 stats->rx_crc_errors =
9218b44d
GP		 3046 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3047 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3048 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a
GP		 3049 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3050 stats->rx_frame_errors;
3051 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3052
3053 /* vport multicast also counts packets that are dropped due to steering
3054 * or rx out of buffer
3055 */
9218b44d
GP		 3056 stats->multicast =
3057 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 3058}
3059
3060static void mlx5e_set_rx_mode(struct net_device *dev)
3061{
3062 struct mlx5e_priv *priv = netdev_priv(dev);
3063
7bb29755 3064 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3065}
3066
3067static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3068{
3069 struct mlx5e_priv *priv = netdev_priv(netdev);
3070 struct sockaddr *saddr = addr;
3071
3072 if (!is_valid_ether_addr(saddr->sa_data))
3073 return -EADDRNOTAVAIL;
3074
3075 netif_addr_lock_bh(netdev);
3076 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3077 netif_addr_unlock_bh(netdev);
3078
7bb29755 3079 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3080
3081 return 0;
3082}
3083
75b81ce7 3084#define MLX5E_SET_FEATURE(features, feature, enable) \
0e405443
GP		 3085 do { \
3086 if (enable) \
75b81ce7 3087 *features |= feature; \
0e405443 3088 else \
75b81ce7 3089 *features &= ~feature; \
0e405443
GP		 3090 } while (0)
3091
3092typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3093
3094static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 3095{
3096 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3097 struct mlx5e_channels new_channels = {};
3098 int err = 0;
3099 bool reset;
f62b8bb8
AV		 3100
3101 mutex_lock(&priv->state_lock);
f62b8bb8 3102
2e20a151
SM		 3103 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3104 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3105
2e20a151
SM		 3106 new_channels.params = priv->channels.params;
3107 new_channels.params.lro_en = enable;
3108
3109 if (!reset) {
3110 priv->channels.params = new_channels.params;
3111 err = mlx5e_modify_tirs_lro(priv);
3112 goto out;
98e81b0a 3113 }
f62b8bb8 3114
2e20a151
SM		 3115 err = mlx5e_open_channels(priv, &new_channels);
3116 if (err)
3117 goto out;
0e405443 3118
2e20a151
SM		 3119 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3120out:
9b37b07f 3121 mutex_unlock(&priv->state_lock);
0e405443
GP		 3122 return err;
3123}
3124
2b52a283 3125static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
0e405443
GP		 3126{
3127 struct mlx5e_priv *priv = netdev_priv(netdev);
3128
3129 if (enable)
2b52a283 3130 mlx5e_enable_cvlan_filter(priv);
0e405443 3131 else
2b52a283 3132 mlx5e_disable_cvlan_filter(priv);
0e405443
GP		 3133
3134 return 0;
3135}
3136
3137static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3138{
3139 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 3140
0e405443 3141 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 3142 netdev_err(netdev,
3143 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3144 return -EINVAL;
3145 }
3146
0e405443
GP		 3147 return 0;
3148}
3149
94cb1ebb
EBE		 3150static int set_feature_rx_all(struct net_device *netdev, bool enable)
3151{
3152 struct mlx5e_priv *priv = netdev_priv(netdev);
3153 struct mlx5_core_dev *mdev = priv->mdev;
3154
3155 return mlx5_set_port_fcs(mdev, !enable);
3156}
3157
102722fc
GE		 3158static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3159{
3160 struct mlx5e_priv *priv = netdev_priv(netdev);
3161 int err;
3162
3163 mutex_lock(&priv->state_lock);
3164
3165 priv->channels.params.scatter_fcs_en = enable;
3166 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3167 if (err)
3168 priv->channels.params.scatter_fcs_en = !enable;
3169
3170 mutex_unlock(&priv->state_lock);
3171
3172 return err;
3173}
3174
36350114
GP		 3175static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3176{
3177 struct mlx5e_priv *priv = netdev_priv(netdev);
ff9c852f 3178 int err = 0;
36350114
GP		 3179
3180 mutex_lock(&priv->state_lock);
3181
6a9764ef 3182 priv->channels.params.vlan_strip_disable = !enable;
ff9c852f
SM		 3183 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3184 goto unlock;
3185
3186 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
36350114 3187 if (err)
6a9764ef 3188 priv->channels.params.vlan_strip_disable = enable;
36350114 3189
ff9c852f 3190unlock:
36350114
GP		 3191 mutex_unlock(&priv->state_lock);
3192
3193 return err;
3194}
3195
45bf454a
MG		 3196#ifdef CONFIG_RFS_ACCEL
3197static int set_feature_arfs(struct net_device *netdev, bool enable)
3198{
3199 struct mlx5e_priv *priv = netdev_priv(netdev);
3200 int err;
3201
3202 if (enable)
3203 err = mlx5e_arfs_enable(priv);
3204 else
3205 err = mlx5e_arfs_disable(priv);
3206
3207 return err;
3208}
3209#endif
3210
0e405443 3211static int mlx5e_handle_feature(struct net_device *netdev,
75b81ce7 3212 netdev_features_t *features,
0e405443
GP		 3213 netdev_features_t wanted_features,
3214 netdev_features_t feature,
3215 mlx5e_feature_handler feature_handler)
3216{
3217 netdev_features_t changes = wanted_features ^ netdev->features;
3218 bool enable = !!(wanted_features & feature);
3219 int err;
3220
3221 if (!(changes & feature))
3222 return 0;
3223
3224 err = feature_handler(netdev, enable);
3225 if (err) {
b20eab15
GP		 3226 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3227 enable ? "Enable" : "Disable", &feature, err);
0e405443
GP		 3228 return err;
3229 }
3230
75b81ce7 3231 MLX5E_SET_FEATURE(features, feature, enable);
0e405443
GP		 3232 return 0;
3233}
3234
3235static int mlx5e_set_features(struct net_device *netdev,
3236 netdev_features_t features)
3237{
75b81ce7 3238 netdev_features_t oper_features = netdev->features;
0e405443
GP		 3239 int err;
3240
75b81ce7
GP		 3241 err = mlx5e_handle_feature(netdev, &oper_features, features,
3242 NETIF_F_LRO, set_feature_lro);
3243 err |= mlx5e_handle_feature(netdev, &oper_features, features,
0e405443 3244 NETIF_F_HW_VLAN_CTAG_FILTER,
2b52a283 3245 set_feature_cvlan_filter);
75b81ce7
GP		 3246 err |= mlx5e_handle_feature(netdev, &oper_features, features,
3247 NETIF_F_HW_TC, set_feature_tc_num_filters);
3248 err |= mlx5e_handle_feature(netdev, &oper_features, features,
3249 NETIF_F_RXALL, set_feature_rx_all);
3250 err |= mlx5e_handle_feature(netdev, &oper_features, features,
3251 NETIF_F_RXFCS, set_feature_rx_fcs);
3252 err |= mlx5e_handle_feature(netdev, &oper_features, features,
3253 NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
45bf454a 3254#ifdef CONFIG_RFS_ACCEL
75b81ce7
GP		 3255 err |= mlx5e_handle_feature(netdev, &oper_features, features,
3256 NETIF_F_NTUPLE, set_feature_arfs);
45bf454a 3257#endif
0e405443 3258
75b81ce7
GP		 3259 if (err) {
3260 netdev->features = oper_features;
3261 return -EINVAL;
3262 }
3263
3264 return 0;
f62b8bb8
AV		 3265}
3266
7d92d580
GP		 3267static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3268 netdev_features_t features)
3269{
3270 struct mlx5e_priv *priv = netdev_priv(netdev);
3271
3272 mutex_lock(&priv->state_lock);
3273 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3274 /* HW strips the outer C-tag header, this is a problem
3275 * for S-tag traffic.
3276 */
3277 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3278 if (!priv->channels.params.vlan_strip_disable)
3279 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3280 }
3281 mutex_unlock(&priv->state_lock);
3282
3283 return features;
3284}
3285
f62b8bb8
AV		 3286static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3287{
3288 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3289 struct mlx5e_channels new_channels = {};
3290 int curr_mtu;
98e81b0a 3291 int err = 0;
506753b0 3292 bool reset;
f62b8bb8 3293
f62b8bb8 3294 mutex_lock(&priv->state_lock);
98e81b0a 3295
6a9764ef
SM		 3296 reset = !priv->channels.params.lro_en &&
3297 (priv->channels.params.rq_wq_type !=
506753b0
TT		 3298 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3299
2e20a151 3300 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3301
2e20a151 3302 curr_mtu = netdev->mtu;
f62b8bb8 3303 netdev->mtu = new_mtu;
98e81b0a 3304
2e20a151
SM		 3305 if (!reset) {
3306 mlx5e_set_dev_port_mtu(priv);
3307 goto out;
3308 }
98e81b0a 3309
2e20a151
SM		 3310 new_channels.params = priv->channels.params;
3311 err = mlx5e_open_channels(priv, &new_channels);
3312 if (err) {
3313 netdev->mtu = curr_mtu;
3314 goto out;
3315 }
3316
3317 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
f62b8bb8 3318
2e20a151
SM		 3319out:
3320 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 3321 return err;
3322}
3323
7c39afb3
FD		 3324int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3325{
3326 struct hwtstamp_config config;
3327 int err;
3328
3329 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3330 return -EOPNOTSUPP;
3331
3332 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3333 return -EFAULT;
3334
3335 /* TX HW timestamp */
3336 switch (config.tx_type) {
3337 case HWTSTAMP_TX_OFF:
3338 case HWTSTAMP_TX_ON:
3339 break;
3340 default:
3341 return -ERANGE;
3342 }
3343
3344 mutex_lock(&priv->state_lock);
3345 /* RX HW timestamp */
3346 switch (config.rx_filter) {
3347 case HWTSTAMP_FILTER_NONE:
3348 /* Reset CQE compression to Admin default */
3349 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3350 break;
3351 case HWTSTAMP_FILTER_ALL:
3352 case HWTSTAMP_FILTER_SOME:
3353 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3354 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3355 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3356 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3357 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3358 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3359 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3360 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3361 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3362 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3363 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3364 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3365 case HWTSTAMP_FILTER_NTP_ALL:
3366 /* Disable CQE compression */
3367 netdev_warn(priv->netdev, "Disabling cqe compression");
3368 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3369 if (err) {
3370 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3371 mutex_unlock(&priv->state_lock);
3372 return err;
3373 }
3374 config.rx_filter = HWTSTAMP_FILTER_ALL;
3375 break;
3376 default:
3377 mutex_unlock(&priv->state_lock);
3378 return -ERANGE;
3379 }
3380
3381 memcpy(&priv->tstamp, &config, sizeof(config));
3382 mutex_unlock(&priv->state_lock);
3383
3384 return copy_to_user(ifr->ifr_data, &config,
3385 sizeof(config)) ? -EFAULT : 0;
3386}
3387
3388int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3389{
3390 struct hwtstamp_config *cfg = &priv->tstamp;
3391
3392 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3393 return -EOPNOTSUPP;
3394
3395 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3396}
3397
ef9814de
EBE		 3398static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3399{
1170fbd8
FD		 3400 struct mlx5e_priv *priv = netdev_priv(dev);
3401
ef9814de
EBE		 3402 switch (cmd) {
3403 case SIOCSHWTSTAMP:
1170fbd8 3404 return mlx5e_hwstamp_set(priv, ifr);
ef9814de 3405 case SIOCGHWTSTAMP:
1170fbd8 3406 return mlx5e_hwstamp_get(priv, ifr);
ef9814de
EBE		 3407 default:
3408 return -EOPNOTSUPP;
3409 }
3410}
3411
e80541ec 3412#ifdef CONFIG_MLX5_ESWITCH
66e49ded
SM		 3413static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3414{
3415 struct mlx5e_priv *priv = netdev_priv(dev);
3416 struct mlx5_core_dev *mdev = priv->mdev;
3417
3418 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3419}
3420
79aab093
MS		 3421static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3422 __be16 vlan_proto)
66e49ded
SM		 3423{
3424 struct mlx5e_priv *priv = netdev_priv(dev);
3425 struct mlx5_core_dev *mdev = priv->mdev;
3426
79aab093
MS		 3427 if (vlan_proto != htons(ETH_P_8021Q))
3428 return -EPROTONOSUPPORT;
3429
66e49ded
SM		 3430 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3431 vlan, qos);
3432}
3433
f942380c
MHY		 3434static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3435{
3436 struct mlx5e_priv *priv = netdev_priv(dev);
3437 struct mlx5_core_dev *mdev = priv->mdev;
3438
3439 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3440}
3441
1edc57e2
MHY		 3442static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3443{
3444 struct mlx5e_priv *priv = netdev_priv(dev);
3445 struct mlx5_core_dev *mdev = priv->mdev;
3446
3447 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3448}
bd77bf1c
MHY		 3449
3450static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3451 int max_tx_rate)
3452{
3453 struct mlx5e_priv *priv = netdev_priv(dev);
3454 struct mlx5_core_dev *mdev = priv->mdev;
3455
bd77bf1c 3456 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3457 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3458}
3459
66e49ded
SM		 3460static int mlx5_vport_link2ifla(u8 esw_link)
3461{
3462 switch (esw_link) {
3463 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3464 return IFLA_VF_LINK_STATE_DISABLE;
3465 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3466 return IFLA_VF_LINK_STATE_ENABLE;
3467 }
3468 return IFLA_VF_LINK_STATE_AUTO;
3469}
3470
3471static int mlx5_ifla_link2vport(u8 ifla_link)
3472{
3473 switch (ifla_link) {
3474 case IFLA_VF_LINK_STATE_DISABLE:
3475 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3476 case IFLA_VF_LINK_STATE_ENABLE:
3477 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3478 }
3479 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3480}
3481
3482static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3483 int link_state)
3484{
3485 struct mlx5e_priv *priv = netdev_priv(dev);
3486 struct mlx5_core_dev *mdev = priv->mdev;
3487
3488 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3489 mlx5_ifla_link2vport(link_state));
3490}
3491
3492static int mlx5e_get_vf_config(struct net_device *dev,
3493 int vf, struct ifla_vf_info *ivi)
3494{
3495 struct mlx5e_priv *priv = netdev_priv(dev);
3496 struct mlx5_core_dev *mdev = priv->mdev;
3497 int err;
3498
3499 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3500 if (err)
3501 return err;
3502 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3503 return 0;
3504}
3505
3506static int mlx5e_get_vf_stats(struct net_device *dev,
3507 int vf, struct ifla_vf_stats *vf_stats)
3508{
3509 struct mlx5e_priv *priv = netdev_priv(dev);
3510 struct mlx5_core_dev *mdev = priv->mdev;
3511
3512 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3513 vf_stats);
3514}
e80541ec 3515#endif
66e49ded 3516
1ad9a00a
PB		 3517static void mlx5e_add_vxlan_port(struct net_device *netdev,
3518 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3519{
3520 struct mlx5e_priv *priv = netdev_priv(netdev);
3521
974c3f30
AD		 3522 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3523 return;
3524
b3f63c3d
MF		 3525 if (!mlx5e_vxlan_allowed(priv->mdev))
3526 return;
3527
974c3f30 3528 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3529}
3530
1ad9a00a
PB		 3531static void mlx5e_del_vxlan_port(struct net_device *netdev,
3532 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3533{
3534 struct mlx5e_priv *priv = netdev_priv(netdev);
3535
974c3f30
AD		 3536 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3537 return;
3538
b3f63c3d
MF		 3539 if (!mlx5e_vxlan_allowed(priv->mdev))
3540 return;
3541
974c3f30 3542 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3543}
3544
27299841
GP		 3545static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3546 struct sk_buff *skb,
3547 netdev_features_t features)
b3f63c3d 3548{
2989ad1e 3549 unsigned int offset = 0;
b3f63c3d 3550 struct udphdr *udph;
27299841
GP		 3551 u8 proto;
3552 u16 port;
b3f63c3d
MF		 3553
3554 switch (vlan_get_protocol(skb)) {
3555 case htons(ETH_P_IP):
3556 proto = ip_hdr(skb)->protocol;
3557 break;
3558 case htons(ETH_P_IPV6):
2989ad1e 3559 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
b3f63c3d
MF		 3560 break;
3561 default:
3562 goto out;
3563 }
3564
27299841
GP		 3565 switch (proto) {
3566 case IPPROTO_GRE:
3567 return features;
3568 case IPPROTO_UDP:
b3f63c3d
MF		 3569 udph = udp_hdr(skb);
3570 port = be16_to_cpu(udph->dest);
b3f63c3d 3571
27299841
GP		 3572 /* Verify if UDP port is being offloaded by HW */
3573 if (mlx5e_vxlan_lookup_port(priv, port))
3574 return features;
3575 }
b3f63c3d
MF		 3576
3577out:
3578 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3579 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3580}
3581
3582static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3583 struct net_device *netdev,
3584 netdev_features_t features)
3585{
3586 struct mlx5e_priv *priv = netdev_priv(netdev);
3587
3588 features = vlan_features_check(skb, features);
3589 features = vxlan_features_check(skb, features);
3590
2ac9cfe7
IT		 3591#ifdef CONFIG_MLX5_EN_IPSEC
3592 if (mlx5e_ipsec_feature_check(skb, netdev, features))
3593 return features;
3594#endif
3595
b3f63c3d
MF		 3596 /* Validate if the tunneled packet is being offloaded by HW */
3597 if (skb->encapsulation &&
3598 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
27299841 3599 return mlx5e_tunnel_features_check(priv, skb, features);
b3f63c3d
MF		 3600
3601 return features;
3602}
3603
7ca560b5
EBE		 3604static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
3605 struct mlx5e_txqsq *sq)
3606{
3607 struct mlx5e_priv *priv = netdev_priv(dev);
3608 struct mlx5_core_dev *mdev = priv->mdev;
3609 int irqn_not_used, eqn;
3610 struct mlx5_eq *eq;
3611 u32 eqe_count;
3612
3613 if (mlx5_vector2eqn(mdev, sq->cq.mcq.vector, &eqn, &irqn_not_used))
3614 return false;
3615
3616 eq = mlx5_eqn2eq(mdev, eqn);
3617 if (IS_ERR(eq))
3618 return false;
3619
3620 netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
3621 eqn, eq->cons_index, eq->irqn);
3622
3623 eqe_count = mlx5_eq_poll_irq_disabled(eq);
3624 if (!eqe_count)
3625 return false;
3626
3627 netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
57d689a8 3628 sq->channel->stats.eq_rearm++;
7ca560b5
EBE		 3629 return true;
3630}
3631
3947ca18
DJ		 3632static void mlx5e_tx_timeout(struct net_device *dev)
3633{
3634 struct mlx5e_priv *priv = netdev_priv(dev);
7ca560b5 3635 bool reopen_channels = false;
3947ca18
DJ		 3636 int i;
3637
3638 netdev_err(dev, "TX timeout detected\n");
3639
6a9764ef 3640 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
84990945 3641 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
acc6c595 3642 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3947ca18 3643
84990945 3644 if (!netif_xmit_stopped(dev_queue))
3947ca18 3645 continue;
84990945
EBE		 3646 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
3647 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
3648 jiffies_to_usecs(jiffies - dev_queue->trans_start));
3a32b26a 3649
7ca560b5
EBE		 3650 /* If we recover a lost interrupt, most likely TX timeout will
3651 * be resolved, skip reopening channels
3652 */
3653 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
3654 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3655 reopen_channels = true;
3656 }
3947ca18
DJ		 3657 }
3658
7ca560b5 3659 if (reopen_channels && test_bit(MLX5E_STATE_OPENED, &priv->state))
3947ca18
DJ		 3660 schedule_work(&priv->tx_timeout_work);
3661}
3662
86994156
RS		 3663static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3664{
3665 struct mlx5e_priv *priv = netdev_priv(netdev);
3666 struct bpf_prog *old_prog;
3667 int err = 0;
3668 bool reset, was_opened;
3669 int i;
3670
3671 mutex_lock(&priv->state_lock);
3672
3673 if ((netdev->features & NETIF_F_LRO) && prog) {
3674 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3675 err = -EINVAL;
3676 goto unlock;
3677 }
3678
547eede0
IT		 3679 if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3680 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3681 err = -EINVAL;
3682 goto unlock;
3683 }
3684
86994156
RS		 3685 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3686 /* no need for full reset when exchanging programs */
6a9764ef 3687 reset = (!priv->channels.params.xdp_prog || !prog);
86994156
RS		 3688
3689 if (was_opened && reset)
3690 mlx5e_close_locked(netdev);
c54c0629
DB		 3691 if (was_opened && !reset) {
3692 /* num_channels is invariant here, so we can take the
3693 * batched reference right upfront.
3694 */
6a9764ef 3695 prog = bpf_prog_add(prog, priv->channels.num);
c54c0629
DB		 3696 if (IS_ERR(prog)) {
3697 err = PTR_ERR(prog);
3698 goto unlock;
3699 }
3700 }
86994156 3701
c54c0629
DB		 3702 /* exchange programs, extra prog reference we got from caller
3703 * as long as we don't fail from this point onwards.
3704 */
6a9764ef 3705 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
86994156
RS		 3706 if (old_prog)
3707 bpf_prog_put(old_prog);
3708
3709 if (reset) /* change RQ type according to priv->xdp_prog */
6a9764ef 3710 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
86994156
RS		 3711
3712 if (was_opened && reset)
3713 mlx5e_open_locked(netdev);
3714
3715 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3716 goto unlock;
3717
3718 /* exchanging programs w/o reset, we update ref counts on behalf
3719 * of the channels RQs here.
3720 */
ff9c852f
SM		 3721 for (i = 0; i < priv->channels.num; i++) {
3722 struct mlx5e_channel *c = priv->channels.c[i];
86994156 3723
c0f1147d 3724 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3725 napi_synchronize(&c->napi);
3726 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3727
3728 old_prog = xchg(&c->rq.xdp_prog, prog);
3729
c0f1147d 3730 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156 3731 /* napi_schedule in case we have missed anything */
86994156
RS		 3732 napi_schedule(&c->napi);
3733
3734 if (old_prog)
3735 bpf_prog_put(old_prog);
3736 }
3737
3738unlock:
3739 mutex_unlock(&priv->state_lock);
3740 return err;
3741}
3742
821b2e29 3743static u32 mlx5e_xdp_query(struct net_device *dev)
86994156
RS		 3744{
3745 struct mlx5e_priv *priv = netdev_priv(dev);
821b2e29
MKL		 3746 const struct bpf_prog *xdp_prog;
3747 u32 prog_id = 0;
86994156 3748
821b2e29
MKL		 3749 mutex_lock(&priv->state_lock);
3750 xdp_prog = priv->channels.params.xdp_prog;
3751 if (xdp_prog)
3752 prog_id = xdp_prog->aux->id;
3753 mutex_unlock(&priv->state_lock);
3754
3755 return prog_id;
86994156
RS		 3756}
3757
f4e63525 3758static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
86994156
RS		 3759{
3760 switch (xdp->command) {
3761 case XDP_SETUP_PROG:
3762 return mlx5e_xdp_set(dev, xdp->prog);
3763 case XDP_QUERY_PROG:
821b2e29
MKL		 3764 xdp->prog_id = mlx5e_xdp_query(dev);
3765 xdp->prog_attached = !!xdp->prog_id;
86994156
RS		 3766 return 0;
3767 default:
3768 return -EINVAL;
3769 }
3770}
3771
80378384
CO		 3772#ifdef CONFIG_NET_POLL_CONTROLLER
3773/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3774 * reenabling interrupts.
3775 */
3776static void mlx5e_netpoll(struct net_device *dev)
3777{
3778 struct mlx5e_priv *priv = netdev_priv(dev);
ff9c852f
SM		 3779 struct mlx5e_channels *chs = &priv->channels;
3780
80378384
CO		 3781 int i;
3782
ff9c852f
SM		 3783 for (i = 0; i < chs->num; i++)
3784 napi_schedule(&chs->c[i]->napi);
80378384
CO		 3785}
3786#endif
3787
e80541ec 3788static const struct net_device_ops mlx5e_netdev_ops = {
f62b8bb8
AV		 3789 .ndo_open = mlx5e_open,
3790 .ndo_stop = mlx5e_close,
3791 .ndo_start_xmit = mlx5e_xmit,
0cf0f6d3 3792 .ndo_setup_tc = mlx5e_setup_tc,
08fb1dac 3793 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3794 .ndo_get_stats64 = mlx5e_get_stats,
3795 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3796 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3797 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3798 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3799 .ndo_set_features = mlx5e_set_features,
7d92d580 3800 .ndo_fix_features = mlx5e_fix_features,
b0eed40e
SM		 3801 .ndo_change_mtu = mlx5e_change_mtu,
3802 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3803 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
706b3583
SM		 3804 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3805 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3806 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3807#ifdef CONFIG_RFS_ACCEL
3808 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3809#endif
3947ca18 3810 .ndo_tx_timeout = mlx5e_tx_timeout,
f4e63525 3811 .ndo_bpf = mlx5e_xdp,
80378384
CO		 3812#ifdef CONFIG_NET_POLL_CONTROLLER
3813 .ndo_poll_controller = mlx5e_netpoll,
3814#endif
e80541ec 3815#ifdef CONFIG_MLX5_ESWITCH
706b3583 3816 /* SRIOV E-Switch NDOs */
b0eed40e
SM		 3817 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3818 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3819 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3820 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3821 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3822 .ndo_get_vf_config = mlx5e_get_vf_config,
3823 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3824 .ndo_get_vf_stats = mlx5e_get_vf_stats,
370bad0f
OG		 3825 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3826 .ndo_get_offload_stats = mlx5e_get_offload_stats,
e80541ec 3827#endif
f62b8bb8
AV		 3828};
3829
3830static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3831{
3832 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 3833 return -EOPNOTSUPP;
f62b8bb8
AV		 3834 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3835 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3836 !MLX5_CAP_ETH(mdev, csum_cap) ||
3837 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3838 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3839 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3840 MLX5_CAP_FLOWTABLE(mdev,
3841 flow_table_properties_nic_receive.max_ft_level)
3842 < 3) {
f62b8bb8
AV		 3843 mlx5_core_warn(mdev,
3844 "Not creating net device, some required device capabilities are missing\n");
9eb78923 3845 return -EOPNOTSUPP;
f62b8bb8 3846 }
66189961
TT		 3847 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3848 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8 3849 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3e432ab6 3850 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
66189961 3851
f62b8bb8
AV		 3852 return 0;
3853}
3854
58d52291
AS		 3855u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3856{
3857 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3858
3859 return bf_buf_size -
3860 sizeof(struct mlx5e_tx_wqe) +
3861 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3862}
3863
d4b6c488 3864void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
85082dba
TT		 3865 int num_channels)
3866{
3867 int i;
3868
3869 for (i = 0; i < len; i++)
3870 indirection_rqt[i] = i % num_channels;
3871}
3872
b797a684
SM		 3873static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3874{
3875 enum pcie_link_width width;
3876 enum pci_bus_speed speed;
3877 int err = 0;
3878
3879 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3880 if (err)
3881 return err;
3882
3883 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3884 return -EINVAL;
3885
3886 switch (speed) {
3887 case PCIE_SPEED_2_5GT:
3888 *pci_bw = 2500 * width;
3889 break;
3890 case PCIE_SPEED_5_0GT:
3891 *pci_bw = 5000 * width;
3892 break;
3893 case PCIE_SPEED_8_0GT:
3894 *pci_bw = 8000 * width;
3895 break;
3896 default:
3897 return -EINVAL;
3898 }
3899
3900 return 0;
3901}
3902
3903static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3904{
3905 return (link_speed && pci_bw &&
3906 (pci_bw < 40000) && (pci_bw < link_speed));
3907}
3908
0f6e4cf6
EBE		 3909static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
3910{
3911 return !(link_speed && pci_bw &&
3912 (pci_bw <= 16000) && (pci_bw < link_speed));
3913}
3914
0088cbbc
TG		 3915void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3916{
3917 params->tx_cq_moderation.cq_period_mode = cq_period_mode;
3918
3919 params->tx_cq_moderation.pkts =
3920 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3921 params->tx_cq_moderation.usec =
3922 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3923
3924 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3925 params->tx_cq_moderation.usec =
3926 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
3927
3928 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
3929 params->tx_cq_moderation.cq_period_mode ==
3930 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3931}
3932
9908aa29
TT		 3933void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3934{
0088cbbc 3935 params->rx_cq_moderation.cq_period_mode = cq_period_mode;
9908aa29
TT		 3936
3937 params->rx_cq_moderation.pkts =
3938 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3939 params->rx_cq_moderation.usec =
0088cbbc 3940 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
9908aa29
TT		 3941
3942 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3943 params->rx_cq_moderation.usec =
3944 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
6a9764ef 3945
9a317425
AG		 3946 if (params->rx_dim_enabled) {
3947 switch (cq_period_mode) {
3948 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
3949 params->rx_cq_moderation =
3950 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE);
3951 break;
3952 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
3953 default:
3954 params->rx_cq_moderation =
3955 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE);
3956 }
3957 }
457fcd8a 3958
6a9764ef 3959 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
0088cbbc
TG		 3960 params->rx_cq_moderation.cq_period_mode ==
3961 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29
TT		 3962}
3963
2b029556
SM		 3964u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3965{
3966 int i;
3967
3968 /* The supported periods are organized in ascending order */
3969 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3970 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3971 break;
3972
3973 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3974}
3975
8f493ffd
SM		 3976void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3977 struct mlx5e_params *params,
3978 u16 max_channels)
f62b8bb8 3979{
6a9764ef 3980 u8 cq_period_mode = 0;
b797a684
SM		 3981 u32 link_speed = 0;
3982 u32 pci_bw = 0;
2fc4bfb7 3983
6a9764ef
SM		 3984 params->num_channels = max_channels;
3985 params->num_tc = 1;
2b029556 3986
0f6e4cf6
EBE		 3987 mlx5e_get_max_linkspeed(mdev, &link_speed);
3988 mlx5e_get_pci_bw(mdev, &pci_bw);
3989 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3990 link_speed, pci_bw);
3991
6a9764ef
SM		 3992 /* SQ */
3993 params->log_sq_size = is_kdump_kernel() ?
b4e029da
KH		 3994 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3995 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3996
b797a684 3997 /* set CQE compression */
6a9764ef 3998 params->rx_cqe_compress_def = false;
b797a684 3999 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
e53eef63 4000 MLX5_CAP_GEN(mdev, vport_group_manager))
6a9764ef 4001 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
0f6e4cf6 4002
6a9764ef
SM		 4003 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4004
4005 /* RQ */
4006 mlx5e_set_rq_params(mdev, params);
b797a684 4007
6a9764ef 4008 /* HW LRO */
c139dbfd 4009
5426a0b2 4010 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
6a9764ef 4011 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
0f6e4cf6 4012 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
6a9764ef 4013 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
b0d4660b 4014
6a9764ef
SM		 4015 /* CQ moderation params */
4016 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4017 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4018 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
9a317425 4019 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
6a9764ef 4020 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
0088cbbc 4021 mlx5e_set_tx_cq_mode_params(params, cq_period_mode);
9908aa29 4022
6a9764ef
SM		 4023 /* TX inline */
4024 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
fbcb127e 4025 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
a6f402e4 4026
6a9764ef
SM		 4027 /* RSS */
4028 params->rss_hfunc = ETH_RSS_HASH_XOR;
4029 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
d4b6c488 4030 mlx5e_build_default_indir_rqt(params->indirection_rqt,
6a9764ef
SM		 4031 MLX5E_INDIR_RQT_SIZE, max_channels);
4032}
f62b8bb8 4033
6a9764ef
SM		 4034static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4035 struct net_device *netdev,
4036 const struct mlx5e_profile *profile,
4037 void *ppriv)
4038{
4039 struct mlx5e_priv *priv = netdev_priv(netdev);
57afead5 4040
6a9764ef
SM		 4041 priv->mdev = mdev;
4042 priv->netdev = netdev;
4043 priv->profile = profile;
4044 priv->ppriv = ppriv;
79c48764 4045 priv->msglevel = MLX5E_MSG_LEVEL;
c139dbfd 4046 priv->hard_mtu = MLX5E_ETH_HARD_MTU;
2d75b2bc 4047
6a9764ef 4048 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
9908aa29 4049
f62b8bb8
AV		 4050 mutex_init(&priv->state_lock);
4051
4052 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4053 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 4054 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8 4055 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
237f258c
FD		 4056
4057 mlx5e_timestamp_init(priv);
f62b8bb8
AV		 4058}
4059
4060static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4061{
4062 struct mlx5e_priv *priv = netdev_priv(netdev);
4063
e1d7d349 4064 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 4065 if (is_zero_ether_addr(netdev->dev_addr) &&
4066 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4067 eth_hw_addr_random(netdev);
4068 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4069 }
f62b8bb8
AV		 4070}
4071
f125376b 4072#if IS_ENABLED(CONFIG_MLX5_ESWITCH)
cb67b832
HHZ		 4073static const struct switchdev_ops mlx5e_switchdev_ops = {
4074 .switchdev_port_attr_get = mlx5e_attr_get,
4075};
e80541ec 4076#endif
cb67b832 4077
6bfd390b 4078static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 4079{
4080 struct mlx5e_priv *priv = netdev_priv(netdev);
4081 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 4082 bool fcs_supported;
4083 bool fcs_enabled;
f62b8bb8
AV		 4084
4085 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4086
e80541ec
SM		 4087 netdev->netdev_ops = &mlx5e_netdev_ops;
4088
08fb1dac 4089#ifdef CONFIG_MLX5_CORE_EN_DCB
e80541ec
SM		 4090 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4091 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac 4092#endif
66e49ded 4093
f62b8bb8
AV		 4094 netdev->watchdog_timeo = 15 * HZ;
4095
4096 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4097
12be4b21 4098 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 4099 netdev->vlan_features |= NETIF_F_IP_CSUM;
4100 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4101 netdev->vlan_features |= NETIF_F_GRO;
4102 netdev->vlan_features |= NETIF_F_TSO;
4103 netdev->vlan_features |= NETIF_F_TSO6;
4104 netdev->vlan_features |= NETIF_F_RXCSUM;
4105 netdev->vlan_features |= NETIF_F_RXHASH;
4106
4107 if (!!MLX5_CAP_ETH(mdev, lro_cap))
4108 netdev->vlan_features |= NETIF_F_LRO;
4109
4110 netdev->hw_features = netdev->vlan_features;
e4cf27bd 4111 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 4112 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4113 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4382c7b9 4114 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
f62b8bb8 4115
27299841
GP		 4116 if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4117 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
b3f63c3d 4118 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 4119 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 4120 netdev->hw_enc_features |= NETIF_F_TSO;
4121 netdev->hw_enc_features |= NETIF_F_TSO6;
27299841
GP		 4122 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4123 }
4124
4125 if (mlx5e_vxlan_allowed(mdev)) {
4126 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4127 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4128 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4129 NETIF_F_GSO_UDP_TUNNEL_CSUM;
b49663c8 4130 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 4131 }
4132
27299841
GP		 4133 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4134 netdev->hw_features |= NETIF_F_GSO_GRE |
4135 NETIF_F_GSO_GRE_CSUM;
4136 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4137 NETIF_F_GSO_GRE_CSUM;
4138 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4139 NETIF_F_GSO_GRE_CSUM;
4140 }
4141
94cb1ebb
EBE		 4142 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4143
4144 if (fcs_supported)
4145 netdev->hw_features |= NETIF_F_RXALL;
4146
102722fc
GE		 4147 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4148 netdev->hw_features |= NETIF_F_RXFCS;
4149
f62b8bb8 4150 netdev->features = netdev->hw_features;
6a9764ef 4151 if (!priv->channels.params.lro_en)
f62b8bb8
AV		 4152 netdev->features &= ~NETIF_F_LRO;
4153
94cb1ebb
EBE		 4154 if (fcs_enabled)
4155 netdev->features &= ~NETIF_F_RXALL;
4156
102722fc
GE		 4157 if (!priv->channels.params.scatter_fcs_en)
4158 netdev->features &= ~NETIF_F_RXFCS;
4159
e8f887ac
AV		 4160#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4161 if (FT_CAP(flow_modify_en) &&
4162 FT_CAP(modify_root) &&
4163 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 4164 FT_CAP(flow_table_modify)) {
4165 netdev->hw_features |= NETIF_F_HW_TC;
4166#ifdef CONFIG_RFS_ACCEL
4167 netdev->hw_features |= NETIF_F_NTUPLE;
4168#endif
4169 }
e8f887ac 4170
f62b8bb8 4171 netdev->features |= NETIF_F_HIGHDMA;
7d92d580 4172 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
f62b8bb8
AV		 4173
4174 netdev->priv_flags |= IFF_UNICAST_FLT;
4175
4176 mlx5e_set_netdev_dev_addr(netdev);
cb67b832 4177
f125376b 4178#if IS_ENABLED(CONFIG_MLX5_ESWITCH)
a9f7705f 4179 if (MLX5_VPORT_MANAGER(mdev))
cb67b832
HHZ		 4180 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4181#endif
547eede0
IT		 4182
4183 mlx5e_ipsec_build_netdev(priv);
f62b8bb8
AV		 4184}
4185
593cf338
RS		 4186static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4187{
4188 struct mlx5_core_dev *mdev = priv->mdev;
4189 int err;
4190
4191 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4192 if (err) {
4193 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4194 priv->q_counter = 0;
4195 }
4196}
4197
4198static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4199{
4200 if (!priv->q_counter)
4201 return;
4202
4203 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4204}
4205
6bfd390b
HHZ		 4206static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4207 struct net_device *netdev,
127ea380
HHZ		 4208 const struct mlx5e_profile *profile,
4209 void *ppriv)
6bfd390b
HHZ		 4210{
4211 struct mlx5e_priv *priv = netdev_priv(netdev);
547eede0 4212 int err;
6bfd390b 4213
127ea380 4214 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
547eede0
IT		 4215 err = mlx5e_ipsec_init(priv);
4216 if (err)
4217 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
6bfd390b
HHZ		 4218 mlx5e_build_nic_netdev(netdev);
4219 mlx5e_vxlan_init(priv);
4220}
4221
4222static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4223{
547eede0 4224 mlx5e_ipsec_cleanup(priv);
6bfd390b
HHZ		 4225 mlx5e_vxlan_cleanup(priv);
4226}
4227
4228static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4229{
4230 struct mlx5_core_dev *mdev = priv->mdev;
4231 int err;
6bfd390b 4232
8f493ffd
SM		 4233 err = mlx5e_create_indirect_rqt(priv);
4234 if (err)
6bfd390b 4235 return err;
6bfd390b
HHZ		 4236
4237 err = mlx5e_create_direct_rqts(priv);
8f493ffd 4238 if (err)
6bfd390b 4239 goto err_destroy_indirect_rqts;
6bfd390b
HHZ		 4240
4241 err = mlx5e_create_indirect_tirs(priv);
8f493ffd 4242 if (err)
6bfd390b 4243 goto err_destroy_direct_rqts;
6bfd390b
HHZ		 4244
4245 err = mlx5e_create_direct_tirs(priv);
8f493ffd 4246 if (err)
6bfd390b 4247 goto err_destroy_indirect_tirs;
6bfd390b
HHZ		 4248
4249 err = mlx5e_create_flow_steering(priv);
4250 if (err) {
4251 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4252 goto err_destroy_direct_tirs;
4253 }
4254
4255 err = mlx5e_tc_init(priv);
4256 if (err)
4257 goto err_destroy_flow_steering;
4258
4259 return 0;
4260
4261err_destroy_flow_steering:
4262 mlx5e_destroy_flow_steering(priv);
4263err_destroy_direct_tirs:
4264 mlx5e_destroy_direct_tirs(priv);
4265err_destroy_indirect_tirs:
4266 mlx5e_destroy_indirect_tirs(priv);
4267err_destroy_direct_rqts:
8f493ffd 4268 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4269err_destroy_indirect_rqts:
4270 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4271 return err;
4272}
4273
4274static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4275{
6bfd390b
HHZ		 4276 mlx5e_tc_cleanup(priv);
4277 mlx5e_destroy_flow_steering(priv);
4278 mlx5e_destroy_direct_tirs(priv);
4279 mlx5e_destroy_indirect_tirs(priv);
8f493ffd 4280 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4281 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4282}
4283
4284static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4285{
4286 int err;
4287
4288 err = mlx5e_create_tises(priv);
4289 if (err) {
4290 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4291 return err;
4292 }
4293
4294#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 4295 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 4296#endif
4297 return 0;
4298}
4299
4300static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4301{
4302 struct net_device *netdev = priv->netdev;
4303 struct mlx5_core_dev *mdev = priv->mdev;
2c3b5bee
SM		 4304 u16 max_mtu;
4305
4306 mlx5e_init_l2_addr(priv);
4307
63bfd399
EBE		 4308 /* Marking the link as currently not needed by the Driver */
4309 if (!netif_running(netdev))
4310 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4311
2c3b5bee
SM		 4312 /* MTU range: 68 - hw-specific max */
4313 netdev->min_mtu = ETH_MIN_MTU;
4314 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
c139dbfd 4315 netdev->max_mtu = MLX5E_HW2SW_MTU(priv, max_mtu);
2c3b5bee 4316 mlx5e_set_dev_port_mtu(priv);
6bfd390b 4317
7907f23a
AH		 4318 mlx5_lag_add(mdev, netdev);
4319
6bfd390b 4320 mlx5e_enable_async_events(priv);
127ea380 4321
a9f7705f 4322 if (MLX5_VPORT_MANAGER(priv->mdev))
1d447a39 4323 mlx5e_register_vport_reps(priv);
2c3b5bee 4324
610e89e0
SM		 4325 if (netdev->reg_state != NETREG_REGISTERED)
4326 return;
2a5e7a13
HN		 4327#ifdef CONFIG_MLX5_CORE_EN_DCB
4328 mlx5e_dcbnl_init_app(priv);
4329#endif
610e89e0
SM		 4330 /* Device already registered: sync netdev system state */
4331 if (mlx5e_vxlan_allowed(mdev)) {
4332 rtnl_lock();
4333 udp_tunnel_get_rx_info(netdev);
4334 rtnl_unlock();
4335 }
4336
4337 queue_work(priv->wq, &priv->set_rx_mode_work);
2c3b5bee
SM		 4338
4339 rtnl_lock();
4340 if (netif_running(netdev))
4341 mlx5e_open(netdev);
4342 netif_device_attach(netdev);
4343 rtnl_unlock();
6bfd390b
HHZ		 4344}
4345
4346static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4347{
3deef8ce 4348 struct mlx5_core_dev *mdev = priv->mdev;
3deef8ce 4349
2a5e7a13
HN		 4350#ifdef CONFIG_MLX5_CORE_EN_DCB
4351 if (priv->netdev->reg_state == NETREG_REGISTERED)
4352 mlx5e_dcbnl_delete_app(priv);
4353#endif
4354
2c3b5bee
SM		 4355 rtnl_lock();
4356 if (netif_running(priv->netdev))
4357 mlx5e_close(priv->netdev);
4358 netif_device_detach(priv->netdev);
4359 rtnl_unlock();
4360
6bfd390b 4361 queue_work(priv->wq, &priv->set_rx_mode_work);
1d447a39 4362
a9f7705f 4363 if (MLX5_VPORT_MANAGER(priv->mdev))
1d447a39
SM		 4364 mlx5e_unregister_vport_reps(priv);
4365
6bfd390b 4366 mlx5e_disable_async_events(priv);
3deef8ce 4367 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 4368}
4369
4370static const struct mlx5e_profile mlx5e_nic_profile = {
4371 .init = mlx5e_nic_init,
4372 .cleanup = mlx5e_nic_cleanup,
4373 .init_rx = mlx5e_init_nic_rx,
4374 .cleanup_rx = mlx5e_cleanup_nic_rx,
4375 .init_tx = mlx5e_init_nic_tx,
4376 .cleanup_tx = mlx5e_cleanup_nic_tx,
4377 .enable = mlx5e_nic_enable,
4378 .disable = mlx5e_nic_disable,
3834a5e6 4379 .update_stats = mlx5e_update_ndo_stats,
6bfd390b 4380 .max_nch = mlx5e_get_max_num_channels,
7ca42c80 4381 .update_carrier = mlx5e_update_carrier,
20fd0c19
SM		 4382 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4383 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
6bfd390b
HHZ		 4384 .max_tc = MLX5E_MAX_NUM_TC,
4385};
4386
2c3b5bee
SM		 4387/* mlx5e generic netdev management API (move to en_common.c) */
4388
26e59d80
MHY		 4389struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4390 const struct mlx5e_profile *profile,
4391 void *ppriv)
f62b8bb8 4392{
26e59d80 4393 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 4394 struct net_device *netdev;
4395 struct mlx5e_priv *priv;
f62b8bb8 4396
08fb1dac 4397 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 4398 nch * profile->max_tc,
08fb1dac 4399 nch);
f62b8bb8
AV		 4400 if (!netdev) {
4401 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4402 return NULL;
4403 }
4404
be4891af
SM		 4405#ifdef CONFIG_RFS_ACCEL
4406 netdev->rx_cpu_rmap = mdev->rmap;
4407#endif
4408
127ea380 4409 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 4410
4411 netif_carrier_off(netdev);
4412
4413 priv = netdev_priv(netdev);
4414
7bb29755
MF		 4415 priv->wq = create_singlethread_workqueue("mlx5e");
4416 if (!priv->wq)
26e59d80
MHY		 4417 goto err_cleanup_nic;
4418
4419 return netdev;
4420
4421err_cleanup_nic:
31ac9338
OG		 4422 if (profile->cleanup)
4423 profile->cleanup(priv);
26e59d80
MHY		 4424 free_netdev(netdev);
4425
4426 return NULL;
4427}
4428
2c3b5bee 4429int mlx5e_attach_netdev(struct mlx5e_priv *priv)
26e59d80 4430{
2c3b5bee 4431 struct mlx5_core_dev *mdev = priv->mdev;
26e59d80 4432 const struct mlx5e_profile *profile;
26e59d80
MHY		 4433 int err;
4434
26e59d80
MHY		 4435 profile = priv->profile;
4436 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 4437
6bfd390b
HHZ		 4438 err = profile->init_tx(priv);
4439 if (err)
ec8b9981 4440 goto out;
5c50368f 4441
a43b25da 4442 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
5c50368f
AS		 4443 if (err) {
4444 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 4445 goto err_cleanup_tx;
5c50368f
AS		 4446 }
4447
6bfd390b
HHZ		 4448 err = profile->init_rx(priv);
4449 if (err)
5c50368f 4450 goto err_close_drop_rq;
5c50368f 4451
593cf338
RS		 4452 mlx5e_create_q_counter(priv);
4453
6bfd390b
HHZ		 4454 if (profile->enable)
4455 profile->enable(priv);
f62b8bb8 4456
26e59d80 4457 return 0;
5c50368f
AS		 4458
4459err_close_drop_rq:
a43b25da 4460 mlx5e_close_drop_rq(&priv->drop_rq);
5c50368f 4461
6bfd390b
HHZ		 4462err_cleanup_tx:
4463 profile->cleanup_tx(priv);
5c50368f 4464
26e59d80
MHY		 4465out:
4466 return err;
f62b8bb8
AV		 4467}
4468
2c3b5bee 4469void mlx5e_detach_netdev(struct mlx5e_priv *priv)
26e59d80 4470{
26e59d80
MHY		 4471 const struct mlx5e_profile *profile = priv->profile;
4472
4473 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80 4474
37f304d1
SM		 4475 if (profile->disable)
4476 profile->disable(priv);
4477 flush_workqueue(priv->wq);
4478
26e59d80
MHY		 4479 mlx5e_destroy_q_counter(priv);
4480 profile->cleanup_rx(priv);
a43b25da 4481 mlx5e_close_drop_rq(&priv->drop_rq);
26e59d80 4482 profile->cleanup_tx(priv);
26e59d80
MHY		 4483 cancel_delayed_work_sync(&priv->update_stats_work);
4484}
4485
2c3b5bee
SM		 4486void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4487{
4488 const struct mlx5e_profile *profile = priv->profile;
4489 struct net_device *netdev = priv->netdev;
4490
4491 destroy_workqueue(priv->wq);
4492 if (profile->cleanup)
4493 profile->cleanup(priv);
4494 free_netdev(netdev);
4495}
4496
26e59d80
MHY		 4497/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4498 * hardware contexts and to connect it to the current netdev.
4499 */
4500static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4501{
4502 struct mlx5e_priv *priv = vpriv;
4503 struct net_device *netdev = priv->netdev;
4504 int err;
4505
4506 if (netif_device_present(netdev))
4507 return 0;
4508
4509 err = mlx5e_create_mdev_resources(mdev);
4510 if (err)
4511 return err;
4512
2c3b5bee 4513 err = mlx5e_attach_netdev(priv);
26e59d80
MHY		 4514 if (err) {
4515 mlx5e_destroy_mdev_resources(mdev);
4516 return err;
4517 }
4518
4519 return 0;
4520}
4521
4522static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4523{
4524 struct mlx5e_priv *priv = vpriv;
4525 struct net_device *netdev = priv->netdev;
4526
4527 if (!netif_device_present(netdev))
4528 return;
4529
2c3b5bee 4530 mlx5e_detach_netdev(priv);
26e59d80
MHY		 4531 mlx5e_destroy_mdev_resources(mdev);
4532}
4533
b50d292b
HHZ		 4534static void *mlx5e_add(struct mlx5_core_dev *mdev)
4535{
07c9f1e5
SM		 4536 struct net_device *netdev;
4537 void *rpriv = NULL;
26e59d80 4538 void *priv;
26e59d80 4539 int err;
b50d292b 4540
26e59d80
MHY		 4541 err = mlx5e_check_required_hca_cap(mdev);
4542 if (err)
b50d292b
HHZ		 4543 return NULL;
4544
e80541ec 4545#ifdef CONFIG_MLX5_ESWITCH
a9f7705f 4546 if (MLX5_VPORT_MANAGER(mdev)) {
07c9f1e5 4547 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
1d447a39 4548 if (!rpriv) {
07c9f1e5 4549 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
1d447a39
SM		 4550 return NULL;
4551 }
1d447a39 4552 }
e80541ec 4553#endif
127ea380 4554
1d447a39 4555 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
26e59d80
MHY		 4556 if (!netdev) {
4557 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
07c9f1e5 4558 goto err_free_rpriv;
26e59d80
MHY		 4559 }
4560
4561 priv = netdev_priv(netdev);
4562
4563 err = mlx5e_attach(mdev, priv);
4564 if (err) {
4565 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4566 goto err_destroy_netdev;
4567 }
4568
4569 err = register_netdev(netdev);
4570 if (err) {
4571 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4572 goto err_detach;
b50d292b 4573 }
26e59d80 4574
2a5e7a13
HN		 4575#ifdef CONFIG_MLX5_CORE_EN_DCB
4576 mlx5e_dcbnl_init_app(priv);
4577#endif
26e59d80
MHY		 4578 return priv;
4579
4580err_detach:
4581 mlx5e_detach(mdev, priv);
26e59d80 4582err_destroy_netdev:
2c3b5bee 4583 mlx5e_destroy_netdev(priv);
07c9f1e5 4584err_free_rpriv:
1d447a39 4585 kfree(rpriv);
26e59d80 4586 return NULL;
b50d292b
HHZ		 4587}
4588
b50d292b
HHZ		 4589static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4590{
4591 struct mlx5e_priv *priv = vpriv;
1d447a39 4592 void *ppriv = priv->ppriv;
127ea380 4593
2a5e7a13
HN		 4594#ifdef CONFIG_MLX5_CORE_EN_DCB
4595 mlx5e_dcbnl_delete_app(priv);
4596#endif
5e1e93c7 4597 unregister_netdev(priv->netdev);
26e59d80 4598 mlx5e_detach(mdev, vpriv);
2c3b5bee 4599 mlx5e_destroy_netdev(priv);
1d447a39 4600 kfree(ppriv);
b50d292b
HHZ		 4601}
4602
f62b8bb8
AV		 4603static void *mlx5e_get_netdev(void *vpriv)
4604{
4605 struct mlx5e_priv *priv = vpriv;
4606
4607 return priv->netdev;
4608}
4609
4610static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4611 .add = mlx5e_add,
4612 .remove = mlx5e_remove,
26e59d80
MHY		 4613 .attach = mlx5e_attach,
4614 .detach = mlx5e_detach,
f62b8bb8
AV		 4615 .event = mlx5e_async_event,
4616 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4617 .get_dev = mlx5e_get_netdev,
4618};
4619
4620void mlx5e_init(void)
4621{
2ac9cfe7 4622 mlx5e_ipsec_build_inverse_table();
665bc539 4623 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4624 mlx5_register_interface(&mlx5e_interface);
4625}
4626
4627void mlx5e_cleanup(void)
4628{
4629 mlx5_unregister_interface(&mlx5e_interface);
4630}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git