]> git.ipfire.org Git - thirdparty/kernel/stable.git/blame - drivers/net/ethernet/mellanox/mlx5/core/en_main.c
projects / thirdparty / kernel / stable.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net_sch: red: Add offload ability to RED qdisc
[thirdparty/kernel/stable.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
1d447a39 38#include "eswitch.h"
f62b8bb8 39#include "en.h"
e8f887ac 40#include "en_tc.h"
1d447a39 41#include "en_rep.h"
547eede0 42#include "en_accel/ipsec.h"
899a59d3
IT		 43#include "en_accel/ipsec_rxtx.h"
44#include "accel/ipsec.h"
b3f63c3d 45#include "vxlan.h"
f62b8bb8
AV		 46
47struct mlx5e_rq_param {
cb3c7fd4
GR		 48 u32 rqc[MLX5_ST_SZ_DW(rqc)];
49 struct mlx5_wq_param wq;
f62b8bb8
AV		 50};
51
52struct mlx5e_sq_param {
53 u32 sqc[MLX5_ST_SZ_DW(sqc)];
54 struct mlx5_wq_param wq;
55};
56
57struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
9908aa29 61 u8 cq_period_mode;
f62b8bb8
AV		 62};
63
64struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
b5503b99 67 struct mlx5e_sq_param xdp_sq;
d3c9bc27 68 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
d3c9bc27 71 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 72};
73
a435393a
SG		 74static int mlx5e_get_node(struct mlx5e_priv *priv, int ix)
75{
76 return pci_irq_get_node(priv->mdev->pdev, MLX5_EQ_VEC_COMP_BASE + ix);
77}
78
2fc4bfb7
SM		 79static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
80{
81 return MLX5_CAP_GEN(mdev, striding_rq) &&
82 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
83 MLX5_CAP_ETH(mdev, reg_umr_sq);
84}
85
6a9764ef
SM		 86void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
87 struct mlx5e_params *params, u8 rq_type)
2fc4bfb7 88{
6a9764ef
SM		 89 params->rq_wq_type = rq_type;
90 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
91 switch (params->rq_wq_type) {
2fc4bfb7 92 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 93 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 94 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
95 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
6a9764ef
SM		 96 params->mpwqe_log_stride_sz =
97 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
98 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
99 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
100 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
101 params->mpwqe_log_stride_sz;
2fc4bfb7
SM		 102 break;
103 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 104 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 105 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
106 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
bce2b2bf
TT		 107 params->rq_headroom = params->xdp_prog ?
108 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
109 params->rq_headroom += NET_IP_ALIGN;
4078e637
TT		 110
111 /* Extra room needed for build_skb */
bce2b2bf 112 params->lro_wqe_sz -= params->rq_headroom +
4078e637 113 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2fc4bfb7 114 }
2fc4bfb7 115
6a9764ef
SM		 116 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
117 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
118 BIT(params->log_rq_size),
119 BIT(params->mpwqe_log_stride_sz),
120 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 121}
122
6a9764ef 123static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
2fc4bfb7 124{
6a9764ef 125 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
899a59d3 126 !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
2fc4bfb7
SM		 127 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
128 MLX5_WQ_TYPE_LINKED_LIST;
6a9764ef 129 mlx5e_set_rq_type_params(mdev, params, rq_type);
2fc4bfb7
SM		 130}
131
f62b8bb8
AV		 132static void mlx5e_update_carrier(struct mlx5e_priv *priv)
133{
134 struct mlx5_core_dev *mdev = priv->mdev;
135 u8 port_state;
136
137 port_state = mlx5_query_vport_state(mdev,
e53eef63
OG		 138 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
139 0);
f62b8bb8 140
87424ad5
SD		 141 if (port_state == VPORT_STATE_UP) {
142 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 143 netif_carrier_on(priv->netdev);
87424ad5
SD		 144 } else {
145 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 146 netif_carrier_off(priv->netdev);
87424ad5 147 }
f62b8bb8
AV		 148}
149
150static void mlx5e_update_carrier_work(struct work_struct *work)
151{
152 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
153 update_carrier_work);
154
155 mutex_lock(&priv->state_lock);
156 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
7ca42c80
ES		 157 if (priv->profile->update_carrier)
158 priv->profile->update_carrier(priv);
f62b8bb8
AV		 159 mutex_unlock(&priv->state_lock);
160}
161
3947ca18
DJ		 162static void mlx5e_tx_timeout_work(struct work_struct *work)
163{
164 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
165 tx_timeout_work);
166 int err;
167
168 rtnl_lock();
169 mutex_lock(&priv->state_lock);
170 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
171 goto unlock;
172 mlx5e_close_locked(priv->netdev);
173 err = mlx5e_open_locked(priv->netdev);
174 if (err)
175 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
176 err);
177unlock:
178 mutex_unlock(&priv->state_lock);
179 rtnl_unlock();
180}
181
9218b44d 182static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 183{
1510d728 184 struct mlx5e_sw_stats temp, *s = &temp;
f62b8bb8
AV		 185 struct mlx5e_rq_stats *rq_stats;
186 struct mlx5e_sq_stats *sq_stats;
f62b8bb8
AV		 187 int i, j;
188
9218b44d 189 memset(s, 0, sizeof(*s));
ff9c852f
SM		 190 for (i = 0; i < priv->channels.num; i++) {
191 struct mlx5e_channel *c = priv->channels.c[i];
192
193 rq_stats = &c->rq.stats;
f62b8bb8 194
faf4478b
GP		 195 s->rx_packets += rq_stats->packets;
196 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 197 s->rx_lro_packets += rq_stats->lro_packets;
198 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 199 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1 200 s->rx_csum_complete += rq_stats->csum_complete;
603e1f5b 201 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
bfe6d8d1 202 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 203 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 204 s->rx_xdp_tx += rq_stats->xdp_tx;
205 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 206 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 207 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 208 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 209 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
210 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
accd5883 211 s->rx_page_reuse += rq_stats->page_reuse;
4415a031
TT		 212 s->rx_cache_reuse += rq_stats->cache_reuse;
213 s->rx_cache_full += rq_stats->cache_full;
214 s->rx_cache_empty += rq_stats->cache_empty;
215 s->rx_cache_busy += rq_stats->cache_busy;
70871f1e 216 s->rx_cache_waive += rq_stats->cache_waive;
f62b8bb8 217
6a9764ef 218 for (j = 0; j < priv->channels.params.num_tc; j++) {
ff9c852f 219 sq_stats = &c->sq[j].stats;
f62b8bb8 220
faf4478b
GP		 221 s->tx_packets += sq_stats->packets;
222 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 223 s->tx_tso_packets += sq_stats->tso_packets;
224 s->tx_tso_bytes += sq_stats->tso_bytes;
225 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
226 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 227 s->tx_queue_stopped += sq_stats->stopped;
228 s->tx_queue_wake += sq_stats->wake;
229 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 230 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1 231 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
603e1f5b
GP		 232 s->tx_csum_none += sq_stats->csum_none;
233 s->tx_csum_partial += sq_stats->csum_partial;
f62b8bb8
AV		 234 }
235 }
236
bfe6d8d1 237 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 238 priv->stats.pport.phy_counters,
239 counter_set.phys_layer_cntrs.link_down_events);
1510d728 240 memcpy(&priv->stats.sw, s, sizeof(*s));
9218b44d
GP		 241}
242
243static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
244{
245 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
246 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 247 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 248 struct mlx5_core_dev *mdev = priv->mdev;
249
f62b8bb8
AV		 250 MLX5_SET(query_vport_counter_in, in, opcode,
251 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
252 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
253 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
254
9218b44d
GP		 255 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
256}
257
3834a5e6 258static void mlx5e_update_pport_counters(struct mlx5e_priv *priv, bool full)
9218b44d
GP		 259{
260 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
261 struct mlx5_core_dev *mdev = priv->mdev;
0883b4f4 262 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
9218b44d 263 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 264 int prio;
9218b44d 265 void *out;
f62b8bb8 266
9218b44d 267 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 268
9218b44d
GP		 269 out = pstats->IEEE_802_3_counters;
270 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
271 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 272
3834a5e6
GP		 273 if (!full)
274 return;
275
9218b44d
GP		 276 out = pstats->RFC_2863_counters;
277 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
278 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
279
280 out = pstats->RFC_2819_counters;
281 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
282 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 283
121fcdc8
GP		 284 out = pstats->phy_counters;
285 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
286 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
287
5db0a4f6
GP		 288 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
289 out = pstats->phy_statistical_counters;
290 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
291 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
292 }
293
068aef33
GP		 294 if (MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters)) {
295 out = pstats->eth_ext_counters;
296 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
5db0a4f6
GP		 297 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
298 }
299
cf678570
GP		 300 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
301 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
302 out = pstats->per_prio_counters[prio];
303 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
304 mlx5_core_access_reg(mdev, in, sz, out, sz,
305 MLX5_REG_PPCNT, 0, 0);
306 }
9218b44d
GP		 307}
308
309static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
310{
311 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
432609a4
GP		 312 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
313 int err;
9218b44d
GP		 314
315 if (!priv->q_counter)
316 return;
317
432609a4
GP		 318 err = mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, sizeof(out));
319 if (err)
320 return;
321
322 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer);
9218b44d
GP		 323}
324
0f7f3481
GP		 325static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
326{
327 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
328 struct mlx5_core_dev *mdev = priv->mdev;
0883b4f4 329 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
0f7f3481
GP		 330 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
331 void *out;
0f7f3481
GP		 332
333 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
334 return;
335
0f7f3481
GP		 336 out = pcie_stats->pcie_perf_counters;
337 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
338 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
0f7f3481
GP		 339}
340
3834a5e6 341void mlx5e_update_stats(struct mlx5e_priv *priv, bool full)
9218b44d 342{
164f16f7 343 if (full) {
3834a5e6 344 mlx5e_update_pcie_counters(priv);
164f16f7
IT		 345 mlx5e_ipsec_update_stats(priv);
346 }
3834a5e6 347 mlx5e_update_pport_counters(priv, full);
3dd69e3d
SM		 348 mlx5e_update_vport_counters(priv);
349 mlx5e_update_q_counter(priv);
121fcdc8 350 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 351}
352
3834a5e6
GP		 353static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
354{
355 mlx5e_update_stats(priv, false);
356}
357
cb67b832 358void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 359{
360 struct delayed_work *dwork = to_delayed_work(work);
361 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
362 update_stats_work);
363 mutex_lock(&priv->state_lock);
364 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 365 priv->profile->update_stats(priv);
7bb29755
MF		 366 queue_delayed_work(priv->wq, dwork,
367 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 368 }
369 mutex_unlock(&priv->state_lock);
370}
371
daa21560
TT		 372static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
373 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 374{
daa21560
TT		 375 struct mlx5e_priv *priv = vpriv;
376
e0f46eb9 377 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 378 return;
379
f62b8bb8
AV		 380 switch (event) {
381 case MLX5_DEV_EVENT_PORT_UP:
382 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 383 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 384 break;
f62b8bb8
AV		 385 default:
386 break;
387 }
388}
389
f62b8bb8
AV		 390static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
391{
e0f46eb9 392 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 393}
394
395static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
396{
e0f46eb9 397 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
78249c42 398 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 399}
400
7e426671
TT		 401static inline int mlx5e_get_wqe_mtt_sz(void)
402{
403 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
404 * To avoid copying garbage after the mtt array, we allocate
405 * a little more.
406 */
407 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
408 MLX5_UMR_MTT_ALIGNMENT);
409}
410
31391048
SM		 411static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
412 struct mlx5e_icosq *sq,
413 struct mlx5e_umr_wqe *wqe,
414 u16 ix)
7e426671
TT		 415{
416 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
417 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
418 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 419 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 420 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
421 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
422
423 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
424 ds_cnt);
425 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
426 cseg->imm = rq->mkey_be;
427
428 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
31616255 429 ucseg->xlt_octowords =
7e426671
TT		 430 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
431 ucseg->bsf_octowords =
432 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
433 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
434
435 dseg->lkey = sq->mkey_be;
436 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
437}
438
439static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
440 struct mlx5e_channel *c)
441{
442 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
443 int mtt_sz = mlx5e_get_wqe_mtt_sz();
444 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
a435393a 445 int node = mlx5e_get_node(c->priv, c->ix);
7e426671
TT		 446 int i;
447
21c59685 448 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
a435393a 449 GFP_KERNEL, node);
21c59685 450 if (!rq->mpwqe.info)
7e426671
TT		 451 goto err_out;
452
453 /* We allocate more than mtt_sz as we will align the pointer */
a435393a
SG		 454 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz,
455 GFP_KERNEL, node);
21c59685 456 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 457 goto err_free_wqe_info;
458
459 for (i = 0; i < wq_sz; i++) {
21c59685 460 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 461
21c59685 462 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 463 MLX5_UMR_ALIGN);
464 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
465 PCI_DMA_TODEVICE);
466 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
467 goto err_unmap_mtts;
468
469 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
470 }
471
472 return 0;
473
474err_unmap_mtts:
475 while (--i >= 0) {
21c59685 476 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 477
478 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
479 PCI_DMA_TODEVICE);
480 }
21c59685 481 kfree(rq->mpwqe.mtt_no_align);
7e426671 482err_free_wqe_info:
21c59685 483 kfree(rq->mpwqe.info);
7e426671
TT		 484
485err_out:
486 return -ENOMEM;
487}
488
489static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
490{
491 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
492 int mtt_sz = mlx5e_get_wqe_mtt_sz();
493 int i;
494
495 for (i = 0; i < wq_sz; i++) {
21c59685 496 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 497
498 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
499 PCI_DMA_TODEVICE);
500 }
21c59685
SM		 501 kfree(rq->mpwqe.mtt_no_align);
502 kfree(rq->mpwqe.info);
7e426671
TT		 503}
504
a43b25da 505static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
ec8b9981
TT		 506 u64 npages, u8 page_shift,
507 struct mlx5_core_mkey *umr_mkey)
3608ae77 508{
3608ae77
TT		 509 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
510 void *mkc;
511 u32 *in;
512 int err;
513
ec8b9981
TT		 514 if (!MLX5E_VALID_NUM_MTTS(npages))
515 return -EINVAL;
516
1b9a07ee 517 in = kvzalloc(inlen, GFP_KERNEL);
3608ae77
TT		 518 if (!in)
519 return -ENOMEM;
520
521 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
522
3608ae77
TT		 523 MLX5_SET(mkc, mkc, free, 1);
524 MLX5_SET(mkc, mkc, umr_en, 1);
525 MLX5_SET(mkc, mkc, lw, 1);
526 MLX5_SET(mkc, mkc, lr, 1);
527 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
528
529 MLX5_SET(mkc, mkc, qpn, 0xffffff);
530 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 531 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 532 MLX5_SET(mkc, mkc, translations_octword_size,
533 MLX5_MTT_OCTW(npages));
ec8b9981 534 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 535
ec8b9981 536 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 537
538 kvfree(in);
539 return err;
540}
541
a43b25da 542static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
ec8b9981 543{
6a9764ef 544 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
ec8b9981 545
a43b25da 546 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
ec8b9981
TT		 547}
548
3b77235b 549static int mlx5e_alloc_rq(struct mlx5e_channel *c,
6a9764ef
SM		 550 struct mlx5e_params *params,
551 struct mlx5e_rq_param *rqp,
3b77235b 552 struct mlx5e_rq *rq)
f62b8bb8 553{
a43b25da 554 struct mlx5_core_dev *mdev = c->mdev;
6a9764ef 555 void *rqc = rqp->rqc;
f62b8bb8 556 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 557 u32 byte_count;
1bfecfca 558 int npages;
f62b8bb8
AV		 559 int wq_sz;
560 int err;
561 int i;
562
a435393a 563 rqp->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
311c7c71 564
6a9764ef 565 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
f62b8bb8
AV		 566 &rq->wq_ctrl);
567 if (err)
568 return err;
569
570 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
571
572 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 573
6a9764ef 574 rq->wq_type = params->rq_wq_type;
7e426671
TT		 575 rq->pdev = c->pdev;
576 rq->netdev = c->netdev;
a43b25da 577 rq->tstamp = c->tstamp;
7c39afb3 578 rq->clock = &mdev->clock;
7e426671
TT		 579 rq->channel = c;
580 rq->ix = c->ix;
a43b25da 581 rq->mdev = mdev;
97bc402d 582
6a9764ef 583 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
97bc402d
DB		 584 if (IS_ERR(rq->xdp_prog)) {
585 err = PTR_ERR(rq->xdp_prog);
586 rq->xdp_prog = NULL;
587 goto err_rq_wq_destroy;
588 }
7e426671 589
bce2b2bf 590 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
b45d8b50 591 rq->buff.headroom = params->rq_headroom;
b5503b99 592
6a9764ef 593 switch (rq->wq_type) {
461017cb 594 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476 595
7cc6d77b 596 rq->post_wqes = mlx5e_post_rx_mpwqes;
6cd392a0 597 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 598
20fd0c19 599 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
899a59d3
IT		 600#ifdef CONFIG_MLX5_EN_IPSEC
601 if (MLX5_IPSEC_DEV(mdev)) {
602 err = -EINVAL;
603 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
604 goto err_rq_wq_destroy;
605 }
606#endif
20fd0c19
SM		 607 if (!rq->handle_rx_cqe) {
608 err = -EINVAL;
609 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
610 goto err_rq_wq_destroy;
611 }
612
89e89f7a 613 rq->mpwqe.log_stride_sz = params->mpwqe_log_stride_sz;
b45d8b50 614 rq->mpwqe.num_strides = BIT(params->mpwqe_log_num_strides);
1bfecfca 615
b681c481 616 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
ec8b9981 617
a43b25da 618 err = mlx5e_create_rq_umr_mkey(mdev, rq);
7e426671
TT		 619 if (err)
620 goto err_rq_wq_destroy;
ec8b9981
TT		 621 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
622
623 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
624 if (err)
625 goto err_destroy_umr_mkey;
461017cb
TT		 626 break;
627 default: /* MLX5_WQ_TYPE_LINKED_LIST */
accd5883
TT		 628 rq->wqe.frag_info =
629 kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
a435393a
SG		 630 GFP_KERNEL,
631 mlx5e_get_node(c->priv, c->ix));
accd5883 632 if (!rq->wqe.frag_info) {
461017cb
TT		 633 err = -ENOMEM;
634 goto err_rq_wq_destroy;
635 }
7cc6d77b 636 rq->post_wqes = mlx5e_post_rx_wqes;
6cd392a0 637 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 638
899a59d3
IT		 639#ifdef CONFIG_MLX5_EN_IPSEC
640 if (c->priv->ipsec)
641 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
642 else
643#endif
644 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
20fd0c19 645 if (!rq->handle_rx_cqe) {
accd5883 646 kfree(rq->wqe.frag_info);
20fd0c19
SM		 647 err = -EINVAL;
648 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
649 goto err_rq_wq_destroy;
650 }
651
b681c481 652 byte_count = params->lro_en ?
6a9764ef 653 params->lro_wqe_sz :
c139dbfd 654 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
899a59d3
IT		 655#ifdef CONFIG_MLX5_EN_IPSEC
656 if (MLX5_IPSEC_DEV(mdev))
b681c481 657 byte_count += MLX5E_METADATA_ETHER_LEN;
899a59d3 658#endif
accd5883 659 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
1bfecfca
SM		 660
661 /* calc the required page order */
b45d8b50 662 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
accd5883 663 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
1bfecfca
SM		 664 rq->buff.page_order = order_base_2(npages);
665
461017cb 666 byte_count |= MLX5_HW_START_PADDING;
7e426671 667 rq->mkey_be = c->mkey_be;
461017cb 668 }
f62b8bb8
AV		 669
670 for (i = 0; i < wq_sz; i++) {
671 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
672
4c2af5cc
TT		 673 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
674 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT;
675
676 wqe->data.addr = cpu_to_be64(dma_offset);
677 }
678
461017cb 679 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 680 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 681 }
682
cb3c7fd4 683 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
0088cbbc 684 rq->am.mode = params->rx_cq_moderation.cq_period_mode;
4415a031
TT		 685 rq->page_cache.head = 0;
686 rq->page_cache.tail = 0;
687
f62b8bb8
AV		 688 return 0;
689
ec8b9981
TT		 690err_destroy_umr_mkey:
691 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
692
f62b8bb8 693err_rq_wq_destroy:
97bc402d
DB		 694 if (rq->xdp_prog)
695 bpf_prog_put(rq->xdp_prog);
f62b8bb8
AV		 696 mlx5_wq_destroy(&rq->wq_ctrl);
697
698 return err;
699}
700
3b77235b 701static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 702{
4415a031
TT		 703 int i;
704
86994156
RS		 705 if (rq->xdp_prog)
706 bpf_prog_put(rq->xdp_prog);
707
461017cb
TT		 708 switch (rq->wq_type) {
709 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 710 mlx5e_rq_free_mpwqe_info(rq);
a43b25da 711 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
461017cb
TT		 712 break;
713 default: /* MLX5_WQ_TYPE_LINKED_LIST */
accd5883 714 kfree(rq->wqe.frag_info);
461017cb
TT		 715 }
716
4415a031
TT		 717 for (i = rq->page_cache.head; i != rq->page_cache.tail;
718 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
719 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
720
721 mlx5e_page_release(rq, dma_info, false);
722 }
f62b8bb8
AV		 723 mlx5_wq_destroy(&rq->wq_ctrl);
724}
725
6a9764ef
SM		 726static int mlx5e_create_rq(struct mlx5e_rq *rq,
727 struct mlx5e_rq_param *param)
f62b8bb8 728{
a43b25da 729 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 730
731 void *in;
732 void *rqc;
733 void *wq;
734 int inlen;
735 int err;
736
737 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
738 sizeof(u64) * rq->wq_ctrl.buf.npages;
1b9a07ee 739 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 740 if (!in)
741 return -ENOMEM;
742
743 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
744 wq = MLX5_ADDR_OF(rqc, rqc, wq);
745
746 memcpy(rqc, param->rqc, sizeof(param->rqc));
747
97de9f31 748 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 749 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
f62b8bb8 750 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 751 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 752 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
753
754 mlx5_fill_page_array(&rq->wq_ctrl.buf,
755 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
756
7db22ffb 757 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 758
759 kvfree(in);
760
761 return err;
762}
763
36350114
GP		 764static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
765 int next_state)
f62b8bb8
AV		 766{
767 struct mlx5e_channel *c = rq->channel;
a43b25da 768 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 769
770 void *in;
771 void *rqc;
772 int inlen;
773 int err;
774
775 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 776 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 777 if (!in)
778 return -ENOMEM;
779
780 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
781
782 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
783 MLX5_SET(rqc, rqc, state, next_state);
784
7db22ffb 785 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 786
787 kvfree(in);
788
789 return err;
790}
791
102722fc
GE		 792static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
793{
794 struct mlx5e_channel *c = rq->channel;
795 struct mlx5e_priv *priv = c->priv;
796 struct mlx5_core_dev *mdev = priv->mdev;
797
798 void *in;
799 void *rqc;
800 int inlen;
801 int err;
802
803 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 804 in = kvzalloc(inlen, GFP_KERNEL);
102722fc
GE		 805 if (!in)
806 return -ENOMEM;
807
808 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
809
810 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
811 MLX5_SET64(modify_rq_in, in, modify_bitmask,
812 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
813 MLX5_SET(rqc, rqc, scatter_fcs, enable);
814 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
815
816 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
817
818 kvfree(in);
819
820 return err;
821}
822
36350114
GP		 823static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
824{
825 struct mlx5e_channel *c = rq->channel;
a43b25da 826 struct mlx5_core_dev *mdev = c->mdev;
36350114
GP		 827 void *in;
828 void *rqc;
829 int inlen;
830 int err;
831
832 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 833 in = kvzalloc(inlen, GFP_KERNEL);
36350114
GP		 834 if (!in)
835 return -ENOMEM;
836
837 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
838
839 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 840 MLX5_SET64(modify_rq_in, in, modify_bitmask,
841 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 842 MLX5_SET(rqc, rqc, vsd, vsd);
843 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
844
845 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
846
847 kvfree(in);
848
849 return err;
850}
851
3b77235b 852static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 853{
a43b25da 854 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
f62b8bb8
AV		 855}
856
857static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
858{
01c196a2 859 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8 860 struct mlx5e_channel *c = rq->channel;
a43b25da 861
f62b8bb8 862 struct mlx5_wq_ll *wq = &rq->wq;
6a9764ef 863 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
f62b8bb8 864
01c196a2 865 while (time_before(jiffies, exp_time)) {
6a9764ef 866 if (wq->cur_sz >= min_wqes)
f62b8bb8
AV		 867 return 0;
868
869 msleep(20);
870 }
871
a43b25da 872 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
6a9764ef 873 rq->rqn, wq->cur_sz, min_wqes);
f62b8bb8
AV		 874 return -ETIMEDOUT;
875}
876
f2fde18c
SM		 877static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
878{
879 struct mlx5_wq_ll *wq = &rq->wq;
880 struct mlx5e_rx_wqe *wqe;
881 __be16 wqe_ix_be;
882 u16 wqe_ix;
883
8484f9ed 884 /* UMR WQE (if in progress) is always at wq->head */
a071cb9f
TT		 885 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
886 rq->mpwqe.umr_in_progress)
21c59685 887 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 888
f2fde18c
SM		 889 while (!mlx5_wq_ll_is_empty(wq)) {
890 wqe_ix_be = *wq->tail_next;
891 wqe_ix = be16_to_cpu(wqe_ix_be);
892 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
893 rq->dealloc_wqe(rq, wqe_ix);
894 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
895 &wqe->next.next_wqe_index);
896 }
accd5883
TT		 897
898 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
899 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
900 * but yet to be re-posted.
901 */
902 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
903
904 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
905 rq->dealloc_wqe(rq, wqe_ix);
906 }
f2fde18c
SM		 907}
908
f62b8bb8 909static int mlx5e_open_rq(struct mlx5e_channel *c,
6a9764ef 910 struct mlx5e_params *params,
f62b8bb8
AV		 911 struct mlx5e_rq_param *param,
912 struct mlx5e_rq *rq)
913{
914 int err;
915
6a9764ef 916 err = mlx5e_alloc_rq(c, params, param, rq);
f62b8bb8
AV		 917 if (err)
918 return err;
919
3b77235b 920 err = mlx5e_create_rq(rq, param);
f62b8bb8 921 if (err)
3b77235b 922 goto err_free_rq;
f62b8bb8 923
36350114 924 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 925 if (err)
3b77235b 926 goto err_destroy_rq;
f62b8bb8 927
6a9764ef 928 if (params->rx_am_enabled)
a1eaba4c 929 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
cb3c7fd4 930
f62b8bb8
AV		 931 return 0;
932
f62b8bb8
AV		 933err_destroy_rq:
934 mlx5e_destroy_rq(rq);
3b77235b
SM		 935err_free_rq:
936 mlx5e_free_rq(rq);
f62b8bb8
AV		 937
938 return err;
939}
940
acc6c595
SM		 941static void mlx5e_activate_rq(struct mlx5e_rq *rq)
942{
943 struct mlx5e_icosq *sq = &rq->channel->icosq;
944 u16 pi = sq->pc & sq->wq.sz_m1;
945 struct mlx5e_tx_wqe *nopwqe;
946
947 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
948 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
acc6c595
SM		 949 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
950 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
951}
952
953static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
f62b8bb8 954{
c0f1147d 955 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 956 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
acc6c595 957}
cb3c7fd4 958
acc6c595
SM		 959static void mlx5e_close_rq(struct mlx5e_rq *rq)
960{
961 cancel_work_sync(&rq->am.work);
f62b8bb8 962 mlx5e_destroy_rq(rq);
3b77235b
SM		 963 mlx5e_free_rx_descs(rq);
964 mlx5e_free_rq(rq);
f62b8bb8
AV		 965}
966
31391048 967static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
b5503b99 968{
31391048 969 kfree(sq->db.di);
b5503b99
SM		 970}
971
31391048 972static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
b5503b99
SM		 973{
974 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
975
31391048 976 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
b5503b99 977 GFP_KERNEL, numa);
31391048
SM		 978 if (!sq->db.di) {
979 mlx5e_free_xdpsq_db(sq);
b5503b99
SM		 980 return -ENOMEM;
981 }
982
983 return 0;
984}
985
31391048 986static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
6a9764ef 987 struct mlx5e_params *params,
31391048
SM		 988 struct mlx5e_sq_param *param,
989 struct mlx5e_xdpsq *sq)
990{
991 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 992 struct mlx5_core_dev *mdev = c->mdev;
31391048
SM		 993 int err;
994
995 sq->pdev = c->pdev;
996 sq->mkey_be = c->mkey_be;
997 sq->channel = c;
998 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 999 sq->min_inline_mode = params->tx_min_inline_mode;
31391048 1000
a435393a 1001 param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
31391048
SM		 1002 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1003 if (err)
1004 return err;
1005 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1006
a435393a 1007 err = mlx5e_alloc_xdpsq_db(sq, mlx5e_get_node(c->priv, c->ix));
31391048
SM		 1008 if (err)
1009 goto err_sq_wq_destroy;
1010
1011 return 0;
1012
1013err_sq_wq_destroy:
1014 mlx5_wq_destroy(&sq->wq_ctrl);
1015
1016 return err;
1017}
1018
1019static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1020{
1021 mlx5e_free_xdpsq_db(sq);
1022 mlx5_wq_destroy(&sq->wq_ctrl);
1023}
1024
1025static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
f62b8bb8 1026{
f10b7cc7 1027 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 1028}
1029
31391048 1030static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
f10b7cc7
SM		 1031{
1032 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1033
1034 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1035 GFP_KERNEL, numa);
1036 if (!sq->db.ico_wqe)
1037 return -ENOMEM;
1038
1039 return 0;
1040}
1041
31391048 1042static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
31391048
SM		 1043 struct mlx5e_sq_param *param,
1044 struct mlx5e_icosq *sq)
f10b7cc7 1045{
31391048 1046 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1047 struct mlx5_core_dev *mdev = c->mdev;
31391048 1048 int err;
f10b7cc7 1049
31391048
SM		 1050 sq->mkey_be = c->mkey_be;
1051 sq->channel = c;
1052 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f62b8bb8 1053
a435393a 1054 param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
31391048
SM		 1055 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1056 if (err)
1057 return err;
1058 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1059
a435393a 1060 err = mlx5e_alloc_icosq_db(sq, mlx5e_get_node(c->priv, c->ix));
31391048
SM		 1061 if (err)
1062 goto err_sq_wq_destroy;
1063
1064 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
f62b8bb8
AV		 1065
1066 return 0;
31391048
SM		 1067
1068err_sq_wq_destroy:
1069 mlx5_wq_destroy(&sq->wq_ctrl);
1070
1071 return err;
f62b8bb8
AV		 1072}
1073
31391048 1074static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
f10b7cc7 1075{
31391048
SM		 1076 mlx5e_free_icosq_db(sq);
1077 mlx5_wq_destroy(&sq->wq_ctrl);
f10b7cc7
SM		 1078}
1079
31391048 1080static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
f10b7cc7 1081{
31391048
SM		 1082 kfree(sq->db.wqe_info);
1083 kfree(sq->db.dma_fifo);
f10b7cc7
SM		 1084}
1085
31391048 1086static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
b5503b99 1087{
31391048
SM		 1088 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1089 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1090
31391048
SM		 1091 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1092 GFP_KERNEL, numa);
1093 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1094 GFP_KERNEL, numa);
77bdf895 1095 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
31391048
SM		 1096 mlx5e_free_txqsq_db(sq);
1097 return -ENOMEM;
b5503b99 1098 }
31391048
SM		 1099
1100 sq->dma_fifo_mask = df_sz - 1;
1101
1102 return 0;
b5503b99
SM		 1103}
1104
31391048 1105static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
acc6c595 1106 int txq_ix,
6a9764ef 1107 struct mlx5e_params *params,
31391048
SM		 1108 struct mlx5e_sq_param *param,
1109 struct mlx5e_txqsq *sq)
f62b8bb8 1110{
31391048 1111 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1112 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 1113 int err;
1114
f10b7cc7 1115 sq->pdev = c->pdev;
a43b25da 1116 sq->tstamp = c->tstamp;
7c39afb3 1117 sq->clock = &mdev->clock;
f10b7cc7
SM		 1118 sq->mkey_be = c->mkey_be;
1119 sq->channel = c;
acc6c595 1120 sq->txq_ix = txq_ix;
aff26157 1121 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef
SM		 1122 sq->max_inline = params->tx_max_inline;
1123 sq->min_inline_mode = params->tx_min_inline_mode;
2ac9cfe7
IT		 1124 if (MLX5_IPSEC_DEV(c->priv->mdev))
1125 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
f10b7cc7 1126
a435393a 1127 param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
31391048 1128 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
f62b8bb8 1129 if (err)
aff26157 1130 return err;
31391048 1131 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1132
a435393a 1133 err = mlx5e_alloc_txqsq_db(sq, mlx5e_get_node(c->priv, c->ix));
7ec0bb22 1134 if (err)
f62b8bb8
AV		 1135 goto err_sq_wq_destroy;
1136
31391048 1137 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
f62b8bb8
AV		 1138
1139 return 0;
1140
1141err_sq_wq_destroy:
1142 mlx5_wq_destroy(&sq->wq_ctrl);
1143
f62b8bb8
AV		 1144 return err;
1145}
1146
31391048 1147static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1148{
31391048 1149 mlx5e_free_txqsq_db(sq);
f62b8bb8 1150 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1151}
1152
33ad9711
SM		 1153struct mlx5e_create_sq_param {
1154 struct mlx5_wq_ctrl *wq_ctrl;
1155 u32 cqn;
1156 u32 tisn;
1157 u8 tis_lst_sz;
1158 u8 min_inline_mode;
1159};
1160
a43b25da 1161static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
33ad9711
SM		 1162 struct mlx5e_sq_param *param,
1163 struct mlx5e_create_sq_param *csp,
1164 u32 *sqn)
f62b8bb8 1165{
f62b8bb8
AV		 1166 void *in;
1167 void *sqc;
1168 void *wq;
1169 int inlen;
1170 int err;
1171
1172 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
33ad9711 1173 sizeof(u64) * csp->wq_ctrl->buf.npages;
1b9a07ee 1174 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1175 if (!in)
1176 return -ENOMEM;
1177
1178 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1179 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1180
1181 memcpy(sqc, param->sqc, sizeof(param->sqc));
33ad9711
SM		 1182 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1183 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1184 MLX5_SET(sqc, sqc, cqn, csp->cqn);
a6f402e4
SM		 1185
1186 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
33ad9711 1187 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
a6f402e4 1188
33ad9711 1189 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f62b8bb8
AV		 1190
1191 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
a43b25da 1192 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
33ad9711 1193 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
68cdf5d6 1194 MLX5_ADAPTER_PAGE_SHIFT);
33ad9711 1195 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
f62b8bb8 1196
33ad9711 1197 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 1198
33ad9711 1199 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
f62b8bb8
AV		 1200
1201 kvfree(in);
1202
1203 return err;
1204}
1205
33ad9711
SM		 1206struct mlx5e_modify_sq_param {
1207 int curr_state;
1208 int next_state;
1209 bool rl_update;
1210 int rl_index;
1211};
1212
a43b25da 1213static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
33ad9711 1214 struct mlx5e_modify_sq_param *p)
f62b8bb8 1215{
f62b8bb8
AV		 1216 void *in;
1217 void *sqc;
1218 int inlen;
1219 int err;
1220
1221 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 1222 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1223 if (!in)
1224 return -ENOMEM;
1225
1226 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1227
33ad9711
SM		 1228 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1229 MLX5_SET(sqc, sqc, state, p->next_state);
1230 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
507f0c81 1231 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
33ad9711 1232 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
507f0c81 1233 }
f62b8bb8 1234
33ad9711 1235 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
f62b8bb8
AV		 1236
1237 kvfree(in);
1238
1239 return err;
1240}
1241
a43b25da 1242static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
33ad9711 1243{
a43b25da 1244 mlx5_core_destroy_sq(mdev, sqn);
f62b8bb8
AV		 1245}
1246
a43b25da 1247static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
31391048
SM		 1248 struct mlx5e_sq_param *param,
1249 struct mlx5e_create_sq_param *csp,
1250 u32 *sqn)
f62b8bb8 1251{
33ad9711 1252 struct mlx5e_modify_sq_param msp = {0};
31391048
SM		 1253 int err;
1254
a43b25da 1255 err = mlx5e_create_sq(mdev, param, csp, sqn);
31391048
SM		 1256 if (err)
1257 return err;
1258
1259 msp.curr_state = MLX5_SQC_STATE_RST;
1260 msp.next_state = MLX5_SQC_STATE_RDY;
a43b25da 1261 err = mlx5e_modify_sq(mdev, *sqn, &msp);
31391048 1262 if (err)
a43b25da 1263 mlx5e_destroy_sq(mdev, *sqn);
31391048
SM		 1264
1265 return err;
1266}
1267
7f859ecf
SM		 1268static int mlx5e_set_sq_maxrate(struct net_device *dev,
1269 struct mlx5e_txqsq *sq, u32 rate);
1270
31391048 1271static int mlx5e_open_txqsq(struct mlx5e_channel *c,
a43b25da 1272 u32 tisn,
acc6c595 1273 int txq_ix,
6a9764ef 1274 struct mlx5e_params *params,
31391048
SM		 1275 struct mlx5e_sq_param *param,
1276 struct mlx5e_txqsq *sq)
1277{
1278 struct mlx5e_create_sq_param csp = {};
7f859ecf 1279 u32 tx_rate;
f62b8bb8
AV		 1280 int err;
1281
6a9764ef 1282 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
f62b8bb8
AV		 1283 if (err)
1284 return err;
1285
a43b25da 1286 csp.tisn = tisn;
31391048 1287 csp.tis_lst_sz = 1;
33ad9711
SM		 1288 csp.cqn = sq->cq.mcq.cqn;
1289 csp.wq_ctrl = &sq->wq_ctrl;
1290 csp.min_inline_mode = sq->min_inline_mode;
a43b25da 1291 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
f62b8bb8 1292 if (err)
31391048 1293 goto err_free_txqsq;
f62b8bb8 1294
a43b25da 1295 tx_rate = c->priv->tx_rates[sq->txq_ix];
7f859ecf 1296 if (tx_rate)
a43b25da 1297 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
7f859ecf 1298
f62b8bb8
AV		 1299 return 0;
1300
31391048 1301err_free_txqsq:
3b77235b 1302 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
31391048 1303 mlx5e_free_txqsq(sq);
f62b8bb8
AV		 1304
1305 return err;
1306}
1307
acc6c595
SM		 1308static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1309{
a43b25da 1310 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
acc6c595
SM		 1311 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1312 netdev_tx_reset_queue(sq->txq);
1313 netif_tx_start_queue(sq->txq);
1314}
1315
f62b8bb8
AV		 1316static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1317{
1318 __netif_tx_lock_bh(txq);
1319 netif_tx_stop_queue(txq);
1320 __netif_tx_unlock_bh(txq);
1321}
1322
acc6c595 1323static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1324{
33ad9711 1325 struct mlx5e_channel *c = sq->channel;
33ad9711 1326
c0f1147d 1327 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6 1328 /* prevent netif_tx_wake_queue */
33ad9711 1329 napi_synchronize(&c->napi);
29429f33 1330
31391048 1331 netif_tx_disable_queue(sq->txq);
f62b8bb8 1332
31391048
SM		 1333 /* last doorbell out, godspeed .. */
1334 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1335 struct mlx5e_tx_wqe *nop;
864b2d71 1336
77bdf895 1337 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
31391048
SM		 1338 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1339 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
29429f33 1340 }
acc6c595
SM		 1341}
1342
1343static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1344{
1345 struct mlx5e_channel *c = sq->channel;
a43b25da 1346 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1347
a43b25da 1348 mlx5e_destroy_sq(mdev, sq->sqn);
33ad9711
SM		 1349 if (sq->rate_limit)
1350 mlx5_rl_remove_rate(mdev, sq->rate_limit);
31391048
SM		 1351 mlx5e_free_txqsq_descs(sq);
1352 mlx5e_free_txqsq(sq);
1353}
1354
1355static int mlx5e_open_icosq(struct mlx5e_channel *c,
6a9764ef 1356 struct mlx5e_params *params,
31391048
SM		 1357 struct mlx5e_sq_param *param,
1358 struct mlx5e_icosq *sq)
1359{
1360 struct mlx5e_create_sq_param csp = {};
1361 int err;
1362
6a9764ef 1363 err = mlx5e_alloc_icosq(c, param, sq);
31391048
SM		 1364 if (err)
1365 return err;
1366
1367 csp.cqn = sq->cq.mcq.cqn;
1368 csp.wq_ctrl = &sq->wq_ctrl;
6a9764ef 1369 csp.min_inline_mode = params->tx_min_inline_mode;
31391048 1370 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1371 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1372 if (err)
1373 goto err_free_icosq;
1374
1375 return 0;
1376
1377err_free_icosq:
1378 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1379 mlx5e_free_icosq(sq);
1380
1381 return err;
1382}
1383
1384static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1385{
1386 struct mlx5e_channel *c = sq->channel;
1387
1388 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1389 napi_synchronize(&c->napi);
1390
a43b25da 1391 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1392 mlx5e_free_icosq(sq);
1393}
1394
1395static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
6a9764ef 1396 struct mlx5e_params *params,
31391048
SM		 1397 struct mlx5e_sq_param *param,
1398 struct mlx5e_xdpsq *sq)
1399{
1400 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1401 struct mlx5e_create_sq_param csp = {};
31391048
SM		 1402 unsigned int inline_hdr_sz = 0;
1403 int err;
1404 int i;
1405
6a9764ef 1406 err = mlx5e_alloc_xdpsq(c, params, param, sq);
31391048
SM		 1407 if (err)
1408 return err;
1409
1410 csp.tis_lst_sz = 1;
a43b25da 1411 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
31391048
SM		 1412 csp.cqn = sq->cq.mcq.cqn;
1413 csp.wq_ctrl = &sq->wq_ctrl;
1414 csp.min_inline_mode = sq->min_inline_mode;
1415 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1416 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1417 if (err)
1418 goto err_free_xdpsq;
1419
1420 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1421 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1422 ds_cnt++;
1423 }
1424
1425 /* Pre initialize fixed WQE fields */
1426 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1427 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1428 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1429 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1430 struct mlx5_wqe_data_seg *dseg;
1431
1432 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1433 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1434
1435 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1436 dseg->lkey = sq->mkey_be;
1437 }
1438
1439 return 0;
1440
1441err_free_xdpsq:
1442 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1443 mlx5e_free_xdpsq(sq);
1444
1445 return err;
1446}
1447
1448static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1449{
1450 struct mlx5e_channel *c = sq->channel;
1451
1452 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1453 napi_synchronize(&c->napi);
1454
a43b25da 1455 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1456 mlx5e_free_xdpsq_descs(sq);
1457 mlx5e_free_xdpsq(sq);
f62b8bb8
AV		 1458}
1459
95b6c6a5
EBE		 1460static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1461 struct mlx5e_cq_param *param,
1462 struct mlx5e_cq *cq)
f62b8bb8 1463{
f62b8bb8
AV		 1464 struct mlx5_core_cq *mcq = &cq->mcq;
1465 int eqn_not_used;
0b6e26ce 1466 unsigned int irqn;
f62b8bb8
AV		 1467 int err;
1468 u32 i;
1469
f62b8bb8
AV		 1470 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1471 &cq->wq_ctrl);
1472 if (err)
1473 return err;
1474
1475 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1476
f62b8bb8
AV		 1477 mcq->cqe_sz = 64;
1478 mcq->set_ci_db = cq->wq_ctrl.db.db;
1479 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1480 *mcq->set_ci_db = 0;
1481 *mcq->arm_db = 0;
1482 mcq->vector = param->eq_ix;
1483 mcq->comp = mlx5e_completion_event;
1484 mcq->event = mlx5e_cq_error_event;
1485 mcq->irqn = irqn;
f62b8bb8
AV		 1486
1487 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1488 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1489
1490 cqe->op_own = 0xf1;
1491 }
1492
a43b25da 1493 cq->mdev = mdev;
f62b8bb8
AV		 1494
1495 return 0;
1496}
1497
95b6c6a5
EBE		 1498static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1499 struct mlx5e_cq_param *param,
1500 struct mlx5e_cq *cq)
1501{
1502 struct mlx5_core_dev *mdev = c->priv->mdev;
1503 int err;
1504
a435393a
SG		 1505 param->wq.buf_numa_node = mlx5e_get_node(c->priv, c->ix);
1506 param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
95b6c6a5
EBE		 1507 param->eq_ix = c->ix;
1508
1509 err = mlx5e_alloc_cq_common(mdev, param, cq);
1510
1511 cq->napi = &c->napi;
1512 cq->channel = c;
1513
1514 return err;
1515}
1516
3b77235b 1517static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1518{
1c1b5228 1519 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1520}
1521
3b77235b 1522static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1523{
a43b25da 1524 struct mlx5_core_dev *mdev = cq->mdev;
f62b8bb8
AV		 1525 struct mlx5_core_cq *mcq = &cq->mcq;
1526
1527 void *in;
1528 void *cqc;
1529 int inlen;
0b6e26ce 1530 unsigned int irqn_not_used;
f62b8bb8
AV		 1531 int eqn;
1532 int err;
1533
1534 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1535 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1b9a07ee 1536 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1537 if (!in)
1538 return -ENOMEM;
1539
1540 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1541
1542 memcpy(cqc, param->cqc, sizeof(param->cqc));
1543
1c1b5228
TT		 1544 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1545 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1546
1547 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1548
9908aa29 1549 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1550 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1551 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1c1b5228 1552 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1553 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1554 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1555
1556 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1557
1558 kvfree(in);
1559
1560 if (err)
1561 return err;
1562
1563 mlx5e_cq_arm(cq);
1564
1565 return 0;
1566}
1567
3b77235b 1568static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1569{
a43b25da 1570 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
f62b8bb8
AV		 1571}
1572
1573static int mlx5e_open_cq(struct mlx5e_channel *c,
6a9764ef 1574 struct mlx5e_cq_moder moder,
f62b8bb8 1575 struct mlx5e_cq_param *param,
6a9764ef 1576 struct mlx5e_cq *cq)
f62b8bb8 1577{
a43b25da 1578 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1579 int err;
f62b8bb8 1580
3b77235b 1581 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1582 if (err)
1583 return err;
1584
3b77235b 1585 err = mlx5e_create_cq(cq, param);
f62b8bb8 1586 if (err)
3b77235b 1587 goto err_free_cq;
f62b8bb8 1588
7524a5d8 1589 if (MLX5_CAP_GEN(mdev, cq_moderation))
6a9764ef 1590 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
f62b8bb8
AV		 1591 return 0;
1592
3b77235b
SM		 1593err_free_cq:
1594 mlx5e_free_cq(cq);
f62b8bb8
AV		 1595
1596 return err;
1597}
1598
1599static void mlx5e_close_cq(struct mlx5e_cq *cq)
1600{
f62b8bb8 1601 mlx5e_destroy_cq(cq);
3b77235b 1602 mlx5e_free_cq(cq);
f62b8bb8
AV		 1603}
1604
f62b8bb8 1605static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
6a9764ef 1606 struct mlx5e_params *params,
f62b8bb8
AV		 1607 struct mlx5e_channel_param *cparam)
1608{
f62b8bb8
AV		 1609 int err;
1610 int tc;
1611
1612 for (tc = 0; tc < c->num_tc; tc++) {
6a9764ef
SM		 1613 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1614 &cparam->tx_cq, &c->sq[tc].cq);
f62b8bb8
AV		 1615 if (err)
1616 goto err_close_tx_cqs;
f62b8bb8
AV		 1617 }
1618
1619 return 0;
1620
1621err_close_tx_cqs:
1622 for (tc--; tc >= 0; tc--)
1623 mlx5e_close_cq(&c->sq[tc].cq);
1624
1625 return err;
1626}
1627
1628static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1629{
1630 int tc;
1631
1632 for (tc = 0; tc < c->num_tc; tc++)
1633 mlx5e_close_cq(&c->sq[tc].cq);
1634}
1635
1636static int mlx5e_open_sqs(struct mlx5e_channel *c,
6a9764ef 1637 struct mlx5e_params *params,
f62b8bb8
AV		 1638 struct mlx5e_channel_param *cparam)
1639{
1640 int err;
1641 int tc;
1642
6a9764ef
SM		 1643 for (tc = 0; tc < params->num_tc; tc++) {
1644 int txq_ix = c->ix + tc * params->num_channels;
acc6c595 1645
a43b25da
SM		 1646 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1647 params, &cparam->sq, &c->sq[tc]);
f62b8bb8
AV		 1648 if (err)
1649 goto err_close_sqs;
1650 }
1651
1652 return 0;
1653
1654err_close_sqs:
1655 for (tc--; tc >= 0; tc--)
31391048 1656 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1657
1658 return err;
1659}
1660
1661static void mlx5e_close_sqs(struct mlx5e_channel *c)
1662{
1663 int tc;
1664
1665 for (tc = 0; tc < c->num_tc; tc++)
31391048 1666 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1667}
1668
507f0c81 1669static int mlx5e_set_sq_maxrate(struct net_device *dev,
31391048 1670 struct mlx5e_txqsq *sq, u32 rate)
507f0c81
YP		 1671{
1672 struct mlx5e_priv *priv = netdev_priv(dev);
1673 struct mlx5_core_dev *mdev = priv->mdev;
33ad9711 1674 struct mlx5e_modify_sq_param msp = {0};
507f0c81
YP		 1675 u16 rl_index = 0;
1676 int err;
1677
1678 if (rate == sq->rate_limit)
1679 /* nothing to do */
1680 return 0;
1681
1682 if (sq->rate_limit)
1683 /* remove current rl index to free space to next ones */
1684 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1685
1686 sq->rate_limit = 0;
1687
1688 if (rate) {
1689 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1690 if (err) {
1691 netdev_err(dev, "Failed configuring rate %u: %d\n",
1692 rate, err);
1693 return err;
1694 }
1695 }
1696
33ad9711
SM		 1697 msp.curr_state = MLX5_SQC_STATE_RDY;
1698 msp.next_state = MLX5_SQC_STATE_RDY;
1699 msp.rl_index = rl_index;
1700 msp.rl_update = true;
a43b25da 1701 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
507f0c81
YP		 1702 if (err) {
1703 netdev_err(dev, "Failed configuring rate %u: %d\n",
1704 rate, err);
1705 /* remove the rate from the table */
1706 if (rate)
1707 mlx5_rl_remove_rate(mdev, rate);
1708 return err;
1709 }
1710
1711 sq->rate_limit = rate;
1712 return 0;
1713}
1714
1715static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1716{
1717 struct mlx5e_priv *priv = netdev_priv(dev);
1718 struct mlx5_core_dev *mdev = priv->mdev;
acc6c595 1719 struct mlx5e_txqsq *sq = priv->txq2sq[index];
507f0c81
YP		 1720 int err = 0;
1721
1722 if (!mlx5_rl_is_supported(mdev)) {
1723 netdev_err(dev, "Rate limiting is not supported on this device\n");
1724 return -EINVAL;
1725 }
1726
1727 /* rate is given in Mb/sec, HW config is in Kb/sec */
1728 rate = rate << 10;
1729
1730 /* Check whether rate in valid range, 0 is always valid */
1731 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1732 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1733 return -ERANGE;
1734 }
1735
1736 mutex_lock(&priv->state_lock);
1737 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1738 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1739 if (!err)
1740 priv->tx_rates[index] = rate;
1741 mutex_unlock(&priv->state_lock);
1742
1743 return err;
1744}
1745
f62b8bb8 1746static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
6a9764ef 1747 struct mlx5e_params *params,
f62b8bb8
AV		 1748 struct mlx5e_channel_param *cparam,
1749 struct mlx5e_channel **cp)
1750{
6a9764ef 1751 struct mlx5e_cq_moder icocq_moder = {0, 0};
f62b8bb8 1752 struct net_device *netdev = priv->netdev;
f62b8bb8 1753 struct mlx5e_channel *c;
a8c2eb15 1754 unsigned int irq;
f62b8bb8 1755 int err;
a8c2eb15 1756 int eqn;
f62b8bb8 1757
a435393a 1758 c = kzalloc_node(sizeof(*c), GFP_KERNEL, mlx5e_get_node(priv, ix));
f62b8bb8
AV		 1759 if (!c)
1760 return -ENOMEM;
1761
1762 c->priv = priv;
a43b25da
SM		 1763 c->mdev = priv->mdev;
1764 c->tstamp = &priv->tstamp;
f62b8bb8 1765 c->ix = ix;
f62b8bb8
AV		 1766 c->pdev = &priv->mdev->pdev->dev;
1767 c->netdev = priv->netdev;
b50d292b 1768 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
6a9764ef
SM		 1769 c->num_tc = params->num_tc;
1770 c->xdp = !!params->xdp_prog;
cb3c7fd4 1771
a8c2eb15
TT		 1772 mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1773 c->irq_desc = irq_to_desc(irq);
1774
f62b8bb8
AV		 1775 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1776
6a9764ef 1777 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
f62b8bb8
AV		 1778 if (err)
1779 goto err_napi_del;
1780
6a9764ef 1781 err = mlx5e_open_tx_cqs(c, params, cparam);
d3c9bc27
TT		 1782 if (err)
1783 goto err_close_icosq_cq;
1784
6a9764ef 1785 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
f62b8bb8
AV		 1786 if (err)
1787 goto err_close_tx_cqs;
f62b8bb8 1788
d7a0ecab 1789 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
6a9764ef
SM		 1790 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1791 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
d7a0ecab
SM		 1792 if (err)
1793 goto err_close_rx_cq;
1794
f62b8bb8
AV		 1795 napi_enable(&c->napi);
1796
6a9764ef 1797 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1798 if (err)
1799 goto err_disable_napi;
1800
6a9764ef 1801 err = mlx5e_open_sqs(c, params, cparam);
d3c9bc27
TT		 1802 if (err)
1803 goto err_close_icosq;
1804
6a9764ef 1805 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
d7a0ecab
SM		 1806 if (err)
1807 goto err_close_sqs;
b5503b99 1808
6a9764ef 1809 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
f62b8bb8 1810 if (err)
b5503b99 1811 goto err_close_xdp_sq;
f62b8bb8 1812
f62b8bb8
AV		 1813 *cp = c;
1814
1815 return 0;
b5503b99 1816err_close_xdp_sq:
d7a0ecab 1817 if (c->xdp)
31391048 1818 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8
AV		 1819
1820err_close_sqs:
1821 mlx5e_close_sqs(c);
1822
d3c9bc27 1823err_close_icosq:
31391048 1824 mlx5e_close_icosq(&c->icosq);
d3c9bc27 1825
f62b8bb8
AV		 1826err_disable_napi:
1827 napi_disable(&c->napi);
d7a0ecab 1828 if (c->xdp)
31871f87 1829 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 1830
1831err_close_rx_cq:
f62b8bb8
AV		 1832 mlx5e_close_cq(&c->rq.cq);
1833
1834err_close_tx_cqs:
1835 mlx5e_close_tx_cqs(c);
1836
d3c9bc27
TT		 1837err_close_icosq_cq:
1838 mlx5e_close_cq(&c->icosq.cq);
1839
f62b8bb8
AV		 1840err_napi_del:
1841 netif_napi_del(&c->napi);
1842 kfree(c);
1843
1844 return err;
1845}
1846
acc6c595
SM		 1847static void mlx5e_activate_channel(struct mlx5e_channel *c)
1848{
1849 int tc;
1850
1851 for (tc = 0; tc < c->num_tc; tc++)
1852 mlx5e_activate_txqsq(&c->sq[tc]);
1853 mlx5e_activate_rq(&c->rq);
a435393a
SG		 1854 netif_set_xps_queue(c->netdev,
1855 mlx5_get_vector_affinity(c->priv->mdev, c->ix), c->ix);
acc6c595
SM		 1856}
1857
1858static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1859{
1860 int tc;
1861
1862 mlx5e_deactivate_rq(&c->rq);
1863 for (tc = 0; tc < c->num_tc; tc++)
1864 mlx5e_deactivate_txqsq(&c->sq[tc]);
1865}
1866
f62b8bb8
AV		 1867static void mlx5e_close_channel(struct mlx5e_channel *c)
1868{
1869 mlx5e_close_rq(&c->rq);
b5503b99 1870 if (c->xdp)
31391048 1871 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8 1872 mlx5e_close_sqs(c);
31391048 1873 mlx5e_close_icosq(&c->icosq);
f62b8bb8 1874 napi_disable(&c->napi);
b5503b99 1875 if (c->xdp)
31871f87 1876 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8
AV		 1877 mlx5e_close_cq(&c->rq.cq);
1878 mlx5e_close_tx_cqs(c);
d3c9bc27 1879 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1880 netif_napi_del(&c->napi);
7ae92ae5 1881
f62b8bb8
AV		 1882 kfree(c);
1883}
1884
1885static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
6a9764ef 1886 struct mlx5e_params *params,
f62b8bb8
AV		 1887 struct mlx5e_rq_param *param)
1888{
1889 void *rqc = param->rqc;
1890 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1891
6a9764ef 1892 switch (params->rq_wq_type) {
461017cb 1893 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef
SM		 1894 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1895 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
461017cb
TT		 1896 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1897 break;
1898 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1899 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1900 }
1901
f62b8bb8
AV		 1902 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1903 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
6a9764ef 1904 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
b50d292b 1905 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1906 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
6a9764ef 1907 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
102722fc 1908 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
f62b8bb8 1909
311c7c71 1910 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1911 param->wq.linear = 1;
1912}
1913
556dd1b9
TT		 1914static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1915{
1916 void *rqc = param->rqc;
1917 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1918
1919 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1920 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1921}
1922
d3c9bc27
TT		 1923static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1924 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1925{
1926 void *sqc = param->sqc;
1927 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1928
f62b8bb8 1929 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1930 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1931
311c7c71 1932 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1933}
1934
1935static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
6a9764ef 1936 struct mlx5e_params *params,
d3c9bc27
TT		 1937 struct mlx5e_sq_param *param)
1938{
1939 void *sqc = param->sqc;
1940 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1941
1942 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1943 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2ac9cfe7 1944 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
f62b8bb8
AV		 1945}
1946
1947static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1948 struct mlx5e_cq_param *param)
1949{
1950 void *cqc = param->cqc;
1951
30aa60b3 1952 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 1953}
1954
1955static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1956 struct mlx5e_params *params,
f62b8bb8
AV		 1957 struct mlx5e_cq_param *param)
1958{
1959 void *cqc = param->cqc;
461017cb 1960 u8 log_cq_size;
f62b8bb8 1961
6a9764ef 1962 switch (params->rq_wq_type) {
461017cb 1963 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 1964 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
461017cb
TT		 1965 break;
1966 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 1967 log_cq_size = params->log_rq_size;
461017cb
TT		 1968 }
1969
1970 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
6a9764ef 1971 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1972 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1973 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1974 }
f62b8bb8
AV		 1975
1976 mlx5e_build_common_cq_param(priv, param);
0088cbbc 1977 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 1978}
1979
1980static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1981 struct mlx5e_params *params,
f62b8bb8
AV		 1982 struct mlx5e_cq_param *param)
1983{
1984 void *cqc = param->cqc;
1985
6a9764ef 1986 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
f62b8bb8
AV		 1987
1988 mlx5e_build_common_cq_param(priv, param);
0088cbbc 1989 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 1990}
1991
d3c9bc27 1992static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1993 u8 log_wq_size,
1994 struct mlx5e_cq_param *param)
d3c9bc27
TT		 1995{
1996 void *cqc = param->cqc;
1997
1998 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1999
2000 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 2001
2002 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 2003}
2004
2005static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 2006 u8 log_wq_size,
2007 struct mlx5e_sq_param *param)
d3c9bc27
TT		 2008{
2009 void *sqc = param->sqc;
2010 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2011
2012 mlx5e_build_sq_param_common(priv, param);
2013
2014 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 2015 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 2016}
2017
b5503b99 2018static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
6a9764ef 2019 struct mlx5e_params *params,
b5503b99
SM		 2020 struct mlx5e_sq_param *param)
2021{
2022 void *sqc = param->sqc;
2023 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2024
2025 mlx5e_build_sq_param_common(priv, param);
6a9764ef 2026 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
b5503b99
SM		 2027}
2028
6a9764ef
SM		 2029static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2030 struct mlx5e_params *params,
2031 struct mlx5e_channel_param *cparam)
f62b8bb8 2032{
bc77b240 2033 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 2034
6a9764ef
SM		 2035 mlx5e_build_rq_param(priv, params, &cparam->rq);
2036 mlx5e_build_sq_param(priv, params, &cparam->sq);
2037 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2038 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2039 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2040 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2041 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
f62b8bb8
AV		 2042}
2043
55c2503d
SM		 2044int mlx5e_open_channels(struct mlx5e_priv *priv,
2045 struct mlx5e_channels *chs)
f62b8bb8 2046{
6b87663f 2047 struct mlx5e_channel_param *cparam;
03289b88 2048 int err = -ENOMEM;
f62b8bb8 2049 int i;
f62b8bb8 2050
6a9764ef 2051 chs->num = chs->params.num_channels;
03289b88 2052
ff9c852f 2053 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
6b87663f 2054 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
acc6c595
SM		 2055 if (!chs->c || !cparam)
2056 goto err_free;
f62b8bb8 2057
6a9764ef 2058 mlx5e_build_channel_param(priv, &chs->params, cparam);
ff9c852f 2059 for (i = 0; i < chs->num; i++) {
6a9764ef 2060 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
f62b8bb8
AV		 2061 if (err)
2062 goto err_close_channels;
2063 }
2064
6b87663f 2065 kfree(cparam);
f62b8bb8
AV		 2066 return 0;
2067
2068err_close_channels:
2069 for (i--; i >= 0; i--)
ff9c852f 2070 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2071
acc6c595 2072err_free:
ff9c852f 2073 kfree(chs->c);
6b87663f 2074 kfree(cparam);
ff9c852f 2075 chs->num = 0;
f62b8bb8
AV		 2076 return err;
2077}
2078
acc6c595 2079static void mlx5e_activate_channels(struct mlx5e_channels *chs)
f62b8bb8
AV		 2080{
2081 int i;
2082
acc6c595
SM		 2083 for (i = 0; i < chs->num; i++)
2084 mlx5e_activate_channel(chs->c[i]);
2085}
2086
2087static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2088{
2089 int err = 0;
2090 int i;
2091
2092 for (i = 0; i < chs->num; i++) {
2093 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2094 if (err)
2095 break;
2096 }
2097
2098 return err;
2099}
2100
2101static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2102{
2103 int i;
2104
2105 for (i = 0; i < chs->num; i++)
2106 mlx5e_deactivate_channel(chs->c[i]);
2107}
2108
55c2503d 2109void mlx5e_close_channels(struct mlx5e_channels *chs)
acc6c595
SM		 2110{
2111 int i;
c3b7c5c9 2112
ff9c852f
SM		 2113 for (i = 0; i < chs->num; i++)
2114 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2115
ff9c852f
SM		 2116 kfree(chs->c);
2117 chs->num = 0;
f62b8bb8
AV		 2118}
2119
a5f97fee
SM		 2120static int
2121mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 2122{
2123 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2124 void *rqtc;
2125 int inlen;
2126 int err;
1da36696 2127 u32 *in;
a5f97fee 2128 int i;
f62b8bb8 2129
f62b8bb8 2130 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2131 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2132 if (!in)
2133 return -ENOMEM;
2134
2135 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2136
2137 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2138 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2139
a5f97fee
SM		 2140 for (i = 0; i < sz; i++)
2141 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2be6967c 2142
398f3351
HHZ		 2143 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2144 if (!err)
2145 rqt->enabled = true;
f62b8bb8
AV		 2146
2147 kvfree(in);
1da36696
TT		 2148 return err;
2149}
2150
cb67b832 2151void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2152{
398f3351
HHZ		 2153 rqt->enabled = false;
2154 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2155}
2156
8f493ffd 2157int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2158{
2159 struct mlx5e_rqt *rqt = &priv->indir_rqt;
8f493ffd 2160 int err;
6bfd390b 2161
8f493ffd
SM		 2162 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2163 if (err)
2164 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2165 return err;
6bfd390b
HHZ		 2166}
2167
cb67b832 2168int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2169{
398f3351 2170 struct mlx5e_rqt *rqt;
1da36696
TT		 2171 int err;
2172 int ix;
2173
6bfd390b 2174 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351 2175 rqt = &priv->direct_tir[ix].rqt;
a5f97fee 2176 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
1da36696
TT		 2177 if (err)
2178 goto err_destroy_rqts;
2179 }
2180
2181 return 0;
2182
2183err_destroy_rqts:
8f493ffd 2184 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
1da36696 2185 for (ix--; ix >= 0; ix--)
398f3351 2186 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2187
f62b8bb8
AV		 2188 return err;
2189}
2190
8f493ffd
SM		 2191void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2192{
2193 int i;
2194
2195 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2196 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2197}
2198
a5f97fee
SM		 2199static int mlx5e_rx_hash_fn(int hfunc)
2200{
2201 return (hfunc == ETH_RSS_HASH_TOP) ?
2202 MLX5_RX_HASH_FN_TOEPLITZ :
2203 MLX5_RX_HASH_FN_INVERTED_XOR8;
2204}
2205
2206static int mlx5e_bits_invert(unsigned long a, int size)
2207{
2208 int inv = 0;
2209 int i;
2210
2211 for (i = 0; i < size; i++)
2212 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2213
2214 return inv;
2215}
2216
2217static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2218 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2219{
2220 int i;
2221
2222 for (i = 0; i < sz; i++) {
2223 u32 rqn;
2224
2225 if (rrp.is_rss) {
2226 int ix = i;
2227
2228 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2229 ix = mlx5e_bits_invert(i, ilog2(sz));
2230
6a9764ef 2231 ix = priv->channels.params.indirection_rqt[ix];
a5f97fee
SM		 2232 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2233 } else {
2234 rqn = rrp.rqn;
2235 }
2236 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2237 }
2238}
2239
2240int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2241 struct mlx5e_redirect_rqt_param rrp)
5c50368f
AS		 2242{
2243 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2244 void *rqtc;
2245 int inlen;
1da36696 2246 u32 *in;
5c50368f
AS		 2247 int err;
2248
5c50368f 2249 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2250 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2251 if (!in)
2252 return -ENOMEM;
2253
2254 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2255
2256 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5c50368f 2257 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
a5f97fee 2258 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
1da36696 2259 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2260
2261 kvfree(in);
5c50368f
AS		 2262 return err;
2263}
2264
a5f97fee
SM		 2265static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2266 struct mlx5e_redirect_rqt_param rrp)
2267{
2268 if (!rrp.is_rss)
2269 return rrp.rqn;
2270
2271 if (ix >= rrp.rss.channels->num)
2272 return priv->drop_rq.rqn;
2273
2274 return rrp.rss.channels->c[ix]->rq.rqn;
2275}
2276
2277static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2278 struct mlx5e_redirect_rqt_param rrp)
40ab6a6e 2279{
1da36696
TT		 2280 u32 rqtn;
2281 int ix;
2282
398f3351 2283 if (priv->indir_rqt.enabled) {
a5f97fee 2284 /* RSS RQ table */
398f3351 2285 rqtn = priv->indir_rqt.rqtn;
a5f97fee 2286 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
398f3351
HHZ		 2287 }
2288
a5f97fee
SM		 2289 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2290 struct mlx5e_redirect_rqt_param direct_rrp = {
2291 .is_rss = false,
95632791
AM		 2292 {
2293 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2294 },
a5f97fee
SM		 2295 };
2296
2297 /* Direct RQ Tables */
398f3351
HHZ		 2298 if (!priv->direct_tir[ix].rqt.enabled)
2299 continue;
a5f97fee 2300
398f3351 2301 rqtn = priv->direct_tir[ix].rqt.rqtn;
a5f97fee 2302 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
1da36696 2303 }
40ab6a6e
AS		 2304}
2305
a5f97fee
SM		 2306static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2307 struct mlx5e_channels *chs)
2308{
2309 struct mlx5e_redirect_rqt_param rrp = {
2310 .is_rss = true,
95632791
AM		 2311 {
2312 .rss = {
2313 .channels = chs,
2314 .hfunc = chs->params.rss_hfunc,
2315 }
2316 },
a5f97fee
SM		 2317 };
2318
2319 mlx5e_redirect_rqts(priv, rrp);
2320}
2321
2322static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2323{
2324 struct mlx5e_redirect_rqt_param drop_rrp = {
2325 .is_rss = false,
95632791
AM		 2326 {
2327 .rqn = priv->drop_rq.rqn,
2328 },
a5f97fee
SM		 2329 };
2330
2331 mlx5e_redirect_rqts(priv, drop_rrp);
2332}
2333
6a9764ef 2334static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
5c50368f 2335{
6a9764ef 2336 if (!params->lro_en)
5c50368f
AS		 2337 return;
2338
2339#define ROUGH_MAX_L2_L3_HDR_SZ 256
2340
2341 MLX5_SET(tirc, tirc, lro_enable_mask,
2342 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2343 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2344 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
6a9764ef
SM		 2345 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2346 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
5c50368f
AS		 2347}
2348
6a9764ef
SM		 2349void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2350 enum mlx5e_traffic_types tt,
7b3722fa 2351 void *tirc, bool inner)
bdfc028d 2352{
7b3722fa
GP		 2353 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2354 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
a100ff3e
GP		 2355
2356#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2357 MLX5_HASH_FIELD_SEL_DST_IP)
2358
2359#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2360 MLX5_HASH_FIELD_SEL_DST_IP |\
2361 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2362 MLX5_HASH_FIELD_SEL_L4_DPORT)
2363
2364#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2365 MLX5_HASH_FIELD_SEL_DST_IP |\
2366 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2367
6a9764ef
SM		 2368 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2369 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
bdfc028d
TT		 2370 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2371 rx_hash_toeplitz_key);
2372 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2373 rx_hash_toeplitz_key);
2374
2375 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
6a9764ef 2376 memcpy(rss_key, params->toeplitz_hash_key, len);
bdfc028d 2377 }
a100ff3e
GP		 2378
2379 switch (tt) {
2380 case MLX5E_TT_IPV4_TCP:
2381 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2382 MLX5_L3_PROT_TYPE_IPV4);
2383 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2384 MLX5_L4_PROT_TYPE_TCP);
2385 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2386 MLX5_HASH_IP_L4PORTS);
2387 break;
2388
2389 case MLX5E_TT_IPV6_TCP:
2390 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2391 MLX5_L3_PROT_TYPE_IPV6);
2392 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2393 MLX5_L4_PROT_TYPE_TCP);
2394 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2395 MLX5_HASH_IP_L4PORTS);
2396 break;
2397
2398 case MLX5E_TT_IPV4_UDP:
2399 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2400 MLX5_L3_PROT_TYPE_IPV4);
2401 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2402 MLX5_L4_PROT_TYPE_UDP);
2403 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2404 MLX5_HASH_IP_L4PORTS);
2405 break;
2406
2407 case MLX5E_TT_IPV6_UDP:
2408 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2409 MLX5_L3_PROT_TYPE_IPV6);
2410 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2411 MLX5_L4_PROT_TYPE_UDP);
2412 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2413 MLX5_HASH_IP_L4PORTS);
2414 break;
2415
2416 case MLX5E_TT_IPV4_IPSEC_AH:
2417 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2418 MLX5_L3_PROT_TYPE_IPV4);
2419 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2420 MLX5_HASH_IP_IPSEC_SPI);
2421 break;
2422
2423 case MLX5E_TT_IPV6_IPSEC_AH:
2424 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2425 MLX5_L3_PROT_TYPE_IPV6);
2426 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2427 MLX5_HASH_IP_IPSEC_SPI);
2428 break;
2429
2430 case MLX5E_TT_IPV4_IPSEC_ESP:
2431 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2432 MLX5_L3_PROT_TYPE_IPV4);
2433 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2434 MLX5_HASH_IP_IPSEC_SPI);
2435 break;
2436
2437 case MLX5E_TT_IPV6_IPSEC_ESP:
2438 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2439 MLX5_L3_PROT_TYPE_IPV6);
2440 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2441 MLX5_HASH_IP_IPSEC_SPI);
2442 break;
2443
2444 case MLX5E_TT_IPV4:
2445 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2446 MLX5_L3_PROT_TYPE_IPV4);
2447 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2448 MLX5_HASH_IP);
2449 break;
2450
2451 case MLX5E_TT_IPV6:
2452 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2453 MLX5_L3_PROT_TYPE_IPV6);
2454 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2455 MLX5_HASH_IP);
2456 break;
2457 default:
2458 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2459 }
bdfc028d
TT		 2460}
2461
ab0394fe 2462static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2463{
2464 struct mlx5_core_dev *mdev = priv->mdev;
2465
2466 void *in;
2467 void *tirc;
2468 int inlen;
2469 int err;
ab0394fe 2470 int tt;
1da36696 2471 int ix;
5c50368f
AS		 2472
2473 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1b9a07ee 2474 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2475 if (!in)
2476 return -ENOMEM;
2477
2478 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2479 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2480
6a9764ef 2481 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
5c50368f 2482
1da36696 2483 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2484 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2485 inlen);
ab0394fe 2486 if (err)
1da36696 2487 goto free_in;
ab0394fe 2488 }
5c50368f 2489
6bfd390b 2490 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2491 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2492 in, inlen);
2493 if (err)
2494 goto free_in;
2495 }
2496
2497free_in:
5c50368f
AS		 2498 kvfree(in);
2499
2500 return err;
2501}
2502
7b3722fa
GP		 2503static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2504 enum mlx5e_traffic_types tt,
2505 u32 *tirc)
2506{
2507 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2508
2509 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2510
2511 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2512 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2513 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2514
2515 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2516}
2517
cd255eff 2518static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2519{
40ab6a6e 2520 struct mlx5_core_dev *mdev = priv->mdev;
c139dbfd 2521 u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
40ab6a6e
AS		 2522 int err;
2523
cd255eff 2524 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2525 if (err)
2526 return err;
2527
cd255eff
SM		 2528 /* Update vport context MTU */
2529 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2530 return 0;
2531}
40ab6a6e 2532
cd255eff
SM		 2533static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2534{
2535 struct mlx5_core_dev *mdev = priv->mdev;
2536 u16 hw_mtu = 0;
2537 int err;
40ab6a6e 2538
cd255eff
SM		 2539 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2540 if (err || !hw_mtu) /* fallback to port oper mtu */
2541 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2542
c139dbfd 2543 *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
cd255eff
SM		 2544}
2545
2e20a151 2546static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
cd255eff 2547{
2e20a151 2548 struct net_device *netdev = priv->netdev;
cd255eff
SM		 2549 u16 mtu;
2550 int err;
2551
2552 err = mlx5e_set_mtu(priv, netdev->mtu);
2553 if (err)
2554 return err;
40ab6a6e 2555
cd255eff
SM		 2556 mlx5e_query_mtu(priv, &mtu);
2557 if (mtu != netdev->mtu)
2558 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2559 __func__, mtu, netdev->mtu);
40ab6a6e 2560
cd255eff 2561 netdev->mtu = mtu;
40ab6a6e
AS		 2562 return 0;
2563}
2564
08fb1dac
SM		 2565static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2566{
2567 struct mlx5e_priv *priv = netdev_priv(netdev);
6a9764ef
SM		 2568 int nch = priv->channels.params.num_channels;
2569 int ntc = priv->channels.params.num_tc;
08fb1dac
SM		 2570 int tc;
2571
2572 netdev_reset_tc(netdev);
2573
2574 if (ntc == 1)
2575 return;
2576
2577 netdev_set_num_tc(netdev, ntc);
2578
7ccdd084
RS		 2579 /* Map netdev TCs to offset 0
2580 * We have our own UP to TXQ mapping for QoS
2581 */
08fb1dac 2582 for (tc = 0; tc < ntc; tc++)
7ccdd084 2583 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2584}
2585
acc6c595
SM		 2586static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2587{
2588 struct mlx5e_channel *c;
2589 struct mlx5e_txqsq *sq;
2590 int i, tc;
2591
2592 for (i = 0; i < priv->channels.num; i++)
2593 for (tc = 0; tc < priv->profile->max_tc; tc++)
2594 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2595
2596 for (i = 0; i < priv->channels.num; i++) {
2597 c = priv->channels.c[i];
2598 for (tc = 0; tc < c->num_tc; tc++) {
2599 sq = &c->sq[tc];
2600 priv->txq2sq[sq->txq_ix] = sq;
2601 }
2602 }
2603}
2604
603f4a45 2605void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2606{
9008ae07
SM		 2607 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2608 struct net_device *netdev = priv->netdev;
2609
2610 mlx5e_netdev_set_tcs(netdev);
053ee0a7
TR		 2611 netif_set_real_num_tx_queues(netdev, num_txqs);
2612 netif_set_real_num_rx_queues(netdev, priv->channels.num);
9008ae07 2613
acc6c595
SM		 2614 mlx5e_build_channels_tx_maps(priv);
2615 mlx5e_activate_channels(&priv->channels);
2616 netif_tx_start_all_queues(priv->netdev);
9008ae07 2617
a9f7705f 2618 if (MLX5_VPORT_MANAGER(priv->mdev))
9008ae07
SM		 2619 mlx5e_add_sqs_fwd_rules(priv);
2620
acc6c595 2621 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
9008ae07 2622 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
acc6c595
SM		 2623}
2624
603f4a45 2625void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2626{
9008ae07
SM		 2627 mlx5e_redirect_rqts_to_drop(priv);
2628
a9f7705f 2629 if (MLX5_VPORT_MANAGER(priv->mdev))
9008ae07
SM		 2630 mlx5e_remove_sqs_fwd_rules(priv);
2631
acc6c595
SM		 2632 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2633 * polling for inactive tx queues.
2634 */
2635 netif_tx_stop_all_queues(priv->netdev);
2636 netif_tx_disable(priv->netdev);
2637 mlx5e_deactivate_channels(&priv->channels);
2638}
2639
55c2503d 2640void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2e20a151
SM		 2641 struct mlx5e_channels *new_chs,
2642 mlx5e_fp_hw_modify hw_modify)
55c2503d
SM		 2643{
2644 struct net_device *netdev = priv->netdev;
2645 int new_num_txqs;
7ca42c80 2646 int carrier_ok;
55c2503d
SM		 2647 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2648
7ca42c80 2649 carrier_ok = netif_carrier_ok(netdev);
55c2503d
SM		 2650 netif_carrier_off(netdev);
2651
2652 if (new_num_txqs < netdev->real_num_tx_queues)
2653 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2654
2655 mlx5e_deactivate_priv_channels(priv);
2656 mlx5e_close_channels(&priv->channels);
2657
2658 priv->channels = *new_chs;
2659
2e20a151
SM		 2660 /* New channels are ready to roll, modify HW settings if needed */
2661 if (hw_modify)
2662 hw_modify(priv);
2663
55c2503d
SM		 2664 mlx5e_refresh_tirs(priv, false);
2665 mlx5e_activate_priv_channels(priv);
2666
7ca42c80
ES		 2667 /* return carrier back if needed */
2668 if (carrier_ok)
2669 netif_carrier_on(netdev);
55c2503d
SM		 2670}
2671
7c39afb3
FD		 2672void mlx5e_timestamp_set(struct mlx5e_priv *priv)
2673{
2674 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2675 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2676}
2677
40ab6a6e
AS		 2678int mlx5e_open_locked(struct net_device *netdev)
2679{
2680 struct mlx5e_priv *priv = netdev_priv(netdev);
40ab6a6e
AS		 2681 int err;
2682
2683 set_bit(MLX5E_STATE_OPENED, &priv->state);
2684
ff9c852f 2685 err = mlx5e_open_channels(priv, &priv->channels);
acc6c595 2686 if (err)
343b29f3 2687 goto err_clear_state_opened_flag;
40ab6a6e 2688
b676f653 2689 mlx5e_refresh_tirs(priv, false);
acc6c595 2690 mlx5e_activate_priv_channels(priv);
7ca42c80
ES		 2691 if (priv->profile->update_carrier)
2692 priv->profile->update_carrier(priv);
7c39afb3 2693 mlx5e_timestamp_set(priv);
be4891af 2694
cb67b832
HHZ		 2695 if (priv->profile->update_stats)
2696 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2697
9b37b07f 2698 return 0;
343b29f3
AS		 2699
2700err_clear_state_opened_flag:
2701 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2702 return err;
40ab6a6e
AS		 2703}
2704
cb67b832 2705int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2706{
2707 struct mlx5e_priv *priv = netdev_priv(netdev);
2708 int err;
2709
2710 mutex_lock(&priv->state_lock);
2711 err = mlx5e_open_locked(netdev);
63bfd399
EBE		 2712 if (!err)
2713 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
40ab6a6e
AS		 2714 mutex_unlock(&priv->state_lock);
2715
2716 return err;
2717}
2718
2719int mlx5e_close_locked(struct net_device *netdev)
2720{
2721 struct mlx5e_priv *priv = netdev_priv(netdev);
2722
a1985740
AS		 2723 /* May already be CLOSED in case a previous configuration operation
2724 * (e.g RX/TX queue size change) that involves close&open failed.
2725 */
2726 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2727 return 0;
2728
40ab6a6e
AS		 2729 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2730
40ab6a6e 2731 netif_carrier_off(priv->netdev);
acc6c595
SM		 2732 mlx5e_deactivate_priv_channels(priv);
2733 mlx5e_close_channels(&priv->channels);
40ab6a6e
AS		 2734
2735 return 0;
2736}
2737
cb67b832 2738int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2739{
2740 struct mlx5e_priv *priv = netdev_priv(netdev);
2741 int err;
2742
26e59d80
MHY		 2743 if (!netif_device_present(netdev))
2744 return -ENODEV;
2745
40ab6a6e 2746 mutex_lock(&priv->state_lock);
63bfd399 2747 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
40ab6a6e
AS		 2748 err = mlx5e_close_locked(netdev);
2749 mutex_unlock(&priv->state_lock);
2750
2751 return err;
2752}
2753
a43b25da 2754static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2755 struct mlx5e_rq *rq,
2756 struct mlx5e_rq_param *param)
40ab6a6e 2757{
40ab6a6e
AS		 2758 void *rqc = param->rqc;
2759 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2760 int err;
2761
2762 param->wq.db_numa_node = param->wq.buf_numa_node;
2763
2764 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2765 &rq->wq_ctrl);
2766 if (err)
2767 return err;
2768
a43b25da 2769 rq->mdev = mdev;
40ab6a6e
AS		 2770
2771 return 0;
2772}
2773
a43b25da 2774static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2775 struct mlx5e_cq *cq,
2776 struct mlx5e_cq_param *param)
40ab6a6e 2777{
95b6c6a5 2778 return mlx5e_alloc_cq_common(mdev, param, cq);
40ab6a6e
AS		 2779}
2780
a43b25da
SM		 2781static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2782 struct mlx5e_rq *drop_rq)
40ab6a6e 2783{
a43b25da
SM		 2784 struct mlx5e_cq_param cq_param = {};
2785 struct mlx5e_rq_param rq_param = {};
2786 struct mlx5e_cq *cq = &drop_rq->cq;
40ab6a6e
AS		 2787 int err;
2788
556dd1b9 2789 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e 2790
a43b25da 2791 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
40ab6a6e
AS		 2792 if (err)
2793 return err;
2794
3b77235b 2795 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 2796 if (err)
3b77235b 2797 goto err_free_cq;
40ab6a6e 2798
a43b25da 2799 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
40ab6a6e 2800 if (err)
3b77235b 2801 goto err_destroy_cq;
40ab6a6e 2802
a43b25da 2803 err = mlx5e_create_rq(drop_rq, &rq_param);
40ab6a6e 2804 if (err)
3b77235b 2805 goto err_free_rq;
40ab6a6e
AS		 2806
2807 return 0;
2808
3b77235b 2809err_free_rq:
a43b25da 2810 mlx5e_free_rq(drop_rq);
40ab6a6e
AS		 2811
2812err_destroy_cq:
a43b25da 2813 mlx5e_destroy_cq(cq);
40ab6a6e 2814
3b77235b 2815err_free_cq:
a43b25da 2816 mlx5e_free_cq(cq);
3b77235b 2817
40ab6a6e
AS		 2818 return err;
2819}
2820
a43b25da 2821static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
40ab6a6e 2822{
a43b25da
SM		 2823 mlx5e_destroy_rq(drop_rq);
2824 mlx5e_free_rq(drop_rq);
2825 mlx5e_destroy_cq(&drop_rq->cq);
2826 mlx5e_free_cq(&drop_rq->cq);
40ab6a6e
AS		 2827}
2828
5426a0b2
SM		 2829int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2830 u32 underlay_qpn, u32 *tisn)
40ab6a6e 2831{
c4f287c4 2832 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2833 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2834
08fb1dac 2835 MLX5_SET(tisc, tisc, prio, tc << 1);
5426a0b2 2836 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
b50d292b 2837 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2838
2839 if (mlx5_lag_is_lacp_owner(mdev))
2840 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2841
5426a0b2 2842 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
40ab6a6e
AS		 2843}
2844
5426a0b2 2845void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
40ab6a6e 2846{
5426a0b2 2847 mlx5_core_destroy_tis(mdev, tisn);
40ab6a6e
AS		 2848}
2849
cb67b832 2850int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2851{
2852 int err;
2853 int tc;
2854
6bfd390b 2855 for (tc = 0; tc < priv->profile->max_tc; tc++) {
5426a0b2 2856 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
40ab6a6e
AS		 2857 if (err)
2858 goto err_close_tises;
2859 }
2860
2861 return 0;
2862
2863err_close_tises:
2864 for (tc--; tc >= 0; tc--)
5426a0b2 2865 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2866
2867 return err;
2868}
2869
cb67b832 2870void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2871{
2872 int tc;
2873
6bfd390b 2874 for (tc = 0; tc < priv->profile->max_tc; tc++)
5426a0b2 2875 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2876}
2877
6a9764ef
SM		 2878static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2879 enum mlx5e_traffic_types tt,
2880 u32 *tirc)
f62b8bb8 2881{
b50d292b 2882 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2883
6a9764ef 2884 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
f62b8bb8 2885
4cbeaff5 2886 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2887 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
7b3722fa 2888 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
f62b8bb8
AV		 2889}
2890
6a9764ef 2891static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
f62b8bb8 2892{
b50d292b 2893 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696 2894
6a9764ef 2895 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
1da36696
TT		 2896
2897 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2898 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2899 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2900}
2901
8f493ffd 2902int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2903{
724b2aa1 2904 struct mlx5e_tir *tir;
f62b8bb8
AV		 2905 void *tirc;
2906 int inlen;
7b3722fa 2907 int i = 0;
f62b8bb8 2908 int err;
1da36696 2909 u32 *in;
1da36696 2910 int tt;
f62b8bb8
AV		 2911
2912 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2913 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2914 if (!in)
2915 return -ENOMEM;
2916
1da36696
TT		 2917 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2918 memset(in, 0, inlen);
724b2aa1 2919 tir = &priv->indir_tir[tt];
1da36696 2920 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2921 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
724b2aa1 2922 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
7b3722fa
GP		 2923 if (err) {
2924 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2925 goto err_destroy_inner_tirs;
2926 }
f62b8bb8
AV		 2927 }
2928
7b3722fa
GP		 2929 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2930 goto out;
2931
2932 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2933 memset(in, 0, inlen);
2934 tir = &priv->inner_indir_tir[i];
2935 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2936 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2937 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2938 if (err) {
2939 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2940 goto err_destroy_inner_tirs;
2941 }
2942 }
2943
2944out:
6bfd390b
HHZ		 2945 kvfree(in);
2946
2947 return 0;
2948
7b3722fa
GP		 2949err_destroy_inner_tirs:
2950 for (i--; i >= 0; i--)
2951 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2952
6bfd390b
HHZ		 2953 for (tt--; tt >= 0; tt--)
2954 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2955
2956 kvfree(in);
2957
2958 return err;
2959}
2960
cb67b832 2961int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2962{
2963 int nch = priv->profile->max_nch(priv->mdev);
2964 struct mlx5e_tir *tir;
2965 void *tirc;
2966 int inlen;
2967 int err;
2968 u32 *in;
2969 int ix;
2970
2971 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2972 in = kvzalloc(inlen, GFP_KERNEL);
6bfd390b
HHZ		 2973 if (!in)
2974 return -ENOMEM;
2975
1da36696
TT		 2976 for (ix = 0; ix < nch; ix++) {
2977 memset(in, 0, inlen);
724b2aa1 2978 tir = &priv->direct_tir[ix];
1da36696 2979 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2980 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
724b2aa1 2981 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2982 if (err)
2983 goto err_destroy_ch_tirs;
2984 }
2985
2986 kvfree(in);
2987
f62b8bb8
AV		 2988 return 0;
2989
1da36696 2990err_destroy_ch_tirs:
8f493ffd 2991 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
1da36696 2992 for (ix--; ix >= 0; ix--)
724b2aa1 2993 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2994
1da36696 2995 kvfree(in);
f62b8bb8
AV		 2996
2997 return err;
2998}
2999
8f493ffd 3000void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 3001{
3002 int i;
3003
1da36696 3004 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 3005 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
7b3722fa
GP		 3006
3007 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3008 return;
3009
3010 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3011 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
f62b8bb8
AV		 3012}
3013
cb67b832 3014void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 3015{
3016 int nch = priv->profile->max_nch(priv->mdev);
3017 int i;
3018
3019 for (i = 0; i < nch; i++)
3020 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3021}
3022
102722fc
GE		 3023static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3024{
3025 int err = 0;
3026 int i;
3027
3028 for (i = 0; i < chs->num; i++) {
3029 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3030 if (err)
3031 return err;
3032 }
3033
3034 return 0;
3035}
3036
f6d96a20 3037static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
36350114
GP		 3038{
3039 int err = 0;
3040 int i;
3041
ff9c852f
SM		 3042 for (i = 0; i < chs->num; i++) {
3043 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
36350114
GP		 3044 if (err)
3045 return err;
3046 }
3047
3048 return 0;
3049}
3050
0cf0f6d3
JP		 3051static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3052 struct tc_mqprio_qopt *mqprio)
08fb1dac
SM		 3053{
3054 struct mlx5e_priv *priv = netdev_priv(netdev);
6f9485af 3055 struct mlx5e_channels new_channels = {};
0cf0f6d3 3056 u8 tc = mqprio->num_tc;
08fb1dac
SM		 3057 int err = 0;
3058
0cf0f6d3
JP		 3059 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3060
08fb1dac
SM		 3061 if (tc && tc != MLX5E_MAX_NUM_TC)
3062 return -EINVAL;
3063
3064 mutex_lock(&priv->state_lock);
3065
6f9485af
SM		 3066 new_channels.params = priv->channels.params;
3067 new_channels.params.num_tc = tc ? tc : 1;
08fb1dac 3068
20b6a1c7 3069 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6f9485af
SM		 3070 priv->channels.params = new_channels.params;
3071 goto out;
3072 }
08fb1dac 3073
6f9485af
SM		 3074 err = mlx5e_open_channels(priv, &new_channels);
3075 if (err)
3076 goto out;
08fb1dac 3077
2e20a151 3078 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
6f9485af 3079out:
08fb1dac 3080 mutex_unlock(&priv->state_lock);
08fb1dac
SM		 3081 return err;
3082}
3083
e80541ec 3084#ifdef CONFIG_MLX5_ESWITCH
d6c862ba 3085static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
0cf0f6d3 3086 struct tc_cls_flower_offload *cls_flower)
08fb1dac 3087{
d6c862ba 3088 if (cls_flower->common.chain_index)
0cf0f6d3 3089 return -EOPNOTSUPP;
e8f887ac 3090
0cf0f6d3
JP		 3091 switch (cls_flower->command) {
3092 case TC_CLSFLOWER_REPLACE:
5fd9fc4e 3093 return mlx5e_configure_flower(priv, cls_flower);
0cf0f6d3
JP		 3094 case TC_CLSFLOWER_DESTROY:
3095 return mlx5e_delete_flower(priv, cls_flower);
3096 case TC_CLSFLOWER_STATS:
3097 return mlx5e_stats_flower(priv, cls_flower);
3098 default:
a5fcf8a6 3099 return -EOPNOTSUPP;
0cf0f6d3
JP		 3100 }
3101}
d6c862ba
JP		 3102
3103int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3104 void *cb_priv)
3105{
3106 struct mlx5e_priv *priv = cb_priv;
3107
44ae12a7
JP		 3108 if (!tc_can_offload(priv->netdev))
3109 return -EOPNOTSUPP;
3110
d6c862ba
JP		 3111 switch (type) {
3112 case TC_SETUP_CLSFLOWER:
3113 return mlx5e_setup_tc_cls_flower(priv, type_data);
3114 default:
3115 return -EOPNOTSUPP;
3116 }
3117}
3118
3119static int mlx5e_setup_tc_block(struct net_device *dev,
3120 struct tc_block_offload *f)
3121{
3122 struct mlx5e_priv *priv = netdev_priv(dev);
3123
3124 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3125 return -EOPNOTSUPP;
3126
3127 switch (f->command) {
3128 case TC_BLOCK_BIND:
3129 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3130 priv, priv);
3131 case TC_BLOCK_UNBIND:
3132 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3133 priv);
3134 return 0;
3135 default:
3136 return -EOPNOTSUPP;
3137 }
3138}
e80541ec 3139#endif
a5fcf8a6 3140
717503b9
JP		 3141int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3142 void *type_data)
0cf0f6d3 3143{
2572ac53 3144 switch (type) {
fde6af47 3145#ifdef CONFIG_MLX5_ESWITCH
d6c862ba
JP		 3146 case TC_SETUP_BLOCK:
3147 return mlx5e_setup_tc_block(dev, type_data);
fde6af47 3148#endif
0cf0f6d3 3149 case TC_SETUP_MQPRIO:
de4784ca 3150 return mlx5e_setup_tc_mqprio(dev, type_data);
e8f887ac
AV		 3151 default:
3152 return -EOPNOTSUPP;
3153 }
08fb1dac
SM		 3154}
3155
bc1f4470 3156static void
f62b8bb8
AV		 3157mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3158{
3159 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 3160 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 3161 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 3162 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 3163
370bad0f
OG		 3164 if (mlx5e_is_uplink_rep(priv)) {
3165 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3166 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3167 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3168 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3169 } else {
3170 stats->rx_packets = sstats->rx_packets;
3171 stats->rx_bytes = sstats->rx_bytes;
3172 stats->tx_packets = sstats->tx_packets;
3173 stats->tx_bytes = sstats->tx_bytes;
3174 stats->tx_dropped = sstats->tx_queue_dropped;
3175 }
269e6b3a
GP		 3176
3177 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 3178
3179 stats->rx_length_errors =
9218b44d
GP		 3180 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3181 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3182 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 3183 stats->rx_crc_errors =
9218b44d
GP		 3184 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3185 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3186 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a
GP		 3187 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3188 stats->rx_frame_errors;
3189 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3190
3191 /* vport multicast also counts packets that are dropped due to steering
3192 * or rx out of buffer
3193 */
9218b44d
GP		 3194 stats->multicast =
3195 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 3196}
3197
3198static void mlx5e_set_rx_mode(struct net_device *dev)
3199{
3200 struct mlx5e_priv *priv = netdev_priv(dev);
3201
7bb29755 3202 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3203}
3204
3205static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3206{
3207 struct mlx5e_priv *priv = netdev_priv(netdev);
3208 struct sockaddr *saddr = addr;
3209
3210 if (!is_valid_ether_addr(saddr->sa_data))
3211 return -EADDRNOTAVAIL;
3212
3213 netif_addr_lock_bh(netdev);
3214 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3215 netif_addr_unlock_bh(netdev);
3216
7bb29755 3217 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3218
3219 return 0;
3220}
3221
0e405443
GP		 3222#define MLX5E_SET_FEATURE(netdev, feature, enable) \
3223 do { \
3224 if (enable) \
3225 netdev->features |= feature; \
3226 else \
3227 netdev->features &= ~feature; \
3228 } while (0)
3229
3230typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3231
3232static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 3233{
3234 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3235 struct mlx5e_channels new_channels = {};
3236 int err = 0;
3237 bool reset;
f62b8bb8
AV		 3238
3239 mutex_lock(&priv->state_lock);
f62b8bb8 3240
2e20a151
SM		 3241 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3242 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3243
2e20a151
SM		 3244 new_channels.params = priv->channels.params;
3245 new_channels.params.lro_en = enable;
3246
3247 if (!reset) {
3248 priv->channels.params = new_channels.params;
3249 err = mlx5e_modify_tirs_lro(priv);
3250 goto out;
98e81b0a 3251 }
f62b8bb8 3252
2e20a151
SM		 3253 err = mlx5e_open_channels(priv, &new_channels);
3254 if (err)
3255 goto out;
0e405443 3256
2e20a151
SM		 3257 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3258out:
9b37b07f 3259 mutex_unlock(&priv->state_lock);
0e405443
GP		 3260 return err;
3261}
3262
3263static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
3264{
3265 struct mlx5e_priv *priv = netdev_priv(netdev);
3266
3267 if (enable)
3268 mlx5e_enable_vlan_filter(priv);
3269 else
3270 mlx5e_disable_vlan_filter(priv);
3271
3272 return 0;
3273}
3274
3275static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3276{
3277 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 3278
0e405443 3279 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 3280 netdev_err(netdev,
3281 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3282 return -EINVAL;
3283 }
3284
0e405443
GP		 3285 return 0;
3286}
3287
94cb1ebb
EBE		 3288static int set_feature_rx_all(struct net_device *netdev, bool enable)
3289{
3290 struct mlx5e_priv *priv = netdev_priv(netdev);
3291 struct mlx5_core_dev *mdev = priv->mdev;
3292
3293 return mlx5_set_port_fcs(mdev, !enable);
3294}
3295
102722fc
GE		 3296static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3297{
3298 struct mlx5e_priv *priv = netdev_priv(netdev);
3299 int err;
3300
3301 mutex_lock(&priv->state_lock);
3302
3303 priv->channels.params.scatter_fcs_en = enable;
3304 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3305 if (err)
3306 priv->channels.params.scatter_fcs_en = !enable;
3307
3308 mutex_unlock(&priv->state_lock);
3309
3310 return err;
3311}
3312
36350114
GP		 3313static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3314{
3315 struct mlx5e_priv *priv = netdev_priv(netdev);
ff9c852f 3316 int err = 0;
36350114
GP		 3317
3318 mutex_lock(&priv->state_lock);
3319
6a9764ef 3320 priv->channels.params.vlan_strip_disable = !enable;
ff9c852f
SM		 3321 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3322 goto unlock;
3323
3324 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
36350114 3325 if (err)
6a9764ef 3326 priv->channels.params.vlan_strip_disable = enable;
36350114 3327
ff9c852f 3328unlock:
36350114
GP		 3329 mutex_unlock(&priv->state_lock);
3330
3331 return err;
3332}
3333
45bf454a
MG		 3334#ifdef CONFIG_RFS_ACCEL
3335static int set_feature_arfs(struct net_device *netdev, bool enable)
3336{
3337 struct mlx5e_priv *priv = netdev_priv(netdev);
3338 int err;
3339
3340 if (enable)
3341 err = mlx5e_arfs_enable(priv);
3342 else
3343 err = mlx5e_arfs_disable(priv);
3344
3345 return err;
3346}
3347#endif
3348
0e405443
GP		 3349static int mlx5e_handle_feature(struct net_device *netdev,
3350 netdev_features_t wanted_features,
3351 netdev_features_t feature,
3352 mlx5e_feature_handler feature_handler)
3353{
3354 netdev_features_t changes = wanted_features ^ netdev->features;
3355 bool enable = !!(wanted_features & feature);
3356 int err;
3357
3358 if (!(changes & feature))
3359 return 0;
3360
3361 err = feature_handler(netdev, enable);
3362 if (err) {
b20eab15
GP		 3363 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3364 enable ? "Enable" : "Disable", &feature, err);
0e405443
GP		 3365 return err;
3366 }
3367
3368 MLX5E_SET_FEATURE(netdev, feature, enable);
3369 return 0;
3370}
3371
3372static int mlx5e_set_features(struct net_device *netdev,
3373 netdev_features_t features)
3374{
3375 int err;
3376
3377 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3378 set_feature_lro);
3379 err |= mlx5e_handle_feature(netdev, features,
3380 NETIF_F_HW_VLAN_CTAG_FILTER,
3381 set_feature_vlan_filter);
3382 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3383 set_feature_tc_num_filters);
94cb1ebb
EBE		 3384 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3385 set_feature_rx_all);
102722fc
GE		 3386 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3387 set_feature_rx_fcs);
36350114
GP		 3388 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3389 set_feature_rx_vlan);
45bf454a
MG		 3390#ifdef CONFIG_RFS_ACCEL
3391 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3392 set_feature_arfs);
3393#endif
0e405443
GP		 3394
3395 return err ? -EINVAL : 0;
f62b8bb8
AV		 3396}
3397
3398static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3399{
3400 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3401 struct mlx5e_channels new_channels = {};
3402 int curr_mtu;
98e81b0a 3403 int err = 0;
506753b0 3404 bool reset;
f62b8bb8 3405
f62b8bb8 3406 mutex_lock(&priv->state_lock);
98e81b0a 3407
6a9764ef
SM		 3408 reset = !priv->channels.params.lro_en &&
3409 (priv->channels.params.rq_wq_type !=
506753b0
TT		 3410 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3411
2e20a151 3412 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3413
2e20a151 3414 curr_mtu = netdev->mtu;
f62b8bb8 3415 netdev->mtu = new_mtu;
98e81b0a 3416
2e20a151
SM		 3417 if (!reset) {
3418 mlx5e_set_dev_port_mtu(priv);
3419 goto out;
3420 }
98e81b0a 3421
2e20a151
SM		 3422 new_channels.params = priv->channels.params;
3423 err = mlx5e_open_channels(priv, &new_channels);
3424 if (err) {
3425 netdev->mtu = curr_mtu;
3426 goto out;
3427 }
3428
3429 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
f62b8bb8 3430
2e20a151
SM		 3431out:
3432 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 3433 return err;
3434}
3435
7c39afb3
FD		 3436int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3437{
3438 struct hwtstamp_config config;
3439 int err;
3440
3441 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3442 return -EOPNOTSUPP;
3443
3444 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3445 return -EFAULT;
3446
3447 /* TX HW timestamp */
3448 switch (config.tx_type) {
3449 case HWTSTAMP_TX_OFF:
3450 case HWTSTAMP_TX_ON:
3451 break;
3452 default:
3453 return -ERANGE;
3454 }
3455
3456 mutex_lock(&priv->state_lock);
3457 /* RX HW timestamp */
3458 switch (config.rx_filter) {
3459 case HWTSTAMP_FILTER_NONE:
3460 /* Reset CQE compression to Admin default */
3461 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3462 break;
3463 case HWTSTAMP_FILTER_ALL:
3464 case HWTSTAMP_FILTER_SOME:
3465 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3466 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3467 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3468 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3469 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3470 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3471 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3472 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3473 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3474 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3475 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3476 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3477 case HWTSTAMP_FILTER_NTP_ALL:
3478 /* Disable CQE compression */
3479 netdev_warn(priv->netdev, "Disabling cqe compression");
3480 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3481 if (err) {
3482 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3483 mutex_unlock(&priv->state_lock);
3484 return err;
3485 }
3486 config.rx_filter = HWTSTAMP_FILTER_ALL;
3487 break;
3488 default:
3489 mutex_unlock(&priv->state_lock);
3490 return -ERANGE;
3491 }
3492
3493 memcpy(&priv->tstamp, &config, sizeof(config));
3494 mutex_unlock(&priv->state_lock);
3495
3496 return copy_to_user(ifr->ifr_data, &config,
3497 sizeof(config)) ? -EFAULT : 0;
3498}
3499
3500int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3501{
3502 struct hwtstamp_config *cfg = &priv->tstamp;
3503
3504 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3505 return -EOPNOTSUPP;
3506
3507 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3508}
3509
ef9814de
EBE		 3510static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3511{
1170fbd8
FD		 3512 struct mlx5e_priv *priv = netdev_priv(dev);
3513
ef9814de
EBE		 3514 switch (cmd) {
3515 case SIOCSHWTSTAMP:
1170fbd8 3516 return mlx5e_hwstamp_set(priv, ifr);
ef9814de 3517 case SIOCGHWTSTAMP:
1170fbd8 3518 return mlx5e_hwstamp_get(priv, ifr);
ef9814de
EBE		 3519 default:
3520 return -EOPNOTSUPP;
3521 }
3522}
3523
e80541ec 3524#ifdef CONFIG_MLX5_ESWITCH
66e49ded
SM		 3525static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3526{
3527 struct mlx5e_priv *priv = netdev_priv(dev);
3528 struct mlx5_core_dev *mdev = priv->mdev;
3529
3530 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3531}
3532
79aab093
MS		 3533static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3534 __be16 vlan_proto)
66e49ded
SM		 3535{
3536 struct mlx5e_priv *priv = netdev_priv(dev);
3537 struct mlx5_core_dev *mdev = priv->mdev;
3538
79aab093
MS		 3539 if (vlan_proto != htons(ETH_P_8021Q))
3540 return -EPROTONOSUPPORT;
3541
66e49ded
SM		 3542 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3543 vlan, qos);
3544}
3545
f942380c
MHY		 3546static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3547{
3548 struct mlx5e_priv *priv = netdev_priv(dev);
3549 struct mlx5_core_dev *mdev = priv->mdev;
3550
3551 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3552}
3553
1edc57e2
MHY		 3554static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3555{
3556 struct mlx5e_priv *priv = netdev_priv(dev);
3557 struct mlx5_core_dev *mdev = priv->mdev;
3558
3559 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3560}
bd77bf1c
MHY		 3561
3562static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3563 int max_tx_rate)
3564{
3565 struct mlx5e_priv *priv = netdev_priv(dev);
3566 struct mlx5_core_dev *mdev = priv->mdev;
3567
bd77bf1c 3568 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3569 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3570}
3571
66e49ded
SM		 3572static int mlx5_vport_link2ifla(u8 esw_link)
3573{
3574 switch (esw_link) {
3575 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3576 return IFLA_VF_LINK_STATE_DISABLE;
3577 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3578 return IFLA_VF_LINK_STATE_ENABLE;
3579 }
3580 return IFLA_VF_LINK_STATE_AUTO;
3581}
3582
3583static int mlx5_ifla_link2vport(u8 ifla_link)
3584{
3585 switch (ifla_link) {
3586 case IFLA_VF_LINK_STATE_DISABLE:
3587 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3588 case IFLA_VF_LINK_STATE_ENABLE:
3589 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3590 }
3591 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3592}
3593
3594static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3595 int link_state)
3596{
3597 struct mlx5e_priv *priv = netdev_priv(dev);
3598 struct mlx5_core_dev *mdev = priv->mdev;
3599
3600 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3601 mlx5_ifla_link2vport(link_state));
3602}
3603
3604static int mlx5e_get_vf_config(struct net_device *dev,
3605 int vf, struct ifla_vf_info *ivi)
3606{
3607 struct mlx5e_priv *priv = netdev_priv(dev);
3608 struct mlx5_core_dev *mdev = priv->mdev;
3609 int err;
3610
3611 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3612 if (err)
3613 return err;
3614 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3615 return 0;
3616}
3617
3618static int mlx5e_get_vf_stats(struct net_device *dev,
3619 int vf, struct ifla_vf_stats *vf_stats)
3620{
3621 struct mlx5e_priv *priv = netdev_priv(dev);
3622 struct mlx5_core_dev *mdev = priv->mdev;
3623
3624 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3625 vf_stats);
3626}
e80541ec 3627#endif
66e49ded 3628
1ad9a00a
PB		 3629static void mlx5e_add_vxlan_port(struct net_device *netdev,
3630 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3631{
3632 struct mlx5e_priv *priv = netdev_priv(netdev);
3633
974c3f30
AD		 3634 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3635 return;
3636
b3f63c3d
MF		 3637 if (!mlx5e_vxlan_allowed(priv->mdev))
3638 return;
3639
974c3f30 3640 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3641}
3642
1ad9a00a
PB		 3643static void mlx5e_del_vxlan_port(struct net_device *netdev,
3644 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3645{
3646 struct mlx5e_priv *priv = netdev_priv(netdev);
3647
974c3f30
AD		 3648 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3649 return;
3650
b3f63c3d
MF		 3651 if (!mlx5e_vxlan_allowed(priv->mdev))
3652 return;
3653
974c3f30 3654 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3655}
3656
27299841
GP		 3657static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3658 struct sk_buff *skb,
3659 netdev_features_t features)
b3f63c3d
MF		 3660{
3661 struct udphdr *udph;
27299841
GP		 3662 u8 proto;
3663 u16 port;
b3f63c3d
MF		 3664
3665 switch (vlan_get_protocol(skb)) {
3666 case htons(ETH_P_IP):
3667 proto = ip_hdr(skb)->protocol;
3668 break;
3669 case htons(ETH_P_IPV6):
3670 proto = ipv6_hdr(skb)->nexthdr;
3671 break;
3672 default:
3673 goto out;
3674 }
3675
27299841
GP		 3676 switch (proto) {
3677 case IPPROTO_GRE:
3678 return features;
3679 case IPPROTO_UDP:
b3f63c3d
MF		 3680 udph = udp_hdr(skb);
3681 port = be16_to_cpu(udph->dest);
b3f63c3d 3682
27299841
GP		 3683 /* Verify if UDP port is being offloaded by HW */
3684 if (mlx5e_vxlan_lookup_port(priv, port))
3685 return features;
3686 }
b3f63c3d
MF		 3687
3688out:
3689 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3690 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3691}
3692
3693static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3694 struct net_device *netdev,
3695 netdev_features_t features)
3696{
3697 struct mlx5e_priv *priv = netdev_priv(netdev);
3698
3699 features = vlan_features_check(skb, features);
3700 features = vxlan_features_check(skb, features);
3701
2ac9cfe7
IT		 3702#ifdef CONFIG_MLX5_EN_IPSEC
3703 if (mlx5e_ipsec_feature_check(skb, netdev, features))
3704 return features;
3705#endif
3706
b3f63c3d
MF		 3707 /* Validate if the tunneled packet is being offloaded by HW */
3708 if (skb->encapsulation &&
3709 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
27299841 3710 return mlx5e_tunnel_features_check(priv, skb, features);
b3f63c3d
MF		 3711
3712 return features;
3713}
3714
3947ca18
DJ		 3715static void mlx5e_tx_timeout(struct net_device *dev)
3716{
3717 struct mlx5e_priv *priv = netdev_priv(dev);
3718 bool sched_work = false;
3719 int i;
3720
3721 netdev_err(dev, "TX timeout detected\n");
3722
6a9764ef 3723 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
acc6c595 3724 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3947ca18 3725
2c1ccc99 3726 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3727 continue;
3728 sched_work = true;
c0f1147d 3729 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3947ca18
DJ		 3730 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3731 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3732 }
3733
3734 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3735 schedule_work(&priv->tx_timeout_work);
3736}
3737
86994156
RS		 3738static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3739{
3740 struct mlx5e_priv *priv = netdev_priv(netdev);
3741 struct bpf_prog *old_prog;
3742 int err = 0;
3743 bool reset, was_opened;
3744 int i;
3745
3746 mutex_lock(&priv->state_lock);
3747
3748 if ((netdev->features & NETIF_F_LRO) && prog) {
3749 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3750 err = -EINVAL;
3751 goto unlock;
3752 }
3753
547eede0
IT		 3754 if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3755 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3756 err = -EINVAL;
3757 goto unlock;
3758 }
3759
86994156
RS		 3760 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3761 /* no need for full reset when exchanging programs */
6a9764ef 3762 reset = (!priv->channels.params.xdp_prog || !prog);
86994156
RS		 3763
3764 if (was_opened && reset)
3765 mlx5e_close_locked(netdev);
c54c0629
DB		 3766 if (was_opened && !reset) {
3767 /* num_channels is invariant here, so we can take the
3768 * batched reference right upfront.
3769 */
6a9764ef 3770 prog = bpf_prog_add(prog, priv->channels.num);
c54c0629
DB		 3771 if (IS_ERR(prog)) {
3772 err = PTR_ERR(prog);
3773 goto unlock;
3774 }
3775 }
86994156 3776
c54c0629
DB		 3777 /* exchange programs, extra prog reference we got from caller
3778 * as long as we don't fail from this point onwards.
3779 */
6a9764ef 3780 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
86994156
RS		 3781 if (old_prog)
3782 bpf_prog_put(old_prog);
3783
3784 if (reset) /* change RQ type according to priv->xdp_prog */
6a9764ef 3785 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
86994156
RS		 3786
3787 if (was_opened && reset)
3788 mlx5e_open_locked(netdev);
3789
3790 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3791 goto unlock;
3792
3793 /* exchanging programs w/o reset, we update ref counts on behalf
3794 * of the channels RQs here.
3795 */
ff9c852f
SM		 3796 for (i = 0; i < priv->channels.num; i++) {
3797 struct mlx5e_channel *c = priv->channels.c[i];
86994156 3798
c0f1147d 3799 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3800 napi_synchronize(&c->napi);
3801 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3802
3803 old_prog = xchg(&c->rq.xdp_prog, prog);
3804
c0f1147d 3805 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156 3806 /* napi_schedule in case we have missed anything */
86994156
RS		 3807 napi_schedule(&c->napi);
3808
3809 if (old_prog)
3810 bpf_prog_put(old_prog);
3811 }
3812
3813unlock:
3814 mutex_unlock(&priv->state_lock);
3815 return err;
3816}
3817
821b2e29 3818static u32 mlx5e_xdp_query(struct net_device *dev)
86994156
RS		 3819{
3820 struct mlx5e_priv *priv = netdev_priv(dev);
821b2e29
MKL		 3821 const struct bpf_prog *xdp_prog;
3822 u32 prog_id = 0;
86994156 3823
821b2e29
MKL		 3824 mutex_lock(&priv->state_lock);
3825 xdp_prog = priv->channels.params.xdp_prog;
3826 if (xdp_prog)
3827 prog_id = xdp_prog->aux->id;
3828 mutex_unlock(&priv->state_lock);
3829
3830 return prog_id;
86994156
RS		 3831}
3832
f4e63525 3833static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
86994156
RS		 3834{
3835 switch (xdp->command) {
3836 case XDP_SETUP_PROG:
3837 return mlx5e_xdp_set(dev, xdp->prog);
3838 case XDP_QUERY_PROG:
821b2e29
MKL		 3839 xdp->prog_id = mlx5e_xdp_query(dev);
3840 xdp->prog_attached = !!xdp->prog_id;
86994156
RS		 3841 return 0;
3842 default:
3843 return -EINVAL;
3844 }
3845}
3846
80378384
CO		 3847#ifdef CONFIG_NET_POLL_CONTROLLER
3848/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3849 * reenabling interrupts.
3850 */
3851static void mlx5e_netpoll(struct net_device *dev)
3852{
3853 struct mlx5e_priv *priv = netdev_priv(dev);
ff9c852f
SM		 3854 struct mlx5e_channels *chs = &priv->channels;
3855
80378384
CO		 3856 int i;
3857
ff9c852f
SM		 3858 for (i = 0; i < chs->num; i++)
3859 napi_schedule(&chs->c[i]->napi);
80378384
CO		 3860}
3861#endif
3862
e80541ec 3863static const struct net_device_ops mlx5e_netdev_ops = {
f62b8bb8
AV		 3864 .ndo_open = mlx5e_open,
3865 .ndo_stop = mlx5e_close,
3866 .ndo_start_xmit = mlx5e_xmit,
0cf0f6d3 3867 .ndo_setup_tc = mlx5e_setup_tc,
08fb1dac 3868 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3869 .ndo_get_stats64 = mlx5e_get_stats,
3870 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3871 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3872 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3873 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3874 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 3875 .ndo_change_mtu = mlx5e_change_mtu,
3876 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3877 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
706b3583
SM		 3878 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3879 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3880 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3881#ifdef CONFIG_RFS_ACCEL
3882 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3883#endif
3947ca18 3884 .ndo_tx_timeout = mlx5e_tx_timeout,
f4e63525 3885 .ndo_bpf = mlx5e_xdp,
80378384
CO		 3886#ifdef CONFIG_NET_POLL_CONTROLLER
3887 .ndo_poll_controller = mlx5e_netpoll,
3888#endif
e80541ec 3889#ifdef CONFIG_MLX5_ESWITCH
706b3583 3890 /* SRIOV E-Switch NDOs */
b0eed40e
SM		 3891 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3892 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3893 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3894 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3895 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3896 .ndo_get_vf_config = mlx5e_get_vf_config,
3897 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3898 .ndo_get_vf_stats = mlx5e_get_vf_stats,
370bad0f
OG		 3899 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3900 .ndo_get_offload_stats = mlx5e_get_offload_stats,
e80541ec 3901#endif
f62b8bb8
AV		 3902};
3903
3904static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3905{
3906 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 3907 return -EOPNOTSUPP;
f62b8bb8
AV		 3908 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3909 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3910 !MLX5_CAP_ETH(mdev, csum_cap) ||
3911 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3912 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3913 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3914 MLX5_CAP_FLOWTABLE(mdev,
3915 flow_table_properties_nic_receive.max_ft_level)
3916 < 3) {
f62b8bb8
AV		 3917 mlx5_core_warn(mdev,
3918 "Not creating net device, some required device capabilities are missing\n");
9eb78923 3919 return -EOPNOTSUPP;
f62b8bb8 3920 }
66189961
TT		 3921 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3922 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8 3923 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3e432ab6 3924 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
66189961 3925
f62b8bb8
AV		 3926 return 0;
3927}
3928
58d52291
AS		 3929u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3930{
3931 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3932
3933 return bf_buf_size -
3934 sizeof(struct mlx5e_tx_wqe) +
3935 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3936}
3937
d4b6c488 3938void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
85082dba
TT		 3939 int num_channels)
3940{
3941 int i;
3942
3943 for (i = 0; i < len; i++)
3944 indirection_rqt[i] = i % num_channels;
3945}
3946
b797a684
SM		 3947static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3948{
3949 enum pcie_link_width width;
3950 enum pci_bus_speed speed;
3951 int err = 0;
3952
3953 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3954 if (err)
3955 return err;
3956
3957 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3958 return -EINVAL;
3959
3960 switch (speed) {
3961 case PCIE_SPEED_2_5GT:
3962 *pci_bw = 2500 * width;
3963 break;
3964 case PCIE_SPEED_5_0GT:
3965 *pci_bw = 5000 * width;
3966 break;
3967 case PCIE_SPEED_8_0GT:
3968 *pci_bw = 8000 * width;
3969 break;
3970 default:
3971 return -EINVAL;
3972 }
3973
3974 return 0;
3975}
3976
3977static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3978{
3979 return (link_speed && pci_bw &&
3980 (pci_bw < 40000) && (pci_bw < link_speed));
3981}
3982
0f6e4cf6
EBE		 3983static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
3984{
3985 return !(link_speed && pci_bw &&
3986 (pci_bw <= 16000) && (pci_bw < link_speed));
3987}
3988
0088cbbc
TG		 3989void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3990{
3991 params->tx_cq_moderation.cq_period_mode = cq_period_mode;
3992
3993 params->tx_cq_moderation.pkts =
3994 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3995 params->tx_cq_moderation.usec =
3996 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3997
3998 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3999 params->tx_cq_moderation.usec =
4000 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4001
4002 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4003 params->tx_cq_moderation.cq_period_mode ==
4004 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4005}
4006
9908aa29
TT		 4007void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4008{
0088cbbc 4009 params->rx_cq_moderation.cq_period_mode = cq_period_mode;
9908aa29
TT		 4010
4011 params->rx_cq_moderation.pkts =
4012 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4013 params->rx_cq_moderation.usec =
0088cbbc 4014 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
9908aa29
TT		 4015
4016 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4017 params->rx_cq_moderation.usec =
4018 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
6a9764ef 4019
457fcd8a
SM		 4020 if (params->rx_am_enabled)
4021 params->rx_cq_moderation =
0088cbbc 4022 mlx5e_am_get_def_profile(cq_period_mode);
457fcd8a 4023
6a9764ef 4024 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
0088cbbc
TG		 4025 params->rx_cq_moderation.cq_period_mode ==
4026 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29
TT		 4027}
4028
2b029556
SM		 4029u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4030{
4031 int i;
4032
4033 /* The supported periods are organized in ascending order */
4034 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4035 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4036 break;
4037
4038 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4039}
4040
8f493ffd
SM		 4041void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4042 struct mlx5e_params *params,
4043 u16 max_channels)
f62b8bb8 4044{
6a9764ef 4045 u8 cq_period_mode = 0;
b797a684
SM		 4046 u32 link_speed = 0;
4047 u32 pci_bw = 0;
2fc4bfb7 4048
6a9764ef
SM		 4049 params->num_channels = max_channels;
4050 params->num_tc = 1;
2b029556 4051
0f6e4cf6
EBE		 4052 mlx5e_get_max_linkspeed(mdev, &link_speed);
4053 mlx5e_get_pci_bw(mdev, &pci_bw);
4054 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
4055 link_speed, pci_bw);
4056
6a9764ef
SM		 4057 /* SQ */
4058 params->log_sq_size = is_kdump_kernel() ?
b4e029da
KH		 4059 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4060 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 4061
b797a684 4062 /* set CQE compression */
6a9764ef 4063 params->rx_cqe_compress_def = false;
b797a684 4064 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
e53eef63 4065 MLX5_CAP_GEN(mdev, vport_group_manager))
6a9764ef 4066 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
0f6e4cf6 4067
6a9764ef
SM		 4068 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4069
4070 /* RQ */
4071 mlx5e_set_rq_params(mdev, params);
b797a684 4072
6a9764ef 4073 /* HW LRO */
c139dbfd 4074
5426a0b2 4075 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
6a9764ef 4076 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
0f6e4cf6 4077 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
6a9764ef 4078 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
b0d4660b 4079
6a9764ef
SM		 4080 /* CQ moderation params */
4081 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4082 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4083 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4084 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4085 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
0088cbbc 4086 mlx5e_set_tx_cq_mode_params(params, cq_period_mode);
9908aa29 4087
6a9764ef
SM		 4088 /* TX inline */
4089 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
fbcb127e 4090 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
a6f402e4 4091
6a9764ef
SM		 4092 /* RSS */
4093 params->rss_hfunc = ETH_RSS_HASH_XOR;
4094 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
d4b6c488 4095 mlx5e_build_default_indir_rqt(params->indirection_rqt,
6a9764ef
SM		 4096 MLX5E_INDIR_RQT_SIZE, max_channels);
4097}
f62b8bb8 4098
6a9764ef
SM		 4099static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4100 struct net_device *netdev,
4101 const struct mlx5e_profile *profile,
4102 void *ppriv)
4103{
4104 struct mlx5e_priv *priv = netdev_priv(netdev);
57afead5 4105
6a9764ef
SM		 4106 priv->mdev = mdev;
4107 priv->netdev = netdev;
4108 priv->profile = profile;
4109 priv->ppriv = ppriv;
79c48764 4110 priv->msglevel = MLX5E_MSG_LEVEL;
c139dbfd 4111 priv->hard_mtu = MLX5E_ETH_HARD_MTU;
2d75b2bc 4112
6a9764ef 4113 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
9908aa29 4114
f62b8bb8
AV		 4115 mutex_init(&priv->state_lock);
4116
4117 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4118 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 4119 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 4120 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4121}
4122
4123static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4124{
4125 struct mlx5e_priv *priv = netdev_priv(netdev);
4126
e1d7d349 4127 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 4128 if (is_zero_ether_addr(netdev->dev_addr) &&
4129 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4130 eth_hw_addr_random(netdev);
4131 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4132 }
f62b8bb8
AV		 4133}
4134
e80541ec 4135#if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
cb67b832
HHZ		 4136static const struct switchdev_ops mlx5e_switchdev_ops = {
4137 .switchdev_port_attr_get = mlx5e_attr_get,
4138};
e80541ec 4139#endif
cb67b832 4140
6bfd390b 4141static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 4142{
4143 struct mlx5e_priv *priv = netdev_priv(netdev);
4144 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 4145 bool fcs_supported;
4146 bool fcs_enabled;
f62b8bb8
AV		 4147
4148 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4149
e80541ec
SM		 4150 netdev->netdev_ops = &mlx5e_netdev_ops;
4151
08fb1dac 4152#ifdef CONFIG_MLX5_CORE_EN_DCB
e80541ec
SM		 4153 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4154 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac 4155#endif
66e49ded 4156
f62b8bb8
AV		 4157 netdev->watchdog_timeo = 15 * HZ;
4158
4159 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4160
12be4b21 4161 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 4162 netdev->vlan_features |= NETIF_F_IP_CSUM;
4163 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4164 netdev->vlan_features |= NETIF_F_GRO;
4165 netdev->vlan_features |= NETIF_F_TSO;
4166 netdev->vlan_features |= NETIF_F_TSO6;
4167 netdev->vlan_features |= NETIF_F_RXCSUM;
4168 netdev->vlan_features |= NETIF_F_RXHASH;
4169
4170 if (!!MLX5_CAP_ETH(mdev, lro_cap))
4171 netdev->vlan_features |= NETIF_F_LRO;
4172
4173 netdev->hw_features = netdev->vlan_features;
e4cf27bd 4174 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 4175 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4176 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4177
27299841
GP		 4178 if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4179 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
b3f63c3d 4180 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 4181 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 4182 netdev->hw_enc_features |= NETIF_F_TSO;
4183 netdev->hw_enc_features |= NETIF_F_TSO6;
27299841
GP		 4184 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4185 }
4186
4187 if (mlx5e_vxlan_allowed(mdev)) {
4188 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4189 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4190 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4191 NETIF_F_GSO_UDP_TUNNEL_CSUM;
b49663c8 4192 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 4193 }
4194
27299841
GP		 4195 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4196 netdev->hw_features |= NETIF_F_GSO_GRE |
4197 NETIF_F_GSO_GRE_CSUM;
4198 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4199 NETIF_F_GSO_GRE_CSUM;
4200 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4201 NETIF_F_GSO_GRE_CSUM;
4202 }
4203
94cb1ebb
EBE		 4204 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4205
4206 if (fcs_supported)
4207 netdev->hw_features |= NETIF_F_RXALL;
4208
102722fc
GE		 4209 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4210 netdev->hw_features |= NETIF_F_RXFCS;
4211
f62b8bb8 4212 netdev->features = netdev->hw_features;
6a9764ef 4213 if (!priv->channels.params.lro_en)
f62b8bb8
AV		 4214 netdev->features &= ~NETIF_F_LRO;
4215
94cb1ebb
EBE		 4216 if (fcs_enabled)
4217 netdev->features &= ~NETIF_F_RXALL;
4218
102722fc
GE		 4219 if (!priv->channels.params.scatter_fcs_en)
4220 netdev->features &= ~NETIF_F_RXFCS;
4221
e8f887ac
AV		 4222#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4223 if (FT_CAP(flow_modify_en) &&
4224 FT_CAP(modify_root) &&
4225 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 4226 FT_CAP(flow_table_modify)) {
4227 netdev->hw_features |= NETIF_F_HW_TC;
4228#ifdef CONFIG_RFS_ACCEL
4229 netdev->hw_features |= NETIF_F_NTUPLE;
4230#endif
4231 }
e8f887ac 4232
f62b8bb8
AV		 4233 netdev->features |= NETIF_F_HIGHDMA;
4234
4235 netdev->priv_flags |= IFF_UNICAST_FLT;
4236
4237 mlx5e_set_netdev_dev_addr(netdev);
cb67b832 4238
e80541ec 4239#if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
a9f7705f 4240 if (MLX5_VPORT_MANAGER(mdev))
cb67b832
HHZ		 4241 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4242#endif
547eede0
IT		 4243
4244 mlx5e_ipsec_build_netdev(priv);
f62b8bb8
AV		 4245}
4246
593cf338
RS		 4247static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4248{
4249 struct mlx5_core_dev *mdev = priv->mdev;
4250 int err;
4251
4252 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4253 if (err) {
4254 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4255 priv->q_counter = 0;
4256 }
4257}
4258
4259static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4260{
4261 if (!priv->q_counter)
4262 return;
4263
4264 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4265}
4266
6bfd390b
HHZ		 4267static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4268 struct net_device *netdev,
127ea380
HHZ		 4269 const struct mlx5e_profile *profile,
4270 void *ppriv)
6bfd390b
HHZ		 4271{
4272 struct mlx5e_priv *priv = netdev_priv(netdev);
547eede0 4273 int err;
6bfd390b 4274
127ea380 4275 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
547eede0
IT		 4276 err = mlx5e_ipsec_init(priv);
4277 if (err)
4278 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
6bfd390b
HHZ		 4279 mlx5e_build_nic_netdev(netdev);
4280 mlx5e_vxlan_init(priv);
4281}
4282
4283static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4284{
547eede0 4285 mlx5e_ipsec_cleanup(priv);
6bfd390b 4286 mlx5e_vxlan_cleanup(priv);
127ea380 4287
6a9764ef
SM		 4288 if (priv->channels.params.xdp_prog)
4289 bpf_prog_put(priv->channels.params.xdp_prog);
6bfd390b
HHZ		 4290}
4291
4292static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4293{
4294 struct mlx5_core_dev *mdev = priv->mdev;
4295 int err;
6bfd390b 4296
8f493ffd
SM		 4297 err = mlx5e_create_indirect_rqt(priv);
4298 if (err)
6bfd390b 4299 return err;
6bfd390b
HHZ		 4300
4301 err = mlx5e_create_direct_rqts(priv);
8f493ffd 4302 if (err)
6bfd390b 4303 goto err_destroy_indirect_rqts;
6bfd390b
HHZ		 4304
4305 err = mlx5e_create_indirect_tirs(priv);
8f493ffd 4306 if (err)
6bfd390b 4307 goto err_destroy_direct_rqts;
6bfd390b
HHZ		 4308
4309 err = mlx5e_create_direct_tirs(priv);
8f493ffd 4310 if (err)
6bfd390b 4311 goto err_destroy_indirect_tirs;
6bfd390b
HHZ		 4312
4313 err = mlx5e_create_flow_steering(priv);
4314 if (err) {
4315 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4316 goto err_destroy_direct_tirs;
4317 }
4318
4319 err = mlx5e_tc_init(priv);
4320 if (err)
4321 goto err_destroy_flow_steering;
4322
4323 return 0;
4324
4325err_destroy_flow_steering:
4326 mlx5e_destroy_flow_steering(priv);
4327err_destroy_direct_tirs:
4328 mlx5e_destroy_direct_tirs(priv);
4329err_destroy_indirect_tirs:
4330 mlx5e_destroy_indirect_tirs(priv);
4331err_destroy_direct_rqts:
8f493ffd 4332 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4333err_destroy_indirect_rqts:
4334 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4335 return err;
4336}
4337
4338static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4339{
6bfd390b
HHZ		 4340 mlx5e_tc_cleanup(priv);
4341 mlx5e_destroy_flow_steering(priv);
4342 mlx5e_destroy_direct_tirs(priv);
4343 mlx5e_destroy_indirect_tirs(priv);
8f493ffd 4344 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4345 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4346}
4347
4348static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4349{
4350 int err;
4351
4352 err = mlx5e_create_tises(priv);
4353 if (err) {
4354 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4355 return err;
4356 }
4357
4358#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 4359 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 4360#endif
4361 return 0;
4362}
4363
4364static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4365{
4366 struct net_device *netdev = priv->netdev;
4367 struct mlx5_core_dev *mdev = priv->mdev;
2c3b5bee
SM		 4368 u16 max_mtu;
4369
4370 mlx5e_init_l2_addr(priv);
4371
63bfd399
EBE		 4372 /* Marking the link as currently not needed by the Driver */
4373 if (!netif_running(netdev))
4374 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4375
2c3b5bee
SM		 4376 /* MTU range: 68 - hw-specific max */
4377 netdev->min_mtu = ETH_MIN_MTU;
4378 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
c139dbfd 4379 netdev->max_mtu = MLX5E_HW2SW_MTU(priv, max_mtu);
2c3b5bee 4380 mlx5e_set_dev_port_mtu(priv);
6bfd390b 4381
7907f23a
AH		 4382 mlx5_lag_add(mdev, netdev);
4383
6bfd390b 4384 mlx5e_enable_async_events(priv);
127ea380 4385
a9f7705f 4386 if (MLX5_VPORT_MANAGER(priv->mdev))
1d447a39 4387 mlx5e_register_vport_reps(priv);
2c3b5bee 4388
610e89e0
SM		 4389 if (netdev->reg_state != NETREG_REGISTERED)
4390 return;
2a5e7a13
HN		 4391#ifdef CONFIG_MLX5_CORE_EN_DCB
4392 mlx5e_dcbnl_init_app(priv);
4393#endif
610e89e0
SM		 4394 /* Device already registered: sync netdev system state */
4395 if (mlx5e_vxlan_allowed(mdev)) {
4396 rtnl_lock();
4397 udp_tunnel_get_rx_info(netdev);
4398 rtnl_unlock();
4399 }
4400
4401 queue_work(priv->wq, &priv->set_rx_mode_work);
2c3b5bee
SM		 4402
4403 rtnl_lock();
4404 if (netif_running(netdev))
4405 mlx5e_open(netdev);
4406 netif_device_attach(netdev);
4407 rtnl_unlock();
6bfd390b
HHZ		 4408}
4409
4410static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4411{
3deef8ce 4412 struct mlx5_core_dev *mdev = priv->mdev;
3deef8ce 4413
2a5e7a13
HN		 4414#ifdef CONFIG_MLX5_CORE_EN_DCB
4415 if (priv->netdev->reg_state == NETREG_REGISTERED)
4416 mlx5e_dcbnl_delete_app(priv);
4417#endif
4418
2c3b5bee
SM		 4419 rtnl_lock();
4420 if (netif_running(priv->netdev))
4421 mlx5e_close(priv->netdev);
4422 netif_device_detach(priv->netdev);
4423 rtnl_unlock();
4424
6bfd390b 4425 queue_work(priv->wq, &priv->set_rx_mode_work);
1d447a39 4426
a9f7705f 4427 if (MLX5_VPORT_MANAGER(priv->mdev))
1d447a39
SM		 4428 mlx5e_unregister_vport_reps(priv);
4429
6bfd390b 4430 mlx5e_disable_async_events(priv);
3deef8ce 4431 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 4432}
4433
4434static const struct mlx5e_profile mlx5e_nic_profile = {
4435 .init = mlx5e_nic_init,
4436 .cleanup = mlx5e_nic_cleanup,
4437 .init_rx = mlx5e_init_nic_rx,
4438 .cleanup_rx = mlx5e_cleanup_nic_rx,
4439 .init_tx = mlx5e_init_nic_tx,
4440 .cleanup_tx = mlx5e_cleanup_nic_tx,
4441 .enable = mlx5e_nic_enable,
4442 .disable = mlx5e_nic_disable,
3834a5e6 4443 .update_stats = mlx5e_update_ndo_stats,
6bfd390b 4444 .max_nch = mlx5e_get_max_num_channels,
7ca42c80 4445 .update_carrier = mlx5e_update_carrier,
20fd0c19
SM		 4446 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4447 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
6bfd390b
HHZ		 4448 .max_tc = MLX5E_MAX_NUM_TC,
4449};
4450
2c3b5bee
SM		 4451/* mlx5e generic netdev management API (move to en_common.c) */
4452
26e59d80
MHY		 4453struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4454 const struct mlx5e_profile *profile,
4455 void *ppriv)
f62b8bb8 4456{
26e59d80 4457 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 4458 struct net_device *netdev;
4459 struct mlx5e_priv *priv;
f62b8bb8 4460
08fb1dac 4461 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 4462 nch * profile->max_tc,
08fb1dac 4463 nch);
f62b8bb8
AV		 4464 if (!netdev) {
4465 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4466 return NULL;
4467 }
4468
be4891af
SM		 4469#ifdef CONFIG_RFS_ACCEL
4470 netdev->rx_cpu_rmap = mdev->rmap;
4471#endif
4472
127ea380 4473 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 4474
4475 netif_carrier_off(netdev);
4476
4477 priv = netdev_priv(netdev);
4478
7bb29755
MF		 4479 priv->wq = create_singlethread_workqueue("mlx5e");
4480 if (!priv->wq)
26e59d80
MHY		 4481 goto err_cleanup_nic;
4482
4483 return netdev;
4484
4485err_cleanup_nic:
31ac9338
OG		 4486 if (profile->cleanup)
4487 profile->cleanup(priv);
26e59d80
MHY		 4488 free_netdev(netdev);
4489
4490 return NULL;
4491}
4492
2c3b5bee 4493int mlx5e_attach_netdev(struct mlx5e_priv *priv)
26e59d80 4494{
2c3b5bee 4495 struct mlx5_core_dev *mdev = priv->mdev;
26e59d80 4496 const struct mlx5e_profile *profile;
26e59d80
MHY		 4497 int err;
4498
26e59d80
MHY		 4499 profile = priv->profile;
4500 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 4501
6bfd390b
HHZ		 4502 err = profile->init_tx(priv);
4503 if (err)
ec8b9981 4504 goto out;
5c50368f 4505
a43b25da 4506 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
5c50368f
AS		 4507 if (err) {
4508 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 4509 goto err_cleanup_tx;
5c50368f
AS		 4510 }
4511
6bfd390b
HHZ		 4512 err = profile->init_rx(priv);
4513 if (err)
5c50368f 4514 goto err_close_drop_rq;
5c50368f 4515
593cf338
RS		 4516 mlx5e_create_q_counter(priv);
4517
6bfd390b
HHZ		 4518 if (profile->enable)
4519 profile->enable(priv);
f62b8bb8 4520
26e59d80 4521 return 0;
5c50368f
AS		 4522
4523err_close_drop_rq:
a43b25da 4524 mlx5e_close_drop_rq(&priv->drop_rq);
5c50368f 4525
6bfd390b
HHZ		 4526err_cleanup_tx:
4527 profile->cleanup_tx(priv);
5c50368f 4528
26e59d80
MHY		 4529out:
4530 return err;
f62b8bb8
AV		 4531}
4532
2c3b5bee 4533void mlx5e_detach_netdev(struct mlx5e_priv *priv)
26e59d80 4534{
26e59d80
MHY		 4535 const struct mlx5e_profile *profile = priv->profile;
4536
4537 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80 4538
37f304d1
SM		 4539 if (profile->disable)
4540 profile->disable(priv);
4541 flush_workqueue(priv->wq);
4542
26e59d80
MHY		 4543 mlx5e_destroy_q_counter(priv);
4544 profile->cleanup_rx(priv);
a43b25da 4545 mlx5e_close_drop_rq(&priv->drop_rq);
26e59d80 4546 profile->cleanup_tx(priv);
26e59d80
MHY		 4547 cancel_delayed_work_sync(&priv->update_stats_work);
4548}
4549
2c3b5bee
SM		 4550void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4551{
4552 const struct mlx5e_profile *profile = priv->profile;
4553 struct net_device *netdev = priv->netdev;
4554
4555 destroy_workqueue(priv->wq);
4556 if (profile->cleanup)
4557 profile->cleanup(priv);
4558 free_netdev(netdev);
4559}
4560
26e59d80
MHY		 4561/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4562 * hardware contexts and to connect it to the current netdev.
4563 */
4564static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4565{
4566 struct mlx5e_priv *priv = vpriv;
4567 struct net_device *netdev = priv->netdev;
4568 int err;
4569
4570 if (netif_device_present(netdev))
4571 return 0;
4572
4573 err = mlx5e_create_mdev_resources(mdev);
4574 if (err)
4575 return err;
4576
2c3b5bee 4577 err = mlx5e_attach_netdev(priv);
26e59d80
MHY		 4578 if (err) {
4579 mlx5e_destroy_mdev_resources(mdev);
4580 return err;
4581 }
4582
4583 return 0;
4584}
4585
4586static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4587{
4588 struct mlx5e_priv *priv = vpriv;
4589 struct net_device *netdev = priv->netdev;
4590
4591 if (!netif_device_present(netdev))
4592 return;
4593
2c3b5bee 4594 mlx5e_detach_netdev(priv);
26e59d80
MHY		 4595 mlx5e_destroy_mdev_resources(mdev);
4596}
4597
b50d292b
HHZ		 4598static void *mlx5e_add(struct mlx5_core_dev *mdev)
4599{
07c9f1e5
SM		 4600 struct net_device *netdev;
4601 void *rpriv = NULL;
26e59d80 4602 void *priv;
26e59d80 4603 int err;
b50d292b 4604
26e59d80
MHY		 4605 err = mlx5e_check_required_hca_cap(mdev);
4606 if (err)
b50d292b
HHZ		 4607 return NULL;
4608
e80541ec 4609#ifdef CONFIG_MLX5_ESWITCH
a9f7705f 4610 if (MLX5_VPORT_MANAGER(mdev)) {
07c9f1e5 4611 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
1d447a39 4612 if (!rpriv) {
07c9f1e5 4613 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
1d447a39
SM		 4614 return NULL;
4615 }
1d447a39 4616 }
e80541ec 4617#endif
127ea380 4618
1d447a39 4619 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
26e59d80
MHY		 4620 if (!netdev) {
4621 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
07c9f1e5 4622 goto err_free_rpriv;
26e59d80
MHY		 4623 }
4624
4625 priv = netdev_priv(netdev);
4626
4627 err = mlx5e_attach(mdev, priv);
4628 if (err) {
4629 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4630 goto err_destroy_netdev;
4631 }
4632
4633 err = register_netdev(netdev);
4634 if (err) {
4635 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4636 goto err_detach;
b50d292b 4637 }
26e59d80 4638
2a5e7a13
HN		 4639#ifdef CONFIG_MLX5_CORE_EN_DCB
4640 mlx5e_dcbnl_init_app(priv);
4641#endif
26e59d80
MHY		 4642 return priv;
4643
4644err_detach:
4645 mlx5e_detach(mdev, priv);
26e59d80 4646err_destroy_netdev:
2c3b5bee 4647 mlx5e_destroy_netdev(priv);
07c9f1e5 4648err_free_rpriv:
1d447a39 4649 kfree(rpriv);
26e59d80 4650 return NULL;
b50d292b
HHZ		 4651}
4652
b50d292b
HHZ		 4653static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4654{
4655 struct mlx5e_priv *priv = vpriv;
1d447a39 4656 void *ppriv = priv->ppriv;
127ea380 4657
2a5e7a13
HN		 4658#ifdef CONFIG_MLX5_CORE_EN_DCB
4659 mlx5e_dcbnl_delete_app(priv);
4660#endif
5e1e93c7 4661 unregister_netdev(priv->netdev);
26e59d80 4662 mlx5e_detach(mdev, vpriv);
2c3b5bee 4663 mlx5e_destroy_netdev(priv);
1d447a39 4664 kfree(ppriv);
b50d292b
HHZ		 4665}
4666
f62b8bb8
AV		 4667static void *mlx5e_get_netdev(void *vpriv)
4668{
4669 struct mlx5e_priv *priv = vpriv;
4670
4671 return priv->netdev;
4672}
4673
4674static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4675 .add = mlx5e_add,
4676 .remove = mlx5e_remove,
26e59d80
MHY		 4677 .attach = mlx5e_attach,
4678 .detach = mlx5e_detach,
f62b8bb8
AV		 4679 .event = mlx5e_async_event,
4680 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4681 .get_dev = mlx5e_get_netdev,
4682};
4683
4684void mlx5e_init(void)
4685{
2ac9cfe7 4686 mlx5e_ipsec_build_inverse_table();
665bc539 4687 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4688 mlx5_register_interface(&mlx5e_interface);
4689}
4690
4691void mlx5e_cleanup(void)
4692{
4693 mlx5_unregister_interface(&mlx5e_interface);
4694}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git