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IB/mlx5: Enable Eth VFs to query their min-inline value for user-space
[thirdparty/kernel/stable.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
f62b8bb8 38#include "en.h"
e8f887ac 39#include "en_tc.h"
66e49ded 40#include "eswitch.h"
b3f63c3d 41#include "vxlan.h"
f62b8bb8
AV		 42
43struct mlx5e_rq_param {
cb3c7fd4
GR		 44 u32 rqc[MLX5_ST_SZ_DW(rqc)];
45 struct mlx5_wq_param wq;
46 bool am_enabled;
f62b8bb8
AV		 47};
48
49struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
58d52291 52 u16 max_inline;
cff92d7c 53 u8 min_inline_mode;
f10b7cc7 54 enum mlx5e_sq_type type;
f62b8bb8
AV		 55};
56
57struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
9908aa29 61 u8 cq_period_mode;
f62b8bb8
AV		 62};
63
64struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
b5503b99 67 struct mlx5e_sq_param xdp_sq;
d3c9bc27 68 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
d3c9bc27 71 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 72};
73
2fc4bfb7
SM		 74static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75{
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
79}
80
81static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
82{
83 priv->params.rq_wq_type = rq_type;
84 switch (priv->params.rq_wq_type) {
85 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
86 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
9bcc8606
SD		 87 priv->params.mpwqe_log_stride_sz =
88 MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
2fc4bfb7
SM		 89 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
90 MLX5_MPWRQ_LOG_STRIDE_SIZE;
91 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
92 priv->params.mpwqe_log_stride_sz;
93 break;
94 default: /* MLX5_WQ_TYPE_LINKED_LIST */
95 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
96 }
97 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
98 BIT(priv->params.log_rq_size));
99
100 mlx5_core_info(priv->mdev,
101 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
102 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
103 BIT(priv->params.log_rq_size),
104 BIT(priv->params.mpwqe_log_stride_sz),
9bcc8606 105 MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 106}
107
108static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
109{
86994156
RS		 110 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
111 !priv->xdp_prog ?
2fc4bfb7
SM		 112 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
113 MLX5_WQ_TYPE_LINKED_LIST;
114 mlx5e_set_rq_type_params(priv, rq_type);
115}
116
f62b8bb8
AV		 117static void mlx5e_update_carrier(struct mlx5e_priv *priv)
118{
119 struct mlx5_core_dev *mdev = priv->mdev;
120 u8 port_state;
121
122 port_state = mlx5_query_vport_state(mdev,
e7546514 123 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8 124
87424ad5
SD		 125 if (port_state == VPORT_STATE_UP) {
126 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 127 netif_carrier_on(priv->netdev);
87424ad5
SD		 128 } else {
129 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 130 netif_carrier_off(priv->netdev);
87424ad5 131 }
f62b8bb8
AV		 132}
133
134static void mlx5e_update_carrier_work(struct work_struct *work)
135{
136 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
137 update_carrier_work);
138
139 mutex_lock(&priv->state_lock);
140 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
141 mlx5e_update_carrier(priv);
142 mutex_unlock(&priv->state_lock);
143}
144
3947ca18
DJ		 145static void mlx5e_tx_timeout_work(struct work_struct *work)
146{
147 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
148 tx_timeout_work);
149 int err;
150
151 rtnl_lock();
152 mutex_lock(&priv->state_lock);
153 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
154 goto unlock;
155 mlx5e_close_locked(priv->netdev);
156 err = mlx5e_open_locked(priv->netdev);
157 if (err)
158 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
159 err);
160unlock:
161 mutex_unlock(&priv->state_lock);
162 rtnl_unlock();
163}
164
9218b44d 165static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 166{
9218b44d 167 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 168 struct mlx5e_rq_stats *rq_stats;
169 struct mlx5e_sq_stats *sq_stats;
9218b44d 170 u64 tx_offload_none = 0;
f62b8bb8
AV		 171 int i, j;
172
9218b44d 173 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 174 for (i = 0; i < priv->params.num_channels; i++) {
175 rq_stats = &priv->channel[i]->rq.stats;
176
faf4478b
GP		 177 s->rx_packets += rq_stats->packets;
178 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 179 s->rx_lro_packets += rq_stats->lro_packets;
180 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 181 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 182 s->rx_csum_complete += rq_stats->csum_complete;
183 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 184 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 185 s->rx_xdp_tx += rq_stats->xdp_tx;
186 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 187 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 188 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 189 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 190 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
191 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
4415a031
TT		 192 s->rx_cache_reuse += rq_stats->cache_reuse;
193 s->rx_cache_full += rq_stats->cache_full;
194 s->rx_cache_empty += rq_stats->cache_empty;
195 s->rx_cache_busy += rq_stats->cache_busy;
f62b8bb8 196
a4418a6c 197 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 198 sq_stats = &priv->channel[i]->sq[j].stats;
199
faf4478b
GP		 200 s->tx_packets += sq_stats->packets;
201 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 202 s->tx_tso_packets += sq_stats->tso_packets;
203 s->tx_tso_bytes += sq_stats->tso_bytes;
204 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
205 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 206 s->tx_queue_stopped += sq_stats->stopped;
207 s->tx_queue_wake += sq_stats->wake;
208 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 209 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1
GP		 210 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
211 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 212 }
213 }
214
9218b44d 215 /* Update calculated offload counters */
bfe6d8d1
GP		 216 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
217 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 218
bfe6d8d1 219 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 220 priv->stats.pport.phy_counters,
221 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 222}
223
224static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
225{
226 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
227 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 228 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 229 struct mlx5_core_dev *mdev = priv->mdev;
230
f62b8bb8
AV		 231 MLX5_SET(query_vport_counter_in, in, opcode,
232 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
233 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
234 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
235
236 memset(out, 0, outlen);
9218b44d
GP		 237 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
238}
239
240static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
241{
242 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
243 struct mlx5_core_dev *mdev = priv->mdev;
244 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 245 int prio;
9218b44d
GP		 246 void *out;
247 u32 *in;
248
249 in = mlx5_vzalloc(sz);
250 if (!in)
f62b8bb8
AV		 251 goto free_out;
252
9218b44d 253 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 254
9218b44d
GP		 255 out = pstats->IEEE_802_3_counters;
256 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
257 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 258
9218b44d
GP		 259 out = pstats->RFC_2863_counters;
260 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
261 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
262
263 out = pstats->RFC_2819_counters;
264 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
265 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 266
121fcdc8
GP		 267 out = pstats->phy_counters;
268 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
269 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
270
5db0a4f6
GP		 271 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
272 out = pstats->phy_statistical_counters;
273 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
274 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
275 }
276
cf678570
GP		 277 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
278 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
279 out = pstats->per_prio_counters[prio];
280 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
281 mlx5_core_access_reg(mdev, in, sz, out, sz,
282 MLX5_REG_PPCNT, 0, 0);
283 }
284
f62b8bb8 285free_out:
9218b44d
GP		 286 kvfree(in);
287}
288
289static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
290{
291 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
292
293 if (!priv->q_counter)
294 return;
295
296 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
297 &qcnt->rx_out_of_buffer);
298}
299
0f7f3481
GP		 300static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
301{
302 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
303 struct mlx5_core_dev *mdev = priv->mdev;
304 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
305 void *out;
306 u32 *in;
307
308 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
309 return;
310
311 in = mlx5_vzalloc(sz);
312 if (!in)
313 return;
314
315 out = pcie_stats->pcie_perf_counters;
316 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
317 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
318
319 kvfree(in);
320}
321
9218b44d
GP		 322void mlx5e_update_stats(struct mlx5e_priv *priv)
323{
3dd69e3d 324 mlx5e_update_pcie_counters(priv);
9218b44d 325 mlx5e_update_pport_counters(priv);
3dd69e3d
SM		 326 mlx5e_update_vport_counters(priv);
327 mlx5e_update_q_counter(priv);
121fcdc8 328 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 329}
330
cb67b832 331void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 332{
333 struct delayed_work *dwork = to_delayed_work(work);
334 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
335 update_stats_work);
336 mutex_lock(&priv->state_lock);
337 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 338 priv->profile->update_stats(priv);
7bb29755
MF		 339 queue_delayed_work(priv->wq, dwork,
340 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 341 }
342 mutex_unlock(&priv->state_lock);
343}
344
daa21560
TT		 345static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
346 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 347{
daa21560 348 struct mlx5e_priv *priv = vpriv;
ee7f1220
EE		 349 struct ptp_clock_event ptp_event;
350 struct mlx5_eqe *eqe = NULL;
daa21560 351
e0f46eb9 352 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 353 return;
354
f62b8bb8
AV		 355 switch (event) {
356 case MLX5_DEV_EVENT_PORT_UP:
357 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 358 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 359 break;
ee7f1220
EE		 360 case MLX5_DEV_EVENT_PPS:
361 eqe = (struct mlx5_eqe *)param;
362 ptp_event.type = PTP_CLOCK_EXTTS;
363 ptp_event.index = eqe->data.pps.pin;
364 ptp_event.timestamp =
365 timecounter_cyc2time(&priv->tstamp.clock,
366 be64_to_cpu(eqe->data.pps.time_stamp));
367 mlx5e_pps_event_handler(vpriv, &ptp_event);
368 break;
f62b8bb8
AV		 369 default:
370 break;
371 }
372}
373
f62b8bb8
AV		 374static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
375{
e0f46eb9 376 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 377}
378
379static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
380{
e0f46eb9 381 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 382 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 383}
384
7e426671
TT		 385static inline int mlx5e_get_wqe_mtt_sz(void)
386{
387 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
388 * To avoid copying garbage after the mtt array, we allocate
389 * a little more.
390 */
391 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
392 MLX5_UMR_MTT_ALIGNMENT);
393}
394
395static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
396 struct mlx5e_umr_wqe *wqe, u16 ix)
397{
398 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
399 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
400 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 401 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 402 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
403 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
404
405 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
406 ds_cnt);
407 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
408 cseg->imm = rq->mkey_be;
409
410 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
31616255 411 ucseg->xlt_octowords =
7e426671
TT		 412 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
413 ucseg->bsf_octowords =
414 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
415 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
416
417 dseg->lkey = sq->mkey_be;
418 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
419}
420
421static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
422 struct mlx5e_channel *c)
423{
424 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
425 int mtt_sz = mlx5e_get_wqe_mtt_sz();
426 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
427 int i;
428
21c59685
SM		 429 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
430 GFP_KERNEL, cpu_to_node(c->cpu));
431 if (!rq->mpwqe.info)
7e426671
TT		 432 goto err_out;
433
434 /* We allocate more than mtt_sz as we will align the pointer */
21c59685 435 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
7e426671 436 cpu_to_node(c->cpu));
21c59685 437 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 438 goto err_free_wqe_info;
439
440 for (i = 0; i < wq_sz; i++) {
21c59685 441 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 442
21c59685 443 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 444 MLX5_UMR_ALIGN);
445 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
446 PCI_DMA_TODEVICE);
447 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
448 goto err_unmap_mtts;
449
450 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
451 }
452
453 return 0;
454
455err_unmap_mtts:
456 while (--i >= 0) {
21c59685 457 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 458
459 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
460 PCI_DMA_TODEVICE);
461 }
21c59685 462 kfree(rq->mpwqe.mtt_no_align);
7e426671 463err_free_wqe_info:
21c59685 464 kfree(rq->mpwqe.info);
7e426671
TT		 465
466err_out:
467 return -ENOMEM;
468}
469
470static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
471{
472 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
473 int mtt_sz = mlx5e_get_wqe_mtt_sz();
474 int i;
475
476 for (i = 0; i < wq_sz; i++) {
21c59685 477 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 478
479 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
480 PCI_DMA_TODEVICE);
481 }
21c59685
SM		 482 kfree(rq->mpwqe.mtt_no_align);
483 kfree(rq->mpwqe.info);
7e426671
TT		 484}
485
ec8b9981
TT		 486static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv,
487 u64 npages, u8 page_shift,
488 struct mlx5_core_mkey *umr_mkey)
3608ae77
TT		 489{
490 struct mlx5_core_dev *mdev = priv->mdev;
3608ae77
TT		 491 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
492 void *mkc;
493 u32 *in;
494 int err;
495
ec8b9981
TT		 496 if (!MLX5E_VALID_NUM_MTTS(npages))
497 return -EINVAL;
498
3608ae77
TT		 499 in = mlx5_vzalloc(inlen);
500 if (!in)
501 return -ENOMEM;
502
503 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
504
3608ae77
TT		 505 MLX5_SET(mkc, mkc, free, 1);
506 MLX5_SET(mkc, mkc, umr_en, 1);
507 MLX5_SET(mkc, mkc, lw, 1);
508 MLX5_SET(mkc, mkc, lr, 1);
509 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
510
511 MLX5_SET(mkc, mkc, qpn, 0xffffff);
512 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 513 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 514 MLX5_SET(mkc, mkc, translations_octword_size,
515 MLX5_MTT_OCTW(npages));
ec8b9981 516 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 517
ec8b9981 518 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 519
520 kvfree(in);
521 return err;
522}
523
ec8b9981
TT		 524static int mlx5e_create_rq_umr_mkey(struct mlx5e_rq *rq)
525{
526 struct mlx5e_priv *priv = rq->priv;
527 u64 num_mtts = MLX5E_REQUIRED_MTTS(BIT(priv->params.log_rq_size));
528
529 return mlx5e_create_umr_mkey(priv, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
530}
531
f62b8bb8
AV		 532static int mlx5e_create_rq(struct mlx5e_channel *c,
533 struct mlx5e_rq_param *param,
534 struct mlx5e_rq *rq)
535{
536 struct mlx5e_priv *priv = c->priv;
537 struct mlx5_core_dev *mdev = priv->mdev;
538 void *rqc = param->rqc;
539 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 540 u32 byte_count;
1bfecfca
SM		 541 u32 frag_sz;
542 int npages;
f62b8bb8
AV		 543 int wq_sz;
544 int err;
545 int i;
546
311c7c71
SM		 547 param->wq.db_numa_node = cpu_to_node(c->cpu);
548
f62b8bb8
AV		 549 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
550 &rq->wq_ctrl);
551 if (err)
552 return err;
553
554 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
555
556 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 557
7e426671
TT		 558 rq->wq_type = priv->params.rq_wq_type;
559 rq->pdev = c->pdev;
560 rq->netdev = c->netdev;
561 rq->tstamp = &priv->tstamp;
562 rq->channel = c;
563 rq->ix = c->ix;
564 rq->priv = c->priv;
97bc402d
DB		 565
566 rq->xdp_prog = priv->xdp_prog ? bpf_prog_inc(priv->xdp_prog) : NULL;
567 if (IS_ERR(rq->xdp_prog)) {
568 err = PTR_ERR(rq->xdp_prog);
569 rq->xdp_prog = NULL;
570 goto err_rq_wq_destroy;
571 }
7e426671 572
d8bec2b2 573 if (rq->xdp_prog) {
b5503b99 574 rq->buff.map_dir = DMA_BIDIRECTIONAL;
d8bec2b2
MKL		 575 rq->rx_headroom = XDP_PACKET_HEADROOM;
576 } else {
577 rq->buff.map_dir = DMA_FROM_DEVICE;
578 rq->rx_headroom = MLX5_RX_HEADROOM;
579 }
b5503b99 580
461017cb
TT		 581 switch (priv->params.rq_wq_type) {
582 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476
OG		 583 if (mlx5e_is_vf_vport_rep(priv)) {
584 err = -EINVAL;
585 goto err_rq_wq_destroy;
586 }
587
461017cb
TT		 588 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
589 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 590 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 591
d9d9f156
TT		 592 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
593 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
1bfecfca
SM		 594
595 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
596 byte_count = rq->buff.wqe_sz;
ec8b9981
TT		 597
598 err = mlx5e_create_rq_umr_mkey(rq);
7e426671
TT		 599 if (err)
600 goto err_rq_wq_destroy;
ec8b9981
TT		 601 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
602
603 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
604 if (err)
605 goto err_destroy_umr_mkey;
461017cb
TT		 606 break;
607 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca
SM		 608 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
609 GFP_KERNEL, cpu_to_node(c->cpu));
610 if (!rq->dma_info) {
461017cb
TT		 611 err = -ENOMEM;
612 goto err_rq_wq_destroy;
613 }
1bfecfca 614
f5f82476
OG		 615 if (mlx5e_is_vf_vport_rep(priv))
616 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
617 else
618 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
619
461017cb 620 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 621 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 622
1bfecfca 623 rq->buff.wqe_sz = (priv->params.lro_en) ?
461017cb
TT		 624 priv->params.lro_wqe_sz :
625 MLX5E_SW2HW_MTU(priv->netdev->mtu);
1bfecfca
SM		 626 byte_count = rq->buff.wqe_sz;
627
628 /* calc the required page order */
d8bec2b2 629 frag_sz = rq->rx_headroom +
1bfecfca
SM		 630 byte_count /* packet data */ +
631 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
632 frag_sz = SKB_DATA_ALIGN(frag_sz);
633
634 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
635 rq->buff.page_order = order_base_2(npages);
636
461017cb 637 byte_count |= MLX5_HW_START_PADDING;
7e426671 638 rq->mkey_be = c->mkey_be;
461017cb 639 }
f62b8bb8
AV		 640
641 for (i = 0; i < wq_sz; i++) {
642 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
643
461017cb 644 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 645 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 646 }
647
cb3c7fd4
GR		 648 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
649 rq->am.mode = priv->params.rx_cq_period_mode;
650
4415a031
TT		 651 rq->page_cache.head = 0;
652 rq->page_cache.tail = 0;
653
f62b8bb8
AV		 654 return 0;
655
ec8b9981
TT		 656err_destroy_umr_mkey:
657 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
658
f62b8bb8 659err_rq_wq_destroy:
97bc402d
DB		 660 if (rq->xdp_prog)
661 bpf_prog_put(rq->xdp_prog);
f62b8bb8
AV		 662 mlx5_wq_destroy(&rq->wq_ctrl);
663
664 return err;
665}
666
667static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
668{
4415a031
TT		 669 int i;
670
86994156
RS		 671 if (rq->xdp_prog)
672 bpf_prog_put(rq->xdp_prog);
673
461017cb
TT		 674 switch (rq->wq_type) {
675 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 676 mlx5e_rq_free_mpwqe_info(rq);
ec8b9981 677 mlx5_core_destroy_mkey(rq->priv->mdev, &rq->umr_mkey);
461017cb
TT		 678 break;
679 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca 680 kfree(rq->dma_info);
461017cb
TT		 681 }
682
4415a031
TT		 683 for (i = rq->page_cache.head; i != rq->page_cache.tail;
684 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
685 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
686
687 mlx5e_page_release(rq, dma_info, false);
688 }
f62b8bb8
AV		 689 mlx5_wq_destroy(&rq->wq_ctrl);
690}
691
692static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
693{
50cfa25a 694 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 695 struct mlx5_core_dev *mdev = priv->mdev;
696
697 void *in;
698 void *rqc;
699 void *wq;
700 int inlen;
701 int err;
702
703 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
704 sizeof(u64) * rq->wq_ctrl.buf.npages;
705 in = mlx5_vzalloc(inlen);
706 if (!in)
707 return -ENOMEM;
708
709 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
710 wq = MLX5_ADDR_OF(rqc, rqc, wq);
711
712 memcpy(rqc, param->rqc, sizeof(param->rqc));
713
97de9f31 714 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 715 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
36350114 716 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
f62b8bb8 717 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 718 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 719 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
720
721 mlx5_fill_page_array(&rq->wq_ctrl.buf,
722 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
723
7db22ffb 724 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 725
726 kvfree(in);
727
728 return err;
729}
730
36350114
GP		 731static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
732 int next_state)
f62b8bb8
AV		 733{
734 struct mlx5e_channel *c = rq->channel;
735 struct mlx5e_priv *priv = c->priv;
736 struct mlx5_core_dev *mdev = priv->mdev;
737
738 void *in;
739 void *rqc;
740 int inlen;
741 int err;
742
743 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
744 in = mlx5_vzalloc(inlen);
745 if (!in)
746 return -ENOMEM;
747
748 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
749
750 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
751 MLX5_SET(rqc, rqc, state, next_state);
752
7db22ffb 753 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 754
755 kvfree(in);
756
757 return err;
758}
759
36350114
GP		 760static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
761{
762 struct mlx5e_channel *c = rq->channel;
763 struct mlx5e_priv *priv = c->priv;
764 struct mlx5_core_dev *mdev = priv->mdev;
765
766 void *in;
767 void *rqc;
768 int inlen;
769 int err;
770
771 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
772 in = mlx5_vzalloc(inlen);
773 if (!in)
774 return -ENOMEM;
775
776 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
777
778 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 779 MLX5_SET64(modify_rq_in, in, modify_bitmask,
780 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 781 MLX5_SET(rqc, rqc, vsd, vsd);
782 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
783
784 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
785
786 kvfree(in);
787
788 return err;
789}
790
f62b8bb8
AV		 791static void mlx5e_disable_rq(struct mlx5e_rq *rq)
792{
50cfa25a 793 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 794}
795
796static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
797{
01c196a2 798 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 799 struct mlx5e_channel *c = rq->channel;
800 struct mlx5e_priv *priv = c->priv;
801 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 802
01c196a2 803 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 804 if (wq->cur_sz >= priv->params.min_rx_wqes)
805 return 0;
806
807 msleep(20);
808 }
809
810 return -ETIMEDOUT;
811}
812
f2fde18c
SM		 813static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
814{
815 struct mlx5_wq_ll *wq = &rq->wq;
816 struct mlx5e_rx_wqe *wqe;
817 __be16 wqe_ix_be;
818 u16 wqe_ix;
819
8484f9ed
SM		 820 /* UMR WQE (if in progress) is always at wq->head */
821 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
21c59685 822 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 823
f2fde18c
SM		 824 while (!mlx5_wq_ll_is_empty(wq)) {
825 wqe_ix_be = *wq->tail_next;
826 wqe_ix = be16_to_cpu(wqe_ix_be);
827 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
828 rq->dealloc_wqe(rq, wqe_ix);
829 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
830 &wqe->next.next_wqe_index);
831 }
832}
833
f62b8bb8
AV		 834static int mlx5e_open_rq(struct mlx5e_channel *c,
835 struct mlx5e_rq_param *param,
836 struct mlx5e_rq *rq)
837{
d3c9bc27
TT		 838 struct mlx5e_sq *sq = &c->icosq;
839 u16 pi = sq->pc & sq->wq.sz_m1;
f62b8bb8
AV		 840 int err;
841
842 err = mlx5e_create_rq(c, param, rq);
843 if (err)
844 return err;
845
846 err = mlx5e_enable_rq(rq, param);
847 if (err)
848 goto err_destroy_rq;
849
c0f1147d 850 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
36350114 851 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8
AV		 852 if (err)
853 goto err_disable_rq;
854
cb3c7fd4
GR		 855 if (param->am_enabled)
856 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
857
f10b7cc7
SM		 858 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
859 sq->db.ico_wqe[pi].num_wqebbs = 1;
d3c9bc27 860 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 861
862 return 0;
863
864err_disable_rq:
c0f1147d 865 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8
AV		 866 mlx5e_disable_rq(rq);
867err_destroy_rq:
868 mlx5e_destroy_rq(rq);
869
870 return err;
871}
872
873static void mlx5e_close_rq(struct mlx5e_rq *rq)
874{
c0f1147d 875 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 876 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
cb3c7fd4
GR		 877 cancel_work_sync(&rq->am.work);
878
f62b8bb8 879 mlx5e_disable_rq(rq);
6cd392a0 880 mlx5e_free_rx_descs(rq);
f62b8bb8
AV		 881 mlx5e_destroy_rq(rq);
882}
883
b5503b99
SM		 884static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
885{
886 kfree(sq->db.xdp.di);
887 kfree(sq->db.xdp.wqe_info);
888}
889
890static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
891{
892 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
893
894 sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
895 GFP_KERNEL, numa);
896 sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
897 GFP_KERNEL, numa);
898 if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
899 mlx5e_free_sq_xdp_db(sq);
900 return -ENOMEM;
901 }
902
903 return 0;
904}
905
f10b7cc7 906static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
f62b8bb8 907{
f10b7cc7 908 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 909}
910
f10b7cc7
SM		 911static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
912{
913 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
914
915 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
916 GFP_KERNEL, numa);
917 if (!sq->db.ico_wqe)
918 return -ENOMEM;
919
920 return 0;
921}
922
923static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
924{
925 kfree(sq->db.txq.wqe_info);
926 kfree(sq->db.txq.dma_fifo);
927 kfree(sq->db.txq.skb);
928}
929
930static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
f62b8bb8
AV		 931{
932 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
933 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
934
f10b7cc7
SM		 935 sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
936 GFP_KERNEL, numa);
937 sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
938 GFP_KERNEL, numa);
939 sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
940 GFP_KERNEL, numa);
941 if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
942 mlx5e_free_sq_txq_db(sq);
f62b8bb8
AV		 943 return -ENOMEM;
944 }
945
946 sq->dma_fifo_mask = df_sz - 1;
947
948 return 0;
949}
950
f10b7cc7
SM		 951static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
952{
953 switch (sq->type) {
954 case MLX5E_SQ_TXQ:
955 mlx5e_free_sq_txq_db(sq);
956 break;
957 case MLX5E_SQ_ICO:
958 mlx5e_free_sq_ico_db(sq);
959 break;
b5503b99
SM		 960 case MLX5E_SQ_XDP:
961 mlx5e_free_sq_xdp_db(sq);
962 break;
f10b7cc7
SM		 963 }
964}
965
966static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
967{
968 switch (sq->type) {
969 case MLX5E_SQ_TXQ:
970 return mlx5e_alloc_sq_txq_db(sq, numa);
971 case MLX5E_SQ_ICO:
972 return mlx5e_alloc_sq_ico_db(sq, numa);
b5503b99
SM		 973 case MLX5E_SQ_XDP:
974 return mlx5e_alloc_sq_xdp_db(sq, numa);
f10b7cc7
SM		 975 }
976
977 return 0;
978}
979
b5503b99
SM		 980static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
981{
982 switch (sq_type) {
983 case MLX5E_SQ_ICO:
984 return MLX5E_ICOSQ_MAX_WQEBBS;
985 case MLX5E_SQ_XDP:
986 return MLX5E_XDP_TX_WQEBBS;
987 }
988 return MLX5_SEND_WQE_MAX_WQEBBS;
989}
990
f62b8bb8
AV		 991static int mlx5e_create_sq(struct mlx5e_channel *c,
992 int tc,
993 struct mlx5e_sq_param *param,
994 struct mlx5e_sq *sq)
995{
996 struct mlx5e_priv *priv = c->priv;
997 struct mlx5_core_dev *mdev = priv->mdev;
998
999 void *sqc = param->sqc;
1000 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1001 int err;
1002
f10b7cc7
SM		 1003 sq->type = param->type;
1004 sq->pdev = c->pdev;
1005 sq->tstamp = &priv->tstamp;
1006 sq->mkey_be = c->mkey_be;
1007 sq->channel = c;
1008 sq->tc = tc;
1009
30aa60b3 1010 err = mlx5_alloc_bfreg(mdev, &sq->bfreg, MLX5_CAP_GEN(mdev, bf), false);
f62b8bb8
AV		 1011 if (err)
1012 return err;
1013
311c7c71
SM		 1014 param->wq.db_numa_node = cpu_to_node(c->cpu);
1015
f62b8bb8
AV		 1016 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1017 &sq->wq_ctrl);
1018 if (err)
1019 goto err_unmap_free_uar;
1020
1021 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
30aa60b3 1022 if (sq->bfreg.wc)
0ba42241 1023 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
30aa60b3 1024
f62b8bb8 1025 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 1026 sq->max_inline = param->max_inline;
cff92d7c 1027 sq->min_inline_mode =
34e4e990 1028 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT ?
cff92d7c 1029 param->min_inline_mode : 0;
f62b8bb8 1030
7ec0bb22
DC		 1031 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
1032 if (err)
f62b8bb8
AV		 1033 goto err_sq_wq_destroy;
1034
f10b7cc7 1035 if (sq->type == MLX5E_SQ_TXQ) {
d3c9bc27
TT		 1036 int txq_ix;
1037
1038 txq_ix = c->ix + tc * priv->params.num_channels;
1039 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
1040 priv->txq_to_sq_map[txq_ix] = sq;
1041 }
f62b8bb8 1042
b5503b99 1043 sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
88a85f99 1044 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
f62b8bb8
AV		 1045
1046 return 0;
1047
1048err_sq_wq_destroy:
1049 mlx5_wq_destroy(&sq->wq_ctrl);
1050
1051err_unmap_free_uar:
30aa60b3 1052 mlx5_free_bfreg(mdev, &sq->bfreg);
f62b8bb8
AV		 1053
1054 return err;
1055}
1056
1057static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
1058{
1059 struct mlx5e_channel *c = sq->channel;
1060 struct mlx5e_priv *priv = c->priv;
1061
1062 mlx5e_free_sq_db(sq);
1063 mlx5_wq_destroy(&sq->wq_ctrl);
30aa60b3 1064 mlx5_free_bfreg(priv->mdev, &sq->bfreg);
f62b8bb8
AV		 1065}
1066
1067static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1068{
1069 struct mlx5e_channel *c = sq->channel;
1070 struct mlx5e_priv *priv = c->priv;
1071 struct mlx5_core_dev *mdev = priv->mdev;
1072
1073 void *in;
1074 void *sqc;
1075 void *wq;
1076 int inlen;
1077 int err;
1078
1079 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1080 sizeof(u64) * sq->wq_ctrl.buf.npages;
1081 in = mlx5_vzalloc(inlen);
1082 if (!in)
1083 return -ENOMEM;
1084
1085 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1086 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1087
1088 memcpy(sqc, param->sqc, sizeof(param->sqc));
1089
f10b7cc7
SM		 1090 MLX5_SET(sqc, sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1091 0 : priv->tisn[sq->tc]);
d3c9bc27 1092 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
cff92d7c 1093 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
f62b8bb8 1094 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f10b7cc7 1095 MLX5_SET(sqc, sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
f62b8bb8
AV		 1096
1097 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
30aa60b3 1098 MLX5_SET(wq, wq, uar_page, sq->bfreg.index);
f62b8bb8 1099 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 1100 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1101 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1102
1103 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1104 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1105
7db22ffb 1106 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 1107
1108 kvfree(in);
1109
1110 return err;
1111}
1112
507f0c81
YP		 1113static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1114 int next_state, bool update_rl, int rl_index)
f62b8bb8
AV		 1115{
1116 struct mlx5e_channel *c = sq->channel;
1117 struct mlx5e_priv *priv = c->priv;
1118 struct mlx5_core_dev *mdev = priv->mdev;
1119
1120 void *in;
1121 void *sqc;
1122 int inlen;
1123 int err;
1124
1125 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1126 in = mlx5_vzalloc(inlen);
1127 if (!in)
1128 return -ENOMEM;
1129
1130 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1131
1132 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1133 MLX5_SET(sqc, sqc, state, next_state);
507f0c81
YP		 1134 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1135 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1136 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
1137 }
f62b8bb8 1138
7db22ffb 1139 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 1140
1141 kvfree(in);
1142
1143 return err;
1144}
1145
1146static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1147{
1148 struct mlx5e_channel *c = sq->channel;
1149 struct mlx5e_priv *priv = c->priv;
1150 struct mlx5_core_dev *mdev = priv->mdev;
1151
7db22ffb 1152 mlx5_core_destroy_sq(mdev, sq->sqn);
507f0c81
YP		 1153 if (sq->rate_limit)
1154 mlx5_rl_remove_rate(mdev, sq->rate_limit);
f62b8bb8
AV		 1155}
1156
1157static int mlx5e_open_sq(struct mlx5e_channel *c,
1158 int tc,
1159 struct mlx5e_sq_param *param,
1160 struct mlx5e_sq *sq)
1161{
1162 int err;
1163
1164 err = mlx5e_create_sq(c, tc, param, sq);
1165 if (err)
1166 return err;
1167
1168 err = mlx5e_enable_sq(sq, param);
1169 if (err)
1170 goto err_destroy_sq;
1171
c0f1147d 1172 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
507f0c81
YP		 1173 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1174 false, 0);
f62b8bb8
AV		 1175 if (err)
1176 goto err_disable_sq;
1177
d3c9bc27 1178 if (sq->txq) {
d3c9bc27
TT		 1179 netdev_tx_reset_queue(sq->txq);
1180 netif_tx_start_queue(sq->txq);
1181 }
f62b8bb8
AV		 1182
1183 return 0;
1184
1185err_disable_sq:
c0f1147d 1186 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
f62b8bb8
AV		 1187 mlx5e_disable_sq(sq);
1188err_destroy_sq:
1189 mlx5e_destroy_sq(sq);
1190
1191 return err;
1192}
1193
1194static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1195{
1196 __netif_tx_lock_bh(txq);
1197 netif_tx_stop_queue(txq);
1198 __netif_tx_unlock_bh(txq);
1199}
1200
1201static void mlx5e_close_sq(struct mlx5e_sq *sq)
1202{
c0f1147d 1203 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6
SM		 1204 /* prevent netif_tx_wake_queue */
1205 napi_synchronize(&sq->channel->napi);
29429f33 1206
d3c9bc27 1207 if (sq->txq) {
d3c9bc27 1208 netif_tx_disable_queue(sq->txq);
f62b8bb8 1209
6e8dd6d6 1210 /* last doorbell out, godspeed .. */
f10b7cc7
SM		 1211 if (mlx5e_sq_has_room_for(sq, 1)) {
1212 sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
d3c9bc27 1213 mlx5e_send_nop(sq, true);
f10b7cc7 1214 }
29429f33 1215 }
f62b8bb8 1216
f62b8bb8 1217 mlx5e_disable_sq(sq);
b5503b99 1218 mlx5e_free_sq_descs(sq);
f62b8bb8
AV		 1219 mlx5e_destroy_sq(sq);
1220}
1221
1222static int mlx5e_create_cq(struct mlx5e_channel *c,
1223 struct mlx5e_cq_param *param,
1224 struct mlx5e_cq *cq)
1225{
1226 struct mlx5e_priv *priv = c->priv;
1227 struct mlx5_core_dev *mdev = priv->mdev;
1228 struct mlx5_core_cq *mcq = &cq->mcq;
1229 int eqn_not_used;
0b6e26ce 1230 unsigned int irqn;
f62b8bb8
AV		 1231 int err;
1232 u32 i;
1233
311c7c71
SM		 1234 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1235 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 1236 param->eq_ix = c->ix;
1237
1238 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1239 &cq->wq_ctrl);
1240 if (err)
1241 return err;
1242
1243 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1244
1245 cq->napi = &c->napi;
1246
1247 mcq->cqe_sz = 64;
1248 mcq->set_ci_db = cq->wq_ctrl.db.db;
1249 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1250 *mcq->set_ci_db = 0;
1251 *mcq->arm_db = 0;
1252 mcq->vector = param->eq_ix;
1253 mcq->comp = mlx5e_completion_event;
1254 mcq->event = mlx5e_cq_error_event;
1255 mcq->irqn = irqn;
f62b8bb8
AV		 1256
1257 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1258 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1259
1260 cqe->op_own = 0xf1;
1261 }
1262
1263 cq->channel = c;
50cfa25a 1264 cq->priv = priv;
f62b8bb8
AV		 1265
1266 return 0;
1267}
1268
1269static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1270{
1c1b5228 1271 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1272}
1273
1274static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1275{
50cfa25a 1276 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 1277 struct mlx5_core_dev *mdev = priv->mdev;
1278 struct mlx5_core_cq *mcq = &cq->mcq;
1279
1280 void *in;
1281 void *cqc;
1282 int inlen;
0b6e26ce 1283 unsigned int irqn_not_used;
f62b8bb8
AV		 1284 int eqn;
1285 int err;
1286
1287 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1288 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
f62b8bb8
AV		 1289 in = mlx5_vzalloc(inlen);
1290 if (!in)
1291 return -ENOMEM;
1292
1293 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1294
1295 memcpy(cqc, param->cqc, sizeof(param->cqc));
1296
1c1b5228
TT		 1297 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1298 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1299
1300 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1301
9908aa29 1302 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1303 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1304 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1c1b5228 1305 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1306 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1307 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1308
1309 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1310
1311 kvfree(in);
1312
1313 if (err)
1314 return err;
1315
1316 mlx5e_cq_arm(cq);
1317
1318 return 0;
1319}
1320
1321static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1322{
50cfa25a 1323 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 1324 struct mlx5_core_dev *mdev = priv->mdev;
1325
1326 mlx5_core_destroy_cq(mdev, &cq->mcq);
1327}
1328
1329static int mlx5e_open_cq(struct mlx5e_channel *c,
1330 struct mlx5e_cq_param *param,
1331 struct mlx5e_cq *cq,
9908aa29 1332 struct mlx5e_cq_moder moderation)
f62b8bb8
AV		 1333{
1334 int err;
1335 struct mlx5e_priv *priv = c->priv;
1336 struct mlx5_core_dev *mdev = priv->mdev;
1337
1338 err = mlx5e_create_cq(c, param, cq);
1339 if (err)
1340 return err;
1341
1342 err = mlx5e_enable_cq(cq, param);
1343 if (err)
1344 goto err_destroy_cq;
1345
7524a5d8
GP		 1346 if (MLX5_CAP_GEN(mdev, cq_moderation))
1347 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
9908aa29
TT		 1348 moderation.usec,
1349 moderation.pkts);
f62b8bb8
AV		 1350 return 0;
1351
1352err_destroy_cq:
1353 mlx5e_destroy_cq(cq);
1354
1355 return err;
1356}
1357
1358static void mlx5e_close_cq(struct mlx5e_cq *cq)
1359{
1360 mlx5e_disable_cq(cq);
1361 mlx5e_destroy_cq(cq);
1362}
1363
1364static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1365{
1366 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1367}
1368
1369static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1370 struct mlx5e_channel_param *cparam)
1371{
1372 struct mlx5e_priv *priv = c->priv;
1373 int err;
1374 int tc;
1375
1376 for (tc = 0; tc < c->num_tc; tc++) {
1377 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
9908aa29 1378 priv->params.tx_cq_moderation);
f62b8bb8
AV		 1379 if (err)
1380 goto err_close_tx_cqs;
f62b8bb8
AV		 1381 }
1382
1383 return 0;
1384
1385err_close_tx_cqs:
1386 for (tc--; tc >= 0; tc--)
1387 mlx5e_close_cq(&c->sq[tc].cq);
1388
1389 return err;
1390}
1391
1392static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1393{
1394 int tc;
1395
1396 for (tc = 0; tc < c->num_tc; tc++)
1397 mlx5e_close_cq(&c->sq[tc].cq);
1398}
1399
1400static int mlx5e_open_sqs(struct mlx5e_channel *c,
1401 struct mlx5e_channel_param *cparam)
1402{
1403 int err;
1404 int tc;
1405
1406 for (tc = 0; tc < c->num_tc; tc++) {
1407 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1408 if (err)
1409 goto err_close_sqs;
1410 }
1411
1412 return 0;
1413
1414err_close_sqs:
1415 for (tc--; tc >= 0; tc--)
1416 mlx5e_close_sq(&c->sq[tc]);
1417
1418 return err;
1419}
1420
1421static void mlx5e_close_sqs(struct mlx5e_channel *c)
1422{
1423 int tc;
1424
1425 for (tc = 0; tc < c->num_tc; tc++)
1426 mlx5e_close_sq(&c->sq[tc]);
1427}
1428
5283af89 1429static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 1430{
1431 int i;
1432
6bfd390b 1433 for (i = 0; i < priv->profile->max_tc; i++)
5283af89
RS		 1434 priv->channeltc_to_txq_map[ix][i] =
1435 ix + i * priv->params.num_channels;
03289b88
SM		 1436}
1437
507f0c81
YP		 1438static int mlx5e_set_sq_maxrate(struct net_device *dev,
1439 struct mlx5e_sq *sq, u32 rate)
1440{
1441 struct mlx5e_priv *priv = netdev_priv(dev);
1442 struct mlx5_core_dev *mdev = priv->mdev;
1443 u16 rl_index = 0;
1444 int err;
1445
1446 if (rate == sq->rate_limit)
1447 /* nothing to do */
1448 return 0;
1449
1450 if (sq->rate_limit)
1451 /* remove current rl index to free space to next ones */
1452 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1453
1454 sq->rate_limit = 0;
1455
1456 if (rate) {
1457 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1458 if (err) {
1459 netdev_err(dev, "Failed configuring rate %u: %d\n",
1460 rate, err);
1461 return err;
1462 }
1463 }
1464
1465 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1466 MLX5_SQC_STATE_RDY, true, rl_index);
1467 if (err) {
1468 netdev_err(dev, "Failed configuring rate %u: %d\n",
1469 rate, err);
1470 /* remove the rate from the table */
1471 if (rate)
1472 mlx5_rl_remove_rate(mdev, rate);
1473 return err;
1474 }
1475
1476 sq->rate_limit = rate;
1477 return 0;
1478}
1479
1480static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1481{
1482 struct mlx5e_priv *priv = netdev_priv(dev);
1483 struct mlx5_core_dev *mdev = priv->mdev;
1484 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1485 int err = 0;
1486
1487 if (!mlx5_rl_is_supported(mdev)) {
1488 netdev_err(dev, "Rate limiting is not supported on this device\n");
1489 return -EINVAL;
1490 }
1491
1492 /* rate is given in Mb/sec, HW config is in Kb/sec */
1493 rate = rate << 10;
1494
1495 /* Check whether rate in valid range, 0 is always valid */
1496 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1497 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1498 return -ERANGE;
1499 }
1500
1501 mutex_lock(&priv->state_lock);
1502 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1503 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1504 if (!err)
1505 priv->tx_rates[index] = rate;
1506 mutex_unlock(&priv->state_lock);
1507
1508 return err;
1509}
1510
f62b8bb8
AV		 1511static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1512 struct mlx5e_channel_param *cparam,
1513 struct mlx5e_channel **cp)
1514{
9908aa29 1515 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
f62b8bb8 1516 struct net_device *netdev = priv->netdev;
cb3c7fd4 1517 struct mlx5e_cq_moder rx_cq_profile;
f62b8bb8
AV		 1518 int cpu = mlx5e_get_cpu(priv, ix);
1519 struct mlx5e_channel *c;
507f0c81 1520 struct mlx5e_sq *sq;
f62b8bb8 1521 int err;
507f0c81 1522 int i;
f62b8bb8
AV		 1523
1524 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1525 if (!c)
1526 return -ENOMEM;
1527
1528 c->priv = priv;
1529 c->ix = ix;
1530 c->cpu = cpu;
1531 c->pdev = &priv->mdev->pdev->dev;
1532 c->netdev = priv->netdev;
b50d292b 1533 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
a4418a6c 1534 c->num_tc = priv->params.num_tc;
d7a0ecab 1535 c->xdp = !!priv->xdp_prog;
f62b8bb8 1536
cb3c7fd4
GR		 1537 if (priv->params.rx_am_enabled)
1538 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1539 else
1540 rx_cq_profile = priv->params.rx_cq_moderation;
1541
5283af89 1542 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1543
f62b8bb8
AV		 1544 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1545
9908aa29 1546 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
f62b8bb8
AV		 1547 if (err)
1548 goto err_napi_del;
1549
d3c9bc27
TT		 1550 err = mlx5e_open_tx_cqs(c, cparam);
1551 if (err)
1552 goto err_close_icosq_cq;
1553
f62b8bb8 1554 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
cb3c7fd4 1555 rx_cq_profile);
f62b8bb8
AV		 1556 if (err)
1557 goto err_close_tx_cqs;
f62b8bb8 1558
d7a0ecab
SM		 1559 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1560 err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1561 priv->params.tx_cq_moderation) : 0;
1562 if (err)
1563 goto err_close_rx_cq;
1564
f62b8bb8
AV		 1565 napi_enable(&c->napi);
1566
d3c9bc27 1567 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1568 if (err)
1569 goto err_disable_napi;
1570
d3c9bc27
TT		 1571 err = mlx5e_open_sqs(c, cparam);
1572 if (err)
1573 goto err_close_icosq;
1574
507f0c81
YP		 1575 for (i = 0; i < priv->params.num_tc; i++) {
1576 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1577
1578 if (priv->tx_rates[txq_ix]) {
1579 sq = priv->txq_to_sq_map[txq_ix];
1580 mlx5e_set_sq_maxrate(priv->netdev, sq,
1581 priv->tx_rates[txq_ix]);
1582 }
1583 }
1584
d7a0ecab
SM		 1585 err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0;
1586 if (err)
1587 goto err_close_sqs;
b5503b99 1588
f62b8bb8
AV		 1589 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1590 if (err)
b5503b99 1591 goto err_close_xdp_sq;
f62b8bb8
AV		 1592
1593 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1594 *cp = c;
1595
1596 return 0;
b5503b99 1597err_close_xdp_sq:
d7a0ecab 1598 if (c->xdp)
87dc0255 1599 mlx5e_close_sq(&c->xdp_sq);
f62b8bb8
AV		 1600
1601err_close_sqs:
1602 mlx5e_close_sqs(c);
1603
d3c9bc27
TT		 1604err_close_icosq:
1605 mlx5e_close_sq(&c->icosq);
1606
f62b8bb8
AV		 1607err_disable_napi:
1608 napi_disable(&c->napi);
d7a0ecab
SM		 1609 if (c->xdp)
1610 mlx5e_close_cq(&c->xdp_sq.cq);
1611
1612err_close_rx_cq:
f62b8bb8
AV		 1613 mlx5e_close_cq(&c->rq.cq);
1614
1615err_close_tx_cqs:
1616 mlx5e_close_tx_cqs(c);
1617
d3c9bc27
TT		 1618err_close_icosq_cq:
1619 mlx5e_close_cq(&c->icosq.cq);
1620
f62b8bb8
AV		 1621err_napi_del:
1622 netif_napi_del(&c->napi);
1623 kfree(c);
1624
1625 return err;
1626}
1627
1628static void mlx5e_close_channel(struct mlx5e_channel *c)
1629{
1630 mlx5e_close_rq(&c->rq);
b5503b99
SM		 1631 if (c->xdp)
1632 mlx5e_close_sq(&c->xdp_sq);
f62b8bb8 1633 mlx5e_close_sqs(c);
d3c9bc27 1634 mlx5e_close_sq(&c->icosq);
f62b8bb8 1635 napi_disable(&c->napi);
b5503b99
SM		 1636 if (c->xdp)
1637 mlx5e_close_cq(&c->xdp_sq.cq);
f62b8bb8
AV		 1638 mlx5e_close_cq(&c->rq.cq);
1639 mlx5e_close_tx_cqs(c);
d3c9bc27 1640 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1641 netif_napi_del(&c->napi);
7ae92ae5 1642
f62b8bb8
AV		 1643 kfree(c);
1644}
1645
1646static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1647 struct mlx5e_rq_param *param)
1648{
1649 void *rqc = param->rqc;
1650 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1651
461017cb
TT		 1652 switch (priv->params.rq_wq_type) {
1653 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1654 MLX5_SET(wq, wq, log_wqe_num_of_strides,
d9d9f156 1655 priv->params.mpwqe_log_num_strides - 9);
461017cb 1656 MLX5_SET(wq, wq, log_wqe_stride_size,
d9d9f156 1657 priv->params.mpwqe_log_stride_sz - 6);
461017cb
TT		 1658 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1659 break;
1660 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1661 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1662 }
1663
f62b8bb8
AV		 1664 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1665 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1666 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
b50d292b 1667 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1668 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1669
311c7c71 1670 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8 1671 param->wq.linear = 1;
cb3c7fd4
GR		 1672
1673 param->am_enabled = priv->params.rx_am_enabled;
f62b8bb8
AV		 1674}
1675
556dd1b9
TT		 1676static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1677{
1678 void *rqc = param->rqc;
1679 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1680
1681 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1682 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1683}
1684
d3c9bc27
TT		 1685static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1686 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1687{
1688 void *sqc = param->sqc;
1689 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1690
f62b8bb8 1691 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1692 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1693
311c7c71 1694 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1695}
1696
1697static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1698 struct mlx5e_sq_param *param)
1699{
1700 void *sqc = param->sqc;
1701 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1702
1703 mlx5e_build_sq_param_common(priv, param);
1704 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1705
58d52291 1706 param->max_inline = priv->params.tx_max_inline;
cff92d7c 1707 param->min_inline_mode = priv->params.tx_min_inline_mode;
f10b7cc7 1708 param->type = MLX5E_SQ_TXQ;
f62b8bb8
AV		 1709}
1710
1711static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1712 struct mlx5e_cq_param *param)
1713{
1714 void *cqc = param->cqc;
1715
30aa60b3 1716 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 1717}
1718
1719static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1720 struct mlx5e_cq_param *param)
1721{
1722 void *cqc = param->cqc;
461017cb 1723 u8 log_cq_size;
f62b8bb8 1724
461017cb
TT		 1725 switch (priv->params.rq_wq_type) {
1726 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1727 log_cq_size = priv->params.log_rq_size +
d9d9f156 1728 priv->params.mpwqe_log_num_strides;
461017cb
TT		 1729 break;
1730 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1731 log_cq_size = priv->params.log_rq_size;
1732 }
1733
1734 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
9bcc8606 1735 if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1736 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1737 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1738 }
f62b8bb8
AV		 1739
1740 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1741
1742 param->cq_period_mode = priv->params.rx_cq_period_mode;
f62b8bb8
AV		 1743}
1744
1745static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1746 struct mlx5e_cq_param *param)
1747{
1748 void *cqc = param->cqc;
1749
d3c9bc27 1750 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1751
1752 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1753
1754 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1755}
1756
d3c9bc27
TT		 1757static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1758 struct mlx5e_cq_param *param,
1759 u8 log_wq_size)
1760{
1761 void *cqc = param->cqc;
1762
1763 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1764
1765 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1766
1767 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1768}
1769
1770static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1771 struct mlx5e_sq_param *param,
1772 u8 log_wq_size)
1773{
1774 void *sqc = param->sqc;
1775 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1776
1777 mlx5e_build_sq_param_common(priv, param);
1778
1779 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1780 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27 1781
f10b7cc7 1782 param->type = MLX5E_SQ_ICO;
d3c9bc27
TT		 1783}
1784
b5503b99
SM		 1785static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1786 struct mlx5e_sq_param *param)
1787{
1788 void *sqc = param->sqc;
1789 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1790
1791 mlx5e_build_sq_param_common(priv, param);
1792 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1793
1794 param->max_inline = priv->params.tx_max_inline;
1795 /* FOR XDP SQs will support only L2 inline mode */
1796 param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1797 param->type = MLX5E_SQ_XDP;
1798}
1799
6b87663f 1800static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
f62b8bb8 1801{
bc77b240 1802 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1803
f62b8bb8
AV		 1804 mlx5e_build_rq_param(priv, &cparam->rq);
1805 mlx5e_build_sq_param(priv, &cparam->sq);
b5503b99 1806 mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
d3c9bc27 1807 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1808 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1809 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1810 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1811}
1812
1813static int mlx5e_open_channels(struct mlx5e_priv *priv)
1814{
6b87663f 1815 struct mlx5e_channel_param *cparam;
a4418a6c 1816 int nch = priv->params.num_channels;
03289b88 1817 int err = -ENOMEM;
f62b8bb8
AV		 1818 int i;
1819 int j;
1820
a4418a6c
AS		 1821 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1822 GFP_KERNEL);
03289b88 1823
a4418a6c 1824 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1825 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1826
6b87663f
AB		 1827 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1828
1829 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
03289b88 1830 goto err_free_txq_to_sq_map;
f62b8bb8 1831
6b87663f
AB		 1832 mlx5e_build_channel_param(priv, cparam);
1833
a4418a6c 1834 for (i = 0; i < nch; i++) {
6b87663f 1835 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
f62b8bb8
AV		 1836 if (err)
1837 goto err_close_channels;
1838 }
1839
a4418a6c 1840 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1841 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1842 if (err)
1843 goto err_close_channels;
1844 }
1845
c3b7c5c9
MHY		 1846 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1847 * polling for inactive tx queues.
1848 */
1849 netif_tx_start_all_queues(priv->netdev);
1850
6b87663f 1851 kfree(cparam);
f62b8bb8
AV		 1852 return 0;
1853
1854err_close_channels:
1855 for (i--; i >= 0; i--)
1856 mlx5e_close_channel(priv->channel[i]);
1857
03289b88
SM		 1858err_free_txq_to_sq_map:
1859 kfree(priv->txq_to_sq_map);
f62b8bb8 1860 kfree(priv->channel);
6b87663f 1861 kfree(cparam);
f62b8bb8
AV		 1862
1863 return err;
1864}
1865
1866static void mlx5e_close_channels(struct mlx5e_priv *priv)
1867{
1868 int i;
1869
c3b7c5c9
MHY		 1870 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1871 * polling for inactive tx queues.
1872 */
1873 netif_tx_stop_all_queues(priv->netdev);
1874 netif_tx_disable(priv->netdev);
1875
f62b8bb8
AV		 1876 for (i = 0; i < priv->params.num_channels; i++)
1877 mlx5e_close_channel(priv->channel[i]);
1878
03289b88 1879 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1880 kfree(priv->channel);
1881}
1882
2be6967c
SM		 1883static int mlx5e_rx_hash_fn(int hfunc)
1884{
1885 return (hfunc == ETH_RSS_HASH_TOP) ?
1886 MLX5_RX_HASH_FN_TOEPLITZ :
1887 MLX5_RX_HASH_FN_INVERTED_XOR8;
1888}
1889
1890static int mlx5e_bits_invert(unsigned long a, int size)
1891{
1892 int inv = 0;
1893 int i;
1894
1895 for (i = 0; i < size; i++)
1896 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1897
1898 return inv;
1899}
1900
936896e9
AS		 1901static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1902{
1903 int i;
1904
1905 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1906 int ix = i;
1da36696 1907 u32 rqn;
936896e9
AS		 1908
1909 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1910 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1911
2d75b2bc 1912 ix = priv->params.indirection_rqt[ix];
1da36696
TT		 1913 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1914 priv->channel[ix]->rq.rqn :
1915 priv->drop_rq.rqn;
1916 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
936896e9
AS		 1917 }
1918}
1919
1da36696
TT		 1920static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1921 int ix)
4cbeaff5 1922{
1da36696
TT		 1923 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1924 priv->channel[ix]->rq.rqn :
1925 priv->drop_rq.rqn;
4cbeaff5 1926
1da36696 1927 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
4cbeaff5
AS		 1928}
1929
398f3351
HHZ		 1930static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1931 int ix, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 1932{
1933 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1934 void *rqtc;
1935 int inlen;
1936 int err;
1da36696 1937 u32 *in;
f62b8bb8 1938
f62b8bb8
AV		 1939 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1940 in = mlx5_vzalloc(inlen);
1941 if (!in)
1942 return -ENOMEM;
1943
1944 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1945
1946 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1947 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1948
1da36696
TT		 1949 if (sz > 1) /* RSS */
1950 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1951 else
1952 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2be6967c 1953
398f3351
HHZ		 1954 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1955 if (!err)
1956 rqt->enabled = true;
f62b8bb8
AV		 1957
1958 kvfree(in);
1da36696
TT		 1959 return err;
1960}
1961
cb67b832 1962void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 1963{
398f3351
HHZ		 1964 rqt->enabled = false;
1965 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 1966}
1967
6bfd390b
HHZ		 1968static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1969{
1970 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1971
1972 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1973}
1974
cb67b832 1975int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 1976{
398f3351 1977 struct mlx5e_rqt *rqt;
1da36696
TT		 1978 int err;
1979 int ix;
1980
6bfd390b 1981 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351
HHZ		 1982 rqt = &priv->direct_tir[ix].rqt;
1983 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1da36696
TT		 1984 if (err)
1985 goto err_destroy_rqts;
1986 }
1987
1988 return 0;
1989
1990err_destroy_rqts:
1991 for (ix--; ix >= 0; ix--)
398f3351 1992 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 1993
f62b8bb8
AV		 1994 return err;
1995}
1996
1da36696 1997int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
5c50368f
AS		 1998{
1999 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2000 void *rqtc;
2001 int inlen;
1da36696 2002 u32 *in;
5c50368f
AS		 2003 int err;
2004
5c50368f
AS		 2005 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2006 in = mlx5_vzalloc(inlen);
2007 if (!in)
2008 return -ENOMEM;
2009
2010 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2011
2012 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1da36696
TT		 2013 if (sz > 1) /* RSS */
2014 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
2015 else
2016 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
5c50368f
AS		 2017
2018 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2019
1da36696 2020 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2021
2022 kvfree(in);
2023
2024 return err;
2025}
2026
40ab6a6e
AS		 2027static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
2028{
1da36696
TT		 2029 u32 rqtn;
2030 int ix;
2031
398f3351
HHZ		 2032 if (priv->indir_rqt.enabled) {
2033 rqtn = priv->indir_rqt.rqtn;
2034 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
2035 }
2036
1da36696 2037 for (ix = 0; ix < priv->params.num_channels; ix++) {
398f3351
HHZ		 2038 if (!priv->direct_tir[ix].rqt.enabled)
2039 continue;
2040 rqtn = priv->direct_tir[ix].rqt.rqtn;
1da36696
TT		 2041 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
2042 }
40ab6a6e
AS		 2043}
2044
5c50368f
AS		 2045static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
2046{
2047 if (!priv->params.lro_en)
2048 return;
2049
2050#define ROUGH_MAX_L2_L3_HDR_SZ 256
2051
2052 MLX5_SET(tirc, tirc, lro_enable_mask,
2053 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2054 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2055 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2056 (priv->params.lro_wqe_sz -
2057 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2b029556 2058 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
5c50368f
AS		 2059}
2060
bdfc028d
TT		 2061void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
2062{
2063 MLX5_SET(tirc, tirc, rx_hash_fn,
2064 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
2065 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
2066 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2067 rx_hash_toeplitz_key);
2068 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2069 rx_hash_toeplitz_key);
2070
2071 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2072 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2073 }
2074}
2075
ab0394fe 2076static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2077{
2078 struct mlx5_core_dev *mdev = priv->mdev;
2079
2080 void *in;
2081 void *tirc;
2082 int inlen;
2083 int err;
ab0394fe 2084 int tt;
1da36696 2085 int ix;
5c50368f
AS		 2086
2087 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2088 in = mlx5_vzalloc(inlen);
2089 if (!in)
2090 return -ENOMEM;
2091
2092 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2093 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2094
2095 mlx5e_build_tir_ctx_lro(tirc, priv);
2096
1da36696 2097 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2098 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2099 inlen);
ab0394fe 2100 if (err)
1da36696 2101 goto free_in;
ab0394fe 2102 }
5c50368f 2103
6bfd390b 2104 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2105 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2106 in, inlen);
2107 if (err)
2108 goto free_in;
2109 }
2110
2111free_in:
5c50368f
AS		 2112 kvfree(in);
2113
2114 return err;
2115}
2116
cd255eff 2117static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2118{
40ab6a6e 2119 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 2120 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 2121 int err;
2122
cd255eff 2123 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2124 if (err)
2125 return err;
2126
cd255eff
SM		 2127 /* Update vport context MTU */
2128 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2129 return 0;
2130}
40ab6a6e 2131
cd255eff
SM		 2132static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2133{
2134 struct mlx5_core_dev *mdev = priv->mdev;
2135 u16 hw_mtu = 0;
2136 int err;
40ab6a6e 2137
cd255eff
SM		 2138 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2139 if (err || !hw_mtu) /* fallback to port oper mtu */
2140 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2141
2142 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2143}
2144
2145static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2146{
2147 struct mlx5e_priv *priv = netdev_priv(netdev);
2148 u16 mtu;
2149 int err;
2150
2151 err = mlx5e_set_mtu(priv, netdev->mtu);
2152 if (err)
2153 return err;
40ab6a6e 2154
cd255eff
SM		 2155 mlx5e_query_mtu(priv, &mtu);
2156 if (mtu != netdev->mtu)
2157 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2158 __func__, mtu, netdev->mtu);
40ab6a6e 2159
cd255eff 2160 netdev->mtu = mtu;
40ab6a6e
AS		 2161 return 0;
2162}
2163
08fb1dac
SM		 2164static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2165{
2166 struct mlx5e_priv *priv = netdev_priv(netdev);
2167 int nch = priv->params.num_channels;
2168 int ntc = priv->params.num_tc;
2169 int tc;
2170
2171 netdev_reset_tc(netdev);
2172
2173 if (ntc == 1)
2174 return;
2175
2176 netdev_set_num_tc(netdev, ntc);
2177
7ccdd084
RS		 2178 /* Map netdev TCs to offset 0
2179 * We have our own UP to TXQ mapping for QoS
2180 */
08fb1dac 2181 for (tc = 0; tc < ntc; tc++)
7ccdd084 2182 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2183}
2184
40ab6a6e
AS		 2185int mlx5e_open_locked(struct net_device *netdev)
2186{
2187 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 2188 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e
AS		 2189 int num_txqs;
2190 int err;
2191
2192 set_bit(MLX5E_STATE_OPENED, &priv->state);
2193
08fb1dac
SM		 2194 mlx5e_netdev_set_tcs(netdev);
2195
40ab6a6e
AS		 2196 num_txqs = priv->params.num_channels * priv->params.num_tc;
2197 netif_set_real_num_tx_queues(netdev, num_txqs);
2198 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2199
40ab6a6e
AS		 2200 err = mlx5e_open_channels(priv);
2201 if (err) {
2202 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2203 __func__, err);
343b29f3 2204 goto err_clear_state_opened_flag;
40ab6a6e
AS		 2205 }
2206
0952da79 2207 err = mlx5e_refresh_tirs_self_loopback(priv->mdev, false);
66189961
TT		 2208 if (err) {
2209 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2210 __func__, err);
2211 goto err_close_channels;
2212 }
2213
40ab6a6e 2214 mlx5e_redirect_rqts(priv);
ce89ef36 2215 mlx5e_update_carrier(priv);
ef9814de 2216 mlx5e_timestamp_init(priv);
5a7b27eb
MG		 2217#ifdef CONFIG_RFS_ACCEL
2218 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2219#endif
cb67b832
HHZ		 2220 if (priv->profile->update_stats)
2221 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2222
cb67b832
HHZ		 2223 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2224 err = mlx5e_add_sqs_fwd_rules(priv);
2225 if (err)
2226 goto err_close_channels;
2227 }
9b37b07f 2228 return 0;
343b29f3 2229
66189961
TT		 2230err_close_channels:
2231 mlx5e_close_channels(priv);
343b29f3
AS		 2232err_clear_state_opened_flag:
2233 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2234 return err;
40ab6a6e
AS		 2235}
2236
cb67b832 2237int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2238{
2239 struct mlx5e_priv *priv = netdev_priv(netdev);
2240 int err;
2241
2242 mutex_lock(&priv->state_lock);
2243 err = mlx5e_open_locked(netdev);
2244 mutex_unlock(&priv->state_lock);
2245
2246 return err;
2247}
2248
2249int mlx5e_close_locked(struct net_device *netdev)
2250{
2251 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 2252 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e 2253
a1985740
AS		 2254 /* May already be CLOSED in case a previous configuration operation
2255 * (e.g RX/TX queue size change) that involves close&open failed.
2256 */
2257 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2258 return 0;
2259
40ab6a6e
AS		 2260 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2261
cb67b832
HHZ		 2262 if (MLX5_CAP_GEN(mdev, vport_group_manager))
2263 mlx5e_remove_sqs_fwd_rules(priv);
2264
ef9814de 2265 mlx5e_timestamp_cleanup(priv);
40ab6a6e 2266 netif_carrier_off(priv->netdev);
ce89ef36 2267 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 2268 mlx5e_close_channels(priv);
2269
2270 return 0;
2271}
2272
cb67b832 2273int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2274{
2275 struct mlx5e_priv *priv = netdev_priv(netdev);
2276 int err;
2277
26e59d80
MHY		 2278 if (!netif_device_present(netdev))
2279 return -ENODEV;
2280
40ab6a6e
AS		 2281 mutex_lock(&priv->state_lock);
2282 err = mlx5e_close_locked(netdev);
2283 mutex_unlock(&priv->state_lock);
2284
2285 return err;
2286}
2287
2288static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2289 struct mlx5e_rq *rq,
2290 struct mlx5e_rq_param *param)
2291{
2292 struct mlx5_core_dev *mdev = priv->mdev;
2293 void *rqc = param->rqc;
2294 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2295 int err;
2296
2297 param->wq.db_numa_node = param->wq.buf_numa_node;
2298
2299 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2300 &rq->wq_ctrl);
2301 if (err)
2302 return err;
2303
2304 rq->priv = priv;
2305
2306 return 0;
2307}
2308
2309static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2310 struct mlx5e_cq *cq,
2311 struct mlx5e_cq_param *param)
2312{
2313 struct mlx5_core_dev *mdev = priv->mdev;
2314 struct mlx5_core_cq *mcq = &cq->mcq;
2315 int eqn_not_used;
0b6e26ce 2316 unsigned int irqn;
40ab6a6e
AS		 2317 int err;
2318
2319 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2320 &cq->wq_ctrl);
2321 if (err)
2322 return err;
2323
2324 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2325
2326 mcq->cqe_sz = 64;
2327 mcq->set_ci_db = cq->wq_ctrl.db.db;
2328 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2329 *mcq->set_ci_db = 0;
2330 *mcq->arm_db = 0;
2331 mcq->vector = param->eq_ix;
2332 mcq->comp = mlx5e_completion_event;
2333 mcq->event = mlx5e_cq_error_event;
2334 mcq->irqn = irqn;
40ab6a6e
AS		 2335
2336 cq->priv = priv;
2337
2338 return 0;
2339}
2340
2341static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2342{
2343 struct mlx5e_cq_param cq_param;
2344 struct mlx5e_rq_param rq_param;
2345 struct mlx5e_rq *rq = &priv->drop_rq;
2346 struct mlx5e_cq *cq = &priv->drop_rq.cq;
2347 int err;
2348
2349 memset(&cq_param, 0, sizeof(cq_param));
2350 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 2351 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 2352
2353 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2354 if (err)
2355 return err;
2356
2357 err = mlx5e_enable_cq(cq, &cq_param);
2358 if (err)
2359 goto err_destroy_cq;
2360
2361 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2362 if (err)
2363 goto err_disable_cq;
2364
2365 err = mlx5e_enable_rq(rq, &rq_param);
2366 if (err)
2367 goto err_destroy_rq;
2368
2369 return 0;
2370
2371err_destroy_rq:
2372 mlx5e_destroy_rq(&priv->drop_rq);
2373
2374err_disable_cq:
2375 mlx5e_disable_cq(&priv->drop_rq.cq);
2376
2377err_destroy_cq:
2378 mlx5e_destroy_cq(&priv->drop_rq.cq);
2379
2380 return err;
2381}
2382
2383static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2384{
2385 mlx5e_disable_rq(&priv->drop_rq);
2386 mlx5e_destroy_rq(&priv->drop_rq);
2387 mlx5e_disable_cq(&priv->drop_rq.cq);
2388 mlx5e_destroy_cq(&priv->drop_rq.cq);
2389}
2390
2391static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2392{
2393 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 2394 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2395 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2396
08fb1dac 2397 MLX5_SET(tisc, tisc, prio, tc << 1);
b50d292b 2398 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2399
2400 if (mlx5_lag_is_lacp_owner(mdev))
2401 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2402
40ab6a6e
AS		 2403 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2404}
2405
2406static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2407{
2408 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2409}
2410
cb67b832 2411int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2412{
2413 int err;
2414 int tc;
2415
6bfd390b 2416 for (tc = 0; tc < priv->profile->max_tc; tc++) {
40ab6a6e
AS		 2417 err = mlx5e_create_tis(priv, tc);
2418 if (err)
2419 goto err_close_tises;
2420 }
2421
2422 return 0;
2423
2424err_close_tises:
2425 for (tc--; tc >= 0; tc--)
2426 mlx5e_destroy_tis(priv, tc);
2427
2428 return err;
2429}
2430
cb67b832 2431void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2432{
2433 int tc;
2434
6bfd390b 2435 for (tc = 0; tc < priv->profile->max_tc; tc++)
40ab6a6e
AS		 2436 mlx5e_destroy_tis(priv, tc);
2437}
2438
1da36696
TT		 2439static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2440 enum mlx5e_traffic_types tt)
f62b8bb8
AV		 2441{
2442 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2443
b50d292b 2444 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2445
5a6f8aef
AS		 2446#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2447 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 2448
5a6f8aef
AS		 2449#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2450 MLX5_HASH_FIELD_SEL_DST_IP |\
2451 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2452 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 2453
a741749f
AS		 2454#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2455 MLX5_HASH_FIELD_SEL_DST_IP |\
2456 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2457
5c50368f 2458 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 2459
4cbeaff5 2460 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2461 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
1da36696 2462 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 2463
2464 switch (tt) {
2465 case MLX5E_TT_IPV4_TCP:
2466 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2467 MLX5_L3_PROT_TYPE_IPV4);
2468 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2469 MLX5_L4_PROT_TYPE_TCP);
2470 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2471 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2472 break;
2473
2474 case MLX5E_TT_IPV6_TCP:
2475 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2476 MLX5_L3_PROT_TYPE_IPV6);
2477 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2478 MLX5_L4_PROT_TYPE_TCP);
2479 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2480 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2481 break;
2482
2483 case MLX5E_TT_IPV4_UDP:
2484 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2485 MLX5_L3_PROT_TYPE_IPV4);
2486 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2487 MLX5_L4_PROT_TYPE_UDP);
2488 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2489 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2490 break;
2491
2492 case MLX5E_TT_IPV6_UDP:
2493 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2494 MLX5_L3_PROT_TYPE_IPV6);
2495 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2496 MLX5_L4_PROT_TYPE_UDP);
2497 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2498 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2499 break;
2500
a741749f
AS		 2501 case MLX5E_TT_IPV4_IPSEC_AH:
2502 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2503 MLX5_L3_PROT_TYPE_IPV4);
2504 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2505 MLX5_HASH_IP_IPSEC_SPI);
2506 break;
2507
2508 case MLX5E_TT_IPV6_IPSEC_AH:
2509 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2510 MLX5_L3_PROT_TYPE_IPV6);
2511 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2512 MLX5_HASH_IP_IPSEC_SPI);
2513 break;
2514
2515 case MLX5E_TT_IPV4_IPSEC_ESP:
2516 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2517 MLX5_L3_PROT_TYPE_IPV4);
2518 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2519 MLX5_HASH_IP_IPSEC_SPI);
2520 break;
2521
2522 case MLX5E_TT_IPV6_IPSEC_ESP:
2523 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2524 MLX5_L3_PROT_TYPE_IPV6);
2525 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2526 MLX5_HASH_IP_IPSEC_SPI);
2527 break;
2528
f62b8bb8
AV		 2529 case MLX5E_TT_IPV4:
2530 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2531 MLX5_L3_PROT_TYPE_IPV4);
2532 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2533 MLX5_HASH_IP);
2534 break;
2535
2536 case MLX5E_TT_IPV6:
2537 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2538 MLX5_L3_PROT_TYPE_IPV6);
2539 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2540 MLX5_HASH_IP);
2541 break;
1da36696
TT		 2542 default:
2543 WARN_ONCE(true,
2544 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
f62b8bb8
AV		 2545 }
2546}
2547
1da36696
TT		 2548static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2549 u32 rqtn)
f62b8bb8 2550{
b50d292b 2551 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696
TT		 2552
2553 mlx5e_build_tir_ctx_lro(tirc, priv);
2554
2555 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2556 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2557 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2558}
2559
6bfd390b 2560static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2561{
724b2aa1 2562 struct mlx5e_tir *tir;
f62b8bb8
AV		 2563 void *tirc;
2564 int inlen;
2565 int err;
1da36696 2566 u32 *in;
1da36696 2567 int tt;
f62b8bb8
AV		 2568
2569 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2570 in = mlx5_vzalloc(inlen);
2571 if (!in)
2572 return -ENOMEM;
2573
1da36696
TT		 2574 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2575 memset(in, 0, inlen);
724b2aa1 2576 tir = &priv->indir_tir[tt];
1da36696
TT		 2577 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2578 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
724b2aa1 2579 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2580 if (err)
40ab6a6e 2581 goto err_destroy_tirs;
f62b8bb8
AV		 2582 }
2583
6bfd390b
HHZ		 2584 kvfree(in);
2585
2586 return 0;
2587
2588err_destroy_tirs:
2589 for (tt--; tt >= 0; tt--)
2590 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2591
2592 kvfree(in);
2593
2594 return err;
2595}
2596
cb67b832 2597int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2598{
2599 int nch = priv->profile->max_nch(priv->mdev);
2600 struct mlx5e_tir *tir;
2601 void *tirc;
2602 int inlen;
2603 int err;
2604 u32 *in;
2605 int ix;
2606
2607 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2608 in = mlx5_vzalloc(inlen);
2609 if (!in)
2610 return -ENOMEM;
2611
1da36696
TT		 2612 for (ix = 0; ix < nch; ix++) {
2613 memset(in, 0, inlen);
724b2aa1 2614 tir = &priv->direct_tir[ix];
1da36696
TT		 2615 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2616 mlx5e_build_direct_tir_ctx(priv, tirc,
398f3351 2617 priv->direct_tir[ix].rqt.rqtn);
724b2aa1 2618 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2619 if (err)
2620 goto err_destroy_ch_tirs;
2621 }
2622
2623 kvfree(in);
2624
f62b8bb8
AV		 2625 return 0;
2626
1da36696
TT		 2627err_destroy_ch_tirs:
2628 for (ix--; ix >= 0; ix--)
724b2aa1 2629 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2630
1da36696 2631 kvfree(in);
f62b8bb8
AV		 2632
2633 return err;
2634}
2635
6bfd390b 2636static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2637{
2638 int i;
2639
1da36696 2640 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2641 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2642}
2643
cb67b832 2644void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2645{
2646 int nch = priv->profile->max_nch(priv->mdev);
2647 int i;
2648
2649 for (i = 0; i < nch; i++)
2650 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2651}
2652
36350114
GP		 2653int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2654{
2655 int err = 0;
2656 int i;
2657
2658 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2659 return 0;
2660
2661 for (i = 0; i < priv->params.num_channels; i++) {
2662 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2663 if (err)
2664 return err;
2665 }
2666
2667 return 0;
2668}
2669
08fb1dac
SM		 2670static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2671{
2672 struct mlx5e_priv *priv = netdev_priv(netdev);
2673 bool was_opened;
2674 int err = 0;
2675
2676 if (tc && tc != MLX5E_MAX_NUM_TC)
2677 return -EINVAL;
2678
2679 mutex_lock(&priv->state_lock);
2680
2681 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2682 if (was_opened)
2683 mlx5e_close_locked(priv->netdev);
2684
2685 priv->params.num_tc = tc ? tc : 1;
2686
2687 if (was_opened)
2688 err = mlx5e_open_locked(priv->netdev);
2689
2690 mutex_unlock(&priv->state_lock);
2691
2692 return err;
2693}
2694
2695static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2696 __be16 proto, struct tc_to_netdev *tc)
2697{
e8f887ac
AV		 2698 struct mlx5e_priv *priv = netdev_priv(dev);
2699
2700 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2701 goto mqprio;
2702
2703 switch (tc->type) {
e3a2b7ed
AV		 2704 case TC_SETUP_CLSFLOWER:
2705 switch (tc->cls_flower->command) {
2706 case TC_CLSFLOWER_REPLACE:
2707 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2708 case TC_CLSFLOWER_DESTROY:
2709 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 2710 case TC_CLSFLOWER_STATS:
2711 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 2712 }
e8f887ac
AV		 2713 default:
2714 return -EOPNOTSUPP;
2715 }
2716
2717mqprio:
67ba422e 2718 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2719 return -EINVAL;
2720
2721 return mlx5e_setup_tc(dev, tc->tc);
2722}
2723
bc1f4470 2724static void
f62b8bb8
AV		 2725mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2726{
2727 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2728 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2729 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2730 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2731
370bad0f
OG		 2732 if (mlx5e_is_uplink_rep(priv)) {
2733 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
2734 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
2735 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
2736 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
2737 } else {
2738 stats->rx_packets = sstats->rx_packets;
2739 stats->rx_bytes = sstats->rx_bytes;
2740 stats->tx_packets = sstats->tx_packets;
2741 stats->tx_bytes = sstats->tx_bytes;
2742 stats->tx_dropped = sstats->tx_queue_dropped;
2743 }
269e6b3a
GP		 2744
2745 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 2746
2747 stats->rx_length_errors =
9218b44d
GP		 2748 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2749 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2750 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2751 stats->rx_crc_errors =
9218b44d
GP		 2752 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2753 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2754 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2755 stats->tx_carrier_errors =
9218b44d 2756 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2757 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2758 stats->rx_frame_errors;
2759 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2760
2761 /* vport multicast also counts packets that are dropped due to steering
2762 * or rx out of buffer
2763 */
9218b44d
GP		 2764 stats->multicast =
2765 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8 2766
f62b8bb8
AV		 2767}
2768
2769static void mlx5e_set_rx_mode(struct net_device *dev)
2770{
2771 struct mlx5e_priv *priv = netdev_priv(dev);
2772
7bb29755 2773 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2774}
2775
2776static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2777{
2778 struct mlx5e_priv *priv = netdev_priv(netdev);
2779 struct sockaddr *saddr = addr;
2780
2781 if (!is_valid_ether_addr(saddr->sa_data))
2782 return -EADDRNOTAVAIL;
2783
2784 netif_addr_lock_bh(netdev);
2785 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2786 netif_addr_unlock_bh(netdev);
2787
7bb29755 2788 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2789
2790 return 0;
2791}
2792
0e405443
GP		 2793#define MLX5E_SET_FEATURE(netdev, feature, enable) \
2794 do { \
2795 if (enable) \
2796 netdev->features |= feature; \
2797 else \
2798 netdev->features &= ~feature; \
2799 } while (0)
2800
2801typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2802
2803static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 2804{
2805 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 2806 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2807 int err;
f62b8bb8
AV		 2808
2809 mutex_lock(&priv->state_lock);
f62b8bb8 2810
0e405443
GP		 2811 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2812 mlx5e_close_locked(priv->netdev);
98e81b0a 2813
0e405443
GP		 2814 priv->params.lro_en = enable;
2815 err = mlx5e_modify_tirs_lro(priv);
2816 if (err) {
2817 netdev_err(netdev, "lro modify failed, %d\n", err);
2818 priv->params.lro_en = !enable;
98e81b0a 2819 }
f62b8bb8 2820
0e405443
GP		 2821 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2822 mlx5e_open_locked(priv->netdev);
2823
9b37b07f
AS		 2824 mutex_unlock(&priv->state_lock);
2825
0e405443
GP		 2826 return err;
2827}
2828
2829static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2830{
2831 struct mlx5e_priv *priv = netdev_priv(netdev);
2832
2833 if (enable)
2834 mlx5e_enable_vlan_filter(priv);
2835 else
2836 mlx5e_disable_vlan_filter(priv);
2837
2838 return 0;
2839}
2840
2841static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2842{
2843 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 2844
0e405443 2845 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 2846 netdev_err(netdev,
2847 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2848 return -EINVAL;
2849 }
2850
0e405443
GP		 2851 return 0;
2852}
2853
94cb1ebb
EBE		 2854static int set_feature_rx_all(struct net_device *netdev, bool enable)
2855{
2856 struct mlx5e_priv *priv = netdev_priv(netdev);
2857 struct mlx5_core_dev *mdev = priv->mdev;
2858
2859 return mlx5_set_port_fcs(mdev, !enable);
2860}
2861
36350114
GP		 2862static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2863{
2864 struct mlx5e_priv *priv = netdev_priv(netdev);
2865 int err;
2866
2867 mutex_lock(&priv->state_lock);
2868
2869 priv->params.vlan_strip_disable = !enable;
2870 err = mlx5e_modify_rqs_vsd(priv, !enable);
2871 if (err)
2872 priv->params.vlan_strip_disable = enable;
2873
2874 mutex_unlock(&priv->state_lock);
2875
2876 return err;
2877}
2878
45bf454a
MG		 2879#ifdef CONFIG_RFS_ACCEL
2880static int set_feature_arfs(struct net_device *netdev, bool enable)
2881{
2882 struct mlx5e_priv *priv = netdev_priv(netdev);
2883 int err;
2884
2885 if (enable)
2886 err = mlx5e_arfs_enable(priv);
2887 else
2888 err = mlx5e_arfs_disable(priv);
2889
2890 return err;
2891}
2892#endif
2893
0e405443
GP		 2894static int mlx5e_handle_feature(struct net_device *netdev,
2895 netdev_features_t wanted_features,
2896 netdev_features_t feature,
2897 mlx5e_feature_handler feature_handler)
2898{
2899 netdev_features_t changes = wanted_features ^ netdev->features;
2900 bool enable = !!(wanted_features & feature);
2901 int err;
2902
2903 if (!(changes & feature))
2904 return 0;
2905
2906 err = feature_handler(netdev, enable);
2907 if (err) {
2908 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2909 enable ? "Enable" : "Disable", feature, err);
2910 return err;
2911 }
2912
2913 MLX5E_SET_FEATURE(netdev, feature, enable);
2914 return 0;
2915}
2916
2917static int mlx5e_set_features(struct net_device *netdev,
2918 netdev_features_t features)
2919{
2920 int err;
2921
2922 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2923 set_feature_lro);
2924 err |= mlx5e_handle_feature(netdev, features,
2925 NETIF_F_HW_VLAN_CTAG_FILTER,
2926 set_feature_vlan_filter);
2927 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2928 set_feature_tc_num_filters);
94cb1ebb
EBE		 2929 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2930 set_feature_rx_all);
36350114
GP		 2931 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2932 set_feature_rx_vlan);
45bf454a
MG		 2933#ifdef CONFIG_RFS_ACCEL
2934 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2935 set_feature_arfs);
2936#endif
0e405443
GP		 2937
2938 return err ? -EINVAL : 0;
f62b8bb8
AV		 2939}
2940
2941static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2942{
2943 struct mlx5e_priv *priv = netdev_priv(netdev);
98e81b0a 2944 bool was_opened;
98e81b0a 2945 int err = 0;
506753b0 2946 bool reset;
f62b8bb8 2947
f62b8bb8 2948 mutex_lock(&priv->state_lock);
98e81b0a 2949
506753b0
TT		 2950 reset = !priv->params.lro_en &&
2951 (priv->params.rq_wq_type !=
2952 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2953
98e81b0a 2954 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
506753b0 2955 if (was_opened && reset)
98e81b0a
AS		 2956 mlx5e_close_locked(netdev);
2957
f62b8bb8 2958 netdev->mtu = new_mtu;
13f9bba7 2959 mlx5e_set_dev_port_mtu(netdev);
98e81b0a 2960
506753b0 2961 if (was_opened && reset)
98e81b0a
AS		 2962 err = mlx5e_open_locked(netdev);
2963
f62b8bb8
AV		 2964 mutex_unlock(&priv->state_lock);
2965
2966 return err;
2967}
2968
ef9814de
EBE		 2969static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2970{
2971 switch (cmd) {
2972 case SIOCSHWTSTAMP:
2973 return mlx5e_hwstamp_set(dev, ifr);
2974 case SIOCGHWTSTAMP:
2975 return mlx5e_hwstamp_get(dev, ifr);
2976 default:
2977 return -EOPNOTSUPP;
2978 }
2979}
2980
66e49ded
SM		 2981static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2982{
2983 struct mlx5e_priv *priv = netdev_priv(dev);
2984 struct mlx5_core_dev *mdev = priv->mdev;
2985
2986 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2987}
2988
79aab093
MS		 2989static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2990 __be16 vlan_proto)
66e49ded
SM		 2991{
2992 struct mlx5e_priv *priv = netdev_priv(dev);
2993 struct mlx5_core_dev *mdev = priv->mdev;
2994
79aab093
MS		 2995 if (vlan_proto != htons(ETH_P_8021Q))
2996 return -EPROTONOSUPPORT;
2997
66e49ded
SM		 2998 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2999 vlan, qos);
3000}
3001
f942380c
MHY		 3002static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3003{
3004 struct mlx5e_priv *priv = netdev_priv(dev);
3005 struct mlx5_core_dev *mdev = priv->mdev;
3006
3007 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3008}
3009
1edc57e2
MHY		 3010static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3011{
3012 struct mlx5e_priv *priv = netdev_priv(dev);
3013 struct mlx5_core_dev *mdev = priv->mdev;
3014
3015 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3016}
bd77bf1c
MHY		 3017
3018static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3019 int max_tx_rate)
3020{
3021 struct mlx5e_priv *priv = netdev_priv(dev);
3022 struct mlx5_core_dev *mdev = priv->mdev;
3023
bd77bf1c 3024 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3025 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3026}
3027
66e49ded
SM		 3028static int mlx5_vport_link2ifla(u8 esw_link)
3029{
3030 switch (esw_link) {
3031 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3032 return IFLA_VF_LINK_STATE_DISABLE;
3033 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3034 return IFLA_VF_LINK_STATE_ENABLE;
3035 }
3036 return IFLA_VF_LINK_STATE_AUTO;
3037}
3038
3039static int mlx5_ifla_link2vport(u8 ifla_link)
3040{
3041 switch (ifla_link) {
3042 case IFLA_VF_LINK_STATE_DISABLE:
3043 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3044 case IFLA_VF_LINK_STATE_ENABLE:
3045 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3046 }
3047 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3048}
3049
3050static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3051 int link_state)
3052{
3053 struct mlx5e_priv *priv = netdev_priv(dev);
3054 struct mlx5_core_dev *mdev = priv->mdev;
3055
3056 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3057 mlx5_ifla_link2vport(link_state));
3058}
3059
3060static int mlx5e_get_vf_config(struct net_device *dev,
3061 int vf, struct ifla_vf_info *ivi)
3062{
3063 struct mlx5e_priv *priv = netdev_priv(dev);
3064 struct mlx5_core_dev *mdev = priv->mdev;
3065 int err;
3066
3067 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3068 if (err)
3069 return err;
3070 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3071 return 0;
3072}
3073
3074static int mlx5e_get_vf_stats(struct net_device *dev,
3075 int vf, struct ifla_vf_stats *vf_stats)
3076{
3077 struct mlx5e_priv *priv = netdev_priv(dev);
3078 struct mlx5_core_dev *mdev = priv->mdev;
3079
3080 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3081 vf_stats);
3082}
3083
4a25730e
HHZ		 3084void mlx5e_add_vxlan_port(struct net_device *netdev,
3085 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3086{
3087 struct mlx5e_priv *priv = netdev_priv(netdev);
3088
974c3f30
AD		 3089 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3090 return;
3091
b3f63c3d
MF		 3092 if (!mlx5e_vxlan_allowed(priv->mdev))
3093 return;
3094
974c3f30 3095 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3096}
3097
4a25730e
HHZ		 3098void mlx5e_del_vxlan_port(struct net_device *netdev,
3099 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3100{
3101 struct mlx5e_priv *priv = netdev_priv(netdev);
3102
974c3f30
AD		 3103 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3104 return;
3105
b3f63c3d
MF		 3106 if (!mlx5e_vxlan_allowed(priv->mdev))
3107 return;
3108
974c3f30 3109 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3110}
3111
3112static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3113 struct sk_buff *skb,
3114 netdev_features_t features)
3115{
3116 struct udphdr *udph;
3117 u16 proto;
3118 u16 port = 0;
3119
3120 switch (vlan_get_protocol(skb)) {
3121 case htons(ETH_P_IP):
3122 proto = ip_hdr(skb)->protocol;
3123 break;
3124 case htons(ETH_P_IPV6):
3125 proto = ipv6_hdr(skb)->nexthdr;
3126 break;
3127 default:
3128 goto out;
3129 }
3130
3131 if (proto == IPPROTO_UDP) {
3132 udph = udp_hdr(skb);
3133 port = be16_to_cpu(udph->dest);
3134 }
3135
3136 /* Verify if UDP port is being offloaded by HW */
3137 if (port && mlx5e_vxlan_lookup_port(priv, port))
3138 return features;
3139
3140out:
3141 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3142 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3143}
3144
3145static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3146 struct net_device *netdev,
3147 netdev_features_t features)
3148{
3149 struct mlx5e_priv *priv = netdev_priv(netdev);
3150
3151 features = vlan_features_check(skb, features);
3152 features = vxlan_features_check(skb, features);
3153
3154 /* Validate if the tunneled packet is being offloaded by HW */
3155 if (skb->encapsulation &&
3156 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3157 return mlx5e_vxlan_features_check(priv, skb, features);
3158
3159 return features;
3160}
3161
3947ca18
DJ		 3162static void mlx5e_tx_timeout(struct net_device *dev)
3163{
3164 struct mlx5e_priv *priv = netdev_priv(dev);
3165 bool sched_work = false;
3166 int i;
3167
3168 netdev_err(dev, "TX timeout detected\n");
3169
3170 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3171 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3172
2c1ccc99 3173 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3174 continue;
3175 sched_work = true;
c0f1147d 3176 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3947ca18
DJ		 3177 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3178 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3179 }
3180
3181 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3182 schedule_work(&priv->tx_timeout_work);
3183}
3184
86994156
RS		 3185static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3186{
3187 struct mlx5e_priv *priv = netdev_priv(netdev);
3188 struct bpf_prog *old_prog;
3189 int err = 0;
3190 bool reset, was_opened;
3191 int i;
3192
3193 mutex_lock(&priv->state_lock);
3194
3195 if ((netdev->features & NETIF_F_LRO) && prog) {
3196 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3197 err = -EINVAL;
3198 goto unlock;
3199 }
3200
3201 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3202 /* no need for full reset when exchanging programs */
3203 reset = (!priv->xdp_prog || !prog);
3204
3205 if (was_opened && reset)
3206 mlx5e_close_locked(netdev);
c54c0629
DB		 3207 if (was_opened && !reset) {
3208 /* num_channels is invariant here, so we can take the
3209 * batched reference right upfront.
3210 */
3211 prog = bpf_prog_add(prog, priv->params.num_channels);
3212 if (IS_ERR(prog)) {
3213 err = PTR_ERR(prog);
3214 goto unlock;
3215 }
3216 }
86994156 3217
c54c0629
DB		 3218 /* exchange programs, extra prog reference we got from caller
3219 * as long as we don't fail from this point onwards.
3220 */
86994156 3221 old_prog = xchg(&priv->xdp_prog, prog);
86994156
RS		 3222 if (old_prog)
3223 bpf_prog_put(old_prog);
3224
3225 if (reset) /* change RQ type according to priv->xdp_prog */
3226 mlx5e_set_rq_priv_params(priv);
3227
3228 if (was_opened && reset)
3229 mlx5e_open_locked(netdev);
3230
3231 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3232 goto unlock;
3233
3234 /* exchanging programs w/o reset, we update ref counts on behalf
3235 * of the channels RQs here.
3236 */
86994156
RS		 3237 for (i = 0; i < priv->params.num_channels; i++) {
3238 struct mlx5e_channel *c = priv->channel[i];
3239
c0f1147d 3240 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3241 napi_synchronize(&c->napi);
3242 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3243
3244 old_prog = xchg(&c->rq.xdp_prog, prog);
3245
c0f1147d 3246 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3247 /* napi_schedule in case we have missed anything */
3248 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3249 napi_schedule(&c->napi);
3250
3251 if (old_prog)
3252 bpf_prog_put(old_prog);
3253 }
3254
3255unlock:
3256 mutex_unlock(&priv->state_lock);
3257 return err;
3258}
3259
3260static bool mlx5e_xdp_attached(struct net_device *dev)
3261{
3262 struct mlx5e_priv *priv = netdev_priv(dev);
3263
3264 return !!priv->xdp_prog;
3265}
3266
3267static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3268{
3269 switch (xdp->command) {
3270 case XDP_SETUP_PROG:
3271 return mlx5e_xdp_set(dev, xdp->prog);
3272 case XDP_QUERY_PROG:
3273 xdp->prog_attached = mlx5e_xdp_attached(dev);
3274 return 0;
3275 default:
3276 return -EINVAL;
3277 }
3278}
3279
80378384
CO		 3280#ifdef CONFIG_NET_POLL_CONTROLLER
3281/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3282 * reenabling interrupts.
3283 */
3284static void mlx5e_netpoll(struct net_device *dev)
3285{
3286 struct mlx5e_priv *priv = netdev_priv(dev);
3287 int i;
3288
3289 for (i = 0; i < priv->params.num_channels; i++)
3290 napi_schedule(&priv->channel[i]->napi);
3291}
3292#endif
3293
b0eed40e 3294static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 3295 .ndo_open = mlx5e_open,
3296 .ndo_stop = mlx5e_close,
3297 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3298 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3299 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3300 .ndo_get_stats64 = mlx5e_get_stats,
3301 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3302 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3303 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3304 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3305 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 3306 .ndo_change_mtu = mlx5e_change_mtu,
3307 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3308 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 3309#ifdef CONFIG_RFS_ACCEL
3310 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3311#endif
3947ca18 3312 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3313 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3314#ifdef CONFIG_NET_POLL_CONTROLLER
3315 .ndo_poll_controller = mlx5e_netpoll,
3316#endif
b0eed40e
SM		 3317};
3318
3319static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3320 .ndo_open = mlx5e_open,
3321 .ndo_stop = mlx5e_close,
3322 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3323 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3324 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 3325 .ndo_get_stats64 = mlx5e_get_stats,
3326 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3327 .ndo_set_mac_address = mlx5e_set_mac,
3328 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3329 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3330 .ndo_set_features = mlx5e_set_features,
3331 .ndo_change_mtu = mlx5e_change_mtu,
3332 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 3333 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3334 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 3335 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 3336 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3337#ifdef CONFIG_RFS_ACCEL
3338 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3339#endif
b0eed40e
SM		 3340 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3341 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3342 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3343 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3344 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3345 .ndo_get_vf_config = mlx5e_get_vf_config,
3346 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3347 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 3348 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3349 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3350#ifdef CONFIG_NET_POLL_CONTROLLER
3351 .ndo_poll_controller = mlx5e_netpoll,
3352#endif
370bad0f
OG		 3353 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3354 .ndo_get_offload_stats = mlx5e_get_offload_stats,
f62b8bb8
AV		 3355};
3356
3357static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3358{
3359 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3360 return -ENOTSUPP;
3361 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3362 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3363 !MLX5_CAP_ETH(mdev, csum_cap) ||
3364 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3365 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3366 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3367 MLX5_CAP_FLOWTABLE(mdev,
3368 flow_table_properties_nic_receive.max_ft_level)
3369 < 3) {
f62b8bb8
AV		 3370 mlx5_core_warn(mdev,
3371 "Not creating net device, some required device capabilities are missing\n");
3372 return -ENOTSUPP;
3373 }
66189961
TT		 3374 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3375 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 3376 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3377 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 3378
f62b8bb8
AV		 3379 return 0;
3380}
3381
58d52291
AS		 3382u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3383{
3384 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3385
3386 return bf_buf_size -
3387 sizeof(struct mlx5e_tx_wqe) +
3388 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3389}
3390
d8c9660d
TT		 3391void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3392 u32 *indirection_rqt, int len,
85082dba
TT		 3393 int num_channels)
3394{
d8c9660d
TT		 3395 int node = mdev->priv.numa_node;
3396 int node_num_of_cores;
85082dba
TT		 3397 int i;
3398
d8c9660d
TT		 3399 if (node == -1)
3400 node = first_online_node;
3401
3402 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3403
3404 if (node_num_of_cores)
3405 num_channels = min_t(int, num_channels, node_num_of_cores);
3406
85082dba
TT		 3407 for (i = 0; i < len; i++)
3408 indirection_rqt[i] = i % num_channels;
3409}
3410
b797a684
SM		 3411static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3412{
3413 enum pcie_link_width width;
3414 enum pci_bus_speed speed;
3415 int err = 0;
3416
3417 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3418 if (err)
3419 return err;
3420
3421 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3422 return -EINVAL;
3423
3424 switch (speed) {
3425 case PCIE_SPEED_2_5GT:
3426 *pci_bw = 2500 * width;
3427 break;
3428 case PCIE_SPEED_5_0GT:
3429 *pci_bw = 5000 * width;
3430 break;
3431 case PCIE_SPEED_8_0GT:
3432 *pci_bw = 8000 * width;
3433 break;
3434 default:
3435 return -EINVAL;
3436 }
3437
3438 return 0;
3439}
3440
3441static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3442{
3443 return (link_speed && pci_bw &&
3444 (pci_bw < 40000) && (pci_bw < link_speed));
3445}
3446
9908aa29
TT		 3447void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3448{
3449 params->rx_cq_period_mode = cq_period_mode;
3450
3451 params->rx_cq_moderation.pkts =
3452 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3453 params->rx_cq_moderation.usec =
3454 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3455
3456 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3457 params->rx_cq_moderation.usec =
3458 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3459}
3460
2b029556
SM		 3461u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3462{
3463 int i;
3464
3465 /* The supported periods are organized in ascending order */
3466 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3467 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3468 break;
3469
3470 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3471}
3472
6bfd390b
HHZ		 3473static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3474 struct net_device *netdev,
127ea380
HHZ		 3475 const struct mlx5e_profile *profile,
3476 void *ppriv)
f62b8bb8
AV		 3477{
3478 struct mlx5e_priv *priv = netdev_priv(netdev);
b797a684
SM		 3479 u32 link_speed = 0;
3480 u32 pci_bw = 0;
cb3c7fd4
GR		 3481 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3482 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3483 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8 3484
2fc4bfb7
SM		 3485 priv->mdev = mdev;
3486 priv->netdev = netdev;
3487 priv->params.num_channels = profile->max_nch(mdev);
3488 priv->profile = profile;
3489 priv->ppriv = ppriv;
3490
2b029556
SM		 3491 priv->params.lro_timeout =
3492 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3493
2fc4bfb7 3494 priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3495
b797a684 3496 /* set CQE compression */
9bcc8606 3497 priv->params.rx_cqe_compress_def = false;
b797a684
SM		 3498 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3499 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3500 mlx5e_get_max_linkspeed(mdev, &link_speed);
3501 mlx5e_get_pci_bw(mdev, &pci_bw);
3502 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3503 link_speed, pci_bw);
9bcc8606 3504 priv->params.rx_cqe_compress_def =
b797a684
SM		 3505 cqe_compress_heuristic(link_speed, pci_bw);
3506 }
b797a684 3507
2fc4bfb7
SM		 3508 mlx5e_set_rq_priv_params(priv);
3509 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
461017cb 3510 priv->params.lro_en = true;
9908aa29 3511
cb3c7fd4
GR		 3512 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3513 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
9908aa29
TT		 3514
3515 priv->params.tx_cq_moderation.usec =
f62b8bb8 3516 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
9908aa29 3517 priv->params.tx_cq_moderation.pkts =
f62b8bb8 3518 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 3519 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
8c7245a6 3520 mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
f62b8bb8 3521 priv->params.num_tc = 1;
2be6967c 3522 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 3523
57afead5
AS		 3524 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3525 sizeof(priv->params.toeplitz_hash_key));
3526
d8c9660d 3527 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
6bfd390b 3528 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
2d75b2bc 3529
e4b85508
SM		 3530 priv->params.lro_wqe_sz =
3531 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3532 /* Extra room needed for build_skb */
3533 MLX5_RX_HEADROOM -
3534 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
f62b8bb8 3535
9908aa29 3536 /* Initialize pflags */
59ece1c9
SD		 3537 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3538 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9bcc8606 3539 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, priv->params.rx_cqe_compress_def);
9908aa29 3540
f62b8bb8
AV		 3541 mutex_init(&priv->state_lock);
3542
3543 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3544 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3545 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3546 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3547}
3548
3549static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3550{
3551 struct mlx5e_priv *priv = netdev_priv(netdev);
3552
e1d7d349 3553 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3554 if (is_zero_ether_addr(netdev->dev_addr) &&
3555 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3556 eth_hw_addr_random(netdev);
3557 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3558 }
f62b8bb8
AV		 3559}
3560
cb67b832
HHZ		 3561static const struct switchdev_ops mlx5e_switchdev_ops = {
3562 .switchdev_port_attr_get = mlx5e_attr_get,
3563};
3564
6bfd390b 3565static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3566{
3567 struct mlx5e_priv *priv = netdev_priv(netdev);
3568 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3569 bool fcs_supported;
3570 bool fcs_enabled;
f62b8bb8
AV		 3571
3572 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3573
08fb1dac 3574 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3575 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac 3576#ifdef CONFIG_MLX5_CORE_EN_DCB
80653f73
HN		 3577 if (MLX5_CAP_GEN(mdev, qos))
3578 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac
SM		 3579#endif
3580 } else {
b0eed40e 3581 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3582 }
66e49ded 3583
f62b8bb8
AV		 3584 netdev->watchdog_timeo = 15 * HZ;
3585
3586 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3587
12be4b21 3588 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3589 netdev->vlan_features |= NETIF_F_IP_CSUM;
3590 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3591 netdev->vlan_features |= NETIF_F_GRO;
3592 netdev->vlan_features |= NETIF_F_TSO;
3593 netdev->vlan_features |= NETIF_F_TSO6;
3594 netdev->vlan_features |= NETIF_F_RXCSUM;
3595 netdev->vlan_features |= NETIF_F_RXHASH;
3596
3597 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3598 netdev->vlan_features |= NETIF_F_LRO;
3599
3600 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3601 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3602 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3603 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3604
b3f63c3d 3605 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3606 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3607 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3608 NETIF_F_GSO_PARTIAL;
b3f63c3d 3609 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3610 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3611 netdev->hw_enc_features |= NETIF_F_TSO;
3612 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3613 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3614 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3615 NETIF_F_GSO_PARTIAL;
3616 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3617 }
3618
94cb1ebb
EBE		 3619 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3620
3621 if (fcs_supported)
3622 netdev->hw_features |= NETIF_F_RXALL;
3623
f62b8bb8
AV		 3624 netdev->features = netdev->hw_features;
3625 if (!priv->params.lro_en)
3626 netdev->features &= ~NETIF_F_LRO;
3627
94cb1ebb
EBE		 3628 if (fcs_enabled)
3629 netdev->features &= ~NETIF_F_RXALL;
3630
e8f887ac
AV		 3631#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3632 if (FT_CAP(flow_modify_en) &&
3633 FT_CAP(modify_root) &&
3634 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3635 FT_CAP(flow_table_modify)) {
3636 netdev->hw_features |= NETIF_F_HW_TC;
3637#ifdef CONFIG_RFS_ACCEL
3638 netdev->hw_features |= NETIF_F_NTUPLE;
3639#endif
3640 }
e8f887ac 3641
f62b8bb8
AV		 3642 netdev->features |= NETIF_F_HIGHDMA;
3643
3644 netdev->priv_flags |= IFF_UNICAST_FLT;
3645
3646 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 3647
3648#ifdef CONFIG_NET_SWITCHDEV
3649 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3650 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3651#endif
f62b8bb8
AV		 3652}
3653
593cf338
RS		 3654static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3655{
3656 struct mlx5_core_dev *mdev = priv->mdev;
3657 int err;
3658
3659 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3660 if (err) {
3661 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3662 priv->q_counter = 0;
3663 }
3664}
3665
3666static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3667{
3668 if (!priv->q_counter)
3669 return;
3670
3671 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3672}
3673
6bfd390b
HHZ		 3674static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3675 struct net_device *netdev,
127ea380
HHZ		 3676 const struct mlx5e_profile *profile,
3677 void *ppriv)
6bfd390b
HHZ		 3678{
3679 struct mlx5e_priv *priv = netdev_priv(netdev);
3680
127ea380 3681 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 3682 mlx5e_build_nic_netdev(netdev);
3683 mlx5e_vxlan_init(priv);
3684}
3685
3686static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3687{
3688 mlx5e_vxlan_cleanup(priv);
127ea380 3689
a055c19b
DB		 3690 if (priv->xdp_prog)
3691 bpf_prog_put(priv->xdp_prog);
6bfd390b
HHZ		 3692}
3693
3694static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3695{
3696 struct mlx5_core_dev *mdev = priv->mdev;
3697 int err;
3698 int i;
3699
3700 err = mlx5e_create_indirect_rqts(priv);
3701 if (err) {
3702 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3703 return err;
3704 }
3705
3706 err = mlx5e_create_direct_rqts(priv);
3707 if (err) {
3708 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3709 goto err_destroy_indirect_rqts;
3710 }
3711
3712 err = mlx5e_create_indirect_tirs(priv);
3713 if (err) {
3714 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3715 goto err_destroy_direct_rqts;
3716 }
3717
3718 err = mlx5e_create_direct_tirs(priv);
3719 if (err) {
3720 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3721 goto err_destroy_indirect_tirs;
3722 }
3723
3724 err = mlx5e_create_flow_steering(priv);
3725 if (err) {
3726 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3727 goto err_destroy_direct_tirs;
3728 }
3729
3730 err = mlx5e_tc_init(priv);
3731 if (err)
3732 goto err_destroy_flow_steering;
3733
3734 return 0;
3735
3736err_destroy_flow_steering:
3737 mlx5e_destroy_flow_steering(priv);
3738err_destroy_direct_tirs:
3739 mlx5e_destroy_direct_tirs(priv);
3740err_destroy_indirect_tirs:
3741 mlx5e_destroy_indirect_tirs(priv);
3742err_destroy_direct_rqts:
3743 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3744 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3745err_destroy_indirect_rqts:
3746 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3747 return err;
3748}
3749
3750static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3751{
3752 int i;
3753
3754 mlx5e_tc_cleanup(priv);
3755 mlx5e_destroy_flow_steering(priv);
3756 mlx5e_destroy_direct_tirs(priv);
3757 mlx5e_destroy_indirect_tirs(priv);
3758 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3759 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3760 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3761}
3762
3763static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3764{
3765 int err;
3766
3767 err = mlx5e_create_tises(priv);
3768 if (err) {
3769 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3770 return err;
3771 }
3772
3773#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 3774 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 3775#endif
3776 return 0;
3777}
3778
3779static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3780{
3781 struct net_device *netdev = priv->netdev;
3782 struct mlx5_core_dev *mdev = priv->mdev;
127ea380
HHZ		 3783 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3784 struct mlx5_eswitch_rep rep;
6bfd390b 3785
7907f23a
AH		 3786 mlx5_lag_add(mdev, netdev);
3787
6bfd390b 3788 mlx5e_enable_async_events(priv);
127ea380
HHZ		 3789
3790 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
dbe413e3 3791 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
cb67b832
HHZ		 3792 rep.load = mlx5e_nic_rep_load;
3793 rep.unload = mlx5e_nic_rep_unload;
9deb2241 3794 rep.vport = FDB_UPLINK_VPORT;
726293f1 3795 rep.netdev = netdev;
9deb2241 3796 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
127ea380 3797 }
610e89e0
SM		 3798
3799 if (netdev->reg_state != NETREG_REGISTERED)
3800 return;
3801
3802 /* Device already registered: sync netdev system state */
3803 if (mlx5e_vxlan_allowed(mdev)) {
3804 rtnl_lock();
3805 udp_tunnel_get_rx_info(netdev);
3806 rtnl_unlock();
3807 }
3808
3809 queue_work(priv->wq, &priv->set_rx_mode_work);
6bfd390b
HHZ		 3810}
3811
3812static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3813{
3deef8ce
SM		 3814 struct mlx5_core_dev *mdev = priv->mdev;
3815 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3816
6bfd390b 3817 queue_work(priv->wq, &priv->set_rx_mode_work);
3deef8ce
SM		 3818 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3819 mlx5_eswitch_unregister_vport_rep(esw, 0);
6bfd390b 3820 mlx5e_disable_async_events(priv);
3deef8ce 3821 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 3822}
3823
3824static const struct mlx5e_profile mlx5e_nic_profile = {
3825 .init = mlx5e_nic_init,
3826 .cleanup = mlx5e_nic_cleanup,
3827 .init_rx = mlx5e_init_nic_rx,
3828 .cleanup_rx = mlx5e_cleanup_nic_rx,
3829 .init_tx = mlx5e_init_nic_tx,
3830 .cleanup_tx = mlx5e_cleanup_nic_tx,
3831 .enable = mlx5e_nic_enable,
3832 .disable = mlx5e_nic_disable,
3833 .update_stats = mlx5e_update_stats,
3834 .max_nch = mlx5e_get_max_num_channels,
3835 .max_tc = MLX5E_MAX_NUM_TC,
3836};
3837
26e59d80
MHY		 3838struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3839 const struct mlx5e_profile *profile,
3840 void *ppriv)
f62b8bb8 3841{
26e59d80 3842 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 3843 struct net_device *netdev;
3844 struct mlx5e_priv *priv;
f62b8bb8 3845
08fb1dac 3846 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 3847 nch * profile->max_tc,
08fb1dac 3848 nch);
f62b8bb8
AV		 3849 if (!netdev) {
3850 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3851 return NULL;
3852 }
3853
127ea380 3854 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 3855
3856 netif_carrier_off(netdev);
3857
3858 priv = netdev_priv(netdev);
3859
7bb29755
MF		 3860 priv->wq = create_singlethread_workqueue("mlx5e");
3861 if (!priv->wq)
26e59d80
MHY		 3862 goto err_cleanup_nic;
3863
3864 return netdev;
3865
3866err_cleanup_nic:
3867 profile->cleanup(priv);
3868 free_netdev(netdev);
3869
3870 return NULL;
3871}
3872
3873int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3874{
3875 const struct mlx5e_profile *profile;
3876 struct mlx5e_priv *priv;
b80f71f5 3877 u16 max_mtu;
26e59d80
MHY		 3878 int err;
3879
3880 priv = netdev_priv(netdev);
3881 profile = priv->profile;
3882 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 3883
6bfd390b
HHZ		 3884 err = profile->init_tx(priv);
3885 if (err)
ec8b9981 3886 goto out;
5c50368f
AS		 3887
3888 err = mlx5e_open_drop_rq(priv);
3889 if (err) {
3890 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 3891 goto err_cleanup_tx;
5c50368f
AS		 3892 }
3893
6bfd390b
HHZ		 3894 err = profile->init_rx(priv);
3895 if (err)
5c50368f 3896 goto err_close_drop_rq;
5c50368f 3897
593cf338
RS		 3898 mlx5e_create_q_counter(priv);
3899
33cfaaa8 3900 mlx5e_init_l2_addr(priv);
5c50368f 3901
b80f71f5
JW		 3902 /* MTU range: 68 - hw-specific max */
3903 netdev->min_mtu = ETH_MIN_MTU;
3904 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
3905 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
3906
13f9bba7
SM		 3907 mlx5e_set_dev_port_mtu(netdev);
3908
6bfd390b
HHZ		 3909 if (profile->enable)
3910 profile->enable(priv);
f62b8bb8 3911
26e59d80
MHY		 3912 rtnl_lock();
3913 if (netif_running(netdev))
3914 mlx5e_open(netdev);
3915 netif_device_attach(netdev);
3916 rtnl_unlock();
f62b8bb8 3917
26e59d80 3918 return 0;
5c50368f
AS		 3919
3920err_close_drop_rq:
3921 mlx5e_close_drop_rq(priv);
3922
6bfd390b
HHZ		 3923err_cleanup_tx:
3924 profile->cleanup_tx(priv);
5c50368f 3925
26e59d80
MHY		 3926out:
3927 return err;
f62b8bb8
AV		 3928}
3929
127ea380
HHZ		 3930static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3931{
3932 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3933 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3934 int vport;
dbe413e3 3935 u8 mac[ETH_ALEN];
127ea380
HHZ		 3936
3937 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3938 return;
3939
dbe413e3
HHZ		 3940 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3941
127ea380
HHZ		 3942 for (vport = 1; vport < total_vfs; vport++) {
3943 struct mlx5_eswitch_rep rep;
3944
cb67b832
HHZ		 3945 rep.load = mlx5e_vport_rep_load;
3946 rep.unload = mlx5e_vport_rep_unload;
127ea380 3947 rep.vport = vport;
dbe413e3 3948 ether_addr_copy(rep.hw_id, mac);
9deb2241 3949 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
127ea380
HHZ		 3950 }
3951}
3952
26e59d80
MHY		 3953void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3954{
3955 struct mlx5e_priv *priv = netdev_priv(netdev);
3956 const struct mlx5e_profile *profile = priv->profile;
3957
3958 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80
MHY		 3959
3960 rtnl_lock();
3961 if (netif_running(netdev))
3962 mlx5e_close(netdev);
3963 netif_device_detach(netdev);
3964 rtnl_unlock();
3965
37f304d1
SM		 3966 if (profile->disable)
3967 profile->disable(priv);
3968 flush_workqueue(priv->wq);
3969
26e59d80
MHY		 3970 mlx5e_destroy_q_counter(priv);
3971 profile->cleanup_rx(priv);
3972 mlx5e_close_drop_rq(priv);
3973 profile->cleanup_tx(priv);
26e59d80
MHY		 3974 cancel_delayed_work_sync(&priv->update_stats_work);
3975}
3976
3977/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3978 * hardware contexts and to connect it to the current netdev.
3979 */
3980static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
3981{
3982 struct mlx5e_priv *priv = vpriv;
3983 struct net_device *netdev = priv->netdev;
3984 int err;
3985
3986 if (netif_device_present(netdev))
3987 return 0;
3988
3989 err = mlx5e_create_mdev_resources(mdev);
3990 if (err)
3991 return err;
3992
3993 err = mlx5e_attach_netdev(mdev, netdev);
3994 if (err) {
3995 mlx5e_destroy_mdev_resources(mdev);
3996 return err;
3997 }
3998
3999 return 0;
4000}
4001
4002static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4003{
4004 struct mlx5e_priv *priv = vpriv;
4005 struct net_device *netdev = priv->netdev;
4006
4007 if (!netif_device_present(netdev))
4008 return;
4009
4010 mlx5e_detach_netdev(mdev, netdev);
4011 mlx5e_destroy_mdev_resources(mdev);
4012}
4013
b50d292b
HHZ		 4014static void *mlx5e_add(struct mlx5_core_dev *mdev)
4015{
127ea380 4016 struct mlx5_eswitch *esw = mdev->priv.eswitch;
26e59d80 4017 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
127ea380 4018 void *ppriv = NULL;
26e59d80
MHY		 4019 void *priv;
4020 int vport;
4021 int err;
4022 struct net_device *netdev;
b50d292b 4023
26e59d80
MHY		 4024 err = mlx5e_check_required_hca_cap(mdev);
4025 if (err)
b50d292b
HHZ		 4026 return NULL;
4027
127ea380
HHZ		 4028 mlx5e_register_vport_rep(mdev);
4029
4030 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4031 ppriv = &esw->offloads.vport_reps[0];
4032
26e59d80
MHY		 4033 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4034 if (!netdev) {
4035 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4036 goto err_unregister_reps;
4037 }
4038
4039 priv = netdev_priv(netdev);
4040
4041 err = mlx5e_attach(mdev, priv);
4042 if (err) {
4043 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4044 goto err_destroy_netdev;
4045 }
4046
4047 err = register_netdev(netdev);
4048 if (err) {
4049 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4050 goto err_detach;
b50d292b 4051 }
26e59d80
MHY		 4052
4053 return priv;
4054
4055err_detach:
4056 mlx5e_detach(mdev, priv);
4057
4058err_destroy_netdev:
4059 mlx5e_destroy_netdev(mdev, priv);
4060
4061err_unregister_reps:
4062 for (vport = 1; vport < total_vfs; vport++)
4063 mlx5_eswitch_unregister_vport_rep(esw, vport);
4064
4065 return NULL;
b50d292b
HHZ		 4066}
4067
cb67b832 4068void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
f62b8bb8 4069{
6bfd390b 4070 const struct mlx5e_profile *profile = priv->profile;
f62b8bb8
AV		 4071 struct net_device *netdev = priv->netdev;
4072
7bb29755 4073 destroy_workqueue(priv->wq);
6bfd390b
HHZ		 4074 if (profile->cleanup)
4075 profile->cleanup(priv);
26e59d80 4076 free_netdev(netdev);
f62b8bb8
AV		 4077}
4078
b50d292b
HHZ		 4079static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4080{
127ea380
HHZ		 4081 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4082 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
b50d292b 4083 struct mlx5e_priv *priv = vpriv;
127ea380 4084 int vport;
b50d292b 4085
127ea380
HHZ		 4086 for (vport = 1; vport < total_vfs; vport++)
4087 mlx5_eswitch_unregister_vport_rep(esw, vport);
4088
5e1e93c7 4089 unregister_netdev(priv->netdev);
26e59d80
MHY		 4090 mlx5e_detach(mdev, vpriv);
4091 mlx5e_destroy_netdev(mdev, priv);
b50d292b
HHZ		 4092}
4093
f62b8bb8
AV		 4094static void *mlx5e_get_netdev(void *vpriv)
4095{
4096 struct mlx5e_priv *priv = vpriv;
4097
4098 return priv->netdev;
4099}
4100
4101static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4102 .add = mlx5e_add,
4103 .remove = mlx5e_remove,
26e59d80
MHY		 4104 .attach = mlx5e_attach,
4105 .detach = mlx5e_detach,
f62b8bb8
AV		 4106 .event = mlx5e_async_event,
4107 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4108 .get_dev = mlx5e_get_netdev,
4109};
4110
4111void mlx5e_init(void)
4112{
665bc539 4113 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4114 mlx5_register_interface(&mlx5e_interface);
4115}
4116
4117void mlx5e_cleanup(void)
4118{
4119 mlx5_unregister_interface(&mlx5e_interface);
4120}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git