]>
Commit | Line | Data |
---|---|---|
f62b8bb8 | 1 | /* |
b3f63c3d | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
e8f887ac AV |
33 | #include <net/tc_act/tc_gact.h> |
34 | #include <net/pkt_cls.h> | |
86d722ad | 35 | #include <linux/mlx5/fs.h> |
b3f63c3d | 36 | #include <net/vxlan.h> |
86994156 | 37 | #include <linux/bpf.h> |
60bbf7ee | 38 | #include <net/page_pool.h> |
1d447a39 | 39 | #include "eswitch.h" |
f62b8bb8 | 40 | #include "en.h" |
e8f887ac | 41 | #include "en_tc.h" |
1d447a39 | 42 | #include "en_rep.h" |
547eede0 | 43 | #include "en_accel/ipsec.h" |
899a59d3 | 44 | #include "en_accel/ipsec_rxtx.h" |
c83294b9 | 45 | #include "en_accel/tls.h" |
899a59d3 | 46 | #include "accel/ipsec.h" |
c83294b9 | 47 | #include "accel/tls.h" |
b3f63c3d | 48 | #include "vxlan.h" |
f62b8bb8 AV |
49 | |
50 | struct mlx5e_rq_param { | |
cb3c7fd4 GR |
51 | u32 rqc[MLX5_ST_SZ_DW(rqc)]; |
52 | struct mlx5_wq_param wq; | |
f62b8bb8 AV |
53 | }; |
54 | ||
55 | struct mlx5e_sq_param { | |
56 | u32 sqc[MLX5_ST_SZ_DW(sqc)]; | |
57 | struct mlx5_wq_param wq; | |
58 | }; | |
59 | ||
60 | struct mlx5e_cq_param { | |
61 | u32 cqc[MLX5_ST_SZ_DW(cqc)]; | |
62 | struct mlx5_wq_param wq; | |
63 | u16 eq_ix; | |
9908aa29 | 64 | u8 cq_period_mode; |
f62b8bb8 AV |
65 | }; |
66 | ||
67 | struct mlx5e_channel_param { | |
68 | struct mlx5e_rq_param rq; | |
69 | struct mlx5e_sq_param sq; | |
b5503b99 | 70 | struct mlx5e_sq_param xdp_sq; |
d3c9bc27 | 71 | struct mlx5e_sq_param icosq; |
f62b8bb8 AV |
72 | struct mlx5e_cq_param rx_cq; |
73 | struct mlx5e_cq_param tx_cq; | |
d3c9bc27 | 74 | struct mlx5e_cq_param icosq_cq; |
f62b8bb8 AV |
75 | }; |
76 | ||
2ccb0a79 | 77 | bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev) |
2fc4bfb7 | 78 | { |
ea3886ca | 79 | bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && |
2fc4bfb7 SM |
80 | MLX5_CAP_GEN(mdev, umr_ptr_rlky) && |
81 | MLX5_CAP_ETH(mdev, reg_umr_sq); | |
ea3886ca TT |
82 | u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq); |
83 | bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap; | |
84 | ||
85 | if (!striding_rq_umr) | |
86 | return false; | |
87 | if (!inline_umr) { | |
88 | mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n", | |
89 | (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap); | |
90 | return false; | |
91 | } | |
92 | return true; | |
2fc4bfb7 SM |
93 | } |
94 | ||
73281b78 TT |
95 | static u32 mlx5e_mpwqe_get_linear_frag_sz(struct mlx5e_params *params) |
96 | { | |
619a8f2a TT |
97 | if (!params->xdp_prog) { |
98 | u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); | |
99 | u16 rq_headroom = MLX5_RX_HEADROOM + NET_IP_ALIGN; | |
73281b78 | 100 | |
619a8f2a TT |
101 | return MLX5_SKB_FRAG_SZ(rq_headroom + hw_mtu); |
102 | } | |
103 | ||
104 | return PAGE_SIZE; | |
73281b78 TT |
105 | } |
106 | ||
107 | static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params) | |
108 | { | |
109 | u32 linear_frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params); | |
110 | ||
111 | return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz); | |
112 | } | |
113 | ||
619a8f2a TT |
114 | static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev, |
115 | struct mlx5e_params *params) | |
116 | { | |
117 | u32 frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params); | |
118 | s8 signed_log_num_strides_param; | |
119 | u8 log_num_strides; | |
120 | ||
121 | if (params->lro_en || frag_sz > PAGE_SIZE) | |
122 | return false; | |
123 | ||
124 | if (MLX5_CAP_GEN(mdev, ext_stride_num_range)) | |
125 | return true; | |
126 | ||
127 | log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz); | |
128 | signed_log_num_strides_param = | |
129 | (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE; | |
130 | ||
131 | return signed_log_num_strides_param >= 0; | |
132 | } | |
133 | ||
73281b78 TT |
134 | static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params) |
135 | { | |
136 | if (params->log_rq_mtu_frames < | |
137 | mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW) | |
138 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
139 | ||
140 | return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params); | |
141 | } | |
142 | ||
143 | static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev, | |
144 | struct mlx5e_params *params) | |
f1e4fc9b | 145 | { |
619a8f2a TT |
146 | if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params)) |
147 | return order_base_2(mlx5e_mpwqe_get_linear_frag_sz(params)); | |
148 | ||
f1e4fc9b TT |
149 | return MLX5E_MPWQE_STRIDE_SZ(mdev, |
150 | MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)); | |
151 | } | |
152 | ||
73281b78 TT |
153 | static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev, |
154 | struct mlx5e_params *params) | |
f1e4fc9b TT |
155 | { |
156 | return MLX5_MPWRQ_LOG_WQE_SZ - | |
157 | mlx5e_mpwqe_get_log_stride_size(mdev, params); | |
158 | } | |
159 | ||
619a8f2a TT |
160 | static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev, |
161 | struct mlx5e_params *params) | |
b0cedc84 TT |
162 | { |
163 | u16 linear_rq_headroom = params->xdp_prog ? | |
164 | XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM; | |
165 | ||
166 | linear_rq_headroom += NET_IP_ALIGN; | |
167 | ||
168 | if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST) | |
169 | return linear_rq_headroom; | |
170 | ||
619a8f2a TT |
171 | if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params)) |
172 | return linear_rq_headroom; | |
173 | ||
b0cedc84 TT |
174 | return 0; |
175 | } | |
176 | ||
696a97cf | 177 | void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, |
2a0f561b | 178 | struct mlx5e_params *params) |
2fc4bfb7 | 179 | { |
6a9764ef | 180 | params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; |
73281b78 TT |
181 | params->log_rq_mtu_frames = is_kdump_kernel() ? |
182 | MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE : | |
183 | MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; | |
6a9764ef | 184 | switch (params->rq_wq_type) { |
2fc4bfb7 | 185 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: |
2fc4bfb7 SM |
186 | break; |
187 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
4078e637 | 188 | /* Extra room needed for build_skb */ |
619a8f2a | 189 | params->lro_wqe_sz -= mlx5e_get_rq_headroom(mdev, params) + |
4078e637 | 190 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
2fc4bfb7 | 191 | } |
2fc4bfb7 | 192 | |
6a9764ef SM |
193 | mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n", |
194 | params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ, | |
619a8f2a TT |
195 | params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ? |
196 | BIT(mlx5e_mpwqe_get_log_rq_size(params)) : | |
73281b78 | 197 | BIT(params->log_rq_mtu_frames), |
f1e4fc9b | 198 | BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)), |
6a9764ef | 199 | MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)); |
2fc4bfb7 SM |
200 | } |
201 | ||
2ccb0a79 TT |
202 | bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev, |
203 | struct mlx5e_params *params) | |
204 | { | |
205 | return mlx5e_check_fragmented_striding_rq_cap(mdev) && | |
22f45398 TT |
206 | !MLX5_IPSEC_DEV(mdev) && |
207 | !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params)); | |
2ccb0a79 | 208 | } |
291f445e | 209 | |
2ccb0a79 | 210 | void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params) |
2fc4bfb7 | 211 | { |
2ccb0a79 TT |
212 | params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) && |
213 | MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ? | |
291f445e TT |
214 | MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ : |
215 | MLX5_WQ_TYPE_LINKED_LIST; | |
2fc4bfb7 SM |
216 | } |
217 | ||
f62b8bb8 AV |
218 | static void mlx5e_update_carrier(struct mlx5e_priv *priv) |
219 | { | |
220 | struct mlx5_core_dev *mdev = priv->mdev; | |
221 | u8 port_state; | |
222 | ||
223 | port_state = mlx5_query_vport_state(mdev, | |
e53eef63 OG |
224 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, |
225 | 0); | |
f62b8bb8 | 226 | |
87424ad5 SD |
227 | if (port_state == VPORT_STATE_UP) { |
228 | netdev_info(priv->netdev, "Link up\n"); | |
f62b8bb8 | 229 | netif_carrier_on(priv->netdev); |
87424ad5 SD |
230 | } else { |
231 | netdev_info(priv->netdev, "Link down\n"); | |
f62b8bb8 | 232 | netif_carrier_off(priv->netdev); |
87424ad5 | 233 | } |
f62b8bb8 AV |
234 | } |
235 | ||
236 | static void mlx5e_update_carrier_work(struct work_struct *work) | |
237 | { | |
238 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, | |
239 | update_carrier_work); | |
240 | ||
241 | mutex_lock(&priv->state_lock); | |
242 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
7ca42c80 ES |
243 | if (priv->profile->update_carrier) |
244 | priv->profile->update_carrier(priv); | |
f62b8bb8 AV |
245 | mutex_unlock(&priv->state_lock); |
246 | } | |
247 | ||
19386177 | 248 | void mlx5e_update_stats(struct mlx5e_priv *priv) |
f62b8bb8 | 249 | { |
19386177 | 250 | int i; |
f62b8bb8 | 251 | |
19386177 KH |
252 | for (i = mlx5e_num_stats_grps - 1; i >= 0; i--) |
253 | if (mlx5e_stats_grps[i].update_stats) | |
254 | mlx5e_stats_grps[i].update_stats(priv); | |
f62b8bb8 AV |
255 | } |
256 | ||
3834a5e6 GP |
257 | static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv) |
258 | { | |
19386177 KH |
259 | int i; |
260 | ||
261 | for (i = mlx5e_num_stats_grps - 1; i >= 0; i--) | |
262 | if (mlx5e_stats_grps[i].update_stats_mask & | |
263 | MLX5E_NDO_UPDATE_STATS) | |
264 | mlx5e_stats_grps[i].update_stats(priv); | |
3834a5e6 GP |
265 | } |
266 | ||
cb67b832 | 267 | void mlx5e_update_stats_work(struct work_struct *work) |
f62b8bb8 AV |
268 | { |
269 | struct delayed_work *dwork = to_delayed_work(work); | |
270 | struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv, | |
271 | update_stats_work); | |
272 | mutex_lock(&priv->state_lock); | |
273 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
6bfd390b | 274 | priv->profile->update_stats(priv); |
7bb29755 MF |
275 | queue_delayed_work(priv->wq, dwork, |
276 | msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL)); | |
f62b8bb8 AV |
277 | } |
278 | mutex_unlock(&priv->state_lock); | |
279 | } | |
280 | ||
daa21560 TT |
281 | static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, |
282 | enum mlx5_dev_event event, unsigned long param) | |
f62b8bb8 | 283 | { |
daa21560 TT |
284 | struct mlx5e_priv *priv = vpriv; |
285 | ||
e0f46eb9 | 286 | if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state)) |
daa21560 TT |
287 | return; |
288 | ||
f62b8bb8 AV |
289 | switch (event) { |
290 | case MLX5_DEV_EVENT_PORT_UP: | |
291 | case MLX5_DEV_EVENT_PORT_DOWN: | |
7bb29755 | 292 | queue_work(priv->wq, &priv->update_carrier_work); |
f62b8bb8 | 293 | break; |
f62b8bb8 AV |
294 | default: |
295 | break; | |
296 | } | |
297 | } | |
298 | ||
f62b8bb8 AV |
299 | static void mlx5e_enable_async_events(struct mlx5e_priv *priv) |
300 | { | |
e0f46eb9 | 301 | set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state); |
f62b8bb8 AV |
302 | } |
303 | ||
304 | static void mlx5e_disable_async_events(struct mlx5e_priv *priv) | |
305 | { | |
e0f46eb9 | 306 | clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state); |
78249c42 | 307 | synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC)); |
f62b8bb8 AV |
308 | } |
309 | ||
31391048 SM |
310 | static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, |
311 | struct mlx5e_icosq *sq, | |
b8a98a4c | 312 | struct mlx5e_umr_wqe *wqe) |
7e426671 TT |
313 | { |
314 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
315 | struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl; | |
ea3886ca | 316 | u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS); |
7e426671 TT |
317 | |
318 | cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) | | |
319 | ds_cnt); | |
320 | cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; | |
321 | cseg->imm = rq->mkey_be; | |
322 | ||
ea3886ca | 323 | ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE; |
31616255 | 324 | ucseg->xlt_octowords = |
7e426671 | 325 | cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE)); |
7e426671 | 326 | ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); |
7e426671 TT |
327 | } |
328 | ||
329 | static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, | |
330 | struct mlx5e_channel *c) | |
331 | { | |
332 | int wq_sz = mlx5_wq_ll_get_size(&rq->wq); | |
7e426671 | 333 | |
21c59685 | 334 | rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info), |
231243c8 | 335 | GFP_KERNEL, cpu_to_node(c->cpu)); |
21c59685 | 336 | if (!rq->mpwqe.info) |
ea3886ca | 337 | return -ENOMEM; |
7e426671 | 338 | |
b8a98a4c | 339 | mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe); |
7e426671 TT |
340 | |
341 | return 0; | |
7e426671 TT |
342 | } |
343 | ||
a43b25da | 344 | static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev, |
ec8b9981 TT |
345 | u64 npages, u8 page_shift, |
346 | struct mlx5_core_mkey *umr_mkey) | |
3608ae77 | 347 | { |
3608ae77 TT |
348 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
349 | void *mkc; | |
350 | u32 *in; | |
351 | int err; | |
352 | ||
1b9a07ee | 353 | in = kvzalloc(inlen, GFP_KERNEL); |
3608ae77 TT |
354 | if (!in) |
355 | return -ENOMEM; | |
356 | ||
357 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
358 | ||
3608ae77 TT |
359 | MLX5_SET(mkc, mkc, free, 1); |
360 | MLX5_SET(mkc, mkc, umr_en, 1); | |
361 | MLX5_SET(mkc, mkc, lw, 1); | |
362 | MLX5_SET(mkc, mkc, lr, 1); | |
cdbd0d2b | 363 | MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); |
3608ae77 TT |
364 | |
365 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
366 | MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn); | |
ec8b9981 | 367 | MLX5_SET64(mkc, mkc, len, npages << page_shift); |
3608ae77 TT |
368 | MLX5_SET(mkc, mkc, translations_octword_size, |
369 | MLX5_MTT_OCTW(npages)); | |
ec8b9981 | 370 | MLX5_SET(mkc, mkc, log_page_size, page_shift); |
3608ae77 | 371 | |
ec8b9981 | 372 | err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen); |
3608ae77 TT |
373 | |
374 | kvfree(in); | |
375 | return err; | |
376 | } | |
377 | ||
a43b25da | 378 | static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq) |
ec8b9981 | 379 | { |
6a9764ef | 380 | u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq)); |
ec8b9981 | 381 | |
a43b25da | 382 | return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey); |
ec8b9981 TT |
383 | } |
384 | ||
b8a98a4c TT |
385 | static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix) |
386 | { | |
387 | return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT; | |
388 | } | |
389 | ||
3b77235b | 390 | static int mlx5e_alloc_rq(struct mlx5e_channel *c, |
6a9764ef SM |
391 | struct mlx5e_params *params, |
392 | struct mlx5e_rq_param *rqp, | |
3b77235b | 393 | struct mlx5e_rq *rq) |
f62b8bb8 | 394 | { |
60bbf7ee | 395 | struct page_pool_params pp_params = { 0 }; |
a43b25da | 396 | struct mlx5_core_dev *mdev = c->mdev; |
6a9764ef | 397 | void *rqc = rqp->rqc; |
f62b8bb8 | 398 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); |
60bbf7ee | 399 | u32 byte_count, pool_size; |
1bfecfca | 400 | int npages; |
f62b8bb8 AV |
401 | int wq_sz; |
402 | int err; | |
403 | int i; | |
404 | ||
231243c8 | 405 | rqp->wq.db_numa_node = cpu_to_node(c->cpu); |
311c7c71 | 406 | |
6a9764ef | 407 | err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq, |
f62b8bb8 AV |
408 | &rq->wq_ctrl); |
409 | if (err) | |
410 | return err; | |
411 | ||
412 | rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; | |
413 | ||
414 | wq_sz = mlx5_wq_ll_get_size(&rq->wq); | |
f62b8bb8 | 415 | |
6a9764ef | 416 | rq->wq_type = params->rq_wq_type; |
7e426671 TT |
417 | rq->pdev = c->pdev; |
418 | rq->netdev = c->netdev; | |
a43b25da | 419 | rq->tstamp = c->tstamp; |
7c39afb3 | 420 | rq->clock = &mdev->clock; |
7e426671 TT |
421 | rq->channel = c; |
422 | rq->ix = c->ix; | |
a43b25da | 423 | rq->mdev = mdev; |
472a1e44 | 424 | rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); |
97bc402d | 425 | |
6a9764ef | 426 | rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL; |
97bc402d DB |
427 | if (IS_ERR(rq->xdp_prog)) { |
428 | err = PTR_ERR(rq->xdp_prog); | |
429 | rq->xdp_prog = NULL; | |
430 | goto err_rq_wq_destroy; | |
431 | } | |
7e426671 | 432 | |
e213f5b6 WY |
433 | err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix); |
434 | if (err < 0) | |
0ddf5432 JDB |
435 | goto err_rq_wq_destroy; |
436 | ||
bce2b2bf | 437 | rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; |
619a8f2a | 438 | rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params); |
60bbf7ee | 439 | pool_size = 1 << params->log_rq_mtu_frames; |
b5503b99 | 440 | |
6a9764ef | 441 | switch (rq->wq_type) { |
461017cb | 442 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: |
60bbf7ee JDB |
443 | |
444 | pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params); | |
7cc6d77b | 445 | rq->post_wqes = mlx5e_post_rx_mpwqes; |
6cd392a0 | 446 | rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe; |
461017cb | 447 | |
20fd0c19 | 448 | rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe; |
899a59d3 IT |
449 | #ifdef CONFIG_MLX5_EN_IPSEC |
450 | if (MLX5_IPSEC_DEV(mdev)) { | |
451 | err = -EINVAL; | |
452 | netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n"); | |
453 | goto err_rq_wq_destroy; | |
454 | } | |
455 | #endif | |
20fd0c19 SM |
456 | if (!rq->handle_rx_cqe) { |
457 | err = -EINVAL; | |
458 | netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err); | |
459 | goto err_rq_wq_destroy; | |
460 | } | |
461 | ||
619a8f2a TT |
462 | rq->mpwqe.skb_from_cqe_mpwrq = |
463 | mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ? | |
464 | mlx5e_skb_from_cqe_mpwrq_linear : | |
465 | mlx5e_skb_from_cqe_mpwrq_nonlinear; | |
f1e4fc9b TT |
466 | rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params); |
467 | rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params)); | |
1bfecfca | 468 | |
b681c481 | 469 | byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz; |
ec8b9981 | 470 | |
a43b25da | 471 | err = mlx5e_create_rq_umr_mkey(mdev, rq); |
7e426671 TT |
472 | if (err) |
473 | goto err_rq_wq_destroy; | |
ec8b9981 TT |
474 | rq->mkey_be = cpu_to_be32(rq->umr_mkey.key); |
475 | ||
476 | err = mlx5e_rq_alloc_mpwqe_info(rq, c); | |
477 | if (err) | |
478 | goto err_destroy_umr_mkey; | |
461017cb TT |
479 | break; |
480 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
accd5883 TT |
481 | rq->wqe.frag_info = |
482 | kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info), | |
231243c8 | 483 | GFP_KERNEL, cpu_to_node(c->cpu)); |
accd5883 | 484 | if (!rq->wqe.frag_info) { |
461017cb TT |
485 | err = -ENOMEM; |
486 | goto err_rq_wq_destroy; | |
487 | } | |
7cc6d77b | 488 | rq->post_wqes = mlx5e_post_rx_wqes; |
6cd392a0 | 489 | rq->dealloc_wqe = mlx5e_dealloc_rx_wqe; |
461017cb | 490 | |
899a59d3 IT |
491 | #ifdef CONFIG_MLX5_EN_IPSEC |
492 | if (c->priv->ipsec) | |
493 | rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe; | |
494 | else | |
495 | #endif | |
496 | rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe; | |
20fd0c19 | 497 | if (!rq->handle_rx_cqe) { |
accd5883 | 498 | kfree(rq->wqe.frag_info); |
20fd0c19 SM |
499 | err = -EINVAL; |
500 | netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err); | |
501 | goto err_rq_wq_destroy; | |
502 | } | |
503 | ||
b681c481 | 504 | byte_count = params->lro_en ? |
6a9764ef | 505 | params->lro_wqe_sz : |
472a1e44 | 506 | MLX5E_SW2HW_MTU(params, params->sw_mtu); |
899a59d3 IT |
507 | #ifdef CONFIG_MLX5_EN_IPSEC |
508 | if (MLX5_IPSEC_DEV(mdev)) | |
b681c481 | 509 | byte_count += MLX5E_METADATA_ETHER_LEN; |
899a59d3 | 510 | #endif |
accd5883 | 511 | rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en; |
1bfecfca SM |
512 | |
513 | /* calc the required page order */ | |
b45d8b50 | 514 | rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count); |
accd5883 | 515 | npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE); |
1bfecfca SM |
516 | rq->buff.page_order = order_base_2(npages); |
517 | ||
461017cb | 518 | byte_count |= MLX5_HW_START_PADDING; |
7e426671 | 519 | rq->mkey_be = c->mkey_be; |
461017cb | 520 | } |
f62b8bb8 | 521 | |
60bbf7ee JDB |
522 | /* Create a page_pool and register it with rxq */ |
523 | pp_params.order = rq->buff.page_order; | |
524 | pp_params.flags = 0; /* No-internal DMA mapping in page_pool */ | |
525 | pp_params.pool_size = pool_size; | |
526 | pp_params.nid = cpu_to_node(c->cpu); | |
527 | pp_params.dev = c->pdev; | |
528 | pp_params.dma_dir = rq->buff.map_dir; | |
529 | ||
530 | /* page_pool can be used even when there is no rq->xdp_prog, | |
531 | * given page_pool does not handle DMA mapping there is no | |
532 | * required state to clear. And page_pool gracefully handle | |
533 | * elevated refcnt. | |
534 | */ | |
535 | rq->page_pool = page_pool_create(&pp_params); | |
536 | if (IS_ERR(rq->page_pool)) { | |
537 | if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) | |
538 | kfree(rq->wqe.frag_info); | |
539 | err = PTR_ERR(rq->page_pool); | |
540 | rq->page_pool = NULL; | |
541 | goto err_rq_wq_destroy; | |
84f5e3fb | 542 | } |
60bbf7ee JDB |
543 | err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq, |
544 | MEM_TYPE_PAGE_POOL, rq->page_pool); | |
545 | if (err) | |
546 | goto err_rq_wq_destroy; | |
84f5e3fb | 547 | |
f62b8bb8 AV |
548 | for (i = 0; i < wq_sz; i++) { |
549 | struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); | |
550 | ||
4c2af5cc | 551 | if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { |
b8a98a4c | 552 | u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i); |
4c2af5cc | 553 | |
619a8f2a | 554 | wqe->data.addr = cpu_to_be64(dma_offset + rq->buff.headroom); |
4c2af5cc TT |
555 | } |
556 | ||
461017cb | 557 | wqe->data.byte_count = cpu_to_be32(byte_count); |
7e426671 | 558 | wqe->data.lkey = rq->mkey_be; |
f62b8bb8 AV |
559 | } |
560 | ||
9a317425 AG |
561 | INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work); |
562 | ||
563 | switch (params->rx_cq_moderation.cq_period_mode) { | |
564 | case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: | |
565 | rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; | |
566 | break; | |
567 | case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: | |
568 | default: | |
569 | rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; | |
570 | } | |
571 | ||
4415a031 TT |
572 | rq->page_cache.head = 0; |
573 | rq->page_cache.tail = 0; | |
574 | ||
f62b8bb8 AV |
575 | return 0; |
576 | ||
ec8b9981 TT |
577 | err_destroy_umr_mkey: |
578 | mlx5_core_destroy_mkey(mdev, &rq->umr_mkey); | |
579 | ||
f62b8bb8 | 580 | err_rq_wq_destroy: |
97bc402d DB |
581 | if (rq->xdp_prog) |
582 | bpf_prog_put(rq->xdp_prog); | |
0ddf5432 | 583 | xdp_rxq_info_unreg(&rq->xdp_rxq); |
60bbf7ee JDB |
584 | if (rq->page_pool) |
585 | page_pool_destroy(rq->page_pool); | |
f62b8bb8 AV |
586 | mlx5_wq_destroy(&rq->wq_ctrl); |
587 | ||
588 | return err; | |
589 | } | |
590 | ||
3b77235b | 591 | static void mlx5e_free_rq(struct mlx5e_rq *rq) |
f62b8bb8 | 592 | { |
4415a031 TT |
593 | int i; |
594 | ||
86994156 RS |
595 | if (rq->xdp_prog) |
596 | bpf_prog_put(rq->xdp_prog); | |
597 | ||
0ddf5432 | 598 | xdp_rxq_info_unreg(&rq->xdp_rxq); |
60bbf7ee JDB |
599 | if (rq->page_pool) |
600 | page_pool_destroy(rq->page_pool); | |
0ddf5432 | 601 | |
461017cb TT |
602 | switch (rq->wq_type) { |
603 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
ea3886ca | 604 | kfree(rq->mpwqe.info); |
a43b25da | 605 | mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey); |
461017cb TT |
606 | break; |
607 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
accd5883 | 608 | kfree(rq->wqe.frag_info); |
461017cb TT |
609 | } |
610 | ||
4415a031 TT |
611 | for (i = rq->page_cache.head; i != rq->page_cache.tail; |
612 | i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) { | |
613 | struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i]; | |
614 | ||
615 | mlx5e_page_release(rq, dma_info, false); | |
616 | } | |
f62b8bb8 AV |
617 | mlx5_wq_destroy(&rq->wq_ctrl); |
618 | } | |
619 | ||
6a9764ef SM |
620 | static int mlx5e_create_rq(struct mlx5e_rq *rq, |
621 | struct mlx5e_rq_param *param) | |
f62b8bb8 | 622 | { |
a43b25da | 623 | struct mlx5_core_dev *mdev = rq->mdev; |
f62b8bb8 AV |
624 | |
625 | void *in; | |
626 | void *rqc; | |
627 | void *wq; | |
628 | int inlen; | |
629 | int err; | |
630 | ||
631 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + | |
632 | sizeof(u64) * rq->wq_ctrl.buf.npages; | |
1b9a07ee | 633 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
634 | if (!in) |
635 | return -ENOMEM; | |
636 | ||
637 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); | |
638 | wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
639 | ||
640 | memcpy(rqc, param->rqc, sizeof(param->rqc)); | |
641 | ||
97de9f31 | 642 | MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn); |
f62b8bb8 | 643 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); |
f62b8bb8 | 644 | MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - |
68cdf5d6 | 645 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
646 | MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); |
647 | ||
648 | mlx5_fill_page_array(&rq->wq_ctrl.buf, | |
649 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
650 | ||
7db22ffb | 651 | err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); |
f62b8bb8 AV |
652 | |
653 | kvfree(in); | |
654 | ||
655 | return err; | |
656 | } | |
657 | ||
36350114 GP |
658 | static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, |
659 | int next_state) | |
f62b8bb8 | 660 | { |
7cbaf9a3 | 661 | struct mlx5_core_dev *mdev = rq->mdev; |
f62b8bb8 AV |
662 | |
663 | void *in; | |
664 | void *rqc; | |
665 | int inlen; | |
666 | int err; | |
667 | ||
668 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 669 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
670 | if (!in) |
671 | return -ENOMEM; | |
672 | ||
673 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
674 | ||
675 | MLX5_SET(modify_rq_in, in, rq_state, curr_state); | |
676 | MLX5_SET(rqc, rqc, state, next_state); | |
677 | ||
7db22ffb | 678 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); |
f62b8bb8 AV |
679 | |
680 | kvfree(in); | |
681 | ||
682 | return err; | |
683 | } | |
684 | ||
102722fc GE |
685 | static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable) |
686 | { | |
687 | struct mlx5e_channel *c = rq->channel; | |
688 | struct mlx5e_priv *priv = c->priv; | |
689 | struct mlx5_core_dev *mdev = priv->mdev; | |
690 | ||
691 | void *in; | |
692 | void *rqc; | |
693 | int inlen; | |
694 | int err; | |
695 | ||
696 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 697 | in = kvzalloc(inlen, GFP_KERNEL); |
102722fc GE |
698 | if (!in) |
699 | return -ENOMEM; | |
700 | ||
701 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
702 | ||
703 | MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); | |
704 | MLX5_SET64(modify_rq_in, in, modify_bitmask, | |
705 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS); | |
706 | MLX5_SET(rqc, rqc, scatter_fcs, enable); | |
707 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); | |
708 | ||
709 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); | |
710 | ||
711 | kvfree(in); | |
712 | ||
713 | return err; | |
714 | } | |
715 | ||
36350114 GP |
716 | static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd) |
717 | { | |
718 | struct mlx5e_channel *c = rq->channel; | |
a43b25da | 719 | struct mlx5_core_dev *mdev = c->mdev; |
36350114 GP |
720 | void *in; |
721 | void *rqc; | |
722 | int inlen; | |
723 | int err; | |
724 | ||
725 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 726 | in = kvzalloc(inlen, GFP_KERNEL); |
36350114 GP |
727 | if (!in) |
728 | return -ENOMEM; | |
729 | ||
730 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
731 | ||
732 | MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); | |
83b502a1 AV |
733 | MLX5_SET64(modify_rq_in, in, modify_bitmask, |
734 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); | |
36350114 GP |
735 | MLX5_SET(rqc, rqc, vsd, vsd); |
736 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); | |
737 | ||
738 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); | |
739 | ||
740 | kvfree(in); | |
741 | ||
742 | return err; | |
743 | } | |
744 | ||
3b77235b | 745 | static void mlx5e_destroy_rq(struct mlx5e_rq *rq) |
f62b8bb8 | 746 | { |
a43b25da | 747 | mlx5_core_destroy_rq(rq->mdev, rq->rqn); |
f62b8bb8 AV |
748 | } |
749 | ||
1e7477ae | 750 | static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time) |
f62b8bb8 | 751 | { |
1e7477ae | 752 | unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time); |
f62b8bb8 | 753 | struct mlx5e_channel *c = rq->channel; |
a43b25da | 754 | |
f62b8bb8 | 755 | struct mlx5_wq_ll *wq = &rq->wq; |
6a9764ef | 756 | u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq)); |
f62b8bb8 | 757 | |
1e7477ae | 758 | do { |
6a9764ef | 759 | if (wq->cur_sz >= min_wqes) |
f62b8bb8 AV |
760 | return 0; |
761 | ||
762 | msleep(20); | |
1e7477ae EBE |
763 | } while (time_before(jiffies, exp_time)); |
764 | ||
765 | netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n", | |
766 | c->ix, rq->rqn, wq->cur_sz, min_wqes); | |
f62b8bb8 AV |
767 | |
768 | return -ETIMEDOUT; | |
769 | } | |
770 | ||
f2fde18c SM |
771 | static void mlx5e_free_rx_descs(struct mlx5e_rq *rq) |
772 | { | |
773 | struct mlx5_wq_ll *wq = &rq->wq; | |
774 | struct mlx5e_rx_wqe *wqe; | |
775 | __be16 wqe_ix_be; | |
776 | u16 wqe_ix; | |
777 | ||
8484f9ed | 778 | /* UMR WQE (if in progress) is always at wq->head */ |
a071cb9f TT |
779 | if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ && |
780 | rq->mpwqe.umr_in_progress) | |
21c59685 | 781 | mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]); |
8484f9ed | 782 | |
f2fde18c SM |
783 | while (!mlx5_wq_ll_is_empty(wq)) { |
784 | wqe_ix_be = *wq->tail_next; | |
785 | wqe_ix = be16_to_cpu(wqe_ix_be); | |
786 | wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix); | |
787 | rq->dealloc_wqe(rq, wqe_ix); | |
788 | mlx5_wq_ll_pop(&rq->wq, wqe_ix_be, | |
789 | &wqe->next.next_wqe_index); | |
790 | } | |
accd5883 TT |
791 | |
792 | if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) { | |
793 | /* Clean outstanding pages on handled WQEs that decided to do page-reuse, | |
794 | * but yet to be re-posted. | |
795 | */ | |
796 | int wq_sz = mlx5_wq_ll_get_size(&rq->wq); | |
797 | ||
798 | for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++) | |
799 | rq->dealloc_wqe(rq, wqe_ix); | |
800 | } | |
f2fde18c SM |
801 | } |
802 | ||
f62b8bb8 | 803 | static int mlx5e_open_rq(struct mlx5e_channel *c, |
6a9764ef | 804 | struct mlx5e_params *params, |
f62b8bb8 AV |
805 | struct mlx5e_rq_param *param, |
806 | struct mlx5e_rq *rq) | |
807 | { | |
808 | int err; | |
809 | ||
6a9764ef | 810 | err = mlx5e_alloc_rq(c, params, param, rq); |
f62b8bb8 AV |
811 | if (err) |
812 | return err; | |
813 | ||
3b77235b | 814 | err = mlx5e_create_rq(rq, param); |
f62b8bb8 | 815 | if (err) |
3b77235b | 816 | goto err_free_rq; |
f62b8bb8 | 817 | |
36350114 | 818 | err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); |
f62b8bb8 | 819 | if (err) |
3b77235b | 820 | goto err_destroy_rq; |
f62b8bb8 | 821 | |
9a317425 | 822 | if (params->rx_dim_enabled) |
af5a6c93 | 823 | __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state); |
cb3c7fd4 | 824 | |
f62b8bb8 AV |
825 | return 0; |
826 | ||
f62b8bb8 AV |
827 | err_destroy_rq: |
828 | mlx5e_destroy_rq(rq); | |
3b77235b SM |
829 | err_free_rq: |
830 | mlx5e_free_rq(rq); | |
f62b8bb8 AV |
831 | |
832 | return err; | |
833 | } | |
834 | ||
acc6c595 SM |
835 | static void mlx5e_activate_rq(struct mlx5e_rq *rq) |
836 | { | |
837 | struct mlx5e_icosq *sq = &rq->channel->icosq; | |
838 | u16 pi = sq->pc & sq->wq.sz_m1; | |
839 | struct mlx5e_tx_wqe *nopwqe; | |
840 | ||
841 | set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); | |
842 | sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; | |
acc6c595 SM |
843 | nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc); |
844 | mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl); | |
845 | } | |
846 | ||
847 | static void mlx5e_deactivate_rq(struct mlx5e_rq *rq) | |
f62b8bb8 | 848 | { |
c0f1147d | 849 | clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); |
f62b8bb8 | 850 | napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */ |
acc6c595 | 851 | } |
cb3c7fd4 | 852 | |
acc6c595 SM |
853 | static void mlx5e_close_rq(struct mlx5e_rq *rq) |
854 | { | |
9a317425 | 855 | cancel_work_sync(&rq->dim.work); |
f62b8bb8 | 856 | mlx5e_destroy_rq(rq); |
3b77235b SM |
857 | mlx5e_free_rx_descs(rq); |
858 | mlx5e_free_rq(rq); | |
f62b8bb8 AV |
859 | } |
860 | ||
31391048 | 861 | static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq) |
b5503b99 | 862 | { |
31391048 | 863 | kfree(sq->db.di); |
b5503b99 SM |
864 | } |
865 | ||
31391048 | 866 | static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa) |
b5503b99 SM |
867 | { |
868 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
869 | ||
31391048 | 870 | sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz, |
b5503b99 | 871 | GFP_KERNEL, numa); |
31391048 SM |
872 | if (!sq->db.di) { |
873 | mlx5e_free_xdpsq_db(sq); | |
b5503b99 SM |
874 | return -ENOMEM; |
875 | } | |
876 | ||
877 | return 0; | |
878 | } | |
879 | ||
31391048 | 880 | static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c, |
6a9764ef | 881 | struct mlx5e_params *params, |
31391048 SM |
882 | struct mlx5e_sq_param *param, |
883 | struct mlx5e_xdpsq *sq) | |
884 | { | |
885 | void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); | |
a43b25da | 886 | struct mlx5_core_dev *mdev = c->mdev; |
31391048 SM |
887 | int err; |
888 | ||
889 | sq->pdev = c->pdev; | |
890 | sq->mkey_be = c->mkey_be; | |
891 | sq->channel = c; | |
892 | sq->uar_map = mdev->mlx5e_res.bfreg.map; | |
6a9764ef | 893 | sq->min_inline_mode = params->tx_min_inline_mode; |
31391048 | 894 | |
231243c8 | 895 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
31391048 SM |
896 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl); |
897 | if (err) | |
898 | return err; | |
899 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; | |
900 | ||
231243c8 | 901 | err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu)); |
31391048 SM |
902 | if (err) |
903 | goto err_sq_wq_destroy; | |
904 | ||
905 | return 0; | |
906 | ||
907 | err_sq_wq_destroy: | |
908 | mlx5_wq_destroy(&sq->wq_ctrl); | |
909 | ||
910 | return err; | |
911 | } | |
912 | ||
913 | static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq) | |
914 | { | |
915 | mlx5e_free_xdpsq_db(sq); | |
916 | mlx5_wq_destroy(&sq->wq_ctrl); | |
917 | } | |
918 | ||
919 | static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq) | |
f62b8bb8 | 920 | { |
f10b7cc7 | 921 | kfree(sq->db.ico_wqe); |
f62b8bb8 AV |
922 | } |
923 | ||
31391048 | 924 | static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa) |
f10b7cc7 SM |
925 | { |
926 | u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
927 | ||
928 | sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz, | |
929 | GFP_KERNEL, numa); | |
930 | if (!sq->db.ico_wqe) | |
931 | return -ENOMEM; | |
932 | ||
933 | return 0; | |
934 | } | |
935 | ||
31391048 | 936 | static int mlx5e_alloc_icosq(struct mlx5e_channel *c, |
31391048 SM |
937 | struct mlx5e_sq_param *param, |
938 | struct mlx5e_icosq *sq) | |
f10b7cc7 | 939 | { |
31391048 | 940 | void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); |
a43b25da | 941 | struct mlx5_core_dev *mdev = c->mdev; |
31391048 | 942 | int err; |
f10b7cc7 | 943 | |
31391048 SM |
944 | sq->channel = c; |
945 | sq->uar_map = mdev->mlx5e_res.bfreg.map; | |
f62b8bb8 | 946 | |
231243c8 | 947 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
31391048 SM |
948 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl); |
949 | if (err) | |
950 | return err; | |
951 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; | |
f62b8bb8 | 952 | |
231243c8 | 953 | err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu)); |
31391048 SM |
954 | if (err) |
955 | goto err_sq_wq_destroy; | |
956 | ||
957 | sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS; | |
f62b8bb8 AV |
958 | |
959 | return 0; | |
31391048 SM |
960 | |
961 | err_sq_wq_destroy: | |
962 | mlx5_wq_destroy(&sq->wq_ctrl); | |
963 | ||
964 | return err; | |
f62b8bb8 AV |
965 | } |
966 | ||
31391048 | 967 | static void mlx5e_free_icosq(struct mlx5e_icosq *sq) |
f10b7cc7 | 968 | { |
31391048 SM |
969 | mlx5e_free_icosq_db(sq); |
970 | mlx5_wq_destroy(&sq->wq_ctrl); | |
f10b7cc7 SM |
971 | } |
972 | ||
31391048 | 973 | static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq) |
f10b7cc7 | 974 | { |
31391048 SM |
975 | kfree(sq->db.wqe_info); |
976 | kfree(sq->db.dma_fifo); | |
f10b7cc7 SM |
977 | } |
978 | ||
31391048 | 979 | static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa) |
b5503b99 | 980 | { |
31391048 SM |
981 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); |
982 | int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS; | |
983 | ||
31391048 SM |
984 | sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo), |
985 | GFP_KERNEL, numa); | |
986 | sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info), | |
987 | GFP_KERNEL, numa); | |
77bdf895 | 988 | if (!sq->db.dma_fifo || !sq->db.wqe_info) { |
31391048 SM |
989 | mlx5e_free_txqsq_db(sq); |
990 | return -ENOMEM; | |
b5503b99 | 991 | } |
31391048 SM |
992 | |
993 | sq->dma_fifo_mask = df_sz - 1; | |
994 | ||
995 | return 0; | |
b5503b99 SM |
996 | } |
997 | ||
db75373c | 998 | static void mlx5e_sq_recover(struct work_struct *work); |
31391048 | 999 | static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, |
acc6c595 | 1000 | int txq_ix, |
6a9764ef | 1001 | struct mlx5e_params *params, |
31391048 SM |
1002 | struct mlx5e_sq_param *param, |
1003 | struct mlx5e_txqsq *sq) | |
f62b8bb8 | 1004 | { |
31391048 | 1005 | void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); |
a43b25da | 1006 | struct mlx5_core_dev *mdev = c->mdev; |
f62b8bb8 AV |
1007 | int err; |
1008 | ||
f10b7cc7 | 1009 | sq->pdev = c->pdev; |
a43b25da | 1010 | sq->tstamp = c->tstamp; |
7c39afb3 | 1011 | sq->clock = &mdev->clock; |
f10b7cc7 SM |
1012 | sq->mkey_be = c->mkey_be; |
1013 | sq->channel = c; | |
acc6c595 | 1014 | sq->txq_ix = txq_ix; |
aff26157 | 1015 | sq->uar_map = mdev->mlx5e_res.bfreg.map; |
6a9764ef | 1016 | sq->min_inline_mode = params->tx_min_inline_mode; |
db75373c | 1017 | INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover); |
2ac9cfe7 IT |
1018 | if (MLX5_IPSEC_DEV(c->priv->mdev)) |
1019 | set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state); | |
bf239741 IL |
1020 | if (mlx5_accel_is_tls_device(c->priv->mdev)) |
1021 | set_bit(MLX5E_SQ_STATE_TLS, &sq->state); | |
f10b7cc7 | 1022 | |
231243c8 | 1023 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
31391048 | 1024 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl); |
f62b8bb8 | 1025 | if (err) |
aff26157 | 1026 | return err; |
31391048 | 1027 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; |
f62b8bb8 | 1028 | |
231243c8 | 1029 | err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu)); |
7ec0bb22 | 1030 | if (err) |
f62b8bb8 AV |
1031 | goto err_sq_wq_destroy; |
1032 | ||
cbce4f44 TG |
1033 | INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work); |
1034 | sq->dim.mode = params->tx_cq_moderation.cq_period_mode; | |
1035 | ||
31391048 | 1036 | sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS; |
f62b8bb8 AV |
1037 | |
1038 | return 0; | |
1039 | ||
1040 | err_sq_wq_destroy: | |
1041 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1042 | ||
f62b8bb8 AV |
1043 | return err; |
1044 | } | |
1045 | ||
31391048 | 1046 | static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq) |
f62b8bb8 | 1047 | { |
31391048 | 1048 | mlx5e_free_txqsq_db(sq); |
f62b8bb8 | 1049 | mlx5_wq_destroy(&sq->wq_ctrl); |
f62b8bb8 AV |
1050 | } |
1051 | ||
33ad9711 SM |
1052 | struct mlx5e_create_sq_param { |
1053 | struct mlx5_wq_ctrl *wq_ctrl; | |
1054 | u32 cqn; | |
1055 | u32 tisn; | |
1056 | u8 tis_lst_sz; | |
1057 | u8 min_inline_mode; | |
1058 | }; | |
1059 | ||
a43b25da | 1060 | static int mlx5e_create_sq(struct mlx5_core_dev *mdev, |
33ad9711 SM |
1061 | struct mlx5e_sq_param *param, |
1062 | struct mlx5e_create_sq_param *csp, | |
1063 | u32 *sqn) | |
f62b8bb8 | 1064 | { |
f62b8bb8 AV |
1065 | void *in; |
1066 | void *sqc; | |
1067 | void *wq; | |
1068 | int inlen; | |
1069 | int err; | |
1070 | ||
1071 | inlen = MLX5_ST_SZ_BYTES(create_sq_in) + | |
33ad9711 | 1072 | sizeof(u64) * csp->wq_ctrl->buf.npages; |
1b9a07ee | 1073 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
1074 | if (!in) |
1075 | return -ENOMEM; | |
1076 | ||
1077 | sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); | |
1078 | wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1079 | ||
1080 | memcpy(sqc, param->sqc, sizeof(param->sqc)); | |
33ad9711 SM |
1081 | MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz); |
1082 | MLX5_SET(sqc, sqc, tis_num_0, csp->tisn); | |
1083 | MLX5_SET(sqc, sqc, cqn, csp->cqn); | |
a6f402e4 SM |
1084 | |
1085 | if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) | |
33ad9711 | 1086 | MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode); |
a6f402e4 | 1087 | |
33ad9711 | 1088 | MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); |
db75373c | 1089 | MLX5_SET(sqc, sqc, flush_in_error_en, 1); |
f62b8bb8 AV |
1090 | |
1091 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
a43b25da | 1092 | MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index); |
33ad9711 | 1093 | MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift - |
68cdf5d6 | 1094 | MLX5_ADAPTER_PAGE_SHIFT); |
33ad9711 | 1095 | MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma); |
f62b8bb8 | 1096 | |
33ad9711 | 1097 | mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); |
f62b8bb8 | 1098 | |
33ad9711 | 1099 | err = mlx5_core_create_sq(mdev, in, inlen, sqn); |
f62b8bb8 AV |
1100 | |
1101 | kvfree(in); | |
1102 | ||
1103 | return err; | |
1104 | } | |
1105 | ||
33ad9711 SM |
1106 | struct mlx5e_modify_sq_param { |
1107 | int curr_state; | |
1108 | int next_state; | |
1109 | bool rl_update; | |
1110 | int rl_index; | |
1111 | }; | |
1112 | ||
a43b25da | 1113 | static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, |
33ad9711 | 1114 | struct mlx5e_modify_sq_param *p) |
f62b8bb8 | 1115 | { |
f62b8bb8 AV |
1116 | void *in; |
1117 | void *sqc; | |
1118 | int inlen; | |
1119 | int err; | |
1120 | ||
1121 | inlen = MLX5_ST_SZ_BYTES(modify_sq_in); | |
1b9a07ee | 1122 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
1123 | if (!in) |
1124 | return -ENOMEM; | |
1125 | ||
1126 | sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); | |
1127 | ||
33ad9711 SM |
1128 | MLX5_SET(modify_sq_in, in, sq_state, p->curr_state); |
1129 | MLX5_SET(sqc, sqc, state, p->next_state); | |
1130 | if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) { | |
507f0c81 | 1131 | MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); |
33ad9711 | 1132 | MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index); |
507f0c81 | 1133 | } |
f62b8bb8 | 1134 | |
33ad9711 | 1135 | err = mlx5_core_modify_sq(mdev, sqn, in, inlen); |
f62b8bb8 AV |
1136 | |
1137 | kvfree(in); | |
1138 | ||
1139 | return err; | |
1140 | } | |
1141 | ||
a43b25da | 1142 | static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn) |
33ad9711 | 1143 | { |
a43b25da | 1144 | mlx5_core_destroy_sq(mdev, sqn); |
f62b8bb8 AV |
1145 | } |
1146 | ||
a43b25da | 1147 | static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, |
31391048 SM |
1148 | struct mlx5e_sq_param *param, |
1149 | struct mlx5e_create_sq_param *csp, | |
1150 | u32 *sqn) | |
f62b8bb8 | 1151 | { |
33ad9711 | 1152 | struct mlx5e_modify_sq_param msp = {0}; |
31391048 SM |
1153 | int err; |
1154 | ||
a43b25da | 1155 | err = mlx5e_create_sq(mdev, param, csp, sqn); |
31391048 SM |
1156 | if (err) |
1157 | return err; | |
1158 | ||
1159 | msp.curr_state = MLX5_SQC_STATE_RST; | |
1160 | msp.next_state = MLX5_SQC_STATE_RDY; | |
a43b25da | 1161 | err = mlx5e_modify_sq(mdev, *sqn, &msp); |
31391048 | 1162 | if (err) |
a43b25da | 1163 | mlx5e_destroy_sq(mdev, *sqn); |
31391048 SM |
1164 | |
1165 | return err; | |
1166 | } | |
1167 | ||
7f859ecf SM |
1168 | static int mlx5e_set_sq_maxrate(struct net_device *dev, |
1169 | struct mlx5e_txqsq *sq, u32 rate); | |
1170 | ||
31391048 | 1171 | static int mlx5e_open_txqsq(struct mlx5e_channel *c, |
a43b25da | 1172 | u32 tisn, |
acc6c595 | 1173 | int txq_ix, |
6a9764ef | 1174 | struct mlx5e_params *params, |
31391048 SM |
1175 | struct mlx5e_sq_param *param, |
1176 | struct mlx5e_txqsq *sq) | |
1177 | { | |
1178 | struct mlx5e_create_sq_param csp = {}; | |
7f859ecf | 1179 | u32 tx_rate; |
f62b8bb8 AV |
1180 | int err; |
1181 | ||
6a9764ef | 1182 | err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq); |
f62b8bb8 AV |
1183 | if (err) |
1184 | return err; | |
1185 | ||
a43b25da | 1186 | csp.tisn = tisn; |
31391048 | 1187 | csp.tis_lst_sz = 1; |
33ad9711 SM |
1188 | csp.cqn = sq->cq.mcq.cqn; |
1189 | csp.wq_ctrl = &sq->wq_ctrl; | |
1190 | csp.min_inline_mode = sq->min_inline_mode; | |
a43b25da | 1191 | err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn); |
f62b8bb8 | 1192 | if (err) |
31391048 | 1193 | goto err_free_txqsq; |
f62b8bb8 | 1194 | |
a43b25da | 1195 | tx_rate = c->priv->tx_rates[sq->txq_ix]; |
7f859ecf | 1196 | if (tx_rate) |
a43b25da | 1197 | mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate); |
7f859ecf | 1198 | |
cbce4f44 TG |
1199 | if (params->tx_dim_enabled) |
1200 | sq->state |= BIT(MLX5E_SQ_STATE_AM); | |
1201 | ||
f62b8bb8 AV |
1202 | return 0; |
1203 | ||
31391048 | 1204 | err_free_txqsq: |
3b77235b | 1205 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
31391048 | 1206 | mlx5e_free_txqsq(sq); |
f62b8bb8 AV |
1207 | |
1208 | return err; | |
1209 | } | |
1210 | ||
db75373c EBE |
1211 | static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq) |
1212 | { | |
1213 | WARN_ONCE(sq->cc != sq->pc, | |
1214 | "SQ 0x%x: cc (0x%x) != pc (0x%x)\n", | |
1215 | sq->sqn, sq->cc, sq->pc); | |
1216 | sq->cc = 0; | |
1217 | sq->dma_fifo_cc = 0; | |
1218 | sq->pc = 0; | |
1219 | } | |
1220 | ||
acc6c595 SM |
1221 | static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq) |
1222 | { | |
a43b25da | 1223 | sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix); |
db75373c | 1224 | clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state); |
acc6c595 SM |
1225 | set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
1226 | netdev_tx_reset_queue(sq->txq); | |
1227 | netif_tx_start_queue(sq->txq); | |
1228 | } | |
1229 | ||
f62b8bb8 AV |
1230 | static inline void netif_tx_disable_queue(struct netdev_queue *txq) |
1231 | { | |
1232 | __netif_tx_lock_bh(txq); | |
1233 | netif_tx_stop_queue(txq); | |
1234 | __netif_tx_unlock_bh(txq); | |
1235 | } | |
1236 | ||
acc6c595 | 1237 | static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq) |
f62b8bb8 | 1238 | { |
33ad9711 | 1239 | struct mlx5e_channel *c = sq->channel; |
33ad9711 | 1240 | |
c0f1147d | 1241 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
6e8dd6d6 | 1242 | /* prevent netif_tx_wake_queue */ |
33ad9711 | 1243 | napi_synchronize(&c->napi); |
29429f33 | 1244 | |
31391048 | 1245 | netif_tx_disable_queue(sq->txq); |
f62b8bb8 | 1246 | |
31391048 SM |
1247 | /* last doorbell out, godspeed .. */ |
1248 | if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) { | |
1249 | struct mlx5e_tx_wqe *nop; | |
864b2d71 | 1250 | |
77bdf895 | 1251 | sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL; |
31391048 SM |
1252 | nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc); |
1253 | mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl); | |
29429f33 | 1254 | } |
acc6c595 SM |
1255 | } |
1256 | ||
1257 | static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq) | |
1258 | { | |
1259 | struct mlx5e_channel *c = sq->channel; | |
a43b25da | 1260 | struct mlx5_core_dev *mdev = c->mdev; |
05d3ac97 | 1261 | struct mlx5_rate_limit rl = {0}; |
f62b8bb8 | 1262 | |
a43b25da | 1263 | mlx5e_destroy_sq(mdev, sq->sqn); |
05d3ac97 BW |
1264 | if (sq->rate_limit) { |
1265 | rl.rate = sq->rate_limit; | |
1266 | mlx5_rl_remove_rate(mdev, &rl); | |
1267 | } | |
31391048 SM |
1268 | mlx5e_free_txqsq_descs(sq); |
1269 | mlx5e_free_txqsq(sq); | |
1270 | } | |
1271 | ||
db75373c EBE |
1272 | static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq) |
1273 | { | |
1274 | unsigned long exp_time = jiffies + msecs_to_jiffies(2000); | |
1275 | ||
1276 | while (time_before(jiffies, exp_time)) { | |
1277 | if (sq->cc == sq->pc) | |
1278 | return 0; | |
1279 | ||
1280 | msleep(20); | |
1281 | } | |
1282 | ||
1283 | netdev_err(sq->channel->netdev, | |
1284 | "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n", | |
1285 | sq->sqn, sq->cc, sq->pc); | |
1286 | ||
1287 | return -ETIMEDOUT; | |
1288 | } | |
1289 | ||
1290 | static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state) | |
1291 | { | |
1292 | struct mlx5_core_dev *mdev = sq->channel->mdev; | |
1293 | struct net_device *dev = sq->channel->netdev; | |
1294 | struct mlx5e_modify_sq_param msp = {0}; | |
1295 | int err; | |
1296 | ||
1297 | msp.curr_state = curr_state; | |
1298 | msp.next_state = MLX5_SQC_STATE_RST; | |
1299 | ||
1300 | err = mlx5e_modify_sq(mdev, sq->sqn, &msp); | |
1301 | if (err) { | |
1302 | netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn); | |
1303 | return err; | |
1304 | } | |
1305 | ||
1306 | memset(&msp, 0, sizeof(msp)); | |
1307 | msp.curr_state = MLX5_SQC_STATE_RST; | |
1308 | msp.next_state = MLX5_SQC_STATE_RDY; | |
1309 | ||
1310 | err = mlx5e_modify_sq(mdev, sq->sqn, &msp); | |
1311 | if (err) { | |
1312 | netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn); | |
1313 | return err; | |
1314 | } | |
1315 | ||
1316 | return 0; | |
1317 | } | |
1318 | ||
1319 | static void mlx5e_sq_recover(struct work_struct *work) | |
1320 | { | |
1321 | struct mlx5e_txqsq_recover *recover = | |
1322 | container_of(work, struct mlx5e_txqsq_recover, | |
1323 | recover_work); | |
1324 | struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq, | |
1325 | recover); | |
1326 | struct mlx5_core_dev *mdev = sq->channel->mdev; | |
1327 | struct net_device *dev = sq->channel->netdev; | |
1328 | u8 state; | |
1329 | int err; | |
1330 | ||
1331 | err = mlx5_core_query_sq_state(mdev, sq->sqn, &state); | |
1332 | if (err) { | |
1333 | netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n", | |
1334 | sq->sqn, err); | |
1335 | return; | |
1336 | } | |
1337 | ||
1338 | if (state != MLX5_RQC_STATE_ERR) { | |
1339 | netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn); | |
1340 | return; | |
1341 | } | |
1342 | ||
1343 | netif_tx_disable_queue(sq->txq); | |
1344 | ||
1345 | if (mlx5e_wait_for_sq_flush(sq)) | |
1346 | return; | |
1347 | ||
1348 | /* If the interval between two consecutive recovers per SQ is too | |
1349 | * short, don't recover to avoid infinite loop of ERR_CQE -> recover. | |
1350 | * If we reached this state, there is probably a bug that needs to be | |
1351 | * fixed. let's keep the queue close and let tx timeout cleanup. | |
1352 | */ | |
1353 | if (jiffies_to_msecs(jiffies - recover->last_recover) < | |
1354 | MLX5E_SQ_RECOVER_MIN_INTERVAL) { | |
1355 | netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n", | |
1356 | sq->sqn); | |
1357 | return; | |
1358 | } | |
1359 | ||
1360 | /* At this point, no new packets will arrive from the stack as TXQ is | |
1361 | * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all | |
1362 | * pending WQEs. SQ can safely reset the SQ. | |
1363 | */ | |
1364 | if (mlx5e_sq_to_ready(sq, state)) | |
1365 | return; | |
1366 | ||
1367 | mlx5e_reset_txqsq_cc_pc(sq); | |
1368 | sq->stats.recover++; | |
1369 | recover->last_recover = jiffies; | |
1370 | mlx5e_activate_txqsq(sq); | |
1371 | } | |
1372 | ||
31391048 | 1373 | static int mlx5e_open_icosq(struct mlx5e_channel *c, |
6a9764ef | 1374 | struct mlx5e_params *params, |
31391048 SM |
1375 | struct mlx5e_sq_param *param, |
1376 | struct mlx5e_icosq *sq) | |
1377 | { | |
1378 | struct mlx5e_create_sq_param csp = {}; | |
1379 | int err; | |
1380 | ||
6a9764ef | 1381 | err = mlx5e_alloc_icosq(c, param, sq); |
31391048 SM |
1382 | if (err) |
1383 | return err; | |
1384 | ||
1385 | csp.cqn = sq->cq.mcq.cqn; | |
1386 | csp.wq_ctrl = &sq->wq_ctrl; | |
6a9764ef | 1387 | csp.min_inline_mode = params->tx_min_inline_mode; |
31391048 | 1388 | set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
a43b25da | 1389 | err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn); |
31391048 SM |
1390 | if (err) |
1391 | goto err_free_icosq; | |
1392 | ||
1393 | return 0; | |
1394 | ||
1395 | err_free_icosq: | |
1396 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1397 | mlx5e_free_icosq(sq); | |
1398 | ||
1399 | return err; | |
1400 | } | |
1401 | ||
1402 | static void mlx5e_close_icosq(struct mlx5e_icosq *sq) | |
1403 | { | |
1404 | struct mlx5e_channel *c = sq->channel; | |
1405 | ||
1406 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1407 | napi_synchronize(&c->napi); | |
1408 | ||
a43b25da | 1409 | mlx5e_destroy_sq(c->mdev, sq->sqn); |
31391048 SM |
1410 | mlx5e_free_icosq(sq); |
1411 | } | |
1412 | ||
1413 | static int mlx5e_open_xdpsq(struct mlx5e_channel *c, | |
6a9764ef | 1414 | struct mlx5e_params *params, |
31391048 SM |
1415 | struct mlx5e_sq_param *param, |
1416 | struct mlx5e_xdpsq *sq) | |
1417 | { | |
1418 | unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT; | |
1419 | struct mlx5e_create_sq_param csp = {}; | |
31391048 SM |
1420 | unsigned int inline_hdr_sz = 0; |
1421 | int err; | |
1422 | int i; | |
1423 | ||
6a9764ef | 1424 | err = mlx5e_alloc_xdpsq(c, params, param, sq); |
31391048 SM |
1425 | if (err) |
1426 | return err; | |
1427 | ||
1428 | csp.tis_lst_sz = 1; | |
a43b25da | 1429 | csp.tisn = c->priv->tisn[0]; /* tc = 0 */ |
31391048 SM |
1430 | csp.cqn = sq->cq.mcq.cqn; |
1431 | csp.wq_ctrl = &sq->wq_ctrl; | |
1432 | csp.min_inline_mode = sq->min_inline_mode; | |
1433 | set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
a43b25da | 1434 | err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn); |
31391048 SM |
1435 | if (err) |
1436 | goto err_free_xdpsq; | |
1437 | ||
1438 | if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { | |
1439 | inline_hdr_sz = MLX5E_XDP_MIN_INLINE; | |
1440 | ds_cnt++; | |
1441 | } | |
1442 | ||
1443 | /* Pre initialize fixed WQE fields */ | |
1444 | for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) { | |
1445 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i); | |
1446 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
1447 | struct mlx5_wqe_eth_seg *eseg = &wqe->eth; | |
1448 | struct mlx5_wqe_data_seg *dseg; | |
1449 | ||
1450 | cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt); | |
1451 | eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz); | |
1452 | ||
1453 | dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1); | |
1454 | dseg->lkey = sq->mkey_be; | |
1455 | } | |
1456 | ||
1457 | return 0; | |
1458 | ||
1459 | err_free_xdpsq: | |
1460 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1461 | mlx5e_free_xdpsq(sq); | |
1462 | ||
1463 | return err; | |
1464 | } | |
1465 | ||
1466 | static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq) | |
1467 | { | |
1468 | struct mlx5e_channel *c = sq->channel; | |
1469 | ||
1470 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1471 | napi_synchronize(&c->napi); | |
1472 | ||
a43b25da | 1473 | mlx5e_destroy_sq(c->mdev, sq->sqn); |
31391048 SM |
1474 | mlx5e_free_xdpsq_descs(sq); |
1475 | mlx5e_free_xdpsq(sq); | |
f62b8bb8 AV |
1476 | } |
1477 | ||
95b6c6a5 EBE |
1478 | static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev, |
1479 | struct mlx5e_cq_param *param, | |
1480 | struct mlx5e_cq *cq) | |
f62b8bb8 | 1481 | { |
f62b8bb8 AV |
1482 | struct mlx5_core_cq *mcq = &cq->mcq; |
1483 | int eqn_not_used; | |
0b6e26ce | 1484 | unsigned int irqn; |
f62b8bb8 AV |
1485 | int err; |
1486 | u32 i; | |
1487 | ||
f62b8bb8 AV |
1488 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, |
1489 | &cq->wq_ctrl); | |
1490 | if (err) | |
1491 | return err; | |
1492 | ||
1493 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); | |
1494 | ||
f62b8bb8 AV |
1495 | mcq->cqe_sz = 64; |
1496 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
1497 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
1498 | *mcq->set_ci_db = 0; | |
1499 | *mcq->arm_db = 0; | |
1500 | mcq->vector = param->eq_ix; | |
1501 | mcq->comp = mlx5e_completion_event; | |
1502 | mcq->event = mlx5e_cq_error_event; | |
1503 | mcq->irqn = irqn; | |
f62b8bb8 AV |
1504 | |
1505 | for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { | |
1506 | struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); | |
1507 | ||
1508 | cqe->op_own = 0xf1; | |
1509 | } | |
1510 | ||
a43b25da | 1511 | cq->mdev = mdev; |
f62b8bb8 AV |
1512 | |
1513 | return 0; | |
1514 | } | |
1515 | ||
95b6c6a5 EBE |
1516 | static int mlx5e_alloc_cq(struct mlx5e_channel *c, |
1517 | struct mlx5e_cq_param *param, | |
1518 | struct mlx5e_cq *cq) | |
1519 | { | |
1520 | struct mlx5_core_dev *mdev = c->priv->mdev; | |
1521 | int err; | |
1522 | ||
231243c8 SM |
1523 | param->wq.buf_numa_node = cpu_to_node(c->cpu); |
1524 | param->wq.db_numa_node = cpu_to_node(c->cpu); | |
95b6c6a5 EBE |
1525 | param->eq_ix = c->ix; |
1526 | ||
1527 | err = mlx5e_alloc_cq_common(mdev, param, cq); | |
1528 | ||
1529 | cq->napi = &c->napi; | |
1530 | cq->channel = c; | |
1531 | ||
1532 | return err; | |
1533 | } | |
1534 | ||
3b77235b | 1535 | static void mlx5e_free_cq(struct mlx5e_cq *cq) |
f62b8bb8 | 1536 | { |
1c1b5228 | 1537 | mlx5_cqwq_destroy(&cq->wq_ctrl); |
f62b8bb8 AV |
1538 | } |
1539 | ||
3b77235b | 1540 | static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) |
f62b8bb8 | 1541 | { |
a43b25da | 1542 | struct mlx5_core_dev *mdev = cq->mdev; |
f62b8bb8 AV |
1543 | struct mlx5_core_cq *mcq = &cq->mcq; |
1544 | ||
1545 | void *in; | |
1546 | void *cqc; | |
1547 | int inlen; | |
0b6e26ce | 1548 | unsigned int irqn_not_used; |
f62b8bb8 AV |
1549 | int eqn; |
1550 | int err; | |
1551 | ||
1552 | inlen = MLX5_ST_SZ_BYTES(create_cq_in) + | |
1c1b5228 | 1553 | sizeof(u64) * cq->wq_ctrl.frag_buf.npages; |
1b9a07ee | 1554 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
1555 | if (!in) |
1556 | return -ENOMEM; | |
1557 | ||
1558 | cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); | |
1559 | ||
1560 | memcpy(cqc, param->cqc, sizeof(param->cqc)); | |
1561 | ||
1c1b5228 TT |
1562 | mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf, |
1563 | (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas)); | |
f62b8bb8 AV |
1564 | |
1565 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used); | |
1566 | ||
9908aa29 | 1567 | MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode); |
f62b8bb8 | 1568 | MLX5_SET(cqc, cqc, c_eqn, eqn); |
30aa60b3 | 1569 | MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index); |
1c1b5228 | 1570 | MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift - |
68cdf5d6 | 1571 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
1572 | MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); |
1573 | ||
1574 | err = mlx5_core_create_cq(mdev, mcq, in, inlen); | |
1575 | ||
1576 | kvfree(in); | |
1577 | ||
1578 | if (err) | |
1579 | return err; | |
1580 | ||
1581 | mlx5e_cq_arm(cq); | |
1582 | ||
1583 | return 0; | |
1584 | } | |
1585 | ||
3b77235b | 1586 | static void mlx5e_destroy_cq(struct mlx5e_cq *cq) |
f62b8bb8 | 1587 | { |
a43b25da | 1588 | mlx5_core_destroy_cq(cq->mdev, &cq->mcq); |
f62b8bb8 AV |
1589 | } |
1590 | ||
1591 | static int mlx5e_open_cq(struct mlx5e_channel *c, | |
9a317425 | 1592 | struct net_dim_cq_moder moder, |
f62b8bb8 | 1593 | struct mlx5e_cq_param *param, |
6a9764ef | 1594 | struct mlx5e_cq *cq) |
f62b8bb8 | 1595 | { |
a43b25da | 1596 | struct mlx5_core_dev *mdev = c->mdev; |
f62b8bb8 | 1597 | int err; |
f62b8bb8 | 1598 | |
3b77235b | 1599 | err = mlx5e_alloc_cq(c, param, cq); |
f62b8bb8 AV |
1600 | if (err) |
1601 | return err; | |
1602 | ||
3b77235b | 1603 | err = mlx5e_create_cq(cq, param); |
f62b8bb8 | 1604 | if (err) |
3b77235b | 1605 | goto err_free_cq; |
f62b8bb8 | 1606 | |
7524a5d8 | 1607 | if (MLX5_CAP_GEN(mdev, cq_moderation)) |
6a9764ef | 1608 | mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts); |
f62b8bb8 AV |
1609 | return 0; |
1610 | ||
3b77235b SM |
1611 | err_free_cq: |
1612 | mlx5e_free_cq(cq); | |
f62b8bb8 AV |
1613 | |
1614 | return err; | |
1615 | } | |
1616 | ||
1617 | static void mlx5e_close_cq(struct mlx5e_cq *cq) | |
1618 | { | |
f62b8bb8 | 1619 | mlx5e_destroy_cq(cq); |
3b77235b | 1620 | mlx5e_free_cq(cq); |
f62b8bb8 AV |
1621 | } |
1622 | ||
231243c8 SM |
1623 | static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix) |
1624 | { | |
1625 | return cpumask_first(priv->mdev->priv.irq_info[ix].mask); | |
1626 | } | |
1627 | ||
f62b8bb8 | 1628 | static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, |
6a9764ef | 1629 | struct mlx5e_params *params, |
f62b8bb8 AV |
1630 | struct mlx5e_channel_param *cparam) |
1631 | { | |
f62b8bb8 AV |
1632 | int err; |
1633 | int tc; | |
1634 | ||
1635 | for (tc = 0; tc < c->num_tc; tc++) { | |
6a9764ef SM |
1636 | err = mlx5e_open_cq(c, params->tx_cq_moderation, |
1637 | &cparam->tx_cq, &c->sq[tc].cq); | |
f62b8bb8 AV |
1638 | if (err) |
1639 | goto err_close_tx_cqs; | |
f62b8bb8 AV |
1640 | } |
1641 | ||
1642 | return 0; | |
1643 | ||
1644 | err_close_tx_cqs: | |
1645 | for (tc--; tc >= 0; tc--) | |
1646 | mlx5e_close_cq(&c->sq[tc].cq); | |
1647 | ||
1648 | return err; | |
1649 | } | |
1650 | ||
1651 | static void mlx5e_close_tx_cqs(struct mlx5e_channel *c) | |
1652 | { | |
1653 | int tc; | |
1654 | ||
1655 | for (tc = 0; tc < c->num_tc; tc++) | |
1656 | mlx5e_close_cq(&c->sq[tc].cq); | |
1657 | } | |
1658 | ||
1659 | static int mlx5e_open_sqs(struct mlx5e_channel *c, | |
6a9764ef | 1660 | struct mlx5e_params *params, |
f62b8bb8 AV |
1661 | struct mlx5e_channel_param *cparam) |
1662 | { | |
1663 | int err; | |
1664 | int tc; | |
1665 | ||
6a9764ef SM |
1666 | for (tc = 0; tc < params->num_tc; tc++) { |
1667 | int txq_ix = c->ix + tc * params->num_channels; | |
acc6c595 | 1668 | |
a43b25da SM |
1669 | err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix, |
1670 | params, &cparam->sq, &c->sq[tc]); | |
f62b8bb8 AV |
1671 | if (err) |
1672 | goto err_close_sqs; | |
1673 | } | |
1674 | ||
1675 | return 0; | |
1676 | ||
1677 | err_close_sqs: | |
1678 | for (tc--; tc >= 0; tc--) | |
31391048 | 1679 | mlx5e_close_txqsq(&c->sq[tc]); |
f62b8bb8 AV |
1680 | |
1681 | return err; | |
1682 | } | |
1683 | ||
1684 | static void mlx5e_close_sqs(struct mlx5e_channel *c) | |
1685 | { | |
1686 | int tc; | |
1687 | ||
1688 | for (tc = 0; tc < c->num_tc; tc++) | |
31391048 | 1689 | mlx5e_close_txqsq(&c->sq[tc]); |
f62b8bb8 AV |
1690 | } |
1691 | ||
507f0c81 | 1692 | static int mlx5e_set_sq_maxrate(struct net_device *dev, |
31391048 | 1693 | struct mlx5e_txqsq *sq, u32 rate) |
507f0c81 YP |
1694 | { |
1695 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1696 | struct mlx5_core_dev *mdev = priv->mdev; | |
33ad9711 | 1697 | struct mlx5e_modify_sq_param msp = {0}; |
05d3ac97 | 1698 | struct mlx5_rate_limit rl = {0}; |
507f0c81 YP |
1699 | u16 rl_index = 0; |
1700 | int err; | |
1701 | ||
1702 | if (rate == sq->rate_limit) | |
1703 | /* nothing to do */ | |
1704 | return 0; | |
1705 | ||
05d3ac97 BW |
1706 | if (sq->rate_limit) { |
1707 | rl.rate = sq->rate_limit; | |
507f0c81 | 1708 | /* remove current rl index to free space to next ones */ |
05d3ac97 BW |
1709 | mlx5_rl_remove_rate(mdev, &rl); |
1710 | } | |
507f0c81 YP |
1711 | |
1712 | sq->rate_limit = 0; | |
1713 | ||
1714 | if (rate) { | |
05d3ac97 BW |
1715 | rl.rate = rate; |
1716 | err = mlx5_rl_add_rate(mdev, &rl_index, &rl); | |
507f0c81 YP |
1717 | if (err) { |
1718 | netdev_err(dev, "Failed configuring rate %u: %d\n", | |
1719 | rate, err); | |
1720 | return err; | |
1721 | } | |
1722 | } | |
1723 | ||
33ad9711 SM |
1724 | msp.curr_state = MLX5_SQC_STATE_RDY; |
1725 | msp.next_state = MLX5_SQC_STATE_RDY; | |
1726 | msp.rl_index = rl_index; | |
1727 | msp.rl_update = true; | |
a43b25da | 1728 | err = mlx5e_modify_sq(mdev, sq->sqn, &msp); |
507f0c81 YP |
1729 | if (err) { |
1730 | netdev_err(dev, "Failed configuring rate %u: %d\n", | |
1731 | rate, err); | |
1732 | /* remove the rate from the table */ | |
1733 | if (rate) | |
05d3ac97 | 1734 | mlx5_rl_remove_rate(mdev, &rl); |
507f0c81 YP |
1735 | return err; |
1736 | } | |
1737 | ||
1738 | sq->rate_limit = rate; | |
1739 | return 0; | |
1740 | } | |
1741 | ||
1742 | static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate) | |
1743 | { | |
1744 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1745 | struct mlx5_core_dev *mdev = priv->mdev; | |
acc6c595 | 1746 | struct mlx5e_txqsq *sq = priv->txq2sq[index]; |
507f0c81 YP |
1747 | int err = 0; |
1748 | ||
1749 | if (!mlx5_rl_is_supported(mdev)) { | |
1750 | netdev_err(dev, "Rate limiting is not supported on this device\n"); | |
1751 | return -EINVAL; | |
1752 | } | |
1753 | ||
1754 | /* rate is given in Mb/sec, HW config is in Kb/sec */ | |
1755 | rate = rate << 10; | |
1756 | ||
1757 | /* Check whether rate in valid range, 0 is always valid */ | |
1758 | if (rate && !mlx5_rl_is_in_range(mdev, rate)) { | |
1759 | netdev_err(dev, "TX rate %u, is not in range\n", rate); | |
1760 | return -ERANGE; | |
1761 | } | |
1762 | ||
1763 | mutex_lock(&priv->state_lock); | |
1764 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
1765 | err = mlx5e_set_sq_maxrate(dev, sq, rate); | |
1766 | if (!err) | |
1767 | priv->tx_rates[index] = rate; | |
1768 | mutex_unlock(&priv->state_lock); | |
1769 | ||
1770 | return err; | |
1771 | } | |
1772 | ||
f62b8bb8 | 1773 | static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, |
6a9764ef | 1774 | struct mlx5e_params *params, |
f62b8bb8 AV |
1775 | struct mlx5e_channel_param *cparam, |
1776 | struct mlx5e_channel **cp) | |
1777 | { | |
9a317425 | 1778 | struct net_dim_cq_moder icocq_moder = {0, 0}; |
f62b8bb8 | 1779 | struct net_device *netdev = priv->netdev; |
231243c8 | 1780 | int cpu = mlx5e_get_cpu(priv, ix); |
f62b8bb8 | 1781 | struct mlx5e_channel *c; |
a8c2eb15 | 1782 | unsigned int irq; |
f62b8bb8 | 1783 | int err; |
a8c2eb15 | 1784 | int eqn; |
f62b8bb8 | 1785 | |
231243c8 | 1786 | c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu)); |
f62b8bb8 AV |
1787 | if (!c) |
1788 | return -ENOMEM; | |
1789 | ||
1790 | c->priv = priv; | |
a43b25da SM |
1791 | c->mdev = priv->mdev; |
1792 | c->tstamp = &priv->tstamp; | |
f62b8bb8 | 1793 | c->ix = ix; |
231243c8 | 1794 | c->cpu = cpu; |
f62b8bb8 AV |
1795 | c->pdev = &priv->mdev->pdev->dev; |
1796 | c->netdev = priv->netdev; | |
b50d292b | 1797 | c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key); |
6a9764ef SM |
1798 | c->num_tc = params->num_tc; |
1799 | c->xdp = !!params->xdp_prog; | |
cb3c7fd4 | 1800 | |
a8c2eb15 TT |
1801 | mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq); |
1802 | c->irq_desc = irq_to_desc(irq); | |
1803 | ||
f62b8bb8 AV |
1804 | netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64); |
1805 | ||
6a9764ef | 1806 | err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq); |
f62b8bb8 AV |
1807 | if (err) |
1808 | goto err_napi_del; | |
1809 | ||
6a9764ef | 1810 | err = mlx5e_open_tx_cqs(c, params, cparam); |
d3c9bc27 TT |
1811 | if (err) |
1812 | goto err_close_icosq_cq; | |
1813 | ||
6a9764ef | 1814 | err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq); |
f62b8bb8 AV |
1815 | if (err) |
1816 | goto err_close_tx_cqs; | |
f62b8bb8 | 1817 | |
d7a0ecab | 1818 | /* XDP SQ CQ params are same as normal TXQ sq CQ params */ |
6a9764ef SM |
1819 | err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation, |
1820 | &cparam->tx_cq, &c->rq.xdpsq.cq) : 0; | |
d7a0ecab SM |
1821 | if (err) |
1822 | goto err_close_rx_cq; | |
1823 | ||
f62b8bb8 AV |
1824 | napi_enable(&c->napi); |
1825 | ||
6a9764ef | 1826 | err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq); |
f62b8bb8 AV |
1827 | if (err) |
1828 | goto err_disable_napi; | |
1829 | ||
6a9764ef | 1830 | err = mlx5e_open_sqs(c, params, cparam); |
d3c9bc27 TT |
1831 | if (err) |
1832 | goto err_close_icosq; | |
1833 | ||
6a9764ef | 1834 | err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0; |
d7a0ecab SM |
1835 | if (err) |
1836 | goto err_close_sqs; | |
b5503b99 | 1837 | |
6a9764ef | 1838 | err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq); |
f62b8bb8 | 1839 | if (err) |
b5503b99 | 1840 | goto err_close_xdp_sq; |
f62b8bb8 | 1841 | |
f62b8bb8 AV |
1842 | *cp = c; |
1843 | ||
1844 | return 0; | |
b5503b99 | 1845 | err_close_xdp_sq: |
d7a0ecab | 1846 | if (c->xdp) |
31391048 | 1847 | mlx5e_close_xdpsq(&c->rq.xdpsq); |
f62b8bb8 AV |
1848 | |
1849 | err_close_sqs: | |
1850 | mlx5e_close_sqs(c); | |
1851 | ||
d3c9bc27 | 1852 | err_close_icosq: |
31391048 | 1853 | mlx5e_close_icosq(&c->icosq); |
d3c9bc27 | 1854 | |
f62b8bb8 AV |
1855 | err_disable_napi: |
1856 | napi_disable(&c->napi); | |
d7a0ecab | 1857 | if (c->xdp) |
31871f87 | 1858 | mlx5e_close_cq(&c->rq.xdpsq.cq); |
d7a0ecab SM |
1859 | |
1860 | err_close_rx_cq: | |
f62b8bb8 AV |
1861 | mlx5e_close_cq(&c->rq.cq); |
1862 | ||
1863 | err_close_tx_cqs: | |
1864 | mlx5e_close_tx_cqs(c); | |
1865 | ||
d3c9bc27 TT |
1866 | err_close_icosq_cq: |
1867 | mlx5e_close_cq(&c->icosq.cq); | |
1868 | ||
f62b8bb8 AV |
1869 | err_napi_del: |
1870 | netif_napi_del(&c->napi); | |
1871 | kfree(c); | |
1872 | ||
1873 | return err; | |
1874 | } | |
1875 | ||
acc6c595 SM |
1876 | static void mlx5e_activate_channel(struct mlx5e_channel *c) |
1877 | { | |
1878 | int tc; | |
1879 | ||
1880 | for (tc = 0; tc < c->num_tc; tc++) | |
1881 | mlx5e_activate_txqsq(&c->sq[tc]); | |
1882 | mlx5e_activate_rq(&c->rq); | |
231243c8 | 1883 | netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix); |
acc6c595 SM |
1884 | } |
1885 | ||
1886 | static void mlx5e_deactivate_channel(struct mlx5e_channel *c) | |
1887 | { | |
1888 | int tc; | |
1889 | ||
1890 | mlx5e_deactivate_rq(&c->rq); | |
1891 | for (tc = 0; tc < c->num_tc; tc++) | |
1892 | mlx5e_deactivate_txqsq(&c->sq[tc]); | |
1893 | } | |
1894 | ||
f62b8bb8 AV |
1895 | static void mlx5e_close_channel(struct mlx5e_channel *c) |
1896 | { | |
1897 | mlx5e_close_rq(&c->rq); | |
b5503b99 | 1898 | if (c->xdp) |
31391048 | 1899 | mlx5e_close_xdpsq(&c->rq.xdpsq); |
f62b8bb8 | 1900 | mlx5e_close_sqs(c); |
31391048 | 1901 | mlx5e_close_icosq(&c->icosq); |
f62b8bb8 | 1902 | napi_disable(&c->napi); |
b5503b99 | 1903 | if (c->xdp) |
31871f87 | 1904 | mlx5e_close_cq(&c->rq.xdpsq.cq); |
f62b8bb8 AV |
1905 | mlx5e_close_cq(&c->rq.cq); |
1906 | mlx5e_close_tx_cqs(c); | |
d3c9bc27 | 1907 | mlx5e_close_cq(&c->icosq.cq); |
f62b8bb8 | 1908 | netif_napi_del(&c->napi); |
7ae92ae5 | 1909 | |
f62b8bb8 AV |
1910 | kfree(c); |
1911 | } | |
1912 | ||
1913 | static void mlx5e_build_rq_param(struct mlx5e_priv *priv, | |
6a9764ef | 1914 | struct mlx5e_params *params, |
f62b8bb8 AV |
1915 | struct mlx5e_rq_param *param) |
1916 | { | |
f1e4fc9b | 1917 | struct mlx5_core_dev *mdev = priv->mdev; |
f62b8bb8 AV |
1918 | void *rqc = param->rqc; |
1919 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1920 | ||
6a9764ef | 1921 | switch (params->rq_wq_type) { |
461017cb | 1922 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: |
f1e4fc9b | 1923 | MLX5_SET(wq, wq, log_wqe_num_of_strides, |
619a8f2a TT |
1924 | mlx5e_mpwqe_get_log_num_strides(mdev, params) - |
1925 | MLX5_MPWQE_LOG_NUM_STRIDES_BASE); | |
f1e4fc9b | 1926 | MLX5_SET(wq, wq, log_wqe_stride_size, |
619a8f2a TT |
1927 | mlx5e_mpwqe_get_log_stride_size(mdev, params) - |
1928 | MLX5_MPWQE_LOG_STRIDE_SZ_BASE); | |
461017cb | 1929 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ); |
73281b78 | 1930 | MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params)); |
461017cb TT |
1931 | break; |
1932 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
1933 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
73281b78 | 1934 | MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames); |
461017cb TT |
1935 | } |
1936 | ||
f62b8bb8 AV |
1937 | MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); |
1938 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
f1e4fc9b | 1939 | MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn); |
593cf338 | 1940 | MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter); |
6a9764ef | 1941 | MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable); |
102722fc | 1942 | MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en); |
f62b8bb8 | 1943 | |
f1e4fc9b | 1944 | param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev); |
f62b8bb8 AV |
1945 | } |
1946 | ||
7cbaf9a3 | 1947 | static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv, |
2f0db879 | 1948 | struct mlx5e_rq_param *param) |
556dd1b9 | 1949 | { |
7cbaf9a3 | 1950 | struct mlx5_core_dev *mdev = priv->mdev; |
556dd1b9 TT |
1951 | void *rqc = param->rqc; |
1952 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1953 | ||
1954 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
1955 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
7cbaf9a3 | 1956 | MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter); |
2f0db879 GP |
1957 | |
1958 | param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev); | |
556dd1b9 TT |
1959 | } |
1960 | ||
d3c9bc27 TT |
1961 | static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv, |
1962 | struct mlx5e_sq_param *param) | |
f62b8bb8 AV |
1963 | { |
1964 | void *sqc = param->sqc; | |
1965 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1966 | ||
f62b8bb8 | 1967 | MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); |
b50d292b | 1968 | MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn); |
f62b8bb8 | 1969 | |
311c7c71 | 1970 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); |
d3c9bc27 TT |
1971 | } |
1972 | ||
1973 | static void mlx5e_build_sq_param(struct mlx5e_priv *priv, | |
6a9764ef | 1974 | struct mlx5e_params *params, |
d3c9bc27 TT |
1975 | struct mlx5e_sq_param *param) |
1976 | { | |
1977 | void *sqc = param->sqc; | |
1978 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1979 | ||
1980 | mlx5e_build_sq_param_common(priv, param); | |
6a9764ef | 1981 | MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size); |
2ac9cfe7 | 1982 | MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev)); |
f62b8bb8 AV |
1983 | } |
1984 | ||
1985 | static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv, | |
1986 | struct mlx5e_cq_param *param) | |
1987 | { | |
1988 | void *cqc = param->cqc; | |
1989 | ||
30aa60b3 | 1990 | MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index); |
f62b8bb8 AV |
1991 | } |
1992 | ||
1993 | static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, | |
6a9764ef | 1994 | struct mlx5e_params *params, |
f62b8bb8 AV |
1995 | struct mlx5e_cq_param *param) |
1996 | { | |
73281b78 | 1997 | struct mlx5_core_dev *mdev = priv->mdev; |
f62b8bb8 | 1998 | void *cqc = param->cqc; |
461017cb | 1999 | u8 log_cq_size; |
f62b8bb8 | 2000 | |
6a9764ef | 2001 | switch (params->rq_wq_type) { |
461017cb | 2002 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: |
73281b78 TT |
2003 | log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) + |
2004 | mlx5e_mpwqe_get_log_num_strides(mdev, params); | |
461017cb TT |
2005 | break; |
2006 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
73281b78 | 2007 | log_cq_size = params->log_rq_mtu_frames; |
461017cb TT |
2008 | } |
2009 | ||
2010 | MLX5_SET(cqc, cqc, log_cq_size, log_cq_size); | |
6a9764ef | 2011 | if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) { |
7219ab34 TT |
2012 | MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM); |
2013 | MLX5_SET(cqc, cqc, cqe_comp_en, 1); | |
2014 | } | |
f62b8bb8 AV |
2015 | |
2016 | mlx5e_build_common_cq_param(priv, param); | |
0088cbbc | 2017 | param->cq_period_mode = params->rx_cq_moderation.cq_period_mode; |
f62b8bb8 AV |
2018 | } |
2019 | ||
2020 | static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, | |
6a9764ef | 2021 | struct mlx5e_params *params, |
f62b8bb8 AV |
2022 | struct mlx5e_cq_param *param) |
2023 | { | |
2024 | void *cqc = param->cqc; | |
2025 | ||
6a9764ef | 2026 | MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size); |
f62b8bb8 AV |
2027 | |
2028 | mlx5e_build_common_cq_param(priv, param); | |
0088cbbc | 2029 | param->cq_period_mode = params->tx_cq_moderation.cq_period_mode; |
f62b8bb8 AV |
2030 | } |
2031 | ||
d3c9bc27 | 2032 | static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv, |
6a9764ef SM |
2033 | u8 log_wq_size, |
2034 | struct mlx5e_cq_param *param) | |
d3c9bc27 TT |
2035 | { |
2036 | void *cqc = param->cqc; | |
2037 | ||
2038 | MLX5_SET(cqc, cqc, log_cq_size, log_wq_size); | |
2039 | ||
2040 | mlx5e_build_common_cq_param(priv, param); | |
9908aa29 | 2041 | |
9a317425 | 2042 | param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; |
d3c9bc27 TT |
2043 | } |
2044 | ||
2045 | static void mlx5e_build_icosq_param(struct mlx5e_priv *priv, | |
6a9764ef SM |
2046 | u8 log_wq_size, |
2047 | struct mlx5e_sq_param *param) | |
d3c9bc27 TT |
2048 | { |
2049 | void *sqc = param->sqc; | |
2050 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
2051 | ||
2052 | mlx5e_build_sq_param_common(priv, param); | |
2053 | ||
2054 | MLX5_SET(wq, wq, log_wq_sz, log_wq_size); | |
bc77b240 | 2055 | MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq)); |
d3c9bc27 TT |
2056 | } |
2057 | ||
b5503b99 | 2058 | static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv, |
6a9764ef | 2059 | struct mlx5e_params *params, |
b5503b99 SM |
2060 | struct mlx5e_sq_param *param) |
2061 | { | |
2062 | void *sqc = param->sqc; | |
2063 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
2064 | ||
2065 | mlx5e_build_sq_param_common(priv, param); | |
6a9764ef | 2066 | MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size); |
b5503b99 SM |
2067 | } |
2068 | ||
6a9764ef SM |
2069 | static void mlx5e_build_channel_param(struct mlx5e_priv *priv, |
2070 | struct mlx5e_params *params, | |
2071 | struct mlx5e_channel_param *cparam) | |
f62b8bb8 | 2072 | { |
bc77b240 | 2073 | u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; |
d3c9bc27 | 2074 | |
6a9764ef SM |
2075 | mlx5e_build_rq_param(priv, params, &cparam->rq); |
2076 | mlx5e_build_sq_param(priv, params, &cparam->sq); | |
2077 | mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq); | |
2078 | mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq); | |
2079 | mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq); | |
2080 | mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq); | |
2081 | mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq); | |
f62b8bb8 AV |
2082 | } |
2083 | ||
55c2503d SM |
2084 | int mlx5e_open_channels(struct mlx5e_priv *priv, |
2085 | struct mlx5e_channels *chs) | |
f62b8bb8 | 2086 | { |
6b87663f | 2087 | struct mlx5e_channel_param *cparam; |
03289b88 | 2088 | int err = -ENOMEM; |
f62b8bb8 | 2089 | int i; |
f62b8bb8 | 2090 | |
6a9764ef | 2091 | chs->num = chs->params.num_channels; |
03289b88 | 2092 | |
ff9c852f | 2093 | chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL); |
6b87663f | 2094 | cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL); |
acc6c595 SM |
2095 | if (!chs->c || !cparam) |
2096 | goto err_free; | |
f62b8bb8 | 2097 | |
6a9764ef | 2098 | mlx5e_build_channel_param(priv, &chs->params, cparam); |
ff9c852f | 2099 | for (i = 0; i < chs->num; i++) { |
6a9764ef | 2100 | err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]); |
f62b8bb8 AV |
2101 | if (err) |
2102 | goto err_close_channels; | |
2103 | } | |
2104 | ||
6b87663f | 2105 | kfree(cparam); |
f62b8bb8 AV |
2106 | return 0; |
2107 | ||
2108 | err_close_channels: | |
2109 | for (i--; i >= 0; i--) | |
ff9c852f | 2110 | mlx5e_close_channel(chs->c[i]); |
f62b8bb8 | 2111 | |
acc6c595 | 2112 | err_free: |
ff9c852f | 2113 | kfree(chs->c); |
6b87663f | 2114 | kfree(cparam); |
ff9c852f | 2115 | chs->num = 0; |
f62b8bb8 AV |
2116 | return err; |
2117 | } | |
2118 | ||
acc6c595 | 2119 | static void mlx5e_activate_channels(struct mlx5e_channels *chs) |
f62b8bb8 AV |
2120 | { |
2121 | int i; | |
2122 | ||
acc6c595 SM |
2123 | for (i = 0; i < chs->num; i++) |
2124 | mlx5e_activate_channel(chs->c[i]); | |
2125 | } | |
2126 | ||
2127 | static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs) | |
2128 | { | |
2129 | int err = 0; | |
2130 | int i; | |
2131 | ||
1e7477ae EBE |
2132 | for (i = 0; i < chs->num; i++) |
2133 | err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, | |
2134 | err ? 0 : 20000); | |
acc6c595 | 2135 | |
1e7477ae | 2136 | return err ? -ETIMEDOUT : 0; |
acc6c595 SM |
2137 | } |
2138 | ||
2139 | static void mlx5e_deactivate_channels(struct mlx5e_channels *chs) | |
2140 | { | |
2141 | int i; | |
2142 | ||
2143 | for (i = 0; i < chs->num; i++) | |
2144 | mlx5e_deactivate_channel(chs->c[i]); | |
2145 | } | |
2146 | ||
55c2503d | 2147 | void mlx5e_close_channels(struct mlx5e_channels *chs) |
acc6c595 SM |
2148 | { |
2149 | int i; | |
c3b7c5c9 | 2150 | |
ff9c852f SM |
2151 | for (i = 0; i < chs->num; i++) |
2152 | mlx5e_close_channel(chs->c[i]); | |
f62b8bb8 | 2153 | |
ff9c852f SM |
2154 | kfree(chs->c); |
2155 | chs->num = 0; | |
f62b8bb8 AV |
2156 | } |
2157 | ||
a5f97fee SM |
2158 | static int |
2159 | mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt) | |
f62b8bb8 AV |
2160 | { |
2161 | struct mlx5_core_dev *mdev = priv->mdev; | |
f62b8bb8 AV |
2162 | void *rqtc; |
2163 | int inlen; | |
2164 | int err; | |
1da36696 | 2165 | u32 *in; |
a5f97fee | 2166 | int i; |
f62b8bb8 | 2167 | |
f62b8bb8 | 2168 | inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; |
1b9a07ee | 2169 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
2170 | if (!in) |
2171 | return -ENOMEM; | |
2172 | ||
2173 | rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); | |
2174 | ||
2175 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
2176 | MLX5_SET(rqtc, rqtc, rqt_max_size, sz); | |
2177 | ||
a5f97fee SM |
2178 | for (i = 0; i < sz; i++) |
2179 | MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn); | |
2be6967c | 2180 | |
398f3351 HHZ |
2181 | err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn); |
2182 | if (!err) | |
2183 | rqt->enabled = true; | |
f62b8bb8 AV |
2184 | |
2185 | kvfree(in); | |
1da36696 TT |
2186 | return err; |
2187 | } | |
2188 | ||
cb67b832 | 2189 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt) |
1da36696 | 2190 | { |
398f3351 HHZ |
2191 | rqt->enabled = false; |
2192 | mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn); | |
1da36696 TT |
2193 | } |
2194 | ||
8f493ffd | 2195 | int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv) |
6bfd390b HHZ |
2196 | { |
2197 | struct mlx5e_rqt *rqt = &priv->indir_rqt; | |
8f493ffd | 2198 | int err; |
6bfd390b | 2199 | |
8f493ffd SM |
2200 | err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt); |
2201 | if (err) | |
2202 | mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err); | |
2203 | return err; | |
6bfd390b HHZ |
2204 | } |
2205 | ||
cb67b832 | 2206 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv) |
1da36696 | 2207 | { |
398f3351 | 2208 | struct mlx5e_rqt *rqt; |
1da36696 TT |
2209 | int err; |
2210 | int ix; | |
2211 | ||
6bfd390b | 2212 | for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) { |
398f3351 | 2213 | rqt = &priv->direct_tir[ix].rqt; |
a5f97fee | 2214 | err = mlx5e_create_rqt(priv, 1 /*size */, rqt); |
1da36696 TT |
2215 | if (err) |
2216 | goto err_destroy_rqts; | |
2217 | } | |
2218 | ||
2219 | return 0; | |
2220 | ||
2221 | err_destroy_rqts: | |
8f493ffd | 2222 | mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err); |
1da36696 | 2223 | for (ix--; ix >= 0; ix--) |
398f3351 | 2224 | mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt); |
1da36696 | 2225 | |
f62b8bb8 AV |
2226 | return err; |
2227 | } | |
2228 | ||
8f493ffd SM |
2229 | void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv) |
2230 | { | |
2231 | int i; | |
2232 | ||
2233 | for (i = 0; i < priv->profile->max_nch(priv->mdev); i++) | |
2234 | mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt); | |
2235 | } | |
2236 | ||
a5f97fee SM |
2237 | static int mlx5e_rx_hash_fn(int hfunc) |
2238 | { | |
2239 | return (hfunc == ETH_RSS_HASH_TOP) ? | |
2240 | MLX5_RX_HASH_FN_TOEPLITZ : | |
2241 | MLX5_RX_HASH_FN_INVERTED_XOR8; | |
2242 | } | |
2243 | ||
3f6d08d1 | 2244 | int mlx5e_bits_invert(unsigned long a, int size) |
a5f97fee SM |
2245 | { |
2246 | int inv = 0; | |
2247 | int i; | |
2248 | ||
2249 | for (i = 0; i < size; i++) | |
2250 | inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i; | |
2251 | ||
2252 | return inv; | |
2253 | } | |
2254 | ||
2255 | static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz, | |
2256 | struct mlx5e_redirect_rqt_param rrp, void *rqtc) | |
2257 | { | |
2258 | int i; | |
2259 | ||
2260 | for (i = 0; i < sz; i++) { | |
2261 | u32 rqn; | |
2262 | ||
2263 | if (rrp.is_rss) { | |
2264 | int ix = i; | |
2265 | ||
2266 | if (rrp.rss.hfunc == ETH_RSS_HASH_XOR) | |
2267 | ix = mlx5e_bits_invert(i, ilog2(sz)); | |
2268 | ||
6a9764ef | 2269 | ix = priv->channels.params.indirection_rqt[ix]; |
a5f97fee SM |
2270 | rqn = rrp.rss.channels->c[ix]->rq.rqn; |
2271 | } else { | |
2272 | rqn = rrp.rqn; | |
2273 | } | |
2274 | MLX5_SET(rqtc, rqtc, rq_num[i], rqn); | |
2275 | } | |
2276 | } | |
2277 | ||
2278 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, | |
2279 | struct mlx5e_redirect_rqt_param rrp) | |
5c50368f AS |
2280 | { |
2281 | struct mlx5_core_dev *mdev = priv->mdev; | |
5c50368f AS |
2282 | void *rqtc; |
2283 | int inlen; | |
1da36696 | 2284 | u32 *in; |
5c50368f AS |
2285 | int err; |
2286 | ||
5c50368f | 2287 | inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; |
1b9a07ee | 2288 | in = kvzalloc(inlen, GFP_KERNEL); |
5c50368f AS |
2289 | if (!in) |
2290 | return -ENOMEM; | |
2291 | ||
2292 | rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); | |
2293 | ||
2294 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
5c50368f | 2295 | MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); |
a5f97fee | 2296 | mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc); |
1da36696 | 2297 | err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen); |
5c50368f AS |
2298 | |
2299 | kvfree(in); | |
5c50368f AS |
2300 | return err; |
2301 | } | |
2302 | ||
a5f97fee SM |
2303 | static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix, |
2304 | struct mlx5e_redirect_rqt_param rrp) | |
2305 | { | |
2306 | if (!rrp.is_rss) | |
2307 | return rrp.rqn; | |
2308 | ||
2309 | if (ix >= rrp.rss.channels->num) | |
2310 | return priv->drop_rq.rqn; | |
2311 | ||
2312 | return rrp.rss.channels->c[ix]->rq.rqn; | |
2313 | } | |
2314 | ||
2315 | static void mlx5e_redirect_rqts(struct mlx5e_priv *priv, | |
2316 | struct mlx5e_redirect_rqt_param rrp) | |
40ab6a6e | 2317 | { |
1da36696 TT |
2318 | u32 rqtn; |
2319 | int ix; | |
2320 | ||
398f3351 | 2321 | if (priv->indir_rqt.enabled) { |
a5f97fee | 2322 | /* RSS RQ table */ |
398f3351 | 2323 | rqtn = priv->indir_rqt.rqtn; |
a5f97fee | 2324 | mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp); |
398f3351 HHZ |
2325 | } |
2326 | ||
a5f97fee SM |
2327 | for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) { |
2328 | struct mlx5e_redirect_rqt_param direct_rrp = { | |
2329 | .is_rss = false, | |
95632791 AM |
2330 | { |
2331 | .rqn = mlx5e_get_direct_rqn(priv, ix, rrp) | |
2332 | }, | |
a5f97fee SM |
2333 | }; |
2334 | ||
2335 | /* Direct RQ Tables */ | |
398f3351 HHZ |
2336 | if (!priv->direct_tir[ix].rqt.enabled) |
2337 | continue; | |
a5f97fee | 2338 | |
398f3351 | 2339 | rqtn = priv->direct_tir[ix].rqt.rqtn; |
a5f97fee | 2340 | mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp); |
1da36696 | 2341 | } |
40ab6a6e AS |
2342 | } |
2343 | ||
a5f97fee SM |
2344 | static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv, |
2345 | struct mlx5e_channels *chs) | |
2346 | { | |
2347 | struct mlx5e_redirect_rqt_param rrp = { | |
2348 | .is_rss = true, | |
95632791 AM |
2349 | { |
2350 | .rss = { | |
2351 | .channels = chs, | |
2352 | .hfunc = chs->params.rss_hfunc, | |
2353 | } | |
2354 | }, | |
a5f97fee SM |
2355 | }; |
2356 | ||
2357 | mlx5e_redirect_rqts(priv, rrp); | |
2358 | } | |
2359 | ||
2360 | static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv) | |
2361 | { | |
2362 | struct mlx5e_redirect_rqt_param drop_rrp = { | |
2363 | .is_rss = false, | |
95632791 AM |
2364 | { |
2365 | .rqn = priv->drop_rq.rqn, | |
2366 | }, | |
a5f97fee SM |
2367 | }; |
2368 | ||
2369 | mlx5e_redirect_rqts(priv, drop_rrp); | |
2370 | } | |
2371 | ||
6a9764ef | 2372 | static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc) |
5c50368f | 2373 | { |
6a9764ef | 2374 | if (!params->lro_en) |
5c50368f AS |
2375 | return; |
2376 | ||
2377 | #define ROUGH_MAX_L2_L3_HDR_SZ 256 | |
2378 | ||
2379 | MLX5_SET(tirc, tirc, lro_enable_mask, | |
2380 | MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | | |
2381 | MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); | |
2382 | MLX5_SET(tirc, tirc, lro_max_ip_payload_size, | |
6a9764ef SM |
2383 | (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8); |
2384 | MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout); | |
5c50368f AS |
2385 | } |
2386 | ||
6a9764ef SM |
2387 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params, |
2388 | enum mlx5e_traffic_types tt, | |
7b3722fa | 2389 | void *tirc, bool inner) |
bdfc028d | 2390 | { |
7b3722fa GP |
2391 | void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) : |
2392 | MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | |
a100ff3e GP |
2393 | |
2394 | #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ | |
2395 | MLX5_HASH_FIELD_SEL_DST_IP) | |
2396 | ||
2397 | #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\ | |
2398 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
2399 | MLX5_HASH_FIELD_SEL_L4_SPORT |\ | |
2400 | MLX5_HASH_FIELD_SEL_L4_DPORT) | |
2401 | ||
2402 | #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ | |
2403 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
2404 | MLX5_HASH_FIELD_SEL_IPSEC_SPI) | |
2405 | ||
6a9764ef SM |
2406 | MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc)); |
2407 | if (params->rss_hfunc == ETH_RSS_HASH_TOP) { | |
bdfc028d TT |
2408 | void *rss_key = MLX5_ADDR_OF(tirc, tirc, |
2409 | rx_hash_toeplitz_key); | |
2410 | size_t len = MLX5_FLD_SZ_BYTES(tirc, | |
2411 | rx_hash_toeplitz_key); | |
2412 | ||
2413 | MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); | |
6a9764ef | 2414 | memcpy(rss_key, params->toeplitz_hash_key, len); |
bdfc028d | 2415 | } |
a100ff3e GP |
2416 | |
2417 | switch (tt) { | |
2418 | case MLX5E_TT_IPV4_TCP: | |
2419 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2420 | MLX5_L3_PROT_TYPE_IPV4); | |
2421 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2422 | MLX5_L4_PROT_TYPE_TCP); | |
2423 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2424 | MLX5_HASH_IP_L4PORTS); | |
2425 | break; | |
2426 | ||
2427 | case MLX5E_TT_IPV6_TCP: | |
2428 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2429 | MLX5_L3_PROT_TYPE_IPV6); | |
2430 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2431 | MLX5_L4_PROT_TYPE_TCP); | |
2432 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2433 | MLX5_HASH_IP_L4PORTS); | |
2434 | break; | |
2435 | ||
2436 | case MLX5E_TT_IPV4_UDP: | |
2437 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2438 | MLX5_L3_PROT_TYPE_IPV4); | |
2439 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2440 | MLX5_L4_PROT_TYPE_UDP); | |
2441 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2442 | MLX5_HASH_IP_L4PORTS); | |
2443 | break; | |
2444 | ||
2445 | case MLX5E_TT_IPV6_UDP: | |
2446 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2447 | MLX5_L3_PROT_TYPE_IPV6); | |
2448 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2449 | MLX5_L4_PROT_TYPE_UDP); | |
2450 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2451 | MLX5_HASH_IP_L4PORTS); | |
2452 | break; | |
2453 | ||
2454 | case MLX5E_TT_IPV4_IPSEC_AH: | |
2455 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2456 | MLX5_L3_PROT_TYPE_IPV4); | |
2457 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2458 | MLX5_HASH_IP_IPSEC_SPI); | |
2459 | break; | |
2460 | ||
2461 | case MLX5E_TT_IPV6_IPSEC_AH: | |
2462 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2463 | MLX5_L3_PROT_TYPE_IPV6); | |
2464 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2465 | MLX5_HASH_IP_IPSEC_SPI); | |
2466 | break; | |
2467 | ||
2468 | case MLX5E_TT_IPV4_IPSEC_ESP: | |
2469 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2470 | MLX5_L3_PROT_TYPE_IPV4); | |
2471 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2472 | MLX5_HASH_IP_IPSEC_SPI); | |
2473 | break; | |
2474 | ||
2475 | case MLX5E_TT_IPV6_IPSEC_ESP: | |
2476 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2477 | MLX5_L3_PROT_TYPE_IPV6); | |
2478 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2479 | MLX5_HASH_IP_IPSEC_SPI); | |
2480 | break; | |
2481 | ||
2482 | case MLX5E_TT_IPV4: | |
2483 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2484 | MLX5_L3_PROT_TYPE_IPV4); | |
2485 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2486 | MLX5_HASH_IP); | |
2487 | break; | |
2488 | ||
2489 | case MLX5E_TT_IPV6: | |
2490 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2491 | MLX5_L3_PROT_TYPE_IPV6); | |
2492 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2493 | MLX5_HASH_IP); | |
2494 | break; | |
2495 | default: | |
2496 | WARN_ONCE(true, "%s: bad traffic type!\n", __func__); | |
2497 | } | |
bdfc028d TT |
2498 | } |
2499 | ||
ab0394fe | 2500 | static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv) |
5c50368f AS |
2501 | { |
2502 | struct mlx5_core_dev *mdev = priv->mdev; | |
2503 | ||
2504 | void *in; | |
2505 | void *tirc; | |
2506 | int inlen; | |
2507 | int err; | |
ab0394fe | 2508 | int tt; |
1da36696 | 2509 | int ix; |
5c50368f AS |
2510 | |
2511 | inlen = MLX5_ST_SZ_BYTES(modify_tir_in); | |
1b9a07ee | 2512 | in = kvzalloc(inlen, GFP_KERNEL); |
5c50368f AS |
2513 | if (!in) |
2514 | return -ENOMEM; | |
2515 | ||
2516 | MLX5_SET(modify_tir_in, in, bitmask.lro, 1); | |
2517 | tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx); | |
2518 | ||
6a9764ef | 2519 | mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); |
5c50368f | 2520 | |
1da36696 | 2521 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { |
724b2aa1 | 2522 | err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, |
1da36696 | 2523 | inlen); |
ab0394fe | 2524 | if (err) |
1da36696 | 2525 | goto free_in; |
ab0394fe | 2526 | } |
5c50368f | 2527 | |
6bfd390b | 2528 | for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) { |
1da36696 TT |
2529 | err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, |
2530 | in, inlen); | |
2531 | if (err) | |
2532 | goto free_in; | |
2533 | } | |
2534 | ||
2535 | free_in: | |
5c50368f AS |
2536 | kvfree(in); |
2537 | ||
2538 | return err; | |
2539 | } | |
2540 | ||
7b3722fa GP |
2541 | static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv, |
2542 | enum mlx5e_traffic_types tt, | |
2543 | u32 *tirc) | |
2544 | { | |
2545 | MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); | |
2546 | ||
2547 | mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); | |
2548 | ||
2549 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | |
2550 | MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn); | |
2551 | MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1); | |
2552 | ||
2553 | mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true); | |
2554 | } | |
2555 | ||
472a1e44 TT |
2556 | static int mlx5e_set_mtu(struct mlx5_core_dev *mdev, |
2557 | struct mlx5e_params *params, u16 mtu) | |
40ab6a6e | 2558 | { |
472a1e44 | 2559 | u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu); |
40ab6a6e AS |
2560 | int err; |
2561 | ||
cd255eff | 2562 | err = mlx5_set_port_mtu(mdev, hw_mtu, 1); |
40ab6a6e AS |
2563 | if (err) |
2564 | return err; | |
2565 | ||
cd255eff SM |
2566 | /* Update vport context MTU */ |
2567 | mlx5_modify_nic_vport_mtu(mdev, hw_mtu); | |
2568 | return 0; | |
2569 | } | |
40ab6a6e | 2570 | |
472a1e44 TT |
2571 | static void mlx5e_query_mtu(struct mlx5_core_dev *mdev, |
2572 | struct mlx5e_params *params, u16 *mtu) | |
cd255eff | 2573 | { |
cd255eff SM |
2574 | u16 hw_mtu = 0; |
2575 | int err; | |
40ab6a6e | 2576 | |
cd255eff SM |
2577 | err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu); |
2578 | if (err || !hw_mtu) /* fallback to port oper mtu */ | |
2579 | mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1); | |
2580 | ||
472a1e44 | 2581 | *mtu = MLX5E_HW2SW_MTU(params, hw_mtu); |
cd255eff SM |
2582 | } |
2583 | ||
2e20a151 | 2584 | static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv) |
cd255eff | 2585 | { |
472a1e44 | 2586 | struct mlx5e_params *params = &priv->channels.params; |
2e20a151 | 2587 | struct net_device *netdev = priv->netdev; |
472a1e44 | 2588 | struct mlx5_core_dev *mdev = priv->mdev; |
cd255eff SM |
2589 | u16 mtu; |
2590 | int err; | |
2591 | ||
472a1e44 | 2592 | err = mlx5e_set_mtu(mdev, params, params->sw_mtu); |
cd255eff SM |
2593 | if (err) |
2594 | return err; | |
40ab6a6e | 2595 | |
472a1e44 TT |
2596 | mlx5e_query_mtu(mdev, params, &mtu); |
2597 | if (mtu != params->sw_mtu) | |
cd255eff | 2598 | netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n", |
472a1e44 | 2599 | __func__, mtu, params->sw_mtu); |
40ab6a6e | 2600 | |
472a1e44 | 2601 | params->sw_mtu = mtu; |
40ab6a6e AS |
2602 | return 0; |
2603 | } | |
2604 | ||
08fb1dac SM |
2605 | static void mlx5e_netdev_set_tcs(struct net_device *netdev) |
2606 | { | |
2607 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
6a9764ef SM |
2608 | int nch = priv->channels.params.num_channels; |
2609 | int ntc = priv->channels.params.num_tc; | |
08fb1dac SM |
2610 | int tc; |
2611 | ||
2612 | netdev_reset_tc(netdev); | |
2613 | ||
2614 | if (ntc == 1) | |
2615 | return; | |
2616 | ||
2617 | netdev_set_num_tc(netdev, ntc); | |
2618 | ||
7ccdd084 RS |
2619 | /* Map netdev TCs to offset 0 |
2620 | * We have our own UP to TXQ mapping for QoS | |
2621 | */ | |
08fb1dac | 2622 | for (tc = 0; tc < ntc; tc++) |
7ccdd084 | 2623 | netdev_set_tc_queue(netdev, tc, nch, 0); |
08fb1dac SM |
2624 | } |
2625 | ||
acc6c595 SM |
2626 | static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv) |
2627 | { | |
2628 | struct mlx5e_channel *c; | |
2629 | struct mlx5e_txqsq *sq; | |
2630 | int i, tc; | |
2631 | ||
2632 | for (i = 0; i < priv->channels.num; i++) | |
2633 | for (tc = 0; tc < priv->profile->max_tc; tc++) | |
2634 | priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num; | |
2635 | ||
2636 | for (i = 0; i < priv->channels.num; i++) { | |
2637 | c = priv->channels.c[i]; | |
2638 | for (tc = 0; tc < c->num_tc; tc++) { | |
2639 | sq = &c->sq[tc]; | |
2640 | priv->txq2sq[sq->txq_ix] = sq; | |
2641 | } | |
2642 | } | |
2643 | } | |
2644 | ||
603f4a45 | 2645 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv) |
acc6c595 | 2646 | { |
9008ae07 SM |
2647 | int num_txqs = priv->channels.num * priv->channels.params.num_tc; |
2648 | struct net_device *netdev = priv->netdev; | |
2649 | ||
2650 | mlx5e_netdev_set_tcs(netdev); | |
053ee0a7 TR |
2651 | netif_set_real_num_tx_queues(netdev, num_txqs); |
2652 | netif_set_real_num_rx_queues(netdev, priv->channels.num); | |
9008ae07 | 2653 | |
acc6c595 SM |
2654 | mlx5e_build_channels_tx_maps(priv); |
2655 | mlx5e_activate_channels(&priv->channels); | |
2656 | netif_tx_start_all_queues(priv->netdev); | |
9008ae07 | 2657 | |
a9f7705f | 2658 | if (MLX5_VPORT_MANAGER(priv->mdev)) |
9008ae07 SM |
2659 | mlx5e_add_sqs_fwd_rules(priv); |
2660 | ||
acc6c595 | 2661 | mlx5e_wait_channels_min_rx_wqes(&priv->channels); |
9008ae07 | 2662 | mlx5e_redirect_rqts_to_channels(priv, &priv->channels); |
acc6c595 SM |
2663 | } |
2664 | ||
603f4a45 | 2665 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv) |
acc6c595 | 2666 | { |
9008ae07 SM |
2667 | mlx5e_redirect_rqts_to_drop(priv); |
2668 | ||
a9f7705f | 2669 | if (MLX5_VPORT_MANAGER(priv->mdev)) |
9008ae07 SM |
2670 | mlx5e_remove_sqs_fwd_rules(priv); |
2671 | ||
acc6c595 SM |
2672 | /* FIXME: This is a W/A only for tx timeout watch dog false alarm when |
2673 | * polling for inactive tx queues. | |
2674 | */ | |
2675 | netif_tx_stop_all_queues(priv->netdev); | |
2676 | netif_tx_disable(priv->netdev); | |
2677 | mlx5e_deactivate_channels(&priv->channels); | |
2678 | } | |
2679 | ||
55c2503d | 2680 | void mlx5e_switch_priv_channels(struct mlx5e_priv *priv, |
2e20a151 SM |
2681 | struct mlx5e_channels *new_chs, |
2682 | mlx5e_fp_hw_modify hw_modify) | |
55c2503d SM |
2683 | { |
2684 | struct net_device *netdev = priv->netdev; | |
2685 | int new_num_txqs; | |
7ca42c80 | 2686 | int carrier_ok; |
55c2503d SM |
2687 | new_num_txqs = new_chs->num * new_chs->params.num_tc; |
2688 | ||
7ca42c80 | 2689 | carrier_ok = netif_carrier_ok(netdev); |
55c2503d SM |
2690 | netif_carrier_off(netdev); |
2691 | ||
2692 | if (new_num_txqs < netdev->real_num_tx_queues) | |
2693 | netif_set_real_num_tx_queues(netdev, new_num_txqs); | |
2694 | ||
2695 | mlx5e_deactivate_priv_channels(priv); | |
2696 | mlx5e_close_channels(&priv->channels); | |
2697 | ||
2698 | priv->channels = *new_chs; | |
2699 | ||
2e20a151 SM |
2700 | /* New channels are ready to roll, modify HW settings if needed */ |
2701 | if (hw_modify) | |
2702 | hw_modify(priv); | |
2703 | ||
55c2503d SM |
2704 | mlx5e_refresh_tirs(priv, false); |
2705 | mlx5e_activate_priv_channels(priv); | |
2706 | ||
7ca42c80 ES |
2707 | /* return carrier back if needed */ |
2708 | if (carrier_ok) | |
2709 | netif_carrier_on(netdev); | |
55c2503d SM |
2710 | } |
2711 | ||
237f258c | 2712 | void mlx5e_timestamp_init(struct mlx5e_priv *priv) |
7c39afb3 FD |
2713 | { |
2714 | priv->tstamp.tx_type = HWTSTAMP_TX_OFF; | |
2715 | priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE; | |
2716 | } | |
2717 | ||
40ab6a6e AS |
2718 | int mlx5e_open_locked(struct net_device *netdev) |
2719 | { | |
2720 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
40ab6a6e AS |
2721 | int err; |
2722 | ||
2723 | set_bit(MLX5E_STATE_OPENED, &priv->state); | |
2724 | ||
ff9c852f | 2725 | err = mlx5e_open_channels(priv, &priv->channels); |
acc6c595 | 2726 | if (err) |
343b29f3 | 2727 | goto err_clear_state_opened_flag; |
40ab6a6e | 2728 | |
b676f653 | 2729 | mlx5e_refresh_tirs(priv, false); |
acc6c595 | 2730 | mlx5e_activate_priv_channels(priv); |
7ca42c80 ES |
2731 | if (priv->profile->update_carrier) |
2732 | priv->profile->update_carrier(priv); | |
be4891af | 2733 | |
cb67b832 HHZ |
2734 | if (priv->profile->update_stats) |
2735 | queue_delayed_work(priv->wq, &priv->update_stats_work, 0); | |
40ab6a6e | 2736 | |
9b37b07f | 2737 | return 0; |
343b29f3 AS |
2738 | |
2739 | err_clear_state_opened_flag: | |
2740 | clear_bit(MLX5E_STATE_OPENED, &priv->state); | |
2741 | return err; | |
40ab6a6e AS |
2742 | } |
2743 | ||
cb67b832 | 2744 | int mlx5e_open(struct net_device *netdev) |
40ab6a6e AS |
2745 | { |
2746 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2747 | int err; | |
2748 | ||
2749 | mutex_lock(&priv->state_lock); | |
2750 | err = mlx5e_open_locked(netdev); | |
63bfd399 EBE |
2751 | if (!err) |
2752 | mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP); | |
40ab6a6e AS |
2753 | mutex_unlock(&priv->state_lock); |
2754 | ||
a117f73d SK |
2755 | if (mlx5e_vxlan_allowed(priv->mdev)) |
2756 | udp_tunnel_get_rx_info(netdev); | |
2757 | ||
40ab6a6e AS |
2758 | return err; |
2759 | } | |
2760 | ||
2761 | int mlx5e_close_locked(struct net_device *netdev) | |
2762 | { | |
2763 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2764 | ||
a1985740 AS |
2765 | /* May already be CLOSED in case a previous configuration operation |
2766 | * (e.g RX/TX queue size change) that involves close&open failed. | |
2767 | */ | |
2768 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
2769 | return 0; | |
2770 | ||
40ab6a6e AS |
2771 | clear_bit(MLX5E_STATE_OPENED, &priv->state); |
2772 | ||
40ab6a6e | 2773 | netif_carrier_off(priv->netdev); |
acc6c595 SM |
2774 | mlx5e_deactivate_priv_channels(priv); |
2775 | mlx5e_close_channels(&priv->channels); | |
40ab6a6e AS |
2776 | |
2777 | return 0; | |
2778 | } | |
2779 | ||
cb67b832 | 2780 | int mlx5e_close(struct net_device *netdev) |
40ab6a6e AS |
2781 | { |
2782 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2783 | int err; | |
2784 | ||
26e59d80 MHY |
2785 | if (!netif_device_present(netdev)) |
2786 | return -ENODEV; | |
2787 | ||
40ab6a6e | 2788 | mutex_lock(&priv->state_lock); |
63bfd399 | 2789 | mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN); |
40ab6a6e AS |
2790 | err = mlx5e_close_locked(netdev); |
2791 | mutex_unlock(&priv->state_lock); | |
2792 | ||
2793 | return err; | |
2794 | } | |
2795 | ||
a43b25da | 2796 | static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev, |
3b77235b SM |
2797 | struct mlx5e_rq *rq, |
2798 | struct mlx5e_rq_param *param) | |
40ab6a6e | 2799 | { |
40ab6a6e AS |
2800 | void *rqc = param->rqc; |
2801 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
2802 | int err; | |
2803 | ||
2804 | param->wq.db_numa_node = param->wq.buf_numa_node; | |
2805 | ||
2806 | err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, | |
2807 | &rq->wq_ctrl); | |
2808 | if (err) | |
2809 | return err; | |
2810 | ||
0ddf5432 JDB |
2811 | /* Mark as unused given "Drop-RQ" packets never reach XDP */ |
2812 | xdp_rxq_info_unused(&rq->xdp_rxq); | |
2813 | ||
a43b25da | 2814 | rq->mdev = mdev; |
40ab6a6e AS |
2815 | |
2816 | return 0; | |
2817 | } | |
2818 | ||
a43b25da | 2819 | static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev, |
3b77235b SM |
2820 | struct mlx5e_cq *cq, |
2821 | struct mlx5e_cq_param *param) | |
40ab6a6e | 2822 | { |
2f0db879 GP |
2823 | param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev); |
2824 | param->wq.db_numa_node = dev_to_node(&mdev->pdev->dev); | |
2825 | ||
95b6c6a5 | 2826 | return mlx5e_alloc_cq_common(mdev, param, cq); |
40ab6a6e AS |
2827 | } |
2828 | ||
7cbaf9a3 | 2829 | static int mlx5e_open_drop_rq(struct mlx5e_priv *priv, |
a43b25da | 2830 | struct mlx5e_rq *drop_rq) |
40ab6a6e | 2831 | { |
7cbaf9a3 | 2832 | struct mlx5_core_dev *mdev = priv->mdev; |
a43b25da SM |
2833 | struct mlx5e_cq_param cq_param = {}; |
2834 | struct mlx5e_rq_param rq_param = {}; | |
2835 | struct mlx5e_cq *cq = &drop_rq->cq; | |
40ab6a6e AS |
2836 | int err; |
2837 | ||
7cbaf9a3 | 2838 | mlx5e_build_drop_rq_param(priv, &rq_param); |
40ab6a6e | 2839 | |
a43b25da | 2840 | err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param); |
40ab6a6e AS |
2841 | if (err) |
2842 | return err; | |
2843 | ||
3b77235b | 2844 | err = mlx5e_create_cq(cq, &cq_param); |
40ab6a6e | 2845 | if (err) |
3b77235b | 2846 | goto err_free_cq; |
40ab6a6e | 2847 | |
a43b25da | 2848 | err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param); |
40ab6a6e | 2849 | if (err) |
3b77235b | 2850 | goto err_destroy_cq; |
40ab6a6e | 2851 | |
a43b25da | 2852 | err = mlx5e_create_rq(drop_rq, &rq_param); |
40ab6a6e | 2853 | if (err) |
3b77235b | 2854 | goto err_free_rq; |
40ab6a6e | 2855 | |
7cbaf9a3 MS |
2856 | err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); |
2857 | if (err) | |
2858 | mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err); | |
2859 | ||
40ab6a6e AS |
2860 | return 0; |
2861 | ||
3b77235b | 2862 | err_free_rq: |
a43b25da | 2863 | mlx5e_free_rq(drop_rq); |
40ab6a6e AS |
2864 | |
2865 | err_destroy_cq: | |
a43b25da | 2866 | mlx5e_destroy_cq(cq); |
40ab6a6e | 2867 | |
3b77235b | 2868 | err_free_cq: |
a43b25da | 2869 | mlx5e_free_cq(cq); |
3b77235b | 2870 | |
40ab6a6e AS |
2871 | return err; |
2872 | } | |
2873 | ||
a43b25da | 2874 | static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq) |
40ab6a6e | 2875 | { |
a43b25da SM |
2876 | mlx5e_destroy_rq(drop_rq); |
2877 | mlx5e_free_rq(drop_rq); | |
2878 | mlx5e_destroy_cq(&drop_rq->cq); | |
2879 | mlx5e_free_cq(&drop_rq->cq); | |
40ab6a6e AS |
2880 | } |
2881 | ||
5426a0b2 SM |
2882 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc, |
2883 | u32 underlay_qpn, u32 *tisn) | |
40ab6a6e | 2884 | { |
c4f287c4 | 2885 | u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; |
40ab6a6e AS |
2886 | void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); |
2887 | ||
08fb1dac | 2888 | MLX5_SET(tisc, tisc, prio, tc << 1); |
5426a0b2 | 2889 | MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn); |
b50d292b | 2890 | MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn); |
db60b802 AH |
2891 | |
2892 | if (mlx5_lag_is_lacp_owner(mdev)) | |
2893 | MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1); | |
2894 | ||
5426a0b2 | 2895 | return mlx5_core_create_tis(mdev, in, sizeof(in), tisn); |
40ab6a6e AS |
2896 | } |
2897 | ||
5426a0b2 | 2898 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn) |
40ab6a6e | 2899 | { |
5426a0b2 | 2900 | mlx5_core_destroy_tis(mdev, tisn); |
40ab6a6e AS |
2901 | } |
2902 | ||
cb67b832 | 2903 | int mlx5e_create_tises(struct mlx5e_priv *priv) |
40ab6a6e AS |
2904 | { |
2905 | int err; | |
2906 | int tc; | |
2907 | ||
6bfd390b | 2908 | for (tc = 0; tc < priv->profile->max_tc; tc++) { |
5426a0b2 | 2909 | err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]); |
40ab6a6e AS |
2910 | if (err) |
2911 | goto err_close_tises; | |
2912 | } | |
2913 | ||
2914 | return 0; | |
2915 | ||
2916 | err_close_tises: | |
2917 | for (tc--; tc >= 0; tc--) | |
5426a0b2 | 2918 | mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]); |
40ab6a6e AS |
2919 | |
2920 | return err; | |
2921 | } | |
2922 | ||
cb67b832 | 2923 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv) |
40ab6a6e AS |
2924 | { |
2925 | int tc; | |
2926 | ||
6bfd390b | 2927 | for (tc = 0; tc < priv->profile->max_tc; tc++) |
5426a0b2 | 2928 | mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]); |
40ab6a6e AS |
2929 | } |
2930 | ||
6a9764ef SM |
2931 | static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, |
2932 | enum mlx5e_traffic_types tt, | |
2933 | u32 *tirc) | |
f62b8bb8 | 2934 | { |
b50d292b | 2935 | MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); |
3191e05f | 2936 | |
6a9764ef | 2937 | mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); |
f62b8bb8 | 2938 | |
4cbeaff5 | 2939 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); |
398f3351 | 2940 | MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn); |
7b3722fa | 2941 | mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false); |
f62b8bb8 AV |
2942 | } |
2943 | ||
6a9764ef | 2944 | static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc) |
f62b8bb8 | 2945 | { |
b50d292b | 2946 | MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); |
1da36696 | 2947 | |
6a9764ef | 2948 | mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); |
1da36696 TT |
2949 | |
2950 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | |
2951 | MLX5_SET(tirc, tirc, indirect_table, rqtn); | |
2952 | MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8); | |
2953 | } | |
2954 | ||
8f493ffd | 2955 | int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv) |
1da36696 | 2956 | { |
724b2aa1 | 2957 | struct mlx5e_tir *tir; |
f62b8bb8 AV |
2958 | void *tirc; |
2959 | int inlen; | |
7b3722fa | 2960 | int i = 0; |
f62b8bb8 | 2961 | int err; |
1da36696 | 2962 | u32 *in; |
1da36696 | 2963 | int tt; |
f62b8bb8 AV |
2964 | |
2965 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
1b9a07ee | 2966 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
2967 | if (!in) |
2968 | return -ENOMEM; | |
2969 | ||
1da36696 TT |
2970 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { |
2971 | memset(in, 0, inlen); | |
724b2aa1 | 2972 | tir = &priv->indir_tir[tt]; |
1da36696 | 2973 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); |
6a9764ef | 2974 | mlx5e_build_indir_tir_ctx(priv, tt, tirc); |
724b2aa1 | 2975 | err = mlx5e_create_tir(priv->mdev, tir, in, inlen); |
7b3722fa GP |
2976 | if (err) { |
2977 | mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err); | |
2978 | goto err_destroy_inner_tirs; | |
2979 | } | |
f62b8bb8 AV |
2980 | } |
2981 | ||
7b3722fa GP |
2982 | if (!mlx5e_tunnel_inner_ft_supported(priv->mdev)) |
2983 | goto out; | |
2984 | ||
2985 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) { | |
2986 | memset(in, 0, inlen); | |
2987 | tir = &priv->inner_indir_tir[i]; | |
2988 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
2989 | mlx5e_build_inner_indir_tir_ctx(priv, i, tirc); | |
2990 | err = mlx5e_create_tir(priv->mdev, tir, in, inlen); | |
2991 | if (err) { | |
2992 | mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err); | |
2993 | goto err_destroy_inner_tirs; | |
2994 | } | |
2995 | } | |
2996 | ||
2997 | out: | |
6bfd390b HHZ |
2998 | kvfree(in); |
2999 | ||
3000 | return 0; | |
3001 | ||
7b3722fa GP |
3002 | err_destroy_inner_tirs: |
3003 | for (i--; i >= 0; i--) | |
3004 | mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]); | |
3005 | ||
6bfd390b HHZ |
3006 | for (tt--; tt >= 0; tt--) |
3007 | mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]); | |
3008 | ||
3009 | kvfree(in); | |
3010 | ||
3011 | return err; | |
3012 | } | |
3013 | ||
cb67b832 | 3014 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv) |
6bfd390b HHZ |
3015 | { |
3016 | int nch = priv->profile->max_nch(priv->mdev); | |
3017 | struct mlx5e_tir *tir; | |
3018 | void *tirc; | |
3019 | int inlen; | |
3020 | int err; | |
3021 | u32 *in; | |
3022 | int ix; | |
3023 | ||
3024 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
1b9a07ee | 3025 | in = kvzalloc(inlen, GFP_KERNEL); |
6bfd390b HHZ |
3026 | if (!in) |
3027 | return -ENOMEM; | |
3028 | ||
1da36696 TT |
3029 | for (ix = 0; ix < nch; ix++) { |
3030 | memset(in, 0, inlen); | |
724b2aa1 | 3031 | tir = &priv->direct_tir[ix]; |
1da36696 | 3032 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); |
6a9764ef | 3033 | mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc); |
724b2aa1 | 3034 | err = mlx5e_create_tir(priv->mdev, tir, in, inlen); |
1da36696 TT |
3035 | if (err) |
3036 | goto err_destroy_ch_tirs; | |
3037 | } | |
3038 | ||
3039 | kvfree(in); | |
3040 | ||
f62b8bb8 AV |
3041 | return 0; |
3042 | ||
1da36696 | 3043 | err_destroy_ch_tirs: |
8f493ffd | 3044 | mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err); |
1da36696 | 3045 | for (ix--; ix >= 0; ix--) |
724b2aa1 | 3046 | mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]); |
1da36696 | 3047 | |
1da36696 | 3048 | kvfree(in); |
f62b8bb8 AV |
3049 | |
3050 | return err; | |
3051 | } | |
3052 | ||
8f493ffd | 3053 | void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv) |
f62b8bb8 AV |
3054 | { |
3055 | int i; | |
3056 | ||
1da36696 | 3057 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) |
724b2aa1 | 3058 | mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]); |
7b3722fa GP |
3059 | |
3060 | if (!mlx5e_tunnel_inner_ft_supported(priv->mdev)) | |
3061 | return; | |
3062 | ||
3063 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) | |
3064 | mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]); | |
f62b8bb8 AV |
3065 | } |
3066 | ||
cb67b832 | 3067 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv) |
6bfd390b HHZ |
3068 | { |
3069 | int nch = priv->profile->max_nch(priv->mdev); | |
3070 | int i; | |
3071 | ||
3072 | for (i = 0; i < nch; i++) | |
3073 | mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]); | |
3074 | } | |
3075 | ||
102722fc GE |
3076 | static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable) |
3077 | { | |
3078 | int err = 0; | |
3079 | int i; | |
3080 | ||
3081 | for (i = 0; i < chs->num; i++) { | |
3082 | err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable); | |
3083 | if (err) | |
3084 | return err; | |
3085 | } | |
3086 | ||
3087 | return 0; | |
3088 | } | |
3089 | ||
f6d96a20 | 3090 | static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd) |
36350114 GP |
3091 | { |
3092 | int err = 0; | |
3093 | int i; | |
3094 | ||
ff9c852f SM |
3095 | for (i = 0; i < chs->num; i++) { |
3096 | err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd); | |
36350114 GP |
3097 | if (err) |
3098 | return err; | |
3099 | } | |
3100 | ||
3101 | return 0; | |
3102 | } | |
3103 | ||
0cf0f6d3 JP |
3104 | static int mlx5e_setup_tc_mqprio(struct net_device *netdev, |
3105 | struct tc_mqprio_qopt *mqprio) | |
08fb1dac SM |
3106 | { |
3107 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
6f9485af | 3108 | struct mlx5e_channels new_channels = {}; |
0cf0f6d3 | 3109 | u8 tc = mqprio->num_tc; |
08fb1dac SM |
3110 | int err = 0; |
3111 | ||
0cf0f6d3 JP |
3112 | mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; |
3113 | ||
08fb1dac SM |
3114 | if (tc && tc != MLX5E_MAX_NUM_TC) |
3115 | return -EINVAL; | |
3116 | ||
3117 | mutex_lock(&priv->state_lock); | |
3118 | ||
6f9485af SM |
3119 | new_channels.params = priv->channels.params; |
3120 | new_channels.params.num_tc = tc ? tc : 1; | |
08fb1dac | 3121 | |
20b6a1c7 | 3122 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { |
6f9485af SM |
3123 | priv->channels.params = new_channels.params; |
3124 | goto out; | |
3125 | } | |
08fb1dac | 3126 | |
6f9485af SM |
3127 | err = mlx5e_open_channels(priv, &new_channels); |
3128 | if (err) | |
3129 | goto out; | |
08fb1dac | 3130 | |
2e20a151 | 3131 | mlx5e_switch_priv_channels(priv, &new_channels, NULL); |
6f9485af | 3132 | out: |
08fb1dac | 3133 | mutex_unlock(&priv->state_lock); |
08fb1dac SM |
3134 | return err; |
3135 | } | |
3136 | ||
e80541ec | 3137 | #ifdef CONFIG_MLX5_ESWITCH |
d6c862ba | 3138 | static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv, |
0cf0f6d3 | 3139 | struct tc_cls_flower_offload *cls_flower) |
08fb1dac | 3140 | { |
0cf0f6d3 JP |
3141 | switch (cls_flower->command) { |
3142 | case TC_CLSFLOWER_REPLACE: | |
5fd9fc4e | 3143 | return mlx5e_configure_flower(priv, cls_flower); |
0cf0f6d3 JP |
3144 | case TC_CLSFLOWER_DESTROY: |
3145 | return mlx5e_delete_flower(priv, cls_flower); | |
3146 | case TC_CLSFLOWER_STATS: | |
3147 | return mlx5e_stats_flower(priv, cls_flower); | |
3148 | default: | |
a5fcf8a6 | 3149 | return -EOPNOTSUPP; |
0cf0f6d3 JP |
3150 | } |
3151 | } | |
d6c862ba JP |
3152 | |
3153 | int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, | |
3154 | void *cb_priv) | |
3155 | { | |
3156 | struct mlx5e_priv *priv = cb_priv; | |
3157 | ||
9ab88e83 | 3158 | if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data)) |
44ae12a7 JP |
3159 | return -EOPNOTSUPP; |
3160 | ||
d6c862ba JP |
3161 | switch (type) { |
3162 | case TC_SETUP_CLSFLOWER: | |
3163 | return mlx5e_setup_tc_cls_flower(priv, type_data); | |
3164 | default: | |
3165 | return -EOPNOTSUPP; | |
3166 | } | |
3167 | } | |
3168 | ||
3169 | static int mlx5e_setup_tc_block(struct net_device *dev, | |
3170 | struct tc_block_offload *f) | |
3171 | { | |
3172 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3173 | ||
3174 | if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) | |
3175 | return -EOPNOTSUPP; | |
3176 | ||
3177 | switch (f->command) { | |
3178 | case TC_BLOCK_BIND: | |
3179 | return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb, | |
3180 | priv, priv); | |
3181 | case TC_BLOCK_UNBIND: | |
3182 | tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb, | |
3183 | priv); | |
3184 | return 0; | |
3185 | default: | |
3186 | return -EOPNOTSUPP; | |
3187 | } | |
3188 | } | |
e80541ec | 3189 | #endif |
a5fcf8a6 | 3190 | |
9afe9a53 OG |
3191 | static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type, |
3192 | void *type_data) | |
0cf0f6d3 | 3193 | { |
2572ac53 | 3194 | switch (type) { |
fde6af47 | 3195 | #ifdef CONFIG_MLX5_ESWITCH |
d6c862ba JP |
3196 | case TC_SETUP_BLOCK: |
3197 | return mlx5e_setup_tc_block(dev, type_data); | |
fde6af47 | 3198 | #endif |
575ed7d3 | 3199 | case TC_SETUP_QDISC_MQPRIO: |
de4784ca | 3200 | return mlx5e_setup_tc_mqprio(dev, type_data); |
e8f887ac AV |
3201 | default: |
3202 | return -EOPNOTSUPP; | |
3203 | } | |
08fb1dac SM |
3204 | } |
3205 | ||
bc1f4470 | 3206 | static void |
f62b8bb8 AV |
3207 | mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) |
3208 | { | |
3209 | struct mlx5e_priv *priv = netdev_priv(dev); | |
9218b44d | 3210 | struct mlx5e_sw_stats *sstats = &priv->stats.sw; |
f62b8bb8 | 3211 | struct mlx5e_vport_stats *vstats = &priv->stats.vport; |
269e6b3a | 3212 | struct mlx5e_pport_stats *pstats = &priv->stats.pport; |
f62b8bb8 | 3213 | |
370bad0f OG |
3214 | if (mlx5e_is_uplink_rep(priv)) { |
3215 | stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok); | |
3216 | stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok); | |
3217 | stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok); | |
3218 | stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok); | |
3219 | } else { | |
3220 | stats->rx_packets = sstats->rx_packets; | |
3221 | stats->rx_bytes = sstats->rx_bytes; | |
3222 | stats->tx_packets = sstats->tx_packets; | |
3223 | stats->tx_bytes = sstats->tx_bytes; | |
3224 | stats->tx_dropped = sstats->tx_queue_dropped; | |
3225 | } | |
269e6b3a GP |
3226 | |
3227 | stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer; | |
269e6b3a GP |
3228 | |
3229 | stats->rx_length_errors = | |
9218b44d GP |
3230 | PPORT_802_3_GET(pstats, a_in_range_length_errors) + |
3231 | PPORT_802_3_GET(pstats, a_out_of_range_length_field) + | |
3232 | PPORT_802_3_GET(pstats, a_frame_too_long_errors); | |
269e6b3a | 3233 | stats->rx_crc_errors = |
9218b44d GP |
3234 | PPORT_802_3_GET(pstats, a_frame_check_sequence_errors); |
3235 | stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors); | |
3236 | stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards); | |
269e6b3a GP |
3237 | stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + |
3238 | stats->rx_frame_errors; | |
3239 | stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors; | |
3240 | ||
3241 | /* vport multicast also counts packets that are dropped due to steering | |
3242 | * or rx out of buffer | |
3243 | */ | |
9218b44d GP |
3244 | stats->multicast = |
3245 | VPORT_COUNTER_GET(vstats, received_eth_multicast.packets); | |
f62b8bb8 AV |
3246 | } |
3247 | ||
3248 | static void mlx5e_set_rx_mode(struct net_device *dev) | |
3249 | { | |
3250 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3251 | ||
7bb29755 | 3252 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
3253 | } |
3254 | ||
3255 | static int mlx5e_set_mac(struct net_device *netdev, void *addr) | |
3256 | { | |
3257 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3258 | struct sockaddr *saddr = addr; | |
3259 | ||
3260 | if (!is_valid_ether_addr(saddr->sa_data)) | |
3261 | return -EADDRNOTAVAIL; | |
3262 | ||
3263 | netif_addr_lock_bh(netdev); | |
3264 | ether_addr_copy(netdev->dev_addr, saddr->sa_data); | |
3265 | netif_addr_unlock_bh(netdev); | |
3266 | ||
7bb29755 | 3267 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
3268 | |
3269 | return 0; | |
3270 | } | |
3271 | ||
75b81ce7 | 3272 | #define MLX5E_SET_FEATURE(features, feature, enable) \ |
0e405443 GP |
3273 | do { \ |
3274 | if (enable) \ | |
75b81ce7 | 3275 | *features |= feature; \ |
0e405443 | 3276 | else \ |
75b81ce7 | 3277 | *features &= ~feature; \ |
0e405443 GP |
3278 | } while (0) |
3279 | ||
3280 | typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable); | |
3281 | ||
3282 | static int set_feature_lro(struct net_device *netdev, bool enable) | |
f62b8bb8 AV |
3283 | { |
3284 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
619a8f2a | 3285 | struct mlx5_core_dev *mdev = priv->mdev; |
2e20a151 | 3286 | struct mlx5e_channels new_channels = {}; |
619a8f2a | 3287 | struct mlx5e_params *old_params; |
2e20a151 SM |
3288 | int err = 0; |
3289 | bool reset; | |
f62b8bb8 AV |
3290 | |
3291 | mutex_lock(&priv->state_lock); | |
f62b8bb8 | 3292 | |
619a8f2a TT |
3293 | old_params = &priv->channels.params; |
3294 | reset = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
98e81b0a | 3295 | |
619a8f2a | 3296 | new_channels.params = *old_params; |
2e20a151 SM |
3297 | new_channels.params.lro_en = enable; |
3298 | ||
619a8f2a TT |
3299 | if (old_params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST) { |
3300 | if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) == | |
3301 | mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params)) | |
3302 | reset = false; | |
3303 | } | |
3304 | ||
2e20a151 | 3305 | if (!reset) { |
619a8f2a | 3306 | *old_params = new_channels.params; |
2e20a151 SM |
3307 | err = mlx5e_modify_tirs_lro(priv); |
3308 | goto out; | |
98e81b0a | 3309 | } |
f62b8bb8 | 3310 | |
2e20a151 SM |
3311 | err = mlx5e_open_channels(priv, &new_channels); |
3312 | if (err) | |
3313 | goto out; | |
0e405443 | 3314 | |
2e20a151 SM |
3315 | mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro); |
3316 | out: | |
9b37b07f | 3317 | mutex_unlock(&priv->state_lock); |
0e405443 GP |
3318 | return err; |
3319 | } | |
3320 | ||
2b52a283 | 3321 | static int set_feature_cvlan_filter(struct net_device *netdev, bool enable) |
0e405443 GP |
3322 | { |
3323 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3324 | ||
3325 | if (enable) | |
2b52a283 | 3326 | mlx5e_enable_cvlan_filter(priv); |
0e405443 | 3327 | else |
2b52a283 | 3328 | mlx5e_disable_cvlan_filter(priv); |
0e405443 GP |
3329 | |
3330 | return 0; | |
3331 | } | |
3332 | ||
3333 | static int set_feature_tc_num_filters(struct net_device *netdev, bool enable) | |
3334 | { | |
3335 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
f62b8bb8 | 3336 | |
0e405443 | 3337 | if (!enable && mlx5e_tc_num_filters(priv)) { |
e8f887ac AV |
3338 | netdev_err(netdev, |
3339 | "Active offloaded tc filters, can't turn hw_tc_offload off\n"); | |
3340 | return -EINVAL; | |
3341 | } | |
3342 | ||
0e405443 GP |
3343 | return 0; |
3344 | } | |
3345 | ||
94cb1ebb EBE |
3346 | static int set_feature_rx_all(struct net_device *netdev, bool enable) |
3347 | { | |
3348 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3349 | struct mlx5_core_dev *mdev = priv->mdev; | |
3350 | ||
3351 | return mlx5_set_port_fcs(mdev, !enable); | |
3352 | } | |
3353 | ||
102722fc GE |
3354 | static int set_feature_rx_fcs(struct net_device *netdev, bool enable) |
3355 | { | |
3356 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3357 | int err; | |
3358 | ||
3359 | mutex_lock(&priv->state_lock); | |
3360 | ||
3361 | priv->channels.params.scatter_fcs_en = enable; | |
3362 | err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable); | |
3363 | if (err) | |
3364 | priv->channels.params.scatter_fcs_en = !enable; | |
3365 | ||
3366 | mutex_unlock(&priv->state_lock); | |
3367 | ||
3368 | return err; | |
3369 | } | |
3370 | ||
36350114 GP |
3371 | static int set_feature_rx_vlan(struct net_device *netdev, bool enable) |
3372 | { | |
3373 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
ff9c852f | 3374 | int err = 0; |
36350114 GP |
3375 | |
3376 | mutex_lock(&priv->state_lock); | |
3377 | ||
6a9764ef | 3378 | priv->channels.params.vlan_strip_disable = !enable; |
ff9c852f SM |
3379 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) |
3380 | goto unlock; | |
3381 | ||
3382 | err = mlx5e_modify_channels_vsd(&priv->channels, !enable); | |
36350114 | 3383 | if (err) |
6a9764ef | 3384 | priv->channels.params.vlan_strip_disable = enable; |
36350114 | 3385 | |
ff9c852f | 3386 | unlock: |
36350114 GP |
3387 | mutex_unlock(&priv->state_lock); |
3388 | ||
3389 | return err; | |
3390 | } | |
3391 | ||
45bf454a MG |
3392 | #ifdef CONFIG_RFS_ACCEL |
3393 | static int set_feature_arfs(struct net_device *netdev, bool enable) | |
3394 | { | |
3395 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3396 | int err; | |
3397 | ||
3398 | if (enable) | |
3399 | err = mlx5e_arfs_enable(priv); | |
3400 | else | |
3401 | err = mlx5e_arfs_disable(priv); | |
3402 | ||
3403 | return err; | |
3404 | } | |
3405 | #endif | |
3406 | ||
0e405443 | 3407 | static int mlx5e_handle_feature(struct net_device *netdev, |
75b81ce7 | 3408 | netdev_features_t *features, |
0e405443 GP |
3409 | netdev_features_t wanted_features, |
3410 | netdev_features_t feature, | |
3411 | mlx5e_feature_handler feature_handler) | |
3412 | { | |
3413 | netdev_features_t changes = wanted_features ^ netdev->features; | |
3414 | bool enable = !!(wanted_features & feature); | |
3415 | int err; | |
3416 | ||
3417 | if (!(changes & feature)) | |
3418 | return 0; | |
3419 | ||
3420 | err = feature_handler(netdev, enable); | |
3421 | if (err) { | |
b20eab15 GP |
3422 | netdev_err(netdev, "%s feature %pNF failed, err %d\n", |
3423 | enable ? "Enable" : "Disable", &feature, err); | |
0e405443 GP |
3424 | return err; |
3425 | } | |
3426 | ||
75b81ce7 | 3427 | MLX5E_SET_FEATURE(features, feature, enable); |
0e405443 GP |
3428 | return 0; |
3429 | } | |
3430 | ||
3431 | static int mlx5e_set_features(struct net_device *netdev, | |
3432 | netdev_features_t features) | |
3433 | { | |
75b81ce7 | 3434 | netdev_features_t oper_features = netdev->features; |
be0f780b GP |
3435 | int err = 0; |
3436 | ||
3437 | #define MLX5E_HANDLE_FEATURE(feature, handler) \ | |
3438 | mlx5e_handle_feature(netdev, &oper_features, features, feature, handler) | |
0e405443 | 3439 | |
be0f780b GP |
3440 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro); |
3441 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER, | |
2b52a283 | 3442 | set_feature_cvlan_filter); |
be0f780b GP |
3443 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters); |
3444 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all); | |
3445 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs); | |
3446 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan); | |
45bf454a | 3447 | #ifdef CONFIG_RFS_ACCEL |
be0f780b | 3448 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs); |
45bf454a | 3449 | #endif |
0e405443 | 3450 | |
75b81ce7 GP |
3451 | if (err) { |
3452 | netdev->features = oper_features; | |
3453 | return -EINVAL; | |
3454 | } | |
3455 | ||
3456 | return 0; | |
f62b8bb8 AV |
3457 | } |
3458 | ||
7d92d580 GP |
3459 | static netdev_features_t mlx5e_fix_features(struct net_device *netdev, |
3460 | netdev_features_t features) | |
3461 | { | |
3462 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3463 | ||
3464 | mutex_lock(&priv->state_lock); | |
3465 | if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) { | |
3466 | /* HW strips the outer C-tag header, this is a problem | |
3467 | * for S-tag traffic. | |
3468 | */ | |
3469 | features &= ~NETIF_F_HW_VLAN_CTAG_RX; | |
3470 | if (!priv->channels.params.vlan_strip_disable) | |
3471 | netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n"); | |
3472 | } | |
3473 | mutex_unlock(&priv->state_lock); | |
3474 | ||
3475 | return features; | |
3476 | } | |
3477 | ||
f62b8bb8 AV |
3478 | static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu) |
3479 | { | |
3480 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2e20a151 | 3481 | struct mlx5e_channels new_channels = {}; |
472a1e44 | 3482 | struct mlx5e_params *params; |
98e81b0a | 3483 | int err = 0; |
506753b0 | 3484 | bool reset; |
f62b8bb8 | 3485 | |
f62b8bb8 | 3486 | mutex_lock(&priv->state_lock); |
98e81b0a | 3487 | |
472a1e44 | 3488 | params = &priv->channels.params; |
506753b0 | 3489 | |
73281b78 | 3490 | reset = !params->lro_en; |
2e20a151 | 3491 | reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state); |
98e81b0a | 3492 | |
73281b78 TT |
3493 | new_channels.params = *params; |
3494 | new_channels.params.sw_mtu = new_mtu; | |
3495 | ||
3496 | if (params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST) { | |
3497 | u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params); | |
3498 | u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params); | |
3499 | ||
3500 | reset = reset && (ppw_old != ppw_new); | |
3501 | } | |
3502 | ||
2e20a151 | 3503 | if (!reset) { |
472a1e44 | 3504 | params->sw_mtu = new_mtu; |
2e20a151 | 3505 | mlx5e_set_dev_port_mtu(priv); |
472a1e44 | 3506 | netdev->mtu = params->sw_mtu; |
2e20a151 SM |
3507 | goto out; |
3508 | } | |
98e81b0a | 3509 | |
2e20a151 | 3510 | err = mlx5e_open_channels(priv, &new_channels); |
472a1e44 | 3511 | if (err) |
2e20a151 | 3512 | goto out; |
2e20a151 SM |
3513 | |
3514 | mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu); | |
472a1e44 | 3515 | netdev->mtu = new_channels.params.sw_mtu; |
f62b8bb8 | 3516 | |
2e20a151 SM |
3517 | out: |
3518 | mutex_unlock(&priv->state_lock); | |
f62b8bb8 AV |
3519 | return err; |
3520 | } | |
3521 | ||
7c39afb3 FD |
3522 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr) |
3523 | { | |
3524 | struct hwtstamp_config config; | |
3525 | int err; | |
3526 | ||
3527 | if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz)) | |
3528 | return -EOPNOTSUPP; | |
3529 | ||
3530 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
3531 | return -EFAULT; | |
3532 | ||
3533 | /* TX HW timestamp */ | |
3534 | switch (config.tx_type) { | |
3535 | case HWTSTAMP_TX_OFF: | |
3536 | case HWTSTAMP_TX_ON: | |
3537 | break; | |
3538 | default: | |
3539 | return -ERANGE; | |
3540 | } | |
3541 | ||
3542 | mutex_lock(&priv->state_lock); | |
3543 | /* RX HW timestamp */ | |
3544 | switch (config.rx_filter) { | |
3545 | case HWTSTAMP_FILTER_NONE: | |
3546 | /* Reset CQE compression to Admin default */ | |
3547 | mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def); | |
3548 | break; | |
3549 | case HWTSTAMP_FILTER_ALL: | |
3550 | case HWTSTAMP_FILTER_SOME: | |
3551 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
3552 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
3553 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
3554 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
3555 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
3556 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
3557 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
3558 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
3559 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
3560 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
3561 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
3562 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
3563 | case HWTSTAMP_FILTER_NTP_ALL: | |
3564 | /* Disable CQE compression */ | |
3565 | netdev_warn(priv->netdev, "Disabling cqe compression"); | |
3566 | err = mlx5e_modify_rx_cqe_compression_locked(priv, false); | |
3567 | if (err) { | |
3568 | netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err); | |
3569 | mutex_unlock(&priv->state_lock); | |
3570 | return err; | |
3571 | } | |
3572 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
3573 | break; | |
3574 | default: | |
3575 | mutex_unlock(&priv->state_lock); | |
3576 | return -ERANGE; | |
3577 | } | |
3578 | ||
3579 | memcpy(&priv->tstamp, &config, sizeof(config)); | |
3580 | mutex_unlock(&priv->state_lock); | |
3581 | ||
3582 | return copy_to_user(ifr->ifr_data, &config, | |
3583 | sizeof(config)) ? -EFAULT : 0; | |
3584 | } | |
3585 | ||
3586 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr) | |
3587 | { | |
3588 | struct hwtstamp_config *cfg = &priv->tstamp; | |
3589 | ||
3590 | if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz)) | |
3591 | return -EOPNOTSUPP; | |
3592 | ||
3593 | return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0; | |
3594 | } | |
3595 | ||
ef9814de EBE |
3596 | static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
3597 | { | |
1170fbd8 FD |
3598 | struct mlx5e_priv *priv = netdev_priv(dev); |
3599 | ||
ef9814de EBE |
3600 | switch (cmd) { |
3601 | case SIOCSHWTSTAMP: | |
1170fbd8 | 3602 | return mlx5e_hwstamp_set(priv, ifr); |
ef9814de | 3603 | case SIOCGHWTSTAMP: |
1170fbd8 | 3604 | return mlx5e_hwstamp_get(priv, ifr); |
ef9814de EBE |
3605 | default: |
3606 | return -EOPNOTSUPP; | |
3607 | } | |
3608 | } | |
3609 | ||
e80541ec | 3610 | #ifdef CONFIG_MLX5_ESWITCH |
66e49ded SM |
3611 | static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac) |
3612 | { | |
3613 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3614 | struct mlx5_core_dev *mdev = priv->mdev; | |
3615 | ||
3616 | return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac); | |
3617 | } | |
3618 | ||
79aab093 MS |
3619 | static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos, |
3620 | __be16 vlan_proto) | |
66e49ded SM |
3621 | { |
3622 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3623 | struct mlx5_core_dev *mdev = priv->mdev; | |
3624 | ||
79aab093 MS |
3625 | if (vlan_proto != htons(ETH_P_8021Q)) |
3626 | return -EPROTONOSUPPORT; | |
3627 | ||
66e49ded SM |
3628 | return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1, |
3629 | vlan, qos); | |
3630 | } | |
3631 | ||
f942380c MHY |
3632 | static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting) |
3633 | { | |
3634 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3635 | struct mlx5_core_dev *mdev = priv->mdev; | |
3636 | ||
3637 | return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting); | |
3638 | } | |
3639 | ||
1edc57e2 MHY |
3640 | static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting) |
3641 | { | |
3642 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3643 | struct mlx5_core_dev *mdev = priv->mdev; | |
3644 | ||
3645 | return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting); | |
3646 | } | |
bd77bf1c MHY |
3647 | |
3648 | static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, | |
3649 | int max_tx_rate) | |
3650 | { | |
3651 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3652 | struct mlx5_core_dev *mdev = priv->mdev; | |
3653 | ||
bd77bf1c | 3654 | return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1, |
c9497c98 | 3655 | max_tx_rate, min_tx_rate); |
bd77bf1c MHY |
3656 | } |
3657 | ||
66e49ded SM |
3658 | static int mlx5_vport_link2ifla(u8 esw_link) |
3659 | { | |
3660 | switch (esw_link) { | |
3661 | case MLX5_ESW_VPORT_ADMIN_STATE_DOWN: | |
3662 | return IFLA_VF_LINK_STATE_DISABLE; | |
3663 | case MLX5_ESW_VPORT_ADMIN_STATE_UP: | |
3664 | return IFLA_VF_LINK_STATE_ENABLE; | |
3665 | } | |
3666 | return IFLA_VF_LINK_STATE_AUTO; | |
3667 | } | |
3668 | ||
3669 | static int mlx5_ifla_link2vport(u8 ifla_link) | |
3670 | { | |
3671 | switch (ifla_link) { | |
3672 | case IFLA_VF_LINK_STATE_DISABLE: | |
3673 | return MLX5_ESW_VPORT_ADMIN_STATE_DOWN; | |
3674 | case IFLA_VF_LINK_STATE_ENABLE: | |
3675 | return MLX5_ESW_VPORT_ADMIN_STATE_UP; | |
3676 | } | |
3677 | return MLX5_ESW_VPORT_ADMIN_STATE_AUTO; | |
3678 | } | |
3679 | ||
3680 | static int mlx5e_set_vf_link_state(struct net_device *dev, int vf, | |
3681 | int link_state) | |
3682 | { | |
3683 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3684 | struct mlx5_core_dev *mdev = priv->mdev; | |
3685 | ||
3686 | return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1, | |
3687 | mlx5_ifla_link2vport(link_state)); | |
3688 | } | |
3689 | ||
3690 | static int mlx5e_get_vf_config(struct net_device *dev, | |
3691 | int vf, struct ifla_vf_info *ivi) | |
3692 | { | |
3693 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3694 | struct mlx5_core_dev *mdev = priv->mdev; | |
3695 | int err; | |
3696 | ||
3697 | err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi); | |
3698 | if (err) | |
3699 | return err; | |
3700 | ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate); | |
3701 | return 0; | |
3702 | } | |
3703 | ||
3704 | static int mlx5e_get_vf_stats(struct net_device *dev, | |
3705 | int vf, struct ifla_vf_stats *vf_stats) | |
3706 | { | |
3707 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3708 | struct mlx5_core_dev *mdev = priv->mdev; | |
3709 | ||
3710 | return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1, | |
3711 | vf_stats); | |
3712 | } | |
e80541ec | 3713 | #endif |
66e49ded | 3714 | |
1ad9a00a PB |
3715 | static void mlx5e_add_vxlan_port(struct net_device *netdev, |
3716 | struct udp_tunnel_info *ti) | |
b3f63c3d MF |
3717 | { |
3718 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3719 | ||
974c3f30 AD |
3720 | if (ti->type != UDP_TUNNEL_TYPE_VXLAN) |
3721 | return; | |
3722 | ||
b3f63c3d MF |
3723 | if (!mlx5e_vxlan_allowed(priv->mdev)) |
3724 | return; | |
3725 | ||
974c3f30 | 3726 | mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1); |
b3f63c3d MF |
3727 | } |
3728 | ||
1ad9a00a PB |
3729 | static void mlx5e_del_vxlan_port(struct net_device *netdev, |
3730 | struct udp_tunnel_info *ti) | |
b3f63c3d MF |
3731 | { |
3732 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3733 | ||
974c3f30 AD |
3734 | if (ti->type != UDP_TUNNEL_TYPE_VXLAN) |
3735 | return; | |
3736 | ||
b3f63c3d MF |
3737 | if (!mlx5e_vxlan_allowed(priv->mdev)) |
3738 | return; | |
3739 | ||
974c3f30 | 3740 | mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0); |
b3f63c3d MF |
3741 | } |
3742 | ||
27299841 GP |
3743 | static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv, |
3744 | struct sk_buff *skb, | |
3745 | netdev_features_t features) | |
b3f63c3d | 3746 | { |
2989ad1e | 3747 | unsigned int offset = 0; |
b3f63c3d | 3748 | struct udphdr *udph; |
27299841 GP |
3749 | u8 proto; |
3750 | u16 port; | |
b3f63c3d MF |
3751 | |
3752 | switch (vlan_get_protocol(skb)) { | |
3753 | case htons(ETH_P_IP): | |
3754 | proto = ip_hdr(skb)->protocol; | |
3755 | break; | |
3756 | case htons(ETH_P_IPV6): | |
2989ad1e | 3757 | proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL); |
b3f63c3d MF |
3758 | break; |
3759 | default: | |
3760 | goto out; | |
3761 | } | |
3762 | ||
27299841 GP |
3763 | switch (proto) { |
3764 | case IPPROTO_GRE: | |
3765 | return features; | |
3766 | case IPPROTO_UDP: | |
b3f63c3d MF |
3767 | udph = udp_hdr(skb); |
3768 | port = be16_to_cpu(udph->dest); | |
b3f63c3d | 3769 | |
27299841 GP |
3770 | /* Verify if UDP port is being offloaded by HW */ |
3771 | if (mlx5e_vxlan_lookup_port(priv, port)) | |
3772 | return features; | |
3773 | } | |
b3f63c3d MF |
3774 | |
3775 | out: | |
3776 | /* Disable CSUM and GSO if the udp dport is not offloaded by HW */ | |
3777 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
3778 | } | |
3779 | ||
3780 | static netdev_features_t mlx5e_features_check(struct sk_buff *skb, | |
3781 | struct net_device *netdev, | |
3782 | netdev_features_t features) | |
3783 | { | |
3784 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3785 | ||
3786 | features = vlan_features_check(skb, features); | |
3787 | features = vxlan_features_check(skb, features); | |
3788 | ||
2ac9cfe7 IT |
3789 | #ifdef CONFIG_MLX5_EN_IPSEC |
3790 | if (mlx5e_ipsec_feature_check(skb, netdev, features)) | |
3791 | return features; | |
3792 | #endif | |
3793 | ||
b3f63c3d MF |
3794 | /* Validate if the tunneled packet is being offloaded by HW */ |
3795 | if (skb->encapsulation && | |
3796 | (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK)) | |
27299841 | 3797 | return mlx5e_tunnel_features_check(priv, skb, features); |
b3f63c3d MF |
3798 | |
3799 | return features; | |
3800 | } | |
3801 | ||
7ca560b5 EBE |
3802 | static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev, |
3803 | struct mlx5e_txqsq *sq) | |
3804 | { | |
7b2117bb | 3805 | struct mlx5_eq *eq = sq->cq.mcq.eq; |
7ca560b5 EBE |
3806 | u32 eqe_count; |
3807 | ||
7ca560b5 | 3808 | netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n", |
7b2117bb | 3809 | eq->eqn, eq->cons_index, eq->irqn); |
7ca560b5 EBE |
3810 | |
3811 | eqe_count = mlx5_eq_poll_irq_disabled(eq); | |
3812 | if (!eqe_count) | |
3813 | return false; | |
3814 | ||
3815 | netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn); | |
57d689a8 | 3816 | sq->channel->stats.eq_rearm++; |
7ca560b5 EBE |
3817 | return true; |
3818 | } | |
3819 | ||
bfc647d5 | 3820 | static void mlx5e_tx_timeout_work(struct work_struct *work) |
3947ca18 | 3821 | { |
bfc647d5 EBE |
3822 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, |
3823 | tx_timeout_work); | |
3824 | struct net_device *dev = priv->netdev; | |
7ca560b5 | 3825 | bool reopen_channels = false; |
bfc647d5 | 3826 | int i, err; |
3947ca18 | 3827 | |
bfc647d5 EBE |
3828 | rtnl_lock(); |
3829 | mutex_lock(&priv->state_lock); | |
3830 | ||
3831 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
3832 | goto unlock; | |
3947ca18 | 3833 | |
6a9764ef | 3834 | for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) { |
84990945 | 3835 | struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i); |
acc6c595 | 3836 | struct mlx5e_txqsq *sq = priv->txq2sq[i]; |
3947ca18 | 3837 | |
84990945 | 3838 | if (!netif_xmit_stopped(dev_queue)) |
3947ca18 | 3839 | continue; |
bfc647d5 EBE |
3840 | |
3841 | netdev_err(dev, | |
3842 | "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n", | |
84990945 EBE |
3843 | i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc, |
3844 | jiffies_to_usecs(jiffies - dev_queue->trans_start)); | |
3a32b26a | 3845 | |
7ca560b5 EBE |
3846 | /* If we recover a lost interrupt, most likely TX timeout will |
3847 | * be resolved, skip reopening channels | |
3848 | */ | |
3849 | if (!mlx5e_tx_timeout_eq_recover(dev, sq)) { | |
3850 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
3851 | reopen_channels = true; | |
3852 | } | |
3947ca18 DJ |
3853 | } |
3854 | ||
bfc647d5 EBE |
3855 | if (!reopen_channels) |
3856 | goto unlock; | |
3857 | ||
3858 | mlx5e_close_locked(dev); | |
3859 | err = mlx5e_open_locked(dev); | |
3860 | if (err) | |
3861 | netdev_err(priv->netdev, | |
3862 | "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n", | |
3863 | err); | |
3864 | ||
3865 | unlock: | |
3866 | mutex_unlock(&priv->state_lock); | |
3867 | rtnl_unlock(); | |
3868 | } | |
3869 | ||
3870 | static void mlx5e_tx_timeout(struct net_device *dev) | |
3871 | { | |
3872 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3873 | ||
3874 | netdev_err(dev, "TX timeout detected\n"); | |
3875 | queue_work(priv->wq, &priv->tx_timeout_work); | |
3947ca18 DJ |
3876 | } |
3877 | ||
86994156 RS |
3878 | static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog) |
3879 | { | |
3880 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3881 | struct bpf_prog *old_prog; | |
3882 | int err = 0; | |
3883 | bool reset, was_opened; | |
3884 | int i; | |
3885 | ||
3886 | mutex_lock(&priv->state_lock); | |
3887 | ||
3888 | if ((netdev->features & NETIF_F_LRO) && prog) { | |
3889 | netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n"); | |
3890 | err = -EINVAL; | |
3891 | goto unlock; | |
3892 | } | |
3893 | ||
547eede0 IT |
3894 | if ((netdev->features & NETIF_F_HW_ESP) && prog) { |
3895 | netdev_warn(netdev, "can't set XDP with IPSec offload\n"); | |
3896 | err = -EINVAL; | |
3897 | goto unlock; | |
3898 | } | |
3899 | ||
86994156 RS |
3900 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); |
3901 | /* no need for full reset when exchanging programs */ | |
6a9764ef | 3902 | reset = (!priv->channels.params.xdp_prog || !prog); |
86994156 RS |
3903 | |
3904 | if (was_opened && reset) | |
3905 | mlx5e_close_locked(netdev); | |
c54c0629 DB |
3906 | if (was_opened && !reset) { |
3907 | /* num_channels is invariant here, so we can take the | |
3908 | * batched reference right upfront. | |
3909 | */ | |
6a9764ef | 3910 | prog = bpf_prog_add(prog, priv->channels.num); |
c54c0629 DB |
3911 | if (IS_ERR(prog)) { |
3912 | err = PTR_ERR(prog); | |
3913 | goto unlock; | |
3914 | } | |
3915 | } | |
86994156 | 3916 | |
c54c0629 DB |
3917 | /* exchange programs, extra prog reference we got from caller |
3918 | * as long as we don't fail from this point onwards. | |
3919 | */ | |
6a9764ef | 3920 | old_prog = xchg(&priv->channels.params.xdp_prog, prog); |
86994156 RS |
3921 | if (old_prog) |
3922 | bpf_prog_put(old_prog); | |
3923 | ||
3924 | if (reset) /* change RQ type according to priv->xdp_prog */ | |
2a0f561b | 3925 | mlx5e_set_rq_type(priv->mdev, &priv->channels.params); |
86994156 RS |
3926 | |
3927 | if (was_opened && reset) | |
3928 | mlx5e_open_locked(netdev); | |
3929 | ||
3930 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset) | |
3931 | goto unlock; | |
3932 | ||
3933 | /* exchanging programs w/o reset, we update ref counts on behalf | |
3934 | * of the channels RQs here. | |
3935 | */ | |
ff9c852f SM |
3936 | for (i = 0; i < priv->channels.num; i++) { |
3937 | struct mlx5e_channel *c = priv->channels.c[i]; | |
86994156 | 3938 | |
c0f1147d | 3939 | clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state); |
86994156 RS |
3940 | napi_synchronize(&c->napi); |
3941 | /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */ | |
3942 | ||
3943 | old_prog = xchg(&c->rq.xdp_prog, prog); | |
3944 | ||
c0f1147d | 3945 | set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state); |
86994156 | 3946 | /* napi_schedule in case we have missed anything */ |
86994156 RS |
3947 | napi_schedule(&c->napi); |
3948 | ||
3949 | if (old_prog) | |
3950 | bpf_prog_put(old_prog); | |
3951 | } | |
3952 | ||
3953 | unlock: | |
3954 | mutex_unlock(&priv->state_lock); | |
3955 | return err; | |
3956 | } | |
3957 | ||
821b2e29 | 3958 | static u32 mlx5e_xdp_query(struct net_device *dev) |
86994156 RS |
3959 | { |
3960 | struct mlx5e_priv *priv = netdev_priv(dev); | |
821b2e29 MKL |
3961 | const struct bpf_prog *xdp_prog; |
3962 | u32 prog_id = 0; | |
86994156 | 3963 | |
821b2e29 MKL |
3964 | mutex_lock(&priv->state_lock); |
3965 | xdp_prog = priv->channels.params.xdp_prog; | |
3966 | if (xdp_prog) | |
3967 | prog_id = xdp_prog->aux->id; | |
3968 | mutex_unlock(&priv->state_lock); | |
3969 | ||
3970 | return prog_id; | |
86994156 RS |
3971 | } |
3972 | ||
f4e63525 | 3973 | static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp) |
86994156 RS |
3974 | { |
3975 | switch (xdp->command) { | |
3976 | case XDP_SETUP_PROG: | |
3977 | return mlx5e_xdp_set(dev, xdp->prog); | |
3978 | case XDP_QUERY_PROG: | |
821b2e29 MKL |
3979 | xdp->prog_id = mlx5e_xdp_query(dev); |
3980 | xdp->prog_attached = !!xdp->prog_id; | |
86994156 RS |
3981 | return 0; |
3982 | default: | |
3983 | return -EINVAL; | |
3984 | } | |
3985 | } | |
3986 | ||
80378384 CO |
3987 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3988 | /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without | |
3989 | * reenabling interrupts. | |
3990 | */ | |
3991 | static void mlx5e_netpoll(struct net_device *dev) | |
3992 | { | |
3993 | struct mlx5e_priv *priv = netdev_priv(dev); | |
ff9c852f SM |
3994 | struct mlx5e_channels *chs = &priv->channels; |
3995 | ||
80378384 CO |
3996 | int i; |
3997 | ||
ff9c852f SM |
3998 | for (i = 0; i < chs->num; i++) |
3999 | napi_schedule(&chs->c[i]->napi); | |
80378384 CO |
4000 | } |
4001 | #endif | |
4002 | ||
e80541ec | 4003 | static const struct net_device_ops mlx5e_netdev_ops = { |
f62b8bb8 AV |
4004 | .ndo_open = mlx5e_open, |
4005 | .ndo_stop = mlx5e_close, | |
4006 | .ndo_start_xmit = mlx5e_xmit, | |
0cf0f6d3 | 4007 | .ndo_setup_tc = mlx5e_setup_tc, |
08fb1dac | 4008 | .ndo_select_queue = mlx5e_select_queue, |
f62b8bb8 AV |
4009 | .ndo_get_stats64 = mlx5e_get_stats, |
4010 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
4011 | .ndo_set_mac_address = mlx5e_set_mac, | |
b0eed40e SM |
4012 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, |
4013 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
f62b8bb8 | 4014 | .ndo_set_features = mlx5e_set_features, |
7d92d580 | 4015 | .ndo_fix_features = mlx5e_fix_features, |
b0eed40e SM |
4016 | .ndo_change_mtu = mlx5e_change_mtu, |
4017 | .ndo_do_ioctl = mlx5e_ioctl, | |
507f0c81 | 4018 | .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate, |
706b3583 SM |
4019 | .ndo_udp_tunnel_add = mlx5e_add_vxlan_port, |
4020 | .ndo_udp_tunnel_del = mlx5e_del_vxlan_port, | |
4021 | .ndo_features_check = mlx5e_features_check, | |
45bf454a MG |
4022 | #ifdef CONFIG_RFS_ACCEL |
4023 | .ndo_rx_flow_steer = mlx5e_rx_flow_steer, | |
4024 | #endif | |
3947ca18 | 4025 | .ndo_tx_timeout = mlx5e_tx_timeout, |
f4e63525 | 4026 | .ndo_bpf = mlx5e_xdp, |
80378384 CO |
4027 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4028 | .ndo_poll_controller = mlx5e_netpoll, | |
4029 | #endif | |
e80541ec | 4030 | #ifdef CONFIG_MLX5_ESWITCH |
706b3583 | 4031 | /* SRIOV E-Switch NDOs */ |
b0eed40e SM |
4032 | .ndo_set_vf_mac = mlx5e_set_vf_mac, |
4033 | .ndo_set_vf_vlan = mlx5e_set_vf_vlan, | |
f942380c | 4034 | .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk, |
1edc57e2 | 4035 | .ndo_set_vf_trust = mlx5e_set_vf_trust, |
bd77bf1c | 4036 | .ndo_set_vf_rate = mlx5e_set_vf_rate, |
b0eed40e SM |
4037 | .ndo_get_vf_config = mlx5e_get_vf_config, |
4038 | .ndo_set_vf_link_state = mlx5e_set_vf_link_state, | |
4039 | .ndo_get_vf_stats = mlx5e_get_vf_stats, | |
370bad0f OG |
4040 | .ndo_has_offload_stats = mlx5e_has_offload_stats, |
4041 | .ndo_get_offload_stats = mlx5e_get_offload_stats, | |
e80541ec | 4042 | #endif |
f62b8bb8 AV |
4043 | }; |
4044 | ||
4045 | static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) | |
4046 | { | |
4047 | if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
9eb78923 | 4048 | return -EOPNOTSUPP; |
f62b8bb8 AV |
4049 | if (!MLX5_CAP_GEN(mdev, eth_net_offloads) || |
4050 | !MLX5_CAP_GEN(mdev, nic_flow_table) || | |
4051 | !MLX5_CAP_ETH(mdev, csum_cap) || | |
4052 | !MLX5_CAP_ETH(mdev, max_lso_cap) || | |
4053 | !MLX5_CAP_ETH(mdev, vlan_cap) || | |
796a27ec GP |
4054 | !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) || |
4055 | MLX5_CAP_FLOWTABLE(mdev, | |
4056 | flow_table_properties_nic_receive.max_ft_level) | |
4057 | < 3) { | |
f62b8bb8 AV |
4058 | mlx5_core_warn(mdev, |
4059 | "Not creating net device, some required device capabilities are missing\n"); | |
9eb78923 | 4060 | return -EOPNOTSUPP; |
f62b8bb8 | 4061 | } |
66189961 TT |
4062 | if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable)) |
4063 | mlx5_core_warn(mdev, "Self loop back prevention is not supported\n"); | |
7524a5d8 | 4064 | if (!MLX5_CAP_GEN(mdev, cq_moderation)) |
3e432ab6 | 4065 | mlx5_core_warn(mdev, "CQ moderation is not supported\n"); |
66189961 | 4066 | |
f62b8bb8 AV |
4067 | return 0; |
4068 | } | |
4069 | ||
d4b6c488 | 4070 | void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, |
85082dba TT |
4071 | int num_channels) |
4072 | { | |
4073 | int i; | |
4074 | ||
4075 | for (i = 0; i < len; i++) | |
4076 | indirection_rqt[i] = i % num_channels; | |
4077 | } | |
4078 | ||
0608d4db | 4079 | static bool slow_pci_heuristic(struct mlx5_core_dev *mdev) |
b797a684 | 4080 | { |
0608d4db TT |
4081 | u32 link_speed = 0; |
4082 | u32 pci_bw = 0; | |
b797a684 | 4083 | |
0608d4db | 4084 | mlx5e_get_max_linkspeed(mdev, &link_speed); |
3c0d551e | 4085 | pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL); |
0608d4db TT |
4086 | mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n", |
4087 | link_speed, pci_bw); | |
4088 | ||
4089 | #define MLX5E_SLOW_PCI_RATIO (2) | |
4090 | ||
4091 | return link_speed && pci_bw && | |
4092 | link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw; | |
0f6e4cf6 EBE |
4093 | } |
4094 | ||
cbce4f44 | 4095 | static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode) |
0088cbbc | 4096 | { |
cbce4f44 TG |
4097 | struct net_dim_cq_moder moder; |
4098 | ||
4099 | moder.cq_period_mode = cq_period_mode; | |
4100 | moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; | |
4101 | moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; | |
4102 | if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) | |
4103 | moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE; | |
4104 | ||
4105 | return moder; | |
4106 | } | |
0088cbbc | 4107 | |
cbce4f44 TG |
4108 | static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode) |
4109 | { | |
4110 | struct net_dim_cq_moder moder; | |
0088cbbc | 4111 | |
cbce4f44 TG |
4112 | moder.cq_period_mode = cq_period_mode; |
4113 | moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; | |
4114 | moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; | |
0088cbbc | 4115 | if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) |
cbce4f44 TG |
4116 | moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE; |
4117 | ||
4118 | return moder; | |
4119 | } | |
4120 | ||
4121 | static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode) | |
4122 | { | |
4123 | return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ? | |
4124 | NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE : | |
4125 | NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; | |
4126 | } | |
4127 | ||
4128 | void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) | |
4129 | { | |
4130 | if (params->tx_dim_enabled) { | |
4131 | u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); | |
4132 | ||
4133 | params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode); | |
4134 | } else { | |
4135 | params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode); | |
4136 | } | |
0088cbbc TG |
4137 | |
4138 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER, | |
4139 | params->tx_cq_moderation.cq_period_mode == | |
4140 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE); | |
4141 | } | |
4142 | ||
9908aa29 TT |
4143 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) |
4144 | { | |
9a317425 | 4145 | if (params->rx_dim_enabled) { |
cbce4f44 TG |
4146 | u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); |
4147 | ||
4148 | params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode); | |
4149 | } else { | |
4150 | params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode); | |
9a317425 | 4151 | } |
457fcd8a | 4152 | |
6a9764ef | 4153 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER, |
0088cbbc TG |
4154 | params->rx_cq_moderation.cq_period_mode == |
4155 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE); | |
9908aa29 TT |
4156 | } |
4157 | ||
707129dc | 4158 | static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout) |
2b029556 SM |
4159 | { |
4160 | int i; | |
4161 | ||
4162 | /* The supported periods are organized in ascending order */ | |
4163 | for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++) | |
4164 | if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout) | |
4165 | break; | |
4166 | ||
4167 | return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]); | |
4168 | } | |
4169 | ||
8f493ffd SM |
4170 | void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, |
4171 | struct mlx5e_params *params, | |
472a1e44 | 4172 | u16 max_channels, u16 mtu) |
f62b8bb8 | 4173 | { |
48bfc397 | 4174 | u8 rx_cq_period_mode; |
2fc4bfb7 | 4175 | |
472a1e44 TT |
4176 | params->sw_mtu = mtu; |
4177 | params->hard_mtu = MLX5E_ETH_HARD_MTU; | |
6a9764ef SM |
4178 | params->num_channels = max_channels; |
4179 | params->num_tc = 1; | |
2b029556 | 4180 | |
6a9764ef SM |
4181 | /* SQ */ |
4182 | params->log_sq_size = is_kdump_kernel() ? | |
b4e029da KH |
4183 | MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE : |
4184 | MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; | |
461017cb | 4185 | |
b797a684 | 4186 | /* set CQE compression */ |
6a9764ef | 4187 | params->rx_cqe_compress_def = false; |
b797a684 | 4188 | if (MLX5_CAP_GEN(mdev, cqe_compression) && |
e53eef63 | 4189 | MLX5_CAP_GEN(mdev, vport_group_manager)) |
0608d4db | 4190 | params->rx_cqe_compress_def = slow_pci_heuristic(mdev); |
0f6e4cf6 | 4191 | |
6a9764ef SM |
4192 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def); |
4193 | ||
4194 | /* RQ */ | |
2ccb0a79 TT |
4195 | if (mlx5e_striding_rq_possible(mdev, params)) |
4196 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, | |
4197 | !slow_pci_heuristic(mdev)); | |
2a0f561b TT |
4198 | mlx5e_set_rq_type(mdev, params); |
4199 | mlx5e_init_rq_type_params(mdev, params); | |
b797a684 | 4200 | |
6a9764ef | 4201 | /* HW LRO */ |
c139dbfd | 4202 | |
5426a0b2 | 4203 | /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */ |
6a9764ef | 4204 | if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) |
619a8f2a TT |
4205 | if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params)) |
4206 | params->lro_en = !slow_pci_heuristic(mdev); | |
6a9764ef | 4207 | params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT); |
b0d4660b | 4208 | |
6a9764ef | 4209 | /* CQ moderation params */ |
48bfc397 | 4210 | rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? |
6a9764ef SM |
4211 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE : |
4212 | MLX5_CQ_PERIOD_MODE_START_FROM_EQE; | |
9a317425 | 4213 | params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation); |
cbce4f44 | 4214 | params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation); |
48bfc397 TG |
4215 | mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode); |
4216 | mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); | |
9908aa29 | 4217 | |
6a9764ef | 4218 | /* TX inline */ |
fbcb127e | 4219 | params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev); |
a6f402e4 | 4220 | |
6a9764ef SM |
4221 | /* RSS */ |
4222 | params->rss_hfunc = ETH_RSS_HASH_XOR; | |
4223 | netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key)); | |
d4b6c488 | 4224 | mlx5e_build_default_indir_rqt(params->indirection_rqt, |
6a9764ef SM |
4225 | MLX5E_INDIR_RQT_SIZE, max_channels); |
4226 | } | |
f62b8bb8 | 4227 | |
6a9764ef SM |
4228 | static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev, |
4229 | struct net_device *netdev, | |
4230 | const struct mlx5e_profile *profile, | |
4231 | void *ppriv) | |
4232 | { | |
4233 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
57afead5 | 4234 | |
6a9764ef SM |
4235 | priv->mdev = mdev; |
4236 | priv->netdev = netdev; | |
4237 | priv->profile = profile; | |
4238 | priv->ppriv = ppriv; | |
79c48764 | 4239 | priv->msglevel = MLX5E_MSG_LEVEL; |
2d75b2bc | 4240 | |
472a1e44 TT |
4241 | mlx5e_build_nic_params(mdev, &priv->channels.params, |
4242 | profile->max_nch(mdev), netdev->mtu); | |
9908aa29 | 4243 | |
f62b8bb8 AV |
4244 | mutex_init(&priv->state_lock); |
4245 | ||
4246 | INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); | |
4247 | INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); | |
3947ca18 | 4248 | INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work); |
f62b8bb8 | 4249 | INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work); |
237f258c FD |
4250 | |
4251 | mlx5e_timestamp_init(priv); | |
f62b8bb8 AV |
4252 | } |
4253 | ||
4254 | static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) | |
4255 | { | |
4256 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
4257 | ||
e1d7d349 | 4258 | mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr); |
108805fc SM |
4259 | if (is_zero_ether_addr(netdev->dev_addr) && |
4260 | !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) { | |
4261 | eth_hw_addr_random(netdev); | |
4262 | mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr); | |
4263 | } | |
f62b8bb8 AV |
4264 | } |
4265 | ||
f125376b | 4266 | #if IS_ENABLED(CONFIG_MLX5_ESWITCH) |
cb67b832 HHZ |
4267 | static const struct switchdev_ops mlx5e_switchdev_ops = { |
4268 | .switchdev_port_attr_get = mlx5e_attr_get, | |
4269 | }; | |
e80541ec | 4270 | #endif |
cb67b832 | 4271 | |
6bfd390b | 4272 | static void mlx5e_build_nic_netdev(struct net_device *netdev) |
f62b8bb8 AV |
4273 | { |
4274 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
4275 | struct mlx5_core_dev *mdev = priv->mdev; | |
94cb1ebb EBE |
4276 | bool fcs_supported; |
4277 | bool fcs_enabled; | |
f62b8bb8 AV |
4278 | |
4279 | SET_NETDEV_DEV(netdev, &mdev->pdev->dev); | |
4280 | ||
e80541ec SM |
4281 | netdev->netdev_ops = &mlx5e_netdev_ops; |
4282 | ||
08fb1dac | 4283 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
e80541ec SM |
4284 | if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos)) |
4285 | netdev->dcbnl_ops = &mlx5e_dcbnl_ops; | |
08fb1dac | 4286 | #endif |
66e49ded | 4287 | |
f62b8bb8 AV |
4288 | netdev->watchdog_timeo = 15 * HZ; |
4289 | ||
4290 | netdev->ethtool_ops = &mlx5e_ethtool_ops; | |
4291 | ||
12be4b21 | 4292 | netdev->vlan_features |= NETIF_F_SG; |
f62b8bb8 AV |
4293 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
4294 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; | |
4295 | netdev->vlan_features |= NETIF_F_GRO; | |
4296 | netdev->vlan_features |= NETIF_F_TSO; | |
4297 | netdev->vlan_features |= NETIF_F_TSO6; | |
4298 | netdev->vlan_features |= NETIF_F_RXCSUM; | |
4299 | netdev->vlan_features |= NETIF_F_RXHASH; | |
4300 | ||
71186172 AH |
4301 | netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX; |
4302 | netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX; | |
4303 | ||
f62b8bb8 AV |
4304 | if (!!MLX5_CAP_ETH(mdev, lro_cap)) |
4305 | netdev->vlan_features |= NETIF_F_LRO; | |
4306 | ||
4307 | netdev->hw_features = netdev->vlan_features; | |
e4cf27bd | 4308 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; |
f62b8bb8 AV |
4309 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; |
4310 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
4382c7b9 | 4311 | netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX; |
f62b8bb8 | 4312 | |
27299841 GP |
4313 | if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) { |
4314 | netdev->hw_features |= NETIF_F_GSO_PARTIAL; | |
b3f63c3d | 4315 | netdev->hw_enc_features |= NETIF_F_IP_CSUM; |
f3ed653c | 4316 | netdev->hw_enc_features |= NETIF_F_IPV6_CSUM; |
b3f63c3d MF |
4317 | netdev->hw_enc_features |= NETIF_F_TSO; |
4318 | netdev->hw_enc_features |= NETIF_F_TSO6; | |
27299841 GP |
4319 | netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL; |
4320 | } | |
4321 | ||
4322 | if (mlx5e_vxlan_allowed(mdev)) { | |
4323 | netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | | |
4324 | NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
4325 | netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL | | |
4326 | NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
b49663c8 | 4327 | netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM; |
b3f63c3d MF |
4328 | } |
4329 | ||
27299841 GP |
4330 | if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) { |
4331 | netdev->hw_features |= NETIF_F_GSO_GRE | | |
4332 | NETIF_F_GSO_GRE_CSUM; | |
4333 | netdev->hw_enc_features |= NETIF_F_GSO_GRE | | |
4334 | NETIF_F_GSO_GRE_CSUM; | |
4335 | netdev->gso_partial_features |= NETIF_F_GSO_GRE | | |
4336 | NETIF_F_GSO_GRE_CSUM; | |
4337 | } | |
4338 | ||
94cb1ebb EBE |
4339 | mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled); |
4340 | ||
4341 | if (fcs_supported) | |
4342 | netdev->hw_features |= NETIF_F_RXALL; | |
4343 | ||
102722fc GE |
4344 | if (MLX5_CAP_ETH(mdev, scatter_fcs)) |
4345 | netdev->hw_features |= NETIF_F_RXFCS; | |
4346 | ||
f62b8bb8 | 4347 | netdev->features = netdev->hw_features; |
6a9764ef | 4348 | if (!priv->channels.params.lro_en) |
f62b8bb8 AV |
4349 | netdev->features &= ~NETIF_F_LRO; |
4350 | ||
94cb1ebb EBE |
4351 | if (fcs_enabled) |
4352 | netdev->features &= ~NETIF_F_RXALL; | |
4353 | ||
102722fc GE |
4354 | if (!priv->channels.params.scatter_fcs_en) |
4355 | netdev->features &= ~NETIF_F_RXFCS; | |
4356 | ||
e8f887ac AV |
4357 | #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f) |
4358 | if (FT_CAP(flow_modify_en) && | |
4359 | FT_CAP(modify_root) && | |
4360 | FT_CAP(identified_miss_table_mode) && | |
1cabe6b0 MG |
4361 | FT_CAP(flow_table_modify)) { |
4362 | netdev->hw_features |= NETIF_F_HW_TC; | |
4363 | #ifdef CONFIG_RFS_ACCEL | |
4364 | netdev->hw_features |= NETIF_F_NTUPLE; | |
4365 | #endif | |
4366 | } | |
e8f887ac | 4367 | |
f62b8bb8 | 4368 | netdev->features |= NETIF_F_HIGHDMA; |
7d92d580 | 4369 | netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER; |
f62b8bb8 AV |
4370 | |
4371 | netdev->priv_flags |= IFF_UNICAST_FLT; | |
4372 | ||
4373 | mlx5e_set_netdev_dev_addr(netdev); | |
cb67b832 | 4374 | |
f125376b | 4375 | #if IS_ENABLED(CONFIG_MLX5_ESWITCH) |
a9f7705f | 4376 | if (MLX5_VPORT_MANAGER(mdev)) |
cb67b832 HHZ |
4377 | netdev->switchdev_ops = &mlx5e_switchdev_ops; |
4378 | #endif | |
547eede0 IT |
4379 | |
4380 | mlx5e_ipsec_build_netdev(priv); | |
c83294b9 | 4381 | mlx5e_tls_build_netdev(priv); |
f62b8bb8 AV |
4382 | } |
4383 | ||
7cbaf9a3 | 4384 | static void mlx5e_create_q_counters(struct mlx5e_priv *priv) |
593cf338 RS |
4385 | { |
4386 | struct mlx5_core_dev *mdev = priv->mdev; | |
4387 | int err; | |
4388 | ||
4389 | err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter); | |
4390 | if (err) { | |
4391 | mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err); | |
4392 | priv->q_counter = 0; | |
4393 | } | |
7cbaf9a3 MS |
4394 | |
4395 | err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter); | |
4396 | if (err) { | |
4397 | mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err); | |
4398 | priv->drop_rq_q_counter = 0; | |
4399 | } | |
593cf338 RS |
4400 | } |
4401 | ||
7cbaf9a3 | 4402 | static void mlx5e_destroy_q_counters(struct mlx5e_priv *priv) |
593cf338 | 4403 | { |
7cbaf9a3 MS |
4404 | if (priv->q_counter) |
4405 | mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter); | |
593cf338 | 4406 | |
7cbaf9a3 MS |
4407 | if (priv->drop_rq_q_counter) |
4408 | mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter); | |
593cf338 RS |
4409 | } |
4410 | ||
6bfd390b HHZ |
4411 | static void mlx5e_nic_init(struct mlx5_core_dev *mdev, |
4412 | struct net_device *netdev, | |
127ea380 HHZ |
4413 | const struct mlx5e_profile *profile, |
4414 | void *ppriv) | |
6bfd390b HHZ |
4415 | { |
4416 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
547eede0 | 4417 | int err; |
6bfd390b | 4418 | |
127ea380 | 4419 | mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv); |
547eede0 IT |
4420 | err = mlx5e_ipsec_init(priv); |
4421 | if (err) | |
4422 | mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err); | |
43585a41 IL |
4423 | err = mlx5e_tls_init(priv); |
4424 | if (err) | |
4425 | mlx5_core_err(mdev, "TLS initialization failed, %d\n", err); | |
6bfd390b HHZ |
4426 | mlx5e_build_nic_netdev(netdev); |
4427 | mlx5e_vxlan_init(priv); | |
4428 | } | |
4429 | ||
4430 | static void mlx5e_nic_cleanup(struct mlx5e_priv *priv) | |
4431 | { | |
43585a41 | 4432 | mlx5e_tls_cleanup(priv); |
547eede0 | 4433 | mlx5e_ipsec_cleanup(priv); |
6bfd390b HHZ |
4434 | mlx5e_vxlan_cleanup(priv); |
4435 | } | |
4436 | ||
4437 | static int mlx5e_init_nic_rx(struct mlx5e_priv *priv) | |
4438 | { | |
4439 | struct mlx5_core_dev *mdev = priv->mdev; | |
4440 | int err; | |
6bfd390b | 4441 | |
8f493ffd SM |
4442 | err = mlx5e_create_indirect_rqt(priv); |
4443 | if (err) | |
6bfd390b | 4444 | return err; |
6bfd390b HHZ |
4445 | |
4446 | err = mlx5e_create_direct_rqts(priv); | |
8f493ffd | 4447 | if (err) |
6bfd390b | 4448 | goto err_destroy_indirect_rqts; |
6bfd390b HHZ |
4449 | |
4450 | err = mlx5e_create_indirect_tirs(priv); | |
8f493ffd | 4451 | if (err) |
6bfd390b | 4452 | goto err_destroy_direct_rqts; |
6bfd390b HHZ |
4453 | |
4454 | err = mlx5e_create_direct_tirs(priv); | |
8f493ffd | 4455 | if (err) |
6bfd390b | 4456 | goto err_destroy_indirect_tirs; |
6bfd390b HHZ |
4457 | |
4458 | err = mlx5e_create_flow_steering(priv); | |
4459 | if (err) { | |
4460 | mlx5_core_warn(mdev, "create flow steering failed, %d\n", err); | |
4461 | goto err_destroy_direct_tirs; | |
4462 | } | |
4463 | ||
4464 | err = mlx5e_tc_init(priv); | |
4465 | if (err) | |
4466 | goto err_destroy_flow_steering; | |
4467 | ||
4468 | return 0; | |
4469 | ||
4470 | err_destroy_flow_steering: | |
4471 | mlx5e_destroy_flow_steering(priv); | |
4472 | err_destroy_direct_tirs: | |
4473 | mlx5e_destroy_direct_tirs(priv); | |
4474 | err_destroy_indirect_tirs: | |
4475 | mlx5e_destroy_indirect_tirs(priv); | |
4476 | err_destroy_direct_rqts: | |
8f493ffd | 4477 | mlx5e_destroy_direct_rqts(priv); |
6bfd390b HHZ |
4478 | err_destroy_indirect_rqts: |
4479 | mlx5e_destroy_rqt(priv, &priv->indir_rqt); | |
4480 | return err; | |
4481 | } | |
4482 | ||
4483 | static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv) | |
4484 | { | |
6bfd390b HHZ |
4485 | mlx5e_tc_cleanup(priv); |
4486 | mlx5e_destroy_flow_steering(priv); | |
4487 | mlx5e_destroy_direct_tirs(priv); | |
4488 | mlx5e_destroy_indirect_tirs(priv); | |
8f493ffd | 4489 | mlx5e_destroy_direct_rqts(priv); |
6bfd390b HHZ |
4490 | mlx5e_destroy_rqt(priv, &priv->indir_rqt); |
4491 | } | |
4492 | ||
4493 | static int mlx5e_init_nic_tx(struct mlx5e_priv *priv) | |
4494 | { | |
4495 | int err; | |
4496 | ||
4497 | err = mlx5e_create_tises(priv); | |
4498 | if (err) { | |
4499 | mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err); | |
4500 | return err; | |
4501 | } | |
4502 | ||
4503 | #ifdef CONFIG_MLX5_CORE_EN_DCB | |
e207b7e9 | 4504 | mlx5e_dcbnl_initialize(priv); |
6bfd390b HHZ |
4505 | #endif |
4506 | return 0; | |
4507 | } | |
4508 | ||
4509 | static void mlx5e_nic_enable(struct mlx5e_priv *priv) | |
4510 | { | |
4511 | struct net_device *netdev = priv->netdev; | |
4512 | struct mlx5_core_dev *mdev = priv->mdev; | |
2c3b5bee SM |
4513 | u16 max_mtu; |
4514 | ||
4515 | mlx5e_init_l2_addr(priv); | |
4516 | ||
63bfd399 EBE |
4517 | /* Marking the link as currently not needed by the Driver */ |
4518 | if (!netif_running(netdev)) | |
4519 | mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN); | |
4520 | ||
2c3b5bee SM |
4521 | /* MTU range: 68 - hw-specific max */ |
4522 | netdev->min_mtu = ETH_MIN_MTU; | |
4523 | mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1); | |
472a1e44 | 4524 | netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu); |
2c3b5bee | 4525 | mlx5e_set_dev_port_mtu(priv); |
6bfd390b | 4526 | |
7907f23a AH |
4527 | mlx5_lag_add(mdev, netdev); |
4528 | ||
6bfd390b | 4529 | mlx5e_enable_async_events(priv); |
127ea380 | 4530 | |
a9f7705f | 4531 | if (MLX5_VPORT_MANAGER(priv->mdev)) |
1d447a39 | 4532 | mlx5e_register_vport_reps(priv); |
2c3b5bee | 4533 | |
610e89e0 SM |
4534 | if (netdev->reg_state != NETREG_REGISTERED) |
4535 | return; | |
2a5e7a13 HN |
4536 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
4537 | mlx5e_dcbnl_init_app(priv); | |
4538 | #endif | |
610e89e0 SM |
4539 | |
4540 | queue_work(priv->wq, &priv->set_rx_mode_work); | |
2c3b5bee SM |
4541 | |
4542 | rtnl_lock(); | |
4543 | if (netif_running(netdev)) | |
4544 | mlx5e_open(netdev); | |
4545 | netif_device_attach(netdev); | |
4546 | rtnl_unlock(); | |
6bfd390b HHZ |
4547 | } |
4548 | ||
4549 | static void mlx5e_nic_disable(struct mlx5e_priv *priv) | |
4550 | { | |
3deef8ce | 4551 | struct mlx5_core_dev *mdev = priv->mdev; |
3deef8ce | 4552 | |
2a5e7a13 HN |
4553 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
4554 | if (priv->netdev->reg_state == NETREG_REGISTERED) | |
4555 | mlx5e_dcbnl_delete_app(priv); | |
4556 | #endif | |
4557 | ||
2c3b5bee SM |
4558 | rtnl_lock(); |
4559 | if (netif_running(priv->netdev)) | |
4560 | mlx5e_close(priv->netdev); | |
4561 | netif_device_detach(priv->netdev); | |
4562 | rtnl_unlock(); | |
4563 | ||
6bfd390b | 4564 | queue_work(priv->wq, &priv->set_rx_mode_work); |
1d447a39 | 4565 | |
a9f7705f | 4566 | if (MLX5_VPORT_MANAGER(priv->mdev)) |
1d447a39 SM |
4567 | mlx5e_unregister_vport_reps(priv); |
4568 | ||
6bfd390b | 4569 | mlx5e_disable_async_events(priv); |
3deef8ce | 4570 | mlx5_lag_remove(mdev); |
6bfd390b HHZ |
4571 | } |
4572 | ||
4573 | static const struct mlx5e_profile mlx5e_nic_profile = { | |
4574 | .init = mlx5e_nic_init, | |
4575 | .cleanup = mlx5e_nic_cleanup, | |
4576 | .init_rx = mlx5e_init_nic_rx, | |
4577 | .cleanup_rx = mlx5e_cleanup_nic_rx, | |
4578 | .init_tx = mlx5e_init_nic_tx, | |
4579 | .cleanup_tx = mlx5e_cleanup_nic_tx, | |
4580 | .enable = mlx5e_nic_enable, | |
4581 | .disable = mlx5e_nic_disable, | |
3834a5e6 | 4582 | .update_stats = mlx5e_update_ndo_stats, |
6bfd390b | 4583 | .max_nch = mlx5e_get_max_num_channels, |
7ca42c80 | 4584 | .update_carrier = mlx5e_update_carrier, |
20fd0c19 SM |
4585 | .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe, |
4586 | .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq, | |
6bfd390b HHZ |
4587 | .max_tc = MLX5E_MAX_NUM_TC, |
4588 | }; | |
4589 | ||
2c3b5bee SM |
4590 | /* mlx5e generic netdev management API (move to en_common.c) */ |
4591 | ||
26e59d80 MHY |
4592 | struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev, |
4593 | const struct mlx5e_profile *profile, | |
4594 | void *ppriv) | |
f62b8bb8 | 4595 | { |
26e59d80 | 4596 | int nch = profile->max_nch(mdev); |
f62b8bb8 AV |
4597 | struct net_device *netdev; |
4598 | struct mlx5e_priv *priv; | |
f62b8bb8 | 4599 | |
08fb1dac | 4600 | netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), |
6bfd390b | 4601 | nch * profile->max_tc, |
08fb1dac | 4602 | nch); |
f62b8bb8 AV |
4603 | if (!netdev) { |
4604 | mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n"); | |
4605 | return NULL; | |
4606 | } | |
4607 | ||
be4891af SM |
4608 | #ifdef CONFIG_RFS_ACCEL |
4609 | netdev->rx_cpu_rmap = mdev->rmap; | |
4610 | #endif | |
4611 | ||
127ea380 | 4612 | profile->init(mdev, netdev, profile, ppriv); |
f62b8bb8 AV |
4613 | |
4614 | netif_carrier_off(netdev); | |
4615 | ||
4616 | priv = netdev_priv(netdev); | |
4617 | ||
7bb29755 MF |
4618 | priv->wq = create_singlethread_workqueue("mlx5e"); |
4619 | if (!priv->wq) | |
26e59d80 MHY |
4620 | goto err_cleanup_nic; |
4621 | ||
4622 | return netdev; | |
4623 | ||
4624 | err_cleanup_nic: | |
31ac9338 OG |
4625 | if (profile->cleanup) |
4626 | profile->cleanup(priv); | |
26e59d80 MHY |
4627 | free_netdev(netdev); |
4628 | ||
4629 | return NULL; | |
4630 | } | |
4631 | ||
2c3b5bee | 4632 | int mlx5e_attach_netdev(struct mlx5e_priv *priv) |
26e59d80 | 4633 | { |
2c3b5bee | 4634 | struct mlx5_core_dev *mdev = priv->mdev; |
26e59d80 | 4635 | const struct mlx5e_profile *profile; |
26e59d80 MHY |
4636 | int err; |
4637 | ||
26e59d80 MHY |
4638 | profile = priv->profile; |
4639 | clear_bit(MLX5E_STATE_DESTROYING, &priv->state); | |
7bb29755 | 4640 | |
6bfd390b HHZ |
4641 | err = profile->init_tx(priv); |
4642 | if (err) | |
ec8b9981 | 4643 | goto out; |
5c50368f | 4644 | |
7cbaf9a3 MS |
4645 | mlx5e_create_q_counters(priv); |
4646 | ||
4647 | err = mlx5e_open_drop_rq(priv, &priv->drop_rq); | |
5c50368f AS |
4648 | if (err) { |
4649 | mlx5_core_err(mdev, "open drop rq failed, %d\n", err); | |
7cbaf9a3 | 4650 | goto err_destroy_q_counters; |
5c50368f AS |
4651 | } |
4652 | ||
6bfd390b HHZ |
4653 | err = profile->init_rx(priv); |
4654 | if (err) | |
5c50368f | 4655 | goto err_close_drop_rq; |
5c50368f | 4656 | |
6bfd390b HHZ |
4657 | if (profile->enable) |
4658 | profile->enable(priv); | |
f62b8bb8 | 4659 | |
26e59d80 | 4660 | return 0; |
5c50368f AS |
4661 | |
4662 | err_close_drop_rq: | |
a43b25da | 4663 | mlx5e_close_drop_rq(&priv->drop_rq); |
5c50368f | 4664 | |
7cbaf9a3 MS |
4665 | err_destroy_q_counters: |
4666 | mlx5e_destroy_q_counters(priv); | |
6bfd390b | 4667 | profile->cleanup_tx(priv); |
5c50368f | 4668 | |
26e59d80 MHY |
4669 | out: |
4670 | return err; | |
f62b8bb8 AV |
4671 | } |
4672 | ||
2c3b5bee | 4673 | void mlx5e_detach_netdev(struct mlx5e_priv *priv) |
26e59d80 | 4674 | { |
26e59d80 MHY |
4675 | const struct mlx5e_profile *profile = priv->profile; |
4676 | ||
4677 | set_bit(MLX5E_STATE_DESTROYING, &priv->state); | |
26e59d80 | 4678 | |
37f304d1 SM |
4679 | if (profile->disable) |
4680 | profile->disable(priv); | |
4681 | flush_workqueue(priv->wq); | |
4682 | ||
26e59d80 | 4683 | profile->cleanup_rx(priv); |
a43b25da | 4684 | mlx5e_close_drop_rq(&priv->drop_rq); |
7cbaf9a3 | 4685 | mlx5e_destroy_q_counters(priv); |
26e59d80 | 4686 | profile->cleanup_tx(priv); |
26e59d80 MHY |
4687 | cancel_delayed_work_sync(&priv->update_stats_work); |
4688 | } | |
4689 | ||
2c3b5bee SM |
4690 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv) |
4691 | { | |
4692 | const struct mlx5e_profile *profile = priv->profile; | |
4693 | struct net_device *netdev = priv->netdev; | |
4694 | ||
4695 | destroy_workqueue(priv->wq); | |
4696 | if (profile->cleanup) | |
4697 | profile->cleanup(priv); | |
4698 | free_netdev(netdev); | |
4699 | } | |
4700 | ||
26e59d80 MHY |
4701 | /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying |
4702 | * hardware contexts and to connect it to the current netdev. | |
4703 | */ | |
4704 | static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv) | |
4705 | { | |
4706 | struct mlx5e_priv *priv = vpriv; | |
4707 | struct net_device *netdev = priv->netdev; | |
4708 | int err; | |
4709 | ||
4710 | if (netif_device_present(netdev)) | |
4711 | return 0; | |
4712 | ||
4713 | err = mlx5e_create_mdev_resources(mdev); | |
4714 | if (err) | |
4715 | return err; | |
4716 | ||
2c3b5bee | 4717 | err = mlx5e_attach_netdev(priv); |
26e59d80 MHY |
4718 | if (err) { |
4719 | mlx5e_destroy_mdev_resources(mdev); | |
4720 | return err; | |
4721 | } | |
4722 | ||
4723 | return 0; | |
4724 | } | |
4725 | ||
4726 | static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv) | |
4727 | { | |
4728 | struct mlx5e_priv *priv = vpriv; | |
4729 | struct net_device *netdev = priv->netdev; | |
4730 | ||
4731 | if (!netif_device_present(netdev)) | |
4732 | return; | |
4733 | ||
2c3b5bee | 4734 | mlx5e_detach_netdev(priv); |
26e59d80 MHY |
4735 | mlx5e_destroy_mdev_resources(mdev); |
4736 | } | |
4737 | ||
b50d292b HHZ |
4738 | static void *mlx5e_add(struct mlx5_core_dev *mdev) |
4739 | { | |
07c9f1e5 SM |
4740 | struct net_device *netdev; |
4741 | void *rpriv = NULL; | |
26e59d80 | 4742 | void *priv; |
26e59d80 | 4743 | int err; |
b50d292b | 4744 | |
26e59d80 MHY |
4745 | err = mlx5e_check_required_hca_cap(mdev); |
4746 | if (err) | |
b50d292b HHZ |
4747 | return NULL; |
4748 | ||
e80541ec | 4749 | #ifdef CONFIG_MLX5_ESWITCH |
a9f7705f | 4750 | if (MLX5_VPORT_MANAGER(mdev)) { |
07c9f1e5 | 4751 | rpriv = mlx5e_alloc_nic_rep_priv(mdev); |
1d447a39 | 4752 | if (!rpriv) { |
07c9f1e5 | 4753 | mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n"); |
1d447a39 SM |
4754 | return NULL; |
4755 | } | |
1d447a39 | 4756 | } |
e80541ec | 4757 | #endif |
127ea380 | 4758 | |
1d447a39 | 4759 | netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv); |
26e59d80 MHY |
4760 | if (!netdev) { |
4761 | mlx5_core_err(mdev, "mlx5e_create_netdev failed\n"); | |
07c9f1e5 | 4762 | goto err_free_rpriv; |
26e59d80 MHY |
4763 | } |
4764 | ||
4765 | priv = netdev_priv(netdev); | |
4766 | ||
4767 | err = mlx5e_attach(mdev, priv); | |
4768 | if (err) { | |
4769 | mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err); | |
4770 | goto err_destroy_netdev; | |
4771 | } | |
4772 | ||
4773 | err = register_netdev(netdev); | |
4774 | if (err) { | |
4775 | mlx5_core_err(mdev, "register_netdev failed, %d\n", err); | |
4776 | goto err_detach; | |
b50d292b | 4777 | } |
26e59d80 | 4778 | |
2a5e7a13 HN |
4779 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
4780 | mlx5e_dcbnl_init_app(priv); | |
4781 | #endif | |
26e59d80 MHY |
4782 | return priv; |
4783 | ||
4784 | err_detach: | |
4785 | mlx5e_detach(mdev, priv); | |
26e59d80 | 4786 | err_destroy_netdev: |
2c3b5bee | 4787 | mlx5e_destroy_netdev(priv); |
07c9f1e5 | 4788 | err_free_rpriv: |
1d447a39 | 4789 | kfree(rpriv); |
26e59d80 | 4790 | return NULL; |
b50d292b HHZ |
4791 | } |
4792 | ||
b50d292b HHZ |
4793 | static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv) |
4794 | { | |
4795 | struct mlx5e_priv *priv = vpriv; | |
1d447a39 | 4796 | void *ppriv = priv->ppriv; |
127ea380 | 4797 | |
2a5e7a13 HN |
4798 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
4799 | mlx5e_dcbnl_delete_app(priv); | |
4800 | #endif | |
5e1e93c7 | 4801 | unregister_netdev(priv->netdev); |
26e59d80 | 4802 | mlx5e_detach(mdev, vpriv); |
2c3b5bee | 4803 | mlx5e_destroy_netdev(priv); |
1d447a39 | 4804 | kfree(ppriv); |
b50d292b HHZ |
4805 | } |
4806 | ||
f62b8bb8 AV |
4807 | static void *mlx5e_get_netdev(void *vpriv) |
4808 | { | |
4809 | struct mlx5e_priv *priv = vpriv; | |
4810 | ||
4811 | return priv->netdev; | |
4812 | } | |
4813 | ||
4814 | static struct mlx5_interface mlx5e_interface = { | |
b50d292b HHZ |
4815 | .add = mlx5e_add, |
4816 | .remove = mlx5e_remove, | |
26e59d80 MHY |
4817 | .attach = mlx5e_attach, |
4818 | .detach = mlx5e_detach, | |
f62b8bb8 AV |
4819 | .event = mlx5e_async_event, |
4820 | .protocol = MLX5_INTERFACE_PROTOCOL_ETH, | |
4821 | .get_dev = mlx5e_get_netdev, | |
4822 | }; | |
4823 | ||
4824 | void mlx5e_init(void) | |
4825 | { | |
2ac9cfe7 | 4826 | mlx5e_ipsec_build_inverse_table(); |
665bc539 | 4827 | mlx5e_build_ptys2ethtool_map(); |
f62b8bb8 AV |
4828 | mlx5_register_interface(&mlx5e_interface); |
4829 | } | |
4830 | ||
4831 | void mlx5e_cleanup(void) | |
4832 | { | |
4833 | mlx5_unregister_interface(&mlx5e_interface); | |
4834 | } |