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net/mlx5e: IPoIB, RSS flow steering tables
[thirdparty/kernel/stable.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
f62b8bb8 38#include "en.h"
e8f887ac 39#include "en_tc.h"
66e49ded 40#include "eswitch.h"
b3f63c3d 41#include "vxlan.h"
f62b8bb8
AV		 42
43struct mlx5e_rq_param {
cb3c7fd4
GR		 44 u32 rqc[MLX5_ST_SZ_DW(rqc)];
45 struct mlx5_wq_param wq;
f62b8bb8
AV		 46};
47
48struct mlx5e_sq_param {
49 u32 sqc[MLX5_ST_SZ_DW(sqc)];
50 struct mlx5_wq_param wq;
51};
52
53struct mlx5e_cq_param {
54 u32 cqc[MLX5_ST_SZ_DW(cqc)];
55 struct mlx5_wq_param wq;
56 u16 eq_ix;
9908aa29 57 u8 cq_period_mode;
f62b8bb8
AV		 58};
59
60struct mlx5e_channel_param {
61 struct mlx5e_rq_param rq;
62 struct mlx5e_sq_param sq;
b5503b99 63 struct mlx5e_sq_param xdp_sq;
d3c9bc27 64 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 65 struct mlx5e_cq_param rx_cq;
66 struct mlx5e_cq_param tx_cq;
d3c9bc27 67 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 68};
69
2fc4bfb7
SM		 70static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
71{
72 return MLX5_CAP_GEN(mdev, striding_rq) &&
73 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
74 MLX5_CAP_ETH(mdev, reg_umr_sq);
75}
76
6a9764ef
SM		 77void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
78 struct mlx5e_params *params, u8 rq_type)
2fc4bfb7 79{
6a9764ef
SM		 80 params->rq_wq_type = rq_type;
81 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
82 switch (params->rq_wq_type) {
2fc4bfb7 83 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 84 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 85 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
86 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
6a9764ef
SM		 87 params->mpwqe_log_stride_sz =
88 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
89 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
90 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
91 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
92 params->mpwqe_log_stride_sz;
2fc4bfb7
SM		 93 break;
94 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 95 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 96 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
97 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
4078e637
TT		 98
99 /* Extra room needed for build_skb */
6a9764ef 100 params->lro_wqe_sz -= MLX5_RX_HEADROOM +
4078e637 101 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2fc4bfb7 102 }
2fc4bfb7 103
6a9764ef
SM		 104 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
105 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
106 BIT(params->log_rq_size),
107 BIT(params->mpwqe_log_stride_sz),
108 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 109}
110
6a9764ef 111static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
2fc4bfb7 112{
6a9764ef
SM		 113 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
114 !params->xdp_prog ?
2fc4bfb7
SM		 115 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
116 MLX5_WQ_TYPE_LINKED_LIST;
6a9764ef 117 mlx5e_set_rq_type_params(mdev, params, rq_type);
2fc4bfb7
SM		 118}
119
f62b8bb8
AV		 120static void mlx5e_update_carrier(struct mlx5e_priv *priv)
121{
122 struct mlx5_core_dev *mdev = priv->mdev;
123 u8 port_state;
124
125 port_state = mlx5_query_vport_state(mdev,
e7546514 126 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8 127
87424ad5
SD		 128 if (port_state == VPORT_STATE_UP) {
129 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 130 netif_carrier_on(priv->netdev);
87424ad5
SD		 131 } else {
132 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 133 netif_carrier_off(priv->netdev);
87424ad5 134 }
f62b8bb8
AV		 135}
136
137static void mlx5e_update_carrier_work(struct work_struct *work)
138{
139 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
140 update_carrier_work);
141
142 mutex_lock(&priv->state_lock);
143 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
144 mlx5e_update_carrier(priv);
145 mutex_unlock(&priv->state_lock);
146}
147
3947ca18
DJ		 148static void mlx5e_tx_timeout_work(struct work_struct *work)
149{
150 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
151 tx_timeout_work);
152 int err;
153
154 rtnl_lock();
155 mutex_lock(&priv->state_lock);
156 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
157 goto unlock;
158 mlx5e_close_locked(priv->netdev);
159 err = mlx5e_open_locked(priv->netdev);
160 if (err)
161 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
162 err);
163unlock:
164 mutex_unlock(&priv->state_lock);
165 rtnl_unlock();
166}
167
9218b44d 168static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 169{
9218b44d 170 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 171 struct mlx5e_rq_stats *rq_stats;
172 struct mlx5e_sq_stats *sq_stats;
9218b44d 173 u64 tx_offload_none = 0;
f62b8bb8
AV		 174 int i, j;
175
9218b44d 176 memset(s, 0, sizeof(*s));
ff9c852f
SM		 177 for (i = 0; i < priv->channels.num; i++) {
178 struct mlx5e_channel *c = priv->channels.c[i];
179
180 rq_stats = &c->rq.stats;
f62b8bb8 181
faf4478b
GP		 182 s->rx_packets += rq_stats->packets;
183 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 184 s->rx_lro_packets += rq_stats->lro_packets;
185 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 186 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 187 s->rx_csum_complete += rq_stats->csum_complete;
188 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 189 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 190 s->rx_xdp_tx += rq_stats->xdp_tx;
191 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 192 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 193 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 194 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 195 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
196 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
4415a031
TT		 197 s->rx_cache_reuse += rq_stats->cache_reuse;
198 s->rx_cache_full += rq_stats->cache_full;
199 s->rx_cache_empty += rq_stats->cache_empty;
200 s->rx_cache_busy += rq_stats->cache_busy;
f62b8bb8 201
6a9764ef 202 for (j = 0; j < priv->channels.params.num_tc; j++) {
ff9c852f 203 sq_stats = &c->sq[j].stats;
f62b8bb8 204
faf4478b
GP		 205 s->tx_packets += sq_stats->packets;
206 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 207 s->tx_tso_packets += sq_stats->tso_packets;
208 s->tx_tso_bytes += sq_stats->tso_bytes;
209 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
210 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 211 s->tx_queue_stopped += sq_stats->stopped;
212 s->tx_queue_wake += sq_stats->wake;
213 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 214 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1
GP		 215 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
216 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 217 }
218 }
219
9218b44d 220 /* Update calculated offload counters */
bfe6d8d1
GP		 221 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
222 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 223
bfe6d8d1 224 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 225 priv->stats.pport.phy_counters,
226 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 227}
228
229static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
230{
231 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
232 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 233 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 234 struct mlx5_core_dev *mdev = priv->mdev;
235
f62b8bb8
AV		 236 MLX5_SET(query_vport_counter_in, in, opcode,
237 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
238 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
239 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
240
241 memset(out, 0, outlen);
9218b44d
GP		 242 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
243}
244
245static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
246{
247 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
248 struct mlx5_core_dev *mdev = priv->mdev;
249 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 250 int prio;
9218b44d
GP		 251 void *out;
252 u32 *in;
253
254 in = mlx5_vzalloc(sz);
255 if (!in)
f62b8bb8
AV		 256 goto free_out;
257
9218b44d 258 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 259
9218b44d
GP		 260 out = pstats->IEEE_802_3_counters;
261 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
262 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 263
9218b44d
GP		 264 out = pstats->RFC_2863_counters;
265 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
266 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
267
268 out = pstats->RFC_2819_counters;
269 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
270 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 271
121fcdc8
GP		 272 out = pstats->phy_counters;
273 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
274 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
275
5db0a4f6
GP		 276 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
277 out = pstats->phy_statistical_counters;
278 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
279 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
280 }
281
cf678570
GP		 282 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
283 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
284 out = pstats->per_prio_counters[prio];
285 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
286 mlx5_core_access_reg(mdev, in, sz, out, sz,
287 MLX5_REG_PPCNT, 0, 0);
288 }
289
f62b8bb8 290free_out:
9218b44d
GP		 291 kvfree(in);
292}
293
294static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
295{
296 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
297
298 if (!priv->q_counter)
299 return;
300
301 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
302 &qcnt->rx_out_of_buffer);
303}
304
0f7f3481
GP		 305static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
306{
307 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
308 struct mlx5_core_dev *mdev = priv->mdev;
309 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
310 void *out;
311 u32 *in;
312
313 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
314 return;
315
316 in = mlx5_vzalloc(sz);
317 if (!in)
318 return;
319
320 out = pcie_stats->pcie_perf_counters;
321 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
322 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
323
324 kvfree(in);
325}
326
9218b44d
GP		 327void mlx5e_update_stats(struct mlx5e_priv *priv)
328{
3dd69e3d 329 mlx5e_update_pcie_counters(priv);
9218b44d 330 mlx5e_update_pport_counters(priv);
3dd69e3d
SM		 331 mlx5e_update_vport_counters(priv);
332 mlx5e_update_q_counter(priv);
121fcdc8 333 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 334}
335
cb67b832 336void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 337{
338 struct delayed_work *dwork = to_delayed_work(work);
339 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
340 update_stats_work);
341 mutex_lock(&priv->state_lock);
342 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 343 priv->profile->update_stats(priv);
7bb29755
MF		 344 queue_delayed_work(priv->wq, dwork,
345 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 346 }
347 mutex_unlock(&priv->state_lock);
348}
349
daa21560
TT		 350static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
351 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 352{
daa21560 353 struct mlx5e_priv *priv = vpriv;
ee7f1220
EE		 354 struct ptp_clock_event ptp_event;
355 struct mlx5_eqe *eqe = NULL;
daa21560 356
e0f46eb9 357 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 358 return;
359
f62b8bb8
AV		 360 switch (event) {
361 case MLX5_DEV_EVENT_PORT_UP:
362 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 363 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 364 break;
ee7f1220
EE		 365 case MLX5_DEV_EVENT_PPS:
366 eqe = (struct mlx5_eqe *)param;
367 ptp_event.type = PTP_CLOCK_EXTTS;
368 ptp_event.index = eqe->data.pps.pin;
369 ptp_event.timestamp =
370 timecounter_cyc2time(&priv->tstamp.clock,
371 be64_to_cpu(eqe->data.pps.time_stamp));
372 mlx5e_pps_event_handler(vpriv, &ptp_event);
373 break;
f62b8bb8
AV		 374 default:
375 break;
376 }
377}
378
f62b8bb8
AV		 379static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
380{
e0f46eb9 381 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 382}
383
384static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
385{
e0f46eb9 386 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 387 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 388}
389
7e426671
TT		 390static inline int mlx5e_get_wqe_mtt_sz(void)
391{
392 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
393 * To avoid copying garbage after the mtt array, we allocate
394 * a little more.
395 */
396 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
397 MLX5_UMR_MTT_ALIGNMENT);
398}
399
31391048
SM		 400static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
401 struct mlx5e_icosq *sq,
402 struct mlx5e_umr_wqe *wqe,
403 u16 ix)
7e426671
TT		 404{
405 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
406 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
407 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 408 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 409 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
410 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
411
412 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
413 ds_cnt);
414 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
415 cseg->imm = rq->mkey_be;
416
417 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
31616255 418 ucseg->xlt_octowords =
7e426671
TT		 419 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
420 ucseg->bsf_octowords =
421 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
422 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
423
424 dseg->lkey = sq->mkey_be;
425 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
426}
427
428static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
429 struct mlx5e_channel *c)
430{
431 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
432 int mtt_sz = mlx5e_get_wqe_mtt_sz();
433 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
434 int i;
435
21c59685
SM		 436 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
437 GFP_KERNEL, cpu_to_node(c->cpu));
438 if (!rq->mpwqe.info)
7e426671
TT		 439 goto err_out;
440
441 /* We allocate more than mtt_sz as we will align the pointer */
21c59685 442 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
7e426671 443 cpu_to_node(c->cpu));
21c59685 444 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 445 goto err_free_wqe_info;
446
447 for (i = 0; i < wq_sz; i++) {
21c59685 448 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 449
21c59685 450 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 451 MLX5_UMR_ALIGN);
452 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
453 PCI_DMA_TODEVICE);
454 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
455 goto err_unmap_mtts;
456
457 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
458 }
459
460 return 0;
461
462err_unmap_mtts:
463 while (--i >= 0) {
21c59685 464 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 465
466 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
467 PCI_DMA_TODEVICE);
468 }
21c59685 469 kfree(rq->mpwqe.mtt_no_align);
7e426671 470err_free_wqe_info:
21c59685 471 kfree(rq->mpwqe.info);
7e426671
TT		 472
473err_out:
474 return -ENOMEM;
475}
476
477static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
478{
479 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
480 int mtt_sz = mlx5e_get_wqe_mtt_sz();
481 int i;
482
483 for (i = 0; i < wq_sz; i++) {
21c59685 484 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 485
486 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
487 PCI_DMA_TODEVICE);
488 }
21c59685
SM		 489 kfree(rq->mpwqe.mtt_no_align);
490 kfree(rq->mpwqe.info);
7e426671
TT		 491}
492
a43b25da 493static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
ec8b9981
TT		 494 u64 npages, u8 page_shift,
495 struct mlx5_core_mkey *umr_mkey)
3608ae77 496{
3608ae77
TT		 497 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
498 void *mkc;
499 u32 *in;
500 int err;
501
ec8b9981
TT		 502 if (!MLX5E_VALID_NUM_MTTS(npages))
503 return -EINVAL;
504
3608ae77
TT		 505 in = mlx5_vzalloc(inlen);
506 if (!in)
507 return -ENOMEM;
508
509 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
510
3608ae77
TT		 511 MLX5_SET(mkc, mkc, free, 1);
512 MLX5_SET(mkc, mkc, umr_en, 1);
513 MLX5_SET(mkc, mkc, lw, 1);
514 MLX5_SET(mkc, mkc, lr, 1);
515 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
516
517 MLX5_SET(mkc, mkc, qpn, 0xffffff);
518 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 519 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 520 MLX5_SET(mkc, mkc, translations_octword_size,
521 MLX5_MTT_OCTW(npages));
ec8b9981 522 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 523
ec8b9981 524 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 525
526 kvfree(in);
527 return err;
528}
529
a43b25da 530static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
ec8b9981 531{
6a9764ef 532 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
ec8b9981 533
a43b25da 534 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
ec8b9981
TT		 535}
536
3b77235b 537static int mlx5e_alloc_rq(struct mlx5e_channel *c,
6a9764ef
SM		 538 struct mlx5e_params *params,
539 struct mlx5e_rq_param *rqp,
3b77235b 540 struct mlx5e_rq *rq)
f62b8bb8 541{
a43b25da 542 struct mlx5_core_dev *mdev = c->mdev;
6a9764ef 543 void *rqc = rqp->rqc;
f62b8bb8 544 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 545 u32 byte_count;
1bfecfca
SM		 546 u32 frag_sz;
547 int npages;
f62b8bb8
AV		 548 int wq_sz;
549 int err;
550 int i;
551
6a9764ef 552 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
311c7c71 553
6a9764ef 554 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
f62b8bb8
AV		 555 &rq->wq_ctrl);
556 if (err)
557 return err;
558
559 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
560
561 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 562
6a9764ef 563 rq->wq_type = params->rq_wq_type;
7e426671
TT		 564 rq->pdev = c->pdev;
565 rq->netdev = c->netdev;
a43b25da 566 rq->tstamp = c->tstamp;
7e426671
TT		 567 rq->channel = c;
568 rq->ix = c->ix;
a43b25da 569 rq->mdev = mdev;
97bc402d 570
6a9764ef 571 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
97bc402d
DB		 572 if (IS_ERR(rq->xdp_prog)) {
573 err = PTR_ERR(rq->xdp_prog);
574 rq->xdp_prog = NULL;
575 goto err_rq_wq_destroy;
576 }
7e426671 577
d8bec2b2 578 if (rq->xdp_prog) {
b5503b99 579 rq->buff.map_dir = DMA_BIDIRECTIONAL;
d8bec2b2
MKL		 580 rq->rx_headroom = XDP_PACKET_HEADROOM;
581 } else {
582 rq->buff.map_dir = DMA_FROM_DEVICE;
583 rq->rx_headroom = MLX5_RX_HEADROOM;
584 }
b5503b99 585
6a9764ef 586 switch (rq->wq_type) {
461017cb 587 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
a43b25da 588 if (mlx5e_is_vf_vport_rep(c->priv)) {
f5f82476
OG		 589 err = -EINVAL;
590 goto err_rq_wq_destroy;
591 }
592
461017cb
TT		 593 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
594 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 595 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 596
6a9764ef
SM		 597 rq->mpwqe_stride_sz = BIT(params->mpwqe_log_stride_sz);
598 rq->mpwqe_num_strides = BIT(params->mpwqe_log_num_strides);
1bfecfca
SM		 599
600 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
601 byte_count = rq->buff.wqe_sz;
ec8b9981 602
a43b25da 603 err = mlx5e_create_rq_umr_mkey(mdev, rq);
7e426671
TT		 604 if (err)
605 goto err_rq_wq_destroy;
ec8b9981
TT		 606 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
607
608 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
609 if (err)
610 goto err_destroy_umr_mkey;
461017cb
TT		 611 break;
612 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca
SM		 613 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
614 GFP_KERNEL, cpu_to_node(c->cpu));
615 if (!rq->dma_info) {
461017cb
TT		 616 err = -ENOMEM;
617 goto err_rq_wq_destroy;
618 }
1bfecfca 619
a43b25da 620 if (mlx5e_is_vf_vport_rep(c->priv))
f5f82476
OG		 621 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
622 else
623 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
624
461017cb 625 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 626 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 627
6a9764ef
SM		 628 rq->buff.wqe_sz = params->lro_en ?
629 params->lro_wqe_sz :
a43b25da 630 MLX5E_SW2HW_MTU(c->netdev->mtu);
1bfecfca
SM		 631 byte_count = rq->buff.wqe_sz;
632
633 /* calc the required page order */
d8bec2b2 634 frag_sz = rq->rx_headroom +
1bfecfca
SM		 635 byte_count /* packet data */ +
636 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
637 frag_sz = SKB_DATA_ALIGN(frag_sz);
638
639 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
640 rq->buff.page_order = order_base_2(npages);
641
461017cb 642 byte_count |= MLX5_HW_START_PADDING;
7e426671 643 rq->mkey_be = c->mkey_be;
461017cb 644 }
f62b8bb8
AV		 645
646 for (i = 0; i < wq_sz; i++) {
647 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
648
461017cb 649 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 650 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 651 }
652
cb3c7fd4 653 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
6a9764ef 654 rq->am.mode = params->rx_cq_period_mode;
4415a031
TT		 655 rq->page_cache.head = 0;
656 rq->page_cache.tail = 0;
657
f62b8bb8
AV		 658 return 0;
659
ec8b9981
TT		 660err_destroy_umr_mkey:
661 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
662
f62b8bb8 663err_rq_wq_destroy:
97bc402d
DB		 664 if (rq->xdp_prog)
665 bpf_prog_put(rq->xdp_prog);
f62b8bb8
AV		 666 mlx5_wq_destroy(&rq->wq_ctrl);
667
668 return err;
669}
670
3b77235b 671static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 672{
4415a031
TT		 673 int i;
674
86994156
RS		 675 if (rq->xdp_prog)
676 bpf_prog_put(rq->xdp_prog);
677
461017cb
TT		 678 switch (rq->wq_type) {
679 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 680 mlx5e_rq_free_mpwqe_info(rq);
a43b25da 681 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
461017cb
TT		 682 break;
683 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca 684 kfree(rq->dma_info);
461017cb
TT		 685 }
686
4415a031
TT		 687 for (i = rq->page_cache.head; i != rq->page_cache.tail;
688 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
689 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
690
691 mlx5e_page_release(rq, dma_info, false);
692 }
f62b8bb8
AV		 693 mlx5_wq_destroy(&rq->wq_ctrl);
694}
695
6a9764ef
SM		 696static int mlx5e_create_rq(struct mlx5e_rq *rq,
697 struct mlx5e_rq_param *param)
f62b8bb8 698{
a43b25da 699 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 700
701 void *in;
702 void *rqc;
703 void *wq;
704 int inlen;
705 int err;
706
707 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
708 sizeof(u64) * rq->wq_ctrl.buf.npages;
709 in = mlx5_vzalloc(inlen);
710 if (!in)
711 return -ENOMEM;
712
713 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
714 wq = MLX5_ADDR_OF(rqc, rqc, wq);
715
716 memcpy(rqc, param->rqc, sizeof(param->rqc));
717
97de9f31 718 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 719 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
f62b8bb8 720 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 721 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 722 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
723
724 mlx5_fill_page_array(&rq->wq_ctrl.buf,
725 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
726
7db22ffb 727 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 728
729 kvfree(in);
730
731 return err;
732}
733
36350114
GP		 734static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
735 int next_state)
f62b8bb8
AV		 736{
737 struct mlx5e_channel *c = rq->channel;
a43b25da 738 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 739
740 void *in;
741 void *rqc;
742 int inlen;
743 int err;
744
745 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
746 in = mlx5_vzalloc(inlen);
747 if (!in)
748 return -ENOMEM;
749
750 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
751
752 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
753 MLX5_SET(rqc, rqc, state, next_state);
754
7db22ffb 755 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 756
757 kvfree(in);
758
759 return err;
760}
761
102722fc
GE		 762static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
763{
764 struct mlx5e_channel *c = rq->channel;
765 struct mlx5e_priv *priv = c->priv;
766 struct mlx5_core_dev *mdev = priv->mdev;
767
768 void *in;
769 void *rqc;
770 int inlen;
771 int err;
772
773 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
774 in = mlx5_vzalloc(inlen);
775 if (!in)
776 return -ENOMEM;
777
778 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
779
780 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
781 MLX5_SET64(modify_rq_in, in, modify_bitmask,
782 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
783 MLX5_SET(rqc, rqc, scatter_fcs, enable);
784 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
785
786 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
787
788 kvfree(in);
789
790 return err;
791}
792
36350114
GP		 793static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
794{
795 struct mlx5e_channel *c = rq->channel;
a43b25da 796 struct mlx5_core_dev *mdev = c->mdev;
36350114
GP		 797 void *in;
798 void *rqc;
799 int inlen;
800 int err;
801
802 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
803 in = mlx5_vzalloc(inlen);
804 if (!in)
805 return -ENOMEM;
806
807 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
808
809 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 810 MLX5_SET64(modify_rq_in, in, modify_bitmask,
811 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 812 MLX5_SET(rqc, rqc, vsd, vsd);
813 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
814
815 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
816
817 kvfree(in);
818
819 return err;
820}
821
3b77235b 822static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 823{
a43b25da 824 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
f62b8bb8
AV		 825}
826
827static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
828{
01c196a2 829 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8 830 struct mlx5e_channel *c = rq->channel;
a43b25da 831
f62b8bb8 832 struct mlx5_wq_ll *wq = &rq->wq;
6a9764ef 833 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
f62b8bb8 834
01c196a2 835 while (time_before(jiffies, exp_time)) {
6a9764ef 836 if (wq->cur_sz >= min_wqes)
f62b8bb8
AV		 837 return 0;
838
839 msleep(20);
840 }
841
a43b25da 842 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
6a9764ef 843 rq->rqn, wq->cur_sz, min_wqes);
f62b8bb8
AV		 844 return -ETIMEDOUT;
845}
846
f2fde18c
SM		 847static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
848{
849 struct mlx5_wq_ll *wq = &rq->wq;
850 struct mlx5e_rx_wqe *wqe;
851 __be16 wqe_ix_be;
852 u16 wqe_ix;
853
8484f9ed
SM		 854 /* UMR WQE (if in progress) is always at wq->head */
855 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
21c59685 856 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 857
f2fde18c
SM		 858 while (!mlx5_wq_ll_is_empty(wq)) {
859 wqe_ix_be = *wq->tail_next;
860 wqe_ix = be16_to_cpu(wqe_ix_be);
861 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
862 rq->dealloc_wqe(rq, wqe_ix);
863 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
864 &wqe->next.next_wqe_index);
865 }
866}
867
f62b8bb8 868static int mlx5e_open_rq(struct mlx5e_channel *c,
6a9764ef 869 struct mlx5e_params *params,
f62b8bb8
AV		 870 struct mlx5e_rq_param *param,
871 struct mlx5e_rq *rq)
872{
873 int err;
874
6a9764ef 875 err = mlx5e_alloc_rq(c, params, param, rq);
f62b8bb8
AV		 876 if (err)
877 return err;
878
3b77235b 879 err = mlx5e_create_rq(rq, param);
f62b8bb8 880 if (err)
3b77235b 881 goto err_free_rq;
f62b8bb8 882
36350114 883 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 884 if (err)
3b77235b 885 goto err_destroy_rq;
f62b8bb8 886
6a9764ef 887 if (params->rx_am_enabled)
cb3c7fd4
GR		 888 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
889
f62b8bb8
AV		 890 return 0;
891
f62b8bb8
AV		 892err_destroy_rq:
893 mlx5e_destroy_rq(rq);
3b77235b
SM		 894err_free_rq:
895 mlx5e_free_rq(rq);
f62b8bb8
AV		 896
897 return err;
898}
899
acc6c595
SM		 900static void mlx5e_activate_rq(struct mlx5e_rq *rq)
901{
902 struct mlx5e_icosq *sq = &rq->channel->icosq;
903 u16 pi = sq->pc & sq->wq.sz_m1;
904 struct mlx5e_tx_wqe *nopwqe;
905
906 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
907 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
908 sq->db.ico_wqe[pi].num_wqebbs = 1;
909 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
910 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
911}
912
913static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
f62b8bb8 914{
c0f1147d 915 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 916 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
acc6c595 917}
cb3c7fd4 918
acc6c595
SM		 919static void mlx5e_close_rq(struct mlx5e_rq *rq)
920{
921 cancel_work_sync(&rq->am.work);
f62b8bb8 922 mlx5e_destroy_rq(rq);
3b77235b
SM		 923 mlx5e_free_rx_descs(rq);
924 mlx5e_free_rq(rq);
f62b8bb8
AV		 925}
926
31391048 927static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
b5503b99 928{
31391048 929 kfree(sq->db.di);
b5503b99
SM		 930}
931
31391048 932static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
b5503b99
SM		 933{
934 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
935
31391048 936 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
b5503b99 937 GFP_KERNEL, numa);
31391048
SM		 938 if (!sq->db.di) {
939 mlx5e_free_xdpsq_db(sq);
b5503b99
SM		 940 return -ENOMEM;
941 }
942
943 return 0;
944}
945
31391048 946static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
6a9764ef 947 struct mlx5e_params *params,
31391048
SM		 948 struct mlx5e_sq_param *param,
949 struct mlx5e_xdpsq *sq)
950{
951 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 952 struct mlx5_core_dev *mdev = c->mdev;
31391048
SM		 953 int err;
954
955 sq->pdev = c->pdev;
956 sq->mkey_be = c->mkey_be;
957 sq->channel = c;
958 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 959 sq->min_inline_mode = params->tx_min_inline_mode;
31391048
SM		 960
961 param->wq.db_numa_node = cpu_to_node(c->cpu);
962 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
963 if (err)
964 return err;
965 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
966
967 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
968 if (err)
969 goto err_sq_wq_destroy;
970
971 return 0;
972
973err_sq_wq_destroy:
974 mlx5_wq_destroy(&sq->wq_ctrl);
975
976 return err;
977}
978
979static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
980{
981 mlx5e_free_xdpsq_db(sq);
982 mlx5_wq_destroy(&sq->wq_ctrl);
983}
984
985static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
f62b8bb8 986{
f10b7cc7 987 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 988}
989
31391048 990static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
f10b7cc7
SM		 991{
992 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
993
994 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
995 GFP_KERNEL, numa);
996 if (!sq->db.ico_wqe)
997 return -ENOMEM;
998
999 return 0;
1000}
1001
31391048 1002static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
31391048
SM		 1003 struct mlx5e_sq_param *param,
1004 struct mlx5e_icosq *sq)
f10b7cc7 1005{
31391048 1006 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1007 struct mlx5_core_dev *mdev = c->mdev;
31391048 1008 int err;
f10b7cc7 1009
31391048
SM		 1010 sq->pdev = c->pdev;
1011 sq->mkey_be = c->mkey_be;
1012 sq->channel = c;
1013 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f62b8bb8 1014
31391048
SM		 1015 param->wq.db_numa_node = cpu_to_node(c->cpu);
1016 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1017 if (err)
1018 return err;
1019 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1020
31391048
SM		 1021 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1022 if (err)
1023 goto err_sq_wq_destroy;
1024
1025 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
f62b8bb8
AV		 1026
1027 return 0;
31391048
SM		 1028
1029err_sq_wq_destroy:
1030 mlx5_wq_destroy(&sq->wq_ctrl);
1031
1032 return err;
f62b8bb8
AV		 1033}
1034
31391048 1035static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
f10b7cc7 1036{
31391048
SM		 1037 mlx5e_free_icosq_db(sq);
1038 mlx5_wq_destroy(&sq->wq_ctrl);
f10b7cc7
SM		 1039}
1040
31391048 1041static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
f10b7cc7 1042{
31391048
SM		 1043 kfree(sq->db.wqe_info);
1044 kfree(sq->db.dma_fifo);
1045 kfree(sq->db.skb);
f10b7cc7
SM		 1046}
1047
31391048 1048static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
b5503b99 1049{
31391048
SM		 1050 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1051 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1052
1053 sq->db.skb = kzalloc_node(wq_sz * sizeof(*sq->db.skb),
1054 GFP_KERNEL, numa);
1055 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1056 GFP_KERNEL, numa);
1057 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1058 GFP_KERNEL, numa);
1059 if (!sq->db.skb || !sq->db.dma_fifo || !sq->db.wqe_info) {
1060 mlx5e_free_txqsq_db(sq);
1061 return -ENOMEM;
b5503b99 1062 }
31391048
SM		 1063
1064 sq->dma_fifo_mask = df_sz - 1;
1065
1066 return 0;
b5503b99
SM		 1067}
1068
31391048 1069static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
acc6c595 1070 int txq_ix,
6a9764ef 1071 struct mlx5e_params *params,
31391048
SM		 1072 struct mlx5e_sq_param *param,
1073 struct mlx5e_txqsq *sq)
f62b8bb8 1074{
31391048 1075 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1076 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 1077 int err;
1078
f10b7cc7 1079 sq->pdev = c->pdev;
a43b25da 1080 sq->tstamp = c->tstamp;
f10b7cc7
SM		 1081 sq->mkey_be = c->mkey_be;
1082 sq->channel = c;
acc6c595 1083 sq->txq_ix = txq_ix;
aff26157 1084 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef
SM		 1085 sq->max_inline = params->tx_max_inline;
1086 sq->min_inline_mode = params->tx_min_inline_mode;
f10b7cc7 1087
311c7c71 1088 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048 1089 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
f62b8bb8 1090 if (err)
aff26157 1091 return err;
31391048 1092 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1093
31391048 1094 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
7ec0bb22 1095 if (err)
f62b8bb8
AV		 1096 goto err_sq_wq_destroy;
1097
31391048 1098 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
f62b8bb8
AV		 1099
1100 return 0;
1101
1102err_sq_wq_destroy:
1103 mlx5_wq_destroy(&sq->wq_ctrl);
1104
f62b8bb8
AV		 1105 return err;
1106}
1107
31391048 1108static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1109{
31391048 1110 mlx5e_free_txqsq_db(sq);
f62b8bb8 1111 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1112}
1113
33ad9711
SM		 1114struct mlx5e_create_sq_param {
1115 struct mlx5_wq_ctrl *wq_ctrl;
1116 u32 cqn;
1117 u32 tisn;
1118 u8 tis_lst_sz;
1119 u8 min_inline_mode;
1120};
1121
a43b25da 1122static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
33ad9711
SM		 1123 struct mlx5e_sq_param *param,
1124 struct mlx5e_create_sq_param *csp,
1125 u32 *sqn)
f62b8bb8 1126{
f62b8bb8
AV		 1127 void *in;
1128 void *sqc;
1129 void *wq;
1130 int inlen;
1131 int err;
1132
1133 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
33ad9711 1134 sizeof(u64) * csp->wq_ctrl->buf.npages;
f62b8bb8
AV		 1135 in = mlx5_vzalloc(inlen);
1136 if (!in)
1137 return -ENOMEM;
1138
1139 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1140 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1141
1142 memcpy(sqc, param->sqc, sizeof(param->sqc));
33ad9711
SM		 1143 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1144 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1145 MLX5_SET(sqc, sqc, cqn, csp->cqn);
a6f402e4
SM		 1146
1147 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
33ad9711 1148 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
a6f402e4 1149
33ad9711 1150 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f62b8bb8
AV		 1151
1152 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
a43b25da 1153 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
33ad9711 1154 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
68cdf5d6 1155 MLX5_ADAPTER_PAGE_SHIFT);
33ad9711 1156 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
f62b8bb8 1157
33ad9711 1158 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 1159
33ad9711 1160 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
f62b8bb8
AV		 1161
1162 kvfree(in);
1163
1164 return err;
1165}
1166
33ad9711
SM		 1167struct mlx5e_modify_sq_param {
1168 int curr_state;
1169 int next_state;
1170 bool rl_update;
1171 int rl_index;
1172};
1173
a43b25da 1174static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
33ad9711 1175 struct mlx5e_modify_sq_param *p)
f62b8bb8 1176{
f62b8bb8
AV		 1177 void *in;
1178 void *sqc;
1179 int inlen;
1180 int err;
1181
1182 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1183 in = mlx5_vzalloc(inlen);
1184 if (!in)
1185 return -ENOMEM;
1186
1187 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1188
33ad9711
SM		 1189 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1190 MLX5_SET(sqc, sqc, state, p->next_state);
1191 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
507f0c81 1192 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
33ad9711 1193 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
507f0c81 1194 }
f62b8bb8 1195
33ad9711 1196 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
f62b8bb8
AV		 1197
1198 kvfree(in);
1199
1200 return err;
1201}
1202
a43b25da 1203static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
33ad9711 1204{
a43b25da 1205 mlx5_core_destroy_sq(mdev, sqn);
f62b8bb8
AV		 1206}
1207
a43b25da 1208static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
31391048
SM		 1209 struct mlx5e_sq_param *param,
1210 struct mlx5e_create_sq_param *csp,
1211 u32 *sqn)
f62b8bb8 1212{
33ad9711 1213 struct mlx5e_modify_sq_param msp = {0};
31391048
SM		 1214 int err;
1215
a43b25da 1216 err = mlx5e_create_sq(mdev, param, csp, sqn);
31391048
SM		 1217 if (err)
1218 return err;
1219
1220 msp.curr_state = MLX5_SQC_STATE_RST;
1221 msp.next_state = MLX5_SQC_STATE_RDY;
a43b25da 1222 err = mlx5e_modify_sq(mdev, *sqn, &msp);
31391048 1223 if (err)
a43b25da 1224 mlx5e_destroy_sq(mdev, *sqn);
31391048
SM		 1225
1226 return err;
1227}
1228
7f859ecf
SM		 1229static int mlx5e_set_sq_maxrate(struct net_device *dev,
1230 struct mlx5e_txqsq *sq, u32 rate);
1231
31391048 1232static int mlx5e_open_txqsq(struct mlx5e_channel *c,
a43b25da 1233 u32 tisn,
acc6c595 1234 int txq_ix,
6a9764ef 1235 struct mlx5e_params *params,
31391048
SM		 1236 struct mlx5e_sq_param *param,
1237 struct mlx5e_txqsq *sq)
1238{
1239 struct mlx5e_create_sq_param csp = {};
7f859ecf 1240 u32 tx_rate;
f62b8bb8
AV		 1241 int err;
1242
6a9764ef 1243 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
f62b8bb8
AV		 1244 if (err)
1245 return err;
1246
a43b25da 1247 csp.tisn = tisn;
31391048 1248 csp.tis_lst_sz = 1;
33ad9711
SM		 1249 csp.cqn = sq->cq.mcq.cqn;
1250 csp.wq_ctrl = &sq->wq_ctrl;
1251 csp.min_inline_mode = sq->min_inline_mode;
a43b25da 1252 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
f62b8bb8 1253 if (err)
31391048 1254 goto err_free_txqsq;
f62b8bb8 1255
a43b25da 1256 tx_rate = c->priv->tx_rates[sq->txq_ix];
7f859ecf 1257 if (tx_rate)
a43b25da 1258 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
7f859ecf 1259
f62b8bb8
AV		 1260 return 0;
1261
31391048 1262err_free_txqsq:
3b77235b 1263 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
31391048 1264 mlx5e_free_txqsq(sq);
f62b8bb8
AV		 1265
1266 return err;
1267}
1268
acc6c595
SM		 1269static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1270{
a43b25da 1271 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
acc6c595
SM		 1272 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1273 netdev_tx_reset_queue(sq->txq);
1274 netif_tx_start_queue(sq->txq);
1275}
1276
f62b8bb8
AV		 1277static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1278{
1279 __netif_tx_lock_bh(txq);
1280 netif_tx_stop_queue(txq);
1281 __netif_tx_unlock_bh(txq);
1282}
1283
acc6c595 1284static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1285{
33ad9711 1286 struct mlx5e_channel *c = sq->channel;
33ad9711 1287
c0f1147d 1288 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6 1289 /* prevent netif_tx_wake_queue */
33ad9711 1290 napi_synchronize(&c->napi);
29429f33 1291
31391048 1292 netif_tx_disable_queue(sq->txq);
f62b8bb8 1293
31391048
SM		 1294 /* last doorbell out, godspeed .. */
1295 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1296 struct mlx5e_tx_wqe *nop;
864b2d71 1297
31391048
SM		 1298 sq->db.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1299 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1300 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
29429f33 1301 }
acc6c595
SM		 1302}
1303
1304static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1305{
1306 struct mlx5e_channel *c = sq->channel;
a43b25da 1307 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1308
a43b25da 1309 mlx5e_destroy_sq(mdev, sq->sqn);
33ad9711
SM		 1310 if (sq->rate_limit)
1311 mlx5_rl_remove_rate(mdev, sq->rate_limit);
31391048
SM		 1312 mlx5e_free_txqsq_descs(sq);
1313 mlx5e_free_txqsq(sq);
1314}
1315
1316static int mlx5e_open_icosq(struct mlx5e_channel *c,
6a9764ef 1317 struct mlx5e_params *params,
31391048
SM		 1318 struct mlx5e_sq_param *param,
1319 struct mlx5e_icosq *sq)
1320{
1321 struct mlx5e_create_sq_param csp = {};
1322 int err;
1323
6a9764ef 1324 err = mlx5e_alloc_icosq(c, param, sq);
31391048
SM		 1325 if (err)
1326 return err;
1327
1328 csp.cqn = sq->cq.mcq.cqn;
1329 csp.wq_ctrl = &sq->wq_ctrl;
6a9764ef 1330 csp.min_inline_mode = params->tx_min_inline_mode;
31391048 1331 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1332 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1333 if (err)
1334 goto err_free_icosq;
1335
1336 return 0;
1337
1338err_free_icosq:
1339 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1340 mlx5e_free_icosq(sq);
1341
1342 return err;
1343}
1344
1345static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1346{
1347 struct mlx5e_channel *c = sq->channel;
1348
1349 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1350 napi_synchronize(&c->napi);
1351
a43b25da 1352 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1353 mlx5e_free_icosq(sq);
1354}
1355
1356static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
6a9764ef 1357 struct mlx5e_params *params,
31391048
SM		 1358 struct mlx5e_sq_param *param,
1359 struct mlx5e_xdpsq *sq)
1360{
1361 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1362 struct mlx5e_create_sq_param csp = {};
31391048
SM		 1363 unsigned int inline_hdr_sz = 0;
1364 int err;
1365 int i;
1366
6a9764ef 1367 err = mlx5e_alloc_xdpsq(c, params, param, sq);
31391048
SM		 1368 if (err)
1369 return err;
1370
1371 csp.tis_lst_sz = 1;
a43b25da 1372 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
31391048
SM		 1373 csp.cqn = sq->cq.mcq.cqn;
1374 csp.wq_ctrl = &sq->wq_ctrl;
1375 csp.min_inline_mode = sq->min_inline_mode;
1376 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1377 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1378 if (err)
1379 goto err_free_xdpsq;
1380
1381 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1382 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1383 ds_cnt++;
1384 }
1385
1386 /* Pre initialize fixed WQE fields */
1387 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1388 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1389 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1390 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1391 struct mlx5_wqe_data_seg *dseg;
1392
1393 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1394 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1395
1396 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1397 dseg->lkey = sq->mkey_be;
1398 }
1399
1400 return 0;
1401
1402err_free_xdpsq:
1403 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1404 mlx5e_free_xdpsq(sq);
1405
1406 return err;
1407}
1408
1409static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1410{
1411 struct mlx5e_channel *c = sq->channel;
1412
1413 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1414 napi_synchronize(&c->napi);
1415
a43b25da 1416 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1417 mlx5e_free_xdpsq_descs(sq);
1418 mlx5e_free_xdpsq(sq);
f62b8bb8
AV		 1419}
1420
95b6c6a5
EBE		 1421static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1422 struct mlx5e_cq_param *param,
1423 struct mlx5e_cq *cq)
f62b8bb8 1424{
f62b8bb8
AV		 1425 struct mlx5_core_cq *mcq = &cq->mcq;
1426 int eqn_not_used;
0b6e26ce 1427 unsigned int irqn;
f62b8bb8
AV		 1428 int err;
1429 u32 i;
1430
f62b8bb8
AV		 1431 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1432 &cq->wq_ctrl);
1433 if (err)
1434 return err;
1435
1436 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1437
f62b8bb8
AV		 1438 mcq->cqe_sz = 64;
1439 mcq->set_ci_db = cq->wq_ctrl.db.db;
1440 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1441 *mcq->set_ci_db = 0;
1442 *mcq->arm_db = 0;
1443 mcq->vector = param->eq_ix;
1444 mcq->comp = mlx5e_completion_event;
1445 mcq->event = mlx5e_cq_error_event;
1446 mcq->irqn = irqn;
f62b8bb8
AV		 1447
1448 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1449 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1450
1451 cqe->op_own = 0xf1;
1452 }
1453
a43b25da 1454 cq->mdev = mdev;
f62b8bb8
AV		 1455
1456 return 0;
1457}
1458
95b6c6a5
EBE		 1459static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1460 struct mlx5e_cq_param *param,
1461 struct mlx5e_cq *cq)
1462{
1463 struct mlx5_core_dev *mdev = c->priv->mdev;
1464 int err;
1465
1466 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1467 param->wq.db_numa_node = cpu_to_node(c->cpu);
1468 param->eq_ix = c->ix;
1469
1470 err = mlx5e_alloc_cq_common(mdev, param, cq);
1471
1472 cq->napi = &c->napi;
1473 cq->channel = c;
1474
1475 return err;
1476}
1477
3b77235b 1478static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1479{
1c1b5228 1480 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1481}
1482
3b77235b 1483static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1484{
a43b25da 1485 struct mlx5_core_dev *mdev = cq->mdev;
f62b8bb8
AV		 1486 struct mlx5_core_cq *mcq = &cq->mcq;
1487
1488 void *in;
1489 void *cqc;
1490 int inlen;
0b6e26ce 1491 unsigned int irqn_not_used;
f62b8bb8
AV		 1492 int eqn;
1493 int err;
1494
1495 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1496 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
f62b8bb8
AV		 1497 in = mlx5_vzalloc(inlen);
1498 if (!in)
1499 return -ENOMEM;
1500
1501 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1502
1503 memcpy(cqc, param->cqc, sizeof(param->cqc));
1504
1c1b5228
TT		 1505 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1506 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1507
1508 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1509
9908aa29 1510 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1511 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1512 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1c1b5228 1513 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1514 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1515 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1516
1517 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1518
1519 kvfree(in);
1520
1521 if (err)
1522 return err;
1523
1524 mlx5e_cq_arm(cq);
1525
1526 return 0;
1527}
1528
3b77235b 1529static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1530{
a43b25da 1531 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
f62b8bb8
AV		 1532}
1533
1534static int mlx5e_open_cq(struct mlx5e_channel *c,
6a9764ef 1535 struct mlx5e_cq_moder moder,
f62b8bb8 1536 struct mlx5e_cq_param *param,
6a9764ef 1537 struct mlx5e_cq *cq)
f62b8bb8 1538{
a43b25da 1539 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1540 int err;
f62b8bb8 1541
3b77235b 1542 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1543 if (err)
1544 return err;
1545
3b77235b 1546 err = mlx5e_create_cq(cq, param);
f62b8bb8 1547 if (err)
3b77235b 1548 goto err_free_cq;
f62b8bb8 1549
7524a5d8 1550 if (MLX5_CAP_GEN(mdev, cq_moderation))
6a9764ef 1551 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
f62b8bb8
AV		 1552 return 0;
1553
3b77235b
SM		 1554err_free_cq:
1555 mlx5e_free_cq(cq);
f62b8bb8
AV		 1556
1557 return err;
1558}
1559
1560static void mlx5e_close_cq(struct mlx5e_cq *cq)
1561{
f62b8bb8 1562 mlx5e_destroy_cq(cq);
3b77235b 1563 mlx5e_free_cq(cq);
f62b8bb8
AV		 1564}
1565
1566static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1567{
1568 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1569}
1570
1571static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
6a9764ef 1572 struct mlx5e_params *params,
f62b8bb8
AV		 1573 struct mlx5e_channel_param *cparam)
1574{
f62b8bb8
AV		 1575 int err;
1576 int tc;
1577
1578 for (tc = 0; tc < c->num_tc; tc++) {
6a9764ef
SM		 1579 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1580 &cparam->tx_cq, &c->sq[tc].cq);
f62b8bb8
AV		 1581 if (err)
1582 goto err_close_tx_cqs;
f62b8bb8
AV		 1583 }
1584
1585 return 0;
1586
1587err_close_tx_cqs:
1588 for (tc--; tc >= 0; tc--)
1589 mlx5e_close_cq(&c->sq[tc].cq);
1590
1591 return err;
1592}
1593
1594static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1595{
1596 int tc;
1597
1598 for (tc = 0; tc < c->num_tc; tc++)
1599 mlx5e_close_cq(&c->sq[tc].cq);
1600}
1601
1602static int mlx5e_open_sqs(struct mlx5e_channel *c,
6a9764ef 1603 struct mlx5e_params *params,
f62b8bb8
AV		 1604 struct mlx5e_channel_param *cparam)
1605{
1606 int err;
1607 int tc;
1608
6a9764ef
SM		 1609 for (tc = 0; tc < params->num_tc; tc++) {
1610 int txq_ix = c->ix + tc * params->num_channels;
acc6c595 1611
a43b25da
SM		 1612 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1613 params, &cparam->sq, &c->sq[tc]);
f62b8bb8
AV		 1614 if (err)
1615 goto err_close_sqs;
1616 }
1617
1618 return 0;
1619
1620err_close_sqs:
1621 for (tc--; tc >= 0; tc--)
31391048 1622 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1623
1624 return err;
1625}
1626
1627static void mlx5e_close_sqs(struct mlx5e_channel *c)
1628{
1629 int tc;
1630
1631 for (tc = 0; tc < c->num_tc; tc++)
31391048 1632 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1633}
1634
507f0c81 1635static int mlx5e_set_sq_maxrate(struct net_device *dev,
31391048 1636 struct mlx5e_txqsq *sq, u32 rate)
507f0c81
YP		 1637{
1638 struct mlx5e_priv *priv = netdev_priv(dev);
1639 struct mlx5_core_dev *mdev = priv->mdev;
33ad9711 1640 struct mlx5e_modify_sq_param msp = {0};
507f0c81
YP		 1641 u16 rl_index = 0;
1642 int err;
1643
1644 if (rate == sq->rate_limit)
1645 /* nothing to do */
1646 return 0;
1647
1648 if (sq->rate_limit)
1649 /* remove current rl index to free space to next ones */
1650 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1651
1652 sq->rate_limit = 0;
1653
1654 if (rate) {
1655 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1656 if (err) {
1657 netdev_err(dev, "Failed configuring rate %u: %d\n",
1658 rate, err);
1659 return err;
1660 }
1661 }
1662
33ad9711
SM		 1663 msp.curr_state = MLX5_SQC_STATE_RDY;
1664 msp.next_state = MLX5_SQC_STATE_RDY;
1665 msp.rl_index = rl_index;
1666 msp.rl_update = true;
a43b25da 1667 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
507f0c81
YP		 1668 if (err) {
1669 netdev_err(dev, "Failed configuring rate %u: %d\n",
1670 rate, err);
1671 /* remove the rate from the table */
1672 if (rate)
1673 mlx5_rl_remove_rate(mdev, rate);
1674 return err;
1675 }
1676
1677 sq->rate_limit = rate;
1678 return 0;
1679}
1680
1681static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1682{
1683 struct mlx5e_priv *priv = netdev_priv(dev);
1684 struct mlx5_core_dev *mdev = priv->mdev;
acc6c595 1685 struct mlx5e_txqsq *sq = priv->txq2sq[index];
507f0c81
YP		 1686 int err = 0;
1687
1688 if (!mlx5_rl_is_supported(mdev)) {
1689 netdev_err(dev, "Rate limiting is not supported on this device\n");
1690 return -EINVAL;
1691 }
1692
1693 /* rate is given in Mb/sec, HW config is in Kb/sec */
1694 rate = rate << 10;
1695
1696 /* Check whether rate in valid range, 0 is always valid */
1697 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1698 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1699 return -ERANGE;
1700 }
1701
1702 mutex_lock(&priv->state_lock);
1703 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1704 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1705 if (!err)
1706 priv->tx_rates[index] = rate;
1707 mutex_unlock(&priv->state_lock);
1708
1709 return err;
1710}
1711
f62b8bb8 1712static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
6a9764ef 1713 struct mlx5e_params *params,
f62b8bb8
AV		 1714 struct mlx5e_channel_param *cparam,
1715 struct mlx5e_channel **cp)
1716{
6a9764ef 1717 struct mlx5e_cq_moder icocq_moder = {0, 0};
f62b8bb8
AV		 1718 struct net_device *netdev = priv->netdev;
1719 int cpu = mlx5e_get_cpu(priv, ix);
1720 struct mlx5e_channel *c;
1721 int err;
1722
1723 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1724 if (!c)
1725 return -ENOMEM;
1726
1727 c->priv = priv;
a43b25da
SM		 1728 c->mdev = priv->mdev;
1729 c->tstamp = &priv->tstamp;
f62b8bb8
AV		 1730 c->ix = ix;
1731 c->cpu = cpu;
1732 c->pdev = &priv->mdev->pdev->dev;
1733 c->netdev = priv->netdev;
b50d292b 1734 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
6a9764ef
SM		 1735 c->num_tc = params->num_tc;
1736 c->xdp = !!params->xdp_prog;
cb3c7fd4 1737
f62b8bb8
AV		 1738 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1739
6a9764ef 1740 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
f62b8bb8
AV		 1741 if (err)
1742 goto err_napi_del;
1743
6a9764ef 1744 err = mlx5e_open_tx_cqs(c, params, cparam);
d3c9bc27
TT		 1745 if (err)
1746 goto err_close_icosq_cq;
1747
6a9764ef 1748 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
f62b8bb8
AV		 1749 if (err)
1750 goto err_close_tx_cqs;
f62b8bb8 1751
d7a0ecab 1752 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
6a9764ef
SM		 1753 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1754 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
d7a0ecab
SM		 1755 if (err)
1756 goto err_close_rx_cq;
1757
f62b8bb8
AV		 1758 napi_enable(&c->napi);
1759
6a9764ef 1760 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1761 if (err)
1762 goto err_disable_napi;
1763
6a9764ef 1764 err = mlx5e_open_sqs(c, params, cparam);
d3c9bc27
TT		 1765 if (err)
1766 goto err_close_icosq;
1767
6a9764ef 1768 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
d7a0ecab
SM		 1769 if (err)
1770 goto err_close_sqs;
b5503b99 1771
6a9764ef 1772 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
f62b8bb8 1773 if (err)
b5503b99 1774 goto err_close_xdp_sq;
f62b8bb8 1775
f62b8bb8
AV		 1776 *cp = c;
1777
1778 return 0;
b5503b99 1779err_close_xdp_sq:
d7a0ecab 1780 if (c->xdp)
31391048 1781 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8
AV		 1782
1783err_close_sqs:
1784 mlx5e_close_sqs(c);
1785
d3c9bc27 1786err_close_icosq:
31391048 1787 mlx5e_close_icosq(&c->icosq);
d3c9bc27 1788
f62b8bb8
AV		 1789err_disable_napi:
1790 napi_disable(&c->napi);
d7a0ecab 1791 if (c->xdp)
31871f87 1792 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 1793
1794err_close_rx_cq:
f62b8bb8
AV		 1795 mlx5e_close_cq(&c->rq.cq);
1796
1797err_close_tx_cqs:
1798 mlx5e_close_tx_cqs(c);
1799
d3c9bc27
TT		 1800err_close_icosq_cq:
1801 mlx5e_close_cq(&c->icosq.cq);
1802
f62b8bb8
AV		 1803err_napi_del:
1804 netif_napi_del(&c->napi);
1805 kfree(c);
1806
1807 return err;
1808}
1809
acc6c595
SM		 1810static void mlx5e_activate_channel(struct mlx5e_channel *c)
1811{
1812 int tc;
1813
1814 for (tc = 0; tc < c->num_tc; tc++)
1815 mlx5e_activate_txqsq(&c->sq[tc]);
1816 mlx5e_activate_rq(&c->rq);
a43b25da 1817 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
acc6c595
SM		 1818}
1819
1820static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1821{
1822 int tc;
1823
1824 mlx5e_deactivate_rq(&c->rq);
1825 for (tc = 0; tc < c->num_tc; tc++)
1826 mlx5e_deactivate_txqsq(&c->sq[tc]);
1827}
1828
f62b8bb8
AV		 1829static void mlx5e_close_channel(struct mlx5e_channel *c)
1830{
1831 mlx5e_close_rq(&c->rq);
b5503b99 1832 if (c->xdp)
31391048 1833 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8 1834 mlx5e_close_sqs(c);
31391048 1835 mlx5e_close_icosq(&c->icosq);
f62b8bb8 1836 napi_disable(&c->napi);
b5503b99 1837 if (c->xdp)
31871f87 1838 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8
AV		 1839 mlx5e_close_cq(&c->rq.cq);
1840 mlx5e_close_tx_cqs(c);
d3c9bc27 1841 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1842 netif_napi_del(&c->napi);
7ae92ae5 1843
f62b8bb8
AV		 1844 kfree(c);
1845}
1846
1847static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
6a9764ef 1848 struct mlx5e_params *params,
f62b8bb8
AV		 1849 struct mlx5e_rq_param *param)
1850{
1851 void *rqc = param->rqc;
1852 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1853
6a9764ef 1854 switch (params->rq_wq_type) {
461017cb 1855 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef
SM		 1856 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1857 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
461017cb
TT		 1858 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1859 break;
1860 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1861 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1862 }
1863
f62b8bb8
AV		 1864 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1865 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
6a9764ef 1866 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
b50d292b 1867 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1868 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
6a9764ef 1869 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
102722fc 1870 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
f62b8bb8 1871
311c7c71 1872 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1873 param->wq.linear = 1;
1874}
1875
556dd1b9
TT		 1876static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1877{
1878 void *rqc = param->rqc;
1879 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1880
1881 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1882 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1883}
1884
d3c9bc27
TT		 1885static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1886 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1887{
1888 void *sqc = param->sqc;
1889 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1890
f62b8bb8 1891 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1892 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1893
311c7c71 1894 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1895}
1896
1897static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
6a9764ef 1898 struct mlx5e_params *params,
d3c9bc27
TT		 1899 struct mlx5e_sq_param *param)
1900{
1901 void *sqc = param->sqc;
1902 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1903
1904 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1905 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
f62b8bb8
AV		 1906}
1907
1908static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1909 struct mlx5e_cq_param *param)
1910{
1911 void *cqc = param->cqc;
1912
30aa60b3 1913 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 1914}
1915
1916static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1917 struct mlx5e_params *params,
f62b8bb8
AV		 1918 struct mlx5e_cq_param *param)
1919{
1920 void *cqc = param->cqc;
461017cb 1921 u8 log_cq_size;
f62b8bb8 1922
6a9764ef 1923 switch (params->rq_wq_type) {
461017cb 1924 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 1925 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
461017cb
TT		 1926 break;
1927 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 1928 log_cq_size = params->log_rq_size;
461017cb
TT		 1929 }
1930
1931 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
6a9764ef 1932 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1933 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1934 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1935 }
f62b8bb8
AV		 1936
1937 mlx5e_build_common_cq_param(priv, param);
1938}
1939
1940static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1941 struct mlx5e_params *params,
f62b8bb8
AV		 1942 struct mlx5e_cq_param *param)
1943{
1944 void *cqc = param->cqc;
1945
6a9764ef 1946 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
f62b8bb8
AV		 1947
1948 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1949
1950 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1951}
1952
d3c9bc27 1953static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1954 u8 log_wq_size,
1955 struct mlx5e_cq_param *param)
d3c9bc27
TT		 1956{
1957 void *cqc = param->cqc;
1958
1959 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1960
1961 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1962
1963 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1964}
1965
1966static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1967 u8 log_wq_size,
1968 struct mlx5e_sq_param *param)
d3c9bc27
TT		 1969{
1970 void *sqc = param->sqc;
1971 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1972
1973 mlx5e_build_sq_param_common(priv, param);
1974
1975 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1976 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1977}
1978
b5503b99 1979static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
6a9764ef 1980 struct mlx5e_params *params,
b5503b99
SM		 1981 struct mlx5e_sq_param *param)
1982{
1983 void *sqc = param->sqc;
1984 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1985
1986 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1987 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
b5503b99
SM		 1988}
1989
6a9764ef
SM		 1990static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1991 struct mlx5e_params *params,
1992 struct mlx5e_channel_param *cparam)
f62b8bb8 1993{
bc77b240 1994 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1995
6a9764ef
SM		 1996 mlx5e_build_rq_param(priv, params, &cparam->rq);
1997 mlx5e_build_sq_param(priv, params, &cparam->sq);
1998 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
1999 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2000 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2001 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2002 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
f62b8bb8
AV		 2003}
2004
55c2503d
SM		 2005int mlx5e_open_channels(struct mlx5e_priv *priv,
2006 struct mlx5e_channels *chs)
f62b8bb8 2007{
6b87663f 2008 struct mlx5e_channel_param *cparam;
03289b88 2009 int err = -ENOMEM;
f62b8bb8 2010 int i;
f62b8bb8 2011
6a9764ef 2012 chs->num = chs->params.num_channels;
03289b88 2013
ff9c852f 2014 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
6b87663f 2015 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
acc6c595
SM		 2016 if (!chs->c || !cparam)
2017 goto err_free;
f62b8bb8 2018
6a9764ef 2019 mlx5e_build_channel_param(priv, &chs->params, cparam);
ff9c852f 2020 for (i = 0; i < chs->num; i++) {
6a9764ef 2021 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
f62b8bb8
AV		 2022 if (err)
2023 goto err_close_channels;
2024 }
2025
6b87663f 2026 kfree(cparam);
f62b8bb8
AV		 2027 return 0;
2028
2029err_close_channels:
2030 for (i--; i >= 0; i--)
ff9c852f 2031 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2032
acc6c595 2033err_free:
ff9c852f 2034 kfree(chs->c);
6b87663f 2035 kfree(cparam);
ff9c852f 2036 chs->num = 0;
f62b8bb8
AV		 2037 return err;
2038}
2039
acc6c595 2040static void mlx5e_activate_channels(struct mlx5e_channels *chs)
f62b8bb8
AV		 2041{
2042 int i;
2043
acc6c595
SM		 2044 for (i = 0; i < chs->num; i++)
2045 mlx5e_activate_channel(chs->c[i]);
2046}
2047
2048static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2049{
2050 int err = 0;
2051 int i;
2052
2053 for (i = 0; i < chs->num; i++) {
2054 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2055 if (err)
2056 break;
2057 }
2058
2059 return err;
2060}
2061
2062static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2063{
2064 int i;
2065
2066 for (i = 0; i < chs->num; i++)
2067 mlx5e_deactivate_channel(chs->c[i]);
2068}
2069
55c2503d 2070void mlx5e_close_channels(struct mlx5e_channels *chs)
acc6c595
SM		 2071{
2072 int i;
c3b7c5c9 2073
ff9c852f
SM		 2074 for (i = 0; i < chs->num; i++)
2075 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2076
ff9c852f
SM		 2077 kfree(chs->c);
2078 chs->num = 0;
f62b8bb8
AV		 2079}
2080
a5f97fee
SM		 2081static int
2082mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 2083{
2084 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2085 void *rqtc;
2086 int inlen;
2087 int err;
1da36696 2088 u32 *in;
a5f97fee 2089 int i;
f62b8bb8 2090
f62b8bb8
AV		 2091 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2092 in = mlx5_vzalloc(inlen);
2093 if (!in)
2094 return -ENOMEM;
2095
2096 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2097
2098 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2099 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2100
a5f97fee
SM		 2101 for (i = 0; i < sz; i++)
2102 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2be6967c 2103
398f3351
HHZ		 2104 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2105 if (!err)
2106 rqt->enabled = true;
f62b8bb8
AV		 2107
2108 kvfree(in);
1da36696
TT		 2109 return err;
2110}
2111
cb67b832 2112void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2113{
398f3351
HHZ		 2114 rqt->enabled = false;
2115 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2116}
2117
8f493ffd 2118int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2119{
2120 struct mlx5e_rqt *rqt = &priv->indir_rqt;
8f493ffd 2121 int err;
6bfd390b 2122
8f493ffd
SM		 2123 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2124 if (err)
2125 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2126 return err;
6bfd390b
HHZ		 2127}
2128
cb67b832 2129int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2130{
398f3351 2131 struct mlx5e_rqt *rqt;
1da36696
TT		 2132 int err;
2133 int ix;
2134
6bfd390b 2135 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351 2136 rqt = &priv->direct_tir[ix].rqt;
a5f97fee 2137 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
1da36696
TT		 2138 if (err)
2139 goto err_destroy_rqts;
2140 }
2141
2142 return 0;
2143
2144err_destroy_rqts:
8f493ffd 2145 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
1da36696 2146 for (ix--; ix >= 0; ix--)
398f3351 2147 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2148
f62b8bb8
AV		 2149 return err;
2150}
2151
8f493ffd
SM		 2152void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2153{
2154 int i;
2155
2156 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2157 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2158}
2159
a5f97fee
SM		 2160static int mlx5e_rx_hash_fn(int hfunc)
2161{
2162 return (hfunc == ETH_RSS_HASH_TOP) ?
2163 MLX5_RX_HASH_FN_TOEPLITZ :
2164 MLX5_RX_HASH_FN_INVERTED_XOR8;
2165}
2166
2167static int mlx5e_bits_invert(unsigned long a, int size)
2168{
2169 int inv = 0;
2170 int i;
2171
2172 for (i = 0; i < size; i++)
2173 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2174
2175 return inv;
2176}
2177
2178static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2179 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2180{
2181 int i;
2182
2183 for (i = 0; i < sz; i++) {
2184 u32 rqn;
2185
2186 if (rrp.is_rss) {
2187 int ix = i;
2188
2189 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2190 ix = mlx5e_bits_invert(i, ilog2(sz));
2191
6a9764ef 2192 ix = priv->channels.params.indirection_rqt[ix];
a5f97fee
SM		 2193 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2194 } else {
2195 rqn = rrp.rqn;
2196 }
2197 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2198 }
2199}
2200
2201int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2202 struct mlx5e_redirect_rqt_param rrp)
5c50368f
AS		 2203{
2204 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2205 void *rqtc;
2206 int inlen;
1da36696 2207 u32 *in;
5c50368f
AS		 2208 int err;
2209
5c50368f
AS		 2210 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2211 in = mlx5_vzalloc(inlen);
2212 if (!in)
2213 return -ENOMEM;
2214
2215 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2216
2217 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5c50368f 2218 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
a5f97fee 2219 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
1da36696 2220 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2221
2222 kvfree(in);
5c50368f
AS		 2223 return err;
2224}
2225
a5f97fee
SM		 2226static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2227 struct mlx5e_redirect_rqt_param rrp)
2228{
2229 if (!rrp.is_rss)
2230 return rrp.rqn;
2231
2232 if (ix >= rrp.rss.channels->num)
2233 return priv->drop_rq.rqn;
2234
2235 return rrp.rss.channels->c[ix]->rq.rqn;
2236}
2237
2238static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2239 struct mlx5e_redirect_rqt_param rrp)
40ab6a6e 2240{
1da36696
TT		 2241 u32 rqtn;
2242 int ix;
2243
398f3351 2244 if (priv->indir_rqt.enabled) {
a5f97fee 2245 /* RSS RQ table */
398f3351 2246 rqtn = priv->indir_rqt.rqtn;
a5f97fee 2247 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
398f3351
HHZ		 2248 }
2249
a5f97fee
SM		 2250 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2251 struct mlx5e_redirect_rqt_param direct_rrp = {
2252 .is_rss = false,
95632791
AM		 2253 {
2254 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2255 },
a5f97fee
SM		 2256 };
2257
2258 /* Direct RQ Tables */
398f3351
HHZ		 2259 if (!priv->direct_tir[ix].rqt.enabled)
2260 continue;
a5f97fee 2261
398f3351 2262 rqtn = priv->direct_tir[ix].rqt.rqtn;
a5f97fee 2263 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
1da36696 2264 }
40ab6a6e
AS		 2265}
2266
a5f97fee
SM		 2267static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2268 struct mlx5e_channels *chs)
2269{
2270 struct mlx5e_redirect_rqt_param rrp = {
2271 .is_rss = true,
95632791
AM		 2272 {
2273 .rss = {
2274 .channels = chs,
2275 .hfunc = chs->params.rss_hfunc,
2276 }
2277 },
a5f97fee
SM		 2278 };
2279
2280 mlx5e_redirect_rqts(priv, rrp);
2281}
2282
2283static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2284{
2285 struct mlx5e_redirect_rqt_param drop_rrp = {
2286 .is_rss = false,
95632791
AM		 2287 {
2288 .rqn = priv->drop_rq.rqn,
2289 },
a5f97fee
SM		 2290 };
2291
2292 mlx5e_redirect_rqts(priv, drop_rrp);
2293}
2294
6a9764ef 2295static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
5c50368f 2296{
6a9764ef 2297 if (!params->lro_en)
5c50368f
AS		 2298 return;
2299
2300#define ROUGH_MAX_L2_L3_HDR_SZ 256
2301
2302 MLX5_SET(tirc, tirc, lro_enable_mask,
2303 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2304 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2305 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
6a9764ef
SM		 2306 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2307 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
5c50368f
AS		 2308}
2309
6a9764ef
SM		 2310void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2311 enum mlx5e_traffic_types tt,
2312 void *tirc)
bdfc028d 2313{
a100ff3e
GP		 2314 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2315
2316#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2317 MLX5_HASH_FIELD_SEL_DST_IP)
2318
2319#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2320 MLX5_HASH_FIELD_SEL_DST_IP |\
2321 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2322 MLX5_HASH_FIELD_SEL_L4_DPORT)
2323
2324#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2325 MLX5_HASH_FIELD_SEL_DST_IP |\
2326 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2327
6a9764ef
SM		 2328 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2329 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
bdfc028d
TT		 2330 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2331 rx_hash_toeplitz_key);
2332 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2333 rx_hash_toeplitz_key);
2334
2335 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
6a9764ef 2336 memcpy(rss_key, params->toeplitz_hash_key, len);
bdfc028d 2337 }
a100ff3e
GP		 2338
2339 switch (tt) {
2340 case MLX5E_TT_IPV4_TCP:
2341 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2342 MLX5_L3_PROT_TYPE_IPV4);
2343 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2344 MLX5_L4_PROT_TYPE_TCP);
2345 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2346 MLX5_HASH_IP_L4PORTS);
2347 break;
2348
2349 case MLX5E_TT_IPV6_TCP:
2350 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2351 MLX5_L3_PROT_TYPE_IPV6);
2352 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2353 MLX5_L4_PROT_TYPE_TCP);
2354 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2355 MLX5_HASH_IP_L4PORTS);
2356 break;
2357
2358 case MLX5E_TT_IPV4_UDP:
2359 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2360 MLX5_L3_PROT_TYPE_IPV4);
2361 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2362 MLX5_L4_PROT_TYPE_UDP);
2363 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2364 MLX5_HASH_IP_L4PORTS);
2365 break;
2366
2367 case MLX5E_TT_IPV6_UDP:
2368 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2369 MLX5_L3_PROT_TYPE_IPV6);
2370 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2371 MLX5_L4_PROT_TYPE_UDP);
2372 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2373 MLX5_HASH_IP_L4PORTS);
2374 break;
2375
2376 case MLX5E_TT_IPV4_IPSEC_AH:
2377 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2378 MLX5_L3_PROT_TYPE_IPV4);
2379 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2380 MLX5_HASH_IP_IPSEC_SPI);
2381 break;
2382
2383 case MLX5E_TT_IPV6_IPSEC_AH:
2384 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2385 MLX5_L3_PROT_TYPE_IPV6);
2386 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2387 MLX5_HASH_IP_IPSEC_SPI);
2388 break;
2389
2390 case MLX5E_TT_IPV4_IPSEC_ESP:
2391 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2392 MLX5_L3_PROT_TYPE_IPV4);
2393 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2394 MLX5_HASH_IP_IPSEC_SPI);
2395 break;
2396
2397 case MLX5E_TT_IPV6_IPSEC_ESP:
2398 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2399 MLX5_L3_PROT_TYPE_IPV6);
2400 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2401 MLX5_HASH_IP_IPSEC_SPI);
2402 break;
2403
2404 case MLX5E_TT_IPV4:
2405 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2406 MLX5_L3_PROT_TYPE_IPV4);
2407 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2408 MLX5_HASH_IP);
2409 break;
2410
2411 case MLX5E_TT_IPV6:
2412 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2413 MLX5_L3_PROT_TYPE_IPV6);
2414 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2415 MLX5_HASH_IP);
2416 break;
2417 default:
2418 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2419 }
bdfc028d
TT		 2420}
2421
ab0394fe 2422static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2423{
2424 struct mlx5_core_dev *mdev = priv->mdev;
2425
2426 void *in;
2427 void *tirc;
2428 int inlen;
2429 int err;
ab0394fe 2430 int tt;
1da36696 2431 int ix;
5c50368f
AS		 2432
2433 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2434 in = mlx5_vzalloc(inlen);
2435 if (!in)
2436 return -ENOMEM;
2437
2438 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2439 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2440
6a9764ef 2441 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
5c50368f 2442
1da36696 2443 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2444 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2445 inlen);
ab0394fe 2446 if (err)
1da36696 2447 goto free_in;
ab0394fe 2448 }
5c50368f 2449
6bfd390b 2450 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2451 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2452 in, inlen);
2453 if (err)
2454 goto free_in;
2455 }
2456
2457free_in:
5c50368f
AS		 2458 kvfree(in);
2459
2460 return err;
2461}
2462
cd255eff 2463static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2464{
40ab6a6e 2465 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 2466 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 2467 int err;
2468
cd255eff 2469 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2470 if (err)
2471 return err;
2472
cd255eff
SM		 2473 /* Update vport context MTU */
2474 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2475 return 0;
2476}
40ab6a6e 2477
cd255eff
SM		 2478static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2479{
2480 struct mlx5_core_dev *mdev = priv->mdev;
2481 u16 hw_mtu = 0;
2482 int err;
40ab6a6e 2483
cd255eff
SM		 2484 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2485 if (err || !hw_mtu) /* fallback to port oper mtu */
2486 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2487
2488 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2489}
2490
2e20a151 2491static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
cd255eff 2492{
2e20a151 2493 struct net_device *netdev = priv->netdev;
cd255eff
SM		 2494 u16 mtu;
2495 int err;
2496
2497 err = mlx5e_set_mtu(priv, netdev->mtu);
2498 if (err)
2499 return err;
40ab6a6e 2500
cd255eff
SM		 2501 mlx5e_query_mtu(priv, &mtu);
2502 if (mtu != netdev->mtu)
2503 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2504 __func__, mtu, netdev->mtu);
40ab6a6e 2505
cd255eff 2506 netdev->mtu = mtu;
40ab6a6e
AS		 2507 return 0;
2508}
2509
08fb1dac
SM		 2510static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2511{
2512 struct mlx5e_priv *priv = netdev_priv(netdev);
6a9764ef
SM		 2513 int nch = priv->channels.params.num_channels;
2514 int ntc = priv->channels.params.num_tc;
08fb1dac
SM		 2515 int tc;
2516
2517 netdev_reset_tc(netdev);
2518
2519 if (ntc == 1)
2520 return;
2521
2522 netdev_set_num_tc(netdev, ntc);
2523
7ccdd084
RS		 2524 /* Map netdev TCs to offset 0
2525 * We have our own UP to TXQ mapping for QoS
2526 */
08fb1dac 2527 for (tc = 0; tc < ntc; tc++)
7ccdd084 2528 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2529}
2530
acc6c595
SM		 2531static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2532{
2533 struct mlx5e_channel *c;
2534 struct mlx5e_txqsq *sq;
2535 int i, tc;
2536
2537 for (i = 0; i < priv->channels.num; i++)
2538 for (tc = 0; tc < priv->profile->max_tc; tc++)
2539 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2540
2541 for (i = 0; i < priv->channels.num; i++) {
2542 c = priv->channels.c[i];
2543 for (tc = 0; tc < c->num_tc; tc++) {
2544 sq = &c->sq[tc];
2545 priv->txq2sq[sq->txq_ix] = sq;
2546 }
2547 }
2548}
2549
2550static void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2551{
9008ae07
SM		 2552 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2553 struct net_device *netdev = priv->netdev;
2554
2555 mlx5e_netdev_set_tcs(netdev);
053ee0a7
TR		 2556 netif_set_real_num_tx_queues(netdev, num_txqs);
2557 netif_set_real_num_rx_queues(netdev, priv->channels.num);
9008ae07 2558
acc6c595
SM		 2559 mlx5e_build_channels_tx_maps(priv);
2560 mlx5e_activate_channels(&priv->channels);
2561 netif_tx_start_all_queues(priv->netdev);
9008ae07
SM		 2562
2563 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager))
2564 mlx5e_add_sqs_fwd_rules(priv);
2565
acc6c595 2566 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
9008ae07 2567 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
acc6c595
SM		 2568}
2569
2570static void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2571{
9008ae07
SM		 2572 mlx5e_redirect_rqts_to_drop(priv);
2573
2574 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager))
2575 mlx5e_remove_sqs_fwd_rules(priv);
2576
acc6c595
SM		 2577 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2578 * polling for inactive tx queues.
2579 */
2580 netif_tx_stop_all_queues(priv->netdev);
2581 netif_tx_disable(priv->netdev);
2582 mlx5e_deactivate_channels(&priv->channels);
2583}
2584
55c2503d 2585void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2e20a151
SM		 2586 struct mlx5e_channels *new_chs,
2587 mlx5e_fp_hw_modify hw_modify)
55c2503d
SM		 2588{
2589 struct net_device *netdev = priv->netdev;
2590 int new_num_txqs;
2591
2592 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2593
2594 netif_carrier_off(netdev);
2595
2596 if (new_num_txqs < netdev->real_num_tx_queues)
2597 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2598
2599 mlx5e_deactivate_priv_channels(priv);
2600 mlx5e_close_channels(&priv->channels);
2601
2602 priv->channels = *new_chs;
2603
2e20a151
SM		 2604 /* New channels are ready to roll, modify HW settings if needed */
2605 if (hw_modify)
2606 hw_modify(priv);
2607
55c2503d
SM		 2608 mlx5e_refresh_tirs(priv, false);
2609 mlx5e_activate_priv_channels(priv);
2610
2611 mlx5e_update_carrier(priv);
2612}
2613
40ab6a6e
AS		 2614int mlx5e_open_locked(struct net_device *netdev)
2615{
2616 struct mlx5e_priv *priv = netdev_priv(netdev);
40ab6a6e
AS		 2617 int err;
2618
2619 set_bit(MLX5E_STATE_OPENED, &priv->state);
2620
ff9c852f 2621 err = mlx5e_open_channels(priv, &priv->channels);
acc6c595 2622 if (err)
343b29f3 2623 goto err_clear_state_opened_flag;
40ab6a6e 2624
b676f653 2625 mlx5e_refresh_tirs(priv, false);
acc6c595 2626 mlx5e_activate_priv_channels(priv);
ce89ef36 2627 mlx5e_update_carrier(priv);
ef9814de 2628 mlx5e_timestamp_init(priv);
be4891af 2629
cb67b832
HHZ		 2630 if (priv->profile->update_stats)
2631 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2632
9b37b07f 2633 return 0;
343b29f3
AS		 2634
2635err_clear_state_opened_flag:
2636 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2637 return err;
40ab6a6e
AS		 2638}
2639
cb67b832 2640int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2641{
2642 struct mlx5e_priv *priv = netdev_priv(netdev);
2643 int err;
2644
2645 mutex_lock(&priv->state_lock);
2646 err = mlx5e_open_locked(netdev);
2647 mutex_unlock(&priv->state_lock);
2648
2649 return err;
2650}
2651
2652int mlx5e_close_locked(struct net_device *netdev)
2653{
2654 struct mlx5e_priv *priv = netdev_priv(netdev);
2655
a1985740
AS		 2656 /* May already be CLOSED in case a previous configuration operation
2657 * (e.g RX/TX queue size change) that involves close&open failed.
2658 */
2659 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2660 return 0;
2661
40ab6a6e
AS		 2662 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2663
ef9814de 2664 mlx5e_timestamp_cleanup(priv);
40ab6a6e 2665 netif_carrier_off(priv->netdev);
acc6c595
SM		 2666 mlx5e_deactivate_priv_channels(priv);
2667 mlx5e_close_channels(&priv->channels);
40ab6a6e
AS		 2668
2669 return 0;
2670}
2671
cb67b832 2672int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2673{
2674 struct mlx5e_priv *priv = netdev_priv(netdev);
2675 int err;
2676
26e59d80
MHY		 2677 if (!netif_device_present(netdev))
2678 return -ENODEV;
2679
40ab6a6e
AS		 2680 mutex_lock(&priv->state_lock);
2681 err = mlx5e_close_locked(netdev);
2682 mutex_unlock(&priv->state_lock);
2683
2684 return err;
2685}
2686
a43b25da 2687static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2688 struct mlx5e_rq *rq,
2689 struct mlx5e_rq_param *param)
40ab6a6e 2690{
40ab6a6e
AS		 2691 void *rqc = param->rqc;
2692 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2693 int err;
2694
2695 param->wq.db_numa_node = param->wq.buf_numa_node;
2696
2697 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2698 &rq->wq_ctrl);
2699 if (err)
2700 return err;
2701
a43b25da 2702 rq->mdev = mdev;
40ab6a6e
AS		 2703
2704 return 0;
2705}
2706
a43b25da 2707static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2708 struct mlx5e_cq *cq,
2709 struct mlx5e_cq_param *param)
40ab6a6e 2710{
95b6c6a5 2711 return mlx5e_alloc_cq_common(mdev, param, cq);
40ab6a6e
AS		 2712}
2713
a43b25da
SM		 2714static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2715 struct mlx5e_rq *drop_rq)
40ab6a6e 2716{
a43b25da
SM		 2717 struct mlx5e_cq_param cq_param = {};
2718 struct mlx5e_rq_param rq_param = {};
2719 struct mlx5e_cq *cq = &drop_rq->cq;
40ab6a6e
AS		 2720 int err;
2721
556dd1b9 2722 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e 2723
a43b25da 2724 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
40ab6a6e
AS		 2725 if (err)
2726 return err;
2727
3b77235b 2728 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 2729 if (err)
3b77235b 2730 goto err_free_cq;
40ab6a6e 2731
a43b25da 2732 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
40ab6a6e 2733 if (err)
3b77235b 2734 goto err_destroy_cq;
40ab6a6e 2735
a43b25da 2736 err = mlx5e_create_rq(drop_rq, &rq_param);
40ab6a6e 2737 if (err)
3b77235b 2738 goto err_free_rq;
40ab6a6e
AS		 2739
2740 return 0;
2741
3b77235b 2742err_free_rq:
a43b25da 2743 mlx5e_free_rq(drop_rq);
40ab6a6e
AS		 2744
2745err_destroy_cq:
a43b25da 2746 mlx5e_destroy_cq(cq);
40ab6a6e 2747
3b77235b 2748err_free_cq:
a43b25da 2749 mlx5e_free_cq(cq);
3b77235b 2750
40ab6a6e
AS		 2751 return err;
2752}
2753
a43b25da 2754static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
40ab6a6e 2755{
a43b25da
SM		 2756 mlx5e_destroy_rq(drop_rq);
2757 mlx5e_free_rq(drop_rq);
2758 mlx5e_destroy_cq(&drop_rq->cq);
2759 mlx5e_free_cq(&drop_rq->cq);
40ab6a6e
AS		 2760}
2761
2762static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2763{
2764 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 2765 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2766 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2767
08fb1dac 2768 MLX5_SET(tisc, tisc, prio, tc << 1);
b50d292b 2769 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2770
2771 if (mlx5_lag_is_lacp_owner(mdev))
2772 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2773
40ab6a6e
AS		 2774 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2775}
2776
2777static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2778{
2779 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2780}
2781
cb67b832 2782int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2783{
2784 int err;
2785 int tc;
2786
6bfd390b 2787 for (tc = 0; tc < priv->profile->max_tc; tc++) {
40ab6a6e
AS		 2788 err = mlx5e_create_tis(priv, tc);
2789 if (err)
2790 goto err_close_tises;
2791 }
2792
2793 return 0;
2794
2795err_close_tises:
2796 for (tc--; tc >= 0; tc--)
2797 mlx5e_destroy_tis(priv, tc);
2798
2799 return err;
2800}
2801
cb67b832 2802void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2803{
2804 int tc;
2805
6bfd390b 2806 for (tc = 0; tc < priv->profile->max_tc; tc++)
40ab6a6e
AS		 2807 mlx5e_destroy_tis(priv, tc);
2808}
2809
6a9764ef
SM		 2810static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2811 enum mlx5e_traffic_types tt,
2812 u32 *tirc)
f62b8bb8 2813{
b50d292b 2814 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2815
6a9764ef 2816 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
f62b8bb8 2817
4cbeaff5 2818 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2819 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
6a9764ef 2820 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
f62b8bb8
AV		 2821}
2822
6a9764ef 2823static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
f62b8bb8 2824{
b50d292b 2825 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696 2826
6a9764ef 2827 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
1da36696
TT		 2828
2829 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2830 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2831 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2832}
2833
8f493ffd 2834int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2835{
724b2aa1 2836 struct mlx5e_tir *tir;
f62b8bb8
AV		 2837 void *tirc;
2838 int inlen;
2839 int err;
1da36696 2840 u32 *in;
1da36696 2841 int tt;
f62b8bb8
AV		 2842
2843 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2844 in = mlx5_vzalloc(inlen);
2845 if (!in)
2846 return -ENOMEM;
2847
1da36696
TT		 2848 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2849 memset(in, 0, inlen);
724b2aa1 2850 tir = &priv->indir_tir[tt];
1da36696 2851 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2852 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
724b2aa1 2853 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2854 if (err)
40ab6a6e 2855 goto err_destroy_tirs;
f62b8bb8
AV		 2856 }
2857
6bfd390b
HHZ		 2858 kvfree(in);
2859
2860 return 0;
2861
2862err_destroy_tirs:
8f493ffd 2863 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
6bfd390b
HHZ		 2864 for (tt--; tt >= 0; tt--)
2865 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2866
2867 kvfree(in);
2868
2869 return err;
2870}
2871
cb67b832 2872int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2873{
2874 int nch = priv->profile->max_nch(priv->mdev);
2875 struct mlx5e_tir *tir;
2876 void *tirc;
2877 int inlen;
2878 int err;
2879 u32 *in;
2880 int ix;
2881
2882 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2883 in = mlx5_vzalloc(inlen);
2884 if (!in)
2885 return -ENOMEM;
2886
1da36696
TT		 2887 for (ix = 0; ix < nch; ix++) {
2888 memset(in, 0, inlen);
724b2aa1 2889 tir = &priv->direct_tir[ix];
1da36696 2890 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2891 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
724b2aa1 2892 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2893 if (err)
2894 goto err_destroy_ch_tirs;
2895 }
2896
2897 kvfree(in);
2898
f62b8bb8
AV		 2899 return 0;
2900
1da36696 2901err_destroy_ch_tirs:
8f493ffd 2902 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
1da36696 2903 for (ix--; ix >= 0; ix--)
724b2aa1 2904 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2905
1da36696 2906 kvfree(in);
f62b8bb8
AV		 2907
2908 return err;
2909}
2910
8f493ffd 2911void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2912{
2913 int i;
2914
1da36696 2915 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2916 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2917}
2918
cb67b832 2919void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2920{
2921 int nch = priv->profile->max_nch(priv->mdev);
2922 int i;
2923
2924 for (i = 0; i < nch; i++)
2925 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2926}
2927
102722fc
GE		 2928static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2929{
2930 int err = 0;
2931 int i;
2932
2933 for (i = 0; i < chs->num; i++) {
2934 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2935 if (err)
2936 return err;
2937 }
2938
2939 return 0;
2940}
2941
f6d96a20 2942static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
36350114
GP		 2943{
2944 int err = 0;
2945 int i;
2946
ff9c852f
SM		 2947 for (i = 0; i < chs->num; i++) {
2948 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
36350114
GP		 2949 if (err)
2950 return err;
2951 }
2952
2953 return 0;
2954}
2955
08fb1dac
SM		 2956static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2957{
2958 struct mlx5e_priv *priv = netdev_priv(netdev);
6f9485af 2959 struct mlx5e_channels new_channels = {};
08fb1dac
SM		 2960 int err = 0;
2961
2962 if (tc && tc != MLX5E_MAX_NUM_TC)
2963 return -EINVAL;
2964
2965 mutex_lock(&priv->state_lock);
2966
6f9485af
SM		 2967 new_channels.params = priv->channels.params;
2968 new_channels.params.num_tc = tc ? tc : 1;
08fb1dac 2969
6f9485af
SM		 2970 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
2971 priv->channels.params = new_channels.params;
2972 goto out;
2973 }
08fb1dac 2974
6f9485af
SM		 2975 err = mlx5e_open_channels(priv, &new_channels);
2976 if (err)
2977 goto out;
08fb1dac 2978
2e20a151 2979 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
6f9485af 2980out:
08fb1dac 2981 mutex_unlock(&priv->state_lock);
08fb1dac
SM		 2982 return err;
2983}
2984
2985static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2986 __be16 proto, struct tc_to_netdev *tc)
2987{
e8f887ac
AV		 2988 struct mlx5e_priv *priv = netdev_priv(dev);
2989
2990 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2991 goto mqprio;
2992
2993 switch (tc->type) {
e3a2b7ed
AV		 2994 case TC_SETUP_CLSFLOWER:
2995 switch (tc->cls_flower->command) {
2996 case TC_CLSFLOWER_REPLACE:
2997 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2998 case TC_CLSFLOWER_DESTROY:
2999 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 3000 case TC_CLSFLOWER_STATS:
3001 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 3002 }
e8f887ac
AV		 3003 default:
3004 return -EOPNOTSUPP;
3005 }
3006
3007mqprio:
67ba422e 3008 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 3009 return -EINVAL;
3010
56f36acd
AN		 3011 tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3012
3013 return mlx5e_setup_tc(dev, tc->mqprio->num_tc);
08fb1dac
SM		 3014}
3015
bc1f4470 3016static void
f62b8bb8
AV		 3017mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3018{
3019 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 3020 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 3021 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 3022 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 3023
370bad0f
OG		 3024 if (mlx5e_is_uplink_rep(priv)) {
3025 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3026 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3027 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3028 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3029 } else {
3030 stats->rx_packets = sstats->rx_packets;
3031 stats->rx_bytes = sstats->rx_bytes;
3032 stats->tx_packets = sstats->tx_packets;
3033 stats->tx_bytes = sstats->tx_bytes;
3034 stats->tx_dropped = sstats->tx_queue_dropped;
3035 }
269e6b3a
GP		 3036
3037 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 3038
3039 stats->rx_length_errors =
9218b44d
GP		 3040 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3041 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3042 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 3043 stats->rx_crc_errors =
9218b44d
GP		 3044 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3045 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3046 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 3047 stats->tx_carrier_errors =
9218b44d 3048 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 3049 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3050 stats->rx_frame_errors;
3051 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3052
3053 /* vport multicast also counts packets that are dropped due to steering
3054 * or rx out of buffer
3055 */
9218b44d
GP		 3056 stats->multicast =
3057 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8 3058
f62b8bb8
AV		 3059}
3060
3061static void mlx5e_set_rx_mode(struct net_device *dev)
3062{
3063 struct mlx5e_priv *priv = netdev_priv(dev);
3064
7bb29755 3065 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3066}
3067
3068static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3069{
3070 struct mlx5e_priv *priv = netdev_priv(netdev);
3071 struct sockaddr *saddr = addr;
3072
3073 if (!is_valid_ether_addr(saddr->sa_data))
3074 return -EADDRNOTAVAIL;
3075
3076 netif_addr_lock_bh(netdev);
3077 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3078 netif_addr_unlock_bh(netdev);
3079
7bb29755 3080 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3081
3082 return 0;
3083}
3084
0e405443
GP		 3085#define MLX5E_SET_FEATURE(netdev, feature, enable) \
3086 do { \
3087 if (enable) \
3088 netdev->features |= feature; \
3089 else \
3090 netdev->features &= ~feature; \
3091 } while (0)
3092
3093typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3094
3095static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 3096{
3097 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3098 struct mlx5e_channels new_channels = {};
3099 int err = 0;
3100 bool reset;
f62b8bb8
AV		 3101
3102 mutex_lock(&priv->state_lock);
f62b8bb8 3103
2e20a151
SM		 3104 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3105 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3106
2e20a151
SM		 3107 new_channels.params = priv->channels.params;
3108 new_channels.params.lro_en = enable;
3109
3110 if (!reset) {
3111 priv->channels.params = new_channels.params;
3112 err = mlx5e_modify_tirs_lro(priv);
3113 goto out;
98e81b0a 3114 }
f62b8bb8 3115
2e20a151
SM		 3116 err = mlx5e_open_channels(priv, &new_channels);
3117 if (err)
3118 goto out;
0e405443 3119
2e20a151
SM		 3120 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3121out:
9b37b07f 3122 mutex_unlock(&priv->state_lock);
0e405443
GP		 3123 return err;
3124}
3125
3126static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
3127{
3128 struct mlx5e_priv *priv = netdev_priv(netdev);
3129
3130 if (enable)
3131 mlx5e_enable_vlan_filter(priv);
3132 else
3133 mlx5e_disable_vlan_filter(priv);
3134
3135 return 0;
3136}
3137
3138static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3139{
3140 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 3141
0e405443 3142 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 3143 netdev_err(netdev,
3144 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3145 return -EINVAL;
3146 }
3147
0e405443
GP		 3148 return 0;
3149}
3150
94cb1ebb
EBE		 3151static int set_feature_rx_all(struct net_device *netdev, bool enable)
3152{
3153 struct mlx5e_priv *priv = netdev_priv(netdev);
3154 struct mlx5_core_dev *mdev = priv->mdev;
3155
3156 return mlx5_set_port_fcs(mdev, !enable);
3157}
3158
102722fc
GE		 3159static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3160{
3161 struct mlx5e_priv *priv = netdev_priv(netdev);
3162 int err;
3163
3164 mutex_lock(&priv->state_lock);
3165
3166 priv->channels.params.scatter_fcs_en = enable;
3167 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3168 if (err)
3169 priv->channels.params.scatter_fcs_en = !enable;
3170
3171 mutex_unlock(&priv->state_lock);
3172
3173 return err;
3174}
3175
36350114
GP		 3176static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3177{
3178 struct mlx5e_priv *priv = netdev_priv(netdev);
ff9c852f 3179 int err = 0;
36350114
GP		 3180
3181 mutex_lock(&priv->state_lock);
3182
6a9764ef 3183 priv->channels.params.vlan_strip_disable = !enable;
ff9c852f
SM		 3184 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3185 goto unlock;
3186
3187 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
36350114 3188 if (err)
6a9764ef 3189 priv->channels.params.vlan_strip_disable = enable;
36350114 3190
ff9c852f 3191unlock:
36350114
GP		 3192 mutex_unlock(&priv->state_lock);
3193
3194 return err;
3195}
3196
45bf454a
MG		 3197#ifdef CONFIG_RFS_ACCEL
3198static int set_feature_arfs(struct net_device *netdev, bool enable)
3199{
3200 struct mlx5e_priv *priv = netdev_priv(netdev);
3201 int err;
3202
3203 if (enable)
3204 err = mlx5e_arfs_enable(priv);
3205 else
3206 err = mlx5e_arfs_disable(priv);
3207
3208 return err;
3209}
3210#endif
3211
0e405443
GP		 3212static int mlx5e_handle_feature(struct net_device *netdev,
3213 netdev_features_t wanted_features,
3214 netdev_features_t feature,
3215 mlx5e_feature_handler feature_handler)
3216{
3217 netdev_features_t changes = wanted_features ^ netdev->features;
3218 bool enable = !!(wanted_features & feature);
3219 int err;
3220
3221 if (!(changes & feature))
3222 return 0;
3223
3224 err = feature_handler(netdev, enable);
3225 if (err) {
3226 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
3227 enable ? "Enable" : "Disable", feature, err);
3228 return err;
3229 }
3230
3231 MLX5E_SET_FEATURE(netdev, feature, enable);
3232 return 0;
3233}
3234
3235static int mlx5e_set_features(struct net_device *netdev,
3236 netdev_features_t features)
3237{
3238 int err;
3239
3240 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3241 set_feature_lro);
3242 err |= mlx5e_handle_feature(netdev, features,
3243 NETIF_F_HW_VLAN_CTAG_FILTER,
3244 set_feature_vlan_filter);
3245 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3246 set_feature_tc_num_filters);
94cb1ebb
EBE		 3247 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3248 set_feature_rx_all);
102722fc
GE		 3249 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3250 set_feature_rx_fcs);
36350114
GP		 3251 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3252 set_feature_rx_vlan);
45bf454a
MG		 3253#ifdef CONFIG_RFS_ACCEL
3254 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3255 set_feature_arfs);
3256#endif
0e405443
GP		 3257
3258 return err ? -EINVAL : 0;
f62b8bb8
AV		 3259}
3260
3261static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3262{
3263 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3264 struct mlx5e_channels new_channels = {};
3265 int curr_mtu;
98e81b0a 3266 int err = 0;
506753b0 3267 bool reset;
f62b8bb8 3268
f62b8bb8 3269 mutex_lock(&priv->state_lock);
98e81b0a 3270
6a9764ef
SM		 3271 reset = !priv->channels.params.lro_en &&
3272 (priv->channels.params.rq_wq_type !=
506753b0
TT		 3273 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3274
2e20a151 3275 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3276
2e20a151 3277 curr_mtu = netdev->mtu;
f62b8bb8 3278 netdev->mtu = new_mtu;
98e81b0a 3279
2e20a151
SM		 3280 if (!reset) {
3281 mlx5e_set_dev_port_mtu(priv);
3282 goto out;
3283 }
98e81b0a 3284
2e20a151
SM		 3285 new_channels.params = priv->channels.params;
3286 err = mlx5e_open_channels(priv, &new_channels);
3287 if (err) {
3288 netdev->mtu = curr_mtu;
3289 goto out;
3290 }
3291
3292 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
f62b8bb8 3293
2e20a151
SM		 3294out:
3295 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 3296 return err;
3297}
3298
ef9814de
EBE		 3299static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3300{
3301 switch (cmd) {
3302 case SIOCSHWTSTAMP:
3303 return mlx5e_hwstamp_set(dev, ifr);
3304 case SIOCGHWTSTAMP:
3305 return mlx5e_hwstamp_get(dev, ifr);
3306 default:
3307 return -EOPNOTSUPP;
3308 }
3309}
3310
66e49ded
SM		 3311static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3312{
3313 struct mlx5e_priv *priv = netdev_priv(dev);
3314 struct mlx5_core_dev *mdev = priv->mdev;
3315
3316 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3317}
3318
79aab093
MS		 3319static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3320 __be16 vlan_proto)
66e49ded
SM		 3321{
3322 struct mlx5e_priv *priv = netdev_priv(dev);
3323 struct mlx5_core_dev *mdev = priv->mdev;
3324
79aab093
MS		 3325 if (vlan_proto != htons(ETH_P_8021Q))
3326 return -EPROTONOSUPPORT;
3327
66e49ded
SM		 3328 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3329 vlan, qos);
3330}
3331
f942380c
MHY		 3332static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3333{
3334 struct mlx5e_priv *priv = netdev_priv(dev);
3335 struct mlx5_core_dev *mdev = priv->mdev;
3336
3337 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3338}
3339
1edc57e2
MHY		 3340static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3341{
3342 struct mlx5e_priv *priv = netdev_priv(dev);
3343 struct mlx5_core_dev *mdev = priv->mdev;
3344
3345 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3346}
bd77bf1c
MHY		 3347
3348static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3349 int max_tx_rate)
3350{
3351 struct mlx5e_priv *priv = netdev_priv(dev);
3352 struct mlx5_core_dev *mdev = priv->mdev;
3353
bd77bf1c 3354 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3355 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3356}
3357
66e49ded
SM		 3358static int mlx5_vport_link2ifla(u8 esw_link)
3359{
3360 switch (esw_link) {
3361 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3362 return IFLA_VF_LINK_STATE_DISABLE;
3363 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3364 return IFLA_VF_LINK_STATE_ENABLE;
3365 }
3366 return IFLA_VF_LINK_STATE_AUTO;
3367}
3368
3369static int mlx5_ifla_link2vport(u8 ifla_link)
3370{
3371 switch (ifla_link) {
3372 case IFLA_VF_LINK_STATE_DISABLE:
3373 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3374 case IFLA_VF_LINK_STATE_ENABLE:
3375 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3376 }
3377 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3378}
3379
3380static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3381 int link_state)
3382{
3383 struct mlx5e_priv *priv = netdev_priv(dev);
3384 struct mlx5_core_dev *mdev = priv->mdev;
3385
3386 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3387 mlx5_ifla_link2vport(link_state));
3388}
3389
3390static int mlx5e_get_vf_config(struct net_device *dev,
3391 int vf, struct ifla_vf_info *ivi)
3392{
3393 struct mlx5e_priv *priv = netdev_priv(dev);
3394 struct mlx5_core_dev *mdev = priv->mdev;
3395 int err;
3396
3397 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3398 if (err)
3399 return err;
3400 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3401 return 0;
3402}
3403
3404static int mlx5e_get_vf_stats(struct net_device *dev,
3405 int vf, struct ifla_vf_stats *vf_stats)
3406{
3407 struct mlx5e_priv *priv = netdev_priv(dev);
3408 struct mlx5_core_dev *mdev = priv->mdev;
3409
3410 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3411 vf_stats);
3412}
3413
1ad9a00a
PB		 3414static void mlx5e_add_vxlan_port(struct net_device *netdev,
3415 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3416{
3417 struct mlx5e_priv *priv = netdev_priv(netdev);
3418
974c3f30
AD		 3419 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3420 return;
3421
b3f63c3d
MF		 3422 if (!mlx5e_vxlan_allowed(priv->mdev))
3423 return;
3424
974c3f30 3425 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3426}
3427
1ad9a00a
PB		 3428static void mlx5e_del_vxlan_port(struct net_device *netdev,
3429 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3430{
3431 struct mlx5e_priv *priv = netdev_priv(netdev);
3432
974c3f30
AD		 3433 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3434 return;
3435
b3f63c3d
MF		 3436 if (!mlx5e_vxlan_allowed(priv->mdev))
3437 return;
3438
974c3f30 3439 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3440}
3441
3442static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3443 struct sk_buff *skb,
3444 netdev_features_t features)
3445{
3446 struct udphdr *udph;
3447 u16 proto;
3448 u16 port = 0;
3449
3450 switch (vlan_get_protocol(skb)) {
3451 case htons(ETH_P_IP):
3452 proto = ip_hdr(skb)->protocol;
3453 break;
3454 case htons(ETH_P_IPV6):
3455 proto = ipv6_hdr(skb)->nexthdr;
3456 break;
3457 default:
3458 goto out;
3459 }
3460
3461 if (proto == IPPROTO_UDP) {
3462 udph = udp_hdr(skb);
3463 port = be16_to_cpu(udph->dest);
3464 }
3465
3466 /* Verify if UDP port is being offloaded by HW */
3467 if (port && mlx5e_vxlan_lookup_port(priv, port))
3468 return features;
3469
3470out:
3471 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3472 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3473}
3474
3475static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3476 struct net_device *netdev,
3477 netdev_features_t features)
3478{
3479 struct mlx5e_priv *priv = netdev_priv(netdev);
3480
3481 features = vlan_features_check(skb, features);
3482 features = vxlan_features_check(skb, features);
3483
3484 /* Validate if the tunneled packet is being offloaded by HW */
3485 if (skb->encapsulation &&
3486 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3487 return mlx5e_vxlan_features_check(priv, skb, features);
3488
3489 return features;
3490}
3491
3947ca18
DJ		 3492static void mlx5e_tx_timeout(struct net_device *dev)
3493{
3494 struct mlx5e_priv *priv = netdev_priv(dev);
3495 bool sched_work = false;
3496 int i;
3497
3498 netdev_err(dev, "TX timeout detected\n");
3499
6a9764ef 3500 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
acc6c595 3501 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3947ca18 3502
2c1ccc99 3503 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3504 continue;
3505 sched_work = true;
c0f1147d 3506 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3947ca18
DJ		 3507 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3508 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3509 }
3510
3511 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3512 schedule_work(&priv->tx_timeout_work);
3513}
3514
86994156
RS		 3515static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3516{
3517 struct mlx5e_priv *priv = netdev_priv(netdev);
3518 struct bpf_prog *old_prog;
3519 int err = 0;
3520 bool reset, was_opened;
3521 int i;
3522
3523 mutex_lock(&priv->state_lock);
3524
3525 if ((netdev->features & NETIF_F_LRO) && prog) {
3526 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3527 err = -EINVAL;
3528 goto unlock;
3529 }
3530
3531 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3532 /* no need for full reset when exchanging programs */
6a9764ef 3533 reset = (!priv->channels.params.xdp_prog || !prog);
86994156
RS		 3534
3535 if (was_opened && reset)
3536 mlx5e_close_locked(netdev);
c54c0629
DB		 3537 if (was_opened && !reset) {
3538 /* num_channels is invariant here, so we can take the
3539 * batched reference right upfront.
3540 */
6a9764ef 3541 prog = bpf_prog_add(prog, priv->channels.num);
c54c0629
DB		 3542 if (IS_ERR(prog)) {
3543 err = PTR_ERR(prog);
3544 goto unlock;
3545 }
3546 }
86994156 3547
c54c0629
DB		 3548 /* exchange programs, extra prog reference we got from caller
3549 * as long as we don't fail from this point onwards.
3550 */
6a9764ef 3551 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
86994156
RS		 3552 if (old_prog)
3553 bpf_prog_put(old_prog);
3554
3555 if (reset) /* change RQ type according to priv->xdp_prog */
6a9764ef 3556 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
86994156
RS		 3557
3558 if (was_opened && reset)
3559 mlx5e_open_locked(netdev);
3560
3561 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3562 goto unlock;
3563
3564 /* exchanging programs w/o reset, we update ref counts on behalf
3565 * of the channels RQs here.
3566 */
ff9c852f
SM		 3567 for (i = 0; i < priv->channels.num; i++) {
3568 struct mlx5e_channel *c = priv->channels.c[i];
86994156 3569
c0f1147d 3570 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3571 napi_synchronize(&c->napi);
3572 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3573
3574 old_prog = xchg(&c->rq.xdp_prog, prog);
3575
c0f1147d 3576 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3577 /* napi_schedule in case we have missed anything */
3578 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3579 napi_schedule(&c->napi);
3580
3581 if (old_prog)
3582 bpf_prog_put(old_prog);
3583 }
3584
3585unlock:
3586 mutex_unlock(&priv->state_lock);
3587 return err;
3588}
3589
3590static bool mlx5e_xdp_attached(struct net_device *dev)
3591{
3592 struct mlx5e_priv *priv = netdev_priv(dev);
3593
6a9764ef 3594 return !!priv->channels.params.xdp_prog;
86994156
RS		 3595}
3596
3597static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3598{
3599 switch (xdp->command) {
3600 case XDP_SETUP_PROG:
3601 return mlx5e_xdp_set(dev, xdp->prog);
3602 case XDP_QUERY_PROG:
3603 xdp->prog_attached = mlx5e_xdp_attached(dev);
3604 return 0;
3605 default:
3606 return -EINVAL;
3607 }
3608}
3609
80378384
CO		 3610#ifdef CONFIG_NET_POLL_CONTROLLER
3611/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3612 * reenabling interrupts.
3613 */
3614static void mlx5e_netpoll(struct net_device *dev)
3615{
3616 struct mlx5e_priv *priv = netdev_priv(dev);
ff9c852f
SM		 3617 struct mlx5e_channels *chs = &priv->channels;
3618
80378384
CO		 3619 int i;
3620
ff9c852f
SM		 3621 for (i = 0; i < chs->num; i++)
3622 napi_schedule(&chs->c[i]->napi);
80378384
CO		 3623}
3624#endif
3625
b0eed40e 3626static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 3627 .ndo_open = mlx5e_open,
3628 .ndo_stop = mlx5e_close,
3629 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3630 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3631 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3632 .ndo_get_stats64 = mlx5e_get_stats,
3633 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3634 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3635 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3636 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3637 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 3638 .ndo_change_mtu = mlx5e_change_mtu,
3639 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3640 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 3641#ifdef CONFIG_RFS_ACCEL
3642 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3643#endif
3947ca18 3644 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3645 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3646#ifdef CONFIG_NET_POLL_CONTROLLER
3647 .ndo_poll_controller = mlx5e_netpoll,
3648#endif
b0eed40e
SM		 3649};
3650
3651static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3652 .ndo_open = mlx5e_open,
3653 .ndo_stop = mlx5e_close,
3654 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3655 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3656 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 3657 .ndo_get_stats64 = mlx5e_get_stats,
3658 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3659 .ndo_set_mac_address = mlx5e_set_mac,
3660 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3661 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3662 .ndo_set_features = mlx5e_set_features,
3663 .ndo_change_mtu = mlx5e_change_mtu,
3664 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 3665 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3666 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 3667 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 3668 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3669#ifdef CONFIG_RFS_ACCEL
3670 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3671#endif
b0eed40e
SM		 3672 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3673 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3674 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3675 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3676 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3677 .ndo_get_vf_config = mlx5e_get_vf_config,
3678 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3679 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 3680 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3681 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3682#ifdef CONFIG_NET_POLL_CONTROLLER
3683 .ndo_poll_controller = mlx5e_netpoll,
3684#endif
370bad0f
OG		 3685 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3686 .ndo_get_offload_stats = mlx5e_get_offload_stats,
f62b8bb8
AV		 3687};
3688
3689static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3690{
3691 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 3692 return -EOPNOTSUPP;
f62b8bb8
AV		 3693 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3694 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3695 !MLX5_CAP_ETH(mdev, csum_cap) ||
3696 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3697 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3698 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3699 MLX5_CAP_FLOWTABLE(mdev,
3700 flow_table_properties_nic_receive.max_ft_level)
3701 < 3) {
f62b8bb8
AV		 3702 mlx5_core_warn(mdev,
3703 "Not creating net device, some required device capabilities are missing\n");
9eb78923 3704 return -EOPNOTSUPP;
f62b8bb8 3705 }
66189961
TT		 3706 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3707 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 3708 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3709 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 3710
f62b8bb8
AV		 3711 return 0;
3712}
3713
58d52291
AS		 3714u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3715{
3716 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3717
3718 return bf_buf_size -
3719 sizeof(struct mlx5e_tx_wqe) +
3720 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3721}
3722
d8c9660d
TT		 3723void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3724 u32 *indirection_rqt, int len,
85082dba
TT		 3725 int num_channels)
3726{
d8c9660d
TT		 3727 int node = mdev->priv.numa_node;
3728 int node_num_of_cores;
85082dba
TT		 3729 int i;
3730
d8c9660d
TT		 3731 if (node == -1)
3732 node = first_online_node;
3733
3734 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3735
3736 if (node_num_of_cores)
3737 num_channels = min_t(int, num_channels, node_num_of_cores);
3738
85082dba
TT		 3739 for (i = 0; i < len; i++)
3740 indirection_rqt[i] = i % num_channels;
3741}
3742
b797a684
SM		 3743static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3744{
3745 enum pcie_link_width width;
3746 enum pci_bus_speed speed;
3747 int err = 0;
3748
3749 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3750 if (err)
3751 return err;
3752
3753 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3754 return -EINVAL;
3755
3756 switch (speed) {
3757 case PCIE_SPEED_2_5GT:
3758 *pci_bw = 2500 * width;
3759 break;
3760 case PCIE_SPEED_5_0GT:
3761 *pci_bw = 5000 * width;
3762 break;
3763 case PCIE_SPEED_8_0GT:
3764 *pci_bw = 8000 * width;
3765 break;
3766 default:
3767 return -EINVAL;
3768 }
3769
3770 return 0;
3771}
3772
3773static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3774{
3775 return (link_speed && pci_bw &&
3776 (pci_bw < 40000) && (pci_bw < link_speed));
3777}
3778
9908aa29
TT		 3779void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3780{
3781 params->rx_cq_period_mode = cq_period_mode;
3782
3783 params->rx_cq_moderation.pkts =
3784 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3785 params->rx_cq_moderation.usec =
3786 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3787
3788 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3789 params->rx_cq_moderation.usec =
3790 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
6a9764ef 3791
457fcd8a
SM		 3792 if (params->rx_am_enabled)
3793 params->rx_cq_moderation =
3794 mlx5e_am_get_def_profile(params->rx_cq_period_mode);
3795
6a9764ef
SM		 3796 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3797 params->rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29
TT		 3798}
3799
2b029556
SM		 3800u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3801{
3802 int i;
3803
3804 /* The supported periods are organized in ascending order */
3805 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3806 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3807 break;
3808
3809 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3810}
3811
8f493ffd
SM		 3812void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3813 struct mlx5e_params *params,
3814 u16 max_channels)
f62b8bb8 3815{
6a9764ef 3816 u8 cq_period_mode = 0;
b797a684
SM		 3817 u32 link_speed = 0;
3818 u32 pci_bw = 0;
2fc4bfb7 3819
6a9764ef
SM		 3820 params->num_channels = max_channels;
3821 params->num_tc = 1;
2b029556 3822
6a9764ef
SM		 3823 /* SQ */
3824 params->log_sq_size = is_kdump_kernel() ?
b4e029da
KH		 3825 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3826 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3827
b797a684 3828 /* set CQE compression */
6a9764ef 3829 params->rx_cqe_compress_def = false;
b797a684 3830 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
6a9764ef 3831 MLX5_CAP_GEN(mdev, vport_group_manager)) {
b797a684
SM		 3832 mlx5e_get_max_linkspeed(mdev, &link_speed);
3833 mlx5e_get_pci_bw(mdev, &pci_bw);
3834 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
6a9764ef
SM		 3835 link_speed, pci_bw);
3836 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
b797a684 3837 }
6a9764ef
SM		 3838 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
3839
3840 /* RQ */
3841 mlx5e_set_rq_params(mdev, params);
b797a684 3842
6a9764ef
SM		 3843 /* HW LRO */
3844 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3845 params->lro_en = true;
3846 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
b0d4660b 3847
6a9764ef
SM		 3848 /* CQ moderation params */
3849 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3850 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3851 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3852 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3853 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
9908aa29 3854
6a9764ef
SM		 3855 params->tx_cq_moderation.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3856 params->tx_cq_moderation.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
9908aa29 3857
6a9764ef
SM		 3858 /* TX inline */
3859 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3860 mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
3861 if (params->tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
a6f402e4 3862 !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
6a9764ef 3863 params->tx_min_inline_mode = MLX5_INLINE_MODE_L2;
a6f402e4 3864
6a9764ef
SM		 3865 /* RSS */
3866 params->rss_hfunc = ETH_RSS_HASH_XOR;
3867 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
3868 mlx5e_build_default_indir_rqt(mdev, params->indirection_rqt,
3869 MLX5E_INDIR_RQT_SIZE, max_channels);
3870}
f62b8bb8 3871
6a9764ef
SM		 3872static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3873 struct net_device *netdev,
3874 const struct mlx5e_profile *profile,
3875 void *ppriv)
3876{
3877 struct mlx5e_priv *priv = netdev_priv(netdev);
57afead5 3878
6a9764ef
SM		 3879 priv->mdev = mdev;
3880 priv->netdev = netdev;
3881 priv->profile = profile;
3882 priv->ppriv = ppriv;
2d75b2bc 3883
6a9764ef 3884 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
9908aa29 3885
f62b8bb8
AV		 3886 mutex_init(&priv->state_lock);
3887
3888 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3889 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3890 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3891 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3892}
3893
3894static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3895{
3896 struct mlx5e_priv *priv = netdev_priv(netdev);
3897
e1d7d349 3898 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3899 if (is_zero_ether_addr(netdev->dev_addr) &&
3900 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3901 eth_hw_addr_random(netdev);
3902 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3903 }
f62b8bb8
AV		 3904}
3905
cb67b832
HHZ		 3906static const struct switchdev_ops mlx5e_switchdev_ops = {
3907 .switchdev_port_attr_get = mlx5e_attr_get,
3908};
3909
6bfd390b 3910static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3911{
3912 struct mlx5e_priv *priv = netdev_priv(netdev);
3913 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3914 bool fcs_supported;
3915 bool fcs_enabled;
f62b8bb8
AV		 3916
3917 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3918
08fb1dac 3919 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3920 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac 3921#ifdef CONFIG_MLX5_CORE_EN_DCB
80653f73
HN		 3922 if (MLX5_CAP_GEN(mdev, qos))
3923 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac
SM		 3924#endif
3925 } else {
b0eed40e 3926 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3927 }
66e49ded 3928
f62b8bb8
AV		 3929 netdev->watchdog_timeo = 15 * HZ;
3930
3931 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3932
12be4b21 3933 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3934 netdev->vlan_features |= NETIF_F_IP_CSUM;
3935 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3936 netdev->vlan_features |= NETIF_F_GRO;
3937 netdev->vlan_features |= NETIF_F_TSO;
3938 netdev->vlan_features |= NETIF_F_TSO6;
3939 netdev->vlan_features |= NETIF_F_RXCSUM;
3940 netdev->vlan_features |= NETIF_F_RXHASH;
3941
3942 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3943 netdev->vlan_features |= NETIF_F_LRO;
3944
3945 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3946 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3947 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3948 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3949
b3f63c3d 3950 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3951 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3952 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3953 NETIF_F_GSO_PARTIAL;
b3f63c3d 3954 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3955 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3956 netdev->hw_enc_features |= NETIF_F_TSO;
3957 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3958 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3959 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3960 NETIF_F_GSO_PARTIAL;
3961 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3962 }
3963
94cb1ebb
EBE		 3964 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3965
3966 if (fcs_supported)
3967 netdev->hw_features |= NETIF_F_RXALL;
3968
102722fc
GE		 3969 if (MLX5_CAP_ETH(mdev, scatter_fcs))
3970 netdev->hw_features |= NETIF_F_RXFCS;
3971
f62b8bb8 3972 netdev->features = netdev->hw_features;
6a9764ef 3973 if (!priv->channels.params.lro_en)
f62b8bb8
AV		 3974 netdev->features &= ~NETIF_F_LRO;
3975
94cb1ebb
EBE		 3976 if (fcs_enabled)
3977 netdev->features &= ~NETIF_F_RXALL;
3978
102722fc
GE		 3979 if (!priv->channels.params.scatter_fcs_en)
3980 netdev->features &= ~NETIF_F_RXFCS;
3981
e8f887ac
AV		 3982#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3983 if (FT_CAP(flow_modify_en) &&
3984 FT_CAP(modify_root) &&
3985 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3986 FT_CAP(flow_table_modify)) {
3987 netdev->hw_features |= NETIF_F_HW_TC;
3988#ifdef CONFIG_RFS_ACCEL
3989 netdev->hw_features |= NETIF_F_NTUPLE;
3990#endif
3991 }
e8f887ac 3992
f62b8bb8
AV		 3993 netdev->features |= NETIF_F_HIGHDMA;
3994
3995 netdev->priv_flags |= IFF_UNICAST_FLT;
3996
3997 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 3998
3999#ifdef CONFIG_NET_SWITCHDEV
4000 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4001 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4002#endif
f62b8bb8
AV		 4003}
4004
593cf338
RS		 4005static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4006{
4007 struct mlx5_core_dev *mdev = priv->mdev;
4008 int err;
4009
4010 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4011 if (err) {
4012 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4013 priv->q_counter = 0;
4014 }
4015}
4016
4017static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4018{
4019 if (!priv->q_counter)
4020 return;
4021
4022 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4023}
4024
6bfd390b
HHZ		 4025static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4026 struct net_device *netdev,
127ea380
HHZ		 4027 const struct mlx5e_profile *profile,
4028 void *ppriv)
6bfd390b
HHZ		 4029{
4030 struct mlx5e_priv *priv = netdev_priv(netdev);
4031
127ea380 4032 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 4033 mlx5e_build_nic_netdev(netdev);
4034 mlx5e_vxlan_init(priv);
4035}
4036
4037static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4038{
4039 mlx5e_vxlan_cleanup(priv);
127ea380 4040
6a9764ef
SM		 4041 if (priv->channels.params.xdp_prog)
4042 bpf_prog_put(priv->channels.params.xdp_prog);
6bfd390b
HHZ		 4043}
4044
4045static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4046{
4047 struct mlx5_core_dev *mdev = priv->mdev;
4048 int err;
6bfd390b 4049
8f493ffd
SM		 4050 err = mlx5e_create_indirect_rqt(priv);
4051 if (err)
6bfd390b 4052 return err;
6bfd390b
HHZ		 4053
4054 err = mlx5e_create_direct_rqts(priv);
8f493ffd 4055 if (err)
6bfd390b 4056 goto err_destroy_indirect_rqts;
6bfd390b
HHZ		 4057
4058 err = mlx5e_create_indirect_tirs(priv);
8f493ffd 4059 if (err)
6bfd390b 4060 goto err_destroy_direct_rqts;
6bfd390b
HHZ		 4061
4062 err = mlx5e_create_direct_tirs(priv);
8f493ffd 4063 if (err)
6bfd390b 4064 goto err_destroy_indirect_tirs;
6bfd390b
HHZ		 4065
4066 err = mlx5e_create_flow_steering(priv);
4067 if (err) {
4068 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4069 goto err_destroy_direct_tirs;
4070 }
4071
4072 err = mlx5e_tc_init(priv);
4073 if (err)
4074 goto err_destroy_flow_steering;
4075
4076 return 0;
4077
4078err_destroy_flow_steering:
4079 mlx5e_destroy_flow_steering(priv);
4080err_destroy_direct_tirs:
4081 mlx5e_destroy_direct_tirs(priv);
4082err_destroy_indirect_tirs:
4083 mlx5e_destroy_indirect_tirs(priv);
4084err_destroy_direct_rqts:
8f493ffd 4085 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4086err_destroy_indirect_rqts:
4087 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4088 return err;
4089}
4090
4091static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4092{
6bfd390b
HHZ		 4093 mlx5e_tc_cleanup(priv);
4094 mlx5e_destroy_flow_steering(priv);
4095 mlx5e_destroy_direct_tirs(priv);
4096 mlx5e_destroy_indirect_tirs(priv);
8f493ffd 4097 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4098 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4099}
4100
4101static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4102{
4103 int err;
4104
4105 err = mlx5e_create_tises(priv);
4106 if (err) {
4107 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4108 return err;
4109 }
4110
4111#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 4112 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 4113#endif
4114 return 0;
4115}
4116
2c3b5bee
SM		 4117static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
4118{
4119 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4120 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4121 int vport;
4122 u8 mac[ETH_ALEN];
4123
4124 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
4125 return;
4126
4127 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
4128
4129 for (vport = 1; vport < total_vfs; vport++) {
4130 struct mlx5_eswitch_rep rep;
4131
4132 rep.load = mlx5e_vport_rep_load;
4133 rep.unload = mlx5e_vport_rep_unload;
4134 rep.vport = vport;
4135 ether_addr_copy(rep.hw_id, mac);
4136 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
4137 }
4138}
4139
4140static void mlx5e_unregister_vport_rep(struct mlx5_core_dev *mdev)
4141{
4142 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4143 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4144 int vport;
4145
4146 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
4147 return;
4148
4149 for (vport = 1; vport < total_vfs; vport++)
4150 mlx5_eswitch_unregister_vport_rep(esw, vport);
4151}
4152
6bfd390b
HHZ		 4153static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4154{
4155 struct net_device *netdev = priv->netdev;
4156 struct mlx5_core_dev *mdev = priv->mdev;
127ea380
HHZ		 4157 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4158 struct mlx5_eswitch_rep rep;
2c3b5bee
SM		 4159 u16 max_mtu;
4160
4161 mlx5e_init_l2_addr(priv);
4162
4163 /* MTU range: 68 - hw-specific max */
4164 netdev->min_mtu = ETH_MIN_MTU;
4165 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4166 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
4167 mlx5e_set_dev_port_mtu(priv);
6bfd390b 4168
7907f23a
AH		 4169 mlx5_lag_add(mdev, netdev);
4170
6bfd390b 4171 mlx5e_enable_async_events(priv);
127ea380
HHZ		 4172
4173 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
dbe413e3 4174 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
cb67b832
HHZ		 4175 rep.load = mlx5e_nic_rep_load;
4176 rep.unload = mlx5e_nic_rep_unload;
9deb2241 4177 rep.vport = FDB_UPLINK_VPORT;
726293f1 4178 rep.netdev = netdev;
9deb2241 4179 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
127ea380 4180 }
610e89e0 4181
2c3b5bee
SM		 4182 mlx5e_register_vport_rep(mdev);
4183
610e89e0
SM		 4184 if (netdev->reg_state != NETREG_REGISTERED)
4185 return;
4186
4187 /* Device already registered: sync netdev system state */
4188 if (mlx5e_vxlan_allowed(mdev)) {
4189 rtnl_lock();
4190 udp_tunnel_get_rx_info(netdev);
4191 rtnl_unlock();
4192 }
4193
4194 queue_work(priv->wq, &priv->set_rx_mode_work);
2c3b5bee
SM		 4195
4196 rtnl_lock();
4197 if (netif_running(netdev))
4198 mlx5e_open(netdev);
4199 netif_device_attach(netdev);
4200 rtnl_unlock();
6bfd390b
HHZ		 4201}
4202
4203static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4204{
3deef8ce
SM		 4205 struct mlx5_core_dev *mdev = priv->mdev;
4206 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4207
2c3b5bee
SM		 4208 rtnl_lock();
4209 if (netif_running(priv->netdev))
4210 mlx5e_close(priv->netdev);
4211 netif_device_detach(priv->netdev);
4212 rtnl_unlock();
4213
6bfd390b 4214 queue_work(priv->wq, &priv->set_rx_mode_work);
2c3b5bee 4215 mlx5e_unregister_vport_rep(mdev);
3deef8ce
SM		 4216 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4217 mlx5_eswitch_unregister_vport_rep(esw, 0);
6bfd390b 4218 mlx5e_disable_async_events(priv);
3deef8ce 4219 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 4220}
4221
4222static const struct mlx5e_profile mlx5e_nic_profile = {
4223 .init = mlx5e_nic_init,
4224 .cleanup = mlx5e_nic_cleanup,
4225 .init_rx = mlx5e_init_nic_rx,
4226 .cleanup_rx = mlx5e_cleanup_nic_rx,
4227 .init_tx = mlx5e_init_nic_tx,
4228 .cleanup_tx = mlx5e_cleanup_nic_tx,
4229 .enable = mlx5e_nic_enable,
4230 .disable = mlx5e_nic_disable,
4231 .update_stats = mlx5e_update_stats,
4232 .max_nch = mlx5e_get_max_num_channels,
4233 .max_tc = MLX5E_MAX_NUM_TC,
4234};
4235
2c3b5bee
SM		 4236/* mlx5e generic netdev management API (move to en_common.c) */
4237
26e59d80
MHY		 4238struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4239 const struct mlx5e_profile *profile,
4240 void *ppriv)
f62b8bb8 4241{
26e59d80 4242 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 4243 struct net_device *netdev;
4244 struct mlx5e_priv *priv;
f62b8bb8 4245
08fb1dac 4246 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 4247 nch * profile->max_tc,
08fb1dac 4248 nch);
f62b8bb8
AV		 4249 if (!netdev) {
4250 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4251 return NULL;
4252 }
4253
be4891af
SM		 4254#ifdef CONFIG_RFS_ACCEL
4255 netdev->rx_cpu_rmap = mdev->rmap;
4256#endif
4257
127ea380 4258 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 4259
4260 netif_carrier_off(netdev);
4261
4262 priv = netdev_priv(netdev);
4263
7bb29755
MF		 4264 priv->wq = create_singlethread_workqueue("mlx5e");
4265 if (!priv->wq)
26e59d80
MHY		 4266 goto err_cleanup_nic;
4267
4268 return netdev;
4269
4270err_cleanup_nic:
4271 profile->cleanup(priv);
4272 free_netdev(netdev);
4273
4274 return NULL;
4275}
4276
2c3b5bee 4277int mlx5e_attach_netdev(struct mlx5e_priv *priv)
26e59d80 4278{
2c3b5bee 4279 struct mlx5_core_dev *mdev = priv->mdev;
26e59d80 4280 const struct mlx5e_profile *profile;
26e59d80
MHY		 4281 int err;
4282
26e59d80
MHY		 4283 profile = priv->profile;
4284 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 4285
6bfd390b
HHZ		 4286 err = profile->init_tx(priv);
4287 if (err)
ec8b9981 4288 goto out;
5c50368f 4289
a43b25da 4290 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
5c50368f
AS		 4291 if (err) {
4292 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 4293 goto err_cleanup_tx;
5c50368f
AS		 4294 }
4295
6bfd390b
HHZ		 4296 err = profile->init_rx(priv);
4297 if (err)
5c50368f 4298 goto err_close_drop_rq;
5c50368f 4299
593cf338
RS		 4300 mlx5e_create_q_counter(priv);
4301
6bfd390b
HHZ		 4302 if (profile->enable)
4303 profile->enable(priv);
f62b8bb8 4304
26e59d80 4305 return 0;
5c50368f
AS		 4306
4307err_close_drop_rq:
a43b25da 4308 mlx5e_close_drop_rq(&priv->drop_rq);
5c50368f 4309
6bfd390b
HHZ		 4310err_cleanup_tx:
4311 profile->cleanup_tx(priv);
5c50368f 4312
26e59d80
MHY		 4313out:
4314 return err;
f62b8bb8
AV		 4315}
4316
2c3b5bee 4317void mlx5e_detach_netdev(struct mlx5e_priv *priv)
26e59d80 4318{
26e59d80
MHY		 4319 const struct mlx5e_profile *profile = priv->profile;
4320
4321 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80 4322
37f304d1
SM		 4323 if (profile->disable)
4324 profile->disable(priv);
4325 flush_workqueue(priv->wq);
4326
26e59d80
MHY		 4327 mlx5e_destroy_q_counter(priv);
4328 profile->cleanup_rx(priv);
a43b25da 4329 mlx5e_close_drop_rq(&priv->drop_rq);
26e59d80 4330 profile->cleanup_tx(priv);
26e59d80
MHY		 4331 cancel_delayed_work_sync(&priv->update_stats_work);
4332}
4333
2c3b5bee
SM		 4334void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4335{
4336 const struct mlx5e_profile *profile = priv->profile;
4337 struct net_device *netdev = priv->netdev;
4338
4339 destroy_workqueue(priv->wq);
4340 if (profile->cleanup)
4341 profile->cleanup(priv);
4342 free_netdev(netdev);
4343}
4344
26e59d80
MHY		 4345/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4346 * hardware contexts and to connect it to the current netdev.
4347 */
4348static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4349{
4350 struct mlx5e_priv *priv = vpriv;
4351 struct net_device *netdev = priv->netdev;
4352 int err;
4353
4354 if (netif_device_present(netdev))
4355 return 0;
4356
4357 err = mlx5e_create_mdev_resources(mdev);
4358 if (err)
4359 return err;
4360
2c3b5bee 4361 err = mlx5e_attach_netdev(priv);
26e59d80
MHY		 4362 if (err) {
4363 mlx5e_destroy_mdev_resources(mdev);
4364 return err;
4365 }
4366
4367 return 0;
4368}
4369
4370static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4371{
4372 struct mlx5e_priv *priv = vpriv;
4373 struct net_device *netdev = priv->netdev;
4374
4375 if (!netif_device_present(netdev))
4376 return;
4377
2c3b5bee 4378 mlx5e_detach_netdev(priv);
26e59d80
MHY		 4379 mlx5e_destroy_mdev_resources(mdev);
4380}
4381
b50d292b
HHZ		 4382static void *mlx5e_add(struct mlx5_core_dev *mdev)
4383{
127ea380 4384 struct mlx5_eswitch *esw = mdev->priv.eswitch;
26e59d80 4385 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
127ea380 4386 void *ppriv = NULL;
26e59d80
MHY		 4387 void *priv;
4388 int vport;
4389 int err;
4390 struct net_device *netdev;
b50d292b 4391
26e59d80
MHY		 4392 err = mlx5e_check_required_hca_cap(mdev);
4393 if (err)
b50d292b
HHZ		 4394 return NULL;
4395
127ea380
HHZ		 4396 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4397 ppriv = &esw->offloads.vport_reps[0];
4398
26e59d80
MHY		 4399 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4400 if (!netdev) {
4401 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4402 goto err_unregister_reps;
4403 }
4404
4405 priv = netdev_priv(netdev);
4406
4407 err = mlx5e_attach(mdev, priv);
4408 if (err) {
4409 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4410 goto err_destroy_netdev;
4411 }
4412
4413 err = register_netdev(netdev);
4414 if (err) {
4415 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4416 goto err_detach;
b50d292b 4417 }
26e59d80
MHY		 4418
4419 return priv;
4420
4421err_detach:
4422 mlx5e_detach(mdev, priv);
4423
4424err_destroy_netdev:
2c3b5bee 4425 mlx5e_destroy_netdev(priv);
26e59d80
MHY		 4426
4427err_unregister_reps:
4428 for (vport = 1; vport < total_vfs; vport++)
4429 mlx5_eswitch_unregister_vport_rep(esw, vport);
4430
4431 return NULL;
b50d292b
HHZ		 4432}
4433
b50d292b
HHZ		 4434static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4435{
4436 struct mlx5e_priv *priv = vpriv;
127ea380 4437
5e1e93c7 4438 unregister_netdev(priv->netdev);
26e59d80 4439 mlx5e_detach(mdev, vpriv);
2c3b5bee 4440 mlx5e_destroy_netdev(priv);
b50d292b
HHZ		 4441}
4442
f62b8bb8
AV		 4443static void *mlx5e_get_netdev(void *vpriv)
4444{
4445 struct mlx5e_priv *priv = vpriv;
4446
4447 return priv->netdev;
4448}
4449
4450static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4451 .add = mlx5e_add,
4452 .remove = mlx5e_remove,
26e59d80
MHY		 4453 .attach = mlx5e_attach,
4454 .detach = mlx5e_detach,
f62b8bb8
AV		 4455 .event = mlx5e_async_event,
4456 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4457 .get_dev = mlx5e_get_netdev,
4458};
4459
4460void mlx5e_init(void)
4461{
665bc539 4462 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4463 mlx5_register_interface(&mlx5e_interface);
4464}
4465
4466void mlx5e_cleanup(void)
4467{
4468 mlx5_unregister_interface(&mlx5e_interface);
4469}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git