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net/mlx5: E-Switch, Provide flow dest when creating vport rx rule
[thirdparty/kernel/stable.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
60bbf7ee 38#include <net/page_pool.h>
1d447a39 39#include "eswitch.h"
f62b8bb8 40#include "en.h"
e8f887ac 41#include "en_tc.h"
1d447a39 42#include "en_rep.h"
547eede0 43#include "en_accel/ipsec.h"
899a59d3 44#include "en_accel/ipsec_rxtx.h"
c83294b9 45#include "en_accel/tls.h"
899a59d3 46#include "accel/ipsec.h"
c83294b9 47#include "accel/tls.h"
358aa5ce 48#include "lib/vxlan.h"
6dbc80ca 49#include "lib/clock.h"
2c81bfd5 50#include "en/port.h"
159d2131 51#include "en/xdp.h"
f62b8bb8
AV		 52
53struct mlx5e_rq_param {
cb3c7fd4
GR		 54 u32 rqc[MLX5_ST_SZ_DW(rqc)];
55 struct mlx5_wq_param wq;
069d1146 56 struct mlx5e_rq_frags_info frags_info;
f62b8bb8
AV		 57};
58
59struct mlx5e_sq_param {
60 u32 sqc[MLX5_ST_SZ_DW(sqc)];
61 struct mlx5_wq_param wq;
62};
63
64struct mlx5e_cq_param {
65 u32 cqc[MLX5_ST_SZ_DW(cqc)];
66 struct mlx5_wq_param wq;
67 u16 eq_ix;
9908aa29 68 u8 cq_period_mode;
f62b8bb8
AV		 69};
70
71struct mlx5e_channel_param {
72 struct mlx5e_rq_param rq;
73 struct mlx5e_sq_param sq;
b5503b99 74 struct mlx5e_sq_param xdp_sq;
d3c9bc27 75 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 76 struct mlx5e_cq_param rx_cq;
77 struct mlx5e_cq_param tx_cq;
d3c9bc27 78 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 79};
80
2ccb0a79 81bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2fc4bfb7 82{
ea3886ca 83 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
2fc4bfb7
SM		 84 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
85 MLX5_CAP_ETH(mdev, reg_umr_sq);
ea3886ca
TT		 86 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
87 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
88
89 if (!striding_rq_umr)
90 return false;
91 if (!inline_umr) {
92 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
93 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
94 return false;
95 }
96 return true;
2fc4bfb7
SM		 97}
98
069d1146 99static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
73281b78 100{
a26a5bdf
TT		 101 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
102 u16 linear_rq_headroom = params->xdp_prog ?
103 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
104 u32 frag_sz;
73281b78 105
a26a5bdf 106 linear_rq_headroom += NET_IP_ALIGN;
619a8f2a 107
a26a5bdf
TT		 108 frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu);
109
110 if (params->xdp_prog && frag_sz < PAGE_SIZE)
111 frag_sz = PAGE_SIZE;
112
113 return frag_sz;
73281b78
TT		 114}
115
116static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
117{
069d1146 118 u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
73281b78
TT		 119
120 return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
121}
122
069d1146
TT		 123static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
124 struct mlx5e_params *params)
125{
126 u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
127
128 return !params->lro_en && frag_sz <= PAGE_SIZE;
129}
130
619a8f2a
TT		 131static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
132 struct mlx5e_params *params)
133{
069d1146 134 u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
619a8f2a
TT		 135 s8 signed_log_num_strides_param;
136 u8 log_num_strides;
137
069d1146 138 if (!mlx5e_rx_is_linear_skb(mdev, params))
619a8f2a
TT		 139 return false;
140
141 if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
142 return true;
143
144 log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
145 signed_log_num_strides_param =
146 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
147
148 return signed_log_num_strides_param >= 0;
149}
150
73281b78
TT		 151static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
152{
153 if (params->log_rq_mtu_frames <
154 mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
155 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
156
157 return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
158}
159
160static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
161 struct mlx5e_params *params)
f1e4fc9b 162{
619a8f2a 163 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
069d1146 164 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
619a8f2a 165
f1e4fc9b
TT		 166 return MLX5E_MPWQE_STRIDE_SZ(mdev,
167 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
168}
169
73281b78
TT		 170static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
171 struct mlx5e_params *params)
f1e4fc9b
TT		 172{
173 return MLX5_MPWRQ_LOG_WQE_SZ -
174 mlx5e_mpwqe_get_log_stride_size(mdev, params);
175}
176
619a8f2a
TT		 177static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
178 struct mlx5e_params *params)
b0cedc84
TT		 179{
180 u16 linear_rq_headroom = params->xdp_prog ?
181 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
069d1146 182 bool is_linear_skb;
b0cedc84
TT		 183
184 linear_rq_headroom += NET_IP_ALIGN;
185
069d1146
TT		 186 is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
187 mlx5e_rx_is_linear_skb(mdev, params) :
188 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
b0cedc84 189
069d1146 190 return is_linear_skb ? linear_rq_headroom : 0;
b0cedc84
TT		 191}
192
696a97cf 193void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
2a0f561b 194 struct mlx5e_params *params)
2fc4bfb7 195{
6a9764ef 196 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
73281b78
TT		 197 params->log_rq_mtu_frames = is_kdump_kernel() ?
198 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
199 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2fc4bfb7 200
6a9764ef
SM		 201 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
202 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
619a8f2a
TT		 203 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
204 BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
73281b78 205 BIT(params->log_rq_mtu_frames),
f1e4fc9b 206 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
6a9764ef 207 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 208}
209
2ccb0a79
TT		 210bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
211 struct mlx5e_params *params)
212{
213 return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
22f45398
TT		 214 !MLX5_IPSEC_DEV(mdev) &&
215 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
2ccb0a79 216}
291f445e 217
2ccb0a79 218void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
2fc4bfb7 219{
2ccb0a79
TT		 220 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
221 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
291f445e 222 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
99cbfa93 223 MLX5_WQ_TYPE_CYCLIC;
2fc4bfb7
SM		 224}
225
f62b8bb8
AV		 226static void mlx5e_update_carrier(struct mlx5e_priv *priv)
227{
228 struct mlx5_core_dev *mdev = priv->mdev;
229 u8 port_state;
230
231 port_state = mlx5_query_vport_state(mdev,
cc9c82a8 232 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
e53eef63 233 0);
f62b8bb8 234
87424ad5
SD		 235 if (port_state == VPORT_STATE_UP) {
236 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 237 netif_carrier_on(priv->netdev);
87424ad5
SD		 238 } else {
239 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 240 netif_carrier_off(priv->netdev);
87424ad5 241 }
f62b8bb8
AV		 242}
243
244static void mlx5e_update_carrier_work(struct work_struct *work)
245{
246 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
247 update_carrier_work);
248
249 mutex_lock(&priv->state_lock);
250 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
7ca42c80
ES		 251 if (priv->profile->update_carrier)
252 priv->profile->update_carrier(priv);
f62b8bb8
AV		 253 mutex_unlock(&priv->state_lock);
254}
255
19386177 256void mlx5e_update_stats(struct mlx5e_priv *priv)
f62b8bb8 257{
19386177 258 int i;
f62b8bb8 259
19386177
KH		 260 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
261 if (mlx5e_stats_grps[i].update_stats)
262 mlx5e_stats_grps[i].update_stats(priv);
f62b8bb8
AV		 263}
264
3834a5e6
GP		 265static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
266{
19386177
KH		 267 int i;
268
269 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
270 if (mlx5e_stats_grps[i].update_stats_mask &
271 MLX5E_NDO_UPDATE_STATS)
272 mlx5e_stats_grps[i].update_stats(priv);
3834a5e6
GP		 273}
274
cb67b832 275void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 276{
277 struct delayed_work *dwork = to_delayed_work(work);
278 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
279 update_stats_work);
ed56c519 280
f62b8bb8 281 mutex_lock(&priv->state_lock);
ed56c519 282 priv->profile->update_stats(priv);
f62b8bb8
AV		 283 mutex_unlock(&priv->state_lock);
284}
285
daa21560
TT		 286static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
287 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 288{
daa21560
TT		 289 struct mlx5e_priv *priv = vpriv;
290
e0f46eb9 291 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 292 return;
293
f62b8bb8
AV		 294 switch (event) {
295 case MLX5_DEV_EVENT_PORT_UP:
296 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 297 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 298 break;
f62b8bb8
AV		 299 default:
300 break;
301 }
302}
303
f62b8bb8
AV		 304static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
305{
e0f46eb9 306 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 307}
308
309static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
310{
e0f46eb9 311 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
78249c42 312 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 313}
314
31391048
SM		 315static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
316 struct mlx5e_icosq *sq,
b8a98a4c 317 struct mlx5e_umr_wqe *wqe)
7e426671
TT		 318{
319 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
320 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
ea3886ca 321 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
7e426671
TT		 322
323 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
324 ds_cnt);
325 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
326 cseg->imm = rq->mkey_be;
327
ea3886ca 328 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
31616255 329 ucseg->xlt_octowords =
7e426671 330 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
7e426671 331 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
7e426671
TT		 332}
333
422d4c40
TT		 334static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
335{
336 switch (rq->wq_type) {
337 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
338 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
339 default:
99cbfa93 340 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
422d4c40
TT		 341 }
342}
343
344static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
345{
346 switch (rq->wq_type) {
347 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
348 return rq->mpwqe.wq.cur_sz;
349 default:
350 return rq->wqe.wq.cur_sz;
351 }
352}
353
7e426671
TT		 354static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
355 struct mlx5e_channel *c)
356{
422d4c40 357 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
7e426671 358
eec4edc9
KC		 359 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
360 sizeof(*rq->mpwqe.info)),
ca11b798 361 GFP_KERNEL, cpu_to_node(c->cpu));
21c59685 362 if (!rq->mpwqe.info)
ea3886ca 363 return -ENOMEM;
7e426671 364
b8a98a4c 365 mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
7e426671
TT		 366
367 return 0;
7e426671
TT		 368}
369
a43b25da 370static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
ec8b9981
TT		 371 u64 npages, u8 page_shift,
372 struct mlx5_core_mkey *umr_mkey)
3608ae77 373{
3608ae77
TT		 374 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
375 void *mkc;
376 u32 *in;
377 int err;
378
1b9a07ee 379 in = kvzalloc(inlen, GFP_KERNEL);
3608ae77
TT		 380 if (!in)
381 return -ENOMEM;
382
383 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
384
3608ae77
TT		 385 MLX5_SET(mkc, mkc, free, 1);
386 MLX5_SET(mkc, mkc, umr_en, 1);
387 MLX5_SET(mkc, mkc, lw, 1);
388 MLX5_SET(mkc, mkc, lr, 1);
cdbd0d2b 389 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
3608ae77
TT		 390
391 MLX5_SET(mkc, mkc, qpn, 0xffffff);
392 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 393 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 394 MLX5_SET(mkc, mkc, translations_octword_size,
395 MLX5_MTT_OCTW(npages));
ec8b9981 396 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 397
ec8b9981 398 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 399
400 kvfree(in);
401 return err;
402}
403
a43b25da 404static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
ec8b9981 405{
422d4c40 406 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
ec8b9981 407
a43b25da 408 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
ec8b9981
TT		 409}
410
b8a98a4c
TT		 411static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
412{
413 return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
414}
415
069d1146
TT		 416static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
417{
418 struct mlx5e_wqe_frag_info next_frag, *prev;
419 int i;
420
421 next_frag.di = &rq->wqe.di[0];
422 next_frag.offset = 0;
423 prev = NULL;
424
425 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
426 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
427 struct mlx5e_wqe_frag_info *frag =
428 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
429 int f;
430
431 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
432 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
433 next_frag.di++;
434 next_frag.offset = 0;
435 if (prev)
436 prev->last_in_page = true;
437 }
438 *frag = next_frag;
439
440 /* prepare next */
441 next_frag.offset += frag_info[f].frag_stride;
442 prev = frag;
443 }
444 }
445
446 if (prev)
447 prev->last_in_page = true;
448}
449
450static int mlx5e_init_di_list(struct mlx5e_rq *rq,
451 struct mlx5e_params *params,
452 int wq_sz, int cpu)
453{
454 int len = wq_sz << rq->wqe.info.log_num_frags;
455
84ca176b 456 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
069d1146
TT		 457 GFP_KERNEL, cpu_to_node(cpu));
458 if (!rq->wqe.di)
459 return -ENOMEM;
460
461 mlx5e_init_frags_partition(rq);
462
463 return 0;
464}
465
466static void mlx5e_free_di_list(struct mlx5e_rq *rq)
467{
468 kvfree(rq->wqe.di);
469}
470
3b77235b 471static int mlx5e_alloc_rq(struct mlx5e_channel *c,
6a9764ef
SM		 472 struct mlx5e_params *params,
473 struct mlx5e_rq_param *rqp,
3b77235b 474 struct mlx5e_rq *rq)
f62b8bb8 475{
60bbf7ee 476 struct page_pool_params pp_params = { 0 };
a43b25da 477 struct mlx5_core_dev *mdev = c->mdev;
6a9764ef 478 void *rqc = rqp->rqc;
f62b8bb8 479 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
069d1146 480 u32 pool_size;
f62b8bb8
AV		 481 int wq_sz;
482 int err;
483 int i;
484
231243c8 485 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
311c7c71 486
6a9764ef 487 rq->wq_type = params->rq_wq_type;
7e426671
TT		 488 rq->pdev = c->pdev;
489 rq->netdev = c->netdev;
a43b25da 490 rq->tstamp = c->tstamp;
7c39afb3 491 rq->clock = &mdev->clock;
7e426671
TT		 492 rq->channel = c;
493 rq->ix = c->ix;
a43b25da 494 rq->mdev = mdev;
05909bab 495 rq->stats = &c->priv->channel_stats[c->ix].rq;
97bc402d 496
6a9764ef 497 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
97bc402d
DB		 498 if (IS_ERR(rq->xdp_prog)) {
499 err = PTR_ERR(rq->xdp_prog);
500 rq->xdp_prog = NULL;
501 goto err_rq_wq_destroy;
502 }
7e426671 503
e213f5b6
WY		 504 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
505 if (err < 0)
0ddf5432
JDB		 506 goto err_rq_wq_destroy;
507
bce2b2bf 508 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
619a8f2a 509 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
60bbf7ee 510 pool_size = 1 << params->log_rq_mtu_frames;
b5503b99 511
6a9764ef 512 switch (rq->wq_type) {
461017cb 513 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
422d4c40
TT		 514 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
515 &rq->wq_ctrl);
516 if (err)
517 return err;
518
519 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
520
521 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
60bbf7ee
JDB		 522
523 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
422d4c40 524
7cc6d77b 525 rq->post_wqes = mlx5e_post_rx_mpwqes;
6cd392a0 526 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 527
20fd0c19 528 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
899a59d3
IT		 529#ifdef CONFIG_MLX5_EN_IPSEC
530 if (MLX5_IPSEC_DEV(mdev)) {
531 err = -EINVAL;
532 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
533 goto err_rq_wq_destroy;
534 }
535#endif
20fd0c19
SM		 536 if (!rq->handle_rx_cqe) {
537 err = -EINVAL;
538 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
539 goto err_rq_wq_destroy;
540 }
541
619a8f2a
TT		 542 rq->mpwqe.skb_from_cqe_mpwrq =
543 mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
544 mlx5e_skb_from_cqe_mpwrq_linear :
545 mlx5e_skb_from_cqe_mpwrq_nonlinear;
f1e4fc9b
TT		 546 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
547 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
1bfecfca 548
a43b25da 549 err = mlx5e_create_rq_umr_mkey(mdev, rq);
7e426671
TT		 550 if (err)
551 goto err_rq_wq_destroy;
ec8b9981
TT		 552 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
553
554 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
555 if (err)
069d1146 556 goto err_free;
461017cb 557 break;
99cbfa93
TT		 558 default: /* MLX5_WQ_TYPE_CYCLIC */
559 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
560 &rq->wq_ctrl);
422d4c40
TT		 561 if (err)
562 return err;
563
564 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
565
99cbfa93 566 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
422d4c40 567
069d1146
TT		 568 rq->wqe.info = rqp->frags_info;
569 rq->wqe.frags =
84ca176b
KC		 570 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
571 (wq_sz << rq->wqe.info.log_num_frags)),
069d1146 572 GFP_KERNEL, cpu_to_node(c->cpu));
47a6ca3f
WY		 573 if (!rq->wqe.frags) {
574 err = -ENOMEM;
069d1146 575 goto err_free;
47a6ca3f 576 }
069d1146
TT		 577
578 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
579 if (err)
580 goto err_free;
7cc6d77b 581 rq->post_wqes = mlx5e_post_rx_wqes;
6cd392a0 582 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 583
899a59d3
IT		 584#ifdef CONFIG_MLX5_EN_IPSEC
585 if (c->priv->ipsec)
586 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
587 else
588#endif
589 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
20fd0c19 590 if (!rq->handle_rx_cqe) {
20fd0c19
SM		 591 err = -EINVAL;
592 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
069d1146 593 goto err_free;
20fd0c19
SM		 594 }
595
069d1146
TT		 596 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
597 mlx5e_skb_from_cqe_linear :
598 mlx5e_skb_from_cqe_nonlinear;
7e426671 599 rq->mkey_be = c->mkey_be;
461017cb 600 }
f62b8bb8 601
60bbf7ee 602 /* Create a page_pool and register it with rxq */
069d1146 603 pp_params.order = 0;
60bbf7ee
JDB		 604 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
605 pp_params.pool_size = pool_size;
606 pp_params.nid = cpu_to_node(c->cpu);
607 pp_params.dev = c->pdev;
608 pp_params.dma_dir = rq->buff.map_dir;
609
610 /* page_pool can be used even when there is no rq->xdp_prog,
611 * given page_pool does not handle DMA mapping there is no
612 * required state to clear. And page_pool gracefully handle
613 * elevated refcnt.
614 */
615 rq->page_pool = page_pool_create(&pp_params);
616 if (IS_ERR(rq->page_pool)) {
60bbf7ee
JDB		 617 err = PTR_ERR(rq->page_pool);
618 rq->page_pool = NULL;
069d1146 619 goto err_free;
84f5e3fb 620 }
60bbf7ee
JDB		 621 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
622 MEM_TYPE_PAGE_POOL, rq->page_pool);
623 if (err)
069d1146 624 goto err_free;
84f5e3fb 625
f62b8bb8 626 for (i = 0; i < wq_sz; i++) {
4c2af5cc 627 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
99cbfa93 628 struct mlx5e_rx_wqe_ll *wqe =
422d4c40 629 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
069d1146
TT		 630 u32 byte_count =
631 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
b8a98a4c 632 u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
4c2af5cc 633
99cbfa93
TT		 634 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
635 wqe->data[0].byte_count = cpu_to_be32(byte_count);
636 wqe->data[0].lkey = rq->mkey_be;
422d4c40 637 } else {
99cbfa93
TT		 638 struct mlx5e_rx_wqe_cyc *wqe =
639 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
069d1146
TT		 640 int f;
641
642 for (f = 0; f < rq->wqe.info.num_frags; f++) {
643 u32 frag_size = rq->wqe.info.arr[f].frag_size |
644 MLX5_HW_START_PADDING;
645
646 wqe->data[f].byte_count = cpu_to_be32(frag_size);
647 wqe->data[f].lkey = rq->mkey_be;
648 }
649 /* check if num_frags is not a pow of two */
650 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
651 wqe->data[f].byte_count = 0;
652 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
653 wqe->data[f].addr = 0;
654 }
422d4c40 655 }
f62b8bb8
AV		 656 }
657
9a317425
AG		 658 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
659
660 switch (params->rx_cq_moderation.cq_period_mode) {
661 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
662 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
663 break;
664 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
665 default:
666 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
667 }
668
4415a031
TT		 669 rq->page_cache.head = 0;
670 rq->page_cache.tail = 0;
671
f62b8bb8
AV		 672 return 0;
673
069d1146
TT		 674err_free:
675 switch (rq->wq_type) {
676 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
ca11b798 677 kvfree(rq->mpwqe.info);
069d1146
TT		 678 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
679 break;
680 default: /* MLX5_WQ_TYPE_CYCLIC */
681 kvfree(rq->wqe.frags);
682 mlx5e_free_di_list(rq);
683 }
ec8b9981 684
f62b8bb8 685err_rq_wq_destroy:
97bc402d
DB		 686 if (rq->xdp_prog)
687 bpf_prog_put(rq->xdp_prog);
0ddf5432 688 xdp_rxq_info_unreg(&rq->xdp_rxq);
60bbf7ee
JDB		 689 if (rq->page_pool)
690 page_pool_destroy(rq->page_pool);
f62b8bb8
AV		 691 mlx5_wq_destroy(&rq->wq_ctrl);
692
693 return err;
694}
695
3b77235b 696static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 697{
4415a031
TT		 698 int i;
699
86994156
RS		 700 if (rq->xdp_prog)
701 bpf_prog_put(rq->xdp_prog);
702
0ddf5432 703 xdp_rxq_info_unreg(&rq->xdp_rxq);
60bbf7ee
JDB		 704 if (rq->page_pool)
705 page_pool_destroy(rq->page_pool);
0ddf5432 706
461017cb
TT		 707 switch (rq->wq_type) {
708 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
ca11b798 709 kvfree(rq->mpwqe.info);
a43b25da 710 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
461017cb 711 break;
99cbfa93 712 default: /* MLX5_WQ_TYPE_CYCLIC */
069d1146
TT		 713 kvfree(rq->wqe.frags);
714 mlx5e_free_di_list(rq);
461017cb
TT		 715 }
716
4415a031
TT		 717 for (i = rq->page_cache.head; i != rq->page_cache.tail;
718 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
719 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
720
721 mlx5e_page_release(rq, dma_info, false);
722 }
f62b8bb8
AV		 723 mlx5_wq_destroy(&rq->wq_ctrl);
724}
725
6a9764ef
SM		 726static int mlx5e_create_rq(struct mlx5e_rq *rq,
727 struct mlx5e_rq_param *param)
f62b8bb8 728{
a43b25da 729 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 730
731 void *in;
732 void *rqc;
733 void *wq;
734 int inlen;
735 int err;
736
737 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
738 sizeof(u64) * rq->wq_ctrl.buf.npages;
1b9a07ee 739 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 740 if (!in)
741 return -ENOMEM;
742
743 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
744 wq = MLX5_ADDR_OF(rqc, rqc, wq);
745
746 memcpy(rqc, param->rqc, sizeof(param->rqc));
747
97de9f31 748 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 749 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
f62b8bb8 750 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 751 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 752 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
753
3a2f7033
TT		 754 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
755 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 756
7db22ffb 757 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 758
759 kvfree(in);
760
761 return err;
762}
763
36350114
GP		 764static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
765 int next_state)
f62b8bb8 766{
7cbaf9a3 767 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 768
769 void *in;
770 void *rqc;
771 int inlen;
772 int err;
773
774 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 775 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 776 if (!in)
777 return -ENOMEM;
778
779 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
780
781 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
782 MLX5_SET(rqc, rqc, state, next_state);
783
7db22ffb 784 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 785
786 kvfree(in);
787
788 return err;
789}
790
102722fc
GE		 791static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
792{
793 struct mlx5e_channel *c = rq->channel;
794 struct mlx5e_priv *priv = c->priv;
795 struct mlx5_core_dev *mdev = priv->mdev;
796
797 void *in;
798 void *rqc;
799 int inlen;
800 int err;
801
802 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 803 in = kvzalloc(inlen, GFP_KERNEL);
102722fc
GE		 804 if (!in)
805 return -ENOMEM;
806
807 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
808
809 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
810 MLX5_SET64(modify_rq_in, in, modify_bitmask,
811 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
812 MLX5_SET(rqc, rqc, scatter_fcs, enable);
813 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
814
815 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
816
817 kvfree(in);
818
819 return err;
820}
821
36350114
GP		 822static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
823{
824 struct mlx5e_channel *c = rq->channel;
a43b25da 825 struct mlx5_core_dev *mdev = c->mdev;
36350114
GP		 826 void *in;
827 void *rqc;
828 int inlen;
829 int err;
830
831 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 832 in = kvzalloc(inlen, GFP_KERNEL);
36350114
GP		 833 if (!in)
834 return -ENOMEM;
835
836 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
837
838 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 839 MLX5_SET64(modify_rq_in, in, modify_bitmask,
840 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 841 MLX5_SET(rqc, rqc, vsd, vsd);
842 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
843
844 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
845
846 kvfree(in);
847
848 return err;
849}
850
3b77235b 851static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 852{
a43b25da 853 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
f62b8bb8
AV		 854}
855
1e7477ae 856static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
f62b8bb8 857{
1e7477ae 858 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
f62b8bb8 859 struct mlx5e_channel *c = rq->channel;
a43b25da 860
422d4c40 861 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
f62b8bb8 862
1e7477ae 863 do {
422d4c40 864 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
f62b8bb8
AV		 865 return 0;
866
867 msleep(20);
1e7477ae
EBE		 868 } while (time_before(jiffies, exp_time));
869
870 netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
422d4c40 871 c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
f62b8bb8
AV		 872
873 return -ETIMEDOUT;
874}
875
f2fde18c
SM		 876static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
877{
f2fde18c
SM		 878 __be16 wqe_ix_be;
879 u16 wqe_ix;
880
422d4c40
TT		 881 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
882 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
883
99cbfa93 884 /* UMR WQE (if in progress) is always at wq->head */
422d4c40 885 if (rq->mpwqe.umr_in_progress)
afab995e 886 rq->dealloc_wqe(rq, wq->head);
422d4c40
TT		 887
888 while (!mlx5_wq_ll_is_empty(wq)) {
99cbfa93 889 struct mlx5e_rx_wqe_ll *wqe;
422d4c40
TT		 890
891 wqe_ix_be = *wq->tail_next;
892 wqe_ix = be16_to_cpu(wqe_ix_be);
893 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
894 rq->dealloc_wqe(rq, wqe_ix);
895 mlx5_wq_ll_pop(wq, wqe_ix_be,
896 &wqe->next.next_wqe_index);
897 }
898 } else {
99cbfa93 899 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
422d4c40 900
99cbfa93
TT		 901 while (!mlx5_wq_cyc_is_empty(wq)) {
902 wqe_ix = mlx5_wq_cyc_get_tail(wq);
422d4c40 903 rq->dealloc_wqe(rq, wqe_ix);
99cbfa93 904 mlx5_wq_cyc_pop(wq);
422d4c40 905 }
accd5883 906 }
069d1146 907
f2fde18c
SM		 908}
909
f62b8bb8 910static int mlx5e_open_rq(struct mlx5e_channel *c,
6a9764ef 911 struct mlx5e_params *params,
f62b8bb8
AV		 912 struct mlx5e_rq_param *param,
913 struct mlx5e_rq *rq)
914{
915 int err;
916
6a9764ef 917 err = mlx5e_alloc_rq(c, params, param, rq);
f62b8bb8
AV		 918 if (err)
919 return err;
920
3b77235b 921 err = mlx5e_create_rq(rq, param);
f62b8bb8 922 if (err)
3b77235b 923 goto err_free_rq;
f62b8bb8 924
36350114 925 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 926 if (err)
3b77235b 927 goto err_destroy_rq;
f62b8bb8 928
9a317425 929 if (params->rx_dim_enabled)
af5a6c93 930 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
cb3c7fd4 931
f62b8bb8
AV		 932 return 0;
933
f62b8bb8
AV		 934err_destroy_rq:
935 mlx5e_destroy_rq(rq);
3b77235b
SM		 936err_free_rq:
937 mlx5e_free_rq(rq);
f62b8bb8
AV		 938
939 return err;
940}
941
acc6c595
SM		 942static void mlx5e_activate_rq(struct mlx5e_rq *rq)
943{
944 struct mlx5e_icosq *sq = &rq->channel->icosq;
ddf385e3 945 struct mlx5_wq_cyc *wq = &sq->wq;
acc6c595
SM		 946 struct mlx5e_tx_wqe *nopwqe;
947
ddf385e3
TT		 948 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
949
acc6c595
SM		 950 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
951 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
ddf385e3
TT		 952 nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
953 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
acc6c595
SM		 954}
955
956static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
f62b8bb8 957{
c0f1147d 958 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 959 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
acc6c595 960}
cb3c7fd4 961
acc6c595
SM		 962static void mlx5e_close_rq(struct mlx5e_rq *rq)
963{
9a317425 964 cancel_work_sync(&rq->dim.work);
f62b8bb8 965 mlx5e_destroy_rq(rq);
3b77235b
SM		 966 mlx5e_free_rx_descs(rq);
967 mlx5e_free_rq(rq);
f62b8bb8
AV		 968}
969
31391048 970static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
b5503b99 971{
c94e4f11 972 kvfree(sq->db.xdpi);
b5503b99
SM		 973}
974
31391048 975static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
b5503b99
SM		 976{
977 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
978
c94e4f11
TT		 979 sq->db.xdpi = kvzalloc_node(array_size(wq_sz, sizeof(*sq->db.xdpi)),
980 GFP_KERNEL, numa);
981 if (!sq->db.xdpi) {
31391048 982 mlx5e_free_xdpsq_db(sq);
b5503b99
SM		 983 return -ENOMEM;
984 }
985
986 return 0;
987}
988
31391048 989static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
6a9764ef 990 struct mlx5e_params *params,
31391048 991 struct mlx5e_sq_param *param,
58b99ee3
TT		 992 struct mlx5e_xdpsq *sq,
993 bool is_redirect)
31391048
SM		 994{
995 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 996 struct mlx5_core_dev *mdev = c->mdev;
ddf385e3 997 struct mlx5_wq_cyc *wq = &sq->wq;
31391048
SM		 998 int err;
999
1000 sq->pdev = c->pdev;
1001 sq->mkey_be = c->mkey_be;
1002 sq->channel = c;
1003 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 1004 sq->min_inline_mode = params->tx_min_inline_mode;
c94e4f11 1005 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
58b99ee3
TT		 1006 sq->stats = is_redirect ?
1007 &c->priv->channel_stats[c->ix].xdpsq :
1008 &c->priv->channel_stats[c->ix].rq_xdpsq;
31391048 1009
231243c8 1010 param->wq.db_numa_node = cpu_to_node(c->cpu);
ddf385e3 1011 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
31391048
SM		 1012 if (err)
1013 return err;
ddf385e3 1014 wq->db = &wq->db[MLX5_SND_DBR];
31391048 1015
231243c8 1016 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
31391048
SM		 1017 if (err)
1018 goto err_sq_wq_destroy;
1019
1020 return 0;
1021
1022err_sq_wq_destroy:
1023 mlx5_wq_destroy(&sq->wq_ctrl);
1024
1025 return err;
1026}
1027
1028static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1029{
1030 mlx5e_free_xdpsq_db(sq);
1031 mlx5_wq_destroy(&sq->wq_ctrl);
1032}
1033
1034static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
f62b8bb8 1035{
ca11b798 1036 kvfree(sq->db.ico_wqe);
f62b8bb8
AV		 1037}
1038
31391048 1039static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
f10b7cc7
SM		 1040{
1041 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1042
eec4edc9
KC		 1043 sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1044 sizeof(*sq->db.ico_wqe)),
ca11b798 1045 GFP_KERNEL, numa);
f10b7cc7
SM		 1046 if (!sq->db.ico_wqe)
1047 return -ENOMEM;
1048
1049 return 0;
1050}
1051
31391048 1052static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
31391048
SM		 1053 struct mlx5e_sq_param *param,
1054 struct mlx5e_icosq *sq)
f10b7cc7 1055{
31391048 1056 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1057 struct mlx5_core_dev *mdev = c->mdev;
ddf385e3 1058 struct mlx5_wq_cyc *wq = &sq->wq;
31391048 1059 int err;
f10b7cc7 1060
31391048
SM		 1061 sq->channel = c;
1062 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f62b8bb8 1063
231243c8 1064 param->wq.db_numa_node = cpu_to_node(c->cpu);
ddf385e3 1065 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
31391048
SM		 1066 if (err)
1067 return err;
ddf385e3 1068 wq->db = &wq->db[MLX5_SND_DBR];
f62b8bb8 1069
231243c8 1070 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
31391048
SM		 1071 if (err)
1072 goto err_sq_wq_destroy;
1073
f62b8bb8 1074 return 0;
31391048
SM		 1075
1076err_sq_wq_destroy:
1077 mlx5_wq_destroy(&sq->wq_ctrl);
1078
1079 return err;
f62b8bb8
AV		 1080}
1081
31391048 1082static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
f10b7cc7 1083{
31391048
SM		 1084 mlx5e_free_icosq_db(sq);
1085 mlx5_wq_destroy(&sq->wq_ctrl);
f10b7cc7
SM		 1086}
1087
31391048 1088static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
f10b7cc7 1089{
ca11b798
TT		 1090 kvfree(sq->db.wqe_info);
1091 kvfree(sq->db.dma_fifo);
f10b7cc7
SM		 1092}
1093
31391048 1094static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
b5503b99 1095{
31391048
SM		 1096 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1097 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1098
eec4edc9
KC		 1099 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1100 sizeof(*sq->db.dma_fifo)),
ca11b798 1101 GFP_KERNEL, numa);
eec4edc9
KC		 1102 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1103 sizeof(*sq->db.wqe_info)),
ca11b798 1104 GFP_KERNEL, numa);
77bdf895 1105 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
31391048
SM		 1106 mlx5e_free_txqsq_db(sq);
1107 return -ENOMEM;
b5503b99 1108 }
31391048
SM		 1109
1110 sq->dma_fifo_mask = df_sz - 1;
1111
1112 return 0;
b5503b99
SM		 1113}
1114
db75373c 1115static void mlx5e_sq_recover(struct work_struct *work);
31391048 1116static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
acc6c595 1117 int txq_ix,
6a9764ef 1118 struct mlx5e_params *params,
31391048 1119 struct mlx5e_sq_param *param,
05909bab
EBE		 1120 struct mlx5e_txqsq *sq,
1121 int tc)
f62b8bb8 1122{
31391048 1123 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1124 struct mlx5_core_dev *mdev = c->mdev;
ddf385e3 1125 struct mlx5_wq_cyc *wq = &sq->wq;
f62b8bb8
AV		 1126 int err;
1127
f10b7cc7 1128 sq->pdev = c->pdev;
a43b25da 1129 sq->tstamp = c->tstamp;
7c39afb3 1130 sq->clock = &mdev->clock;
f10b7cc7
SM		 1131 sq->mkey_be = c->mkey_be;
1132 sq->channel = c;
acc6c595 1133 sq->txq_ix = txq_ix;
aff26157 1134 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 1135 sq->min_inline_mode = params->tx_min_inline_mode;
05909bab 1136 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
db75373c 1137 INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
2ac9cfe7
IT		 1138 if (MLX5_IPSEC_DEV(c->priv->mdev))
1139 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
bf239741
IL		 1140 if (mlx5_accel_is_tls_device(c->priv->mdev))
1141 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
f10b7cc7 1142
231243c8 1143 param->wq.db_numa_node = cpu_to_node(c->cpu);
ddf385e3 1144 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
f62b8bb8 1145 if (err)
aff26157 1146 return err;
ddf385e3 1147 wq->db = &wq->db[MLX5_SND_DBR];
f62b8bb8 1148
231243c8 1149 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
7ec0bb22 1150 if (err)
f62b8bb8
AV		 1151 goto err_sq_wq_destroy;
1152
cbce4f44
TG		 1153 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1154 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1155
f62b8bb8
AV		 1156 return 0;
1157
1158err_sq_wq_destroy:
1159 mlx5_wq_destroy(&sq->wq_ctrl);
1160
f62b8bb8
AV		 1161 return err;
1162}
1163
31391048 1164static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1165{
31391048 1166 mlx5e_free_txqsq_db(sq);
f62b8bb8 1167 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1168}
1169
33ad9711
SM		 1170struct mlx5e_create_sq_param {
1171 struct mlx5_wq_ctrl *wq_ctrl;
1172 u32 cqn;
1173 u32 tisn;
1174 u8 tis_lst_sz;
1175 u8 min_inline_mode;
1176};
1177
a43b25da 1178static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
33ad9711
SM		 1179 struct mlx5e_sq_param *param,
1180 struct mlx5e_create_sq_param *csp,
1181 u32 *sqn)
f62b8bb8 1182{
f62b8bb8
AV		 1183 void *in;
1184 void *sqc;
1185 void *wq;
1186 int inlen;
1187 int err;
1188
1189 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
33ad9711 1190 sizeof(u64) * csp->wq_ctrl->buf.npages;
1b9a07ee 1191 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1192 if (!in)
1193 return -ENOMEM;
1194
1195 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1196 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1197
1198 memcpy(sqc, param->sqc, sizeof(param->sqc));
33ad9711
SM		 1199 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1200 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1201 MLX5_SET(sqc, sqc, cqn, csp->cqn);
a6f402e4
SM		 1202
1203 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
33ad9711 1204 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
a6f402e4 1205
33ad9711 1206 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
db75373c 1207 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
f62b8bb8
AV		 1208
1209 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
a43b25da 1210 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
33ad9711 1211 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
68cdf5d6 1212 MLX5_ADAPTER_PAGE_SHIFT);
33ad9711 1213 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
f62b8bb8 1214
3a2f7033
TT		 1215 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1216 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 1217
33ad9711 1218 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
f62b8bb8
AV		 1219
1220 kvfree(in);
1221
1222 return err;
1223}
1224
33ad9711
SM		 1225struct mlx5e_modify_sq_param {
1226 int curr_state;
1227 int next_state;
1228 bool rl_update;
1229 int rl_index;
1230};
1231
a43b25da 1232static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
33ad9711 1233 struct mlx5e_modify_sq_param *p)
f62b8bb8 1234{
f62b8bb8
AV		 1235 void *in;
1236 void *sqc;
1237 int inlen;
1238 int err;
1239
1240 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 1241 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1242 if (!in)
1243 return -ENOMEM;
1244
1245 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1246
33ad9711
SM		 1247 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1248 MLX5_SET(sqc, sqc, state, p->next_state);
1249 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
507f0c81 1250 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
33ad9711 1251 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
507f0c81 1252 }
f62b8bb8 1253
33ad9711 1254 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
f62b8bb8
AV		 1255
1256 kvfree(in);
1257
1258 return err;
1259}
1260
a43b25da 1261static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
33ad9711 1262{
a43b25da 1263 mlx5_core_destroy_sq(mdev, sqn);
f62b8bb8
AV		 1264}
1265
a43b25da 1266static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
31391048
SM		 1267 struct mlx5e_sq_param *param,
1268 struct mlx5e_create_sq_param *csp,
1269 u32 *sqn)
f62b8bb8 1270{
33ad9711 1271 struct mlx5e_modify_sq_param msp = {0};
31391048
SM		 1272 int err;
1273
a43b25da 1274 err = mlx5e_create_sq(mdev, param, csp, sqn);
31391048
SM		 1275 if (err)
1276 return err;
1277
1278 msp.curr_state = MLX5_SQC_STATE_RST;
1279 msp.next_state = MLX5_SQC_STATE_RDY;
a43b25da 1280 err = mlx5e_modify_sq(mdev, *sqn, &msp);
31391048 1281 if (err)
a43b25da 1282 mlx5e_destroy_sq(mdev, *sqn);
31391048
SM		 1283
1284 return err;
1285}
1286
7f859ecf
SM		 1287static int mlx5e_set_sq_maxrate(struct net_device *dev,
1288 struct mlx5e_txqsq *sq, u32 rate);
1289
31391048 1290static int mlx5e_open_txqsq(struct mlx5e_channel *c,
a43b25da 1291 u32 tisn,
acc6c595 1292 int txq_ix,
6a9764ef 1293 struct mlx5e_params *params,
31391048 1294 struct mlx5e_sq_param *param,
05909bab
EBE		 1295 struct mlx5e_txqsq *sq,
1296 int tc)
31391048
SM		 1297{
1298 struct mlx5e_create_sq_param csp = {};
7f859ecf 1299 u32 tx_rate;
f62b8bb8
AV		 1300 int err;
1301
05909bab 1302 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
f62b8bb8
AV		 1303 if (err)
1304 return err;
1305
a43b25da 1306 csp.tisn = tisn;
31391048 1307 csp.tis_lst_sz = 1;
33ad9711
SM		 1308 csp.cqn = sq->cq.mcq.cqn;
1309 csp.wq_ctrl = &sq->wq_ctrl;
1310 csp.min_inline_mode = sq->min_inline_mode;
a43b25da 1311 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
f62b8bb8 1312 if (err)
31391048 1313 goto err_free_txqsq;
f62b8bb8 1314
a43b25da 1315 tx_rate = c->priv->tx_rates[sq->txq_ix];
7f859ecf 1316 if (tx_rate)
a43b25da 1317 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
7f859ecf 1318
cbce4f44
TG		 1319 if (params->tx_dim_enabled)
1320 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1321
f62b8bb8
AV		 1322 return 0;
1323
31391048 1324err_free_txqsq:
3b77235b 1325 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
31391048 1326 mlx5e_free_txqsq(sq);
f62b8bb8
AV		 1327
1328 return err;
1329}
1330
db75373c
EBE		 1331static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1332{
1333 WARN_ONCE(sq->cc != sq->pc,
1334 "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1335 sq->sqn, sq->cc, sq->pc);
1336 sq->cc = 0;
1337 sq->dma_fifo_cc = 0;
1338 sq->pc = 0;
1339}
1340
acc6c595
SM		 1341static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1342{
a43b25da 1343 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
db75373c 1344 clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
acc6c595
SM		 1345 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1346 netdev_tx_reset_queue(sq->txq);
1347 netif_tx_start_queue(sq->txq);
1348}
1349
f62b8bb8
AV		 1350static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1351{
1352 __netif_tx_lock_bh(txq);
1353 netif_tx_stop_queue(txq);
1354 __netif_tx_unlock_bh(txq);
1355}
1356
acc6c595 1357static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1358{
33ad9711 1359 struct mlx5e_channel *c = sq->channel;
ddf385e3 1360 struct mlx5_wq_cyc *wq = &sq->wq;
33ad9711 1361
c0f1147d 1362 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6 1363 /* prevent netif_tx_wake_queue */
33ad9711 1364 napi_synchronize(&c->napi);
29429f33 1365
31391048 1366 netif_tx_disable_queue(sq->txq);
f62b8bb8 1367
31391048 1368 /* last doorbell out, godspeed .. */
ddf385e3
TT		 1369 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1370 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
31391048 1371 struct mlx5e_tx_wqe *nop;
864b2d71 1372
ddf385e3
TT		 1373 sq->db.wqe_info[pi].skb = NULL;
1374 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1375 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
29429f33 1376 }
acc6c595
SM		 1377}
1378
1379static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1380{
1381 struct mlx5e_channel *c = sq->channel;
a43b25da 1382 struct mlx5_core_dev *mdev = c->mdev;
05d3ac97 1383 struct mlx5_rate_limit rl = {0};
f62b8bb8 1384
a43b25da 1385 mlx5e_destroy_sq(mdev, sq->sqn);
05d3ac97
BW		 1386 if (sq->rate_limit) {
1387 rl.rate = sq->rate_limit;
1388 mlx5_rl_remove_rate(mdev, &rl);
1389 }
31391048
SM		 1390 mlx5e_free_txqsq_descs(sq);
1391 mlx5e_free_txqsq(sq);
1392}
1393
db75373c
EBE		 1394static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1395{
1396 unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1397
1398 while (time_before(jiffies, exp_time)) {
1399 if (sq->cc == sq->pc)
1400 return 0;
1401
1402 msleep(20);
1403 }
1404
1405 netdev_err(sq->channel->netdev,
1406 "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1407 sq->sqn, sq->cc, sq->pc);
1408
1409 return -ETIMEDOUT;
1410}
1411
1412static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1413{
1414 struct mlx5_core_dev *mdev = sq->channel->mdev;
1415 struct net_device *dev = sq->channel->netdev;
1416 struct mlx5e_modify_sq_param msp = {0};
1417 int err;
1418
1419 msp.curr_state = curr_state;
1420 msp.next_state = MLX5_SQC_STATE_RST;
1421
1422 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1423 if (err) {
1424 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1425 return err;
1426 }
1427
1428 memset(&msp, 0, sizeof(msp));
1429 msp.curr_state = MLX5_SQC_STATE_RST;
1430 msp.next_state = MLX5_SQC_STATE_RDY;
1431
1432 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1433 if (err) {
1434 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1435 return err;
1436 }
1437
1438 return 0;
1439}
1440
1441static void mlx5e_sq_recover(struct work_struct *work)
1442{
1443 struct mlx5e_txqsq_recover *recover =
1444 container_of(work, struct mlx5e_txqsq_recover,
1445 recover_work);
1446 struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1447 recover);
1448 struct mlx5_core_dev *mdev = sq->channel->mdev;
1449 struct net_device *dev = sq->channel->netdev;
1450 u8 state;
1451 int err;
1452
1453 err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1454 if (err) {
1455 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1456 sq->sqn, err);
1457 return;
1458 }
1459
1460 if (state != MLX5_RQC_STATE_ERR) {
1461 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1462 return;
1463 }
1464
1465 netif_tx_disable_queue(sq->txq);
1466
1467 if (mlx5e_wait_for_sq_flush(sq))
1468 return;
1469
1470 /* If the interval between two consecutive recovers per SQ is too
1471 * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1472 * If we reached this state, there is probably a bug that needs to be
1473 * fixed. let's keep the queue close and let tx timeout cleanup.
1474 */
1475 if (jiffies_to_msecs(jiffies - recover->last_recover) <
1476 MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1477 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1478 sq->sqn);
1479 return;
1480 }
1481
1482 /* At this point, no new packets will arrive from the stack as TXQ is
1483 * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1484 * pending WQEs. SQ can safely reset the SQ.
1485 */
1486 if (mlx5e_sq_to_ready(sq, state))
1487 return;
1488
1489 mlx5e_reset_txqsq_cc_pc(sq);
05909bab 1490 sq->stats->recover++;
db75373c
EBE		 1491 recover->last_recover = jiffies;
1492 mlx5e_activate_txqsq(sq);
1493}
1494
31391048 1495static int mlx5e_open_icosq(struct mlx5e_channel *c,
6a9764ef 1496 struct mlx5e_params *params,
31391048
SM		 1497 struct mlx5e_sq_param *param,
1498 struct mlx5e_icosq *sq)
1499{
1500 struct mlx5e_create_sq_param csp = {};
1501 int err;
1502
6a9764ef 1503 err = mlx5e_alloc_icosq(c, param, sq);
31391048
SM		 1504 if (err)
1505 return err;
1506
1507 csp.cqn = sq->cq.mcq.cqn;
1508 csp.wq_ctrl = &sq->wq_ctrl;
6a9764ef 1509 csp.min_inline_mode = params->tx_min_inline_mode;
31391048 1510 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1511 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1512 if (err)
1513 goto err_free_icosq;
1514
1515 return 0;
1516
1517err_free_icosq:
1518 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1519 mlx5e_free_icosq(sq);
1520
1521 return err;
1522}
1523
1524static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1525{
1526 struct mlx5e_channel *c = sq->channel;
1527
1528 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1529 napi_synchronize(&c->napi);
1530
a43b25da 1531 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1532 mlx5e_free_icosq(sq);
1533}
1534
1535static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
6a9764ef 1536 struct mlx5e_params *params,
31391048 1537 struct mlx5e_sq_param *param,
58b99ee3
TT		 1538 struct mlx5e_xdpsq *sq,
1539 bool is_redirect)
31391048
SM		 1540{
1541 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1542 struct mlx5e_create_sq_param csp = {};
31391048
SM		 1543 unsigned int inline_hdr_sz = 0;
1544 int err;
1545 int i;
1546
58b99ee3 1547 err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
31391048
SM		 1548 if (err)
1549 return err;
1550
1551 csp.tis_lst_sz = 1;
a43b25da 1552 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
31391048
SM		 1553 csp.cqn = sq->cq.mcq.cqn;
1554 csp.wq_ctrl = &sq->wq_ctrl;
1555 csp.min_inline_mode = sq->min_inline_mode;
58b99ee3
TT		 1556 if (is_redirect)
1557 set_bit(MLX5E_SQ_STATE_REDIRECT, &sq->state);
31391048 1558 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1559 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1560 if (err)
1561 goto err_free_xdpsq;
1562
1563 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1564 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1565 ds_cnt++;
1566 }
1567
1568 /* Pre initialize fixed WQE fields */
1569 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1570 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1571 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1572 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1573 struct mlx5_wqe_data_seg *dseg;
1574
1575 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1576 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1577
1578 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1579 dseg->lkey = sq->mkey_be;
1580 }
1581
1582 return 0;
1583
1584err_free_xdpsq:
1585 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1586 mlx5e_free_xdpsq(sq);
1587
1588 return err;
1589}
1590
1591static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1592{
1593 struct mlx5e_channel *c = sq->channel;
1594
1595 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1596 napi_synchronize(&c->napi);
1597
a43b25da 1598 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1599 mlx5e_free_xdpsq_descs(sq);
1600 mlx5e_free_xdpsq(sq);
f62b8bb8
AV		 1601}
1602
95b6c6a5
EBE		 1603static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1604 struct mlx5e_cq_param *param,
1605 struct mlx5e_cq *cq)
f62b8bb8 1606{
f62b8bb8
AV		 1607 struct mlx5_core_cq *mcq = &cq->mcq;
1608 int eqn_not_used;
0b6e26ce 1609 unsigned int irqn;
f62b8bb8
AV		 1610 int err;
1611 u32 i;
1612
f62b8bb8
AV		 1613 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1614 &cq->wq_ctrl);
1615 if (err)
1616 return err;
1617
1618 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1619
f62b8bb8
AV		 1620 mcq->cqe_sz = 64;
1621 mcq->set_ci_db = cq->wq_ctrl.db.db;
1622 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1623 *mcq->set_ci_db = 0;
1624 *mcq->arm_db = 0;
1625 mcq->vector = param->eq_ix;
1626 mcq->comp = mlx5e_completion_event;
1627 mcq->event = mlx5e_cq_error_event;
1628 mcq->irqn = irqn;
f62b8bb8
AV		 1629
1630 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1631 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1632
1633 cqe->op_own = 0xf1;
1634 }
1635
a43b25da 1636 cq->mdev = mdev;
f62b8bb8
AV		 1637
1638 return 0;
1639}
1640
95b6c6a5
EBE		 1641static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1642 struct mlx5e_cq_param *param,
1643 struct mlx5e_cq *cq)
1644{
1645 struct mlx5_core_dev *mdev = c->priv->mdev;
1646 int err;
1647
231243c8
SM		 1648 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1649 param->wq.db_numa_node = cpu_to_node(c->cpu);
95b6c6a5
EBE		 1650 param->eq_ix = c->ix;
1651
1652 err = mlx5e_alloc_cq_common(mdev, param, cq);
1653
1654 cq->napi = &c->napi;
1655 cq->channel = c;
1656
1657 return err;
1658}
1659
3b77235b 1660static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1661{
3a2f7033 1662 mlx5_wq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1663}
1664
3b77235b 1665static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1666{
a43b25da 1667 struct mlx5_core_dev *mdev = cq->mdev;
f62b8bb8
AV		 1668 struct mlx5_core_cq *mcq = &cq->mcq;
1669
1670 void *in;
1671 void *cqc;
1672 int inlen;
0b6e26ce 1673 unsigned int irqn_not_used;
f62b8bb8
AV		 1674 int eqn;
1675 int err;
1676
1677 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
3a2f7033 1678 sizeof(u64) * cq->wq_ctrl.buf.npages;
1b9a07ee 1679 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1680 if (!in)
1681 return -ENOMEM;
1682
1683 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1684
1685 memcpy(cqc, param->cqc, sizeof(param->cqc));
1686
3a2f7033 1687 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1c1b5228 1688 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1689
1690 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1691
9908aa29 1692 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1693 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1694 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
3a2f7033 1695 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 1696 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1697 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1698
1699 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1700
1701 kvfree(in);
1702
1703 if (err)
1704 return err;
1705
1706 mlx5e_cq_arm(cq);
1707
1708 return 0;
1709}
1710
3b77235b 1711static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1712{
a43b25da 1713 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
f62b8bb8
AV		 1714}
1715
1716static int mlx5e_open_cq(struct mlx5e_channel *c,
9a317425 1717 struct net_dim_cq_moder moder,
f62b8bb8 1718 struct mlx5e_cq_param *param,
6a9764ef 1719 struct mlx5e_cq *cq)
f62b8bb8 1720{
a43b25da 1721 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1722 int err;
f62b8bb8 1723
3b77235b 1724 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1725 if (err)
1726 return err;
1727
3b77235b 1728 err = mlx5e_create_cq(cq, param);
f62b8bb8 1729 if (err)
3b77235b 1730 goto err_free_cq;
f62b8bb8 1731
7524a5d8 1732 if (MLX5_CAP_GEN(mdev, cq_moderation))
6a9764ef 1733 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
f62b8bb8
AV		 1734 return 0;
1735
3b77235b
SM		 1736err_free_cq:
1737 mlx5e_free_cq(cq);
f62b8bb8
AV		 1738
1739 return err;
1740}
1741
1742static void mlx5e_close_cq(struct mlx5e_cq *cq)
1743{
f62b8bb8 1744 mlx5e_destroy_cq(cq);
3b77235b 1745 mlx5e_free_cq(cq);
f62b8bb8
AV		 1746}
1747
231243c8
SM		 1748static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1749{
1750 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1751}
1752
f62b8bb8 1753static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
6a9764ef 1754 struct mlx5e_params *params,
f62b8bb8
AV		 1755 struct mlx5e_channel_param *cparam)
1756{
f62b8bb8
AV		 1757 int err;
1758 int tc;
1759
1760 for (tc = 0; tc < c->num_tc; tc++) {
6a9764ef
SM		 1761 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1762 &cparam->tx_cq, &c->sq[tc].cq);
f62b8bb8
AV		 1763 if (err)
1764 goto err_close_tx_cqs;
f62b8bb8
AV		 1765 }
1766
1767 return 0;
1768
1769err_close_tx_cqs:
1770 for (tc--; tc >= 0; tc--)
1771 mlx5e_close_cq(&c->sq[tc].cq);
1772
1773 return err;
1774}
1775
1776static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1777{
1778 int tc;
1779
1780 for (tc = 0; tc < c->num_tc; tc++)
1781 mlx5e_close_cq(&c->sq[tc].cq);
1782}
1783
1784static int mlx5e_open_sqs(struct mlx5e_channel *c,
6a9764ef 1785 struct mlx5e_params *params,
f62b8bb8
AV		 1786 struct mlx5e_channel_param *cparam)
1787{
05909bab
EBE		 1788 struct mlx5e_priv *priv = c->priv;
1789 int err, tc, max_nch = priv->profile->max_nch(priv->mdev);
f62b8bb8 1790
6a9764ef 1791 for (tc = 0; tc < params->num_tc; tc++) {
05909bab 1792 int txq_ix = c->ix + tc * max_nch;
acc6c595 1793
a43b25da 1794 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
05909bab 1795 params, &cparam->sq, &c->sq[tc], tc);
f62b8bb8
AV		 1796 if (err)
1797 goto err_close_sqs;
1798 }
1799
1800 return 0;
1801
1802err_close_sqs:
1803 for (tc--; tc >= 0; tc--)
31391048 1804 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1805
1806 return err;
1807}
1808
1809static void mlx5e_close_sqs(struct mlx5e_channel *c)
1810{
1811 int tc;
1812
1813 for (tc = 0; tc < c->num_tc; tc++)
31391048 1814 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1815}
1816
507f0c81 1817static int mlx5e_set_sq_maxrate(struct net_device *dev,
31391048 1818 struct mlx5e_txqsq *sq, u32 rate)
507f0c81
YP		 1819{
1820 struct mlx5e_priv *priv = netdev_priv(dev);
1821 struct mlx5_core_dev *mdev = priv->mdev;
33ad9711 1822 struct mlx5e_modify_sq_param msp = {0};
05d3ac97 1823 struct mlx5_rate_limit rl = {0};
507f0c81
YP		 1824 u16 rl_index = 0;
1825 int err;
1826
1827 if (rate == sq->rate_limit)
1828 /* nothing to do */
1829 return 0;
1830
05d3ac97
BW		 1831 if (sq->rate_limit) {
1832 rl.rate = sq->rate_limit;
507f0c81 1833 /* remove current rl index to free space to next ones */
05d3ac97
BW		 1834 mlx5_rl_remove_rate(mdev, &rl);
1835 }
507f0c81
YP		 1836
1837 sq->rate_limit = 0;
1838
1839 if (rate) {
05d3ac97
BW		 1840 rl.rate = rate;
1841 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
507f0c81
YP		 1842 if (err) {
1843 netdev_err(dev, "Failed configuring rate %u: %d\n",
1844 rate, err);
1845 return err;
1846 }
1847 }
1848
33ad9711
SM		 1849 msp.curr_state = MLX5_SQC_STATE_RDY;
1850 msp.next_state = MLX5_SQC_STATE_RDY;
1851 msp.rl_index = rl_index;
1852 msp.rl_update = true;
a43b25da 1853 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
507f0c81
YP		 1854 if (err) {
1855 netdev_err(dev, "Failed configuring rate %u: %d\n",
1856 rate, err);
1857 /* remove the rate from the table */
1858 if (rate)
05d3ac97 1859 mlx5_rl_remove_rate(mdev, &rl);
507f0c81
YP		 1860 return err;
1861 }
1862
1863 sq->rate_limit = rate;
1864 return 0;
1865}
1866
1867static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1868{
1869 struct mlx5e_priv *priv = netdev_priv(dev);
1870 struct mlx5_core_dev *mdev = priv->mdev;
acc6c595 1871 struct mlx5e_txqsq *sq = priv->txq2sq[index];
507f0c81
YP		 1872 int err = 0;
1873
1874 if (!mlx5_rl_is_supported(mdev)) {
1875 netdev_err(dev, "Rate limiting is not supported on this device\n");
1876 return -EINVAL;
1877 }
1878
1879 /* rate is given in Mb/sec, HW config is in Kb/sec */
1880 rate = rate << 10;
1881
1882 /* Check whether rate in valid range, 0 is always valid */
1883 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1884 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1885 return -ERANGE;
1886 }
1887
1888 mutex_lock(&priv->state_lock);
1889 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1890 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1891 if (!err)
1892 priv->tx_rates[index] = rate;
1893 mutex_unlock(&priv->state_lock);
1894
1895 return err;
1896}
1897
f62b8bb8 1898static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
6a9764ef 1899 struct mlx5e_params *params,
f62b8bb8
AV		 1900 struct mlx5e_channel_param *cparam,
1901 struct mlx5e_channel **cp)
1902{
9a317425 1903 struct net_dim_cq_moder icocq_moder = {0, 0};
f62b8bb8 1904 struct net_device *netdev = priv->netdev;
231243c8 1905 int cpu = mlx5e_get_cpu(priv, ix);
f62b8bb8 1906 struct mlx5e_channel *c;
a8c2eb15 1907 unsigned int irq;
f62b8bb8 1908 int err;
a8c2eb15 1909 int eqn;
f62b8bb8 1910
ca11b798 1911 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
f62b8bb8
AV		 1912 if (!c)
1913 return -ENOMEM;
1914
1915 c->priv = priv;
a43b25da
SM		 1916 c->mdev = priv->mdev;
1917 c->tstamp = &priv->tstamp;
f62b8bb8 1918 c->ix = ix;
231243c8 1919 c->cpu = cpu;
f62b8bb8
AV		 1920 c->pdev = &priv->mdev->pdev->dev;
1921 c->netdev = priv->netdev;
b50d292b 1922 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
6a9764ef
SM		 1923 c->num_tc = params->num_tc;
1924 c->xdp = !!params->xdp_prog;
05909bab 1925 c->stats = &priv->channel_stats[ix].ch;
cb3c7fd4 1926
a8c2eb15
TT		 1927 mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1928 c->irq_desc = irq_to_desc(irq);
1929
f62b8bb8
AV		 1930 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1931
6a9764ef 1932 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
f62b8bb8
AV		 1933 if (err)
1934 goto err_napi_del;
1935
6a9764ef 1936 err = mlx5e_open_tx_cqs(c, params, cparam);
d3c9bc27
TT		 1937 if (err)
1938 goto err_close_icosq_cq;
1939
58b99ee3 1940 err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
f62b8bb8
AV		 1941 if (err)
1942 goto err_close_tx_cqs;
f62b8bb8 1943
58b99ee3
TT		 1944 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1945 if (err)
1946 goto err_close_xdp_tx_cqs;
1947
d7a0ecab 1948 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
6a9764ef
SM		 1949 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1950 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
d7a0ecab
SM		 1951 if (err)
1952 goto err_close_rx_cq;
1953
f62b8bb8
AV		 1954 napi_enable(&c->napi);
1955
6a9764ef 1956 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1957 if (err)
1958 goto err_disable_napi;
1959
6a9764ef 1960 err = mlx5e_open_sqs(c, params, cparam);
d3c9bc27
TT		 1961 if (err)
1962 goto err_close_icosq;
1963
58b99ee3 1964 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
d7a0ecab
SM		 1965 if (err)
1966 goto err_close_sqs;
b5503b99 1967
6a9764ef 1968 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
f62b8bb8 1969 if (err)
b5503b99 1970 goto err_close_xdp_sq;
f62b8bb8 1971
58b99ee3
TT		 1972 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
1973 if (err)
1974 goto err_close_rq;
1975
f62b8bb8
AV		 1976 *cp = c;
1977
1978 return 0;
58b99ee3
TT		 1979
1980err_close_rq:
1981 mlx5e_close_rq(&c->rq);
1982
b5503b99 1983err_close_xdp_sq:
d7a0ecab 1984 if (c->xdp)
31391048 1985 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8
AV		 1986
1987err_close_sqs:
1988 mlx5e_close_sqs(c);
1989
d3c9bc27 1990err_close_icosq:
31391048 1991 mlx5e_close_icosq(&c->icosq);
d3c9bc27 1992
f62b8bb8
AV		 1993err_disable_napi:
1994 napi_disable(&c->napi);
d7a0ecab 1995 if (c->xdp)
31871f87 1996 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 1997
1998err_close_rx_cq:
f62b8bb8
AV		 1999 mlx5e_close_cq(&c->rq.cq);
2000
58b99ee3
TT		 2001err_close_xdp_tx_cqs:
2002 mlx5e_close_cq(&c->xdpsq.cq);
2003
f62b8bb8
AV		 2004err_close_tx_cqs:
2005 mlx5e_close_tx_cqs(c);
2006
d3c9bc27
TT		 2007err_close_icosq_cq:
2008 mlx5e_close_cq(&c->icosq.cq);
2009
f62b8bb8
AV		 2010err_napi_del:
2011 netif_napi_del(&c->napi);
ca11b798 2012 kvfree(c);
f62b8bb8
AV		 2013
2014 return err;
2015}
2016
acc6c595
SM		 2017static void mlx5e_activate_channel(struct mlx5e_channel *c)
2018{
2019 int tc;
2020
2021 for (tc = 0; tc < c->num_tc; tc++)
2022 mlx5e_activate_txqsq(&c->sq[tc]);
2023 mlx5e_activate_rq(&c->rq);
231243c8 2024 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
acc6c595
SM		 2025}
2026
2027static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2028{
2029 int tc;
2030
2031 mlx5e_deactivate_rq(&c->rq);
2032 for (tc = 0; tc < c->num_tc; tc++)
2033 mlx5e_deactivate_txqsq(&c->sq[tc]);
2034}
2035
f62b8bb8
AV		 2036static void mlx5e_close_channel(struct mlx5e_channel *c)
2037{
58b99ee3 2038 mlx5e_close_xdpsq(&c->xdpsq);
f62b8bb8 2039 mlx5e_close_rq(&c->rq);
b5503b99 2040 if (c->xdp)
31391048 2041 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8 2042 mlx5e_close_sqs(c);
31391048 2043 mlx5e_close_icosq(&c->icosq);
f62b8bb8 2044 napi_disable(&c->napi);
b5503b99 2045 if (c->xdp)
31871f87 2046 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8 2047 mlx5e_close_cq(&c->rq.cq);
58b99ee3 2048 mlx5e_close_cq(&c->xdpsq.cq);
f62b8bb8 2049 mlx5e_close_tx_cqs(c);
d3c9bc27 2050 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 2051 netif_napi_del(&c->napi);
7ae92ae5 2052
ca11b798 2053 kvfree(c);
f62b8bb8
AV		 2054}
2055
069d1146
TT		 2056#define DEFAULT_FRAG_SIZE (2048)
2057
2058static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2059 struct mlx5e_params *params,
2060 struct mlx5e_rq_frags_info *info)
2061{
2062 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2063 int frag_size_max = DEFAULT_FRAG_SIZE;
2064 u32 buf_size = 0;
2065 int i;
2066
2067#ifdef CONFIG_MLX5_EN_IPSEC
2068 if (MLX5_IPSEC_DEV(mdev))
2069 byte_count += MLX5E_METADATA_ETHER_LEN;
2070#endif
2071
2072 if (mlx5e_rx_is_linear_skb(mdev, params)) {
2073 int frag_stride;
2074
2075 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2076 frag_stride = roundup_pow_of_two(frag_stride);
2077
2078 info->arr[0].frag_size = byte_count;
2079 info->arr[0].frag_stride = frag_stride;
2080 info->num_frags = 1;
2081 info->wqe_bulk = PAGE_SIZE / frag_stride;
2082 goto out;
2083 }
2084
2085 if (byte_count > PAGE_SIZE +
2086 (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2087 frag_size_max = PAGE_SIZE;
2088
2089 i = 0;
2090 while (buf_size < byte_count) {
2091 int frag_size = byte_count - buf_size;
2092
2093 if (i < MLX5E_MAX_RX_FRAGS - 1)
2094 frag_size = min(frag_size, frag_size_max);
2095
2096 info->arr[i].frag_size = frag_size;
2097 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2098
2099 buf_size += frag_size;
2100 i++;
2101 }
2102 info->num_frags = i;
2103 /* number of different wqes sharing a page */
2104 info->wqe_bulk = 1 + (info->num_frags % 2);
2105
2106out:
2107 info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2108 info->log_num_frags = order_base_2(info->num_frags);
2109}
2110
99cbfa93
TT		 2111static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2112{
2113 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2114
2115 switch (wq_type) {
2116 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2117 sz += sizeof(struct mlx5e_rx_wqe_ll);
2118 break;
2119 default: /* MLX5_WQ_TYPE_CYCLIC */
2120 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2121 }
2122
2123 return order_base_2(sz);
2124}
2125
f62b8bb8 2126static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
6a9764ef 2127 struct mlx5e_params *params,
f62b8bb8
AV		 2128 struct mlx5e_rq_param *param)
2129{
f1e4fc9b 2130 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2131 void *rqc = param->rqc;
2132 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
99cbfa93 2133 int ndsegs = 1;
f62b8bb8 2134
6a9764ef 2135 switch (params->rq_wq_type) {
461017cb 2136 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f1e4fc9b 2137 MLX5_SET(wq, wq, log_wqe_num_of_strides,
619a8f2a
TT		 2138 mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2139 MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
f1e4fc9b 2140 MLX5_SET(wq, wq, log_wqe_stride_size,
619a8f2a
TT		 2141 mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2142 MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
73281b78 2143 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
461017cb 2144 break;
99cbfa93 2145 default: /* MLX5_WQ_TYPE_CYCLIC */
73281b78 2146 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
069d1146
TT		 2147 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2148 ndsegs = param->frags_info.num_frags;
461017cb
TT		 2149 }
2150
99cbfa93 2151 MLX5_SET(wq, wq, wq_type, params->rq_wq_type);
f62b8bb8 2152 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
99cbfa93
TT		 2153 MLX5_SET(wq, wq, log_wq_stride,
2154 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
f1e4fc9b 2155 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn);
593cf338 2156 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
6a9764ef 2157 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
102722fc 2158 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
f62b8bb8 2159
f1e4fc9b 2160 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
f62b8bb8
AV		 2161}
2162
7cbaf9a3 2163static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2f0db879 2164 struct mlx5e_rq_param *param)
556dd1b9 2165{
7cbaf9a3 2166 struct mlx5_core_dev *mdev = priv->mdev;
556dd1b9
TT		 2167 void *rqc = param->rqc;
2168 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2169
99cbfa93
TT		 2170 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2171 MLX5_SET(wq, wq, log_wq_stride,
2172 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
7cbaf9a3 2173 MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2f0db879
GP		 2174
2175 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
556dd1b9
TT		 2176}
2177
d3c9bc27
TT		 2178static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2179 struct mlx5e_sq_param *param)
f62b8bb8
AV		 2180{
2181 void *sqc = param->sqc;
2182 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2183
f62b8bb8 2184 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 2185 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 2186
311c7c71 2187 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 2188}
2189
2190static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
6a9764ef 2191 struct mlx5e_params *params,
d3c9bc27
TT		 2192 struct mlx5e_sq_param *param)
2193{
2194 void *sqc = param->sqc;
2195 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2196
2197 mlx5e_build_sq_param_common(priv, param);
6a9764ef 2198 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2ac9cfe7 2199 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
f62b8bb8
AV		 2200}
2201
2202static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2203 struct mlx5e_cq_param *param)
2204{
2205 void *cqc = param->cqc;
2206
30aa60b3 2207 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 2208}
2209
2210static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
6a9764ef 2211 struct mlx5e_params *params,
f62b8bb8
AV		 2212 struct mlx5e_cq_param *param)
2213{
73281b78 2214 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8 2215 void *cqc = param->cqc;
461017cb 2216 u8 log_cq_size;
f62b8bb8 2217
6a9764ef 2218 switch (params->rq_wq_type) {
461017cb 2219 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
73281b78
TT		 2220 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2221 mlx5e_mpwqe_get_log_num_strides(mdev, params);
461017cb 2222 break;
99cbfa93 2223 default: /* MLX5_WQ_TYPE_CYCLIC */
73281b78 2224 log_cq_size = params->log_rq_mtu_frames;
461017cb
TT		 2225 }
2226
2227 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
6a9764ef 2228 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 2229 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2230 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2231 }
f62b8bb8
AV		 2232
2233 mlx5e_build_common_cq_param(priv, param);
0088cbbc 2234 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 2235}
2236
2237static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
6a9764ef 2238 struct mlx5e_params *params,
f62b8bb8
AV		 2239 struct mlx5e_cq_param *param)
2240{
2241 void *cqc = param->cqc;
2242
6a9764ef 2243 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
f62b8bb8
AV		 2244
2245 mlx5e_build_common_cq_param(priv, param);
0088cbbc 2246 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 2247}
2248
d3c9bc27 2249static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 2250 u8 log_wq_size,
2251 struct mlx5e_cq_param *param)
d3c9bc27
TT		 2252{
2253 void *cqc = param->cqc;
2254
2255 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2256
2257 mlx5e_build_common_cq_param(priv, param);
9908aa29 2258
9a317425 2259 param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 2260}
2261
2262static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 2263 u8 log_wq_size,
2264 struct mlx5e_sq_param *param)
d3c9bc27
TT		 2265{
2266 void *sqc = param->sqc;
2267 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2268
2269 mlx5e_build_sq_param_common(priv, param);
2270
2271 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 2272 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 2273}
2274
b5503b99 2275static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
6a9764ef 2276 struct mlx5e_params *params,
b5503b99
SM		 2277 struct mlx5e_sq_param *param)
2278{
2279 void *sqc = param->sqc;
2280 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2281
2282 mlx5e_build_sq_param_common(priv, param);
6a9764ef 2283 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
b5503b99
SM		 2284}
2285
6a9764ef
SM		 2286static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2287 struct mlx5e_params *params,
2288 struct mlx5e_channel_param *cparam)
f62b8bb8 2289{
bc77b240 2290 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 2291
6a9764ef
SM		 2292 mlx5e_build_rq_param(priv, params, &cparam->rq);
2293 mlx5e_build_sq_param(priv, params, &cparam->sq);
2294 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2295 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2296 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2297 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2298 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
f62b8bb8
AV		 2299}
2300
55c2503d
SM		 2301int mlx5e_open_channels(struct mlx5e_priv *priv,
2302 struct mlx5e_channels *chs)
f62b8bb8 2303{
6b87663f 2304 struct mlx5e_channel_param *cparam;
03289b88 2305 int err = -ENOMEM;
f62b8bb8 2306 int i;
f62b8bb8 2307
6a9764ef 2308 chs->num = chs->params.num_channels;
03289b88 2309
ff9c852f 2310 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
ca11b798 2311 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
acc6c595
SM		 2312 if (!chs->c || !cparam)
2313 goto err_free;
f62b8bb8 2314
6a9764ef 2315 mlx5e_build_channel_param(priv, &chs->params, cparam);
ff9c852f 2316 for (i = 0; i < chs->num; i++) {
6a9764ef 2317 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
f62b8bb8
AV		 2318 if (err)
2319 goto err_close_channels;
2320 }
2321
ca11b798 2322 kvfree(cparam);
f62b8bb8
AV		 2323 return 0;
2324
2325err_close_channels:
2326 for (i--; i >= 0; i--)
ff9c852f 2327 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2328
acc6c595 2329err_free:
ff9c852f 2330 kfree(chs->c);
ca11b798 2331 kvfree(cparam);
ff9c852f 2332 chs->num = 0;
f62b8bb8
AV		 2333 return err;
2334}
2335
acc6c595 2336static void mlx5e_activate_channels(struct mlx5e_channels *chs)
f62b8bb8
AV		 2337{
2338 int i;
2339
acc6c595
SM		 2340 for (i = 0; i < chs->num; i++)
2341 mlx5e_activate_channel(chs->c[i]);
2342}
2343
2344static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2345{
2346 int err = 0;
2347 int i;
2348
1e7477ae
EBE		 2349 for (i = 0; i < chs->num; i++)
2350 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2351 err ? 0 : 20000);
acc6c595 2352
1e7477ae 2353 return err ? -ETIMEDOUT : 0;
acc6c595
SM		 2354}
2355
2356static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2357{
2358 int i;
2359
2360 for (i = 0; i < chs->num; i++)
2361 mlx5e_deactivate_channel(chs->c[i]);
2362}
2363
55c2503d 2364void mlx5e_close_channels(struct mlx5e_channels *chs)
acc6c595
SM		 2365{
2366 int i;
c3b7c5c9 2367
ff9c852f
SM		 2368 for (i = 0; i < chs->num; i++)
2369 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2370
ff9c852f
SM		 2371 kfree(chs->c);
2372 chs->num = 0;
f62b8bb8
AV		 2373}
2374
a5f97fee
SM		 2375static int
2376mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 2377{
2378 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2379 void *rqtc;
2380 int inlen;
2381 int err;
1da36696 2382 u32 *in;
a5f97fee 2383 int i;
f62b8bb8 2384
f62b8bb8 2385 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2386 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2387 if (!in)
2388 return -ENOMEM;
2389
2390 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2391
2392 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2393 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2394
a5f97fee
SM		 2395 for (i = 0; i < sz; i++)
2396 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2be6967c 2397
398f3351
HHZ		 2398 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2399 if (!err)
2400 rqt->enabled = true;
f62b8bb8
AV		 2401
2402 kvfree(in);
1da36696
TT		 2403 return err;
2404}
2405
cb67b832 2406void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2407{
398f3351
HHZ		 2408 rqt->enabled = false;
2409 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2410}
2411
8f493ffd 2412int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2413{
2414 struct mlx5e_rqt *rqt = &priv->indir_rqt;
8f493ffd 2415 int err;
6bfd390b 2416
8f493ffd
SM		 2417 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2418 if (err)
2419 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2420 return err;
6bfd390b
HHZ		 2421}
2422
cb67b832 2423int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2424{
398f3351 2425 struct mlx5e_rqt *rqt;
1da36696
TT		 2426 int err;
2427 int ix;
2428
6bfd390b 2429 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351 2430 rqt = &priv->direct_tir[ix].rqt;
a5f97fee 2431 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
1da36696
TT		 2432 if (err)
2433 goto err_destroy_rqts;
2434 }
2435
2436 return 0;
2437
2438err_destroy_rqts:
8f493ffd 2439 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
1da36696 2440 for (ix--; ix >= 0; ix--)
398f3351 2441 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2442
f62b8bb8
AV		 2443 return err;
2444}
2445
8f493ffd
SM		 2446void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2447{
2448 int i;
2449
2450 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2451 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2452}
2453
a5f97fee
SM		 2454static int mlx5e_rx_hash_fn(int hfunc)
2455{
2456 return (hfunc == ETH_RSS_HASH_TOP) ?
2457 MLX5_RX_HASH_FN_TOEPLITZ :
2458 MLX5_RX_HASH_FN_INVERTED_XOR8;
2459}
2460
3f6d08d1 2461int mlx5e_bits_invert(unsigned long a, int size)
a5f97fee
SM		 2462{
2463 int inv = 0;
2464 int i;
2465
2466 for (i = 0; i < size; i++)
2467 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2468
2469 return inv;
2470}
2471
2472static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2473 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2474{
2475 int i;
2476
2477 for (i = 0; i < sz; i++) {
2478 u32 rqn;
2479
2480 if (rrp.is_rss) {
2481 int ix = i;
2482
2483 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2484 ix = mlx5e_bits_invert(i, ilog2(sz));
2485
6a9764ef 2486 ix = priv->channels.params.indirection_rqt[ix];
a5f97fee
SM		 2487 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2488 } else {
2489 rqn = rrp.rqn;
2490 }
2491 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2492 }
2493}
2494
2495int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2496 struct mlx5e_redirect_rqt_param rrp)
5c50368f
AS		 2497{
2498 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2499 void *rqtc;
2500 int inlen;
1da36696 2501 u32 *in;
5c50368f
AS		 2502 int err;
2503
5c50368f 2504 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2505 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2506 if (!in)
2507 return -ENOMEM;
2508
2509 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2510
2511 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5c50368f 2512 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
a5f97fee 2513 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
1da36696 2514 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2515
2516 kvfree(in);
5c50368f
AS		 2517 return err;
2518}
2519
a5f97fee
SM		 2520static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2521 struct mlx5e_redirect_rqt_param rrp)
2522{
2523 if (!rrp.is_rss)
2524 return rrp.rqn;
2525
2526 if (ix >= rrp.rss.channels->num)
2527 return priv->drop_rq.rqn;
2528
2529 return rrp.rss.channels->c[ix]->rq.rqn;
2530}
2531
2532static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2533 struct mlx5e_redirect_rqt_param rrp)
40ab6a6e 2534{
1da36696
TT		 2535 u32 rqtn;
2536 int ix;
2537
398f3351 2538 if (priv->indir_rqt.enabled) {
a5f97fee 2539 /* RSS RQ table */
398f3351 2540 rqtn = priv->indir_rqt.rqtn;
a5f97fee 2541 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
398f3351
HHZ		 2542 }
2543
a5f97fee
SM		 2544 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2545 struct mlx5e_redirect_rqt_param direct_rrp = {
2546 .is_rss = false,
95632791
AM		 2547 {
2548 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2549 },
a5f97fee
SM		 2550 };
2551
2552 /* Direct RQ Tables */
398f3351
HHZ		 2553 if (!priv->direct_tir[ix].rqt.enabled)
2554 continue;
a5f97fee 2555
398f3351 2556 rqtn = priv->direct_tir[ix].rqt.rqtn;
a5f97fee 2557 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
1da36696 2558 }
40ab6a6e
AS		 2559}
2560
a5f97fee
SM		 2561static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2562 struct mlx5e_channels *chs)
2563{
2564 struct mlx5e_redirect_rqt_param rrp = {
2565 .is_rss = true,
95632791
AM		 2566 {
2567 .rss = {
2568 .channels = chs,
2569 .hfunc = chs->params.rss_hfunc,
2570 }
2571 },
a5f97fee
SM		 2572 };
2573
2574 mlx5e_redirect_rqts(priv, rrp);
2575}
2576
2577static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2578{
2579 struct mlx5e_redirect_rqt_param drop_rrp = {
2580 .is_rss = false,
95632791
AM		 2581 {
2582 .rqn = priv->drop_rq.rqn,
2583 },
a5f97fee
SM		 2584 };
2585
2586 mlx5e_redirect_rqts(priv, drop_rrp);
2587}
2588
6a9764ef 2589static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
5c50368f 2590{
6a9764ef 2591 if (!params->lro_en)
5c50368f
AS		 2592 return;
2593
2594#define ROUGH_MAX_L2_L3_HDR_SZ 256
2595
2596 MLX5_SET(tirc, tirc, lro_enable_mask,
2597 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2598 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2599 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
6a9764ef
SM		 2600 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2601 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
5c50368f
AS		 2602}
2603
6a9764ef
SM		 2604void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2605 enum mlx5e_traffic_types tt,
7b3722fa 2606 void *tirc, bool inner)
bdfc028d 2607{
7b3722fa
GP		 2608 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2609 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
a100ff3e
GP		 2610
2611#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2612 MLX5_HASH_FIELD_SEL_DST_IP)
2613
2614#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2615 MLX5_HASH_FIELD_SEL_DST_IP |\
2616 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2617 MLX5_HASH_FIELD_SEL_L4_DPORT)
2618
2619#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2620 MLX5_HASH_FIELD_SEL_DST_IP |\
2621 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2622
6a9764ef
SM		 2623 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2624 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
bdfc028d
TT		 2625 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2626 rx_hash_toeplitz_key);
2627 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2628 rx_hash_toeplitz_key);
2629
2630 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
6a9764ef 2631 memcpy(rss_key, params->toeplitz_hash_key, len);
bdfc028d 2632 }
a100ff3e
GP		 2633
2634 switch (tt) {
2635 case MLX5E_TT_IPV4_TCP:
2636 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2637 MLX5_L3_PROT_TYPE_IPV4);
2638 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2639 MLX5_L4_PROT_TYPE_TCP);
2640 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2641 MLX5_HASH_IP_L4PORTS);
2642 break;
2643
2644 case MLX5E_TT_IPV6_TCP:
2645 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2646 MLX5_L3_PROT_TYPE_IPV6);
2647 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2648 MLX5_L4_PROT_TYPE_TCP);
2649 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2650 MLX5_HASH_IP_L4PORTS);
2651 break;
2652
2653 case MLX5E_TT_IPV4_UDP:
2654 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2655 MLX5_L3_PROT_TYPE_IPV4);
2656 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2657 MLX5_L4_PROT_TYPE_UDP);
2658 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2659 MLX5_HASH_IP_L4PORTS);
2660 break;
2661
2662 case MLX5E_TT_IPV6_UDP:
2663 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2664 MLX5_L3_PROT_TYPE_IPV6);
2665 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2666 MLX5_L4_PROT_TYPE_UDP);
2667 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2668 MLX5_HASH_IP_L4PORTS);
2669 break;
2670
2671 case MLX5E_TT_IPV4_IPSEC_AH:
2672 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2673 MLX5_L3_PROT_TYPE_IPV4);
2674 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2675 MLX5_HASH_IP_IPSEC_SPI);
2676 break;
2677
2678 case MLX5E_TT_IPV6_IPSEC_AH:
2679 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2680 MLX5_L3_PROT_TYPE_IPV6);
2681 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2682 MLX5_HASH_IP_IPSEC_SPI);
2683 break;
2684
2685 case MLX5E_TT_IPV4_IPSEC_ESP:
2686 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2687 MLX5_L3_PROT_TYPE_IPV4);
2688 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2689 MLX5_HASH_IP_IPSEC_SPI);
2690 break;
2691
2692 case MLX5E_TT_IPV6_IPSEC_ESP:
2693 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2694 MLX5_L3_PROT_TYPE_IPV6);
2695 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2696 MLX5_HASH_IP_IPSEC_SPI);
2697 break;
2698
2699 case MLX5E_TT_IPV4:
2700 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2701 MLX5_L3_PROT_TYPE_IPV4);
2702 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2703 MLX5_HASH_IP);
2704 break;
2705
2706 case MLX5E_TT_IPV6:
2707 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2708 MLX5_L3_PROT_TYPE_IPV6);
2709 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2710 MLX5_HASH_IP);
2711 break;
2712 default:
2713 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2714 }
bdfc028d
TT		 2715}
2716
ab0394fe 2717static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2718{
2719 struct mlx5_core_dev *mdev = priv->mdev;
2720
2721 void *in;
2722 void *tirc;
2723 int inlen;
2724 int err;
ab0394fe 2725 int tt;
1da36696 2726 int ix;
5c50368f
AS		 2727
2728 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1b9a07ee 2729 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2730 if (!in)
2731 return -ENOMEM;
2732
2733 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2734 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2735
6a9764ef 2736 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
5c50368f 2737
1da36696 2738 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2739 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2740 inlen);
ab0394fe 2741 if (err)
1da36696 2742 goto free_in;
ab0394fe 2743 }
5c50368f 2744
6bfd390b 2745 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2746 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2747 in, inlen);
2748 if (err)
2749 goto free_in;
2750 }
2751
2752free_in:
5c50368f
AS		 2753 kvfree(in);
2754
2755 return err;
2756}
2757
7b3722fa
GP		 2758static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2759 enum mlx5e_traffic_types tt,
2760 u32 *tirc)
2761{
2762 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2763
2764 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2765
2766 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2767 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2768 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2769
2770 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2771}
2772
472a1e44
TT		 2773static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2774 struct mlx5e_params *params, u16 mtu)
40ab6a6e 2775{
472a1e44 2776 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
40ab6a6e
AS		 2777 int err;
2778
cd255eff 2779 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2780 if (err)
2781 return err;
2782
cd255eff
SM		 2783 /* Update vport context MTU */
2784 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2785 return 0;
2786}
40ab6a6e 2787
472a1e44
TT		 2788static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2789 struct mlx5e_params *params, u16 *mtu)
cd255eff 2790{
cd255eff
SM		 2791 u16 hw_mtu = 0;
2792 int err;
40ab6a6e 2793
cd255eff
SM		 2794 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2795 if (err || !hw_mtu) /* fallback to port oper mtu */
2796 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2797
472a1e44 2798 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
cd255eff
SM		 2799}
2800
2e20a151 2801static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
cd255eff 2802{
472a1e44 2803 struct mlx5e_params *params = &priv->channels.params;
2e20a151 2804 struct net_device *netdev = priv->netdev;
472a1e44 2805 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff
SM		 2806 u16 mtu;
2807 int err;
2808
472a1e44 2809 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
cd255eff
SM		 2810 if (err)
2811 return err;
40ab6a6e 2812
472a1e44
TT		 2813 mlx5e_query_mtu(mdev, params, &mtu);
2814 if (mtu != params->sw_mtu)
cd255eff 2815 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
472a1e44 2816 __func__, mtu, params->sw_mtu);
40ab6a6e 2817
472a1e44 2818 params->sw_mtu = mtu;
40ab6a6e
AS		 2819 return 0;
2820}
2821
08fb1dac
SM		 2822static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2823{
2824 struct mlx5e_priv *priv = netdev_priv(netdev);
6a9764ef
SM		 2825 int nch = priv->channels.params.num_channels;
2826 int ntc = priv->channels.params.num_tc;
08fb1dac
SM		 2827 int tc;
2828
2829 netdev_reset_tc(netdev);
2830
2831 if (ntc == 1)
2832 return;
2833
2834 netdev_set_num_tc(netdev, ntc);
2835
7ccdd084
RS		 2836 /* Map netdev TCs to offset 0
2837 * We have our own UP to TXQ mapping for QoS
2838 */
08fb1dac 2839 for (tc = 0; tc < ntc; tc++)
7ccdd084 2840 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2841}
2842
8bfaf07f 2843static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
acc6c595 2844{
8bfaf07f 2845 int max_nch = priv->profile->max_nch(priv->mdev);
acc6c595
SM		 2846 int i, tc;
2847
8bfaf07f 2848 for (i = 0; i < max_nch; i++)
acc6c595 2849 for (tc = 0; tc < priv->profile->max_tc; tc++)
8bfaf07f
EBE		 2850 priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2851}
2852
2853static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2854{
2855 struct mlx5e_channel *c;
2856 struct mlx5e_txqsq *sq;
2857 int i, tc;
acc6c595
SM		 2858
2859 for (i = 0; i < priv->channels.num; i++) {
2860 c = priv->channels.c[i];
2861 for (tc = 0; tc < c->num_tc; tc++) {
2862 sq = &c->sq[tc];
2863 priv->txq2sq[sq->txq_ix] = sq;
2864 }
2865 }
2866}
2867
603f4a45 2868void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2869{
9008ae07
SM		 2870 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2871 struct net_device *netdev = priv->netdev;
2872
2873 mlx5e_netdev_set_tcs(netdev);
053ee0a7
TR		 2874 netif_set_real_num_tx_queues(netdev, num_txqs);
2875 netif_set_real_num_rx_queues(netdev, priv->channels.num);
9008ae07 2876
8bfaf07f 2877 mlx5e_build_tx2sq_maps(priv);
acc6c595
SM		 2878 mlx5e_activate_channels(&priv->channels);
2879 netif_tx_start_all_queues(priv->netdev);
9008ae07 2880
733d3e54 2881 if (MLX5_ESWITCH_MANAGER(priv->mdev))
9008ae07
SM		 2882 mlx5e_add_sqs_fwd_rules(priv);
2883
acc6c595 2884 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
9008ae07 2885 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
acc6c595
SM		 2886}
2887
603f4a45 2888void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2889{
9008ae07
SM		 2890 mlx5e_redirect_rqts_to_drop(priv);
2891
733d3e54 2892 if (MLX5_ESWITCH_MANAGER(priv->mdev))
9008ae07
SM		 2893 mlx5e_remove_sqs_fwd_rules(priv);
2894
acc6c595
SM		 2895 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2896 * polling for inactive tx queues.
2897 */
2898 netif_tx_stop_all_queues(priv->netdev);
2899 netif_tx_disable(priv->netdev);
2900 mlx5e_deactivate_channels(&priv->channels);
2901}
2902
55c2503d 2903void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2e20a151
SM		 2904 struct mlx5e_channels *new_chs,
2905 mlx5e_fp_hw_modify hw_modify)
55c2503d
SM		 2906{
2907 struct net_device *netdev = priv->netdev;
2908 int new_num_txqs;
7ca42c80 2909 int carrier_ok;
55c2503d
SM		 2910 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2911
7ca42c80 2912 carrier_ok = netif_carrier_ok(netdev);
55c2503d
SM		 2913 netif_carrier_off(netdev);
2914
2915 if (new_num_txqs < netdev->real_num_tx_queues)
2916 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2917
2918 mlx5e_deactivate_priv_channels(priv);
2919 mlx5e_close_channels(&priv->channels);
2920
2921 priv->channels = *new_chs;
2922
2e20a151
SM		 2923 /* New channels are ready to roll, modify HW settings if needed */
2924 if (hw_modify)
2925 hw_modify(priv);
2926
55c2503d
SM		 2927 mlx5e_refresh_tirs(priv, false);
2928 mlx5e_activate_priv_channels(priv);
2929
7ca42c80
ES		 2930 /* return carrier back if needed */
2931 if (carrier_ok)
2932 netif_carrier_on(netdev);
55c2503d
SM		 2933}
2934
237f258c 2935void mlx5e_timestamp_init(struct mlx5e_priv *priv)
7c39afb3
FD		 2936{
2937 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2938 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2939}
2940
40ab6a6e
AS		 2941int mlx5e_open_locked(struct net_device *netdev)
2942{
2943 struct mlx5e_priv *priv = netdev_priv(netdev);
40ab6a6e
AS		 2944 int err;
2945
2946 set_bit(MLX5E_STATE_OPENED, &priv->state);
2947
ff9c852f 2948 err = mlx5e_open_channels(priv, &priv->channels);
acc6c595 2949 if (err)
343b29f3 2950 goto err_clear_state_opened_flag;
40ab6a6e 2951
b676f653 2952 mlx5e_refresh_tirs(priv, false);
acc6c595 2953 mlx5e_activate_priv_channels(priv);
7ca42c80
ES		 2954 if (priv->profile->update_carrier)
2955 priv->profile->update_carrier(priv);
be4891af 2956
cb67b832
HHZ		 2957 if (priv->profile->update_stats)
2958 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2959
9b37b07f 2960 return 0;
343b29f3
AS		 2961
2962err_clear_state_opened_flag:
2963 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2964 return err;
40ab6a6e
AS		 2965}
2966
cb67b832 2967int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2968{
2969 struct mlx5e_priv *priv = netdev_priv(netdev);
2970 int err;
2971
2972 mutex_lock(&priv->state_lock);
2973 err = mlx5e_open_locked(netdev);
63bfd399
EBE		 2974 if (!err)
2975 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
40ab6a6e
AS		 2976 mutex_unlock(&priv->state_lock);
2977
358aa5ce 2978 if (mlx5_vxlan_allowed(priv->mdev->vxlan))
a117f73d
SK		 2979 udp_tunnel_get_rx_info(netdev);
2980
40ab6a6e
AS		 2981 return err;
2982}
2983
2984int mlx5e_close_locked(struct net_device *netdev)
2985{
2986 struct mlx5e_priv *priv = netdev_priv(netdev);
2987
a1985740
AS		 2988 /* May already be CLOSED in case a previous configuration operation
2989 * (e.g RX/TX queue size change) that involves close&open failed.
2990 */
2991 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2992 return 0;
2993
40ab6a6e
AS		 2994 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2995
40ab6a6e 2996 netif_carrier_off(priv->netdev);
acc6c595
SM		 2997 mlx5e_deactivate_priv_channels(priv);
2998 mlx5e_close_channels(&priv->channels);
40ab6a6e
AS		 2999
3000 return 0;
3001}
3002
cb67b832 3003int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 3004{
3005 struct mlx5e_priv *priv = netdev_priv(netdev);
3006 int err;
3007
26e59d80
MHY		 3008 if (!netif_device_present(netdev))
3009 return -ENODEV;
3010
40ab6a6e 3011 mutex_lock(&priv->state_lock);
63bfd399 3012 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
40ab6a6e
AS		 3013 err = mlx5e_close_locked(netdev);
3014 mutex_unlock(&priv->state_lock);
3015
3016 return err;
3017}
3018
a43b25da 3019static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3b77235b
SM		 3020 struct mlx5e_rq *rq,
3021 struct mlx5e_rq_param *param)
40ab6a6e 3022{
40ab6a6e
AS		 3023 void *rqc = param->rqc;
3024 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3025 int err;
3026
3027 param->wq.db_numa_node = param->wq.buf_numa_node;
3028
99cbfa93
TT		 3029 err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3030 &rq->wq_ctrl);
40ab6a6e
AS		 3031 if (err)
3032 return err;
3033
0ddf5432
JDB		 3034 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3035 xdp_rxq_info_unused(&rq->xdp_rxq);
3036
a43b25da 3037 rq->mdev = mdev;
40ab6a6e
AS		 3038
3039 return 0;
3040}
3041
a43b25da 3042static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3b77235b
SM		 3043 struct mlx5e_cq *cq,
3044 struct mlx5e_cq_param *param)
40ab6a6e 3045{
2f0db879
GP		 3046 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3047 param->wq.db_numa_node = dev_to_node(&mdev->pdev->dev);
3048
95b6c6a5 3049 return mlx5e_alloc_cq_common(mdev, param, cq);
40ab6a6e
AS		 3050}
3051
1462e48d
RD		 3052int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3053 struct mlx5e_rq *drop_rq)
40ab6a6e 3054{
7cbaf9a3 3055 struct mlx5_core_dev *mdev = priv->mdev;
a43b25da
SM		 3056 struct mlx5e_cq_param cq_param = {};
3057 struct mlx5e_rq_param rq_param = {};
3058 struct mlx5e_cq *cq = &drop_rq->cq;
40ab6a6e
AS		 3059 int err;
3060
7cbaf9a3 3061 mlx5e_build_drop_rq_param(priv, &rq_param);
40ab6a6e 3062
a43b25da 3063 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
40ab6a6e
AS		 3064 if (err)
3065 return err;
3066
3b77235b 3067 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 3068 if (err)
3b77235b 3069 goto err_free_cq;
40ab6a6e 3070
a43b25da 3071 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
40ab6a6e 3072 if (err)
3b77235b 3073 goto err_destroy_cq;
40ab6a6e 3074
a43b25da 3075 err = mlx5e_create_rq(drop_rq, &rq_param);
40ab6a6e 3076 if (err)
3b77235b 3077 goto err_free_rq;
40ab6a6e 3078
7cbaf9a3
MS		 3079 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3080 if (err)
3081 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3082
40ab6a6e
AS		 3083 return 0;
3084
3b77235b 3085err_free_rq:
a43b25da 3086 mlx5e_free_rq(drop_rq);
40ab6a6e
AS		 3087
3088err_destroy_cq:
a43b25da 3089 mlx5e_destroy_cq(cq);
40ab6a6e 3090
3b77235b 3091err_free_cq:
a43b25da 3092 mlx5e_free_cq(cq);
3b77235b 3093
40ab6a6e
AS		 3094 return err;
3095}
3096
1462e48d 3097void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
40ab6a6e 3098{
a43b25da
SM		 3099 mlx5e_destroy_rq(drop_rq);
3100 mlx5e_free_rq(drop_rq);
3101 mlx5e_destroy_cq(&drop_rq->cq);
3102 mlx5e_free_cq(&drop_rq->cq);
40ab6a6e
AS		 3103}
3104
5426a0b2
SM		 3105int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3106 u32 underlay_qpn, u32 *tisn)
40ab6a6e 3107{
c4f287c4 3108 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 3109 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3110
08fb1dac 3111 MLX5_SET(tisc, tisc, prio, tc << 1);
5426a0b2 3112 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
b50d292b 3113 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 3114
3115 if (mlx5_lag_is_lacp_owner(mdev))
3116 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3117
5426a0b2 3118 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
40ab6a6e
AS		 3119}
3120
5426a0b2 3121void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
40ab6a6e 3122{
5426a0b2 3123 mlx5_core_destroy_tis(mdev, tisn);
40ab6a6e
AS		 3124}
3125
cb67b832 3126int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 3127{
3128 int err;
3129 int tc;
3130
6bfd390b 3131 for (tc = 0; tc < priv->profile->max_tc; tc++) {
5426a0b2 3132 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
40ab6a6e
AS		 3133 if (err)
3134 goto err_close_tises;
3135 }
3136
3137 return 0;
3138
3139err_close_tises:
3140 for (tc--; tc >= 0; tc--)
5426a0b2 3141 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 3142
3143 return err;
3144}
3145
cb67b832 3146void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 3147{
3148 int tc;
3149
6bfd390b 3150 for (tc = 0; tc < priv->profile->max_tc; tc++)
5426a0b2 3151 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 3152}
3153
6a9764ef
SM		 3154static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3155 enum mlx5e_traffic_types tt,
3156 u32 *tirc)
f62b8bb8 3157{
b50d292b 3158 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 3159
6a9764ef 3160 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
f62b8bb8 3161
4cbeaff5 3162 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 3163 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
7b3722fa 3164 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
f62b8bb8
AV		 3165}
3166
6a9764ef 3167static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
f62b8bb8 3168{
b50d292b 3169 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696 3170
6a9764ef 3171 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
1da36696
TT		 3172
3173 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3174 MLX5_SET(tirc, tirc, indirect_table, rqtn);
3175 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3176}
3177
8f493ffd 3178int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 3179{
724b2aa1 3180 struct mlx5e_tir *tir;
f62b8bb8
AV		 3181 void *tirc;
3182 int inlen;
7b3722fa 3183 int i = 0;
f62b8bb8 3184 int err;
1da36696 3185 u32 *in;
1da36696 3186 int tt;
f62b8bb8
AV		 3187
3188 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 3189 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 3190 if (!in)
3191 return -ENOMEM;
3192
1da36696
TT		 3193 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3194 memset(in, 0, inlen);
724b2aa1 3195 tir = &priv->indir_tir[tt];
1da36696 3196 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 3197 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
724b2aa1 3198 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
7b3722fa
GP		 3199 if (err) {
3200 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3201 goto err_destroy_inner_tirs;
3202 }
f62b8bb8
AV		 3203 }
3204
7b3722fa
GP		 3205 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3206 goto out;
3207
3208 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3209 memset(in, 0, inlen);
3210 tir = &priv->inner_indir_tir[i];
3211 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3212 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3213 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3214 if (err) {
3215 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3216 goto err_destroy_inner_tirs;
3217 }
3218 }
3219
3220out:
6bfd390b
HHZ		 3221 kvfree(in);
3222
3223 return 0;
3224
7b3722fa
GP		 3225err_destroy_inner_tirs:
3226 for (i--; i >= 0; i--)
3227 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3228
6bfd390b
HHZ		 3229 for (tt--; tt >= 0; tt--)
3230 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3231
3232 kvfree(in);
3233
3234 return err;
3235}
3236
cb67b832 3237int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 3238{
3239 int nch = priv->profile->max_nch(priv->mdev);
3240 struct mlx5e_tir *tir;
3241 void *tirc;
3242 int inlen;
3243 int err;
3244 u32 *in;
3245 int ix;
3246
3247 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 3248 in = kvzalloc(inlen, GFP_KERNEL);
6bfd390b
HHZ		 3249 if (!in)
3250 return -ENOMEM;
3251
1da36696
TT		 3252 for (ix = 0; ix < nch; ix++) {
3253 memset(in, 0, inlen);
724b2aa1 3254 tir = &priv->direct_tir[ix];
1da36696 3255 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 3256 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
724b2aa1 3257 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 3258 if (err)
3259 goto err_destroy_ch_tirs;
3260 }
3261
3262 kvfree(in);
3263
f62b8bb8
AV		 3264 return 0;
3265
1da36696 3266err_destroy_ch_tirs:
8f493ffd 3267 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
1da36696 3268 for (ix--; ix >= 0; ix--)
724b2aa1 3269 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 3270
1da36696 3271 kvfree(in);
f62b8bb8
AV		 3272
3273 return err;
3274}
3275
8f493ffd 3276void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 3277{
3278 int i;
3279
1da36696 3280 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 3281 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
7b3722fa
GP		 3282
3283 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3284 return;
3285
3286 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3287 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
f62b8bb8
AV		 3288}
3289
cb67b832 3290void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 3291{
3292 int nch = priv->profile->max_nch(priv->mdev);
3293 int i;
3294
3295 for (i = 0; i < nch; i++)
3296 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3297}
3298
102722fc
GE		 3299static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3300{
3301 int err = 0;
3302 int i;
3303
3304 for (i = 0; i < chs->num; i++) {
3305 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3306 if (err)
3307 return err;
3308 }
3309
3310 return 0;
3311}
3312
f6d96a20 3313static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
36350114
GP		 3314{
3315 int err = 0;
3316 int i;
3317
ff9c852f
SM		 3318 for (i = 0; i < chs->num; i++) {
3319 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
36350114
GP		 3320 if (err)
3321 return err;
3322 }
3323
3324 return 0;
3325}
3326
0cf0f6d3
JP		 3327static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3328 struct tc_mqprio_qopt *mqprio)
08fb1dac
SM		 3329{
3330 struct mlx5e_priv *priv = netdev_priv(netdev);
6f9485af 3331 struct mlx5e_channels new_channels = {};
0cf0f6d3 3332 u8 tc = mqprio->num_tc;
08fb1dac
SM		 3333 int err = 0;
3334
0cf0f6d3
JP		 3335 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3336
08fb1dac
SM		 3337 if (tc && tc != MLX5E_MAX_NUM_TC)
3338 return -EINVAL;
3339
3340 mutex_lock(&priv->state_lock);
3341
6f9485af
SM		 3342 new_channels.params = priv->channels.params;
3343 new_channels.params.num_tc = tc ? tc : 1;
08fb1dac 3344
20b6a1c7 3345 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6f9485af
SM		 3346 priv->channels.params = new_channels.params;
3347 goto out;
3348 }
08fb1dac 3349
6f9485af
SM		 3350 err = mlx5e_open_channels(priv, &new_channels);
3351 if (err)
3352 goto out;
08fb1dac 3353
05909bab
EBE		 3354 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3355 new_channels.params.num_tc);
2e20a151 3356 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
6f9485af 3357out:
08fb1dac 3358 mutex_unlock(&priv->state_lock);
08fb1dac
SM		 3359 return err;
3360}
3361
e80541ec 3362#ifdef CONFIG_MLX5_ESWITCH
d6c862ba 3363static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
60bd4af8
OG		 3364 struct tc_cls_flower_offload *cls_flower,
3365 int flags)
08fb1dac 3366{
0cf0f6d3
JP		 3367 switch (cls_flower->command) {
3368 case TC_CLSFLOWER_REPLACE:
60bd4af8 3369 return mlx5e_configure_flower(priv, cls_flower, flags);
0cf0f6d3 3370 case TC_CLSFLOWER_DESTROY:
60bd4af8 3371 return mlx5e_delete_flower(priv, cls_flower, flags);
0cf0f6d3 3372 case TC_CLSFLOWER_STATS:
60bd4af8 3373 return mlx5e_stats_flower(priv, cls_flower, flags);
0cf0f6d3 3374 default:
a5fcf8a6 3375 return -EOPNOTSUPP;
0cf0f6d3
JP		 3376 }
3377}
d6c862ba 3378
60bd4af8
OG		 3379static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3380 void *cb_priv)
d6c862ba
JP		 3381{
3382 struct mlx5e_priv *priv = cb_priv;
3383
9ab88e83 3384 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
44ae12a7
JP		 3385 return -EOPNOTSUPP;
3386
d6c862ba
JP		 3387 switch (type) {
3388 case TC_SETUP_CLSFLOWER:
60bd4af8 3389 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS);
d6c862ba
JP		 3390 default:
3391 return -EOPNOTSUPP;
3392 }
3393}
3394
3395static int mlx5e_setup_tc_block(struct net_device *dev,
3396 struct tc_block_offload *f)
3397{
3398 struct mlx5e_priv *priv = netdev_priv(dev);
3399
3400 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3401 return -EOPNOTSUPP;
3402
3403 switch (f->command) {
3404 case TC_BLOCK_BIND:
3405 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
60513bd8 3406 priv, priv, f->extack);
d6c862ba
JP		 3407 case TC_BLOCK_UNBIND:
3408 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3409 priv);
3410 return 0;
3411 default:
3412 return -EOPNOTSUPP;
3413 }
3414}
e80541ec 3415#endif
a5fcf8a6 3416
9afe9a53
OG		 3417static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3418 void *type_data)
0cf0f6d3 3419{
2572ac53 3420 switch (type) {
fde6af47 3421#ifdef CONFIG_MLX5_ESWITCH
d6c862ba
JP		 3422 case TC_SETUP_BLOCK:
3423 return mlx5e_setup_tc_block(dev, type_data);
fde6af47 3424#endif
575ed7d3 3425 case TC_SETUP_QDISC_MQPRIO:
de4784ca 3426 return mlx5e_setup_tc_mqprio(dev, type_data);
e8f887ac
AV		 3427 default:
3428 return -EOPNOTSUPP;
3429 }
08fb1dac
SM		 3430}
3431
bc1f4470 3432static void
f62b8bb8
AV		 3433mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3434{
3435 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 3436 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 3437 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 3438 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 3439
ed56c519
SM		 3440 /* update HW stats in background for next time */
3441 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
3442
370bad0f
OG		 3443 if (mlx5e_is_uplink_rep(priv)) {
3444 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3445 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3446 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3447 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3448 } else {
868a01a2 3449 mlx5e_grp_sw_update_stats(priv);
370bad0f
OG		 3450 stats->rx_packets = sstats->rx_packets;
3451 stats->rx_bytes = sstats->rx_bytes;
3452 stats->tx_packets = sstats->tx_packets;
3453 stats->tx_bytes = sstats->tx_bytes;
3454 stats->tx_dropped = sstats->tx_queue_dropped;
3455 }
269e6b3a
GP		 3456
3457 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 3458
3459 stats->rx_length_errors =
9218b44d
GP		 3460 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3461 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3462 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 3463 stats->rx_crc_errors =
9218b44d
GP		 3464 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3465 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3466 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a
GP		 3467 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3468 stats->rx_frame_errors;
3469 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3470
3471 /* vport multicast also counts packets that are dropped due to steering
3472 * or rx out of buffer
3473 */
9218b44d
GP		 3474 stats->multicast =
3475 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 3476}
3477
3478static void mlx5e_set_rx_mode(struct net_device *dev)
3479{
3480 struct mlx5e_priv *priv = netdev_priv(dev);
3481
7bb29755 3482 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3483}
3484
3485static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3486{
3487 struct mlx5e_priv *priv = netdev_priv(netdev);
3488 struct sockaddr *saddr = addr;
3489
3490 if (!is_valid_ether_addr(saddr->sa_data))
3491 return -EADDRNOTAVAIL;
3492
3493 netif_addr_lock_bh(netdev);
3494 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3495 netif_addr_unlock_bh(netdev);
3496
7bb29755 3497 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3498
3499 return 0;
3500}
3501
75b81ce7 3502#define MLX5E_SET_FEATURE(features, feature, enable) \
0e405443
GP		 3503 do { \
3504 if (enable) \
75b81ce7 3505 *features |= feature; \
0e405443 3506 else \
75b81ce7 3507 *features &= ~feature; \
0e405443
GP		 3508 } while (0)
3509
3510typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3511
3512static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 3513{
3514 struct mlx5e_priv *priv = netdev_priv(netdev);
619a8f2a 3515 struct mlx5_core_dev *mdev = priv->mdev;
2e20a151 3516 struct mlx5e_channels new_channels = {};
619a8f2a 3517 struct mlx5e_params *old_params;
2e20a151
SM		 3518 int err = 0;
3519 bool reset;
f62b8bb8
AV		 3520
3521 mutex_lock(&priv->state_lock);
f62b8bb8 3522
619a8f2a 3523 old_params = &priv->channels.params;
6c3a823e
TT		 3524 if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3525 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3526 err = -EINVAL;
3527 goto out;
3528 }
3529
619a8f2a 3530 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3531
619a8f2a 3532 new_channels.params = *old_params;
2e20a151
SM		 3533 new_channels.params.lro_en = enable;
3534
99cbfa93 3535 if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
619a8f2a
TT		 3536 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3537 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3538 reset = false;
3539 }
3540
2e20a151 3541 if (!reset) {
619a8f2a 3542 *old_params = new_channels.params;
2e20a151
SM		 3543 err = mlx5e_modify_tirs_lro(priv);
3544 goto out;
98e81b0a 3545 }
f62b8bb8 3546
2e20a151
SM		 3547 err = mlx5e_open_channels(priv, &new_channels);
3548 if (err)
3549 goto out;
0e405443 3550
2e20a151
SM		 3551 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3552out:
9b37b07f 3553 mutex_unlock(&priv->state_lock);
0e405443
GP		 3554 return err;
3555}
3556
2b52a283 3557static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
0e405443
GP		 3558{
3559 struct mlx5e_priv *priv = netdev_priv(netdev);
3560
3561 if (enable)
2b52a283 3562 mlx5e_enable_cvlan_filter(priv);
0e405443 3563 else
2b52a283 3564 mlx5e_disable_cvlan_filter(priv);
0e405443
GP		 3565
3566 return 0;
3567}
3568
3569static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3570{
3571 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 3572
0e405443 3573 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 3574 netdev_err(netdev,
3575 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3576 return -EINVAL;
3577 }
3578
0e405443
GP		 3579 return 0;
3580}
3581
94cb1ebb
EBE		 3582static int set_feature_rx_all(struct net_device *netdev, bool enable)
3583{
3584 struct mlx5e_priv *priv = netdev_priv(netdev);
3585 struct mlx5_core_dev *mdev = priv->mdev;
3586
3587 return mlx5_set_port_fcs(mdev, !enable);
3588}
3589
102722fc
GE		 3590static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3591{
3592 struct mlx5e_priv *priv = netdev_priv(netdev);
3593 int err;
3594
3595 mutex_lock(&priv->state_lock);
3596
3597 priv->channels.params.scatter_fcs_en = enable;
3598 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3599 if (err)
3600 priv->channels.params.scatter_fcs_en = !enable;
3601
3602 mutex_unlock(&priv->state_lock);
3603
3604 return err;
3605}
3606
36350114
GP		 3607static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3608{
3609 struct mlx5e_priv *priv = netdev_priv(netdev);
ff9c852f 3610 int err = 0;
36350114
GP		 3611
3612 mutex_lock(&priv->state_lock);
3613
6a9764ef 3614 priv->channels.params.vlan_strip_disable = !enable;
ff9c852f
SM		 3615 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3616 goto unlock;
3617
3618 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
36350114 3619 if (err)
6a9764ef 3620 priv->channels.params.vlan_strip_disable = enable;
36350114 3621
ff9c852f 3622unlock:
36350114
GP		 3623 mutex_unlock(&priv->state_lock);
3624
3625 return err;
3626}
3627
ec080045 3628#ifdef CONFIG_MLX5_EN_ARFS
45bf454a
MG		 3629static int set_feature_arfs(struct net_device *netdev, bool enable)
3630{
3631 struct mlx5e_priv *priv = netdev_priv(netdev);
3632 int err;
3633
3634 if (enable)
3635 err = mlx5e_arfs_enable(priv);
3636 else
3637 err = mlx5e_arfs_disable(priv);
3638
3639 return err;
3640}
3641#endif
3642
0e405443 3643static int mlx5e_handle_feature(struct net_device *netdev,
75b81ce7 3644 netdev_features_t *features,
0e405443
GP		 3645 netdev_features_t wanted_features,
3646 netdev_features_t feature,
3647 mlx5e_feature_handler feature_handler)
3648{
3649 netdev_features_t changes = wanted_features ^ netdev->features;
3650 bool enable = !!(wanted_features & feature);
3651 int err;
3652
3653 if (!(changes & feature))
3654 return 0;
3655
3656 err = feature_handler(netdev, enable);
3657 if (err) {
b20eab15
GP		 3658 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3659 enable ? "Enable" : "Disable", &feature, err);
0e405443
GP		 3660 return err;
3661 }
3662
75b81ce7 3663 MLX5E_SET_FEATURE(features, feature, enable);
0e405443
GP		 3664 return 0;
3665}
3666
3667static int mlx5e_set_features(struct net_device *netdev,
3668 netdev_features_t features)
3669{
75b81ce7 3670 netdev_features_t oper_features = netdev->features;
be0f780b
GP		 3671 int err = 0;
3672
3673#define MLX5E_HANDLE_FEATURE(feature, handler) \
3674 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
0e405443 3675
be0f780b
GP		 3676 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3677 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
2b52a283 3678 set_feature_cvlan_filter);
be0f780b
GP		 3679 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3680 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3681 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3682 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
ec080045 3683#ifdef CONFIG_MLX5_EN_ARFS
be0f780b 3684 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
45bf454a 3685#endif
0e405443 3686
75b81ce7
GP		 3687 if (err) {
3688 netdev->features = oper_features;
3689 return -EINVAL;
3690 }
3691
3692 return 0;
f62b8bb8
AV		 3693}
3694
7d92d580
GP		 3695static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3696 netdev_features_t features)
3697{
3698 struct mlx5e_priv *priv = netdev_priv(netdev);
6c3a823e 3699 struct mlx5e_params *params;
7d92d580
GP		 3700
3701 mutex_lock(&priv->state_lock);
6c3a823e 3702 params = &priv->channels.params;
7d92d580
GP		 3703 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3704 /* HW strips the outer C-tag header, this is a problem
3705 * for S-tag traffic.
3706 */
3707 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
6c3a823e 3708 if (!params->vlan_strip_disable)
7d92d580
GP		 3709 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3710 }
6c3a823e
TT		 3711 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3712 features &= ~NETIF_F_LRO;
3713 if (params->lro_en)
3714 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3715 }
3716
7d92d580
GP		 3717 mutex_unlock(&priv->state_lock);
3718
3719 return features;
3720}
3721
250a42b6
AN		 3722int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3723 change_hw_mtu_cb set_mtu_cb)
f62b8bb8
AV		 3724{
3725 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151 3726 struct mlx5e_channels new_channels = {};
472a1e44 3727 struct mlx5e_params *params;
98e81b0a 3728 int err = 0;
506753b0 3729 bool reset;
f62b8bb8 3730
f62b8bb8 3731 mutex_lock(&priv->state_lock);
98e81b0a 3732
472a1e44 3733 params = &priv->channels.params;
506753b0 3734
73281b78 3735 reset = !params->lro_en;
2e20a151 3736 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3737
73281b78
TT		 3738 new_channels.params = *params;
3739 new_channels.params.sw_mtu = new_mtu;
3740
a26a5bdf
TT		 3741 if (params->xdp_prog &&
3742 !mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
3743 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3744 new_mtu, MLX5E_XDP_MAX_MTU);
3745 err = -EINVAL;
3746 goto out;
3747 }
3748
99cbfa93 3749 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
73281b78
TT		 3750 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3751 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3752
3753 reset = reset && (ppw_old != ppw_new);
3754 }
3755
2e20a151 3756 if (!reset) {
472a1e44 3757 params->sw_mtu = new_mtu;
eacecf27
AN		 3758 if (set_mtu_cb)
3759 set_mtu_cb(priv);
472a1e44 3760 netdev->mtu = params->sw_mtu;
2e20a151
SM		 3761 goto out;
3762 }
98e81b0a 3763
2e20a151 3764 err = mlx5e_open_channels(priv, &new_channels);
472a1e44 3765 if (err)
2e20a151 3766 goto out;
2e20a151 3767
250a42b6 3768 mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb);
472a1e44 3769 netdev->mtu = new_channels.params.sw_mtu;
f62b8bb8 3770
2e20a151
SM		 3771out:
3772 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 3773 return err;
3774}
3775
250a42b6
AN		 3776static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3777{
3778 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3779}
3780
7c39afb3
FD		 3781int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3782{
3783 struct hwtstamp_config config;
3784 int err;
3785
6dbc80ca
MS		 3786 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3787 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
7c39afb3
FD		 3788 return -EOPNOTSUPP;
3789
3790 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3791 return -EFAULT;
3792
3793 /* TX HW timestamp */
3794 switch (config.tx_type) {
3795 case HWTSTAMP_TX_OFF:
3796 case HWTSTAMP_TX_ON:
3797 break;
3798 default:
3799 return -ERANGE;
3800 }
3801
3802 mutex_lock(&priv->state_lock);
3803 /* RX HW timestamp */
3804 switch (config.rx_filter) {
3805 case HWTSTAMP_FILTER_NONE:
3806 /* Reset CQE compression to Admin default */
3807 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3808 break;
3809 case HWTSTAMP_FILTER_ALL:
3810 case HWTSTAMP_FILTER_SOME:
3811 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3812 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3813 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3814 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3815 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3816 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3817 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3818 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3819 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3820 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3821 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3822 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3823 case HWTSTAMP_FILTER_NTP_ALL:
3824 /* Disable CQE compression */
3825 netdev_warn(priv->netdev, "Disabling cqe compression");
3826 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3827 if (err) {
3828 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3829 mutex_unlock(&priv->state_lock);
3830 return err;
3831 }
3832 config.rx_filter = HWTSTAMP_FILTER_ALL;
3833 break;
3834 default:
3835 mutex_unlock(&priv->state_lock);
3836 return -ERANGE;
3837 }
3838
3839 memcpy(&priv->tstamp, &config, sizeof(config));
3840 mutex_unlock(&priv->state_lock);
3841
3842 return copy_to_user(ifr->ifr_data, &config,
3843 sizeof(config)) ? -EFAULT : 0;
3844}
3845
3846int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3847{
3848 struct hwtstamp_config *cfg = &priv->tstamp;
3849
3850 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3851 return -EOPNOTSUPP;
3852
3853 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3854}
3855
ef9814de
EBE		 3856static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3857{
1170fbd8
FD		 3858 struct mlx5e_priv *priv = netdev_priv(dev);
3859
ef9814de
EBE		 3860 switch (cmd) {
3861 case SIOCSHWTSTAMP:
1170fbd8 3862 return mlx5e_hwstamp_set(priv, ifr);
ef9814de 3863 case SIOCGHWTSTAMP:
1170fbd8 3864 return mlx5e_hwstamp_get(priv, ifr);
ef9814de
EBE		 3865 default:
3866 return -EOPNOTSUPP;
3867 }
3868}
3869
e80541ec 3870#ifdef CONFIG_MLX5_ESWITCH
66e49ded
SM		 3871static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3872{
3873 struct mlx5e_priv *priv = netdev_priv(dev);
3874 struct mlx5_core_dev *mdev = priv->mdev;
3875
3876 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3877}
3878
79aab093
MS		 3879static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3880 __be16 vlan_proto)
66e49ded
SM		 3881{
3882 struct mlx5e_priv *priv = netdev_priv(dev);
3883 struct mlx5_core_dev *mdev = priv->mdev;
3884
79aab093
MS		 3885 if (vlan_proto != htons(ETH_P_8021Q))
3886 return -EPROTONOSUPPORT;
3887
66e49ded
SM		 3888 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3889 vlan, qos);
3890}
3891
f942380c
MHY		 3892static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3893{
3894 struct mlx5e_priv *priv = netdev_priv(dev);
3895 struct mlx5_core_dev *mdev = priv->mdev;
3896
3897 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3898}
3899
1edc57e2
MHY		 3900static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3901{
3902 struct mlx5e_priv *priv = netdev_priv(dev);
3903 struct mlx5_core_dev *mdev = priv->mdev;
3904
3905 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3906}
bd77bf1c
MHY		 3907
3908static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3909 int max_tx_rate)
3910{
3911 struct mlx5e_priv *priv = netdev_priv(dev);
3912 struct mlx5_core_dev *mdev = priv->mdev;
3913
bd77bf1c 3914 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3915 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3916}
3917
66e49ded
SM		 3918static int mlx5_vport_link2ifla(u8 esw_link)
3919{
3920 switch (esw_link) {
cc9c82a8 3921 case MLX5_VPORT_ADMIN_STATE_DOWN:
66e49ded 3922 return IFLA_VF_LINK_STATE_DISABLE;
cc9c82a8 3923 case MLX5_VPORT_ADMIN_STATE_UP:
66e49ded
SM		 3924 return IFLA_VF_LINK_STATE_ENABLE;
3925 }
3926 return IFLA_VF_LINK_STATE_AUTO;
3927}
3928
3929static int mlx5_ifla_link2vport(u8 ifla_link)
3930{
3931 switch (ifla_link) {
3932 case IFLA_VF_LINK_STATE_DISABLE:
cc9c82a8 3933 return MLX5_VPORT_ADMIN_STATE_DOWN;
66e49ded 3934 case IFLA_VF_LINK_STATE_ENABLE:
cc9c82a8 3935 return MLX5_VPORT_ADMIN_STATE_UP;
66e49ded 3936 }
cc9c82a8 3937 return MLX5_VPORT_ADMIN_STATE_AUTO;
66e49ded
SM		 3938}
3939
3940static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3941 int link_state)
3942{
3943 struct mlx5e_priv *priv = netdev_priv(dev);
3944 struct mlx5_core_dev *mdev = priv->mdev;
3945
3946 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3947 mlx5_ifla_link2vport(link_state));
3948}
3949
3950static int mlx5e_get_vf_config(struct net_device *dev,
3951 int vf, struct ifla_vf_info *ivi)
3952{
3953 struct mlx5e_priv *priv = netdev_priv(dev);
3954 struct mlx5_core_dev *mdev = priv->mdev;
3955 int err;
3956
3957 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3958 if (err)
3959 return err;
3960 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3961 return 0;
3962}
3963
3964static int mlx5e_get_vf_stats(struct net_device *dev,
3965 int vf, struct ifla_vf_stats *vf_stats)
3966{
3967 struct mlx5e_priv *priv = netdev_priv(dev);
3968 struct mlx5_core_dev *mdev = priv->mdev;
3969
3970 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3971 vf_stats);
3972}
e80541ec 3973#endif
66e49ded 3974
dccea6bf
SM		 3975struct mlx5e_vxlan_work {
3976 struct work_struct work;
3977 struct mlx5e_priv *priv;
3978 u16 port;
3979};
3980
3981static void mlx5e_vxlan_add_work(struct work_struct *work)
3982{
3983 struct mlx5e_vxlan_work *vxlan_work =
3984 container_of(work, struct mlx5e_vxlan_work, work);
3985 struct mlx5e_priv *priv = vxlan_work->priv;
3986 u16 port = vxlan_work->port;
3987
3988 mutex_lock(&priv->state_lock);
358aa5ce 3989 mlx5_vxlan_add_port(priv->mdev->vxlan, port);
dccea6bf
SM		 3990 mutex_unlock(&priv->state_lock);
3991
3992 kfree(vxlan_work);
3993}
3994
3995static void mlx5e_vxlan_del_work(struct work_struct *work)
3996{
3997 struct mlx5e_vxlan_work *vxlan_work =
3998 container_of(work, struct mlx5e_vxlan_work, work);
3999 struct mlx5e_priv *priv = vxlan_work->priv;
4000 u16 port = vxlan_work->port;
4001
4002 mutex_lock(&priv->state_lock);
358aa5ce 4003 mlx5_vxlan_del_port(priv->mdev->vxlan, port);
dccea6bf
SM		 4004 mutex_unlock(&priv->state_lock);
4005 kfree(vxlan_work);
4006}
4007
4008static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4009{
4010 struct mlx5e_vxlan_work *vxlan_work;
4011
4012 vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4013 if (!vxlan_work)
4014 return;
4015
4016 if (add)
4017 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4018 else
4019 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4020
4021 vxlan_work->priv = priv;
4022 vxlan_work->port = port;
4023 queue_work(priv->wq, &vxlan_work->work);
4024}
4025
1ad9a00a
PB		 4026static void mlx5e_add_vxlan_port(struct net_device *netdev,
4027 struct udp_tunnel_info *ti)
b3f63c3d
MF		 4028{
4029 struct mlx5e_priv *priv = netdev_priv(netdev);
4030
974c3f30
AD		 4031 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4032 return;
4033
358aa5ce 4034 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
b3f63c3d
MF		 4035 return;
4036
278d7f3d 4037 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 4038}
4039
1ad9a00a
PB		 4040static void mlx5e_del_vxlan_port(struct net_device *netdev,
4041 struct udp_tunnel_info *ti)
b3f63c3d
MF		 4042{
4043 struct mlx5e_priv *priv = netdev_priv(netdev);
4044
974c3f30
AD		 4045 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4046 return;
4047
358aa5ce 4048 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
b3f63c3d
MF		 4049 return;
4050
278d7f3d 4051 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 4052}
4053
27299841
GP		 4054static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4055 struct sk_buff *skb,
4056 netdev_features_t features)
b3f63c3d 4057{
2989ad1e 4058 unsigned int offset = 0;
b3f63c3d 4059 struct udphdr *udph;
27299841
GP		 4060 u8 proto;
4061 u16 port;
b3f63c3d
MF		 4062
4063 switch (vlan_get_protocol(skb)) {
4064 case htons(ETH_P_IP):
4065 proto = ip_hdr(skb)->protocol;
4066 break;
4067 case htons(ETH_P_IPV6):
2989ad1e 4068 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
b3f63c3d
MF		 4069 break;
4070 default:
4071 goto out;
4072 }
4073
27299841
GP		 4074 switch (proto) {
4075 case IPPROTO_GRE:
4076 return features;
4077 case IPPROTO_UDP:
b3f63c3d
MF		 4078 udph = udp_hdr(skb);
4079 port = be16_to_cpu(udph->dest);
b3f63c3d 4080
27299841 4081 /* Verify if UDP port is being offloaded by HW */
358aa5ce 4082 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
27299841
GP		 4083 return features;
4084 }
b3f63c3d
MF		 4085
4086out:
4087 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4088 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4089}
4090
4091static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4092 struct net_device *netdev,
4093 netdev_features_t features)
4094{
4095 struct mlx5e_priv *priv = netdev_priv(netdev);
4096
4097 features = vlan_features_check(skb, features);
4098 features = vxlan_features_check(skb, features);
4099
2ac9cfe7
IT		 4100#ifdef CONFIG_MLX5_EN_IPSEC
4101 if (mlx5e_ipsec_feature_check(skb, netdev, features))
4102 return features;
4103#endif
4104
b3f63c3d
MF		 4105 /* Validate if the tunneled packet is being offloaded by HW */
4106 if (skb->encapsulation &&
4107 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
27299841 4108 return mlx5e_tunnel_features_check(priv, skb, features);
b3f63c3d
MF		 4109
4110 return features;
4111}
4112
7ca560b5
EBE		 4113static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
4114 struct mlx5e_txqsq *sq)
4115{
7b2117bb 4116 struct mlx5_eq *eq = sq->cq.mcq.eq;
7ca560b5
EBE		 4117 u32 eqe_count;
4118
7ca560b5 4119 netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
7b2117bb 4120 eq->eqn, eq->cons_index, eq->irqn);
7ca560b5
EBE		 4121
4122 eqe_count = mlx5_eq_poll_irq_disabled(eq);
4123 if (!eqe_count)
4124 return false;
4125
4126 netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
05909bab 4127 sq->channel->stats->eq_rearm++;
7ca560b5
EBE		 4128 return true;
4129}
4130
bfc647d5 4131static void mlx5e_tx_timeout_work(struct work_struct *work)
3947ca18 4132{
bfc647d5
EBE		 4133 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4134 tx_timeout_work);
4135 struct net_device *dev = priv->netdev;
7ca560b5 4136 bool reopen_channels = false;
bfc647d5 4137 int i, err;
3947ca18 4138
bfc647d5
EBE		 4139 rtnl_lock();
4140 mutex_lock(&priv->state_lock);
4141
4142 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4143 goto unlock;
3947ca18 4144
6a9764ef 4145 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
84990945 4146 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
acc6c595 4147 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3947ca18 4148
84990945 4149 if (!netif_xmit_stopped(dev_queue))
3947ca18 4150 continue;
bfc647d5
EBE		 4151
4152 netdev_err(dev,
4153 "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
84990945
EBE		 4154 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
4155 jiffies_to_usecs(jiffies - dev_queue->trans_start));
3a32b26a 4156
7ca560b5
EBE		 4157 /* If we recover a lost interrupt, most likely TX timeout will
4158 * be resolved, skip reopening channels
4159 */
4160 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
4161 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
4162 reopen_channels = true;
4163 }
3947ca18
DJ		 4164 }
4165
bfc647d5
EBE		 4166 if (!reopen_channels)
4167 goto unlock;
4168
4169 mlx5e_close_locked(dev);
4170 err = mlx5e_open_locked(dev);
4171 if (err)
4172 netdev_err(priv->netdev,
4173 "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
4174 err);
4175
4176unlock:
4177 mutex_unlock(&priv->state_lock);
4178 rtnl_unlock();
4179}
4180
4181static void mlx5e_tx_timeout(struct net_device *dev)
4182{
4183 struct mlx5e_priv *priv = netdev_priv(dev);
4184
4185 netdev_err(dev, "TX timeout detected\n");
4186 queue_work(priv->wq, &priv->tx_timeout_work);
3947ca18
DJ		 4187}
4188
a26a5bdf 4189static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
0ec13877
TT		 4190{
4191 struct net_device *netdev = priv->netdev;
a26a5bdf 4192 struct mlx5e_channels new_channels = {};
0ec13877
TT		 4193
4194 if (priv->channels.params.lro_en) {
4195 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4196 return -EINVAL;
4197 }
4198
4199 if (MLX5_IPSEC_DEV(priv->mdev)) {
4200 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4201 return -EINVAL;
4202 }
4203
a26a5bdf
TT		 4204 new_channels.params = priv->channels.params;
4205 new_channels.params.xdp_prog = prog;
4206
4207 if (!mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
4208 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4209 new_channels.params.sw_mtu, MLX5E_XDP_MAX_MTU);
4210 return -EINVAL;
4211 }
4212
0ec13877
TT		 4213 return 0;
4214}
4215
86994156
RS		 4216static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4217{
4218 struct mlx5e_priv *priv = netdev_priv(netdev);
4219 struct bpf_prog *old_prog;
86994156 4220 bool reset, was_opened;
96d39502 4221 int err = 0;
86994156
RS		 4222 int i;
4223
4224 mutex_lock(&priv->state_lock);
4225
0ec13877 4226 if (prog) {
a26a5bdf 4227 err = mlx5e_xdp_allowed(priv, prog);
0ec13877
TT		 4228 if (err)
4229 goto unlock;
547eede0
IT		 4230 }
4231
86994156
RS		 4232 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4233 /* no need for full reset when exchanging programs */
6a9764ef 4234 reset = (!priv->channels.params.xdp_prog || !prog);
86994156
RS		 4235
4236 if (was_opened && reset)
4237 mlx5e_close_locked(netdev);
c54c0629
DB		 4238 if (was_opened && !reset) {
4239 /* num_channels is invariant here, so we can take the
4240 * batched reference right upfront.
4241 */
6a9764ef 4242 prog = bpf_prog_add(prog, priv->channels.num);
c54c0629
DB		 4243 if (IS_ERR(prog)) {
4244 err = PTR_ERR(prog);
4245 goto unlock;
4246 }
4247 }
86994156 4248
c54c0629
DB		 4249 /* exchange programs, extra prog reference we got from caller
4250 * as long as we don't fail from this point onwards.
4251 */
6a9764ef 4252 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
86994156
RS		 4253 if (old_prog)
4254 bpf_prog_put(old_prog);
4255
4256 if (reset) /* change RQ type according to priv->xdp_prog */
2a0f561b 4257 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
86994156
RS		 4258
4259 if (was_opened && reset)
4260 mlx5e_open_locked(netdev);
4261
4262 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4263 goto unlock;
4264
4265 /* exchanging programs w/o reset, we update ref counts on behalf
4266 * of the channels RQs here.
4267 */
ff9c852f
SM		 4268 for (i = 0; i < priv->channels.num; i++) {
4269 struct mlx5e_channel *c = priv->channels.c[i];
86994156 4270
c0f1147d 4271 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 4272 napi_synchronize(&c->napi);
4273 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4274
4275 old_prog = xchg(&c->rq.xdp_prog, prog);
4276
c0f1147d 4277 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156 4278 /* napi_schedule in case we have missed anything */
86994156
RS		 4279 napi_schedule(&c->napi);
4280
4281 if (old_prog)
4282 bpf_prog_put(old_prog);
4283 }
4284
4285unlock:
4286 mutex_unlock(&priv->state_lock);
4287 return err;
4288}
4289
821b2e29 4290static u32 mlx5e_xdp_query(struct net_device *dev)
86994156
RS		 4291{
4292 struct mlx5e_priv *priv = netdev_priv(dev);
821b2e29
MKL		 4293 const struct bpf_prog *xdp_prog;
4294 u32 prog_id = 0;
86994156 4295
821b2e29
MKL		 4296 mutex_lock(&priv->state_lock);
4297 xdp_prog = priv->channels.params.xdp_prog;
4298 if (xdp_prog)
4299 prog_id = xdp_prog->aux->id;
4300 mutex_unlock(&priv->state_lock);
4301
4302 return prog_id;
86994156
RS		 4303}
4304
f4e63525 4305static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
86994156
RS		 4306{
4307 switch (xdp->command) {
4308 case XDP_SETUP_PROG:
4309 return mlx5e_xdp_set(dev, xdp->prog);
4310 case XDP_QUERY_PROG:
821b2e29 4311 xdp->prog_id = mlx5e_xdp_query(dev);
86994156
RS		 4312 return 0;
4313 default:
4314 return -EINVAL;
4315 }
4316}
4317
e80541ec 4318static const struct net_device_ops mlx5e_netdev_ops = {
f62b8bb8
AV		 4319 .ndo_open = mlx5e_open,
4320 .ndo_stop = mlx5e_close,
4321 .ndo_start_xmit = mlx5e_xmit,
0cf0f6d3 4322 .ndo_setup_tc = mlx5e_setup_tc,
08fb1dac 4323 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 4324 .ndo_get_stats64 = mlx5e_get_stats,
4325 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4326 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 4327 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4328 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 4329 .ndo_set_features = mlx5e_set_features,
7d92d580 4330 .ndo_fix_features = mlx5e_fix_features,
250a42b6 4331 .ndo_change_mtu = mlx5e_change_nic_mtu,
b0eed40e 4332 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 4333 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
706b3583
SM		 4334 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
4335 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
4336 .ndo_features_check = mlx5e_features_check,
3947ca18 4337 .ndo_tx_timeout = mlx5e_tx_timeout,
f4e63525 4338 .ndo_bpf = mlx5e_xdp,
58b99ee3 4339 .ndo_xdp_xmit = mlx5e_xdp_xmit,
ec080045
SM		 4340#ifdef CONFIG_MLX5_EN_ARFS
4341 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4342#endif
e80541ec 4343#ifdef CONFIG_MLX5_ESWITCH
706b3583 4344 /* SRIOV E-Switch NDOs */
b0eed40e
SM		 4345 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4346 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 4347 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 4348 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 4349 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 4350 .ndo_get_vf_config = mlx5e_get_vf_config,
4351 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4352 .ndo_get_vf_stats = mlx5e_get_vf_stats,
370bad0f
OG		 4353 .ndo_has_offload_stats = mlx5e_has_offload_stats,
4354 .ndo_get_offload_stats = mlx5e_get_offload_stats,
e80541ec 4355#endif
f62b8bb8
AV		 4356};
4357
4358static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4359{
4360 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 4361 return -EOPNOTSUPP;
f62b8bb8
AV		 4362 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4363 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4364 !MLX5_CAP_ETH(mdev, csum_cap) ||
4365 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4366 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 4367 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4368 MLX5_CAP_FLOWTABLE(mdev,
4369 flow_table_properties_nic_receive.max_ft_level)
4370 < 3) {
f62b8bb8
AV		 4371 mlx5_core_warn(mdev,
4372 "Not creating net device, some required device capabilities are missing\n");
9eb78923 4373 return -EOPNOTSUPP;
f62b8bb8 4374 }
66189961
TT		 4375 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4376 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8 4377 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3e432ab6 4378 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
66189961 4379
f62b8bb8
AV		 4380 return 0;
4381}
4382
d4b6c488 4383void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
85082dba
TT		 4384 int num_channels)
4385{
4386 int i;
4387
4388 for (i = 0; i < len; i++)
4389 indirection_rqt[i] = i % num_channels;
4390}
4391
0608d4db 4392static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
b797a684 4393{
0608d4db
TT		 4394 u32 link_speed = 0;
4395 u32 pci_bw = 0;
b797a684 4396
2c81bfd5 4397 mlx5e_port_max_linkspeed(mdev, &link_speed);
3c0d551e 4398 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
0608d4db
TT		 4399 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4400 link_speed, pci_bw);
4401
4402#define MLX5E_SLOW_PCI_RATIO (2)
4403
4404 return link_speed && pci_bw &&
4405 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
0f6e4cf6
EBE		 4406}
4407
cbce4f44 4408static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
0088cbbc 4409{
cbce4f44
TG		 4410 struct net_dim_cq_moder moder;
4411
4412 moder.cq_period_mode = cq_period_mode;
4413 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4414 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4415 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4416 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4417
4418 return moder;
4419}
0088cbbc 4420
cbce4f44
TG		 4421static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4422{
4423 struct net_dim_cq_moder moder;
0088cbbc 4424
cbce4f44
TG		 4425 moder.cq_period_mode = cq_period_mode;
4426 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4427 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
0088cbbc 4428 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
cbce4f44
TG		 4429 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4430
4431 return moder;
4432}
4433
4434static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4435{
4436 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4437 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4438 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4439}
4440
4441void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4442{
4443 if (params->tx_dim_enabled) {
4444 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4445
4446 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4447 } else {
4448 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4449 }
0088cbbc
TG		 4450
4451 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4452 params->tx_cq_moderation.cq_period_mode ==
4453 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4454}
4455
9908aa29
TT		 4456void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4457{
9a317425 4458 if (params->rx_dim_enabled) {
cbce4f44
TG		 4459 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4460
4461 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4462 } else {
4463 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
9a317425 4464 }
457fcd8a 4465
6a9764ef 4466 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
0088cbbc
TG		 4467 params->rx_cq_moderation.cq_period_mode ==
4468 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29
TT		 4469}
4470
707129dc 4471static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
2b029556
SM		 4472{
4473 int i;
4474
4475 /* The supported periods are organized in ascending order */
4476 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4477 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4478 break;
4479
4480 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4481}
4482
749359f4
GT		 4483void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4484 struct mlx5e_params *params)
4485{
4486 /* Prefer Striding RQ, unless any of the following holds:
4487 * - Striding RQ configuration is not possible/supported.
4488 * - Slow PCI heuristic.
4489 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4490 */
4491 if (!slow_pci_heuristic(mdev) &&
4492 mlx5e_striding_rq_possible(mdev, params) &&
4493 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4494 !mlx5e_rx_is_linear_skb(mdev, params)))
4495 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4496 mlx5e_set_rq_type(mdev, params);
4497 mlx5e_init_rq_type_params(mdev, params);
4498}
4499
8f493ffd
SM		 4500void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4501 struct mlx5e_params *params,
472a1e44 4502 u16 max_channels, u16 mtu)
f62b8bb8 4503{
48bfc397 4504 u8 rx_cq_period_mode;
2fc4bfb7 4505
472a1e44
TT		 4506 params->sw_mtu = mtu;
4507 params->hard_mtu = MLX5E_ETH_HARD_MTU;
6a9764ef
SM		 4508 params->num_channels = max_channels;
4509 params->num_tc = 1;
2b029556 4510
6a9764ef
SM		 4511 /* SQ */
4512 params->log_sq_size = is_kdump_kernel() ?
b4e029da
KH		 4513 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4514 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 4515
b797a684 4516 /* set CQE compression */
6a9764ef 4517 params->rx_cqe_compress_def = false;
b797a684 4518 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
e53eef63 4519 MLX5_CAP_GEN(mdev, vport_group_manager))
0608d4db 4520 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
0f6e4cf6 4521
6a9764ef
SM		 4522 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4523
4524 /* RQ */
749359f4 4525 mlx5e_build_rq_params(mdev, params);
b797a684 4526
6a9764ef 4527 /* HW LRO */
c139dbfd 4528
5426a0b2 4529 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
6a9764ef 4530 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
619a8f2a
TT		 4531 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4532 params->lro_en = !slow_pci_heuristic(mdev);
6a9764ef 4533 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
b0d4660b 4534
6a9764ef 4535 /* CQ moderation params */
48bfc397 4536 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
6a9764ef
SM		 4537 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4538 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
9a317425 4539 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
cbce4f44 4540 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
48bfc397
TG		 4541 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4542 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
9908aa29 4543
6a9764ef 4544 /* TX inline */
fbcb127e 4545 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
a6f402e4 4546
6a9764ef
SM		 4547 /* RSS */
4548 params->rss_hfunc = ETH_RSS_HASH_XOR;
4549 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
d4b6c488 4550 mlx5e_build_default_indir_rqt(params->indirection_rqt,
6a9764ef
SM		 4551 MLX5E_INDIR_RQT_SIZE, max_channels);
4552}
f62b8bb8 4553
6a9764ef
SM		 4554static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4555 struct net_device *netdev,
4556 const struct mlx5e_profile *profile,
4557 void *ppriv)
4558{
4559 struct mlx5e_priv *priv = netdev_priv(netdev);
57afead5 4560
6a9764ef
SM		 4561 priv->mdev = mdev;
4562 priv->netdev = netdev;
4563 priv->profile = profile;
4564 priv->ppriv = ppriv;
79c48764 4565 priv->msglevel = MLX5E_MSG_LEVEL;
05909bab 4566 priv->max_opened_tc = 1;
2d75b2bc 4567
472a1e44
TT		 4568 mlx5e_build_nic_params(mdev, &priv->channels.params,
4569 profile->max_nch(mdev), netdev->mtu);
9908aa29 4570
f62b8bb8
AV		 4571 mutex_init(&priv->state_lock);
4572
4573 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4574 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 4575 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8 4576 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
237f258c
FD		 4577
4578 mlx5e_timestamp_init(priv);
f62b8bb8
AV		 4579}
4580
4581static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4582{
4583 struct mlx5e_priv *priv = netdev_priv(netdev);
4584
e1d7d349 4585 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 4586 if (is_zero_ether_addr(netdev->dev_addr) &&
4587 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4588 eth_hw_addr_random(netdev);
4589 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4590 }
f62b8bb8
AV		 4591}
4592
f125376b 4593#if IS_ENABLED(CONFIG_MLX5_ESWITCH)
cb67b832
HHZ		 4594static const struct switchdev_ops mlx5e_switchdev_ops = {
4595 .switchdev_port_attr_get = mlx5e_attr_get,
4596};
e80541ec 4597#endif
cb67b832 4598
6bfd390b 4599static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 4600{
4601 struct mlx5e_priv *priv = netdev_priv(netdev);
4602 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 4603 bool fcs_supported;
4604 bool fcs_enabled;
f62b8bb8
AV		 4605
4606 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4607
e80541ec
SM		 4608 netdev->netdev_ops = &mlx5e_netdev_ops;
4609
08fb1dac 4610#ifdef CONFIG_MLX5_CORE_EN_DCB
e80541ec
SM		 4611 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4612 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac 4613#endif
66e49ded 4614
f62b8bb8
AV		 4615 netdev->watchdog_timeo = 15 * HZ;
4616
4617 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4618
12be4b21 4619 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 4620 netdev->vlan_features |= NETIF_F_IP_CSUM;
4621 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4622 netdev->vlan_features |= NETIF_F_GRO;
4623 netdev->vlan_features |= NETIF_F_TSO;
4624 netdev->vlan_features |= NETIF_F_TSO6;
4625 netdev->vlan_features |= NETIF_F_RXCSUM;
4626 netdev->vlan_features |= NETIF_F_RXHASH;
4627
71186172
AH		 4628 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4629 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4630
6c3a823e
TT		 4631 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4632 mlx5e_check_fragmented_striding_rq_cap(mdev))
f62b8bb8
AV		 4633 netdev->vlan_features |= NETIF_F_LRO;
4634
4635 netdev->hw_features = netdev->vlan_features;
e4cf27bd 4636 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 4637 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4638 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4382c7b9 4639 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
f62b8bb8 4640
358aa5ce 4641 if (mlx5_vxlan_allowed(mdev->vxlan) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
b3f63c3d 4642 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 4643 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 4644 netdev->hw_enc_features |= NETIF_F_TSO;
4645 netdev->hw_enc_features |= NETIF_F_TSO6;
27299841
GP		 4646 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4647 }
4648
358aa5ce 4649 if (mlx5_vxlan_allowed(mdev->vxlan)) {
27299841
GP		 4650 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4651 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4652 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4653 NETIF_F_GSO_UDP_TUNNEL_CSUM;
b49663c8 4654 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 4655 }
4656
27299841
GP		 4657 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4658 netdev->hw_features |= NETIF_F_GSO_GRE |
4659 NETIF_F_GSO_GRE_CSUM;
4660 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4661 NETIF_F_GSO_GRE_CSUM;
4662 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4663 NETIF_F_GSO_GRE_CSUM;
4664 }
4665
3f44899e
BP		 4666 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4667 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
4668 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
4669 netdev->features |= NETIF_F_GSO_UDP_L4;
4670
94cb1ebb
EBE		 4671 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4672
4673 if (fcs_supported)
4674 netdev->hw_features |= NETIF_F_RXALL;
4675
102722fc
GE		 4676 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4677 netdev->hw_features |= NETIF_F_RXFCS;
4678
f62b8bb8 4679 netdev->features = netdev->hw_features;
6a9764ef 4680 if (!priv->channels.params.lro_en)
f62b8bb8
AV		 4681 netdev->features &= ~NETIF_F_LRO;
4682
94cb1ebb
EBE		 4683 if (fcs_enabled)
4684 netdev->features &= ~NETIF_F_RXALL;
4685
102722fc
GE		 4686 if (!priv->channels.params.scatter_fcs_en)
4687 netdev->features &= ~NETIF_F_RXFCS;
4688
e8f887ac
AV		 4689#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4690 if (FT_CAP(flow_modify_en) &&
4691 FT_CAP(modify_root) &&
4692 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 4693 FT_CAP(flow_table_modify)) {
4694 netdev->hw_features |= NETIF_F_HW_TC;
ec080045 4695#ifdef CONFIG_MLX5_EN_ARFS
1cabe6b0
MG		 4696 netdev->hw_features |= NETIF_F_NTUPLE;
4697#endif
4698 }
e8f887ac 4699
f62b8bb8 4700 netdev->features |= NETIF_F_HIGHDMA;
7d92d580 4701 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
f62b8bb8
AV		 4702
4703 netdev->priv_flags |= IFF_UNICAST_FLT;
4704
4705 mlx5e_set_netdev_dev_addr(netdev);
cb67b832 4706
f125376b 4707#if IS_ENABLED(CONFIG_MLX5_ESWITCH)
733d3e54 4708 if (MLX5_ESWITCH_MANAGER(mdev))
cb67b832
HHZ		 4709 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4710#endif
547eede0
IT		 4711
4712 mlx5e_ipsec_build_netdev(priv);
c83294b9 4713 mlx5e_tls_build_netdev(priv);
f62b8bb8
AV		 4714}
4715
1462e48d 4716void mlx5e_create_q_counters(struct mlx5e_priv *priv)
593cf338
RS		 4717{
4718 struct mlx5_core_dev *mdev = priv->mdev;
4719 int err;
4720
4721 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4722 if (err) {
4723 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4724 priv->q_counter = 0;
4725 }
7cbaf9a3
MS		 4726
4727 err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4728 if (err) {
4729 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4730 priv->drop_rq_q_counter = 0;
4731 }
593cf338
RS		 4732}
4733
1462e48d 4734void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
593cf338 4735{
7cbaf9a3
MS		 4736 if (priv->q_counter)
4737 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
593cf338 4738
7cbaf9a3
MS		 4739 if (priv->drop_rq_q_counter)
4740 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
593cf338
RS		 4741}
4742
6bfd390b
HHZ		 4743static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4744 struct net_device *netdev,
127ea380
HHZ		 4745 const struct mlx5e_profile *profile,
4746 void *ppriv)
6bfd390b
HHZ		 4747{
4748 struct mlx5e_priv *priv = netdev_priv(netdev);
547eede0 4749 int err;
6bfd390b 4750
127ea380 4751 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
547eede0
IT		 4752 err = mlx5e_ipsec_init(priv);
4753 if (err)
4754 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
43585a41
IL		 4755 err = mlx5e_tls_init(priv);
4756 if (err)
4757 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
6bfd390b 4758 mlx5e_build_nic_netdev(netdev);
8bfaf07f 4759 mlx5e_build_tc2txq_maps(priv);
6bfd390b
HHZ		 4760}
4761
4762static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4763{
43585a41 4764 mlx5e_tls_cleanup(priv);
547eede0 4765 mlx5e_ipsec_cleanup(priv);
6bfd390b
HHZ		 4766}
4767
4768static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4769{
4770 struct mlx5_core_dev *mdev = priv->mdev;
4771 int err;
6bfd390b 4772
1462e48d
RD		 4773 mlx5e_create_q_counters(priv);
4774
4775 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4776 if (err) {
4777 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4778 goto err_destroy_q_counters;
4779 }
4780
8f493ffd
SM		 4781 err = mlx5e_create_indirect_rqt(priv);
4782 if (err)
1462e48d 4783 goto err_close_drop_rq;
6bfd390b
HHZ		 4784
4785 err = mlx5e_create_direct_rqts(priv);
8f493ffd 4786 if (err)
6bfd390b 4787 goto err_destroy_indirect_rqts;
6bfd390b
HHZ		 4788
4789 err = mlx5e_create_indirect_tirs(priv);
8f493ffd 4790 if (err)
6bfd390b 4791 goto err_destroy_direct_rqts;
6bfd390b
HHZ		 4792
4793 err = mlx5e_create_direct_tirs(priv);
8f493ffd 4794 if (err)
6bfd390b 4795 goto err_destroy_indirect_tirs;
6bfd390b
HHZ		 4796
4797 err = mlx5e_create_flow_steering(priv);
4798 if (err) {
4799 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4800 goto err_destroy_direct_tirs;
4801 }
4802
655dc3d2 4803 err = mlx5e_tc_nic_init(priv);
6bfd390b
HHZ		 4804 if (err)
4805 goto err_destroy_flow_steering;
4806
4807 return 0;
4808
4809err_destroy_flow_steering:
4810 mlx5e_destroy_flow_steering(priv);
4811err_destroy_direct_tirs:
4812 mlx5e_destroy_direct_tirs(priv);
4813err_destroy_indirect_tirs:
4814 mlx5e_destroy_indirect_tirs(priv);
4815err_destroy_direct_rqts:
8f493ffd 4816 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4817err_destroy_indirect_rqts:
4818 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
1462e48d
RD		 4819err_close_drop_rq:
4820 mlx5e_close_drop_rq(&priv->drop_rq);
4821err_destroy_q_counters:
4822 mlx5e_destroy_q_counters(priv);
6bfd390b
HHZ		 4823 return err;
4824}
4825
4826static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4827{
655dc3d2 4828 mlx5e_tc_nic_cleanup(priv);
6bfd390b
HHZ		 4829 mlx5e_destroy_flow_steering(priv);
4830 mlx5e_destroy_direct_tirs(priv);
4831 mlx5e_destroy_indirect_tirs(priv);
8f493ffd 4832 mlx5e_destroy_direct_rqts(priv);
6bfd390b 4833 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
1462e48d
RD		 4834 mlx5e_close_drop_rq(&priv->drop_rq);
4835 mlx5e_destroy_q_counters(priv);
6bfd390b
HHZ		 4836}
4837
4838static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4839{
4840 int err;
4841
4842 err = mlx5e_create_tises(priv);
4843 if (err) {
4844 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4845 return err;
4846 }
4847
4848#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 4849 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 4850#endif
4851 return 0;
4852}
4853
4854static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4855{
4856 struct net_device *netdev = priv->netdev;
4857 struct mlx5_core_dev *mdev = priv->mdev;
2c3b5bee
SM		 4858 u16 max_mtu;
4859
4860 mlx5e_init_l2_addr(priv);
4861
63bfd399
EBE		 4862 /* Marking the link as currently not needed by the Driver */
4863 if (!netif_running(netdev))
4864 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4865
2c3b5bee
SM		 4866 /* MTU range: 68 - hw-specific max */
4867 netdev->min_mtu = ETH_MIN_MTU;
4868 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
472a1e44 4869 netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
2c3b5bee 4870 mlx5e_set_dev_port_mtu(priv);
6bfd390b 4871
7907f23a
AH		 4872 mlx5_lag_add(mdev, netdev);
4873
6bfd390b 4874 mlx5e_enable_async_events(priv);
127ea380 4875
733d3e54 4876 if (MLX5_ESWITCH_MANAGER(priv->mdev))
1d447a39 4877 mlx5e_register_vport_reps(priv);
2c3b5bee 4878
610e89e0
SM		 4879 if (netdev->reg_state != NETREG_REGISTERED)
4880 return;
2a5e7a13
HN		 4881#ifdef CONFIG_MLX5_CORE_EN_DCB
4882 mlx5e_dcbnl_init_app(priv);
4883#endif
610e89e0
SM		 4884
4885 queue_work(priv->wq, &priv->set_rx_mode_work);
2c3b5bee
SM		 4886
4887 rtnl_lock();
4888 if (netif_running(netdev))
4889 mlx5e_open(netdev);
4890 netif_device_attach(netdev);
4891 rtnl_unlock();
6bfd390b
HHZ		 4892}
4893
4894static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4895{
3deef8ce 4896 struct mlx5_core_dev *mdev = priv->mdev;
3deef8ce 4897
2a5e7a13
HN		 4898#ifdef CONFIG_MLX5_CORE_EN_DCB
4899 if (priv->netdev->reg_state == NETREG_REGISTERED)
4900 mlx5e_dcbnl_delete_app(priv);
4901#endif
4902
2c3b5bee
SM		 4903 rtnl_lock();
4904 if (netif_running(priv->netdev))
4905 mlx5e_close(priv->netdev);
4906 netif_device_detach(priv->netdev);
4907 rtnl_unlock();
4908
6bfd390b 4909 queue_work(priv->wq, &priv->set_rx_mode_work);
1d447a39 4910
733d3e54 4911 if (MLX5_ESWITCH_MANAGER(priv->mdev))
1d447a39
SM		 4912 mlx5e_unregister_vport_reps(priv);
4913
6bfd390b 4914 mlx5e_disable_async_events(priv);
3deef8ce 4915 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 4916}
4917
4918static const struct mlx5e_profile mlx5e_nic_profile = {
4919 .init = mlx5e_nic_init,
4920 .cleanup = mlx5e_nic_cleanup,
4921 .init_rx = mlx5e_init_nic_rx,
4922 .cleanup_rx = mlx5e_cleanup_nic_rx,
4923 .init_tx = mlx5e_init_nic_tx,
4924 .cleanup_tx = mlx5e_cleanup_nic_tx,
4925 .enable = mlx5e_nic_enable,
4926 .disable = mlx5e_nic_disable,
3834a5e6 4927 .update_stats = mlx5e_update_ndo_stats,
6bfd390b 4928 .max_nch = mlx5e_get_max_num_channels,
7ca42c80 4929 .update_carrier = mlx5e_update_carrier,
20fd0c19
SM		 4930 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4931 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
6bfd390b
HHZ		 4932 .max_tc = MLX5E_MAX_NUM_TC,
4933};
4934
2c3b5bee
SM		 4935/* mlx5e generic netdev management API (move to en_common.c) */
4936
26e59d80
MHY		 4937struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4938 const struct mlx5e_profile *profile,
4939 void *ppriv)
f62b8bb8 4940{
26e59d80 4941 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 4942 struct net_device *netdev;
4943 struct mlx5e_priv *priv;
f62b8bb8 4944
08fb1dac 4945 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 4946 nch * profile->max_tc,
08fb1dac 4947 nch);
f62b8bb8
AV		 4948 if (!netdev) {
4949 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4950 return NULL;
4951 }
4952
ec080045 4953#ifdef CONFIG_MLX5_EN_ARFS
be4891af
SM		 4954 netdev->rx_cpu_rmap = mdev->rmap;
4955#endif
4956
127ea380 4957 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 4958
4959 netif_carrier_off(netdev);
4960
4961 priv = netdev_priv(netdev);
4962
7bb29755
MF		 4963 priv->wq = create_singlethread_workqueue("mlx5e");
4964 if (!priv->wq)
26e59d80
MHY		 4965 goto err_cleanup_nic;
4966
4967 return netdev;
4968
4969err_cleanup_nic:
31ac9338
OG		 4970 if (profile->cleanup)
4971 profile->cleanup(priv);
26e59d80
MHY		 4972 free_netdev(netdev);
4973
4974 return NULL;
4975}
4976
2c3b5bee 4977int mlx5e_attach_netdev(struct mlx5e_priv *priv)
26e59d80
MHY		 4978{
4979 const struct mlx5e_profile *profile;
26e59d80
MHY		 4980 int err;
4981
26e59d80
MHY		 4982 profile = priv->profile;
4983 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 4984
6bfd390b
HHZ		 4985 err = profile->init_tx(priv);
4986 if (err)
ec8b9981 4987 goto out;
5c50368f 4988
6bfd390b
HHZ		 4989 err = profile->init_rx(priv);
4990 if (err)
1462e48d 4991 goto err_cleanup_tx;
5c50368f 4992
6bfd390b
HHZ		 4993 if (profile->enable)
4994 profile->enable(priv);
f62b8bb8 4995
26e59d80 4996 return 0;
5c50368f 4997
1462e48d 4998err_cleanup_tx:
6bfd390b 4999 profile->cleanup_tx(priv);
5c50368f 5000
26e59d80
MHY		 5001out:
5002 return err;
f62b8bb8
AV		 5003}
5004
2c3b5bee 5005void mlx5e_detach_netdev(struct mlx5e_priv *priv)
26e59d80 5006{
26e59d80
MHY		 5007 const struct mlx5e_profile *profile = priv->profile;
5008
5009 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80 5010
37f304d1
SM		 5011 if (profile->disable)
5012 profile->disable(priv);
5013 flush_workqueue(priv->wq);
5014
26e59d80 5015 profile->cleanup_rx(priv);
26e59d80 5016 profile->cleanup_tx(priv);
26e59d80
MHY		 5017 cancel_delayed_work_sync(&priv->update_stats_work);
5018}
5019
2c3b5bee
SM		 5020void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5021{
5022 const struct mlx5e_profile *profile = priv->profile;
5023 struct net_device *netdev = priv->netdev;
5024
5025 destroy_workqueue(priv->wq);
5026 if (profile->cleanup)
5027 profile->cleanup(priv);
5028 free_netdev(netdev);
5029}
5030
26e59d80
MHY		 5031/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5032 * hardware contexts and to connect it to the current netdev.
5033 */
5034static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5035{
5036 struct mlx5e_priv *priv = vpriv;
5037 struct net_device *netdev = priv->netdev;
5038 int err;
5039
5040 if (netif_device_present(netdev))
5041 return 0;
5042
5043 err = mlx5e_create_mdev_resources(mdev);
5044 if (err)
5045 return err;
5046
2c3b5bee 5047 err = mlx5e_attach_netdev(priv);
26e59d80
MHY		 5048 if (err) {
5049 mlx5e_destroy_mdev_resources(mdev);
5050 return err;
5051 }
5052
5053 return 0;
5054}
5055
5056static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5057{
5058 struct mlx5e_priv *priv = vpriv;
5059 struct net_device *netdev = priv->netdev;
5060
5061 if (!netif_device_present(netdev))
5062 return;
5063
2c3b5bee 5064 mlx5e_detach_netdev(priv);
26e59d80
MHY		 5065 mlx5e_destroy_mdev_resources(mdev);
5066}
5067
b50d292b
HHZ		 5068static void *mlx5e_add(struct mlx5_core_dev *mdev)
5069{
07c9f1e5
SM		 5070 struct net_device *netdev;
5071 void *rpriv = NULL;
26e59d80 5072 void *priv;
26e59d80 5073 int err;
b50d292b 5074
26e59d80
MHY		 5075 err = mlx5e_check_required_hca_cap(mdev);
5076 if (err)
b50d292b
HHZ		 5077 return NULL;
5078
e80541ec 5079#ifdef CONFIG_MLX5_ESWITCH
733d3e54 5080 if (MLX5_ESWITCH_MANAGER(mdev)) {
07c9f1e5 5081 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
1d447a39 5082 if (!rpriv) {
07c9f1e5 5083 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
1d447a39
SM		 5084 return NULL;
5085 }
1d447a39 5086 }
e80541ec 5087#endif
127ea380 5088
1d447a39 5089 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
26e59d80
MHY		 5090 if (!netdev) {
5091 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
07c9f1e5 5092 goto err_free_rpriv;
26e59d80
MHY		 5093 }
5094
5095 priv = netdev_priv(netdev);
5096
5097 err = mlx5e_attach(mdev, priv);
5098 if (err) {
5099 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5100 goto err_destroy_netdev;
5101 }
5102
5103 err = register_netdev(netdev);
5104 if (err) {
5105 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5106 goto err_detach;
b50d292b 5107 }
26e59d80 5108
2a5e7a13
HN		 5109#ifdef CONFIG_MLX5_CORE_EN_DCB
5110 mlx5e_dcbnl_init_app(priv);
5111#endif
26e59d80
MHY		 5112 return priv;
5113
5114err_detach:
5115 mlx5e_detach(mdev, priv);
26e59d80 5116err_destroy_netdev:
2c3b5bee 5117 mlx5e_destroy_netdev(priv);
07c9f1e5 5118err_free_rpriv:
1d447a39 5119 kfree(rpriv);
26e59d80 5120 return NULL;
b50d292b
HHZ		 5121}
5122
b50d292b
HHZ		 5123static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5124{
5125 struct mlx5e_priv *priv = vpriv;
1d447a39 5126 void *ppriv = priv->ppriv;
127ea380 5127
2a5e7a13
HN		 5128#ifdef CONFIG_MLX5_CORE_EN_DCB
5129 mlx5e_dcbnl_delete_app(priv);
5130#endif
5e1e93c7 5131 unregister_netdev(priv->netdev);
26e59d80 5132 mlx5e_detach(mdev, vpriv);
2c3b5bee 5133 mlx5e_destroy_netdev(priv);
1d447a39 5134 kfree(ppriv);
b50d292b
HHZ		 5135}
5136
f62b8bb8
AV		 5137static void *mlx5e_get_netdev(void *vpriv)
5138{
5139 struct mlx5e_priv *priv = vpriv;
5140
5141 return priv->netdev;
5142}
5143
5144static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 5145 .add = mlx5e_add,
5146 .remove = mlx5e_remove,
26e59d80
MHY		 5147 .attach = mlx5e_attach,
5148 .detach = mlx5e_detach,
f62b8bb8
AV		 5149 .event = mlx5e_async_event,
5150 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
5151 .get_dev = mlx5e_get_netdev,
5152};
5153
5154void mlx5e_init(void)
5155{
2ac9cfe7 5156 mlx5e_ipsec_build_inverse_table();
665bc539 5157 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 5158 mlx5_register_interface(&mlx5e_interface);
5159}
5160
5161void mlx5e_cleanup(void)
5162{
5163 mlx5_unregister_interface(&mlx5e_interface);
5164}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git