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net/mlx5e: Expand WQE stride when CQE compression is enabled
[thirdparty/kernel/stable.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
f62b8bb8 37#include "en.h"
e8f887ac 38#include "en_tc.h"
66e49ded 39#include "eswitch.h"
b3f63c3d 40#include "vxlan.h"
f62b8bb8
AV		 41
42struct mlx5e_rq_param {
43 u32 rqc[MLX5_ST_SZ_DW(rqc)];
44 struct mlx5_wq_param wq;
45};
46
47struct mlx5e_sq_param {
48 u32 sqc[MLX5_ST_SZ_DW(sqc)];
49 struct mlx5_wq_param wq;
58d52291 50 u16 max_inline;
d3c9bc27 51 bool icosq;
f62b8bb8
AV		 52};
53
54struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
57 u16 eq_ix;
58};
59
60struct mlx5e_channel_param {
61 struct mlx5e_rq_param rq;
62 struct mlx5e_sq_param sq;
d3c9bc27 63 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 64 struct mlx5e_cq_param rx_cq;
65 struct mlx5e_cq_param tx_cq;
d3c9bc27 66 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 67};
68
69static void mlx5e_update_carrier(struct mlx5e_priv *priv)
70{
71 struct mlx5_core_dev *mdev = priv->mdev;
72 u8 port_state;
73
74 port_state = mlx5_query_vport_state(mdev,
e7546514 75 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8
AV		 76
77 if (port_state == VPORT_STATE_UP)
78 netif_carrier_on(priv->netdev);
79 else
80 netif_carrier_off(priv->netdev);
81}
82
83static void mlx5e_update_carrier_work(struct work_struct *work)
84{
85 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
86 update_carrier_work);
87
88 mutex_lock(&priv->state_lock);
89 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
90 mlx5e_update_carrier(priv);
91 mutex_unlock(&priv->state_lock);
92}
93
9218b44d 94static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 95{
9218b44d 96 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 97 struct mlx5e_rq_stats *rq_stats;
98 struct mlx5e_sq_stats *sq_stats;
9218b44d 99 u64 tx_offload_none = 0;
f62b8bb8
AV		 100 int i, j;
101
9218b44d 102 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 103 for (i = 0; i < priv->params.num_channels; i++) {
104 rq_stats = &priv->channel[i]->rq.stats;
105
faf4478b
GP		 106 s->rx_packets += rq_stats->packets;
107 s->rx_bytes += rq_stats->bytes;
f62b8bb8
AV		 108 s->lro_packets += rq_stats->lro_packets;
109 s->lro_bytes += rq_stats->lro_bytes;
110 s->rx_csum_none += rq_stats->csum_none;
bbceefce 111 s->rx_csum_sw += rq_stats->csum_sw;
1b223dd3 112 s->rx_csum_inner += rq_stats->csum_inner;
f62b8bb8 113 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 114 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
bc77b240 115 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
54984407 116 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 117 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
118 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
f62b8bb8 119
a4418a6c 120 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 121 sq_stats = &priv->channel[i]->sq[j].stats;
122
faf4478b
GP		 123 s->tx_packets += sq_stats->packets;
124 s->tx_bytes += sq_stats->bytes;
f62b8bb8
AV		 125 s->tso_packets += sq_stats->tso_packets;
126 s->tso_bytes += sq_stats->tso_bytes;
89db09eb
MF		 127 s->tso_inner_packets += sq_stats->tso_inner_packets;
128 s->tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 129 s->tx_queue_stopped += sq_stats->stopped;
130 s->tx_queue_wake += sq_stats->wake;
131 s->tx_queue_dropped += sq_stats->dropped;
89db09eb 132 s->tx_csum_inner += sq_stats->csum_offload_inner;
f62b8bb8
AV		 133 tx_offload_none += sq_stats->csum_offload_none;
134 }
135 }
136
9218b44d
GP		 137 /* Update calculated offload counters */
138 s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
139 s->rx_csum_good = s->rx_packets - s->rx_csum_none -
140 s->rx_csum_sw;
121fcdc8
GP		 141
142 s->link_down_events = MLX5_GET(ppcnt_reg,
143 priv->stats.pport.phy_counters,
144 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 145}
146
147static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
148{
149 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
150 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
151 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
152 struct mlx5_core_dev *mdev = priv->mdev;
153
f62b8bb8
AV		 154 memset(in, 0, sizeof(in));
155
156 MLX5_SET(query_vport_counter_in, in, opcode,
157 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
158 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
159 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
160
161 memset(out, 0, outlen);
162
9218b44d
GP		 163 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
164}
165
166static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
167{
168 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
169 struct mlx5_core_dev *mdev = priv->mdev;
170 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 171 int prio;
9218b44d
GP		 172 void *out;
173 u32 *in;
174
175 in = mlx5_vzalloc(sz);
176 if (!in)
f62b8bb8
AV		 177 goto free_out;
178
9218b44d 179 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 180
9218b44d
GP		 181 out = pstats->IEEE_802_3_counters;
182 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
183 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 184
9218b44d
GP		 185 out = pstats->RFC_2863_counters;
186 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
187 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
188
189 out = pstats->RFC_2819_counters;
190 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
191 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 192
121fcdc8
GP		 193 out = pstats->phy_counters;
194 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
195 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
196
cf678570
GP		 197 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
198 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
199 out = pstats->per_prio_counters[prio];
200 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
201 mlx5_core_access_reg(mdev, in, sz, out, sz,
202 MLX5_REG_PPCNT, 0, 0);
203 }
204
f62b8bb8 205free_out:
9218b44d
GP		 206 kvfree(in);
207}
208
209static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
210{
211 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
212
213 if (!priv->q_counter)
214 return;
215
216 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
217 &qcnt->rx_out_of_buffer);
218}
219
220void mlx5e_update_stats(struct mlx5e_priv *priv)
221{
9218b44d
GP		 222 mlx5e_update_q_counter(priv);
223 mlx5e_update_vport_counters(priv);
224 mlx5e_update_pport_counters(priv);
121fcdc8 225 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 226}
227
228static void mlx5e_update_stats_work(struct work_struct *work)
229{
230 struct delayed_work *dwork = to_delayed_work(work);
231 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
232 update_stats_work);
233 mutex_lock(&priv->state_lock);
234 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
235 mlx5e_update_stats(priv);
7bb29755
MF		 236 queue_delayed_work(priv->wq, dwork,
237 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 238 }
239 mutex_unlock(&priv->state_lock);
240}
241
daa21560
TT		 242static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
243 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 244{
daa21560
TT		 245 struct mlx5e_priv *priv = vpriv;
246
247 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
248 return;
249
f62b8bb8
AV		 250 switch (event) {
251 case MLX5_DEV_EVENT_PORT_UP:
252 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 253 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8
AV		 254 break;
255
256 default:
257 break;
258 }
259}
260
f62b8bb8
AV		 261static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
262{
263 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
264}
265
266static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
267{
f62b8bb8 268 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
daa21560 269 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 270}
271
facc9699
SM		 272#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
273#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
274
f62b8bb8
AV		 275static int mlx5e_create_rq(struct mlx5e_channel *c,
276 struct mlx5e_rq_param *param,
277 struct mlx5e_rq *rq)
278{
279 struct mlx5e_priv *priv = c->priv;
280 struct mlx5_core_dev *mdev = priv->mdev;
281 void *rqc = param->rqc;
282 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 283 u32 byte_count;
f62b8bb8
AV		 284 int wq_sz;
285 int err;
286 int i;
287
311c7c71
SM		 288 param->wq.db_numa_node = cpu_to_node(c->cpu);
289
f62b8bb8
AV		 290 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
291 &rq->wq_ctrl);
292 if (err)
293 return err;
294
295 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
296
297 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 298
461017cb
TT		 299 switch (priv->params.rq_wq_type) {
300 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
301 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
302 GFP_KERNEL, cpu_to_node(c->cpu));
303 if (!rq->wqe_info) {
304 err = -ENOMEM;
305 goto err_rq_wq_destroy;
306 }
307 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
308 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
309
d9d9f156
TT		 310 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
311 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
312 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
461017cb
TT		 313 byte_count = rq->wqe_sz;
314 break;
315 default: /* MLX5_WQ_TYPE_LINKED_LIST */
316 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
317 cpu_to_node(c->cpu));
318 if (!rq->skb) {
319 err = -ENOMEM;
320 goto err_rq_wq_destroy;
321 }
322 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
323 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
324
325 rq->wqe_sz = (priv->params.lro_en) ?
326 priv->params.lro_wqe_sz :
327 MLX5E_SW2HW_MTU(priv->netdev->mtu);
c5adb96f
TT		 328 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
329 byte_count = rq->wqe_sz;
461017cb
TT		 330 byte_count |= MLX5_HW_START_PADDING;
331 }
f62b8bb8
AV		 332
333 for (i = 0; i < wq_sz; i++) {
334 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
335
461017cb 336 wqe->data.byte_count = cpu_to_be32(byte_count);
f62b8bb8
AV		 337 }
338
461017cb 339 rq->wq_type = priv->params.rq_wq_type;
f62b8bb8
AV		 340 rq->pdev = c->pdev;
341 rq->netdev = c->netdev;
ef9814de 342 rq->tstamp = &priv->tstamp;
f62b8bb8
AV		 343 rq->channel = c;
344 rq->ix = c->ix;
50cfa25a 345 rq->priv = c->priv;
bc77b240
TT		 346 rq->mkey_be = c->mkey_be;
347 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
f62b8bb8
AV		 348
349 return 0;
350
351err_rq_wq_destroy:
352 mlx5_wq_destroy(&rq->wq_ctrl);
353
354 return err;
355}
356
357static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
358{
461017cb
TT		 359 switch (rq->wq_type) {
360 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
361 kfree(rq->wqe_info);
362 break;
363 default: /* MLX5_WQ_TYPE_LINKED_LIST */
364 kfree(rq->skb);
365 }
366
f62b8bb8
AV		 367 mlx5_wq_destroy(&rq->wq_ctrl);
368}
369
370static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
371{
50cfa25a 372 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 373 struct mlx5_core_dev *mdev = priv->mdev;
374
375 void *in;
376 void *rqc;
377 void *wq;
378 int inlen;
379 int err;
380
381 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
382 sizeof(u64) * rq->wq_ctrl.buf.npages;
383 in = mlx5_vzalloc(inlen);
384 if (!in)
385 return -ENOMEM;
386
387 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
388 wq = MLX5_ADDR_OF(rqc, rqc, wq);
389
390 memcpy(rqc, param->rqc, sizeof(param->rqc));
391
97de9f31 392 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8
AV		 393 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
394 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
36350114 395 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
f62b8bb8 396 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 397 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 398 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
399
400 mlx5_fill_page_array(&rq->wq_ctrl.buf,
401 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
402
7db22ffb 403 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 404
405 kvfree(in);
406
407 return err;
408}
409
36350114
GP		 410static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
411 int next_state)
f62b8bb8
AV		 412{
413 struct mlx5e_channel *c = rq->channel;
414 struct mlx5e_priv *priv = c->priv;
415 struct mlx5_core_dev *mdev = priv->mdev;
416
417 void *in;
418 void *rqc;
419 int inlen;
420 int err;
421
422 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
423 in = mlx5_vzalloc(inlen);
424 if (!in)
425 return -ENOMEM;
426
427 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
428
429 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
430 MLX5_SET(rqc, rqc, state, next_state);
431
7db22ffb 432 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 433
434 kvfree(in);
435
436 return err;
437}
438
36350114
GP		 439static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
440{
441 struct mlx5e_channel *c = rq->channel;
442 struct mlx5e_priv *priv = c->priv;
443 struct mlx5_core_dev *mdev = priv->mdev;
444
445 void *in;
446 void *rqc;
447 int inlen;
448 int err;
449
450 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
451 in = mlx5_vzalloc(inlen);
452 if (!in)
453 return -ENOMEM;
454
455 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
456
457 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
458 MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
459 MLX5_SET(rqc, rqc, vsd, vsd);
460 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
461
462 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
463
464 kvfree(in);
465
466 return err;
467}
468
f62b8bb8
AV		 469static void mlx5e_disable_rq(struct mlx5e_rq *rq)
470{
50cfa25a 471 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 472}
473
474static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
475{
01c196a2 476 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 477 struct mlx5e_channel *c = rq->channel;
478 struct mlx5e_priv *priv = c->priv;
479 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 480
01c196a2 481 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 482 if (wq->cur_sz >= priv->params.min_rx_wqes)
483 return 0;
484
485 msleep(20);
486 }
487
488 return -ETIMEDOUT;
489}
490
491static int mlx5e_open_rq(struct mlx5e_channel *c,
492 struct mlx5e_rq_param *param,
493 struct mlx5e_rq *rq)
494{
d3c9bc27
TT		 495 struct mlx5e_sq *sq = &c->icosq;
496 u16 pi = sq->pc & sq->wq.sz_m1;
f62b8bb8
AV		 497 int err;
498
499 err = mlx5e_create_rq(c, param, rq);
500 if (err)
501 return err;
502
503 err = mlx5e_enable_rq(rq, param);
504 if (err)
505 goto err_destroy_rq;
506
36350114 507 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8
AV		 508 if (err)
509 goto err_disable_rq;
510
511 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
d3c9bc27
TT		 512
513 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
514 sq->ico_wqe_info[pi].num_wqebbs = 1;
515 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 516
517 return 0;
518
519err_disable_rq:
520 mlx5e_disable_rq(rq);
521err_destroy_rq:
522 mlx5e_destroy_rq(rq);
523
524 return err;
525}
526
527static void mlx5e_close_rq(struct mlx5e_rq *rq)
528{
529 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
530 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
531
36350114 532 mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
f62b8bb8
AV		 533 while (!mlx5_wq_ll_is_empty(&rq->wq))
534 msleep(20);
535
536 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
537 napi_synchronize(&rq->channel->napi);
538
539 mlx5e_disable_rq(rq);
540 mlx5e_destroy_rq(rq);
541}
542
543static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
544{
34802a42 545 kfree(sq->wqe_info);
f62b8bb8
AV		 546 kfree(sq->dma_fifo);
547 kfree(sq->skb);
548}
549
550static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
551{
552 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
553 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
554
555 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
556 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
557 numa);
34802a42
AS		 558 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
559 numa);
f62b8bb8 560
34802a42 561 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
f62b8bb8
AV		 562 mlx5e_free_sq_db(sq);
563 return -ENOMEM;
564 }
565
566 sq->dma_fifo_mask = df_sz - 1;
567
568 return 0;
569}
570
571static int mlx5e_create_sq(struct mlx5e_channel *c,
572 int tc,
573 struct mlx5e_sq_param *param,
574 struct mlx5e_sq *sq)
575{
576 struct mlx5e_priv *priv = c->priv;
577 struct mlx5_core_dev *mdev = priv->mdev;
578
579 void *sqc = param->sqc;
580 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
581 int err;
582
0ba42241 583 err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
f62b8bb8
AV		 584 if (err)
585 return err;
586
311c7c71
SM		 587 param->wq.db_numa_node = cpu_to_node(c->cpu);
588
f62b8bb8
AV		 589 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
590 &sq->wq_ctrl);
591 if (err)
592 goto err_unmap_free_uar;
593
594 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
0ba42241
ML		 595 if (sq->uar.bf_map) {
596 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
597 sq->uar_map = sq->uar.bf_map;
598 } else {
599 sq->uar_map = sq->uar.map;
600 }
f62b8bb8 601 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 602 sq->max_inline = param->max_inline;
f62b8bb8 603
7ec0bb22
DC		 604 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
605 if (err)
f62b8bb8
AV		 606 goto err_sq_wq_destroy;
607
d3c9bc27
TT		 608 if (param->icosq) {
609 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
610
611 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
612 wq_sz,
613 GFP_KERNEL,
614 cpu_to_node(c->cpu));
615 if (!sq->ico_wqe_info) {
616 err = -ENOMEM;
617 goto err_free_sq_db;
618 }
619 } else {
620 int txq_ix;
621
622 txq_ix = c->ix + tc * priv->params.num_channels;
623 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
624 priv->txq_to_sq_map[txq_ix] = sq;
625 }
f62b8bb8 626
88a85f99 627 sq->pdev = c->pdev;
ef9814de 628 sq->tstamp = &priv->tstamp;
88a85f99
AS		 629 sq->mkey_be = c->mkey_be;
630 sq->channel = c;
631 sq->tc = tc;
632 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
633 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
f62b8bb8
AV		 634
635 return 0;
636
d3c9bc27
TT		 637err_free_sq_db:
638 mlx5e_free_sq_db(sq);
639
f62b8bb8
AV		 640err_sq_wq_destroy:
641 mlx5_wq_destroy(&sq->wq_ctrl);
642
643err_unmap_free_uar:
644 mlx5_unmap_free_uar(mdev, &sq->uar);
645
646 return err;
647}
648
649static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
650{
651 struct mlx5e_channel *c = sq->channel;
652 struct mlx5e_priv *priv = c->priv;
653
d3c9bc27 654 kfree(sq->ico_wqe_info);
f62b8bb8
AV		 655 mlx5e_free_sq_db(sq);
656 mlx5_wq_destroy(&sq->wq_ctrl);
657 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
658}
659
660static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
661{
662 struct mlx5e_channel *c = sq->channel;
663 struct mlx5e_priv *priv = c->priv;
664 struct mlx5_core_dev *mdev = priv->mdev;
665
666 void *in;
667 void *sqc;
668 void *wq;
669 int inlen;
670 int err;
671
672 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
673 sizeof(u64) * sq->wq_ctrl.buf.npages;
674 in = mlx5_vzalloc(inlen);
675 if (!in)
676 return -ENOMEM;
677
678 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
679 wq = MLX5_ADDR_OF(sqc, sqc, wq);
680
681 memcpy(sqc, param->sqc, sizeof(param->sqc));
682
d3c9bc27
TT		 683 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
684 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
f62b8bb8 685 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
d3c9bc27 686 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
f62b8bb8
AV		 687 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
688
689 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
690 MLX5_SET(wq, wq, uar_page, sq->uar.index);
691 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 692 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 693 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
694
695 mlx5_fill_page_array(&sq->wq_ctrl.buf,
696 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
697
7db22ffb 698 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 699
700 kvfree(in);
701
702 return err;
703}
704
705static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
706{
707 struct mlx5e_channel *c = sq->channel;
708 struct mlx5e_priv *priv = c->priv;
709 struct mlx5_core_dev *mdev = priv->mdev;
710
711 void *in;
712 void *sqc;
713 int inlen;
714 int err;
715
716 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
717 in = mlx5_vzalloc(inlen);
718 if (!in)
719 return -ENOMEM;
720
721 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
722
723 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
724 MLX5_SET(sqc, sqc, state, next_state);
725
7db22ffb 726 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 727
728 kvfree(in);
729
730 return err;
731}
732
733static void mlx5e_disable_sq(struct mlx5e_sq *sq)
734{
735 struct mlx5e_channel *c = sq->channel;
736 struct mlx5e_priv *priv = c->priv;
737 struct mlx5_core_dev *mdev = priv->mdev;
738
7db22ffb 739 mlx5_core_destroy_sq(mdev, sq->sqn);
f62b8bb8
AV		 740}
741
742static int mlx5e_open_sq(struct mlx5e_channel *c,
743 int tc,
744 struct mlx5e_sq_param *param,
745 struct mlx5e_sq *sq)
746{
747 int err;
748
749 err = mlx5e_create_sq(c, tc, param, sq);
750 if (err)
751 return err;
752
753 err = mlx5e_enable_sq(sq, param);
754 if (err)
755 goto err_destroy_sq;
756
757 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
758 if (err)
759 goto err_disable_sq;
760
d3c9bc27
TT		 761 if (sq->txq) {
762 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
763 netdev_tx_reset_queue(sq->txq);
764 netif_tx_start_queue(sq->txq);
765 }
f62b8bb8
AV		 766
767 return 0;
768
769err_disable_sq:
770 mlx5e_disable_sq(sq);
771err_destroy_sq:
772 mlx5e_destroy_sq(sq);
773
774 return err;
775}
776
777static inline void netif_tx_disable_queue(struct netdev_queue *txq)
778{
779 __netif_tx_lock_bh(txq);
780 netif_tx_stop_queue(txq);
781 __netif_tx_unlock_bh(txq);
782}
783
784static void mlx5e_close_sq(struct mlx5e_sq *sq)
785{
d3c9bc27
TT		 786 if (sq->txq) {
787 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
788 /* prevent netif_tx_wake_queue */
789 napi_synchronize(&sq->channel->napi);
790 netif_tx_disable_queue(sq->txq);
f62b8bb8 791
d3c9bc27
TT		 792 /* ensure hw is notified of all pending wqes */
793 if (mlx5e_sq_has_room_for(sq, 1))
794 mlx5e_send_nop(sq, true);
795
796 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
797 }
f62b8bb8 798
f62b8bb8
AV		 799 while (sq->cc != sq->pc) /* wait till sq is empty */
800 msleep(20);
801
802 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
803 napi_synchronize(&sq->channel->napi);
804
805 mlx5e_disable_sq(sq);
806 mlx5e_destroy_sq(sq);
807}
808
809static int mlx5e_create_cq(struct mlx5e_channel *c,
810 struct mlx5e_cq_param *param,
811 struct mlx5e_cq *cq)
812{
813 struct mlx5e_priv *priv = c->priv;
814 struct mlx5_core_dev *mdev = priv->mdev;
815 struct mlx5_core_cq *mcq = &cq->mcq;
816 int eqn_not_used;
0b6e26ce 817 unsigned int irqn;
f62b8bb8
AV		 818 int err;
819 u32 i;
820
311c7c71
SM		 821 param->wq.buf_numa_node = cpu_to_node(c->cpu);
822 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 823 param->eq_ix = c->ix;
824
825 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
826 &cq->wq_ctrl);
827 if (err)
828 return err;
829
830 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
831
832 cq->napi = &c->napi;
833
834 mcq->cqe_sz = 64;
835 mcq->set_ci_db = cq->wq_ctrl.db.db;
836 mcq->arm_db = cq->wq_ctrl.db.db + 1;
837 *mcq->set_ci_db = 0;
838 *mcq->arm_db = 0;
839 mcq->vector = param->eq_ix;
840 mcq->comp = mlx5e_completion_event;
841 mcq->event = mlx5e_cq_error_event;
842 mcq->irqn = irqn;
843 mcq->uar = &priv->cq_uar;
844
845 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
846 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
847
848 cqe->op_own = 0xf1;
849 }
850
851 cq->channel = c;
50cfa25a 852 cq->priv = priv;
f62b8bb8
AV		 853
854 return 0;
855}
856
857static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
858{
859 mlx5_wq_destroy(&cq->wq_ctrl);
860}
861
862static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
863{
50cfa25a 864 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 865 struct mlx5_core_dev *mdev = priv->mdev;
866 struct mlx5_core_cq *mcq = &cq->mcq;
867
868 void *in;
869 void *cqc;
870 int inlen;
0b6e26ce 871 unsigned int irqn_not_used;
f62b8bb8
AV		 872 int eqn;
873 int err;
874
875 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
876 sizeof(u64) * cq->wq_ctrl.buf.npages;
877 in = mlx5_vzalloc(inlen);
878 if (!in)
879 return -ENOMEM;
880
881 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
882
883 memcpy(cqc, param->cqc, sizeof(param->cqc));
884
885 mlx5_fill_page_array(&cq->wq_ctrl.buf,
886 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
887
888 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
889
890 MLX5_SET(cqc, cqc, c_eqn, eqn);
891 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
892 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 893 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 894 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
895
896 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
897
898 kvfree(in);
899
900 if (err)
901 return err;
902
903 mlx5e_cq_arm(cq);
904
905 return 0;
906}
907
908static void mlx5e_disable_cq(struct mlx5e_cq *cq)
909{
50cfa25a 910 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 911 struct mlx5_core_dev *mdev = priv->mdev;
912
913 mlx5_core_destroy_cq(mdev, &cq->mcq);
914}
915
916static int mlx5e_open_cq(struct mlx5e_channel *c,
917 struct mlx5e_cq_param *param,
918 struct mlx5e_cq *cq,
919 u16 moderation_usecs,
920 u16 moderation_frames)
921{
922 int err;
923 struct mlx5e_priv *priv = c->priv;
924 struct mlx5_core_dev *mdev = priv->mdev;
925
926 err = mlx5e_create_cq(c, param, cq);
927 if (err)
928 return err;
929
930 err = mlx5e_enable_cq(cq, param);
931 if (err)
932 goto err_destroy_cq;
933
7524a5d8
GP		 934 if (MLX5_CAP_GEN(mdev, cq_moderation))
935 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
936 moderation_usecs,
937 moderation_frames);
f62b8bb8
AV		 938 return 0;
939
940err_destroy_cq:
941 mlx5e_destroy_cq(cq);
942
943 return err;
944}
945
946static void mlx5e_close_cq(struct mlx5e_cq *cq)
947{
948 mlx5e_disable_cq(cq);
949 mlx5e_destroy_cq(cq);
950}
951
952static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
953{
954 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
955}
956
957static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
958 struct mlx5e_channel_param *cparam)
959{
960 struct mlx5e_priv *priv = c->priv;
961 int err;
962 int tc;
963
964 for (tc = 0; tc < c->num_tc; tc++) {
965 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
966 priv->params.tx_cq_moderation_usec,
967 priv->params.tx_cq_moderation_pkts);
968 if (err)
969 goto err_close_tx_cqs;
f62b8bb8
AV		 970 }
971
972 return 0;
973
974err_close_tx_cqs:
975 for (tc--; tc >= 0; tc--)
976 mlx5e_close_cq(&c->sq[tc].cq);
977
978 return err;
979}
980
981static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
982{
983 int tc;
984
985 for (tc = 0; tc < c->num_tc; tc++)
986 mlx5e_close_cq(&c->sq[tc].cq);
987}
988
989static int mlx5e_open_sqs(struct mlx5e_channel *c,
990 struct mlx5e_channel_param *cparam)
991{
992 int err;
993 int tc;
994
995 for (tc = 0; tc < c->num_tc; tc++) {
996 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
997 if (err)
998 goto err_close_sqs;
999 }
1000
1001 return 0;
1002
1003err_close_sqs:
1004 for (tc--; tc >= 0; tc--)
1005 mlx5e_close_sq(&c->sq[tc]);
1006
1007 return err;
1008}
1009
1010static void mlx5e_close_sqs(struct mlx5e_channel *c)
1011{
1012 int tc;
1013
1014 for (tc = 0; tc < c->num_tc; tc++)
1015 mlx5e_close_sq(&c->sq[tc]);
1016}
1017
5283af89 1018static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 1019{
1020 int i;
1021
1022 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
5283af89
RS		 1023 priv->channeltc_to_txq_map[ix][i] =
1024 ix + i * priv->params.num_channels;
03289b88
SM		 1025}
1026
f62b8bb8
AV		 1027static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1028 struct mlx5e_channel_param *cparam,
1029 struct mlx5e_channel **cp)
1030{
1031 struct net_device *netdev = priv->netdev;
1032 int cpu = mlx5e_get_cpu(priv, ix);
1033 struct mlx5e_channel *c;
1034 int err;
1035
1036 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1037 if (!c)
1038 return -ENOMEM;
1039
1040 c->priv = priv;
1041 c->ix = ix;
1042 c->cpu = cpu;
1043 c->pdev = &priv->mdev->pdev->dev;
1044 c->netdev = priv->netdev;
a606b0f6 1045 c->mkey_be = cpu_to_be32(priv->mkey.key);
a4418a6c 1046 c->num_tc = priv->params.num_tc;
f62b8bb8 1047
5283af89 1048 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1049
f62b8bb8
AV		 1050 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1051
d3c9bc27 1052 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
f62b8bb8
AV		 1053 if (err)
1054 goto err_napi_del;
1055
d3c9bc27
TT		 1056 err = mlx5e_open_tx_cqs(c, cparam);
1057 if (err)
1058 goto err_close_icosq_cq;
1059
f62b8bb8
AV		 1060 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1061 priv->params.rx_cq_moderation_usec,
1062 priv->params.rx_cq_moderation_pkts);
1063 if (err)
1064 goto err_close_tx_cqs;
f62b8bb8
AV		 1065
1066 napi_enable(&c->napi);
1067
d3c9bc27 1068 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1069 if (err)
1070 goto err_disable_napi;
1071
d3c9bc27
TT		 1072 err = mlx5e_open_sqs(c, cparam);
1073 if (err)
1074 goto err_close_icosq;
1075
f62b8bb8
AV		 1076 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1077 if (err)
1078 goto err_close_sqs;
1079
1080 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1081 *cp = c;
1082
1083 return 0;
1084
1085err_close_sqs:
1086 mlx5e_close_sqs(c);
1087
d3c9bc27
TT		 1088err_close_icosq:
1089 mlx5e_close_sq(&c->icosq);
1090
f62b8bb8
AV		 1091err_disable_napi:
1092 napi_disable(&c->napi);
1093 mlx5e_close_cq(&c->rq.cq);
1094
1095err_close_tx_cqs:
1096 mlx5e_close_tx_cqs(c);
1097
d3c9bc27
TT		 1098err_close_icosq_cq:
1099 mlx5e_close_cq(&c->icosq.cq);
1100
f62b8bb8
AV		 1101err_napi_del:
1102 netif_napi_del(&c->napi);
7ae92ae5 1103 napi_hash_del(&c->napi);
f62b8bb8
AV		 1104 kfree(c);
1105
1106 return err;
1107}
1108
1109static void mlx5e_close_channel(struct mlx5e_channel *c)
1110{
1111 mlx5e_close_rq(&c->rq);
1112 mlx5e_close_sqs(c);
d3c9bc27 1113 mlx5e_close_sq(&c->icosq);
f62b8bb8
AV		 1114 napi_disable(&c->napi);
1115 mlx5e_close_cq(&c->rq.cq);
1116 mlx5e_close_tx_cqs(c);
d3c9bc27 1117 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1118 netif_napi_del(&c->napi);
7ae92ae5
ED		 1119
1120 napi_hash_del(&c->napi);
1121 synchronize_rcu();
1122
f62b8bb8
AV		 1123 kfree(c);
1124}
1125
1126static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1127 struct mlx5e_rq_param *param)
1128{
1129 void *rqc = param->rqc;
1130 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1131
461017cb
TT		 1132 switch (priv->params.rq_wq_type) {
1133 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1134 MLX5_SET(wq, wq, log_wqe_num_of_strides,
d9d9f156 1135 priv->params.mpwqe_log_num_strides - 9);
461017cb 1136 MLX5_SET(wq, wq, log_wqe_stride_size,
d9d9f156 1137 priv->params.mpwqe_log_stride_sz - 6);
461017cb
TT		 1138 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1139 break;
1140 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1141 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1142 }
1143
f62b8bb8
AV		 1144 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1145 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1146 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1147 MLX5_SET(wq, wq, pd, priv->pdn);
593cf338 1148 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1149
311c7c71 1150 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1151 param->wq.linear = 1;
1152}
1153
556dd1b9
TT		 1154static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1155{
1156 void *rqc = param->rqc;
1157 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1158
1159 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1160 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1161}
1162
d3c9bc27
TT		 1163static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1164 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1165{
1166 void *sqc = param->sqc;
1167 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1168
f62b8bb8
AV		 1169 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1170 MLX5_SET(wq, wq, pd, priv->pdn);
1171
311c7c71 1172 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1173}
1174
1175static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1176 struct mlx5e_sq_param *param)
1177{
1178 void *sqc = param->sqc;
1179 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1180
1181 mlx5e_build_sq_param_common(priv, param);
1182 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1183
58d52291 1184 param->max_inline = priv->params.tx_max_inline;
f62b8bb8
AV		 1185}
1186
1187static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1188 struct mlx5e_cq_param *param)
1189{
1190 void *cqc = param->cqc;
1191
1192 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1193}
1194
1195static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1196 struct mlx5e_cq_param *param)
1197{
1198 void *cqc = param->cqc;
461017cb 1199 u8 log_cq_size;
f62b8bb8 1200
461017cb
TT		 1201 switch (priv->params.rq_wq_type) {
1202 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1203 log_cq_size = priv->params.log_rq_size +
d9d9f156 1204 priv->params.mpwqe_log_num_strides;
461017cb
TT		 1205 break;
1206 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1207 log_cq_size = priv->params.log_rq_size;
1208 }
1209
1210 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
7219ab34
TT		 1211 if (priv->params.rx_cqe_compress) {
1212 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1213 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1214 }
f62b8bb8
AV		 1215
1216 mlx5e_build_common_cq_param(priv, param);
1217}
1218
1219static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1220 struct mlx5e_cq_param *param)
1221{
1222 void *cqc = param->cqc;
1223
d3c9bc27 1224 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1225
1226 mlx5e_build_common_cq_param(priv, param);
1227}
1228
d3c9bc27
TT		 1229static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1230 struct mlx5e_cq_param *param,
1231 u8 log_wq_size)
1232{
1233 void *cqc = param->cqc;
1234
1235 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1236
1237 mlx5e_build_common_cq_param(priv, param);
1238}
1239
1240static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1241 struct mlx5e_sq_param *param,
1242 u8 log_wq_size)
1243{
1244 void *sqc = param->sqc;
1245 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1246
1247 mlx5e_build_sq_param_common(priv, param);
1248
1249 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1250 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1251
1252 param->icosq = true;
1253}
1254
6b87663f 1255static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
f62b8bb8 1256{
bc77b240 1257 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1258
f62b8bb8
AV		 1259 mlx5e_build_rq_param(priv, &cparam->rq);
1260 mlx5e_build_sq_param(priv, &cparam->sq);
d3c9bc27 1261 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1262 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1263 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1264 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1265}
1266
1267static int mlx5e_open_channels(struct mlx5e_priv *priv)
1268{
6b87663f 1269 struct mlx5e_channel_param *cparam;
a4418a6c 1270 int nch = priv->params.num_channels;
03289b88 1271 int err = -ENOMEM;
f62b8bb8
AV		 1272 int i;
1273 int j;
1274
a4418a6c
AS		 1275 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1276 GFP_KERNEL);
03289b88 1277
a4418a6c 1278 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1279 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1280
6b87663f
AB		 1281 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1282
1283 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
03289b88 1284 goto err_free_txq_to_sq_map;
f62b8bb8 1285
6b87663f
AB		 1286 mlx5e_build_channel_param(priv, cparam);
1287
a4418a6c 1288 for (i = 0; i < nch; i++) {
6b87663f 1289 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
f62b8bb8
AV		 1290 if (err)
1291 goto err_close_channels;
1292 }
1293
a4418a6c 1294 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1295 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1296 if (err)
1297 goto err_close_channels;
1298 }
1299
6b87663f 1300 kfree(cparam);
f62b8bb8
AV		 1301 return 0;
1302
1303err_close_channels:
1304 for (i--; i >= 0; i--)
1305 mlx5e_close_channel(priv->channel[i]);
1306
03289b88
SM		 1307err_free_txq_to_sq_map:
1308 kfree(priv->txq_to_sq_map);
f62b8bb8 1309 kfree(priv->channel);
6b87663f 1310 kfree(cparam);
f62b8bb8
AV		 1311
1312 return err;
1313}
1314
1315static void mlx5e_close_channels(struct mlx5e_priv *priv)
1316{
1317 int i;
1318
1319 for (i = 0; i < priv->params.num_channels; i++)
1320 mlx5e_close_channel(priv->channel[i]);
1321
03289b88 1322 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1323 kfree(priv->channel);
1324}
1325
2be6967c
SM		 1326static int mlx5e_rx_hash_fn(int hfunc)
1327{
1328 return (hfunc == ETH_RSS_HASH_TOP) ?
1329 MLX5_RX_HASH_FN_TOEPLITZ :
1330 MLX5_RX_HASH_FN_INVERTED_XOR8;
1331}
1332
1333static int mlx5e_bits_invert(unsigned long a, int size)
1334{
1335 int inv = 0;
1336 int i;
1337
1338 for (i = 0; i < size; i++)
1339 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1340
1341 return inv;
1342}
1343
936896e9
AS		 1344static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1345{
1346 int i;
1347
1348 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1349 int ix = i;
1da36696 1350 u32 rqn;
936896e9
AS		 1351
1352 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1353 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1354
2d75b2bc 1355 ix = priv->params.indirection_rqt[ix];
1da36696
TT		 1356 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1357 priv->channel[ix]->rq.rqn :
1358 priv->drop_rq.rqn;
1359 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
936896e9
AS		 1360 }
1361}
1362
1da36696
TT		 1363static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1364 int ix)
4cbeaff5 1365{
1da36696
TT		 1366 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1367 priv->channel[ix]->rq.rqn :
1368 priv->drop_rq.rqn;
4cbeaff5 1369
1da36696 1370 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
4cbeaff5
AS		 1371}
1372
1da36696 1373static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn)
f62b8bb8
AV		 1374{
1375 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1376 void *rqtc;
1377 int inlen;
1378 int err;
1da36696 1379 u32 *in;
f62b8bb8 1380
f62b8bb8
AV		 1381 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1382 in = mlx5_vzalloc(inlen);
1383 if (!in)
1384 return -ENOMEM;
1385
1386 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1387
1388 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1389 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1390
1da36696
TT		 1391 if (sz > 1) /* RSS */
1392 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1393 else
1394 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2be6967c 1395
1da36696 1396 err = mlx5_core_create_rqt(mdev, in, inlen, rqtn);
f62b8bb8
AV		 1397
1398 kvfree(in);
1da36696
TT		 1399 return err;
1400}
1401
1402static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn)
1403{
1404 mlx5_core_destroy_rqt(priv->mdev, rqtn);
1405}
1406
1407static int mlx5e_create_rqts(struct mlx5e_priv *priv)
1408{
1409 int nch = mlx5e_get_max_num_channels(priv->mdev);
1410 u32 *rqtn;
1411 int err;
1412 int ix;
1413
1414 /* Indirect RQT */
1415 rqtn = &priv->indir_rqtn;
1416 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn);
1417 if (err)
1418 return err;
1419
1420 /* Direct RQTs */
1421 for (ix = 0; ix < nch; ix++) {
1422 rqtn = &priv->direct_tir[ix].rqtn;
1423 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn);
1424 if (err)
1425 goto err_destroy_rqts;
1426 }
1427
1428 return 0;
1429
1430err_destroy_rqts:
1431 for (ix--; ix >= 0; ix--)
1432 mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn);
1433
1434 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
f62b8bb8
AV		 1435
1436 return err;
1437}
1438
1da36696
TT		 1439static void mlx5e_destroy_rqts(struct mlx5e_priv *priv)
1440{
1441 int nch = mlx5e_get_max_num_channels(priv->mdev);
1442 int i;
1443
1444 for (i = 0; i < nch; i++)
1445 mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn);
1446
1447 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1448}
1449
1450int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
5c50368f
AS		 1451{
1452 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 1453 void *rqtc;
1454 int inlen;
1da36696 1455 u32 *in;
5c50368f
AS		 1456 int err;
1457
5c50368f
AS		 1458 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1459 in = mlx5_vzalloc(inlen);
1460 if (!in)
1461 return -ENOMEM;
1462
1463 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1464
1465 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1da36696
TT		 1466 if (sz > 1) /* RSS */
1467 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1468 else
1469 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
5c50368f
AS		 1470
1471 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1472
1da36696 1473 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 1474
1475 kvfree(in);
1476
1477 return err;
1478}
1479
40ab6a6e
AS		 1480static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1481{
1da36696
TT		 1482 u32 rqtn;
1483 int ix;
1484
1485 rqtn = priv->indir_rqtn;
1486 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1487 for (ix = 0; ix < priv->params.num_channels; ix++) {
1488 rqtn = priv->direct_tir[ix].rqtn;
1489 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1490 }
40ab6a6e
AS		 1491}
1492
5c50368f
AS		 1493static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1494{
1495 if (!priv->params.lro_en)
1496 return;
1497
1498#define ROUGH_MAX_L2_L3_HDR_SZ 256
1499
1500 MLX5_SET(tirc, tirc, lro_enable_mask,
1501 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1502 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1503 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1504 (priv->params.lro_wqe_sz -
1505 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1506 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1507 MLX5_CAP_ETH(priv->mdev,
d9a40271 1508 lro_timer_supported_periods[2]));
5c50368f
AS		 1509}
1510
bdfc028d
TT		 1511void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1512{
1513 MLX5_SET(tirc, tirc, rx_hash_fn,
1514 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1515 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1516 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1517 rx_hash_toeplitz_key);
1518 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1519 rx_hash_toeplitz_key);
1520
1521 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1522 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1523 }
1524}
1525
ab0394fe 1526static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 1527{
1528 struct mlx5_core_dev *mdev = priv->mdev;
1529
1530 void *in;
1531 void *tirc;
1532 int inlen;
1533 int err;
ab0394fe 1534 int tt;
1da36696 1535 int ix;
5c50368f
AS		 1536
1537 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1538 in = mlx5_vzalloc(inlen);
1539 if (!in)
1540 return -ENOMEM;
1541
1542 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1543 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1544
1545 mlx5e_build_tir_ctx_lro(tirc, priv);
1546
1da36696
TT		 1547 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1548 err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in,
1549 inlen);
ab0394fe 1550 if (err)
1da36696 1551 goto free_in;
ab0394fe 1552 }
5c50368f 1553
1da36696
TT		 1554 for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) {
1555 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1556 in, inlen);
1557 if (err)
1558 goto free_in;
1559 }
1560
1561free_in:
5c50368f
AS		 1562 kvfree(in);
1563
1564 return err;
1565}
1566
1da36696 1567static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
66189961
TT		 1568{
1569 void *in;
1570 int inlen;
1571 int err;
1da36696 1572 int i;
66189961
TT		 1573
1574 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1575 in = mlx5_vzalloc(inlen);
1576 if (!in)
1577 return -ENOMEM;
1578
1579 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1580
1da36696
TT		 1581 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
1582 err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in,
1583 inlen);
1584 if (err)
1585 return err;
1586 }
66189961 1587
1da36696
TT		 1588 for (i = 0; i < priv->params.num_channels; i++) {
1589 err = mlx5_core_modify_tir(priv->mdev,
1590 priv->direct_tir[i].tirn, in,
1591 inlen);
66189961
TT		 1592 if (err)
1593 return err;
1594 }
1595
1da36696
TT		 1596 kvfree(in);
1597
66189961
TT		 1598 return 0;
1599}
1600
cd255eff 1601static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 1602{
40ab6a6e 1603 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 1604 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 1605 int err;
1606
cd255eff 1607 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 1608 if (err)
1609 return err;
1610
cd255eff
SM		 1611 /* Update vport context MTU */
1612 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1613 return 0;
1614}
40ab6a6e 1615
cd255eff
SM		 1616static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1617{
1618 struct mlx5_core_dev *mdev = priv->mdev;
1619 u16 hw_mtu = 0;
1620 int err;
40ab6a6e 1621
cd255eff
SM		 1622 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1623 if (err || !hw_mtu) /* fallback to port oper mtu */
1624 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1625
1626 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1627}
1628
1629static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1630{
1631 struct mlx5e_priv *priv = netdev_priv(netdev);
1632 u16 mtu;
1633 int err;
1634
1635 err = mlx5e_set_mtu(priv, netdev->mtu);
1636 if (err)
1637 return err;
40ab6a6e 1638
cd255eff
SM		 1639 mlx5e_query_mtu(priv, &mtu);
1640 if (mtu != netdev->mtu)
1641 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1642 __func__, mtu, netdev->mtu);
40ab6a6e 1643
cd255eff 1644 netdev->mtu = mtu;
40ab6a6e
AS		 1645 return 0;
1646}
1647
08fb1dac
SM		 1648static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1649{
1650 struct mlx5e_priv *priv = netdev_priv(netdev);
1651 int nch = priv->params.num_channels;
1652 int ntc = priv->params.num_tc;
1653 int tc;
1654
1655 netdev_reset_tc(netdev);
1656
1657 if (ntc == 1)
1658 return;
1659
1660 netdev_set_num_tc(netdev, ntc);
1661
1662 for (tc = 0; tc < ntc; tc++)
1663 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1664}
1665
40ab6a6e
AS		 1666int mlx5e_open_locked(struct net_device *netdev)
1667{
1668 struct mlx5e_priv *priv = netdev_priv(netdev);
1669 int num_txqs;
1670 int err;
1671
1672 set_bit(MLX5E_STATE_OPENED, &priv->state);
1673
08fb1dac
SM		 1674 mlx5e_netdev_set_tcs(netdev);
1675
40ab6a6e
AS		 1676 num_txqs = priv->params.num_channels * priv->params.num_tc;
1677 netif_set_real_num_tx_queues(netdev, num_txqs);
1678 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1679
1680 err = mlx5e_set_dev_port_mtu(netdev);
1681 if (err)
343b29f3 1682 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1683
1684 err = mlx5e_open_channels(priv);
1685 if (err) {
1686 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1687 __func__, err);
343b29f3 1688 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1689 }
1690
66189961
TT		 1691 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1692 if (err) {
1693 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1694 __func__, err);
1695 goto err_close_channels;
1696 }
1697
40ab6a6e 1698 mlx5e_redirect_rqts(priv);
ce89ef36 1699 mlx5e_update_carrier(priv);
ef9814de 1700 mlx5e_timestamp_init(priv);
5a7b27eb
MG		 1701#ifdef CONFIG_RFS_ACCEL
1702 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1703#endif
40ab6a6e 1704
7bb29755 1705 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 1706
9b37b07f 1707 return 0;
343b29f3 1708
66189961
TT		 1709err_close_channels:
1710 mlx5e_close_channels(priv);
343b29f3
AS		 1711err_clear_state_opened_flag:
1712 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1713 return err;
40ab6a6e
AS		 1714}
1715
1716static int mlx5e_open(struct net_device *netdev)
1717{
1718 struct mlx5e_priv *priv = netdev_priv(netdev);
1719 int err;
1720
1721 mutex_lock(&priv->state_lock);
1722 err = mlx5e_open_locked(netdev);
1723 mutex_unlock(&priv->state_lock);
1724
1725 return err;
1726}
1727
1728int mlx5e_close_locked(struct net_device *netdev)
1729{
1730 struct mlx5e_priv *priv = netdev_priv(netdev);
1731
a1985740
AS		 1732 /* May already be CLOSED in case a previous configuration operation
1733 * (e.g RX/TX queue size change) that involves close&open failed.
1734 */
1735 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1736 return 0;
1737
40ab6a6e
AS		 1738 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1739
ef9814de 1740 mlx5e_timestamp_cleanup(priv);
40ab6a6e 1741 netif_carrier_off(priv->netdev);
ce89ef36 1742 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 1743 mlx5e_close_channels(priv);
1744
1745 return 0;
1746}
1747
1748static int mlx5e_close(struct net_device *netdev)
1749{
1750 struct mlx5e_priv *priv = netdev_priv(netdev);
1751 int err;
1752
1753 mutex_lock(&priv->state_lock);
1754 err = mlx5e_close_locked(netdev);
1755 mutex_unlock(&priv->state_lock);
1756
1757 return err;
1758}
1759
1760static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1761 struct mlx5e_rq *rq,
1762 struct mlx5e_rq_param *param)
1763{
1764 struct mlx5_core_dev *mdev = priv->mdev;
1765 void *rqc = param->rqc;
1766 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1767 int err;
1768
1769 param->wq.db_numa_node = param->wq.buf_numa_node;
1770
1771 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1772 &rq->wq_ctrl);
1773 if (err)
1774 return err;
1775
1776 rq->priv = priv;
1777
1778 return 0;
1779}
1780
1781static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1782 struct mlx5e_cq *cq,
1783 struct mlx5e_cq_param *param)
1784{
1785 struct mlx5_core_dev *mdev = priv->mdev;
1786 struct mlx5_core_cq *mcq = &cq->mcq;
1787 int eqn_not_used;
0b6e26ce 1788 unsigned int irqn;
40ab6a6e
AS		 1789 int err;
1790
1791 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1792 &cq->wq_ctrl);
1793 if (err)
1794 return err;
1795
1796 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1797
1798 mcq->cqe_sz = 64;
1799 mcq->set_ci_db = cq->wq_ctrl.db.db;
1800 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1801 *mcq->set_ci_db = 0;
1802 *mcq->arm_db = 0;
1803 mcq->vector = param->eq_ix;
1804 mcq->comp = mlx5e_completion_event;
1805 mcq->event = mlx5e_cq_error_event;
1806 mcq->irqn = irqn;
1807 mcq->uar = &priv->cq_uar;
1808
1809 cq->priv = priv;
1810
1811 return 0;
1812}
1813
1814static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1815{
1816 struct mlx5e_cq_param cq_param;
1817 struct mlx5e_rq_param rq_param;
1818 struct mlx5e_rq *rq = &priv->drop_rq;
1819 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1820 int err;
1821
1822 memset(&cq_param, 0, sizeof(cq_param));
1823 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 1824 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 1825
1826 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1827 if (err)
1828 return err;
1829
1830 err = mlx5e_enable_cq(cq, &cq_param);
1831 if (err)
1832 goto err_destroy_cq;
1833
1834 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1835 if (err)
1836 goto err_disable_cq;
1837
1838 err = mlx5e_enable_rq(rq, &rq_param);
1839 if (err)
1840 goto err_destroy_rq;
1841
1842 return 0;
1843
1844err_destroy_rq:
1845 mlx5e_destroy_rq(&priv->drop_rq);
1846
1847err_disable_cq:
1848 mlx5e_disable_cq(&priv->drop_rq.cq);
1849
1850err_destroy_cq:
1851 mlx5e_destroy_cq(&priv->drop_rq.cq);
1852
1853 return err;
1854}
1855
1856static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1857{
1858 mlx5e_disable_rq(&priv->drop_rq);
1859 mlx5e_destroy_rq(&priv->drop_rq);
1860 mlx5e_disable_cq(&priv->drop_rq.cq);
1861 mlx5e_destroy_cq(&priv->drop_rq.cq);
1862}
1863
1864static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1865{
1866 struct mlx5_core_dev *mdev = priv->mdev;
1867 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1868 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1869
1870 memset(in, 0, sizeof(in));
1871
08fb1dac 1872 MLX5_SET(tisc, tisc, prio, tc << 1);
40ab6a6e
AS		 1873 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1874
1875 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1876}
1877
1878static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1879{
1880 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1881}
1882
1883static int mlx5e_create_tises(struct mlx5e_priv *priv)
1884{
1885 int err;
1886 int tc;
1887
08fb1dac 1888 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
40ab6a6e
AS		 1889 err = mlx5e_create_tis(priv, tc);
1890 if (err)
1891 goto err_close_tises;
1892 }
1893
1894 return 0;
1895
1896err_close_tises:
1897 for (tc--; tc >= 0; tc--)
1898 mlx5e_destroy_tis(priv, tc);
1899
1900 return err;
1901}
1902
1903static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1904{
1905 int tc;
1906
08fb1dac 1907 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
40ab6a6e
AS		 1908 mlx5e_destroy_tis(priv, tc);
1909}
1910
1da36696
TT		 1911static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
1912 enum mlx5e_traffic_types tt)
f62b8bb8
AV		 1913{
1914 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1915
3191e05f
AS		 1916 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1917
5a6f8aef
AS		 1918#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1919 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 1920
5a6f8aef
AS		 1921#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1922 MLX5_HASH_FIELD_SEL_DST_IP |\
1923 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1924 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 1925
a741749f
AS		 1926#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1927 MLX5_HASH_FIELD_SEL_DST_IP |\
1928 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1929
5c50368f 1930 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 1931
4cbeaff5 1932 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1da36696
TT		 1933 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn);
1934 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 1935
1936 switch (tt) {
1937 case MLX5E_TT_IPV4_TCP:
1938 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1939 MLX5_L3_PROT_TYPE_IPV4);
1940 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1941 MLX5_L4_PROT_TYPE_TCP);
1942 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1943 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1944 break;
1945
1946 case MLX5E_TT_IPV6_TCP:
1947 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1948 MLX5_L3_PROT_TYPE_IPV6);
1949 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1950 MLX5_L4_PROT_TYPE_TCP);
1951 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1952 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1953 break;
1954
1955 case MLX5E_TT_IPV4_UDP:
1956 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1957 MLX5_L3_PROT_TYPE_IPV4);
1958 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1959 MLX5_L4_PROT_TYPE_UDP);
1960 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1961 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1962 break;
1963
1964 case MLX5E_TT_IPV6_UDP:
1965 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1966 MLX5_L3_PROT_TYPE_IPV6);
1967 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1968 MLX5_L4_PROT_TYPE_UDP);
1969 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1970 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1971 break;
1972
a741749f
AS		 1973 case MLX5E_TT_IPV4_IPSEC_AH:
1974 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1975 MLX5_L3_PROT_TYPE_IPV4);
1976 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1977 MLX5_HASH_IP_IPSEC_SPI);
1978 break;
1979
1980 case MLX5E_TT_IPV6_IPSEC_AH:
1981 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1982 MLX5_L3_PROT_TYPE_IPV6);
1983 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1984 MLX5_HASH_IP_IPSEC_SPI);
1985 break;
1986
1987 case MLX5E_TT_IPV4_IPSEC_ESP:
1988 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1989 MLX5_L3_PROT_TYPE_IPV4);
1990 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1991 MLX5_HASH_IP_IPSEC_SPI);
1992 break;
1993
1994 case MLX5E_TT_IPV6_IPSEC_ESP:
1995 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1996 MLX5_L3_PROT_TYPE_IPV6);
1997 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1998 MLX5_HASH_IP_IPSEC_SPI);
1999 break;
2000
f62b8bb8
AV		 2001 case MLX5E_TT_IPV4:
2002 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2003 MLX5_L3_PROT_TYPE_IPV4);
2004 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2005 MLX5_HASH_IP);
2006 break;
2007
2008 case MLX5E_TT_IPV6:
2009 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2010 MLX5_L3_PROT_TYPE_IPV6);
2011 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2012 MLX5_HASH_IP);
2013 break;
1da36696
TT		 2014 default:
2015 WARN_ONCE(true,
2016 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
f62b8bb8
AV		 2017 }
2018}
2019
1da36696
TT		 2020static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2021 u32 rqtn)
f62b8bb8 2022{
1da36696
TT		 2023 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2024
2025 mlx5e_build_tir_ctx_lro(tirc, priv);
2026
2027 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2028 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2029 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2030}
2031
2032static int mlx5e_create_tirs(struct mlx5e_priv *priv)
2033{
2034 int nch = mlx5e_get_max_num_channels(priv->mdev);
f62b8bb8
AV		 2035 void *tirc;
2036 int inlen;
1da36696 2037 u32 *tirn;
f62b8bb8 2038 int err;
1da36696
TT		 2039 u32 *in;
2040 int ix;
2041 int tt;
f62b8bb8
AV		 2042
2043 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2044 in = mlx5_vzalloc(inlen);
2045 if (!in)
2046 return -ENOMEM;
2047
1da36696
TT		 2048 /* indirect tirs */
2049 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2050 memset(in, 0, inlen);
2051 tirn = &priv->indir_tirn[tt];
2052 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2053 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2054 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
f62b8bb8 2055 if (err)
40ab6a6e 2056 goto err_destroy_tirs;
f62b8bb8
AV		 2057 }
2058
1da36696
TT		 2059 /* direct tirs */
2060 for (ix = 0; ix < nch; ix++) {
2061 memset(in, 0, inlen);
2062 tirn = &priv->direct_tir[ix].tirn;
2063 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2064 mlx5e_build_direct_tir_ctx(priv, tirc,
2065 priv->direct_tir[ix].rqtn);
2066 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2067 if (err)
2068 goto err_destroy_ch_tirs;
2069 }
2070
2071 kvfree(in);
2072
f62b8bb8
AV		 2073 return 0;
2074
1da36696
TT		 2075err_destroy_ch_tirs:
2076 for (ix--; ix >= 0; ix--)
2077 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn);
2078
40ab6a6e 2079err_destroy_tirs:
1da36696
TT		 2080 for (tt--; tt >= 0; tt--)
2081 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]);
2082
2083 kvfree(in);
f62b8bb8
AV		 2084
2085 return err;
2086}
2087
40ab6a6e 2088static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
f62b8bb8 2089{
1da36696 2090 int nch = mlx5e_get_max_num_channels(priv->mdev);
f62b8bb8
AV		 2091 int i;
2092
1da36696
TT		 2093 for (i = 0; i < nch; i++)
2094 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn);
2095
2096 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2097 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]);
f62b8bb8
AV		 2098}
2099
36350114
GP		 2100int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2101{
2102 int err = 0;
2103 int i;
2104
2105 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2106 return 0;
2107
2108 for (i = 0; i < priv->params.num_channels; i++) {
2109 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2110 if (err)
2111 return err;
2112 }
2113
2114 return 0;
2115}
2116
08fb1dac
SM		 2117static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2118{
2119 struct mlx5e_priv *priv = netdev_priv(netdev);
2120 bool was_opened;
2121 int err = 0;
2122
2123 if (tc && tc != MLX5E_MAX_NUM_TC)
2124 return -EINVAL;
2125
2126 mutex_lock(&priv->state_lock);
2127
2128 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2129 if (was_opened)
2130 mlx5e_close_locked(priv->netdev);
2131
2132 priv->params.num_tc = tc ? tc : 1;
2133
2134 if (was_opened)
2135 err = mlx5e_open_locked(priv->netdev);
2136
2137 mutex_unlock(&priv->state_lock);
2138
2139 return err;
2140}
2141
2142static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2143 __be16 proto, struct tc_to_netdev *tc)
2144{
e8f887ac
AV		 2145 struct mlx5e_priv *priv = netdev_priv(dev);
2146
2147 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2148 goto mqprio;
2149
2150 switch (tc->type) {
e3a2b7ed
AV		 2151 case TC_SETUP_CLSFLOWER:
2152 switch (tc->cls_flower->command) {
2153 case TC_CLSFLOWER_REPLACE:
2154 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2155 case TC_CLSFLOWER_DESTROY:
2156 return mlx5e_delete_flower(priv, tc->cls_flower);
2157 }
e8f887ac
AV		 2158 default:
2159 return -EOPNOTSUPP;
2160 }
2161
2162mqprio:
67ba422e 2163 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2164 return -EINVAL;
2165
2166 return mlx5e_setup_tc(dev, tc->tc);
2167}
2168
f62b8bb8
AV		 2169static struct rtnl_link_stats64 *
2170mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2171{
2172 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2173 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2174 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2175 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2176
9218b44d
GP		 2177 stats->rx_packets = sstats->rx_packets;
2178 stats->rx_bytes = sstats->rx_bytes;
2179 stats->tx_packets = sstats->tx_packets;
2180 stats->tx_bytes = sstats->tx_bytes;
269e6b3a
GP		 2181
2182 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
9218b44d 2183 stats->tx_dropped = sstats->tx_queue_dropped;
269e6b3a
GP		 2184
2185 stats->rx_length_errors =
9218b44d
GP		 2186 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2187 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2188 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2189 stats->rx_crc_errors =
9218b44d
GP		 2190 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2191 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2192 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2193 stats->tx_carrier_errors =
9218b44d 2194 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2195 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2196 stats->rx_frame_errors;
2197 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2198
2199 /* vport multicast also counts packets that are dropped due to steering
2200 * or rx out of buffer
2201 */
9218b44d
GP		 2202 stats->multicast =
2203 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 2204
2205 return stats;
2206}
2207
2208static void mlx5e_set_rx_mode(struct net_device *dev)
2209{
2210 struct mlx5e_priv *priv = netdev_priv(dev);
2211
7bb29755 2212 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2213}
2214
2215static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2216{
2217 struct mlx5e_priv *priv = netdev_priv(netdev);
2218 struct sockaddr *saddr = addr;
2219
2220 if (!is_valid_ether_addr(saddr->sa_data))
2221 return -EADDRNOTAVAIL;
2222
2223 netif_addr_lock_bh(netdev);
2224 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2225 netif_addr_unlock_bh(netdev);
2226
7bb29755 2227 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2228
2229 return 0;
2230}
2231
0e405443
GP		 2232#define MLX5E_SET_FEATURE(netdev, feature, enable) \
2233 do { \
2234 if (enable) \
2235 netdev->features |= feature; \
2236 else \
2237 netdev->features &= ~feature; \
2238 } while (0)
2239
2240typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2241
2242static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 2243{
2244 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 2245 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2246 int err;
f62b8bb8
AV		 2247
2248 mutex_lock(&priv->state_lock);
f62b8bb8 2249
0e405443
GP		 2250 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2251 mlx5e_close_locked(priv->netdev);
98e81b0a 2252
0e405443
GP		 2253 priv->params.lro_en = enable;
2254 err = mlx5e_modify_tirs_lro(priv);
2255 if (err) {
2256 netdev_err(netdev, "lro modify failed, %d\n", err);
2257 priv->params.lro_en = !enable;
98e81b0a 2258 }
f62b8bb8 2259
0e405443
GP		 2260 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2261 mlx5e_open_locked(priv->netdev);
2262
9b37b07f
AS		 2263 mutex_unlock(&priv->state_lock);
2264
0e405443
GP		 2265 return err;
2266}
2267
2268static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2269{
2270 struct mlx5e_priv *priv = netdev_priv(netdev);
2271
2272 if (enable)
2273 mlx5e_enable_vlan_filter(priv);
2274 else
2275 mlx5e_disable_vlan_filter(priv);
2276
2277 return 0;
2278}
2279
2280static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2281{
2282 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 2283
0e405443 2284 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 2285 netdev_err(netdev,
2286 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2287 return -EINVAL;
2288 }
2289
0e405443
GP		 2290 return 0;
2291}
2292
94cb1ebb
EBE		 2293static int set_feature_rx_all(struct net_device *netdev, bool enable)
2294{
2295 struct mlx5e_priv *priv = netdev_priv(netdev);
2296 struct mlx5_core_dev *mdev = priv->mdev;
2297
2298 return mlx5_set_port_fcs(mdev, !enable);
2299}
2300
36350114
GP		 2301static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2302{
2303 struct mlx5e_priv *priv = netdev_priv(netdev);
2304 int err;
2305
2306 mutex_lock(&priv->state_lock);
2307
2308 priv->params.vlan_strip_disable = !enable;
2309 err = mlx5e_modify_rqs_vsd(priv, !enable);
2310 if (err)
2311 priv->params.vlan_strip_disable = enable;
2312
2313 mutex_unlock(&priv->state_lock);
2314
2315 return err;
2316}
2317
45bf454a
MG		 2318#ifdef CONFIG_RFS_ACCEL
2319static int set_feature_arfs(struct net_device *netdev, bool enable)
2320{
2321 struct mlx5e_priv *priv = netdev_priv(netdev);
2322 int err;
2323
2324 if (enable)
2325 err = mlx5e_arfs_enable(priv);
2326 else
2327 err = mlx5e_arfs_disable(priv);
2328
2329 return err;
2330}
2331#endif
2332
0e405443
GP		 2333static int mlx5e_handle_feature(struct net_device *netdev,
2334 netdev_features_t wanted_features,
2335 netdev_features_t feature,
2336 mlx5e_feature_handler feature_handler)
2337{
2338 netdev_features_t changes = wanted_features ^ netdev->features;
2339 bool enable = !!(wanted_features & feature);
2340 int err;
2341
2342 if (!(changes & feature))
2343 return 0;
2344
2345 err = feature_handler(netdev, enable);
2346 if (err) {
2347 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2348 enable ? "Enable" : "Disable", feature, err);
2349 return err;
2350 }
2351
2352 MLX5E_SET_FEATURE(netdev, feature, enable);
2353 return 0;
2354}
2355
2356static int mlx5e_set_features(struct net_device *netdev,
2357 netdev_features_t features)
2358{
2359 int err;
2360
2361 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2362 set_feature_lro);
2363 err |= mlx5e_handle_feature(netdev, features,
2364 NETIF_F_HW_VLAN_CTAG_FILTER,
2365 set_feature_vlan_filter);
2366 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2367 set_feature_tc_num_filters);
94cb1ebb
EBE		 2368 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2369 set_feature_rx_all);
36350114
GP		 2370 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2371 set_feature_rx_vlan);
45bf454a
MG		 2372#ifdef CONFIG_RFS_ACCEL
2373 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2374 set_feature_arfs);
2375#endif
0e405443
GP		 2376
2377 return err ? -EINVAL : 0;
f62b8bb8
AV		 2378}
2379
d8edd246
SM		 2380#define MXL5_HW_MIN_MTU 64
2381#define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2382
f62b8bb8
AV		 2383static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2384{
2385 struct mlx5e_priv *priv = netdev_priv(netdev);
2386 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 2387 bool was_opened;
046339ea 2388 u16 max_mtu;
d8edd246 2389 u16 min_mtu;
98e81b0a 2390 int err = 0;
f62b8bb8 2391
facc9699 2392 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 2393
50a9eea6 2394 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
d8edd246 2395 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
50a9eea6 2396
d8edd246 2397 if (new_mtu > max_mtu || new_mtu < min_mtu) {
facc9699 2398 netdev_err(netdev,
d8edd246
SM		 2399 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2400 __func__, new_mtu, min_mtu, max_mtu);
f62b8bb8
AV		 2401 return -EINVAL;
2402 }
2403
2404 mutex_lock(&priv->state_lock);
98e81b0a
AS		 2405
2406 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2407 if (was_opened)
2408 mlx5e_close_locked(netdev);
2409
f62b8bb8 2410 netdev->mtu = new_mtu;
98e81b0a
AS		 2411
2412 if (was_opened)
2413 err = mlx5e_open_locked(netdev);
2414
f62b8bb8
AV		 2415 mutex_unlock(&priv->state_lock);
2416
2417 return err;
2418}
2419
ef9814de
EBE		 2420static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2421{
2422 switch (cmd) {
2423 case SIOCSHWTSTAMP:
2424 return mlx5e_hwstamp_set(dev, ifr);
2425 case SIOCGHWTSTAMP:
2426 return mlx5e_hwstamp_get(dev, ifr);
2427 default:
2428 return -EOPNOTSUPP;
2429 }
2430}
2431
66e49ded
SM		 2432static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2433{
2434 struct mlx5e_priv *priv = netdev_priv(dev);
2435 struct mlx5_core_dev *mdev = priv->mdev;
2436
2437 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2438}
2439
2440static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2441{
2442 struct mlx5e_priv *priv = netdev_priv(dev);
2443 struct mlx5_core_dev *mdev = priv->mdev;
2444
2445 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2446 vlan, qos);
2447}
2448
f942380c
MHY		 2449static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2450{
2451 struct mlx5e_priv *priv = netdev_priv(dev);
2452 struct mlx5_core_dev *mdev = priv->mdev;
2453
2454 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2455}
2456
1edc57e2
MHY		 2457static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2458{
2459 struct mlx5e_priv *priv = netdev_priv(dev);
2460 struct mlx5_core_dev *mdev = priv->mdev;
2461
2462 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2463}
66e49ded
SM		 2464static int mlx5_vport_link2ifla(u8 esw_link)
2465{
2466 switch (esw_link) {
2467 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2468 return IFLA_VF_LINK_STATE_DISABLE;
2469 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2470 return IFLA_VF_LINK_STATE_ENABLE;
2471 }
2472 return IFLA_VF_LINK_STATE_AUTO;
2473}
2474
2475static int mlx5_ifla_link2vport(u8 ifla_link)
2476{
2477 switch (ifla_link) {
2478 case IFLA_VF_LINK_STATE_DISABLE:
2479 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2480 case IFLA_VF_LINK_STATE_ENABLE:
2481 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2482 }
2483 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2484}
2485
2486static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2487 int link_state)
2488{
2489 struct mlx5e_priv *priv = netdev_priv(dev);
2490 struct mlx5_core_dev *mdev = priv->mdev;
2491
2492 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2493 mlx5_ifla_link2vport(link_state));
2494}
2495
2496static int mlx5e_get_vf_config(struct net_device *dev,
2497 int vf, struct ifla_vf_info *ivi)
2498{
2499 struct mlx5e_priv *priv = netdev_priv(dev);
2500 struct mlx5_core_dev *mdev = priv->mdev;
2501 int err;
2502
2503 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2504 if (err)
2505 return err;
2506 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2507 return 0;
2508}
2509
2510static int mlx5e_get_vf_stats(struct net_device *dev,
2511 int vf, struct ifla_vf_stats *vf_stats)
2512{
2513 struct mlx5e_priv *priv = netdev_priv(dev);
2514 struct mlx5_core_dev *mdev = priv->mdev;
2515
2516 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2517 vf_stats);
2518}
2519
b3f63c3d
MF		 2520static void mlx5e_add_vxlan_port(struct net_device *netdev,
2521 sa_family_t sa_family, __be16 port)
2522{
2523 struct mlx5e_priv *priv = netdev_priv(netdev);
2524
2525 if (!mlx5e_vxlan_allowed(priv->mdev))
2526 return;
2527
d8cf2dda 2528 mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 1);
b3f63c3d
MF		 2529}
2530
2531static void mlx5e_del_vxlan_port(struct net_device *netdev,
2532 sa_family_t sa_family, __be16 port)
2533{
2534 struct mlx5e_priv *priv = netdev_priv(netdev);
2535
2536 if (!mlx5e_vxlan_allowed(priv->mdev))
2537 return;
2538
d8cf2dda 2539 mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 0);
b3f63c3d
MF		 2540}
2541
2542static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2543 struct sk_buff *skb,
2544 netdev_features_t features)
2545{
2546 struct udphdr *udph;
2547 u16 proto;
2548 u16 port = 0;
2549
2550 switch (vlan_get_protocol(skb)) {
2551 case htons(ETH_P_IP):
2552 proto = ip_hdr(skb)->protocol;
2553 break;
2554 case htons(ETH_P_IPV6):
2555 proto = ipv6_hdr(skb)->nexthdr;
2556 break;
2557 default:
2558 goto out;
2559 }
2560
2561 if (proto == IPPROTO_UDP) {
2562 udph = udp_hdr(skb);
2563 port = be16_to_cpu(udph->dest);
2564 }
2565
2566 /* Verify if UDP port is being offloaded by HW */
2567 if (port && mlx5e_vxlan_lookup_port(priv, port))
2568 return features;
2569
2570out:
2571 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2572 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2573}
2574
2575static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2576 struct net_device *netdev,
2577 netdev_features_t features)
2578{
2579 struct mlx5e_priv *priv = netdev_priv(netdev);
2580
2581 features = vlan_features_check(skb, features);
2582 features = vxlan_features_check(skb, features);
2583
2584 /* Validate if the tunneled packet is being offloaded by HW */
2585 if (skb->encapsulation &&
2586 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2587 return mlx5e_vxlan_features_check(priv, skb, features);
2588
2589 return features;
2590}
2591
b0eed40e 2592static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 2593 .ndo_open = mlx5e_open,
2594 .ndo_stop = mlx5e_close,
2595 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2596 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2597 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 2598 .ndo_get_stats64 = mlx5e_get_stats,
2599 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2600 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 2601 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2602 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 2603 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 2604 .ndo_change_mtu = mlx5e_change_mtu,
2605 .ndo_do_ioctl = mlx5e_ioctl,
45bf454a
MG		 2606#ifdef CONFIG_RFS_ACCEL
2607 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2608#endif
b0eed40e
SM		 2609};
2610
2611static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2612 .ndo_open = mlx5e_open,
2613 .ndo_stop = mlx5e_close,
2614 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2615 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2616 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 2617 .ndo_get_stats64 = mlx5e_get_stats,
2618 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2619 .ndo_set_mac_address = mlx5e_set_mac,
2620 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2621 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2622 .ndo_set_features = mlx5e_set_features,
2623 .ndo_change_mtu = mlx5e_change_mtu,
2624 .ndo_do_ioctl = mlx5e_ioctl,
b3f63c3d
MF		 2625 .ndo_add_vxlan_port = mlx5e_add_vxlan_port,
2626 .ndo_del_vxlan_port = mlx5e_del_vxlan_port,
2627 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 2628#ifdef CONFIG_RFS_ACCEL
2629 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2630#endif
b0eed40e
SM		 2631 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2632 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 2633 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 2634 .ndo_set_vf_trust = mlx5e_set_vf_trust,
b0eed40e
SM		 2635 .ndo_get_vf_config = mlx5e_get_vf_config,
2636 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2637 .ndo_get_vf_stats = mlx5e_get_vf_stats,
f62b8bb8
AV		 2638};
2639
2640static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2641{
2642 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2643 return -ENOTSUPP;
2644 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2645 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2646 !MLX5_CAP_ETH(mdev, csum_cap) ||
2647 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2648 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 2649 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2650 MLX5_CAP_FLOWTABLE(mdev,
2651 flow_table_properties_nic_receive.max_ft_level)
2652 < 3) {
f62b8bb8
AV		 2653 mlx5_core_warn(mdev,
2654 "Not creating net device, some required device capabilities are missing\n");
2655 return -ENOTSUPP;
2656 }
66189961
TT		 2657 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2658 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 2659 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2660 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 2661
f62b8bb8
AV		 2662 return 0;
2663}
2664
58d52291
AS		 2665u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2666{
2667 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2668
2669 return bf_buf_size -
2670 sizeof(struct mlx5e_tx_wqe) +
2671 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2672}
2673
08fb1dac
SM		 2674#ifdef CONFIG_MLX5_CORE_EN_DCB
2675static void mlx5e_ets_init(struct mlx5e_priv *priv)
2676{
2677 int i;
2678
2679 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2680 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2681 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2682 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2683 priv->params.ets.prio_tc[i] = i;
2684 }
2685
2686 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2687 priv->params.ets.prio_tc[0] = 1;
2688 priv->params.ets.prio_tc[1] = 0;
2689}
2690#endif
2691
d8c9660d
TT		 2692void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2693 u32 *indirection_rqt, int len,
85082dba
TT		 2694 int num_channels)
2695{
d8c9660d
TT		 2696 int node = mdev->priv.numa_node;
2697 int node_num_of_cores;
85082dba
TT		 2698 int i;
2699
d8c9660d
TT		 2700 if (node == -1)
2701 node = first_online_node;
2702
2703 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2704
2705 if (node_num_of_cores)
2706 num_channels = min_t(int, num_channels, node_num_of_cores);
2707
85082dba
TT		 2708 for (i = 0; i < len; i++)
2709 indirection_rqt[i] = i % num_channels;
2710}
2711
bc77b240
TT		 2712static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2713{
2714 return MLX5_CAP_GEN(mdev, striding_rq) &&
2715 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2716 MLX5_CAP_ETH(mdev, reg_umr_sq);
2717}
2718
f62b8bb8
AV		 2719static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2720 struct net_device *netdev,
936896e9 2721 int num_channels)
f62b8bb8
AV		 2722{
2723 struct mlx5e_priv *priv = netdev_priv(netdev);
2724
2725 priv->params.log_sq_size =
2726 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
bc77b240 2727 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
461017cb
TT		 2728 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2729 MLX5_WQ_TYPE_LINKED_LIST;
2730
2731 switch (priv->params.rq_wq_type) {
2732 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2733 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
d9d9f156
TT		 2734 priv->params.mpwqe_log_stride_sz =
2735 priv->params.rx_cqe_compress ?
2736 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
2737 MLX5_MPWRQ_LOG_STRIDE_SIZE;
2738 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
2739 priv->params.mpwqe_log_stride_sz;
461017cb
TT		 2740 priv->params.lro_en = true;
2741 break;
2742 default: /* MLX5_WQ_TYPE_LINKED_LIST */
2743 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2744 }
2745
d9d9f156
TT		 2746 mlx5_core_info(mdev,
2747 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
2748 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
2749 BIT(priv->params.log_rq_size),
2750 BIT(priv->params.mpwqe_log_stride_sz),
2751 priv->params.rx_cqe_compress_admin);
2752
461017cb
TT		 2753 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2754 BIT(priv->params.log_rq_size));
f62b8bb8
AV		 2755 priv->params.rx_cq_moderation_usec =
2756 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2757 priv->params.rx_cq_moderation_pkts =
2758 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2759 priv->params.tx_cq_moderation_usec =
2760 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2761 priv->params.tx_cq_moderation_pkts =
2762 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 2763 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
f62b8bb8 2764 priv->params.num_tc = 1;
2be6967c 2765 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 2766
57afead5
AS		 2767 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2768 sizeof(priv->params.toeplitz_hash_key));
2769
d8c9660d 2770 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
85082dba 2771 MLX5E_INDIR_RQT_SIZE, num_channels);
2d75b2bc 2772
f62b8bb8
AV		 2773 priv->params.lro_wqe_sz =
2774 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2775
2776 priv->mdev = mdev;
2777 priv->netdev = netdev;
936896e9 2778 priv->params.num_channels = num_channels;
f62b8bb8 2779
08fb1dac
SM		 2780#ifdef CONFIG_MLX5_CORE_EN_DCB
2781 mlx5e_ets_init(priv);
2782#endif
f62b8bb8 2783
f62b8bb8
AV		 2784 mutex_init(&priv->state_lock);
2785
2786 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2787 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2788 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2789}
2790
2791static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2792{
2793 struct mlx5e_priv *priv = netdev_priv(netdev);
2794
e1d7d349 2795 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 2796 if (is_zero_ether_addr(netdev->dev_addr) &&
2797 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2798 eth_hw_addr_random(netdev);
2799 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2800 }
f62b8bb8
AV		 2801}
2802
2803static void mlx5e_build_netdev(struct net_device *netdev)
2804{
2805 struct mlx5e_priv *priv = netdev_priv(netdev);
2806 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 2807 bool fcs_supported;
2808 bool fcs_enabled;
f62b8bb8
AV		 2809
2810 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2811
08fb1dac 2812 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 2813 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac
SM		 2814#ifdef CONFIG_MLX5_CORE_EN_DCB
2815 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2816#endif
2817 } else {
b0eed40e 2818 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 2819 }
66e49ded 2820
f62b8bb8
AV		 2821 netdev->watchdog_timeo = 15 * HZ;
2822
2823 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2824
12be4b21 2825 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 2826 netdev->vlan_features |= NETIF_F_IP_CSUM;
2827 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2828 netdev->vlan_features |= NETIF_F_GRO;
2829 netdev->vlan_features |= NETIF_F_TSO;
2830 netdev->vlan_features |= NETIF_F_TSO6;
2831 netdev->vlan_features |= NETIF_F_RXCSUM;
2832 netdev->vlan_features |= NETIF_F_RXHASH;
2833
2834 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2835 netdev->vlan_features |= NETIF_F_LRO;
2836
2837 netdev->hw_features = netdev->vlan_features;
e4cf27bd 2838 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 2839 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2840 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2841
b3f63c3d 2842 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 2843 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
2844 NETIF_F_GSO_UDP_TUNNEL_CSUM |
2845 NETIF_F_GSO_PARTIAL;
b3f63c3d 2846 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 2847 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 2848 netdev->hw_enc_features |= NETIF_F_TSO;
2849 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 2850 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 2851 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
2852 NETIF_F_GSO_PARTIAL;
2853 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 2854 }
2855
94cb1ebb
EBE		 2856 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
2857
2858 if (fcs_supported)
2859 netdev->hw_features |= NETIF_F_RXALL;
2860
f62b8bb8
AV		 2861 netdev->features = netdev->hw_features;
2862 if (!priv->params.lro_en)
2863 netdev->features &= ~NETIF_F_LRO;
2864
94cb1ebb
EBE		 2865 if (fcs_enabled)
2866 netdev->features &= ~NETIF_F_RXALL;
2867
e8f887ac
AV		 2868#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2869 if (FT_CAP(flow_modify_en) &&
2870 FT_CAP(modify_root) &&
2871 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 2872 FT_CAP(flow_table_modify)) {
2873 netdev->hw_features |= NETIF_F_HW_TC;
2874#ifdef CONFIG_RFS_ACCEL
2875 netdev->hw_features |= NETIF_F_NTUPLE;
2876#endif
2877 }
e8f887ac 2878
f62b8bb8
AV		 2879 netdev->features |= NETIF_F_HIGHDMA;
2880
2881 netdev->priv_flags |= IFF_UNICAST_FLT;
2882
2883 mlx5e_set_netdev_dev_addr(netdev);
2884}
2885
2886static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
a606b0f6 2887 struct mlx5_core_mkey *mkey)
f62b8bb8
AV		 2888{
2889 struct mlx5_core_dev *mdev = priv->mdev;
2890 struct mlx5_create_mkey_mbox_in *in;
2891 int err;
2892
2893 in = mlx5_vzalloc(sizeof(*in));
2894 if (!in)
2895 return -ENOMEM;
2896
2897 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2898 MLX5_PERM_LOCAL_READ |
2899 MLX5_ACCESS_MODE_PA;
2900 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2901 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2902
a606b0f6 2903 err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
f62b8bb8
AV		 2904 NULL);
2905
2906 kvfree(in);
2907
2908 return err;
2909}
2910
593cf338
RS		 2911static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2912{
2913 struct mlx5_core_dev *mdev = priv->mdev;
2914 int err;
2915
2916 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2917 if (err) {
2918 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2919 priv->q_counter = 0;
2920 }
2921}
2922
2923static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2924{
2925 if (!priv->q_counter)
2926 return;
2927
2928 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2929}
2930
bc77b240
TT		 2931static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
2932{
2933 struct mlx5_core_dev *mdev = priv->mdev;
2934 struct mlx5_create_mkey_mbox_in *in;
2935 struct mlx5_mkey_seg *mkc;
2936 int inlen = sizeof(*in);
2937 u64 npages =
2938 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
2939 int err;
2940
2941 in = mlx5_vzalloc(inlen);
2942 if (!in)
2943 return -ENOMEM;
2944
2945 mkc = &in->seg;
2946 mkc->status = MLX5_MKEY_STATUS_FREE;
2947 mkc->flags = MLX5_PERM_UMR_EN |
2948 MLX5_PERM_LOCAL_READ |
2949 MLX5_PERM_LOCAL_WRITE |
2950 MLX5_ACCESS_MODE_MTT;
2951
2952 mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2953 mkc->flags_pd = cpu_to_be32(priv->pdn);
2954 mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
2955 mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
2956 mkc->log2_page_size = PAGE_SHIFT;
2957
2958 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
2959 NULL, NULL);
2960
2961 kvfree(in);
2962
2963 return err;
2964}
2965
f62b8bb8
AV		 2966static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2967{
2968 struct net_device *netdev;
2969 struct mlx5e_priv *priv;
3435ab59 2970 int nch = mlx5e_get_max_num_channels(mdev);
f62b8bb8
AV		 2971 int err;
2972
2973 if (mlx5e_check_required_hca_cap(mdev))
2974 return NULL;
2975
08fb1dac
SM		 2976 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2977 nch * MLX5E_MAX_NUM_TC,
2978 nch);
f62b8bb8
AV		 2979 if (!netdev) {
2980 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2981 return NULL;
2982 }
2983
936896e9 2984 mlx5e_build_netdev_priv(mdev, netdev, nch);
f62b8bb8
AV		 2985 mlx5e_build_netdev(netdev);
2986
2987 netif_carrier_off(netdev);
2988
2989 priv = netdev_priv(netdev);
2990
7bb29755
MF		 2991 priv->wq = create_singlethread_workqueue("mlx5e");
2992 if (!priv->wq)
2993 goto err_free_netdev;
2994
0ba42241 2995 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
f62b8bb8 2996 if (err) {
1f2a3003 2997 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
7bb29755 2998 goto err_destroy_wq;
f62b8bb8
AV		 2999 }
3000
3001 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3002 if (err) {
1f2a3003 3003 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
f62b8bb8
AV		 3004 goto err_unmap_free_uar;
3005 }
3006
8d7f9ecb 3007 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3191e05f 3008 if (err) {
1f2a3003 3009 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3191e05f
AS		 3010 goto err_dealloc_pd;
3011 }
3012
a606b0f6 3013 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
f62b8bb8 3014 if (err) {
1f2a3003 3015 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3191e05f 3016 goto err_dealloc_transport_domain;
f62b8bb8
AV		 3017 }
3018
bc77b240
TT		 3019 err = mlx5e_create_umr_mkey(priv);
3020 if (err) {
3021 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3022 goto err_destroy_mkey;
3023 }
3024
40ab6a6e 3025 err = mlx5e_create_tises(priv);
5c50368f 3026 if (err) {
40ab6a6e 3027 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
bc77b240 3028 goto err_destroy_umr_mkey;
5c50368f
AS		 3029 }
3030
3031 err = mlx5e_open_drop_rq(priv);
3032 if (err) {
3033 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
40ab6a6e 3034 goto err_destroy_tises;
5c50368f
AS		 3035 }
3036
1da36696 3037 err = mlx5e_create_rqts(priv);
5c50368f 3038 if (err) {
1da36696 3039 mlx5_core_warn(mdev, "create rqts failed, %d\n", err);
5c50368f
AS		 3040 goto err_close_drop_rq;
3041 }
3042
40ab6a6e 3043 err = mlx5e_create_tirs(priv);
5c50368f 3044 if (err) {
40ab6a6e 3045 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
1da36696 3046 goto err_destroy_rqts;
5c50368f
AS		 3047 }
3048
acff797c 3049 err = mlx5e_create_flow_steering(priv);
5c50368f 3050 if (err) {
acff797c 3051 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
40ab6a6e 3052 goto err_destroy_tirs;
5c50368f
AS		 3053 }
3054
593cf338
RS		 3055 mlx5e_create_q_counter(priv);
3056
33cfaaa8 3057 mlx5e_init_l2_addr(priv);
5c50368f 3058
b3f63c3d
MF		 3059 mlx5e_vxlan_init(priv);
3060
e8f887ac
AV		 3061 err = mlx5e_tc_init(priv);
3062 if (err)
593cf338 3063 goto err_dealloc_q_counters;
e8f887ac 3064
08fb1dac
SM		 3065#ifdef CONFIG_MLX5_CORE_EN_DCB
3066 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3067#endif
3068
f62b8bb8
AV		 3069 err = register_netdev(netdev);
3070 if (err) {
1f2a3003 3071 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
e8f887ac 3072 goto err_tc_cleanup;
f62b8bb8
AV		 3073 }
3074
01a14098
MF		 3075 if (mlx5e_vxlan_allowed(mdev)) {
3076 rtnl_lock();
b3f63c3d 3077 vxlan_get_rx_port(netdev);
01a14098
MF		 3078 rtnl_unlock();
3079 }
b3f63c3d 3080
f62b8bb8 3081 mlx5e_enable_async_events(priv);
7bb29755 3082 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3083
3084 return priv;
3085
e8f887ac
AV		 3086err_tc_cleanup:
3087 mlx5e_tc_cleanup(priv);
3088
593cf338
RS		 3089err_dealloc_q_counters:
3090 mlx5e_destroy_q_counter(priv);
acff797c 3091 mlx5e_destroy_flow_steering(priv);
5c50368f 3092
40ab6a6e
AS		 3093err_destroy_tirs:
3094 mlx5e_destroy_tirs(priv);
5c50368f 3095
1da36696
TT		 3096err_destroy_rqts:
3097 mlx5e_destroy_rqts(priv);
5c50368f
AS		 3098
3099err_close_drop_rq:
3100 mlx5e_close_drop_rq(priv);
3101
40ab6a6e
AS		 3102err_destroy_tises:
3103 mlx5e_destroy_tises(priv);
5c50368f 3104
bc77b240
TT		 3105err_destroy_umr_mkey:
3106 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3107
f62b8bb8 3108err_destroy_mkey:
a606b0f6 3109 mlx5_core_destroy_mkey(mdev, &priv->mkey);
f62b8bb8 3110
3191e05f 3111err_dealloc_transport_domain:
8d7f9ecb 3112 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3191e05f 3113
f62b8bb8
AV		 3114err_dealloc_pd:
3115 mlx5_core_dealloc_pd(mdev, priv->pdn);
3116
3117err_unmap_free_uar:
3118 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3119
7bb29755
MF		 3120err_destroy_wq:
3121 destroy_workqueue(priv->wq);
3122
f62b8bb8
AV		 3123err_free_netdev:
3124 free_netdev(netdev);
3125
3126 return NULL;
3127}
3128
3129static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
3130{
3131 struct mlx5e_priv *priv = vpriv;
3132 struct net_device *netdev = priv->netdev;
3133
9b37b07f
AS		 3134 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3135
7bb29755 3136 queue_work(priv->wq, &priv->set_rx_mode_work);
1cefa326 3137 mlx5e_disable_async_events(priv);
7bb29755 3138 flush_workqueue(priv->wq);
5fc7197d
MD		 3139 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3140 netif_device_detach(netdev);
3141 mutex_lock(&priv->state_lock);
3142 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
3143 mlx5e_close_locked(netdev);
3144 mutex_unlock(&priv->state_lock);
3145 } else {
3146 unregister_netdev(netdev);
3147 }
3148
e8f887ac 3149 mlx5e_tc_cleanup(priv);
b3f63c3d 3150 mlx5e_vxlan_cleanup(priv);
593cf338 3151 mlx5e_destroy_q_counter(priv);
acff797c 3152 mlx5e_destroy_flow_steering(priv);
40ab6a6e 3153 mlx5e_destroy_tirs(priv);
1da36696 3154 mlx5e_destroy_rqts(priv);
5c50368f 3155 mlx5e_close_drop_rq(priv);
40ab6a6e 3156 mlx5e_destroy_tises(priv);
bc77b240 3157 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
a606b0f6 3158 mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
8d7f9ecb 3159 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
f62b8bb8
AV		 3160 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3161 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
7bb29755
MF		 3162 cancel_delayed_work_sync(&priv->update_stats_work);
3163 destroy_workqueue(priv->wq);
5fc7197d
MD		 3164
3165 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3166 free_netdev(netdev);
f62b8bb8
AV		 3167}
3168
3169static void *mlx5e_get_netdev(void *vpriv)
3170{
3171 struct mlx5e_priv *priv = vpriv;
3172
3173 return priv->netdev;
3174}
3175
3176static struct mlx5_interface mlx5e_interface = {
3177 .add = mlx5e_create_netdev,
3178 .remove = mlx5e_destroy_netdev,
3179 .event = mlx5e_async_event,
3180 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3181 .get_dev = mlx5e_get_netdev,
3182};
3183
3184void mlx5e_init(void)
3185{
3186 mlx5_register_interface(&mlx5e_interface);
3187}
3188
3189void mlx5e_cleanup(void)
3190{
3191 mlx5_unregister_interface(&mlx5e_interface);
3192}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git