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cxgb4vf: Fix SGE FL buffer initialization logic for 64K pages
[thirdparty/kernel/stable.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
1d447a39 38#include "eswitch.h"
f62b8bb8 39#include "en.h"
e8f887ac 40#include "en_tc.h"
1d447a39 41#include "en_rep.h"
547eede0 42#include "en_accel/ipsec.h"
899a59d3
IT		 43#include "en_accel/ipsec_rxtx.h"
44#include "accel/ipsec.h"
b3f63c3d 45#include "vxlan.h"
f62b8bb8
AV		 46
47struct mlx5e_rq_param {
cb3c7fd4
GR		 48 u32 rqc[MLX5_ST_SZ_DW(rqc)];
49 struct mlx5_wq_param wq;
f62b8bb8
AV		 50};
51
52struct mlx5e_sq_param {
53 u32 sqc[MLX5_ST_SZ_DW(sqc)];
54 struct mlx5_wq_param wq;
55};
56
57struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
9908aa29 61 u8 cq_period_mode;
f62b8bb8
AV		 62};
63
64struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
b5503b99 67 struct mlx5e_sq_param xdp_sq;
d3c9bc27 68 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
d3c9bc27 71 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 72};
73
2fc4bfb7
SM		 74static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75{
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
79}
80
696a97cf
EE		 81void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
82 struct mlx5e_params *params, u8 rq_type)
2fc4bfb7 83{
6a9764ef
SM		 84 params->rq_wq_type = rq_type;
85 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
86 switch (params->rq_wq_type) {
2fc4bfb7 87 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 88 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 89 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
90 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
696a97cf
EE		 91 params->mpwqe_log_stride_sz = MLX5E_MPWQE_STRIDE_SZ(mdev,
92 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
6a9764ef
SM		 93 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
94 params->mpwqe_log_stride_sz;
2fc4bfb7
SM		 95 break;
96 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 97 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 98 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
99 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
bce2b2bf
TT		 100 params->rq_headroom = params->xdp_prog ?
101 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
102 params->rq_headroom += NET_IP_ALIGN;
4078e637
TT		 103
104 /* Extra room needed for build_skb */
bce2b2bf 105 params->lro_wqe_sz -= params->rq_headroom +
4078e637 106 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2fc4bfb7 107 }
2fc4bfb7 108
6a9764ef
SM		 109 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
110 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
111 BIT(params->log_rq_size),
112 BIT(params->mpwqe_log_stride_sz),
113 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 114}
115
696a97cf
EE		 116static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev,
117 struct mlx5e_params *params)
2fc4bfb7 118{
6a9764ef 119 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
899a59d3 120 !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
2fc4bfb7
SM		 121 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
122 MLX5_WQ_TYPE_LINKED_LIST;
696a97cf 123 mlx5e_init_rq_type_params(mdev, params, rq_type);
2fc4bfb7
SM		 124}
125
f62b8bb8
AV		 126static void mlx5e_update_carrier(struct mlx5e_priv *priv)
127{
128 struct mlx5_core_dev *mdev = priv->mdev;
129 u8 port_state;
130
131 port_state = mlx5_query_vport_state(mdev,
e53eef63
OG		 132 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
133 0);
f62b8bb8 134
87424ad5
SD		 135 if (port_state == VPORT_STATE_UP) {
136 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 137 netif_carrier_on(priv->netdev);
87424ad5
SD		 138 } else {
139 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 140 netif_carrier_off(priv->netdev);
87424ad5 141 }
f62b8bb8
AV		 142}
143
144static void mlx5e_update_carrier_work(struct work_struct *work)
145{
146 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
147 update_carrier_work);
148
149 mutex_lock(&priv->state_lock);
150 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
7ca42c80
ES		 151 if (priv->profile->update_carrier)
152 priv->profile->update_carrier(priv);
f62b8bb8
AV		 153 mutex_unlock(&priv->state_lock);
154}
155
3947ca18
DJ		 156static void mlx5e_tx_timeout_work(struct work_struct *work)
157{
158 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
159 tx_timeout_work);
160 int err;
161
162 rtnl_lock();
163 mutex_lock(&priv->state_lock);
164 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
165 goto unlock;
166 mlx5e_close_locked(priv->netdev);
167 err = mlx5e_open_locked(priv->netdev);
168 if (err)
169 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
170 err);
171unlock:
172 mutex_unlock(&priv->state_lock);
173 rtnl_unlock();
174}
175
9218b44d 176static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 177{
1510d728 178 struct mlx5e_sw_stats temp, *s = &temp;
f62b8bb8
AV		 179 struct mlx5e_rq_stats *rq_stats;
180 struct mlx5e_sq_stats *sq_stats;
f62b8bb8
AV		 181 int i, j;
182
9218b44d 183 memset(s, 0, sizeof(*s));
ff9c852f
SM		 184 for (i = 0; i < priv->channels.num; i++) {
185 struct mlx5e_channel *c = priv->channels.c[i];
186
187 rq_stats = &c->rq.stats;
f62b8bb8 188
faf4478b
GP		 189 s->rx_packets += rq_stats->packets;
190 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 191 s->rx_lro_packets += rq_stats->lro_packets;
192 s->rx_lro_bytes += rq_stats->lro_bytes;
f24686e8 193 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
f62b8bb8 194 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1 195 s->rx_csum_complete += rq_stats->csum_complete;
603e1f5b 196 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
bfe6d8d1 197 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 198 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 199 s->rx_xdp_tx += rq_stats->xdp_tx;
200 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 201 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 202 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 203 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 204 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
205 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
accd5883 206 s->rx_page_reuse += rq_stats->page_reuse;
4415a031
TT		 207 s->rx_cache_reuse += rq_stats->cache_reuse;
208 s->rx_cache_full += rq_stats->cache_full;
209 s->rx_cache_empty += rq_stats->cache_empty;
210 s->rx_cache_busy += rq_stats->cache_busy;
70871f1e 211 s->rx_cache_waive += rq_stats->cache_waive;
f62b8bb8 212
6a9764ef 213 for (j = 0; j < priv->channels.params.num_tc; j++) {
ff9c852f 214 sq_stats = &c->sq[j].stats;
f62b8bb8 215
faf4478b
GP		 216 s->tx_packets += sq_stats->packets;
217 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 218 s->tx_tso_packets += sq_stats->tso_packets;
219 s->tx_tso_bytes += sq_stats->tso_bytes;
220 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
221 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f24686e8 222 s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
f62b8bb8
AV		 223 s->tx_queue_stopped += sq_stats->stopped;
224 s->tx_queue_wake += sq_stats->wake;
225 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 226 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1 227 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
603e1f5b
GP		 228 s->tx_csum_none += sq_stats->csum_none;
229 s->tx_csum_partial += sq_stats->csum_partial;
f62b8bb8
AV		 230 }
231 }
232
bfe6d8d1 233 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 234 priv->stats.pport.phy_counters,
235 counter_set.phys_layer_cntrs.link_down_events);
1510d728 236 memcpy(&priv->stats.sw, s, sizeof(*s));
9218b44d
GP		 237}
238
239static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
240{
241 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
242 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 243 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 244 struct mlx5_core_dev *mdev = priv->mdev;
245
f62b8bb8
AV		 246 MLX5_SET(query_vport_counter_in, in, opcode,
247 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
248 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
249 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
250
9218b44d
GP		 251 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
252}
253
3834a5e6 254static void mlx5e_update_pport_counters(struct mlx5e_priv *priv, bool full)
9218b44d
GP		 255{
256 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
257 struct mlx5_core_dev *mdev = priv->mdev;
0883b4f4 258 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
9218b44d 259 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 260 int prio;
9218b44d 261 void *out;
f62b8bb8 262
9218b44d 263 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 264
9218b44d
GP		 265 out = pstats->IEEE_802_3_counters;
266 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
267 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 268
3834a5e6
GP		 269 if (!full)
270 return;
271
9218b44d
GP		 272 out = pstats->RFC_2863_counters;
273 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
274 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
275
276 out = pstats->RFC_2819_counters;
277 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
278 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 279
121fcdc8
GP		 280 out = pstats->phy_counters;
281 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
282 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
283
5db0a4f6
GP		 284 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
285 out = pstats->phy_statistical_counters;
286 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
287 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
288 }
289
068aef33
GP		 290 if (MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters)) {
291 out = pstats->eth_ext_counters;
292 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
5db0a4f6
GP		 293 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
294 }
295
cf678570
GP		 296 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
297 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
298 out = pstats->per_prio_counters[prio];
299 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
300 mlx5_core_access_reg(mdev, in, sz, out, sz,
301 MLX5_REG_PPCNT, 0, 0);
302 }
9218b44d
GP		 303}
304
305static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
306{
307 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
432609a4
GP		 308 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
309 int err;
9218b44d
GP		 310
311 if (!priv->q_counter)
312 return;
313
432609a4
GP		 314 err = mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, sizeof(out));
315 if (err)
316 return;
317
318 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer);
9218b44d
GP		 319}
320
0f7f3481
GP		 321static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
322{
323 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
324 struct mlx5_core_dev *mdev = priv->mdev;
0883b4f4 325 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
0f7f3481
GP		 326 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
327 void *out;
0f7f3481
GP		 328
329 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
330 return;
331
0f7f3481
GP		 332 out = pcie_stats->pcie_perf_counters;
333 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
334 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
0f7f3481
GP		 335}
336
3834a5e6 337void mlx5e_update_stats(struct mlx5e_priv *priv, bool full)
9218b44d 338{
164f16f7 339 if (full) {
3834a5e6 340 mlx5e_update_pcie_counters(priv);
164f16f7
IT		 341 mlx5e_ipsec_update_stats(priv);
342 }
3834a5e6 343 mlx5e_update_pport_counters(priv, full);
3dd69e3d
SM		 344 mlx5e_update_vport_counters(priv);
345 mlx5e_update_q_counter(priv);
121fcdc8 346 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 347}
348
3834a5e6
GP		 349static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
350{
351 mlx5e_update_stats(priv, false);
352}
353
cb67b832 354void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 355{
356 struct delayed_work *dwork = to_delayed_work(work);
357 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
358 update_stats_work);
359 mutex_lock(&priv->state_lock);
360 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 361 priv->profile->update_stats(priv);
7bb29755
MF		 362 queue_delayed_work(priv->wq, dwork,
363 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 364 }
365 mutex_unlock(&priv->state_lock);
366}
367
daa21560
TT		 368static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
369 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 370{
daa21560
TT		 371 struct mlx5e_priv *priv = vpriv;
372
e0f46eb9 373 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 374 return;
375
f62b8bb8
AV		 376 switch (event) {
377 case MLX5_DEV_EVENT_PORT_UP:
378 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 379 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 380 break;
f62b8bb8
AV		 381 default:
382 break;
383 }
384}
385
f62b8bb8
AV		 386static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
387{
e0f46eb9 388 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 389}
390
391static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
392{
e0f46eb9 393 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
78249c42 394 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 395}
396
7e426671
TT		 397static inline int mlx5e_get_wqe_mtt_sz(void)
398{
399 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
400 * To avoid copying garbage after the mtt array, we allocate
401 * a little more.
402 */
403 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
404 MLX5_UMR_MTT_ALIGNMENT);
405}
406
31391048
SM		 407static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
408 struct mlx5e_icosq *sq,
409 struct mlx5e_umr_wqe *wqe,
410 u16 ix)
7e426671
TT		 411{
412 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
413 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
414 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 415 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 416 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
417 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
418
419 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
420 ds_cnt);
421 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
422 cseg->imm = rq->mkey_be;
423
424 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
31616255 425 ucseg->xlt_octowords =
7e426671
TT		 426 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
427 ucseg->bsf_octowords =
428 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
429 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
430
431 dseg->lkey = sq->mkey_be;
432 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
433}
434
435static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
436 struct mlx5e_channel *c)
437{
438 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
439 int mtt_sz = mlx5e_get_wqe_mtt_sz();
440 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
441 int i;
442
21c59685 443 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
231243c8 444 GFP_KERNEL, cpu_to_node(c->cpu));
21c59685 445 if (!rq->mpwqe.info)
7e426671
TT		 446 goto err_out;
447
448 /* We allocate more than mtt_sz as we will align the pointer */
231243c8
SM		 449 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
450 cpu_to_node(c->cpu));
21c59685 451 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 452 goto err_free_wqe_info;
453
454 for (i = 0; i < wq_sz; i++) {
21c59685 455 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 456
21c59685 457 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 458 MLX5_UMR_ALIGN);
459 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
460 PCI_DMA_TODEVICE);
461 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
462 goto err_unmap_mtts;
463
464 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
465 }
466
467 return 0;
468
469err_unmap_mtts:
470 while (--i >= 0) {
21c59685 471 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 472
473 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
474 PCI_DMA_TODEVICE);
475 }
21c59685 476 kfree(rq->mpwqe.mtt_no_align);
7e426671 477err_free_wqe_info:
21c59685 478 kfree(rq->mpwqe.info);
7e426671
TT		 479
480err_out:
481 return -ENOMEM;
482}
483
484static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
485{
486 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
487 int mtt_sz = mlx5e_get_wqe_mtt_sz();
488 int i;
489
490 for (i = 0; i < wq_sz; i++) {
21c59685 491 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 492
493 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
494 PCI_DMA_TODEVICE);
495 }
21c59685
SM		 496 kfree(rq->mpwqe.mtt_no_align);
497 kfree(rq->mpwqe.info);
7e426671
TT		 498}
499
a43b25da 500static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
ec8b9981
TT		 501 u64 npages, u8 page_shift,
502 struct mlx5_core_mkey *umr_mkey)
3608ae77 503{
3608ae77
TT		 504 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
505 void *mkc;
506 u32 *in;
507 int err;
508
ec8b9981
TT		 509 if (!MLX5E_VALID_NUM_MTTS(npages))
510 return -EINVAL;
511
1b9a07ee 512 in = kvzalloc(inlen, GFP_KERNEL);
3608ae77
TT		 513 if (!in)
514 return -ENOMEM;
515
516 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
517
3608ae77
TT		 518 MLX5_SET(mkc, mkc, free, 1);
519 MLX5_SET(mkc, mkc, umr_en, 1);
520 MLX5_SET(mkc, mkc, lw, 1);
521 MLX5_SET(mkc, mkc, lr, 1);
522 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
523
524 MLX5_SET(mkc, mkc, qpn, 0xffffff);
525 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 526 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 527 MLX5_SET(mkc, mkc, translations_octword_size,
528 MLX5_MTT_OCTW(npages));
ec8b9981 529 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 530
ec8b9981 531 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 532
533 kvfree(in);
534 return err;
535}
536
a43b25da 537static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
ec8b9981 538{
6a9764ef 539 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
ec8b9981 540
a43b25da 541 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
ec8b9981
TT		 542}
543
3b77235b 544static int mlx5e_alloc_rq(struct mlx5e_channel *c,
6a9764ef
SM		 545 struct mlx5e_params *params,
546 struct mlx5e_rq_param *rqp,
3b77235b 547 struct mlx5e_rq *rq)
f62b8bb8 548{
a43b25da 549 struct mlx5_core_dev *mdev = c->mdev;
6a9764ef 550 void *rqc = rqp->rqc;
f62b8bb8 551 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 552 u32 byte_count;
1bfecfca 553 int npages;
f62b8bb8
AV		 554 int wq_sz;
555 int err;
556 int i;
557
231243c8 558 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
311c7c71 559
6a9764ef 560 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
f62b8bb8
AV		 561 &rq->wq_ctrl);
562 if (err)
563 return err;
564
565 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
566
567 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 568
6a9764ef 569 rq->wq_type = params->rq_wq_type;
7e426671
TT		 570 rq->pdev = c->pdev;
571 rq->netdev = c->netdev;
a43b25da 572 rq->tstamp = c->tstamp;
7c39afb3 573 rq->clock = &mdev->clock;
7e426671
TT		 574 rq->channel = c;
575 rq->ix = c->ix;
a43b25da 576 rq->mdev = mdev;
97bc402d 577
6a9764ef 578 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
97bc402d
DB		 579 if (IS_ERR(rq->xdp_prog)) {
580 err = PTR_ERR(rq->xdp_prog);
581 rq->xdp_prog = NULL;
582 goto err_rq_wq_destroy;
583 }
7e426671 584
0ddf5432
JDB		 585 if (xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix) < 0)
586 goto err_rq_wq_destroy;
587
bce2b2bf 588 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
b45d8b50 589 rq->buff.headroom = params->rq_headroom;
b5503b99 590
6a9764ef 591 switch (rq->wq_type) {
461017cb 592 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476 593
7cc6d77b 594 rq->post_wqes = mlx5e_post_rx_mpwqes;
6cd392a0 595 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 596
20fd0c19 597 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
899a59d3
IT		 598#ifdef CONFIG_MLX5_EN_IPSEC
599 if (MLX5_IPSEC_DEV(mdev)) {
600 err = -EINVAL;
601 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
602 goto err_rq_wq_destroy;
603 }
604#endif
20fd0c19
SM		 605 if (!rq->handle_rx_cqe) {
606 err = -EINVAL;
607 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
608 goto err_rq_wq_destroy;
609 }
610
89e89f7a 611 rq->mpwqe.log_stride_sz = params->mpwqe_log_stride_sz;
b45d8b50 612 rq->mpwqe.num_strides = BIT(params->mpwqe_log_num_strides);
1bfecfca 613
b681c481 614 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
ec8b9981 615
a43b25da 616 err = mlx5e_create_rq_umr_mkey(mdev, rq);
7e426671
TT		 617 if (err)
618 goto err_rq_wq_destroy;
ec8b9981
TT		 619 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
620
621 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
622 if (err)
623 goto err_destroy_umr_mkey;
461017cb
TT		 624 break;
625 default: /* MLX5_WQ_TYPE_LINKED_LIST */
accd5883
TT		 626 rq->wqe.frag_info =
627 kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
231243c8 628 GFP_KERNEL, cpu_to_node(c->cpu));
accd5883 629 if (!rq->wqe.frag_info) {
461017cb
TT		 630 err = -ENOMEM;
631 goto err_rq_wq_destroy;
632 }
7cc6d77b 633 rq->post_wqes = mlx5e_post_rx_wqes;
6cd392a0 634 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 635
899a59d3
IT		 636#ifdef CONFIG_MLX5_EN_IPSEC
637 if (c->priv->ipsec)
638 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
639 else
640#endif
641 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
20fd0c19 642 if (!rq->handle_rx_cqe) {
accd5883 643 kfree(rq->wqe.frag_info);
20fd0c19
SM		 644 err = -EINVAL;
645 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
646 goto err_rq_wq_destroy;
647 }
648
b681c481 649 byte_count = params->lro_en ?
6a9764ef 650 params->lro_wqe_sz :
c139dbfd 651 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
899a59d3
IT		 652#ifdef CONFIG_MLX5_EN_IPSEC
653 if (MLX5_IPSEC_DEV(mdev))
b681c481 654 byte_count += MLX5E_METADATA_ETHER_LEN;
899a59d3 655#endif
accd5883 656 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
1bfecfca
SM		 657
658 /* calc the required page order */
b45d8b50 659 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
accd5883 660 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
1bfecfca
SM		 661 rq->buff.page_order = order_base_2(npages);
662
461017cb 663 byte_count |= MLX5_HW_START_PADDING;
7e426671 664 rq->mkey_be = c->mkey_be;
461017cb 665 }
f62b8bb8
AV		 666
667 for (i = 0; i < wq_sz; i++) {
668 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
669
4c2af5cc
TT		 670 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
671 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT;
672
673 wqe->data.addr = cpu_to_be64(dma_offset);
674 }
675
461017cb 676 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 677 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 678 }
679
9a317425
AG		 680 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
681
682 switch (params->rx_cq_moderation.cq_period_mode) {
683 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
684 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
685 break;
686 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
687 default:
688 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
689 }
690
4415a031
TT		 691 rq->page_cache.head = 0;
692 rq->page_cache.tail = 0;
693
f62b8bb8
AV		 694 return 0;
695
ec8b9981
TT		 696err_destroy_umr_mkey:
697 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
698
f62b8bb8 699err_rq_wq_destroy:
97bc402d
DB		 700 if (rq->xdp_prog)
701 bpf_prog_put(rq->xdp_prog);
0ddf5432 702 xdp_rxq_info_unreg(&rq->xdp_rxq);
f62b8bb8
AV		 703 mlx5_wq_destroy(&rq->wq_ctrl);
704
705 return err;
706}
707
3b77235b 708static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 709{
4415a031
TT		 710 int i;
711
86994156
RS		 712 if (rq->xdp_prog)
713 bpf_prog_put(rq->xdp_prog);
714
0ddf5432
JDB		 715 xdp_rxq_info_unreg(&rq->xdp_rxq);
716
461017cb
TT		 717 switch (rq->wq_type) {
718 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 719 mlx5e_rq_free_mpwqe_info(rq);
a43b25da 720 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
461017cb
TT		 721 break;
722 default: /* MLX5_WQ_TYPE_LINKED_LIST */
accd5883 723 kfree(rq->wqe.frag_info);
461017cb
TT		 724 }
725
4415a031
TT		 726 for (i = rq->page_cache.head; i != rq->page_cache.tail;
727 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
728 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
729
730 mlx5e_page_release(rq, dma_info, false);
731 }
f62b8bb8
AV		 732 mlx5_wq_destroy(&rq->wq_ctrl);
733}
734
6a9764ef
SM		 735static int mlx5e_create_rq(struct mlx5e_rq *rq,
736 struct mlx5e_rq_param *param)
f62b8bb8 737{
a43b25da 738 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 739
740 void *in;
741 void *rqc;
742 void *wq;
743 int inlen;
744 int err;
745
746 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
747 sizeof(u64) * rq->wq_ctrl.buf.npages;
1b9a07ee 748 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 749 if (!in)
750 return -ENOMEM;
751
752 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
753 wq = MLX5_ADDR_OF(rqc, rqc, wq);
754
755 memcpy(rqc, param->rqc, sizeof(param->rqc));
756
97de9f31 757 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 758 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
f62b8bb8 759 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 760 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 761 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
762
763 mlx5_fill_page_array(&rq->wq_ctrl.buf,
764 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
765
7db22ffb 766 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 767
768 kvfree(in);
769
770 return err;
771}
772
36350114
GP		 773static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
774 int next_state)
f62b8bb8
AV		 775{
776 struct mlx5e_channel *c = rq->channel;
a43b25da 777 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 778
779 void *in;
780 void *rqc;
781 int inlen;
782 int err;
783
784 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 785 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 786 if (!in)
787 return -ENOMEM;
788
789 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
790
791 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
792 MLX5_SET(rqc, rqc, state, next_state);
793
7db22ffb 794 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 795
796 kvfree(in);
797
798 return err;
799}
800
102722fc
GE		 801static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
802{
803 struct mlx5e_channel *c = rq->channel;
804 struct mlx5e_priv *priv = c->priv;
805 struct mlx5_core_dev *mdev = priv->mdev;
806
807 void *in;
808 void *rqc;
809 int inlen;
810 int err;
811
812 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 813 in = kvzalloc(inlen, GFP_KERNEL);
102722fc
GE		 814 if (!in)
815 return -ENOMEM;
816
817 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
818
819 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
820 MLX5_SET64(modify_rq_in, in, modify_bitmask,
821 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
822 MLX5_SET(rqc, rqc, scatter_fcs, enable);
823 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
824
825 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
826
827 kvfree(in);
828
829 return err;
830}
831
36350114
GP		 832static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
833{
834 struct mlx5e_channel *c = rq->channel;
a43b25da 835 struct mlx5_core_dev *mdev = c->mdev;
36350114
GP		 836 void *in;
837 void *rqc;
838 int inlen;
839 int err;
840
841 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 842 in = kvzalloc(inlen, GFP_KERNEL);
36350114
GP		 843 if (!in)
844 return -ENOMEM;
845
846 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
847
848 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 849 MLX5_SET64(modify_rq_in, in, modify_bitmask,
850 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 851 MLX5_SET(rqc, rqc, vsd, vsd);
852 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
853
854 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
855
856 kvfree(in);
857
858 return err;
859}
860
3b77235b 861static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 862{
a43b25da 863 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
f62b8bb8
AV		 864}
865
866static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
867{
01c196a2 868 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8 869 struct mlx5e_channel *c = rq->channel;
a43b25da 870
f62b8bb8 871 struct mlx5_wq_ll *wq = &rq->wq;
6a9764ef 872 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
f62b8bb8 873
01c196a2 874 while (time_before(jiffies, exp_time)) {
6a9764ef 875 if (wq->cur_sz >= min_wqes)
f62b8bb8
AV		 876 return 0;
877
878 msleep(20);
879 }
880
a43b25da 881 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
6a9764ef 882 rq->rqn, wq->cur_sz, min_wqes);
f62b8bb8
AV		 883 return -ETIMEDOUT;
884}
885
f2fde18c
SM		 886static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
887{
888 struct mlx5_wq_ll *wq = &rq->wq;
889 struct mlx5e_rx_wqe *wqe;
890 __be16 wqe_ix_be;
891 u16 wqe_ix;
892
8484f9ed 893 /* UMR WQE (if in progress) is always at wq->head */
a071cb9f
TT		 894 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
895 rq->mpwqe.umr_in_progress)
21c59685 896 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 897
f2fde18c
SM		 898 while (!mlx5_wq_ll_is_empty(wq)) {
899 wqe_ix_be = *wq->tail_next;
900 wqe_ix = be16_to_cpu(wqe_ix_be);
901 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
902 rq->dealloc_wqe(rq, wqe_ix);
903 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
904 &wqe->next.next_wqe_index);
905 }
accd5883
TT		 906
907 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
908 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
909 * but yet to be re-posted.
910 */
911 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
912
913 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
914 rq->dealloc_wqe(rq, wqe_ix);
915 }
f2fde18c
SM		 916}
917
f62b8bb8 918static int mlx5e_open_rq(struct mlx5e_channel *c,
6a9764ef 919 struct mlx5e_params *params,
f62b8bb8
AV		 920 struct mlx5e_rq_param *param,
921 struct mlx5e_rq *rq)
922{
923 int err;
924
6a9764ef 925 err = mlx5e_alloc_rq(c, params, param, rq);
f62b8bb8
AV		 926 if (err)
927 return err;
928
3b77235b 929 err = mlx5e_create_rq(rq, param);
f62b8bb8 930 if (err)
3b77235b 931 goto err_free_rq;
f62b8bb8 932
36350114 933 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 934 if (err)
3b77235b 935 goto err_destroy_rq;
f62b8bb8 936
9a317425 937 if (params->rx_dim_enabled)
a1eaba4c 938 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
cb3c7fd4 939
f62b8bb8
AV		 940 return 0;
941
f62b8bb8
AV		 942err_destroy_rq:
943 mlx5e_destroy_rq(rq);
3b77235b
SM		 944err_free_rq:
945 mlx5e_free_rq(rq);
f62b8bb8
AV		 946
947 return err;
948}
949
acc6c595
SM		 950static void mlx5e_activate_rq(struct mlx5e_rq *rq)
951{
952 struct mlx5e_icosq *sq = &rq->channel->icosq;
953 u16 pi = sq->pc & sq->wq.sz_m1;
954 struct mlx5e_tx_wqe *nopwqe;
955
956 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
957 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
acc6c595
SM		 958 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
959 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
960}
961
962static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
f62b8bb8 963{
c0f1147d 964 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 965 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
acc6c595 966}
cb3c7fd4 967
acc6c595
SM		 968static void mlx5e_close_rq(struct mlx5e_rq *rq)
969{
9a317425 970 cancel_work_sync(&rq->dim.work);
f62b8bb8 971 mlx5e_destroy_rq(rq);
3b77235b
SM		 972 mlx5e_free_rx_descs(rq);
973 mlx5e_free_rq(rq);
f62b8bb8
AV		 974}
975
31391048 976static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
b5503b99 977{
31391048 978 kfree(sq->db.di);
b5503b99
SM		 979}
980
31391048 981static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
b5503b99
SM		 982{
983 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
984
31391048 985 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
b5503b99 986 GFP_KERNEL, numa);
31391048
SM		 987 if (!sq->db.di) {
988 mlx5e_free_xdpsq_db(sq);
b5503b99
SM		 989 return -ENOMEM;
990 }
991
992 return 0;
993}
994
31391048 995static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
6a9764ef 996 struct mlx5e_params *params,
31391048
SM		 997 struct mlx5e_sq_param *param,
998 struct mlx5e_xdpsq *sq)
999{
1000 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1001 struct mlx5_core_dev *mdev = c->mdev;
31391048
SM		 1002 int err;
1003
1004 sq->pdev = c->pdev;
1005 sq->mkey_be = c->mkey_be;
1006 sq->channel = c;
1007 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 1008 sq->min_inline_mode = params->tx_min_inline_mode;
31391048 1009
231243c8 1010 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048
SM		 1011 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1012 if (err)
1013 return err;
1014 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1015
231243c8 1016 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
31391048
SM		 1017 if (err)
1018 goto err_sq_wq_destroy;
1019
1020 return 0;
1021
1022err_sq_wq_destroy:
1023 mlx5_wq_destroy(&sq->wq_ctrl);
1024
1025 return err;
1026}
1027
1028static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1029{
1030 mlx5e_free_xdpsq_db(sq);
1031 mlx5_wq_destroy(&sq->wq_ctrl);
1032}
1033
1034static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
f62b8bb8 1035{
f10b7cc7 1036 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 1037}
1038
31391048 1039static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
f10b7cc7
SM		 1040{
1041 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1042
1043 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1044 GFP_KERNEL, numa);
1045 if (!sq->db.ico_wqe)
1046 return -ENOMEM;
1047
1048 return 0;
1049}
1050
31391048 1051static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
31391048
SM		 1052 struct mlx5e_sq_param *param,
1053 struct mlx5e_icosq *sq)
f10b7cc7 1054{
31391048 1055 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1056 struct mlx5_core_dev *mdev = c->mdev;
31391048 1057 int err;
f10b7cc7 1058
31391048
SM		 1059 sq->mkey_be = c->mkey_be;
1060 sq->channel = c;
1061 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f62b8bb8 1062
231243c8 1063 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048
SM		 1064 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1065 if (err)
1066 return err;
1067 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1068
231243c8 1069 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
31391048
SM		 1070 if (err)
1071 goto err_sq_wq_destroy;
1072
1073 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
f62b8bb8
AV		 1074
1075 return 0;
31391048
SM		 1076
1077err_sq_wq_destroy:
1078 mlx5_wq_destroy(&sq->wq_ctrl);
1079
1080 return err;
f62b8bb8
AV		 1081}
1082
31391048 1083static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
f10b7cc7 1084{
31391048
SM		 1085 mlx5e_free_icosq_db(sq);
1086 mlx5_wq_destroy(&sq->wq_ctrl);
f10b7cc7
SM		 1087}
1088
31391048 1089static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
f10b7cc7 1090{
31391048
SM		 1091 kfree(sq->db.wqe_info);
1092 kfree(sq->db.dma_fifo);
f10b7cc7
SM		 1093}
1094
31391048 1095static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
b5503b99 1096{
31391048
SM		 1097 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1098 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1099
31391048
SM		 1100 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1101 GFP_KERNEL, numa);
1102 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1103 GFP_KERNEL, numa);
77bdf895 1104 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
31391048
SM		 1105 mlx5e_free_txqsq_db(sq);
1106 return -ENOMEM;
b5503b99 1107 }
31391048
SM		 1108
1109 sq->dma_fifo_mask = df_sz - 1;
1110
1111 return 0;
b5503b99
SM		 1112}
1113
31391048 1114static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
acc6c595 1115 int txq_ix,
6a9764ef 1116 struct mlx5e_params *params,
31391048
SM		 1117 struct mlx5e_sq_param *param,
1118 struct mlx5e_txqsq *sq)
f62b8bb8 1119{
31391048 1120 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1121 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 1122 int err;
1123
f10b7cc7 1124 sq->pdev = c->pdev;
a43b25da 1125 sq->tstamp = c->tstamp;
7c39afb3 1126 sq->clock = &mdev->clock;
f10b7cc7
SM		 1127 sq->mkey_be = c->mkey_be;
1128 sq->channel = c;
acc6c595 1129 sq->txq_ix = txq_ix;
aff26157 1130 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef
SM		 1131 sq->max_inline = params->tx_max_inline;
1132 sq->min_inline_mode = params->tx_min_inline_mode;
2ac9cfe7
IT		 1133 if (MLX5_IPSEC_DEV(c->priv->mdev))
1134 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
f10b7cc7 1135
231243c8 1136 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048 1137 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
f62b8bb8 1138 if (err)
aff26157 1139 return err;
31391048 1140 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1141
231243c8 1142 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
7ec0bb22 1143 if (err)
f62b8bb8
AV		 1144 goto err_sq_wq_destroy;
1145
31391048 1146 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
f62b8bb8
AV		 1147
1148 return 0;
1149
1150err_sq_wq_destroy:
1151 mlx5_wq_destroy(&sq->wq_ctrl);
1152
f62b8bb8
AV		 1153 return err;
1154}
1155
31391048 1156static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1157{
31391048 1158 mlx5e_free_txqsq_db(sq);
f62b8bb8 1159 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1160}
1161
33ad9711
SM		 1162struct mlx5e_create_sq_param {
1163 struct mlx5_wq_ctrl *wq_ctrl;
1164 u32 cqn;
1165 u32 tisn;
1166 u8 tis_lst_sz;
1167 u8 min_inline_mode;
1168};
1169
a43b25da 1170static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
33ad9711
SM		 1171 struct mlx5e_sq_param *param,
1172 struct mlx5e_create_sq_param *csp,
1173 u32 *sqn)
f62b8bb8 1174{
f62b8bb8
AV		 1175 void *in;
1176 void *sqc;
1177 void *wq;
1178 int inlen;
1179 int err;
1180
1181 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
33ad9711 1182 sizeof(u64) * csp->wq_ctrl->buf.npages;
1b9a07ee 1183 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1184 if (!in)
1185 return -ENOMEM;
1186
1187 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1188 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1189
1190 memcpy(sqc, param->sqc, sizeof(param->sqc));
33ad9711
SM		 1191 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1192 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1193 MLX5_SET(sqc, sqc, cqn, csp->cqn);
a6f402e4
SM		 1194
1195 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
33ad9711 1196 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
a6f402e4 1197
33ad9711 1198 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f62b8bb8
AV		 1199
1200 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
a43b25da 1201 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
33ad9711 1202 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
68cdf5d6 1203 MLX5_ADAPTER_PAGE_SHIFT);
33ad9711 1204 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
f62b8bb8 1205
33ad9711 1206 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 1207
33ad9711 1208 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
f62b8bb8
AV		 1209
1210 kvfree(in);
1211
1212 return err;
1213}
1214
33ad9711
SM		 1215struct mlx5e_modify_sq_param {
1216 int curr_state;
1217 int next_state;
1218 bool rl_update;
1219 int rl_index;
1220};
1221
a43b25da 1222static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
33ad9711 1223 struct mlx5e_modify_sq_param *p)
f62b8bb8 1224{
f62b8bb8
AV		 1225 void *in;
1226 void *sqc;
1227 int inlen;
1228 int err;
1229
1230 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 1231 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1232 if (!in)
1233 return -ENOMEM;
1234
1235 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1236
33ad9711
SM		 1237 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1238 MLX5_SET(sqc, sqc, state, p->next_state);
1239 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
507f0c81 1240 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
33ad9711 1241 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
507f0c81 1242 }
f62b8bb8 1243
33ad9711 1244 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
f62b8bb8
AV		 1245
1246 kvfree(in);
1247
1248 return err;
1249}
1250
a43b25da 1251static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
33ad9711 1252{
a43b25da 1253 mlx5_core_destroy_sq(mdev, sqn);
f62b8bb8
AV		 1254}
1255
a43b25da 1256static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
31391048
SM		 1257 struct mlx5e_sq_param *param,
1258 struct mlx5e_create_sq_param *csp,
1259 u32 *sqn)
f62b8bb8 1260{
33ad9711 1261 struct mlx5e_modify_sq_param msp = {0};
31391048
SM		 1262 int err;
1263
a43b25da 1264 err = mlx5e_create_sq(mdev, param, csp, sqn);
31391048
SM		 1265 if (err)
1266 return err;
1267
1268 msp.curr_state = MLX5_SQC_STATE_RST;
1269 msp.next_state = MLX5_SQC_STATE_RDY;
a43b25da 1270 err = mlx5e_modify_sq(mdev, *sqn, &msp);
31391048 1271 if (err)
a43b25da 1272 mlx5e_destroy_sq(mdev, *sqn);
31391048
SM		 1273
1274 return err;
1275}
1276
7f859ecf
SM		 1277static int mlx5e_set_sq_maxrate(struct net_device *dev,
1278 struct mlx5e_txqsq *sq, u32 rate);
1279
31391048 1280static int mlx5e_open_txqsq(struct mlx5e_channel *c,
a43b25da 1281 u32 tisn,
acc6c595 1282 int txq_ix,
6a9764ef 1283 struct mlx5e_params *params,
31391048
SM		 1284 struct mlx5e_sq_param *param,
1285 struct mlx5e_txqsq *sq)
1286{
1287 struct mlx5e_create_sq_param csp = {};
7f859ecf 1288 u32 tx_rate;
f62b8bb8
AV		 1289 int err;
1290
6a9764ef 1291 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
f62b8bb8
AV		 1292 if (err)
1293 return err;
1294
a43b25da 1295 csp.tisn = tisn;
31391048 1296 csp.tis_lst_sz = 1;
33ad9711
SM		 1297 csp.cqn = sq->cq.mcq.cqn;
1298 csp.wq_ctrl = &sq->wq_ctrl;
1299 csp.min_inline_mode = sq->min_inline_mode;
a43b25da 1300 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
f62b8bb8 1301 if (err)
31391048 1302 goto err_free_txqsq;
f62b8bb8 1303
a43b25da 1304 tx_rate = c->priv->tx_rates[sq->txq_ix];
7f859ecf 1305 if (tx_rate)
a43b25da 1306 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
7f859ecf 1307
f62b8bb8
AV		 1308 return 0;
1309
31391048 1310err_free_txqsq:
3b77235b 1311 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
31391048 1312 mlx5e_free_txqsq(sq);
f62b8bb8
AV		 1313
1314 return err;
1315}
1316
acc6c595
SM		 1317static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1318{
a43b25da 1319 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
acc6c595
SM		 1320 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1321 netdev_tx_reset_queue(sq->txq);
1322 netif_tx_start_queue(sq->txq);
1323}
1324
f62b8bb8
AV		 1325static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1326{
1327 __netif_tx_lock_bh(txq);
1328 netif_tx_stop_queue(txq);
1329 __netif_tx_unlock_bh(txq);
1330}
1331
acc6c595 1332static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1333{
33ad9711 1334 struct mlx5e_channel *c = sq->channel;
33ad9711 1335
c0f1147d 1336 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6 1337 /* prevent netif_tx_wake_queue */
33ad9711 1338 napi_synchronize(&c->napi);
29429f33 1339
31391048 1340 netif_tx_disable_queue(sq->txq);
f62b8bb8 1341
31391048
SM		 1342 /* last doorbell out, godspeed .. */
1343 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1344 struct mlx5e_tx_wqe *nop;
864b2d71 1345
77bdf895 1346 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
31391048
SM		 1347 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1348 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
29429f33 1349 }
acc6c595
SM		 1350}
1351
1352static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1353{
1354 struct mlx5e_channel *c = sq->channel;
a43b25da 1355 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1356
a43b25da 1357 mlx5e_destroy_sq(mdev, sq->sqn);
33ad9711
SM		 1358 if (sq->rate_limit)
1359 mlx5_rl_remove_rate(mdev, sq->rate_limit);
31391048
SM		 1360 mlx5e_free_txqsq_descs(sq);
1361 mlx5e_free_txqsq(sq);
1362}
1363
1364static int mlx5e_open_icosq(struct mlx5e_channel *c,
6a9764ef 1365 struct mlx5e_params *params,
31391048
SM		 1366 struct mlx5e_sq_param *param,
1367 struct mlx5e_icosq *sq)
1368{
1369 struct mlx5e_create_sq_param csp = {};
1370 int err;
1371
6a9764ef 1372 err = mlx5e_alloc_icosq(c, param, sq);
31391048
SM		 1373 if (err)
1374 return err;
1375
1376 csp.cqn = sq->cq.mcq.cqn;
1377 csp.wq_ctrl = &sq->wq_ctrl;
6a9764ef 1378 csp.min_inline_mode = params->tx_min_inline_mode;
31391048 1379 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1380 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1381 if (err)
1382 goto err_free_icosq;
1383
1384 return 0;
1385
1386err_free_icosq:
1387 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1388 mlx5e_free_icosq(sq);
1389
1390 return err;
1391}
1392
1393static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1394{
1395 struct mlx5e_channel *c = sq->channel;
1396
1397 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1398 napi_synchronize(&c->napi);
1399
a43b25da 1400 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1401 mlx5e_free_icosq(sq);
1402}
1403
1404static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
6a9764ef 1405 struct mlx5e_params *params,
31391048
SM		 1406 struct mlx5e_sq_param *param,
1407 struct mlx5e_xdpsq *sq)
1408{
1409 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1410 struct mlx5e_create_sq_param csp = {};
31391048
SM		 1411 unsigned int inline_hdr_sz = 0;
1412 int err;
1413 int i;
1414
6a9764ef 1415 err = mlx5e_alloc_xdpsq(c, params, param, sq);
31391048
SM		 1416 if (err)
1417 return err;
1418
1419 csp.tis_lst_sz = 1;
a43b25da 1420 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
31391048
SM		 1421 csp.cqn = sq->cq.mcq.cqn;
1422 csp.wq_ctrl = &sq->wq_ctrl;
1423 csp.min_inline_mode = sq->min_inline_mode;
1424 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1425 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1426 if (err)
1427 goto err_free_xdpsq;
1428
1429 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1430 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1431 ds_cnt++;
1432 }
1433
1434 /* Pre initialize fixed WQE fields */
1435 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1436 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1437 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1438 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1439 struct mlx5_wqe_data_seg *dseg;
1440
1441 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1442 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1443
1444 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1445 dseg->lkey = sq->mkey_be;
1446 }
1447
1448 return 0;
1449
1450err_free_xdpsq:
1451 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1452 mlx5e_free_xdpsq(sq);
1453
1454 return err;
1455}
1456
1457static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1458{
1459 struct mlx5e_channel *c = sq->channel;
1460
1461 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1462 napi_synchronize(&c->napi);
1463
a43b25da 1464 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1465 mlx5e_free_xdpsq_descs(sq);
1466 mlx5e_free_xdpsq(sq);
f62b8bb8
AV		 1467}
1468
95b6c6a5
EBE		 1469static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1470 struct mlx5e_cq_param *param,
1471 struct mlx5e_cq *cq)
f62b8bb8 1472{
f62b8bb8
AV		 1473 struct mlx5_core_cq *mcq = &cq->mcq;
1474 int eqn_not_used;
0b6e26ce 1475 unsigned int irqn;
f62b8bb8
AV		 1476 int err;
1477 u32 i;
1478
f62b8bb8
AV		 1479 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1480 &cq->wq_ctrl);
1481 if (err)
1482 return err;
1483
1484 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1485
f62b8bb8
AV		 1486 mcq->cqe_sz = 64;
1487 mcq->set_ci_db = cq->wq_ctrl.db.db;
1488 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1489 *mcq->set_ci_db = 0;
1490 *mcq->arm_db = 0;
1491 mcq->vector = param->eq_ix;
1492 mcq->comp = mlx5e_completion_event;
1493 mcq->event = mlx5e_cq_error_event;
1494 mcq->irqn = irqn;
f62b8bb8
AV		 1495
1496 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1497 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1498
1499 cqe->op_own = 0xf1;
1500 }
1501
a43b25da 1502 cq->mdev = mdev;
f62b8bb8
AV		 1503
1504 return 0;
1505}
1506
95b6c6a5
EBE		 1507static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1508 struct mlx5e_cq_param *param,
1509 struct mlx5e_cq *cq)
1510{
1511 struct mlx5_core_dev *mdev = c->priv->mdev;
1512 int err;
1513
231243c8
SM		 1514 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1515 param->wq.db_numa_node = cpu_to_node(c->cpu);
95b6c6a5
EBE		 1516 param->eq_ix = c->ix;
1517
1518 err = mlx5e_alloc_cq_common(mdev, param, cq);
1519
1520 cq->napi = &c->napi;
1521 cq->channel = c;
1522
1523 return err;
1524}
1525
3b77235b 1526static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1527{
1c1b5228 1528 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1529}
1530
3b77235b 1531static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1532{
a43b25da 1533 struct mlx5_core_dev *mdev = cq->mdev;
f62b8bb8
AV		 1534 struct mlx5_core_cq *mcq = &cq->mcq;
1535
1536 void *in;
1537 void *cqc;
1538 int inlen;
0b6e26ce 1539 unsigned int irqn_not_used;
f62b8bb8
AV		 1540 int eqn;
1541 int err;
1542
1543 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1544 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1b9a07ee 1545 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1546 if (!in)
1547 return -ENOMEM;
1548
1549 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1550
1551 memcpy(cqc, param->cqc, sizeof(param->cqc));
1552
1c1b5228
TT		 1553 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1554 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1555
1556 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1557
9908aa29 1558 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1559 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1560 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1c1b5228 1561 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1562 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1563 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1564
1565 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1566
1567 kvfree(in);
1568
1569 if (err)
1570 return err;
1571
1572 mlx5e_cq_arm(cq);
1573
1574 return 0;
1575}
1576
3b77235b 1577static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1578{
a43b25da 1579 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
f62b8bb8
AV		 1580}
1581
1582static int mlx5e_open_cq(struct mlx5e_channel *c,
9a317425 1583 struct net_dim_cq_moder moder,
f62b8bb8 1584 struct mlx5e_cq_param *param,
6a9764ef 1585 struct mlx5e_cq *cq)
f62b8bb8 1586{
a43b25da 1587 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1588 int err;
f62b8bb8 1589
3b77235b 1590 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1591 if (err)
1592 return err;
1593
3b77235b 1594 err = mlx5e_create_cq(cq, param);
f62b8bb8 1595 if (err)
3b77235b 1596 goto err_free_cq;
f62b8bb8 1597
7524a5d8 1598 if (MLX5_CAP_GEN(mdev, cq_moderation))
6a9764ef 1599 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
f62b8bb8
AV		 1600 return 0;
1601
3b77235b
SM		 1602err_free_cq:
1603 mlx5e_free_cq(cq);
f62b8bb8
AV		 1604
1605 return err;
1606}
1607
1608static void mlx5e_close_cq(struct mlx5e_cq *cq)
1609{
f62b8bb8 1610 mlx5e_destroy_cq(cq);
3b77235b 1611 mlx5e_free_cq(cq);
f62b8bb8
AV		 1612}
1613
231243c8
SM		 1614static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1615{
1616 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1617}
1618
f62b8bb8 1619static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
6a9764ef 1620 struct mlx5e_params *params,
f62b8bb8
AV		 1621 struct mlx5e_channel_param *cparam)
1622{
f62b8bb8
AV		 1623 int err;
1624 int tc;
1625
1626 for (tc = 0; tc < c->num_tc; tc++) {
6a9764ef
SM		 1627 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1628 &cparam->tx_cq, &c->sq[tc].cq);
f62b8bb8
AV		 1629 if (err)
1630 goto err_close_tx_cqs;
f62b8bb8
AV		 1631 }
1632
1633 return 0;
1634
1635err_close_tx_cqs:
1636 for (tc--; tc >= 0; tc--)
1637 mlx5e_close_cq(&c->sq[tc].cq);
1638
1639 return err;
1640}
1641
1642static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1643{
1644 int tc;
1645
1646 for (tc = 0; tc < c->num_tc; tc++)
1647 mlx5e_close_cq(&c->sq[tc].cq);
1648}
1649
1650static int mlx5e_open_sqs(struct mlx5e_channel *c,
6a9764ef 1651 struct mlx5e_params *params,
f62b8bb8
AV		 1652 struct mlx5e_channel_param *cparam)
1653{
1654 int err;
1655 int tc;
1656
6a9764ef
SM		 1657 for (tc = 0; tc < params->num_tc; tc++) {
1658 int txq_ix = c->ix + tc * params->num_channels;
acc6c595 1659
a43b25da
SM		 1660 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1661 params, &cparam->sq, &c->sq[tc]);
f62b8bb8
AV		 1662 if (err)
1663 goto err_close_sqs;
1664 }
1665
1666 return 0;
1667
1668err_close_sqs:
1669 for (tc--; tc >= 0; tc--)
31391048 1670 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1671
1672 return err;
1673}
1674
1675static void mlx5e_close_sqs(struct mlx5e_channel *c)
1676{
1677 int tc;
1678
1679 for (tc = 0; tc < c->num_tc; tc++)
31391048 1680 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1681}
1682
507f0c81 1683static int mlx5e_set_sq_maxrate(struct net_device *dev,
31391048 1684 struct mlx5e_txqsq *sq, u32 rate)
507f0c81
YP		 1685{
1686 struct mlx5e_priv *priv = netdev_priv(dev);
1687 struct mlx5_core_dev *mdev = priv->mdev;
33ad9711 1688 struct mlx5e_modify_sq_param msp = {0};
507f0c81
YP		 1689 u16 rl_index = 0;
1690 int err;
1691
1692 if (rate == sq->rate_limit)
1693 /* nothing to do */
1694 return 0;
1695
1696 if (sq->rate_limit)
1697 /* remove current rl index to free space to next ones */
1698 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1699
1700 sq->rate_limit = 0;
1701
1702 if (rate) {
1703 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1704 if (err) {
1705 netdev_err(dev, "Failed configuring rate %u: %d\n",
1706 rate, err);
1707 return err;
1708 }
1709 }
1710
33ad9711
SM		 1711 msp.curr_state = MLX5_SQC_STATE_RDY;
1712 msp.next_state = MLX5_SQC_STATE_RDY;
1713 msp.rl_index = rl_index;
1714 msp.rl_update = true;
a43b25da 1715 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
507f0c81
YP		 1716 if (err) {
1717 netdev_err(dev, "Failed configuring rate %u: %d\n",
1718 rate, err);
1719 /* remove the rate from the table */
1720 if (rate)
1721 mlx5_rl_remove_rate(mdev, rate);
1722 return err;
1723 }
1724
1725 sq->rate_limit = rate;
1726 return 0;
1727}
1728
1729static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1730{
1731 struct mlx5e_priv *priv = netdev_priv(dev);
1732 struct mlx5_core_dev *mdev = priv->mdev;
acc6c595 1733 struct mlx5e_txqsq *sq = priv->txq2sq[index];
507f0c81
YP		 1734 int err = 0;
1735
1736 if (!mlx5_rl_is_supported(mdev)) {
1737 netdev_err(dev, "Rate limiting is not supported on this device\n");
1738 return -EINVAL;
1739 }
1740
1741 /* rate is given in Mb/sec, HW config is in Kb/sec */
1742 rate = rate << 10;
1743
1744 /* Check whether rate in valid range, 0 is always valid */
1745 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1746 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1747 return -ERANGE;
1748 }
1749
1750 mutex_lock(&priv->state_lock);
1751 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1752 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1753 if (!err)
1754 priv->tx_rates[index] = rate;
1755 mutex_unlock(&priv->state_lock);
1756
1757 return err;
1758}
1759
f62b8bb8 1760static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
6a9764ef 1761 struct mlx5e_params *params,
f62b8bb8
AV		 1762 struct mlx5e_channel_param *cparam,
1763 struct mlx5e_channel **cp)
1764{
9a317425 1765 struct net_dim_cq_moder icocq_moder = {0, 0};
f62b8bb8 1766 struct net_device *netdev = priv->netdev;
231243c8 1767 int cpu = mlx5e_get_cpu(priv, ix);
f62b8bb8 1768 struct mlx5e_channel *c;
a8c2eb15 1769 unsigned int irq;
f62b8bb8 1770 int err;
a8c2eb15 1771 int eqn;
f62b8bb8 1772
231243c8 1773 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
f62b8bb8
AV		 1774 if (!c)
1775 return -ENOMEM;
1776
1777 c->priv = priv;
a43b25da
SM		 1778 c->mdev = priv->mdev;
1779 c->tstamp = &priv->tstamp;
f62b8bb8 1780 c->ix = ix;
231243c8 1781 c->cpu = cpu;
f62b8bb8
AV		 1782 c->pdev = &priv->mdev->pdev->dev;
1783 c->netdev = priv->netdev;
b50d292b 1784 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
6a9764ef
SM		 1785 c->num_tc = params->num_tc;
1786 c->xdp = !!params->xdp_prog;
cb3c7fd4 1787
a8c2eb15
TT		 1788 mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1789 c->irq_desc = irq_to_desc(irq);
1790
f62b8bb8
AV		 1791 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1792
6a9764ef 1793 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
f62b8bb8
AV		 1794 if (err)
1795 goto err_napi_del;
1796
6a9764ef 1797 err = mlx5e_open_tx_cqs(c, params, cparam);
d3c9bc27
TT		 1798 if (err)
1799 goto err_close_icosq_cq;
1800
6a9764ef 1801 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
f62b8bb8
AV		 1802 if (err)
1803 goto err_close_tx_cqs;
f62b8bb8 1804
d7a0ecab 1805 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
6a9764ef
SM		 1806 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1807 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
d7a0ecab
SM		 1808 if (err)
1809 goto err_close_rx_cq;
1810
f62b8bb8
AV		 1811 napi_enable(&c->napi);
1812
6a9764ef 1813 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1814 if (err)
1815 goto err_disable_napi;
1816
6a9764ef 1817 err = mlx5e_open_sqs(c, params, cparam);
d3c9bc27
TT		 1818 if (err)
1819 goto err_close_icosq;
1820
6a9764ef 1821 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
d7a0ecab
SM		 1822 if (err)
1823 goto err_close_sqs;
b5503b99 1824
6a9764ef 1825 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
f62b8bb8 1826 if (err)
b5503b99 1827 goto err_close_xdp_sq;
f62b8bb8 1828
f62b8bb8
AV		 1829 *cp = c;
1830
1831 return 0;
b5503b99 1832err_close_xdp_sq:
d7a0ecab 1833 if (c->xdp)
31391048 1834 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8
AV		 1835
1836err_close_sqs:
1837 mlx5e_close_sqs(c);
1838
d3c9bc27 1839err_close_icosq:
31391048 1840 mlx5e_close_icosq(&c->icosq);
d3c9bc27 1841
f62b8bb8
AV		 1842err_disable_napi:
1843 napi_disable(&c->napi);
d7a0ecab 1844 if (c->xdp)
31871f87 1845 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 1846
1847err_close_rx_cq:
f62b8bb8
AV		 1848 mlx5e_close_cq(&c->rq.cq);
1849
1850err_close_tx_cqs:
1851 mlx5e_close_tx_cqs(c);
1852
d3c9bc27
TT		 1853err_close_icosq_cq:
1854 mlx5e_close_cq(&c->icosq.cq);
1855
f62b8bb8
AV		 1856err_napi_del:
1857 netif_napi_del(&c->napi);
1858 kfree(c);
1859
1860 return err;
1861}
1862
acc6c595
SM		 1863static void mlx5e_activate_channel(struct mlx5e_channel *c)
1864{
1865 int tc;
1866
1867 for (tc = 0; tc < c->num_tc; tc++)
1868 mlx5e_activate_txqsq(&c->sq[tc]);
1869 mlx5e_activate_rq(&c->rq);
231243c8 1870 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
acc6c595
SM		 1871}
1872
1873static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1874{
1875 int tc;
1876
1877 mlx5e_deactivate_rq(&c->rq);
1878 for (tc = 0; tc < c->num_tc; tc++)
1879 mlx5e_deactivate_txqsq(&c->sq[tc]);
1880}
1881
f62b8bb8
AV		 1882static void mlx5e_close_channel(struct mlx5e_channel *c)
1883{
1884 mlx5e_close_rq(&c->rq);
b5503b99 1885 if (c->xdp)
31391048 1886 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8 1887 mlx5e_close_sqs(c);
31391048 1888 mlx5e_close_icosq(&c->icosq);
f62b8bb8 1889 napi_disable(&c->napi);
b5503b99 1890 if (c->xdp)
31871f87 1891 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8
AV		 1892 mlx5e_close_cq(&c->rq.cq);
1893 mlx5e_close_tx_cqs(c);
d3c9bc27 1894 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1895 netif_napi_del(&c->napi);
7ae92ae5 1896
f62b8bb8
AV		 1897 kfree(c);
1898}
1899
1900static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
6a9764ef 1901 struct mlx5e_params *params,
f62b8bb8
AV		 1902 struct mlx5e_rq_param *param)
1903{
1904 void *rqc = param->rqc;
1905 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1906
6a9764ef 1907 switch (params->rq_wq_type) {
461017cb 1908 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef
SM		 1909 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1910 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
461017cb
TT		 1911 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1912 break;
1913 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1914 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1915 }
1916
f62b8bb8
AV		 1917 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1918 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
6a9764ef 1919 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
b50d292b 1920 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1921 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
6a9764ef 1922 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
102722fc 1923 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
f62b8bb8 1924
311c7c71 1925 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1926 param->wq.linear = 1;
1927}
1928
556dd1b9
TT		 1929static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1930{
1931 void *rqc = param->rqc;
1932 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1933
1934 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1935 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1936}
1937
d3c9bc27
TT		 1938static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1939 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1940{
1941 void *sqc = param->sqc;
1942 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1943
f62b8bb8 1944 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1945 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1946
311c7c71 1947 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1948}
1949
1950static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
6a9764ef 1951 struct mlx5e_params *params,
d3c9bc27
TT		 1952 struct mlx5e_sq_param *param)
1953{
1954 void *sqc = param->sqc;
1955 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1956
1957 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1958 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2ac9cfe7 1959 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
f62b8bb8
AV		 1960}
1961
1962static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1963 struct mlx5e_cq_param *param)
1964{
1965 void *cqc = param->cqc;
1966
30aa60b3 1967 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 1968}
1969
1970static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1971 struct mlx5e_params *params,
f62b8bb8
AV		 1972 struct mlx5e_cq_param *param)
1973{
1974 void *cqc = param->cqc;
461017cb 1975 u8 log_cq_size;
f62b8bb8 1976
6a9764ef 1977 switch (params->rq_wq_type) {
461017cb 1978 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 1979 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
461017cb
TT		 1980 break;
1981 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 1982 log_cq_size = params->log_rq_size;
461017cb
TT		 1983 }
1984
1985 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
6a9764ef 1986 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1987 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1988 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1989 }
f62b8bb8
AV		 1990
1991 mlx5e_build_common_cq_param(priv, param);
0088cbbc 1992 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 1993}
1994
1995static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1996 struct mlx5e_params *params,
f62b8bb8
AV		 1997 struct mlx5e_cq_param *param)
1998{
1999 void *cqc = param->cqc;
2000
6a9764ef 2001 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
f62b8bb8
AV		 2002
2003 mlx5e_build_common_cq_param(priv, param);
0088cbbc 2004 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 2005}
2006
d3c9bc27 2007static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 2008 u8 log_wq_size,
2009 struct mlx5e_cq_param *param)
d3c9bc27
TT		 2010{
2011 void *cqc = param->cqc;
2012
2013 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2014
2015 mlx5e_build_common_cq_param(priv, param);
9908aa29 2016
9a317425 2017 param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 2018}
2019
2020static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 2021 u8 log_wq_size,
2022 struct mlx5e_sq_param *param)
d3c9bc27
TT		 2023{
2024 void *sqc = param->sqc;
2025 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2026
2027 mlx5e_build_sq_param_common(priv, param);
2028
2029 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 2030 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 2031}
2032
b5503b99 2033static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
6a9764ef 2034 struct mlx5e_params *params,
b5503b99
SM		 2035 struct mlx5e_sq_param *param)
2036{
2037 void *sqc = param->sqc;
2038 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2039
2040 mlx5e_build_sq_param_common(priv, param);
6a9764ef 2041 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
b5503b99
SM		 2042}
2043
6a9764ef
SM		 2044static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2045 struct mlx5e_params *params,
2046 struct mlx5e_channel_param *cparam)
f62b8bb8 2047{
bc77b240 2048 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 2049
6a9764ef
SM		 2050 mlx5e_build_rq_param(priv, params, &cparam->rq);
2051 mlx5e_build_sq_param(priv, params, &cparam->sq);
2052 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2053 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2054 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2055 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2056 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
f62b8bb8
AV		 2057}
2058
55c2503d
SM		 2059int mlx5e_open_channels(struct mlx5e_priv *priv,
2060 struct mlx5e_channels *chs)
f62b8bb8 2061{
6b87663f 2062 struct mlx5e_channel_param *cparam;
03289b88 2063 int err = -ENOMEM;
f62b8bb8 2064 int i;
f62b8bb8 2065
6a9764ef 2066 chs->num = chs->params.num_channels;
03289b88 2067
ff9c852f 2068 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
6b87663f 2069 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
acc6c595
SM		 2070 if (!chs->c || !cparam)
2071 goto err_free;
f62b8bb8 2072
6a9764ef 2073 mlx5e_build_channel_param(priv, &chs->params, cparam);
ff9c852f 2074 for (i = 0; i < chs->num; i++) {
6a9764ef 2075 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
f62b8bb8
AV		 2076 if (err)
2077 goto err_close_channels;
2078 }
2079
6b87663f 2080 kfree(cparam);
f62b8bb8
AV		 2081 return 0;
2082
2083err_close_channels:
2084 for (i--; i >= 0; i--)
ff9c852f 2085 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2086
acc6c595 2087err_free:
ff9c852f 2088 kfree(chs->c);
6b87663f 2089 kfree(cparam);
ff9c852f 2090 chs->num = 0;
f62b8bb8
AV		 2091 return err;
2092}
2093
acc6c595 2094static void mlx5e_activate_channels(struct mlx5e_channels *chs)
f62b8bb8
AV		 2095{
2096 int i;
2097
acc6c595
SM		 2098 for (i = 0; i < chs->num; i++)
2099 mlx5e_activate_channel(chs->c[i]);
2100}
2101
2102static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2103{
2104 int err = 0;
2105 int i;
2106
2107 for (i = 0; i < chs->num; i++) {
2108 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2109 if (err)
2110 break;
2111 }
2112
2113 return err;
2114}
2115
2116static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2117{
2118 int i;
2119
2120 for (i = 0; i < chs->num; i++)
2121 mlx5e_deactivate_channel(chs->c[i]);
2122}
2123
55c2503d 2124void mlx5e_close_channels(struct mlx5e_channels *chs)
acc6c595
SM		 2125{
2126 int i;
c3b7c5c9 2127
ff9c852f
SM		 2128 for (i = 0; i < chs->num; i++)
2129 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2130
ff9c852f
SM		 2131 kfree(chs->c);
2132 chs->num = 0;
f62b8bb8
AV		 2133}
2134
a5f97fee
SM		 2135static int
2136mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 2137{
2138 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2139 void *rqtc;
2140 int inlen;
2141 int err;
1da36696 2142 u32 *in;
a5f97fee 2143 int i;
f62b8bb8 2144
f62b8bb8 2145 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2146 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2147 if (!in)
2148 return -ENOMEM;
2149
2150 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2151
2152 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2153 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2154
a5f97fee
SM		 2155 for (i = 0; i < sz; i++)
2156 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2be6967c 2157
398f3351
HHZ		 2158 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2159 if (!err)
2160 rqt->enabled = true;
f62b8bb8
AV		 2161
2162 kvfree(in);
1da36696
TT		 2163 return err;
2164}
2165
cb67b832 2166void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2167{
398f3351
HHZ		 2168 rqt->enabled = false;
2169 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2170}
2171
8f493ffd 2172int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2173{
2174 struct mlx5e_rqt *rqt = &priv->indir_rqt;
8f493ffd 2175 int err;
6bfd390b 2176
8f493ffd
SM		 2177 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2178 if (err)
2179 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2180 return err;
6bfd390b
HHZ		 2181}
2182
cb67b832 2183int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2184{
398f3351 2185 struct mlx5e_rqt *rqt;
1da36696
TT		 2186 int err;
2187 int ix;
2188
6bfd390b 2189 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351 2190 rqt = &priv->direct_tir[ix].rqt;
a5f97fee 2191 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
1da36696
TT		 2192 if (err)
2193 goto err_destroy_rqts;
2194 }
2195
2196 return 0;
2197
2198err_destroy_rqts:
8f493ffd 2199 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
1da36696 2200 for (ix--; ix >= 0; ix--)
398f3351 2201 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2202
f62b8bb8
AV		 2203 return err;
2204}
2205
8f493ffd
SM		 2206void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2207{
2208 int i;
2209
2210 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2211 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2212}
2213
a5f97fee
SM		 2214static int mlx5e_rx_hash_fn(int hfunc)
2215{
2216 return (hfunc == ETH_RSS_HASH_TOP) ?
2217 MLX5_RX_HASH_FN_TOEPLITZ :
2218 MLX5_RX_HASH_FN_INVERTED_XOR8;
2219}
2220
2221static int mlx5e_bits_invert(unsigned long a, int size)
2222{
2223 int inv = 0;
2224 int i;
2225
2226 for (i = 0; i < size; i++)
2227 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2228
2229 return inv;
2230}
2231
2232static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2233 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2234{
2235 int i;
2236
2237 for (i = 0; i < sz; i++) {
2238 u32 rqn;
2239
2240 if (rrp.is_rss) {
2241 int ix = i;
2242
2243 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2244 ix = mlx5e_bits_invert(i, ilog2(sz));
2245
6a9764ef 2246 ix = priv->channels.params.indirection_rqt[ix];
a5f97fee
SM		 2247 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2248 } else {
2249 rqn = rrp.rqn;
2250 }
2251 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2252 }
2253}
2254
2255int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2256 struct mlx5e_redirect_rqt_param rrp)
5c50368f
AS		 2257{
2258 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2259 void *rqtc;
2260 int inlen;
1da36696 2261 u32 *in;
5c50368f
AS		 2262 int err;
2263
5c50368f 2264 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2265 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2266 if (!in)
2267 return -ENOMEM;
2268
2269 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2270
2271 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5c50368f 2272 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
a5f97fee 2273 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
1da36696 2274 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2275
2276 kvfree(in);
5c50368f
AS		 2277 return err;
2278}
2279
a5f97fee
SM		 2280static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2281 struct mlx5e_redirect_rqt_param rrp)
2282{
2283 if (!rrp.is_rss)
2284 return rrp.rqn;
2285
2286 if (ix >= rrp.rss.channels->num)
2287 return priv->drop_rq.rqn;
2288
2289 return rrp.rss.channels->c[ix]->rq.rqn;
2290}
2291
2292static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2293 struct mlx5e_redirect_rqt_param rrp)
40ab6a6e 2294{
1da36696
TT		 2295 u32 rqtn;
2296 int ix;
2297
398f3351 2298 if (priv->indir_rqt.enabled) {
a5f97fee 2299 /* RSS RQ table */
398f3351 2300 rqtn = priv->indir_rqt.rqtn;
a5f97fee 2301 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
398f3351
HHZ		 2302 }
2303
a5f97fee
SM		 2304 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2305 struct mlx5e_redirect_rqt_param direct_rrp = {
2306 .is_rss = false,
95632791
AM		 2307 {
2308 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2309 },
a5f97fee
SM		 2310 };
2311
2312 /* Direct RQ Tables */
398f3351
HHZ		 2313 if (!priv->direct_tir[ix].rqt.enabled)
2314 continue;
a5f97fee 2315
398f3351 2316 rqtn = priv->direct_tir[ix].rqt.rqtn;
a5f97fee 2317 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
1da36696 2318 }
40ab6a6e
AS		 2319}
2320
a5f97fee
SM		 2321static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2322 struct mlx5e_channels *chs)
2323{
2324 struct mlx5e_redirect_rqt_param rrp = {
2325 .is_rss = true,
95632791
AM		 2326 {
2327 .rss = {
2328 .channels = chs,
2329 .hfunc = chs->params.rss_hfunc,
2330 }
2331 },
a5f97fee
SM		 2332 };
2333
2334 mlx5e_redirect_rqts(priv, rrp);
2335}
2336
2337static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2338{
2339 struct mlx5e_redirect_rqt_param drop_rrp = {
2340 .is_rss = false,
95632791
AM		 2341 {
2342 .rqn = priv->drop_rq.rqn,
2343 },
a5f97fee
SM		 2344 };
2345
2346 mlx5e_redirect_rqts(priv, drop_rrp);
2347}
2348
6a9764ef 2349static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
5c50368f 2350{
6a9764ef 2351 if (!params->lro_en)
5c50368f
AS		 2352 return;
2353
2354#define ROUGH_MAX_L2_L3_HDR_SZ 256
2355
2356 MLX5_SET(tirc, tirc, lro_enable_mask,
2357 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2358 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2359 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
6a9764ef
SM		 2360 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2361 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
5c50368f
AS		 2362}
2363
6a9764ef
SM		 2364void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2365 enum mlx5e_traffic_types tt,
7b3722fa 2366 void *tirc, bool inner)
bdfc028d 2367{
7b3722fa
GP		 2368 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2369 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
a100ff3e
GP		 2370
2371#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2372 MLX5_HASH_FIELD_SEL_DST_IP)
2373
2374#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2375 MLX5_HASH_FIELD_SEL_DST_IP |\
2376 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2377 MLX5_HASH_FIELD_SEL_L4_DPORT)
2378
2379#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2380 MLX5_HASH_FIELD_SEL_DST_IP |\
2381 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2382
6a9764ef
SM		 2383 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2384 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
bdfc028d
TT		 2385 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2386 rx_hash_toeplitz_key);
2387 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2388 rx_hash_toeplitz_key);
2389
2390 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
6a9764ef 2391 memcpy(rss_key, params->toeplitz_hash_key, len);
bdfc028d 2392 }
a100ff3e
GP		 2393
2394 switch (tt) {
2395 case MLX5E_TT_IPV4_TCP:
2396 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2397 MLX5_L3_PROT_TYPE_IPV4);
2398 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2399 MLX5_L4_PROT_TYPE_TCP);
2400 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2401 MLX5_HASH_IP_L4PORTS);
2402 break;
2403
2404 case MLX5E_TT_IPV6_TCP:
2405 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2406 MLX5_L3_PROT_TYPE_IPV6);
2407 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2408 MLX5_L4_PROT_TYPE_TCP);
2409 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2410 MLX5_HASH_IP_L4PORTS);
2411 break;
2412
2413 case MLX5E_TT_IPV4_UDP:
2414 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2415 MLX5_L3_PROT_TYPE_IPV4);
2416 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2417 MLX5_L4_PROT_TYPE_UDP);
2418 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2419 MLX5_HASH_IP_L4PORTS);
2420 break;
2421
2422 case MLX5E_TT_IPV6_UDP:
2423 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2424 MLX5_L3_PROT_TYPE_IPV6);
2425 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2426 MLX5_L4_PROT_TYPE_UDP);
2427 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2428 MLX5_HASH_IP_L4PORTS);
2429 break;
2430
2431 case MLX5E_TT_IPV4_IPSEC_AH:
2432 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2433 MLX5_L3_PROT_TYPE_IPV4);
2434 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2435 MLX5_HASH_IP_IPSEC_SPI);
2436 break;
2437
2438 case MLX5E_TT_IPV6_IPSEC_AH:
2439 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2440 MLX5_L3_PROT_TYPE_IPV6);
2441 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2442 MLX5_HASH_IP_IPSEC_SPI);
2443 break;
2444
2445 case MLX5E_TT_IPV4_IPSEC_ESP:
2446 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2447 MLX5_L3_PROT_TYPE_IPV4);
2448 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2449 MLX5_HASH_IP_IPSEC_SPI);
2450 break;
2451
2452 case MLX5E_TT_IPV6_IPSEC_ESP:
2453 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2454 MLX5_L3_PROT_TYPE_IPV6);
2455 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2456 MLX5_HASH_IP_IPSEC_SPI);
2457 break;
2458
2459 case MLX5E_TT_IPV4:
2460 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2461 MLX5_L3_PROT_TYPE_IPV4);
2462 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2463 MLX5_HASH_IP);
2464 break;
2465
2466 case MLX5E_TT_IPV6:
2467 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2468 MLX5_L3_PROT_TYPE_IPV6);
2469 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2470 MLX5_HASH_IP);
2471 break;
2472 default:
2473 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2474 }
bdfc028d
TT		 2475}
2476
ab0394fe 2477static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2478{
2479 struct mlx5_core_dev *mdev = priv->mdev;
2480
2481 void *in;
2482 void *tirc;
2483 int inlen;
2484 int err;
ab0394fe 2485 int tt;
1da36696 2486 int ix;
5c50368f
AS		 2487
2488 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1b9a07ee 2489 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2490 if (!in)
2491 return -ENOMEM;
2492
2493 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2494 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2495
6a9764ef 2496 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
5c50368f 2497
1da36696 2498 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2499 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2500 inlen);
ab0394fe 2501 if (err)
1da36696 2502 goto free_in;
ab0394fe 2503 }
5c50368f 2504
6bfd390b 2505 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2506 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2507 in, inlen);
2508 if (err)
2509 goto free_in;
2510 }
2511
2512free_in:
5c50368f
AS		 2513 kvfree(in);
2514
2515 return err;
2516}
2517
7b3722fa
GP		 2518static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2519 enum mlx5e_traffic_types tt,
2520 u32 *tirc)
2521{
2522 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2523
2524 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2525
2526 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2527 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2528 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2529
2530 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2531}
2532
cd255eff 2533static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2534{
40ab6a6e 2535 struct mlx5_core_dev *mdev = priv->mdev;
c139dbfd 2536 u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
40ab6a6e
AS		 2537 int err;
2538
cd255eff 2539 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2540 if (err)
2541 return err;
2542
cd255eff
SM		 2543 /* Update vport context MTU */
2544 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2545 return 0;
2546}
40ab6a6e 2547
cd255eff
SM		 2548static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2549{
2550 struct mlx5_core_dev *mdev = priv->mdev;
2551 u16 hw_mtu = 0;
2552 int err;
40ab6a6e 2553
cd255eff
SM		 2554 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2555 if (err || !hw_mtu) /* fallback to port oper mtu */
2556 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2557
c139dbfd 2558 *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
cd255eff
SM		 2559}
2560
2e20a151 2561static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
cd255eff 2562{
2e20a151 2563 struct net_device *netdev = priv->netdev;
cd255eff
SM		 2564 u16 mtu;
2565 int err;
2566
2567 err = mlx5e_set_mtu(priv, netdev->mtu);
2568 if (err)
2569 return err;
40ab6a6e 2570
cd255eff
SM		 2571 mlx5e_query_mtu(priv, &mtu);
2572 if (mtu != netdev->mtu)
2573 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2574 __func__, mtu, netdev->mtu);
40ab6a6e 2575
cd255eff 2576 netdev->mtu = mtu;
40ab6a6e
AS		 2577 return 0;
2578}
2579
08fb1dac
SM		 2580static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2581{
2582 struct mlx5e_priv *priv = netdev_priv(netdev);
6a9764ef
SM		 2583 int nch = priv->channels.params.num_channels;
2584 int ntc = priv->channels.params.num_tc;
08fb1dac
SM		 2585 int tc;
2586
2587 netdev_reset_tc(netdev);
2588
2589 if (ntc == 1)
2590 return;
2591
2592 netdev_set_num_tc(netdev, ntc);
2593
7ccdd084
RS		 2594 /* Map netdev TCs to offset 0
2595 * We have our own UP to TXQ mapping for QoS
2596 */
08fb1dac 2597 for (tc = 0; tc < ntc; tc++)
7ccdd084 2598 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2599}
2600
acc6c595
SM		 2601static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2602{
2603 struct mlx5e_channel *c;
2604 struct mlx5e_txqsq *sq;
2605 int i, tc;
2606
2607 for (i = 0; i < priv->channels.num; i++)
2608 for (tc = 0; tc < priv->profile->max_tc; tc++)
2609 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2610
2611 for (i = 0; i < priv->channels.num; i++) {
2612 c = priv->channels.c[i];
2613 for (tc = 0; tc < c->num_tc; tc++) {
2614 sq = &c->sq[tc];
2615 priv->txq2sq[sq->txq_ix] = sq;
2616 }
2617 }
2618}
2619
603f4a45 2620void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2621{
9008ae07
SM		 2622 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2623 struct net_device *netdev = priv->netdev;
2624
2625 mlx5e_netdev_set_tcs(netdev);
053ee0a7
TR		 2626 netif_set_real_num_tx_queues(netdev, num_txqs);
2627 netif_set_real_num_rx_queues(netdev, priv->channels.num);
9008ae07 2628
acc6c595
SM		 2629 mlx5e_build_channels_tx_maps(priv);
2630 mlx5e_activate_channels(&priv->channels);
2631 netif_tx_start_all_queues(priv->netdev);
9008ae07 2632
a9f7705f 2633 if (MLX5_VPORT_MANAGER(priv->mdev))
9008ae07
SM		 2634 mlx5e_add_sqs_fwd_rules(priv);
2635
acc6c595 2636 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
9008ae07 2637 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
acc6c595
SM		 2638}
2639
603f4a45 2640void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2641{
9008ae07
SM		 2642 mlx5e_redirect_rqts_to_drop(priv);
2643
a9f7705f 2644 if (MLX5_VPORT_MANAGER(priv->mdev))
9008ae07
SM		 2645 mlx5e_remove_sqs_fwd_rules(priv);
2646
acc6c595
SM		 2647 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2648 * polling for inactive tx queues.
2649 */
2650 netif_tx_stop_all_queues(priv->netdev);
2651 netif_tx_disable(priv->netdev);
2652 mlx5e_deactivate_channels(&priv->channels);
2653}
2654
55c2503d 2655void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2e20a151
SM		 2656 struct mlx5e_channels *new_chs,
2657 mlx5e_fp_hw_modify hw_modify)
55c2503d
SM		 2658{
2659 struct net_device *netdev = priv->netdev;
2660 int new_num_txqs;
7ca42c80 2661 int carrier_ok;
55c2503d
SM		 2662 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2663
7ca42c80 2664 carrier_ok = netif_carrier_ok(netdev);
55c2503d
SM		 2665 netif_carrier_off(netdev);
2666
2667 if (new_num_txqs < netdev->real_num_tx_queues)
2668 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2669
2670 mlx5e_deactivate_priv_channels(priv);
2671 mlx5e_close_channels(&priv->channels);
2672
2673 priv->channels = *new_chs;
2674
2e20a151
SM		 2675 /* New channels are ready to roll, modify HW settings if needed */
2676 if (hw_modify)
2677 hw_modify(priv);
2678
55c2503d
SM		 2679 mlx5e_refresh_tirs(priv, false);
2680 mlx5e_activate_priv_channels(priv);
2681
7ca42c80
ES		 2682 /* return carrier back if needed */
2683 if (carrier_ok)
2684 netif_carrier_on(netdev);
55c2503d
SM		 2685}
2686
7c39afb3
FD		 2687void mlx5e_timestamp_set(struct mlx5e_priv *priv)
2688{
2689 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2690 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2691}
2692
40ab6a6e
AS		 2693int mlx5e_open_locked(struct net_device *netdev)
2694{
2695 struct mlx5e_priv *priv = netdev_priv(netdev);
40ab6a6e
AS		 2696 int err;
2697
2698 set_bit(MLX5E_STATE_OPENED, &priv->state);
2699
ff9c852f 2700 err = mlx5e_open_channels(priv, &priv->channels);
acc6c595 2701 if (err)
343b29f3 2702 goto err_clear_state_opened_flag;
40ab6a6e 2703
b676f653 2704 mlx5e_refresh_tirs(priv, false);
acc6c595 2705 mlx5e_activate_priv_channels(priv);
7ca42c80
ES		 2706 if (priv->profile->update_carrier)
2707 priv->profile->update_carrier(priv);
7c39afb3 2708 mlx5e_timestamp_set(priv);
be4891af 2709
cb67b832
HHZ		 2710 if (priv->profile->update_stats)
2711 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2712
9b37b07f 2713 return 0;
343b29f3
AS		 2714
2715err_clear_state_opened_flag:
2716 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2717 return err;
40ab6a6e
AS		 2718}
2719
cb67b832 2720int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2721{
2722 struct mlx5e_priv *priv = netdev_priv(netdev);
2723 int err;
2724
2725 mutex_lock(&priv->state_lock);
2726 err = mlx5e_open_locked(netdev);
63bfd399
EBE		 2727 if (!err)
2728 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
40ab6a6e
AS		 2729 mutex_unlock(&priv->state_lock);
2730
2731 return err;
2732}
2733
2734int mlx5e_close_locked(struct net_device *netdev)
2735{
2736 struct mlx5e_priv *priv = netdev_priv(netdev);
2737
a1985740
AS		 2738 /* May already be CLOSED in case a previous configuration operation
2739 * (e.g RX/TX queue size change) that involves close&open failed.
2740 */
2741 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2742 return 0;
2743
40ab6a6e
AS		 2744 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2745
40ab6a6e 2746 netif_carrier_off(priv->netdev);
acc6c595
SM		 2747 mlx5e_deactivate_priv_channels(priv);
2748 mlx5e_close_channels(&priv->channels);
40ab6a6e
AS		 2749
2750 return 0;
2751}
2752
cb67b832 2753int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2754{
2755 struct mlx5e_priv *priv = netdev_priv(netdev);
2756 int err;
2757
26e59d80
MHY		 2758 if (!netif_device_present(netdev))
2759 return -ENODEV;
2760
40ab6a6e 2761 mutex_lock(&priv->state_lock);
63bfd399 2762 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
40ab6a6e
AS		 2763 err = mlx5e_close_locked(netdev);
2764 mutex_unlock(&priv->state_lock);
2765
2766 return err;
2767}
2768
a43b25da 2769static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2770 struct mlx5e_rq *rq,
2771 struct mlx5e_rq_param *param)
40ab6a6e 2772{
40ab6a6e
AS		 2773 void *rqc = param->rqc;
2774 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2775 int err;
2776
2777 param->wq.db_numa_node = param->wq.buf_numa_node;
2778
2779 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2780 &rq->wq_ctrl);
2781 if (err)
2782 return err;
2783
0ddf5432
JDB		 2784 /* Mark as unused given "Drop-RQ" packets never reach XDP */
2785 xdp_rxq_info_unused(&rq->xdp_rxq);
2786
a43b25da 2787 rq->mdev = mdev;
40ab6a6e
AS		 2788
2789 return 0;
2790}
2791
a43b25da 2792static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2793 struct mlx5e_cq *cq,
2794 struct mlx5e_cq_param *param)
40ab6a6e 2795{
95b6c6a5 2796 return mlx5e_alloc_cq_common(mdev, param, cq);
40ab6a6e
AS		 2797}
2798
a43b25da
SM		 2799static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2800 struct mlx5e_rq *drop_rq)
40ab6a6e 2801{
a43b25da
SM		 2802 struct mlx5e_cq_param cq_param = {};
2803 struct mlx5e_rq_param rq_param = {};
2804 struct mlx5e_cq *cq = &drop_rq->cq;
40ab6a6e
AS		 2805 int err;
2806
556dd1b9 2807 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e 2808
a43b25da 2809 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
40ab6a6e
AS		 2810 if (err)
2811 return err;
2812
3b77235b 2813 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 2814 if (err)
3b77235b 2815 goto err_free_cq;
40ab6a6e 2816
a43b25da 2817 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
40ab6a6e 2818 if (err)
3b77235b 2819 goto err_destroy_cq;
40ab6a6e 2820
a43b25da 2821 err = mlx5e_create_rq(drop_rq, &rq_param);
40ab6a6e 2822 if (err)
3b77235b 2823 goto err_free_rq;
40ab6a6e
AS		 2824
2825 return 0;
2826
3b77235b 2827err_free_rq:
a43b25da 2828 mlx5e_free_rq(drop_rq);
40ab6a6e
AS		 2829
2830err_destroy_cq:
a43b25da 2831 mlx5e_destroy_cq(cq);
40ab6a6e 2832
3b77235b 2833err_free_cq:
a43b25da 2834 mlx5e_free_cq(cq);
3b77235b 2835
40ab6a6e
AS		 2836 return err;
2837}
2838
a43b25da 2839static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
40ab6a6e 2840{
a43b25da
SM		 2841 mlx5e_destroy_rq(drop_rq);
2842 mlx5e_free_rq(drop_rq);
2843 mlx5e_destroy_cq(&drop_rq->cq);
2844 mlx5e_free_cq(&drop_rq->cq);
40ab6a6e
AS		 2845}
2846
5426a0b2
SM		 2847int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2848 u32 underlay_qpn, u32 *tisn)
40ab6a6e 2849{
c4f287c4 2850 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2851 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2852
08fb1dac 2853 MLX5_SET(tisc, tisc, prio, tc << 1);
5426a0b2 2854 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
b50d292b 2855 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2856
2857 if (mlx5_lag_is_lacp_owner(mdev))
2858 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2859
5426a0b2 2860 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
40ab6a6e
AS		 2861}
2862
5426a0b2 2863void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
40ab6a6e 2864{
5426a0b2 2865 mlx5_core_destroy_tis(mdev, tisn);
40ab6a6e
AS		 2866}
2867
cb67b832 2868int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2869{
2870 int err;
2871 int tc;
2872
6bfd390b 2873 for (tc = 0; tc < priv->profile->max_tc; tc++) {
5426a0b2 2874 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
40ab6a6e
AS		 2875 if (err)
2876 goto err_close_tises;
2877 }
2878
2879 return 0;
2880
2881err_close_tises:
2882 for (tc--; tc >= 0; tc--)
5426a0b2 2883 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2884
2885 return err;
2886}
2887
cb67b832 2888void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2889{
2890 int tc;
2891
6bfd390b 2892 for (tc = 0; tc < priv->profile->max_tc; tc++)
5426a0b2 2893 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2894}
2895
6a9764ef
SM		 2896static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2897 enum mlx5e_traffic_types tt,
2898 u32 *tirc)
f62b8bb8 2899{
b50d292b 2900 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2901
6a9764ef 2902 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
f62b8bb8 2903
4cbeaff5 2904 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2905 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
7b3722fa 2906 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
f62b8bb8
AV		 2907}
2908
6a9764ef 2909static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
f62b8bb8 2910{
b50d292b 2911 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696 2912
6a9764ef 2913 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
1da36696
TT		 2914
2915 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2916 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2917 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2918}
2919
8f493ffd 2920int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2921{
724b2aa1 2922 struct mlx5e_tir *tir;
f62b8bb8
AV		 2923 void *tirc;
2924 int inlen;
7b3722fa 2925 int i = 0;
f62b8bb8 2926 int err;
1da36696 2927 u32 *in;
1da36696 2928 int tt;
f62b8bb8
AV		 2929
2930 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2931 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2932 if (!in)
2933 return -ENOMEM;
2934
1da36696
TT		 2935 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2936 memset(in, 0, inlen);
724b2aa1 2937 tir = &priv->indir_tir[tt];
1da36696 2938 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2939 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
724b2aa1 2940 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
7b3722fa
GP		 2941 if (err) {
2942 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2943 goto err_destroy_inner_tirs;
2944 }
f62b8bb8
AV		 2945 }
2946
7b3722fa
GP		 2947 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2948 goto out;
2949
2950 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2951 memset(in, 0, inlen);
2952 tir = &priv->inner_indir_tir[i];
2953 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2954 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2955 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2956 if (err) {
2957 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2958 goto err_destroy_inner_tirs;
2959 }
2960 }
2961
2962out:
6bfd390b
HHZ		 2963 kvfree(in);
2964
2965 return 0;
2966
7b3722fa
GP		 2967err_destroy_inner_tirs:
2968 for (i--; i >= 0; i--)
2969 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2970
6bfd390b
HHZ		 2971 for (tt--; tt >= 0; tt--)
2972 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2973
2974 kvfree(in);
2975
2976 return err;
2977}
2978
cb67b832 2979int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2980{
2981 int nch = priv->profile->max_nch(priv->mdev);
2982 struct mlx5e_tir *tir;
2983 void *tirc;
2984 int inlen;
2985 int err;
2986 u32 *in;
2987 int ix;
2988
2989 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2990 in = kvzalloc(inlen, GFP_KERNEL);
6bfd390b
HHZ		 2991 if (!in)
2992 return -ENOMEM;
2993
1da36696
TT		 2994 for (ix = 0; ix < nch; ix++) {
2995 memset(in, 0, inlen);
724b2aa1 2996 tir = &priv->direct_tir[ix];
1da36696 2997 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2998 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
724b2aa1 2999 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 3000 if (err)
3001 goto err_destroy_ch_tirs;
3002 }
3003
3004 kvfree(in);
3005
f62b8bb8
AV		 3006 return 0;
3007
1da36696 3008err_destroy_ch_tirs:
8f493ffd 3009 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
1da36696 3010 for (ix--; ix >= 0; ix--)
724b2aa1 3011 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 3012
1da36696 3013 kvfree(in);
f62b8bb8
AV		 3014
3015 return err;
3016}
3017
8f493ffd 3018void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 3019{
3020 int i;
3021
1da36696 3022 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 3023 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
7b3722fa
GP		 3024
3025 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3026 return;
3027
3028 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3029 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
f62b8bb8
AV		 3030}
3031
cb67b832 3032void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 3033{
3034 int nch = priv->profile->max_nch(priv->mdev);
3035 int i;
3036
3037 for (i = 0; i < nch; i++)
3038 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3039}
3040
102722fc
GE		 3041static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3042{
3043 int err = 0;
3044 int i;
3045
3046 for (i = 0; i < chs->num; i++) {
3047 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3048 if (err)
3049 return err;
3050 }
3051
3052 return 0;
3053}
3054
f6d96a20 3055static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
36350114
GP		 3056{
3057 int err = 0;
3058 int i;
3059
ff9c852f
SM		 3060 for (i = 0; i < chs->num; i++) {
3061 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
36350114
GP		 3062 if (err)
3063 return err;
3064 }
3065
3066 return 0;
3067}
3068
0cf0f6d3
JP		 3069static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3070 struct tc_mqprio_qopt *mqprio)
08fb1dac
SM		 3071{
3072 struct mlx5e_priv *priv = netdev_priv(netdev);
6f9485af 3073 struct mlx5e_channels new_channels = {};
0cf0f6d3 3074 u8 tc = mqprio->num_tc;
08fb1dac
SM		 3075 int err = 0;
3076
0cf0f6d3
JP		 3077 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3078
08fb1dac
SM		 3079 if (tc && tc != MLX5E_MAX_NUM_TC)
3080 return -EINVAL;
3081
3082 mutex_lock(&priv->state_lock);
3083
6f9485af
SM		 3084 new_channels.params = priv->channels.params;
3085 new_channels.params.num_tc = tc ? tc : 1;
08fb1dac 3086
20b6a1c7 3087 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6f9485af
SM		 3088 priv->channels.params = new_channels.params;
3089 goto out;
3090 }
08fb1dac 3091
6f9485af
SM		 3092 err = mlx5e_open_channels(priv, &new_channels);
3093 if (err)
3094 goto out;
08fb1dac 3095
2e20a151 3096 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
6f9485af 3097out:
08fb1dac 3098 mutex_unlock(&priv->state_lock);
08fb1dac
SM		 3099 return err;
3100}
3101
e80541ec 3102#ifdef CONFIG_MLX5_ESWITCH
d6c862ba 3103static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
0cf0f6d3 3104 struct tc_cls_flower_offload *cls_flower)
08fb1dac 3105{
d6c862ba 3106 if (cls_flower->common.chain_index)
0cf0f6d3 3107 return -EOPNOTSUPP;
e8f887ac 3108
0cf0f6d3
JP		 3109 switch (cls_flower->command) {
3110 case TC_CLSFLOWER_REPLACE:
5fd9fc4e 3111 return mlx5e_configure_flower(priv, cls_flower);
0cf0f6d3
JP		 3112 case TC_CLSFLOWER_DESTROY:
3113 return mlx5e_delete_flower(priv, cls_flower);
3114 case TC_CLSFLOWER_STATS:
3115 return mlx5e_stats_flower(priv, cls_flower);
3116 default:
a5fcf8a6 3117 return -EOPNOTSUPP;
0cf0f6d3
JP		 3118 }
3119}
d6c862ba
JP		 3120
3121int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3122 void *cb_priv)
3123{
3124 struct mlx5e_priv *priv = cb_priv;
3125
44ae12a7
JP		 3126 if (!tc_can_offload(priv->netdev))
3127 return -EOPNOTSUPP;
3128
d6c862ba
JP		 3129 switch (type) {
3130 case TC_SETUP_CLSFLOWER:
3131 return mlx5e_setup_tc_cls_flower(priv, type_data);
3132 default:
3133 return -EOPNOTSUPP;
3134 }
3135}
3136
3137static int mlx5e_setup_tc_block(struct net_device *dev,
3138 struct tc_block_offload *f)
3139{
3140 struct mlx5e_priv *priv = netdev_priv(dev);
3141
3142 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3143 return -EOPNOTSUPP;
3144
3145 switch (f->command) {
3146 case TC_BLOCK_BIND:
3147 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3148 priv, priv);
3149 case TC_BLOCK_UNBIND:
3150 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3151 priv);
3152 return 0;
3153 default:
3154 return -EOPNOTSUPP;
3155 }
3156}
e80541ec 3157#endif
a5fcf8a6 3158
717503b9
JP		 3159int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3160 void *type_data)
0cf0f6d3 3161{
2572ac53 3162 switch (type) {
fde6af47 3163#ifdef CONFIG_MLX5_ESWITCH
d6c862ba
JP		 3164 case TC_SETUP_BLOCK:
3165 return mlx5e_setup_tc_block(dev, type_data);
fde6af47 3166#endif
575ed7d3 3167 case TC_SETUP_QDISC_MQPRIO:
de4784ca 3168 return mlx5e_setup_tc_mqprio(dev, type_data);
e8f887ac
AV		 3169 default:
3170 return -EOPNOTSUPP;
3171 }
08fb1dac
SM		 3172}
3173
bc1f4470 3174static void
f62b8bb8
AV		 3175mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3176{
3177 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 3178 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 3179 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 3180 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 3181
370bad0f
OG		 3182 if (mlx5e_is_uplink_rep(priv)) {
3183 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3184 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3185 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3186 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3187 } else {
3188 stats->rx_packets = sstats->rx_packets;
3189 stats->rx_bytes = sstats->rx_bytes;
3190 stats->tx_packets = sstats->tx_packets;
3191 stats->tx_bytes = sstats->tx_bytes;
3192 stats->tx_dropped = sstats->tx_queue_dropped;
3193 }
269e6b3a
GP		 3194
3195 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 3196
3197 stats->rx_length_errors =
9218b44d
GP		 3198 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3199 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3200 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 3201 stats->rx_crc_errors =
9218b44d
GP		 3202 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3203 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3204 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a
GP		 3205 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3206 stats->rx_frame_errors;
3207 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3208
3209 /* vport multicast also counts packets that are dropped due to steering
3210 * or rx out of buffer
3211 */
9218b44d
GP		 3212 stats->multicast =
3213 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 3214}
3215
3216static void mlx5e_set_rx_mode(struct net_device *dev)
3217{
3218 struct mlx5e_priv *priv = netdev_priv(dev);
3219
7bb29755 3220 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3221}
3222
3223static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3224{
3225 struct mlx5e_priv *priv = netdev_priv(netdev);
3226 struct sockaddr *saddr = addr;
3227
3228 if (!is_valid_ether_addr(saddr->sa_data))
3229 return -EADDRNOTAVAIL;
3230
3231 netif_addr_lock_bh(netdev);
3232 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3233 netif_addr_unlock_bh(netdev);
3234
7bb29755 3235 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3236
3237 return 0;
3238}
3239
0e405443
GP		 3240#define MLX5E_SET_FEATURE(netdev, feature, enable) \
3241 do { \
3242 if (enable) \
3243 netdev->features |= feature; \
3244 else \
3245 netdev->features &= ~feature; \
3246 } while (0)
3247
3248typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3249
3250static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 3251{
3252 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3253 struct mlx5e_channels new_channels = {};
3254 int err = 0;
3255 bool reset;
f62b8bb8
AV		 3256
3257 mutex_lock(&priv->state_lock);
f62b8bb8 3258
2e20a151
SM		 3259 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3260 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3261
2e20a151
SM		 3262 new_channels.params = priv->channels.params;
3263 new_channels.params.lro_en = enable;
3264
3265 if (!reset) {
3266 priv->channels.params = new_channels.params;
3267 err = mlx5e_modify_tirs_lro(priv);
3268 goto out;
98e81b0a 3269 }
f62b8bb8 3270
2e20a151
SM		 3271 err = mlx5e_open_channels(priv, &new_channels);
3272 if (err)
3273 goto out;
0e405443 3274
2e20a151
SM		 3275 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3276out:
9b37b07f 3277 mutex_unlock(&priv->state_lock);
0e405443
GP		 3278 return err;
3279}
3280
2b52a283 3281static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
0e405443
GP		 3282{
3283 struct mlx5e_priv *priv = netdev_priv(netdev);
3284
3285 if (enable)
2b52a283 3286 mlx5e_enable_cvlan_filter(priv);
0e405443 3287 else
2b52a283 3288 mlx5e_disable_cvlan_filter(priv);
0e405443
GP		 3289
3290 return 0;
3291}
3292
3293static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3294{
3295 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 3296
0e405443 3297 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 3298 netdev_err(netdev,
3299 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3300 return -EINVAL;
3301 }
3302
0e405443
GP		 3303 return 0;
3304}
3305
94cb1ebb
EBE		 3306static int set_feature_rx_all(struct net_device *netdev, bool enable)
3307{
3308 struct mlx5e_priv *priv = netdev_priv(netdev);
3309 struct mlx5_core_dev *mdev = priv->mdev;
3310
3311 return mlx5_set_port_fcs(mdev, !enable);
3312}
3313
102722fc
GE		 3314static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3315{
3316 struct mlx5e_priv *priv = netdev_priv(netdev);
3317 int err;
3318
3319 mutex_lock(&priv->state_lock);
3320
3321 priv->channels.params.scatter_fcs_en = enable;
3322 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3323 if (err)
3324 priv->channels.params.scatter_fcs_en = !enable;
3325
3326 mutex_unlock(&priv->state_lock);
3327
3328 return err;
3329}
3330
36350114
GP		 3331static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3332{
3333 struct mlx5e_priv *priv = netdev_priv(netdev);
ff9c852f 3334 int err = 0;
36350114
GP		 3335
3336 mutex_lock(&priv->state_lock);
3337
6a9764ef 3338 priv->channels.params.vlan_strip_disable = !enable;
ff9c852f
SM		 3339 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3340 goto unlock;
3341
3342 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
36350114 3343 if (err)
6a9764ef 3344 priv->channels.params.vlan_strip_disable = enable;
36350114 3345
ff9c852f 3346unlock:
36350114
GP		 3347 mutex_unlock(&priv->state_lock);
3348
3349 return err;
3350}
3351
45bf454a
MG		 3352#ifdef CONFIG_RFS_ACCEL
3353static int set_feature_arfs(struct net_device *netdev, bool enable)
3354{
3355 struct mlx5e_priv *priv = netdev_priv(netdev);
3356 int err;
3357
3358 if (enable)
3359 err = mlx5e_arfs_enable(priv);
3360 else
3361 err = mlx5e_arfs_disable(priv);
3362
3363 return err;
3364}
3365#endif
3366
0e405443
GP		 3367static int mlx5e_handle_feature(struct net_device *netdev,
3368 netdev_features_t wanted_features,
3369 netdev_features_t feature,
3370 mlx5e_feature_handler feature_handler)
3371{
3372 netdev_features_t changes = wanted_features ^ netdev->features;
3373 bool enable = !!(wanted_features & feature);
3374 int err;
3375
3376 if (!(changes & feature))
3377 return 0;
3378
3379 err = feature_handler(netdev, enable);
3380 if (err) {
b20eab15
GP		 3381 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3382 enable ? "Enable" : "Disable", &feature, err);
0e405443
GP		 3383 return err;
3384 }
3385
3386 MLX5E_SET_FEATURE(netdev, feature, enable);
3387 return 0;
3388}
3389
3390static int mlx5e_set_features(struct net_device *netdev,
3391 netdev_features_t features)
3392{
3393 int err;
3394
3395 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3396 set_feature_lro);
3397 err |= mlx5e_handle_feature(netdev, features,
3398 NETIF_F_HW_VLAN_CTAG_FILTER,
2b52a283 3399 set_feature_cvlan_filter);
0e405443
GP		 3400 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3401 set_feature_tc_num_filters);
94cb1ebb
EBE		 3402 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3403 set_feature_rx_all);
102722fc
GE		 3404 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3405 set_feature_rx_fcs);
36350114
GP		 3406 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3407 set_feature_rx_vlan);
45bf454a
MG		 3408#ifdef CONFIG_RFS_ACCEL
3409 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3410 set_feature_arfs);
3411#endif
0e405443
GP		 3412
3413 return err ? -EINVAL : 0;
f62b8bb8
AV		 3414}
3415
7d92d580
GP		 3416static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3417 netdev_features_t features)
3418{
3419 struct mlx5e_priv *priv = netdev_priv(netdev);
3420
3421 mutex_lock(&priv->state_lock);
3422 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3423 /* HW strips the outer C-tag header, this is a problem
3424 * for S-tag traffic.
3425 */
3426 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3427 if (!priv->channels.params.vlan_strip_disable)
3428 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3429 }
3430 mutex_unlock(&priv->state_lock);
3431
3432 return features;
3433}
3434
f62b8bb8
AV		 3435static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3436{
3437 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3438 struct mlx5e_channels new_channels = {};
3439 int curr_mtu;
98e81b0a 3440 int err = 0;
506753b0 3441 bool reset;
f62b8bb8 3442
f62b8bb8 3443 mutex_lock(&priv->state_lock);
98e81b0a 3444
6a9764ef
SM		 3445 reset = !priv->channels.params.lro_en &&
3446 (priv->channels.params.rq_wq_type !=
506753b0
TT		 3447 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3448
2e20a151 3449 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3450
2e20a151 3451 curr_mtu = netdev->mtu;
f62b8bb8 3452 netdev->mtu = new_mtu;
98e81b0a 3453
2e20a151
SM		 3454 if (!reset) {
3455 mlx5e_set_dev_port_mtu(priv);
3456 goto out;
3457 }
98e81b0a 3458
2e20a151
SM		 3459 new_channels.params = priv->channels.params;
3460 err = mlx5e_open_channels(priv, &new_channels);
3461 if (err) {
3462 netdev->mtu = curr_mtu;
3463 goto out;
3464 }
3465
3466 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
f62b8bb8 3467
2e20a151
SM		 3468out:
3469 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 3470 return err;
3471}
3472
7c39afb3
FD		 3473int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3474{
3475 struct hwtstamp_config config;
3476 int err;
3477
3478 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3479 return -EOPNOTSUPP;
3480
3481 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3482 return -EFAULT;
3483
3484 /* TX HW timestamp */
3485 switch (config.tx_type) {
3486 case HWTSTAMP_TX_OFF:
3487 case HWTSTAMP_TX_ON:
3488 break;
3489 default:
3490 return -ERANGE;
3491 }
3492
3493 mutex_lock(&priv->state_lock);
3494 /* RX HW timestamp */
3495 switch (config.rx_filter) {
3496 case HWTSTAMP_FILTER_NONE:
3497 /* Reset CQE compression to Admin default */
3498 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3499 break;
3500 case HWTSTAMP_FILTER_ALL:
3501 case HWTSTAMP_FILTER_SOME:
3502 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3503 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3504 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3505 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3506 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3507 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3508 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3509 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3510 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3511 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3512 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3513 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3514 case HWTSTAMP_FILTER_NTP_ALL:
3515 /* Disable CQE compression */
3516 netdev_warn(priv->netdev, "Disabling cqe compression");
3517 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3518 if (err) {
3519 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3520 mutex_unlock(&priv->state_lock);
3521 return err;
3522 }
3523 config.rx_filter = HWTSTAMP_FILTER_ALL;
3524 break;
3525 default:
3526 mutex_unlock(&priv->state_lock);
3527 return -ERANGE;
3528 }
3529
3530 memcpy(&priv->tstamp, &config, sizeof(config));
3531 mutex_unlock(&priv->state_lock);
3532
3533 return copy_to_user(ifr->ifr_data, &config,
3534 sizeof(config)) ? -EFAULT : 0;
3535}
3536
3537int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3538{
3539 struct hwtstamp_config *cfg = &priv->tstamp;
3540
3541 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3542 return -EOPNOTSUPP;
3543
3544 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3545}
3546
ef9814de
EBE		 3547static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3548{
1170fbd8
FD		 3549 struct mlx5e_priv *priv = netdev_priv(dev);
3550
ef9814de
EBE		 3551 switch (cmd) {
3552 case SIOCSHWTSTAMP:
1170fbd8 3553 return mlx5e_hwstamp_set(priv, ifr);
ef9814de 3554 case SIOCGHWTSTAMP:
1170fbd8 3555 return mlx5e_hwstamp_get(priv, ifr);
ef9814de
EBE		 3556 default:
3557 return -EOPNOTSUPP;
3558 }
3559}
3560
e80541ec 3561#ifdef CONFIG_MLX5_ESWITCH
66e49ded
SM		 3562static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3563{
3564 struct mlx5e_priv *priv = netdev_priv(dev);
3565 struct mlx5_core_dev *mdev = priv->mdev;
3566
3567 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3568}
3569
79aab093
MS		 3570static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3571 __be16 vlan_proto)
66e49ded
SM		 3572{
3573 struct mlx5e_priv *priv = netdev_priv(dev);
3574 struct mlx5_core_dev *mdev = priv->mdev;
3575
79aab093
MS		 3576 if (vlan_proto != htons(ETH_P_8021Q))
3577 return -EPROTONOSUPPORT;
3578
66e49ded
SM		 3579 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3580 vlan, qos);
3581}
3582
f942380c
MHY		 3583static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3584{
3585 struct mlx5e_priv *priv = netdev_priv(dev);
3586 struct mlx5_core_dev *mdev = priv->mdev;
3587
3588 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3589}
3590
1edc57e2
MHY		 3591static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3592{
3593 struct mlx5e_priv *priv = netdev_priv(dev);
3594 struct mlx5_core_dev *mdev = priv->mdev;
3595
3596 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3597}
bd77bf1c
MHY		 3598
3599static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3600 int max_tx_rate)
3601{
3602 struct mlx5e_priv *priv = netdev_priv(dev);
3603 struct mlx5_core_dev *mdev = priv->mdev;
3604
bd77bf1c 3605 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3606 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3607}
3608
66e49ded
SM		 3609static int mlx5_vport_link2ifla(u8 esw_link)
3610{
3611 switch (esw_link) {
3612 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3613 return IFLA_VF_LINK_STATE_DISABLE;
3614 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3615 return IFLA_VF_LINK_STATE_ENABLE;
3616 }
3617 return IFLA_VF_LINK_STATE_AUTO;
3618}
3619
3620static int mlx5_ifla_link2vport(u8 ifla_link)
3621{
3622 switch (ifla_link) {
3623 case IFLA_VF_LINK_STATE_DISABLE:
3624 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3625 case IFLA_VF_LINK_STATE_ENABLE:
3626 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3627 }
3628 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3629}
3630
3631static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3632 int link_state)
3633{
3634 struct mlx5e_priv *priv = netdev_priv(dev);
3635 struct mlx5_core_dev *mdev = priv->mdev;
3636
3637 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3638 mlx5_ifla_link2vport(link_state));
3639}
3640
3641static int mlx5e_get_vf_config(struct net_device *dev,
3642 int vf, struct ifla_vf_info *ivi)
3643{
3644 struct mlx5e_priv *priv = netdev_priv(dev);
3645 struct mlx5_core_dev *mdev = priv->mdev;
3646 int err;
3647
3648 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3649 if (err)
3650 return err;
3651 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3652 return 0;
3653}
3654
3655static int mlx5e_get_vf_stats(struct net_device *dev,
3656 int vf, struct ifla_vf_stats *vf_stats)
3657{
3658 struct mlx5e_priv *priv = netdev_priv(dev);
3659 struct mlx5_core_dev *mdev = priv->mdev;
3660
3661 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3662 vf_stats);
3663}
e80541ec 3664#endif
66e49ded 3665
1ad9a00a
PB		 3666static void mlx5e_add_vxlan_port(struct net_device *netdev,
3667 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3668{
3669 struct mlx5e_priv *priv = netdev_priv(netdev);
3670
974c3f30
AD		 3671 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3672 return;
3673
b3f63c3d
MF		 3674 if (!mlx5e_vxlan_allowed(priv->mdev))
3675 return;
3676
974c3f30 3677 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3678}
3679
1ad9a00a
PB		 3680static void mlx5e_del_vxlan_port(struct net_device *netdev,
3681 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3682{
3683 struct mlx5e_priv *priv = netdev_priv(netdev);
3684
974c3f30
AD		 3685 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3686 return;
3687
b3f63c3d
MF		 3688 if (!mlx5e_vxlan_allowed(priv->mdev))
3689 return;
3690
974c3f30 3691 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3692}
3693
27299841
GP		 3694static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3695 struct sk_buff *skb,
3696 netdev_features_t features)
b3f63c3d 3697{
2989ad1e 3698 unsigned int offset = 0;
b3f63c3d 3699 struct udphdr *udph;
27299841
GP		 3700 u8 proto;
3701 u16 port;
b3f63c3d
MF		 3702
3703 switch (vlan_get_protocol(skb)) {
3704 case htons(ETH_P_IP):
3705 proto = ip_hdr(skb)->protocol;
3706 break;
3707 case htons(ETH_P_IPV6):
2989ad1e 3708 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
b3f63c3d
MF		 3709 break;
3710 default:
3711 goto out;
3712 }
3713
27299841
GP		 3714 switch (proto) {
3715 case IPPROTO_GRE:
3716 return features;
3717 case IPPROTO_UDP:
b3f63c3d
MF		 3718 udph = udp_hdr(skb);
3719 port = be16_to_cpu(udph->dest);
b3f63c3d 3720
27299841
GP		 3721 /* Verify if UDP port is being offloaded by HW */
3722 if (mlx5e_vxlan_lookup_port(priv, port))
3723 return features;
3724 }
b3f63c3d
MF		 3725
3726out:
3727 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3728 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3729}
3730
3731static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3732 struct net_device *netdev,
3733 netdev_features_t features)
3734{
3735 struct mlx5e_priv *priv = netdev_priv(netdev);
3736
3737 features = vlan_features_check(skb, features);
3738 features = vxlan_features_check(skb, features);
3739
2ac9cfe7
IT		 3740#ifdef CONFIG_MLX5_EN_IPSEC
3741 if (mlx5e_ipsec_feature_check(skb, netdev, features))
3742 return features;
3743#endif
3744
b3f63c3d
MF		 3745 /* Validate if the tunneled packet is being offloaded by HW */
3746 if (skb->encapsulation &&
3747 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
27299841 3748 return mlx5e_tunnel_features_check(priv, skb, features);
b3f63c3d
MF		 3749
3750 return features;
3751}
3752
3947ca18
DJ		 3753static void mlx5e_tx_timeout(struct net_device *dev)
3754{
3755 struct mlx5e_priv *priv = netdev_priv(dev);
3756 bool sched_work = false;
3757 int i;
3758
3759 netdev_err(dev, "TX timeout detected\n");
3760
6a9764ef 3761 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
acc6c595 3762 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3947ca18 3763
2c1ccc99 3764 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3765 continue;
3766 sched_work = true;
c0f1147d 3767 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3947ca18
DJ		 3768 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3769 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3770 }
3771
3772 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3773 schedule_work(&priv->tx_timeout_work);
3774}
3775
86994156
RS		 3776static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3777{
3778 struct mlx5e_priv *priv = netdev_priv(netdev);
3779 struct bpf_prog *old_prog;
3780 int err = 0;
3781 bool reset, was_opened;
3782 int i;
3783
3784 mutex_lock(&priv->state_lock);
3785
3786 if ((netdev->features & NETIF_F_LRO) && prog) {
3787 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3788 err = -EINVAL;
3789 goto unlock;
3790 }
3791
547eede0
IT		 3792 if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3793 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3794 err = -EINVAL;
3795 goto unlock;
3796 }
3797
86994156
RS		 3798 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3799 /* no need for full reset when exchanging programs */
6a9764ef 3800 reset = (!priv->channels.params.xdp_prog || !prog);
86994156
RS		 3801
3802 if (was_opened && reset)
3803 mlx5e_close_locked(netdev);
c54c0629
DB		 3804 if (was_opened && !reset) {
3805 /* num_channels is invariant here, so we can take the
3806 * batched reference right upfront.
3807 */
6a9764ef 3808 prog = bpf_prog_add(prog, priv->channels.num);
c54c0629
DB		 3809 if (IS_ERR(prog)) {
3810 err = PTR_ERR(prog);
3811 goto unlock;
3812 }
3813 }
86994156 3814
c54c0629
DB		 3815 /* exchange programs, extra prog reference we got from caller
3816 * as long as we don't fail from this point onwards.
3817 */
6a9764ef 3818 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
86994156
RS		 3819 if (old_prog)
3820 bpf_prog_put(old_prog);
3821
3822 if (reset) /* change RQ type according to priv->xdp_prog */
6a9764ef 3823 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
86994156
RS		 3824
3825 if (was_opened && reset)
3826 mlx5e_open_locked(netdev);
3827
3828 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3829 goto unlock;
3830
3831 /* exchanging programs w/o reset, we update ref counts on behalf
3832 * of the channels RQs here.
3833 */
ff9c852f
SM		 3834 for (i = 0; i < priv->channels.num; i++) {
3835 struct mlx5e_channel *c = priv->channels.c[i];
86994156 3836
c0f1147d 3837 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3838 napi_synchronize(&c->napi);
3839 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3840
3841 old_prog = xchg(&c->rq.xdp_prog, prog);
3842
c0f1147d 3843 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156 3844 /* napi_schedule in case we have missed anything */
86994156
RS		 3845 napi_schedule(&c->napi);
3846
3847 if (old_prog)
3848 bpf_prog_put(old_prog);
3849 }
3850
3851unlock:
3852 mutex_unlock(&priv->state_lock);
3853 return err;
3854}
3855
821b2e29 3856static u32 mlx5e_xdp_query(struct net_device *dev)
86994156
RS		 3857{
3858 struct mlx5e_priv *priv = netdev_priv(dev);
821b2e29
MKL		 3859 const struct bpf_prog *xdp_prog;
3860 u32 prog_id = 0;
86994156 3861
821b2e29
MKL		 3862 mutex_lock(&priv->state_lock);
3863 xdp_prog = priv->channels.params.xdp_prog;
3864 if (xdp_prog)
3865 prog_id = xdp_prog->aux->id;
3866 mutex_unlock(&priv->state_lock);
3867
3868 return prog_id;
86994156
RS		 3869}
3870
f4e63525 3871static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
86994156
RS		 3872{
3873 switch (xdp->command) {
3874 case XDP_SETUP_PROG:
3875 return mlx5e_xdp_set(dev, xdp->prog);
3876 case XDP_QUERY_PROG:
821b2e29
MKL		 3877 xdp->prog_id = mlx5e_xdp_query(dev);
3878 xdp->prog_attached = !!xdp->prog_id;
86994156
RS		 3879 return 0;
3880 default:
3881 return -EINVAL;
3882 }
3883}
3884
80378384
CO		 3885#ifdef CONFIG_NET_POLL_CONTROLLER
3886/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3887 * reenabling interrupts.
3888 */
3889static void mlx5e_netpoll(struct net_device *dev)
3890{
3891 struct mlx5e_priv *priv = netdev_priv(dev);
ff9c852f
SM		 3892 struct mlx5e_channels *chs = &priv->channels;
3893
80378384
CO		 3894 int i;
3895
ff9c852f
SM		 3896 for (i = 0; i < chs->num; i++)
3897 napi_schedule(&chs->c[i]->napi);
80378384
CO		 3898}
3899#endif
3900
e80541ec 3901static const struct net_device_ops mlx5e_netdev_ops = {
f62b8bb8
AV		 3902 .ndo_open = mlx5e_open,
3903 .ndo_stop = mlx5e_close,
3904 .ndo_start_xmit = mlx5e_xmit,
0cf0f6d3 3905 .ndo_setup_tc = mlx5e_setup_tc,
08fb1dac 3906 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3907 .ndo_get_stats64 = mlx5e_get_stats,
3908 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3909 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3910 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3911 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3912 .ndo_set_features = mlx5e_set_features,
7d92d580 3913 .ndo_fix_features = mlx5e_fix_features,
b0eed40e
SM		 3914 .ndo_change_mtu = mlx5e_change_mtu,
3915 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3916 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
706b3583
SM		 3917 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3918 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3919 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3920#ifdef CONFIG_RFS_ACCEL
3921 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3922#endif
3947ca18 3923 .ndo_tx_timeout = mlx5e_tx_timeout,
f4e63525 3924 .ndo_bpf = mlx5e_xdp,
80378384
CO		 3925#ifdef CONFIG_NET_POLL_CONTROLLER
3926 .ndo_poll_controller = mlx5e_netpoll,
3927#endif
e80541ec 3928#ifdef CONFIG_MLX5_ESWITCH
706b3583 3929 /* SRIOV E-Switch NDOs */
b0eed40e
SM		 3930 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3931 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3932 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3933 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3934 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3935 .ndo_get_vf_config = mlx5e_get_vf_config,
3936 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3937 .ndo_get_vf_stats = mlx5e_get_vf_stats,
370bad0f
OG		 3938 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3939 .ndo_get_offload_stats = mlx5e_get_offload_stats,
e80541ec 3940#endif
f62b8bb8
AV		 3941};
3942
3943static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3944{
3945 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 3946 return -EOPNOTSUPP;
f62b8bb8
AV		 3947 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3948 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3949 !MLX5_CAP_ETH(mdev, csum_cap) ||
3950 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3951 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3952 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3953 MLX5_CAP_FLOWTABLE(mdev,
3954 flow_table_properties_nic_receive.max_ft_level)
3955 < 3) {
f62b8bb8
AV		 3956 mlx5_core_warn(mdev,
3957 "Not creating net device, some required device capabilities are missing\n");
9eb78923 3958 return -EOPNOTSUPP;
f62b8bb8 3959 }
66189961
TT		 3960 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3961 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8 3962 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3e432ab6 3963 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
66189961 3964
f62b8bb8
AV		 3965 return 0;
3966}
3967
58d52291
AS		 3968u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3969{
3970 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3971
3972 return bf_buf_size -
3973 sizeof(struct mlx5e_tx_wqe) +
3974 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3975}
3976
d4b6c488 3977void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
85082dba
TT		 3978 int num_channels)
3979{
3980 int i;
3981
3982 for (i = 0; i < len; i++)
3983 indirection_rqt[i] = i % num_channels;
3984}
3985
b797a684
SM		 3986static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3987{
3988 enum pcie_link_width width;
3989 enum pci_bus_speed speed;
3990 int err = 0;
3991
3992 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3993 if (err)
3994 return err;
3995
3996 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3997 return -EINVAL;
3998
3999 switch (speed) {
4000 case PCIE_SPEED_2_5GT:
4001 *pci_bw = 2500 * width;
4002 break;
4003 case PCIE_SPEED_5_0GT:
4004 *pci_bw = 5000 * width;
4005 break;
4006 case PCIE_SPEED_8_0GT:
4007 *pci_bw = 8000 * width;
4008 break;
4009 default:
4010 return -EINVAL;
4011 }
4012
4013 return 0;
4014}
4015
4016static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
4017{
4018 return (link_speed && pci_bw &&
4019 (pci_bw < 40000) && (pci_bw < link_speed));
4020}
4021
0f6e4cf6
EBE		 4022static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
4023{
4024 return !(link_speed && pci_bw &&
4025 (pci_bw <= 16000) && (pci_bw < link_speed));
4026}
4027
0088cbbc
TG		 4028void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4029{
4030 params->tx_cq_moderation.cq_period_mode = cq_period_mode;
4031
4032 params->tx_cq_moderation.pkts =
4033 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4034 params->tx_cq_moderation.usec =
4035 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4036
4037 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4038 params->tx_cq_moderation.usec =
4039 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4040
4041 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4042 params->tx_cq_moderation.cq_period_mode ==
4043 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4044}
4045
9908aa29
TT		 4046void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4047{
0088cbbc 4048 params->rx_cq_moderation.cq_period_mode = cq_period_mode;
9908aa29
TT		 4049
4050 params->rx_cq_moderation.pkts =
4051 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4052 params->rx_cq_moderation.usec =
0088cbbc 4053 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
9908aa29
TT		 4054
4055 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4056 params->rx_cq_moderation.usec =
4057 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
6a9764ef 4058
9a317425
AG		 4059 if (params->rx_dim_enabled) {
4060 switch (cq_period_mode) {
4061 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
4062 params->rx_cq_moderation =
4063 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE);
4064 break;
4065 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
4066 default:
4067 params->rx_cq_moderation =
4068 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE);
4069 }
4070 }
457fcd8a 4071
6a9764ef 4072 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
0088cbbc
TG		 4073 params->rx_cq_moderation.cq_period_mode ==
4074 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29
TT		 4075}
4076
2b029556
SM		 4077u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4078{
4079 int i;
4080
4081 /* The supported periods are organized in ascending order */
4082 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4083 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4084 break;
4085
4086 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4087}
4088
8f493ffd
SM		 4089void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4090 struct mlx5e_params *params,
4091 u16 max_channels)
f62b8bb8 4092{
6a9764ef 4093 u8 cq_period_mode = 0;
b797a684
SM		 4094 u32 link_speed = 0;
4095 u32 pci_bw = 0;
2fc4bfb7 4096
6a9764ef
SM		 4097 params->num_channels = max_channels;
4098 params->num_tc = 1;
2b029556 4099
0f6e4cf6
EBE		 4100 mlx5e_get_max_linkspeed(mdev, &link_speed);
4101 mlx5e_get_pci_bw(mdev, &pci_bw);
4102 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
4103 link_speed, pci_bw);
4104
6a9764ef
SM		 4105 /* SQ */
4106 params->log_sq_size = is_kdump_kernel() ?
b4e029da
KH		 4107 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4108 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 4109
b797a684 4110 /* set CQE compression */
6a9764ef 4111 params->rx_cqe_compress_def = false;
b797a684 4112 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
e53eef63 4113 MLX5_CAP_GEN(mdev, vport_group_manager))
6a9764ef 4114 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
0f6e4cf6 4115
6a9764ef
SM		 4116 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4117
4118 /* RQ */
4119 mlx5e_set_rq_params(mdev, params);
b797a684 4120
6a9764ef 4121 /* HW LRO */
c139dbfd 4122
5426a0b2 4123 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
6a9764ef 4124 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
0f6e4cf6 4125 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
6a9764ef 4126 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
b0d4660b 4127
6a9764ef
SM		 4128 /* CQ moderation params */
4129 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4130 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4131 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
9a317425 4132 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
6a9764ef 4133 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
0088cbbc 4134 mlx5e_set_tx_cq_mode_params(params, cq_period_mode);
9908aa29 4135
6a9764ef
SM		 4136 /* TX inline */
4137 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
fbcb127e 4138 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
a6f402e4 4139
6a9764ef
SM		 4140 /* RSS */
4141 params->rss_hfunc = ETH_RSS_HASH_XOR;
4142 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
d4b6c488 4143 mlx5e_build_default_indir_rqt(params->indirection_rqt,
6a9764ef
SM		 4144 MLX5E_INDIR_RQT_SIZE, max_channels);
4145}
f62b8bb8 4146
6a9764ef
SM		 4147static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4148 struct net_device *netdev,
4149 const struct mlx5e_profile *profile,
4150 void *ppriv)
4151{
4152 struct mlx5e_priv *priv = netdev_priv(netdev);
57afead5 4153
6a9764ef
SM		 4154 priv->mdev = mdev;
4155 priv->netdev = netdev;
4156 priv->profile = profile;
4157 priv->ppriv = ppriv;
79c48764 4158 priv->msglevel = MLX5E_MSG_LEVEL;
c139dbfd 4159 priv->hard_mtu = MLX5E_ETH_HARD_MTU;
2d75b2bc 4160
6a9764ef 4161 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
9908aa29 4162
f62b8bb8
AV		 4163 mutex_init(&priv->state_lock);
4164
4165 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4166 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 4167 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 4168 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4169}
4170
4171static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4172{
4173 struct mlx5e_priv *priv = netdev_priv(netdev);
4174
e1d7d349 4175 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 4176 if (is_zero_ether_addr(netdev->dev_addr) &&
4177 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4178 eth_hw_addr_random(netdev);
4179 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4180 }
f62b8bb8
AV		 4181}
4182
e80541ec 4183#if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
cb67b832
HHZ		 4184static const struct switchdev_ops mlx5e_switchdev_ops = {
4185 .switchdev_port_attr_get = mlx5e_attr_get,
4186};
e80541ec 4187#endif
cb67b832 4188
6bfd390b 4189static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 4190{
4191 struct mlx5e_priv *priv = netdev_priv(netdev);
4192 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 4193 bool fcs_supported;
4194 bool fcs_enabled;
f62b8bb8
AV		 4195
4196 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4197
e80541ec
SM		 4198 netdev->netdev_ops = &mlx5e_netdev_ops;
4199
08fb1dac 4200#ifdef CONFIG_MLX5_CORE_EN_DCB
e80541ec
SM		 4201 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4202 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac 4203#endif
66e49ded 4204
f62b8bb8
AV		 4205 netdev->watchdog_timeo = 15 * HZ;
4206
4207 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4208
12be4b21 4209 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 4210 netdev->vlan_features |= NETIF_F_IP_CSUM;
4211 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4212 netdev->vlan_features |= NETIF_F_GRO;
4213 netdev->vlan_features |= NETIF_F_TSO;
4214 netdev->vlan_features |= NETIF_F_TSO6;
4215 netdev->vlan_features |= NETIF_F_RXCSUM;
4216 netdev->vlan_features |= NETIF_F_RXHASH;
4217
4218 if (!!MLX5_CAP_ETH(mdev, lro_cap))
4219 netdev->vlan_features |= NETIF_F_LRO;
4220
4221 netdev->hw_features = netdev->vlan_features;
e4cf27bd 4222 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 4223 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4224 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4382c7b9 4225 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
f62b8bb8 4226
27299841
GP		 4227 if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4228 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
b3f63c3d 4229 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 4230 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 4231 netdev->hw_enc_features |= NETIF_F_TSO;
4232 netdev->hw_enc_features |= NETIF_F_TSO6;
27299841
GP		 4233 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4234 }
4235
4236 if (mlx5e_vxlan_allowed(mdev)) {
4237 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4238 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4239 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4240 NETIF_F_GSO_UDP_TUNNEL_CSUM;
b49663c8 4241 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 4242 }
4243
27299841
GP		 4244 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4245 netdev->hw_features |= NETIF_F_GSO_GRE |
4246 NETIF_F_GSO_GRE_CSUM;
4247 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4248 NETIF_F_GSO_GRE_CSUM;
4249 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4250 NETIF_F_GSO_GRE_CSUM;
4251 }
4252
94cb1ebb
EBE		 4253 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4254
4255 if (fcs_supported)
4256 netdev->hw_features |= NETIF_F_RXALL;
4257
102722fc
GE		 4258 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4259 netdev->hw_features |= NETIF_F_RXFCS;
4260
f62b8bb8 4261 netdev->features = netdev->hw_features;
6a9764ef 4262 if (!priv->channels.params.lro_en)
f62b8bb8
AV		 4263 netdev->features &= ~NETIF_F_LRO;
4264
94cb1ebb
EBE		 4265 if (fcs_enabled)
4266 netdev->features &= ~NETIF_F_RXALL;
4267
102722fc
GE		 4268 if (!priv->channels.params.scatter_fcs_en)
4269 netdev->features &= ~NETIF_F_RXFCS;
4270
e8f887ac
AV		 4271#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4272 if (FT_CAP(flow_modify_en) &&
4273 FT_CAP(modify_root) &&
4274 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 4275 FT_CAP(flow_table_modify)) {
4276 netdev->hw_features |= NETIF_F_HW_TC;
4277#ifdef CONFIG_RFS_ACCEL
4278 netdev->hw_features |= NETIF_F_NTUPLE;
4279#endif
4280 }
e8f887ac 4281
f62b8bb8 4282 netdev->features |= NETIF_F_HIGHDMA;
7d92d580 4283 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
f62b8bb8
AV		 4284
4285 netdev->priv_flags |= IFF_UNICAST_FLT;
4286
4287 mlx5e_set_netdev_dev_addr(netdev);
cb67b832 4288
e80541ec 4289#if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
a9f7705f 4290 if (MLX5_VPORT_MANAGER(mdev))
cb67b832
HHZ		 4291 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4292#endif
547eede0
IT		 4293
4294 mlx5e_ipsec_build_netdev(priv);
f62b8bb8
AV		 4295}
4296
593cf338
RS		 4297static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4298{
4299 struct mlx5_core_dev *mdev = priv->mdev;
4300 int err;
4301
4302 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4303 if (err) {
4304 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4305 priv->q_counter = 0;
4306 }
4307}
4308
4309static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4310{
4311 if (!priv->q_counter)
4312 return;
4313
4314 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4315}
4316
6bfd390b
HHZ		 4317static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4318 struct net_device *netdev,
127ea380
HHZ		 4319 const struct mlx5e_profile *profile,
4320 void *ppriv)
6bfd390b
HHZ		 4321{
4322 struct mlx5e_priv *priv = netdev_priv(netdev);
547eede0 4323 int err;
6bfd390b 4324
127ea380 4325 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
547eede0
IT		 4326 err = mlx5e_ipsec_init(priv);
4327 if (err)
4328 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
6bfd390b
HHZ		 4329 mlx5e_build_nic_netdev(netdev);
4330 mlx5e_vxlan_init(priv);
4331}
4332
4333static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4334{
547eede0 4335 mlx5e_ipsec_cleanup(priv);
6bfd390b
HHZ		 4336 mlx5e_vxlan_cleanup(priv);
4337}
4338
4339static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4340{
4341 struct mlx5_core_dev *mdev = priv->mdev;
4342 int err;
6bfd390b 4343
8f493ffd
SM		 4344 err = mlx5e_create_indirect_rqt(priv);
4345 if (err)
6bfd390b 4346 return err;
6bfd390b
HHZ		 4347
4348 err = mlx5e_create_direct_rqts(priv);
8f493ffd 4349 if (err)
6bfd390b 4350 goto err_destroy_indirect_rqts;
6bfd390b
HHZ		 4351
4352 err = mlx5e_create_indirect_tirs(priv);
8f493ffd 4353 if (err)
6bfd390b 4354 goto err_destroy_direct_rqts;
6bfd390b
HHZ		 4355
4356 err = mlx5e_create_direct_tirs(priv);
8f493ffd 4357 if (err)
6bfd390b 4358 goto err_destroy_indirect_tirs;
6bfd390b
HHZ		 4359
4360 err = mlx5e_create_flow_steering(priv);
4361 if (err) {
4362 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4363 goto err_destroy_direct_tirs;
4364 }
4365
4366 err = mlx5e_tc_init(priv);
4367 if (err)
4368 goto err_destroy_flow_steering;
4369
4370 return 0;
4371
4372err_destroy_flow_steering:
4373 mlx5e_destroy_flow_steering(priv);
4374err_destroy_direct_tirs:
4375 mlx5e_destroy_direct_tirs(priv);
4376err_destroy_indirect_tirs:
4377 mlx5e_destroy_indirect_tirs(priv);
4378err_destroy_direct_rqts:
8f493ffd 4379 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4380err_destroy_indirect_rqts:
4381 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4382 return err;
4383}
4384
4385static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4386{
6bfd390b
HHZ		 4387 mlx5e_tc_cleanup(priv);
4388 mlx5e_destroy_flow_steering(priv);
4389 mlx5e_destroy_direct_tirs(priv);
4390 mlx5e_destroy_indirect_tirs(priv);
8f493ffd 4391 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4392 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4393}
4394
4395static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4396{
4397 int err;
4398
4399 err = mlx5e_create_tises(priv);
4400 if (err) {
4401 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4402 return err;
4403 }
4404
4405#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 4406 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 4407#endif
4408 return 0;
4409}
4410
4411static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4412{
4413 struct net_device *netdev = priv->netdev;
4414 struct mlx5_core_dev *mdev = priv->mdev;
2c3b5bee
SM		 4415 u16 max_mtu;
4416
4417 mlx5e_init_l2_addr(priv);
4418
63bfd399
EBE		 4419 /* Marking the link as currently not needed by the Driver */
4420 if (!netif_running(netdev))
4421 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4422
2c3b5bee
SM		 4423 /* MTU range: 68 - hw-specific max */
4424 netdev->min_mtu = ETH_MIN_MTU;
4425 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
c139dbfd 4426 netdev->max_mtu = MLX5E_HW2SW_MTU(priv, max_mtu);
2c3b5bee 4427 mlx5e_set_dev_port_mtu(priv);
6bfd390b 4428
7907f23a
AH		 4429 mlx5_lag_add(mdev, netdev);
4430
6bfd390b 4431 mlx5e_enable_async_events(priv);
127ea380 4432
a9f7705f 4433 if (MLX5_VPORT_MANAGER(priv->mdev))
1d447a39 4434 mlx5e_register_vport_reps(priv);
2c3b5bee 4435
610e89e0
SM		 4436 if (netdev->reg_state != NETREG_REGISTERED)
4437 return;
2a5e7a13
HN		 4438#ifdef CONFIG_MLX5_CORE_EN_DCB
4439 mlx5e_dcbnl_init_app(priv);
4440#endif
610e89e0
SM		 4441 /* Device already registered: sync netdev system state */
4442 if (mlx5e_vxlan_allowed(mdev)) {
4443 rtnl_lock();
4444 udp_tunnel_get_rx_info(netdev);
4445 rtnl_unlock();
4446 }
4447
4448 queue_work(priv->wq, &priv->set_rx_mode_work);
2c3b5bee
SM		 4449
4450 rtnl_lock();
4451 if (netif_running(netdev))
4452 mlx5e_open(netdev);
4453 netif_device_attach(netdev);
4454 rtnl_unlock();
6bfd390b
HHZ		 4455}
4456
4457static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4458{
3deef8ce 4459 struct mlx5_core_dev *mdev = priv->mdev;
3deef8ce 4460
2a5e7a13
HN		 4461#ifdef CONFIG_MLX5_CORE_EN_DCB
4462 if (priv->netdev->reg_state == NETREG_REGISTERED)
4463 mlx5e_dcbnl_delete_app(priv);
4464#endif
4465
2c3b5bee
SM		 4466 rtnl_lock();
4467 if (netif_running(priv->netdev))
4468 mlx5e_close(priv->netdev);
4469 netif_device_detach(priv->netdev);
4470 rtnl_unlock();
4471
6bfd390b 4472 queue_work(priv->wq, &priv->set_rx_mode_work);
1d447a39 4473
a9f7705f 4474 if (MLX5_VPORT_MANAGER(priv->mdev))
1d447a39
SM		 4475 mlx5e_unregister_vport_reps(priv);
4476
6bfd390b 4477 mlx5e_disable_async_events(priv);
3deef8ce 4478 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 4479}
4480
4481static const struct mlx5e_profile mlx5e_nic_profile = {
4482 .init = mlx5e_nic_init,
4483 .cleanup = mlx5e_nic_cleanup,
4484 .init_rx = mlx5e_init_nic_rx,
4485 .cleanup_rx = mlx5e_cleanup_nic_rx,
4486 .init_tx = mlx5e_init_nic_tx,
4487 .cleanup_tx = mlx5e_cleanup_nic_tx,
4488 .enable = mlx5e_nic_enable,
4489 .disable = mlx5e_nic_disable,
3834a5e6 4490 .update_stats = mlx5e_update_ndo_stats,
6bfd390b 4491 .max_nch = mlx5e_get_max_num_channels,
7ca42c80 4492 .update_carrier = mlx5e_update_carrier,
20fd0c19
SM		 4493 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4494 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
6bfd390b
HHZ		 4495 .max_tc = MLX5E_MAX_NUM_TC,
4496};
4497
2c3b5bee
SM		 4498/* mlx5e generic netdev management API (move to en_common.c) */
4499
26e59d80
MHY		 4500struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4501 const struct mlx5e_profile *profile,
4502 void *ppriv)
f62b8bb8 4503{
26e59d80 4504 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 4505 struct net_device *netdev;
4506 struct mlx5e_priv *priv;
f62b8bb8 4507
08fb1dac 4508 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 4509 nch * profile->max_tc,
08fb1dac 4510 nch);
f62b8bb8
AV		 4511 if (!netdev) {
4512 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4513 return NULL;
4514 }
4515
be4891af
SM		 4516#ifdef CONFIG_RFS_ACCEL
4517 netdev->rx_cpu_rmap = mdev->rmap;
4518#endif
4519
127ea380 4520 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 4521
4522 netif_carrier_off(netdev);
4523
4524 priv = netdev_priv(netdev);
4525
7bb29755
MF		 4526 priv->wq = create_singlethread_workqueue("mlx5e");
4527 if (!priv->wq)
26e59d80
MHY		 4528 goto err_cleanup_nic;
4529
4530 return netdev;
4531
4532err_cleanup_nic:
31ac9338
OG		 4533 if (profile->cleanup)
4534 profile->cleanup(priv);
26e59d80
MHY		 4535 free_netdev(netdev);
4536
4537 return NULL;
4538}
4539
2c3b5bee 4540int mlx5e_attach_netdev(struct mlx5e_priv *priv)
26e59d80 4541{
2c3b5bee 4542 struct mlx5_core_dev *mdev = priv->mdev;
26e59d80 4543 const struct mlx5e_profile *profile;
26e59d80
MHY		 4544 int err;
4545
26e59d80
MHY		 4546 profile = priv->profile;
4547 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 4548
6bfd390b
HHZ		 4549 err = profile->init_tx(priv);
4550 if (err)
ec8b9981 4551 goto out;
5c50368f 4552
a43b25da 4553 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
5c50368f
AS		 4554 if (err) {
4555 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 4556 goto err_cleanup_tx;
5c50368f
AS		 4557 }
4558
6bfd390b
HHZ		 4559 err = profile->init_rx(priv);
4560 if (err)
5c50368f 4561 goto err_close_drop_rq;
5c50368f 4562
593cf338
RS		 4563 mlx5e_create_q_counter(priv);
4564
6bfd390b
HHZ		 4565 if (profile->enable)
4566 profile->enable(priv);
f62b8bb8 4567
26e59d80 4568 return 0;
5c50368f
AS		 4569
4570err_close_drop_rq:
a43b25da 4571 mlx5e_close_drop_rq(&priv->drop_rq);
5c50368f 4572
6bfd390b
HHZ		 4573err_cleanup_tx:
4574 profile->cleanup_tx(priv);
5c50368f 4575
26e59d80
MHY		 4576out:
4577 return err;
f62b8bb8
AV		 4578}
4579
2c3b5bee 4580void mlx5e_detach_netdev(struct mlx5e_priv *priv)
26e59d80 4581{
26e59d80
MHY		 4582 const struct mlx5e_profile *profile = priv->profile;
4583
4584 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80 4585
37f304d1
SM		 4586 if (profile->disable)
4587 profile->disable(priv);
4588 flush_workqueue(priv->wq);
4589
26e59d80
MHY		 4590 mlx5e_destroy_q_counter(priv);
4591 profile->cleanup_rx(priv);
a43b25da 4592 mlx5e_close_drop_rq(&priv->drop_rq);
26e59d80 4593 profile->cleanup_tx(priv);
26e59d80
MHY		 4594 cancel_delayed_work_sync(&priv->update_stats_work);
4595}
4596
2c3b5bee
SM		 4597void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4598{
4599 const struct mlx5e_profile *profile = priv->profile;
4600 struct net_device *netdev = priv->netdev;
4601
4602 destroy_workqueue(priv->wq);
4603 if (profile->cleanup)
4604 profile->cleanup(priv);
4605 free_netdev(netdev);
4606}
4607
26e59d80
MHY		 4608/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4609 * hardware contexts and to connect it to the current netdev.
4610 */
4611static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4612{
4613 struct mlx5e_priv *priv = vpriv;
4614 struct net_device *netdev = priv->netdev;
4615 int err;
4616
4617 if (netif_device_present(netdev))
4618 return 0;
4619
4620 err = mlx5e_create_mdev_resources(mdev);
4621 if (err)
4622 return err;
4623
2c3b5bee 4624 err = mlx5e_attach_netdev(priv);
26e59d80
MHY		 4625 if (err) {
4626 mlx5e_destroy_mdev_resources(mdev);
4627 return err;
4628 }
4629
4630 return 0;
4631}
4632
4633static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4634{
4635 struct mlx5e_priv *priv = vpriv;
4636 struct net_device *netdev = priv->netdev;
4637
4638 if (!netif_device_present(netdev))
4639 return;
4640
2c3b5bee 4641 mlx5e_detach_netdev(priv);
26e59d80
MHY		 4642 mlx5e_destroy_mdev_resources(mdev);
4643}
4644
b50d292b
HHZ		 4645static void *mlx5e_add(struct mlx5_core_dev *mdev)
4646{
07c9f1e5
SM		 4647 struct net_device *netdev;
4648 void *rpriv = NULL;
26e59d80 4649 void *priv;
26e59d80 4650 int err;
b50d292b 4651
26e59d80
MHY		 4652 err = mlx5e_check_required_hca_cap(mdev);
4653 if (err)
b50d292b
HHZ		 4654 return NULL;
4655
e80541ec 4656#ifdef CONFIG_MLX5_ESWITCH
a9f7705f 4657 if (MLX5_VPORT_MANAGER(mdev)) {
07c9f1e5 4658 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
1d447a39 4659 if (!rpriv) {
07c9f1e5 4660 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
1d447a39
SM		 4661 return NULL;
4662 }
1d447a39 4663 }
e80541ec 4664#endif
127ea380 4665
1d447a39 4666 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
26e59d80
MHY		 4667 if (!netdev) {
4668 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
07c9f1e5 4669 goto err_free_rpriv;
26e59d80
MHY		 4670 }
4671
4672 priv = netdev_priv(netdev);
4673
4674 err = mlx5e_attach(mdev, priv);
4675 if (err) {
4676 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4677 goto err_destroy_netdev;
4678 }
4679
4680 err = register_netdev(netdev);
4681 if (err) {
4682 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4683 goto err_detach;
b50d292b 4684 }
26e59d80 4685
2a5e7a13
HN		 4686#ifdef CONFIG_MLX5_CORE_EN_DCB
4687 mlx5e_dcbnl_init_app(priv);
4688#endif
26e59d80
MHY		 4689 return priv;
4690
4691err_detach:
4692 mlx5e_detach(mdev, priv);
26e59d80 4693err_destroy_netdev:
2c3b5bee 4694 mlx5e_destroy_netdev(priv);
07c9f1e5 4695err_free_rpriv:
1d447a39 4696 kfree(rpriv);
26e59d80 4697 return NULL;
b50d292b
HHZ		 4698}
4699
b50d292b
HHZ		 4700static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4701{
4702 struct mlx5e_priv *priv = vpriv;
1d447a39 4703 void *ppriv = priv->ppriv;
127ea380 4704
2a5e7a13
HN		 4705#ifdef CONFIG_MLX5_CORE_EN_DCB
4706 mlx5e_dcbnl_delete_app(priv);
4707#endif
5e1e93c7 4708 unregister_netdev(priv->netdev);
26e59d80 4709 mlx5e_detach(mdev, vpriv);
2c3b5bee 4710 mlx5e_destroy_netdev(priv);
1d447a39 4711 kfree(ppriv);
b50d292b
HHZ		 4712}
4713
f62b8bb8
AV		 4714static void *mlx5e_get_netdev(void *vpriv)
4715{
4716 struct mlx5e_priv *priv = vpriv;
4717
4718 return priv->netdev;
4719}
4720
4721static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4722 .add = mlx5e_add,
4723 .remove = mlx5e_remove,
26e59d80
MHY		 4724 .attach = mlx5e_attach,
4725 .detach = mlx5e_detach,
f62b8bb8
AV		 4726 .event = mlx5e_async_event,
4727 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4728 .get_dev = mlx5e_get_netdev,
4729};
4730
4731void mlx5e_init(void)
4732{
2ac9cfe7 4733 mlx5e_ipsec_build_inverse_table();
665bc539 4734 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4735 mlx5_register_interface(&mlx5e_interface);
4736}
4737
4738void mlx5e_cleanup(void)
4739{
4740 mlx5_unregister_interface(&mlx5e_interface);
4741}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git