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f62b8bb8 | 1 | /* |
b3f63c3d | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
e8f887ac | 33 | #include <net/tc_act/tc_gact.h> |
86d722ad | 34 | #include <linux/mlx5/fs.h> |
b3f63c3d | 35 | #include <net/vxlan.h> |
e3cfc7e6 | 36 | #include <net/geneve.h> |
86994156 | 37 | #include <linux/bpf.h> |
288eca60 | 38 | #include <linux/debugfs.h> |
4b89251d | 39 | #include <linux/if_bridge.h> |
7d714ff1 | 40 | #include <linux/filter.h> |
a9ca9f9c | 41 | #include <net/page_pool/types.h> |
9adafe2b | 42 | #include <net/pkt_sched.h> |
39d6443c | 43 | #include <net/xdp_sock_drv.h> |
1d447a39 | 44 | #include "eswitch.h" |
f62b8bb8 | 45 | #include "en.h" |
542578c6 | 46 | #include "en/txrx.h" |
e8f887ac | 47 | #include "en_tc.h" |
1d447a39 | 48 | #include "en_rep.h" |
547eede0 | 49 | #include "en_accel/ipsec.h" |
8ff0ac5b | 50 | #include "en_accel/macsec.h" |
e3cfc7e6 | 51 | #include "en_accel/en_accel.h" |
943aa7bd | 52 | #include "en_accel/ktls.h" |
358aa5ce | 53 | #include "lib/vxlan.h" |
6dbc80ca | 54 | #include "lib/clock.h" |
2c81bfd5 | 55 | #include "en/port.h" |
159d2131 | 56 | #include "en/xdp.h" |
f2f3df55 | 57 | #include "lib/eq.h" |
5c7e8bbb | 58 | #include "en/monitor_stats.h" |
4edc17fd | 59 | #include "en/health.h" |
9a22d5d8 | 60 | #include "en/params.h" |
1742b3d5 | 61 | #include "en/xsk/pool.h" |
db05815b MM |
62 | #include "en/xsk/setup.h" |
63 | #include "en/xsk/rx.h" | |
64 | #include "en/xsk/tx.h" | |
cef35af3 | 65 | #include "en/hv_vhca_stats.h" |
c6acd629 | 66 | #include "en/devlink.h" |
71c6eaeb | 67 | #include "lib/mlx5.h" |
145e5637 | 68 | #include "en/ptp.h" |
462b0059 | 69 | #include "en/htb.h" |
214baf22 | 70 | #include "qos.h" |
70038b73 | 71 | #include "en/trap.h" |
f62b8bb8 | 72 | |
6470d2e7 | 73 | bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift, |
168723c1 | 74 | enum mlx5e_mpwrq_umr_mode umr_mode) |
2fc4bfb7 | 75 | { |
e5a3cc83 MM |
76 | u16 umr_wqebbs, max_wqebbs; |
77 | bool striding_rq_umr; | |
ea3886ca | 78 | |
c27bd171 AL |
79 | striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && MLX5_CAP_GEN(mdev, umr_ptr_rlky) && |
80 | MLX5_CAP_ETH(mdev, reg_umr_sq); | |
ea3886ca TT |
81 | if (!striding_rq_umr) |
82 | return false; | |
e5a3cc83 | 83 | |
168723c1 | 84 | umr_wqebbs = mlx5e_mpwrq_umr_wqebbs(mdev, page_shift, umr_mode); |
e5a3cc83 MM |
85 | max_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev); |
86 | /* Sanity check; should never happen, because mlx5e_mpwrq_umr_wqebbs is | |
87 | * calculated from mlx5e_get_max_sq_aligned_wqebbs. | |
88 | */ | |
89 | if (WARN_ON(umr_wqebbs > max_wqebbs)) | |
ea3886ca | 90 | return false; |
e5a3cc83 | 91 | |
ea3886ca | 92 | return true; |
2fc4bfb7 SM |
93 | } |
94 | ||
b36cdb42 | 95 | void mlx5e_update_carrier(struct mlx5e_priv *priv) |
f62b8bb8 AV |
96 | { |
97 | struct mlx5_core_dev *mdev = priv->mdev; | |
98 | u8 port_state; | |
490dceca | 99 | bool up; |
f62b8bb8 AV |
100 | |
101 | port_state = mlx5_query_vport_state(mdev, | |
cc9c82a8 | 102 | MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT, |
e53eef63 | 103 | 0); |
f62b8bb8 | 104 | |
490dceca JK |
105 | up = port_state == VPORT_STATE_UP; |
106 | if (up == netif_carrier_ok(priv->netdev)) | |
107 | netif_carrier_event(priv->netdev); | |
108 | if (up) { | |
87424ad5 | 109 | netdev_info(priv->netdev, "Link up\n"); |
f62b8bb8 | 110 | netif_carrier_on(priv->netdev); |
87424ad5 SD |
111 | } else { |
112 | netdev_info(priv->netdev, "Link down\n"); | |
f62b8bb8 | 113 | netif_carrier_off(priv->netdev); |
87424ad5 | 114 | } |
f62b8bb8 AV |
115 | } |
116 | ||
117 | static void mlx5e_update_carrier_work(struct work_struct *work) | |
118 | { | |
119 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, | |
120 | update_carrier_work); | |
121 | ||
122 | mutex_lock(&priv->state_lock); | |
123 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
7ca42c80 ES |
124 | if (priv->profile->update_carrier) |
125 | priv->profile->update_carrier(priv); | |
f62b8bb8 AV |
126 | mutex_unlock(&priv->state_lock); |
127 | } | |
128 | ||
303211b4 | 129 | static void mlx5e_update_stats_work(struct work_struct *work) |
f62b8bb8 | 130 | { |
cdeef2b1 | 131 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, |
f62b8bb8 | 132 | update_stats_work); |
ed56c519 | 133 | |
f62b8bb8 | 134 | mutex_lock(&priv->state_lock); |
ed56c519 | 135 | priv->profile->update_stats(priv); |
f62b8bb8 AV |
136 | mutex_unlock(&priv->state_lock); |
137 | } | |
138 | ||
cdeef2b1 SM |
139 | void mlx5e_queue_update_stats(struct mlx5e_priv *priv) |
140 | { | |
141 | if (!priv->profile->update_stats) | |
142 | return; | |
143 | ||
144 | if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state))) | |
145 | return; | |
146 | ||
147 | queue_work(priv->wq, &priv->update_stats_work); | |
148 | } | |
149 | ||
7cffaddd | 150 | static int async_event(struct notifier_block *nb, unsigned long event, void *data) |
f62b8bb8 | 151 | { |
7cffaddd SM |
152 | struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb); |
153 | struct mlx5_eqe *eqe = data; | |
daa21560 | 154 | |
7cffaddd SM |
155 | if (event != MLX5_EVENT_TYPE_PORT_CHANGE) |
156 | return NOTIFY_DONE; | |
daa21560 | 157 | |
7cffaddd SM |
158 | switch (eqe->sub_type) { |
159 | case MLX5_PORT_CHANGE_SUBTYPE_DOWN: | |
160 | case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: | |
7bb29755 | 161 | queue_work(priv->wq, &priv->update_carrier_work); |
f62b8bb8 | 162 | break; |
f62b8bb8 | 163 | default: |
7cffaddd | 164 | return NOTIFY_DONE; |
f62b8bb8 | 165 | } |
7cffaddd SM |
166 | |
167 | return NOTIFY_OK; | |
f62b8bb8 AV |
168 | } |
169 | ||
f62b8bb8 AV |
170 | static void mlx5e_enable_async_events(struct mlx5e_priv *priv) |
171 | { | |
7cffaddd SM |
172 | priv->events_nb.notifier_call = async_event; |
173 | mlx5_notifier_register(priv->mdev, &priv->events_nb); | |
f62b8bb8 AV |
174 | } |
175 | ||
176 | static void mlx5e_disable_async_events(struct mlx5e_priv *priv) | |
177 | { | |
7cffaddd | 178 | mlx5_notifier_unregister(priv->mdev, &priv->events_nb); |
f62b8bb8 AV |
179 | } |
180 | ||
70038b73 AL |
181 | static int blocking_event(struct notifier_block *nb, unsigned long event, void *data) |
182 | { | |
183 | struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb); | |
3f26a315 | 184 | struct mlx5_devlink_trap_event_ctx *trap_event_ctx = data; |
70038b73 AL |
185 | int err; |
186 | ||
187 | switch (event) { | |
188 | case MLX5_DRIVER_EVENT_TYPE_TRAP: | |
3f26a315 JP |
189 | err = mlx5e_handle_trap_event(priv, trap_event_ctx->trap); |
190 | if (err) { | |
191 | trap_event_ctx->err = err; | |
192 | return NOTIFY_BAD; | |
193 | } | |
70038b73 AL |
194 | break; |
195 | default: | |
3f26a315 | 196 | return NOTIFY_DONE; |
70038b73 | 197 | } |
3f26a315 | 198 | return NOTIFY_OK; |
70038b73 AL |
199 | } |
200 | ||
201 | static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv) | |
202 | { | |
203 | priv->blocking_events_nb.notifier_call = blocking_event; | |
204 | mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb); | |
205 | } | |
206 | ||
207 | static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv) | |
208 | { | |
209 | mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb); | |
210 | } | |
211 | ||
168723c1 MM |
212 | static u16 mlx5e_mpwrq_umr_octowords(u32 entries, enum mlx5e_mpwrq_umr_mode umr_mode) |
213 | { | |
9f123f74 | 214 | u8 umr_entry_size = mlx5e_mpwrq_umr_entry_size(umr_mode); |
3e874cb1 | 215 | u32 sz; |
9f123f74 | 216 | |
02648b4b | 217 | sz = ALIGN(entries * umr_entry_size, MLX5_UMR_FLEX_ALIGNMENT); |
9f123f74 | 218 | |
3e874cb1 | 219 | return sz / MLX5_OCTWORD; |
168723c1 MM |
220 | } |
221 | ||
31391048 SM |
222 | static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, |
223 | struct mlx5e_icosq *sq, | |
b8a98a4c | 224 | struct mlx5e_umr_wqe *wqe) |
7e426671 TT |
225 | { |
226 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
227 | struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl; | |
6470d2e7 | 228 | u16 octowords; |
997ce6af MM |
229 | u8 ds_cnt; |
230 | ||
6470d2e7 | 231 | ds_cnt = DIV_ROUND_UP(mlx5e_mpwrq_umr_wqe_sz(rq->mdev, rq->mpwqe.page_shift, |
168723c1 | 232 | rq->mpwqe.umr_mode), |
997ce6af | 233 | MLX5_SEND_WQE_DS); |
7e426671 TT |
234 | |
235 | cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) | | |
236 | ds_cnt); | |
ecc7ad2e | 237 | cseg->umr_mkey = rq->mpwqe.umr_mkey_be; |
7e426671 | 238 | |
ea3886ca | 239 | ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE; |
168723c1 | 240 | octowords = mlx5e_mpwrq_umr_octowords(rq->mpwqe.pages_per_wqe, rq->mpwqe.umr_mode); |
6470d2e7 | 241 | ucseg->xlt_octowords = cpu_to_be16(octowords); |
7e426671 | 242 | ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); |
7e426671 TT |
243 | } |
244 | ||
e5ca8fb0 BBI |
245 | static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node) |
246 | { | |
247 | rq->mpwqe.shampo = kvzalloc_node(sizeof(*rq->mpwqe.shampo), | |
248 | GFP_KERNEL, node); | |
249 | if (!rq->mpwqe.shampo) | |
250 | return -ENOMEM; | |
251 | return 0; | |
252 | } | |
253 | ||
254 | static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq) | |
255 | { | |
256 | kvfree(rq->mpwqe.shampo); | |
257 | } | |
258 | ||
259 | static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node) | |
260 | { | |
261 | struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo; | |
262 | ||
263 | shampo->bitmap = bitmap_zalloc_node(shampo->hd_per_wq, GFP_KERNEL, | |
264 | node); | |
e5ca8fb0 BBI |
265 | shampo->info = kvzalloc_node(array_size(shampo->hd_per_wq, |
266 | sizeof(*shampo->info)), | |
267 | GFP_KERNEL, node); | |
ca6ef9f0 DT |
268 | shampo->pages = kvzalloc_node(array_size(shampo->hd_per_wq, |
269 | sizeof(*shampo->pages)), | |
270 | GFP_KERNEL, node); | |
271 | if (!shampo->bitmap || !shampo->info || !shampo->pages) | |
272 | goto err_nomem; | |
273 | ||
e5ca8fb0 | 274 | return 0; |
ca6ef9f0 DT |
275 | |
276 | err_nomem: | |
277 | kvfree(shampo->info); | |
278 | kvfree(shampo->bitmap); | |
279 | kvfree(shampo->pages); | |
280 | ||
281 | return -ENOMEM; | |
e5ca8fb0 BBI |
282 | } |
283 | ||
284 | static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq) | |
285 | { | |
286 | kvfree(rq->mpwqe.shampo->bitmap); | |
287 | kvfree(rq->mpwqe.shampo->info); | |
ca6ef9f0 | 288 | kvfree(rq->mpwqe.shampo->pages); |
e5ca8fb0 BBI |
289 | } |
290 | ||
ea886000 | 291 | static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node) |
7e426671 | 292 | { |
422d4c40 | 293 | int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq); |
258e655c | 294 | size_t alloc_size; |
7e426671 | 295 | |
d39092ca | 296 | alloc_size = array_size(wq_sz, struct_size(rq->mpwqe.info, |
6f574284 | 297 | alloc_units.frag_pages, |
997ce6af | 298 | rq->mpwqe.pages_per_wqe)); |
258e655c MM |
299 | |
300 | rq->mpwqe.info = kvzalloc_node(alloc_size, GFP_KERNEL, node); | |
21c59685 | 301 | if (!rq->mpwqe.info) |
ea3886ca | 302 | return -ENOMEM; |
7e426671 | 303 | |
4c2a1323 DT |
304 | /* For deferred page release (release right before alloc), make sure |
305 | * that on first round release is not called. | |
306 | */ | |
307 | for (int i = 0; i < wq_sz; i++) { | |
308 | struct mlx5e_mpw_info *wi = mlx5e_get_mpw_info(rq, i); | |
309 | ||
310 | bitmap_fill(wi->skip_release_bitmap, rq->mpwqe.pages_per_wqe); | |
311 | } | |
312 | ||
ea886000 | 313 | mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe); |
7e426671 TT |
314 | |
315 | return 0; | |
7e426671 TT |
316 | } |
317 | ||
168723c1 MM |
318 | |
319 | static u8 mlx5e_mpwrq_access_mode(enum mlx5e_mpwrq_umr_mode umr_mode) | |
320 | { | |
321 | switch (umr_mode) { | |
322 | case MLX5E_MPWRQ_UMR_MODE_ALIGNED: | |
323 | return MLX5_MKC_ACCESS_MODE_MTT; | |
324 | case MLX5E_MPWRQ_UMR_MODE_UNALIGNED: | |
325 | return MLX5_MKC_ACCESS_MODE_KSM; | |
13921345 MM |
326 | case MLX5E_MPWRQ_UMR_MODE_OVERSIZED: |
327 | return MLX5_MKC_ACCESS_MODE_KLMS; | |
c2c9e31d MM |
328 | case MLX5E_MPWRQ_UMR_MODE_TRIPLE: |
329 | return MLX5_MKC_ACCESS_MODE_KSM; | |
168723c1 MM |
330 | } |
331 | WARN_ONCE(1, "MPWRQ UMR mode %d is not known\n", umr_mode); | |
332 | return 0; | |
333 | } | |
334 | ||
6470d2e7 MM |
335 | static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev, |
336 | u32 npages, u8 page_shift, u32 *umr_mkey, | |
168723c1 | 337 | dma_addr_t filler_addr, |
13921345 MM |
338 | enum mlx5e_mpwrq_umr_mode umr_mode, |
339 | u32 xsk_chunk_size) | |
3608ae77 | 340 | { |
c3c94023 | 341 | struct mlx5_mtt *mtt; |
6470d2e7 | 342 | struct mlx5_ksm *ksm; |
13921345 | 343 | struct mlx5_klm *klm; |
6470d2e7 | 344 | u32 octwords; |
c3c94023 | 345 | int inlen; |
3608ae77 TT |
346 | void *mkc; |
347 | u32 *in; | |
348 | int err; | |
c3c94023 AL |
349 | int i; |
350 | ||
c2c9e31d MM |
351 | if ((umr_mode == MLX5E_MPWRQ_UMR_MODE_UNALIGNED || |
352 | umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE) && | |
168723c1 | 353 | !MLX5_CAP_GEN(mdev, fixed_buffer_size)) { |
6470d2e7 MM |
354 | mlx5_core_warn(mdev, "Unaligned AF_XDP requires fixed_buffer_size capability\n"); |
355 | return -EINVAL; | |
356 | } | |
357 | ||
168723c1 MM |
358 | octwords = mlx5e_mpwrq_umr_octowords(npages, umr_mode); |
359 | ||
6470d2e7 | 360 | inlen = MLX5_FLEXIBLE_INLEN(mdev, MLX5_ST_SZ_BYTES(create_mkey_in), |
168723c1 | 361 | MLX5_OCTWORD, octwords); |
6470d2e7 MM |
362 | if (inlen < 0) |
363 | return inlen; | |
3608ae77 | 364 | |
1b9a07ee | 365 | in = kvzalloc(inlen, GFP_KERNEL); |
3608ae77 TT |
366 | if (!in) |
367 | return -ENOMEM; | |
368 | ||
369 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
370 | ||
3608ae77 TT |
371 | MLX5_SET(mkc, mkc, free, 1); |
372 | MLX5_SET(mkc, mkc, umr_en, 1); | |
373 | MLX5_SET(mkc, mkc, lw, 1); | |
374 | MLX5_SET(mkc, mkc, lr, 1); | |
168723c1 | 375 | MLX5_SET(mkc, mkc, access_mode_1_0, mlx5e_mpwrq_access_mode(umr_mode)); |
17347d54 | 376 | mlx5e_mkey_set_relaxed_ordering(mdev, mkc); |
3608ae77 | 377 | MLX5_SET(mkc, mkc, qpn, 0xffffff); |
c276aae8 | 378 | MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn); |
ec8b9981 | 379 | MLX5_SET64(mkc, mkc, len, npages << page_shift); |
6470d2e7 | 380 | MLX5_SET(mkc, mkc, translations_octword_size, octwords); |
c2c9e31d MM |
381 | if (umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE) |
382 | MLX5_SET(mkc, mkc, log_page_size, page_shift - 2); | |
383 | else if (umr_mode != MLX5E_MPWRQ_UMR_MODE_OVERSIZED) | |
13921345 | 384 | MLX5_SET(mkc, mkc, log_page_size, page_shift); |
6470d2e7 | 385 | MLX5_SET(create_mkey_in, in, translations_octword_actual_size, octwords); |
c3c94023 AL |
386 | |
387 | /* Initialize the mkey with all MTTs pointing to a default | |
388 | * page (filler_addr). When the channels are activated, UMR | |
389 | * WQEs will redirect the RX WQEs to the actual memory from | |
390 | * the RQ's pool, while the gaps (wqe_overflow) remain mapped | |
391 | * to the default page. | |
392 | */ | |
168723c1 | 393 | switch (umr_mode) { |
13921345 MM |
394 | case MLX5E_MPWRQ_UMR_MODE_OVERSIZED: |
395 | klm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); | |
396 | for (i = 0; i < npages; i++) { | |
397 | klm[i << 1] = (struct mlx5_klm) { | |
398 | .va = cpu_to_be64(filler_addr), | |
399 | .bcount = cpu_to_be32(xsk_chunk_size), | |
400 | .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey), | |
401 | }; | |
402 | klm[(i << 1) + 1] = (struct mlx5_klm) { | |
403 | .va = cpu_to_be64(filler_addr), | |
404 | .bcount = cpu_to_be32((1 << page_shift) - xsk_chunk_size), | |
405 | .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey), | |
406 | }; | |
407 | } | |
408 | break; | |
168723c1 | 409 | case MLX5E_MPWRQ_UMR_MODE_UNALIGNED: |
6470d2e7 MM |
410 | ksm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); |
411 | for (i = 0; i < npages; i++) | |
412 | ksm[i] = (struct mlx5_ksm) { | |
413 | .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey), | |
414 | .va = cpu_to_be64(filler_addr), | |
415 | }; | |
168723c1 MM |
416 | break; |
417 | case MLX5E_MPWRQ_UMR_MODE_ALIGNED: | |
6470d2e7 MM |
418 | mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); |
419 | for (i = 0; i < npages; i++) | |
420 | mtt[i] = (struct mlx5_mtt) { | |
421 | .ptag = cpu_to_be64(filler_addr), | |
422 | }; | |
168723c1 | 423 | break; |
c2c9e31d MM |
424 | case MLX5E_MPWRQ_UMR_MODE_TRIPLE: |
425 | ksm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); | |
426 | for (i = 0; i < npages * 4; i++) { | |
427 | ksm[i] = (struct mlx5_ksm) { | |
428 | .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey), | |
429 | .va = cpu_to_be64(filler_addr), | |
430 | }; | |
431 | } | |
432 | break; | |
6470d2e7 | 433 | } |
3608ae77 | 434 | |
ec8b9981 | 435 | err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen); |
3608ae77 TT |
436 | |
437 | kvfree(in); | |
438 | return err; | |
439 | } | |
440 | ||
e5ca8fb0 BBI |
441 | static int mlx5e_create_umr_klm_mkey(struct mlx5_core_dev *mdev, |
442 | u64 nentries, | |
573bce9e | 443 | u32 *umr_mkey) |
e5ca8fb0 BBI |
444 | { |
445 | int inlen; | |
446 | void *mkc; | |
447 | u32 *in; | |
448 | int err; | |
449 | ||
450 | inlen = MLX5_ST_SZ_BYTES(create_mkey_in); | |
451 | ||
452 | in = kvzalloc(inlen, GFP_KERNEL); | |
453 | if (!in) | |
454 | return -ENOMEM; | |
455 | ||
456 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
457 | ||
458 | MLX5_SET(mkc, mkc, free, 1); | |
459 | MLX5_SET(mkc, mkc, umr_en, 1); | |
460 | MLX5_SET(mkc, mkc, lw, 1); | |
461 | MLX5_SET(mkc, mkc, lr, 1); | |
462 | MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS); | |
463 | mlx5e_mkey_set_relaxed_ordering(mdev, mkc); | |
464 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
465 | MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn); | |
466 | MLX5_SET(mkc, mkc, translations_octword_size, nentries); | |
467 | MLX5_SET(mkc, mkc, length64, 1); | |
468 | err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen); | |
469 | ||
470 | kvfree(in); | |
471 | return err; | |
472 | } | |
473 | ||
a43b25da | 474 | static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq) |
ec8b9981 | 475 | { |
13921345 | 476 | u32 xsk_chunk_size = rq->xsk_pool ? rq->xsk_pool->chunk_size : 0; |
6470d2e7 MM |
477 | u32 wq_size = mlx5_wq_ll_get_size(&rq->mpwqe.wq); |
478 | u32 num_entries, max_num_entries; | |
ecc7ad2e MM |
479 | u32 umr_mkey; |
480 | int err; | |
ec8b9981 | 481 | |
168723c1 | 482 | max_num_entries = mlx5e_mpwrq_max_num_entries(mdev, rq->mpwqe.umr_mode); |
6470d2e7 MM |
483 | |
484 | /* Shouldn't overflow, the result is at most MLX5E_MAX_RQ_NUM_MTTS. */ | |
485 | if (WARN_ON_ONCE(check_mul_overflow(wq_size, (u32)rq->mpwqe.mtts_per_wqe, | |
486 | &num_entries) || | |
487 | num_entries > max_num_entries)) | |
488 | mlx5_core_err(mdev, "%s: multiplication overflow: %u * %u > %u\n", | |
489 | __func__, wq_size, rq->mpwqe.mtts_per_wqe, | |
490 | max_num_entries); | |
491 | ||
492 | err = mlx5e_create_umr_mkey(mdev, num_entries, rq->mpwqe.page_shift, | |
493 | &umr_mkey, rq->wqe_overflow.addr, | |
13921345 | 494 | rq->mpwqe.umr_mode, xsk_chunk_size); |
ecc7ad2e MM |
495 | rq->mpwqe.umr_mkey_be = cpu_to_be32(umr_mkey); |
496 | return err; | |
e5ca8fb0 BBI |
497 | } |
498 | ||
499 | static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev, | |
500 | struct mlx5e_rq *rq) | |
501 | { | |
502 | u32 max_klm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size)); | |
503 | ||
504 | if (max_klm_size < rq->mpwqe.shampo->hd_per_wq) { | |
505 | mlx5_core_err(mdev, "max klm list size 0x%x is smaller than shampo header buffer list size 0x%x\n", | |
506 | max_klm_size, rq->mpwqe.shampo->hd_per_wq); | |
507 | return -EINVAL; | |
508 | } | |
509 | return mlx5e_create_umr_klm_mkey(mdev, rq->mpwqe.shampo->hd_per_wq, | |
510 | &rq->mpwqe.shampo->mkey); | |
ec8b9981 TT |
511 | } |
512 | ||
069d1146 TT |
513 | static void mlx5e_init_frags_partition(struct mlx5e_rq *rq) |
514 | { | |
60d60c8f QC |
515 | struct mlx5e_wqe_frag_info next_frag = {}; |
516 | struct mlx5e_wqe_frag_info *prev = NULL; | |
069d1146 TT |
517 | int i; |
518 | ||
8fb1814f | 519 | WARN_ON(rq->xsk_pool); |
069d1146 | 520 | |
6f574284 | 521 | next_frag.frag_page = &rq->wqe.alloc_units->frag_pages[0]; |
259bbc64 | 522 | |
3f93f829 DT |
523 | /* Skip first release due to deferred release. */ |
524 | next_frag.flags = BIT(MLX5E_WQE_FRAG_SKIP_RELEASE); | |
069d1146 TT |
525 | |
526 | for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) { | |
527 | struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0]; | |
528 | struct mlx5e_wqe_frag_info *frag = | |
529 | &rq->wqe.frags[i << rq->wqe.info.log_num_frags]; | |
530 | int f; | |
531 | ||
532 | for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) { | |
533 | if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) { | |
8fb1814f | 534 | /* Pages are assigned at runtime. */ |
6f574284 | 535 | next_frag.frag_page++; |
069d1146 TT |
536 | next_frag.offset = 0; |
537 | if (prev) | |
625dff29 | 538 | prev->flags |= BIT(MLX5E_WQE_FRAG_LAST_IN_PAGE); |
069d1146 TT |
539 | } |
540 | *frag = next_frag; | |
541 | ||
542 | /* prepare next */ | |
543 | next_frag.offset += frag_info[f].frag_stride; | |
544 | prev = frag; | |
545 | } | |
546 | } | |
547 | ||
548 | if (prev) | |
625dff29 | 549 | prev->flags |= BIT(MLX5E_WQE_FRAG_LAST_IN_PAGE); |
069d1146 TT |
550 | } |
551 | ||
8fb1814f DT |
552 | static void mlx5e_init_xsk_buffs(struct mlx5e_rq *rq) |
553 | { | |
554 | int i; | |
555 | ||
556 | /* Assumptions used by XSK batched allocator. */ | |
557 | WARN_ON(rq->wqe.info.num_frags != 1); | |
558 | WARN_ON(rq->wqe.info.log_num_frags != 0); | |
559 | WARN_ON(rq->wqe.info.arr[0].frag_stride != PAGE_SIZE); | |
560 | ||
561 | /* Considering the above assumptions a fragment maps to a single | |
562 | * xsk_buff. | |
563 | */ | |
3f93f829 | 564 | for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) { |
8fb1814f | 565 | rq->wqe.frags[i].xskp = &rq->wqe.alloc_units->xsk_buffs[i]; |
3f93f829 DT |
566 | |
567 | /* Skip first release due to deferred release as WQES are | |
568 | * not allocated yet. | |
569 | */ | |
570 | rq->wqe.frags[i].flags |= BIT(MLX5E_WQE_FRAG_SKIP_RELEASE); | |
571 | } | |
069d1146 TT |
572 | } |
573 | ||
8fb1814f | 574 | static int mlx5e_init_wqe_alloc_info(struct mlx5e_rq *rq, int node) |
069d1146 | 575 | { |
8fb1814f | 576 | int wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq); |
069d1146 | 577 | int len = wq_sz << rq->wqe.info.log_num_frags; |
8fb1814f DT |
578 | struct mlx5e_wqe_frag_info *frags; |
579 | union mlx5e_alloc_units *aus; | |
580 | int aus_sz; | |
069d1146 | 581 | |
8fb1814f DT |
582 | if (rq->xsk_pool) |
583 | aus_sz = sizeof(*aus->xsk_buffs); | |
584 | else | |
6f574284 | 585 | aus_sz = sizeof(*aus->frag_pages); |
8fb1814f DT |
586 | |
587 | aus = kvzalloc_node(array_size(len, aus_sz), GFP_KERNEL, node); | |
588 | if (!aus) | |
069d1146 TT |
589 | return -ENOMEM; |
590 | ||
8fb1814f DT |
591 | frags = kvzalloc_node(array_size(len, sizeof(*frags)), GFP_KERNEL, node); |
592 | if (!frags) { | |
593 | kvfree(aus); | |
069d1146 | 594 | return -ENOMEM; |
8fb1814f DT |
595 | } |
596 | ||
597 | rq->wqe.alloc_units = aus; | |
598 | rq->wqe.frags = frags; | |
069d1146 | 599 | |
8fb1814f DT |
600 | if (rq->xsk_pool) |
601 | mlx5e_init_xsk_buffs(rq); | |
602 | else | |
603 | mlx5e_init_frags_partition(rq); | |
069d1146 TT |
604 | |
605 | return 0; | |
606 | } | |
607 | ||
8fb1814f | 608 | static void mlx5e_free_wqe_alloc_info(struct mlx5e_rq *rq) |
069d1146 | 609 | { |
8fb1814f | 610 | kvfree(rq->wqe.frags); |
79008676 | 611 | kvfree(rq->wqe.alloc_units); |
069d1146 TT |
612 | } |
613 | ||
8276ea13 AL |
614 | static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work) |
615 | { | |
616 | struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work); | |
617 | ||
618 | mlx5e_reporter_rq_cqe_err(rq); | |
619 | } | |
620 | ||
c3c94023 AL |
621 | static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq) |
622 | { | |
623 | rq->wqe_overflow.page = alloc_page(GFP_KERNEL); | |
624 | if (!rq->wqe_overflow.page) | |
625 | return -ENOMEM; | |
626 | ||
627 | rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0, | |
628 | PAGE_SIZE, rq->buff.map_dir); | |
629 | if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) { | |
630 | __free_page(rq->wqe_overflow.page); | |
631 | return -ENOMEM; | |
632 | } | |
633 | return 0; | |
634 | } | |
635 | ||
636 | static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq) | |
637 | { | |
638 | dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE, | |
639 | rq->buff.map_dir); | |
640 | __free_page(rq->wqe_overflow.page); | |
641 | } | |
642 | ||
869c5f92 | 643 | static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params, |
4e7401fc | 644 | u32 xdp_frag_size, struct mlx5e_rq *rq) |
869c5f92 AL |
645 | { |
646 | struct mlx5_core_dev *mdev = c->mdev; | |
647 | int err; | |
648 | ||
649 | rq->wq_type = params->rq_wq_type; | |
650 | rq->pdev = c->pdev; | |
651 | rq->netdev = c->netdev; | |
652 | rq->priv = c->priv; | |
653 | rq->tstamp = c->tstamp; | |
654 | rq->clock = &mdev->clock; | |
655 | rq->icosq = &c->icosq; | |
656 | rq->ix = c->ix; | |
2e642afb | 657 | rq->channel = c; |
869c5f92 | 658 | rq->mdev = mdev; |
1e662209 AF |
659 | rq->hw_mtu = |
660 | MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN * !params->scatter_fcs_en; | |
869c5f92 | 661 | rq->xdpsq = &c->rq_xdpsq; |
be98737a | 662 | rq->stats = &c->priv->channel_stats[c->ix]->rq; |
869c5f92 AL |
663 | rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev); |
664 | err = mlx5e_rq_set_handlers(rq, params, NULL); | |
665 | if (err) | |
666 | return err; | |
667 | ||
4e7401fc MM |
668 | return __xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, c->napi.napi_id, |
669 | xdp_frag_size); | |
869c5f92 AL |
670 | } |
671 | ||
e5ca8fb0 BBI |
672 | static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev, |
673 | struct mlx5e_params *params, | |
674 | struct mlx5e_rq_param *rqp, | |
675 | struct mlx5e_rq *rq, | |
676 | u32 *pool_size, | |
677 | int node) | |
678 | { | |
679 | void *wqc = MLX5_ADDR_OF(rqc, rqp->rqc, wq); | |
680 | int wq_size; | |
681 | int err; | |
682 | ||
683 | if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) | |
684 | return 0; | |
685 | err = mlx5e_rq_shampo_hd_alloc(rq, node); | |
686 | if (err) | |
687 | goto out; | |
688 | rq->mpwqe.shampo->hd_per_wq = | |
689 | mlx5e_shampo_hd_per_wq(mdev, params, rqp); | |
690 | err = mlx5e_create_rq_hd_umr_mkey(mdev, rq); | |
691 | if (err) | |
692 | goto err_shampo_hd; | |
693 | err = mlx5e_rq_shampo_hd_info_alloc(rq, node); | |
694 | if (err) | |
695 | goto err_shampo_info; | |
92552d3a KM |
696 | rq->hw_gro_data = kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, node); |
697 | if (!rq->hw_gro_data) { | |
698 | err = -ENOMEM; | |
699 | goto err_hw_gro_data; | |
700 | } | |
e5ca8fb0 | 701 | rq->mpwqe.shampo->key = |
573bce9e | 702 | cpu_to_be32(rq->mpwqe.shampo->mkey); |
e5ca8fb0 BBI |
703 | rq->mpwqe.shampo->hd_per_wqe = |
704 | mlx5e_shampo_hd_per_wqe(mdev, params, rqp); | |
705 | wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz)); | |
706 | *pool_size += (rq->mpwqe.shampo->hd_per_wqe * wq_size) / | |
707 | MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; | |
708 | return 0; | |
709 | ||
92552d3a KM |
710 | err_hw_gro_data: |
711 | mlx5e_rq_shampo_hd_info_free(rq); | |
e5ca8fb0 | 712 | err_shampo_info: |
573bce9e | 713 | mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey); |
e5ca8fb0 BBI |
714 | err_shampo_hd: |
715 | mlx5e_rq_shampo_hd_free(rq); | |
716 | out: | |
717 | return err; | |
718 | } | |
719 | ||
720 | static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq) | |
721 | { | |
722 | if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) | |
723 | return; | |
92552d3a KM |
724 | |
725 | kvfree(rq->hw_gro_data); | |
e5ca8fb0 | 726 | mlx5e_rq_shampo_hd_info_free(rq); |
573bce9e | 727 | mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey); |
e5ca8fb0 BBI |
728 | mlx5e_rq_shampo_hd_free(rq); |
729 | } | |
730 | ||
869c5f92 | 731 | static int mlx5e_alloc_rq(struct mlx5e_params *params, |
db05815b | 732 | struct mlx5e_xsk_param *xsk, |
6a9764ef | 733 | struct mlx5e_rq_param *rqp, |
869c5f92 | 734 | int node, struct mlx5e_rq *rq) |
f62b8bb8 | 735 | { |
869c5f92 | 736 | struct mlx5_core_dev *mdev = rq->mdev; |
6a9764ef | 737 | void *rqc = rqp->rqc; |
f62b8bb8 | 738 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); |
069d1146 | 739 | u32 pool_size; |
f62b8bb8 AV |
740 | int wq_sz; |
741 | int err; | |
742 | int i; | |
743 | ||
869c5f92 | 744 | rqp->wq.db_numa_node = node; |
8276ea13 | 745 | INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work); |
97bc402d | 746 | |
85192dbf AN |
747 | if (params->xdp_prog) |
748 | bpf_prog_inc(params->xdp_prog); | |
fe45386a | 749 | RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog); |
7e426671 | 750 | |
fe45386a | 751 | rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; |
db05815b | 752 | rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk); |
60bbf7ee | 753 | pool_size = 1 << params->log_rq_mtu_frames; |
b5503b99 | 754 | |
ecc7ad2e MM |
755 | rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey); |
756 | ||
6a9764ef | 757 | switch (rq->wq_type) { |
461017cb | 758 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: |
422d4c40 TT |
759 | err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq, |
760 | &rq->wq_ctrl); | |
761 | if (err) | |
869c5f92 | 762 | goto err_rq_xdp_prog; |
422d4c40 | 763 | |
c3c94023 | 764 | err = mlx5e_alloc_mpwqe_rq_drop_page(rq); |
422d4c40 | 765 | if (err) |
e692139e | 766 | goto err_rq_wq_destroy; |
422d4c40 TT |
767 | |
768 | rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR]; | |
769 | ||
770 | wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq); | |
60bbf7ee | 771 | |
e5a3cc83 | 772 | rq->mpwqe.page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); |
168723c1 | 773 | rq->mpwqe.umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); |
e5a3cc83 | 774 | rq->mpwqe.pages_per_wqe = |
6470d2e7 | 775 | mlx5e_mpwrq_pages_per_wqe(mdev, rq->mpwqe.page_shift, |
168723c1 | 776 | rq->mpwqe.umr_mode); |
e5a3cc83 | 777 | rq->mpwqe.umr_wqebbs = |
6470d2e7 | 778 | mlx5e_mpwrq_umr_wqebbs(mdev, rq->mpwqe.page_shift, |
168723c1 | 779 | rq->mpwqe.umr_mode); |
e5a3cc83 | 780 | rq->mpwqe.mtts_per_wqe = |
6470d2e7 | 781 | mlx5e_mpwrq_mtts_per_wqe(mdev, rq->mpwqe.page_shift, |
168723c1 | 782 | rq->mpwqe.umr_mode); |
997ce6af MM |
783 | |
784 | pool_size = rq->mpwqe.pages_per_wqe << | |
e5a3cc83 | 785 | mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk); |
422d4c40 | 786 | |
f52ac702 TT |
787 | if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk) && params->xdp_prog) |
788 | pool_size *= 2; /* additional page per packet for the linear part */ | |
789 | ||
db05815b MM |
790 | rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); |
791 | rq->mpwqe.num_strides = | |
792 | BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk)); | |
4b5fba4a | 793 | rq->mpwqe.min_wqe_bulk = mlx5e_mpwqe_get_min_wqe_bulk(wq_sz); |
1bfecfca | 794 | |
d628ee4f JDB |
795 | rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz); |
796 | ||
a43b25da | 797 | err = mlx5e_create_rq_umr_mkey(mdev, rq); |
7e426671 | 798 | if (err) |
c3c94023 | 799 | goto err_rq_drop_page; |
ec8b9981 | 800 | |
869c5f92 | 801 | err = mlx5e_rq_alloc_mpwqe_info(rq, node); |
ec8b9981 | 802 | if (err) |
08a762ce | 803 | goto err_rq_mkey; |
e5ca8fb0 BBI |
804 | |
805 | err = mlx5_rq_shampo_alloc(mdev, params, rqp, rq, &pool_size, node); | |
806 | if (err) | |
8f5ed1c1 | 807 | goto err_free_mpwqe_info; |
e5ca8fb0 | 808 | |
461017cb | 809 | break; |
99cbfa93 TT |
810 | default: /* MLX5_WQ_TYPE_CYCLIC */ |
811 | err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq, | |
812 | &rq->wq_ctrl); | |
422d4c40 | 813 | if (err) |
869c5f92 | 814 | goto err_rq_xdp_prog; |
422d4c40 TT |
815 | |
816 | rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR]; | |
817 | ||
99cbfa93 | 818 | wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq); |
422d4c40 | 819 | |
069d1146 | 820 | rq->wqe.info = rqp->frags_info; |
d628ee4f JDB |
821 | rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride; |
822 | ||
8fb1814f | 823 | err = mlx5e_init_wqe_alloc_info(rq, node); |
069d1146 | 824 | if (err) |
8fb1814f | 825 | goto err_rq_wq_destroy; |
461017cb | 826 | } |
f62b8bb8 | 827 | |
db05815b | 828 | if (xsk) { |
db05815b | 829 | err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq, |
39d6443c | 830 | MEM_TYPE_XSK_BUFF_POOL, NULL); |
c4655761 | 831 | xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq); |
db05815b MM |
832 | } else { |
833 | /* Create a page_pool and register it with rxq */ | |
4a5c5e25 DT |
834 | struct page_pool_params pp_params = { 0 }; |
835 | ||
db05815b | 836 | pp_params.order = 0; |
6f574284 | 837 | pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV | PP_FLAG_PAGE_FRAG; |
db05815b | 838 | pp_params.pool_size = pool_size; |
869c5f92 AL |
839 | pp_params.nid = node; |
840 | pp_params.dev = rq->pdev; | |
a880f814 | 841 | pp_params.napi = rq->cq.napi; |
db05815b | 842 | pp_params.dma_dir = rq->buff.map_dir; |
4a5c5e25 | 843 | pp_params.max_len = PAGE_SIZE; |
db05815b MM |
844 | |
845 | /* page_pool can be used even when there is no rq->xdp_prog, | |
846 | * given page_pool does not handle DMA mapping there is no | |
847 | * required state to clear. And page_pool gracefully handle | |
848 | * elevated refcnt. | |
849 | */ | |
850 | rq->page_pool = page_pool_create(&pp_params); | |
851 | if (IS_ERR(rq->page_pool)) { | |
852 | err = PTR_ERR(rq->page_pool); | |
853 | rq->page_pool = NULL; | |
8f5ed1c1 | 854 | goto err_free_by_rq_type; |
db05815b | 855 | } |
5b232ea9 AL |
856 | if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) |
857 | err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq, | |
858 | MEM_TYPE_PAGE_POOL, rq->page_pool); | |
84f5e3fb | 859 | } |
db05815b | 860 | if (err) |
8f5ed1c1 | 861 | goto err_destroy_page_pool; |
84f5e3fb | 862 | |
f62b8bb8 | 863 | for (i = 0; i < wq_sz; i++) { |
4c2af5cc | 864 | if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { |
99cbfa93 | 865 | struct mlx5e_rx_wqe_ll *wqe = |
422d4c40 | 866 | mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i); |
069d1146 TT |
867 | u32 byte_count = |
868 | rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz; | |
997ce6af MM |
869 | u64 dma_offset = mul_u32_u32(i, rq->mpwqe.mtts_per_wqe) << |
870 | rq->mpwqe.page_shift; | |
e5ca8fb0 BBI |
871 | u16 headroom = test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state) ? |
872 | 0 : rq->buff.headroom; | |
4c2af5cc | 873 | |
e5ca8fb0 | 874 | wqe->data[0].addr = cpu_to_be64(dma_offset + headroom); |
99cbfa93 | 875 | wqe->data[0].byte_count = cpu_to_be32(byte_count); |
ecc7ad2e | 876 | wqe->data[0].lkey = rq->mpwqe.umr_mkey_be; |
422d4c40 | 877 | } else { |
99cbfa93 TT |
878 | struct mlx5e_rx_wqe_cyc *wqe = |
879 | mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i); | |
069d1146 TT |
880 | int f; |
881 | ||
882 | for (f = 0; f < rq->wqe.info.num_frags; f++) { | |
883 | u32 frag_size = rq->wqe.info.arr[f].frag_size | | |
884 | MLX5_HW_START_PADDING; | |
885 | ||
886 | wqe->data[f].byte_count = cpu_to_be32(frag_size); | |
887 | wqe->data[f].lkey = rq->mkey_be; | |
888 | } | |
889 | /* check if num_frags is not a pow of two */ | |
890 | if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) { | |
891 | wqe->data[f].byte_count = 0; | |
1db1f21c | 892 | wqe->data[f].lkey = params->terminate_lkey_be; |
069d1146 TT |
893 | wqe->data[f].addr = 0; |
894 | } | |
422d4c40 | 895 | } |
f62b8bb8 AV |
896 | } |
897 | ||
9a317425 AG |
898 | INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work); |
899 | ||
900 | switch (params->rx_cq_moderation.cq_period_mode) { | |
901 | case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: | |
c002bd52 | 902 | rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; |
9a317425 AG |
903 | break; |
904 | case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: | |
905 | default: | |
c002bd52 | 906 | rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; |
9a317425 AG |
907 | } |
908 | ||
f62b8bb8 AV |
909 | return 0; |
910 | ||
8f5ed1c1 MM |
911 | err_destroy_page_pool: |
912 | page_pool_destroy(rq->page_pool); | |
08a762ce | 913 | err_free_by_rq_type: |
069d1146 TT |
914 | switch (rq->wq_type) { |
915 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
8f5ed1c1 MM |
916 | mlx5e_rq_free_shampo(rq); |
917 | err_free_mpwqe_info: | |
ca11b798 | 918 | kvfree(rq->mpwqe.info); |
08a762ce | 919 | err_rq_mkey: |
ecc7ad2e | 920 | mlx5_core_destroy_mkey(mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be)); |
c3c94023 AL |
921 | err_rq_drop_page: |
922 | mlx5e_free_mpwqe_rq_drop_page(rq); | |
069d1146 TT |
923 | break; |
924 | default: /* MLX5_WQ_TYPE_CYCLIC */ | |
8fb1814f | 925 | mlx5e_free_wqe_alloc_info(rq); |
069d1146 | 926 | } |
f62b8bb8 | 927 | err_rq_wq_destroy: |
08a762ce | 928 | mlx5_wq_destroy(&rq->wq_ctrl); |
08a762ce | 929 | err_rq_xdp_prog: |
fe45386a MM |
930 | if (params->xdp_prog) |
931 | bpf_prog_put(params->xdp_prog); | |
f62b8bb8 AV |
932 | |
933 | return err; | |
934 | } | |
935 | ||
3b77235b | 936 | static void mlx5e_free_rq(struct mlx5e_rq *rq) |
f62b8bb8 | 937 | { |
cdd3f236 | 938 | struct bpf_prog *old_prog; |
4415a031 | 939 | |
e078e8df AL |
940 | if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) { |
941 | old_prog = rcu_dereference_protected(rq->xdp_prog, | |
942 | lockdep_is_held(&rq->priv->state_lock)); | |
943 | if (old_prog) | |
944 | bpf_prog_put(old_prog); | |
945 | } | |
86994156 | 946 | |
461017cb TT |
947 | switch (rq->wq_type) { |
948 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
ca11b798 | 949 | kvfree(rq->mpwqe.info); |
ecc7ad2e | 950 | mlx5_core_destroy_mkey(rq->mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be)); |
c3c94023 | 951 | mlx5e_free_mpwqe_rq_drop_page(rq); |
e5ca8fb0 | 952 | mlx5e_rq_free_shampo(rq); |
461017cb | 953 | break; |
99cbfa93 | 954 | default: /* MLX5_WQ_TYPE_CYCLIC */ |
8fb1814f | 955 | mlx5e_free_wqe_alloc_info(rq); |
4415a031 | 956 | } |
29b006a6 JDB |
957 | |
958 | xdp_rxq_info_unreg(&rq->xdp_rxq); | |
1da4bbef | 959 | page_pool_destroy(rq->page_pool); |
f62b8bb8 AV |
960 | mlx5_wq_destroy(&rq->wq_ctrl); |
961 | } | |
962 | ||
5543e989 | 963 | int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) |
f62b8bb8 | 964 | { |
a43b25da | 965 | struct mlx5_core_dev *mdev = rq->mdev; |
432119de | 966 | u8 ts_format; |
f62b8bb8 AV |
967 | void *in; |
968 | void *rqc; | |
969 | void *wq; | |
970 | int inlen; | |
971 | int err; | |
972 | ||
973 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + | |
974 | sizeof(u64) * rq->wq_ctrl.buf.npages; | |
1b9a07ee | 975 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
976 | if (!in) |
977 | return -ENOMEM; | |
978 | ||
432119de | 979 | ts_format = mlx5_is_real_time_rq(mdev) ? |
9a1ac95a AL |
980 | MLX5_TIMESTAMP_FORMAT_REAL_TIME : |
981 | MLX5_TIMESTAMP_FORMAT_FREE_RUNNING; | |
f62b8bb8 AV |
982 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); |
983 | wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
984 | ||
985 | memcpy(rqc, param->rqc, sizeof(param->rqc)); | |
986 | ||
97de9f31 | 987 | MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn); |
f62b8bb8 | 988 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); |
432119de | 989 | MLX5_SET(rqc, rqc, ts_format, ts_format); |
f62b8bb8 | 990 | MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - |
68cdf5d6 | 991 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
992 | MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); |
993 | ||
e5ca8fb0 BBI |
994 | if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) { |
995 | MLX5_SET(wq, wq, log_headers_buffer_entry_num, | |
996 | order_base_2(rq->mpwqe.shampo->hd_per_wq)); | |
573bce9e | 997 | MLX5_SET(wq, wq, headers_mkey, rq->mpwqe.shampo->mkey); |
e5ca8fb0 BBI |
998 | } |
999 | ||
3a2f7033 TT |
1000 | mlx5_fill_page_frag_array(&rq->wq_ctrl.buf, |
1001 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
f62b8bb8 | 1002 | |
7db22ffb | 1003 | err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); |
f62b8bb8 AV |
1004 | |
1005 | kvfree(in); | |
1006 | ||
1007 | return err; | |
1008 | } | |
1009 | ||
d9ba64de | 1010 | static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state) |
f62b8bb8 | 1011 | { |
7cbaf9a3 | 1012 | struct mlx5_core_dev *mdev = rq->mdev; |
f62b8bb8 AV |
1013 | |
1014 | void *in; | |
1015 | void *rqc; | |
1016 | int inlen; | |
1017 | int err; | |
1018 | ||
1019 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 1020 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
1021 | if (!in) |
1022 | return -ENOMEM; | |
1023 | ||
5ee090ed AL |
1024 | if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY) |
1025 | mlx5e_rqwq_reset(rq); | |
1026 | ||
f62b8bb8 AV |
1027 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); |
1028 | ||
1029 | MLX5_SET(modify_rq_in, in, rq_state, curr_state); | |
1030 | MLX5_SET(rqc, rqc, state, next_state); | |
1031 | ||
e0b4b472 | 1032 | err = mlx5_core_modify_rq(mdev, rq->rqn, in); |
f62b8bb8 AV |
1033 | |
1034 | kvfree(in); | |
1035 | ||
1036 | return err; | |
1037 | } | |
1038 | ||
39646d9b DT |
1039 | static void mlx5e_flush_rq_cq(struct mlx5e_rq *rq) |
1040 | { | |
1041 | struct mlx5_cqwq *cqwq = &rq->cq.wq; | |
1042 | struct mlx5_cqe64 *cqe; | |
1043 | ||
1044 | if (test_bit(MLX5E_RQ_STATE_MINI_CQE_ENHANCED, &rq->state)) { | |
1045 | while ((cqe = mlx5_cqwq_get_cqe_enahnced_comp(cqwq))) | |
1046 | mlx5_cqwq_pop(cqwq); | |
1047 | } else { | |
1048 | while ((cqe = mlx5_cqwq_get_cqe(cqwq))) | |
1049 | mlx5_cqwq_pop(cqwq); | |
1050 | } | |
1051 | ||
1052 | mlx5_cqwq_update_db_record(cqwq); | |
1053 | } | |
1054 | ||
1055 | int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state) | |
d9ba64de MM |
1056 | { |
1057 | struct net_device *dev = rq->netdev; | |
1058 | int err; | |
1059 | ||
1060 | err = mlx5e_modify_rq_state(rq, curr_state, MLX5_RQC_STATE_RST); | |
1061 | if (err) { | |
1062 | netdev_err(dev, "Failed to move rq 0x%x to reset\n", rq->rqn); | |
1063 | return err; | |
1064 | } | |
39646d9b DT |
1065 | |
1066 | mlx5e_free_rx_descs(rq); | |
1067 | mlx5e_flush_rq_cq(rq); | |
1068 | ||
d9ba64de MM |
1069 | err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); |
1070 | if (err) { | |
1071 | netdev_err(dev, "Failed to move rq 0x%x to ready\n", rq->rqn); | |
1072 | return err; | |
1073 | } | |
1074 | ||
1075 | return 0; | |
1076 | } | |
1077 | ||
36350114 GP |
1078 | static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd) |
1079 | { | |
521f31af | 1080 | struct mlx5_core_dev *mdev = rq->mdev; |
36350114 GP |
1081 | void *in; |
1082 | void *rqc; | |
1083 | int inlen; | |
1084 | int err; | |
1085 | ||
1086 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 1087 | in = kvzalloc(inlen, GFP_KERNEL); |
36350114 GP |
1088 | if (!in) |
1089 | return -ENOMEM; | |
1090 | ||
1091 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
1092 | ||
1093 | MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); | |
83b502a1 AV |
1094 | MLX5_SET64(modify_rq_in, in, modify_bitmask, |
1095 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); | |
36350114 GP |
1096 | MLX5_SET(rqc, rqc, vsd, vsd); |
1097 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); | |
1098 | ||
e0b4b472 | 1099 | err = mlx5_core_modify_rq(mdev, rq->rqn, in); |
36350114 GP |
1100 | |
1101 | kvfree(in); | |
1102 | ||
1103 | return err; | |
1104 | } | |
1105 | ||
5543e989 | 1106 | void mlx5e_destroy_rq(struct mlx5e_rq *rq) |
f62b8bb8 | 1107 | { |
a43b25da | 1108 | mlx5_core_destroy_rq(rq->mdev, rq->rqn); |
f62b8bb8 AV |
1109 | } |
1110 | ||
db05815b | 1111 | int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time) |
f62b8bb8 | 1112 | { |
1e7477ae | 1113 | unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time); |
a43b25da | 1114 | |
422d4c40 | 1115 | u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq)); |
f62b8bb8 | 1116 | |
1e7477ae | 1117 | do { |
422d4c40 | 1118 | if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes) |
f62b8bb8 AV |
1119 | return 0; |
1120 | ||
1121 | msleep(20); | |
1e7477ae EBE |
1122 | } while (time_before(jiffies, exp_time)); |
1123 | ||
521f31af AL |
1124 | netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n", |
1125 | rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes); | |
f62b8bb8 | 1126 | |
32c57fb2 | 1127 | mlx5e_reporter_rx_timeout(rq); |
f62b8bb8 AV |
1128 | return -ETIMEDOUT; |
1129 | } | |
1130 | ||
4c2a1323 | 1131 | void mlx5e_free_rx_missing_descs(struct mlx5e_rq *rq) |
e239c6d6 AL |
1132 | { |
1133 | struct mlx5_wq_ll *wq; | |
1134 | u16 head; | |
1135 | int i; | |
1136 | ||
1137 | if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) | |
1138 | return; | |
1139 | ||
1140 | wq = &rq->mpwqe.wq; | |
1141 | head = wq->head; | |
1142 | ||
4c2a1323 DT |
1143 | /* Release WQEs that are in missing state: they have been |
1144 | * popped from the list after completion but were not freed | |
1145 | * due to deferred release. | |
1146 | * Also free the linked-list reserved entry, hence the "+ 1". | |
1147 | */ | |
1148 | for (i = 0; i < mlx5_wq_ll_missing(wq) + 1; i++) { | |
e239c6d6 AL |
1149 | rq->dealloc_wqe(rq, head); |
1150 | head = mlx5_wq_ll_get_wqe_next_ix(wq, head); | |
1151 | } | |
1152 | ||
e5ca8fb0 BBI |
1153 | if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) { |
1154 | u16 len; | |
1155 | ||
1156 | len = (rq->mpwqe.shampo->pi - rq->mpwqe.shampo->ci) & | |
1157 | (rq->mpwqe.shampo->hd_per_wq - 1); | |
1158 | mlx5e_shampo_dealloc_hd(rq, len, rq->mpwqe.shampo->ci, false); | |
1159 | rq->mpwqe.shampo->pi = rq->mpwqe.shampo->ci; | |
1160 | } | |
1161 | ||
e239c6d6 AL |
1162 | rq->mpwqe.actual_wq_head = wq->head; |
1163 | rq->mpwqe.umr_in_progress = 0; | |
1164 | rq->mpwqe.umr_completed = 0; | |
1165 | } | |
1166 | ||
be5323c8 | 1167 | void mlx5e_free_rx_descs(struct mlx5e_rq *rq) |
f2fde18c | 1168 | { |
f2fde18c SM |
1169 | __be16 wqe_ix_be; |
1170 | u16 wqe_ix; | |
1171 | ||
422d4c40 TT |
1172 | if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { |
1173 | struct mlx5_wq_ll *wq = &rq->mpwqe.wq; | |
1174 | ||
4c2a1323 | 1175 | mlx5e_free_rx_missing_descs(rq); |
422d4c40 TT |
1176 | |
1177 | while (!mlx5_wq_ll_is_empty(wq)) { | |
99cbfa93 | 1178 | struct mlx5e_rx_wqe_ll *wqe; |
422d4c40 TT |
1179 | |
1180 | wqe_ix_be = *wq->tail_next; | |
1181 | wqe_ix = be16_to_cpu(wqe_ix_be); | |
1182 | wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix); | |
1183 | rq->dealloc_wqe(rq, wqe_ix); | |
1184 | mlx5_wq_ll_pop(wq, wqe_ix_be, | |
1185 | &wqe->next.next_wqe_index); | |
1186 | } | |
e5ca8fb0 BBI |
1187 | |
1188 | if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) | |
1189 | mlx5e_shampo_dealloc_hd(rq, rq->mpwqe.shampo->hd_per_wq, | |
1190 | 0, true); | |
422d4c40 | 1191 | } else { |
99cbfa93 | 1192 | struct mlx5_wq_cyc *wq = &rq->wqe.wq; |
3f93f829 DT |
1193 | u16 missing = mlx5_wq_cyc_missing(wq); |
1194 | u16 head = mlx5_wq_cyc_get_head(wq); | |
422d4c40 | 1195 | |
99cbfa93 TT |
1196 | while (!mlx5_wq_cyc_is_empty(wq)) { |
1197 | wqe_ix = mlx5_wq_cyc_get_tail(wq); | |
422d4c40 | 1198 | rq->dealloc_wqe(rq, wqe_ix); |
99cbfa93 | 1199 | mlx5_wq_cyc_pop(wq); |
422d4c40 | 1200 | } |
3f93f829 DT |
1201 | /* Missing slots might also contain unreleased pages due to |
1202 | * deferred release. | |
1203 | */ | |
1204 | while (missing--) { | |
1205 | wqe_ix = mlx5_wq_cyc_ctr2ix(wq, head++); | |
1206 | rq->dealloc_wqe(rq, wqe_ix); | |
1207 | } | |
accd5883 | 1208 | } |
069d1146 | 1209 | |
f2fde18c SM |
1210 | } |
1211 | ||
869c5f92 AL |
1212 | int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param, |
1213 | struct mlx5e_xsk_param *xsk, int node, | |
1214 | struct mlx5e_rq *rq) | |
f62b8bb8 | 1215 | { |
869c5f92 | 1216 | struct mlx5_core_dev *mdev = rq->mdev; |
f62b8bb8 AV |
1217 | int err; |
1218 | ||
e5ca8fb0 BBI |
1219 | if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) |
1220 | __set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state); | |
1221 | ||
869c5f92 | 1222 | err = mlx5e_alloc_rq(params, xsk, param, node, rq); |
f62b8bb8 AV |
1223 | if (err) |
1224 | return err; | |
1225 | ||
3b77235b | 1226 | err = mlx5e_create_rq(rq, param); |
f62b8bb8 | 1227 | if (err) |
3b77235b | 1228 | goto err_free_rq; |
f62b8bb8 | 1229 | |
36350114 | 1230 | err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); |
f62b8bb8 | 1231 | if (err) |
3b77235b | 1232 | goto err_destroy_rq; |
f62b8bb8 | 1233 | |
869c5f92 AL |
1234 | if (MLX5_CAP_ETH(mdev, cqe_checksum_full)) |
1235 | __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state); | |
db849faa | 1236 | |
9a317425 | 1237 | if (params->rx_dim_enabled) |
2b5bd5b1 | 1238 | __set_bit(MLX5E_RQ_STATE_DIM, &rq->state); |
cb3c7fd4 | 1239 | |
5d0bb3ba SM |
1240 | /* We disable csum_complete when XDP is enabled since |
1241 | * XDP programs might manipulate packets which will render | |
1242 | * skb->checksum incorrect. | |
1243 | */ | |
869c5f92 AL |
1244 | if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog) |
1245 | __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state); | |
b856df28 | 1246 | |
b7cf0806 OL |
1247 | /* For CQE compression on striding RQ, use stride index provided by |
1248 | * HW if capability is supported. | |
1249 | */ | |
1250 | if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) && | |
869c5f92 AL |
1251 | MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index)) |
1252 | __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state); | |
b7cf0806 | 1253 | |
2c925db0 OL |
1254 | /* For enhanced CQE compression packet processing. decompress |
1255 | * session according to the enhanced layout. | |
1256 | */ | |
1257 | if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) && | |
1258 | MLX5_CAP_GEN(mdev, enhanced_cqe_compression)) | |
1259 | __set_bit(MLX5E_RQ_STATE_MINI_CQE_ENHANCED, &rq->state); | |
1260 | ||
f62b8bb8 AV |
1261 | return 0; |
1262 | ||
f62b8bb8 AV |
1263 | err_destroy_rq: |
1264 | mlx5e_destroy_rq(rq); | |
3b77235b SM |
1265 | err_free_rq: |
1266 | mlx5e_free_rq(rq); | |
f62b8bb8 AV |
1267 | |
1268 | return err; | |
1269 | } | |
1270 | ||
be5323c8 | 1271 | void mlx5e_activate_rq(struct mlx5e_rq *rq) |
acc6c595 | 1272 | { |
acc6c595 | 1273 | set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); |
acc6c595 SM |
1274 | } |
1275 | ||
db05815b | 1276 | void mlx5e_deactivate_rq(struct mlx5e_rq *rq) |
f62b8bb8 | 1277 | { |
c0f1147d | 1278 | clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); |
4d6e6b0c | 1279 | synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */ |
acc6c595 | 1280 | } |
cb3c7fd4 | 1281 | |
db05815b | 1282 | void mlx5e_close_rq(struct mlx5e_rq *rq) |
acc6c595 | 1283 | { |
9a317425 | 1284 | cancel_work_sync(&rq->dim.work); |
8276ea13 | 1285 | cancel_work_sync(&rq->recover_work); |
f62b8bb8 | 1286 | mlx5e_destroy_rq(rq); |
3b77235b SM |
1287 | mlx5e_free_rx_descs(rq); |
1288 | mlx5e_free_rq(rq); | |
f62b8bb8 AV |
1289 | } |
1290 | ||
31391048 | 1291 | static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq) |
b5503b99 | 1292 | { |
fea28dd6 | 1293 | kvfree(sq->db.xdpi_fifo.xi); |
1feeab80 | 1294 | kvfree(sq->db.wqe_info); |
fea28dd6 TT |
1295 | } |
1296 | ||
1297 | static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa) | |
1298 | { | |
1299 | struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo; | |
1300 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
34a79876 | 1301 | int entries; |
51984c9e | 1302 | size_t size; |
fea28dd6 | 1303 | |
34a79876 DT |
1304 | /* upper bound for maximum num of entries of all xmit_modes. */ |
1305 | entries = roundup_pow_of_two(wq_sz * MLX5_SEND_WQEBB_NUM_DS * | |
1306 | MLX5E_XDP_FIFO_ENTRIES2DS_MAX_RATIO); | |
1307 | ||
3f734b8c | 1308 | size = array_size(sizeof(*xdpi_fifo->xi), entries); |
51984c9e | 1309 | xdpi_fifo->xi = kvzalloc_node(size, GFP_KERNEL, numa); |
fea28dd6 TT |
1310 | if (!xdpi_fifo->xi) |
1311 | return -ENOMEM; | |
1312 | ||
1313 | xdpi_fifo->pc = &sq->xdpi_fifo_pc; | |
1314 | xdpi_fifo->cc = &sq->xdpi_fifo_cc; | |
3f734b8c | 1315 | xdpi_fifo->mask = entries - 1; |
fea28dd6 TT |
1316 | |
1317 | return 0; | |
b5503b99 SM |
1318 | } |
1319 | ||
31391048 | 1320 | static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa) |
b5503b99 | 1321 | { |
1feeab80 | 1322 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); |
51984c9e | 1323 | size_t size; |
fea28dd6 | 1324 | int err; |
b5503b99 | 1325 | |
51984c9e GS |
1326 | size = array_size(sizeof(*sq->db.wqe_info), wq_sz); |
1327 | sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa); | |
1feeab80 TT |
1328 | if (!sq->db.wqe_info) |
1329 | return -ENOMEM; | |
1330 | ||
fea28dd6 TT |
1331 | err = mlx5e_alloc_xdpsq_fifo(sq, numa); |
1332 | if (err) { | |
31391048 | 1333 | mlx5e_free_xdpsq_db(sq); |
fea28dd6 | 1334 | return err; |
b5503b99 SM |
1335 | } |
1336 | ||
1337 | return 0; | |
1338 | } | |
1339 | ||
31391048 | 1340 | static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c, |
6a9764ef | 1341 | struct mlx5e_params *params, |
1742b3d5 | 1342 | struct xsk_buff_pool *xsk_pool, |
31391048 | 1343 | struct mlx5e_sq_param *param, |
58b99ee3 TT |
1344 | struct mlx5e_xdpsq *sq, |
1345 | bool is_redirect) | |
31391048 SM |
1346 | { |
1347 | void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); | |
a43b25da | 1348 | struct mlx5_core_dev *mdev = c->mdev; |
ddf385e3 | 1349 | struct mlx5_wq_cyc *wq = &sq->wq; |
31391048 SM |
1350 | int err; |
1351 | ||
1352 | sq->pdev = c->pdev; | |
1353 | sq->mkey_be = c->mkey_be; | |
1354 | sq->channel = c; | |
c276aae8 | 1355 | sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map; |
6a9764ef | 1356 | sq->min_inline_mode = params->tx_min_inline_mode; |
1e267ab8 | 1357 | sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu) - ETH_FCS_LEN; |
1742b3d5 | 1358 | sq->xsk_pool = xsk_pool; |
db05815b | 1359 | |
1742b3d5 | 1360 | sq->stats = sq->xsk_pool ? |
be98737a | 1361 | &c->priv->channel_stats[c->ix]->xsksq : |
db05815b | 1362 | is_redirect ? |
be98737a TT |
1363 | &c->priv->channel_stats[c->ix]->xdpsq : |
1364 | &c->priv->channel_stats[c->ix]->rq_xdpsq; | |
21a0502d MM |
1365 | sq->stop_room = param->is_mpw ? mlx5e_stop_room_for_mpwqe(mdev) : |
1366 | mlx5e_stop_room_for_max_wqe(mdev); | |
ed5c92ff | 1367 | sq->max_sq_mpw_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev); |
31391048 | 1368 | |
231243c8 | 1369 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
ddf385e3 | 1370 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); |
31391048 SM |
1371 | if (err) |
1372 | return err; | |
ddf385e3 | 1373 | wq->db = &wq->db[MLX5_SND_DBR]; |
31391048 | 1374 | |
231243c8 | 1375 | err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu)); |
31391048 SM |
1376 | if (err) |
1377 | goto err_sq_wq_destroy; | |
1378 | ||
1379 | return 0; | |
1380 | ||
1381 | err_sq_wq_destroy: | |
1382 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1383 | ||
1384 | return err; | |
1385 | } | |
1386 | ||
1387 | static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq) | |
1388 | { | |
1389 | mlx5e_free_xdpsq_db(sq); | |
1390 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1391 | } | |
1392 | ||
1393 | static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq) | |
f62b8bb8 | 1394 | { |
7d42c8e9 | 1395 | kvfree(sq->db.wqe_info); |
f62b8bb8 AV |
1396 | } |
1397 | ||
31391048 | 1398 | static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa) |
f10b7cc7 | 1399 | { |
fd9b4be8 | 1400 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); |
7d42c8e9 | 1401 | size_t size; |
f10b7cc7 | 1402 | |
7d42c8e9 MM |
1403 | size = array_size(wq_sz, sizeof(*sq->db.wqe_info)); |
1404 | sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa); | |
1405 | if (!sq->db.wqe_info) | |
f10b7cc7 SM |
1406 | return -ENOMEM; |
1407 | ||
1408 | return 0; | |
1409 | } | |
1410 | ||
be5323c8 AL |
1411 | static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work) |
1412 | { | |
1413 | struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq, | |
1414 | recover_work); | |
1415 | ||
1416 | mlx5e_reporter_icosq_cqe_err(sq); | |
1417 | } | |
1418 | ||
19c4aba2 MM |
1419 | static void mlx5e_async_icosq_err_cqe_work(struct work_struct *recover_work) |
1420 | { | |
1421 | struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq, | |
1422 | recover_work); | |
1423 | ||
1424 | /* Not implemented yet. */ | |
1425 | ||
1426 | netdev_warn(sq->channel->netdev, "async_icosq recovery is not implemented\n"); | |
1427 | } | |
1428 | ||
31391048 | 1429 | static int mlx5e_alloc_icosq(struct mlx5e_channel *c, |
31391048 | 1430 | struct mlx5e_sq_param *param, |
19c4aba2 MM |
1431 | struct mlx5e_icosq *sq, |
1432 | work_func_t recover_work_func) | |
f10b7cc7 | 1433 | { |
31391048 | 1434 | void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); |
a43b25da | 1435 | struct mlx5_core_dev *mdev = c->mdev; |
ddf385e3 | 1436 | struct mlx5_wq_cyc *wq = &sq->wq; |
31391048 | 1437 | int err; |
f10b7cc7 | 1438 | |
31391048 | 1439 | sq->channel = c; |
c276aae8 | 1440 | sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map; |
3ff3874f | 1441 | sq->reserved_room = param->stop_room; |
f62b8bb8 | 1442 | |
231243c8 | 1443 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
ddf385e3 | 1444 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); |
31391048 SM |
1445 | if (err) |
1446 | return err; | |
ddf385e3 | 1447 | wq->db = &wq->db[MLX5_SND_DBR]; |
f62b8bb8 | 1448 | |
231243c8 | 1449 | err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu)); |
31391048 SM |
1450 | if (err) |
1451 | goto err_sq_wq_destroy; | |
1452 | ||
19c4aba2 | 1453 | INIT_WORK(&sq->recover_work, recover_work_func); |
be5323c8 | 1454 | |
f62b8bb8 | 1455 | return 0; |
31391048 SM |
1456 | |
1457 | err_sq_wq_destroy: | |
1458 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1459 | ||
1460 | return err; | |
f62b8bb8 AV |
1461 | } |
1462 | ||
31391048 | 1463 | static void mlx5e_free_icosq(struct mlx5e_icosq *sq) |
f10b7cc7 | 1464 | { |
31391048 SM |
1465 | mlx5e_free_icosq_db(sq); |
1466 | mlx5_wq_destroy(&sq->wq_ctrl); | |
f10b7cc7 SM |
1467 | } |
1468 | ||
145e5637 | 1469 | void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq) |
f10b7cc7 | 1470 | { |
ca11b798 | 1471 | kvfree(sq->db.wqe_info); |
0b676aae | 1472 | kvfree(sq->db.skb_fifo.fifo); |
ca11b798 | 1473 | kvfree(sq->db.dma_fifo); |
f10b7cc7 SM |
1474 | } |
1475 | ||
145e5637 | 1476 | int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa) |
b5503b99 | 1477 | { |
31391048 SM |
1478 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); |
1479 | int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS; | |
1480 | ||
eec4edc9 KC |
1481 | sq->db.dma_fifo = kvzalloc_node(array_size(df_sz, |
1482 | sizeof(*sq->db.dma_fifo)), | |
ca11b798 | 1483 | GFP_KERNEL, numa); |
0b676aae EBE |
1484 | sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz, |
1485 | sizeof(*sq->db.skb_fifo.fifo)), | |
338c46c6 | 1486 | GFP_KERNEL, numa); |
eec4edc9 KC |
1487 | sq->db.wqe_info = kvzalloc_node(array_size(wq_sz, |
1488 | sizeof(*sq->db.wqe_info)), | |
ca11b798 | 1489 | GFP_KERNEL, numa); |
0b676aae | 1490 | if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) { |
31391048 SM |
1491 | mlx5e_free_txqsq_db(sq); |
1492 | return -ENOMEM; | |
b5503b99 | 1493 | } |
31391048 SM |
1494 | |
1495 | sq->dma_fifo_mask = df_sz - 1; | |
0b676aae EBE |
1496 | |
1497 | sq->db.skb_fifo.pc = &sq->skb_fifo_pc; | |
1498 | sq->db.skb_fifo.cc = &sq->skb_fifo_cc; | |
1499 | sq->db.skb_fifo.mask = df_sz - 1; | |
31391048 SM |
1500 | |
1501 | return 0; | |
b5503b99 SM |
1502 | } |
1503 | ||
31391048 | 1504 | static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, |
acc6c595 | 1505 | int txq_ix, |
6a9764ef | 1506 | struct mlx5e_params *params, |
31391048 | 1507 | struct mlx5e_sq_param *param, |
05909bab EBE |
1508 | struct mlx5e_txqsq *sq, |
1509 | int tc) | |
f62b8bb8 | 1510 | { |
31391048 | 1511 | void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); |
a43b25da | 1512 | struct mlx5_core_dev *mdev = c->mdev; |
ddf385e3 | 1513 | struct mlx5_wq_cyc *wq = &sq->wq; |
f62b8bb8 AV |
1514 | int err; |
1515 | ||
f10b7cc7 | 1516 | sq->pdev = c->pdev; |
7c39afb3 | 1517 | sq->clock = &mdev->clock; |
f10b7cc7 | 1518 | sq->mkey_be = c->mkey_be; |
4ad40d8e EBE |
1519 | sq->netdev = c->netdev; |
1520 | sq->mdev = c->mdev; | |
79efecb4 | 1521 | sq->channel = c; |
4ad40d8e | 1522 | sq->priv = c->priv; |
57c70d87 | 1523 | sq->ch_ix = c->ix; |
acc6c595 | 1524 | sq->txq_ix = txq_ix; |
c276aae8 | 1525 | sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map; |
6a9764ef | 1526 | sq->min_inline_mode = params->tx_min_inline_mode; |
84d1bb2b | 1527 | sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); |
ed5c92ff | 1528 | sq->max_sq_mpw_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev); |
de8650a8 | 1529 | INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work); |
b431302e TT |
1530 | if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert)) |
1531 | set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state); | |
2451da08 | 1532 | if (mlx5_ipsec_device_caps(c->priv->mdev)) |
2ac9cfe7 | 1533 | set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state); |
5af75c74 MM |
1534 | if (param->is_mpw) |
1535 | set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state); | |
579524c6 | 1536 | sq->stop_room = param->stop_room; |
183532b7 | 1537 | sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev); |
f10b7cc7 | 1538 | |
231243c8 | 1539 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
ddf385e3 | 1540 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); |
f62b8bb8 | 1541 | if (err) |
aff26157 | 1542 | return err; |
ddf385e3 | 1543 | wq->db = &wq->db[MLX5_SND_DBR]; |
f62b8bb8 | 1544 | |
231243c8 | 1545 | err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu)); |
7ec0bb22 | 1546 | if (err) |
f62b8bb8 AV |
1547 | goto err_sq_wq_destroy; |
1548 | ||
cbce4f44 TG |
1549 | INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work); |
1550 | sq->dim.mode = params->tx_cq_moderation.cq_period_mode; | |
1551 | ||
f62b8bb8 AV |
1552 | return 0; |
1553 | ||
1554 | err_sq_wq_destroy: | |
1555 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1556 | ||
f62b8bb8 AV |
1557 | return err; |
1558 | } | |
1559 | ||
145e5637 | 1560 | void mlx5e_free_txqsq(struct mlx5e_txqsq *sq) |
f62b8bb8 | 1561 | { |
31391048 | 1562 | mlx5e_free_txqsq_db(sq); |
f62b8bb8 | 1563 | mlx5_wq_destroy(&sq->wq_ctrl); |
f62b8bb8 AV |
1564 | } |
1565 | ||
a43b25da | 1566 | static int mlx5e_create_sq(struct mlx5_core_dev *mdev, |
33ad9711 SM |
1567 | struct mlx5e_sq_param *param, |
1568 | struct mlx5e_create_sq_param *csp, | |
1569 | u32 *sqn) | |
f62b8bb8 | 1570 | { |
432119de | 1571 | u8 ts_format; |
f62b8bb8 AV |
1572 | void *in; |
1573 | void *sqc; | |
1574 | void *wq; | |
1575 | int inlen; | |
1576 | int err; | |
1577 | ||
1578 | inlen = MLX5_ST_SZ_BYTES(create_sq_in) + | |
33ad9711 | 1579 | sizeof(u64) * csp->wq_ctrl->buf.npages; |
1b9a07ee | 1580 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
1581 | if (!in) |
1582 | return -ENOMEM; | |
1583 | ||
432119de | 1584 | ts_format = mlx5_is_real_time_sq(mdev) ? |
9a1ac95a AL |
1585 | MLX5_TIMESTAMP_FORMAT_REAL_TIME : |
1586 | MLX5_TIMESTAMP_FORMAT_FREE_RUNNING; | |
f62b8bb8 AV |
1587 | sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); |
1588 | wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1589 | ||
1590 | memcpy(sqc, param->sqc, sizeof(param->sqc)); | |
33ad9711 SM |
1591 | MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz); |
1592 | MLX5_SET(sqc, sqc, tis_num_0, csp->tisn); | |
1593 | MLX5_SET(sqc, sqc, cqn, csp->cqn); | |
1880bc4e | 1594 | MLX5_SET(sqc, sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn); |
432119de AL |
1595 | MLX5_SET(sqc, sqc, ts_format, ts_format); |
1596 | ||
a6f402e4 SM |
1597 | |
1598 | if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) | |
33ad9711 | 1599 | MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode); |
a6f402e4 | 1600 | |
33ad9711 | 1601 | MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); |
db75373c | 1602 | MLX5_SET(sqc, sqc, flush_in_error_en, 1); |
f62b8bb8 AV |
1603 | |
1604 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
c276aae8 | 1605 | MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.hw_objs.bfreg.index); |
33ad9711 | 1606 | MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift - |
68cdf5d6 | 1607 | MLX5_ADAPTER_PAGE_SHIFT); |
33ad9711 | 1608 | MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma); |
f62b8bb8 | 1609 | |
3a2f7033 TT |
1610 | mlx5_fill_page_frag_array(&csp->wq_ctrl->buf, |
1611 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
f62b8bb8 | 1612 | |
33ad9711 | 1613 | err = mlx5_core_create_sq(mdev, in, inlen, sqn); |
f62b8bb8 AV |
1614 | |
1615 | kvfree(in); | |
1616 | ||
1617 | return err; | |
1618 | } | |
1619 | ||
de8650a8 EBE |
1620 | int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, |
1621 | struct mlx5e_modify_sq_param *p) | |
f62b8bb8 | 1622 | { |
214baf22 | 1623 | u64 bitmask = 0; |
f62b8bb8 AV |
1624 | void *in; |
1625 | void *sqc; | |
1626 | int inlen; | |
1627 | int err; | |
1628 | ||
1629 | inlen = MLX5_ST_SZ_BYTES(modify_sq_in); | |
1b9a07ee | 1630 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
1631 | if (!in) |
1632 | return -ENOMEM; | |
1633 | ||
1634 | sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); | |
1635 | ||
33ad9711 SM |
1636 | MLX5_SET(modify_sq_in, in, sq_state, p->curr_state); |
1637 | MLX5_SET(sqc, sqc, state, p->next_state); | |
1638 | if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) { | |
214baf22 MM |
1639 | bitmask |= 1; |
1640 | MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index); | |
507f0c81 | 1641 | } |
214baf22 MM |
1642 | if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) { |
1643 | bitmask |= 1 << 2; | |
1644 | MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id); | |
1645 | } | |
1646 | MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask); | |
f62b8bb8 | 1647 | |
e0b4b472 | 1648 | err = mlx5_core_modify_sq(mdev, sqn, in); |
f62b8bb8 AV |
1649 | |
1650 | kvfree(in); | |
1651 | ||
1652 | return err; | |
1653 | } | |
1654 | ||
a43b25da | 1655 | static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn) |
33ad9711 | 1656 | { |
a43b25da | 1657 | mlx5_core_destroy_sq(mdev, sqn); |
f62b8bb8 AV |
1658 | } |
1659 | ||
145e5637 EBE |
1660 | int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, |
1661 | struct mlx5e_sq_param *param, | |
1662 | struct mlx5e_create_sq_param *csp, | |
214baf22 | 1663 | u16 qos_queue_group_id, |
145e5637 | 1664 | u32 *sqn) |
f62b8bb8 | 1665 | { |
33ad9711 | 1666 | struct mlx5e_modify_sq_param msp = {0}; |
31391048 SM |
1667 | int err; |
1668 | ||
a43b25da | 1669 | err = mlx5e_create_sq(mdev, param, csp, sqn); |
31391048 SM |
1670 | if (err) |
1671 | return err; | |
1672 | ||
1673 | msp.curr_state = MLX5_SQC_STATE_RST; | |
1674 | msp.next_state = MLX5_SQC_STATE_RDY; | |
214baf22 MM |
1675 | if (qos_queue_group_id) { |
1676 | msp.qos_update = true; | |
1677 | msp.qos_queue_group_id = qos_queue_group_id; | |
1678 | } | |
a43b25da | 1679 | err = mlx5e_modify_sq(mdev, *sqn, &msp); |
31391048 | 1680 | if (err) |
a43b25da | 1681 | mlx5e_destroy_sq(mdev, *sqn); |
31391048 SM |
1682 | |
1683 | return err; | |
1684 | } | |
1685 | ||
7f859ecf SM |
1686 | static int mlx5e_set_sq_maxrate(struct net_device *dev, |
1687 | struct mlx5e_txqsq *sq, u32 rate); | |
1688 | ||
214baf22 MM |
1689 | int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix, |
1690 | struct mlx5e_params *params, struct mlx5e_sq_param *param, | |
e0ee6891 TT |
1691 | struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, |
1692 | struct mlx5e_sq_stats *sq_stats) | |
31391048 SM |
1693 | { |
1694 | struct mlx5e_create_sq_param csp = {}; | |
7f859ecf | 1695 | u32 tx_rate; |
f62b8bb8 AV |
1696 | int err; |
1697 | ||
05909bab | 1698 | err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc); |
f62b8bb8 AV |
1699 | if (err) |
1700 | return err; | |
1701 | ||
e0ee6891 | 1702 | sq->stats = sq_stats; |
214baf22 | 1703 | |
a43b25da | 1704 | csp.tisn = tisn; |
31391048 | 1705 | csp.tis_lst_sz = 1; |
33ad9711 SM |
1706 | csp.cqn = sq->cq.mcq.cqn; |
1707 | csp.wq_ctrl = &sq->wq_ctrl; | |
1708 | csp.min_inline_mode = sq->min_inline_mode; | |
214baf22 | 1709 | err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn); |
f62b8bb8 | 1710 | if (err) |
31391048 | 1711 | goto err_free_txqsq; |
f62b8bb8 | 1712 | |
a43b25da | 1713 | tx_rate = c->priv->tx_rates[sq->txq_ix]; |
7f859ecf | 1714 | if (tx_rate) |
a43b25da | 1715 | mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate); |
7f859ecf | 1716 | |
cbce4f44 | 1717 | if (params->tx_dim_enabled) |
2b5bd5b1 | 1718 | sq->state |= BIT(MLX5E_SQ_STATE_DIM); |
cbce4f44 | 1719 | |
f62b8bb8 AV |
1720 | return 0; |
1721 | ||
31391048 | 1722 | err_free_txqsq: |
31391048 | 1723 | mlx5e_free_txqsq(sq); |
f62b8bb8 AV |
1724 | |
1725 | return err; | |
1726 | } | |
1727 | ||
de8650a8 | 1728 | void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq) |
acc6c595 | 1729 | { |
4ad40d8e | 1730 | sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix); |
acc6c595 SM |
1731 | set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
1732 | netdev_tx_reset_queue(sq->txq); | |
1733 | netif_tx_start_queue(sq->txq); | |
1734 | } | |
1735 | ||
de8650a8 | 1736 | void mlx5e_tx_disable_queue(struct netdev_queue *txq) |
f62b8bb8 AV |
1737 | { |
1738 | __netif_tx_lock_bh(txq); | |
1739 | netif_tx_stop_queue(txq); | |
1740 | __netif_tx_unlock_bh(txq); | |
1741 | } | |
1742 | ||
145e5637 | 1743 | void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq) |
f62b8bb8 | 1744 | { |
ddf385e3 | 1745 | struct mlx5_wq_cyc *wq = &sq->wq; |
33ad9711 | 1746 | |
c0f1147d | 1747 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
4d6e6b0c | 1748 | synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */ |
29429f33 | 1749 | |
de8650a8 | 1750 | mlx5e_tx_disable_queue(sq->txq); |
f62b8bb8 | 1751 | |
31391048 | 1752 | /* last doorbell out, godspeed .. */ |
ddf385e3 TT |
1753 | if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) { |
1754 | u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); | |
31391048 | 1755 | struct mlx5e_tx_wqe *nop; |
864b2d71 | 1756 | |
41a8e4eb TT |
1757 | sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) { |
1758 | .num_wqebbs = 1, | |
1759 | }; | |
0c258dec | 1760 | |
ddf385e3 TT |
1761 | nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc); |
1762 | mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl); | |
29429f33 | 1763 | } |
acc6c595 SM |
1764 | } |
1765 | ||
214baf22 | 1766 | void mlx5e_close_txqsq(struct mlx5e_txqsq *sq) |
acc6c595 | 1767 | { |
4ad40d8e | 1768 | struct mlx5_core_dev *mdev = sq->mdev; |
05d3ac97 | 1769 | struct mlx5_rate_limit rl = {0}; |
f62b8bb8 | 1770 | |
fa2bf86b | 1771 | cancel_work_sync(&sq->dim.work); |
de8650a8 | 1772 | cancel_work_sync(&sq->recover_work); |
a43b25da | 1773 | mlx5e_destroy_sq(mdev, sq->sqn); |
05d3ac97 BW |
1774 | if (sq->rate_limit) { |
1775 | rl.rate = sq->rate_limit; | |
1776 | mlx5_rl_remove_rate(mdev, &rl); | |
1777 | } | |
31391048 SM |
1778 | mlx5e_free_txqsq_descs(sq); |
1779 | mlx5e_free_txqsq(sq); | |
1780 | } | |
1781 | ||
145e5637 | 1782 | void mlx5e_tx_err_cqe_work(struct work_struct *recover_work) |
db75373c | 1783 | { |
de8650a8 EBE |
1784 | struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq, |
1785 | recover_work); | |
30e5c2c6 | 1786 | |
06293ae4 | 1787 | mlx5e_reporter_tx_err_cqe(sq); |
db75373c EBE |
1788 | } |
1789 | ||
19c4aba2 MM |
1790 | static int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params, |
1791 | struct mlx5e_sq_param *param, struct mlx5e_icosq *sq, | |
1792 | work_func_t recover_work_func) | |
31391048 SM |
1793 | { |
1794 | struct mlx5e_create_sq_param csp = {}; | |
1795 | int err; | |
1796 | ||
19c4aba2 | 1797 | err = mlx5e_alloc_icosq(c, param, sq, recover_work_func); |
31391048 SM |
1798 | if (err) |
1799 | return err; | |
1800 | ||
1801 | csp.cqn = sq->cq.mcq.cqn; | |
1802 | csp.wq_ctrl = &sq->wq_ctrl; | |
6a9764ef | 1803 | csp.min_inline_mode = params->tx_min_inline_mode; |
214baf22 | 1804 | err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn); |
31391048 SM |
1805 | if (err) |
1806 | goto err_free_icosq; | |
1807 | ||
e9ce991b TT |
1808 | if (param->is_tls) { |
1809 | sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list(); | |
1810 | if (IS_ERR(sq->ktls_resync)) { | |
1811 | err = PTR_ERR(sq->ktls_resync); | |
1812 | goto err_destroy_icosq; | |
1813 | } | |
1814 | } | |
31391048 SM |
1815 | return 0; |
1816 | ||
e9ce991b TT |
1817 | err_destroy_icosq: |
1818 | mlx5e_destroy_sq(c->mdev, sq->sqn); | |
31391048 | 1819 | err_free_icosq: |
31391048 SM |
1820 | mlx5e_free_icosq(sq); |
1821 | ||
1822 | return err; | |
1823 | } | |
1824 | ||
be5323c8 | 1825 | void mlx5e_activate_icosq(struct mlx5e_icosq *icosq) |
31391048 | 1826 | { |
9d18b514 AL |
1827 | set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state); |
1828 | } | |
31391048 | 1829 | |
be5323c8 | 1830 | void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq) |
9d18b514 | 1831 | { |
9d18b514 | 1832 | clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state); |
4d6e6b0c | 1833 | synchronize_net(); /* Sync with NAPI. */ |
9d18b514 AL |
1834 | } |
1835 | ||
19c4aba2 | 1836 | static void mlx5e_close_icosq(struct mlx5e_icosq *sq) |
9d18b514 AL |
1837 | { |
1838 | struct mlx5e_channel *c = sq->channel; | |
31391048 | 1839 | |
e9ce991b TT |
1840 | if (sq->ktls_resync) |
1841 | mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync); | |
a43b25da | 1842 | mlx5e_destroy_sq(c->mdev, sq->sqn); |
1182f365 | 1843 | mlx5e_free_icosq_descs(sq); |
31391048 SM |
1844 | mlx5e_free_icosq(sq); |
1845 | } | |
1846 | ||
db05815b | 1847 | int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, |
1742b3d5 | 1848 | struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, |
db05815b | 1849 | struct mlx5e_xdpsq *sq, bool is_redirect) |
31391048 | 1850 | { |
31391048 | 1851 | struct mlx5e_create_sq_param csp = {}; |
31391048 | 1852 | int err; |
31391048 | 1853 | |
1742b3d5 | 1854 | err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect); |
31391048 SM |
1855 | if (err) |
1856 | return err; | |
1857 | ||
1858 | csp.tis_lst_sz = 1; | |
45f171b1 | 1859 | csp.tisn = c->priv->tisn[c->lag_port][0]; /* tc = 0 */ |
31391048 SM |
1860 | csp.cqn = sq->cq.mcq.cqn; |
1861 | csp.wq_ctrl = &sq->wq_ctrl; | |
1862 | csp.min_inline_mode = sq->min_inline_mode; | |
1863 | set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
9ded70fa | 1864 | |
c1783e74 | 1865 | if (param->is_xdp_mb) |
9ded70fa MM |
1866 | set_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state); |
1867 | ||
214baf22 | 1868 | err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn); |
31391048 SM |
1869 | if (err) |
1870 | goto err_free_xdpsq; | |
1871 | ||
5e0d2eef TT |
1872 | mlx5e_set_xmit_fp(sq, param->is_mpw); |
1873 | ||
9ded70fa | 1874 | if (!param->is_mpw && !test_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state)) { |
08c34e95 | 1875 | unsigned int ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT + 1; |
5e0d2eef TT |
1876 | unsigned int inline_hdr_sz = 0; |
1877 | int i; | |
31391048 | 1878 | |
5e0d2eef TT |
1879 | if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { |
1880 | inline_hdr_sz = MLX5E_XDP_MIN_INLINE; | |
1881 | ds_cnt++; | |
1882 | } | |
1883 | ||
1884 | /* Pre initialize fixed WQE fields */ | |
1885 | for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) { | |
5e0d2eef TT |
1886 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i); |
1887 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
1888 | struct mlx5_wqe_eth_seg *eseg = &wqe->eth; | |
31391048 | 1889 | |
41a8e4eb TT |
1890 | sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) { |
1891 | .num_wqebbs = 1, | |
1892 | .num_pkts = 1, | |
1893 | }; | |
1894 | ||
5e0d2eef TT |
1895 | cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt); |
1896 | eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz); | |
5e0d2eef | 1897 | } |
31391048 SM |
1898 | } |
1899 | ||
1900 | return 0; | |
1901 | ||
1902 | err_free_xdpsq: | |
1903 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1904 | mlx5e_free_xdpsq(sq); | |
1905 | ||
1906 | return err; | |
1907 | } | |
1908 | ||
db05815b | 1909 | void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq) |
31391048 SM |
1910 | { |
1911 | struct mlx5e_channel *c = sq->channel; | |
1912 | ||
1913 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
4d6e6b0c | 1914 | synchronize_net(); /* Sync with NAPI. */ |
31391048 | 1915 | |
a43b25da | 1916 | mlx5e_destroy_sq(c->mdev, sq->sqn); |
b9673cf5 | 1917 | mlx5e_free_xdpsq_descs(sq); |
31391048 | 1918 | mlx5e_free_xdpsq(sq); |
f62b8bb8 AV |
1919 | } |
1920 | ||
4d0b7ef9 | 1921 | static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv, |
95b6c6a5 EBE |
1922 | struct mlx5e_cq_param *param, |
1923 | struct mlx5e_cq *cq) | |
f62b8bb8 | 1924 | { |
4d0b7ef9 | 1925 | struct mlx5_core_dev *mdev = priv->mdev; |
f62b8bb8 | 1926 | struct mlx5_core_cq *mcq = &cq->mcq; |
f62b8bb8 AV |
1927 | int err; |
1928 | u32 i; | |
1929 | ||
f62b8bb8 AV |
1930 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, |
1931 | &cq->wq_ctrl); | |
1932 | if (err) | |
1933 | return err; | |
1934 | ||
f62b8bb8 AV |
1935 | mcq->cqe_sz = 64; |
1936 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
1937 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
1938 | *mcq->set_ci_db = 0; | |
1939 | *mcq->arm_db = 0; | |
1940 | mcq->vector = param->eq_ix; | |
1941 | mcq->comp = mlx5e_completion_event; | |
1942 | mcq->event = mlx5e_cq_error_event; | |
f62b8bb8 AV |
1943 | |
1944 | for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { | |
1945 | struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); | |
1946 | ||
1947 | cqe->op_own = 0xf1; | |
2c925db0 | 1948 | cqe->validity_iteration_count = 0xff; |
f62b8bb8 AV |
1949 | } |
1950 | ||
a43b25da | 1951 | cq->mdev = mdev; |
4d0b7ef9 AL |
1952 | cq->netdev = priv->netdev; |
1953 | cq->priv = priv; | |
f62b8bb8 AV |
1954 | |
1955 | return 0; | |
1956 | } | |
1957 | ||
4d0b7ef9 | 1958 | static int mlx5e_alloc_cq(struct mlx5e_priv *priv, |
95b6c6a5 | 1959 | struct mlx5e_cq_param *param, |
4d0b7ef9 | 1960 | struct mlx5e_create_cq_param *ccp, |
95b6c6a5 EBE |
1961 | struct mlx5e_cq *cq) |
1962 | { | |
95b6c6a5 EBE |
1963 | int err; |
1964 | ||
4d0b7ef9 AL |
1965 | param->wq.buf_numa_node = ccp->node; |
1966 | param->wq.db_numa_node = ccp->node; | |
1967 | param->eq_ix = ccp->ix; | |
95b6c6a5 | 1968 | |
4d0b7ef9 | 1969 | err = mlx5e_alloc_cq_common(priv, param, cq); |
95b6c6a5 | 1970 | |
4d0b7ef9 AL |
1971 | cq->napi = ccp->napi; |
1972 | cq->ch_stats = ccp->ch_stats; | |
95b6c6a5 EBE |
1973 | |
1974 | return err; | |
1975 | } | |
1976 | ||
3b77235b | 1977 | static void mlx5e_free_cq(struct mlx5e_cq *cq) |
f62b8bb8 | 1978 | { |
3a2f7033 | 1979 | mlx5_wq_destroy(&cq->wq_ctrl); |
f62b8bb8 AV |
1980 | } |
1981 | ||
3b77235b | 1982 | static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) |
f62b8bb8 | 1983 | { |
38164b77 | 1984 | u32 out[MLX5_ST_SZ_DW(create_cq_out)]; |
a43b25da | 1985 | struct mlx5_core_dev *mdev = cq->mdev; |
f62b8bb8 AV |
1986 | struct mlx5_core_cq *mcq = &cq->mcq; |
1987 | ||
1988 | void *in; | |
1989 | void *cqc; | |
1990 | int inlen; | |
f62b8bb8 AV |
1991 | int eqn; |
1992 | int err; | |
1993 | ||
f14c1a14 | 1994 | err = mlx5_comp_eqn_get(mdev, param->eq_ix, &eqn); |
a1f240f1 YA |
1995 | if (err) |
1996 | return err; | |
1997 | ||
f62b8bb8 | 1998 | inlen = MLX5_ST_SZ_BYTES(create_cq_in) + |
3a2f7033 | 1999 | sizeof(u64) * cq->wq_ctrl.buf.npages; |
1b9a07ee | 2000 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
2001 | if (!in) |
2002 | return -ENOMEM; | |
2003 | ||
2004 | cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); | |
2005 | ||
2006 | memcpy(cqc, param->cqc, sizeof(param->cqc)); | |
2007 | ||
3a2f7033 | 2008 | mlx5_fill_page_frag_array(&cq->wq_ctrl.buf, |
1c1b5228 | 2009 | (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas)); |
f62b8bb8 | 2010 | |
9908aa29 | 2011 | MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode); |
616d5769 | 2012 | MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn); |
30aa60b3 | 2013 | MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index); |
3a2f7033 | 2014 | MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - |
68cdf5d6 | 2015 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
2016 | MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); |
2017 | ||
38164b77 | 2018 | err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out)); |
f62b8bb8 AV |
2019 | |
2020 | kvfree(in); | |
2021 | ||
2022 | if (err) | |
2023 | return err; | |
2024 | ||
2025 | mlx5e_cq_arm(cq); | |
2026 | ||
2027 | return 0; | |
2028 | } | |
2029 | ||
3b77235b | 2030 | static void mlx5e_destroy_cq(struct mlx5e_cq *cq) |
f62b8bb8 | 2031 | { |
a43b25da | 2032 | mlx5_core_destroy_cq(cq->mdev, &cq->mcq); |
f62b8bb8 AV |
2033 | } |
2034 | ||
4d0b7ef9 AL |
2035 | int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder, |
2036 | struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp, | |
2037 | struct mlx5e_cq *cq) | |
f62b8bb8 | 2038 | { |
4d0b7ef9 | 2039 | struct mlx5_core_dev *mdev = priv->mdev; |
f62b8bb8 | 2040 | int err; |
f62b8bb8 | 2041 | |
4d0b7ef9 | 2042 | err = mlx5e_alloc_cq(priv, param, ccp, cq); |
f62b8bb8 AV |
2043 | if (err) |
2044 | return err; | |
2045 | ||
3b77235b | 2046 | err = mlx5e_create_cq(cq, param); |
f62b8bb8 | 2047 | if (err) |
3b77235b | 2048 | goto err_free_cq; |
f62b8bb8 | 2049 | |
7524a5d8 | 2050 | if (MLX5_CAP_GEN(mdev, cq_moderation)) |
6a9764ef | 2051 | mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts); |
f62b8bb8 AV |
2052 | return 0; |
2053 | ||
3b77235b SM |
2054 | err_free_cq: |
2055 | mlx5e_free_cq(cq); | |
f62b8bb8 AV |
2056 | |
2057 | return err; | |
2058 | } | |
2059 | ||
db05815b | 2060 | void mlx5e_close_cq(struct mlx5e_cq *cq) |
f62b8bb8 | 2061 | { |
f62b8bb8 | 2062 | mlx5e_destroy_cq(cq); |
3b77235b | 2063 | mlx5e_free_cq(cq); |
f62b8bb8 AV |
2064 | } |
2065 | ||
f62b8bb8 | 2066 | static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, |
6a9764ef | 2067 | struct mlx5e_params *params, |
4d0b7ef9 | 2068 | struct mlx5e_create_cq_param *ccp, |
f62b8bb8 AV |
2069 | struct mlx5e_channel_param *cparam) |
2070 | { | |
f62b8bb8 AV |
2071 | int err; |
2072 | int tc; | |
2073 | ||
2074 | for (tc = 0; tc < c->num_tc; tc++) { | |
4d0b7ef9 AL |
2075 | err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp, |
2076 | ccp, &c->sq[tc].cq); | |
f62b8bb8 AV |
2077 | if (err) |
2078 | goto err_close_tx_cqs; | |
f62b8bb8 AV |
2079 | } |
2080 | ||
2081 | return 0; | |
2082 | ||
2083 | err_close_tx_cqs: | |
2084 | for (tc--; tc >= 0; tc--) | |
2085 | mlx5e_close_cq(&c->sq[tc].cq); | |
2086 | ||
2087 | return err; | |
2088 | } | |
2089 | ||
2090 | static void mlx5e_close_tx_cqs(struct mlx5e_channel *c) | |
2091 | { | |
2092 | int tc; | |
2093 | ||
2094 | for (tc = 0; tc < c->num_tc; tc++) | |
2095 | mlx5e_close_cq(&c->sq[tc].cq); | |
2096 | } | |
2097 | ||
80743c4f TT |
2098 | static int mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq *tc_to_txq, unsigned int txq) |
2099 | { | |
2100 | int tc; | |
2101 | ||
2102 | for (tc = 0; tc < TC_MAX_QUEUE; tc++) | |
2103 | if (txq - tc_to_txq[tc].offset < tc_to_txq[tc].count) | |
2104 | return tc; | |
2105 | ||
2106 | WARN(1, "Unexpected TCs configuration. No match found for txq %u", txq); | |
2107 | return -ENOENT; | |
2108 | } | |
2109 | ||
2110 | static int mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params *params, int txq_ix, | |
2111 | u32 *hw_id) | |
2112 | { | |
2113 | int tc; | |
2114 | ||
0bb7228f | 2115 | if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL) { |
80743c4f TT |
2116 | *hw_id = 0; |
2117 | return 0; | |
2118 | } | |
2119 | ||
2120 | tc = mlx5e_mqprio_txq_to_tc(params->mqprio.tc_to_txq, txq_ix); | |
2121 | if (tc < 0) | |
2122 | return tc; | |
2123 | ||
0bb7228f MT |
2124 | if (tc >= params->mqprio.num_tc) { |
2125 | WARN(1, "Unexpected TCs configuration. tc %d is out of range of %u", | |
2126 | tc, params->mqprio.num_tc); | |
2127 | return -EINVAL; | |
2128 | } | |
2129 | ||
2130 | *hw_id = params->mqprio.channel.hw_id[tc]; | |
2131 | return 0; | |
80743c4f TT |
2132 | } |
2133 | ||
f62b8bb8 | 2134 | static int mlx5e_open_sqs(struct mlx5e_channel *c, |
6a9764ef | 2135 | struct mlx5e_params *params, |
f62b8bb8 AV |
2136 | struct mlx5e_channel_param *cparam) |
2137 | { | |
694826e3 | 2138 | int err, tc; |
f62b8bb8 | 2139 | |
86d747a3 | 2140 | for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) { |
c55d8b10 | 2141 | int txq_ix = c->ix + tc * params->num_channels; |
80743c4f TT |
2142 | u32 qos_queue_group_id; |
2143 | ||
2144 | err = mlx5e_txq_get_qos_node_hw_id(params, txq_ix, &qos_queue_group_id); | |
2145 | if (err) | |
2146 | goto err_close_sqs; | |
acc6c595 | 2147 | |
45f171b1 | 2148 | err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix, |
80743c4f TT |
2149 | params, &cparam->txq_sq, &c->sq[tc], tc, |
2150 | qos_queue_group_id, | |
be98737a | 2151 | &c->priv->channel_stats[c->ix]->sq[tc]); |
f62b8bb8 AV |
2152 | if (err) |
2153 | goto err_close_sqs; | |
2154 | } | |
2155 | ||
2156 | return 0; | |
2157 | ||
2158 | err_close_sqs: | |
2159 | for (tc--; tc >= 0; tc--) | |
31391048 | 2160 | mlx5e_close_txqsq(&c->sq[tc]); |
f62b8bb8 AV |
2161 | |
2162 | return err; | |
2163 | } | |
2164 | ||
2165 | static void mlx5e_close_sqs(struct mlx5e_channel *c) | |
2166 | { | |
2167 | int tc; | |
2168 | ||
2169 | for (tc = 0; tc < c->num_tc; tc++) | |
31391048 | 2170 | mlx5e_close_txqsq(&c->sq[tc]); |
f62b8bb8 AV |
2171 | } |
2172 | ||
507f0c81 | 2173 | static int mlx5e_set_sq_maxrate(struct net_device *dev, |
31391048 | 2174 | struct mlx5e_txqsq *sq, u32 rate) |
507f0c81 YP |
2175 | { |
2176 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2177 | struct mlx5_core_dev *mdev = priv->mdev; | |
33ad9711 | 2178 | struct mlx5e_modify_sq_param msp = {0}; |
05d3ac97 | 2179 | struct mlx5_rate_limit rl = {0}; |
507f0c81 YP |
2180 | u16 rl_index = 0; |
2181 | int err; | |
2182 | ||
2183 | if (rate == sq->rate_limit) | |
2184 | /* nothing to do */ | |
2185 | return 0; | |
2186 | ||
05d3ac97 BW |
2187 | if (sq->rate_limit) { |
2188 | rl.rate = sq->rate_limit; | |
507f0c81 | 2189 | /* remove current rl index to free space to next ones */ |
05d3ac97 BW |
2190 | mlx5_rl_remove_rate(mdev, &rl); |
2191 | } | |
507f0c81 YP |
2192 | |
2193 | sq->rate_limit = 0; | |
2194 | ||
2195 | if (rate) { | |
05d3ac97 BW |
2196 | rl.rate = rate; |
2197 | err = mlx5_rl_add_rate(mdev, &rl_index, &rl); | |
507f0c81 YP |
2198 | if (err) { |
2199 | netdev_err(dev, "Failed configuring rate %u: %d\n", | |
2200 | rate, err); | |
2201 | return err; | |
2202 | } | |
2203 | } | |
2204 | ||
33ad9711 SM |
2205 | msp.curr_state = MLX5_SQC_STATE_RDY; |
2206 | msp.next_state = MLX5_SQC_STATE_RDY; | |
2207 | msp.rl_index = rl_index; | |
2208 | msp.rl_update = true; | |
a43b25da | 2209 | err = mlx5e_modify_sq(mdev, sq->sqn, &msp); |
507f0c81 YP |
2210 | if (err) { |
2211 | netdev_err(dev, "Failed configuring rate %u: %d\n", | |
2212 | rate, err); | |
2213 | /* remove the rate from the table */ | |
2214 | if (rate) | |
05d3ac97 | 2215 | mlx5_rl_remove_rate(mdev, &rl); |
507f0c81 YP |
2216 | return err; |
2217 | } | |
2218 | ||
2219 | sq->rate_limit = rate; | |
2220 | return 0; | |
2221 | } | |
2222 | ||
2223 | static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate) | |
2224 | { | |
2225 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2226 | struct mlx5_core_dev *mdev = priv->mdev; | |
acc6c595 | 2227 | struct mlx5e_txqsq *sq = priv->txq2sq[index]; |
507f0c81 YP |
2228 | int err = 0; |
2229 | ||
2230 | if (!mlx5_rl_is_supported(mdev)) { | |
2231 | netdev_err(dev, "Rate limiting is not supported on this device\n"); | |
2232 | return -EINVAL; | |
2233 | } | |
2234 | ||
2235 | /* rate is given in Mb/sec, HW config is in Kb/sec */ | |
2236 | rate = rate << 10; | |
2237 | ||
2238 | /* Check whether rate in valid range, 0 is always valid */ | |
2239 | if (rate && !mlx5_rl_is_in_range(mdev, rate)) { | |
2240 | netdev_err(dev, "TX rate %u, is not in range\n", rate); | |
2241 | return -ERANGE; | |
2242 | } | |
2243 | ||
2244 | mutex_lock(&priv->state_lock); | |
2245 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
2246 | err = mlx5e_set_sq_maxrate(dev, sq, rate); | |
2247 | if (!err) | |
2248 | priv->tx_rates[index] = rate; | |
2249 | mutex_unlock(&priv->state_lock); | |
2250 | ||
2251 | return err; | |
2252 | } | |
2253 | ||
869c5f92 AL |
2254 | static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params, |
2255 | struct mlx5e_rq_param *rq_params) | |
2256 | { | |
2257 | int err; | |
2258 | ||
4e7401fc | 2259 | err = mlx5e_init_rxq_rq(c, params, rq_params->xdp_frag_size, &c->rq); |
869c5f92 AL |
2260 | if (err) |
2261 | return err; | |
2262 | ||
2263 | return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq); | |
2264 | } | |
2265 | ||
0a06382f MM |
2266 | static int mlx5e_open_queues(struct mlx5e_channel *c, |
2267 | struct mlx5e_params *params, | |
2268 | struct mlx5e_channel_param *cparam) | |
f62b8bb8 | 2269 | { |
8960b389 | 2270 | struct dim_cq_moder icocq_moder = {0, 0}; |
2f6b379c | 2271 | struct mlx5e_create_cq_param ccp; |
f62b8bb8 | 2272 | int err; |
f62b8bb8 | 2273 | |
2f6b379c | 2274 | mlx5e_build_create_cq_param(&ccp, c); |
4d0b7ef9 | 2275 | |
ebf79b6b | 2276 | err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp, |
4d0b7ef9 | 2277 | &c->async_icosq.cq); |
f62b8bb8 | 2278 | if (err) |
0a06382f | 2279 | return err; |
f62b8bb8 | 2280 | |
ebf79b6b | 2281 | err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp, |
4d0b7ef9 | 2282 | &c->icosq.cq); |
8d94b590 TT |
2283 | if (err) |
2284 | goto err_close_async_icosq_cq; | |
2285 | ||
4d0b7ef9 | 2286 | err = mlx5e_open_tx_cqs(c, params, &ccp, cparam); |
d3c9bc27 TT |
2287 | if (err) |
2288 | goto err_close_icosq_cq; | |
2289 | ||
4d0b7ef9 AL |
2290 | err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp, |
2291 | &c->xdpsq.cq); | |
f62b8bb8 AV |
2292 | if (err) |
2293 | goto err_close_tx_cqs; | |
f62b8bb8 | 2294 | |
4d0b7ef9 AL |
2295 | err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp, |
2296 | &c->rq.cq); | |
58b99ee3 TT |
2297 | if (err) |
2298 | goto err_close_xdp_tx_cqs; | |
2299 | ||
4d0b7ef9 AL |
2300 | err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, |
2301 | &ccp, &c->rq_xdpsq.cq) : 0; | |
d7a0ecab SM |
2302 | if (err) |
2303 | goto err_close_rx_cq; | |
2304 | ||
8d94b590 TT |
2305 | spin_lock_init(&c->async_icosq_lock); |
2306 | ||
19c4aba2 MM |
2307 | err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq, |
2308 | mlx5e_async_icosq_err_cqe_work); | |
f62b8bb8 | 2309 | if (err) |
7637e499 | 2310 | goto err_close_xdpsq_cq; |
f62b8bb8 | 2311 | |
17958d7c MM |
2312 | mutex_init(&c->icosq_recovery_lock); |
2313 | ||
19c4aba2 MM |
2314 | err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq, |
2315 | mlx5e_icosq_err_cqe_work); | |
8d94b590 TT |
2316 | if (err) |
2317 | goto err_close_async_icosq; | |
2318 | ||
6a9764ef | 2319 | err = mlx5e_open_sqs(c, params, cparam); |
d3c9bc27 TT |
2320 | if (err) |
2321 | goto err_close_icosq; | |
2322 | ||
8ba3e4c8 MM |
2323 | err = mlx5e_open_rxq_rq(c, params, &cparam->rq); |
2324 | if (err) | |
2325 | goto err_close_sqs; | |
2326 | ||
b9673cf5 | 2327 | if (c->xdp) { |
db05815b | 2328 | err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, |
b9673cf5 MM |
2329 | &c->rq_xdpsq, false); |
2330 | if (err) | |
8ba3e4c8 | 2331 | goto err_close_rq; |
b9673cf5 | 2332 | } |
b5503b99 | 2333 | |
db05815b | 2334 | err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true); |
58b99ee3 | 2335 | if (err) |
8ba3e4c8 | 2336 | goto err_close_xdp_sq; |
58b99ee3 | 2337 | |
f62b8bb8 | 2338 | return 0; |
58b99ee3 | 2339 | |
b5503b99 | 2340 | err_close_xdp_sq: |
d7a0ecab | 2341 | if (c->xdp) |
b9673cf5 | 2342 | mlx5e_close_xdpsq(&c->rq_xdpsq); |
f62b8bb8 | 2343 | |
8ba3e4c8 MM |
2344 | err_close_rq: |
2345 | mlx5e_close_rq(&c->rq); | |
2346 | ||
f62b8bb8 AV |
2347 | err_close_sqs: |
2348 | mlx5e_close_sqs(c); | |
2349 | ||
d3c9bc27 | 2350 | err_close_icosq: |
31391048 | 2351 | mlx5e_close_icosq(&c->icosq); |
d3c9bc27 | 2352 | |
8d94b590 TT |
2353 | err_close_async_icosq: |
2354 | mlx5e_close_icosq(&c->async_icosq); | |
2355 | ||
7637e499 | 2356 | err_close_xdpsq_cq: |
d7a0ecab | 2357 | if (c->xdp) |
b9673cf5 | 2358 | mlx5e_close_cq(&c->rq_xdpsq.cq); |
d7a0ecab SM |
2359 | |
2360 | err_close_rx_cq: | |
f62b8bb8 AV |
2361 | mlx5e_close_cq(&c->rq.cq); |
2362 | ||
58b99ee3 TT |
2363 | err_close_xdp_tx_cqs: |
2364 | mlx5e_close_cq(&c->xdpsq.cq); | |
2365 | ||
f62b8bb8 AV |
2366 | err_close_tx_cqs: |
2367 | mlx5e_close_tx_cqs(c); | |
2368 | ||
d3c9bc27 TT |
2369 | err_close_icosq_cq: |
2370 | mlx5e_close_cq(&c->icosq.cq); | |
2371 | ||
8d94b590 TT |
2372 | err_close_async_icosq_cq: |
2373 | mlx5e_close_cq(&c->async_icosq.cq); | |
2374 | ||
0a06382f MM |
2375 | return err; |
2376 | } | |
2377 | ||
2378 | static void mlx5e_close_queues(struct mlx5e_channel *c) | |
2379 | { | |
2380 | mlx5e_close_xdpsq(&c->xdpsq); | |
0a06382f MM |
2381 | if (c->xdp) |
2382 | mlx5e_close_xdpsq(&c->rq_xdpsq); | |
17958d7c MM |
2383 | /* The same ICOSQ is used for UMRs for both RQ and XSKRQ. */ |
2384 | cancel_work_sync(&c->icosq.recover_work); | |
8ba3e4c8 | 2385 | mlx5e_close_rq(&c->rq); |
0a06382f MM |
2386 | mlx5e_close_sqs(c); |
2387 | mlx5e_close_icosq(&c->icosq); | |
17958d7c | 2388 | mutex_destroy(&c->icosq_recovery_lock); |
8d94b590 | 2389 | mlx5e_close_icosq(&c->async_icosq); |
0a06382f MM |
2390 | if (c->xdp) |
2391 | mlx5e_close_cq(&c->rq_xdpsq.cq); | |
2392 | mlx5e_close_cq(&c->rq.cq); | |
2393 | mlx5e_close_cq(&c->xdpsq.cq); | |
2394 | mlx5e_close_tx_cqs(c); | |
2395 | mlx5e_close_cq(&c->icosq.cq); | |
8d94b590 | 2396 | mlx5e_close_cq(&c->async_icosq.cq); |
0a06382f MM |
2397 | } |
2398 | ||
45f171b1 MM |
2399 | static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix) |
2400 | { | |
2401 | u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id); | |
2402 | ||
2403 | return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev); | |
2404 | } | |
2405 | ||
fa691d0c LK |
2406 | static int mlx5e_channel_stats_alloc(struct mlx5e_priv *priv, int ix, int cpu) |
2407 | { | |
2408 | if (ix > priv->stats_nch) { | |
2409 | netdev_warn(priv->netdev, "Unexpected channel stats index %d > %d\n", ix, | |
2410 | priv->stats_nch); | |
2411 | return -EINVAL; | |
2412 | } | |
2413 | ||
2414 | if (priv->channel_stats[ix]) | |
2415 | return 0; | |
2416 | ||
2417 | /* Asymmetric dynamic memory allocation. | |
2418 | * Freed in mlx5e_priv_arrays_free, not on channel closure. | |
2419 | */ | |
559f4c32 | 2420 | netdev_dbg(priv->netdev, "Creating channel stats %d\n", ix); |
fa691d0c LK |
2421 | priv->channel_stats[ix] = kvzalloc_node(sizeof(**priv->channel_stats), |
2422 | GFP_KERNEL, cpu_to_node(cpu)); | |
2423 | if (!priv->channel_stats[ix]) | |
2424 | return -ENOMEM; | |
2425 | priv->stats_nch++; | |
2426 | ||
2427 | return 0; | |
2428 | } | |
2429 | ||
2e642afb MM |
2430 | void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c) |
2431 | { | |
2432 | spin_lock_bh(&c->async_icosq_lock); | |
2433 | mlx5e_trigger_irq(&c->async_icosq); | |
2434 | spin_unlock_bh(&c->async_icosq_lock); | |
2435 | } | |
2436 | ||
2437 | void mlx5e_trigger_napi_sched(struct napi_struct *napi) | |
2438 | { | |
2439 | local_bh_disable(); | |
2440 | napi_schedule(napi); | |
2441 | local_bh_enable(); | |
2442 | } | |
2443 | ||
0a06382f MM |
2444 | static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, |
2445 | struct mlx5e_params *params, | |
2446 | struct mlx5e_channel_param *cparam, | |
1742b3d5 | 2447 | struct xsk_buff_pool *xsk_pool, |
0a06382f MM |
2448 | struct mlx5e_channel **cp) |
2449 | { | |
f3147015 | 2450 | int cpu = mlx5_comp_vector_get_cpu(priv->mdev, ix); |
0a06382f | 2451 | struct net_device *netdev = priv->netdev; |
db05815b | 2452 | struct mlx5e_xsk_param xsk; |
0a06382f MM |
2453 | struct mlx5e_channel *c; |
2454 | unsigned int irq; | |
2455 | int err; | |
0a06382f | 2456 | |
f14c1a14 | 2457 | err = mlx5_comp_irqn_get(priv->mdev, ix, &irq); |
0a06382f MM |
2458 | if (err) |
2459 | return err; | |
2460 | ||
fa691d0c LK |
2461 | err = mlx5e_channel_stats_alloc(priv, ix, cpu); |
2462 | if (err) | |
2463 | return err; | |
2464 | ||
0a06382f MM |
2465 | c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu)); |
2466 | if (!c) | |
2467 | return -ENOMEM; | |
2468 | ||
2469 | c->priv = priv; | |
2470 | c->mdev = priv->mdev; | |
2471 | c->tstamp = &priv->tstamp; | |
2472 | c->ix = ix; | |
2473 | c->cpu = cpu; | |
7be3412a | 2474 | c->pdev = mlx5_core_dma_dev(priv->mdev); |
0a06382f | 2475 | c->netdev = priv->netdev; |
83fec3f1 | 2476 | c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey); |
86d747a3 | 2477 | c->num_tc = mlx5e_get_dcb_num_tc(params); |
0a06382f | 2478 | c->xdp = !!params->xdp_prog; |
be98737a | 2479 | c->stats = &priv->channel_stats[ix]->ch; |
ec7b37b6 | 2480 | c->aff_mask = irq_get_effective_affinity_mask(irq); |
45f171b1 | 2481 | c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix); |
0a06382f | 2482 | |
b48b89f9 | 2483 | netif_napi_add(netdev, &c->napi, mlx5e_napi_poll); |
0a06382f MM |
2484 | |
2485 | err = mlx5e_open_queues(c, params, cparam); | |
2486 | if (unlikely(err)) | |
2487 | goto err_napi_del; | |
2488 | ||
1742b3d5 MK |
2489 | if (xsk_pool) { |
2490 | mlx5e_build_xsk_param(xsk_pool, &xsk); | |
2491 | err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c); | |
db05815b MM |
2492 | if (unlikely(err)) |
2493 | goto err_close_queues; | |
2494 | } | |
2495 | ||
0a06382f MM |
2496 | *cp = c; |
2497 | ||
2498 | return 0; | |
2499 | ||
db05815b MM |
2500 | err_close_queues: |
2501 | mlx5e_close_queues(c); | |
2502 | ||
f62b8bb8 AV |
2503 | err_napi_del: |
2504 | netif_napi_del(&c->napi); | |
149e566f | 2505 | |
ca11b798 | 2506 | kvfree(c); |
f62b8bb8 AV |
2507 | |
2508 | return err; | |
2509 | } | |
2510 | ||
acc6c595 SM |
2511 | static void mlx5e_activate_channel(struct mlx5e_channel *c) |
2512 | { | |
2513 | int tc; | |
2514 | ||
7637e499 TT |
2515 | napi_enable(&c->napi); |
2516 | ||
acc6c595 SM |
2517 | for (tc = 0; tc < c->num_tc; tc++) |
2518 | mlx5e_activate_txqsq(&c->sq[tc]); | |
9d18b514 | 2519 | mlx5e_activate_icosq(&c->icosq); |
8d94b590 | 2520 | mlx5e_activate_icosq(&c->async_icosq); |
db05815b MM |
2521 | |
2522 | if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) | |
2523 | mlx5e_activate_xsk(c); | |
082a9edf MM |
2524 | else |
2525 | mlx5e_activate_rq(&c->rq); | |
acc6c595 SM |
2526 | } |
2527 | ||
2528 | static void mlx5e_deactivate_channel(struct mlx5e_channel *c) | |
2529 | { | |
2530 | int tc; | |
2531 | ||
db05815b MM |
2532 | if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) |
2533 | mlx5e_deactivate_xsk(c); | |
082a9edf MM |
2534 | else |
2535 | mlx5e_deactivate_rq(&c->rq); | |
db05815b | 2536 | |
8d94b590 | 2537 | mlx5e_deactivate_icosq(&c->async_icosq); |
9d18b514 | 2538 | mlx5e_deactivate_icosq(&c->icosq); |
acc6c595 SM |
2539 | for (tc = 0; tc < c->num_tc; tc++) |
2540 | mlx5e_deactivate_txqsq(&c->sq[tc]); | |
214baf22 | 2541 | mlx5e_qos_deactivate_queues(c); |
7637e499 TT |
2542 | |
2543 | napi_disable(&c->napi); | |
acc6c595 SM |
2544 | } |
2545 | ||
f62b8bb8 AV |
2546 | static void mlx5e_close_channel(struct mlx5e_channel *c) |
2547 | { | |
db05815b MM |
2548 | if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) |
2549 | mlx5e_close_xsk(c); | |
0a06382f | 2550 | mlx5e_close_queues(c); |
214baf22 | 2551 | mlx5e_qos_close_queues(c); |
f62b8bb8 | 2552 | netif_napi_del(&c->napi); |
7ae92ae5 | 2553 | |
ca11b798 | 2554 | kvfree(c); |
f62b8bb8 AV |
2555 | } |
2556 | ||
55c2503d SM |
2557 | int mlx5e_open_channels(struct mlx5e_priv *priv, |
2558 | struct mlx5e_channels *chs) | |
f62b8bb8 | 2559 | { |
6b87663f | 2560 | struct mlx5e_channel_param *cparam; |
03289b88 | 2561 | int err = -ENOMEM; |
f62b8bb8 | 2562 | int i; |
f62b8bb8 | 2563 | |
6a9764ef | 2564 | chs->num = chs->params.num_channels; |
03289b88 | 2565 | |
ff9c852f | 2566 | chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL); |
ca11b798 | 2567 | cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL); |
acc6c595 SM |
2568 | if (!chs->c || !cparam) |
2569 | goto err_free; | |
f62b8bb8 | 2570 | |
6980ffa0 TT |
2571 | err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam); |
2572 | if (err) | |
2573 | goto err_free; | |
2574 | ||
ff9c852f | 2575 | for (i = 0; i < chs->num; i++) { |
1742b3d5 | 2576 | struct xsk_buff_pool *xsk_pool = NULL; |
db05815b MM |
2577 | |
2578 | if (chs->params.xdp_prog) | |
1742b3d5 | 2579 | xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i); |
db05815b | 2580 | |
1742b3d5 | 2581 | err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]); |
f62b8bb8 AV |
2582 | if (err) |
2583 | goto err_close_channels; | |
2584 | } | |
2585 | ||
960fbfe2 | 2586 | if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) { |
b0d35de4 | 2587 | err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp); |
145e5637 EBE |
2588 | if (err) |
2589 | goto err_close_channels; | |
2590 | } | |
2591 | ||
28df4a01 MT |
2592 | if (priv->htb) { |
2593 | err = mlx5e_qos_open_queues(priv, chs); | |
2594 | if (err) | |
2595 | goto err_close_ptp; | |
2596 | } | |
214baf22 | 2597 | |
11af6a6d | 2598 | mlx5e_health_channels_update(priv); |
ca11b798 | 2599 | kvfree(cparam); |
f62b8bb8 AV |
2600 | return 0; |
2601 | ||
214baf22 | 2602 | err_close_ptp: |
b0d35de4 AL |
2603 | if (chs->ptp) |
2604 | mlx5e_ptp_close(chs->ptp); | |
214baf22 | 2605 | |
f62b8bb8 AV |
2606 | err_close_channels: |
2607 | for (i--; i >= 0; i--) | |
ff9c852f | 2608 | mlx5e_close_channel(chs->c[i]); |
f62b8bb8 | 2609 | |
acc6c595 | 2610 | err_free: |
ff9c852f | 2611 | kfree(chs->c); |
ca11b798 | 2612 | kvfree(cparam); |
ff9c852f | 2613 | chs->num = 0; |
f62b8bb8 AV |
2614 | return err; |
2615 | } | |
2616 | ||
79efecb4 | 2617 | static void mlx5e_activate_channels(struct mlx5e_priv *priv, struct mlx5e_channels *chs) |
f62b8bb8 AV |
2618 | { |
2619 | int i; | |
2620 | ||
acc6c595 SM |
2621 | for (i = 0; i < chs->num; i++) |
2622 | mlx5e_activate_channel(chs->c[i]); | |
145e5637 | 2623 | |
79efecb4 MM |
2624 | if (priv->htb) |
2625 | mlx5e_qos_activate_queues(priv); | |
2626 | ||
2627 | for (i = 0; i < chs->num; i++) | |
2628 | mlx5e_trigger_napi_icosq(chs->c[i]); | |
2629 | ||
b0d35de4 AL |
2630 | if (chs->ptp) |
2631 | mlx5e_ptp_activate_channel(chs->ptp); | |
acc6c595 SM |
2632 | } |
2633 | ||
2634 | static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs) | |
2635 | { | |
2636 | int err = 0; | |
2637 | int i; | |
2638 | ||
f8ebecf2 MM |
2639 | for (i = 0; i < chs->num; i++) { |
2640 | int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT; | |
082a9edf MM |
2641 | struct mlx5e_channel *c = chs->c[i]; |
2642 | ||
2643 | if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) | |
2644 | continue; | |
f8ebecf2 | 2645 | |
082a9edf | 2646 | err |= mlx5e_wait_for_min_rx_wqes(&c->rq, timeout); |
db05815b MM |
2647 | |
2648 | /* Don't wait on the XSK RQ, because the newer xdpsock sample | |
2649 | * doesn't provide any Fill Ring entries at the setup stage. | |
2650 | */ | |
f8ebecf2 | 2651 | } |
acc6c595 | 2652 | |
1e7477ae | 2653 | return err ? -ETIMEDOUT : 0; |
acc6c595 SM |
2654 | } |
2655 | ||
2656 | static void mlx5e_deactivate_channels(struct mlx5e_channels *chs) | |
2657 | { | |
2658 | int i; | |
2659 | ||
b0d35de4 AL |
2660 | if (chs->ptp) |
2661 | mlx5e_ptp_deactivate_channel(chs->ptp); | |
145e5637 | 2662 | |
acc6c595 SM |
2663 | for (i = 0; i < chs->num; i++) |
2664 | mlx5e_deactivate_channel(chs->c[i]); | |
2665 | } | |
2666 | ||
55c2503d | 2667 | void mlx5e_close_channels(struct mlx5e_channels *chs) |
acc6c595 SM |
2668 | { |
2669 | int i; | |
c3b7c5c9 | 2670 | |
b0d35de4 AL |
2671 | if (chs->ptp) { |
2672 | mlx5e_ptp_close(chs->ptp); | |
2673 | chs->ptp = NULL; | |
1c2cdf0b | 2674 | } |
ff9c852f SM |
2675 | for (i = 0; i < chs->num; i++) |
2676 | mlx5e_close_channel(chs->c[i]); | |
f62b8bb8 | 2677 | |
ff9c852f SM |
2678 | kfree(chs->c); |
2679 | chs->num = 0; | |
f62b8bb8 AV |
2680 | } |
2681 | ||
eaee12f0 | 2682 | static int mlx5e_modify_tirs_packet_merge(struct mlx5e_priv *priv) |
5c50368f | 2683 | { |
3f22d6c7 | 2684 | struct mlx5e_rx_res *res = priv->rx_res; |
5c50368f | 2685 | |
eaee12f0 | 2686 | return mlx5e_rx_res_packet_merge_set_param(res, &priv->channels.params.packet_merge); |
5c50368f AS |
2687 | } |
2688 | ||
eaee12f0 | 2689 | static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_packet_merge); |
b9ab5d0e | 2690 | |
472a1e44 TT |
2691 | static int mlx5e_set_mtu(struct mlx5_core_dev *mdev, |
2692 | struct mlx5e_params *params, u16 mtu) | |
40ab6a6e | 2693 | { |
472a1e44 | 2694 | u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu); |
40ab6a6e AS |
2695 | int err; |
2696 | ||
cd255eff | 2697 | err = mlx5_set_port_mtu(mdev, hw_mtu, 1); |
40ab6a6e AS |
2698 | if (err) |
2699 | return err; | |
2700 | ||
cd255eff SM |
2701 | /* Update vport context MTU */ |
2702 | mlx5_modify_nic_vport_mtu(mdev, hw_mtu); | |
2703 | return 0; | |
2704 | } | |
40ab6a6e | 2705 | |
472a1e44 TT |
2706 | static void mlx5e_query_mtu(struct mlx5_core_dev *mdev, |
2707 | struct mlx5e_params *params, u16 *mtu) | |
cd255eff | 2708 | { |
cd255eff SM |
2709 | u16 hw_mtu = 0; |
2710 | int err; | |
40ab6a6e | 2711 | |
cd255eff SM |
2712 | err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu); |
2713 | if (err || !hw_mtu) /* fallback to port oper mtu */ | |
2714 | mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1); | |
2715 | ||
472a1e44 | 2716 | *mtu = MLX5E_HW2SW_MTU(params, hw_mtu); |
cd255eff SM |
2717 | } |
2718 | ||
d9ee0491 | 2719 | int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv) |
cd255eff | 2720 | { |
472a1e44 | 2721 | struct mlx5e_params *params = &priv->channels.params; |
2e20a151 | 2722 | struct net_device *netdev = priv->netdev; |
472a1e44 | 2723 | struct mlx5_core_dev *mdev = priv->mdev; |
cd255eff SM |
2724 | u16 mtu; |
2725 | int err; | |
2726 | ||
472a1e44 | 2727 | err = mlx5e_set_mtu(mdev, params, params->sw_mtu); |
cd255eff SM |
2728 | if (err) |
2729 | return err; | |
40ab6a6e | 2730 | |
472a1e44 TT |
2731 | mlx5e_query_mtu(mdev, params, &mtu); |
2732 | if (mtu != params->sw_mtu) | |
cd255eff | 2733 | netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n", |
472a1e44 | 2734 | __func__, mtu, params->sw_mtu); |
40ab6a6e | 2735 | |
472a1e44 | 2736 | params->sw_mtu = mtu; |
40ab6a6e AS |
2737 | return 0; |
2738 | } | |
2739 | ||
b9ab5d0e MM |
2740 | MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu); |
2741 | ||
6d7ee2ed TT |
2742 | void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv) |
2743 | { | |
2744 | struct mlx5e_params *params = &priv->channels.params; | |
2745 | struct net_device *netdev = priv->netdev; | |
2746 | struct mlx5_core_dev *mdev = priv->mdev; | |
2747 | u16 max_mtu; | |
2748 | ||
2749 | /* MTU range: 68 - hw-specific max */ | |
2750 | netdev->min_mtu = ETH_MIN_MTU; | |
2751 | ||
2752 | mlx5_query_port_max_mtu(mdev, &max_mtu, 1); | |
2753 | netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu), | |
2754 | ETH_MAX_MTU); | |
2755 | } | |
2756 | ||
ec60c458 | 2757 | static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc, |
7dbc849b | 2758 | struct netdev_tc_txq *tc_to_txq) |
08fb1dac | 2759 | { |
21ecfcb8 | 2760 | int tc, err; |
08fb1dac SM |
2761 | |
2762 | netdev_reset_tc(netdev); | |
2763 | ||
2764 | if (ntc == 1) | |
21ecfcb8 | 2765 | return 0; |
08fb1dac | 2766 | |
21ecfcb8 TT |
2767 | err = netdev_set_num_tc(netdev, ntc); |
2768 | if (err) { | |
2769 | netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc); | |
2770 | return err; | |
2771 | } | |
08fb1dac | 2772 | |
ec60c458 TT |
2773 | for (tc = 0; tc < ntc; tc++) { |
2774 | u16 count, offset; | |
2775 | ||
7dbc849b TT |
2776 | count = tc_to_txq[tc].count; |
2777 | offset = tc_to_txq[tc].offset; | |
ec60c458 TT |
2778 | netdev_set_tc_queue(netdev, tc, count, offset); |
2779 | } | |
21ecfcb8 TT |
2780 | |
2781 | return 0; | |
08fb1dac SM |
2782 | } |
2783 | ||
214baf22 MM |
2784 | int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv) |
2785 | { | |
aaffda6b SM |
2786 | int nch, ntc, num_txqs, err; |
2787 | int qos_queues = 0; | |
214baf22 | 2788 | |
aaffda6b | 2789 | if (priv->htb) |
3685eed5 | 2790 | qos_queues = mlx5e_htb_cur_leaf_nodes(priv->htb); |
214baf22 MM |
2791 | |
2792 | nch = priv->channels.params.num_channels; | |
86d747a3 | 2793 | ntc = mlx5e_get_dcb_num_tc(&priv->channels.params); |
214baf22 MM |
2794 | num_txqs = nch * ntc + qos_queues; |
2795 | if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS)) | |
2796 | num_txqs += ntc; | |
2797 | ||
559f4c32 | 2798 | netdev_dbg(priv->netdev, "Setting num_txqs %d\n", num_txqs); |
214baf22 MM |
2799 | err = netif_set_real_num_tx_queues(priv->netdev, num_txqs); |
2800 | if (err) | |
2801 | netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err); | |
2802 | ||
2803 | return err; | |
2804 | } | |
2805 | ||
fa374877 | 2806 | static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv) |
c2c95271 | 2807 | { |
7dbc849b | 2808 | struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq; |
c2c95271 | 2809 | struct net_device *netdev = priv->netdev; |
fa374877 | 2810 | int old_num_txqs, old_ntc; |
3db4c85c | 2811 | int nch, ntc; |
fa374877 | 2812 | int err; |
7dbc849b | 2813 | int i; |
fa374877 MM |
2814 | |
2815 | old_num_txqs = netdev->real_num_tx_queues; | |
5e7923ac | 2816 | old_ntc = netdev->num_tc ? : 1; |
7dbc849b TT |
2817 | for (i = 0; i < ARRAY_SIZE(old_tc_to_txq); i++) |
2818 | old_tc_to_txq[i] = netdev->tc_to_txq[i]; | |
c2c95271 | 2819 | |
fa374877 | 2820 | nch = priv->channels.params.num_channels; |
7dbc849b | 2821 | ntc = priv->channels.params.mqprio.num_tc; |
7dbc849b | 2822 | tc_to_txq = priv->channels.params.mqprio.tc_to_txq; |
fa374877 | 2823 | |
7dbc849b | 2824 | err = mlx5e_netdev_set_tcs(netdev, nch, ntc, tc_to_txq); |
21ecfcb8 TT |
2825 | if (err) |
2826 | goto err_out; | |
214baf22 MM |
2827 | err = mlx5e_update_tx_netdev_queues(priv); |
2828 | if (err) | |
fa374877 | 2829 | goto err_tcs; |
3db4c85c | 2830 | err = netif_set_real_num_rx_queues(netdev, nch); |
fa374877 MM |
2831 | if (err) { |
2832 | netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err); | |
2833 | goto err_txqs; | |
2834 | } | |
2835 | ||
2836 | return 0; | |
2837 | ||
2838 | err_txqs: | |
2839 | /* netif_set_real_num_rx_queues could fail only when nch increased. Only | |
2840 | * one of nch and ntc is changed in this function. That means, the call | |
2841 | * to netif_set_real_num_tx_queues below should not fail, because it | |
2842 | * decreases the number of TX queues. | |
2843 | */ | |
2844 | WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs)); | |
2845 | ||
2846 | err_tcs: | |
7dbc849b TT |
2847 | WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc, |
2848 | old_tc_to_txq)); | |
21ecfcb8 | 2849 | err_out: |
fa374877 | 2850 | return err; |
c2c95271 MM |
2851 | } |
2852 | ||
7dbc849b TT |
2853 | static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_netdev_queues); |
2854 | ||
3909a12e MM |
2855 | static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv, |
2856 | struct mlx5e_params *params) | |
2857 | { | |
2858 | struct mlx5_core_dev *mdev = priv->mdev; | |
2859 | int num_comp_vectors, ix, irq; | |
2860 | ||
674dd4e2 | 2861 | num_comp_vectors = mlx5_comp_vectors_max(mdev); |
3909a12e MM |
2862 | |
2863 | for (ix = 0; ix < params->num_channels; ix++) { | |
2864 | cpumask_clear(priv->scratchpad.cpumask); | |
2865 | ||
2866 | for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) { | |
f3147015 | 2867 | int cpu = mlx5_comp_vector_get_cpu(mdev, irq); |
3909a12e MM |
2868 | |
2869 | cpumask_set_cpu(cpu, priv->scratchpad.cpumask); | |
2870 | } | |
2871 | ||
2872 | netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix); | |
2873 | } | |
2874 | } | |
2875 | ||
e9542221 | 2876 | static int mlx5e_num_channels_changed(struct mlx5e_priv *priv) |
fe867cac MM |
2877 | { |
2878 | u16 count = priv->channels.params.num_channels; | |
fa374877 MM |
2879 | int err; |
2880 | ||
2881 | err = mlx5e_update_netdev_queues(priv); | |
2882 | if (err) | |
2883 | return err; | |
fe867cac | 2884 | |
3909a12e MM |
2885 | mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params); |
2886 | ||
3f22d6c7 MM |
2887 | /* This function may be called on attach, before priv->rx_res is created. */ |
2888 | if (!netif_is_rxfh_configured(priv->netdev) && priv->rx_res) | |
43ec0f41 | 2889 | mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count); |
fe867cac MM |
2890 | |
2891 | return 0; | |
2892 | } | |
2893 | ||
b9ab5d0e MM |
2894 | MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed); |
2895 | ||
c55d8b10 | 2896 | static void mlx5e_build_txq_maps(struct mlx5e_priv *priv) |
acc6c595 | 2897 | { |
145e5637 | 2898 | int i, ch, tc, num_tc; |
acc6c595 | 2899 | |
c55d8b10 | 2900 | ch = priv->channels.num; |
86d747a3 | 2901 | num_tc = mlx5e_get_dcb_num_tc(&priv->channels.params); |
8bfaf07f | 2902 | |
c55d8b10 | 2903 | for (i = 0; i < ch; i++) { |
145e5637 | 2904 | for (tc = 0; tc < num_tc; tc++) { |
c55d8b10 EBE |
2905 | struct mlx5e_channel *c = priv->channels.c[i]; |
2906 | struct mlx5e_txqsq *sq = &c->sq[tc]; | |
acc6c595 | 2907 | |
acc6c595 SM |
2908 | priv->txq2sq[sq->txq_ix] = sq; |
2909 | } | |
2910 | } | |
145e5637 | 2911 | |
b0d35de4 | 2912 | if (!priv->channels.ptp) |
6ce204ea | 2913 | goto out; |
145e5637 | 2914 | |
24c22dd0 | 2915 | if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state)) |
6ce204ea | 2916 | goto out; |
24c22dd0 | 2917 | |
145e5637 | 2918 | for (tc = 0; tc < num_tc; tc++) { |
b0d35de4 | 2919 | struct mlx5e_ptp *c = priv->channels.ptp; |
145e5637 EBE |
2920 | struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq; |
2921 | ||
2922 | priv->txq2sq[sq->txq_ix] = sq; | |
145e5637 | 2923 | } |
6ce204ea MM |
2924 | |
2925 | out: | |
2926 | /* Make the change to txq2sq visible before the queue is started. | |
2927 | * As mlx5e_xmit runs under a spinlock, there is an implicit ACQUIRE, | |
2928 | * which pairs with this barrier. | |
2929 | */ | |
2930 | smp_wmb(); | |
145e5637 EBE |
2931 | } |
2932 | ||
603f4a45 | 2933 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv) |
acc6c595 | 2934 | { |
c55d8b10 | 2935 | mlx5e_build_txq_maps(priv); |
79efecb4 | 2936 | mlx5e_activate_channels(priv, &priv->channels); |
407e17b1 | 2937 | mlx5e_xdp_tx_enable(priv); |
befa4177 MM |
2938 | |
2939 | /* dev_watchdog() wants all TX queues to be started when the carrier is | |
2940 | * OK, including the ones in range real_num_tx_queues..num_tx_queues-1. | |
2941 | * Make it happy to avoid TX timeout false alarms. | |
2942 | */ | |
acc6c595 | 2943 | netif_tx_start_all_queues(priv->netdev); |
9008ae07 | 2944 | |
d9ee0491 | 2945 | if (mlx5e_is_vport_rep(priv)) |
430e2d5e | 2946 | mlx5e_rep_activate_channels(priv); |
9008ae07 | 2947 | |
acc6c595 | 2948 | mlx5e_wait_channels_min_rx_wqes(&priv->channels); |
db05815b | 2949 | |
43ec0f41 MM |
2950 | if (priv->rx_res) |
2951 | mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels); | |
acc6c595 SM |
2952 | } |
2953 | ||
603f4a45 | 2954 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv) |
acc6c595 | 2955 | { |
43ec0f41 MM |
2956 | if (priv->rx_res) |
2957 | mlx5e_rx_res_channels_deactivate(priv->rx_res); | |
9008ae07 | 2958 | |
d9ee0491 | 2959 | if (mlx5e_is_vport_rep(priv)) |
430e2d5e | 2960 | mlx5e_rep_deactivate_channels(priv); |
9008ae07 | 2961 | |
befa4177 MM |
2962 | /* The results of ndo_select_queue are unreliable, while netdev config |
2963 | * is being changed (real_num_tx_queues, num_tc). Stop all queues to | |
2964 | * prevent ndo_start_xmit from being called, so that it can assume that | |
2965 | * the selected queue is always valid. | |
acc6c595 | 2966 | */ |
acc6c595 | 2967 | netif_tx_disable(priv->netdev); |
befa4177 | 2968 | |
407e17b1 | 2969 | mlx5e_xdp_tx_disable(priv); |
acc6c595 SM |
2970 | mlx5e_deactivate_channels(&priv->channels); |
2971 | } | |
2972 | ||
b3b886cf MM |
2973 | static int mlx5e_switch_priv_params(struct mlx5e_priv *priv, |
2974 | struct mlx5e_params *new_params, | |
2975 | mlx5e_fp_preactivate preactivate, | |
2976 | void *context) | |
2977 | { | |
2978 | struct mlx5e_params old_params; | |
2979 | ||
2980 | old_params = priv->channels.params; | |
2981 | priv->channels.params = *new_params; | |
2982 | ||
2983 | if (preactivate) { | |
2984 | int err; | |
2985 | ||
2986 | err = preactivate(priv, context); | |
2987 | if (err) { | |
2988 | priv->channels.params = old_params; | |
2989 | return err; | |
2990 | } | |
2991 | } | |
2992 | ||
2993 | return 0; | |
2994 | } | |
2995 | ||
35a78ed4 MM |
2996 | static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv, |
2997 | struct mlx5e_channels *new_chs, | |
b9ab5d0e MM |
2998 | mlx5e_fp_preactivate preactivate, |
2999 | void *context) | |
55c2503d SM |
3000 | { |
3001 | struct net_device *netdev = priv->netdev; | |
35a78ed4 | 3002 | struct mlx5e_channels old_chs; |
7ca42c80 | 3003 | int carrier_ok; |
35a78ed4 | 3004 | int err = 0; |
877662e2 | 3005 | |
b3b886cf MM |
3006 | carrier_ok = netif_carrier_ok(netdev); |
3007 | netif_carrier_off(netdev); | |
55c2503d | 3008 | |
b3b886cf | 3009 | mlx5e_deactivate_priv_channels(priv); |
55c2503d | 3010 | |
35a78ed4 | 3011 | old_chs = priv->channels; |
55c2503d SM |
3012 | priv->channels = *new_chs; |
3013 | ||
dca147b3 MM |
3014 | /* New channels are ready to roll, call the preactivate hook if needed |
3015 | * to modify HW settings or update kernel parameters. | |
3016 | */ | |
35a78ed4 | 3017 | if (preactivate) { |
b9ab5d0e | 3018 | err = preactivate(priv, context); |
35a78ed4 MM |
3019 | if (err) { |
3020 | priv->channels = old_chs; | |
3021 | goto out; | |
3022 | } | |
3023 | } | |
2e20a151 | 3024 | |
b3b886cf MM |
3025 | mlx5e_close_channels(&old_chs); |
3026 | priv->profile->update_rx(priv); | |
35a78ed4 | 3027 | |
8bf30be7 | 3028 | mlx5e_selq_apply(&priv->selq); |
35a78ed4 | 3029 | out: |
b3b886cf | 3030 | mlx5e_activate_priv_channels(priv); |
55c2503d | 3031 | |
b3b886cf MM |
3032 | /* return carrier back if needed */ |
3033 | if (carrier_ok) | |
3034 | netif_carrier_on(netdev); | |
35a78ed4 MM |
3035 | |
3036 | return err; | |
55c2503d SM |
3037 | } |
3038 | ||
94872d4e MM |
3039 | int mlx5e_safe_switch_params(struct mlx5e_priv *priv, |
3040 | struct mlx5e_params *params, | |
3041 | mlx5e_fp_preactivate preactivate, | |
3042 | void *context, bool reset) | |
877662e2 | 3043 | { |
78028862 | 3044 | struct mlx5e_channels *new_chs; |
877662e2 TT |
3045 | int err; |
3046 | ||
b3b886cf MM |
3047 | reset &= test_bit(MLX5E_STATE_OPENED, &priv->state); |
3048 | if (!reset) | |
94872d4e | 3049 | return mlx5e_switch_priv_params(priv, params, preactivate, context); |
877662e2 | 3050 | |
78028862 AB |
3051 | new_chs = kzalloc(sizeof(*new_chs), GFP_KERNEL); |
3052 | if (!new_chs) | |
3053 | return -ENOMEM; | |
3054 | new_chs->params = *params; | |
8bf30be7 | 3055 | |
78028862 | 3056 | mlx5e_selq_prepare_params(&priv->selq, &new_chs->params); |
8bf30be7 | 3057 | |
78028862 | 3058 | err = mlx5e_open_channels(priv, new_chs); |
b3b886cf | 3059 | if (err) |
8bf30be7 MM |
3060 | goto err_cancel_selq; |
3061 | ||
78028862 | 3062 | err = mlx5e_switch_priv_channels(priv, new_chs, preactivate, context); |
35a78ed4 | 3063 | if (err) |
8bf30be7 | 3064 | goto err_close; |
35a78ed4 | 3065 | |
78028862 | 3066 | kfree(new_chs); |
8bf30be7 MM |
3067 | return 0; |
3068 | ||
3069 | err_close: | |
78028862 | 3070 | mlx5e_close_channels(new_chs); |
8bf30be7 MM |
3071 | |
3072 | err_cancel_selq: | |
3073 | mlx5e_selq_cancel(&priv->selq); | |
78028862 | 3074 | kfree(new_chs); |
35a78ed4 | 3075 | return err; |
877662e2 TT |
3076 | } |
3077 | ||
484c1ada EBE |
3078 | int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv) |
3079 | { | |
94872d4e | 3080 | return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true); |
484c1ada EBE |
3081 | } |
3082 | ||
237f258c | 3083 | void mlx5e_timestamp_init(struct mlx5e_priv *priv) |
7c39afb3 FD |
3084 | { |
3085 | priv->tstamp.tx_type = HWTSTAMP_TX_OFF; | |
3086 | priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE; | |
3087 | } | |
3088 | ||
7d0314b1 RD |
3089 | static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev, |
3090 | enum mlx5_port_status state) | |
3091 | { | |
3092 | struct mlx5_eswitch *esw = mdev->priv.eswitch; | |
3093 | int vport_admin_state; | |
3094 | ||
3095 | mlx5_set_port_admin_status(mdev, state); | |
3096 | ||
9c9be85f AL |
3097 | if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS || |
3098 | !MLX5_CAP_GEN(mdev, uplink_follow)) | |
7d0314b1 RD |
3099 | return; |
3100 | ||
3101 | if (state == MLX5_PORT_UP) | |
3102 | vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO; | |
3103 | else | |
3104 | vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN; | |
3105 | ||
3106 | mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state); | |
3107 | } | |
3108 | ||
40ab6a6e AS |
3109 | int mlx5e_open_locked(struct net_device *netdev) |
3110 | { | |
3111 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
40ab6a6e AS |
3112 | int err; |
3113 | ||
4f8d1d3a | 3114 | mlx5e_selq_prepare_params(&priv->selq, &priv->channels.params); |
8bf30be7 | 3115 | |
40ab6a6e AS |
3116 | set_bit(MLX5E_STATE_OPENED, &priv->state); |
3117 | ||
ff9c852f | 3118 | err = mlx5e_open_channels(priv, &priv->channels); |
acc6c595 | 3119 | if (err) |
343b29f3 | 3120 | goto err_clear_state_opened_flag; |
40ab6a6e | 3121 | |
e74ae1fa GT |
3122 | err = priv->profile->update_rx(priv); |
3123 | if (err) | |
3124 | goto err_close_channels; | |
3125 | ||
8bf30be7 | 3126 | mlx5e_selq_apply(&priv->selq); |
acc6c595 | 3127 | mlx5e_activate_priv_channels(priv); |
eb3862a0 | 3128 | mlx5e_apply_traps(priv, true); |
7ca42c80 ES |
3129 | if (priv->profile->update_carrier) |
3130 | priv->profile->update_carrier(priv); | |
be4891af | 3131 | |
cdeef2b1 | 3132 | mlx5e_queue_update_stats(priv); |
9b37b07f | 3133 | return 0; |
343b29f3 | 3134 | |
e74ae1fa GT |
3135 | err_close_channels: |
3136 | mlx5e_close_channels(&priv->channels); | |
343b29f3 AS |
3137 | err_clear_state_opened_flag: |
3138 | clear_bit(MLX5E_STATE_OPENED, &priv->state); | |
8bf30be7 | 3139 | mlx5e_selq_cancel(&priv->selq); |
343b29f3 | 3140 | return err; |
40ab6a6e AS |
3141 | } |
3142 | ||
cb67b832 | 3143 | int mlx5e_open(struct net_device *netdev) |
40ab6a6e AS |
3144 | { |
3145 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3146 | int err; | |
3147 | ||
3148 | mutex_lock(&priv->state_lock); | |
3149 | err = mlx5e_open_locked(netdev); | |
63bfd399 | 3150 | if (!err) |
7d0314b1 | 3151 | mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP); |
40ab6a6e AS |
3152 | mutex_unlock(&priv->state_lock); |
3153 | ||
3154 | return err; | |
3155 | } | |
3156 | ||
3157 | int mlx5e_close_locked(struct net_device *netdev) | |
3158 | { | |
3159 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3160 | ||
a1985740 AS |
3161 | /* May already be CLOSED in case a previous configuration operation |
3162 | * (e.g RX/TX queue size change) that involves close&open failed. | |
3163 | */ | |
3164 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
3165 | return 0; | |
3166 | ||
eb3862a0 | 3167 | mlx5e_apply_traps(priv, false); |
40ab6a6e AS |
3168 | clear_bit(MLX5E_STATE_OPENED, &priv->state); |
3169 | ||
40ab6a6e | 3170 | netif_carrier_off(priv->netdev); |
acc6c595 SM |
3171 | mlx5e_deactivate_priv_channels(priv); |
3172 | mlx5e_close_channels(&priv->channels); | |
40ab6a6e AS |
3173 | |
3174 | return 0; | |
3175 | } | |
3176 | ||
cb67b832 | 3177 | int mlx5e_close(struct net_device *netdev) |
40ab6a6e AS |
3178 | { |
3179 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3180 | int err; | |
3181 | ||
26e59d80 MHY |
3182 | if (!netif_device_present(netdev)) |
3183 | return -ENODEV; | |
3184 | ||
40ab6a6e | 3185 | mutex_lock(&priv->state_lock); |
7d0314b1 | 3186 | mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN); |
40ab6a6e AS |
3187 | err = mlx5e_close_locked(netdev); |
3188 | mutex_unlock(&priv->state_lock); | |
3189 | ||
3190 | return err; | |
3191 | } | |
3192 | ||
cdd3f236 TT |
3193 | static void mlx5e_free_drop_rq(struct mlx5e_rq *rq) |
3194 | { | |
3195 | mlx5_wq_destroy(&rq->wq_ctrl); | |
3196 | } | |
3197 | ||
a43b25da | 3198 | static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev, |
3b77235b SM |
3199 | struct mlx5e_rq *rq, |
3200 | struct mlx5e_rq_param *param) | |
40ab6a6e | 3201 | { |
40ab6a6e AS |
3202 | void *rqc = param->rqc; |
3203 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
3204 | int err; | |
3205 | ||
3206 | param->wq.db_numa_node = param->wq.buf_numa_node; | |
3207 | ||
99cbfa93 TT |
3208 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq, |
3209 | &rq->wq_ctrl); | |
40ab6a6e AS |
3210 | if (err) |
3211 | return err; | |
3212 | ||
0ddf5432 JDB |
3213 | /* Mark as unused given "Drop-RQ" packets never reach XDP */ |
3214 | xdp_rxq_info_unused(&rq->xdp_rxq); | |
3215 | ||
a43b25da | 3216 | rq->mdev = mdev; |
40ab6a6e AS |
3217 | |
3218 | return 0; | |
3219 | } | |
3220 | ||
4d0b7ef9 | 3221 | static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv, |
3b77235b SM |
3222 | struct mlx5e_cq *cq, |
3223 | struct mlx5e_cq_param *param) | |
40ab6a6e | 3224 | { |
4d0b7ef9 AL |
3225 | struct mlx5_core_dev *mdev = priv->mdev; |
3226 | ||
7be3412a PP |
3227 | param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); |
3228 | param->wq.db_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); | |
2f0db879 | 3229 | |
4d0b7ef9 | 3230 | return mlx5e_alloc_cq_common(priv, param, cq); |
40ab6a6e AS |
3231 | } |
3232 | ||
1462e48d RD |
3233 | int mlx5e_open_drop_rq(struct mlx5e_priv *priv, |
3234 | struct mlx5e_rq *drop_rq) | |
40ab6a6e | 3235 | { |
7cbaf9a3 | 3236 | struct mlx5_core_dev *mdev = priv->mdev; |
a43b25da SM |
3237 | struct mlx5e_cq_param cq_param = {}; |
3238 | struct mlx5e_rq_param rq_param = {}; | |
3239 | struct mlx5e_cq *cq = &drop_rq->cq; | |
40ab6a6e AS |
3240 | int err; |
3241 | ||
89564920 | 3242 | mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param); |
40ab6a6e | 3243 | |
4d0b7ef9 | 3244 | err = mlx5e_alloc_drop_cq(priv, cq, &cq_param); |
40ab6a6e AS |
3245 | if (err) |
3246 | return err; | |
3247 | ||
3b77235b | 3248 | err = mlx5e_create_cq(cq, &cq_param); |
40ab6a6e | 3249 | if (err) |
3b77235b | 3250 | goto err_free_cq; |
40ab6a6e | 3251 | |
a43b25da | 3252 | err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param); |
40ab6a6e | 3253 | if (err) |
3b77235b | 3254 | goto err_destroy_cq; |
40ab6a6e | 3255 | |
a43b25da | 3256 | err = mlx5e_create_rq(drop_rq, &rq_param); |
40ab6a6e | 3257 | if (err) |
3b77235b | 3258 | goto err_free_rq; |
40ab6a6e | 3259 | |
7cbaf9a3 MS |
3260 | err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); |
3261 | if (err) | |
3262 | mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err); | |
3263 | ||
40ab6a6e AS |
3264 | return 0; |
3265 | ||
3b77235b | 3266 | err_free_rq: |
cdd3f236 | 3267 | mlx5e_free_drop_rq(drop_rq); |
40ab6a6e AS |
3268 | |
3269 | err_destroy_cq: | |
a43b25da | 3270 | mlx5e_destroy_cq(cq); |
40ab6a6e | 3271 | |
3b77235b | 3272 | err_free_cq: |
a43b25da | 3273 | mlx5e_free_cq(cq); |
3b77235b | 3274 | |
40ab6a6e AS |
3275 | return err; |
3276 | } | |
3277 | ||
1462e48d | 3278 | void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq) |
40ab6a6e | 3279 | { |
a43b25da | 3280 | mlx5e_destroy_rq(drop_rq); |
cdd3f236 | 3281 | mlx5e_free_drop_rq(drop_rq); |
a43b25da SM |
3282 | mlx5e_destroy_cq(&drop_rq->cq); |
3283 | mlx5e_free_cq(&drop_rq->cq); | |
40ab6a6e AS |
3284 | } |
3285 | ||
2b257a6e | 3286 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn) |
40ab6a6e | 3287 | { |
40ab6a6e AS |
3288 | void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); |
3289 | ||
c276aae8 | 3290 | MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn); |
db60b802 | 3291 | |
d2ead1f3 | 3292 | if (MLX5_GET(tisc, tisc, tls_en)) |
c276aae8 | 3293 | MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn); |
d2ead1f3 | 3294 | |
db60b802 AH |
3295 | if (mlx5_lag_is_lacp_owner(mdev)) |
3296 | MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1); | |
3297 | ||
e0b4b472 | 3298 | return mlx5_core_create_tis(mdev, in, tisn); |
40ab6a6e AS |
3299 | } |
3300 | ||
5426a0b2 | 3301 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn) |
40ab6a6e | 3302 | { |
5426a0b2 | 3303 | mlx5_core_destroy_tis(mdev, tisn); |
40ab6a6e AS |
3304 | } |
3305 | ||
3c145626 TT |
3306 | void mlx5e_destroy_tises(struct mlx5e_priv *priv) |
3307 | { | |
45f171b1 | 3308 | int tc, i; |
3c145626 | 3309 | |
45f171b1 MM |
3310 | for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) |
3311 | for (tc = 0; tc < priv->profile->max_tc; tc++) | |
3312 | mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]); | |
3313 | } | |
3314 | ||
3315 | static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev) | |
3316 | { | |
3317 | return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1; | |
3c145626 TT |
3318 | } |
3319 | ||
cb67b832 | 3320 | int mlx5e_create_tises(struct mlx5e_priv *priv) |
40ab6a6e | 3321 | { |
45f171b1 | 3322 | int tc, i; |
40ab6a6e | 3323 | int err; |
40ab6a6e | 3324 | |
45f171b1 MM |
3325 | for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) { |
3326 | for (tc = 0; tc < priv->profile->max_tc; tc++) { | |
3327 | u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; | |
3328 | void *tisc; | |
2b257a6e | 3329 | |
45f171b1 | 3330 | tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); |
2b257a6e | 3331 | |
45f171b1 | 3332 | MLX5_SET(tisc, tisc, prio, tc << 1); |
2b257a6e | 3333 | |
45f171b1 MM |
3334 | if (mlx5e_lag_should_assign_affinity(priv->mdev)) |
3335 | MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1); | |
3336 | ||
3337 | err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]); | |
3338 | if (err) | |
3339 | goto err_close_tises; | |
3340 | } | |
40ab6a6e AS |
3341 | } |
3342 | ||
3343 | return 0; | |
3344 | ||
3345 | err_close_tises: | |
45f171b1 MM |
3346 | for (; i >= 0; i--) { |
3347 | for (tc--; tc >= 0; tc--) | |
3348 | mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]); | |
3349 | tc = priv->profile->max_tc; | |
3350 | } | |
40ab6a6e AS |
3351 | |
3352 | return err; | |
3353 | } | |
3354 | ||
d9ee0491 | 3355 | static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv) |
40ab6a6e | 3356 | { |
0bb7228f MT |
3357 | if (priv->mqprio_rl) { |
3358 | mlx5e_mqprio_rl_cleanup(priv->mqprio_rl); | |
3359 | mlx5e_mqprio_rl_free(priv->mqprio_rl); | |
3360 | priv->mqprio_rl = NULL; | |
3361 | } | |
c4dfe704 | 3362 | mlx5e_accel_cleanup_tx(priv); |
3c145626 | 3363 | mlx5e_destroy_tises(priv); |
40ab6a6e AS |
3364 | } |
3365 | ||
f6d96a20 | 3366 | static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd) |
36350114 | 3367 | { |
a759f845 | 3368 | int err; |
36350114 GP |
3369 | int i; |
3370 | ||
ff9c852f SM |
3371 | for (i = 0; i < chs->num; i++) { |
3372 | err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd); | |
36350114 GP |
3373 | if (err) |
3374 | return err; | |
3375 | } | |
a759f845 AL |
3376 | if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state)) |
3377 | return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd); | |
36350114 GP |
3378 | |
3379 | return 0; | |
3380 | } | |
3381 | ||
7dbc849b TT |
3382 | static void mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq *tc_to_txq, |
3383 | int ntc, int nch) | |
3384 | { | |
3385 | int tc; | |
3386 | ||
3387 | memset(tc_to_txq, 0, sizeof(*tc_to_txq) * TC_MAX_QUEUE); | |
3388 | ||
3389 | /* Map netdev TCs to offset 0. | |
3390 | * We have our own UP to TXQ mapping for DCB mode of QoS | |
3391 | */ | |
3392 | for (tc = 0; tc < ntc; tc++) { | |
3393 | tc_to_txq[tc] = (struct netdev_tc_txq) { | |
3394 | .count = nch, | |
3395 | .offset = 0, | |
3396 | }; | |
3397 | } | |
3398 | } | |
3399 | ||
3400 | static void mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq *tc_to_txq, | |
3401 | struct tc_mqprio_qopt *qopt) | |
3402 | { | |
3403 | int tc; | |
3404 | ||
3405 | for (tc = 0; tc < TC_MAX_QUEUE; tc++) { | |
3406 | tc_to_txq[tc] = (struct netdev_tc_txq) { | |
3407 | .count = qopt->count[tc], | |
3408 | .offset = qopt->offset[tc], | |
3409 | }; | |
3410 | } | |
3411 | } | |
3412 | ||
3413 | static void mlx5e_params_mqprio_dcb_set(struct mlx5e_params *params, u8 num_tc) | |
3414 | { | |
3415 | params->mqprio.mode = TC_MQPRIO_MODE_DCB; | |
3416 | params->mqprio.num_tc = num_tc; | |
3417 | mlx5e_mqprio_build_default_tc_to_txq(params->mqprio.tc_to_txq, num_tc, | |
3418 | params->num_channels); | |
3419 | } | |
3420 | ||
0bb7228f MT |
3421 | static void mlx5e_mqprio_rl_update_params(struct mlx5e_params *params, |
3422 | struct mlx5e_mqprio_rl *rl) | |
3423 | { | |
3424 | int tc; | |
3425 | ||
3426 | for (tc = 0; tc < TC_MAX_QUEUE; tc++) { | |
3427 | u32 hw_id = 0; | |
3428 | ||
3429 | if (rl) | |
3430 | mlx5e_mqprio_rl_get_node_hw_id(rl, tc, &hw_id); | |
3431 | params->mqprio.channel.hw_id[tc] = hw_id; | |
3432 | } | |
3433 | } | |
3434 | ||
7dbc849b | 3435 | static void mlx5e_params_mqprio_channel_set(struct mlx5e_params *params, |
0bb7228f | 3436 | struct tc_mqprio_qopt_offload *mqprio, |
80743c4f | 3437 | struct mlx5e_mqprio_rl *rl) |
7dbc849b | 3438 | { |
0bb7228f MT |
3439 | int tc; |
3440 | ||
7dbc849b | 3441 | params->mqprio.mode = TC_MQPRIO_MODE_CHANNEL; |
0bb7228f MT |
3442 | params->mqprio.num_tc = mqprio->qopt.num_tc; |
3443 | ||
3444 | for (tc = 0; tc < TC_MAX_QUEUE; tc++) | |
3445 | params->mqprio.channel.max_rate[tc] = mqprio->max_rate[tc]; | |
3446 | ||
3447 | mlx5e_mqprio_rl_update_params(params, rl); | |
3448 | mlx5e_mqprio_build_tc_to_txq(params->mqprio.tc_to_txq, &mqprio->qopt); | |
7dbc849b TT |
3449 | } |
3450 | ||
3451 | static void mlx5e_params_mqprio_reset(struct mlx5e_params *params) | |
3452 | { | |
3453 | mlx5e_params_mqprio_dcb_set(params, 1); | |
3454 | } | |
3455 | ||
e2aeac44 TT |
3456 | static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv, |
3457 | struct tc_mqprio_qopt *mqprio) | |
08fb1dac | 3458 | { |
94872d4e | 3459 | struct mlx5e_params new_params; |
0cf0f6d3 | 3460 | u8 tc = mqprio->num_tc; |
e2aeac44 | 3461 | int err; |
08fb1dac | 3462 | |
0cf0f6d3 JP |
3463 | mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; |
3464 | ||
08fb1dac SM |
3465 | if (tc && tc != MLX5E_MAX_NUM_TC) |
3466 | return -EINVAL; | |
3467 | ||
94872d4e | 3468 | new_params = priv->channels.params; |
7dbc849b | 3469 | mlx5e_params_mqprio_dcb_set(&new_params, tc ? tc : 1); |
08fb1dac | 3470 | |
94872d4e MM |
3471 | err = mlx5e_safe_switch_params(priv, &new_params, |
3472 | mlx5e_num_channels_changed_ctx, NULL, true); | |
08fb1dac | 3473 | |
0bb7228f MT |
3474 | if (!err && priv->mqprio_rl) { |
3475 | mlx5e_mqprio_rl_cleanup(priv->mqprio_rl); | |
3476 | mlx5e_mqprio_rl_free(priv->mqprio_rl); | |
3477 | priv->mqprio_rl = NULL; | |
3478 | } | |
3479 | ||
5a2ba25a | 3480 | priv->max_opened_tc = max_t(u8, priv->max_opened_tc, |
86d747a3 | 3481 | mlx5e_get_dcb_num_tc(&priv->channels.params)); |
08fb1dac SM |
3482 | return err; |
3483 | } | |
3484 | ||
ec60c458 TT |
3485 | static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv, |
3486 | struct tc_mqprio_qopt_offload *mqprio) | |
3487 | { | |
3488 | struct net_device *netdev = priv->netdev; | |
3bf1742f | 3489 | struct mlx5e_ptp *ptp_channel; |
ec60c458 TT |
3490 | int agg_count = 0; |
3491 | int i; | |
3492 | ||
3bf1742f AL |
3493 | ptp_channel = priv->channels.ptp; |
3494 | if (ptp_channel && test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state)) { | |
3495 | netdev_err(netdev, | |
3496 | "Cannot activate MQPRIO mode channel since it conflicts with TX port TS\n"); | |
3497 | return -EINVAL; | |
3498 | } | |
3499 | ||
ec60c458 TT |
3500 | if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 || |
3501 | mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC) | |
3502 | return -EINVAL; | |
3503 | ||
3504 | for (i = 0; i < mqprio->qopt.num_tc; i++) { | |
3505 | if (!mqprio->qopt.count[i]) { | |
3506 | netdev_err(netdev, "Zero size for queue-group (%d) is not supported\n", i); | |
3507 | return -EINVAL; | |
3508 | } | |
3509 | if (mqprio->min_rate[i]) { | |
3510 | netdev_err(netdev, "Min tx rate is not supported\n"); | |
3511 | return -EINVAL; | |
3512 | } | |
80743c4f | 3513 | |
ec60c458 | 3514 | if (mqprio->max_rate[i]) { |
80743c4f TT |
3515 | int err; |
3516 | ||
3517 | err = mlx5e_qos_bytes_rate_check(priv->mdev, mqprio->max_rate[i]); | |
3518 | if (err) | |
3519 | return err; | |
ec60c458 TT |
3520 | } |
3521 | ||
3522 | if (mqprio->qopt.offset[i] != agg_count) { | |
3523 | netdev_err(netdev, "Discontinuous queues config is not supported\n"); | |
3524 | return -EINVAL; | |
3525 | } | |
3526 | agg_count += mqprio->qopt.count[i]; | |
3527 | } | |
3528 | ||
ca20dfda TT |
3529 | if (priv->channels.params.num_channels != agg_count) { |
3530 | netdev_err(netdev, "Num of queues (%d) does not match available (%d)\n", | |
ec60c458 TT |
3531 | agg_count, priv->channels.params.num_channels); |
3532 | return -EINVAL; | |
3533 | } | |
3534 | ||
3535 | return 0; | |
3536 | } | |
3537 | ||
0bb7228f | 3538 | static bool mlx5e_mqprio_rate_limit(u8 num_tc, u64 max_rate[]) |
80743c4f TT |
3539 | { |
3540 | int tc; | |
3541 | ||
0bb7228f MT |
3542 | for (tc = 0; tc < num_tc; tc++) |
3543 | if (max_rate[tc]) | |
80743c4f TT |
3544 | return true; |
3545 | return false; | |
3546 | } | |
3547 | ||
0bb7228f MT |
3548 | static struct mlx5e_mqprio_rl *mlx5e_mqprio_rl_create(struct mlx5_core_dev *mdev, |
3549 | u8 num_tc, u64 max_rate[]) | |
3550 | { | |
3551 | struct mlx5e_mqprio_rl *rl; | |
3552 | int err; | |
3553 | ||
3554 | if (!mlx5e_mqprio_rate_limit(num_tc, max_rate)) | |
3555 | return NULL; | |
3556 | ||
3557 | rl = mlx5e_mqprio_rl_alloc(); | |
3558 | if (!rl) | |
3559 | return ERR_PTR(-ENOMEM); | |
3560 | ||
3561 | err = mlx5e_mqprio_rl_init(rl, mdev, num_tc, max_rate); | |
3562 | if (err) { | |
3563 | mlx5e_mqprio_rl_free(rl); | |
3564 | return ERR_PTR(err); | |
3565 | } | |
3566 | ||
3567 | return rl; | |
3568 | } | |
3569 | ||
ec60c458 TT |
3570 | static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv, |
3571 | struct tc_mqprio_qopt_offload *mqprio) | |
3572 | { | |
7dbc849b | 3573 | mlx5e_fp_preactivate preactivate; |
ec60c458 | 3574 | struct mlx5e_params new_params; |
80743c4f | 3575 | struct mlx5e_mqprio_rl *rl; |
7dbc849b | 3576 | bool nch_changed; |
ec60c458 TT |
3577 | int err; |
3578 | ||
3579 | err = mlx5e_mqprio_channel_validate(priv, mqprio); | |
3580 | if (err) | |
3581 | return err; | |
3582 | ||
0bb7228f MT |
3583 | rl = mlx5e_mqprio_rl_create(priv->mdev, mqprio->qopt.num_tc, mqprio->max_rate); |
3584 | if (IS_ERR(rl)) | |
3585 | return PTR_ERR(rl); | |
80743c4f | 3586 | |
ec60c458 | 3587 | new_params = priv->channels.params; |
0bb7228f | 3588 | mlx5e_params_mqprio_channel_set(&new_params, mqprio, rl); |
ec60c458 | 3589 | |
7dbc849b TT |
3590 | nch_changed = mlx5e_get_dcb_num_tc(&priv->channels.params) > 1; |
3591 | preactivate = nch_changed ? mlx5e_num_channels_changed_ctx : | |
3592 | mlx5e_update_netdev_queues_ctx; | |
80743c4f | 3593 | err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, true); |
0bb7228f MT |
3594 | if (err) { |
3595 | if (rl) { | |
3596 | mlx5e_mqprio_rl_cleanup(rl); | |
3597 | mlx5e_mqprio_rl_free(rl); | |
3598 | } | |
3599 | return err; | |
80743c4f TT |
3600 | } |
3601 | ||
0bb7228f MT |
3602 | if (priv->mqprio_rl) { |
3603 | mlx5e_mqprio_rl_cleanup(priv->mqprio_rl); | |
3604 | mlx5e_mqprio_rl_free(priv->mqprio_rl); | |
3605 | } | |
3606 | priv->mqprio_rl = rl; | |
3607 | ||
3608 | return 0; | |
ec60c458 TT |
3609 | } |
3610 | ||
e2aeac44 TT |
3611 | static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv, |
3612 | struct tc_mqprio_qopt_offload *mqprio) | |
3613 | { | |
3614 | /* MQPRIO is another toplevel qdisc that can't be attached | |
3615 | * simultaneously with the offloaded HTB. | |
3616 | */ | |
4f8d1d3a | 3617 | if (WARN_ON(mlx5e_selq_is_htb_enabled(&priv->selq))) |
e2aeac44 TT |
3618 | return -EINVAL; |
3619 | ||
3620 | switch (mqprio->mode) { | |
3621 | case TC_MQPRIO_MODE_DCB: | |
3622 | return mlx5e_setup_tc_mqprio_dcb(priv, &mqprio->qopt); | |
ec60c458 TT |
3623 | case TC_MQPRIO_MODE_CHANNEL: |
3624 | return mlx5e_setup_tc_mqprio_channel(priv, mqprio); | |
e2aeac44 TT |
3625 | default: |
3626 | return -EOPNOTSUPP; | |
3627 | } | |
3628 | } | |
3629 | ||
955bcb6e PNA |
3630 | static LIST_HEAD(mlx5e_block_cb_list); |
3631 | ||
9afe9a53 OG |
3632 | static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type, |
3633 | void *type_data) | |
0cf0f6d3 | 3634 | { |
4e95bc26 | 3635 | struct mlx5e_priv *priv = netdev_priv(dev); |
2ff349c5 | 3636 | bool tc_unbind = false; |
214baf22 | 3637 | int err; |
4e95bc26 | 3638 | |
2ff349c5 RD |
3639 | if (type == TC_SETUP_BLOCK && |
3640 | ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND) | |
3641 | tc_unbind = true; | |
3642 | ||
3643 | if (!netif_device_present(dev) && !tc_unbind) | |
3644 | return -ENODEV; | |
3645 | ||
2572ac53 | 3646 | switch (type) { |
daa664a5 VB |
3647 | case TC_SETUP_BLOCK: { |
3648 | struct flow_block_offload *f = type_data; | |
3649 | ||
c9f14470 | 3650 | f->unlocked_driver_cb = true; |
955bcb6e PNA |
3651 | return flow_block_cb_setup_simple(type_data, |
3652 | &mlx5e_block_cb_list, | |
4e95bc26 PNA |
3653 | mlx5e_setup_tc_block_cb, |
3654 | priv, priv, true); | |
daa664a5 | 3655 | } |
575ed7d3 | 3656 | case TC_SETUP_QDISC_MQPRIO: |
e2aeac44 TT |
3657 | mutex_lock(&priv->state_lock); |
3658 | err = mlx5e_setup_tc_mqprio(priv, type_data); | |
3659 | mutex_unlock(&priv->state_lock); | |
3660 | return err; | |
214baf22 MM |
3661 | case TC_SETUP_QDISC_HTB: |
3662 | mutex_lock(&priv->state_lock); | |
efe31799 | 3663 | err = mlx5e_htb_setup_tc(priv, type_data); |
214baf22 MM |
3664 | mutex_unlock(&priv->state_lock); |
3665 | return err; | |
e8f887ac AV |
3666 | default: |
3667 | return -EOPNOTSUPP; | |
3668 | } | |
08fb1dac SM |
3669 | } |
3670 | ||
b832d4fd | 3671 | void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s) |
9659e49a SM |
3672 | { |
3673 | int i; | |
3674 | ||
9d758d4a | 3675 | for (i = 0; i < priv->stats_nch; i++) { |
be98737a | 3676 | struct mlx5e_channel_stats *channel_stats = priv->channel_stats[i]; |
db05815b | 3677 | struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq; |
9659e49a SM |
3678 | struct mlx5e_rq_stats *rq_stats = &channel_stats->rq; |
3679 | int j; | |
3680 | ||
db05815b MM |
3681 | s->rx_packets += rq_stats->packets + xskrq_stats->packets; |
3682 | s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes; | |
47c97e6b | 3683 | s->multicast += rq_stats->mcast_packets + xskrq_stats->mcast_packets; |
9659e49a SM |
3684 | |
3685 | for (j = 0; j < priv->max_opened_tc; j++) { | |
3686 | struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j]; | |
3687 | ||
354521ee AL |
3688 | s->tx_packets += sq_stats->packets; |
3689 | s->tx_bytes += sq_stats->bytes; | |
3690 | s->tx_dropped += sq_stats->dropped; | |
3691 | } | |
3692 | } | |
b0d35de4 | 3693 | if (priv->tx_ptp_opened) { |
354521ee | 3694 | for (i = 0; i < priv->max_opened_tc; i++) { |
b0d35de4 | 3695 | struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i]; |
354521ee | 3696 | |
9659e49a SM |
3697 | s->tx_packets += sq_stats->packets; |
3698 | s->tx_bytes += sq_stats->bytes; | |
3699 | s->tx_dropped += sq_stats->dropped; | |
3700 | } | |
3701 | } | |
a28359e9 AL |
3702 | if (priv->rx_ptp_opened) { |
3703 | struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq; | |
3704 | ||
3705 | s->rx_packets += rq_stats->packets; | |
3706 | s->rx_bytes += rq_stats->bytes; | |
3707 | s->multicast += rq_stats->mcast_packets; | |
3708 | } | |
9659e49a SM |
3709 | } |
3710 | ||
d9ee0491 | 3711 | void |
f62b8bb8 AV |
3712 | mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) |
3713 | { | |
3714 | struct mlx5e_priv *priv = netdev_priv(dev); | |
269e6b3a | 3715 | struct mlx5e_pport_stats *pstats = &priv->stats.pport; |
f62b8bb8 | 3716 | |
2ff349c5 RD |
3717 | if (!netif_device_present(dev)) |
3718 | return; | |
3719 | ||
dcdf4ce0 ZY |
3720 | /* In switchdev mode, monitor counters doesn't monitor |
3721 | * rx/tx stats of 802_3. The update stats mechanism | |
3722 | * should keep the 802_3 layout counters updated | |
3723 | */ | |
3724 | if (!mlx5e_monitor_counter_supported(priv) || | |
3725 | mlx5e_is_uplink_rep(priv)) { | |
5c7e8bbb ED |
3726 | /* update HW stats in background for next time */ |
3727 | mlx5e_queue_update_stats(priv); | |
3728 | } | |
ed56c519 | 3729 | |
370bad0f | 3730 | if (mlx5e_is_uplink_rep(priv)) { |
a0723108 HN |
3731 | struct mlx5e_vport_stats *vstats = &priv->stats.vport; |
3732 | ||
370bad0f OG |
3733 | stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok); |
3734 | stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok); | |
3735 | stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok); | |
3736 | stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok); | |
a0723108 HN |
3737 | |
3738 | /* vport multicast also counts packets that are dropped due to steering | |
3739 | * or rx out of buffer | |
3740 | */ | |
3741 | stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets); | |
370bad0f | 3742 | } else { |
9659e49a | 3743 | mlx5e_fold_sw_stats64(priv, stats); |
370bad0f | 3744 | } |
269e6b3a GP |
3745 | |
3746 | stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer; | |
269e6b3a GP |
3747 | |
3748 | stats->rx_length_errors = | |
9218b44d GP |
3749 | PPORT_802_3_GET(pstats, a_in_range_length_errors) + |
3750 | PPORT_802_3_GET(pstats, a_out_of_range_length_field) + | |
16ab85e7 GP |
3751 | PPORT_802_3_GET(pstats, a_frame_too_long_errors) + |
3752 | VNIC_ENV_GET(&priv->stats.vnic, eth_wqe_too_small); | |
269e6b3a | 3753 | stats->rx_crc_errors = |
9218b44d GP |
3754 | PPORT_802_3_GET(pstats, a_frame_check_sequence_errors); |
3755 | stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors); | |
3756 | stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards); | |
269e6b3a GP |
3757 | stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + |
3758 | stats->rx_frame_errors; | |
3759 | stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors; | |
f62b8bb8 AV |
3760 | } |
3761 | ||
1aa48ca6 RD |
3762 | static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv) |
3763 | { | |
3764 | if (mlx5e_is_uplink_rep(priv)) | |
3765 | return; /* no rx mode for uplink rep */ | |
3766 | ||
3767 | queue_work(priv->wq, &priv->set_rx_mode_work); | |
3768 | } | |
3769 | ||
f62b8bb8 AV |
3770 | static void mlx5e_set_rx_mode(struct net_device *dev) |
3771 | { | |
3772 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3773 | ||
1aa48ca6 | 3774 | mlx5e_nic_set_rx_mode(priv); |
f62b8bb8 AV |
3775 | } |
3776 | ||
3777 | static int mlx5e_set_mac(struct net_device *netdev, void *addr) | |
3778 | { | |
3779 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3780 | struct sockaddr *saddr = addr; | |
3781 | ||
3782 | if (!is_valid_ether_addr(saddr->sa_data)) | |
3783 | return -EADDRNOTAVAIL; | |
3784 | ||
3785 | netif_addr_lock_bh(netdev); | |
f3956ebb | 3786 | eth_hw_addr_set(netdev, saddr->sa_data); |
f62b8bb8 AV |
3787 | netif_addr_unlock_bh(netdev); |
3788 | ||
1aa48ca6 | 3789 | mlx5e_nic_set_rx_mode(priv); |
f62b8bb8 AV |
3790 | |
3791 | return 0; | |
3792 | } | |
3793 | ||
75b81ce7 | 3794 | #define MLX5E_SET_FEATURE(features, feature, enable) \ |
0e405443 GP |
3795 | do { \ |
3796 | if (enable) \ | |
75b81ce7 | 3797 | *features |= feature; \ |
0e405443 | 3798 | else \ |
75b81ce7 | 3799 | *features &= ~feature; \ |
0e405443 GP |
3800 | } while (0) |
3801 | ||
3802 | typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable); | |
3803 | ||
3804 | static int set_feature_lro(struct net_device *netdev, bool enable) | |
f62b8bb8 AV |
3805 | { |
3806 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
619a8f2a | 3807 | struct mlx5_core_dev *mdev = priv->mdev; |
8355060f | 3808 | struct mlx5e_params *cur_params; |
94872d4e | 3809 | struct mlx5e_params new_params; |
b3b886cf | 3810 | bool reset = true; |
2e20a151 | 3811 | int err = 0; |
f62b8bb8 AV |
3812 | |
3813 | mutex_lock(&priv->state_lock); | |
f62b8bb8 | 3814 | |
8355060f | 3815 | cur_params = &priv->channels.params; |
94872d4e | 3816 | new_params = *cur_params; |
2e20a151 | 3817 | |
eaee12f0 KM |
3818 | if (enable) |
3819 | new_params.packet_merge.type = MLX5E_PACKET_MERGE_LRO; | |
3820 | else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO) | |
3821 | new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE; | |
3822 | else | |
3823 | goto out; | |
3824 | ||
3825 | if (!(cur_params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO && | |
3826 | new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)) { | |
3827 | if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { | |
3828 | if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) == | |
3829 | mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL)) | |
3830 | reset = false; | |
3831 | } | |
98e81b0a | 3832 | } |
f62b8bb8 | 3833 | |
94872d4e | 3834 | err = mlx5e_safe_switch_params(priv, &new_params, |
eaee12f0 | 3835 | mlx5e_modify_tirs_packet_merge_ctx, NULL, reset); |
2e20a151 | 3836 | out: |
9b37b07f | 3837 | mutex_unlock(&priv->state_lock); |
0e405443 GP |
3838 | return err; |
3839 | } | |
3840 | ||
83439f3c KM |
3841 | static int set_feature_hw_gro(struct net_device *netdev, bool enable) |
3842 | { | |
3843 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3844 | struct mlx5e_params new_params; | |
3845 | bool reset = true; | |
3846 | int err = 0; | |
3847 | ||
3848 | mutex_lock(&priv->state_lock); | |
3849 | new_params = priv->channels.params; | |
3850 | ||
3851 | if (enable) { | |
3852 | new_params.packet_merge.type = MLX5E_PACKET_MERGE_SHAMPO; | |
3853 | new_params.packet_merge.shampo.match_criteria_type = | |
3854 | MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED; | |
3855 | new_params.packet_merge.shampo.alignment_granularity = | |
3856 | MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE; | |
3857 | } else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) { | |
3858 | new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE; | |
3859 | } else { | |
3860 | goto out; | |
3861 | } | |
3862 | ||
99a2b9be | 3863 | err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset); |
83439f3c KM |
3864 | out: |
3865 | mutex_unlock(&priv->state_lock); | |
3866 | return err; | |
3867 | } | |
3868 | ||
2b52a283 | 3869 | static int set_feature_cvlan_filter(struct net_device *netdev, bool enable) |
0e405443 GP |
3870 | { |
3871 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3872 | ||
3873 | if (enable) | |
d494dd2b LK |
3874 | mlx5e_enable_cvlan_filter(priv->fs, |
3875 | !!(priv->netdev->flags & IFF_PROMISC)); | |
0e405443 | 3876 | else |
d494dd2b LK |
3877 | mlx5e_disable_cvlan_filter(priv->fs, |
3878 | !!(priv->netdev->flags & IFF_PROMISC)); | |
0e405443 GP |
3879 | |
3880 | return 0; | |
3881 | } | |
3882 | ||
214baf22 | 3883 | static int set_feature_hw_tc(struct net_device *netdev, bool enable) |
0e405443 GP |
3884 | { |
3885 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
4f8d1d3a | 3886 | int err = 0; |
f62b8bb8 | 3887 | |
214baf22 | 3888 | #if IS_ENABLED(CONFIG_MLX5_CLS_ACT) |
550f9643 MD |
3889 | int tc_flag = mlx5e_is_uplink_rep(priv) ? MLX5_TC_FLAG(ESW_OFFLOAD) : |
3890 | MLX5_TC_FLAG(NIC_OFFLOAD); | |
3891 | if (!enable && mlx5e_tc_num_filters(priv, tc_flag)) { | |
e8f887ac AV |
3892 | netdev_err(netdev, |
3893 | "Active offloaded tc filters, can't turn hw_tc_offload off\n"); | |
3894 | return -EINVAL; | |
3895 | } | |
214baf22 MM |
3896 | #endif |
3897 | ||
4f8d1d3a MT |
3898 | mutex_lock(&priv->state_lock); |
3899 | if (!enable && mlx5e_selq_is_htb_enabled(&priv->selq)) { | |
214baf22 | 3900 | netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n"); |
4f8d1d3a | 3901 | err = -EINVAL; |
214baf22 | 3902 | } |
4f8d1d3a | 3903 | mutex_unlock(&priv->state_lock); |
e8f887ac | 3904 | |
4f8d1d3a | 3905 | return err; |
0e405443 GP |
3906 | } |
3907 | ||
94cb1ebb EBE |
3908 | static int set_feature_rx_all(struct net_device *netdev, bool enable) |
3909 | { | |
3910 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3911 | struct mlx5_core_dev *mdev = priv->mdev; | |
3912 | ||
3913 | return mlx5_set_port_fcs(mdev, !enable); | |
3914 | } | |
3915 | ||
0bc73ad4 AL |
3916 | static int mlx5e_set_rx_port_ts(struct mlx5_core_dev *mdev, bool enable) |
3917 | { | |
3918 | u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {}; | |
3919 | bool supported, curr_state; | |
3920 | int err; | |
3921 | ||
3922 | if (!MLX5_CAP_GEN(mdev, ports_check)) | |
3923 | return 0; | |
3924 | ||
3925 | err = mlx5_query_ports_check(mdev, in, sizeof(in)); | |
3926 | if (err) | |
3927 | return err; | |
3928 | ||
3929 | supported = MLX5_GET(pcmr_reg, in, rx_ts_over_crc_cap); | |
3930 | curr_state = MLX5_GET(pcmr_reg, in, rx_ts_over_crc); | |
3931 | ||
3932 | if (!supported || enable == curr_state) | |
3933 | return 0; | |
3934 | ||
3935 | MLX5_SET(pcmr_reg, in, local_port, 1); | |
3936 | MLX5_SET(pcmr_reg, in, rx_ts_over_crc, enable); | |
3937 | ||
3938 | return mlx5_set_ports_check(mdev, in, sizeof(in)); | |
3939 | } | |
3940 | ||
1e662209 AF |
3941 | static int mlx5e_set_rx_port_ts_wrap(struct mlx5e_priv *priv, void *ctx) |
3942 | { | |
3943 | struct mlx5_core_dev *mdev = priv->mdev; | |
3944 | bool enable = *(bool *)ctx; | |
3945 | ||
3946 | return mlx5e_set_rx_port_ts(mdev, enable); | |
3947 | } | |
3948 | ||
102722fc GE |
3949 | static int set_feature_rx_fcs(struct net_device *netdev, bool enable) |
3950 | { | |
3951 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
0bc73ad4 | 3952 | struct mlx5e_channels *chs = &priv->channels; |
1e662209 | 3953 | struct mlx5e_params new_params; |
102722fc | 3954 | int err; |
da6192ca | 3955 | bool rx_ts_over_crc = !enable; |
102722fc GE |
3956 | |
3957 | mutex_lock(&priv->state_lock); | |
3958 | ||
1e662209 AF |
3959 | new_params = chs->params; |
3960 | new_params.scatter_fcs_en = enable; | |
3961 | err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_set_rx_port_ts_wrap, | |
da6192ca | 3962 | &rx_ts_over_crc, true); |
0bc73ad4 | 3963 | mutex_unlock(&priv->state_lock); |
102722fc GE |
3964 | return err; |
3965 | } | |
3966 | ||
36350114 GP |
3967 | static int set_feature_rx_vlan(struct net_device *netdev, bool enable) |
3968 | { | |
3969 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
ff9c852f | 3970 | int err = 0; |
36350114 GP |
3971 | |
3972 | mutex_lock(&priv->state_lock); | |
3973 | ||
f52f2fae | 3974 | mlx5e_fs_set_vlan_strip_disable(priv->fs, !enable); |
6a9764ef | 3975 | priv->channels.params.vlan_strip_disable = !enable; |
5b031add | 3976 | |
ff9c852f SM |
3977 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) |
3978 | goto unlock; | |
3979 | ||
3980 | err = mlx5e_modify_channels_vsd(&priv->channels, !enable); | |
5b031add | 3981 | if (err) { |
f52f2fae | 3982 | mlx5e_fs_set_vlan_strip_disable(priv->fs, enable); |
6a9764ef | 3983 | priv->channels.params.vlan_strip_disable = enable; |
5b031add | 3984 | } |
ff9c852f | 3985 | unlock: |
36350114 GP |
3986 | mutex_unlock(&priv->state_lock); |
3987 | ||
3988 | return err; | |
3989 | } | |
3990 | ||
a02c07ea LK |
3991 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) |
3992 | { | |
3993 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3994 | struct mlx5e_flow_steering *fs = priv->fs; | |
3995 | ||
3996 | if (mlx5e_is_uplink_rep(priv)) | |
3997 | return 0; /* no vlan table for uplink rep */ | |
3998 | ||
3999 | return mlx5e_fs_vlan_rx_add_vid(fs, dev, proto, vid); | |
4000 | } | |
4001 | ||
4002 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) | |
4003 | { | |
4004 | struct mlx5e_priv *priv = netdev_priv(dev); | |
4005 | struct mlx5e_flow_steering *fs = priv->fs; | |
4006 | ||
4007 | if (mlx5e_is_uplink_rep(priv)) | |
4008 | return 0; /* no vlan table for uplink rep */ | |
4009 | ||
4010 | return mlx5e_fs_vlan_rx_kill_vid(fs, dev, proto, vid); | |
4011 | } | |
4012 | ||
ec080045 | 4013 | #ifdef CONFIG_MLX5_EN_ARFS |
45bf454a MG |
4014 | static int set_feature_arfs(struct net_device *netdev, bool enable) |
4015 | { | |
4016 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
4017 | int err; | |
4018 | ||
4019 | if (enable) | |
45b83c6c | 4020 | err = mlx5e_arfs_enable(priv->fs); |
45bf454a | 4021 | else |
45b83c6c | 4022 | err = mlx5e_arfs_disable(priv->fs); |
45bf454a MG |
4023 | |
4024 | return err; | |
4025 | } | |
4026 | #endif | |
4027 | ||
0e405443 | 4028 | static int mlx5e_handle_feature(struct net_device *netdev, |
75b81ce7 | 4029 | netdev_features_t *features, |
0e405443 GP |
4030 | netdev_features_t feature, |
4031 | mlx5e_feature_handler feature_handler) | |
4032 | { | |
992d8a4e GP |
4033 | netdev_features_t changes = *features ^ netdev->features; |
4034 | bool enable = !!(*features & feature); | |
0e405443 GP |
4035 | int err; |
4036 | ||
4037 | if (!(changes & feature)) | |
4038 | return 0; | |
4039 | ||
4040 | err = feature_handler(netdev, enable); | |
4041 | if (err) { | |
992d8a4e | 4042 | MLX5E_SET_FEATURE(features, feature, !enable); |
b20eab15 GP |
4043 | netdev_err(netdev, "%s feature %pNF failed, err %d\n", |
4044 | enable ? "Enable" : "Disable", &feature, err); | |
0e405443 GP |
4045 | return err; |
4046 | } | |
4047 | ||
0e405443 GP |
4048 | return 0; |
4049 | } | |
4050 | ||
4d5ab0ad LB |
4051 | void mlx5e_set_xdp_feature(struct net_device *netdev) |
4052 | { | |
4053 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
4054 | struct mlx5e_params *params = &priv->channels.params; | |
4055 | xdp_features_t val; | |
4056 | ||
4057 | if (params->packet_merge.type != MLX5E_PACKET_MERGE_NONE) { | |
4058 | xdp_clear_features_flag(netdev); | |
4059 | return; | |
4060 | } | |
4061 | ||
4062 | val = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | | |
4063 | NETDEV_XDP_ACT_XSK_ZEROCOPY | | |
f52ac702 | 4064 | NETDEV_XDP_ACT_RX_SG | |
c1783e74 TT |
4065 | NETDEV_XDP_ACT_NDO_XMIT | |
4066 | NETDEV_XDP_ACT_NDO_XMIT_SG; | |
4d5ab0ad LB |
4067 | xdp_set_features_flag(netdev, val); |
4068 | } | |
4069 | ||
d3cbd425 | 4070 | int mlx5e_set_features(struct net_device *netdev, netdev_features_t features) |
0e405443 | 4071 | { |
992d8a4e | 4072 | netdev_features_t oper_features = features; |
be0f780b GP |
4073 | int err = 0; |
4074 | ||
4075 | #define MLX5E_HANDLE_FEATURE(feature, handler) \ | |
992d8a4e | 4076 | mlx5e_handle_feature(netdev, &oper_features, feature, handler) |
0e405443 | 4077 | |
be0f780b | 4078 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro); |
83439f3c | 4079 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_GRO_HW, set_feature_hw_gro); |
be0f780b | 4080 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER, |
2b52a283 | 4081 | set_feature_cvlan_filter); |
214baf22 | 4082 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc); |
be0f780b GP |
4083 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all); |
4084 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs); | |
4085 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan); | |
ec080045 | 4086 | #ifdef CONFIG_MLX5_EN_ARFS |
be0f780b | 4087 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs); |
45bf454a | 4088 | #endif |
1182f365 | 4089 | err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx); |
0e405443 | 4090 | |
75b81ce7 GP |
4091 | if (err) { |
4092 | netdev->features = oper_features; | |
4093 | return -EINVAL; | |
4094 | } | |
4095 | ||
4d5ab0ad LB |
4096 | /* update XDP supported features */ |
4097 | mlx5e_set_xdp_feature(netdev); | |
4098 | ||
75b81ce7 | 4099 | return 0; |
f62b8bb8 AV |
4100 | } |
4101 | ||
90b22b9b MD |
4102 | static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev, |
4103 | netdev_features_t features) | |
4104 | { | |
4105 | features &= ~NETIF_F_HW_TLS_RX; | |
4106 | if (netdev->features & NETIF_F_HW_TLS_RX) | |
4107 | netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n"); | |
4108 | ||
4109 | features &= ~NETIF_F_HW_TLS_TX; | |
4110 | if (netdev->features & NETIF_F_HW_TLS_TX) | |
4111 | netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n"); | |
4112 | ||
4113 | features &= ~NETIF_F_NTUPLE; | |
4114 | if (netdev->features & NETIF_F_NTUPLE) | |
4115 | netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n"); | |
4116 | ||
15a5078c AL |
4117 | features &= ~NETIF_F_GRO_HW; |
4118 | if (netdev->features & NETIF_F_GRO_HW) | |
4119 | netdev_warn(netdev, "Disabling HW_GRO, not supported in switchdev mode\n"); | |
4120 | ||
8974aa96 AT |
4121 | features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; |
4122 | if (netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) | |
4123 | netdev_warn(netdev, "Disabling HW_VLAN CTAG FILTERING, not supported in switchdev mode\n"); | |
4124 | ||
90b22b9b MD |
4125 | return features; |
4126 | } | |
4127 | ||
7d92d580 GP |
4128 | static netdev_features_t mlx5e_fix_features(struct net_device *netdev, |
4129 | netdev_features_t features) | |
4130 | { | |
4131 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
f52f2fae | 4132 | struct mlx5e_vlan_table *vlan; |
6c3a823e | 4133 | struct mlx5e_params *params; |
7d92d580 | 4134 | |
ab4b01bf RN |
4135 | if (!netif_device_present(netdev)) |
4136 | return features; | |
4137 | ||
f52f2fae | 4138 | vlan = mlx5e_fs_get_vlan(priv->fs); |
7d92d580 | 4139 | mutex_lock(&priv->state_lock); |
6c3a823e | 4140 | params = &priv->channels.params; |
f52f2fae LK |
4141 | if (!vlan || |
4142 | !bitmap_empty(mlx5e_vlan_get_active_svlans(vlan), VLAN_N_VID)) { | |
7d92d580 GP |
4143 | /* HW strips the outer C-tag header, this is a problem |
4144 | * for S-tag traffic. | |
4145 | */ | |
4146 | features &= ~NETIF_F_HW_VLAN_CTAG_RX; | |
6c3a823e | 4147 | if (!params->vlan_strip_disable) |
7d92d580 GP |
4148 | netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n"); |
4149 | } | |
3ef14e46 | 4150 | |
6c3a823e | 4151 | if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) { |
842a2eb2 | 4152 | if (features & NETIF_F_LRO) { |
6c3a823e | 4153 | netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n"); |
842a2eb2 HN |
4154 | features &= ~NETIF_F_LRO; |
4155 | } | |
83439f3c KM |
4156 | if (features & NETIF_F_GRO_HW) { |
4157 | netdev_warn(netdev, "Disabling HW-GRO, not supported in legacy RQ\n"); | |
4158 | features &= ~NETIF_F_GRO_HW; | |
4159 | } | |
6c3a823e TT |
4160 | } |
4161 | ||
cf6e34c8 MM |
4162 | if (params->xdp_prog) { |
4163 | if (features & NETIF_F_LRO) { | |
4164 | netdev_warn(netdev, "LRO is incompatible with XDP\n"); | |
4165 | features &= ~NETIF_F_LRO; | |
4166 | } | |
b0617e7b MM |
4167 | if (features & NETIF_F_GRO_HW) { |
4168 | netdev_warn(netdev, "HW GRO is incompatible with XDP\n"); | |
4169 | features &= ~NETIF_F_GRO_HW; | |
4170 | } | |
4171 | } | |
4172 | ||
4173 | if (priv->xsk.refcnt) { | |
1c31cb92 MM |
4174 | if (features & NETIF_F_LRO) { |
4175 | netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n", | |
4176 | priv->xsk.refcnt); | |
4177 | features &= ~NETIF_F_LRO; | |
4178 | } | |
b0617e7b MM |
4179 | if (features & NETIF_F_GRO_HW) { |
4180 | netdev_warn(netdev, "HW GRO is incompatible with AF_XDP (%u XSKs are active)\n", | |
4181 | priv->xsk.refcnt); | |
4182 | features &= ~NETIF_F_GRO_HW; | |
4183 | } | |
cf6e34c8 MM |
4184 | } |
4185 | ||
c0194e2d SM |
4186 | if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) { |
4187 | features &= ~NETIF_F_RXHASH; | |
4188 | if (netdev->features & NETIF_F_RXHASH) | |
4189 | netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n"); | |
b5f42903 GP |
4190 | |
4191 | if (features & NETIF_F_GRO_HW) { | |
4192 | netdev_warn(netdev, "Disabling HW-GRO, not supported when CQE compress is active\n"); | |
4193 | features &= ~NETIF_F_GRO_HW; | |
4194 | } | |
c0194e2d SM |
4195 | } |
4196 | ||
c83172b0 | 4197 | if (mlx5e_is_uplink_rep(priv)) { |
90b22b9b | 4198 | features = mlx5e_fix_uplink_rep_features(netdev, features); |
c83172b0 GL |
4199 | features |= NETIF_F_NETNS_LOCAL; |
4200 | } else { | |
4201 | features &= ~NETIF_F_NETNS_LOCAL; | |
4202 | } | |
b38742e4 | 4203 | |
7d92d580 GP |
4204 | mutex_unlock(&priv->state_lock); |
4205 | ||
4206 | return features; | |
4207 | } | |
4208 | ||
db05815b MM |
4209 | static bool mlx5e_xsk_validate_mtu(struct net_device *netdev, |
4210 | struct mlx5e_channels *chs, | |
4211 | struct mlx5e_params *new_params, | |
4212 | struct mlx5_core_dev *mdev) | |
4213 | { | |
4214 | u16 ix; | |
4215 | ||
4216 | for (ix = 0; ix < chs->params.num_channels; ix++) { | |
1742b3d5 MK |
4217 | struct xsk_buff_pool *xsk_pool = |
4218 | mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix); | |
db05815b | 4219 | struct mlx5e_xsk_param xsk; |
78dee7be | 4220 | int max_xdp_mtu; |
db05815b | 4221 | |
1742b3d5 | 4222 | if (!xsk_pool) |
db05815b MM |
4223 | continue; |
4224 | ||
1742b3d5 | 4225 | mlx5e_build_xsk_param(xsk_pool, &xsk); |
78dee7be | 4226 | max_xdp_mtu = mlx5e_xdp_max_mtu(new_params, &xsk); |
db05815b | 4227 | |
78dee7be AF |
4228 | /* Validate XSK params and XDP MTU in advance */ |
4229 | if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev) || | |
4230 | new_params->sw_mtu > max_xdp_mtu) { | |
db05815b MM |
4231 | u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk); |
4232 | int max_mtu_frame, max_mtu_page, max_mtu; | |
4233 | ||
4234 | /* Two criteria must be met: | |
4235 | * 1. HW MTU + all headrooms <= XSK frame size. | |
4236 | * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE. | |
4237 | */ | |
4238 | max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr); | |
411295fb | 4239 | max_mtu_page = MLX5E_HW2SW_MTU(new_params, SKB_MAX_HEAD(0)); |
78dee7be | 4240 | max_mtu = min3(max_mtu_frame, max_mtu_page, max_xdp_mtu); |
db05815b | 4241 | |
78dee7be | 4242 | netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u or its redirection XDP program. Try MTU <= %d\n", |
db05815b MM |
4243 | new_params->sw_mtu, ix, max_mtu); |
4244 | return false; | |
4245 | } | |
4246 | } | |
4247 | ||
4248 | return true; | |
4249 | } | |
4250 | ||
e5a3cc83 MM |
4251 | static bool mlx5e_params_validate_xdp(struct net_device *netdev, |
4252 | struct mlx5_core_dev *mdev, | |
4253 | struct mlx5e_params *params) | |
1b8a10bb MM |
4254 | { |
4255 | bool is_linear; | |
4256 | ||
4257 | /* No XSK params: AF_XDP can't be enabled yet at the point of setting | |
4258 | * the XDP program. | |
4259 | */ | |
7fc06dd2 TT |
4260 | is_linear = params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC ? |
4261 | mlx5e_rx_is_linear_skb(mdev, params, NULL) : | |
4262 | mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL); | |
1b8a10bb | 4263 | |
f52ac702 TT |
4264 | if (!is_linear) { |
4265 | if (!params->xdp_prog->aux->xdp_has_frags) { | |
4266 | netdev_warn(netdev, "MTU(%d) > %d, too big for an XDP program not aware of multi buffer\n", | |
4267 | params->sw_mtu, | |
4268 | mlx5e_xdp_max_mtu(params, NULL)); | |
4269 | return false; | |
4270 | } | |
4271 | if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ && | |
4272 | !mlx5e_verify_params_rx_mpwqe_strides(mdev, params, NULL)) { | |
4273 | netdev_warn(netdev, "XDP is not allowed with striding RQ and MTU(%d) > %d\n", | |
4274 | params->sw_mtu, | |
4275 | mlx5e_xdp_max_mtu(params, NULL)); | |
4276 | return false; | |
4277 | } | |
1b8a10bb MM |
4278 | } |
4279 | ||
4280 | return true; | |
4281 | } | |
4282 | ||
250a42b6 | 4283 | int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, |
b9ab5d0e | 4284 | mlx5e_fp_preactivate preactivate) |
f62b8bb8 AV |
4285 | { |
4286 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
94872d4e | 4287 | struct mlx5e_params new_params; |
472a1e44 | 4288 | struct mlx5e_params *params; |
b3b886cf | 4289 | bool reset = true; |
98e81b0a | 4290 | int err = 0; |
f62b8bb8 | 4291 | |
f62b8bb8 | 4292 | mutex_lock(&priv->state_lock); |
98e81b0a | 4293 | |
472a1e44 | 4294 | params = &priv->channels.params; |
506753b0 | 4295 | |
94872d4e MM |
4296 | new_params = *params; |
4297 | new_params.sw_mtu = new_mtu; | |
4298 | err = mlx5e_validate_params(priv->mdev, &new_params); | |
579524c6 VT |
4299 | if (err) |
4300 | goto out; | |
73281b78 | 4301 | |
e5a3cc83 MM |
4302 | if (new_params.xdp_prog && !mlx5e_params_validate_xdp(netdev, priv->mdev, |
4303 | &new_params)) { | |
a26a5bdf TT |
4304 | err = -EINVAL; |
4305 | goto out; | |
4306 | } | |
4307 | ||
db05815b MM |
4308 | if (priv->xsk.refcnt && |
4309 | !mlx5e_xsk_validate_mtu(netdev, &priv->channels, | |
94872d4e | 4310 | &new_params, priv->mdev)) { |
a26a5bdf TT |
4311 | err = -EINVAL; |
4312 | goto out; | |
4313 | } | |
4314 | ||
eaee12f0 | 4315 | if (params->packet_merge.type == MLX5E_PACKET_MERGE_LRO) |
b3b886cf | 4316 | reset = false; |
69cc4185 | 4317 | |
3904d2af MM |
4318 | if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ && |
4319 | params->packet_merge.type != MLX5E_PACKET_MERGE_SHAMPO) { | |
69cc4185 MM |
4320 | bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL); |
4321 | bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, | |
94872d4e | 4322 | &new_params, NULL); |
e5a3cc83 MM |
4323 | u8 sz_old = mlx5e_mpwqe_get_log_rq_size(priv->mdev, params, NULL); |
4324 | u8 sz_new = mlx5e_mpwqe_get_log_rq_size(priv->mdev, &new_params, NULL); | |
db05815b | 4325 | |
69cc4185 MM |
4326 | /* Always reset in linear mode - hw_mtu is used in data path. |
4327 | * Check that the mode was non-linear and didn't change. | |
4328 | * If XSK is active, XSK RQs are linear. | |
3904d2af | 4329 | * Reset if the RQ size changed, even if it's non-linear. |
69cc4185 MM |
4330 | */ |
4331 | if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt && | |
3904d2af | 4332 | sz_old == sz_new) |
b3b886cf | 4333 | reset = false; |
2e20a151 | 4334 | } |
98e81b0a | 4335 | |
94872d4e | 4336 | err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset); |
f62b8bb8 | 4337 | |
2e20a151 | 4338 | out: |
69cc4185 | 4339 | netdev->mtu = params->sw_mtu; |
2e20a151 | 4340 | mutex_unlock(&priv->state_lock); |
f62b8bb8 AV |
4341 | return err; |
4342 | } | |
4343 | ||
250a42b6 AN |
4344 | static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu) |
4345 | { | |
b9ab5d0e | 4346 | return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx); |
250a42b6 AN |
4347 | } |
4348 | ||
885b8cfb | 4349 | int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx) |
960fbfe2 AL |
4350 | { |
4351 | bool set = *(bool *)ctx; | |
4352 | ||
4353 | return mlx5e_ptp_rx_manage_fs(priv, set); | |
4354 | } | |
4355 | ||
256f79d1 AL |
4356 | static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter) |
4357 | { | |
4358 | bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def; | |
4359 | int err; | |
4360 | ||
4361 | if (!rx_filter) | |
4362 | /* Reset CQE compression to Admin default */ | |
c91c1da7 | 4363 | return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def, false); |
256f79d1 AL |
4364 | |
4365 | if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS)) | |
4366 | return 0; | |
4367 | ||
4368 | /* Disable CQE compression */ | |
4369 | netdev_warn(priv->netdev, "Disabling RX cqe compression\n"); | |
c91c1da7 | 4370 | err = mlx5e_modify_rx_cqe_compression_locked(priv, false, true); |
256f79d1 AL |
4371 | if (err) |
4372 | netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err); | |
4373 | ||
4374 | return err; | |
4375 | } | |
4376 | ||
4377 | static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx) | |
7c39afb3 | 4378 | { |
94872d4e | 4379 | struct mlx5e_params new_params; |
256f79d1 AL |
4380 | |
4381 | if (ptp_rx == priv->channels.params.ptp_rx) | |
4382 | return 0; | |
4383 | ||
4384 | new_params = priv->channels.params; | |
4385 | new_params.ptp_rx = ptp_rx; | |
4386 | return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx, | |
4387 | &new_params.ptp_rx, true); | |
4388 | } | |
4389 | ||
4390 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr) | |
4391 | { | |
7c39afb3 | 4392 | struct hwtstamp_config config; |
960fbfe2 | 4393 | bool rx_cqe_compress_def; |
256f79d1 | 4394 | bool ptp_rx; |
7c39afb3 FD |
4395 | int err; |
4396 | ||
6dbc80ca MS |
4397 | if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) || |
4398 | (mlx5_clock_get_ptp_index(priv->mdev) == -1)) | |
7c39afb3 FD |
4399 | return -EOPNOTSUPP; |
4400 | ||
4401 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
4402 | return -EFAULT; | |
4403 | ||
4404 | /* TX HW timestamp */ | |
4405 | switch (config.tx_type) { | |
4406 | case HWTSTAMP_TX_OFF: | |
4407 | case HWTSTAMP_TX_ON: | |
4408 | break; | |
4409 | default: | |
4410 | return -ERANGE; | |
4411 | } | |
4412 | ||
4413 | mutex_lock(&priv->state_lock); | |
960fbfe2 AL |
4414 | rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def; |
4415 | ||
7c39afb3 FD |
4416 | /* RX HW timestamp */ |
4417 | switch (config.rx_filter) { | |
4418 | case HWTSTAMP_FILTER_NONE: | |
256f79d1 | 4419 | ptp_rx = false; |
7c39afb3 FD |
4420 | break; |
4421 | case HWTSTAMP_FILTER_ALL: | |
4422 | case HWTSTAMP_FILTER_SOME: | |
4423 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
4424 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
4425 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
4426 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
4427 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
4428 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
4429 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
4430 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
4431 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
4432 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
4433 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
4434 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
4435 | case HWTSTAMP_FILTER_NTP_ALL: | |
7c39afb3 | 4436 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
256f79d1 AL |
4437 | /* ptp_rx is set if both HW TS is set and CQE |
4438 | * compression is set | |
4439 | */ | |
4440 | ptp_rx = rx_cqe_compress_def; | |
7c39afb3 FD |
4441 | break; |
4442 | default: | |
256f79d1 AL |
4443 | err = -ERANGE; |
4444 | goto err_unlock; | |
7c39afb3 FD |
4445 | } |
4446 | ||
6c72cb05 | 4447 | if (!mlx5e_profile_feature_cap(priv->profile, PTP_RX)) |
256f79d1 AL |
4448 | err = mlx5e_hwstamp_config_no_ptp_rx(priv, |
4449 | config.rx_filter != HWTSTAMP_FILTER_NONE); | |
4450 | else | |
4451 | err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx); | |
4452 | if (err) | |
4453 | goto err_unlock; | |
960fbfe2 | 4454 | |
7c39afb3 FD |
4455 | memcpy(&priv->tstamp, &config, sizeof(config)); |
4456 | mutex_unlock(&priv->state_lock); | |
4457 | ||
c0194e2d SM |
4458 | /* might need to fix some features */ |
4459 | netdev_update_features(priv->netdev); | |
4460 | ||
7c39afb3 FD |
4461 | return copy_to_user(ifr->ifr_data, &config, |
4462 | sizeof(config)) ? -EFAULT : 0; | |
256f79d1 AL |
4463 | err_unlock: |
4464 | mutex_unlock(&priv->state_lock); | |
4465 | return err; | |
7c39afb3 FD |
4466 | } |
4467 | ||
4468 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr) | |
4469 | { | |
4470 | struct hwtstamp_config *cfg = &priv->tstamp; | |
4471 | ||
4472 | if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz)) | |
4473 | return -EOPNOTSUPP; | |
4474 | ||
4475 | return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0; | |
4476 | } | |
4477 | ||
ef9814de EBE |
4478 | static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
4479 | { | |
1170fbd8 FD |
4480 | struct mlx5e_priv *priv = netdev_priv(dev); |
4481 | ||
ef9814de EBE |
4482 | switch (cmd) { |
4483 | case SIOCSHWTSTAMP: | |
1170fbd8 | 4484 | return mlx5e_hwstamp_set(priv, ifr); |
ef9814de | 4485 | case SIOCGHWTSTAMP: |
1170fbd8 | 4486 | return mlx5e_hwstamp_get(priv, ifr); |
ef9814de EBE |
4487 | default: |
4488 | return -EOPNOTSUPP; | |
4489 | } | |
4490 | } | |
4491 | ||
e80541ec | 4492 | #ifdef CONFIG_MLX5_ESWITCH |
073caf50 | 4493 | int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac) |
66e49ded SM |
4494 | { |
4495 | struct mlx5e_priv *priv = netdev_priv(dev); | |
4496 | struct mlx5_core_dev *mdev = priv->mdev; | |
4497 | ||
4498 | return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac); | |
4499 | } | |
4500 | ||
79aab093 MS |
4501 | static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos, |
4502 | __be16 vlan_proto) | |
66e49ded SM |
4503 | { |
4504 | struct mlx5e_priv *priv = netdev_priv(dev); | |
4505 | struct mlx5_core_dev *mdev = priv->mdev; | |
4506 | ||
79aab093 MS |
4507 | if (vlan_proto != htons(ETH_P_8021Q)) |
4508 | return -EPROTONOSUPPORT; | |
4509 | ||
66e49ded SM |
4510 | return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1, |
4511 | vlan, qos); | |
4512 | } | |
4513 | ||
f942380c MHY |
4514 | static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting) |
4515 | { | |
4516 | struct mlx5e_priv *priv = netdev_priv(dev); | |
4517 | struct mlx5_core_dev *mdev = priv->mdev; | |
4518 | ||
4519 | return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting); | |
4520 | } | |
4521 | ||
1edc57e2 MHY |
4522 | static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting) |
4523 | { | |
4524 | struct mlx5e_priv *priv = netdev_priv(dev); | |
4525 | struct mlx5_core_dev *mdev = priv->mdev; | |
4526 | ||
4527 | return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting); | |
4528 | } | |
bd77bf1c | 4529 | |
073caf50 OG |
4530 | int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, |
4531 | int max_tx_rate) | |
bd77bf1c MHY |
4532 | { |
4533 | struct mlx5e_priv *priv = netdev_priv(dev); | |
4534 | struct mlx5_core_dev *mdev = priv->mdev; | |
4535 | ||
bd77bf1c | 4536 | return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1, |
c9497c98 | 4537 | max_tx_rate, min_tx_rate); |
bd77bf1c MHY |
4538 | } |
4539 | ||
66e49ded SM |
4540 | static int mlx5_vport_link2ifla(u8 esw_link) |
4541 | { | |
4542 | switch (esw_link) { | |
cc9c82a8 | 4543 | case MLX5_VPORT_ADMIN_STATE_DOWN: |
66e49ded | 4544 | return IFLA_VF_LINK_STATE_DISABLE; |
cc9c82a8 | 4545 | case MLX5_VPORT_ADMIN_STATE_UP: |
66e49ded SM |
4546 | return IFLA_VF_LINK_STATE_ENABLE; |
4547 | } | |
4548 | return IFLA_VF_LINK_STATE_AUTO; | |
4549 | } | |
4550 | ||
4551 | static int mlx5_ifla_link2vport(u8 ifla_link) | |
4552 | { | |
4553 | switch (ifla_link) { | |
4554 | case IFLA_VF_LINK_STATE_DISABLE: | |
cc9c82a8 | 4555 | return MLX5_VPORT_ADMIN_STATE_DOWN; |
66e49ded | 4556 | case IFLA_VF_LINK_STATE_ENABLE: |
cc9c82a8 | 4557 | return MLX5_VPORT_ADMIN_STATE_UP; |
66e49ded | 4558 | } |
cc9c82a8 | 4559 | return MLX5_VPORT_ADMIN_STATE_AUTO; |
66e49ded SM |
4560 | } |
4561 | ||
4562 | static int mlx5e_set_vf_link_state(struct net_device *dev, int vf, | |
4563 | int link_state) | |
4564 | { | |
4565 | struct mlx5e_priv *priv = netdev_priv(dev); | |
4566 | struct mlx5_core_dev *mdev = priv->mdev; | |
4567 | ||
1aa48ca6 RD |
4568 | if (mlx5e_is_uplink_rep(priv)) |
4569 | return -EOPNOTSUPP; | |
4570 | ||
66e49ded SM |
4571 | return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1, |
4572 | mlx5_ifla_link2vport(link_state)); | |
4573 | } | |
4574 | ||
073caf50 OG |
4575 | int mlx5e_get_vf_config(struct net_device *dev, |
4576 | int vf, struct ifla_vf_info *ivi) | |
66e49ded SM |
4577 | { |
4578 | struct mlx5e_priv *priv = netdev_priv(dev); | |
4579 | struct mlx5_core_dev *mdev = priv->mdev; | |
4580 | int err; | |
4581 | ||
2ff349c5 RD |
4582 | if (!netif_device_present(dev)) |
4583 | return -EOPNOTSUPP; | |
4584 | ||
66e49ded SM |
4585 | err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi); |
4586 | if (err) | |
4587 | return err; | |
4588 | ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate); | |
4589 | return 0; | |
4590 | } | |
4591 | ||
073caf50 OG |
4592 | int mlx5e_get_vf_stats(struct net_device *dev, |
4593 | int vf, struct ifla_vf_stats *vf_stats) | |
66e49ded SM |
4594 | { |
4595 | struct mlx5e_priv *priv = netdev_priv(dev); | |
4596 | struct mlx5_core_dev *mdev = priv->mdev; | |
4597 | ||
4598 | return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1, | |
4599 | vf_stats); | |
4600 | } | |
ee526030 RD |
4601 | |
4602 | static bool | |
4603 | mlx5e_has_offload_stats(const struct net_device *dev, int attr_id) | |
4604 | { | |
4605 | struct mlx5e_priv *priv = netdev_priv(dev); | |
4606 | ||
2ff349c5 RD |
4607 | if (!netif_device_present(dev)) |
4608 | return false; | |
4609 | ||
ee526030 RD |
4610 | if (!mlx5e_is_uplink_rep(priv)) |
4611 | return false; | |
4612 | ||
4613 | return mlx5e_rep_has_offload_stats(dev, attr_id); | |
4614 | } | |
4615 | ||
4616 | static int | |
4617 | mlx5e_get_offload_stats(int attr_id, const struct net_device *dev, | |
4618 | void *sp) | |
4619 | { | |
4620 | struct mlx5e_priv *priv = netdev_priv(dev); | |
4621 | ||
4622 | if (!mlx5e_is_uplink_rep(priv)) | |
4623 | return -EOPNOTSUPP; | |
4624 | ||
4625 | return mlx5e_rep_get_offload_stats(attr_id, dev, sp); | |
4626 | } | |
e80541ec | 4627 | #endif |
66e49ded | 4628 | |
c28e3bd4 AL |
4629 | static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type) |
4630 | { | |
4631 | switch (proto_type) { | |
4632 | case IPPROTO_GRE: | |
4633 | return MLX5_CAP_ETH(mdev, tunnel_stateless_gre); | |
4634 | case IPPROTO_IPIP: | |
4635 | case IPPROTO_IPV6: | |
4636 | return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) || | |
4637 | MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx)); | |
4638 | default: | |
4639 | return false; | |
4640 | } | |
4641 | } | |
4642 | ||
3d093bc2 AL |
4643 | static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev, |
4644 | struct sk_buff *skb) | |
4645 | { | |
4646 | switch (skb->inner_protocol) { | |
4647 | case htons(ETH_P_IP): | |
4648 | case htons(ETH_P_IPV6): | |
4649 | case htons(ETH_P_TEB): | |
4650 | return true; | |
4651 | case htons(ETH_P_MPLS_UC): | |
4652 | case htons(ETH_P_MPLS_MC): | |
4653 | return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre); | |
4654 | } | |
4655 | return false; | |
4656 | } | |
4657 | ||
27299841 GP |
4658 | static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv, |
4659 | struct sk_buff *skb, | |
4660 | netdev_features_t features) | |
b3f63c3d | 4661 | { |
2989ad1e | 4662 | unsigned int offset = 0; |
b3f63c3d | 4663 | struct udphdr *udph; |
27299841 GP |
4664 | u8 proto; |
4665 | u16 port; | |
b3f63c3d MF |
4666 | |
4667 | switch (vlan_get_protocol(skb)) { | |
4668 | case htons(ETH_P_IP): | |
4669 | proto = ip_hdr(skb)->protocol; | |
4670 | break; | |
4671 | case htons(ETH_P_IPV6): | |
2989ad1e | 4672 | proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL); |
b3f63c3d MF |
4673 | break; |
4674 | default: | |
4675 | goto out; | |
4676 | } | |
4677 | ||
27299841 GP |
4678 | switch (proto) { |
4679 | case IPPROTO_GRE: | |
3d093bc2 AL |
4680 | if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb)) |
4681 | return features; | |
4682 | break; | |
25948b87 MV |
4683 | case IPPROTO_IPIP: |
4684 | case IPPROTO_IPV6: | |
c28e3bd4 | 4685 | if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP)) |
9c98f7ec MV |
4686 | return features; |
4687 | break; | |
27299841 | 4688 | case IPPROTO_UDP: |
b3f63c3d MF |
4689 | udph = udp_hdr(skb); |
4690 | port = be16_to_cpu(udph->dest); | |
b3f63c3d | 4691 | |
27299841 | 4692 | /* Verify if UDP port is being offloaded by HW */ |
358aa5ce | 4693 | if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port)) |
27299841 | 4694 | return features; |
e3cfc7e6 MS |
4695 | |
4696 | #if IS_ENABLED(CONFIG_GENEVE) | |
4697 | /* Support Geneve offload for default UDP port */ | |
4698 | if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev)) | |
4699 | return features; | |
dd7cf00f HN |
4700 | #endif |
4701 | break; | |
4702 | #ifdef CONFIG_MLX5_EN_IPSEC | |
4703 | case IPPROTO_ESP: | |
4704 | return mlx5e_ipsec_feature_check(skb, features); | |
e3cfc7e6 | 4705 | #endif |
27299841 | 4706 | } |
b3f63c3d MF |
4707 | |
4708 | out: | |
4709 | /* Disable CSUM and GSO if the udp dport is not offloaded by HW */ | |
4710 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
4711 | } | |
4712 | ||
073caf50 OG |
4713 | netdev_features_t mlx5e_features_check(struct sk_buff *skb, |
4714 | struct net_device *netdev, | |
4715 | netdev_features_t features) | |
b3f63c3d MF |
4716 | { |
4717 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
4718 | ||
4719 | features = vlan_features_check(skb, features); | |
4720 | features = vxlan_features_check(skb, features); | |
4721 | ||
4722 | /* Validate if the tunneled packet is being offloaded by HW */ | |
4723 | if (skb->encapsulation && | |
4724 | (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK)) | |
27299841 | 4725 | return mlx5e_tunnel_features_check(priv, skb, features); |
b3f63c3d MF |
4726 | |
4727 | return features; | |
4728 | } | |
4729 | ||
bfc647d5 | 4730 | static void mlx5e_tx_timeout_work(struct work_struct *work) |
3947ca18 | 4731 | { |
bfc647d5 EBE |
4732 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, |
4733 | tx_timeout_work); | |
145e5637 | 4734 | struct net_device *netdev = priv->netdev; |
7d91126b | 4735 | int i; |
3947ca18 | 4736 | |
bfc647d5 EBE |
4737 | rtnl_lock(); |
4738 | mutex_lock(&priv->state_lock); | |
4739 | ||
4740 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
4741 | goto unlock; | |
3947ca18 | 4742 | |
145e5637 | 4743 | for (i = 0; i < netdev->real_num_tx_queues; i++) { |
7d91126b | 4744 | struct netdev_queue *dev_queue = |
145e5637 | 4745 | netdev_get_tx_queue(netdev, i); |
acc6c595 | 4746 | struct mlx5e_txqsq *sq = priv->txq2sq[i]; |
3947ca18 | 4747 | |
84990945 | 4748 | if (!netif_xmit_stopped(dev_queue)) |
3947ca18 | 4749 | continue; |
bfc647d5 | 4750 | |
06293ae4 | 4751 | if (mlx5e_reporter_tx_timeout(sq)) |
e6205564 AL |
4752 | /* break if tried to reopened channels */ |
4753 | break; | |
3947ca18 DJ |
4754 | } |
4755 | ||
bfc647d5 EBE |
4756 | unlock: |
4757 | mutex_unlock(&priv->state_lock); | |
4758 | rtnl_unlock(); | |
4759 | } | |
4760 | ||
0290bd29 | 4761 | static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue) |
bfc647d5 EBE |
4762 | { |
4763 | struct mlx5e_priv *priv = netdev_priv(dev); | |
4764 | ||
4765 | netdev_err(dev, "TX timeout detected\n"); | |
4766 | queue_work(priv->wq, &priv->tx_timeout_work); | |
3947ca18 DJ |
4767 | } |
4768 | ||
abd3f84e TT |
4769 | static int mlx5e_xdp_allowed(struct net_device *netdev, struct mlx5_core_dev *mdev, |
4770 | struct mlx5e_params *params) | |
0ec13877 | 4771 | { |
abd3f84e | 4772 | if (params->packet_merge.type != MLX5E_PACKET_MERGE_NONE) { |
eaee12f0 | 4773 | netdev_warn(netdev, "can't set XDP while HW-GRO/LRO is on, disable them first\n"); |
0ec13877 TT |
4774 | return -EINVAL; |
4775 | } | |
4776 | ||
abd3f84e | 4777 | if (!mlx5e_params_validate_xdp(netdev, mdev, params)) |
a26a5bdf | 4778 | return -EINVAL; |
a26a5bdf | 4779 | |
0ec13877 TT |
4780 | return 0; |
4781 | } | |
4782 | ||
fe45386a MM |
4783 | static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog) |
4784 | { | |
4785 | struct bpf_prog *old_prog; | |
4786 | ||
4787 | old_prog = rcu_replace_pointer(rq->xdp_prog, prog, | |
521f31af | 4788 | lockdep_is_held(&rq->priv->state_lock)); |
fe45386a MM |
4789 | if (old_prog) |
4790 | bpf_prog_put(old_prog); | |
4791 | } | |
4792 | ||
86994156 RS |
4793 | static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog) |
4794 | { | |
4795 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
94872d4e | 4796 | struct mlx5e_params new_params; |
86994156 | 4797 | struct bpf_prog *old_prog; |
96d39502 | 4798 | int err = 0; |
b3b886cf | 4799 | bool reset; |
86994156 RS |
4800 | int i; |
4801 | ||
4802 | mutex_lock(&priv->state_lock); | |
4803 | ||
abd3f84e TT |
4804 | new_params = priv->channels.params; |
4805 | new_params.xdp_prog = prog; | |
4806 | ||
0ec13877 | 4807 | if (prog) { |
abd3f84e | 4808 | err = mlx5e_xdp_allowed(netdev, priv->mdev, &new_params); |
0ec13877 TT |
4809 | if (err) |
4810 | goto unlock; | |
547eede0 IT |
4811 | } |
4812 | ||
86994156 | 4813 | /* no need for full reset when exchanging programs */ |
6a9764ef | 4814 | reset = (!priv->channels.params.xdp_prog || !prog); |
86994156 | 4815 | |
b3b886cf | 4816 | old_prog = priv->channels.params.xdp_prog; |
e1895324 | 4817 | |
94872d4e | 4818 | err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset); |
b3b886cf MM |
4819 | if (err) |
4820 | goto unlock; | |
e1895324 | 4821 | |
86994156 RS |
4822 | if (old_prog) |
4823 | bpf_prog_put(old_prog); | |
4824 | ||
b3b886cf | 4825 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset) |
86994156 RS |
4826 | goto unlock; |
4827 | ||
4828 | /* exchanging programs w/o reset, we update ref counts on behalf | |
4829 | * of the channels RQs here. | |
4830 | */ | |
b3b886cf | 4831 | bpf_prog_add(prog, priv->channels.num); |
ff9c852f SM |
4832 | for (i = 0; i < priv->channels.num; i++) { |
4833 | struct mlx5e_channel *c = priv->channels.c[i]; | |
86994156 | 4834 | |
fe45386a | 4835 | mlx5e_rq_replace_xdp_prog(&c->rq, prog); |
e5eb0134 MM |
4836 | if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) { |
4837 | bpf_prog_inc(prog); | |
fe45386a | 4838 | mlx5e_rq_replace_xdp_prog(&c->xskrq, prog); |
e5eb0134 | 4839 | } |
86994156 RS |
4840 | } |
4841 | ||
4842 | unlock: | |
4843 | mutex_unlock(&priv->state_lock); | |
f6279f11 MM |
4844 | |
4845 | /* Need to fix some features. */ | |
4846 | if (!err) | |
4847 | netdev_update_features(netdev); | |
4848 | ||
86994156 RS |
4849 | return err; |
4850 | } | |
4851 | ||
f4e63525 | 4852 | static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp) |
86994156 RS |
4853 | { |
4854 | switch (xdp->command) { | |
4855 | case XDP_SETUP_PROG: | |
4856 | return mlx5e_xdp_set(dev, xdp->prog); | |
1742b3d5 MK |
4857 | case XDP_SETUP_XSK_POOL: |
4858 | return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool, | |
db05815b | 4859 | xdp->xsk.queue_id); |
86994156 RS |
4860 | default: |
4861 | return -EINVAL; | |
4862 | } | |
4863 | } | |
4864 | ||
4b89251d HN |
4865 | #ifdef CONFIG_MLX5_ESWITCH |
4866 | static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, | |
4867 | struct net_device *dev, u32 filter_mask, | |
4868 | int nlflags) | |
4869 | { | |
4870 | struct mlx5e_priv *priv = netdev_priv(dev); | |
4871 | struct mlx5_core_dev *mdev = priv->mdev; | |
4872 | u8 mode, setting; | |
4873 | int err; | |
4874 | ||
4875 | err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting); | |
4876 | if (err) | |
4877 | return err; | |
4878 | mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB; | |
4879 | return ndo_dflt_bridge_getlink(skb, pid, seq, dev, | |
4880 | mode, | |
4881 | 0, 0, nlflags, filter_mask, NULL); | |
4882 | } | |
4883 | ||
4884 | static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, | |
4885 | u16 flags, struct netlink_ext_ack *extack) | |
4886 | { | |
4887 | struct mlx5e_priv *priv = netdev_priv(dev); | |
4888 | struct mlx5_core_dev *mdev = priv->mdev; | |
4889 | struct nlattr *attr, *br_spec; | |
4890 | u16 mode = BRIDGE_MODE_UNDEF; | |
4891 | u8 setting; | |
4892 | int rem; | |
4893 | ||
4894 | br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); | |
4895 | if (!br_spec) | |
4896 | return -EINVAL; | |
4897 | ||
4898 | nla_for_each_nested(attr, br_spec, rem) { | |
4899 | if (nla_type(attr) != IFLA_BRIDGE_MODE) | |
4900 | continue; | |
4901 | ||
4b89251d HN |
4902 | mode = nla_get_u16(attr); |
4903 | if (mode > BRIDGE_MODE_VEPA) | |
4904 | return -EINVAL; | |
4905 | ||
4906 | break; | |
4907 | } | |
4908 | ||
4909 | if (mode == BRIDGE_MODE_UNDEF) | |
4910 | return -EINVAL; | |
4911 | ||
4912 | setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0; | |
4913 | return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting); | |
4914 | } | |
4915 | #endif | |
4916 | ||
4d8fcf21 | 4917 | const struct net_device_ops mlx5e_netdev_ops = { |
f62b8bb8 AV |
4918 | .ndo_open = mlx5e_open, |
4919 | .ndo_stop = mlx5e_close, | |
4920 | .ndo_start_xmit = mlx5e_xmit, | |
0cf0f6d3 | 4921 | .ndo_setup_tc = mlx5e_setup_tc, |
08fb1dac | 4922 | .ndo_select_queue = mlx5e_select_queue, |
f62b8bb8 AV |
4923 | .ndo_get_stats64 = mlx5e_get_stats, |
4924 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
4925 | .ndo_set_mac_address = mlx5e_set_mac, | |
b0eed40e SM |
4926 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, |
4927 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
f62b8bb8 | 4928 | .ndo_set_features = mlx5e_set_features, |
7d92d580 | 4929 | .ndo_fix_features = mlx5e_fix_features, |
250a42b6 | 4930 | .ndo_change_mtu = mlx5e_change_nic_mtu, |
a7605370 | 4931 | .ndo_eth_ioctl = mlx5e_ioctl, |
507f0c81 | 4932 | .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate, |
706b3583 | 4933 | .ndo_features_check = mlx5e_features_check, |
3947ca18 | 4934 | .ndo_tx_timeout = mlx5e_tx_timeout, |
f4e63525 | 4935 | .ndo_bpf = mlx5e_xdp, |
58b99ee3 | 4936 | .ndo_xdp_xmit = mlx5e_xdp_xmit, |
9116e5e2 | 4937 | .ndo_xsk_wakeup = mlx5e_xsk_wakeup, |
ec080045 SM |
4938 | #ifdef CONFIG_MLX5_EN_ARFS |
4939 | .ndo_rx_flow_steer = mlx5e_rx_flow_steer, | |
4940 | #endif | |
e80541ec | 4941 | #ifdef CONFIG_MLX5_ESWITCH |
4b89251d HN |
4942 | .ndo_bridge_setlink = mlx5e_bridge_setlink, |
4943 | .ndo_bridge_getlink = mlx5e_bridge_getlink, | |
4944 | ||
706b3583 | 4945 | /* SRIOV E-Switch NDOs */ |
b0eed40e SM |
4946 | .ndo_set_vf_mac = mlx5e_set_vf_mac, |
4947 | .ndo_set_vf_vlan = mlx5e_set_vf_vlan, | |
f942380c | 4948 | .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk, |
1edc57e2 | 4949 | .ndo_set_vf_trust = mlx5e_set_vf_trust, |
bd77bf1c | 4950 | .ndo_set_vf_rate = mlx5e_set_vf_rate, |
b0eed40e SM |
4951 | .ndo_get_vf_config = mlx5e_get_vf_config, |
4952 | .ndo_set_vf_link_state = mlx5e_set_vf_link_state, | |
4953 | .ndo_get_vf_stats = mlx5e_get_vf_stats, | |
ee526030 RD |
4954 | .ndo_has_offload_stats = mlx5e_has_offload_stats, |
4955 | .ndo_get_offload_stats = mlx5e_get_offload_stats, | |
e80541ec | 4956 | #endif |
f62b8bb8 AV |
4957 | }; |
4958 | ||
707129dc | 4959 | static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout) |
2b029556 SM |
4960 | { |
4961 | int i; | |
4962 | ||
4963 | /* The supported periods are organized in ascending order */ | |
4964 | for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++) | |
4965 | if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout) | |
4966 | break; | |
4967 | ||
4968 | return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]); | |
4969 | } | |
4970 | ||
3ef14e46 | 4971 | void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu) |
f62b8bb8 | 4972 | { |
3ef14e46 | 4973 | struct mlx5e_params *params = &priv->channels.params; |
57c7fce1 | 4974 | struct mlx5_core_dev *mdev = priv->mdev; |
48bfc397 | 4975 | u8 rx_cq_period_mode; |
2fc4bfb7 | 4976 | |
472a1e44 TT |
4977 | params->sw_mtu = mtu; |
4978 | params->hard_mtu = MLX5E_ETH_HARD_MTU; | |
57c7fce1 FL |
4979 | params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2, |
4980 | priv->max_nch); | |
7dbc849b | 4981 | mlx5e_params_mqprio_reset(params); |
2b029556 | 4982 | |
6a9764ef SM |
4983 | /* SQ */ |
4984 | params->log_sq_size = is_kdump_kernel() ? | |
b4e029da KH |
4985 | MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE : |
4986 | MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; | |
040ee617 | 4987 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev)); |
461017cb | 4988 | |
6277053a | 4989 | /* XDP SQ */ |
040ee617 | 4990 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev)); |
6277053a | 4991 | |
b797a684 | 4992 | /* set CQE compression */ |
6a9764ef | 4993 | params->rx_cqe_compress_def = false; |
b797a684 | 4994 | if (MLX5_CAP_GEN(mdev, cqe_compression) && |
e53eef63 | 4995 | MLX5_CAP_GEN(mdev, vport_group_manager)) |
0608d4db | 4996 | params->rx_cqe_compress_def = slow_pci_heuristic(mdev); |
0f6e4cf6 | 4997 | |
6a9764ef | 4998 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def); |
b856df28 | 4999 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false); |
6a9764ef SM |
5000 | |
5001 | /* RQ */ | |
749359f4 | 5002 | mlx5e_build_rq_params(mdev, params); |
b797a684 | 5003 | |
1db1f21c DT |
5004 | params->terminate_lkey_be = mlx5_core_get_terminate_scatter_list_mkey(mdev); |
5005 | ||
eaee12f0 | 5006 | params->packet_merge.timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT); |
b0d4660b | 5007 | |
6a9764ef | 5008 | /* CQ moderation params */ |
48bfc397 | 5009 | rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? |
6a9764ef SM |
5010 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE : |
5011 | MLX5_CQ_PERIOD_MODE_START_FROM_EQE; | |
9a317425 | 5012 | params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation); |
cbce4f44 | 5013 | params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation); |
48bfc397 TG |
5014 | mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode); |
5015 | mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); | |
9908aa29 | 5016 | |
6a9764ef | 5017 | /* TX inline */ |
b431302e | 5018 | mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode); |
a6f402e4 | 5019 | |
db05815b MM |
5020 | /* AF_XDP */ |
5021 | params->xsk = xsk; | |
3ef14e46 SM |
5022 | |
5023 | /* Do not update netdev->features directly in here | |
5024 | * on mlx5e_attach_netdev() we will call mlx5e_update_features() | |
5025 | * To update netdev->features please modify mlx5e_fix_features() | |
5026 | */ | |
6a9764ef | 5027 | } |
f62b8bb8 | 5028 | |
f62b8bb8 AV |
5029 | static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) |
5030 | { | |
5031 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
537e4d2e | 5032 | u8 addr[ETH_ALEN]; |
f62b8bb8 | 5033 | |
537e4d2e JK |
5034 | mlx5_query_mac_address(priv->mdev, addr); |
5035 | if (is_zero_ether_addr(addr) && | |
108805fc SM |
5036 | !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) { |
5037 | eth_hw_addr_random(netdev); | |
5038 | mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr); | |
537e4d2e | 5039 | return; |
108805fc | 5040 | } |
537e4d2e JK |
5041 | |
5042 | eth_hw_addr_set(netdev, addr); | |
f62b8bb8 AV |
5043 | } |
5044 | ||
18a2b7f9 JK |
5045 | static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table, |
5046 | unsigned int entry, struct udp_tunnel_info *ti) | |
5047 | { | |
5048 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
5049 | ||
5050 | return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port)); | |
5051 | } | |
5052 | ||
5053 | static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table, | |
5054 | unsigned int entry, struct udp_tunnel_info *ti) | |
5055 | { | |
5056 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
5057 | ||
5058 | return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port)); | |
5059 | } | |
5060 | ||
5061 | void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv) | |
5062 | { | |
5063 | if (!mlx5_vxlan_allowed(priv->mdev->vxlan)) | |
5064 | return; | |
5065 | ||
5066 | priv->nic_info.set_port = mlx5e_vxlan_set_port; | |
5067 | priv->nic_info.unset_port = mlx5e_vxlan_unset_port; | |
5068 | priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP | | |
5069 | UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN; | |
5070 | priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN; | |
5071 | /* Don't count the space hard-coded to the IANA port */ | |
5072 | priv->nic_info.tables[0].n_entries = | |
5073 | mlx5_vxlan_max_udp_ports(priv->mdev) - 1; | |
5074 | ||
5075 | priv->netdev->udp_tunnel_nic_info = &priv->nic_info; | |
5076 | } | |
5077 | ||
c28e3bd4 AL |
5078 | static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev) |
5079 | { | |
5080 | int tt; | |
5081 | ||
d443c6f6 | 5082 | for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) { |
5fba089e | 5083 | if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5_get_proto_by_tunnel_type(tt))) |
c28e3bd4 AL |
5084 | return true; |
5085 | } | |
5086 | return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)); | |
5087 | } | |
5088 | ||
6bfd390b | 5089 | static void mlx5e_build_nic_netdev(struct net_device *netdev) |
f62b8bb8 AV |
5090 | { |
5091 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
5092 | struct mlx5_core_dev *mdev = priv->mdev; | |
94cb1ebb EBE |
5093 | bool fcs_supported; |
5094 | bool fcs_enabled; | |
f62b8bb8 | 5095 | |
c42260f1 | 5096 | SET_NETDEV_DEV(netdev, mdev->device); |
f62b8bb8 | 5097 | |
e80541ec | 5098 | netdev->netdev_ops = &mlx5e_netdev_ops; |
bc8d405b | 5099 | netdev->xdp_metadata_ops = &mlx5e_xdp_metadata_ops; |
e80541ec | 5100 | |
3f3ab178 | 5101 | mlx5e_dcbnl_build_netdev(netdev); |
66e49ded | 5102 | |
f62b8bb8 AV |
5103 | netdev->watchdog_timeo = 15 * HZ; |
5104 | ||
5105 | netdev->ethtool_ops = &mlx5e_ethtool_ops; | |
5106 | ||
12be4b21 | 5107 | netdev->vlan_features |= NETIF_F_SG; |
e4683f35 | 5108 | netdev->vlan_features |= NETIF_F_HW_CSUM; |
339ccec8 | 5109 | netdev->vlan_features |= NETIF_F_HW_MACSEC; |
f62b8bb8 AV |
5110 | netdev->vlan_features |= NETIF_F_GRO; |
5111 | netdev->vlan_features |= NETIF_F_TSO; | |
5112 | netdev->vlan_features |= NETIF_F_TSO6; | |
5113 | netdev->vlan_features |= NETIF_F_RXCSUM; | |
5114 | netdev->vlan_features |= NETIF_F_RXHASH; | |
682adfa6 | 5115 | netdev->vlan_features |= NETIF_F_GSO_PARTIAL; |
f62b8bb8 | 5116 | |
5dc9520b AL |
5117 | netdev->mpls_features |= NETIF_F_SG; |
5118 | netdev->mpls_features |= NETIF_F_HW_CSUM; | |
5119 | netdev->mpls_features |= NETIF_F_TSO; | |
5120 | netdev->mpls_features |= NETIF_F_TSO6; | |
5121 | ||
71186172 AH |
5122 | netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX; |
5123 | netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX; | |
5124 | ||
26ab7b38 MM |
5125 | /* Tunneled LRO is not supported in the driver, and the same RQs are |
5126 | * shared between inner and outer TIRs, so the driver can't disable LRO | |
5127 | * for inner TIRs while having it enabled for outer TIRs. Due to this, | |
5128 | * block LRO altogether if the firmware declares tunneled LRO support. | |
5129 | */ | |
6c3a823e | 5130 | if (!!MLX5_CAP_ETH(mdev, lro_cap) && |
26ab7b38 MM |
5131 | !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) && |
5132 | !MLX5_CAP_ETH(mdev, tunnel_lro_gre) && | |
168723c1 MM |
5133 | mlx5e_check_fragmented_striding_rq_cap(mdev, PAGE_SHIFT, |
5134 | MLX5E_MPWRQ_UMR_MODE_ALIGNED)) | |
f62b8bb8 AV |
5135 | netdev->vlan_features |= NETIF_F_LRO; |
5136 | ||
5137 | netdev->hw_features = netdev->vlan_features; | |
e4cf27bd | 5138 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; |
f62b8bb8 AV |
5139 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; |
5140 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
4382c7b9 | 5141 | netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX; |
f62b8bb8 | 5142 | |
c28e3bd4 | 5143 | if (mlx5e_tunnel_any_tx_proto_supported(mdev)) { |
e4683f35 | 5144 | netdev->hw_enc_features |= NETIF_F_HW_CSUM; |
b3f63c3d MF |
5145 | netdev->hw_enc_features |= NETIF_F_TSO; |
5146 | netdev->hw_enc_features |= NETIF_F_TSO6; | |
27299841 GP |
5147 | netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL; |
5148 | } | |
5149 | ||
e3cfc7e6 | 5150 | if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) { |
64050cda AL |
5151 | netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | |
5152 | NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
5153 | netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL | | |
5154 | NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
5155 | netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
5156 | netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL | | |
5157 | NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
b3f63c3d MF |
5158 | } |
5159 | ||
c28e3bd4 | 5160 | if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) { |
01c3fd11 AL |
5161 | netdev->hw_features |= NETIF_F_GSO_GRE | |
5162 | NETIF_F_GSO_GRE_CSUM; | |
5163 | netdev->hw_enc_features |= NETIF_F_GSO_GRE | | |
5164 | NETIF_F_GSO_GRE_CSUM; | |
5165 | netdev->gso_partial_features |= NETIF_F_GSO_GRE | | |
5166 | NETIF_F_GSO_GRE_CSUM; | |
27299841 GP |
5167 | } |
5168 | ||
c28e3bd4 | 5169 | if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) { |
25948b87 MV |
5170 | netdev->hw_features |= NETIF_F_GSO_IPXIP4 | |
5171 | NETIF_F_GSO_IPXIP6; | |
5172 | netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 | | |
5173 | NETIF_F_GSO_IPXIP6; | |
5174 | netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 | | |
5175 | NETIF_F_GSO_IPXIP6; | |
5176 | } | |
5177 | ||
3f44899e BP |
5178 | netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4; |
5179 | netdev->hw_features |= NETIF_F_GSO_UDP_L4; | |
5180 | netdev->features |= NETIF_F_GSO_UDP_L4; | |
5181 | ||
94cb1ebb EBE |
5182 | mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled); |
5183 | ||
5184 | if (fcs_supported) | |
5185 | netdev->hw_features |= NETIF_F_RXALL; | |
5186 | ||
102722fc GE |
5187 | if (MLX5_CAP_ETH(mdev, scatter_fcs)) |
5188 | netdev->hw_features |= NETIF_F_RXFCS; | |
5189 | ||
9841d58f MM |
5190 | if (mlx5_qos_is_supported(mdev)) |
5191 | netdev->hw_features |= NETIF_F_HW_TC; | |
5192 | ||
f62b8bb8 | 5193 | netdev->features = netdev->hw_features; |
f62b8bb8 | 5194 | |
3ef14e46 | 5195 | /* Defaults */ |
94cb1ebb EBE |
5196 | if (fcs_enabled) |
5197 | netdev->features &= ~NETIF_F_RXALL; | |
3ef14e46 | 5198 | netdev->features &= ~NETIF_F_LRO; |
83439f3c | 5199 | netdev->features &= ~NETIF_F_GRO_HW; |
3ef14e46 | 5200 | netdev->features &= ~NETIF_F_RXFCS; |
c0194e2d | 5201 | |
e8f887ac AV |
5202 | #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f) |
5203 | if (FT_CAP(flow_modify_en) && | |
5204 | FT_CAP(modify_root) && | |
5205 | FT_CAP(identified_miss_table_mode) && | |
1cabe6b0 | 5206 | FT_CAP(flow_table_modify)) { |
156878d0 | 5207 | #if IS_ENABLED(CONFIG_MLX5_CLS_ACT) |
1cabe6b0 | 5208 | netdev->hw_features |= NETIF_F_HW_TC; |
077ecd78 | 5209 | #endif |
ec080045 | 5210 | #ifdef CONFIG_MLX5_EN_ARFS |
1cabe6b0 MG |
5211 | netdev->hw_features |= NETIF_F_NTUPLE; |
5212 | #endif | |
5213 | } | |
e8f887ac | 5214 | |
f62b8bb8 | 5215 | netdev->features |= NETIF_F_HIGHDMA; |
7d92d580 | 5216 | netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER; |
f62b8bb8 AV |
5217 | |
5218 | netdev->priv_flags |= IFF_UNICAST_FLT; | |
5219 | ||
de78960e | 5220 | netif_set_tso_max_size(netdev, GSO_MAX_SIZE); |
4d5ab0ad | 5221 | mlx5e_set_xdp_feature(netdev); |
f62b8bb8 | 5222 | mlx5e_set_netdev_dev_addr(netdev); |
8ff0ac5b | 5223 | mlx5e_macsec_build_netdev(priv); |
547eede0 | 5224 | mlx5e_ipsec_build_netdev(priv); |
943aa7bd | 5225 | mlx5e_ktls_build_netdev(priv); |
f62b8bb8 AV |
5226 | } |
5227 | ||
1462e48d | 5228 | void mlx5e_create_q_counters(struct mlx5e_priv *priv) |
593cf338 | 5229 | { |
66247fbb LR |
5230 | u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {}; |
5231 | u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {}; | |
593cf338 RS |
5232 | struct mlx5_core_dev *mdev = priv->mdev; |
5233 | int err; | |
5234 | ||
66247fbb LR |
5235 | MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); |
5236 | err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out); | |
5237 | if (!err) | |
5238 | priv->q_counter = | |
5239 | MLX5_GET(alloc_q_counter_out, out, counter_set_id); | |
7cbaf9a3 | 5240 | |
66247fbb LR |
5241 | err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out); |
5242 | if (!err) | |
5243 | priv->drop_rq_q_counter = | |
5244 | MLX5_GET(alloc_q_counter_out, out, counter_set_id); | |
593cf338 RS |
5245 | } |
5246 | ||
1462e48d | 5247 | void mlx5e_destroy_q_counters(struct mlx5e_priv *priv) |
593cf338 | 5248 | { |
66247fbb LR |
5249 | u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {}; |
5250 | ||
5251 | MLX5_SET(dealloc_q_counter_in, in, opcode, | |
5252 | MLX5_CMD_OP_DEALLOC_Q_COUNTER); | |
5253 | if (priv->q_counter) { | |
5254 | MLX5_SET(dealloc_q_counter_in, in, counter_set_id, | |
5255 | priv->q_counter); | |
5256 | mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in); | |
5257 | } | |
593cf338 | 5258 | |
66247fbb LR |
5259 | if (priv->drop_rq_q_counter) { |
5260 | MLX5_SET(dealloc_q_counter_in, in, counter_set_id, | |
5261 | priv->drop_rq_q_counter); | |
5262 | mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in); | |
5263 | } | |
593cf338 RS |
5264 | } |
5265 | ||
182570b2 | 5266 | static int mlx5e_nic_init(struct mlx5_core_dev *mdev, |
3ef14e46 | 5267 | struct net_device *netdev) |
6bfd390b | 5268 | { |
72cc6549 | 5269 | const bool take_rtnl = netdev->reg_state == NETREG_REGISTERED; |
6bfd390b | 5270 | struct mlx5e_priv *priv = netdev_priv(netdev); |
af8bbf73 | 5271 | struct mlx5e_flow_steering *fs; |
547eede0 | 5272 | int err; |
6bfd390b | 5273 | |
3ef14e46 | 5274 | mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu); |
84db6612 | 5275 | mlx5e_vxlan_set_netdev_info(priv); |
519a0bf5 SM |
5276 | |
5277 | mlx5e_timestamp_init(priv); | |
5278 | ||
c4c24fc3 JL |
5279 | priv->dfs_root = debugfs_create_dir("nic", |
5280 | mlx5_debugfs_get_dev_root(mdev)); | |
5281 | ||
5b031add | 5282 | fs = mlx5e_fs_init(priv->profile, mdev, |
3a3da78d GP |
5283 | !test_bit(MLX5E_STATE_DESTROYING, &priv->state), |
5284 | priv->dfs_root); | |
af8bbf73 LK |
5285 | if (!fs) { |
5286 | err = -ENOMEM; | |
68e66e1a | 5287 | mlx5_core_err(mdev, "FS initialization failed, %d\n", err); |
c4c24fc3 | 5288 | debugfs_remove_recursive(priv->dfs_root); |
68e66e1a MS |
5289 | return err; |
5290 | } | |
af8bbf73 | 5291 | priv->fs = fs; |
68e66e1a | 5292 | |
943aa7bd | 5293 | err = mlx5e_ktls_init(priv); |
43585a41 IL |
5294 | if (err) |
5295 | mlx5_core_err(mdev, "TLS initialization failed, %d\n", err); | |
3ef14e46 | 5296 | |
35f69867 | 5297 | mlx5e_health_create_reporters(priv); |
72cc6549 GP |
5298 | |
5299 | /* If netdev is already registered (e.g. move from uplink to nic profile), | |
5300 | * RTNL lock must be held before triggering netdev notifiers. | |
5301 | */ | |
5302 | if (take_rtnl) | |
5303 | rtnl_lock(); | |
5304 | ||
4d5ab0ad LB |
5305 | /* update XDP supported features */ |
5306 | mlx5e_set_xdp_feature(netdev); | |
5307 | ||
72cc6549 GP |
5308 | if (take_rtnl) |
5309 | rtnl_unlock(); | |
5310 | ||
182570b2 | 5311 | return 0; |
6bfd390b HHZ |
5312 | } |
5313 | ||
5314 | static void mlx5e_nic_cleanup(struct mlx5e_priv *priv) | |
5315 | { | |
35f69867 | 5316 | mlx5e_health_destroy_reporters(priv); |
943aa7bd | 5317 | mlx5e_ktls_cleanup(priv); |
af8bbf73 | 5318 | mlx5e_fs_cleanup(priv->fs); |
c4c24fc3 | 5319 | debugfs_remove_recursive(priv->dfs_root); |
0a6b069c | 5320 | priv->fs = NULL; |
6bfd390b HHZ |
5321 | } |
5322 | ||
5323 | static int mlx5e_init_nic_rx(struct mlx5e_priv *priv) | |
5324 | { | |
5325 | struct mlx5_core_dev *mdev = priv->mdev; | |
43ec0f41 | 5326 | enum mlx5e_rx_res_features features; |
6bfd390b | 5327 | int err; |
6bfd390b | 5328 | |
43ec0f41 | 5329 | priv->rx_res = mlx5e_rx_res_alloc(); |
3f22d6c7 MM |
5330 | if (!priv->rx_res) |
5331 | return -ENOMEM; | |
5332 | ||
1462e48d RD |
5333 | mlx5e_create_q_counters(priv); |
5334 | ||
5335 | err = mlx5e_open_drop_rq(priv, &priv->drop_rq); | |
5336 | if (err) { | |
5337 | mlx5_core_err(mdev, "open drop rq failed, %d\n", err); | |
5338 | goto err_destroy_q_counters; | |
5339 | } | |
5340 | ||
3db4c85c | 5341 | features = MLX5E_RX_RES_FEATURE_PTP; |
9a92fe1d | 5342 | if (mlx5_tunnel_inner_ft_supported(mdev)) |
43ec0f41 | 5343 | features |= MLX5E_RX_RES_FEATURE_INNER_FT; |
43ec0f41 | 5344 | err = mlx5e_rx_res_init(priv->rx_res, priv->mdev, features, |
eaee12f0 KM |
5345 | priv->max_nch, priv->drop_rq.rqn, |
5346 | &priv->channels.params.packet_merge, | |
43ec0f41 | 5347 | priv->channels.params.num_channels); |
8f493ffd | 5348 | if (err) |
1462e48d | 5349 | goto err_close_drop_rq; |
6bfd390b | 5350 | |
d494dd2b LK |
5351 | err = mlx5e_create_flow_steering(priv->fs, priv->rx_res, priv->profile, |
5352 | priv->netdev); | |
6bfd390b HHZ |
5353 | if (err) { |
5354 | mlx5_core_warn(mdev, "create flow steering failed, %d\n", err); | |
43ec0f41 | 5355 | goto err_destroy_rx_res; |
6bfd390b HHZ |
5356 | } |
5357 | ||
655dc3d2 | 5358 | err = mlx5e_tc_nic_init(priv); |
6bfd390b HHZ |
5359 | if (err) |
5360 | goto err_destroy_flow_steering; | |
5361 | ||
1182f365 TT |
5362 | err = mlx5e_accel_init_rx(priv); |
5363 | if (err) | |
5364 | goto err_tc_nic_cleanup; | |
5365 | ||
f4aebbfb AL |
5366 | #ifdef CONFIG_MLX5_EN_ARFS |
5367 | priv->netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(priv->mdev); | |
5368 | #endif | |
5369 | ||
6bfd390b HHZ |
5370 | return 0; |
5371 | ||
1182f365 TT |
5372 | err_tc_nic_cleanup: |
5373 | mlx5e_tc_nic_cleanup(priv); | |
6bfd390b | 5374 | err_destroy_flow_steering: |
d494dd2b LK |
5375 | mlx5e_destroy_flow_steering(priv->fs, !!(priv->netdev->hw_features & NETIF_F_NTUPLE), |
5376 | priv->profile); | |
43ec0f41 MM |
5377 | err_destroy_rx_res: |
5378 | mlx5e_rx_res_destroy(priv->rx_res); | |
1462e48d RD |
5379 | err_close_drop_rq: |
5380 | mlx5e_close_drop_rq(&priv->drop_rq); | |
5381 | err_destroy_q_counters: | |
5382 | mlx5e_destroy_q_counters(priv); | |
43ec0f41 | 5383 | mlx5e_rx_res_free(priv->rx_res); |
3f22d6c7 | 5384 | priv->rx_res = NULL; |
6bfd390b HHZ |
5385 | return err; |
5386 | } | |
5387 | ||
5388 | static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv) | |
5389 | { | |
1182f365 | 5390 | mlx5e_accel_cleanup_rx(priv); |
655dc3d2 | 5391 | mlx5e_tc_nic_cleanup(priv); |
d494dd2b LK |
5392 | mlx5e_destroy_flow_steering(priv->fs, !!(priv->netdev->hw_features & NETIF_F_NTUPLE), |
5393 | priv->profile); | |
43ec0f41 | 5394 | mlx5e_rx_res_destroy(priv->rx_res); |
1462e48d RD |
5395 | mlx5e_close_drop_rq(&priv->drop_rq); |
5396 | mlx5e_destroy_q_counters(priv); | |
43ec0f41 | 5397 | mlx5e_rx_res_free(priv->rx_res); |
3f22d6c7 | 5398 | priv->rx_res = NULL; |
6bfd390b HHZ |
5399 | } |
5400 | ||
0bb7228f MT |
5401 | static void mlx5e_set_mqprio_rl(struct mlx5e_priv *priv) |
5402 | { | |
5403 | struct mlx5e_params *params; | |
5404 | struct mlx5e_mqprio_rl *rl; | |
5405 | ||
5406 | params = &priv->channels.params; | |
5407 | if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL) | |
5408 | return; | |
5409 | ||
5410 | rl = mlx5e_mqprio_rl_create(priv->mdev, params->mqprio.num_tc, | |
5411 | params->mqprio.channel.max_rate); | |
5412 | if (IS_ERR(rl)) | |
5413 | rl = NULL; | |
5414 | priv->mqprio_rl = rl; | |
5415 | mlx5e_mqprio_rl_update_params(params, rl); | |
5416 | } | |
5417 | ||
6bfd390b HHZ |
5418 | static int mlx5e_init_nic_tx(struct mlx5e_priv *priv) |
5419 | { | |
5420 | int err; | |
5421 | ||
5422 | err = mlx5e_create_tises(priv); | |
5423 | if (err) { | |
5424 | mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err); | |
5425 | return err; | |
5426 | } | |
5427 | ||
c4dfe704 TT |
5428 | err = mlx5e_accel_init_tx(priv); |
5429 | if (err) | |
5430 | goto err_destroy_tises; | |
5431 | ||
0bb7228f | 5432 | mlx5e_set_mqprio_rl(priv); |
e207b7e9 | 5433 | mlx5e_dcbnl_initialize(priv); |
6bfd390b | 5434 | return 0; |
c4dfe704 TT |
5435 | |
5436 | err_destroy_tises: | |
5437 | mlx5e_destroy_tises(priv); | |
5438 | return err; | |
6bfd390b HHZ |
5439 | } |
5440 | ||
5441 | static void mlx5e_nic_enable(struct mlx5e_priv *priv) | |
5442 | { | |
5443 | struct net_device *netdev = priv->netdev; | |
5444 | struct mlx5_core_dev *mdev = priv->mdev; | |
3fd3fb6b | 5445 | int err; |
2c3b5bee | 5446 | |
069448b2 | 5447 | mlx5e_fs_init_l2_addr(priv->fs, netdev); |
953d7715 | 5448 | mlx5e_ipsec_init(priv); |
2c3b5bee | 5449 | |
3fd3fb6b EH |
5450 | err = mlx5e_macsec_init(priv); |
5451 | if (err) | |
5452 | mlx5_core_err(mdev, "MACsec initialization failed, %d\n", err); | |
5453 | ||
63bfd399 EBE |
5454 | /* Marking the link as currently not needed by the Driver */ |
5455 | if (!netif_running(netdev)) | |
7d0314b1 | 5456 | mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN); |
63bfd399 | 5457 | |
6d7ee2ed | 5458 | mlx5e_set_netdev_mtu_boundaries(priv); |
2c3b5bee | 5459 | mlx5e_set_dev_port_mtu(priv); |
6bfd390b | 5460 | |
8a66e458 | 5461 | mlx5_lag_add_netdev(mdev, netdev); |
7907f23a | 5462 | |
6bfd390b | 5463 | mlx5e_enable_async_events(priv); |
70038b73 | 5464 | mlx5e_enable_blocking_events(priv); |
5c7e8bbb ED |
5465 | if (mlx5e_monitor_counter_supported(priv)) |
5466 | mlx5e_monitor_counter_init(priv); | |
127ea380 | 5467 | |
cef35af3 | 5468 | mlx5e_hv_vhca_stats_create(priv); |
610e89e0 SM |
5469 | if (netdev->reg_state != NETREG_REGISTERED) |
5470 | return; | |
2a5e7a13 | 5471 | mlx5e_dcbnl_init_app(priv); |
610e89e0 | 5472 | |
1aa48ca6 | 5473 | mlx5e_nic_set_rx_mode(priv); |
2c3b5bee SM |
5474 | |
5475 | rtnl_lock(); | |
5476 | if (netif_running(netdev)) | |
5477 | mlx5e_open(netdev); | |
18a2b7f9 | 5478 | udp_tunnel_nic_reset_ntf(priv->netdev); |
2c3b5bee SM |
5479 | netif_device_attach(netdev); |
5480 | rtnl_unlock(); | |
6bfd390b HHZ |
5481 | } |
5482 | ||
5483 | static void mlx5e_nic_disable(struct mlx5e_priv *priv) | |
5484 | { | |
3deef8ce | 5485 | struct mlx5_core_dev *mdev = priv->mdev; |
3deef8ce | 5486 | |
2a5e7a13 HN |
5487 | if (priv->netdev->reg_state == NETREG_REGISTERED) |
5488 | mlx5e_dcbnl_delete_app(priv); | |
2a5e7a13 | 5489 | |
2c3b5bee SM |
5490 | rtnl_lock(); |
5491 | if (netif_running(priv->netdev)) | |
5492 | mlx5e_close(priv->netdev); | |
5493 | netif_device_detach(priv->netdev); | |
5494 | rtnl_unlock(); | |
5495 | ||
1aa48ca6 | 5496 | mlx5e_nic_set_rx_mode(priv); |
1d447a39 | 5497 | |
cef35af3 | 5498 | mlx5e_hv_vhca_stats_destroy(priv); |
5c7e8bbb ED |
5499 | if (mlx5e_monitor_counter_supported(priv)) |
5500 | mlx5e_monitor_counter_cleanup(priv); | |
5501 | ||
70038b73 AL |
5502 | mlx5e_disable_blocking_events(priv); |
5503 | if (priv->en_trap) { | |
5504 | mlx5e_deactivate_trap(priv); | |
5505 | mlx5e_close_trap(priv->en_trap); | |
5506 | priv->en_trap = NULL; | |
5507 | } | |
6bfd390b | 5508 | mlx5e_disable_async_events(priv); |
8a66e458 | 5509 | mlx5_lag_remove_netdev(mdev, priv->netdev); |
c5eb51ad | 5510 | mlx5_vxlan_reset_to_default(mdev->vxlan); |
3fd3fb6b | 5511 | mlx5e_macsec_cleanup(priv); |
953d7715 | 5512 | mlx5e_ipsec_cleanup(priv); |
6bfd390b HHZ |
5513 | } |
5514 | ||
a90f88fe GT |
5515 | int mlx5e_update_nic_rx(struct mlx5e_priv *priv) |
5516 | { | |
80639b19 | 5517 | return mlx5e_refresh_tirs(priv, false, false); |
a90f88fe GT |
5518 | } |
5519 | ||
6bfd390b HHZ |
5520 | static const struct mlx5e_profile mlx5e_nic_profile = { |
5521 | .init = mlx5e_nic_init, | |
5522 | .cleanup = mlx5e_nic_cleanup, | |
5523 | .init_rx = mlx5e_init_nic_rx, | |
5524 | .cleanup_rx = mlx5e_cleanup_nic_rx, | |
5525 | .init_tx = mlx5e_init_nic_tx, | |
5526 | .cleanup_tx = mlx5e_cleanup_nic_tx, | |
5527 | .enable = mlx5e_nic_enable, | |
5528 | .disable = mlx5e_nic_disable, | |
a90f88fe | 5529 | .update_rx = mlx5e_update_nic_rx, |
b521105b | 5530 | .update_stats = mlx5e_stats_update_ndo_stats, |
7ca42c80 | 5531 | .update_carrier = mlx5e_update_carrier, |
5adf4c47 | 5532 | .rx_handlers = &mlx5e_rx_handlers_nic, |
6bfd390b | 5533 | .max_tc = MLX5E_MAX_NUM_TC, |
3460c184 SM |
5534 | .stats_grps = mlx5e_nic_stats_grps, |
5535 | .stats_grps_num = mlx5e_nic_stats_grps_num, | |
1958c2bd TT |
5536 | .features = BIT(MLX5E_PROFILE_FEATURE_PTP_RX) | |
5537 | BIT(MLX5E_PROFILE_FEATURE_PTP_TX) | | |
454533aa LK |
5538 | BIT(MLX5E_PROFILE_FEATURE_QOS_HTB) | |
5539 | BIT(MLX5E_PROFILE_FEATURE_FS_VLAN) | | |
5540 | BIT(MLX5E_PROFILE_FEATURE_FS_TC), | |
6bfd390b HHZ |
5541 | }; |
5542 | ||
473baf2e TT |
5543 | static int mlx5e_profile_max_num_channels(struct mlx5_core_dev *mdev, |
5544 | const struct mlx5e_profile *profile) | |
5545 | { | |
5546 | int nch; | |
5547 | ||
5548 | nch = mlx5e_get_max_num_channels(mdev); | |
5549 | ||
5550 | if (profile->max_nch_limit) | |
5551 | nch = min_t(int, nch, profile->max_nch_limit(mdev)); | |
5552 | return nch; | |
5553 | } | |
5554 | ||
9d758d4a TT |
5555 | static unsigned int |
5556 | mlx5e_calc_max_nch(struct mlx5_core_dev *mdev, struct net_device *netdev, | |
5557 | const struct mlx5e_profile *profile) | |
5558 | ||
5559 | { | |
5560 | unsigned int max_nch, tmp; | |
5561 | ||
5562 | /* core resources */ | |
473baf2e | 5563 | max_nch = mlx5e_profile_max_num_channels(mdev, profile); |
9d758d4a TT |
5564 | |
5565 | /* netdev rx queues */ | |
3db4c85c | 5566 | max_nch = min_t(unsigned int, max_nch, netdev->num_rx_queues); |
9d758d4a TT |
5567 | |
5568 | /* netdev tx queues */ | |
5569 | tmp = netdev->num_tx_queues; | |
5570 | if (mlx5_qos_is_supported(mdev)) | |
5571 | tmp -= mlx5e_qos_max_leaf_nodes(mdev); | |
5572 | if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn)) | |
5573 | tmp -= profile->max_tc; | |
5574 | tmp = tmp / profile->max_tc; | |
5575 | max_nch = min_t(unsigned int, max_nch, tmp); | |
5576 | ||
5577 | return max_nch; | |
5578 | } | |
5579 | ||
6d0ba493 MT |
5580 | int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev) |
5581 | { | |
5582 | /* Indirect TIRS: 2 sets of TTCs (inner + outer steering) | |
5583 | * and 1 set of direct TIRS | |
5584 | */ | |
5585 | return 2 * MLX5E_NUM_INDIR_TIRS | |
5586 | + mlx5e_profile_max_num_channels(mdev, &mlx5e_nic_profile); | |
5587 | } | |
5588 | ||
5b031add LK |
5589 | void mlx5e_set_rx_mode_work(struct work_struct *work) |
5590 | { | |
5591 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, | |
5592 | set_rx_mode_work); | |
5593 | ||
5594 | return mlx5e_fs_set_rx_mode_work(priv->fs, priv->netdev); | |
5595 | } | |
5596 | ||
2c3b5bee | 5597 | /* mlx5e generic netdev management API (move to en_common.c) */ |
c9fd1e33 | 5598 | int mlx5e_priv_init(struct mlx5e_priv *priv, |
9d758d4a | 5599 | const struct mlx5e_profile *profile, |
c9fd1e33 RD |
5600 | struct net_device *netdev, |
5601 | struct mlx5_core_dev *mdev) | |
182570b2 | 5602 | { |
3ab45777 | 5603 | int nch, num_txqs, node; |
8bf30be7 | 5604 | int err; |
0246a57a TT |
5605 | |
5606 | num_txqs = netdev->num_tx_queues; | |
5607 | nch = mlx5e_calc_max_nch(mdev, netdev, profile); | |
5608 | node = dev_to_node(mlx5_core_dma_dev(mdev)); | |
5609 | ||
519a0bf5 SM |
5610 | /* priv init */ |
5611 | priv->mdev = mdev; | |
5612 | priv->netdev = netdev; | |
0246a57a | 5613 | priv->max_nch = nch; |
519a0bf5 | 5614 | priv->max_opened_tc = 1; |
182570b2 | 5615 | |
3909a12e MM |
5616 | if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL)) |
5617 | return -ENOMEM; | |
5618 | ||
519a0bf5 | 5619 | mutex_init(&priv->state_lock); |
8bf30be7 MM |
5620 | |
5621 | err = mlx5e_selq_init(&priv->selq, &priv->state_lock); | |
5622 | if (err) | |
5623 | goto err_free_cpumask; | |
5624 | ||
519a0bf5 SM |
5625 | INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); |
5626 | INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); | |
5627 | INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work); | |
cdeef2b1 | 5628 | INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); |
303211b4 | 5629 | |
182570b2 FD |
5630 | priv->wq = create_singlethread_workqueue("mlx5e"); |
5631 | if (!priv->wq) | |
8bf30be7 | 5632 | goto err_free_selq; |
182570b2 | 5633 | |
0246a57a TT |
5634 | priv->txq2sq = kcalloc_node(num_txqs, sizeof(*priv->txq2sq), GFP_KERNEL, node); |
5635 | if (!priv->txq2sq) | |
5636 | goto err_destroy_workqueue; | |
5637 | ||
5638 | priv->tx_rates = kcalloc_node(num_txqs, sizeof(*priv->tx_rates), GFP_KERNEL, node); | |
5639 | if (!priv->tx_rates) | |
5640 | goto err_free_txq2sq; | |
5641 | ||
0246a57a TT |
5642 | priv->channel_stats = |
5643 | kcalloc_node(nch, sizeof(*priv->channel_stats), GFP_KERNEL, node); | |
5644 | if (!priv->channel_stats) | |
3ab45777 | 5645 | goto err_free_tx_rates; |
0246a57a | 5646 | |
182570b2 | 5647 | return 0; |
3909a12e | 5648 | |
0246a57a TT |
5649 | err_free_tx_rates: |
5650 | kfree(priv->tx_rates); | |
5651 | err_free_txq2sq: | |
5652 | kfree(priv->txq2sq); | |
5653 | err_destroy_workqueue: | |
5654 | destroy_workqueue(priv->wq); | |
8bf30be7 MM |
5655 | err_free_selq: |
5656 | mlx5e_selq_cleanup(&priv->selq); | |
3909a12e MM |
5657 | err_free_cpumask: |
5658 | free_cpumask_var(priv->scratchpad.cpumask); | |
3909a12e | 5659 | return -ENOMEM; |
182570b2 FD |
5660 | } |
5661 | ||
c9fd1e33 | 5662 | void mlx5e_priv_cleanup(struct mlx5e_priv *priv) |
182570b2 | 5663 | { |
214baf22 MM |
5664 | int i; |
5665 | ||
469549e4 RD |
5666 | /* bail if change profile failed and also rollback failed */ |
5667 | if (!priv->mdev) | |
5668 | return; | |
5669 | ||
be98737a TT |
5670 | for (i = 0; i < priv->stats_nch; i++) |
5671 | kvfree(priv->channel_stats[i]); | |
0246a57a | 5672 | kfree(priv->channel_stats); |
0246a57a TT |
5673 | kfree(priv->tx_rates); |
5674 | kfree(priv->txq2sq); | |
182570b2 | 5675 | destroy_workqueue(priv->wq); |
8bf30be7 MM |
5676 | mutex_lock(&priv->state_lock); |
5677 | mlx5e_selq_cleanup(&priv->selq); | |
5678 | mutex_unlock(&priv->state_lock); | |
3909a12e | 5679 | free_cpumask_var(priv->scratchpad.cpumask); |
214baf22 | 5680 | |
db83f24d MT |
5681 | for (i = 0; i < priv->htb_max_qos_sqs; i++) |
5682 | kfree(priv->htb_qos_sq_stats[i]); | |
5683 | kvfree(priv->htb_qos_sq_stats); | |
469549e4 RD |
5684 | |
5685 | memset(priv, 0, sizeof(*priv)); | |
182570b2 FD |
5686 | } |
5687 | ||
1958c2bd TT |
5688 | static unsigned int mlx5e_get_max_num_txqs(struct mlx5_core_dev *mdev, |
5689 | const struct mlx5e_profile *profile) | |
5690 | { | |
5691 | unsigned int nch, ptp_txqs, qos_txqs; | |
5692 | ||
473baf2e | 5693 | nch = mlx5e_profile_max_num_channels(mdev, profile); |
1958c2bd TT |
5694 | |
5695 | ptp_txqs = MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) && | |
5696 | mlx5e_profile_feature_cap(profile, PTP_TX) ? | |
5697 | profile->max_tc : 0; | |
5698 | ||
5699 | qos_txqs = mlx5_qos_is_supported(mdev) && | |
5700 | mlx5e_profile_feature_cap(profile, QOS_HTB) ? | |
5701 | mlx5e_qos_max_leaf_nodes(mdev) : 0; | |
5702 | ||
5703 | return nch * profile->max_tc + ptp_txqs + qos_txqs; | |
5704 | } | |
5705 | ||
5706 | static unsigned int mlx5e_get_max_num_rxqs(struct mlx5_core_dev *mdev, | |
5707 | const struct mlx5e_profile *profile) | |
5708 | { | |
3db4c85c | 5709 | return mlx5e_profile_max_num_channels(mdev, profile); |
1958c2bd TT |
5710 | } |
5711 | ||
3ef14e46 | 5712 | struct net_device * |
1958c2bd | 5713 | mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile) |
f62b8bb8 AV |
5714 | { |
5715 | struct net_device *netdev; | |
1958c2bd | 5716 | unsigned int txqs, rxqs; |
182570b2 | 5717 | int err; |
f62b8bb8 | 5718 | |
1958c2bd TT |
5719 | txqs = mlx5e_get_max_num_txqs(mdev, profile); |
5720 | rxqs = mlx5e_get_max_num_rxqs(mdev, profile); | |
5721 | ||
3ef14e46 | 5722 | netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs); |
f62b8bb8 AV |
5723 | if (!netdev) { |
5724 | mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n"); | |
5725 | return NULL; | |
5726 | } | |
5727 | ||
9d758d4a | 5728 | err = mlx5e_priv_init(netdev_priv(netdev), profile, netdev, mdev); |
182570b2 | 5729 | if (err) { |
c9fd1e33 | 5730 | mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err); |
182570b2 FD |
5731 | goto err_free_netdev; |
5732 | } | |
26e59d80 | 5733 | |
1227bbc5 | 5734 | netif_carrier_off(netdev); |
d08c6e2a | 5735 | netif_tx_disable(netdev); |
3ef14e46 | 5736 | dev_net_set(netdev, mlx5_core_net(mdev)); |
26e59d80 MHY |
5737 | |
5738 | return netdev; | |
5739 | ||
182570b2 | 5740 | err_free_netdev: |
26e59d80 MHY |
5741 | free_netdev(netdev); |
5742 | ||
5743 | return NULL; | |
5744 | } | |
5745 | ||
3ef14e46 SM |
5746 | static void mlx5e_update_features(struct net_device *netdev) |
5747 | { | |
5748 | if (netdev->reg_state != NETREG_REGISTERED) | |
5749 | return; /* features will be updated on netdev registration */ | |
5750 | ||
5751 | rtnl_lock(); | |
5752 | netdev_update_features(netdev); | |
5753 | rtnl_unlock(); | |
5754 | } | |
5755 | ||
77ecd10d SM |
5756 | static void mlx5e_reset_channels(struct net_device *netdev) |
5757 | { | |
5758 | netdev_reset_tc(netdev); | |
5759 | } | |
5760 | ||
2c3b5bee | 5761 | int mlx5e_attach_netdev(struct mlx5e_priv *priv) |
26e59d80 | 5762 | { |
3909a12e | 5763 | const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED; |
3ef14e46 | 5764 | const struct mlx5e_profile *profile = priv->profile; |
a1f240f1 | 5765 | int max_nch; |
26e59d80 MHY |
5766 | int err; |
5767 | ||
26e59d80 | 5768 | clear_bit(MLX5E_STATE_DESTROYING, &priv->state); |
5b031add | 5769 | if (priv->fs) |
f52f2fae LK |
5770 | mlx5e_fs_set_state_destroy(priv->fs, |
5771 | !test_bit(MLX5E_STATE_DESTROYING, &priv->state)); | |
7bb29755 | 5772 | |
f9c955b4 MM |
5773 | /* Validate the max_wqe_size_sq capability. */ |
5774 | if (WARN_ON_ONCE(mlx5e_get_max_sq_wqebbs(priv->mdev) < MLX5E_MAX_TX_WQEBBS)) { | |
163c2c70 SM |
5775 | mlx5_core_warn(priv->mdev, "MLX5E: Max SQ WQEBBs firmware capability: %u, needed %u\n", |
5776 | mlx5e_get_max_sq_wqebbs(priv->mdev), (unsigned int)MLX5E_MAX_TX_WQEBBS); | |
f9c955b4 MM |
5777 | return -EIO; |
5778 | } | |
5779 | ||
a1f240f1 | 5780 | /* max number of channels may have changed */ |
9d758d4a | 5781 | max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile); |
a1f240f1 YA |
5782 | if (priv->channels.params.num_channels > max_nch) { |
5783 | mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch); | |
3909a12e MM |
5784 | /* Reducing the number of channels - RXFH has to be reset, and |
5785 | * mlx5e_num_channels_changed below will build the RQT. | |
5786 | */ | |
fe867cac | 5787 | priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED; |
a1f240f1 | 5788 | priv->channels.params.num_channels = max_nch; |
7dbc849b TT |
5789 | if (priv->channels.params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) { |
5790 | mlx5_core_warn(priv->mdev, "MLX5E: Disabling MQPRIO channel mode\n"); | |
5791 | mlx5e_params_mqprio_reset(&priv->channels.params); | |
5792 | } | |
a1f240f1 | 5793 | } |
9d758d4a TT |
5794 | if (max_nch != priv->max_nch) { |
5795 | mlx5_core_warn(priv->mdev, | |
5796 | "MLX5E: Updating max number of channels from %u to %u\n", | |
5797 | priv->max_nch, max_nch); | |
5798 | priv->max_nch = max_nch; | |
5799 | } | |
5800 | ||
3909a12e MM |
5801 | /* 1. Set the real number of queues in the kernel the first time. |
5802 | * 2. Set our default XPS cpumask. | |
5803 | * 3. Build the RQT. | |
5804 | * | |
5805 | * rtnl_lock is required by netif_set_real_num_*_queues in case the | |
5806 | * netdev has been registered by this point (if this function was called | |
5807 | * in the reload or resume flow). | |
5808 | */ | |
5809 | if (take_rtnl) | |
5810 | rtnl_lock(); | |
fa374877 | 5811 | err = mlx5e_num_channels_changed(priv); |
3909a12e MM |
5812 | if (take_rtnl) |
5813 | rtnl_unlock(); | |
fa374877 MM |
5814 | if (err) |
5815 | goto out; | |
a1f240f1 | 5816 | |
6bfd390b HHZ |
5817 | err = profile->init_tx(priv); |
5818 | if (err) | |
ec8b9981 | 5819 | goto out; |
5c50368f | 5820 | |
6bfd390b HHZ |
5821 | err = profile->init_rx(priv); |
5822 | if (err) | |
1462e48d | 5823 | goto err_cleanup_tx; |
5c50368f | 5824 | |
6bfd390b HHZ |
5825 | if (profile->enable) |
5826 | profile->enable(priv); | |
f62b8bb8 | 5827 | |
3ef14e46 SM |
5828 | mlx5e_update_features(priv->netdev); |
5829 | ||
26e59d80 | 5830 | return 0; |
5c50368f | 5831 | |
1462e48d | 5832 | err_cleanup_tx: |
6bfd390b | 5833 | profile->cleanup_tx(priv); |
5c50368f | 5834 | |
26e59d80 | 5835 | out: |
77ecd10d | 5836 | mlx5e_reset_channels(priv->netdev); |
5cd39b6e | 5837 | set_bit(MLX5E_STATE_DESTROYING, &priv->state); |
5b031add | 5838 | if (priv->fs) |
f52f2fae LK |
5839 | mlx5e_fs_set_state_destroy(priv->fs, |
5840 | !test_bit(MLX5E_STATE_DESTROYING, &priv->state)); | |
5cd39b6e | 5841 | cancel_work_sync(&priv->update_stats_work); |
26e59d80 | 5842 | return err; |
f62b8bb8 AV |
5843 | } |
5844 | ||
2c3b5bee | 5845 | void mlx5e_detach_netdev(struct mlx5e_priv *priv) |
26e59d80 | 5846 | { |
26e59d80 MHY |
5847 | const struct mlx5e_profile *profile = priv->profile; |
5848 | ||
5849 | set_bit(MLX5E_STATE_DESTROYING, &priv->state); | |
5b031add | 5850 | if (priv->fs) |
f52f2fae LK |
5851 | mlx5e_fs_set_state_destroy(priv->fs, |
5852 | !test_bit(MLX5E_STATE_DESTROYING, &priv->state)); | |
26e59d80 | 5853 | |
37f304d1 SM |
5854 | if (profile->disable) |
5855 | profile->disable(priv); | |
5856 | flush_workqueue(priv->wq); | |
5857 | ||
26e59d80 | 5858 | profile->cleanup_rx(priv); |
26e59d80 | 5859 | profile->cleanup_tx(priv); |
77ecd10d | 5860 | mlx5e_reset_channels(priv->netdev); |
cdeef2b1 | 5861 | cancel_work_sync(&priv->update_stats_work); |
26e59d80 MHY |
5862 | } |
5863 | ||
c4d7eb57 | 5864 | static int |
bdf27475 DL |
5865 | mlx5e_netdev_init_profile(struct net_device *netdev, struct mlx5_core_dev *mdev, |
5866 | const struct mlx5e_profile *new_profile, void *new_ppriv) | |
c4d7eb57 | 5867 | { |
469549e4 | 5868 | struct mlx5e_priv *priv = netdev_priv(netdev); |
c4d7eb57 SM |
5869 | int err; |
5870 | ||
9d758d4a | 5871 | err = mlx5e_priv_init(priv, new_profile, netdev, mdev); |
c4d7eb57 | 5872 | if (err) { |
c9fd1e33 | 5873 | mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err); |
c4d7eb57 SM |
5874 | return err; |
5875 | } | |
1227bbc5 | 5876 | netif_carrier_off(netdev); |
c4d7eb57 SM |
5877 | priv->profile = new_profile; |
5878 | priv->ppriv = new_ppriv; | |
5879 | err = new_profile->init(priv->mdev, priv->netdev); | |
5880 | if (err) | |
469549e4 | 5881 | goto priv_cleanup; |
bdf27475 DL |
5882 | |
5883 | return 0; | |
5884 | ||
5885 | priv_cleanup: | |
5886 | mlx5e_priv_cleanup(priv); | |
5887 | return err; | |
5888 | } | |
5889 | ||
5890 | static int | |
5891 | mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev, | |
5892 | const struct mlx5e_profile *new_profile, void *new_ppriv) | |
5893 | { | |
5894 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
5895 | int err; | |
5896 | ||
5897 | err = mlx5e_netdev_init_profile(netdev, mdev, new_profile, new_ppriv); | |
5898 | if (err) | |
5899 | return err; | |
5900 | ||
c4d7eb57 SM |
5901 | err = mlx5e_attach_netdev(priv); |
5902 | if (err) | |
469549e4 RD |
5903 | goto profile_cleanup; |
5904 | return err; | |
5905 | ||
5906 | profile_cleanup: | |
5907 | new_profile->cleanup(priv); | |
469549e4 | 5908 | mlx5e_priv_cleanup(priv); |
c4d7eb57 SM |
5909 | return err; |
5910 | } | |
5911 | ||
5912 | int mlx5e_netdev_change_profile(struct mlx5e_priv *priv, | |
5913 | const struct mlx5e_profile *new_profile, void *new_ppriv) | |
5914 | { | |
c4d7eb57 | 5915 | const struct mlx5e_profile *orig_profile = priv->profile; |
469549e4 RD |
5916 | struct net_device *netdev = priv->netdev; |
5917 | struct mlx5_core_dev *mdev = priv->mdev; | |
c4d7eb57 SM |
5918 | void *orig_ppriv = priv->ppriv; |
5919 | int err, rollback_err; | |
5920 | ||
c4d7eb57 SM |
5921 | /* cleanup old profile */ |
5922 | mlx5e_detach_netdev(priv); | |
5923 | priv->profile->cleanup(priv); | |
c9fd1e33 | 5924 | mlx5e_priv_cleanup(priv); |
c4d7eb57 | 5925 | |
bdf27475 DL |
5926 | if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { |
5927 | mlx5e_netdev_init_profile(netdev, mdev, new_profile, new_ppriv); | |
5928 | set_bit(MLX5E_STATE_DESTROYING, &priv->state); | |
5929 | return -EIO; | |
5930 | } | |
5931 | ||
469549e4 | 5932 | err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv); |
c4d7eb57 | 5933 | if (err) { /* roll back to original profile */ |
469549e4 | 5934 | netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err); |
c4d7eb57 SM |
5935 | goto rollback; |
5936 | } | |
5937 | ||
5938 | return 0; | |
5939 | ||
5940 | rollback: | |
469549e4 RD |
5941 | rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv); |
5942 | if (rollback_err) | |
5943 | netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n", | |
c4d7eb57 | 5944 | __func__, rollback_err); |
c4d7eb57 SM |
5945 | return err; |
5946 | } | |
5947 | ||
7a9fb35e RD |
5948 | void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv) |
5949 | { | |
5950 | mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL); | |
5951 | } | |
5952 | ||
2c3b5bee SM |
5953 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv) |
5954 | { | |
2c3b5bee SM |
5955 | struct net_device *netdev = priv->netdev; |
5956 | ||
c9fd1e33 | 5957 | mlx5e_priv_cleanup(priv); |
2c3b5bee SM |
5958 | free_netdev(netdev); |
5959 | } | |
5960 | ||
912cebf4 | 5961 | static int mlx5e_resume(struct auxiliary_device *adev) |
26e59d80 | 5962 | { |
912cebf4 | 5963 | struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev); |
ee75f1fc JP |
5964 | struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev); |
5965 | struct mlx5e_priv *priv = mlx5e_dev->priv; | |
26e59d80 | 5966 | struct net_device *netdev = priv->netdev; |
912cebf4 | 5967 | struct mlx5_core_dev *mdev = edev->mdev; |
26e59d80 MHY |
5968 | int err; |
5969 | ||
5970 | if (netif_device_present(netdev)) | |
5971 | return 0; | |
5972 | ||
5973 | err = mlx5e_create_mdev_resources(mdev); | |
5974 | if (err) | |
5975 | return err; | |
5976 | ||
2c3b5bee | 5977 | err = mlx5e_attach_netdev(priv); |
26e59d80 MHY |
5978 | if (err) { |
5979 | mlx5e_destroy_mdev_resources(mdev); | |
5980 | return err; | |
5981 | } | |
5982 | ||
5983 | return 0; | |
5984 | } | |
5985 | ||
912cebf4 | 5986 | static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state) |
26e59d80 | 5987 | { |
ee75f1fc JP |
5988 | struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev); |
5989 | struct mlx5e_priv *priv = mlx5e_dev->priv; | |
26e59d80 | 5990 | struct net_device *netdev = priv->netdev; |
912cebf4 | 5991 | struct mlx5_core_dev *mdev = priv->mdev; |
47c9d2c9 | 5992 | |
bdf27475 DL |
5993 | if (!netif_device_present(netdev)) { |
5994 | if (test_bit(MLX5E_STATE_DESTROYING, &priv->state)) | |
5995 | mlx5e_destroy_mdev_resources(mdev); | |
912cebf4 | 5996 | return -ENODEV; |
bdf27475 | 5997 | } |
26e59d80 | 5998 | |
2c3b5bee | 5999 | mlx5e_detach_netdev(priv); |
26e59d80 | 6000 | mlx5e_destroy_mdev_resources(mdev); |
912cebf4 | 6001 | return 0; |
26e59d80 MHY |
6002 | } |
6003 | ||
912cebf4 LR |
6004 | static int mlx5e_probe(struct auxiliary_device *adev, |
6005 | const struct auxiliary_device_id *id) | |
b50d292b | 6006 | { |
912cebf4 | 6007 | struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev); |
3ef14e46 | 6008 | const struct mlx5e_profile *profile = &mlx5e_nic_profile; |
912cebf4 | 6009 | struct mlx5_core_dev *mdev = edev->mdev; |
ee75f1fc | 6010 | struct mlx5e_dev *mlx5e_dev; |
07c9f1e5 | 6011 | struct net_device *netdev; |
912cebf4 | 6012 | pm_message_t state = {}; |
3ef14e46 | 6013 | struct mlx5e_priv *priv; |
26e59d80 | 6014 | int err; |
b50d292b | 6015 | |
de411a82 | 6016 | mlx5e_dev = mlx5e_create_devlink(&adev->dev, mdev); |
ee75f1fc JP |
6017 | if (IS_ERR(mlx5e_dev)) |
6018 | return PTR_ERR(mlx5e_dev); | |
6019 | auxiliary_set_drvdata(adev, mlx5e_dev); | |
6020 | ||
6d6e71e6 JP |
6021 | err = mlx5e_devlink_port_register(mlx5e_dev, mdev); |
6022 | if (err) { | |
6023 | mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err); | |
6024 | goto err_devlink_unregister; | |
6025 | } | |
6026 | ||
1958c2bd | 6027 | netdev = mlx5e_create_netdev(mdev, profile); |
26e59d80 MHY |
6028 | if (!netdev) { |
6029 | mlx5_core_err(mdev, "mlx5e_create_netdev failed\n"); | |
ee75f1fc | 6030 | err = -ENOMEM; |
6d6e71e6 | 6031 | goto err_devlink_port_unregister; |
26e59d80 | 6032 | } |
6d6e71e6 | 6033 | SET_NETDEV_DEVLINK_PORT(netdev, &mlx5e_dev->dl_port); |
26e59d80 | 6034 | |
3ef14e46 SM |
6035 | mlx5e_build_nic_netdev(netdev); |
6036 | ||
26e59d80 | 6037 | priv = netdev_priv(netdev); |
ee75f1fc | 6038 | mlx5e_dev->priv = priv; |
26e59d80 | 6039 | |
3ef14e46 SM |
6040 | priv->profile = profile; |
6041 | priv->ppriv = NULL; | |
865d6d1c | 6042 | |
3ef14e46 SM |
6043 | err = profile->init(mdev, netdev); |
6044 | if (err) { | |
6045 | mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err); | |
6d6e71e6 | 6046 | goto err_destroy_netdev; |
3ef14e46 SM |
6047 | } |
6048 | ||
912cebf4 | 6049 | err = mlx5e_resume(adev); |
26e59d80 | 6050 | if (err) { |
912cebf4 | 6051 | mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err); |
3ef14e46 | 6052 | goto err_profile_cleanup; |
26e59d80 MHY |
6053 | } |
6054 | ||
31e87b39 | 6055 | err = register_netdev(netdev); |
c6acd629 | 6056 | if (err) { |
31e87b39 | 6057 | mlx5_core_err(mdev, "register_netdev failed, %d\n", err); |
912cebf4 | 6058 | goto err_resume; |
c6acd629 VT |
6059 | } |
6060 | ||
2a5e7a13 | 6061 | mlx5e_dcbnl_init_app(priv); |
c7d4e6ab | 6062 | mlx5_core_uplink_netdev_set(mdev, netdev); |
38438d39 | 6063 | mlx5e_params_print_info(mdev, &priv->channels.params); |
912cebf4 | 6064 | return 0; |
26e59d80 | 6065 | |
912cebf4 LR |
6066 | err_resume: |
6067 | mlx5e_suspend(adev, state); | |
3ef14e46 SM |
6068 | err_profile_cleanup: |
6069 | profile->cleanup(priv); | |
26e59d80 | 6070 | err_destroy_netdev: |
2c3b5bee | 6071 | mlx5e_destroy_netdev(priv); |
6d6e71e6 JP |
6072 | err_devlink_port_unregister: |
6073 | mlx5e_devlink_port_unregister(mlx5e_dev); | |
ee75f1fc JP |
6074 | err_devlink_unregister: |
6075 | mlx5e_destroy_devlink(mlx5e_dev); | |
912cebf4 | 6076 | return err; |
b50d292b HHZ |
6077 | } |
6078 | ||
912cebf4 | 6079 | static void mlx5e_remove(struct auxiliary_device *adev) |
b50d292b | 6080 | { |
ee75f1fc JP |
6081 | struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev); |
6082 | struct mlx5e_priv *priv = mlx5e_dev->priv; | |
912cebf4 | 6083 | pm_message_t state = {}; |
127ea380 | 6084 | |
c7d4e6ab | 6085 | mlx5_core_uplink_netdev_set(priv->mdev, NULL); |
2a5e7a13 | 6086 | mlx5e_dcbnl_delete_app(priv); |
5e1e93c7 | 6087 | unregister_netdev(priv->netdev); |
912cebf4 | 6088 | mlx5e_suspend(adev, state); |
3ef14e46 | 6089 | priv->profile->cleanup(priv); |
2c3b5bee | 6090 | mlx5e_destroy_netdev(priv); |
6d6e71e6 | 6091 | mlx5e_devlink_port_unregister(mlx5e_dev); |
ee75f1fc | 6092 | mlx5e_destroy_devlink(mlx5e_dev); |
b50d292b HHZ |
6093 | } |
6094 | ||
912cebf4 LR |
6095 | static const struct auxiliary_device_id mlx5e_id_table[] = { |
6096 | { .name = MLX5_ADEV_NAME ".eth", }, | |
6097 | {}, | |
f62b8bb8 AV |
6098 | }; |
6099 | ||
912cebf4 LR |
6100 | MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table); |
6101 | ||
6102 | static struct auxiliary_driver mlx5e_driver = { | |
6103 | .name = "eth", | |
6104 | .probe = mlx5e_probe, | |
6105 | .remove = mlx5e_remove, | |
6106 | .suspend = mlx5e_suspend, | |
6107 | .resume = mlx5e_resume, | |
6108 | .id_table = mlx5e_id_table, | |
6109 | }; | |
6110 | ||
6111 | int mlx5e_init(void) | |
f62b8bb8 | 6112 | { |
912cebf4 LR |
6113 | int ret; |
6114 | ||
665bc539 | 6115 | mlx5e_build_ptys2ethtool_map(); |
fec2b4bb | 6116 | ret = auxiliary_driver_register(&mlx5e_driver); |
912cebf4 LR |
6117 | if (ret) |
6118 | return ret; | |
6119 | ||
fec2b4bb | 6120 | ret = mlx5e_rep_init(); |
912cebf4 | 6121 | if (ret) |
fec2b4bb | 6122 | auxiliary_driver_unregister(&mlx5e_driver); |
912cebf4 | 6123 | return ret; |
f62b8bb8 AV |
6124 | } |
6125 | ||
6126 | void mlx5e_cleanup(void) | |
6127 | { | |
912cebf4 | 6128 | mlx5e_rep_cleanup(); |
fec2b4bb | 6129 | auxiliary_driver_unregister(&mlx5e_driver); |
f62b8bb8 | 6130 | } |