[thirdparty/kernel/stable.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_stats.h

/*
 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef __MLX5_EN_STATS_H__
#define __MLX5_EN_STATS_H__

#define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
	(*(u64 *)((char *)ptr + dsc[i].offset))
#define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
	be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
#define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
	(*(u32 *)((char *)ptr + dsc[i].offset))
#define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
	be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))

#define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
#define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
#define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
#define MLX5E_DECLARE_XDPSQ_STAT(type, fld) "tx%d_xdp_"#fld, offsetof(type, fld)
#define MLX5E_DECLARE_RQ_XDPSQ_STAT(type, fld) "rx%d_xdp_tx_"#fld, offsetof(type, fld)
#define MLX5E_DECLARE_XSKRQ_STAT(type, fld) "rx%d_xsk_"#fld, offsetof(type, fld)
#define MLX5E_DECLARE_XSKSQ_STAT(type, fld) "tx%d_xsk_"#fld, offsetof(type, fld)
#define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld)

#define MLX5E_DECLARE_PTP_TX_STAT(type, fld) "ptp_tx%d_"#fld, offsetof(type, fld)
#define MLX5E_DECLARE_PTP_CH_STAT(type, fld) "ptp_ch_"#fld, offsetof(type, fld)
#define MLX5E_DECLARE_PTP_CQ_STAT(type, fld) "ptp_cq%d_"#fld, offsetof(type, fld)
#define MLX5E_DECLARE_PTP_RQ_STAT(type, fld) "ptp_rq%d_"#fld, offsetof(type, fld)

#define MLX5E_DECLARE_QOS_TX_STAT(type, fld) "qos_tx%d_"#fld, offsetof(type, fld)

struct counter_desc {
	char		format[ETH_GSTRING_LEN];
	size_t		offset; /* Byte offset */
};

enum {
	MLX5E_NDO_UPDATE_STATS = BIT(0x1),
};

struct mlx5e_priv;
struct mlx5e_stats_grp {
	u16 update_stats_mask;
	int (*get_num_stats)(struct mlx5e_priv *priv);
	int (*fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx);
	int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx);
	void (*update_stats)(struct mlx5e_priv *priv);
};

typedef const struct mlx5e_stats_grp *const mlx5e_stats_grp_t;

#define MLX5E_STATS_GRP_OP(grp, name) mlx5e_stats_grp_ ## grp ## _ ## name

#define MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(grp) \
	int MLX5E_STATS_GRP_OP(grp, num_stats)(struct mlx5e_priv *priv)

#define MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(grp) \
	void MLX5E_STATS_GRP_OP(grp, update_stats)(struct mlx5e_priv *priv)

#define MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(grp) \
	int MLX5E_STATS_GRP_OP(grp, fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx)

#define MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(grp) \
	int MLX5E_STATS_GRP_OP(grp, fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx)

#define MLX5E_STATS_GRP(grp) mlx5e_stats_grp_ ## grp

#define MLX5E_DECLARE_STATS_GRP(grp) \
	const struct mlx5e_stats_grp MLX5E_STATS_GRP(grp)

#define MLX5E_DEFINE_STATS_GRP(grp, mask) \
MLX5E_DECLARE_STATS_GRP(grp) = { \
	.get_num_stats = MLX5E_STATS_GRP_OP(grp, num_stats), \
	.fill_stats    = MLX5E_STATS_GRP_OP(grp, fill_stats), \
	.fill_strings  = MLX5E_STATS_GRP_OP(grp, fill_strings), \
	.update_stats  = MLX5E_STATS_GRP_OP(grp, update_stats), \
	.update_stats_mask = mask, \
}

unsigned int mlx5e_stats_total_num(struct mlx5e_priv *priv);
void mlx5e_stats_update(struct mlx5e_priv *priv);
void mlx5e_stats_fill(struct mlx5e_priv *priv, u64 *data, int idx);
void mlx5e_stats_fill_strings(struct mlx5e_priv *priv, u8 *data);
void mlx5e_stats_update_ndo_stats(struct mlx5e_priv *priv);

void mlx5e_stats_pause_get(struct mlx5e_priv *priv,
			   struct ethtool_pause_stats *pause_stats);
void mlx5e_stats_fec_get(struct mlx5e_priv *priv,
			 struct ethtool_fec_stats *fec_stats);

void mlx5e_stats_eth_phy_get(struct mlx5e_priv *priv,
			     struct ethtool_eth_phy_stats *phy_stats);
void mlx5e_stats_eth_mac_get(struct mlx5e_priv *priv,
			     struct ethtool_eth_mac_stats *mac_stats);
void mlx5e_stats_eth_ctrl_get(struct mlx5e_priv *priv,
			      struct ethtool_eth_ctrl_stats *ctrl_stats);
void mlx5e_stats_rmon_get(struct mlx5e_priv *priv,
			  struct ethtool_rmon_stats *rmon,
			  const struct ethtool_rmon_hist_range **ranges);
void mlx5e_get_link_ext_stats(struct net_device *dev,
			      struct ethtool_link_ext_stats *stats);

/* Concrete NIC Stats */

struct mlx5e_sw_stats {
	u64 rx_packets;
	u64 rx_bytes;
	u64 tx_packets;
	u64 tx_bytes;
	u64 tx_tso_packets;
	u64 tx_tso_bytes;
	u64 tx_tso_inner_packets;
	u64 tx_tso_inner_bytes;
	u64 tx_added_vlan_packets;
	u64 tx_nop;
	u64 tx_mpwqe_blks;
	u64 tx_mpwqe_pkts;
	u64 rx_lro_packets;
	u64 rx_lro_bytes;
	u64 rx_gro_packets;
	u64 rx_gro_bytes;
	u64 rx_gro_skbs;
	u64 rx_gro_match_packets;
	u64 rx_gro_large_hds;
	u64 rx_mcast_packets;
	u64 rx_ecn_mark;
	u64 rx_removed_vlan_packets;
	u64 rx_csum_unnecessary;
	u64 rx_csum_none;
	u64 rx_csum_complete;
	u64 rx_csum_complete_tail;
	u64 rx_csum_complete_tail_slow;
	u64 rx_csum_unnecessary_inner;
	u64 rx_xdp_drop;
	u64 rx_xdp_redirect;
	u64 rx_xdp_tx_xmit;
	u64 rx_xdp_tx_mpwqe;
	u64 rx_xdp_tx_inlnw;
	u64 rx_xdp_tx_nops;
	u64 rx_xdp_tx_full;
	u64 rx_xdp_tx_err;
	u64 rx_xdp_tx_cqe;
	u64 tx_csum_none;
	u64 tx_csum_partial;
	u64 tx_csum_partial_inner;
	u64 tx_queue_stopped;
	u64 tx_queue_dropped;
	u64 tx_xmit_more;
	u64 tx_recover;
	u64 tx_cqes;
	u64 tx_queue_wake;
	u64 tx_cqe_err;
	u64 tx_xdp_xmit;
	u64 tx_xdp_mpwqe;
	u64 tx_xdp_inlnw;
	u64 tx_xdp_nops;
	u64 tx_xdp_full;
	u64 tx_xdp_err;
	u64 tx_xdp_cqes;
	u64 rx_wqe_err;
	u64 rx_mpwqe_filler_cqes;
	u64 rx_mpwqe_filler_strides;
	u64 rx_oversize_pkts_sw_drop;
	u64 rx_buff_alloc_err;
	u64 rx_cqe_compress_blks;
	u64 rx_cqe_compress_pkts;
	u64 rx_congst_umr;
#ifdef CONFIG_MLX5_EN_ARFS
	u64 rx_arfs_add;
	u64 rx_arfs_request_in;
	u64 rx_arfs_request_out;
	u64 rx_arfs_expired;
	u64 rx_arfs_err;
#endif
	u64 rx_recover;
	u64 ch_events;
	u64 ch_poll;
	u64 ch_arm;
	u64 ch_aff_change;
	u64 ch_force_irq;
	u64 ch_eq_rearm;
#ifdef CONFIG_PAGE_POOL_STATS
	u64 rx_pp_alloc_fast;
	u64 rx_pp_alloc_slow;
	u64 rx_pp_alloc_slow_high_order;
	u64 rx_pp_alloc_empty;
	u64 rx_pp_alloc_refill;
	u64 rx_pp_alloc_waive;
	u64 rx_pp_recycle_cached;
	u64 rx_pp_recycle_cache_full;
	u64 rx_pp_recycle_ring;
	u64 rx_pp_recycle_ring_full;
	u64 rx_pp_recycle_released_ref;
#endif
#ifdef CONFIG_MLX5_EN_TLS
	u64 tx_tls_encrypted_packets;
	u64 tx_tls_encrypted_bytes;
	u64 tx_tls_ooo;
	u64 tx_tls_dump_packets;
	u64 tx_tls_dump_bytes;
	u64 tx_tls_resync_bytes;
	u64 tx_tls_skip_no_sync_data;
	u64 tx_tls_drop_no_sync_data;
	u64 tx_tls_drop_bypass_req;

	u64 rx_tls_decrypted_packets;
	u64 rx_tls_decrypted_bytes;
	u64 rx_tls_resync_req_pkt;
	u64 rx_tls_resync_req_start;
	u64 rx_tls_resync_req_end;
	u64 rx_tls_resync_req_skip;
	u64 rx_tls_resync_res_ok;
	u64 rx_tls_resync_res_retry;
	u64 rx_tls_resync_res_skip;
	u64 rx_tls_err;
#endif

	u64 rx_xsk_packets;
	u64 rx_xsk_bytes;
	u64 rx_xsk_csum_complete;
	u64 rx_xsk_csum_unnecessary;
	u64 rx_xsk_csum_unnecessary_inner;
	u64 rx_xsk_csum_none;
	u64 rx_xsk_ecn_mark;
	u64 rx_xsk_removed_vlan_packets;
	u64 rx_xsk_xdp_drop;
	u64 rx_xsk_xdp_redirect;
	u64 rx_xsk_wqe_err;
	u64 rx_xsk_mpwqe_filler_cqes;
	u64 rx_xsk_mpwqe_filler_strides;
	u64 rx_xsk_oversize_pkts_sw_drop;
	u64 rx_xsk_buff_alloc_err;
	u64 rx_xsk_cqe_compress_blks;
	u64 rx_xsk_cqe_compress_pkts;
	u64 rx_xsk_congst_umr;
	u64 tx_xsk_xmit;
	u64 tx_xsk_mpwqe;
	u64 tx_xsk_inlnw;
	u64 tx_xsk_full;
	u64 tx_xsk_err;
	u64 tx_xsk_cqes;
};

struct mlx5e_qcounter_stats {
	u32 rx_out_of_buffer;
	u32 rx_if_down_packets;
};

#define VNIC_ENV_GET(vnic_env_stats, c) \
	MLX5_GET(query_vnic_env_out, (vnic_env_stats)->query_vnic_env_out, \
		 vport_env.c)

struct mlx5e_vnic_env_stats {
	__be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)];
};

#define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
						vstats->query_vport_out, c)

struct mlx5e_vport_stats {
	__be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
};

#define PPORT_802_3_GET(pstats, c) \
	MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
		   counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
#define PPORT_2863_GET(pstats, c) \
	MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
		   counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
#define PPORT_2819_GET(pstats, c) \
	MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
		   counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
#define PPORT_PHY_STATISTICAL_GET(pstats, c) \
	MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
		   counter_set.phys_layer_statistical_cntrs.c##_high)
#define PPORT_PER_PRIO_GET(pstats, prio, c) \
	MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
		   counter_set.eth_per_prio_grp_data_layout.c##_high)
#define NUM_PPORT_PRIO				8
#define PPORT_ETH_EXT_GET(pstats, c) \
	MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
		   counter_set.eth_extended_cntrs_grp_data_layout.c##_high)

struct mlx5e_pport_stats {
	__be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
	__be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
	__be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
	__be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
	__be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
	__be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
	__be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
	__be64 per_tc_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
	__be64 per_tc_congest_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
};

#define PCIE_PERF_GET(pcie_stats, c) \
	MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
		 counter_set.pcie_perf_cntrs_grp_data_layout.c)

#define PCIE_PERF_GET64(pcie_stats, c) \
	MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
		   counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)

struct mlx5e_pcie_stats {
	__be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
};

struct mlx5e_rq_stats {
	u64 packets;
	u64 bytes;
	u64 csum_complete;
	u64 csum_complete_tail;
	u64 csum_complete_tail_slow;
	u64 csum_unnecessary;
	u64 csum_unnecessary_inner;
	u64 csum_none;
	u64 lro_packets;
	u64 lro_bytes;
	u64 gro_packets;
	u64 gro_bytes;
	u64 gro_skbs;
	u64 gro_match_packets;
	u64 gro_large_hds;
	u64 mcast_packets;
	u64 ecn_mark;
	u64 removed_vlan_packets;
	u64 xdp_drop;
	u64 xdp_redirect;
	u64 wqe_err;
	u64 mpwqe_filler_cqes;
	u64 mpwqe_filler_strides;
	u64 oversize_pkts_sw_drop;
	u64 buff_alloc_err;
	u64 cqe_compress_blks;
	u64 cqe_compress_pkts;
	u64 congst_umr;
#ifdef CONFIG_MLX5_EN_ARFS
	u64 arfs_add;
	u64 arfs_request_in;
	u64 arfs_request_out;
	u64 arfs_expired;
	u64 arfs_err;
#endif
	u64 recover;
#ifdef CONFIG_PAGE_POOL_STATS
	u64 pp_alloc_fast;
	u64 pp_alloc_slow;
	u64 pp_alloc_slow_high_order;
	u64 pp_alloc_empty;
	u64 pp_alloc_refill;
	u64 pp_alloc_waive;
	u64 pp_recycle_cached;
	u64 pp_recycle_cache_full;
	u64 pp_recycle_ring;
	u64 pp_recycle_ring_full;
	u64 pp_recycle_released_ref;
#endif
#ifdef CONFIG_MLX5_EN_TLS
	u64 tls_decrypted_packets;
	u64 tls_decrypted_bytes;
	u64 tls_resync_req_pkt;
	u64 tls_resync_req_start;
	u64 tls_resync_req_end;
	u64 tls_resync_req_skip;
	u64 tls_resync_res_ok;
	u64 tls_resync_res_retry;
	u64 tls_resync_res_skip;
	u64 tls_err;
#endif
};

struct mlx5e_sq_stats {
	/* commonly accessed in data path */
	u64 packets;
	u64 bytes;
	u64 xmit_more;
	u64 tso_packets;
	u64 tso_bytes;
	u64 tso_inner_packets;
	u64 tso_inner_bytes;
	u64 csum_partial;
	u64 csum_partial_inner;
	u64 added_vlan_packets;
	u64 nop;
	u64 mpwqe_blks;
	u64 mpwqe_pkts;
#ifdef CONFIG_MLX5_EN_TLS
	u64 tls_encrypted_packets;
	u64 tls_encrypted_bytes;
	u64 tls_ooo;
	u64 tls_dump_packets;
	u64 tls_dump_bytes;
	u64 tls_resync_bytes;
	u64 tls_skip_no_sync_data;
	u64 tls_drop_no_sync_data;
	u64 tls_drop_bypass_req;
#endif
	/* less likely accessed in data path */
	u64 csum_none;
	u64 stopped;
	u64 dropped;
	u64 recover;
	/* dirtied @completion */
	u64 cqes ____cacheline_aligned_in_smp;
	u64 wake;
	u64 cqe_err;
};

struct mlx5e_xdpsq_stats {
	u64 xmit;
	u64 mpwqe;
	u64 inlnw;
	u64 nops;
	u64 full;
	u64 err;
	/* dirtied @completion */
	u64 cqes ____cacheline_aligned_in_smp;
};

struct mlx5e_ch_stats {
	u64 events;
	u64 poll;
	u64 arm;
	u64 aff_change;
	u64 force_irq;
	u64 eq_rearm;
};

struct mlx5e_ptp_cq_stats {
	u64 cqe;
	u64 err_cqe;
	u64 abort;
	u64 abort_abs_diff_ns;
	u64 late_cqe;
};

struct mlx5e_rep_stats {
	u64 vport_rx_packets;
	u64 vport_tx_packets;
	u64 vport_rx_bytes;
	u64 vport_tx_bytes;
	u64 rx_vport_rdma_unicast_packets;
	u64 tx_vport_rdma_unicast_packets;
	u64 rx_vport_rdma_unicast_bytes;
	u64 tx_vport_rdma_unicast_bytes;
	u64 rx_vport_rdma_multicast_packets;
	u64 tx_vport_rdma_multicast_packets;
	u64 rx_vport_rdma_multicast_bytes;
	u64 tx_vport_rdma_multicast_bytes;
};

struct mlx5e_stats {
	struct mlx5e_sw_stats sw;
	struct mlx5e_qcounter_stats qcnt;
	struct mlx5e_vnic_env_stats vnic;
	struct mlx5e_vport_stats vport;
	struct mlx5e_pport_stats pport;
	struct mlx5e_pcie_stats pcie;
	struct mlx5e_rep_stats rep_stats;
};

static inline void mlx5e_stats_copy_rep_stats(struct rtnl_link_stats64 *vf_vport,
					      struct mlx5e_rep_stats *rep_stats)
{
	memset(vf_vport, 0, sizeof(*vf_vport));
	vf_vport->rx_packets = rep_stats->vport_rx_packets;
	vf_vport->tx_packets = rep_stats->vport_tx_packets;
	vf_vport->rx_bytes = rep_stats->vport_rx_bytes;
	vf_vport->tx_bytes = rep_stats->vport_tx_bytes;
}

extern mlx5e_stats_grp_t mlx5e_nic_stats_grps[];
unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv);

extern MLX5E_DECLARE_STATS_GRP(sw);
extern MLX5E_DECLARE_STATS_GRP(qcnt);
extern MLX5E_DECLARE_STATS_GRP(vnic_env);
extern MLX5E_DECLARE_STATS_GRP(vport);
extern MLX5E_DECLARE_STATS_GRP(802_3);
extern MLX5E_DECLARE_STATS_GRP(2863);
extern MLX5E_DECLARE_STATS_GRP(2819);
extern MLX5E_DECLARE_STATS_GRP(phy);
extern MLX5E_DECLARE_STATS_GRP(eth_ext);
extern MLX5E_DECLARE_STATS_GRP(pcie);
extern MLX5E_DECLARE_STATS_GRP(per_prio);
extern MLX5E_DECLARE_STATS_GRP(pme);
extern MLX5E_DECLARE_STATS_GRP(channels);
extern MLX5E_DECLARE_STATS_GRP(per_port_buff_congest);
extern MLX5E_DECLARE_STATS_GRP(ipsec_hw);
extern MLX5E_DECLARE_STATS_GRP(ipsec_sw);
extern MLX5E_DECLARE_STATS_GRP(ptp);
extern MLX5E_DECLARE_STATS_GRP(macsec_hw);

#endif /* __MLX5_EN_STATS_H__ */
Commit	Line	Data
9218b44d GP	1	/*
	2	* Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
96b12796	32
9218b44d GP	33	#ifndef __MLX5_EN_STATS_H__
	34	#define __MLX5_EN_STATS_H__
	35
	36	#define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
	37	((u64 )((char *)ptr + dsc[i].offset))
	38	#define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
	39	be64_to_cpu((__be64 )((char *)ptr + dsc[i].offset))
	40	#define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
	41	((u32 )((char *)ptr + dsc[i].offset))
	42	#define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
0f7f3481	43	be32_to_cpu((__be32 )((char *)ptr + dsc[i].offset))
9218b44d GP	44
9218b44d GP	45	#define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
bfe6d8d1 GP	46	#define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
bfe6d8d1 GP	47	#define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
58b99ee3	48	#define MLX5E_DECLARE_XDPSQ_STAT(type, fld) "tx%d_xdp_"#fld, offsetof(type, fld)
890388ad	49	#define MLX5E_DECLARE_RQ_XDPSQ_STAT(type, fld) "rx%d_xdp_tx_"#fld, offsetof(type, fld)
db05815b MM	50	#define MLX5E_DECLARE_XSKRQ_STAT(type, fld) "rx%d_xsk_"#fld, offsetof(type, fld)
db05815b MM	51	#define MLX5E_DECLARE_XSKSQ_STAT(type, fld) "tx%d_xsk_"#fld, offsetof(type, fld)
57d689a8	52	#define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld)
9218b44d	53
145e5637 EBE	54	#define MLX5E_DECLARE_PTP_TX_STAT(type, fld) "ptp_tx%d_"#fld, offsetof(type, fld)
145e5637 EBE	55	#define MLX5E_DECLARE_PTP_CH_STAT(type, fld) "ptp_ch_"#fld, offsetof(type, fld)
1880bc4e	56	#define MLX5E_DECLARE_PTP_CQ_STAT(type, fld) "ptp_cq%d_"#fld, offsetof(type, fld)
a28359e9	57	#define MLX5E_DECLARE_PTP_RQ_STAT(type, fld) "ptp_rq%d_"#fld, offsetof(type, fld)
145e5637	58
214baf22 MM	59	#define MLX5E_DECLARE_QOS_TX_STAT(type, fld) "qos_tx%d_"#fld, offsetof(type, fld)
214baf22 MM	60
9218b44d	61	struct counter_desc {
bfe6d8d1	62	char format[ETH_GSTRING_LEN];
9da5106c	63	size_t offset; /* Byte offset */
9218b44d GP	64	};
9218b44d GP	65
3460c184 SM	66	enum {
	67	MLX5E_NDO_UPDATE_STATS = BIT(0x1),
	68	};
	69
	70	struct mlx5e_priv;
	71	struct mlx5e_stats_grp {
	72	u16 update_stats_mask;
	73	int (get_num_stats)(struct mlx5e_priv priv);
	74	int (fill_strings)(struct mlx5e_priv priv, u8 *data, int idx);
	75	int (fill_stats)(struct mlx5e_priv priv, u64 *data, int idx);
	76	void (update_stats)(struct mlx5e_priv priv);
	77	};
	78
f0ff8e8c SM	79	typedef const struct mlx5e_stats_grp *const mlx5e_stats_grp_t;
f0ff8e8c SM	80
96b12796 SM	81	#define MLX5E_STATS_GRP_OP(grp, name) mlx5e_stats_grp_ ## grp ## _ ## name
	82
	83	#define MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(grp) \
	84	int MLX5E_STATS_GRP_OP(grp, num_stats)(struct mlx5e_priv *priv)
	85
	86	#define MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(grp) \
	87	void MLX5E_STATS_GRP_OP(grp, update_stats)(struct mlx5e_priv *priv)
	88
	89	#define MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(grp) \
	90	int MLX5E_STATS_GRP_OP(grp, fill_strings)(struct mlx5e_priv priv, u8 data, int idx)
	91
	92	#define MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(grp) \
	93	int MLX5E_STATS_GRP_OP(grp, fill_stats)(struct mlx5e_priv priv, u64 data, int idx)
	94
f0ff8e8c SM	95	#define MLX5E_STATS_GRP(grp) mlx5e_stats_grp_ ## grp
	96
	97	#define MLX5E_DECLARE_STATS_GRP(grp) \
	98	const struct mlx5e_stats_grp MLX5E_STATS_GRP(grp)
	99
	100	#define MLX5E_DEFINE_STATS_GRP(grp, mask) \
	101	MLX5E_DECLARE_STATS_GRP(grp) = { \
96b12796 SM	102	.get_num_stats = MLX5E_STATS_GRP_OP(grp, num_stats), \
	103	.fill_stats = MLX5E_STATS_GRP_OP(grp, fill_stats), \
	104	.fill_strings = MLX5E_STATS_GRP_OP(grp, fill_strings), \
	105	.update_stats = MLX5E_STATS_GRP_OP(grp, update_stats), \
	106	.update_stats_mask = mask, \
	107	}
	108
3460c184 SM	109	unsigned int mlx5e_stats_total_num(struct mlx5e_priv *priv);
	110	void mlx5e_stats_update(struct mlx5e_priv *priv);
	111	void mlx5e_stats_fill(struct mlx5e_priv priv, u64 data, int idx);
	112	void mlx5e_stats_fill_strings(struct mlx5e_priv priv, u8 data);
b521105b	113	void mlx5e_stats_update_ndo_stats(struct mlx5e_priv *priv);
3460c184	114
098d9ed9 JK	115	void mlx5e_stats_pause_get(struct mlx5e_priv *priv,
098d9ed9 JK	116	struct ethtool_pause_stats *pause_stats);
1703bb50 JK	117	void mlx5e_stats_fec_get(struct mlx5e_priv *priv,
1703bb50 JK	118	struct ethtool_fec_stats *fec_stats);
098d9ed9	119
b572ec9f JK	120	void mlx5e_stats_eth_phy_get(struct mlx5e_priv *priv,
	121	struct ethtool_eth_phy_stats *phy_stats);
	122	void mlx5e_stats_eth_mac_get(struct mlx5e_priv *priv,
	123	struct ethtool_eth_mac_stats *mac_stats);
	124	void mlx5e_stats_eth_ctrl_get(struct mlx5e_priv *priv,
	125	struct ethtool_eth_ctrl_stats *ctrl_stats);
	126	void mlx5e_stats_rmon_get(struct mlx5e_priv *priv,
	127	struct ethtool_rmon_stats *rmon,
	128	const struct ethtool_rmon_hist_range **ranges);
e07c4924 SM	129	void mlx5e_get_link_ext_stats(struct net_device *dev,
e07c4924 SM	130	struct ethtool_link_ext_stats *stats);
b572ec9f	131
3460c184 SM	132	/* Concrete NIC Stats */
3460c184 SM	133
9218b44d GP	134	struct mlx5e_sw_stats {
	135	u64 rx_packets;
	136	u64 rx_bytes;
	137	u64 tx_packets;
	138	u64 tx_bytes;
bfe6d8d1 GP	139	u64 tx_tso_packets;
	140	u64 tx_tso_bytes;
	141	u64 tx_tso_inner_packets;
	142	u64 tx_tso_inner_bytes;
f24686e8	143	u64 tx_added_vlan_packets;
2ad9ecdb	144	u64 tx_nop;
5af75c74 MM	145	u64 tx_mpwqe_blks;
5af75c74 MM	146	u64 tx_mpwqe_pkts;
bfe6d8d1 GP	147	u64 rx_lro_packets;
bfe6d8d1 GP	148	u64 rx_lro_bytes;
def09e7b KM	149	u64 rx_gro_packets;
	150	u64 rx_gro_bytes;
	151	u64 rx_gro_skbs;
	152	u64 rx_gro_match_packets;
	153	u64 rx_gro_large_hds;
47c97e6b	154	u64 rx_mcast_packets;
f007c13d	155	u64 rx_ecn_mark;
f24686e8	156	u64 rx_removed_vlan_packets;
bfe6d8d1	157	u64 rx_csum_unnecessary;
9218b44d	158	u64 rx_csum_none;
bfe6d8d1	159	u64 rx_csum_complete;
0aa1d186 SM	160	u64 rx_csum_complete_tail;
0aa1d186 SM	161	u64 rx_csum_complete_tail_slow;
bfe6d8d1	162	u64 rx_csum_unnecessary_inner;
86994156	163	u64 rx_xdp_drop;
86690b4b	164	u64 rx_xdp_redirect;
890388ad	165	u64 rx_xdp_tx_xmit;
73cab880	166	u64 rx_xdp_tx_mpwqe;
c2273219	167	u64 rx_xdp_tx_inlnw;
6c085a8a	168	u64 rx_xdp_tx_nops;
b5503b99	169	u64 rx_xdp_tx_full;
890388ad TT	170	u64 rx_xdp_tx_err;
890388ad TT	171	u64 rx_xdp_tx_cqe;
603e1f5b	172	u64 tx_csum_none;
bfe6d8d1 GP	173	u64 tx_csum_partial;
bfe6d8d1 GP	174	u64 tx_csum_partial_inner;
9218b44d	175	u64 tx_queue_stopped;
9218b44d	176	u64 tx_queue_dropped;
c8cf78fe	177	u64 tx_xmit_more;
db75373c	178	u64 tx_recover;
86155656	179	u64 tx_cqes;
f65a59ff TT	180	u64 tx_queue_wake;
f65a59ff TT	181	u64 tx_cqe_err;
58b99ee3	182	u64 tx_xdp_xmit;
73cab880	183	u64 tx_xdp_mpwqe;
c2273219	184	u64 tx_xdp_inlnw;
6c085a8a	185	u64 tx_xdp_nops;
58b99ee3 TT	186	u64 tx_xdp_full;
	187	u64 tx_xdp_err;
	188	u64 tx_xdp_cqes;
9218b44d	189	u64 rx_wqe_err;
b71ba6b4 TT	190	u64 rx_mpwqe_filler_cqes;
b71ba6b4 TT	191	u64 rx_mpwqe_filler_strides;
0073c8f7	192	u64 rx_oversize_pkts_sw_drop;
9218b44d	193	u64 rx_buff_alloc_err;
7219ab34 TT	194	u64 rx_cqe_compress_blks;
7219ab34 TT	195	u64 rx_cqe_compress_pkts;
dc983f0e	196	u64 rx_congst_umr;
f98e5158 AF	197	#ifdef CONFIG_MLX5_EN_ARFS
	198	u64 rx_arfs_add;
	199	u64 rx_arfs_request_in;
	200	u64 rx_arfs_request_out;
	201	u64 rx_arfs_expired;
94563847	202	u64 rx_arfs_err;
f98e5158	203	#endif
be5323c8	204	u64 rx_recover;
a1bf74dc	205	u64 ch_events;
2d7103c8 TT	206	u64 ch_poll;
	207	u64 ch_arm;
	208	u64 ch_aff_change;
db05815b	209	u64 ch_force_irq;
57d689a8	210	u64 ch_eq_rearm;
cc10e84b JD	211	#ifdef CONFIG_PAGE_POOL_STATS
	212	u64 rx_pp_alloc_fast;
	213	u64 rx_pp_alloc_slow;
	214	u64 rx_pp_alloc_slow_high_order;
	215	u64 rx_pp_alloc_empty;
	216	u64 rx_pp_alloc_refill;
	217	u64 rx_pp_alloc_waive;
	218	u64 rx_pp_recycle_cached;
	219	u64 rx_pp_recycle_cache_full;
	220	u64 rx_pp_recycle_ring;
	221	u64 rx_pp_recycle_ring_full;
	222	u64 rx_pp_recycle_released_ref;
	223	#endif
bf239741	224	#ifdef CONFIG_MLX5_EN_TLS
d2ead1f3 TT	225	u64 tx_tls_encrypted_packets;
d2ead1f3 TT	226	u64 tx_tls_encrypted_bytes;
bf239741	227	u64 tx_tls_ooo;
46a3ea98 TT	228	u64 tx_tls_dump_packets;
46a3ea98 TT	229	u64 tx_tls_dump_bytes;
bf239741	230	u64 tx_tls_resync_bytes;
46a3ea98	231	u64 tx_tls_skip_no_sync_data;
d2ead1f3 TT	232	u64 tx_tls_drop_no_sync_data;
d2ead1f3 TT	233	u64 tx_tls_drop_bypass_req;
76c1e1ac TT	234
	235	u64 rx_tls_decrypted_packets;
	236	u64 rx_tls_decrypted_bytes;
76c1e1ac TT	237	u64 rx_tls_resync_req_pkt;
	238	u64 rx_tls_resync_req_start;
	239	u64 rx_tls_resync_req_end;
	240	u64 rx_tls_resync_req_skip;
	241	u64 rx_tls_resync_res_ok;
e9ce991b	242	u64 rx_tls_resync_res_retry;
76c1e1ac TT	243	u64 rx_tls_resync_res_skip;
76c1e1ac TT	244	u64 rx_tls_err;
bf239741	245	#endif
db05815b MM	246
	247	u64 rx_xsk_packets;
	248	u64 rx_xsk_bytes;
	249	u64 rx_xsk_csum_complete;
	250	u64 rx_xsk_csum_unnecessary;
	251	u64 rx_xsk_csum_unnecessary_inner;
	252	u64 rx_xsk_csum_none;
	253	u64 rx_xsk_ecn_mark;
	254	u64 rx_xsk_removed_vlan_packets;
	255	u64 rx_xsk_xdp_drop;
	256	u64 rx_xsk_xdp_redirect;
	257	u64 rx_xsk_wqe_err;
	258	u64 rx_xsk_mpwqe_filler_cqes;
	259	u64 rx_xsk_mpwqe_filler_strides;
	260	u64 rx_xsk_oversize_pkts_sw_drop;
	261	u64 rx_xsk_buff_alloc_err;
	262	u64 rx_xsk_cqe_compress_blks;
	263	u64 rx_xsk_cqe_compress_pkts;
	264	u64 rx_xsk_congst_umr;
db05815b MM	265	u64 tx_xsk_xmit;
	266	u64 tx_xsk_mpwqe;
	267	u64 tx_xsk_inlnw;
	268	u64 tx_xsk_full;
	269	u64 tx_xsk_err;
	270	u64 tx_xsk_cqes;
9218b44d GP	271	};
9218b44d GP	272
9218b44d GP	273	struct mlx5e_qcounter_stats {
9218b44d GP	274	u32 rx_out_of_buffer;
7cbaf9a3	275	u32 rx_if_down_packets;
9218b44d GP	276	};
9218b44d GP	277
16ab85e7 GP	278	#define VNIC_ENV_GET(vnic_env_stats, c) \
	279	MLX5_GET(query_vnic_env_out, (vnic_env_stats)->query_vnic_env_out, \
	280	vport_env.c)
	281
5c298143 MS	282	struct mlx5e_vnic_env_stats {
	283	__be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)];
	284	};
	285
9218b44d GP	286	#define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
	287	vstats->query_vport_out, c)
	288
	289	struct mlx5e_vport_stats {
	290	__be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
	291	};
	292
9218b44d GP	293	#define PPORT_802_3_GET(pstats, c) \
	294	MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
	295	counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
9218b44d GP	296	#define PPORT_2863_GET(pstats, c) \
	297	MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
	298	counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
9218b44d GP	299	#define PPORT_2819_GET(pstats, c) \
	300	MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
	301	counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
5db0a4f6 GP	302	#define PPORT_PHY_STATISTICAL_GET(pstats, c) \
	303	MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
	304	counter_set.phys_layer_statistical_cntrs.c##_high)
cf678570 GP	305	#define PPORT_PER_PRIO_GET(pstats, prio, c) \
	306	MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
	307	counter_set.eth_per_prio_grp_data_layout.c##_high)
	308	#define NUM_PPORT_PRIO 8
068aef33 GP	309	#define PPORT_ETH_EXT_GET(pstats, c) \
	310	MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
	311	counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
9218b44d GP	312
	313	struct mlx5e_pport_stats {
	314	__be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
	315	__be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
	316	__be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
cf678570	317	__be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
121fcdc8	318	__be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
5db0a4f6	319	__be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
068aef33	320	__be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
1297d97f AL	321	__be64 per_tc_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
1297d97f AL	322	__be64 per_tc_congest_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
9218b44d GP	323	};
9218b44d GP	324
0f7f3481 GP	325	#define PCIE_PERF_GET(pcie_stats, c) \
	326	MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
	327	counter_set.pcie_perf_cntrs_grp_data_layout.c)
	328
efae7f78 EBE	329	#define PCIE_PERF_GET64(pcie_stats, c) \
	330	MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
	331	counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
	332
0f7f3481 GP	333	struct mlx5e_pcie_stats {
	334	__be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
	335	};
	336
9218b44d GP	337	struct mlx5e_rq_stats {
	338	u64 packets;
	339	u64 bytes;
bfe6d8d1	340	u64 csum_complete;
0aa1d186 SM	341	u64 csum_complete_tail;
0aa1d186 SM	342	u64 csum_complete_tail_slow;
603e1f5b	343	u64 csum_unnecessary;
bfe6d8d1	344	u64 csum_unnecessary_inner;
1b223dd3	345	u64 csum_none;
9218b44d GP	346	u64 lro_packets;
9218b44d GP	347	u64 lro_bytes;
def09e7b KM	348	u64 gro_packets;
	349	u64 gro_bytes;
	350	u64 gro_skbs;
	351	u64 gro_match_packets;
	352	u64 gro_large_hds;
47c97e6b	353	u64 mcast_packets;
f007c13d	354	u64 ecn_mark;
f24686e8	355	u64 removed_vlan_packets;
86994156	356	u64 xdp_drop;
86690b4b	357	u64 xdp_redirect;
9218b44d	358	u64 wqe_err;
b71ba6b4 TT	359	u64 mpwqe_filler_cqes;
b71ba6b4 TT	360	u64 mpwqe_filler_strides;
0073c8f7	361	u64 oversize_pkts_sw_drop;
9218b44d	362	u64 buff_alloc_err;
7219ab34 TT	363	u64 cqe_compress_blks;
7219ab34 TT	364	u64 cqe_compress_pkts;
dc983f0e	365	u64 congst_umr;
f98e5158 AF	366	#ifdef CONFIG_MLX5_EN_ARFS
	367	u64 arfs_add;
	368	u64 arfs_request_in;
	369	u64 arfs_request_out;
	370	u64 arfs_expired;
94563847	371	u64 arfs_err;
f98e5158	372	#endif
be5323c8	373	u64 recover;
cc10e84b JD	374	#ifdef CONFIG_PAGE_POOL_STATS
	375	u64 pp_alloc_fast;
	376	u64 pp_alloc_slow;
	377	u64 pp_alloc_slow_high_order;
	378	u64 pp_alloc_empty;
	379	u64 pp_alloc_refill;
	380	u64 pp_alloc_waive;
	381	u64 pp_recycle_cached;
	382	u64 pp_recycle_cache_full;
	383	u64 pp_recycle_ring;
	384	u64 pp_recycle_ring_full;
	385	u64 pp_recycle_released_ref;
	386	#endif
76c1e1ac TT	387	#ifdef CONFIG_MLX5_EN_TLS
	388	u64 tls_decrypted_packets;
	389	u64 tls_decrypted_bytes;
76c1e1ac TT	390	u64 tls_resync_req_pkt;
	391	u64 tls_resync_req_start;
	392	u64 tls_resync_req_end;
	393	u64 tls_resync_req_skip;
	394	u64 tls_resync_res_ok;
e9ce991b	395	u64 tls_resync_res_retry;
76c1e1ac TT	396	u64 tls_resync_res_skip;
	397	u64 tls_err;
	398	#endif
9218b44d GP	399	};
9218b44d GP	400
9218b44d GP	401	struct mlx5e_sq_stats {
	402	/* commonly accessed in data path */
	403	u64 packets;
	404	u64 bytes;
c8cf78fe	405	u64 xmit_more;
9218b44d GP	406	u64 tso_packets;
	407	u64 tso_bytes;
	408	u64 tso_inner_packets;
	409	u64 tso_inner_bytes;
603e1f5b	410	u64 csum_partial;
bfe6d8d1	411	u64 csum_partial_inner;
f24686e8	412	u64 added_vlan_packets;
9218b44d	413	u64 nop;
5af75c74 MM	414	u64 mpwqe_blks;
5af75c74 MM	415	u64 mpwqe_pkts;
bf239741	416	#ifdef CONFIG_MLX5_EN_TLS
d2ead1f3 TT	417	u64 tls_encrypted_packets;
d2ead1f3 TT	418	u64 tls_encrypted_bytes;
bf239741	419	u64 tls_ooo;
46a3ea98 TT	420	u64 tls_dump_packets;
46a3ea98 TT	421	u64 tls_dump_bytes;
bf239741	422	u64 tls_resync_bytes;
46a3ea98	423	u64 tls_skip_no_sync_data;
d2ead1f3 TT	424	u64 tls_drop_no_sync_data;
d2ead1f3 TT	425	u64 tls_drop_bypass_req;
bf239741	426	#endif
9218b44d	427	/* less likely accessed in data path */
bfe6d8d1	428	u64 csum_none;
9218b44d	429	u64 stopped;
9218b44d	430	u64 dropped;
db75373c	431	u64 recover;
f65a59ff	432	/* dirtied @completion */
86155656 TT	433	u64 cqes ____cacheline_aligned_in_smp;
86155656 TT	434	u64 wake;
f65a59ff	435	u64 cqe_err;
9218b44d GP	436	};
9218b44d GP	437
890388ad TT	438	struct mlx5e_xdpsq_stats {
890388ad TT	439	u64 xmit;
73cab880	440	u64 mpwqe;
c2273219	441	u64 inlnw;
6c085a8a	442	u64 nops;
890388ad TT	443	u64 full;
890388ad TT	444	u64 err;
dac0d15f TT	445	/* dirtied @completion */
dac0d15f TT	446	u64 cqes ____cacheline_aligned_in_smp;
890388ad TT	447	};
890388ad TT	448
57d689a8	449	struct mlx5e_ch_stats {
a1bf74dc	450	u64 events;
2d7103c8 TT	451	u64 poll;
	452	u64 arm;
	453	u64 aff_change;
db05815b	454	u64 force_irq;
57d689a8 EBE	455	u64 eq_rearm;
	456	};
	457
1880bc4e EBE	458	struct mlx5e_ptp_cq_stats {
	459	u64 cqe;
	460	u64 err_cqe;
	461	u64 abort;
	462	u64 abort_abs_diff_ns;
3178308a	463	u64 late_cqe;
1880bc4e EBE	464	};
1880bc4e EBE	465
64b68e36 OHT	466	struct mlx5e_rep_stats {
	467	u64 vport_rx_packets;
	468	u64 vport_tx_packets;
	469	u64 vport_rx_bytes;
	470	u64 vport_tx_bytes;
	471	u64 rx_vport_rdma_unicast_packets;
	472	u64 tx_vport_rdma_unicast_packets;
	473	u64 rx_vport_rdma_unicast_bytes;
	474	u64 tx_vport_rdma_unicast_bytes;
	475	u64 rx_vport_rdma_multicast_packets;
	476	u64 tx_vport_rdma_multicast_packets;
	477	u64 rx_vport_rdma_multicast_bytes;
	478	u64 tx_vport_rdma_multicast_bytes;
	479	};
	480
9218b44d GP	481	struct mlx5e_stats {
	482	struct mlx5e_sw_stats sw;
	483	struct mlx5e_qcounter_stats qcnt;
5c298143	484	struct mlx5e_vnic_env_stats vnic;
9218b44d GP	485	struct mlx5e_vport_stats vport;
9218b44d GP	486	struct mlx5e_pport_stats pport;
0f7f3481	487	struct mlx5e_pcie_stats pcie;
64b68e36	488	struct mlx5e_rep_stats rep_stats;
9218b44d GP	489	};
9218b44d GP	490
80f12414 AT	491	static inline void mlx5e_stats_copy_rep_stats(struct rtnl_link_stats64 *vf_vport,
	492	struct mlx5e_rep_stats *rep_stats)
	493	{
	494	memset(vf_vport, 0, sizeof(*vf_vport));
	495	vf_vport->rx_packets = rep_stats->vport_rx_packets;
	496	vf_vport->tx_packets = rep_stats->vport_tx_packets;
	497	vf_vport->rx_bytes = rep_stats->vport_rx_bytes;
	498	vf_vport->tx_bytes = rep_stats->vport_tx_bytes;
	499	}
	500
f0ff8e8c	501	extern mlx5e_stats_grp_t mlx5e_nic_stats_grps[];
3460c184	502	unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv);
c0752f2b	503
2a303f13 SM	504	extern MLX5E_DECLARE_STATS_GRP(sw);
	505	extern MLX5E_DECLARE_STATS_GRP(qcnt);
	506	extern MLX5E_DECLARE_STATS_GRP(vnic_env);
	507	extern MLX5E_DECLARE_STATS_GRP(vport);
	508	extern MLX5E_DECLARE_STATS_GRP(802_3);
	509	extern MLX5E_DECLARE_STATS_GRP(2863);
	510	extern MLX5E_DECLARE_STATS_GRP(2819);
	511	extern MLX5E_DECLARE_STATS_GRP(phy);
7c453526	512	extern MLX5E_DECLARE_STATS_GRP(eth_ext);
2a303f13 SM	513	extern MLX5E_DECLARE_STATS_GRP(pcie);
	514	extern MLX5E_DECLARE_STATS_GRP(per_prio);
	515	extern MLX5E_DECLARE_STATS_GRP(pme);
	516	extern MLX5E_DECLARE_STATS_GRP(channels);
	517	extern MLX5E_DECLARE_STATS_GRP(per_port_buff_congest);
81f8fba5	518	extern MLX5E_DECLARE_STATS_GRP(ipsec_hw);
0aab3e1b	519	extern MLX5E_DECLARE_STATS_GRP(ipsec_sw);
7c5f940d	520	extern MLX5E_DECLARE_STATS_GRP(ptp);
807a1b76	521	extern MLX5E_DECLARE_STATS_GRP(macsec_hw);
2a303f13	522
9218b44d	523	#endif /* __MLX5_EN_STATS_H__ */