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net/mlx5e: Replace the split logic with extended destination
[thirdparty/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG		 41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
f6dfb4c3 47#include <net/arp.h>
e8f887ac 48#include "en.h"
1d447a39 49#include "en_rep.h"
232c0013 50#include "en_tc.h"
03a9d11e 51#include "eswitch.h"
3f6d08d1 52#include "fs_core.h"
2c81bfd5 53#include "en/port.h"
101f4de9 54#include "en/tc_tun.h"
e8f887ac 55
3bc4b7bf
OG		 56struct mlx5_nic_flow_attr {
57 u32 action;
58 u32 flow_tag;
2f4fe4ca 59 u32 mod_hdr_id;
5c65c564 60 u32 hairpin_tirn;
38aa51c1 61 u8 match_level;
3f6d08d1 62 struct mlx5_flow_table *hairpin_ft;
b8aee822 63 struct mlx5_fc *counter;
3bc4b7bf
OG		 64};
65
60bd4af8
OG		 66#define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1)
67
65ba8fb7 68enum {
60bd4af8
OG		 69 MLX5E_TC_FLOW_INGRESS = MLX5E_TC_INGRESS,
70 MLX5E_TC_FLOW_EGRESS = MLX5E_TC_EGRESS,
71 MLX5E_TC_FLOW_ESWITCH = BIT(MLX5E_TC_FLOW_BASE),
72 MLX5E_TC_FLOW_NIC = BIT(MLX5E_TC_FLOW_BASE + 1),
73 MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE + 2),
74 MLX5E_TC_FLOW_HAIRPIN = BIT(MLX5E_TC_FLOW_BASE + 3),
75 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 4),
5dbe906f 76 MLX5E_TC_FLOW_SLOW = BIT(MLX5E_TC_FLOW_BASE + 5),
65ba8fb7
OG		 77};
78
e4ad91f2
CM		 79#define MLX5E_TC_MAX_SPLITS 1
80
e8f887ac
AV		 81struct mlx5e_tc_flow {
82 struct rhash_head node;
655dc3d2 83 struct mlx5e_priv *priv;
e8f887ac 84 u64 cookie;
5dbe906f 85 u16 flags;
e4ad91f2 86 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
11c9c548
OG		 87 struct list_head encap; /* flows sharing the same encap ID */
88 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
5c65c564 89 struct list_head hairpin; /* flows sharing the same hairpin */
3bc4b7bf
OG		 90 union {
91 struct mlx5_esw_flow_attr esw_attr[0];
92 struct mlx5_nic_flow_attr nic_attr[0];
93 };
e8f887ac
AV		 94};
95
17091853 96struct mlx5e_tc_flow_parse_attr {
3c37745e 97 struct ip_tunnel_info tun_info;
d11afc26 98 struct net_device *filter_dev;
17091853 99 struct mlx5_flow_spec spec;
d79b6df6
OG		 100 int num_mod_hdr_actions;
101 void *mod_hdr_actions;
3c37745e 102 int mirred_ifindex;
17091853
OG		 103};
104
acff797c 105#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 106#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 107
77ab67b7
OG		 108struct mlx5e_hairpin {
109 struct mlx5_hairpin *pair;
110
111 struct mlx5_core_dev *func_mdev;
3f6d08d1 112 struct mlx5e_priv *func_priv;
77ab67b7
OG		 113 u32 tdn;
114 u32 tirn;
3f6d08d1
OG		 115
116 int num_channels;
117 struct mlx5e_rqt indir_rqt;
118 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
119 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 120};
121
5c65c564
OG		 122struct mlx5e_hairpin_entry {
123 /* a node of a hash table which keeps all the hairpin entries */
124 struct hlist_node hairpin_hlist;
125
126 /* flows sharing the same hairpin */
127 struct list_head flows;
128
d8822868 129 u16 peer_vhca_id;
106be53b 130 u8 prio;
5c65c564
OG		 131 struct mlx5e_hairpin *hp;
132};
133
11c9c548
OG		 134struct mod_hdr_key {
135 int num_actions;
136 void *actions;
137};
138
139struct mlx5e_mod_hdr_entry {
140 /* a node of a hash table which keeps all the mod_hdr entries */
141 struct hlist_node mod_hdr_hlist;
142
143 /* flows sharing the same mod_hdr entry */
144 struct list_head flows;
145
146 struct mod_hdr_key key;
147
148 u32 mod_hdr_id;
149};
150
151#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
152
153static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
154{
155 return jhash(key->actions,
156 key->num_actions * MLX5_MH_ACT_SZ, 0);
157}
158
159static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
160 struct mod_hdr_key *b)
161{
162 if (a->num_actions != b->num_actions)
163 return 1;
164
165 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
166}
167
168static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
169 struct mlx5e_tc_flow *flow,
170 struct mlx5e_tc_flow_parse_attr *parse_attr)
171{
172 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
173 int num_actions, actions_size, namespace, err;
174 struct mlx5e_mod_hdr_entry *mh;
175 struct mod_hdr_key key;
176 bool found = false;
177 u32 hash_key;
178
179 num_actions = parse_attr->num_mod_hdr_actions;
180 actions_size = MLX5_MH_ACT_SZ * num_actions;
181
182 key.actions = parse_attr->mod_hdr_actions;
183 key.num_actions = num_actions;
184
185 hash_key = hash_mod_hdr_info(&key);
186
187 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
188 namespace = MLX5_FLOW_NAMESPACE_FDB;
189 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
190 mod_hdr_hlist, hash_key) {
191 if (!cmp_mod_hdr_info(&mh->key, &key)) {
192 found = true;
193 break;
194 }
195 }
196 } else {
197 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
198 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
199 mod_hdr_hlist, hash_key) {
200 if (!cmp_mod_hdr_info(&mh->key, &key)) {
201 found = true;
202 break;
203 }
204 }
205 }
206
207 if (found)
208 goto attach_flow;
209
210 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
211 if (!mh)
212 return -ENOMEM;
213
214 mh->key.actions = (void *)mh + sizeof(*mh);
215 memcpy(mh->key.actions, key.actions, actions_size);
216 mh->key.num_actions = num_actions;
217 INIT_LIST_HEAD(&mh->flows);
218
219 err = mlx5_modify_header_alloc(priv->mdev, namespace,
220 mh->key.num_actions,
221 mh->key.actions,
222 &mh->mod_hdr_id);
223 if (err)
224 goto out_err;
225
226 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
227 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
228 else
229 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
230
231attach_flow:
232 list_add(&flow->mod_hdr, &mh->flows);
233 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
234 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
235 else
236 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
237
238 return 0;
239
240out_err:
241 kfree(mh);
242 return err;
243}
244
245static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
246 struct mlx5e_tc_flow *flow)
247{
248 struct list_head *next = flow->mod_hdr.next;
249
250 list_del(&flow->mod_hdr);
251
252 if (list_empty(next)) {
253 struct mlx5e_mod_hdr_entry *mh;
254
255 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
256
257 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
258 hash_del(&mh->mod_hdr_hlist);
259 kfree(mh);
260 }
261}
262
77ab67b7
OG		 263static
264struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
265{
266 struct net_device *netdev;
267 struct mlx5e_priv *priv;
268
269 netdev = __dev_get_by_index(net, ifindex);
270 priv = netdev_priv(netdev);
271 return priv->mdev;
272}
273
274static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
275{
276 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
277 void *tirc;
278 int err;
279
280 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
281 if (err)
282 goto alloc_tdn_err;
283
284 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
285
286 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 287 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 288 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
289
290 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
291 if (err)
292 goto create_tir_err;
293
294 return 0;
295
296create_tir_err:
297 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
298alloc_tdn_err:
299 return err;
300}
301
302static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
303{
304 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
305 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
306}
307
3f6d08d1
OG		 308static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
309{
310 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
311 struct mlx5e_priv *priv = hp->func_priv;
312 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
313
314 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
315 hp->num_channels);
316
317 for (i = 0; i < sz; i++) {
318 ix = i;
bbeb53b8 319 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 320 ix = mlx5e_bits_invert(i, ilog2(sz));
321 ix = indirection_rqt[ix];
322 rqn = hp->pair->rqn[ix];
323 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
324 }
325}
326
327static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
328{
329 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
330 struct mlx5e_priv *priv = hp->func_priv;
331 struct mlx5_core_dev *mdev = priv->mdev;
332 void *rqtc;
333 u32 *in;
334
335 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
336 in = kvzalloc(inlen, GFP_KERNEL);
337 if (!in)
338 return -ENOMEM;
339
340 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
341
342 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
343 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
344
345 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
346
347 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
348 if (!err)
349 hp->indir_rqt.enabled = true;
350
351 kvfree(in);
352 return err;
353}
354
355static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
356{
357 struct mlx5e_priv *priv = hp->func_priv;
358 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
359 int tt, i, err;
360 void *tirc;
361
362 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 363 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
364
3f6d08d1
OG		 365 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
366 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
367
368 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
369 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
370 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 371 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
372
3f6d08d1
OG		 373 err = mlx5_core_create_tir(hp->func_mdev, in,
374 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
375 if (err) {
376 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
377 goto err_destroy_tirs;
378 }
379 }
380 return 0;
381
382err_destroy_tirs:
383 for (i = 0; i < tt; i++)
384 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
385 return err;
386}
387
388static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
389{
390 int tt;
391
392 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
393 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
394}
395
396static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
397 struct ttc_params *ttc_params)
398{
399 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
400 int tt;
401
402 memset(ttc_params, 0, sizeof(*ttc_params));
403
404 ttc_params->any_tt_tirn = hp->tirn;
405
406 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
407 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
408
409 ft_attr->max_fte = MLX5E_NUM_TT;
410 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
411 ft_attr->prio = MLX5E_TC_PRIO;
412}
413
414static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
415{
416 struct mlx5e_priv *priv = hp->func_priv;
417 struct ttc_params ttc_params;
418 int err;
419
420 err = mlx5e_hairpin_create_indirect_rqt(hp);
421 if (err)
422 return err;
423
424 err = mlx5e_hairpin_create_indirect_tirs(hp);
425 if (err)
426 goto err_create_indirect_tirs;
427
428 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
429 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
430 if (err)
431 goto err_create_ttc_table;
432
433 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
434 hp->num_channels, hp->ttc.ft.t->id);
435
436 return 0;
437
438err_create_ttc_table:
439 mlx5e_hairpin_destroy_indirect_tirs(hp);
440err_create_indirect_tirs:
441 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
442
443 return err;
444}
445
446static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
447{
448 struct mlx5e_priv *priv = hp->func_priv;
449
450 mlx5e_destroy_ttc_table(priv, &hp->ttc);
451 mlx5e_hairpin_destroy_indirect_tirs(hp);
452 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
453}
454
77ab67b7
OG		 455static struct mlx5e_hairpin *
456mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
457 int peer_ifindex)
458{
459 struct mlx5_core_dev *func_mdev, *peer_mdev;
460 struct mlx5e_hairpin *hp;
461 struct mlx5_hairpin *pair;
462 int err;
463
464 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
465 if (!hp)
466 return ERR_PTR(-ENOMEM);
467
468 func_mdev = priv->mdev;
469 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
470
471 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
472 if (IS_ERR(pair)) {
473 err = PTR_ERR(pair);
474 goto create_pair_err;
475 }
476 hp->pair = pair;
477 hp->func_mdev = func_mdev;
3f6d08d1
OG		 478 hp->func_priv = priv;
479 hp->num_channels = params->num_channels;
77ab67b7
OG		 480
481 err = mlx5e_hairpin_create_transport(hp);
482 if (err)
483 goto create_transport_err;
484
3f6d08d1
OG		 485 if (hp->num_channels > 1) {
486 err = mlx5e_hairpin_rss_init(hp);
487 if (err)
488 goto rss_init_err;
489 }
490
77ab67b7
OG		 491 return hp;
492
3f6d08d1
OG		 493rss_init_err:
494 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 495create_transport_err:
496 mlx5_core_hairpin_destroy(hp->pair);
497create_pair_err:
498 kfree(hp);
499 return ERR_PTR(err);
500}
501
502static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
503{
3f6d08d1
OG		 504 if (hp->num_channels > 1)
505 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 506 mlx5e_hairpin_destroy_transport(hp);
507 mlx5_core_hairpin_destroy(hp->pair);
508 kvfree(hp);
509}
510
106be53b
OG		 511static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
512{
513 return (peer_vhca_id << 16 | prio);
514}
515
5c65c564 516static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 517 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 518{
519 struct mlx5e_hairpin_entry *hpe;
106be53b 520 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 521
522 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b
OG		 523 hairpin_hlist, hash_key) {
524 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
5c65c564
OG		 525 return hpe;
526 }
527
528 return NULL;
529}
530
106be53b
OG		 531#define UNKNOWN_MATCH_PRIO 8
532
533static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 534 struct mlx5_flow_spec *spec, u8 *match_prio,
535 struct netlink_ext_ack *extack)
106be53b
OG		 536{
537 void *headers_c, *headers_v;
538 u8 prio_val, prio_mask = 0;
539 bool vlan_present;
540
541#ifdef CONFIG_MLX5_CORE_EN_DCB
542 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 543 NL_SET_ERR_MSG_MOD(extack,
544 "only PCP trust state supported for hairpin");
106be53b
OG		 545 return -EOPNOTSUPP;
546 }
547#endif
548 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
549 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
550
551 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
552 if (vlan_present) {
553 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
554 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
555 }
556
557 if (!vlan_present || !prio_mask) {
558 prio_val = UNKNOWN_MATCH_PRIO;
559 } else if (prio_mask != 0x7) {
e98bedf5
EB		 560 NL_SET_ERR_MSG_MOD(extack,
561 "masked priority match not supported for hairpin");
106be53b
OG		 562 return -EOPNOTSUPP;
563 }
564
565 *match_prio = prio_val;
566 return 0;
567}
568
5c65c564
OG		 569static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
570 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 571 struct mlx5e_tc_flow_parse_attr *parse_attr,
572 struct netlink_ext_ack *extack)
5c65c564
OG		 573{
574 int peer_ifindex = parse_attr->mirred_ifindex;
575 struct mlx5_hairpin_params params;
d8822868 576 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 577 struct mlx5e_hairpin_entry *hpe;
578 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 579 u64 link_speed64;
580 u32 link_speed;
106be53b 581 u8 match_prio;
d8822868 582 u16 peer_id;
5c65c564
OG		 583 int err;
584
d8822868
OG		 585 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
586 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 587 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 588 return -EOPNOTSUPP;
589 }
590
d8822868 591 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 592 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
593 extack);
106be53b
OG		 594 if (err)
595 return err;
596 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 597 if (hpe)
598 goto attach_flow;
599
600 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
601 if (!hpe)
602 return -ENOMEM;
603
604 INIT_LIST_HEAD(&hpe->flows);
d8822868 605 hpe->peer_vhca_id = peer_id;
106be53b 606 hpe->prio = match_prio;
5c65c564
OG		 607
608 params.log_data_size = 15;
609 params.log_data_size = min_t(u8, params.log_data_size,
610 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
611 params.log_data_size = max_t(u8, params.log_data_size,
612 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 613
eb9180f7
OG		 614 params.log_num_packets = params.log_data_size -
615 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
616 params.log_num_packets = min_t(u8, params.log_num_packets,
617 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
618
619 params.q_counter = priv->q_counter;
3f6d08d1 620 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 621 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 622 link_speed = max_t(u32, link_speed, 50000);
623 link_speed64 = link_speed;
624 do_div(link_speed64, 50000);
625 params.num_channels = link_speed64;
626
5c65c564
OG		 627 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
628 if (IS_ERR(hp)) {
629 err = PTR_ERR(hp);
630 goto create_hairpin_err;
631 }
632
eb9180f7 633 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
ddae74ac 634 hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
eb9180f7 635 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564
OG		 636
637 hpe->hp = hp;
106be53b
OG		 638 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
639 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 640
641attach_flow:
3f6d08d1
OG		 642 if (hpe->hp->num_channels > 1) {
643 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
644 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
645 } else {
646 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
647 }
5c65c564 648 list_add(&flow->hairpin, &hpe->flows);
3f6d08d1 649
5c65c564
OG		 650 return 0;
651
652create_hairpin_err:
653 kfree(hpe);
654 return err;
655}
656
657static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
658 struct mlx5e_tc_flow *flow)
659{
660 struct list_head *next = flow->hairpin.next;
661
662 list_del(&flow->hairpin);
663
664 /* no more hairpin flows for us, release the hairpin pair */
665 if (list_empty(next)) {
666 struct mlx5e_hairpin_entry *hpe;
667
668 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
669
670 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
671 hpe->hp->pair->peer_mdev->priv.name);
672
673 mlx5e_hairpin_destroy(hpe->hp);
674 hash_del(&hpe->hairpin_hlist);
675 kfree(hpe);
676 }
677}
678
c83954ab 679static int
74491de9 680mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 681 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 682 struct mlx5e_tc_flow *flow,
683 struct netlink_ext_ack *extack)
e8f887ac 684{
aa0cbbae 685 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 686 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 687 struct mlx5_flow_destination dest[2] = {};
66958ed9 688 struct mlx5_flow_act flow_act = {
3bc4b7bf
OG		 689 .action = attr->action,
690 .flow_tag = attr->flow_tag,
60786f09 691 .reformat_id = 0,
42f7ad67 692 .flags = FLOW_ACT_HAS_TAG | FLOW_ACT_NO_APPEND,
66958ed9 693 };
aad7e08d 694 struct mlx5_fc *counter = NULL;
e8f887ac 695 bool table_created = false;
5c65c564 696 int err, dest_ix = 0;
e8f887ac 697
3f6d08d1 698 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
e98bedf5 699 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
3f6d08d1 700 if (err) {
3f6d08d1
OG		 701 goto err_add_hairpin_flow;
702 }
703 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
704 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
705 dest[dest_ix].ft = attr->hairpin_ft;
706 } else {
5c65c564
OG		 707 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
708 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 709 }
710 dest_ix++;
3f6d08d1
OG		 711 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
712 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
713 dest[dest_ix].ft = priv->fs.vlan.ft.t;
714 dest_ix++;
5c65c564 715 }
aad7e08d 716
5c65c564
OG		 717 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
718 counter = mlx5_fc_create(dev, true);
719 if (IS_ERR(counter)) {
c83954ab 720 err = PTR_ERR(counter);
5c65c564
OG		 721 goto err_fc_create;
722 }
723 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 724 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 725 dest_ix++;
b8aee822 726 attr->counter = counter;
aad7e08d
AV		 727 }
728
2f4fe4ca 729 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 730 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 731 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca 732 kfree(parse_attr->mod_hdr_actions);
c83954ab 733 if (err)
2f4fe4ca 734 goto err_create_mod_hdr_id;
2f4fe4ca
OG		 735 }
736
acff797c 737 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 738 int tc_grp_size, tc_tbl_size;
739 u32 max_flow_counter;
740
741 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
742 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
743
744 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
745
746 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
747 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
748
acff797c
MG		 749 priv->fs.tc.t =
750 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
751 MLX5E_TC_PRIO,
21b9c144 752 tc_tbl_size,
acff797c 753 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 754 MLX5E_TC_FT_LEVEL, 0);
acff797c 755 if (IS_ERR(priv->fs.tc.t)) {
e98bedf5
EB		 756 NL_SET_ERR_MSG_MOD(extack,
757 "Failed to create tc offload table\n");
e8f887ac
AV		 758 netdev_err(priv->netdev,
759 "Failed to create tc offload table\n");
c83954ab 760 err = PTR_ERR(priv->fs.tc.t);
aad7e08d 761 goto err_create_ft;
e8f887ac
AV		 762 }
763
764 table_created = true;
765 }
766
38aa51c1
OG		 767 if (attr->match_level != MLX5_MATCH_NONE)
768 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
769
c83954ab
RL		 770 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
771 &flow_act, dest, dest_ix);
aad7e08d 772
c83954ab
RL		 773 if (IS_ERR(flow->rule[0])) {
774 err = PTR_ERR(flow->rule[0]);
aad7e08d 775 goto err_add_rule;
c83954ab 776 }
aad7e08d 777
c83954ab 778 return 0;
e8f887ac 779
aad7e08d
AV		 780err_add_rule:
781 if (table_created) {
acff797c
MG		 782 mlx5_destroy_flow_table(priv->fs.tc.t);
783 priv->fs.tc.t = NULL;
e8f887ac 784 }
aad7e08d 785err_create_ft:
2f4fe4ca 786 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 787 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 788err_create_mod_hdr_id:
aad7e08d 789 mlx5_fc_destroy(dev, counter);
5c65c564
OG		 790err_fc_create:
791 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
792 mlx5e_hairpin_flow_del(priv, flow);
793err_add_hairpin_flow:
c83954ab 794 return err;
e8f887ac
AV		 795}
796
d85cdccb
OG		 797static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
798 struct mlx5e_tc_flow *flow)
799{
513f8f7f 800 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 801 struct mlx5_fc *counter = NULL;
802
b8aee822 803 counter = attr->counter;
e4ad91f2 804 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 805 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 806
b3a433de 807 if (!mlx5e_tc_num_filters(priv) && priv->fs.tc.t) {
d85cdccb
OG		 808 mlx5_destroy_flow_table(priv->fs.tc.t);
809 priv->fs.tc.t = NULL;
810 }
2f4fe4ca 811
513f8f7f 812 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 813 mlx5e_detach_mod_hdr(priv, flow);
5c65c564
OG		 814
815 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
816 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 817}
818
aa0cbbae
OG		 819static void mlx5e_detach_encap(struct mlx5e_priv *priv,
820 struct mlx5e_tc_flow *flow);
821
3c37745e
OG		 822static int mlx5e_attach_encap(struct mlx5e_priv *priv,
823 struct ip_tunnel_info *tun_info,
824 struct net_device *mirred_dev,
825 struct net_device **encap_dev,
e98bedf5
EB		 826 struct mlx5e_tc_flow *flow,
827 struct netlink_ext_ack *extack);
3c37745e 828
6d2a3ed0
OG		 829static struct mlx5_flow_handle *
830mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
831 struct mlx5e_tc_flow *flow,
832 struct mlx5_flow_spec *spec,
833 struct mlx5_esw_flow_attr *attr)
834{
835 struct mlx5_flow_handle *rule;
836
837 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
838 if (IS_ERR(rule))
839 return rule;
840
e85e02ba 841 if (attr->split_count) {
6d2a3ed0
OG		 842 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
843 if (IS_ERR(flow->rule[1])) {
844 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
845 return flow->rule[1];
846 }
847 }
848
849 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
850 return rule;
851}
852
853static void
854mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
855 struct mlx5e_tc_flow *flow,
856 struct mlx5_esw_flow_attr *attr)
857{
858 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
859
e85e02ba 860 if (attr->split_count)
6d2a3ed0
OG		 861 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
862
863 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
864}
865
5dbe906f
PB		 866static struct mlx5_flow_handle *
867mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
868 struct mlx5e_tc_flow *flow,
869 struct mlx5_flow_spec *spec,
870 struct mlx5_esw_flow_attr *slow_attr)
871{
872 struct mlx5_flow_handle *rule;
873
874 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
875 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
e85e02ba 876 slow_attr->split_count = 0,
5dbe906f
PB		 877 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN,
878
879 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
880 if (!IS_ERR(rule))
881 flow->flags |= MLX5E_TC_FLOW_SLOW;
882
883 return rule;
884}
885
886static void
887mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
888 struct mlx5e_tc_flow *flow,
889 struct mlx5_esw_flow_attr *slow_attr)
890{
891 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
892 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
893 flow->flags &= ~MLX5E_TC_FLOW_SLOW;
894}
895
c83954ab 896static int
74491de9 897mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 898 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 899 struct mlx5e_tc_flow *flow,
900 struct netlink_ext_ack *extack)
adb4c123
OG		 901{
902 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
bf07aa73 903 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
aa0cbbae 904 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
bf07aa73 905 u16 max_prio = mlx5_eswitch_get_prio_range(esw);
3c37745e 906 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 907 struct mlx5_fc *counter = NULL;
3c37745e
OG		 908 struct mlx5e_rep_priv *rpriv;
909 struct mlx5e_priv *out_priv;
c83954ab 910 int err = 0, encap_err = 0;
f493f155 911 int out_index;
8b32580d 912
bf07aa73
PB		 913 /* if prios are not supported, keep the old behaviour of using same prio
914 * for all offloaded rules.
915 */
916 if (!mlx5_eswitch_prios_supported(esw))
917 attr->prio = 1;
918
919 if (attr->chain > max_chain) {
920 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
921 err = -EOPNOTSUPP;
922 goto err_max_prio_chain;
923 }
924
925 if (attr->prio > max_prio) {
926 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
927 err = -EOPNOTSUPP;
928 goto err_max_prio_chain;
929 }
e52c2802 930
f493f155
EB		 931 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
932 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
933 continue;
934
3c37745e
OG		 935 out_dev = __dev_get_by_index(dev_net(priv->netdev),
936 attr->parse_attr->mirred_ifindex);
c83954ab
RL		 937 encap_err = mlx5e_attach_encap(priv, &parse_attr->tun_info,
938 out_dev, &encap_dev, flow,
939 extack);
940 if (encap_err && encap_err != -EAGAIN) {
941 err = encap_err;
942 goto err_attach_encap;
3c37745e
OG		 943 }
944 out_priv = netdev_priv(encap_dev);
945 rpriv = out_priv->ppriv;
df65a573
EB		 946 attr->dests[attr->out_count].rep = rpriv->rep;
947 attr->dests[attr->out_count++].mdev = out_priv->mdev;
3c37745e
OG		 948 }
949
8b32580d 950 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 951 if (err)
aa0cbbae 952 goto err_add_vlan;
adb4c123 953
d7e75a32 954 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 955 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 956 kfree(parse_attr->mod_hdr_actions);
c83954ab 957 if (err)
d7e75a32 958 goto err_mod_hdr;
d7e75a32
OG		 959 }
960
b8aee822
MB		 961 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
962 counter = mlx5_fc_create(esw->dev, true);
963 if (IS_ERR(counter)) {
c83954ab 964 err = PTR_ERR(counter);
b8aee822
MB		 965 goto err_create_counter;
966 }
967
968 attr->counter = counter;
969 }
970
c83954ab 971 /* we get here if (1) there's no error or when
3c37745e
OG		 972 * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
973 */
5dbe906f
PB		 974 if (encap_err == -EAGAIN) {
975 /* continue with goto slow path rule instead */
976 struct mlx5_esw_flow_attr slow_attr;
977
978 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
979 } else {
6d2a3ed0 980 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
3c37745e 981 }
c83954ab 982
5dbe906f
PB		 983 if (IS_ERR(flow->rule[0])) {
984 err = PTR_ERR(flow->rule[0]);
985 goto err_add_rule;
986 }
987
988 return 0;
aa0cbbae
OG		 989
990err_add_rule:
b8aee822
MB		 991 mlx5_fc_destroy(esw->dev, counter);
992err_create_counter:
513f8f7f 993 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 994 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 995err_mod_hdr:
aa0cbbae
OG		 996 mlx5_eswitch_del_vlan_action(esw, attr);
997err_add_vlan:
f493f155
EB		 998 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
999 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
1000 mlx5e_detach_encap(priv, flow);
1001 break;
1002 }
3c37745e 1003err_attach_encap:
bf07aa73 1004err_max_prio_chain:
c83954ab 1005 return err;
aa0cbbae 1006}
d85cdccb
OG		 1007
1008static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1009 struct mlx5e_tc_flow *flow)
1010{
1011 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1012 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
5dbe906f 1013 struct mlx5_esw_flow_attr slow_attr;
f493f155 1014 int out_index;
d85cdccb 1015
5dbe906f
PB		 1016 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
1017 if (flow->flags & MLX5E_TC_FLOW_SLOW)
1018 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1019 else
1020 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1021 }
d85cdccb 1022
513f8f7f 1023 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1024
f493f155
EB		 1025 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
1026 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
1027 mlx5e_detach_encap(priv, flow);
1028 break;
1029 }
1030 kvfree(attr->parse_attr);
d7e75a32 1031
513f8f7f 1032 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1033 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1034
1035 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1036 mlx5_fc_destroy(esw->dev, attr->counter);
d85cdccb
OG		 1037}
1038
232c0013
HHZ		 1039void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1040 struct mlx5e_encap_entry *e)
1041{
3c37745e 1042 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1043 struct mlx5_esw_flow_attr slow_attr, *esw_attr;
6d2a3ed0
OG		 1044 struct mlx5_flow_handle *rule;
1045 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1046 struct mlx5e_tc_flow *flow;
1047 int err;
1048
54c177ca
OS		 1049 err = mlx5_packet_reformat_alloc(priv->mdev,
1050 e->reformat_type,
60786f09 1051 e->encap_size, e->encap_header,
31ca3648 1052 MLX5_FLOW_NAMESPACE_FDB,
60786f09 1053 &e->encap_id);
232c0013
HHZ		 1054 if (err) {
1055 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
1056 err);
1057 return;
1058 }
1059 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1060 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013
HHZ		 1061
1062 list_for_each_entry(flow, &e->flows, encap) {
3c37745e
OG		 1063 esw_attr = flow->esw_attr;
1064 esw_attr->encap_id = e->encap_id;
6d2a3ed0
OG		 1065 spec = &esw_attr->parse_attr->spec;
1066
5dbe906f 1067 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1068 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1069 if (IS_ERR(rule)) {
1070 err = PTR_ERR(rule);
232c0013
HHZ		 1071 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1072 err);
1073 continue;
1074 }
5dbe906f
PB		 1075
1076 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1077 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when slow path rule removed */
6d2a3ed0 1078 flow->rule[0] = rule;
232c0013
HHZ		 1079 }
1080}
1081
1082void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1083 struct mlx5e_encap_entry *e)
1084{
3c37745e 1085 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f
PB		 1086 struct mlx5_esw_flow_attr slow_attr;
1087 struct mlx5_flow_handle *rule;
1088 struct mlx5_flow_spec *spec;
232c0013 1089 struct mlx5e_tc_flow *flow;
5dbe906f 1090 int err;
232c0013
HHZ		 1091
1092 list_for_each_entry(flow, &e->flows, encap) {
5dbe906f
PB		 1093 spec = &flow->esw_attr->parse_attr->spec;
1094
1095 /* update from encap rule to slow path rule */
1096 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
1097
1098 if (IS_ERR(rule)) {
1099 err = PTR_ERR(rule);
1100 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1101 err);
1102 continue;
1103 }
1104
1105 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1106 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when fast path rule removed */
1107 flow->rule[0] = rule;
232c0013
HHZ		 1108 }
1109
1110 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
1111 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
60786f09 1112 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013
HHZ		 1113 }
1114}
1115
b8aee822
MB		 1116static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1117{
1118 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1119 return flow->esw_attr->counter;
1120 else
1121 return flow->nic_attr->counter;
1122}
1123
f6dfb4c3
HHZ		 1124void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1125{
1126 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1127 u64 bytes, packets, lastuse = 0;
1128 struct mlx5e_tc_flow *flow;
1129 struct mlx5e_encap_entry *e;
1130 struct mlx5_fc *counter;
1131 struct neigh_table *tbl;
1132 bool neigh_used = false;
1133 struct neighbour *n;
1134
1135 if (m_neigh->family == AF_INET)
1136 tbl = &arp_tbl;
1137#if IS_ENABLED(CONFIG_IPV6)
1138 else if (m_neigh->family == AF_INET6)
423c9db2 1139 tbl = &nd_tbl;
f6dfb4c3
HHZ		 1140#endif
1141 else
1142 return;
1143
1144 list_for_each_entry(e, &nhe->encap_list, encap_list) {
1145 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1146 continue;
1147 list_for_each_entry(flow, &e->flows, encap) {
1148 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
b8aee822 1149 counter = mlx5e_tc_get_counter(flow);
f6dfb4c3
HHZ		 1150 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1151 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1152 neigh_used = true;
1153 break;
1154 }
1155 }
1156 }
e36d4810
RD		 1157 if (neigh_used)
1158 break;
f6dfb4c3
HHZ		 1159 }
1160
1161 if (neigh_used) {
1162 nhe->reported_lastuse = jiffies;
1163
1164 /* find the relevant neigh according to the cached device and
1165 * dst ip pair
1166 */
1167 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1168 if (!n)
f6dfb4c3 1169 return;
f6dfb4c3
HHZ		 1170
1171 neigh_event_send(n, NULL);
1172 neigh_release(n);
1173 }
1174}
1175
d85cdccb
OG		 1176static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1177 struct mlx5e_tc_flow *flow)
1178{
5067b602
RD		 1179 struct list_head *next = flow->encap.next;
1180
1181 list_del(&flow->encap);
1182 if (list_empty(next)) {
c1ae1152 1183 struct mlx5e_encap_entry *e;
5067b602 1184
c1ae1152 1185 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1186 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1187
1188 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
60786f09 1189 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013 1190
cdc5a7f3 1191 hash_del_rcu(&e->encap_hlist);
232c0013 1192 kfree(e->encap_header);
5067b602
RD		 1193 kfree(e);
1194 }
1195}
1196
e8f887ac 1197static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1198 struct mlx5e_tc_flow *flow)
e8f887ac 1199{
d85cdccb
OG		 1200 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1201 mlx5e_tc_del_fdb_flow(priv, flow);
1202 else
1203 mlx5e_tc_del_nic_flow(priv, flow);
e8f887ac
AV		 1204}
1205
bbd00f7e
HHZ		 1206
1207static int parse_tunnel_attr(struct mlx5e_priv *priv,
1208 struct mlx5_flow_spec *spec,
54c177ca
OS		 1209 struct tc_cls_flower_offload *f,
1210 struct net_device *filter_dev)
bbd00f7e 1211{
e98bedf5 1212 struct netlink_ext_ack *extack = f->common.extack;
bbd00f7e
HHZ		 1213 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1214 outer_headers);
1215 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1216 outer_headers);
1217
2e72eb43
OG		 1218 struct flow_dissector_key_control *enc_control =
1219 skb_flow_dissector_target(f->dissector,
1220 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1221 f->key);
54c177ca 1222 int err = 0;
2e72eb43 1223
101f4de9
OS		 1224 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1225 headers_c, headers_v);
54c177ca
OS		 1226 if (err) {
1227 NL_SET_ERR_MSG_MOD(extack,
1228 "failed to parse tunnel attributes");
101f4de9 1229 return err;
bbd00f7e
HHZ		 1230 }
1231
2e72eb43 1232 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ		 1233 struct flow_dissector_key_ipv4_addrs *key =
1234 skb_flow_dissector_target(f->dissector,
1235 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1236 f->key);
1237 struct flow_dissector_key_ipv4_addrs *mask =
1238 skb_flow_dissector_target(f->dissector,
1239 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1240 f->mask);
1241 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1242 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1243 ntohl(mask->src));
1244 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1245 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1246 ntohl(key->src));
1247
1248 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1249 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1250 ntohl(mask->dst));
1251 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1252 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1253 ntohl(key->dst));
bbd00f7e 1254
2e72eb43
OG		 1255 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1256 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG		 1257 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1258 struct flow_dissector_key_ipv6_addrs *key =
1259 skb_flow_dissector_target(f->dissector,
1260 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1261 f->key);
1262 struct flow_dissector_key_ipv6_addrs *mask =
1263 skb_flow_dissector_target(f->dissector,
1264 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1265 f->mask);
1266
1267 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1268 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1269 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1270 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1271 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1272 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1273
1274 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1275 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1276 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1277 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1278 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1279 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1280
1281 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1282 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1283 }
bbd00f7e 1284
bcef735c
OG		 1285 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_IP)) {
1286 struct flow_dissector_key_ip *key =
1287 skb_flow_dissector_target(f->dissector,
1288 FLOW_DISSECTOR_KEY_ENC_IP,
1289 f->key);
1290 struct flow_dissector_key_ip *mask =
1291 skb_flow_dissector_target(f->dissector,
1292 FLOW_DISSECTOR_KEY_ENC_IP,
1293 f->mask);
1294
1295 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1296 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1297
1298 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1299 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1300
1301 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1302 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
e98bedf5
EB		 1303
1304 if (mask->ttl &&
1305 !MLX5_CAP_ESW_FLOWTABLE_FDB
1306 (priv->mdev,
1307 ft_field_support.outer_ipv4_ttl)) {
1308 NL_SET_ERR_MSG_MOD(extack,
1309 "Matching on TTL is not supported");
1310 return -EOPNOTSUPP;
1311 }
1312
bcef735c
OG		 1313 }
1314
bbd00f7e
HHZ		 1315 /* Enforce DMAC when offloading incoming tunneled flows.
1316 * Flow counters require a match on the DMAC.
1317 */
1318 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1319 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1320 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1321 dmac_47_16), priv->netdev->dev_addr);
1322
1323 /* let software handle IP fragments */
1324 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1325 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1326
1327 return 0;
1328}
1329
de0af0bf
RD		 1330static int __parse_cls_flower(struct mlx5e_priv *priv,
1331 struct mlx5_flow_spec *spec,
1332 struct tc_cls_flower_offload *f,
54c177ca 1333 struct net_device *filter_dev,
d708f902 1334 u8 *match_level)
e3a2b7ed 1335{
e98bedf5 1336 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1337 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1338 outer_headers);
1339 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1340 outer_headers);
699e96dd
JL		 1341 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1342 misc_parameters);
1343 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1344 misc_parameters);
e3a2b7ed
AV		 1345 u16 addr_type = 0;
1346 u8 ip_proto = 0;
1347
d708f902 1348 *match_level = MLX5_MATCH_NONE;
de0af0bf 1349
e3a2b7ed
AV		 1350 if (f->dissector->used_keys &
1351 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1352 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1353 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1354 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1355 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1356 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1357 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1358 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1359 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1360 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1361 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1362 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1363 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1364 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c
OG		 1365 BIT(FLOW_DISSECTOR_KEY_IP) |
1366 BIT(FLOW_DISSECTOR_KEY_ENC_IP))) {
e98bedf5 1367 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed
AV		 1368 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1369 f->dissector->used_keys);
1370 return -EOPNOTSUPP;
1371 }
1372
bbd00f7e
HHZ		 1373 if ((dissector_uses_key(f->dissector,
1374 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1375 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1376 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1377 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1378 struct flow_dissector_key_control *key =
1379 skb_flow_dissector_target(f->dissector,
1380 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1381 f->key);
1382 switch (key->addr_type) {
1383 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 1384 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
54c177ca 1385 if (parse_tunnel_attr(priv, spec, f, filter_dev))
bbd00f7e
HHZ		 1386 return -EOPNOTSUPP;
1387 break;
1388 default:
1389 return -EOPNOTSUPP;
1390 }
1391
1392 /* In decap flow, header pointers should point to the inner
1393 * headers, outer header were already set by parse_tunnel_attr
1394 */
1395 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1396 inner_headers);
1397 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1398 inner_headers);
1399 }
1400
d3a80bb5
OG		 1401 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1402 struct flow_dissector_key_basic *key =
e3a2b7ed 1403 skb_flow_dissector_target(f->dissector,
d3a80bb5 1404 FLOW_DISSECTOR_KEY_BASIC,
e3a2b7ed 1405 f->key);
d3a80bb5 1406 struct flow_dissector_key_basic *mask =
e3a2b7ed 1407 skb_flow_dissector_target(f->dissector,
d3a80bb5 1408 FLOW_DISSECTOR_KEY_BASIC,
e3a2b7ed 1409 f->mask);
d3a80bb5
OG		 1410 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1411 ntohs(mask->n_proto));
1412 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1413 ntohs(key->n_proto));
e3a2b7ed 1414
d3a80bb5 1415 if (mask->n_proto)
d708f902 1416 *match_level = MLX5_MATCH_L2;
e3a2b7ed
AV		 1417 }
1418
095b6cfd
OG		 1419 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
1420 struct flow_dissector_key_vlan *key =
1421 skb_flow_dissector_target(f->dissector,
1422 FLOW_DISSECTOR_KEY_VLAN,
1423 f->key);
1424 struct flow_dissector_key_vlan *mask =
1425 skb_flow_dissector_target(f->dissector,
1426 FLOW_DISSECTOR_KEY_VLAN,
1427 f->mask);
699e96dd
JL		 1428 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1429 if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1430 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1431 svlan_tag, 1);
1432 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1433 svlan_tag, 1);
1434 } else {
1435 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1436 cvlan_tag, 1);
1437 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1438 cvlan_tag, 1);
1439 }
095b6cfd
OG		 1440
1441 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
1442 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG		 1443
1444 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
1445 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
54782900 1446
d708f902 1447 *match_level = MLX5_MATCH_L2;
54782900 1448 }
d3a80bb5 1449 } else if (*match_level != MLX5_MATCH_NONE) {
cee26487
JL		 1450 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1451 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 1452 *match_level = MLX5_MATCH_L2;
54782900
OG		 1453 }
1454
699e96dd
JL		 1455 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CVLAN)) {
1456 struct flow_dissector_key_vlan *key =
1457 skb_flow_dissector_target(f->dissector,
1458 FLOW_DISSECTOR_KEY_CVLAN,
1459 f->key);
1460 struct flow_dissector_key_vlan *mask =
1461 skb_flow_dissector_target(f->dissector,
1462 FLOW_DISSECTOR_KEY_CVLAN,
1463 f->mask);
1464 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1465 if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1466 MLX5_SET(fte_match_set_misc, misc_c,
1467 outer_second_svlan_tag, 1);
1468 MLX5_SET(fte_match_set_misc, misc_v,
1469 outer_second_svlan_tag, 1);
1470 } else {
1471 MLX5_SET(fte_match_set_misc, misc_c,
1472 outer_second_cvlan_tag, 1);
1473 MLX5_SET(fte_match_set_misc, misc_v,
1474 outer_second_cvlan_tag, 1);
1475 }
1476
1477 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
1478 mask->vlan_id);
1479 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
1480 key->vlan_id);
1481 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
1482 mask->vlan_priority);
1483 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
1484 key->vlan_priority);
1485
1486 *match_level = MLX5_MATCH_L2;
1487 }
1488 }
1489
d3a80bb5
OG		 1490 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1491 struct flow_dissector_key_eth_addrs *key =
54782900 1492 skb_flow_dissector_target(f->dissector,
d3a80bb5 1493 FLOW_DISSECTOR_KEY_ETH_ADDRS,
54782900 1494 f->key);
d3a80bb5 1495 struct flow_dissector_key_eth_addrs *mask =
54782900 1496 skb_flow_dissector_target(f->dissector,
d3a80bb5 1497 FLOW_DISSECTOR_KEY_ETH_ADDRS,
54782900 1498 f->mask);
54782900 1499
d3a80bb5
OG		 1500 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1501 dmac_47_16),
1502 mask->dst);
1503 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1504 dmac_47_16),
1505 key->dst);
1506
1507 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1508 smac_47_16),
1509 mask->src);
1510 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1511 smac_47_16),
1512 key->src);
1513
1514 if (!is_zero_ether_addr(mask->src) || !is_zero_ether_addr(mask->dst))
d708f902 1515 *match_level = MLX5_MATCH_L2;
54782900
OG		 1516 }
1517
1518 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
1519 struct flow_dissector_key_control *key =
1520 skb_flow_dissector_target(f->dissector,
1521 FLOW_DISSECTOR_KEY_CONTROL,
1522 f->key);
1523
1524 struct flow_dissector_key_control *mask =
1525 skb_flow_dissector_target(f->dissector,
1526 FLOW_DISSECTOR_KEY_CONTROL,
1527 f->mask);
1528 addr_type = key->addr_type;
1529
1530 /* the HW doesn't support frag first/later */
1531 if (mask->flags & FLOW_DIS_FIRST_FRAG)
1532 return -EOPNOTSUPP;
1533
1534 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
1535 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1536 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1537 key->flags & FLOW_DIS_IS_FRAGMENT);
1538
1539 /* the HW doesn't need L3 inline to match on frag=no */
1540 if (!(key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 1541 *match_level = MLX5_MATCH_L2;
54782900
OG		 1542 /* *** L2 attributes parsing up to here *** */
1543 else
83621b7d 1544 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 1545 }
1546 }
1547
54782900
OG		 1548 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1549 struct flow_dissector_key_basic *key =
1550 skb_flow_dissector_target(f->dissector,
1551 FLOW_DISSECTOR_KEY_BASIC,
1552 f->key);
1553 struct flow_dissector_key_basic *mask =
1554 skb_flow_dissector_target(f->dissector,
1555 FLOW_DISSECTOR_KEY_BASIC,
1556 f->mask);
1557 ip_proto = key->ip_proto;
1558
1559 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1560 mask->ip_proto);
1561 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1562 key->ip_proto);
1563
1564 if (mask->ip_proto)
d708f902 1565 *match_level = MLX5_MATCH_L3;
54782900
OG		 1566 }
1567
e3a2b7ed
AV		 1568 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1569 struct flow_dissector_key_ipv4_addrs *key =
1570 skb_flow_dissector_target(f->dissector,
1571 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1572 f->key);
1573 struct flow_dissector_key_ipv4_addrs *mask =
1574 skb_flow_dissector_target(f->dissector,
1575 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1576 f->mask);
1577
1578 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1579 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1580 &mask->src, sizeof(mask->src));
1581 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1582 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1583 &key->src, sizeof(key->src));
1584 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1585 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1586 &mask->dst, sizeof(mask->dst));
1587 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1588 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1589 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1590
1591 if (mask->src || mask->dst)
d708f902 1592 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1593 }
1594
1595 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1596 struct flow_dissector_key_ipv6_addrs *key =
1597 skb_flow_dissector_target(f->dissector,
1598 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1599 f->key);
1600 struct flow_dissector_key_ipv6_addrs *mask =
1601 skb_flow_dissector_target(f->dissector,
1602 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1603 f->mask);
1604
1605 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1606 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1607 &mask->src, sizeof(mask->src));
1608 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1609 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1610 &key->src, sizeof(key->src));
1611
1612 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1613 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1614 &mask->dst, sizeof(mask->dst));
1615 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1616 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1617 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1618
1619 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
1620 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
d708f902 1621 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1622 }
1623
1f97a526
OG		 1624 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
1625 struct flow_dissector_key_ip *key =
1626 skb_flow_dissector_target(f->dissector,
1627 FLOW_DISSECTOR_KEY_IP,
1628 f->key);
1629 struct flow_dissector_key_ip *mask =
1630 skb_flow_dissector_target(f->dissector,
1631 FLOW_DISSECTOR_KEY_IP,
1632 f->mask);
1633
1634 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1635 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1636
1637 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1638 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1639
a8ade55f
OG		 1640 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1641 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1f97a526 1642
a8ade55f
OG		 1643 if (mask->ttl &&
1644 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 1645 ft_field_support.outer_ipv4_ttl)) {
1646 NL_SET_ERR_MSG_MOD(extack,
1647 "Matching on TTL is not supported");
1f97a526 1648 return -EOPNOTSUPP;
e98bedf5 1649 }
a8ade55f
OG		 1650
1651 if (mask->tos || mask->ttl)
d708f902 1652 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 1653 }
1654
54782900
OG		 1655 /* *** L3 attributes parsing up to here *** */
1656
e3a2b7ed
AV		 1657 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
1658 struct flow_dissector_key_ports *key =
1659 skb_flow_dissector_target(f->dissector,
1660 FLOW_DISSECTOR_KEY_PORTS,
1661 f->key);
1662 struct flow_dissector_key_ports *mask =
1663 skb_flow_dissector_target(f->dissector,
1664 FLOW_DISSECTOR_KEY_PORTS,
1665 f->mask);
1666 switch (ip_proto) {
1667 case IPPROTO_TCP:
1668 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1669 tcp_sport, ntohs(mask->src));
1670 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1671 tcp_sport, ntohs(key->src));
1672
1673 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1674 tcp_dport, ntohs(mask->dst));
1675 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1676 tcp_dport, ntohs(key->dst));
1677 break;
1678
1679 case IPPROTO_UDP:
1680 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1681 udp_sport, ntohs(mask->src));
1682 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1683 udp_sport, ntohs(key->src));
1684
1685 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1686 udp_dport, ntohs(mask->dst));
1687 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1688 udp_dport, ntohs(key->dst));
1689 break;
1690 default:
e98bedf5
EB		 1691 NL_SET_ERR_MSG_MOD(extack,
1692 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 1693 netdev_err(priv->netdev,
1694 "Only UDP and TCP transport are supported\n");
1695 return -EINVAL;
1696 }
de0af0bf
RD		 1697
1698 if (mask->src || mask->dst)
d708f902 1699 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 1700 }
1701
e77834ec
OG		 1702 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
1703 struct flow_dissector_key_tcp *key =
1704 skb_flow_dissector_target(f->dissector,
1705 FLOW_DISSECTOR_KEY_TCP,
1706 f->key);
1707 struct flow_dissector_key_tcp *mask =
1708 skb_flow_dissector_target(f->dissector,
1709 FLOW_DISSECTOR_KEY_TCP,
1710 f->mask);
1711
1712 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1713 ntohs(mask->flags));
1714 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1715 ntohs(key->flags));
1716
1717 if (mask->flags)
d708f902 1718 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 1719 }
1720
e3a2b7ed
AV		 1721 return 0;
1722}
1723
de0af0bf 1724static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1725 struct mlx5e_tc_flow *flow,
de0af0bf 1726 struct mlx5_flow_spec *spec,
54c177ca
OS		 1727 struct tc_cls_flower_offload *f,
1728 struct net_device *filter_dev)
de0af0bf 1729{
e98bedf5 1730 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 1731 struct mlx5_core_dev *dev = priv->mdev;
1732 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 1733 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1734 struct mlx5_eswitch_rep *rep;
d708f902 1735 u8 match_level;
de0af0bf
RD		 1736 int err;
1737
54c177ca 1738 err = __parse_cls_flower(priv, spec, f, filter_dev, &match_level);
de0af0bf 1739
1d447a39
SM		 1740 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1741 rep = rpriv->rep;
1742 if (rep->vport != FDB_UPLINK_VPORT &&
1743 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
d708f902 1744 esw->offloads.inline_mode < match_level)) {
e98bedf5
EB		 1745 NL_SET_ERR_MSG_MOD(extack,
1746 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 1747 netdev_warn(priv->netdev,
1748 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
d708f902 1749 match_level, esw->offloads.inline_mode);
de0af0bf
RD		 1750 return -EOPNOTSUPP;
1751 }
1752 }
1753
38aa51c1
OG		 1754 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1755 flow->esw_attr->match_level = match_level;
1756 else
1757 flow->nic_attr->match_level = match_level;
1758
de0af0bf
RD		 1759 return err;
1760}
1761
d79b6df6
OG		 1762struct pedit_headers {
1763 struct ethhdr eth;
1764 struct iphdr ip4;
1765 struct ipv6hdr ip6;
1766 struct tcphdr tcp;
1767 struct udphdr udp;
1768};
1769
1770static int pedit_header_offsets[] = {
1771 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1772 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1773 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1774 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1775 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1776};
1777
1778#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1779
1780static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1781 struct pedit_headers *masks,
1782 struct pedit_headers *vals)
1783{
1784 u32 *curr_pmask, *curr_pval;
1785
1786 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1787 goto out_err;
1788
1789 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1790 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1791
1792 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1793 goto out_err;
1794
1795 *curr_pmask |= mask;
1796 *curr_pval |= (val & mask);
1797
1798 return 0;
1799
1800out_err:
1801 return -EOPNOTSUPP;
1802}
1803
1804struct mlx5_fields {
1805 u8 field;
1806 u8 size;
1807 u32 offset;
1808};
1809
a8e4f0c4
OG		 1810#define OFFLOAD(fw_field, size, field, off) \
1811 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1812
d79b6df6 1813static struct mlx5_fields fields[] = {
a8e4f0c4
OG		 1814 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1815 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1816 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1817 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1818 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
1819
1820 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1821 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1822 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1823
1824 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1825 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1826 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1827 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1828 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1829 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1830 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1831 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
0c0316f5 1832 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
a8e4f0c4
OG		 1833
1834 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1835 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1836 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1837
1838 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1839 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
d79b6df6
OG		 1840};
1841
1842/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1843 * max from the SW pedit action. On success, it says how many HW actions were
1844 * actually parsed.
1845 */
1846static int offload_pedit_fields(struct pedit_headers *masks,
1847 struct pedit_headers *vals,
e98bedf5
EB		 1848 struct mlx5e_tc_flow_parse_attr *parse_attr,
1849 struct netlink_ext_ack *extack)
d79b6df6
OG		 1850{
1851 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 1852 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 1853 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1854 struct mlx5_fields *f;
1855 u8 cmd, field_bsize;
e3ca4e05 1856 u32 s_mask, a_mask;
d79b6df6 1857 unsigned long mask;
2b64beba
OG		 1858 __be32 mask_be32;
1859 __be16 mask_be16;
d79b6df6
OG		 1860 void *action;
1861
1862 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1863 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1864 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1865 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1866
1867 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1868 action = parse_attr->mod_hdr_actions;
1869 max_actions = parse_attr->num_mod_hdr_actions;
1870 nactions = 0;
1871
1872 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1873 f = &fields[i];
1874 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 1875 s_mask = 0;
1876 a_mask = 0;
d79b6df6
OG		 1877
1878 s_masks_p = (void *)set_masks + f->offset;
1879 a_masks_p = (void *)add_masks + f->offset;
1880
1881 memcpy(&s_mask, s_masks_p, f->size);
1882 memcpy(&a_mask, a_masks_p, f->size);
1883
1884 if (!s_mask && !a_mask) /* nothing to offload here */
1885 continue;
1886
1887 if (s_mask && a_mask) {
e98bedf5
EB		 1888 NL_SET_ERR_MSG_MOD(extack,
1889 "can't set and add to the same HW field");
d79b6df6
OG		 1890 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1891 return -EOPNOTSUPP;
1892 }
1893
1894 if (nactions == max_actions) {
e98bedf5
EB		 1895 NL_SET_ERR_MSG_MOD(extack,
1896 "too many pedit actions, can't offload");
d79b6df6
OG		 1897 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1898 return -EOPNOTSUPP;
1899 }
1900
1901 if (s_mask) {
1902 cmd = MLX5_ACTION_TYPE_SET;
1903 mask = s_mask;
1904 vals_p = (void *)set_vals + f->offset;
1905 /* clear to denote we consumed this field */
1906 memset(s_masks_p, 0, f->size);
1907 } else {
1908 cmd = MLX5_ACTION_TYPE_ADD;
1909 mask = a_mask;
1910 vals_p = (void *)add_vals + f->offset;
1911 /* clear to denote we consumed this field */
1912 memset(a_masks_p, 0, f->size);
1913 }
1914
d79b6df6 1915 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 1916
2b64beba
OG		 1917 if (field_bsize == 32) {
1918 mask_be32 = *(__be32 *)&mask;
1919 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1920 } else if (field_bsize == 16) {
1921 mask_be16 = *(__be16 *)&mask;
1922 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1923 }
1924
d79b6df6 1925 first = find_first_bit(&mask, field_bsize);
2b64beba 1926 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 1927 last = find_last_bit(&mask, field_bsize);
2b64beba 1928 if (first < next_z && next_z < last) {
e98bedf5
EB		 1929 NL_SET_ERR_MSG_MOD(extack,
1930 "rewrite of few sub-fields isn't supported");
2b64beba 1931 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 1932 mask);
1933 return -EOPNOTSUPP;
1934 }
1935
1936 MLX5_SET(set_action_in, action, action_type, cmd);
1937 MLX5_SET(set_action_in, action, field, f->field);
1938
1939 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 1940 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 1941 /* length is num of bits to be written, zero means length of 32 */
2b64beba 1942 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 1943 }
1944
1945 if (field_bsize == 32)
2b64beba 1946 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 1947 else if (field_bsize == 16)
2b64beba 1948 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 1949 else if (field_bsize == 8)
2b64beba 1950 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 1951
1952 action += action_size;
1953 nactions++;
1954 }
1955
1956 parse_attr->num_mod_hdr_actions = nactions;
1957 return 0;
1958}
1959
1960static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
1961 const struct tc_action *a, int namespace,
1962 struct mlx5e_tc_flow_parse_attr *parse_attr)
1963{
1964 int nkeys, action_size, max_actions;
1965
1966 nkeys = tcf_pedit_nkeys(a);
1967 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1968
1969 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
1970 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
1971 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
1972 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
1973
1974 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
1975 max_actions = min(max_actions, nkeys * 16);
1976
1977 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
1978 if (!parse_attr->mod_hdr_actions)
1979 return -ENOMEM;
1980
1981 parse_attr->num_mod_hdr_actions = max_actions;
1982 return 0;
1983}
1984
1985static const struct pedit_headers zero_masks = {};
1986
1987static int parse_tc_pedit_action(struct mlx5e_priv *priv,
1988 const struct tc_action *a, int namespace,
e98bedf5
EB		 1989 struct mlx5e_tc_flow_parse_attr *parse_attr,
1990 struct netlink_ext_ack *extack)
d79b6df6
OG		 1991{
1992 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
1993 int nkeys, i, err = -EOPNOTSUPP;
1994 u32 mask, val, offset;
1995 u8 cmd, htype;
1996
1997 nkeys = tcf_pedit_nkeys(a);
1998
1999 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
2000 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
2001
2002 for (i = 0; i < nkeys; i++) {
2003 htype = tcf_pedit_htype(a, i);
2004 cmd = tcf_pedit_cmd(a, i);
2005 err = -EOPNOTSUPP; /* can't be all optimistic */
2006
2007 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
e98bedf5
EB		 2008 NL_SET_ERR_MSG_MOD(extack,
2009 "legacy pedit isn't offloaded");
d79b6df6
OG		 2010 goto out_err;
2011 }
2012
2013 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
e98bedf5 2014 NL_SET_ERR_MSG_MOD(extack, "pedit cmd isn't offloaded");
d79b6df6
OG		 2015 goto out_err;
2016 }
2017
2018 mask = tcf_pedit_mask(a, i);
2019 val = tcf_pedit_val(a, i);
2020 offset = tcf_pedit_offset(a, i);
2021
2022 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
2023 if (err)
2024 goto out_err;
2025 }
2026
2027 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
2028 if (err)
2029 goto out_err;
2030
e98bedf5 2031 err = offload_pedit_fields(masks, vals, parse_attr, extack);
d79b6df6
OG		 2032 if (err < 0)
2033 goto out_dealloc_parsed_actions;
2034
2035 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
2036 cmd_masks = &masks[cmd];
2037 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2038 NL_SET_ERR_MSG_MOD(extack,
2039 "attempt to offload an unsupported field");
b3a433de 2040 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2041 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2042 16, 1, cmd_masks, sizeof(zero_masks), true);
2043 err = -EOPNOTSUPP;
2044 goto out_dealloc_parsed_actions;
2045 }
2046 }
2047
2048 return 0;
2049
2050out_dealloc_parsed_actions:
2051 kfree(parse_attr->mod_hdr_actions);
2052out_err:
2053 return err;
2054}
2055
e98bedf5
EB		 2056static bool csum_offload_supported(struct mlx5e_priv *priv,
2057 u32 action,
2058 u32 update_flags,
2059 struct netlink_ext_ack *extack)
26c02749
OG		 2060{
2061 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2062 TCA_CSUM_UPDATE_FLAG_UDP;
2063
2064 /* The HW recalcs checksums only if re-writing headers */
2065 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2066 NL_SET_ERR_MSG_MOD(extack,
2067 "TC csum action is only offloaded with pedit");
26c02749
OG		 2068 netdev_warn(priv->netdev,
2069 "TC csum action is only offloaded with pedit\n");
2070 return false;
2071 }
2072
2073 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2074 NL_SET_ERR_MSG_MOD(extack,
2075 "can't offload TC csum action for some header/s");
26c02749
OG		 2076 netdev_warn(priv->netdev,
2077 "can't offload TC csum action for some header/s - flags %#x\n",
2078 update_flags);
2079 return false;
2080 }
2081
2082 return true;
2083}
2084
bdd66ac0 2085static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
e98bedf5
EB		 2086 struct tcf_exts *exts,
2087 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2088{
2089 const struct tc_action *a;
2090 bool modify_ip_header;
2091 LIST_HEAD(actions);
2092 u8 htype, ip_proto;
2093 void *headers_v;
2094 u16 ethertype;
2095 int nkeys, i;
2096
2097 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2098 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2099
2100 /* for non-IP we only re-write MACs, so we're okay */
2101 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2102 goto out_ok;
2103
2104 modify_ip_header = false;
244cd96a
CW		 2105 tcf_exts_for_each_action(i, a, exts) {
2106 int k;
2107
bdd66ac0
OG		 2108 if (!is_tcf_pedit(a))
2109 continue;
2110
2111 nkeys = tcf_pedit_nkeys(a);
244cd96a
CW		 2112 for (k = 0; k < nkeys; k++) {
2113 htype = tcf_pedit_htype(a, k);
bdd66ac0
OG		 2114 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
2115 htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
2116 modify_ip_header = true;
2117 break;
2118 }
2119 }
2120 }
2121
2122 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 2123 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2124 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 2125 NL_SET_ERR_MSG_MOD(extack,
2126 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 2127 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2128 return false;
2129 }
2130
2131out_ok:
2132 return true;
2133}
2134
2135static bool actions_match_supported(struct mlx5e_priv *priv,
2136 struct tcf_exts *exts,
2137 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2138 struct mlx5e_tc_flow *flow,
2139 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2140{
2141 u32 actions;
2142
2143 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
2144 actions = flow->esw_attr->action;
2145 else
2146 actions = flow->nic_attr->action;
2147
7e29392e
RD		 2148 if (flow->flags & MLX5E_TC_FLOW_EGRESS &&
2149 !(actions & MLX5_FLOW_CONTEXT_ACTION_DECAP))
2150 return false;
2151
bdd66ac0 2152 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
e98bedf5
EB		 2153 return modify_header_match_supported(&parse_attr->spec, exts,
2154 extack);
bdd66ac0
OG		 2155
2156 return true;
2157}
2158
5c65c564
OG		 2159static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2160{
2161 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 2162 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 2163
2164 fmdev = priv->mdev;
2165 pmdev = peer_priv->mdev;
2166
59c9d35e
AH		 2167 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2168 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 2169
816f6706 2170 return (fsystem_guid == psystem_guid);
5c65c564
OG		 2171}
2172
5c40348c 2173static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae 2174 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2175 struct mlx5e_tc_flow *flow,
2176 struct netlink_ext_ack *extack)
e3a2b7ed 2177{
aa0cbbae 2178 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 2179 const struct tc_action *a;
22dc13c8 2180 LIST_HEAD(actions);
1cab1cd7 2181 u32 action = 0;
244cd96a 2182 int err, i;
e3a2b7ed 2183
3bcc0cec 2184 if (!tcf_exts_has_actions(exts))
e3a2b7ed
AV		 2185 return -EINVAL;
2186
3bc4b7bf 2187 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 2188
244cd96a 2189 tcf_exts_for_each_action(i, a, exts) {
e3a2b7ed 2190 if (is_tcf_gact_shot(a)) {
1cab1cd7 2191 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 2192 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2193 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2194 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV		 2195 continue;
2196 }
2197
2f4fe4ca
OG		 2198 if (is_tcf_pedit(a)) {
2199 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
e98bedf5 2200 parse_attr, extack);
2f4fe4ca
OG		 2201 if (err)
2202 return err;
2203
1cab1cd7
OG		 2204 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2205 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2f4fe4ca
OG		 2206 continue;
2207 }
2208
26c02749 2209 if (is_tcf_csum(a)) {
1cab1cd7 2210 if (csum_offload_supported(priv, action,
e98bedf5
EB		 2211 tcf_csum_update_flags(a),
2212 extack))
26c02749
OG		 2213 continue;
2214
2215 return -EOPNOTSUPP;
2216 }
2217
5c65c564
OG		 2218 if (is_tcf_mirred_egress_redirect(a)) {
2219 struct net_device *peer_dev = tcf_mirred_dev(a);
2220
2221 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2222 same_hw_devs(priv, netdev_priv(peer_dev))) {
2223 parse_attr->mirred_ifindex = peer_dev->ifindex;
2224 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
1cab1cd7
OG		 2225 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2226 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 2227 } else {
e98bedf5
EB		 2228 NL_SET_ERR_MSG_MOD(extack,
2229 "device is not on same HW, can't offload");
5c65c564
OG		 2230 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2231 peer_dev->name);
2232 return -EINVAL;
2233 }
2234 continue;
2235 }
2236
e3a2b7ed
AV		 2237 if (is_tcf_skbedit_mark(a)) {
2238 u32 mark = tcf_skbedit_mark(a);
2239
2240 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 2241 NL_SET_ERR_MSG_MOD(extack,
2242 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 2243 return -EINVAL;
2244 }
2245
3bc4b7bf 2246 attr->flow_tag = mark;
1cab1cd7 2247 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV		 2248 continue;
2249 }
2250
2251 return -EINVAL;
2252 }
2253
1cab1cd7 2254 attr->action = action;
e98bedf5 2255 if (!actions_match_supported(priv, exts, parse_attr, flow, extack))
bdd66ac0
OG		 2256 return -EOPNOTSUPP;
2257
e3a2b7ed
AV		 2258 return 0;
2259}
2260
76f7444d
OG		 2261static inline int cmp_encap_info(struct ip_tunnel_key *a,
2262 struct ip_tunnel_key *b)
a54e20b4
HHZ		 2263{
2264 return memcmp(a, b, sizeof(*a));
2265}
2266
76f7444d 2267static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 2268{
76f7444d 2269 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 2270}
2271
a54e20b4 2272
b1d90e6b
RL		 2273static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2274 struct net_device *peer_netdev)
2275{
2276 struct mlx5e_priv *peer_priv;
2277
2278 peer_priv = netdev_priv(peer_netdev);
2279
2280 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
2281 (priv->netdev->netdev_ops == peer_netdev->netdev_ops) &&
2282 same_hw_devs(priv, peer_priv) &&
2283 MLX5_VPORT_MANAGER(peer_priv->mdev) &&
2284 (peer_priv->mdev->priv.eswitch->mode == SRIOV_OFFLOADS));
2285}
2286
32f3671f 2287
f5bc2c5d 2288
a54e20b4
HHZ		 2289static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2290 struct ip_tunnel_info *tun_info,
2291 struct net_device *mirred_dev,
45247bf2 2292 struct net_device **encap_dev,
e98bedf5
EB		 2293 struct mlx5e_tc_flow *flow,
2294 struct netlink_ext_ack *extack)
a54e20b4
HHZ		 2295{
2296 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2297 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2 2298 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 2299 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 2300 struct mlx5e_encap_entry *e;
a54e20b4
HHZ		 2301 uintptr_t hash_key;
2302 bool found = false;
54c177ca 2303 int err = 0;
a54e20b4 2304
76f7444d 2305 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 2306
2307 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2308 encap_hlist, hash_key) {
76f7444d 2309 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 2310 found = true;
2311 break;
2312 }
2313 }
2314
b2812089 2315 /* must verify if encap is valid or not */
45247bf2
OG		 2316 if (found)
2317 goto attach_flow;
a54e20b4
HHZ		 2318
2319 e = kzalloc(sizeof(*e), GFP_KERNEL);
2320 if (!e)
2321 return -ENOMEM;
2322
76f7444d 2323 e->tun_info = *tun_info;
101f4de9 2324 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
54c177ca
OS		 2325 if (err)
2326 goto out_err;
2327
a54e20b4
HHZ		 2328 INIT_LIST_HEAD(&e->flows);
2329
ce99f6b9 2330 if (family == AF_INET)
101f4de9 2331 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2332 else if (family == AF_INET6)
101f4de9 2333 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2334
232c0013 2335 if (err && err != -EAGAIN)
a54e20b4
HHZ		 2336 goto out_err;
2337
a54e20b4
HHZ		 2338 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2339
45247bf2
OG		 2340attach_flow:
2341 list_add(&flow->encap, &e->flows);
2342 *encap_dev = e->out_dev;
232c0013
HHZ		 2343 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2344 attr->encap_id = e->encap_id;
b2812089
VB		 2345 else
2346 err = -EAGAIN;
45247bf2 2347
232c0013 2348 return err;
a54e20b4
HHZ		 2349
2350out_err:
2351 kfree(e);
2352 return err;
2353}
2354
1482bd3d
JL		 2355static int parse_tc_vlan_action(struct mlx5e_priv *priv,
2356 const struct tc_action *a,
2357 struct mlx5_esw_flow_attr *attr,
2358 u32 *action)
2359{
cc495188
JL		 2360 u8 vlan_idx = attr->total_vlan;
2361
2362 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2363 return -EOPNOTSUPP;
2364
1482bd3d 2365 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
cc495188
JL		 2366 if (vlan_idx) {
2367 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2368 MLX5_FS_VLAN_DEPTH))
2369 return -EOPNOTSUPP;
2370
2371 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2372 } else {
2373 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2374 }
1482bd3d 2375 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
cc495188
JL		 2376 attr->vlan_vid[vlan_idx] = tcf_vlan_push_vid(a);
2377 attr->vlan_prio[vlan_idx] = tcf_vlan_push_prio(a);
2378 attr->vlan_proto[vlan_idx] = tcf_vlan_push_proto(a);
2379 if (!attr->vlan_proto[vlan_idx])
2380 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2381
2382 if (vlan_idx) {
2383 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2384 MLX5_FS_VLAN_DEPTH))
2385 return -EOPNOTSUPP;
2386
2387 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2388 } else {
2389 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
2390 (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q) ||
2391 tcf_vlan_push_prio(a)))
2392 return -EOPNOTSUPP;
2393
2394 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d
JL		 2395 }
2396 } else { /* action is TCA_VLAN_ACT_MODIFY */
2397 return -EOPNOTSUPP;
2398 }
2399
cc495188
JL		 2400 attr->total_vlan = vlan_idx + 1;
2401
1482bd3d
JL		 2402 return 0;
2403}
2404
03a9d11e 2405static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 2406 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2407 struct mlx5e_tc_flow *flow,
2408 struct netlink_ext_ack *extack)
03a9d11e 2409{
bf07aa73 2410 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 2411 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 2412 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 2413 struct ip_tunnel_info *info = NULL;
03a9d11e 2414 const struct tc_action *a;
22dc13c8 2415 LIST_HEAD(actions);
a54e20b4 2416 bool encap = false;
1cab1cd7 2417 u32 action = 0;
244cd96a 2418 int err, i;
03a9d11e 2419
3bcc0cec 2420 if (!tcf_exts_has_actions(exts))
03a9d11e
OG		 2421 return -EINVAL;
2422
1d447a39 2423 attr->in_rep = rpriv->rep;
10ff5359 2424 attr->in_mdev = priv->mdev;
03a9d11e 2425
244cd96a 2426 tcf_exts_for_each_action(i, a, exts) {
03a9d11e 2427 if (is_tcf_gact_shot(a)) {
1cab1cd7
OG		 2428 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2429 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG		 2430 continue;
2431 }
2432
d7e75a32
OG		 2433 if (is_tcf_pedit(a)) {
2434 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
e98bedf5 2435 parse_attr, extack);
d7e75a32
OG		 2436 if (err)
2437 return err;
2438
1cab1cd7 2439 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e85e02ba 2440 attr->split_count = attr->out_count;
d7e75a32
OG		 2441 continue;
2442 }
2443
26c02749 2444 if (is_tcf_csum(a)) {
1cab1cd7 2445 if (csum_offload_supported(priv, action,
e98bedf5
EB		 2446 tcf_csum_update_flags(a),
2447 extack))
26c02749
OG		 2448 continue;
2449
2450 return -EOPNOTSUPP;
2451 }
2452
592d3651 2453 if (is_tcf_mirred_egress_redirect(a) || is_tcf_mirred_egress_mirror(a)) {
03a9d11e 2454 struct mlx5e_priv *out_priv;
592d3651 2455 struct net_device *out_dev;
03a9d11e 2456
9f8a739e 2457 out_dev = tcf_mirred_dev(a);
ef381359
OS		 2458 if (!out_dev) {
2459 /* out_dev is NULL when filters with
2460 * non-existing mirred device are replayed to
2461 * the driver.
2462 */
2463 return -EINVAL;
2464 }
03a9d11e 2465
592d3651 2466 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 2467 NL_SET_ERR_MSG_MOD(extack,
2468 "can't support more output ports, can't offload forwarding");
592d3651
CM		 2469 pr_err("can't support more than %d output ports, can't offload forwarding\n",
2470 attr->out_count);
2471 return -EOPNOTSUPP;
2472 }
2473
f493f155
EB		 2474 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2475 MLX5_FLOW_CONTEXT_ACTION_COUNT;
a54e20b4 2476 if (switchdev_port_same_parent_id(priv->netdev,
b1d90e6b
RL		 2477 out_dev) ||
2478 is_merged_eswitch_dev(priv, out_dev)) {
a54e20b4 2479 out_priv = netdev_priv(out_dev);
1d447a39 2480 rpriv = out_priv->ppriv;
df65a573
EB		 2481 attr->dests[attr->out_count].rep = rpriv->rep;
2482 attr->dests[attr->out_count].mdev = out_priv->mdev;
2483 attr->out_count++;
a54e20b4 2484 } else if (encap) {
9f8a739e 2485 parse_attr->mirred_ifindex = out_dev->ifindex;
3c37745e
OG		 2486 parse_attr->tun_info = *info;
2487 attr->parse_attr = parse_attr;
f493f155
EB		 2488 attr->dests[attr->out_count].flags |=
2489 MLX5_ESW_DEST_ENCAP;
df65a573
EB		 2490 /* attr->dests[].rep is resolved when we
2491 * handle encap
2492 */
ef381359
OS		 2493 } else if (parse_attr->filter_dev != priv->netdev) {
2494 /* All mlx5 devices are called to configure
2495 * high level device filters. Therefore, the
2496 * *attempt* to install a filter on invalid
2497 * eswitch should not trigger an explicit error
2498 */
2499 return -EINVAL;
a54e20b4 2500 } else {
e98bedf5
EB		 2501 NL_SET_ERR_MSG_MOD(extack,
2502 "devices are not on same switch HW, can't offload forwarding");
03a9d11e
OG		 2503 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2504 priv->netdev->name, out_dev->name);
2505 return -EINVAL;
2506 }
a54e20b4
HHZ		 2507 continue;
2508 }
03a9d11e 2509
a54e20b4
HHZ		 2510 if (is_tcf_tunnel_set(a)) {
2511 info = tcf_tunnel_info(a);
2512 if (info)
2513 encap = true;
2514 else
2515 return -EOPNOTSUPP;
03a9d11e
OG		 2516 continue;
2517 }
2518
8b32580d 2519 if (is_tcf_vlan(a)) {
1482bd3d
JL		 2520 err = parse_tc_vlan_action(priv, a, attr, &action);
2521
2522 if (err)
2523 return err;
2524
e85e02ba 2525 attr->split_count = attr->out_count;
8b32580d
OG		 2526 continue;
2527 }
2528
bbd00f7e 2529 if (is_tcf_tunnel_release(a)) {
1cab1cd7 2530 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
bbd00f7e
HHZ		 2531 continue;
2532 }
2533
bf07aa73
PB		 2534 if (is_tcf_gact_goto_chain(a)) {
2535 u32 dest_chain = tcf_gact_goto_chain_index(a);
2536 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
2537
2538 if (dest_chain <= attr->chain) {
2539 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
2540 return -EOPNOTSUPP;
2541 }
2542 if (dest_chain > max_chain) {
2543 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
2544 return -EOPNOTSUPP;
2545 }
2546 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2547 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2548 attr->dest_chain = dest_chain;
2549
2550 continue;
2551 }
2552
03a9d11e
OG		 2553 return -EINVAL;
2554 }
bdd66ac0 2555
1cab1cd7 2556 attr->action = action;
e98bedf5 2557 if (!actions_match_supported(priv, exts, parse_attr, flow, extack))
bdd66ac0
OG		 2558 return -EOPNOTSUPP;
2559
e85e02ba 2560 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 2561 NL_SET_ERR_MSG_MOD(extack,
2562 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 2563 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
2564 return -EOPNOTSUPP;
2565 }
2566
31c8eba5 2567 return 0;
03a9d11e
OG		 2568}
2569
5dbe906f 2570static void get_flags(int flags, u16 *flow_flags)
60bd4af8 2571{
5dbe906f 2572 u16 __flow_flags = 0;
60bd4af8
OG		 2573
2574 if (flags & MLX5E_TC_INGRESS)
2575 __flow_flags |= MLX5E_TC_FLOW_INGRESS;
2576 if (flags & MLX5E_TC_EGRESS)
2577 __flow_flags |= MLX5E_TC_FLOW_EGRESS;
2578
2579 *flow_flags = __flow_flags;
2580}
2581
05866c82
OG		 2582static const struct rhashtable_params tc_ht_params = {
2583 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2584 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2585 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2586 .automatic_shrinking = true,
2587};
2588
2589static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv)
2590{
655dc3d2
OG		 2591 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2592 struct mlx5e_rep_priv *uplink_rpriv;
2593
2594 if (MLX5_VPORT_MANAGER(priv->mdev) && esw->mode == SRIOV_OFFLOADS) {
2595 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 2596 return &uplink_rpriv->uplink_priv.tc_ht;
655dc3d2
OG		 2597 } else
2598 return &priv->fs.tc.ht;
05866c82
OG		 2599}
2600
a88780a9
RD		 2601static int
2602mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
5dbe906f 2603 struct tc_cls_flower_offload *f, u16 flow_flags,
a88780a9
RD		 2604 struct mlx5e_tc_flow_parse_attr **__parse_attr,
2605 struct mlx5e_tc_flow **__flow)
e3a2b7ed 2606{
17091853 2607 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 2608 struct mlx5e_tc_flow *flow;
a88780a9 2609 int err;
e3a2b7ed 2610
65ba8fb7 2611 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 2612 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 2613 if (!parse_attr || !flow) {
e3a2b7ed
AV		 2614 err = -ENOMEM;
2615 goto err_free;
2616 }
2617
2618 flow->cookie = f->cookie;
65ba8fb7 2619 flow->flags = flow_flags;
655dc3d2 2620 flow->priv = priv;
e3a2b7ed 2621
a88780a9
RD		 2622 *__flow = flow;
2623 *__parse_attr = parse_attr;
2624
2625 return 0;
2626
2627err_free:
2628 kfree(flow);
2629 kvfree(parse_attr);
2630 return err;
2631}
2632
2633static int
2634mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
2635 struct tc_cls_flower_offload *f,
5dbe906f 2636 u16 flow_flags,
d11afc26 2637 struct net_device *filter_dev,
a88780a9
RD		 2638 struct mlx5e_tc_flow **__flow)
2639{
2640 struct netlink_ext_ack *extack = f->common.extack;
2641 struct mlx5e_tc_flow_parse_attr *parse_attr;
2642 struct mlx5e_tc_flow *flow;
2643 int attr_size, err;
e3a2b7ed 2644
a88780a9
RD		 2645 flow_flags |= MLX5E_TC_FLOW_ESWITCH;
2646 attr_size = sizeof(struct mlx5_esw_flow_attr);
2647 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
2648 &parse_attr, &flow);
2649 if (err)
2650 goto out;
d11afc26
OS		 2651 parse_attr->filter_dev = filter_dev;
2652 flow->esw_attr->parse_attr = parse_attr;
54c177ca
OS		 2653 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
2654 f, filter_dev);
d11afc26
OS		 2655 if (err)
2656 goto err_free;
a88780a9 2657
bf07aa73
PB		 2658 flow->esw_attr->chain = f->common.chain_index;
2659 flow->esw_attr->prio = TC_H_MAJ(f->common.prio) >> 16;
a88780a9
RD		 2660 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow, extack);
2661 if (err)
2662 goto err_free;
2663
2664 err = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow, extack);
5dbe906f 2665 if (err)
c83954ab 2666 goto err_free;
e3a2b7ed 2667
a88780a9 2668 *__flow = flow;
5c40348c 2669
a88780a9
RD		 2670 return 0;
2671
2672err_free:
2673 kfree(flow);
2674 kvfree(parse_attr);
2675out:
232c0013 2676 return err;
a88780a9
RD		 2677}
2678
2679static int
2680mlx5e_add_nic_flow(struct mlx5e_priv *priv,
2681 struct tc_cls_flower_offload *f,
5dbe906f 2682 u16 flow_flags,
d11afc26 2683 struct net_device *filter_dev,
a88780a9
RD		 2684 struct mlx5e_tc_flow **__flow)
2685{
2686 struct netlink_ext_ack *extack = f->common.extack;
2687 struct mlx5e_tc_flow_parse_attr *parse_attr;
2688 struct mlx5e_tc_flow *flow;
2689 int attr_size, err;
2690
bf07aa73
PB		 2691 /* multi-chain not supported for NIC rules */
2692 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
2693 return -EOPNOTSUPP;
2694
a88780a9
RD		 2695 flow_flags |= MLX5E_TC_FLOW_NIC;
2696 attr_size = sizeof(struct mlx5_nic_flow_attr);
2697 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
2698 &parse_attr, &flow);
2699 if (err)
2700 goto out;
2701
d11afc26 2702 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 2703 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
2704 f, filter_dev);
d11afc26
OS		 2705 if (err)
2706 goto err_free;
2707
a88780a9
RD		 2708 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow, extack);
2709 if (err)
2710 goto err_free;
2711
2712 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
2713 if (err)
2714 goto err_free;
2715
2716 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
2717 kvfree(parse_attr);
2718 *__flow = flow;
2719
2720 return 0;
e3a2b7ed 2721
e3a2b7ed 2722err_free:
a88780a9 2723 kfree(flow);
17091853 2724 kvfree(parse_attr);
a88780a9
RD		 2725out:
2726 return err;
2727}
2728
2729static int
2730mlx5e_tc_add_flow(struct mlx5e_priv *priv,
2731 struct tc_cls_flower_offload *f,
2732 int flags,
d11afc26 2733 struct net_device *filter_dev,
a88780a9
RD		 2734 struct mlx5e_tc_flow **flow)
2735{
2736 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 2737 u16 flow_flags;
a88780a9
RD		 2738 int err;
2739
2740 get_flags(flags, &flow_flags);
2741
bf07aa73
PB		 2742 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
2743 return -EOPNOTSUPP;
2744
a88780a9 2745 if (esw && esw->mode == SRIOV_OFFLOADS)
d11afc26
OS		 2746 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
2747 filter_dev, flow);
a88780a9 2748 else
d11afc26
OS		 2749 err = mlx5e_add_nic_flow(priv, f, flow_flags,
2750 filter_dev, flow);
a88780a9
RD		 2751
2752 return err;
2753}
2754
71d82d2a 2755int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
a88780a9
RD		 2756 struct tc_cls_flower_offload *f, int flags)
2757{
2758 struct netlink_ext_ack *extack = f->common.extack;
2759 struct rhashtable *tc_ht = get_tc_ht(priv);
2760 struct mlx5e_tc_flow *flow;
2761 int err = 0;
2762
2763 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
2764 if (flow) {
2765 NL_SET_ERR_MSG_MOD(extack,
2766 "flow cookie already exists, ignoring");
2767 netdev_warn_once(priv->netdev,
2768 "flow cookie %lx already exists, ignoring\n",
2769 f->cookie);
2770 goto out;
2771 }
2772
d11afc26 2773 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 2774 if (err)
2775 goto out;
2776
2777 err = rhashtable_insert_fast(tc_ht, &flow->node, tc_ht_params);
2778 if (err)
2779 goto err_free;
2780
2781 return 0;
2782
2783err_free:
2784 mlx5e_tc_del_flow(priv, flow);
232c0013 2785 kfree(flow);
a88780a9 2786out:
e3a2b7ed
AV		 2787 return err;
2788}
2789
8f8ae895
OG		 2790#define DIRECTION_MASK (MLX5E_TC_INGRESS | MLX5E_TC_EGRESS)
2791#define FLOW_DIRECTION_MASK (MLX5E_TC_FLOW_INGRESS | MLX5E_TC_FLOW_EGRESS)
2792
2793static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
2794{
2795 if ((flow->flags & FLOW_DIRECTION_MASK) == (flags & DIRECTION_MASK))
2796 return true;
2797
2798 return false;
2799}
2800
71d82d2a 2801int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
60bd4af8 2802 struct tc_cls_flower_offload *f, int flags)
e3a2b7ed 2803{
05866c82 2804 struct rhashtable *tc_ht = get_tc_ht(priv);
e3a2b7ed 2805 struct mlx5e_tc_flow *flow;
e3a2b7ed 2806
05866c82 2807 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 2808 if (!flow || !same_flow_direction(flow, flags))
e3a2b7ed
AV		 2809 return -EINVAL;
2810
05866c82 2811 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
e3a2b7ed 2812
961e8979 2813 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 2814
2815 kfree(flow);
2816
2817 return 0;
2818}
2819
71d82d2a 2820int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
60bd4af8 2821 struct tc_cls_flower_offload *f, int flags)
aad7e08d 2822{
05866c82 2823 struct rhashtable *tc_ht = get_tc_ht(priv);
aad7e08d 2824 struct mlx5e_tc_flow *flow;
aad7e08d
AV		 2825 struct mlx5_fc *counter;
2826 u64 bytes;
2827 u64 packets;
2828 u64 lastuse;
2829
05866c82 2830 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 2831 if (!flow || !same_flow_direction(flow, flags))
aad7e08d
AV		 2832 return -EINVAL;
2833
0b67a38f
HHZ		 2834 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
2835 return 0;
2836
b8aee822 2837 counter = mlx5e_tc_get_counter(flow);
aad7e08d
AV		 2838 if (!counter)
2839 return 0;
2840
2841 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
2842
d897a638 2843 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
fed06ee8 2844
aad7e08d
AV		 2845 return 0;
2846}
2847
4d8fcf21
AH		 2848static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
2849 struct mlx5e_priv *peer_priv)
2850{
2851 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
2852 struct mlx5e_hairpin_entry *hpe;
2853 u16 peer_vhca_id;
2854 int bkt;
2855
2856 if (!same_hw_devs(priv, peer_priv))
2857 return;
2858
2859 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
2860
2861 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) {
2862 if (hpe->peer_vhca_id == peer_vhca_id)
2863 hpe->hp->pair->peer_gone = true;
2864 }
2865}
2866
2867static int mlx5e_tc_netdev_event(struct notifier_block *this,
2868 unsigned long event, void *ptr)
2869{
2870 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
2871 struct mlx5e_flow_steering *fs;
2872 struct mlx5e_priv *peer_priv;
2873 struct mlx5e_tc_table *tc;
2874 struct mlx5e_priv *priv;
2875
2876 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
2877 event != NETDEV_UNREGISTER ||
2878 ndev->reg_state == NETREG_REGISTERED)
2879 return NOTIFY_DONE;
2880
2881 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
2882 fs = container_of(tc, struct mlx5e_flow_steering, tc);
2883 priv = container_of(fs, struct mlx5e_priv, fs);
2884 peer_priv = netdev_priv(ndev);
2885 if (priv == peer_priv ||
2886 !(priv->netdev->features & NETIF_F_HW_TC))
2887 return NOTIFY_DONE;
2888
2889 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
2890
2891 return NOTIFY_DONE;
2892}
2893
655dc3d2 2894int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 2895{
acff797c 2896 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 2897 int err;
e8f887ac 2898
11c9c548 2899 hash_init(tc->mod_hdr_tbl);
5c65c564 2900 hash_init(tc->hairpin_tbl);
11c9c548 2901
4d8fcf21
AH		 2902 err = rhashtable_init(&tc->ht, &tc_ht_params);
2903 if (err)
2904 return err;
2905
2906 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
2907 if (register_netdevice_notifier(&tc->netdevice_nb)) {
2908 tc->netdevice_nb.notifier_call = NULL;
2909 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
2910 }
2911
2912 return err;
e8f887ac
AV		 2913}
2914
2915static void _mlx5e_tc_del_flow(void *ptr, void *arg)
2916{
2917 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 2918 struct mlx5e_priv *priv = flow->priv;
e8f887ac 2919
961e8979 2920 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 2921 kfree(flow);
2922}
2923
655dc3d2 2924void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 2925{
acff797c 2926 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 2927
4d8fcf21
AH		 2928 if (tc->netdevice_nb.notifier_call)
2929 unregister_netdevice_notifier(&tc->netdevice_nb);
2930
655dc3d2 2931 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 2932
acff797c
MG		 2933 if (!IS_ERR_OR_NULL(tc->t)) {
2934 mlx5_destroy_flow_table(tc->t);
2935 tc->t = NULL;
e8f887ac
AV		 2936 }
2937}
655dc3d2
OG		 2938
2939int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
2940{
2941 return rhashtable_init(tc_ht, &tc_ht_params);
2942}
2943
2944void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
2945{
2946 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
2947}
01252a27
OG		 2948
2949int mlx5e_tc_num_filters(struct mlx5e_priv *priv)
2950{
2951 struct rhashtable *tc_ht = get_tc_ht(priv);
2952
2953 return atomic_read(&tc_ht->nelems);
2954}
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