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net/mlx5e: Enlarge the NIC TC offload steering prio to support two levels
[thirdparty/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG		 41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
a54e20b4 47#include <net/vxlan.h>
f6dfb4c3 48#include <net/arp.h>
e8f887ac 49#include "en.h"
1d447a39 50#include "en_rep.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
bbd00f7e 53#include "vxlan.h"
e8f887ac 54
3bc4b7bf
OG		 55struct mlx5_nic_flow_attr {
56 u32 action;
57 u32 flow_tag;
2f4fe4ca 58 u32 mod_hdr_id;
5c65c564 59 u32 hairpin_tirn;
3bc4b7bf
OG		 60};
61
65ba8fb7
OG		 62enum {
63 MLX5E_TC_FLOW_ESWITCH = BIT(0),
3bc4b7bf 64 MLX5E_TC_FLOW_NIC = BIT(1),
0b67a38f 65 MLX5E_TC_FLOW_OFFLOADED = BIT(2),
5c65c564 66 MLX5E_TC_FLOW_HAIRPIN = BIT(3),
65ba8fb7
OG		 67};
68
e8f887ac
AV		 69struct mlx5e_tc_flow {
70 struct rhash_head node;
71 u64 cookie;
65ba8fb7 72 u8 flags;
74491de9 73 struct mlx5_flow_handle *rule;
11c9c548
OG		 74 struct list_head encap; /* flows sharing the same encap ID */
75 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
5c65c564 76 struct list_head hairpin; /* flows sharing the same hairpin */
3bc4b7bf
OG		 77 union {
78 struct mlx5_esw_flow_attr esw_attr[0];
79 struct mlx5_nic_flow_attr nic_attr[0];
80 };
e8f887ac
AV		 81};
82
17091853 83struct mlx5e_tc_flow_parse_attr {
3c37745e 84 struct ip_tunnel_info tun_info;
17091853 85 struct mlx5_flow_spec spec;
d79b6df6
OG		 86 int num_mod_hdr_actions;
87 void *mod_hdr_actions;
3c37745e 88 int mirred_ifindex;
17091853
OG		 89};
90
a54e20b4
HHZ		 91enum {
92 MLX5_HEADER_TYPE_VXLAN = 0x0,
93 MLX5_HEADER_TYPE_NVGRE = 0x1,
94};
95
acff797c 96#define MLX5E_TC_TABLE_NUM_GROUPS 4
21b9c144 97#define MLX5E_TC_TABLE_MAX_GROUP_SIZE (1 << 16)
e8f887ac 98
77ab67b7
OG		 99struct mlx5e_hairpin {
100 struct mlx5_hairpin *pair;
101
102 struct mlx5_core_dev *func_mdev;
103 u32 tdn;
104 u32 tirn;
105};
106
5c65c564
OG		 107struct mlx5e_hairpin_entry {
108 /* a node of a hash table which keeps all the hairpin entries */
109 struct hlist_node hairpin_hlist;
110
111 /* flows sharing the same hairpin */
112 struct list_head flows;
113
d8822868 114 u16 peer_vhca_id;
106be53b 115 u8 prio;
5c65c564
OG		 116 struct mlx5e_hairpin *hp;
117};
118
11c9c548
OG		 119struct mod_hdr_key {
120 int num_actions;
121 void *actions;
122};
123
124struct mlx5e_mod_hdr_entry {
125 /* a node of a hash table which keeps all the mod_hdr entries */
126 struct hlist_node mod_hdr_hlist;
127
128 /* flows sharing the same mod_hdr entry */
129 struct list_head flows;
130
131 struct mod_hdr_key key;
132
133 u32 mod_hdr_id;
134};
135
136#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
137
138static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
139{
140 return jhash(key->actions,
141 key->num_actions * MLX5_MH_ACT_SZ, 0);
142}
143
144static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
145 struct mod_hdr_key *b)
146{
147 if (a->num_actions != b->num_actions)
148 return 1;
149
150 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
151}
152
153static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
154 struct mlx5e_tc_flow *flow,
155 struct mlx5e_tc_flow_parse_attr *parse_attr)
156{
157 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
158 int num_actions, actions_size, namespace, err;
159 struct mlx5e_mod_hdr_entry *mh;
160 struct mod_hdr_key key;
161 bool found = false;
162 u32 hash_key;
163
164 num_actions = parse_attr->num_mod_hdr_actions;
165 actions_size = MLX5_MH_ACT_SZ * num_actions;
166
167 key.actions = parse_attr->mod_hdr_actions;
168 key.num_actions = num_actions;
169
170 hash_key = hash_mod_hdr_info(&key);
171
172 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
173 namespace = MLX5_FLOW_NAMESPACE_FDB;
174 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
175 mod_hdr_hlist, hash_key) {
176 if (!cmp_mod_hdr_info(&mh->key, &key)) {
177 found = true;
178 break;
179 }
180 }
181 } else {
182 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
183 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
184 mod_hdr_hlist, hash_key) {
185 if (!cmp_mod_hdr_info(&mh->key, &key)) {
186 found = true;
187 break;
188 }
189 }
190 }
191
192 if (found)
193 goto attach_flow;
194
195 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
196 if (!mh)
197 return -ENOMEM;
198
199 mh->key.actions = (void *)mh + sizeof(*mh);
200 memcpy(mh->key.actions, key.actions, actions_size);
201 mh->key.num_actions = num_actions;
202 INIT_LIST_HEAD(&mh->flows);
203
204 err = mlx5_modify_header_alloc(priv->mdev, namespace,
205 mh->key.num_actions,
206 mh->key.actions,
207 &mh->mod_hdr_id);
208 if (err)
209 goto out_err;
210
211 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
212 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
213 else
214 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
215
216attach_flow:
217 list_add(&flow->mod_hdr, &mh->flows);
218 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
219 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
220 else
221 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
222
223 return 0;
224
225out_err:
226 kfree(mh);
227 return err;
228}
229
230static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
231 struct mlx5e_tc_flow *flow)
232{
233 struct list_head *next = flow->mod_hdr.next;
234
235 list_del(&flow->mod_hdr);
236
237 if (list_empty(next)) {
238 struct mlx5e_mod_hdr_entry *mh;
239
240 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
241
242 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
243 hash_del(&mh->mod_hdr_hlist);
244 kfree(mh);
245 }
246}
247
77ab67b7
OG		 248static
249struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
250{
251 struct net_device *netdev;
252 struct mlx5e_priv *priv;
253
254 netdev = __dev_get_by_index(net, ifindex);
255 priv = netdev_priv(netdev);
256 return priv->mdev;
257}
258
259static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
260{
261 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
262 void *tirc;
263 int err;
264
265 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
266 if (err)
267 goto alloc_tdn_err;
268
269 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
270
271 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
272 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn);
273 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
274
275 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
276 if (err)
277 goto create_tir_err;
278
279 return 0;
280
281create_tir_err:
282 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
283alloc_tdn_err:
284 return err;
285}
286
287static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
288{
289 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
290 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
291}
292
293static struct mlx5e_hairpin *
294mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
295 int peer_ifindex)
296{
297 struct mlx5_core_dev *func_mdev, *peer_mdev;
298 struct mlx5e_hairpin *hp;
299 struct mlx5_hairpin *pair;
300 int err;
301
302 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
303 if (!hp)
304 return ERR_PTR(-ENOMEM);
305
306 func_mdev = priv->mdev;
307 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
308
309 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
310 if (IS_ERR(pair)) {
311 err = PTR_ERR(pair);
312 goto create_pair_err;
313 }
314 hp->pair = pair;
315 hp->func_mdev = func_mdev;
316
317 err = mlx5e_hairpin_create_transport(hp);
318 if (err)
319 goto create_transport_err;
320
321 return hp;
322
323create_transport_err:
324 mlx5_core_hairpin_destroy(hp->pair);
325create_pair_err:
326 kfree(hp);
327 return ERR_PTR(err);
328}
329
330static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
331{
332 mlx5e_hairpin_destroy_transport(hp);
333 mlx5_core_hairpin_destroy(hp->pair);
334 kvfree(hp);
335}
336
106be53b
OG		 337static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
338{
339 return (peer_vhca_id << 16 | prio);
340}
341
5c65c564 342static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 343 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 344{
345 struct mlx5e_hairpin_entry *hpe;
106be53b 346 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 347
348 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b
OG		 349 hairpin_hlist, hash_key) {
350 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
5c65c564
OG		 351 return hpe;
352 }
353
354 return NULL;
355}
356
106be53b
OG		 357#define UNKNOWN_MATCH_PRIO 8
358
359static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
360 struct mlx5_flow_spec *spec, u8 *match_prio)
361{
362 void *headers_c, *headers_v;
363 u8 prio_val, prio_mask = 0;
364 bool vlan_present;
365
366#ifdef CONFIG_MLX5_CORE_EN_DCB
367 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
368 netdev_warn(priv->netdev,
369 "only PCP trust state supported for hairpin\n");
370 return -EOPNOTSUPP;
371 }
372#endif
373 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
374 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
375
376 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
377 if (vlan_present) {
378 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
379 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
380 }
381
382 if (!vlan_present || !prio_mask) {
383 prio_val = UNKNOWN_MATCH_PRIO;
384 } else if (prio_mask != 0x7) {
385 netdev_warn(priv->netdev,
386 "masked priority match not supported for hairpin\n");
387 return -EOPNOTSUPP;
388 }
389
390 *match_prio = prio_val;
391 return 0;
392}
393
5c65c564
OG		 394static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
395 struct mlx5e_tc_flow *flow,
396 struct mlx5e_tc_flow_parse_attr *parse_attr)
397{
398 int peer_ifindex = parse_attr->mirred_ifindex;
399 struct mlx5_hairpin_params params;
d8822868 400 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 401 struct mlx5e_hairpin_entry *hpe;
402 struct mlx5e_hairpin *hp;
106be53b 403 u8 match_prio;
d8822868 404 u16 peer_id;
5c65c564
OG		 405 int err;
406
d8822868
OG		 407 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
408 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
5c65c564
OG		 409 netdev_warn(priv->netdev, "hairpin is not supported\n");
410 return -EOPNOTSUPP;
411 }
412
d8822868 413 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
106be53b
OG		 414 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio);
415 if (err)
416 return err;
417 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 418 if (hpe)
419 goto attach_flow;
420
421 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
422 if (!hpe)
423 return -ENOMEM;
424
425 INIT_LIST_HEAD(&hpe->flows);
d8822868 426 hpe->peer_vhca_id = peer_id;
106be53b 427 hpe->prio = match_prio;
5c65c564
OG		 428
429 params.log_data_size = 15;
430 params.log_data_size = min_t(u8, params.log_data_size,
431 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
432 params.log_data_size = max_t(u8, params.log_data_size,
433 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
434 params.q_counter = priv->q_counter;
435
436 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
437 if (IS_ERR(hp)) {
438 err = PTR_ERR(hp);
439 goto create_hairpin_err;
440 }
441
106be53b 442 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d log data size %d\n",
5c65c564 443 hp->tirn, hp->pair->rqn, hp->pair->peer_mdev->priv.name,
106be53b 444 hp->pair->sqn, match_prio, params.log_data_size);
5c65c564
OG		 445
446 hpe->hp = hp;
106be53b
OG		 447 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
448 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 449
450attach_flow:
451 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
452 list_add(&flow->hairpin, &hpe->flows);
453 return 0;
454
455create_hairpin_err:
456 kfree(hpe);
457 return err;
458}
459
460static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
461 struct mlx5e_tc_flow *flow)
462{
463 struct list_head *next = flow->hairpin.next;
464
465 list_del(&flow->hairpin);
466
467 /* no more hairpin flows for us, release the hairpin pair */
468 if (list_empty(next)) {
469 struct mlx5e_hairpin_entry *hpe;
470
471 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
472
473 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
474 hpe->hp->pair->peer_mdev->priv.name);
475
476 mlx5e_hairpin_destroy(hpe->hp);
477 hash_del(&hpe->hairpin_hlist);
478 kfree(hpe);
479 }
480}
481
74491de9
MB		 482static struct mlx5_flow_handle *
483mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 484 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 485 struct mlx5e_tc_flow *flow)
e8f887ac 486{
aa0cbbae 487 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 488 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 489 struct mlx5_flow_destination dest[2] = {};
66958ed9 490 struct mlx5_flow_act flow_act = {
3bc4b7bf
OG		 491 .action = attr->action,
492 .flow_tag = attr->flow_tag,
66958ed9
HHZ		 493 .encap_id = 0,
494 };
aad7e08d 495 struct mlx5_fc *counter = NULL;
74491de9 496 struct mlx5_flow_handle *rule;
e8f887ac 497 bool table_created = false;
5c65c564 498 int err, dest_ix = 0;
e8f887ac 499
3bc4b7bf 500 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
5c65c564
OG		 501 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
502 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr);
503 if (err) {
504 rule = ERR_PTR(err);
505 goto err_add_hairpin_flow;
506 }
507 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
508 dest[dest_ix].tir_num = attr->hairpin_tirn;
509 } else {
510 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
511 dest[dest_ix].ft = priv->fs.vlan.ft.t;
512 }
513 dest_ix++;
514 }
aad7e08d 515
5c65c564
OG		 516 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
517 counter = mlx5_fc_create(dev, true);
518 if (IS_ERR(counter)) {
519 rule = ERR_CAST(counter);
520 goto err_fc_create;
521 }
522 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
523 dest[dest_ix].counter = counter;
524 dest_ix++;
aad7e08d
AV		 525 }
526
2f4fe4ca 527 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 528 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 529 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca
OG		 530 kfree(parse_attr->mod_hdr_actions);
531 if (err) {
532 rule = ERR_PTR(err);
533 goto err_create_mod_hdr_id;
534 }
535 }
536
acff797c 537 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 538 int tc_grp_size, tc_tbl_size;
539 u32 max_flow_counter;
540
541 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
542 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
543
544 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
545
546 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
547 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
548
acff797c
MG		 549 priv->fs.tc.t =
550 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
551 MLX5E_TC_PRIO,
21b9c144 552 tc_tbl_size,
acff797c 553 MLX5E_TC_TABLE_NUM_GROUPS,
c9f1b073 554 0, 0);
acff797c 555 if (IS_ERR(priv->fs.tc.t)) {
e8f887ac
AV		 556 netdev_err(priv->netdev,
557 "Failed to create tc offload table\n");
aad7e08d
AV		 558 rule = ERR_CAST(priv->fs.tc.t);
559 goto err_create_ft;
e8f887ac
AV		 560 }
561
562 table_created = true;
563 }
564
17091853
OG		 565 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
566 rule = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
5c65c564 567 &flow_act, dest, dest_ix);
aad7e08d
AV		 568
569 if (IS_ERR(rule))
570 goto err_add_rule;
571
572 return rule;
e8f887ac 573
aad7e08d
AV		 574err_add_rule:
575 if (table_created) {
acff797c
MG		 576 mlx5_destroy_flow_table(priv->fs.tc.t);
577 priv->fs.tc.t = NULL;
e8f887ac 578 }
aad7e08d 579err_create_ft:
2f4fe4ca 580 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 581 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 582err_create_mod_hdr_id:
aad7e08d 583 mlx5_fc_destroy(dev, counter);
5c65c564
OG		 584err_fc_create:
585 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
586 mlx5e_hairpin_flow_del(priv, flow);
587err_add_hairpin_flow:
e8f887ac
AV		 588 return rule;
589}
590
d85cdccb
OG		 591static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
592 struct mlx5e_tc_flow *flow)
593{
513f8f7f 594 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 595 struct mlx5_fc *counter = NULL;
596
aa0cbbae
OG		 597 counter = mlx5_flow_rule_counter(flow->rule);
598 mlx5_del_flow_rules(flow->rule);
599 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb
OG		 600
601 if (!mlx5e_tc_num_filters(priv) && (priv->fs.tc.t)) {
602 mlx5_destroy_flow_table(priv->fs.tc.t);
603 priv->fs.tc.t = NULL;
604 }
2f4fe4ca 605
513f8f7f 606 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 607 mlx5e_detach_mod_hdr(priv, flow);
5c65c564
OG		 608
609 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
610 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 611}
612
aa0cbbae
OG		 613static void mlx5e_detach_encap(struct mlx5e_priv *priv,
614 struct mlx5e_tc_flow *flow);
615
3c37745e
OG		 616static int mlx5e_attach_encap(struct mlx5e_priv *priv,
617 struct ip_tunnel_info *tun_info,
618 struct net_device *mirred_dev,
619 struct net_device **encap_dev,
620 struct mlx5e_tc_flow *flow);
621
74491de9
MB		 622static struct mlx5_flow_handle *
623mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 624 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 625 struct mlx5e_tc_flow *flow)
adb4c123
OG		 626{
627 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae 628 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3c37745e
OG		 629 struct net_device *out_dev, *encap_dev = NULL;
630 struct mlx5_flow_handle *rule = NULL;
631 struct mlx5e_rep_priv *rpriv;
632 struct mlx5e_priv *out_priv;
8b32580d
OG		 633 int err;
634
3c37745e
OG		 635 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
636 out_dev = __dev_get_by_index(dev_net(priv->netdev),
637 attr->parse_attr->mirred_ifindex);
638 err = mlx5e_attach_encap(priv, &parse_attr->tun_info,
639 out_dev, &encap_dev, flow);
640 if (err) {
641 rule = ERR_PTR(err);
642 if (err != -EAGAIN)
643 goto err_attach_encap;
644 }
645 out_priv = netdev_priv(encap_dev);
646 rpriv = out_priv->ppriv;
647 attr->out_rep = rpriv->rep;
648 }
649
8b32580d 650 err = mlx5_eswitch_add_vlan_action(esw, attr);
aa0cbbae
OG		 651 if (err) {
652 rule = ERR_PTR(err);
653 goto err_add_vlan;
654 }
adb4c123 655
d7e75a32 656 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 657 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32
OG		 658 kfree(parse_attr->mod_hdr_actions);
659 if (err) {
660 rule = ERR_PTR(err);
661 goto err_mod_hdr;
662 }
663 }
664
3c37745e
OG		 665 /* we get here if (1) there's no error (rule being null) or when
666 * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
667 */
668 if (rule != ERR_PTR(-EAGAIN)) {
669 rule = mlx5_eswitch_add_offloaded_rule(esw, &parse_attr->spec, attr);
670 if (IS_ERR(rule))
671 goto err_add_rule;
672 }
aa0cbbae
OG		 673 return rule;
674
675err_add_rule:
513f8f7f 676 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 677 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 678err_mod_hdr:
aa0cbbae
OG		 679 mlx5_eswitch_del_vlan_action(esw, attr);
680err_add_vlan:
681 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
682 mlx5e_detach_encap(priv, flow);
3c37745e 683err_attach_encap:
aa0cbbae
OG		 684 return rule;
685}
d85cdccb
OG		 686
687static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
688 struct mlx5e_tc_flow *flow)
689{
690 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 691 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
d85cdccb 692
232c0013
HHZ		 693 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
694 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
513f8f7f 695 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, attr);
232c0013 696 }
d85cdccb 697
513f8f7f 698 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 699
513f8f7f 700 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
d85cdccb 701 mlx5e_detach_encap(priv, flow);
513f8f7f 702 kvfree(attr->parse_attr);
232c0013 703 }
d7e75a32 704
513f8f7f 705 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 706 mlx5e_detach_mod_hdr(priv, flow);
d85cdccb
OG		 707}
708
232c0013
HHZ		 709void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
710 struct mlx5e_encap_entry *e)
711{
3c37745e
OG		 712 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
713 struct mlx5_esw_flow_attr *esw_attr;
232c0013
HHZ		 714 struct mlx5e_tc_flow *flow;
715 int err;
716
717 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
718 e->encap_size, e->encap_header,
719 &e->encap_id);
720 if (err) {
721 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
722 err);
723 return;
724 }
725 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 726 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013
HHZ		 727
728 list_for_each_entry(flow, &e->flows, encap) {
3c37745e
OG		 729 esw_attr = flow->esw_attr;
730 esw_attr->encap_id = e->encap_id;
731 flow->rule = mlx5_eswitch_add_offloaded_rule(esw, &esw_attr->parse_attr->spec, esw_attr);
232c0013
HHZ		 732 if (IS_ERR(flow->rule)) {
733 err = PTR_ERR(flow->rule);
734 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
735 err);
736 continue;
737 }
738 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
739 }
740}
741
742void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
743 struct mlx5e_encap_entry *e)
744{
3c37745e 745 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
232c0013 746 struct mlx5e_tc_flow *flow;
232c0013
HHZ		 747
748 list_for_each_entry(flow, &e->flows, encap) {
749 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
750 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
3c37745e 751 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, flow->esw_attr);
232c0013
HHZ		 752 }
753 }
754
755 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
756 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
757 mlx5_encap_dealloc(priv->mdev, e->encap_id);
758 }
759}
760
f6dfb4c3
HHZ		 761void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
762{
763 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
764 u64 bytes, packets, lastuse = 0;
765 struct mlx5e_tc_flow *flow;
766 struct mlx5e_encap_entry *e;
767 struct mlx5_fc *counter;
768 struct neigh_table *tbl;
769 bool neigh_used = false;
770 struct neighbour *n;
771
772 if (m_neigh->family == AF_INET)
773 tbl = &arp_tbl;
774#if IS_ENABLED(CONFIG_IPV6)
775 else if (m_neigh->family == AF_INET6)
776 tbl = ipv6_stub->nd_tbl;
777#endif
778 else
779 return;
780
781 list_for_each_entry(e, &nhe->encap_list, encap_list) {
782 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
783 continue;
784 list_for_each_entry(flow, &e->flows, encap) {
785 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
786 counter = mlx5_flow_rule_counter(flow->rule);
787 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
788 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
789 neigh_used = true;
790 break;
791 }
792 }
793 }
794 }
795
796 if (neigh_used) {
797 nhe->reported_lastuse = jiffies;
798
799 /* find the relevant neigh according to the cached device and
800 * dst ip pair
801 */
802 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
803 if (!n) {
804 WARN(1, "The neighbour already freed\n");
805 return;
806 }
807
808 neigh_event_send(n, NULL);
809 neigh_release(n);
810 }
811}
812
d85cdccb
OG		 813static void mlx5e_detach_encap(struct mlx5e_priv *priv,
814 struct mlx5e_tc_flow *flow)
815{
5067b602
RD		 816 struct list_head *next = flow->encap.next;
817
818 list_del(&flow->encap);
819 if (list_empty(next)) {
c1ae1152 820 struct mlx5e_encap_entry *e;
5067b602 821
c1ae1152 822 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 823 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
824
825 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
5067b602 826 mlx5_encap_dealloc(priv->mdev, e->encap_id);
232c0013 827
cdc5a7f3 828 hash_del_rcu(&e->encap_hlist);
232c0013 829 kfree(e->encap_header);
5067b602
RD		 830 kfree(e);
831 }
832}
833
e8f887ac 834static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 835 struct mlx5e_tc_flow *flow)
e8f887ac 836{
d85cdccb
OG		 837 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
838 mlx5e_tc_del_fdb_flow(priv, flow);
839 else
840 mlx5e_tc_del_nic_flow(priv, flow);
e8f887ac
AV		 841}
842
bbd00f7e
HHZ		 843static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
844 struct tc_cls_flower_offload *f)
845{
846 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
847 outer_headers);
848 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
849 outer_headers);
850 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
851 misc_parameters);
852 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
853 misc_parameters);
854
855 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
856 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
857
858 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
859 struct flow_dissector_key_keyid *key =
860 skb_flow_dissector_target(f->dissector,
861 FLOW_DISSECTOR_KEY_ENC_KEYID,
862 f->key);
863 struct flow_dissector_key_keyid *mask =
864 skb_flow_dissector_target(f->dissector,
865 FLOW_DISSECTOR_KEY_ENC_KEYID,
866 f->mask);
867 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
868 be32_to_cpu(mask->keyid));
869 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
870 be32_to_cpu(key->keyid));
871 }
872}
873
874static int parse_tunnel_attr(struct mlx5e_priv *priv,
875 struct mlx5_flow_spec *spec,
876 struct tc_cls_flower_offload *f)
877{
878 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
879 outer_headers);
880 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
881 outer_headers);
882
2e72eb43
OG		 883 struct flow_dissector_key_control *enc_control =
884 skb_flow_dissector_target(f->dissector,
885 FLOW_DISSECTOR_KEY_ENC_CONTROL,
886 f->key);
887
bbd00f7e
HHZ		 888 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
889 struct flow_dissector_key_ports *key =
890 skb_flow_dissector_target(f->dissector,
891 FLOW_DISSECTOR_KEY_ENC_PORTS,
892 f->key);
893 struct flow_dissector_key_ports *mask =
894 skb_flow_dissector_target(f->dissector,
895 FLOW_DISSECTOR_KEY_ENC_PORTS,
896 f->mask);
1ad9a00a 897 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a4b97ab4 898 struct mlx5e_rep_priv *uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
5ed99fb4 899 struct net_device *up_dev = uplink_rpriv->netdev;
1ad9a00a 900 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
bbd00f7e
HHZ		 901
902 /* Full udp dst port must be given */
903 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
2fcd82e9 904 goto vxlan_match_offload_err;
bbd00f7e 905
1ad9a00a 906 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->dst)) &&
bbd00f7e
HHZ		 907 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
908 parse_vxlan_attr(spec, f);
2fcd82e9
OG		 909 else {
910 netdev_warn(priv->netdev,
911 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
bbd00f7e 912 return -EOPNOTSUPP;
2fcd82e9 913 }
bbd00f7e
HHZ		 914
915 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
916 udp_dport, ntohs(mask->dst));
917 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
918 udp_dport, ntohs(key->dst));
919
cd377663
OG		 920 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
921 udp_sport, ntohs(mask->src));
922 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
923 udp_sport, ntohs(key->src));
bbd00f7e 924 } else { /* udp dst port must be given */
2fcd82e9
OG		 925vxlan_match_offload_err:
926 netdev_warn(priv->netdev,
927 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
928 return -EOPNOTSUPP;
bbd00f7e
HHZ		 929 }
930
2e72eb43 931 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ		 932 struct flow_dissector_key_ipv4_addrs *key =
933 skb_flow_dissector_target(f->dissector,
934 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
935 f->key);
936 struct flow_dissector_key_ipv4_addrs *mask =
937 skb_flow_dissector_target(f->dissector,
938 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
939 f->mask);
940 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
941 src_ipv4_src_ipv6.ipv4_layout.ipv4,
942 ntohl(mask->src));
943 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
944 src_ipv4_src_ipv6.ipv4_layout.ipv4,
945 ntohl(key->src));
946
947 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
948 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
949 ntohl(mask->dst));
950 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
951 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
952 ntohl(key->dst));
bbd00f7e 953
2e72eb43
OG		 954 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
955 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG		 956 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
957 struct flow_dissector_key_ipv6_addrs *key =
958 skb_flow_dissector_target(f->dissector,
959 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
960 f->key);
961 struct flow_dissector_key_ipv6_addrs *mask =
962 skb_flow_dissector_target(f->dissector,
963 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
964 f->mask);
965
966 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
967 src_ipv4_src_ipv6.ipv6_layout.ipv6),
968 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
969 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
970 src_ipv4_src_ipv6.ipv6_layout.ipv6),
971 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
972
973 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
974 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
975 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
976 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
977 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
978 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
979
980 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
981 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 982 }
bbd00f7e
HHZ		 983
984 /* Enforce DMAC when offloading incoming tunneled flows.
985 * Flow counters require a match on the DMAC.
986 */
987 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
988 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
989 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
990 dmac_47_16), priv->netdev->dev_addr);
991
992 /* let software handle IP fragments */
993 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
994 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
995
996 return 0;
997}
998
de0af0bf
RD		 999static int __parse_cls_flower(struct mlx5e_priv *priv,
1000 struct mlx5_flow_spec *spec,
1001 struct tc_cls_flower_offload *f,
1002 u8 *min_inline)
e3a2b7ed 1003{
c5bb1730
MG		 1004 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1005 outer_headers);
1006 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1007 outer_headers);
e3a2b7ed
AV		 1008 u16 addr_type = 0;
1009 u8 ip_proto = 0;
1010
de0af0bf
RD		 1011 *min_inline = MLX5_INLINE_MODE_L2;
1012
e3a2b7ed
AV		 1013 if (f->dissector->used_keys &
1014 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1015 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1016 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1017 BIT(FLOW_DISSECTOR_KEY_VLAN) |
e3a2b7ed
AV		 1018 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1019 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1020 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1021 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1022 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1023 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1024 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1025 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b
OG		 1026 BIT(FLOW_DISSECTOR_KEY_TCP) |
1027 BIT(FLOW_DISSECTOR_KEY_IP))) {
e3a2b7ed
AV		 1028 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1029 f->dissector->used_keys);
1030 return -EOPNOTSUPP;
1031 }
1032
bbd00f7e
HHZ		 1033 if ((dissector_uses_key(f->dissector,
1034 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1035 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1036 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1037 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1038 struct flow_dissector_key_control *key =
1039 skb_flow_dissector_target(f->dissector,
1040 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1041 f->key);
1042 switch (key->addr_type) {
1043 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 1044 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
bbd00f7e
HHZ		 1045 if (parse_tunnel_attr(priv, spec, f))
1046 return -EOPNOTSUPP;
1047 break;
1048 default:
1049 return -EOPNOTSUPP;
1050 }
1051
1052 /* In decap flow, header pointers should point to the inner
1053 * headers, outer header were already set by parse_tunnel_attr
1054 */
1055 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1056 inner_headers);
1057 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1058 inner_headers);
1059 }
1060
e3a2b7ed
AV		 1061 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
1062 struct flow_dissector_key_control *key =
1063 skb_flow_dissector_target(f->dissector,
1dbd0d37 1064 FLOW_DISSECTOR_KEY_CONTROL,
e3a2b7ed 1065 f->key);
3f7d0eb4
OG		 1066
1067 struct flow_dissector_key_control *mask =
1068 skb_flow_dissector_target(f->dissector,
1069 FLOW_DISSECTOR_KEY_CONTROL,
1070 f->mask);
e3a2b7ed 1071 addr_type = key->addr_type;
3f7d0eb4
OG		 1072
1073 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
1074 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1075 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1076 key->flags & FLOW_DIS_IS_FRAGMENT);
0827444d
OG		 1077
1078 /* the HW doesn't need L3 inline to match on frag=no */
1079 if (key->flags & FLOW_DIS_IS_FRAGMENT)
1080 *min_inline = MLX5_INLINE_MODE_IP;
3f7d0eb4 1081 }
e3a2b7ed
AV		 1082 }
1083
1084 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1085 struct flow_dissector_key_basic *key =
1086 skb_flow_dissector_target(f->dissector,
1087 FLOW_DISSECTOR_KEY_BASIC,
1088 f->key);
1089 struct flow_dissector_key_basic *mask =
1090 skb_flow_dissector_target(f->dissector,
1091 FLOW_DISSECTOR_KEY_BASIC,
1092 f->mask);
1093 ip_proto = key->ip_proto;
1094
1095 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1096 ntohs(mask->n_proto));
1097 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1098 ntohs(key->n_proto));
1099
1100 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1101 mask->ip_proto);
1102 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1103 key->ip_proto);
de0af0bf
RD		 1104
1105 if (mask->ip_proto)
1106 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 1107 }
1108
1109 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1110 struct flow_dissector_key_eth_addrs *key =
1111 skb_flow_dissector_target(f->dissector,
1112 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1113 f->key);
1114 struct flow_dissector_key_eth_addrs *mask =
1115 skb_flow_dissector_target(f->dissector,
1116 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1117 f->mask);
1118
1119 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1120 dmac_47_16),
1121 mask->dst);
1122 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1123 dmac_47_16),
1124 key->dst);
1125
1126 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1127 smac_47_16),
1128 mask->src);
1129 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1130 smac_47_16),
1131 key->src);
1132 }
1133
095b6cfd
OG		 1134 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
1135 struct flow_dissector_key_vlan *key =
1136 skb_flow_dissector_target(f->dissector,
1137 FLOW_DISSECTOR_KEY_VLAN,
1138 f->key);
1139 struct flow_dissector_key_vlan *mask =
1140 skb_flow_dissector_target(f->dissector,
1141 FLOW_DISSECTOR_KEY_VLAN,
1142 f->mask);
358d79a4 1143 if (mask->vlan_id || mask->vlan_priority) {
10543365
MHY		 1144 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
1145 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
095b6cfd
OG		 1146
1147 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
1148 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG		 1149
1150 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
1151 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
095b6cfd
OG		 1152 }
1153 }
1154
e3a2b7ed
AV		 1155 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1156 struct flow_dissector_key_ipv4_addrs *key =
1157 skb_flow_dissector_target(f->dissector,
1158 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1159 f->key);
1160 struct flow_dissector_key_ipv4_addrs *mask =
1161 skb_flow_dissector_target(f->dissector,
1162 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1163 f->mask);
1164
1165 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1166 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1167 &mask->src, sizeof(mask->src));
1168 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1169 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1170 &key->src, sizeof(key->src));
1171 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1172 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1173 &mask->dst, sizeof(mask->dst));
1174 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1175 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1176 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1177
1178 if (mask->src || mask->dst)
1179 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 1180 }
1181
1182 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1183 struct flow_dissector_key_ipv6_addrs *key =
1184 skb_flow_dissector_target(f->dissector,
1185 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1186 f->key);
1187 struct flow_dissector_key_ipv6_addrs *mask =
1188 skb_flow_dissector_target(f->dissector,
1189 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1190 f->mask);
1191
1192 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1193 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1194 &mask->src, sizeof(mask->src));
1195 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1196 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1197 &key->src, sizeof(key->src));
1198
1199 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1200 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1201 &mask->dst, sizeof(mask->dst));
1202 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1203 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1204 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1205
1206 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
1207 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
1208 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 1209 }
1210
1f97a526
OG		 1211 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
1212 struct flow_dissector_key_ip *key =
1213 skb_flow_dissector_target(f->dissector,
1214 FLOW_DISSECTOR_KEY_IP,
1215 f->key);
1216 struct flow_dissector_key_ip *mask =
1217 skb_flow_dissector_target(f->dissector,
1218 FLOW_DISSECTOR_KEY_IP,
1219 f->mask);
1220
1221 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1222 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1223
1224 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1225 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1226
a8ade55f
OG		 1227 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1228 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1f97a526 1229
a8ade55f
OG		 1230 if (mask->ttl &&
1231 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
1232 ft_field_support.outer_ipv4_ttl))
1f97a526 1233 return -EOPNOTSUPP;
a8ade55f
OG		 1234
1235 if (mask->tos || mask->ttl)
1236 *min_inline = MLX5_INLINE_MODE_IP;
1f97a526
OG		 1237 }
1238
e3a2b7ed
AV		 1239 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
1240 struct flow_dissector_key_ports *key =
1241 skb_flow_dissector_target(f->dissector,
1242 FLOW_DISSECTOR_KEY_PORTS,
1243 f->key);
1244 struct flow_dissector_key_ports *mask =
1245 skb_flow_dissector_target(f->dissector,
1246 FLOW_DISSECTOR_KEY_PORTS,
1247 f->mask);
1248 switch (ip_proto) {
1249 case IPPROTO_TCP:
1250 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1251 tcp_sport, ntohs(mask->src));
1252 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1253 tcp_sport, ntohs(key->src));
1254
1255 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1256 tcp_dport, ntohs(mask->dst));
1257 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1258 tcp_dport, ntohs(key->dst));
1259 break;
1260
1261 case IPPROTO_UDP:
1262 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1263 udp_sport, ntohs(mask->src));
1264 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1265 udp_sport, ntohs(key->src));
1266
1267 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1268 udp_dport, ntohs(mask->dst));
1269 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1270 udp_dport, ntohs(key->dst));
1271 break;
1272 default:
1273 netdev_err(priv->netdev,
1274 "Only UDP and TCP transport are supported\n");
1275 return -EINVAL;
1276 }
de0af0bf
RD		 1277
1278 if (mask->src || mask->dst)
1279 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
e3a2b7ed
AV		 1280 }
1281
e77834ec
OG		 1282 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
1283 struct flow_dissector_key_tcp *key =
1284 skb_flow_dissector_target(f->dissector,
1285 FLOW_DISSECTOR_KEY_TCP,
1286 f->key);
1287 struct flow_dissector_key_tcp *mask =
1288 skb_flow_dissector_target(f->dissector,
1289 FLOW_DISSECTOR_KEY_TCP,
1290 f->mask);
1291
1292 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1293 ntohs(mask->flags));
1294 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1295 ntohs(key->flags));
1296
1297 if (mask->flags)
1298 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
1299 }
1300
e3a2b7ed
AV		 1301 return 0;
1302}
1303
de0af0bf 1304static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1305 struct mlx5e_tc_flow *flow,
de0af0bf
RD		 1306 struct mlx5_flow_spec *spec,
1307 struct tc_cls_flower_offload *f)
1308{
1309 struct mlx5_core_dev *dev = priv->mdev;
1310 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 1311 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1312 struct mlx5_eswitch_rep *rep;
de0af0bf
RD		 1313 u8 min_inline;
1314 int err;
1315
1316 err = __parse_cls_flower(priv, spec, f, &min_inline);
1317
1d447a39
SM		 1318 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1319 rep = rpriv->rep;
1320 if (rep->vport != FDB_UPLINK_VPORT &&
1321 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
1322 esw->offloads.inline_mode < min_inline)) {
de0af0bf
RD		 1323 netdev_warn(priv->netdev,
1324 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
1325 min_inline, esw->offloads.inline_mode);
1326 return -EOPNOTSUPP;
1327 }
1328 }
1329
1330 return err;
1331}
1332
d79b6df6
OG		 1333struct pedit_headers {
1334 struct ethhdr eth;
1335 struct iphdr ip4;
1336 struct ipv6hdr ip6;
1337 struct tcphdr tcp;
1338 struct udphdr udp;
1339};
1340
1341static int pedit_header_offsets[] = {
1342 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1343 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1344 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1345 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1346 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1347};
1348
1349#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1350
1351static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1352 struct pedit_headers *masks,
1353 struct pedit_headers *vals)
1354{
1355 u32 *curr_pmask, *curr_pval;
1356
1357 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1358 goto out_err;
1359
1360 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1361 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1362
1363 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1364 goto out_err;
1365
1366 *curr_pmask |= mask;
1367 *curr_pval |= (val & mask);
1368
1369 return 0;
1370
1371out_err:
1372 return -EOPNOTSUPP;
1373}
1374
1375struct mlx5_fields {
1376 u8 field;
1377 u8 size;
1378 u32 offset;
1379};
1380
a8e4f0c4
OG		 1381#define OFFLOAD(fw_field, size, field, off) \
1382 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1383
d79b6df6 1384static struct mlx5_fields fields[] = {
a8e4f0c4
OG		 1385 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1386 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1387 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1388 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1389 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1390 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
1391
1392 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1393 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1394 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1395
1396 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1397 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1398 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1399 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1400 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1401 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1402 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1403 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
0c0316f5 1404 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
a8e4f0c4
OG		 1405
1406 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1407 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1408 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1409
1410 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1411 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
d79b6df6
OG		 1412};
1413
1414/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1415 * max from the SW pedit action. On success, it says how many HW actions were
1416 * actually parsed.
1417 */
1418static int offload_pedit_fields(struct pedit_headers *masks,
1419 struct pedit_headers *vals,
1420 struct mlx5e_tc_flow_parse_attr *parse_attr)
1421{
1422 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 1423 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 1424 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1425 struct mlx5_fields *f;
1426 u8 cmd, field_bsize;
e3ca4e05 1427 u32 s_mask, a_mask;
d79b6df6 1428 unsigned long mask;
2b64beba
OG		 1429 __be32 mask_be32;
1430 __be16 mask_be16;
d79b6df6
OG		 1431 void *action;
1432
1433 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1434 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1435 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1436 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1437
1438 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1439 action = parse_attr->mod_hdr_actions;
1440 max_actions = parse_attr->num_mod_hdr_actions;
1441 nactions = 0;
1442
1443 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1444 f = &fields[i];
1445 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 1446 s_mask = 0;
1447 a_mask = 0;
d79b6df6
OG		 1448
1449 s_masks_p = (void *)set_masks + f->offset;
1450 a_masks_p = (void *)add_masks + f->offset;
1451
1452 memcpy(&s_mask, s_masks_p, f->size);
1453 memcpy(&a_mask, a_masks_p, f->size);
1454
1455 if (!s_mask && !a_mask) /* nothing to offload here */
1456 continue;
1457
1458 if (s_mask && a_mask) {
1459 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1460 return -EOPNOTSUPP;
1461 }
1462
1463 if (nactions == max_actions) {
1464 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1465 return -EOPNOTSUPP;
1466 }
1467
1468 if (s_mask) {
1469 cmd = MLX5_ACTION_TYPE_SET;
1470 mask = s_mask;
1471 vals_p = (void *)set_vals + f->offset;
1472 /* clear to denote we consumed this field */
1473 memset(s_masks_p, 0, f->size);
1474 } else {
1475 cmd = MLX5_ACTION_TYPE_ADD;
1476 mask = a_mask;
1477 vals_p = (void *)add_vals + f->offset;
1478 /* clear to denote we consumed this field */
1479 memset(a_masks_p, 0, f->size);
1480 }
1481
d79b6df6 1482 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 1483
2b64beba
OG		 1484 if (field_bsize == 32) {
1485 mask_be32 = *(__be32 *)&mask;
1486 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1487 } else if (field_bsize == 16) {
1488 mask_be16 = *(__be16 *)&mask;
1489 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1490 }
1491
d79b6df6 1492 first = find_first_bit(&mask, field_bsize);
2b64beba 1493 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 1494 last = find_last_bit(&mask, field_bsize);
2b64beba
OG		 1495 if (first < next_z && next_z < last) {
1496 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 1497 mask);
1498 return -EOPNOTSUPP;
1499 }
1500
1501 MLX5_SET(set_action_in, action, action_type, cmd);
1502 MLX5_SET(set_action_in, action, field, f->field);
1503
1504 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 1505 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 1506 /* length is num of bits to be written, zero means length of 32 */
2b64beba 1507 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 1508 }
1509
1510 if (field_bsize == 32)
2b64beba 1511 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 1512 else if (field_bsize == 16)
2b64beba 1513 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 1514 else if (field_bsize == 8)
2b64beba 1515 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 1516
1517 action += action_size;
1518 nactions++;
1519 }
1520
1521 parse_attr->num_mod_hdr_actions = nactions;
1522 return 0;
1523}
1524
1525static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
1526 const struct tc_action *a, int namespace,
1527 struct mlx5e_tc_flow_parse_attr *parse_attr)
1528{
1529 int nkeys, action_size, max_actions;
1530
1531 nkeys = tcf_pedit_nkeys(a);
1532 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1533
1534 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
1535 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
1536 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
1537 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
1538
1539 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
1540 max_actions = min(max_actions, nkeys * 16);
1541
1542 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
1543 if (!parse_attr->mod_hdr_actions)
1544 return -ENOMEM;
1545
1546 parse_attr->num_mod_hdr_actions = max_actions;
1547 return 0;
1548}
1549
1550static const struct pedit_headers zero_masks = {};
1551
1552static int parse_tc_pedit_action(struct mlx5e_priv *priv,
1553 const struct tc_action *a, int namespace,
1554 struct mlx5e_tc_flow_parse_attr *parse_attr)
1555{
1556 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
1557 int nkeys, i, err = -EOPNOTSUPP;
1558 u32 mask, val, offset;
1559 u8 cmd, htype;
1560
1561 nkeys = tcf_pedit_nkeys(a);
1562
1563 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1564 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1565
1566 for (i = 0; i < nkeys; i++) {
1567 htype = tcf_pedit_htype(a, i);
1568 cmd = tcf_pedit_cmd(a, i);
1569 err = -EOPNOTSUPP; /* can't be all optimistic */
1570
1571 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
1572 printk(KERN_WARNING "mlx5: legacy pedit isn't offloaded\n");
1573 goto out_err;
1574 }
1575
1576 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
1577 printk(KERN_WARNING "mlx5: pedit cmd %d isn't offloaded\n", cmd);
1578 goto out_err;
1579 }
1580
1581 mask = tcf_pedit_mask(a, i);
1582 val = tcf_pedit_val(a, i);
1583 offset = tcf_pedit_offset(a, i);
1584
1585 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
1586 if (err)
1587 goto out_err;
1588 }
1589
1590 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
1591 if (err)
1592 goto out_err;
1593
1594 err = offload_pedit_fields(masks, vals, parse_attr);
1595 if (err < 0)
1596 goto out_dealloc_parsed_actions;
1597
1598 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
1599 cmd_masks = &masks[cmd];
1600 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
1601 printk(KERN_WARNING "mlx5: attempt to offload an unsupported field (cmd %d)\n",
1602 cmd);
1603 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
1604 16, 1, cmd_masks, sizeof(zero_masks), true);
1605 err = -EOPNOTSUPP;
1606 goto out_dealloc_parsed_actions;
1607 }
1608 }
1609
1610 return 0;
1611
1612out_dealloc_parsed_actions:
1613 kfree(parse_attr->mod_hdr_actions);
1614out_err:
1615 return err;
1616}
1617
26c02749
OG		 1618static bool csum_offload_supported(struct mlx5e_priv *priv, u32 action, u32 update_flags)
1619{
1620 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
1621 TCA_CSUM_UPDATE_FLAG_UDP;
1622
1623 /* The HW recalcs checksums only if re-writing headers */
1624 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
1625 netdev_warn(priv->netdev,
1626 "TC csum action is only offloaded with pedit\n");
1627 return false;
1628 }
1629
1630 if (update_flags & ~prot_flags) {
1631 netdev_warn(priv->netdev,
1632 "can't offload TC csum action for some header/s - flags %#x\n",
1633 update_flags);
1634 return false;
1635 }
1636
1637 return true;
1638}
1639
bdd66ac0
OG		 1640static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
1641 struct tcf_exts *exts)
1642{
1643 const struct tc_action *a;
1644 bool modify_ip_header;
1645 LIST_HEAD(actions);
1646 u8 htype, ip_proto;
1647 void *headers_v;
1648 u16 ethertype;
1649 int nkeys, i;
1650
1651 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1652 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1653
1654 /* for non-IP we only re-write MACs, so we're okay */
1655 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
1656 goto out_ok;
1657
1658 modify_ip_header = false;
1659 tcf_exts_to_list(exts, &actions);
1660 list_for_each_entry(a, &actions, list) {
1661 if (!is_tcf_pedit(a))
1662 continue;
1663
1664 nkeys = tcf_pedit_nkeys(a);
1665 for (i = 0; i < nkeys; i++) {
1666 htype = tcf_pedit_htype(a, i);
1667 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
1668 htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
1669 modify_ip_header = true;
1670 break;
1671 }
1672 }
1673 }
1674
1675 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1676 if (modify_ip_header && ip_proto != IPPROTO_TCP && ip_proto != IPPROTO_UDP) {
1677 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
1678 return false;
1679 }
1680
1681out_ok:
1682 return true;
1683}
1684
1685static bool actions_match_supported(struct mlx5e_priv *priv,
1686 struct tcf_exts *exts,
1687 struct mlx5e_tc_flow_parse_attr *parse_attr,
1688 struct mlx5e_tc_flow *flow)
1689{
1690 u32 actions;
1691
1692 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1693 actions = flow->esw_attr->action;
1694 else
1695 actions = flow->nic_attr->action;
1696
1697 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1698 return modify_header_match_supported(&parse_attr->spec, exts);
1699
1700 return true;
1701}
1702
5c65c564
OG		 1703static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
1704{
1705 struct mlx5_core_dev *fmdev, *pmdev;
1706 u16 func_id, peer_id;
1707
1708 fmdev = priv->mdev;
1709 pmdev = peer_priv->mdev;
1710
1711 func_id = (u16)((fmdev->pdev->bus->number << 8) | PCI_SLOT(fmdev->pdev->devfn));
1712 peer_id = (u16)((pmdev->pdev->bus->number << 8) | PCI_SLOT(pmdev->pdev->devfn));
1713
1714 return (func_id == peer_id);
1715}
1716
5c40348c 1717static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae
OG		 1718 struct mlx5e_tc_flow_parse_attr *parse_attr,
1719 struct mlx5e_tc_flow *flow)
e3a2b7ed 1720{
aa0cbbae 1721 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 1722 const struct tc_action *a;
22dc13c8 1723 LIST_HEAD(actions);
2f4fe4ca 1724 int err;
e3a2b7ed 1725
3bcc0cec 1726 if (!tcf_exts_has_actions(exts))
e3a2b7ed
AV		 1727 return -EINVAL;
1728
3bc4b7bf
OG		 1729 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
1730 attr->action = 0;
e3a2b7ed 1731
22dc13c8
WC		 1732 tcf_exts_to_list(exts, &actions);
1733 list_for_each_entry(a, &actions, list) {
e3a2b7ed 1734 if (is_tcf_gact_shot(a)) {
3bc4b7bf 1735 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 1736 if (MLX5_CAP_FLOWTABLE(priv->mdev,
1737 flow_table_properties_nic_receive.flow_counter))
3bc4b7bf 1738 attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV		 1739 continue;
1740 }
1741
2f4fe4ca
OG		 1742 if (is_tcf_pedit(a)) {
1743 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
1744 parse_attr);
1745 if (err)
1746 return err;
1747
1748 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
1749 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1750 continue;
1751 }
1752
26c02749
OG		 1753 if (is_tcf_csum(a)) {
1754 if (csum_offload_supported(priv, attr->action,
1755 tcf_csum_update_flags(a)))
1756 continue;
1757
1758 return -EOPNOTSUPP;
1759 }
1760
5c65c564
OG		 1761 if (is_tcf_mirred_egress_redirect(a)) {
1762 struct net_device *peer_dev = tcf_mirred_dev(a);
1763
1764 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
1765 same_hw_devs(priv, netdev_priv(peer_dev))) {
1766 parse_attr->mirred_ifindex = peer_dev->ifindex;
1767 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
1768 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1769 MLX5_FLOW_CONTEXT_ACTION_COUNT;
1770 } else {
1771 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
1772 peer_dev->name);
1773 return -EINVAL;
1774 }
1775 continue;
1776 }
1777
e3a2b7ed
AV		 1778 if (is_tcf_skbedit_mark(a)) {
1779 u32 mark = tcf_skbedit_mark(a);
1780
1781 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
1782 netdev_warn(priv->netdev, "Bad flow mark - only 16 bit is supported: 0x%x\n",
1783 mark);
1784 return -EINVAL;
1785 }
1786
3bc4b7bf
OG		 1787 attr->flow_tag = mark;
1788 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV		 1789 continue;
1790 }
1791
1792 return -EINVAL;
1793 }
1794
bdd66ac0
OG		 1795 if (!actions_match_supported(priv, exts, parse_attr, flow))
1796 return -EOPNOTSUPP;
1797
e3a2b7ed
AV		 1798 return 0;
1799}
1800
76f7444d
OG		 1801static inline int cmp_encap_info(struct ip_tunnel_key *a,
1802 struct ip_tunnel_key *b)
a54e20b4
HHZ		 1803{
1804 return memcmp(a, b, sizeof(*a));
1805}
1806
76f7444d 1807static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 1808{
76f7444d 1809 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 1810}
1811
1812static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
1813 struct net_device *mirred_dev,
1814 struct net_device **out_dev,
1815 struct flowi4 *fl4,
1816 struct neighbour **out_n,
a54e20b4
HHZ		 1817 int *out_ttl)
1818{
3e621b19 1819 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5ed99fb4 1820 struct mlx5e_rep_priv *uplink_rpriv;
a54e20b4
HHZ		 1821 struct rtable *rt;
1822 struct neighbour *n = NULL;
a54e20b4
HHZ		 1823
1824#if IS_ENABLED(CONFIG_INET)
abeffce9
AB		 1825 int ret;
1826
a54e20b4 1827 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
abeffce9
AB		 1828 ret = PTR_ERR_OR_ZERO(rt);
1829 if (ret)
1830 return ret;
a54e20b4
HHZ		 1831#else
1832 return -EOPNOTSUPP;
1833#endif
a4b97ab4 1834 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3e621b19
HHZ		 1835 /* if the egress device isn't on the same HW e-switch, we use the uplink */
1836 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
5ed99fb4 1837 *out_dev = uplink_rpriv->netdev;
3e621b19
HHZ		 1838 else
1839 *out_dev = rt->dst.dev;
a54e20b4 1840
75c33da8 1841 *out_ttl = ip4_dst_hoplimit(&rt->dst);
a54e20b4
HHZ		 1842 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
1843 ip_rt_put(rt);
1844 if (!n)
1845 return -ENOMEM;
1846
1847 *out_n = n;
a54e20b4
HHZ		 1848 return 0;
1849}
1850
ce99f6b9
OG		 1851static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
1852 struct net_device *mirred_dev,
1853 struct net_device **out_dev,
1854 struct flowi6 *fl6,
1855 struct neighbour **out_n,
1856 int *out_ttl)
1857{
1858 struct neighbour *n = NULL;
1859 struct dst_entry *dst;
1860
1861#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
74bd5d56 1862 struct mlx5e_rep_priv *uplink_rpriv;
ce99f6b9
OG		 1863 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1864 int ret;
1865
08820528
PB		 1866 ret = ipv6_stub->ipv6_dst_lookup(dev_net(mirred_dev), NULL, &dst,
1867 fl6);
1868 if (ret < 0)
ce99f6b9 1869 return ret;
ce99f6b9
OG		 1870
1871 *out_ttl = ip6_dst_hoplimit(dst);
1872
a4b97ab4 1873 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ce99f6b9
OG		 1874 /* if the egress device isn't on the same HW e-switch, we use the uplink */
1875 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
5ed99fb4 1876 *out_dev = uplink_rpriv->netdev;
ce99f6b9
OG		 1877 else
1878 *out_dev = dst->dev;
1879#else
1880 return -EOPNOTSUPP;
1881#endif
1882
1883 n = dst_neigh_lookup(dst, &fl6->daddr);
1884 dst_release(dst);
1885 if (!n)
1886 return -ENOMEM;
1887
1888 *out_n = n;
1889 return 0;
1890}
1891
32f3671f
OG		 1892static void gen_vxlan_header_ipv4(struct net_device *out_dev,
1893 char buf[], int encap_size,
1894 unsigned char h_dest[ETH_ALEN],
1895 int ttl,
1896 __be32 daddr,
1897 __be32 saddr,
1898 __be16 udp_dst_port,
1899 __be32 vx_vni)
a54e20b4 1900{
a54e20b4
HHZ		 1901 struct ethhdr *eth = (struct ethhdr *)buf;
1902 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
1903 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
1904 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
1905
1906 memset(buf, 0, encap_size);
1907
1908 ether_addr_copy(eth->h_dest, h_dest);
1909 ether_addr_copy(eth->h_source, out_dev->dev_addr);
1910 eth->h_proto = htons(ETH_P_IP);
1911
1912 ip->daddr = daddr;
1913 ip->saddr = saddr;
1914
1915 ip->ttl = ttl;
1916 ip->protocol = IPPROTO_UDP;
1917 ip->version = 0x4;
1918 ip->ihl = 0x5;
1919
1920 udp->dest = udp_dst_port;
1921 vxh->vx_flags = VXLAN_HF_VNI;
1922 vxh->vx_vni = vxlan_vni_field(vx_vni);
a54e20b4
HHZ		 1923}
1924
225aabaf
OG		 1925static void gen_vxlan_header_ipv6(struct net_device *out_dev,
1926 char buf[], int encap_size,
1927 unsigned char h_dest[ETH_ALEN],
1928 int ttl,
1929 struct in6_addr *daddr,
1930 struct in6_addr *saddr,
1931 __be16 udp_dst_port,
1932 __be32 vx_vni)
ce99f6b9 1933{
ce99f6b9
OG		 1934 struct ethhdr *eth = (struct ethhdr *)buf;
1935 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
1936 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
1937 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
1938
1939 memset(buf, 0, encap_size);
1940
1941 ether_addr_copy(eth->h_dest, h_dest);
1942 ether_addr_copy(eth->h_source, out_dev->dev_addr);
1943 eth->h_proto = htons(ETH_P_IPV6);
1944
1945 ip6_flow_hdr(ip6h, 0, 0);
1946 /* the HW fills up ipv6 payload len */
1947 ip6h->nexthdr = IPPROTO_UDP;
1948 ip6h->hop_limit = ttl;
1949 ip6h->daddr = *daddr;
1950 ip6h->saddr = *saddr;
1951
1952 udp->dest = udp_dst_port;
1953 vxh->vx_flags = VXLAN_HF_VNI;
1954 vxh->vx_vni = vxlan_vni_field(vx_vni);
ce99f6b9
OG		 1955}
1956
a54e20b4
HHZ		 1957static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
1958 struct net_device *mirred_dev,
1a8552bd 1959 struct mlx5e_encap_entry *e)
a54e20b4
HHZ		 1960{
1961 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
32f3671f 1962 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
76f7444d 1963 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 1964 struct net_device *out_dev;
a42485eb 1965 struct neighbour *n = NULL;
a54e20b4 1966 struct flowi4 fl4 = {};
a54e20b4 1967 char *encap_header;
32f3671f 1968 int ttl, err;
033354d5 1969 u8 nud_state;
32f3671f
OG		 1970
1971 if (max_encap_size < ipv4_encap_size) {
1972 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
1973 ipv4_encap_size, max_encap_size);
1974 return -EOPNOTSUPP;
1975 }
a54e20b4 1976
32f3671f 1977 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
a54e20b4
HHZ		 1978 if (!encap_header)
1979 return -ENOMEM;
1980
1981 switch (e->tunnel_type) {
1982 case MLX5_HEADER_TYPE_VXLAN:
1983 fl4.flowi4_proto = IPPROTO_UDP;
76f7444d 1984 fl4.fl4_dport = tun_key->tp_dst;
a54e20b4
HHZ		 1985 break;
1986 default:
1987 err = -EOPNOTSUPP;
ace74321 1988 goto free_encap;
a54e20b4 1989 }
9a941117 1990 fl4.flowi4_tos = tun_key->tos;
76f7444d 1991 fl4.daddr = tun_key->u.ipv4.dst;
9a941117 1992 fl4.saddr = tun_key->u.ipv4.src;
a54e20b4 1993
1a8552bd 1994 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
9a941117 1995 &fl4, &n, &ttl);
a54e20b4 1996 if (err)
ace74321 1997 goto free_encap;
a54e20b4 1998
232c0013
HHZ		 1999 /* used by mlx5e_detach_encap to lookup a neigh hash table
2000 * entry in the neigh hash table when a user deletes a rule
2001 */
2002 e->m_neigh.dev = n->dev;
f6dfb4c3 2003 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 2004 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2005 e->out_dev = out_dev;
2006
2007 /* It's importent to add the neigh to the hash table before checking
2008 * the neigh validity state. So if we'll get a notification, in case the
2009 * neigh changes it's validity state, we would find the relevant neigh
2010 * in the hash.
2011 */
2012 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2013 if (err)
ace74321 2014 goto free_encap;
232c0013 2015
033354d5
HHZ		 2016 read_lock_bh(&n->lock);
2017 nud_state = n->nud_state;
2018 ether_addr_copy(e->h_dest, n->ha);
2019 read_unlock_bh(&n->lock);
2020
a54e20b4
HHZ		 2021 switch (e->tunnel_type) {
2022 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 2023 gen_vxlan_header_ipv4(out_dev, encap_header,
32f3671f
OG		 2024 ipv4_encap_size, e->h_dest, ttl,
2025 fl4.daddr,
2026 fl4.saddr, tun_key->tp_dst,
2027 tunnel_id_to_key32(tun_key->tun_id));
a54e20b4
HHZ		 2028 break;
2029 default:
2030 err = -EOPNOTSUPP;
232c0013
HHZ		 2031 goto destroy_neigh_entry;
2032 }
2033 e->encap_size = ipv4_encap_size;
2034 e->encap_header = encap_header;
2035
2036 if (!(nud_state & NUD_VALID)) {
2037 neigh_event_send(n, NULL);
27902f08
WY		 2038 err = -EAGAIN;
2039 goto out;
a54e20b4
HHZ		 2040 }
2041
2042 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
32f3671f 2043 ipv4_encap_size, encap_header, &e->encap_id);
232c0013
HHZ		 2044 if (err)
2045 goto destroy_neigh_entry;
2046
2047 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 2048 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 2049 neigh_release(n);
2050 return err;
2051
2052destroy_neigh_entry:
2053 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 2054free_encap:
a54e20b4 2055 kfree(encap_header);
ace74321 2056out:
232c0013
HHZ		 2057 if (n)
2058 neigh_release(n);
a54e20b4
HHZ		 2059 return err;
2060}
2061
ce99f6b9
OG		 2062static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
2063 struct net_device *mirred_dev,
1a8552bd 2064 struct mlx5e_encap_entry *e)
ce99f6b9
OG		 2065{
2066 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
225aabaf 2067 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
ce99f6b9 2068 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 2069 struct net_device *out_dev;
ce99f6b9
OG		 2070 struct neighbour *n = NULL;
2071 struct flowi6 fl6 = {};
2072 char *encap_header;
225aabaf 2073 int err, ttl = 0;
033354d5 2074 u8 nud_state;
ce99f6b9 2075
225aabaf
OG		 2076 if (max_encap_size < ipv6_encap_size) {
2077 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2078 ipv6_encap_size, max_encap_size);
2079 return -EOPNOTSUPP;
2080 }
ce99f6b9 2081
225aabaf 2082 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
ce99f6b9
OG		 2083 if (!encap_header)
2084 return -ENOMEM;
2085
2086 switch (e->tunnel_type) {
2087 case MLX5_HEADER_TYPE_VXLAN:
2088 fl6.flowi6_proto = IPPROTO_UDP;
2089 fl6.fl6_dport = tun_key->tp_dst;
2090 break;
2091 default:
2092 err = -EOPNOTSUPP;
ace74321 2093 goto free_encap;
ce99f6b9
OG		 2094 }
2095
2096 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
2097 fl6.daddr = tun_key->u.ipv6.dst;
2098 fl6.saddr = tun_key->u.ipv6.src;
2099
1a8552bd 2100 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
ce99f6b9
OG		 2101 &fl6, &n, &ttl);
2102 if (err)
ace74321 2103 goto free_encap;
ce99f6b9 2104
232c0013
HHZ		 2105 /* used by mlx5e_detach_encap to lookup a neigh hash table
2106 * entry in the neigh hash table when a user deletes a rule
2107 */
2108 e->m_neigh.dev = n->dev;
f6dfb4c3 2109 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 2110 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2111 e->out_dev = out_dev;
2112
2113 /* It's importent to add the neigh to the hash table before checking
2114 * the neigh validity state. So if we'll get a notification, in case the
2115 * neigh changes it's validity state, we would find the relevant neigh
2116 * in the hash.
2117 */
2118 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2119 if (err)
ace74321 2120 goto free_encap;
232c0013 2121
033354d5
HHZ		 2122 read_lock_bh(&n->lock);
2123 nud_state = n->nud_state;
2124 ether_addr_copy(e->h_dest, n->ha);
2125 read_unlock_bh(&n->lock);
2126
ce99f6b9
OG		 2127 switch (e->tunnel_type) {
2128 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 2129 gen_vxlan_header_ipv6(out_dev, encap_header,
225aabaf
OG		 2130 ipv6_encap_size, e->h_dest, ttl,
2131 &fl6.daddr,
2132 &fl6.saddr, tun_key->tp_dst,
2133 tunnel_id_to_key32(tun_key->tun_id));
ce99f6b9
OG		 2134 break;
2135 default:
2136 err = -EOPNOTSUPP;
232c0013
HHZ		 2137 goto destroy_neigh_entry;
2138 }
2139
2140 e->encap_size = ipv6_encap_size;
2141 e->encap_header = encap_header;
2142
2143 if (!(nud_state & NUD_VALID)) {
2144 neigh_event_send(n, NULL);
27902f08
WY		 2145 err = -EAGAIN;
2146 goto out;
ce99f6b9
OG		 2147 }
2148
2149 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
225aabaf 2150 ipv6_encap_size, encap_header, &e->encap_id);
232c0013
HHZ		 2151 if (err)
2152 goto destroy_neigh_entry;
2153
2154 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 2155 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 2156 neigh_release(n);
2157 return err;
2158
2159destroy_neigh_entry:
2160 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 2161free_encap:
ce99f6b9 2162 kfree(encap_header);
ace74321 2163out:
232c0013
HHZ		 2164 if (n)
2165 neigh_release(n);
ce99f6b9
OG		 2166 return err;
2167}
2168
a54e20b4
HHZ		 2169static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2170 struct ip_tunnel_info *tun_info,
2171 struct net_device *mirred_dev,
45247bf2
OG		 2172 struct net_device **encap_dev,
2173 struct mlx5e_tc_flow *flow)
a54e20b4
HHZ		 2174{
2175 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a4b97ab4
MB		 2176 struct mlx5e_rep_priv *uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw,
2177 REP_ETH);
5ed99fb4 2178 struct net_device *up_dev = uplink_rpriv->netdev;
a54e20b4 2179 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2
OG		 2180 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
2181 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 2182 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 2183 struct mlx5e_encap_entry *e;
45247bf2 2184 int tunnel_type, err = 0;
a54e20b4
HHZ		 2185 uintptr_t hash_key;
2186 bool found = false;
a54e20b4 2187
2fcd82e9 2188 /* udp dst port must be set */
a54e20b4 2189 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2fcd82e9 2190 goto vxlan_encap_offload_err;
a54e20b4 2191
cd377663 2192 /* setting udp src port isn't supported */
2fcd82e9
OG		 2193 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
2194vxlan_encap_offload_err:
2195 netdev_warn(priv->netdev,
2196 "must set udp dst port and not set udp src port\n");
cd377663 2197 return -EOPNOTSUPP;
2fcd82e9 2198 }
cd377663 2199
1ad9a00a 2200 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->tp_dst)) &&
a54e20b4 2201 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
a54e20b4
HHZ		 2202 tunnel_type = MLX5_HEADER_TYPE_VXLAN;
2203 } else {
2fcd82e9
OG		 2204 netdev_warn(priv->netdev,
2205 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
a54e20b4
HHZ		 2206 return -EOPNOTSUPP;
2207 }
2208
76f7444d 2209 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 2210
2211 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2212 encap_hlist, hash_key) {
76f7444d 2213 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 2214 found = true;
2215 break;
2216 }
2217 }
2218
b2812089 2219 /* must verify if encap is valid or not */
45247bf2
OG		 2220 if (found)
2221 goto attach_flow;
a54e20b4
HHZ		 2222
2223 e = kzalloc(sizeof(*e), GFP_KERNEL);
2224 if (!e)
2225 return -ENOMEM;
2226
76f7444d 2227 e->tun_info = *tun_info;
a54e20b4
HHZ		 2228 e->tunnel_type = tunnel_type;
2229 INIT_LIST_HEAD(&e->flows);
2230
ce99f6b9 2231 if (family == AF_INET)
1a8552bd 2232 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2233 else if (family == AF_INET6)
1a8552bd 2234 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2235
232c0013 2236 if (err && err != -EAGAIN)
a54e20b4
HHZ		 2237 goto out_err;
2238
a54e20b4
HHZ		 2239 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2240
45247bf2
OG		 2241attach_flow:
2242 list_add(&flow->encap, &e->flows);
2243 *encap_dev = e->out_dev;
232c0013
HHZ		 2244 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2245 attr->encap_id = e->encap_id;
b2812089
VB		 2246 else
2247 err = -EAGAIN;
45247bf2 2248
232c0013 2249 return err;
a54e20b4
HHZ		 2250
2251out_err:
2252 kfree(e);
2253 return err;
2254}
2255
03a9d11e 2256static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 2257 struct mlx5e_tc_flow_parse_attr *parse_attr,
a54e20b4 2258 struct mlx5e_tc_flow *flow)
03a9d11e 2259{
ecf5bb79 2260 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 2261 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 2262 struct ip_tunnel_info *info = NULL;
03a9d11e 2263 const struct tc_action *a;
22dc13c8 2264 LIST_HEAD(actions);
a54e20b4 2265 bool encap = false;
232c0013 2266 int err = 0;
03a9d11e 2267
3bcc0cec 2268 if (!tcf_exts_has_actions(exts))
03a9d11e
OG		 2269 return -EINVAL;
2270
776b12b6 2271 memset(attr, 0, sizeof(*attr));
1d447a39 2272 attr->in_rep = rpriv->rep;
03a9d11e 2273
22dc13c8
WC		 2274 tcf_exts_to_list(exts, &actions);
2275 list_for_each_entry(a, &actions, list) {
03a9d11e 2276 if (is_tcf_gact_shot(a)) {
8b32580d
OG		 2277 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2278 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG		 2279 continue;
2280 }
2281
d7e75a32
OG		 2282 if (is_tcf_pedit(a)) {
2283 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
2284 parse_attr);
2285 if (err)
2286 return err;
2287
2288 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2289 continue;
2290 }
2291
26c02749
OG		 2292 if (is_tcf_csum(a)) {
2293 if (csum_offload_supported(priv, attr->action,
2294 tcf_csum_update_flags(a)))
2295 continue;
2296
2297 return -EOPNOTSUPP;
2298 }
2299
5724b8b5 2300 if (is_tcf_mirred_egress_redirect(a)) {
3c37745e 2301 struct net_device *out_dev;
03a9d11e 2302 struct mlx5e_priv *out_priv;
03a9d11e 2303
9f8a739e 2304 out_dev = tcf_mirred_dev(a);
03a9d11e 2305
a54e20b4
HHZ		 2306 if (switchdev_port_same_parent_id(priv->netdev,
2307 out_dev)) {
2308 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2309 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2310 out_priv = netdev_priv(out_dev);
1d447a39
SM		 2311 rpriv = out_priv->ppriv;
2312 attr->out_rep = rpriv->rep;
a54e20b4 2313 } else if (encap) {
9f8a739e 2314 parse_attr->mirred_ifindex = out_dev->ifindex;
3c37745e
OG		 2315 parse_attr->tun_info = *info;
2316 attr->parse_attr = parse_attr;
a54e20b4
HHZ		 2317 attr->action |= MLX5_FLOW_CONTEXT_ACTION_ENCAP |
2318 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2319 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3c37745e 2320 /* attr->out_rep is resolved when we handle encap */
a54e20b4 2321 } else {
03a9d11e
OG		 2322 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2323 priv->netdev->name, out_dev->name);
2324 return -EINVAL;
2325 }
a54e20b4
HHZ		 2326 continue;
2327 }
03a9d11e 2328
a54e20b4
HHZ		 2329 if (is_tcf_tunnel_set(a)) {
2330 info = tcf_tunnel_info(a);
2331 if (info)
2332 encap = true;
2333 else
2334 return -EOPNOTSUPP;
03a9d11e
OG		 2335 continue;
2336 }
2337
8b32580d 2338 if (is_tcf_vlan(a)) {
09c91ddf 2339 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
8b32580d 2340 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
09c91ddf 2341 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
8b32580d
OG		 2342 if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q))
2343 return -EOPNOTSUPP;
2344
2345 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
2346 attr->vlan = tcf_vlan_push_vid(a);
09c91ddf
OG		 2347 } else { /* action is TCA_VLAN_ACT_MODIFY */
2348 return -EOPNOTSUPP;
8b32580d
OG		 2349 }
2350 continue;
2351 }
2352
bbd00f7e
HHZ		 2353 if (is_tcf_tunnel_release(a)) {
2354 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2355 continue;
2356 }
2357
03a9d11e
OG		 2358 return -EINVAL;
2359 }
bdd66ac0
OG		 2360
2361 if (!actions_match_supported(priv, exts, parse_attr, flow))
2362 return -EOPNOTSUPP;
2363
232c0013 2364 return err;
03a9d11e
OG		 2365}
2366
5fd9fc4e 2367int mlx5e_configure_flower(struct mlx5e_priv *priv,
e3a2b7ed
AV		 2368 struct tc_cls_flower_offload *f)
2369{
3bc4b7bf 2370 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
17091853 2371 struct mlx5e_tc_flow_parse_attr *parse_attr;
acff797c 2372 struct mlx5e_tc_table *tc = &priv->fs.tc;
3bc4b7bf
OG		 2373 struct mlx5e_tc_flow *flow;
2374 int attr_size, err = 0;
65ba8fb7 2375 u8 flow_flags = 0;
e3a2b7ed 2376
65ba8fb7
OG		 2377 if (esw && esw->mode == SRIOV_OFFLOADS) {
2378 flow_flags = MLX5E_TC_FLOW_ESWITCH;
2379 attr_size = sizeof(struct mlx5_esw_flow_attr);
3bc4b7bf
OG		 2380 } else {
2381 flow_flags = MLX5E_TC_FLOW_NIC;
2382 attr_size = sizeof(struct mlx5_nic_flow_attr);
65ba8fb7 2383 }
e3a2b7ed 2384
65ba8fb7 2385 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 2386 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 2387 if (!parse_attr || !flow) {
e3a2b7ed
AV		 2388 err = -ENOMEM;
2389 goto err_free;
2390 }
2391
2392 flow->cookie = f->cookie;
65ba8fb7 2393 flow->flags = flow_flags;
e3a2b7ed 2394
17091853 2395 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
e3a2b7ed
AV		 2396 if (err < 0)
2397 goto err_free;
2398
65ba8fb7 2399 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
d7e75a32 2400 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow);
adb4c123 2401 if (err < 0)
3c37745e 2402 goto err_free;
aa0cbbae 2403 flow->rule = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow);
adb4c123 2404 } else {
aa0cbbae 2405 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow);
adb4c123
OG		 2406 if (err < 0)
2407 goto err_free;
aa0cbbae 2408 flow->rule = mlx5e_tc_add_nic_flow(priv, parse_attr, flow);
adb4c123 2409 }
e3a2b7ed 2410
e3a2b7ed
AV		 2411 if (IS_ERR(flow->rule)) {
2412 err = PTR_ERR(flow->rule);
3c37745e
OG		 2413 if (err != -EAGAIN)
2414 goto err_free;
e3a2b7ed
AV		 2415 }
2416
3c37745e
OG		 2417 if (err != -EAGAIN)
2418 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
2419
5c40348c
OG		 2420 err = rhashtable_insert_fast(&tc->ht, &flow->node,
2421 tc->ht_params);
2422 if (err)
2423 goto err_del_rule;
2424
232c0013
HHZ		 2425 if (flow->flags & MLX5E_TC_FLOW_ESWITCH &&
2426 !(flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP))
2427 kvfree(parse_attr);
2428 return err;
e3a2b7ed 2429
5c40348c 2430err_del_rule:
5e86397a 2431 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 2432
2433err_free:
17091853 2434 kvfree(parse_attr);
232c0013 2435 kfree(flow);
e3a2b7ed
AV		 2436 return err;
2437}
2438
2439int mlx5e_delete_flower(struct mlx5e_priv *priv,
2440 struct tc_cls_flower_offload *f)
2441{
2442 struct mlx5e_tc_flow *flow;
acff797c 2443 struct mlx5e_tc_table *tc = &priv->fs.tc;
e3a2b7ed
AV		 2444
2445 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2446 tc->ht_params);
2447 if (!flow)
2448 return -EINVAL;
2449
2450 rhashtable_remove_fast(&tc->ht, &flow->node, tc->ht_params);
2451
961e8979 2452 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 2453
2454 kfree(flow);
2455
2456 return 0;
2457}
2458
aad7e08d
AV		 2459int mlx5e_stats_flower(struct mlx5e_priv *priv,
2460 struct tc_cls_flower_offload *f)
2461{
2462 struct mlx5e_tc_table *tc = &priv->fs.tc;
2463 struct mlx5e_tc_flow *flow;
aad7e08d
AV		 2464 struct mlx5_fc *counter;
2465 u64 bytes;
2466 u64 packets;
2467 u64 lastuse;
2468
2469 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2470 tc->ht_params);
2471 if (!flow)
2472 return -EINVAL;
2473
0b67a38f
HHZ		 2474 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
2475 return 0;
2476
aad7e08d
AV		 2477 counter = mlx5_flow_rule_counter(flow->rule);
2478 if (!counter)
2479 return 0;
2480
2481 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
2482
d897a638 2483 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
fed06ee8 2484
aad7e08d
AV		 2485 return 0;
2486}
2487
e8f887ac
AV		 2488static const struct rhashtable_params mlx5e_tc_flow_ht_params = {
2489 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2490 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2491 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2492 .automatic_shrinking = true,
2493};
2494
2495int mlx5e_tc_init(struct mlx5e_priv *priv)
2496{
acff797c 2497 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 2498
11c9c548 2499 hash_init(tc->mod_hdr_tbl);
5c65c564 2500 hash_init(tc->hairpin_tbl);
11c9c548 2501
e8f887ac
AV		 2502 tc->ht_params = mlx5e_tc_flow_ht_params;
2503 return rhashtable_init(&tc->ht, &tc->ht_params);
2504}
2505
2506static void _mlx5e_tc_del_flow(void *ptr, void *arg)
2507{
2508 struct mlx5e_tc_flow *flow = ptr;
2509 struct mlx5e_priv *priv = arg;
2510
961e8979 2511 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 2512 kfree(flow);
2513}
2514
2515void mlx5e_tc_cleanup(struct mlx5e_priv *priv)
2516{
acff797c 2517 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac
AV		 2518
2519 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, priv);
2520
acff797c
MG		 2521 if (!IS_ERR_OR_NULL(tc->t)) {
2522 mlx5_destroy_flow_table(tc->t);
2523 tc->t = NULL;
e8f887ac
AV		 2524 }
2525}
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