]> git.ipfire.org Git - thirdparty/linux.git/blame - drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
net/mlx5e: Use short attribute form when adding/deleting offloaded TC flows
[thirdparty/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV
1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV
35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV
38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG
41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
a54e20b4 47#include <net/vxlan.h>
f6dfb4c3 48#include <net/arp.h>
e8f887ac 49#include "en.h"
1d447a39 50#include "en_rep.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
bbd00f7e 53#include "vxlan.h"
e8f887ac 54
3bc4b7bf
OG
55struct mlx5_nic_flow_attr {
56 u32 action;
57 u32 flow_tag;
2f4fe4ca 58 u32 mod_hdr_id;
3bc4b7bf
OG
59};
60
65ba8fb7
OG
61enum {
62 MLX5E_TC_FLOW_ESWITCH = BIT(0),
3bc4b7bf 63 MLX5E_TC_FLOW_NIC = BIT(1),
0b67a38f 64 MLX5E_TC_FLOW_OFFLOADED = BIT(2),
65ba8fb7
OG
65};
66
e8f887ac
AV
67struct mlx5e_tc_flow {
68 struct rhash_head node;
69 u64 cookie;
65ba8fb7 70 u8 flags;
74491de9 71 struct mlx5_flow_handle *rule;
a54e20b4 72 struct list_head encap; /* flows sharing the same encap */
3bc4b7bf
OG
73 union {
74 struct mlx5_esw_flow_attr esw_attr[0];
75 struct mlx5_nic_flow_attr nic_attr[0];
76 };
e8f887ac
AV
77};
78
17091853
OG
79struct mlx5e_tc_flow_parse_attr {
80 struct mlx5_flow_spec spec;
d79b6df6
OG
81 int num_mod_hdr_actions;
82 void *mod_hdr_actions;
17091853
OG
83};
84
a54e20b4
HHZ
85enum {
86 MLX5_HEADER_TYPE_VXLAN = 0x0,
87 MLX5_HEADER_TYPE_NVGRE = 0x1,
88};
89
acff797c
MG
90#define MLX5E_TC_TABLE_NUM_ENTRIES 1024
91#define MLX5E_TC_TABLE_NUM_GROUPS 4
e8f887ac 92
74491de9
MB
93static struct mlx5_flow_handle *
94mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 95 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 96 struct mlx5e_tc_flow *flow)
e8f887ac 97{
aa0cbbae 98 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 99 struct mlx5_core_dev *dev = priv->mdev;
aa0cbbae 100 struct mlx5_flow_destination dest = {};
66958ed9 101 struct mlx5_flow_act flow_act = {
3bc4b7bf
OG
102 .action = attr->action,
103 .flow_tag = attr->flow_tag,
66958ed9
HHZ
104 .encap_id = 0,
105 };
aad7e08d 106 struct mlx5_fc *counter = NULL;
74491de9 107 struct mlx5_flow_handle *rule;
e8f887ac 108 bool table_created = false;
2f4fe4ca 109 int err;
e8f887ac 110
3bc4b7bf 111 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
aad7e08d
AV
112 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
113 dest.ft = priv->fs.vlan.ft.t;
3bc4b7bf 114 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
aad7e08d
AV
115 counter = mlx5_fc_create(dev, true);
116 if (IS_ERR(counter))
117 return ERR_CAST(counter);
118
119 dest.type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
120 dest.counter = counter;
121 }
122
2f4fe4ca
OG
123 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
124 err = mlx5_modify_header_alloc(dev, MLX5_FLOW_NAMESPACE_KERNEL,
125 parse_attr->num_mod_hdr_actions,
126 parse_attr->mod_hdr_actions,
127 &attr->mod_hdr_id);
d7e75a32 128 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca
OG
129 kfree(parse_attr->mod_hdr_actions);
130 if (err) {
131 rule = ERR_PTR(err);
132 goto err_create_mod_hdr_id;
133 }
134 }
135
acff797c
MG
136 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
137 priv->fs.tc.t =
138 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
139 MLX5E_TC_PRIO,
140 MLX5E_TC_TABLE_NUM_ENTRIES,
141 MLX5E_TC_TABLE_NUM_GROUPS,
c9f1b073 142 0, 0);
acff797c 143 if (IS_ERR(priv->fs.tc.t)) {
e8f887ac
AV
144 netdev_err(priv->netdev,
145 "Failed to create tc offload table\n");
aad7e08d
AV
146 rule = ERR_CAST(priv->fs.tc.t);
147 goto err_create_ft;
e8f887ac
AV
148 }
149
150 table_created = true;
151 }
152
17091853
OG
153 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
154 rule = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
155 &flow_act, &dest, 1);
aad7e08d
AV
156
157 if (IS_ERR(rule))
158 goto err_add_rule;
159
160 return rule;
e8f887ac 161
aad7e08d
AV
162err_add_rule:
163 if (table_created) {
acff797c
MG
164 mlx5_destroy_flow_table(priv->fs.tc.t);
165 priv->fs.tc.t = NULL;
e8f887ac 166 }
aad7e08d 167err_create_ft:
2f4fe4ca
OG
168 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
169 mlx5_modify_header_dealloc(priv->mdev,
170 attr->mod_hdr_id);
171err_create_mod_hdr_id:
aad7e08d 172 mlx5_fc_destroy(dev, counter);
e8f887ac
AV
173
174 return rule;
175}
176
d85cdccb
OG
177static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
178 struct mlx5e_tc_flow *flow)
179{
513f8f7f 180 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG
181 struct mlx5_fc *counter = NULL;
182
aa0cbbae
OG
183 counter = mlx5_flow_rule_counter(flow->rule);
184 mlx5_del_flow_rules(flow->rule);
185 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb
OG
186
187 if (!mlx5e_tc_num_filters(priv) && (priv->fs.tc.t)) {
188 mlx5_destroy_flow_table(priv->fs.tc.t);
189 priv->fs.tc.t = NULL;
190 }
2f4fe4ca 191
513f8f7f 192 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2f4fe4ca 193 mlx5_modify_header_dealloc(priv->mdev,
513f8f7f 194 attr->mod_hdr_id);
d85cdccb
OG
195}
196
aa0cbbae
OG
197static void mlx5e_detach_encap(struct mlx5e_priv *priv,
198 struct mlx5e_tc_flow *flow);
199
74491de9
MB
200static struct mlx5_flow_handle *
201mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 202 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 203 struct mlx5e_tc_flow *flow)
adb4c123
OG
204{
205 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae
OG
206 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
207 struct mlx5_flow_handle *rule;
8b32580d
OG
208 int err;
209
210 err = mlx5_eswitch_add_vlan_action(esw, attr);
aa0cbbae
OG
211 if (err) {
212 rule = ERR_PTR(err);
213 goto err_add_vlan;
214 }
adb4c123 215
d7e75a32
OG
216 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
217 err = mlx5_modify_header_alloc(priv->mdev, MLX5_FLOW_NAMESPACE_FDB,
218 parse_attr->num_mod_hdr_actions,
219 parse_attr->mod_hdr_actions,
220 &attr->mod_hdr_id);
221 kfree(parse_attr->mod_hdr_actions);
222 if (err) {
223 rule = ERR_PTR(err);
224 goto err_mod_hdr;
225 }
226 }
227
aa0cbbae
OG
228 rule = mlx5_eswitch_add_offloaded_rule(esw, &parse_attr->spec, attr);
229 if (IS_ERR(rule))
230 goto err_add_rule;
adb4c123 231
aa0cbbae
OG
232 return rule;
233
234err_add_rule:
513f8f7f 235 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
d7e75a32
OG
236 mlx5_modify_header_dealloc(priv->mdev,
237 attr->mod_hdr_id);
238err_mod_hdr:
aa0cbbae
OG
239 mlx5_eswitch_del_vlan_action(esw, attr);
240err_add_vlan:
241 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
242 mlx5e_detach_encap(priv, flow);
aa0cbbae
OG
243 return rule;
244}
d85cdccb
OG
245
246static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
247 struct mlx5e_tc_flow *flow)
248{
249 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 250 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
d85cdccb 251
232c0013
HHZ
252 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
253 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
513f8f7f 254 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, attr);
232c0013 255 }
d85cdccb 256
513f8f7f 257 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 258
513f8f7f 259 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
d85cdccb 260 mlx5e_detach_encap(priv, flow);
513f8f7f 261 kvfree(attr->parse_attr);
232c0013 262 }
d7e75a32 263
513f8f7f 264 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
d7e75a32
OG
265 mlx5_modify_header_dealloc(priv->mdev,
266 attr->mod_hdr_id);
d85cdccb
OG
267}
268
232c0013
HHZ
269void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
270 struct mlx5e_encap_entry *e)
271{
272 struct mlx5e_tc_flow *flow;
273 int err;
274
275 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
276 e->encap_size, e->encap_header,
277 &e->encap_id);
278 if (err) {
279 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
280 err);
281 return;
282 }
283 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 284 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013
HHZ
285
286 list_for_each_entry(flow, &e->flows, encap) {
287 flow->esw_attr->encap_id = e->encap_id;
288 flow->rule = mlx5e_tc_add_fdb_flow(priv,
289 flow->esw_attr->parse_attr,
290 flow);
291 if (IS_ERR(flow->rule)) {
292 err = PTR_ERR(flow->rule);
293 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
294 err);
295 continue;
296 }
297 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
298 }
299}
300
301void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
302 struct mlx5e_encap_entry *e)
303{
304 struct mlx5e_tc_flow *flow;
305 struct mlx5_fc *counter;
306
307 list_for_each_entry(flow, &e->flows, encap) {
308 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
309 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
310 counter = mlx5_flow_rule_counter(flow->rule);
311 mlx5_del_flow_rules(flow->rule);
312 mlx5_fc_destroy(priv->mdev, counter);
313 }
314 }
315
316 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
317 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
318 mlx5_encap_dealloc(priv->mdev, e->encap_id);
319 }
320}
321
f6dfb4c3
HHZ
322void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
323{
324 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
325 u64 bytes, packets, lastuse = 0;
326 struct mlx5e_tc_flow *flow;
327 struct mlx5e_encap_entry *e;
328 struct mlx5_fc *counter;
329 struct neigh_table *tbl;
330 bool neigh_used = false;
331 struct neighbour *n;
332
333 if (m_neigh->family == AF_INET)
334 tbl = &arp_tbl;
335#if IS_ENABLED(CONFIG_IPV6)
336 else if (m_neigh->family == AF_INET6)
337 tbl = ipv6_stub->nd_tbl;
338#endif
339 else
340 return;
341
342 list_for_each_entry(e, &nhe->encap_list, encap_list) {
343 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
344 continue;
345 list_for_each_entry(flow, &e->flows, encap) {
346 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
347 counter = mlx5_flow_rule_counter(flow->rule);
348 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
349 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
350 neigh_used = true;
351 break;
352 }
353 }
354 }
355 }
356
357 if (neigh_used) {
358 nhe->reported_lastuse = jiffies;
359
360 /* find the relevant neigh according to the cached device and
361 * dst ip pair
362 */
363 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
364 if (!n) {
365 WARN(1, "The neighbour already freed\n");
366 return;
367 }
368
369 neigh_event_send(n, NULL);
370 neigh_release(n);
371 }
372}
373
d85cdccb
OG
374static void mlx5e_detach_encap(struct mlx5e_priv *priv,
375 struct mlx5e_tc_flow *flow)
376{
5067b602
RD
377 struct list_head *next = flow->encap.next;
378
379 list_del(&flow->encap);
380 if (list_empty(next)) {
c1ae1152 381 struct mlx5e_encap_entry *e;
5067b602 382
c1ae1152 383 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ
384 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
385
386 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
5067b602 387 mlx5_encap_dealloc(priv->mdev, e->encap_id);
232c0013 388
cdc5a7f3 389 hash_del_rcu(&e->encap_hlist);
232c0013 390 kfree(e->encap_header);
5067b602
RD
391 kfree(e);
392 }
393}
394
e8f887ac 395static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 396 struct mlx5e_tc_flow *flow)
e8f887ac 397{
d85cdccb
OG
398 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
399 mlx5e_tc_del_fdb_flow(priv, flow);
400 else
401 mlx5e_tc_del_nic_flow(priv, flow);
e8f887ac
AV
402}
403
bbd00f7e
HHZ
404static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
405 struct tc_cls_flower_offload *f)
406{
407 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
408 outer_headers);
409 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
410 outer_headers);
411 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
412 misc_parameters);
413 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
414 misc_parameters);
415
416 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
417 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
418
419 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
420 struct flow_dissector_key_keyid *key =
421 skb_flow_dissector_target(f->dissector,
422 FLOW_DISSECTOR_KEY_ENC_KEYID,
423 f->key);
424 struct flow_dissector_key_keyid *mask =
425 skb_flow_dissector_target(f->dissector,
426 FLOW_DISSECTOR_KEY_ENC_KEYID,
427 f->mask);
428 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
429 be32_to_cpu(mask->keyid));
430 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
431 be32_to_cpu(key->keyid));
432 }
433}
434
435static int parse_tunnel_attr(struct mlx5e_priv *priv,
436 struct mlx5_flow_spec *spec,
437 struct tc_cls_flower_offload *f)
438{
439 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
440 outer_headers);
441 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
442 outer_headers);
443
2e72eb43
OG
444 struct flow_dissector_key_control *enc_control =
445 skb_flow_dissector_target(f->dissector,
446 FLOW_DISSECTOR_KEY_ENC_CONTROL,
447 f->key);
448
bbd00f7e
HHZ
449 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
450 struct flow_dissector_key_ports *key =
451 skb_flow_dissector_target(f->dissector,
452 FLOW_DISSECTOR_KEY_ENC_PORTS,
453 f->key);
454 struct flow_dissector_key_ports *mask =
455 skb_flow_dissector_target(f->dissector,
456 FLOW_DISSECTOR_KEY_ENC_PORTS,
457 f->mask);
1ad9a00a
PB
458 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
459 struct net_device *up_dev = mlx5_eswitch_get_uplink_netdev(esw);
460 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
bbd00f7e
HHZ
461
462 /* Full udp dst port must be given */
463 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
2fcd82e9 464 goto vxlan_match_offload_err;
bbd00f7e 465
1ad9a00a 466 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->dst)) &&
bbd00f7e
HHZ
467 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
468 parse_vxlan_attr(spec, f);
2fcd82e9
OG
469 else {
470 netdev_warn(priv->netdev,
471 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
bbd00f7e 472 return -EOPNOTSUPP;
2fcd82e9 473 }
bbd00f7e
HHZ
474
475 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
476 udp_dport, ntohs(mask->dst));
477 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
478 udp_dport, ntohs(key->dst));
479
cd377663
OG
480 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
481 udp_sport, ntohs(mask->src));
482 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
483 udp_sport, ntohs(key->src));
bbd00f7e 484 } else { /* udp dst port must be given */
2fcd82e9
OG
485vxlan_match_offload_err:
486 netdev_warn(priv->netdev,
487 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
488 return -EOPNOTSUPP;
bbd00f7e
HHZ
489 }
490
2e72eb43 491 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ
492 struct flow_dissector_key_ipv4_addrs *key =
493 skb_flow_dissector_target(f->dissector,
494 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
495 f->key);
496 struct flow_dissector_key_ipv4_addrs *mask =
497 skb_flow_dissector_target(f->dissector,
498 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
499 f->mask);
500 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
501 src_ipv4_src_ipv6.ipv4_layout.ipv4,
502 ntohl(mask->src));
503 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
504 src_ipv4_src_ipv6.ipv4_layout.ipv4,
505 ntohl(key->src));
506
507 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
508 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
509 ntohl(mask->dst));
510 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
511 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
512 ntohl(key->dst));
bbd00f7e 513
2e72eb43
OG
514 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
515 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG
516 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
517 struct flow_dissector_key_ipv6_addrs *key =
518 skb_flow_dissector_target(f->dissector,
519 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
520 f->key);
521 struct flow_dissector_key_ipv6_addrs *mask =
522 skb_flow_dissector_target(f->dissector,
523 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
524 f->mask);
525
526 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
527 src_ipv4_src_ipv6.ipv6_layout.ipv6),
528 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
529 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
530 src_ipv4_src_ipv6.ipv6_layout.ipv6),
531 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
532
533 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
534 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
535 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
536 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
537 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
538 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
539
540 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
541 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 542 }
bbd00f7e
HHZ
543
544 /* Enforce DMAC when offloading incoming tunneled flows.
545 * Flow counters require a match on the DMAC.
546 */
547 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
548 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
549 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
550 dmac_47_16), priv->netdev->dev_addr);
551
552 /* let software handle IP fragments */
553 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
554 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
555
556 return 0;
557}
558
de0af0bf
RD
559static int __parse_cls_flower(struct mlx5e_priv *priv,
560 struct mlx5_flow_spec *spec,
561 struct tc_cls_flower_offload *f,
562 u8 *min_inline)
e3a2b7ed 563{
c5bb1730
MG
564 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
565 outer_headers);
566 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
567 outer_headers);
e3a2b7ed
AV
568 u16 addr_type = 0;
569 u8 ip_proto = 0;
570
de0af0bf
RD
571 *min_inline = MLX5_INLINE_MODE_L2;
572
e3a2b7ed
AV
573 if (f->dissector->used_keys &
574 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
575 BIT(FLOW_DISSECTOR_KEY_BASIC) |
576 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 577 BIT(FLOW_DISSECTOR_KEY_VLAN) |
e3a2b7ed
AV
578 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
579 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ
580 BIT(FLOW_DISSECTOR_KEY_PORTS) |
581 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
582 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
583 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
584 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 585 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b
OG
586 BIT(FLOW_DISSECTOR_KEY_TCP) |
587 BIT(FLOW_DISSECTOR_KEY_IP))) {
e3a2b7ed
AV
588 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
589 f->dissector->used_keys);
590 return -EOPNOTSUPP;
591 }
592
bbd00f7e
HHZ
593 if ((dissector_uses_key(f->dissector,
594 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
595 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
596 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
597 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
598 struct flow_dissector_key_control *key =
599 skb_flow_dissector_target(f->dissector,
600 FLOW_DISSECTOR_KEY_ENC_CONTROL,
601 f->key);
602 switch (key->addr_type) {
603 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 604 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
bbd00f7e
HHZ
605 if (parse_tunnel_attr(priv, spec, f))
606 return -EOPNOTSUPP;
607 break;
608 default:
609 return -EOPNOTSUPP;
610 }
611
612 /* In decap flow, header pointers should point to the inner
613 * headers, outer header were already set by parse_tunnel_attr
614 */
615 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
616 inner_headers);
617 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
618 inner_headers);
619 }
620
e3a2b7ed
AV
621 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
622 struct flow_dissector_key_control *key =
623 skb_flow_dissector_target(f->dissector,
1dbd0d37 624 FLOW_DISSECTOR_KEY_CONTROL,
e3a2b7ed 625 f->key);
3f7d0eb4
OG
626
627 struct flow_dissector_key_control *mask =
628 skb_flow_dissector_target(f->dissector,
629 FLOW_DISSECTOR_KEY_CONTROL,
630 f->mask);
e3a2b7ed 631 addr_type = key->addr_type;
3f7d0eb4
OG
632
633 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
634 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
635 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
636 key->flags & FLOW_DIS_IS_FRAGMENT);
0827444d
OG
637
638 /* the HW doesn't need L3 inline to match on frag=no */
639 if (key->flags & FLOW_DIS_IS_FRAGMENT)
640 *min_inline = MLX5_INLINE_MODE_IP;
3f7d0eb4 641 }
e3a2b7ed
AV
642 }
643
644 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
645 struct flow_dissector_key_basic *key =
646 skb_flow_dissector_target(f->dissector,
647 FLOW_DISSECTOR_KEY_BASIC,
648 f->key);
649 struct flow_dissector_key_basic *mask =
650 skb_flow_dissector_target(f->dissector,
651 FLOW_DISSECTOR_KEY_BASIC,
652 f->mask);
653 ip_proto = key->ip_proto;
654
655 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
656 ntohs(mask->n_proto));
657 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
658 ntohs(key->n_proto));
659
660 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
661 mask->ip_proto);
662 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
663 key->ip_proto);
de0af0bf
RD
664
665 if (mask->ip_proto)
666 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV
667 }
668
669 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
670 struct flow_dissector_key_eth_addrs *key =
671 skb_flow_dissector_target(f->dissector,
672 FLOW_DISSECTOR_KEY_ETH_ADDRS,
673 f->key);
674 struct flow_dissector_key_eth_addrs *mask =
675 skb_flow_dissector_target(f->dissector,
676 FLOW_DISSECTOR_KEY_ETH_ADDRS,
677 f->mask);
678
679 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
680 dmac_47_16),
681 mask->dst);
682 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
683 dmac_47_16),
684 key->dst);
685
686 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
687 smac_47_16),
688 mask->src);
689 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
690 smac_47_16),
691 key->src);
692 }
693
095b6cfd
OG
694 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
695 struct flow_dissector_key_vlan *key =
696 skb_flow_dissector_target(f->dissector,
697 FLOW_DISSECTOR_KEY_VLAN,
698 f->key);
699 struct flow_dissector_key_vlan *mask =
700 skb_flow_dissector_target(f->dissector,
701 FLOW_DISSECTOR_KEY_VLAN,
702 f->mask);
358d79a4 703 if (mask->vlan_id || mask->vlan_priority) {
10543365
MHY
704 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
705 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
095b6cfd
OG
706
707 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
708 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG
709
710 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
711 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
095b6cfd
OG
712 }
713 }
714
e3a2b7ed
AV
715 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
716 struct flow_dissector_key_ipv4_addrs *key =
717 skb_flow_dissector_target(f->dissector,
718 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
719 f->key);
720 struct flow_dissector_key_ipv4_addrs *mask =
721 skb_flow_dissector_target(f->dissector,
722 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
723 f->mask);
724
725 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
726 src_ipv4_src_ipv6.ipv4_layout.ipv4),
727 &mask->src, sizeof(mask->src));
728 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
729 src_ipv4_src_ipv6.ipv4_layout.ipv4),
730 &key->src, sizeof(key->src));
731 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
732 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
733 &mask->dst, sizeof(mask->dst));
734 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
735 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
736 &key->dst, sizeof(key->dst));
de0af0bf
RD
737
738 if (mask->src || mask->dst)
739 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV
740 }
741
742 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
743 struct flow_dissector_key_ipv6_addrs *key =
744 skb_flow_dissector_target(f->dissector,
745 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
746 f->key);
747 struct flow_dissector_key_ipv6_addrs *mask =
748 skb_flow_dissector_target(f->dissector,
749 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
750 f->mask);
751
752 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
753 src_ipv4_src_ipv6.ipv6_layout.ipv6),
754 &mask->src, sizeof(mask->src));
755 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
756 src_ipv4_src_ipv6.ipv6_layout.ipv6),
757 &key->src, sizeof(key->src));
758
759 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
760 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
761 &mask->dst, sizeof(mask->dst));
762 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
763 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
764 &key->dst, sizeof(key->dst));
de0af0bf
RD
765
766 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
767 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
768 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV
769 }
770
771 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
772 struct flow_dissector_key_ports *key =
773 skb_flow_dissector_target(f->dissector,
774 FLOW_DISSECTOR_KEY_PORTS,
775 f->key);
776 struct flow_dissector_key_ports *mask =
777 skb_flow_dissector_target(f->dissector,
778 FLOW_DISSECTOR_KEY_PORTS,
779 f->mask);
780 switch (ip_proto) {
781 case IPPROTO_TCP:
782 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
783 tcp_sport, ntohs(mask->src));
784 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
785 tcp_sport, ntohs(key->src));
786
787 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
788 tcp_dport, ntohs(mask->dst));
789 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
790 tcp_dport, ntohs(key->dst));
791 break;
792
793 case IPPROTO_UDP:
794 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
795 udp_sport, ntohs(mask->src));
796 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
797 udp_sport, ntohs(key->src));
798
799 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
800 udp_dport, ntohs(mask->dst));
801 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
802 udp_dport, ntohs(key->dst));
803 break;
804 default:
805 netdev_err(priv->netdev,
806 "Only UDP and TCP transport are supported\n");
807 return -EINVAL;
808 }
de0af0bf
RD
809
810 if (mask->src || mask->dst)
811 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
e3a2b7ed
AV
812 }
813
fd7da28b
OG
814 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
815 struct flow_dissector_key_ip *key =
816 skb_flow_dissector_target(f->dissector,
817 FLOW_DISSECTOR_KEY_IP,
818 f->key);
819 struct flow_dissector_key_ip *mask =
820 skb_flow_dissector_target(f->dissector,
821 FLOW_DISSECTOR_KEY_IP,
822 f->mask);
823
824 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
825 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
826
827 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
828 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
829
830 if (mask->tos)
831 *min_inline = MLX5_INLINE_MODE_IP;
832
833 if (mask->ttl) /* currently not supported */
834 return -EOPNOTSUPP;
835 }
836
e77834ec
OG
837 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
838 struct flow_dissector_key_tcp *key =
839 skb_flow_dissector_target(f->dissector,
840 FLOW_DISSECTOR_KEY_TCP,
841 f->key);
842 struct flow_dissector_key_tcp *mask =
843 skb_flow_dissector_target(f->dissector,
844 FLOW_DISSECTOR_KEY_TCP,
845 f->mask);
846
847 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
848 ntohs(mask->flags));
849 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
850 ntohs(key->flags));
851
852 if (mask->flags)
853 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
854 }
855
e3a2b7ed
AV
856 return 0;
857}
858
de0af0bf 859static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 860 struct mlx5e_tc_flow *flow,
de0af0bf
RD
861 struct mlx5_flow_spec *spec,
862 struct tc_cls_flower_offload *f)
863{
864 struct mlx5_core_dev *dev = priv->mdev;
865 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM
866 struct mlx5e_rep_priv *rpriv = priv->ppriv;
867 struct mlx5_eswitch_rep *rep;
de0af0bf
RD
868 u8 min_inline;
869 int err;
870
871 err = __parse_cls_flower(priv, spec, f, &min_inline);
872
1d447a39
SM
873 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
874 rep = rpriv->rep;
875 if (rep->vport != FDB_UPLINK_VPORT &&
876 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
877 esw->offloads.inline_mode < min_inline)) {
de0af0bf
RD
878 netdev_warn(priv->netdev,
879 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
880 min_inline, esw->offloads.inline_mode);
881 return -EOPNOTSUPP;
882 }
883 }
884
885 return err;
886}
887
d79b6df6
OG
888struct pedit_headers {
889 struct ethhdr eth;
890 struct iphdr ip4;
891 struct ipv6hdr ip6;
892 struct tcphdr tcp;
893 struct udphdr udp;
894};
895
896static int pedit_header_offsets[] = {
897 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
898 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
899 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
900 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
901 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
902};
903
904#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
905
906static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
907 struct pedit_headers *masks,
908 struct pedit_headers *vals)
909{
910 u32 *curr_pmask, *curr_pval;
911
912 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
913 goto out_err;
914
915 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
916 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
917
918 if (*curr_pmask & mask) /* disallow acting twice on the same location */
919 goto out_err;
920
921 *curr_pmask |= mask;
922 *curr_pval |= (val & mask);
923
924 return 0;
925
926out_err:
927 return -EOPNOTSUPP;
928}
929
930struct mlx5_fields {
931 u8 field;
932 u8 size;
933 u32 offset;
934};
935
936static struct mlx5_fields fields[] = {
937 {MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16, 4, offsetof(struct pedit_headers, eth.h_dest[0])},
938 {MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0, 2, offsetof(struct pedit_headers, eth.h_dest[4])},
939 {MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16, 4, offsetof(struct pedit_headers, eth.h_source[0])},
940 {MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0, 2, offsetof(struct pedit_headers, eth.h_source[4])},
941 {MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE, 2, offsetof(struct pedit_headers, eth.h_proto)},
942
943 {MLX5_ACTION_IN_FIELD_OUT_IP_DSCP, 1, offsetof(struct pedit_headers, ip4.tos)},
944 {MLX5_ACTION_IN_FIELD_OUT_IP_TTL, 1, offsetof(struct pedit_headers, ip4.ttl)},
945 {MLX5_ACTION_IN_FIELD_OUT_SIPV4, 4, offsetof(struct pedit_headers, ip4.saddr)},
946 {MLX5_ACTION_IN_FIELD_OUT_DIPV4, 4, offsetof(struct pedit_headers, ip4.daddr)},
947
948 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[0])},
949 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[1])},
950 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[2])},
951 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[3])},
952 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[0])},
953 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[1])},
954 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[2])},
955 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[3])},
956
957 {MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT, 2, offsetof(struct pedit_headers, tcp.source)},
958 {MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT, 2, offsetof(struct pedit_headers, tcp.dest)},
959 {MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS, 1, offsetof(struct pedit_headers, tcp.ack_seq) + 5},
960
961 {MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT, 2, offsetof(struct pedit_headers, udp.source)},
962 {MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT, 2, offsetof(struct pedit_headers, udp.dest)},
963};
964
965/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
966 * max from the SW pedit action. On success, it says how many HW actions were
967 * actually parsed.
968 */
969static int offload_pedit_fields(struct pedit_headers *masks,
970 struct pedit_headers *vals,
971 struct mlx5e_tc_flow_parse_attr *parse_attr)
972{
973 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
d824bf3f 974 int i, action_size, nactions, max_actions, first, last, first_z;
d79b6df6 975 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG
976 struct mlx5_fields *f;
977 u8 cmd, field_bsize;
e3ca4e05 978 u32 s_mask, a_mask;
d79b6df6
OG
979 unsigned long mask;
980 void *action;
981
982 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
983 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
984 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
985 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
986
987 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
988 action = parse_attr->mod_hdr_actions;
989 max_actions = parse_attr->num_mod_hdr_actions;
990 nactions = 0;
991
992 for (i = 0; i < ARRAY_SIZE(fields); i++) {
993 f = &fields[i];
994 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG
995 s_mask = 0;
996 a_mask = 0;
d79b6df6
OG
997
998 s_masks_p = (void *)set_masks + f->offset;
999 a_masks_p = (void *)add_masks + f->offset;
1000
1001 memcpy(&s_mask, s_masks_p, f->size);
1002 memcpy(&a_mask, a_masks_p, f->size);
1003
1004 if (!s_mask && !a_mask) /* nothing to offload here */
1005 continue;
1006
1007 if (s_mask && a_mask) {
1008 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1009 return -EOPNOTSUPP;
1010 }
1011
1012 if (nactions == max_actions) {
1013 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1014 return -EOPNOTSUPP;
1015 }
1016
1017 if (s_mask) {
1018 cmd = MLX5_ACTION_TYPE_SET;
1019 mask = s_mask;
1020 vals_p = (void *)set_vals + f->offset;
1021 /* clear to denote we consumed this field */
1022 memset(s_masks_p, 0, f->size);
1023 } else {
1024 cmd = MLX5_ACTION_TYPE_ADD;
1025 mask = a_mask;
1026 vals_p = (void *)add_vals + f->offset;
1027 /* clear to denote we consumed this field */
1028 memset(a_masks_p, 0, f->size);
1029 }
1030
d79b6df6 1031 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 1032
d824bf3f 1033 first_z = find_first_zero_bit(&mask, field_bsize);
d79b6df6
OG
1034 first = find_first_bit(&mask, field_bsize);
1035 last = find_last_bit(&mask, field_bsize);
d824bf3f 1036 if (first > 0 || last != (field_bsize - 1) || first_z < last) {
d79b6df6
OG
1037 printk(KERN_WARNING "mlx5: partial rewrite (mask %lx) is currently not offloaded\n",
1038 mask);
1039 return -EOPNOTSUPP;
1040 }
1041
1042 MLX5_SET(set_action_in, action, action_type, cmd);
1043 MLX5_SET(set_action_in, action, field, f->field);
1044
1045 if (cmd == MLX5_ACTION_TYPE_SET) {
1046 MLX5_SET(set_action_in, action, offset, 0);
1047 /* length is num of bits to be written, zero means length of 32 */
1048 MLX5_SET(set_action_in, action, length, field_bsize);
1049 }
1050
1051 if (field_bsize == 32)
e3ca4e05 1052 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p));
d79b6df6 1053 else if (field_bsize == 16)
e3ca4e05 1054 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p));
d79b6df6 1055 else if (field_bsize == 8)
e3ca4e05 1056 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p);
d79b6df6
OG
1057
1058 action += action_size;
1059 nactions++;
1060 }
1061
1062 parse_attr->num_mod_hdr_actions = nactions;
1063 return 0;
1064}
1065
1066static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
1067 const struct tc_action *a, int namespace,
1068 struct mlx5e_tc_flow_parse_attr *parse_attr)
1069{
1070 int nkeys, action_size, max_actions;
1071
1072 nkeys = tcf_pedit_nkeys(a);
1073 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1074
1075 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
1076 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
1077 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
1078 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
1079
1080 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
1081 max_actions = min(max_actions, nkeys * 16);
1082
1083 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
1084 if (!parse_attr->mod_hdr_actions)
1085 return -ENOMEM;
1086
1087 parse_attr->num_mod_hdr_actions = max_actions;
1088 return 0;
1089}
1090
1091static const struct pedit_headers zero_masks = {};
1092
1093static int parse_tc_pedit_action(struct mlx5e_priv *priv,
1094 const struct tc_action *a, int namespace,
1095 struct mlx5e_tc_flow_parse_attr *parse_attr)
1096{
1097 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
1098 int nkeys, i, err = -EOPNOTSUPP;
1099 u32 mask, val, offset;
1100 u8 cmd, htype;
1101
1102 nkeys = tcf_pedit_nkeys(a);
1103
1104 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1105 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1106
1107 for (i = 0; i < nkeys; i++) {
1108 htype = tcf_pedit_htype(a, i);
1109 cmd = tcf_pedit_cmd(a, i);
1110 err = -EOPNOTSUPP; /* can't be all optimistic */
1111
1112 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
1113 printk(KERN_WARNING "mlx5: legacy pedit isn't offloaded\n");
1114 goto out_err;
1115 }
1116
1117 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
1118 printk(KERN_WARNING "mlx5: pedit cmd %d isn't offloaded\n", cmd);
1119 goto out_err;
1120 }
1121
1122 mask = tcf_pedit_mask(a, i);
1123 val = tcf_pedit_val(a, i);
1124 offset = tcf_pedit_offset(a, i);
1125
1126 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
1127 if (err)
1128 goto out_err;
1129 }
1130
1131 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
1132 if (err)
1133 goto out_err;
1134
1135 err = offload_pedit_fields(masks, vals, parse_attr);
1136 if (err < 0)
1137 goto out_dealloc_parsed_actions;
1138
1139 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
1140 cmd_masks = &masks[cmd];
1141 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
1142 printk(KERN_WARNING "mlx5: attempt to offload an unsupported field (cmd %d)\n",
1143 cmd);
1144 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
1145 16, 1, cmd_masks, sizeof(zero_masks), true);
1146 err = -EOPNOTSUPP;
1147 goto out_dealloc_parsed_actions;
1148 }
1149 }
1150
1151 return 0;
1152
1153out_dealloc_parsed_actions:
1154 kfree(parse_attr->mod_hdr_actions);
1155out_err:
1156 return err;
1157}
1158
26c02749
OG
1159static bool csum_offload_supported(struct mlx5e_priv *priv, u32 action, u32 update_flags)
1160{
1161 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
1162 TCA_CSUM_UPDATE_FLAG_UDP;
1163
1164 /* The HW recalcs checksums only if re-writing headers */
1165 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
1166 netdev_warn(priv->netdev,
1167 "TC csum action is only offloaded with pedit\n");
1168 return false;
1169 }
1170
1171 if (update_flags & ~prot_flags) {
1172 netdev_warn(priv->netdev,
1173 "can't offload TC csum action for some header/s - flags %#x\n",
1174 update_flags);
1175 return false;
1176 }
1177
1178 return true;
1179}
1180
5c40348c 1181static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae
OG
1182 struct mlx5e_tc_flow_parse_attr *parse_attr,
1183 struct mlx5e_tc_flow *flow)
e3a2b7ed 1184{
aa0cbbae 1185 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 1186 const struct tc_action *a;
22dc13c8 1187 LIST_HEAD(actions);
2f4fe4ca 1188 int err;
e3a2b7ed
AV
1189
1190 if (tc_no_actions(exts))
1191 return -EINVAL;
1192
3bc4b7bf
OG
1193 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
1194 attr->action = 0;
e3a2b7ed 1195
22dc13c8
WC
1196 tcf_exts_to_list(exts, &actions);
1197 list_for_each_entry(a, &actions, list) {
e3a2b7ed 1198 if (is_tcf_gact_shot(a)) {
3bc4b7bf 1199 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV
1200 if (MLX5_CAP_FLOWTABLE(priv->mdev,
1201 flow_table_properties_nic_receive.flow_counter))
3bc4b7bf 1202 attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV
1203 continue;
1204 }
1205
2f4fe4ca
OG
1206 if (is_tcf_pedit(a)) {
1207 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
1208 parse_attr);
1209 if (err)
1210 return err;
1211
1212 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
1213 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1214 continue;
1215 }
1216
26c02749
OG
1217 if (is_tcf_csum(a)) {
1218 if (csum_offload_supported(priv, attr->action,
1219 tcf_csum_update_flags(a)))
1220 continue;
1221
1222 return -EOPNOTSUPP;
1223 }
1224
e3a2b7ed
AV
1225 if (is_tcf_skbedit_mark(a)) {
1226 u32 mark = tcf_skbedit_mark(a);
1227
1228 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
1229 netdev_warn(priv->netdev, "Bad flow mark - only 16 bit is supported: 0x%x\n",
1230 mark);
1231 return -EINVAL;
1232 }
1233
3bc4b7bf
OG
1234 attr->flow_tag = mark;
1235 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV
1236 continue;
1237 }
1238
1239 return -EINVAL;
1240 }
1241
1242 return 0;
1243}
1244
76f7444d
OG
1245static inline int cmp_encap_info(struct ip_tunnel_key *a,
1246 struct ip_tunnel_key *b)
a54e20b4
HHZ
1247{
1248 return memcmp(a, b, sizeof(*a));
1249}
1250
76f7444d 1251static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 1252{
76f7444d 1253 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ
1254}
1255
1256static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
1257 struct net_device *mirred_dev,
1258 struct net_device **out_dev,
1259 struct flowi4 *fl4,
1260 struct neighbour **out_n,
a54e20b4
HHZ
1261 int *out_ttl)
1262{
3e621b19 1263 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a54e20b4
HHZ
1264 struct rtable *rt;
1265 struct neighbour *n = NULL;
a54e20b4
HHZ
1266
1267#if IS_ENABLED(CONFIG_INET)
abeffce9
AB
1268 int ret;
1269
a54e20b4 1270 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
abeffce9
AB
1271 ret = PTR_ERR_OR_ZERO(rt);
1272 if (ret)
1273 return ret;
a54e20b4
HHZ
1274#else
1275 return -EOPNOTSUPP;
1276#endif
3e621b19
HHZ
1277 /* if the egress device isn't on the same HW e-switch, we use the uplink */
1278 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
1279 *out_dev = mlx5_eswitch_get_uplink_netdev(esw);
1280 else
1281 *out_dev = rt->dst.dev;
a54e20b4 1282
75c33da8 1283 *out_ttl = ip4_dst_hoplimit(&rt->dst);
a54e20b4
HHZ
1284 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
1285 ip_rt_put(rt);
1286 if (!n)
1287 return -ENOMEM;
1288
1289 *out_n = n;
a54e20b4
HHZ
1290 return 0;
1291}
1292
ce99f6b9
OG
1293static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
1294 struct net_device *mirred_dev,
1295 struct net_device **out_dev,
1296 struct flowi6 *fl6,
1297 struct neighbour **out_n,
1298 int *out_ttl)
1299{
1300 struct neighbour *n = NULL;
1301 struct dst_entry *dst;
1302
1303#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
1304 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1305 int ret;
1306
1307 dst = ip6_route_output(dev_net(mirred_dev), NULL, fl6);
321fa4ff
AB
1308 ret = dst->error;
1309 if (ret) {
ce99f6b9
OG
1310 dst_release(dst);
1311 return ret;
1312 }
1313
1314 *out_ttl = ip6_dst_hoplimit(dst);
1315
1316 /* if the egress device isn't on the same HW e-switch, we use the uplink */
1317 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
1318 *out_dev = mlx5_eswitch_get_uplink_netdev(esw);
1319 else
1320 *out_dev = dst->dev;
1321#else
1322 return -EOPNOTSUPP;
1323#endif
1324
1325 n = dst_neigh_lookup(dst, &fl6->daddr);
1326 dst_release(dst);
1327 if (!n)
1328 return -ENOMEM;
1329
1330 *out_n = n;
1331 return 0;
1332}
1333
32f3671f
OG
1334static void gen_vxlan_header_ipv4(struct net_device *out_dev,
1335 char buf[], int encap_size,
1336 unsigned char h_dest[ETH_ALEN],
1337 int ttl,
1338 __be32 daddr,
1339 __be32 saddr,
1340 __be16 udp_dst_port,
1341 __be32 vx_vni)
a54e20b4 1342{
a54e20b4
HHZ
1343 struct ethhdr *eth = (struct ethhdr *)buf;
1344 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
1345 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
1346 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
1347
1348 memset(buf, 0, encap_size);
1349
1350 ether_addr_copy(eth->h_dest, h_dest);
1351 ether_addr_copy(eth->h_source, out_dev->dev_addr);
1352 eth->h_proto = htons(ETH_P_IP);
1353
1354 ip->daddr = daddr;
1355 ip->saddr = saddr;
1356
1357 ip->ttl = ttl;
1358 ip->protocol = IPPROTO_UDP;
1359 ip->version = 0x4;
1360 ip->ihl = 0x5;
1361
1362 udp->dest = udp_dst_port;
1363 vxh->vx_flags = VXLAN_HF_VNI;
1364 vxh->vx_vni = vxlan_vni_field(vx_vni);
a54e20b4
HHZ
1365}
1366
225aabaf
OG
1367static void gen_vxlan_header_ipv6(struct net_device *out_dev,
1368 char buf[], int encap_size,
1369 unsigned char h_dest[ETH_ALEN],
1370 int ttl,
1371 struct in6_addr *daddr,
1372 struct in6_addr *saddr,
1373 __be16 udp_dst_port,
1374 __be32 vx_vni)
ce99f6b9 1375{
ce99f6b9
OG
1376 struct ethhdr *eth = (struct ethhdr *)buf;
1377 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
1378 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
1379 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
1380
1381 memset(buf, 0, encap_size);
1382
1383 ether_addr_copy(eth->h_dest, h_dest);
1384 ether_addr_copy(eth->h_source, out_dev->dev_addr);
1385 eth->h_proto = htons(ETH_P_IPV6);
1386
1387 ip6_flow_hdr(ip6h, 0, 0);
1388 /* the HW fills up ipv6 payload len */
1389 ip6h->nexthdr = IPPROTO_UDP;
1390 ip6h->hop_limit = ttl;
1391 ip6h->daddr = *daddr;
1392 ip6h->saddr = *saddr;
1393
1394 udp->dest = udp_dst_port;
1395 vxh->vx_flags = VXLAN_HF_VNI;
1396 vxh->vx_vni = vxlan_vni_field(vx_vni);
ce99f6b9
OG
1397}
1398
a54e20b4
HHZ
1399static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
1400 struct net_device *mirred_dev,
1a8552bd 1401 struct mlx5e_encap_entry *e)
a54e20b4
HHZ
1402{
1403 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
32f3671f 1404 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
76f7444d 1405 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 1406 struct net_device *out_dev;
a42485eb 1407 struct neighbour *n = NULL;
a54e20b4 1408 struct flowi4 fl4 = {};
a54e20b4 1409 char *encap_header;
32f3671f 1410 int ttl, err;
033354d5 1411 u8 nud_state;
32f3671f
OG
1412
1413 if (max_encap_size < ipv4_encap_size) {
1414 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
1415 ipv4_encap_size, max_encap_size);
1416 return -EOPNOTSUPP;
1417 }
a54e20b4 1418
32f3671f 1419 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
a54e20b4
HHZ
1420 if (!encap_header)
1421 return -ENOMEM;
1422
1423 switch (e->tunnel_type) {
1424 case MLX5_HEADER_TYPE_VXLAN:
1425 fl4.flowi4_proto = IPPROTO_UDP;
76f7444d 1426 fl4.fl4_dport = tun_key->tp_dst;
a54e20b4
HHZ
1427 break;
1428 default:
1429 err = -EOPNOTSUPP;
1430 goto out;
1431 }
9a941117 1432 fl4.flowi4_tos = tun_key->tos;
76f7444d 1433 fl4.daddr = tun_key->u.ipv4.dst;
9a941117 1434 fl4.saddr = tun_key->u.ipv4.src;
a54e20b4 1435
1a8552bd 1436 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
9a941117 1437 &fl4, &n, &ttl);
a54e20b4
HHZ
1438 if (err)
1439 goto out;
1440
232c0013
HHZ
1441 /* used by mlx5e_detach_encap to lookup a neigh hash table
1442 * entry in the neigh hash table when a user deletes a rule
1443 */
1444 e->m_neigh.dev = n->dev;
f6dfb4c3 1445 e->m_neigh.family = n->ops->family;
232c0013
HHZ
1446 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
1447 e->out_dev = out_dev;
1448
1449 /* It's importent to add the neigh to the hash table before checking
1450 * the neigh validity state. So if we'll get a notification, in case the
1451 * neigh changes it's validity state, we would find the relevant neigh
1452 * in the hash.
1453 */
1454 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
1455 if (err)
1456 goto out;
1457
033354d5
HHZ
1458 read_lock_bh(&n->lock);
1459 nud_state = n->nud_state;
1460 ether_addr_copy(e->h_dest, n->ha);
1461 read_unlock_bh(&n->lock);
1462
a54e20b4
HHZ
1463 switch (e->tunnel_type) {
1464 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 1465 gen_vxlan_header_ipv4(out_dev, encap_header,
32f3671f
OG
1466 ipv4_encap_size, e->h_dest, ttl,
1467 fl4.daddr,
1468 fl4.saddr, tun_key->tp_dst,
1469 tunnel_id_to_key32(tun_key->tun_id));
a54e20b4
HHZ
1470 break;
1471 default:
1472 err = -EOPNOTSUPP;
232c0013
HHZ
1473 goto destroy_neigh_entry;
1474 }
1475 e->encap_size = ipv4_encap_size;
1476 e->encap_header = encap_header;
1477
1478 if (!(nud_state & NUD_VALID)) {
1479 neigh_event_send(n, NULL);
27902f08
WY
1480 err = -EAGAIN;
1481 goto out;
a54e20b4
HHZ
1482 }
1483
1484 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
32f3671f 1485 ipv4_encap_size, encap_header, &e->encap_id);
232c0013
HHZ
1486 if (err)
1487 goto destroy_neigh_entry;
1488
1489 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1490 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ
1491 neigh_release(n);
1492 return err;
1493
1494destroy_neigh_entry:
1495 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
a54e20b4
HHZ
1496out:
1497 kfree(encap_header);
232c0013
HHZ
1498 if (n)
1499 neigh_release(n);
a54e20b4
HHZ
1500 return err;
1501}
1502
ce99f6b9
OG
1503static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
1504 struct net_device *mirred_dev,
1a8552bd 1505 struct mlx5e_encap_entry *e)
ce99f6b9
OG
1506{
1507 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
225aabaf 1508 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
ce99f6b9 1509 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 1510 struct net_device *out_dev;
ce99f6b9
OG
1511 struct neighbour *n = NULL;
1512 struct flowi6 fl6 = {};
1513 char *encap_header;
225aabaf 1514 int err, ttl = 0;
033354d5 1515 u8 nud_state;
ce99f6b9 1516
225aabaf
OG
1517 if (max_encap_size < ipv6_encap_size) {
1518 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
1519 ipv6_encap_size, max_encap_size);
1520 return -EOPNOTSUPP;
1521 }
ce99f6b9 1522
225aabaf 1523 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
ce99f6b9
OG
1524 if (!encap_header)
1525 return -ENOMEM;
1526
1527 switch (e->tunnel_type) {
1528 case MLX5_HEADER_TYPE_VXLAN:
1529 fl6.flowi6_proto = IPPROTO_UDP;
1530 fl6.fl6_dport = tun_key->tp_dst;
1531 break;
1532 default:
1533 err = -EOPNOTSUPP;
1534 goto out;
1535 }
1536
1537 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
1538 fl6.daddr = tun_key->u.ipv6.dst;
1539 fl6.saddr = tun_key->u.ipv6.src;
1540
1a8552bd 1541 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
ce99f6b9
OG
1542 &fl6, &n, &ttl);
1543 if (err)
1544 goto out;
1545
232c0013
HHZ
1546 /* used by mlx5e_detach_encap to lookup a neigh hash table
1547 * entry in the neigh hash table when a user deletes a rule
1548 */
1549 e->m_neigh.dev = n->dev;
f6dfb4c3 1550 e->m_neigh.family = n->ops->family;
232c0013
HHZ
1551 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
1552 e->out_dev = out_dev;
1553
1554 /* It's importent to add the neigh to the hash table before checking
1555 * the neigh validity state. So if we'll get a notification, in case the
1556 * neigh changes it's validity state, we would find the relevant neigh
1557 * in the hash.
1558 */
1559 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
1560 if (err)
1561 goto out;
1562
033354d5
HHZ
1563 read_lock_bh(&n->lock);
1564 nud_state = n->nud_state;
1565 ether_addr_copy(e->h_dest, n->ha);
1566 read_unlock_bh(&n->lock);
1567
ce99f6b9
OG
1568 switch (e->tunnel_type) {
1569 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 1570 gen_vxlan_header_ipv6(out_dev, encap_header,
225aabaf
OG
1571 ipv6_encap_size, e->h_dest, ttl,
1572 &fl6.daddr,
1573 &fl6.saddr, tun_key->tp_dst,
1574 tunnel_id_to_key32(tun_key->tun_id));
ce99f6b9
OG
1575 break;
1576 default:
1577 err = -EOPNOTSUPP;
232c0013
HHZ
1578 goto destroy_neigh_entry;
1579 }
1580
1581 e->encap_size = ipv6_encap_size;
1582 e->encap_header = encap_header;
1583
1584 if (!(nud_state & NUD_VALID)) {
1585 neigh_event_send(n, NULL);
27902f08
WY
1586 err = -EAGAIN;
1587 goto out;
ce99f6b9
OG
1588 }
1589
1590 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
225aabaf 1591 ipv6_encap_size, encap_header, &e->encap_id);
232c0013
HHZ
1592 if (err)
1593 goto destroy_neigh_entry;
1594
1595 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1596 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ
1597 neigh_release(n);
1598 return err;
1599
1600destroy_neigh_entry:
1601 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ce99f6b9 1602out:
ce99f6b9 1603 kfree(encap_header);
232c0013
HHZ
1604 if (n)
1605 neigh_release(n);
ce99f6b9
OG
1606 return err;
1607}
1608
a54e20b4
HHZ
1609static int mlx5e_attach_encap(struct mlx5e_priv *priv,
1610 struct ip_tunnel_info *tun_info,
1611 struct net_device *mirred_dev,
45247bf2
OG
1612 struct net_device **encap_dev,
1613 struct mlx5e_tc_flow *flow)
a54e20b4
HHZ
1614{
1615 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1ad9a00a 1616 struct net_device *up_dev = mlx5_eswitch_get_uplink_netdev(esw);
a54e20b4 1617 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2
OG
1618 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
1619 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 1620 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 1621 struct mlx5e_encap_entry *e;
45247bf2 1622 int tunnel_type, err = 0;
a54e20b4
HHZ
1623 uintptr_t hash_key;
1624 bool found = false;
a54e20b4 1625
2fcd82e9 1626 /* udp dst port must be set */
a54e20b4 1627 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2fcd82e9 1628 goto vxlan_encap_offload_err;
a54e20b4 1629
cd377663 1630 /* setting udp src port isn't supported */
2fcd82e9
OG
1631 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
1632vxlan_encap_offload_err:
1633 netdev_warn(priv->netdev,
1634 "must set udp dst port and not set udp src port\n");
cd377663 1635 return -EOPNOTSUPP;
2fcd82e9 1636 }
cd377663 1637
1ad9a00a 1638 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->tp_dst)) &&
a54e20b4 1639 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
a54e20b4
HHZ
1640 tunnel_type = MLX5_HEADER_TYPE_VXLAN;
1641 } else {
2fcd82e9
OG
1642 netdev_warn(priv->netdev,
1643 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
a54e20b4
HHZ
1644 return -EOPNOTSUPP;
1645 }
1646
76f7444d 1647 hash_key = hash_encap_info(key);
a54e20b4
HHZ
1648
1649 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
1650 encap_hlist, hash_key) {
76f7444d 1651 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ
1652 found = true;
1653 break;
1654 }
1655 }
1656
45247bf2
OG
1657 if (found)
1658 goto attach_flow;
a54e20b4
HHZ
1659
1660 e = kzalloc(sizeof(*e), GFP_KERNEL);
1661 if (!e)
1662 return -ENOMEM;
1663
76f7444d 1664 e->tun_info = *tun_info;
a54e20b4
HHZ
1665 e->tunnel_type = tunnel_type;
1666 INIT_LIST_HEAD(&e->flows);
1667
ce99f6b9 1668 if (family == AF_INET)
1a8552bd 1669 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
ce99f6b9 1670 else if (family == AF_INET6)
1a8552bd 1671 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
ce99f6b9 1672
232c0013 1673 if (err && err != -EAGAIN)
a54e20b4
HHZ
1674 goto out_err;
1675
a54e20b4
HHZ
1676 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
1677
45247bf2
OG
1678attach_flow:
1679 list_add(&flow->encap, &e->flows);
1680 *encap_dev = e->out_dev;
232c0013
HHZ
1681 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1682 attr->encap_id = e->encap_id;
45247bf2 1683
232c0013 1684 return err;
a54e20b4
HHZ
1685
1686out_err:
1687 kfree(e);
1688 return err;
1689}
1690
03a9d11e 1691static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 1692 struct mlx5e_tc_flow_parse_attr *parse_attr,
a54e20b4 1693 struct mlx5e_tc_flow *flow)
03a9d11e 1694{
ecf5bb79 1695 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 1696 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 1697 struct ip_tunnel_info *info = NULL;
03a9d11e 1698 const struct tc_action *a;
22dc13c8 1699 LIST_HEAD(actions);
a54e20b4 1700 bool encap = false;
232c0013 1701 int err = 0;
03a9d11e
OG
1702
1703 if (tc_no_actions(exts))
1704 return -EINVAL;
1705
776b12b6 1706 memset(attr, 0, sizeof(*attr));
1d447a39 1707 attr->in_rep = rpriv->rep;
03a9d11e 1708
22dc13c8
WC
1709 tcf_exts_to_list(exts, &actions);
1710 list_for_each_entry(a, &actions, list) {
03a9d11e 1711 if (is_tcf_gact_shot(a)) {
8b32580d
OG
1712 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
1713 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG
1714 continue;
1715 }
1716
d7e75a32
OG
1717 if (is_tcf_pedit(a)) {
1718 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
1719 parse_attr);
1720 if (err)
1721 return err;
1722
1723 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1724 continue;
1725 }
1726
26c02749
OG
1727 if (is_tcf_csum(a)) {
1728 if (csum_offload_supported(priv, attr->action,
1729 tcf_csum_update_flags(a)))
1730 continue;
1731
1732 return -EOPNOTSUPP;
1733 }
1734
5724b8b5 1735 if (is_tcf_mirred_egress_redirect(a)) {
03a9d11e 1736 int ifindex = tcf_mirred_ifindex(a);
45247bf2 1737 struct net_device *out_dev, *encap_dev = NULL;
03a9d11e 1738 struct mlx5e_priv *out_priv;
03a9d11e
OG
1739
1740 out_dev = __dev_get_by_index(dev_net(priv->netdev), ifindex);
1741
a54e20b4
HHZ
1742 if (switchdev_port_same_parent_id(priv->netdev,
1743 out_dev)) {
1744 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1745 MLX5_FLOW_CONTEXT_ACTION_COUNT;
1746 out_priv = netdev_priv(out_dev);
1d447a39
SM
1747 rpriv = out_priv->ppriv;
1748 attr->out_rep = rpriv->rep;
a54e20b4
HHZ
1749 } else if (encap) {
1750 err = mlx5e_attach_encap(priv, info,
45247bf2 1751 out_dev, &encap_dev, flow);
232c0013 1752 if (err && err != -EAGAIN)
a54e20b4 1753 return err;
a54e20b4
HHZ
1754 attr->action |= MLX5_FLOW_CONTEXT_ACTION_ENCAP |
1755 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1756 MLX5_FLOW_CONTEXT_ACTION_COUNT;
45247bf2 1757 out_priv = netdev_priv(encap_dev);
1d447a39
SM
1758 rpriv = out_priv->ppriv;
1759 attr->out_rep = rpriv->rep;
232c0013 1760 attr->parse_attr = parse_attr;
a54e20b4 1761 } else {
03a9d11e
OG
1762 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
1763 priv->netdev->name, out_dev->name);
1764 return -EINVAL;
1765 }
a54e20b4
HHZ
1766 continue;
1767 }
03a9d11e 1768
a54e20b4
HHZ
1769 if (is_tcf_tunnel_set(a)) {
1770 info = tcf_tunnel_info(a);
1771 if (info)
1772 encap = true;
1773 else
1774 return -EOPNOTSUPP;
03a9d11e
OG
1775 continue;
1776 }
1777
8b32580d 1778 if (is_tcf_vlan(a)) {
09c91ddf 1779 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
8b32580d 1780 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
09c91ddf 1781 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
8b32580d
OG
1782 if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q))
1783 return -EOPNOTSUPP;
1784
1785 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1786 attr->vlan = tcf_vlan_push_vid(a);
09c91ddf
OG
1787 } else { /* action is TCA_VLAN_ACT_MODIFY */
1788 return -EOPNOTSUPP;
8b32580d
OG
1789 }
1790 continue;
1791 }
1792
bbd00f7e
HHZ
1793 if (is_tcf_tunnel_release(a)) {
1794 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
1795 continue;
1796 }
1797
03a9d11e
OG
1798 return -EINVAL;
1799 }
232c0013 1800 return err;
03a9d11e
OG
1801}
1802
e3a2b7ed
AV
1803int mlx5e_configure_flower(struct mlx5e_priv *priv, __be16 protocol,
1804 struct tc_cls_flower_offload *f)
1805{
3bc4b7bf 1806 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
17091853 1807 struct mlx5e_tc_flow_parse_attr *parse_attr;
acff797c 1808 struct mlx5e_tc_table *tc = &priv->fs.tc;
3bc4b7bf
OG
1809 struct mlx5e_tc_flow *flow;
1810 int attr_size, err = 0;
65ba8fb7 1811 u8 flow_flags = 0;
e3a2b7ed 1812
65ba8fb7
OG
1813 if (esw && esw->mode == SRIOV_OFFLOADS) {
1814 flow_flags = MLX5E_TC_FLOW_ESWITCH;
1815 attr_size = sizeof(struct mlx5_esw_flow_attr);
3bc4b7bf
OG
1816 } else {
1817 flow_flags = MLX5E_TC_FLOW_NIC;
1818 attr_size = sizeof(struct mlx5_nic_flow_attr);
65ba8fb7 1819 }
e3a2b7ed 1820
65ba8fb7 1821 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 1822 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 1823 if (!parse_attr || !flow) {
e3a2b7ed
AV
1824 err = -ENOMEM;
1825 goto err_free;
1826 }
1827
1828 flow->cookie = f->cookie;
65ba8fb7 1829 flow->flags = flow_flags;
e3a2b7ed 1830
17091853 1831 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
e3a2b7ed
AV
1832 if (err < 0)
1833 goto err_free;
1834
65ba8fb7 1835 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
d7e75a32 1836 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow);
adb4c123 1837 if (err < 0)
232c0013 1838 goto err_handle_encap_flow;
aa0cbbae 1839 flow->rule = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow);
adb4c123 1840 } else {
aa0cbbae 1841 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow);
adb4c123
OG
1842 if (err < 0)
1843 goto err_free;
aa0cbbae 1844 flow->rule = mlx5e_tc_add_nic_flow(priv, parse_attr, flow);
adb4c123 1845 }
e3a2b7ed 1846
e3a2b7ed
AV
1847 if (IS_ERR(flow->rule)) {
1848 err = PTR_ERR(flow->rule);
aa0cbbae 1849 goto err_free;
e3a2b7ed
AV
1850 }
1851
0b67a38f 1852 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
5c40348c
OG
1853 err = rhashtable_insert_fast(&tc->ht, &flow->node,
1854 tc->ht_params);
1855 if (err)
1856 goto err_del_rule;
1857
232c0013
HHZ
1858 if (flow->flags & MLX5E_TC_FLOW_ESWITCH &&
1859 !(flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP))
1860 kvfree(parse_attr);
1861 return err;
e3a2b7ed 1862
5c40348c 1863err_del_rule:
5e86397a 1864 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed 1865
232c0013
HHZ
1866err_handle_encap_flow:
1867 if (err == -EAGAIN) {
1868 err = rhashtable_insert_fast(&tc->ht, &flow->node,
1869 tc->ht_params);
1870 if (err)
1871 mlx5e_tc_del_flow(priv, flow);
1872 else
1873 return 0;
1874 }
1875
e3a2b7ed 1876err_free:
17091853 1877 kvfree(parse_attr);
232c0013 1878 kfree(flow);
e3a2b7ed
AV
1879 return err;
1880}
1881
1882int mlx5e_delete_flower(struct mlx5e_priv *priv,
1883 struct tc_cls_flower_offload *f)
1884{
1885 struct mlx5e_tc_flow *flow;
acff797c 1886 struct mlx5e_tc_table *tc = &priv->fs.tc;
e3a2b7ed
AV
1887
1888 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
1889 tc->ht_params);
1890 if (!flow)
1891 return -EINVAL;
1892
1893 rhashtable_remove_fast(&tc->ht, &flow->node, tc->ht_params);
1894
961e8979 1895 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV
1896
1897 kfree(flow);
1898
1899 return 0;
1900}
1901
aad7e08d
AV
1902int mlx5e_stats_flower(struct mlx5e_priv *priv,
1903 struct tc_cls_flower_offload *f)
1904{
1905 struct mlx5e_tc_table *tc = &priv->fs.tc;
1906 struct mlx5e_tc_flow *flow;
aad7e08d
AV
1907 struct mlx5_fc *counter;
1908 u64 bytes;
1909 u64 packets;
1910 u64 lastuse;
1911
1912 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
1913 tc->ht_params);
1914 if (!flow)
1915 return -EINVAL;
1916
0b67a38f
HHZ
1917 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
1918 return 0;
1919
aad7e08d
AV
1920 counter = mlx5_flow_rule_counter(flow->rule);
1921 if (!counter)
1922 return 0;
1923
1924 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1925
d897a638 1926 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
fed06ee8 1927
aad7e08d
AV
1928 return 0;
1929}
1930
e8f887ac
AV
1931static const struct rhashtable_params mlx5e_tc_flow_ht_params = {
1932 .head_offset = offsetof(struct mlx5e_tc_flow, node),
1933 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
1934 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
1935 .automatic_shrinking = true,
1936};
1937
1938int mlx5e_tc_init(struct mlx5e_priv *priv)
1939{
acff797c 1940 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac
AV
1941
1942 tc->ht_params = mlx5e_tc_flow_ht_params;
1943 return rhashtable_init(&tc->ht, &tc->ht_params);
1944}
1945
1946static void _mlx5e_tc_del_flow(void *ptr, void *arg)
1947{
1948 struct mlx5e_tc_flow *flow = ptr;
1949 struct mlx5e_priv *priv = arg;
1950
961e8979 1951 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV
1952 kfree(flow);
1953}
1954
1955void mlx5e_tc_cleanup(struct mlx5e_priv *priv)
1956{
acff797c 1957 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac
AV
1958
1959 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, priv);
1960
acff797c
MG
1961 if (!IS_ERR_OR_NULL(tc->t)) {
1962 mlx5_destroy_flow_table(tc->t);
1963 tc->t = NULL;
e8f887ac
AV
1964 }
1965}