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e586b3b0 | 1 | /* |
98795158 | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
e586b3b0 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/tcp.h> | |
34 | #include <linux/if_vlan.h> | |
fbcb127e | 35 | #include <net/dsfield.h> |
e586b3b0 | 36 | #include "en.h" |
4301ba7b | 37 | #include "ipoib/ipoib.h" |
bf239741 | 38 | #include "en_accel/en_accel.h" |
7c39afb3 | 39 | #include "lib/clock.h" |
e586b3b0 | 40 | |
12be4b21 | 41 | #define MLX5E_SQ_NOPS_ROOM MLX5_SEND_WQE_MAX_WQEBBS |
bf239741 IL |
42 | |
43 | #ifndef CONFIG_MLX5_EN_TLS | |
12be4b21 SM |
44 | #define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\ |
45 | MLX5E_SQ_NOPS_ROOM) | |
bf239741 IL |
46 | #else |
47 | /* TLS offload requires MLX5E_SQ_STOP_ROOM to have | |
48 | * enough room for a resync SKB, a normal SKB and a NOP | |
49 | */ | |
50 | #define MLX5E_SQ_STOP_ROOM (2 * MLX5_SEND_WQE_MAX_WQEBBS +\ | |
51 | MLX5E_SQ_NOPS_ROOM) | |
52 | #endif | |
12be4b21 | 53 | |
d4e28cbd AS |
54 | static inline void mlx5e_tx_dma_unmap(struct device *pdev, |
55 | struct mlx5e_sq_dma *dma) | |
e586b3b0 | 56 | { |
d4e28cbd AS |
57 | switch (dma->type) { |
58 | case MLX5E_DMA_MAP_SINGLE: | |
59 | dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE); | |
60 | break; | |
61 | case MLX5E_DMA_MAP_PAGE: | |
62 | dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE); | |
63 | break; | |
64 | default: | |
65 | WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n"); | |
e586b3b0 AV |
66 | } |
67 | } | |
68 | ||
8ee48233 TT |
69 | static inline struct mlx5e_sq_dma *mlx5e_dma_get(struct mlx5e_txqsq *sq, u32 i) |
70 | { | |
71 | return &sq->db.dma_fifo[i & sq->dma_fifo_mask]; | |
72 | } | |
73 | ||
31391048 | 74 | static inline void mlx5e_dma_push(struct mlx5e_txqsq *sq, |
d4e28cbd AS |
75 | dma_addr_t addr, |
76 | u32 size, | |
77 | enum mlx5e_dma_map_type map_type) | |
e586b3b0 | 78 | { |
8ee48233 | 79 | struct mlx5e_sq_dma *dma = mlx5e_dma_get(sq, sq->dma_fifo_pc++); |
f10b7cc7 | 80 | |
8ee48233 TT |
81 | dma->addr = addr; |
82 | dma->size = size; | |
83 | dma->type = map_type; | |
d4e28cbd AS |
84 | } |
85 | ||
31391048 | 86 | static void mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq *sq, u8 num_dma) |
e586b3b0 | 87 | { |
d4e28cbd AS |
88 | int i; |
89 | ||
34802a42 | 90 | for (i = 0; i < num_dma; i++) { |
d4e28cbd AS |
91 | struct mlx5e_sq_dma *last_pushed_dma = |
92 | mlx5e_dma_get(sq, --sq->dma_fifo_pc); | |
93 | ||
94 | mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma); | |
95 | } | |
e586b3b0 AV |
96 | } |
97 | ||
fbcb127e HN |
98 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
99 | static inline int mlx5e_get_dscp_up(struct mlx5e_priv *priv, struct sk_buff *skb) | |
100 | { | |
101 | int dscp_cp = 0; | |
102 | ||
103 | if (skb->protocol == htons(ETH_P_IP)) | |
104 | dscp_cp = ipv4_get_dsfield(ip_hdr(skb)) >> 2; | |
105 | else if (skb->protocol == htons(ETH_P_IPV6)) | |
106 | dscp_cp = ipv6_get_dsfield(ipv6_hdr(skb)) >> 2; | |
107 | ||
108 | return priv->dcbx_dp.dscp2prio[dscp_cp]; | |
109 | } | |
110 | #endif | |
111 | ||
e586b3b0 | 112 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
4f49dec9 AD |
113 | struct net_device *sb_dev, |
114 | select_queue_fallback_t fallback) | |
e586b3b0 AV |
115 | { |
116 | struct mlx5e_priv *priv = netdev_priv(dev); | |
8ec56fc3 | 117 | int channel_ix = fallback(dev, skb, NULL); |
6a9764ef | 118 | u16 num_channels; |
7ccdd084 RS |
119 | int up = 0; |
120 | ||
121 | if (!netdev_get_num_tc(dev)) | |
122 | return channel_ix; | |
123 | ||
fbcb127e HN |
124 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
125 | if (priv->dcbx_dp.trust_state == MLX5_QPTS_TRUST_DSCP) | |
126 | up = mlx5e_get_dscp_up(priv, skb); | |
127 | else | |
128 | #endif | |
129 | if (skb_vlan_tag_present(skb)) | |
6c0fbd72 | 130 | up = skb_vlan_tag_get_prio(skb); |
7ccdd084 RS |
131 | |
132 | /* channel_ix can be larger than num_channels since | |
133 | * dev->num_real_tx_queues = num_channels * num_tc | |
134 | */ | |
6a9764ef SM |
135 | num_channels = priv->channels.params.num_channels; |
136 | if (channel_ix >= num_channels) | |
137 | channel_ix = reciprocal_scale(channel_ix, num_channels); | |
e586b3b0 | 138 | |
acc6c595 | 139 | return priv->channel_tc2txq[channel_ix][up]; |
e586b3b0 AV |
140 | } |
141 | ||
ae76715d HHZ |
142 | static inline int mlx5e_skb_l2_header_offset(struct sk_buff *skb) |
143 | { | |
144 | #define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN) | |
145 | ||
146 | return max(skb_network_offset(skb), MLX5E_MIN_INLINE); | |
147 | } | |
148 | ||
149 | static inline int mlx5e_skb_l3_header_offset(struct sk_buff *skb) | |
150 | { | |
ae76715d HHZ |
151 | if (skb_transport_header_was_set(skb)) |
152 | return skb_transport_offset(skb); | |
ae76715d HHZ |
153 | else |
154 | return mlx5e_skb_l2_header_offset(skb); | |
155 | } | |
156 | ||
6aace17e MS |
157 | static inline u16 mlx5e_calc_min_inline(enum mlx5_inline_modes mode, |
158 | struct sk_buff *skb) | |
ae76715d | 159 | { |
6aace17e | 160 | u16 hlen; |
ae76715d HHZ |
161 | |
162 | switch (mode) { | |
a6f402e4 SM |
163 | case MLX5_INLINE_MODE_NONE: |
164 | return 0; | |
ae76715d HHZ |
165 | case MLX5_INLINE_MODE_TCP_UDP: |
166 | hlen = eth_get_headlen(skb->data, skb_headlen(skb)); | |
167 | if (hlen == ETH_HLEN && !skb_vlan_tag_present(skb)) | |
168 | hlen += VLAN_HLEN; | |
6aace17e | 169 | break; |
ae76715d | 170 | case MLX5_INLINE_MODE_IP: |
3517dfe6 MM |
171 | hlen = mlx5e_skb_l3_header_offset(skb); |
172 | break; | |
ae76715d HHZ |
173 | case MLX5_INLINE_MODE_L2: |
174 | default: | |
6aace17e | 175 | hlen = mlx5e_skb_l2_header_offset(skb); |
ae76715d | 176 | } |
f600c608 | 177 | return min_t(u16, hlen, skb_headlen(skb)); |
ae76715d HHZ |
178 | } |
179 | ||
5e7d77a9 | 180 | static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs) |
e4cf27bd AS |
181 | { |
182 | struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start; | |
183 | int cpy1_sz = 2 * ETH_ALEN; | |
3ea4891d | 184 | int cpy2_sz = ihs - cpy1_sz; |
e4cf27bd | 185 | |
5e7d77a9 | 186 | memcpy(vhdr, skb->data, cpy1_sz); |
e4cf27bd AS |
187 | vhdr->h_vlan_proto = skb->vlan_proto; |
188 | vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb)); | |
5e7d77a9 | 189 | memcpy(&vhdr->h_vlan_encapsulated_proto, skb->data + cpy1_sz, cpy2_sz); |
e4cf27bd AS |
190 | } |
191 | ||
77bdf895 SM |
192 | static inline void |
193 | mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg) | |
e586b3b0 | 194 | { |
98795158 MF |
195 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
196 | eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM; | |
89db09eb | 197 | if (skb->encapsulation) { |
98795158 MF |
198 | eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM | |
199 | MLX5_ETH_WQE_L4_INNER_CSUM; | |
05909bab | 200 | sq->stats->csum_partial_inner++; |
89db09eb | 201 | } else { |
98795158 | 202 | eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM; |
05909bab | 203 | sq->stats->csum_partial++; |
89db09eb | 204 | } |
98795158 | 205 | } else |
05909bab | 206 | sq->stats->csum_none++; |
77bdf895 | 207 | } |
e586b3b0 | 208 | |
77bdf895 | 209 | static inline u16 |
043dc78e | 210 | mlx5e_tx_get_gso_ihs(struct mlx5e_txqsq *sq, struct sk_buff *skb) |
77bdf895 | 211 | { |
05909bab | 212 | struct mlx5e_sq_stats *stats = sq->stats; |
77bdf895 | 213 | u16 ihs; |
98795158 | 214 | |
77bdf895 SM |
215 | if (skb->encapsulation) { |
216 | ihs = skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb); | |
05909bab EBE |
217 | stats->tso_inner_packets++; |
218 | stats->tso_inner_bytes += skb->len - ihs; | |
e586b3b0 | 219 | } else { |
689adf0d BP |
220 | if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) |
221 | ihs = skb_transport_offset(skb) + sizeof(struct udphdr); | |
222 | else | |
223 | ihs = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
05909bab EBE |
224 | stats->tso_packets++; |
225 | stats->tso_bytes += skb->len - ihs; | |
e586b3b0 AV |
226 | } |
227 | ||
77bdf895 SM |
228 | return ihs; |
229 | } | |
e586b3b0 | 230 | |
77bdf895 SM |
231 | static inline int |
232 | mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq *sq, struct sk_buff *skb, | |
233 | unsigned char *skb_data, u16 headlen, | |
234 | struct mlx5_wqe_data_seg *dseg) | |
235 | { | |
236 | dma_addr_t dma_addr = 0; | |
237 | u8 num_dma = 0; | |
238 | int i; | |
e586b3b0 | 239 | |
e586b3b0 | 240 | if (headlen) { |
34802a42 | 241 | dma_addr = dma_map_single(sq->pdev, skb_data, headlen, |
e586b3b0 AV |
242 | DMA_TO_DEVICE); |
243 | if (unlikely(dma_mapping_error(sq->pdev, dma_addr))) | |
d9a96ec3 | 244 | goto dma_unmap_wqe_err; |
e586b3b0 AV |
245 | |
246 | dseg->addr = cpu_to_be64(dma_addr); | |
247 | dseg->lkey = sq->mkey_be; | |
248 | dseg->byte_count = cpu_to_be32(headlen); | |
249 | ||
d4e28cbd | 250 | mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE); |
77bdf895 | 251 | num_dma++; |
e586b3b0 AV |
252 | dseg++; |
253 | } | |
254 | ||
255 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
256 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; | |
257 | int fsz = skb_frag_size(frag); | |
258 | ||
259 | dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz, | |
e53eef63 | 260 | DMA_TO_DEVICE); |
e586b3b0 | 261 | if (unlikely(dma_mapping_error(sq->pdev, dma_addr))) |
d9a96ec3 | 262 | goto dma_unmap_wqe_err; |
e586b3b0 AV |
263 | |
264 | dseg->addr = cpu_to_be64(dma_addr); | |
265 | dseg->lkey = sq->mkey_be; | |
266 | dseg->byte_count = cpu_to_be32(fsz); | |
267 | ||
d4e28cbd | 268 | mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE); |
77bdf895 | 269 | num_dma++; |
e586b3b0 AV |
270 | dseg++; |
271 | } | |
272 | ||
77bdf895 | 273 | return num_dma; |
d9a96ec3 TT |
274 | |
275 | dma_unmap_wqe_err: | |
276 | mlx5e_dma_unmap_wqe_err(sq, num_dma); | |
277 | return -ENOMEM; | |
77bdf895 | 278 | } |
e586b3b0 | 279 | |
3a2f7033 TT |
280 | static inline void mlx5e_fill_sq_frag_edge(struct mlx5e_txqsq *sq, |
281 | struct mlx5_wq_cyc *wq, | |
37fdffb2 | 282 | u16 pi, u16 nnops) |
043dc78e TT |
283 | { |
284 | struct mlx5e_tx_wqe_info *edge_wi, *wi = &sq->db.wqe_info[pi]; | |
043dc78e TT |
285 | |
286 | edge_wi = wi + nnops; | |
287 | ||
3a2f7033 | 288 | /* fill sq frag edge with nops to avoid wqe wrapping two pages */ |
043dc78e TT |
289 | for (; wi < edge_wi; wi++) { |
290 | wi->skb = NULL; | |
291 | wi->num_wqebbs = 1; | |
292 | mlx5e_post_nop(wq, sq->sqn, &sq->pc); | |
293 | } | |
05909bab | 294 | sq->stats->nop += nnops; |
043dc78e TT |
295 | } |
296 | ||
77bdf895 SM |
297 | static inline void |
298 | mlx5e_txwqe_complete(struct mlx5e_txqsq *sq, struct sk_buff *skb, | |
043dc78e | 299 | u8 opcode, u16 ds_cnt, u8 num_wqebbs, u32 num_bytes, u8 num_dma, |
77bdf895 SM |
300 | struct mlx5e_tx_wqe_info *wi, struct mlx5_wqe_ctrl_seg *cseg) |
301 | { | |
302 | struct mlx5_wq_cyc *wq = &sq->wq; | |
e586b3b0 | 303 | |
77bdf895 SM |
304 | wi->num_bytes = num_bytes; |
305 | wi->num_dma = num_dma; | |
043dc78e | 306 | wi->num_wqebbs = num_wqebbs; |
77bdf895 | 307 | wi->skb = skb; |
e586b3b0 | 308 | |
77bdf895 SM |
309 | cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode); |
310 | cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt); | |
311 | ||
312 | netdev_tx_sent_queue(sq->txq, num_bytes); | |
e586b3b0 | 313 | |
ef9814de EBE |
314 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) |
315 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
316 | ||
77bdf895 SM |
317 | sq->pc += wi->num_wqebbs; |
318 | if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, MLX5E_SQ_STOP_ROOM))) { | |
e586b3b0 | 319 | netif_tx_stop_queue(sq->txq); |
05909bab | 320 | sq->stats->stopped++; |
e586b3b0 AV |
321 | } |
322 | ||
864b2d71 SM |
323 | if (!skb->xmit_more || netif_xmit_stopped(sq->txq)) |
324 | mlx5e_notify_hw(wq, sq->pc, sq->uar_map, cseg); | |
77bdf895 SM |
325 | } |
326 | ||
043dc78e TT |
327 | #define INL_HDR_START_SZ (sizeof(((struct mlx5_wqe_eth_seg *)NULL)->inline_hdr.start)) |
328 | ||
bf239741 IL |
329 | netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb, |
330 | struct mlx5e_tx_wqe *wqe, u16 pi) | |
77bdf895 | 331 | { |
043dc78e TT |
332 | struct mlx5_wq_cyc *wq = &sq->wq; |
333 | struct mlx5_wqe_ctrl_seg *cseg; | |
334 | struct mlx5_wqe_eth_seg *eseg; | |
335 | struct mlx5_wqe_data_seg *dseg; | |
336 | struct mlx5e_tx_wqe_info *wi; | |
77bdf895 | 337 | |
05909bab | 338 | struct mlx5e_sq_stats *stats = sq->stats; |
37fdffb2 | 339 | u16 headlen, ihs, contig_wqebbs_room; |
043dc78e TT |
340 | u16 ds_cnt, ds_cnt_inl = 0; |
341 | u8 num_wqebbs, opcode; | |
043dc78e | 342 | u32 num_bytes; |
77bdf895 | 343 | int num_dma; |
043dc78e | 344 | __be16 mss; |
77bdf895 | 345 | |
043dc78e TT |
346 | /* Calc ihs and ds cnt, no writes to wqe yet */ |
347 | ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS; | |
77bdf895 | 348 | if (skb_is_gso(skb)) { |
043dc78e TT |
349 | opcode = MLX5_OPCODE_LSO; |
350 | mss = cpu_to_be16(skb_shinfo(skb)->gso_size); | |
351 | ihs = mlx5e_tx_get_gso_ihs(sq, skb); | |
352 | num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs; | |
05909bab | 353 | stats->packets += skb_shinfo(skb)->gso_segs; |
77bdf895 | 354 | } else { |
043dc78e TT |
355 | opcode = MLX5_OPCODE_SEND; |
356 | mss = 0; | |
357 | ihs = mlx5e_calc_min_inline(sq->min_inline_mode, skb); | |
77bdf895 | 358 | num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); |
05909bab | 359 | stats->packets++; |
77bdf895 | 360 | } |
043dc78e | 361 | |
05909bab EBE |
362 | stats->bytes += num_bytes; |
363 | stats->xmit_more += skb->xmit_more; | |
77bdf895 | 364 | |
5e7d77a9 | 365 | headlen = skb->len - ihs - skb->data_len; |
043dc78e TT |
366 | ds_cnt += !!headlen; |
367 | ds_cnt += skb_shinfo(skb)->nr_frags; | |
368 | ||
369 | if (ihs) { | |
370 | ihs += !!skb_vlan_tag_present(skb) * VLAN_HLEN; | |
371 | ||
372 | ds_cnt_inl = DIV_ROUND_UP(ihs - INL_HDR_START_SZ, MLX5_SEND_WQE_DS); | |
373 | ds_cnt += ds_cnt_inl; | |
374 | } | |
375 | ||
376 | num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS); | |
37fdffb2 TT |
377 | contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi); |
378 | if (unlikely(contig_wqebbs_room < num_wqebbs)) { | |
82eaa1fa RS |
379 | #ifdef CONFIG_MLX5_EN_IPSEC |
380 | struct mlx5_wqe_eth_seg cur_eth = wqe->eth; | |
381 | #endif | |
37fdffb2 | 382 | mlx5e_fill_sq_frag_edge(sq, wq, pi, contig_wqebbs_room); |
043dc78e | 383 | mlx5e_sq_fetch_wqe(sq, &wqe, &pi); |
82eaa1fa RS |
384 | #ifdef CONFIG_MLX5_EN_IPSEC |
385 | wqe->eth = cur_eth; | |
386 | #endif | |
043dc78e TT |
387 | } |
388 | ||
389 | /* fill wqe */ | |
390 | wi = &sq->db.wqe_info[pi]; | |
391 | cseg = &wqe->ctrl; | |
392 | eseg = &wqe->eth; | |
393 | dseg = wqe->data; | |
394 | ||
395 | mlx5e_txwqe_build_eseg_csum(sq, skb, eseg); | |
396 | ||
397 | eseg->mss = mss; | |
398 | ||
77bdf895 | 399 | if (ihs) { |
5e7d77a9 | 400 | eseg->inline_hdr.sz = cpu_to_be16(ihs); |
77bdf895 | 401 | if (skb_vlan_tag_present(skb)) { |
5e7d77a9 TT |
402 | ihs -= VLAN_HLEN; |
403 | mlx5e_insert_vlan(eseg->inline_hdr.start, skb, ihs); | |
05909bab | 404 | stats->added_vlan_packets++; |
77bdf895 | 405 | } else { |
5e7d77a9 | 406 | memcpy(eseg->inline_hdr.start, skb->data, ihs); |
77bdf895 | 407 | } |
043dc78e | 408 | dseg += ds_cnt_inl; |
77bdf895 SM |
409 | } else if (skb_vlan_tag_present(skb)) { |
410 | eseg->insert.type = cpu_to_be16(MLX5_ETH_WQE_INSERT_VLAN); | |
4382c7b9 GP |
411 | if (skb->vlan_proto == cpu_to_be16(ETH_P_8021AD)) |
412 | eseg->insert.type |= cpu_to_be16(MLX5_ETH_WQE_SVLAN); | |
77bdf895 | 413 | eseg->insert.vlan_tci = cpu_to_be16(skb_vlan_tag_get(skb)); |
05909bab | 414 | stats->added_vlan_packets++; |
77bdf895 SM |
415 | } |
416 | ||
5e7d77a9 | 417 | num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + ihs, headlen, dseg); |
77bdf895 | 418 | if (unlikely(num_dma < 0)) |
d9a96ec3 | 419 | goto err_drop; |
77bdf895 | 420 | |
043dc78e TT |
421 | mlx5e_txwqe_complete(sq, skb, opcode, ds_cnt, num_wqebbs, num_bytes, |
422 | num_dma, wi, cseg); | |
12be4b21 | 423 | |
e586b3b0 AV |
424 | return NETDEV_TX_OK; |
425 | ||
d9a96ec3 | 426 | err_drop: |
05909bab | 427 | stats->dropped++; |
e586b3b0 AV |
428 | dev_kfree_skb_any(skb); |
429 | ||
430 | return NETDEV_TX_OK; | |
431 | } | |
432 | ||
433 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev) | |
434 | { | |
435 | struct mlx5e_priv *priv = netdev_priv(dev); | |
bf239741 IL |
436 | struct mlx5e_tx_wqe *wqe; |
437 | struct mlx5e_txqsq *sq; | |
438 | u16 pi; | |
2ac9cfe7 | 439 | |
bf239741 IL |
440 | sq = priv->txq2sq[skb_get_queue_mapping(skb)]; |
441 | mlx5e_sq_fetch_wqe(sq, &wqe, &pi); | |
2ac9cfe7 | 442 | |
bf239741 IL |
443 | /* might send skbs and update wqe and pi */ |
444 | skb = mlx5e_accel_handle_tx(skb, sq, dev, &wqe, &pi); | |
445 | if (unlikely(!skb)) | |
446 | return NETDEV_TX_OK; | |
689adf0d | 447 | |
2ac9cfe7 | 448 | return mlx5e_sq_xmit(sq, skb, wqe, pi); |
e586b3b0 AV |
449 | } |
450 | ||
16cc14d8 EBE |
451 | static void mlx5e_dump_error_cqe(struct mlx5e_txqsq *sq, |
452 | struct mlx5_err_cqe *err_cqe) | |
453 | { | |
454 | u32 ci = mlx5_cqwq_get_ci(&sq->cq.wq); | |
455 | ||
456 | netdev_err(sq->channel->netdev, | |
e05b8d4f TT |
457 | "Error cqe on cqn 0x%x, ci 0x%x, sqn 0x%x, opcode 0x%x, syndrome 0x%x, vendor syndrome 0x%x\n", |
458 | sq->cq.mcq.cqn, ci, sq->sqn, | |
459 | get_cqe_opcode((struct mlx5_cqe64 *)err_cqe), | |
460 | err_cqe->syndrome, err_cqe->vendor_err_synd); | |
16cc14d8 EBE |
461 | mlx5_dump_err_cqe(sq->cq.mdev, err_cqe); |
462 | } | |
463 | ||
8ec736e5 | 464 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget) |
e586b3b0 | 465 | { |
86155656 | 466 | struct mlx5e_sq_stats *stats; |
31391048 | 467 | struct mlx5e_txqsq *sq; |
4b7dfc99 | 468 | struct mlx5_cqe64 *cqe; |
e586b3b0 AV |
469 | u32 dma_fifo_cc; |
470 | u32 nbytes; | |
471 | u16 npkts; | |
472 | u16 sqcc; | |
473 | int i; | |
474 | ||
31391048 | 475 | sq = container_of(cq, struct mlx5e_txqsq, cq); |
e586b3b0 | 476 | |
0e5c04f6 | 477 | if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state))) |
29429f33 DJ |
478 | return false; |
479 | ||
4b7dfc99 TT |
480 | cqe = mlx5_cqwq_get_cqe(&cq->wq); |
481 | if (!cqe) | |
482 | return false; | |
483 | ||
86155656 TT |
484 | stats = sq->stats; |
485 | ||
e586b3b0 AV |
486 | npkts = 0; |
487 | nbytes = 0; | |
488 | ||
489 | /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), | |
490 | * otherwise a cq overrun may occur | |
491 | */ | |
492 | sqcc = sq->cc; | |
493 | ||
494 | /* avoid dirtying sq cache line every cqe */ | |
495 | dma_fifo_cc = sq->dma_fifo_cc; | |
496 | ||
4b7dfc99 TT |
497 | i = 0; |
498 | do { | |
059ba072 AS |
499 | u16 wqe_counter; |
500 | bool last_wqe; | |
e586b3b0 | 501 | |
a1f5a1a8 AS |
502 | mlx5_cqwq_pop(&cq->wq); |
503 | ||
059ba072 AS |
504 | wqe_counter = be16_to_cpu(cqe->wqe_counter); |
505 | ||
6254adeb | 506 | if (unlikely(get_cqe_opcode(cqe) == MLX5_CQE_REQ_ERR)) { |
db75373c EBE |
507 | if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING, |
508 | &sq->state)) { | |
16cc14d8 EBE |
509 | mlx5e_dump_error_cqe(sq, |
510 | (struct mlx5_err_cqe *)cqe); | |
2c493ae0 EBE |
511 | queue_work(cq->channel->priv->wq, |
512 | &sq->recover_work); | |
db75373c | 513 | } |
86155656 | 514 | stats->cqe_err++; |
16cc14d8 EBE |
515 | } |
516 | ||
059ba072 | 517 | do { |
34802a42 | 518 | struct mlx5e_tx_wqe_info *wi; |
059ba072 AS |
519 | struct sk_buff *skb; |
520 | u16 ci; | |
521 | int j; | |
522 | ||
523 | last_wqe = (sqcc == wqe_counter); | |
524 | ||
ddf385e3 | 525 | ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc); |
31391048 | 526 | wi = &sq->db.wqe_info[ci]; |
77bdf895 | 527 | skb = wi->skb; |
e586b3b0 | 528 | |
059ba072 | 529 | if (unlikely(!skb)) { /* nop */ |
059ba072 AS |
530 | sqcc++; |
531 | continue; | |
532 | } | |
e586b3b0 | 533 | |
ef9814de EBE |
534 | if (unlikely(skb_shinfo(skb)->tx_flags & |
535 | SKBTX_HW_TSTAMP)) { | |
536 | struct skb_shared_hwtstamps hwts = {}; | |
537 | ||
7c39afb3 FD |
538 | hwts.hwtstamp = |
539 | mlx5_timecounter_cyc2time(sq->clock, | |
540 | get_cqe_ts(cqe)); | |
ef9814de EBE |
541 | skb_tstamp_tx(skb, &hwts); |
542 | } | |
543 | ||
34802a42 | 544 | for (j = 0; j < wi->num_dma; j++) { |
d4e28cbd AS |
545 | struct mlx5e_sq_dma *dma = |
546 | mlx5e_dma_get(sq, dma_fifo_cc++); | |
e586b3b0 | 547 | |
d4e28cbd | 548 | mlx5e_tx_dma_unmap(sq->pdev, dma); |
059ba072 | 549 | } |
e586b3b0 | 550 | |
059ba072 | 551 | npkts++; |
34802a42 AS |
552 | nbytes += wi->num_bytes; |
553 | sqcc += wi->num_wqebbs; | |
8ec736e5 | 554 | napi_consume_skb(skb, napi_budget); |
059ba072 | 555 | } while (!last_wqe); |
4b7dfc99 TT |
556 | |
557 | } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); | |
e586b3b0 | 558 | |
86155656 TT |
559 | stats->cqes += i; |
560 | ||
e586b3b0 AV |
561 | mlx5_cqwq_update_db_record(&cq->wq); |
562 | ||
563 | /* ensure cq space is freed before enabling more cqes */ | |
564 | wmb(); | |
565 | ||
566 | sq->dma_fifo_cc = dma_fifo_cc; | |
567 | sq->cc = sqcc; | |
568 | ||
569 | netdev_tx_completed_queue(sq->txq, npkts, nbytes); | |
570 | ||
571 | if (netif_tx_queue_stopped(sq->txq) && | |
db75373c EBE |
572 | mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, |
573 | MLX5E_SQ_STOP_ROOM) && | |
574 | !test_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state)) { | |
6e8dd6d6 | 575 | netif_tx_wake_queue(sq->txq); |
86155656 | 576 | stats->wake++; |
e586b3b0 | 577 | } |
e586b3b0 | 578 | |
59a7c2fd | 579 | return (i == MLX5E_TX_CQ_POLL_BUDGET); |
e586b3b0 | 580 | } |
6e8dd6d6 | 581 | |
31391048 | 582 | void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq) |
6e8dd6d6 SM |
583 | { |
584 | struct mlx5e_tx_wqe_info *wi; | |
585 | struct sk_buff *skb; | |
586 | u16 ci; | |
587 | int i; | |
588 | ||
589 | while (sq->cc != sq->pc) { | |
ddf385e3 | 590 | ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->cc); |
31391048 | 591 | wi = &sq->db.wqe_info[ci]; |
77bdf895 | 592 | skb = wi->skb; |
6e8dd6d6 SM |
593 | |
594 | if (!skb) { /* nop */ | |
595 | sq->cc++; | |
596 | continue; | |
597 | } | |
598 | ||
599 | for (i = 0; i < wi->num_dma; i++) { | |
600 | struct mlx5e_sq_dma *dma = | |
601 | mlx5e_dma_get(sq, sq->dma_fifo_cc++); | |
602 | ||
603 | mlx5e_tx_dma_unmap(sq->pdev, dma); | |
604 | } | |
605 | ||
606 | dev_kfree_skb_any(skb); | |
607 | sq->cc += wi->num_wqebbs; | |
608 | } | |
609 | } | |
25854544 SM |
610 | |
611 | #ifdef CONFIG_MLX5_CORE_IPOIB | |
25854544 SM |
612 | static inline void |
613 | mlx5i_txwqe_build_datagram(struct mlx5_av *av, u32 dqpn, u32 dqkey, | |
614 | struct mlx5_wqe_datagram_seg *dseg) | |
615 | { | |
616 | memcpy(&dseg->av, av, sizeof(struct mlx5_av)); | |
617 | dseg->av.dqp_dct = cpu_to_be32(dqpn | MLX5_EXTENDED_UD_AV); | |
618 | dseg->av.key.qkey.qkey = cpu_to_be32(dqkey); | |
619 | } | |
620 | ||
621 | netdev_tx_t mlx5i_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb, | |
622 | struct mlx5_av *av, u32 dqpn, u32 dqkey) | |
623 | { | |
043dc78e TT |
624 | struct mlx5_wq_cyc *wq = &sq->wq; |
625 | struct mlx5i_tx_wqe *wqe; | |
25854544 | 626 | |
043dc78e TT |
627 | struct mlx5_wqe_datagram_seg *datagram; |
628 | struct mlx5_wqe_ctrl_seg *cseg; | |
629 | struct mlx5_wqe_eth_seg *eseg; | |
630 | struct mlx5_wqe_data_seg *dseg; | |
631 | struct mlx5e_tx_wqe_info *wi; | |
25854544 | 632 | |
05909bab | 633 | struct mlx5e_sq_stats *stats = sq->stats; |
37fdffb2 | 634 | u16 headlen, ihs, pi, contig_wqebbs_room; |
043dc78e TT |
635 | u16 ds_cnt, ds_cnt_inl = 0; |
636 | u8 num_wqebbs, opcode; | |
043dc78e | 637 | u32 num_bytes; |
25854544 | 638 | int num_dma; |
043dc78e | 639 | __be16 mss; |
25854544 | 640 | |
043dc78e TT |
641 | /* Calc ihs and ds cnt, no writes to wqe yet */ |
642 | ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS; | |
25854544 | 643 | if (skb_is_gso(skb)) { |
043dc78e TT |
644 | opcode = MLX5_OPCODE_LSO; |
645 | mss = cpu_to_be16(skb_shinfo(skb)->gso_size); | |
646 | ihs = mlx5e_tx_get_gso_ihs(sq, skb); | |
647 | num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs; | |
05909bab | 648 | stats->packets += skb_shinfo(skb)->gso_segs; |
25854544 | 649 | } else { |
043dc78e TT |
650 | opcode = MLX5_OPCODE_SEND; |
651 | mss = 0; | |
652 | ihs = mlx5e_calc_min_inline(sq->min_inline_mode, skb); | |
25854544 | 653 | num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); |
05909bab | 654 | stats->packets++; |
25854544 SM |
655 | } |
656 | ||
05909bab EBE |
657 | stats->bytes += num_bytes; |
658 | stats->xmit_more += skb->xmit_more; | |
4ec5cf78 | 659 | |
5e7d77a9 | 660 | headlen = skb->len - ihs - skb->data_len; |
043dc78e TT |
661 | ds_cnt += !!headlen; |
662 | ds_cnt += skb_shinfo(skb)->nr_frags; | |
663 | ||
664 | if (ihs) { | |
665 | ds_cnt_inl = DIV_ROUND_UP(ihs - INL_HDR_START_SZ, MLX5_SEND_WQE_DS); | |
666 | ds_cnt += ds_cnt_inl; | |
667 | } | |
668 | ||
669 | num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS); | |
37fdffb2 TT |
670 | pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); |
671 | contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi); | |
672 | if (unlikely(contig_wqebbs_room < num_wqebbs)) { | |
673 | mlx5e_fill_sq_frag_edge(sq, wq, pi, contig_wqebbs_room); | |
4b3e85a5 | 674 | pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); |
043dc78e TT |
675 | } |
676 | ||
37fdffb2 | 677 | mlx5i_sq_fetch_wqe(sq, &wqe, pi); |
4b3e85a5 | 678 | |
043dc78e TT |
679 | /* fill wqe */ |
680 | wi = &sq->db.wqe_info[pi]; | |
681 | cseg = &wqe->ctrl; | |
682 | datagram = &wqe->datagram; | |
683 | eseg = &wqe->eth; | |
684 | dseg = wqe->data; | |
685 | ||
686 | mlx5i_txwqe_build_datagram(av, dqpn, dqkey, datagram); | |
687 | ||
688 | mlx5e_txwqe_build_eseg_csum(sq, skb, eseg); | |
689 | ||
690 | eseg->mss = mss; | |
691 | ||
25854544 | 692 | if (ihs) { |
5e7d77a9 | 693 | memcpy(eseg->inline_hdr.start, skb->data, ihs); |
25854544 | 694 | eseg->inline_hdr.sz = cpu_to_be16(ihs); |
043dc78e | 695 | dseg += ds_cnt_inl; |
25854544 SM |
696 | } |
697 | ||
5e7d77a9 | 698 | num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + ihs, headlen, dseg); |
25854544 | 699 | if (unlikely(num_dma < 0)) |
d9a96ec3 | 700 | goto err_drop; |
25854544 | 701 | |
043dc78e TT |
702 | mlx5e_txwqe_complete(sq, skb, opcode, ds_cnt, num_wqebbs, num_bytes, |
703 | num_dma, wi, cseg); | |
25854544 SM |
704 | |
705 | return NETDEV_TX_OK; | |
706 | ||
d9a96ec3 | 707 | err_drop: |
05909bab | 708 | stats->dropped++; |
25854544 SM |
709 | dev_kfree_skb_any(skb); |
710 | ||
711 | return NETDEV_TX_OK; | |
712 | } | |
25854544 | 713 | #endif |