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Merge tag 'io_uring-5.7-2020-05-22' of git://git.kernel.dk/linux-block
[thirdparty/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch_offloads.c
CommitLineData
69697b6e
OG		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
34#include <linux/mlx5/driver.h>
35#include <linux/mlx5/mlx5_ifc.h>
36#include <linux/mlx5/vport.h>
37#include <linux/mlx5/fs.h>
38#include "mlx5_core.h"
39#include "eswitch.h"
49964352 40#include "esw/chains.h"
80f09dfc 41#include "rdma.h"
e52c2802
PB		 42#include "en.h"
43#include "fs_core.h"
ac004b83 44#include "lib/devcom.h"
a3888f33 45#include "lib/eq.h"
69697b6e 46
cd7e4186
BW		 47/* There are two match-all miss flows, one for unicast dst mac and
48 * one for multicast.
49 */
50#define MLX5_ESW_MISS_FLOWS (2)
c9b99abc
BW		 51#define UPLINK_REP_INDEX 0
52
96e32687
EC		 53/* Per vport tables */
54
55#define MLX5_ESW_VPORT_TABLE_SIZE 128
56
57/* This struct is used as a key to the hash table and we need it to be packed
58 * so hash result is consistent
59 */
60struct mlx5_vport_key {
61 u32 chain;
62 u16 prio;
63 u16 vport;
64 u16 vhca_id;
65} __packed;
66
67struct mlx5_vport_table {
68 struct hlist_node hlist;
69 struct mlx5_flow_table *fdb;
70 u32 num_rules;
71 struct mlx5_vport_key key;
72};
73
87dac697
JL		 74#define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
75
96e32687
EC		 76static struct mlx5_flow_table *
77esw_vport_tbl_create(struct mlx5_eswitch *esw, struct mlx5_flow_namespace *ns)
78{
79 struct mlx5_flow_table_attr ft_attr = {};
80 struct mlx5_flow_table *fdb;
81
87dac697 82 ft_attr.autogroup.max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS;
96e32687
EC		 83 ft_attr.max_fte = MLX5_ESW_VPORT_TABLE_SIZE;
84 ft_attr.prio = FDB_PER_VPORT;
85 fdb = mlx5_create_auto_grouped_flow_table(ns, &ft_attr);
86 if (IS_ERR(fdb)) {
87 esw_warn(esw->dev, "Failed to create per vport FDB Table err %ld\n",
88 PTR_ERR(fdb));
89 }
90
91 return fdb;
92}
93
94static u32 flow_attr_to_vport_key(struct mlx5_eswitch *esw,
95 struct mlx5_esw_flow_attr *attr,
96 struct mlx5_vport_key *key)
97{
98 key->vport = attr->in_rep->vport;
99 key->chain = attr->chain;
100 key->prio = attr->prio;
101 key->vhca_id = MLX5_CAP_GEN(esw->dev, vhca_id);
102 return jhash(key, sizeof(*key), 0);
103}
104
105/* caller must hold vports.lock */
106static struct mlx5_vport_table *
107esw_vport_tbl_lookup(struct mlx5_eswitch *esw, struct mlx5_vport_key *skey, u32 key)
108{
109 struct mlx5_vport_table *e;
110
111 hash_for_each_possible(esw->fdb_table.offloads.vports.table, e, hlist, key)
112 if (!memcmp(&e->key, skey, sizeof(*skey)))
113 return e;
114
115 return NULL;
116}
117
118static void
119esw_vport_tbl_put(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *attr)
120{
121 struct mlx5_vport_table *e;
122 struct mlx5_vport_key key;
123 u32 hkey;
124
125 mutex_lock(&esw->fdb_table.offloads.vports.lock);
126 hkey = flow_attr_to_vport_key(esw, attr, &key);
127 e = esw_vport_tbl_lookup(esw, &key, hkey);
128 if (!e || --e->num_rules)
129 goto out;
130
131 hash_del(&e->hlist);
132 mlx5_destroy_flow_table(e->fdb);
133 kfree(e);
134out:
135 mutex_unlock(&esw->fdb_table.offloads.vports.lock);
136}
137
138static struct mlx5_flow_table *
139esw_vport_tbl_get(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *attr)
140{
141 struct mlx5_core_dev *dev = esw->dev;
142 struct mlx5_flow_namespace *ns;
143 struct mlx5_flow_table *fdb;
144 struct mlx5_vport_table *e;
145 struct mlx5_vport_key skey;
146 u32 hkey;
147
148 mutex_lock(&esw->fdb_table.offloads.vports.lock);
149 hkey = flow_attr_to_vport_key(esw, attr, &skey);
150 e = esw_vport_tbl_lookup(esw, &skey, hkey);
151 if (e) {
152 e->num_rules++;
153 goto out;
154 }
155
156 e = kzalloc(sizeof(*e), GFP_KERNEL);
157 if (!e) {
158 fdb = ERR_PTR(-ENOMEM);
159 goto err_alloc;
160 }
161
162 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
163 if (!ns) {
164 esw_warn(dev, "Failed to get FDB namespace\n");
165 fdb = ERR_PTR(-ENOENT);
166 goto err_ns;
167 }
168
169 fdb = esw_vport_tbl_create(esw, ns);
170 if (IS_ERR(fdb))
171 goto err_ns;
172
173 e->fdb = fdb;
174 e->num_rules = 1;
175 e->key = skey;
176 hash_add(esw->fdb_table.offloads.vports.table, &e->hlist, hkey);
177out:
178 mutex_unlock(&esw->fdb_table.offloads.vports.lock);
179 return e->fdb;
180
181err_ns:
182 kfree(e);
183err_alloc:
184 mutex_unlock(&esw->fdb_table.offloads.vports.lock);
185 return fdb;
186}
187
188int mlx5_esw_vport_tbl_get(struct mlx5_eswitch *esw)
189{
190 struct mlx5_esw_flow_attr attr = {};
191 struct mlx5_eswitch_rep rep = {};
192 struct mlx5_flow_table *fdb;
193 struct mlx5_vport *vport;
194 int i;
195
196 attr.prio = 1;
197 attr.in_rep = &rep;
198 mlx5_esw_for_all_vports(esw, i, vport) {
199 attr.in_rep->vport = vport->vport;
200 fdb = esw_vport_tbl_get(esw, &attr);
d9fb932f 201 if (IS_ERR(fdb))
96e32687
EC		 202 goto out;
203 }
204 return 0;
205
206out:
207 mlx5_esw_vport_tbl_put(esw);
208 return PTR_ERR(fdb);
209}
210
211void mlx5_esw_vport_tbl_put(struct mlx5_eswitch *esw)
212{
213 struct mlx5_esw_flow_attr attr = {};
214 struct mlx5_eswitch_rep rep = {};
215 struct mlx5_vport *vport;
216 int i;
217
218 attr.prio = 1;
219 attr.in_rep = &rep;
220 mlx5_esw_for_all_vports(esw, i, vport) {
221 attr.in_rep->vport = vport->vport;
222 esw_vport_tbl_put(esw, &attr);
223 }
224}
225
226/* End: Per vport tables */
227
879c8f84
BW		 228static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
229 u16 vport_num)
230{
02f3afd9 231 int idx = mlx5_eswitch_vport_num_to_index(esw, vport_num);
879c8f84
BW		 232
233 WARN_ON(idx > esw->total_vports - 1);
234 return &esw->offloads.vport_reps[idx];
235}
236
b7826076
PP		 237static bool
238esw_check_ingress_prio_tag_enabled(const struct mlx5_eswitch *esw,
239 const struct mlx5_vport *vport)
240{
241 return (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
242 mlx5_eswitch_is_vf_vport(esw, vport->vport));
243}
244
c01cfd0f
JL		 245static void
246mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
247 struct mlx5_flow_spec *spec,
248 struct mlx5_esw_flow_attr *attr)
249{
250 void *misc2;
251 void *misc;
252
253 /* Use metadata matching because vport is not represented by single
254 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
255 */
256 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
257 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
258 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
259 mlx5_eswitch_get_vport_metadata_for_match(attr->in_mdev->priv.eswitch,
260 attr->in_rep->vport));
261
262 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 263 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
264 mlx5_eswitch_get_vport_metadata_mask());
c01cfd0f
JL		 265
266 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
267 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
268 if (memchr_inv(misc, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc)))
269 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
270 } else {
271 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
272 MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport);
273
274 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
275 MLX5_SET(fte_match_set_misc, misc,
276 source_eswitch_owner_vhca_id,
277 MLX5_CAP_GEN(attr->in_mdev, vhca_id));
278
279 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
280 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
281 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
282 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
283 source_eswitch_owner_vhca_id);
284
285 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
286 }
287
288 if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
289 attr->in_rep->vport == MLX5_VPORT_UPLINK)
290 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK;
291}
292
74491de9 293struct mlx5_flow_handle *
3d80d1a2
OG		 294mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
295 struct mlx5_flow_spec *spec,
776b12b6 296 struct mlx5_esw_flow_attr *attr)
3d80d1a2 297{
592d3651 298 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 299 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
e85e02ba 300 bool split = !!(attr->split_count);
74491de9 301 struct mlx5_flow_handle *rule;
e52c2802 302 struct mlx5_flow_table *fdb;
592d3651 303 int j, i = 0;
3d80d1a2 304
f6455de0 305 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
3d80d1a2
OG		 306 return ERR_PTR(-EOPNOTSUPP);
307
6acfbf38
OG		 308 flow_act.action = attr->action;
309 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
cc495188 310 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 311 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
312 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
313 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
1482bd3d
JL		 314 flow_act.vlan[0].ethtype = ntohs(attr->vlan_proto[0]);
315 flow_act.vlan[0].vid = attr->vlan_vid[0];
316 flow_act.vlan[0].prio = attr->vlan_prio[0];
cc495188
JL		 317 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
318 flow_act.vlan[1].ethtype = ntohs(attr->vlan_proto[1]);
319 flow_act.vlan[1].vid = attr->vlan_vid[1];
320 flow_act.vlan[1].prio = attr->vlan_prio[1];
321 }
6acfbf38 322 }
776b12b6 323
66958ed9 324 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
39ac237c 325 struct mlx5_flow_table *ft;
e52c2802 326
d18296ff
PB		 327 if (attr->dest_ft) {
328 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
329 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
330 dest[i].ft = attr->dest_ft;
331 i++;
332 } else if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) {
39ac237c
PB		 333 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
334 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
278d51f2 335 dest[i].ft = mlx5_esw_chains_get_tc_end_ft(esw);
39ac237c
PB		 336 i++;
337 } else if (attr->dest_chain) {
338 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
339 ft = mlx5_esw_chains_get_table(esw, attr->dest_chain,
340 1, 0);
e52c2802
PB		 341 if (IS_ERR(ft)) {
342 rule = ERR_CAST(ft);
343 goto err_create_goto_table;
344 }
345
346 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
347 dest[i].ft = ft;
592d3651 348 i++;
e52c2802 349 } else {
e85e02ba 350 for (j = attr->split_count; j < attr->out_count; j++) {
e52c2802 351 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
df65a573 352 dest[i].vport.num = attr->dests[j].rep->vport;
e52c2802 353 dest[i].vport.vhca_id =
df65a573 354 MLX5_CAP_GEN(attr->dests[j].mdev, vhca_id);
aa39c2c0
EB		 355 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
356 dest[i].vport.flags |=
357 MLX5_FLOW_DEST_VPORT_VHCA_ID;
f493f155
EB		 358 if (attr->dests[j].flags & MLX5_ESW_DEST_ENCAP) {
359 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2b688ea5 360 flow_act.pkt_reformat = attr->dests[j].pkt_reformat;
a18e879d 361 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
2b688ea5
MG		 362 dest[i].vport.pkt_reformat =
363 attr->dests[j].pkt_reformat;
f493f155 364 }
e52c2802
PB		 365 i++;
366 }
56e858df 367 }
e37a79e5 368 }
66958ed9 369 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
e37a79e5 370 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 371 dest[i].counter_id = mlx5_fc_id(attr->counter);
e37a79e5 372 i++;
3d80d1a2
OG		 373 }
374
93b3586e 375 if (attr->outer_match_level != MLX5_MATCH_NONE)
6363651d 376 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
93b3586e
HN		 377 if (attr->inner_match_level != MLX5_MATCH_NONE)
378 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
3d80d1a2 379
aa24670e 380 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 381 flow_act.modify_hdr = attr->modify_hdr;
d7e75a32 382
96e32687
EC		 383 if (split) {
384 fdb = esw_vport_tbl_get(esw, attr);
385 } else {
d18296ff
PB		 386 if (attr->chain || attr->prio)
387 fdb = mlx5_esw_chains_get_table(esw, attr->chain,
388 attr->prio, 0);
389 else
390 fdb = attr->fdb;
6fb0701a
PB		 391
392 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_NO_IN_PORT))
393 mlx5_eswitch_set_rule_source_port(esw, spec, attr);
96e32687 394 }
e52c2802
PB		 395 if (IS_ERR(fdb)) {
396 rule = ERR_CAST(fdb);
397 goto err_esw_get;
398 }
399
84be2fda 400 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
10caabda
OS		 401 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, attr,
402 &flow_act, dest, i);
84be2fda 403 else
10caabda 404 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
3d80d1a2 405 if (IS_ERR(rule))
e52c2802 406 goto err_add_rule;
375f51e2 407 else
525e84be 408 atomic64_inc(&esw->offloads.num_flows);
3d80d1a2 409
e52c2802
PB		 410 return rule;
411
412err_add_rule:
96e32687
EC		 413 if (split)
414 esw_vport_tbl_put(esw, attr);
d18296ff 415 else if (attr->chain || attr->prio)
96e32687 416 mlx5_esw_chains_put_table(esw, attr->chain, attr->prio, 0);
e52c2802 417err_esw_get:
39ac237c
PB		 418 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) && attr->dest_chain)
419 mlx5_esw_chains_put_table(esw, attr->dest_chain, 1, 0);
e52c2802 420err_create_goto_table:
aa0cbbae 421 return rule;
3d80d1a2
OG		 422}
423
e4ad91f2
CM		 424struct mlx5_flow_handle *
425mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
426 struct mlx5_flow_spec *spec,
427 struct mlx5_esw_flow_attr *attr)
428{
429 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
42f7ad67 430 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
e52c2802
PB		 431 struct mlx5_flow_table *fast_fdb;
432 struct mlx5_flow_table *fwd_fdb;
e4ad91f2 433 struct mlx5_flow_handle *rule;
e4ad91f2
CM		 434 int i;
435
39ac237c 436 fast_fdb = mlx5_esw_chains_get_table(esw, attr->chain, attr->prio, 0);
e52c2802
PB		 437 if (IS_ERR(fast_fdb)) {
438 rule = ERR_CAST(fast_fdb);
439 goto err_get_fast;
440 }
441
96e32687 442 fwd_fdb = esw_vport_tbl_get(esw, attr);
e52c2802
PB		 443 if (IS_ERR(fwd_fdb)) {
444 rule = ERR_CAST(fwd_fdb);
445 goto err_get_fwd;
446 }
447
e4ad91f2 448 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e85e02ba 449 for (i = 0; i < attr->split_count; i++) {
e4ad91f2 450 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
df65a573 451 dest[i].vport.num = attr->dests[i].rep->vport;
e4ad91f2 452 dest[i].vport.vhca_id =
df65a573 453 MLX5_CAP_GEN(attr->dests[i].mdev, vhca_id);
aa39c2c0
EB		 454 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
455 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
1cc26d74
EB		 456 if (attr->dests[i].flags & MLX5_ESW_DEST_ENCAP) {
457 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
2b688ea5 458 dest[i].vport.pkt_reformat = attr->dests[i].pkt_reformat;
1cc26d74 459 }
e4ad91f2
CM		 460 }
461 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
e52c2802 462 dest[i].ft = fwd_fdb,
e4ad91f2
CM		 463 i++;
464
c01cfd0f 465 mlx5_eswitch_set_rule_source_port(esw, spec, attr);
e4ad91f2 466
93b3586e 467 if (attr->outer_match_level != MLX5_MATCH_NONE)
c01cfd0f 468 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
e4ad91f2 469
278d51f2 470 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
e52c2802 471 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
e4ad91f2 472
e52c2802
PB		 473 if (IS_ERR(rule))
474 goto add_err;
e4ad91f2 475
525e84be 476 atomic64_inc(&esw->offloads.num_flows);
e52c2802
PB		 477
478 return rule;
479add_err:
96e32687 480 esw_vport_tbl_put(esw, attr);
e52c2802 481err_get_fwd:
39ac237c 482 mlx5_esw_chains_put_table(esw, attr->chain, attr->prio, 0);
e52c2802 483err_get_fast:
e4ad91f2
CM		 484 return rule;
485}
486
e52c2802
PB		 487static void
488__mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
489 struct mlx5_flow_handle *rule,
490 struct mlx5_esw_flow_attr *attr,
491 bool fwd_rule)
492{
e85e02ba 493 bool split = (attr->split_count > 0);
10caabda 494 int i;
e52c2802
PB		 495
496 mlx5_del_flow_rules(rule);
10caabda 497
84be2fda 498 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
d8a2034f
EC		 499 /* unref the term table */
500 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
501 if (attr->dests[i].termtbl)
502 mlx5_eswitch_termtbl_put(esw, attr->dests[i].termtbl);
503 }
10caabda
OS		 504 }
505
525e84be 506 atomic64_dec(&esw->offloads.num_flows);
e52c2802
PB		 507
508 if (fwd_rule) {
96e32687 509 esw_vport_tbl_put(esw, attr);
39ac237c 510 mlx5_esw_chains_put_table(esw, attr->chain, attr->prio, 0);
e52c2802 511 } else {
96e32687
EC		 512 if (split)
513 esw_vport_tbl_put(esw, attr);
d18296ff 514 else if (attr->chain || attr->prio)
96e32687
EC		 515 mlx5_esw_chains_put_table(esw, attr->chain, attr->prio,
516 0);
e52c2802 517 if (attr->dest_chain)
39ac237c 518 mlx5_esw_chains_put_table(esw, attr->dest_chain, 1, 0);
e52c2802
PB		 519 }
520}
521
d85cdccb
OG		 522void
523mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
524 struct mlx5_flow_handle *rule,
525 struct mlx5_esw_flow_attr *attr)
526{
e52c2802 527 __mlx5_eswitch_del_rule(esw, rule, attr, false);
d85cdccb
OG		 528}
529
48265006
OG		 530void
531mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
532 struct mlx5_flow_handle *rule,
533 struct mlx5_esw_flow_attr *attr)
534{
e52c2802 535 __mlx5_eswitch_del_rule(esw, rule, attr, true);
48265006
OG		 536}
537
f5f82476
OG		 538static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
539{
540 struct mlx5_eswitch_rep *rep;
411ec9e0 541 int i, err = 0;
f5f82476
OG		 542
543 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
411ec9e0 544 mlx5_esw_for_each_host_func_rep(esw, i, rep, esw->esw_funcs.num_vfs) {
8693115a 545 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
f5f82476
OG		 546 continue;
547
548 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
549 if (err)
550 goto out;
551 }
552
553out:
554 return err;
555}
556
557static struct mlx5_eswitch_rep *
558esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
559{
560 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
561
562 in_rep = attr->in_rep;
df65a573 563 out_rep = attr->dests[0].rep;
f5f82476
OG		 564
565 if (push)
566 vport = in_rep;
567 else if (pop)
568 vport = out_rep;
569 else
570 vport = in_rep;
571
572 return vport;
573}
574
575static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
576 bool push, bool pop, bool fwd)
577{
578 struct mlx5_eswitch_rep *in_rep, *out_rep;
579
580 if ((push || pop) && !fwd)
581 goto out_notsupp;
582
583 in_rep = attr->in_rep;
df65a573 584 out_rep = attr->dests[0].rep;
f5f82476 585
b05af6aa 586 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 587 goto out_notsupp;
588
b05af6aa 589 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 590 goto out_notsupp;
591
592 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
593 if (!push && !pop && fwd)
b05af6aa 594 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 595 goto out_notsupp;
596
597 /* protects against (1) setting rules with different vlans to push and
598 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
599 */
1482bd3d 600 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
f5f82476
OG		 601 goto out_notsupp;
602
603 return 0;
604
605out_notsupp:
9eb78923 606 return -EOPNOTSUPP;
f5f82476
OG		 607}
608
609int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
610 struct mlx5_esw_flow_attr *attr)
611{
612 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
613 struct mlx5_eswitch_rep *vport = NULL;
614 bool push, pop, fwd;
615 int err = 0;
616
6acfbf38 617 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 618 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 619 return 0;
620
f5f82476
OG		 621 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
622 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
e52c2802
PB		 623 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
624 !attr->dest_chain);
f5f82476 625
0e18134f
VB		 626 mutex_lock(&esw->state_lock);
627
f5f82476
OG		 628 err = esw_add_vlan_action_check(attr, push, pop, fwd);
629 if (err)
0e18134f 630 goto unlock;
f5f82476 631
39ac237c 632 attr->flags &= ~MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476
OG		 633
634 vport = esw_vlan_action_get_vport(attr, push, pop);
635
636 if (!push && !pop && fwd) {
637 /* tracks VF --> wire rules without vlan push action */
b05af6aa 638 if (attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
f5f82476 639 vport->vlan_refcount++;
39ac237c 640 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
f5f82476
OG		 641 }
642
0e18134f 643 goto unlock;
f5f82476
OG		 644 }
645
646 if (!push && !pop)
0e18134f 647 goto unlock;
f5f82476
OG		 648
649 if (!(offloads->vlan_push_pop_refcount)) {
650 /* it's the 1st vlan rule, apply global vlan pop policy */
651 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
652 if (err)
653 goto out;
654 }
655 offloads->vlan_push_pop_refcount++;
656
657 if (push) {
658 if (vport->vlan_refcount)
659 goto skip_set_push;
660
1482bd3d 661 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, attr->vlan_vid[0], 0,
f5f82476
OG		 662 SET_VLAN_INSERT | SET_VLAN_STRIP);
663 if (err)
664 goto out;
1482bd3d 665 vport->vlan = attr->vlan_vid[0];
f5f82476
OG		 666skip_set_push:
667 vport->vlan_refcount++;
668 }
669out:
670 if (!err)
39ac237c 671 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
0e18134f
VB		 672unlock:
673 mutex_unlock(&esw->state_lock);
f5f82476
OG		 674 return err;
675}
676
677int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
678 struct mlx5_esw_flow_attr *attr)
679{
680 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
681 struct mlx5_eswitch_rep *vport = NULL;
682 bool push, pop, fwd;
683 int err = 0;
684
6acfbf38 685 /* nop if we're on the vlan push/pop non emulation mode */
cc495188 686 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
6acfbf38
OG		 687 return 0;
688
39ac237c 689 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_VLAN_HANDLED))
f5f82476
OG		 690 return 0;
691
692 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
693 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
694 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
695
0e18134f
VB		 696 mutex_lock(&esw->state_lock);
697
f5f82476
OG		 698 vport = esw_vlan_action_get_vport(attr, push, pop);
699
700 if (!push && !pop && fwd) {
701 /* tracks VF --> wire rules without vlan push action */
b05af6aa 702 if (attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
f5f82476
OG		 703 vport->vlan_refcount--;
704
0e18134f 705 goto out;
f5f82476
OG		 706 }
707
708 if (push) {
709 vport->vlan_refcount--;
710 if (vport->vlan_refcount)
711 goto skip_unset_push;
712
713 vport->vlan = 0;
714 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
715 0, 0, SET_VLAN_STRIP);
716 if (err)
717 goto out;
718 }
719
720skip_unset_push:
721 offloads->vlan_push_pop_refcount--;
722 if (offloads->vlan_push_pop_refcount)
0e18134f 723 goto out;
f5f82476
OG		 724
725 /* no more vlan rules, stop global vlan pop policy */
726 err = esw_set_global_vlan_pop(esw, 0);
727
728out:
0e18134f 729 mutex_unlock(&esw->state_lock);
f5f82476
OG		 730 return err;
731}
732
f7a68945 733struct mlx5_flow_handle *
02f3afd9
PP		 734mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, u16 vport,
735 u32 sqn)
ab22be9b 736{
66958ed9 737 struct mlx5_flow_act flow_act = {0};
4c5009c5 738 struct mlx5_flow_destination dest = {};
74491de9 739 struct mlx5_flow_handle *flow_rule;
c5bb1730 740 struct mlx5_flow_spec *spec;
ab22be9b
OG		 741 void *misc;
742
1b9a07ee 743 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 744 if (!spec) {
ab22be9b
OG		 745 flow_rule = ERR_PTR(-ENOMEM);
746 goto out;
747 }
748
c5bb1730 749 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
ab22be9b 750 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
a1b3839a
BW		 751 /* source vport is the esw manager */
752 MLX5_SET(fte_match_set_misc, misc, source_port, esw->manager_vport);
ab22be9b 753
c5bb1730 754 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
ab22be9b
OG		 755 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
756 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
757
c5bb1730 758 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
ab22be9b 759 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
b17f7fc1 760 dest.vport.num = vport;
66958ed9 761 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
ab22be9b 762
39ac237c
PB		 763 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
764 spec, &flow_act, &dest, 1);
ab22be9b
OG		 765 if (IS_ERR(flow_rule))
766 esw_warn(esw->dev, "FDB: Failed to add send to vport rule err %ld\n", PTR_ERR(flow_rule));
767out:
c5bb1730 768 kvfree(spec);
ab22be9b
OG		 769 return flow_rule;
770}
57cbd893 771EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
ab22be9b 772
159fe639
MB		 773void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
774{
775 mlx5_del_flow_rules(rule);
776}
777
5b7cb745
PB		 778static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
779{
780 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
781 MLX5_FDB_TO_VPORT_REG_C_1;
782}
783
332bd3a5 784static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
c1286050
JL		 785{
786 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
787 u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
5b7cb745 788 u8 curr, wanted;
c1286050
JL		 789 int err;
790
5b7cb745
PB		 791 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
792 !mlx5_eswitch_vport_match_metadata_enabled(esw))
332bd3a5 793 return 0;
c1286050 794
238302fa 795 err = mlx5_eswitch_query_esw_vport_context(esw->dev, 0, false,
c1286050
JL		 796 out, sizeof(out));
797 if (err)
798 return err;
799
5b7cb745
PB		 800 curr = MLX5_GET(query_esw_vport_context_out, out,
801 esw_vport_context.fdb_to_vport_reg_c_id);
802 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
803 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
804 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
c1286050 805
332bd3a5 806 if (enable)
5b7cb745 807 curr |= wanted;
332bd3a5 808 else
5b7cb745 809 curr &= ~wanted;
c1286050
JL		 810
811 MLX5_SET(modify_esw_vport_context_in, in,
5b7cb745 812 esw_vport_context.fdb_to_vport_reg_c_id, curr);
c1286050
JL		 813
814 MLX5_SET(modify_esw_vport_context_in, in,
815 field_select.fdb_to_vport_reg_c_id, 1);
816
5b7cb745
PB		 817 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, in,
818 sizeof(in));
819 if (!err) {
820 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
821 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
822 else
823 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
824 }
825
826 return err;
c1286050
JL		 827}
828
a5641cb5
JL		 829static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
830 struct mlx5_core_dev *peer_dev,
ac004b83
RD		 831 struct mlx5_flow_spec *spec,
832 struct mlx5_flow_destination *dest)
833{
a5641cb5 834 void *misc;
ac004b83 835
a5641cb5
JL		 836 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
837 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
838 misc_parameters_2);
0f0d3827
PB		 839 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
840 mlx5_eswitch_get_vport_metadata_mask());
ac004b83 841
a5641cb5
JL		 842 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
843 } else {
844 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
845 misc_parameters);
ac004b83 846
a5641cb5
JL		 847 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
848 MLX5_CAP_GEN(peer_dev, vhca_id));
849
850 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
851
852 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
853 misc_parameters);
854 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
855 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
856 source_eswitch_owner_vhca_id);
857 }
ac004b83
RD		 858
859 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 860 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
ac004b83 861 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
04de7dda 862 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
ac004b83
RD		 863}
864
a5641cb5
JL		 865static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
866 struct mlx5_eswitch *peer_esw,
867 struct mlx5_flow_spec *spec,
868 u16 vport)
869{
870 void *misc;
871
872 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
873 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
874 misc_parameters_2);
875 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
876 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
877 vport));
878 } else {
879 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
880 misc_parameters);
881 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
882 }
883}
884
ac004b83
RD		 885static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
886 struct mlx5_core_dev *peer_dev)
887{
888 struct mlx5_flow_destination dest = {};
889 struct mlx5_flow_act flow_act = {0};
890 struct mlx5_flow_handle **flows;
891 struct mlx5_flow_handle *flow;
892 struct mlx5_flow_spec *spec;
893 /* total vports is the same for both e-switches */
894 int nvports = esw->total_vports;
895 void *misc;
896 int err, i;
897
898 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
899 if (!spec)
900 return -ENOMEM;
901
a5641cb5 902 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
ac004b83
RD		 903
904 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
905 if (!flows) {
906 err = -ENOMEM;
907 goto alloc_flows_err;
908 }
909
910 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
911 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
912 misc_parameters);
913
81cd229c 914 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
a5641cb5
JL		 915 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
916 spec, MLX5_VPORT_PF);
917
81cd229c
BW		 918 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
919 spec, &flow_act, &dest, 1);
920 if (IS_ERR(flow)) {
921 err = PTR_ERR(flow);
922 goto add_pf_flow_err;
923 }
924 flows[MLX5_VPORT_PF] = flow;
925 }
926
927 if (mlx5_ecpf_vport_exists(esw->dev)) {
928 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
929 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
930 spec, &flow_act, &dest, 1);
931 if (IS_ERR(flow)) {
932 err = PTR_ERR(flow);
933 goto add_ecpf_flow_err;
934 }
935 flows[mlx5_eswitch_ecpf_idx(esw)] = flow;
936 }
937
786ef904 938 mlx5_esw_for_each_vf_vport_num(esw, i, mlx5_core_max_vfs(esw->dev)) {
a5641cb5
JL		 939 esw_set_peer_miss_rule_source_port(esw,
940 peer_dev->priv.eswitch,
941 spec, i);
942
ac004b83
RD		 943 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
944 spec, &flow_act, &dest, 1);
945 if (IS_ERR(flow)) {
946 err = PTR_ERR(flow);
81cd229c 947 goto add_vf_flow_err;
ac004b83
RD		 948 }
949 flows[i] = flow;
950 }
951
952 esw->fdb_table.offloads.peer_miss_rules = flows;
953
954 kvfree(spec);
955 return 0;
956
81cd229c 957add_vf_flow_err:
879c8f84 958 nvports = --i;
786ef904 959 mlx5_esw_for_each_vf_vport_num_reverse(esw, i, nvports)
ac004b83 960 mlx5_del_flow_rules(flows[i]);
81cd229c
BW		 961
962 if (mlx5_ecpf_vport_exists(esw->dev))
963 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
964add_ecpf_flow_err:
965 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
966 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
967add_pf_flow_err:
968 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
ac004b83
RD		 969 kvfree(flows);
970alloc_flows_err:
971 kvfree(spec);
972 return err;
973}
974
975static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
976{
977 struct mlx5_flow_handle **flows;
978 int i;
979
980 flows = esw->fdb_table.offloads.peer_miss_rules;
981
786ef904
PP		 982 mlx5_esw_for_each_vf_vport_num_reverse(esw, i,
983 mlx5_core_max_vfs(esw->dev))
ac004b83
RD		 984 mlx5_del_flow_rules(flows[i]);
985
81cd229c
BW		 986 if (mlx5_ecpf_vport_exists(esw->dev))
987 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
988
989 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
990 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
991
ac004b83
RD		 992 kvfree(flows);
993}
994
3aa33572
OG		 995static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
996{
66958ed9 997 struct mlx5_flow_act flow_act = {0};
4c5009c5 998 struct mlx5_flow_destination dest = {};
74491de9 999 struct mlx5_flow_handle *flow_rule = NULL;
c5bb1730 1000 struct mlx5_flow_spec *spec;
f80be543
MB		 1001 void *headers_c;
1002 void *headers_v;
3aa33572 1003 int err = 0;
f80be543
MB		 1004 u8 *dmac_c;
1005 u8 *dmac_v;
3aa33572 1006
1b9a07ee 1007 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1008 if (!spec) {
3aa33572
OG		 1009 err = -ENOMEM;
1010 goto out;
1011 }
1012
f80be543
MB		 1013 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1014 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1015 outer_headers);
1016 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1017 outer_headers.dmac_47_16);
1018 dmac_c[0] = 0x01;
1019
3aa33572 1020 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1021 dest.vport.num = esw->manager_vport;
66958ed9 1022 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3aa33572 1023
39ac237c
PB		 1024 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1025 spec, &flow_act, &dest, 1);
3aa33572
OG		 1026 if (IS_ERR(flow_rule)) {
1027 err = PTR_ERR(flow_rule);
f80be543 1028 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
3aa33572
OG		 1029 goto out;
1030 }
1031
f80be543
MB		 1032 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1033
1034 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1035 outer_headers);
1036 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1037 outer_headers.dmac_47_16);
1038 dmac_v[0] = 0x01;
39ac237c
PB		 1039 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1040 spec, &flow_act, &dest, 1);
f80be543
MB		 1041 if (IS_ERR(flow_rule)) {
1042 err = PTR_ERR(flow_rule);
1043 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1044 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1045 goto out;
1046 }
1047
1048 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1049
3aa33572 1050out:
c5bb1730 1051 kvfree(spec);
3aa33572
OG		 1052 return err;
1053}
1054
11b717d6
PB		 1055struct mlx5_flow_handle *
1056esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1057{
1058 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1059 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1060 struct mlx5_flow_context *flow_context;
1061 struct mlx5_flow_handle *flow_rule;
1062 struct mlx5_flow_destination dest;
1063 struct mlx5_flow_spec *spec;
1064 void *misc;
1065
60acc105
PB		 1066 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1067 return ERR_PTR(-EOPNOTSUPP);
1068
11b717d6
PB		 1069 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1070 if (!spec)
1071 return ERR_PTR(-ENOMEM);
1072
1073 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1074 misc_parameters_2);
1075 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1076 ESW_CHAIN_TAG_METADATA_MASK);
1077 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1078 misc_parameters_2);
1079 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1080 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
6724e66b
PB		 1081 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1082 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1083 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
11b717d6
PB		 1084
1085 flow_context = &spec->flow_context;
1086 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1087 flow_context->flow_tag = tag;
1088 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1089 dest.ft = esw->offloads.ft_offloads;
1090
1091 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
1092 kfree(spec);
1093
1094 if (IS_ERR(flow_rule))
1095 esw_warn(esw->dev,
1096 "Failed to create restore rule for tag: %d, err(%d)\n",
1097 tag, (int)PTR_ERR(flow_rule));
1098
1099 return flow_rule;
1100}
1101
1102u32
1103esw_get_max_restore_tag(struct mlx5_eswitch *esw)
1104{
1105 return ESW_CHAIN_TAG_METADATA_MASK;
1106}
1107
1967ce6e 1108#define MAX_PF_SQ 256
cd3d07e7 1109#define MAX_SQ_NVPORTS 32
1967ce6e 1110
a5641cb5
JL		 1111static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1112 u32 *flow_group_in)
1113{
1114 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1115 flow_group_in,
1116 match_criteria);
1117
1118 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1119 MLX5_SET(create_flow_group_in, flow_group_in,
1120 match_criteria_enable,
1121 MLX5_MATCH_MISC_PARAMETERS_2);
1122
0f0d3827
PB		 1123 MLX5_SET(fte_match_param, match_criteria,
1124 misc_parameters_2.metadata_reg_c_0,
1125 mlx5_eswitch_get_vport_metadata_mask());
a5641cb5
JL		 1126 } else {
1127 MLX5_SET(create_flow_group_in, flow_group_in,
1128 match_criteria_enable,
1129 MLX5_MATCH_MISC_PARAMETERS);
1130
1131 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1132 misc_parameters.source_port);
1133 }
1134}
1135
1967ce6e
OG		 1136static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw, int nvports)
1137{
1138 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1139 struct mlx5_flow_table_attr ft_attr = {};
1140 struct mlx5_core_dev *dev = esw->dev;
1141 struct mlx5_flow_namespace *root_ns;
1142 struct mlx5_flow_table *fdb = NULL;
39ac237c
PB		 1143 u32 flags = 0, *flow_group_in;
1144 int table_size, ix, err = 0;
1967ce6e
OG		 1145 struct mlx5_flow_group *g;
1146 void *match_criteria;
f80be543 1147 u8 *dmac;
1967ce6e
OG		 1148
1149 esw_debug(esw->dev, "Create offloads FDB Tables\n");
39ac237c 1150
1b9a07ee 1151 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1967ce6e
OG		 1152 if (!flow_group_in)
1153 return -ENOMEM;
1154
1155 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1156 if (!root_ns) {
1157 esw_warn(dev, "Failed to get FDB flow namespace\n");
1158 err = -EOPNOTSUPP;
1159 goto ns_err;
1160 }
8463daf1
MG		 1161 esw->fdb_table.offloads.ns = root_ns;
1162 err = mlx5_flow_namespace_set_mode(root_ns,
1163 esw->dev->priv.steering->mode);
1164 if (err) {
1165 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1166 goto ns_err;
1167 }
1967ce6e 1168
cd7e4186
BW		 1169 table_size = nvports * MAX_SQ_NVPORTS + MAX_PF_SQ +
1170 MLX5_ESW_MISS_FLOWS + esw->total_vports;
b3ba5149 1171
e52c2802
PB		 1172 /* create the slow path fdb with encap set, so further table instances
1173 * can be created at run time while VFs are probed if the FW allows that.
1174 */
1175 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1176 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1177 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1178
1179 ft_attr.flags = flags;
b3ba5149
ES		 1180 ft_attr.max_fte = table_size;
1181 ft_attr.prio = FDB_SLOW_PATH;
1182
1183 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1033665e
OG		 1184 if (IS_ERR(fdb)) {
1185 err = PTR_ERR(fdb);
1186 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1187 goto slow_fdb_err;
1188 }
52fff327 1189 esw->fdb_table.offloads.slow_fdb = fdb;
1033665e 1190
39ac237c
PB		 1191 err = mlx5_esw_chains_create(esw);
1192 if (err) {
1193 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1194 goto fdb_chains_err;
e52c2802
PB		 1195 }
1196
69697b6e 1197 /* create send-to-vport group */
69697b6e
OG		 1198 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1199 MLX5_MATCH_MISC_PARAMETERS);
1200
1201 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1202
1203 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1204 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
1205
cd3d07e7 1206 ix = nvports * MAX_SQ_NVPORTS + MAX_PF_SQ;
69697b6e
OG		 1207 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1208 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
1209
1210 g = mlx5_create_flow_group(fdb, flow_group_in);
1211 if (IS_ERR(g)) {
1212 err = PTR_ERR(g);
1213 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1214 goto send_vport_err;
1215 }
1216 esw->fdb_table.offloads.send_to_vport_grp = g;
1217
ac004b83
RD		 1218 /* create peer esw miss group */
1219 memset(flow_group_in, 0, inlen);
ac004b83 1220
a5641cb5
JL		 1221 esw_set_flow_group_source_port(esw, flow_group_in);
1222
1223 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1224 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1225 flow_group_in,
1226 match_criteria);
ac004b83 1227
a5641cb5
JL		 1228 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1229 misc_parameters.source_eswitch_owner_vhca_id);
1230
1231 MLX5_SET(create_flow_group_in, flow_group_in,
1232 source_eswitch_owner_vhca_id_valid, 1);
1233 }
ac004b83 1234
ac004b83
RD		 1235 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1236 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1237 ix + esw->total_vports - 1);
1238 ix += esw->total_vports;
1239
1240 g = mlx5_create_flow_group(fdb, flow_group_in);
1241 if (IS_ERR(g)) {
1242 err = PTR_ERR(g);
1243 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
1244 goto peer_miss_err;
1245 }
1246 esw->fdb_table.offloads.peer_miss_grp = g;
1247
69697b6e
OG		 1248 /* create miss group */
1249 memset(flow_group_in, 0, inlen);
f80be543
MB		 1250 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1251 MLX5_MATCH_OUTER_HEADERS);
1252 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1253 match_criteria);
1254 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1255 outer_headers.dmac_47_16);
1256 dmac[0] = 0x01;
69697b6e
OG		 1257
1258 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
cd7e4186
BW		 1259 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1260 ix + MLX5_ESW_MISS_FLOWS);
69697b6e
OG		 1261
1262 g = mlx5_create_flow_group(fdb, flow_group_in);
1263 if (IS_ERR(g)) {
1264 err = PTR_ERR(g);
1265 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
1266 goto miss_err;
1267 }
1268 esw->fdb_table.offloads.miss_grp = g;
1269
3aa33572
OG		 1270 err = esw_add_fdb_miss_rule(esw);
1271 if (err)
1272 goto miss_rule_err;
1273
e52c2802 1274 esw->nvports = nvports;
c88a026e 1275 kvfree(flow_group_in);
69697b6e
OG		 1276 return 0;
1277
3aa33572
OG		 1278miss_rule_err:
1279 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
69697b6e 1280miss_err:
ac004b83
RD		 1281 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1282peer_miss_err:
69697b6e
OG		 1283 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1284send_vport_err:
39ac237c
PB		 1285 mlx5_esw_chains_destroy(esw);
1286fdb_chains_err:
52fff327 1287 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1033665e 1288slow_fdb_err:
8463daf1
MG		 1289 /* Holds true only as long as DMFS is the default */
1290 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e
OG		 1291ns_err:
1292 kvfree(flow_group_in);
1293 return err;
1294}
1295
1967ce6e 1296static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
69697b6e 1297{
e52c2802 1298 if (!esw->fdb_table.offloads.slow_fdb)
69697b6e
OG		 1299 return;
1300
1967ce6e 1301 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
f80be543
MB		 1302 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1303 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
69697b6e 1304 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
ac004b83 1305 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
69697b6e
OG		 1306 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1307
39ac237c 1308 mlx5_esw_chains_destroy(esw);
52fff327 1309 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
8463daf1
MG		 1310 /* Holds true only as long as DMFS is the default */
1311 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1312 MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e 1313}
c116c6ee 1314
cd7e4186 1315static int esw_create_offloads_table(struct mlx5_eswitch *esw, int nvports)
c116c6ee 1316{
b3ba5149 1317 struct mlx5_flow_table_attr ft_attr = {};
c116c6ee 1318 struct mlx5_core_dev *dev = esw->dev;
b3ba5149
ES		 1319 struct mlx5_flow_table *ft_offloads;
1320 struct mlx5_flow_namespace *ns;
c116c6ee
OG		 1321 int err = 0;
1322
1323 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1324 if (!ns) {
1325 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
eff596da 1326 return -EOPNOTSUPP;
c116c6ee
OG		 1327 }
1328
cd7e4186 1329 ft_attr.max_fte = nvports + MLX5_ESW_MISS_FLOWS;
11b717d6 1330 ft_attr.prio = 1;
b3ba5149
ES		 1331
1332 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
c116c6ee
OG		 1333 if (IS_ERR(ft_offloads)) {
1334 err = PTR_ERR(ft_offloads);
1335 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1336 return err;
1337 }
1338
1339 esw->offloads.ft_offloads = ft_offloads;
1340 return 0;
1341}
1342
1343static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1344{
1345 struct mlx5_esw_offload *offloads = &esw->offloads;
1346
1347 mlx5_destroy_flow_table(offloads->ft_offloads);
1348}
fed9ce22 1349
cd7e4186 1350static int esw_create_vport_rx_group(struct mlx5_eswitch *esw, int nvports)
fed9ce22
OG		 1351{
1352 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1353 struct mlx5_flow_group *g;
fed9ce22 1354 u32 *flow_group_in;
fed9ce22 1355 int err = 0;
fed9ce22 1356
cd7e4186 1357 nvports = nvports + MLX5_ESW_MISS_FLOWS;
1b9a07ee 1358 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
fed9ce22
OG		 1359 if (!flow_group_in)
1360 return -ENOMEM;
1361
1362 /* create vport rx group */
a5641cb5 1363 esw_set_flow_group_source_port(esw, flow_group_in);
fed9ce22
OG		 1364
1365 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1366 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1367
1368 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1369
1370 if (IS_ERR(g)) {
1371 err = PTR_ERR(g);
1372 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1373 goto out;
1374 }
1375
1376 esw->offloads.vport_rx_group = g;
1377out:
e574978a 1378 kvfree(flow_group_in);
fed9ce22
OG		 1379 return err;
1380}
1381
1382static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1383{
1384 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1385}
1386
74491de9 1387struct mlx5_flow_handle *
02f3afd9 1388mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
c966f7d5 1389 struct mlx5_flow_destination *dest)
fed9ce22 1390{
66958ed9 1391 struct mlx5_flow_act flow_act = {0};
74491de9 1392 struct mlx5_flow_handle *flow_rule;
c5bb1730 1393 struct mlx5_flow_spec *spec;
fed9ce22
OG		 1394 void *misc;
1395
1b9a07ee 1396 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1397 if (!spec) {
fed9ce22
OG		 1398 flow_rule = ERR_PTR(-ENOMEM);
1399 goto out;
1400 }
1401
a5641cb5
JL		 1402 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1403 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1404 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1405 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
fed9ce22 1406
a5641cb5 1407 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 1408 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1409 mlx5_eswitch_get_vport_metadata_mask());
fed9ce22 1410
a5641cb5
JL		 1411 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1412 } else {
1413 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1414 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1415
1416 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1417 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1418
1419 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1420 }
fed9ce22 1421
66958ed9 1422 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
74491de9 1423 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
c966f7d5 1424 &flow_act, dest, 1);
fed9ce22
OG		 1425 if (IS_ERR(flow_rule)) {
1426 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1427 goto out;
1428 }
1429
1430out:
c5bb1730 1431 kvfree(spec);
fed9ce22
OG		 1432 return flow_rule;
1433}
feae9087 1434
bf3347c4 1435
cc617ced
PP		 1436static int mlx5_eswitch_inline_mode_get(const struct mlx5_eswitch *esw, u8 *mode)
1437{
1438 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
1439 struct mlx5_core_dev *dev = esw->dev;
1440 int vport;
1441
1442 if (!MLX5_CAP_GEN(dev, vport_group_manager))
1443 return -EOPNOTSUPP;
1444
1445 if (esw->mode == MLX5_ESWITCH_NONE)
1446 return -EOPNOTSUPP;
1447
1448 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
1449 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1450 mlx5_mode = MLX5_INLINE_MODE_NONE;
1451 goto out;
1452 case MLX5_CAP_INLINE_MODE_L2:
1453 mlx5_mode = MLX5_INLINE_MODE_L2;
1454 goto out;
1455 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1456 goto query_vports;
1457 }
1458
1459query_vports:
1460 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
1461 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
1462 mlx5_query_nic_vport_min_inline(dev, vport, &mlx5_mode);
1463 if (prev_mlx5_mode != mlx5_mode)
1464 return -EINVAL;
1465 prev_mlx5_mode = mlx5_mode;
1466 }
1467
1468out:
1469 *mode = mlx5_mode;
1470 return 0;
bf3347c4
DM		 1471}
1472
11b717d6
PB		 1473static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
1474{
1475 struct mlx5_esw_offload *offloads = &esw->offloads;
1476
60acc105
PB		 1477 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1478 return;
1479
6724e66b 1480 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
11b717d6
PB		 1481 mlx5_destroy_flow_group(offloads->restore_group);
1482 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
1483}
1484
1485static int esw_create_restore_table(struct mlx5_eswitch *esw)
1486{
6724e66b 1487 u8 modact[MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)] = {};
11b717d6
PB		 1488 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1489 struct mlx5_flow_table_attr ft_attr = {};
1490 struct mlx5_core_dev *dev = esw->dev;
1491 struct mlx5_flow_namespace *ns;
6724e66b 1492 struct mlx5_modify_hdr *mod_hdr;
11b717d6
PB		 1493 void *match_criteria, *misc;
1494 struct mlx5_flow_table *ft;
1495 struct mlx5_flow_group *g;
1496 u32 *flow_group_in;
1497 int err = 0;
1498
60acc105
PB		 1499 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1500 return 0;
1501
11b717d6
PB		 1502 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1503 if (!ns) {
1504 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
1505 return -EOPNOTSUPP;
1506 }
1507
1508 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1509 if (!flow_group_in) {
1510 err = -ENOMEM;
1511 goto out_free;
1512 }
1513
1514 ft_attr.max_fte = 1 << ESW_CHAIN_TAG_METADATA_BITS;
1515 ft = mlx5_create_flow_table(ns, &ft_attr);
1516 if (IS_ERR(ft)) {
1517 err = PTR_ERR(ft);
1518 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
1519 err);
1520 goto out_free;
1521 }
1522
1523 memset(flow_group_in, 0, inlen);
1524 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1525 match_criteria);
1526 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
1527 misc_parameters_2);
1528
1529 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1530 ESW_CHAIN_TAG_METADATA_MASK);
1531 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1532 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1533 ft_attr.max_fte - 1);
1534 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1535 MLX5_MATCH_MISC_PARAMETERS_2);
1536 g = mlx5_create_flow_group(ft, flow_group_in);
1537 if (IS_ERR(g)) {
1538 err = PTR_ERR(g);
1539 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
1540 err);
1541 goto err_group;
1542 }
1543
6724e66b
PB		 1544 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
1545 MLX5_SET(copy_action_in, modact, src_field,
1546 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
1547 MLX5_SET(copy_action_in, modact, dst_field,
1548 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
1549 mod_hdr = mlx5_modify_header_alloc(esw->dev,
1550 MLX5_FLOW_NAMESPACE_KERNEL, 1,
1551 modact);
1552 if (IS_ERR(mod_hdr)) {
e9864539 1553 err = PTR_ERR(mod_hdr);
6724e66b
PB		 1554 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
1555 err);
6724e66b
PB		 1556 goto err_mod_hdr;
1557 }
1558
11b717d6
PB		 1559 esw->offloads.ft_offloads_restore = ft;
1560 esw->offloads.restore_group = g;
6724e66b 1561 esw->offloads.restore_copy_hdr_id = mod_hdr;
11b717d6 1562
c8508713
RD		 1563 kvfree(flow_group_in);
1564
11b717d6
PB		 1565 return 0;
1566
6724e66b
PB		 1567err_mod_hdr:
1568 mlx5_destroy_flow_group(g);
11b717d6
PB		 1569err_group:
1570 mlx5_destroy_flow_table(ft);
1571out_free:
1572 kvfree(flow_group_in);
1573
1574 return err;
cc617ced
PP		 1575}
1576
db7ff19e
EB		 1577static int esw_offloads_start(struct mlx5_eswitch *esw,
1578 struct netlink_ext_ack *extack)
c930a3ad 1579{
062f4bf4 1580 int err, err1;
c930a3ad 1581
f6455de0 1582 if (esw->mode != MLX5_ESWITCH_LEGACY &&
c96692fb 1583 !mlx5_core_is_ecpf_esw_manager(esw->dev)) {
8c98ee77
EB		 1584 NL_SET_ERR_MSG_MOD(extack,
1585 "Can't set offloads mode, SRIOV legacy not enabled");
c930a3ad
OG		 1586 return -EINVAL;
1587 }
1588
8e0aa4bc
PP		 1589 mlx5_eswitch_disable_locked(esw, false);
1590 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
1591 esw->dev->priv.sriov.num_vfs);
6c419ba8 1592 if (err) {
8c98ee77
EB		 1593 NL_SET_ERR_MSG_MOD(extack,
1594 "Failed setting eswitch to offloads");
8e0aa4bc
PP		 1595 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
1596 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 1597 if (err1) {
1598 NL_SET_ERR_MSG_MOD(extack,
1599 "Failed setting eswitch back to legacy");
1600 }
6c419ba8 1601 }
bffaa916
RD		 1602 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
1603 if (mlx5_eswitch_inline_mode_get(esw,
bffaa916
RD		 1604 &esw->offloads.inline_mode)) {
1605 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
8c98ee77
EB		 1606 NL_SET_ERR_MSG_MOD(extack,
1607 "Inline mode is different between vports");
bffaa916
RD		 1608 }
1609 }
c930a3ad
OG		 1610 return err;
1611}
1612
e8d31c4d
MB		 1613void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
1614{
1615 kfree(esw->offloads.vport_reps);
1616}
1617
1618int esw_offloads_init_reps(struct mlx5_eswitch *esw)
1619{
2752b823 1620 int total_vports = esw->total_vports;
e8d31c4d 1621 struct mlx5_eswitch_rep *rep;
d6518db2 1622 int vport_index;
ef2e4094 1623 u8 rep_type;
e8d31c4d 1624
2aca1787 1625 esw->offloads.vport_reps = kcalloc(total_vports,
e8d31c4d
MB		 1626 sizeof(struct mlx5_eswitch_rep),
1627 GFP_KERNEL);
1628 if (!esw->offloads.vport_reps)
1629 return -ENOMEM;
1630
d6518db2
BW		 1631 mlx5_esw_for_all_reps(esw, vport_index, rep) {
1632 rep->vport = mlx5_eswitch_index_to_vport_num(esw, vport_index);
2f69e591 1633 rep->vport_index = vport_index;
f121e0ea
BW		 1634
1635 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
8693115a 1636 atomic_set(&rep->rep_data[rep_type].state,
6f4e0219 1637 REP_UNREGISTERED);
e8d31c4d
MB		 1638 }
1639
e8d31c4d
MB		 1640 return 0;
1641}
1642
c9b99abc
BW		 1643static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
1644 struct mlx5_eswitch_rep *rep, u8 rep_type)
1645{
8693115a 1646 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
6f4e0219 1647 REP_LOADED, REP_REGISTERED) == REP_LOADED)
8693115a 1648 esw->offloads.rep_ops[rep_type]->unload(rep);
c9b99abc
BW		 1649}
1650
4110fc59 1651static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
6ed1803a
MB		 1652{
1653 struct mlx5_eswitch_rep *rep;
4110fc59
BW		 1654 int i;
1655
1656 mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, esw->esw_funcs.num_vfs)
1657 __esw_offloads_unload_rep(esw, rep, rep_type);
c9b99abc 1658
81cd229c
BW		 1659 if (mlx5_ecpf_vport_exists(esw->dev)) {
1660 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
1661 __esw_offloads_unload_rep(esw, rep, rep_type);
1662 }
1663
1664 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1665 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1666 __esw_offloads_unload_rep(esw, rep, rep_type);
1667 }
1668
879c8f84 1669 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
c9b99abc 1670 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 1671}
1672
c2d7712c 1673int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
a4b97ab4 1674{
c2d7712c
BW		 1675 struct mlx5_eswitch_rep *rep;
1676 int rep_type;
a4b97ab4
MB		 1677 int err;
1678
c2d7712c
BW		 1679 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
1680 return 0;
a4b97ab4 1681
c2d7712c
BW		 1682 rep = mlx5_eswitch_get_rep(esw, vport_num);
1683 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
1684 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
1685 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
1686 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
1687 if (err)
1688 goto err_reps;
1689 }
1690
1691 return 0;
a4b97ab4
MB		 1692
1693err_reps:
c2d7712c
BW		 1694 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
1695 for (--rep_type; rep_type >= 0; rep_type--)
1696 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 1697 return err;
1698}
1699
c2d7712c
BW		 1700void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
1701{
1702 struct mlx5_eswitch_rep *rep;
1703 int rep_type;
1704
1705 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
1706 return;
1707
1708 rep = mlx5_eswitch_get_rep(esw, vport_num);
1709 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
1710 __esw_offloads_unload_rep(esw, rep, rep_type);
1711}
1712
ac004b83
RD		 1713#define ESW_OFFLOADS_DEVCOM_PAIR (0)
1714#define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
1715
1716static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
1717 struct mlx5_eswitch *peer_esw)
1718{
1719 int err;
1720
1721 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
1722 if (err)
1723 return err;
1724
1725 return 0;
1726}
1727
1728static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
1729{
04de7dda 1730 mlx5e_tc_clean_fdb_peer_flows(esw);
ac004b83
RD		 1731 esw_del_fdb_peer_miss_rules(esw);
1732}
1733
8463daf1
MG		 1734static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
1735 struct mlx5_eswitch *peer_esw,
1736 bool pair)
1737{
1738 struct mlx5_flow_root_namespace *peer_ns;
1739 struct mlx5_flow_root_namespace *ns;
1740 int err;
1741
1742 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
1743 ns = esw->dev->priv.steering->fdb_root_ns;
1744
1745 if (pair) {
1746 err = mlx5_flow_namespace_set_peer(ns, peer_ns);
1747 if (err)
1748 return err;
1749
e53e6655 1750 err = mlx5_flow_namespace_set_peer(peer_ns, ns);
8463daf1
MG		 1751 if (err) {
1752 mlx5_flow_namespace_set_peer(ns, NULL);
1753 return err;
1754 }
1755 } else {
1756 mlx5_flow_namespace_set_peer(ns, NULL);
1757 mlx5_flow_namespace_set_peer(peer_ns, NULL);
1758 }
1759
1760 return 0;
1761}
1762
ac004b83
RD		 1763static int mlx5_esw_offloads_devcom_event(int event,
1764 void *my_data,
1765 void *event_data)
1766{
1767 struct mlx5_eswitch *esw = my_data;
ac004b83 1768 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
8463daf1 1769 struct mlx5_eswitch *peer_esw = event_data;
ac004b83
RD		 1770 int err;
1771
1772 switch (event) {
1773 case ESW_OFFLOADS_DEVCOM_PAIR:
a5641cb5
JL		 1774 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
1775 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
1776 break;
1777
8463daf1 1778 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
ac004b83
RD		 1779 if (err)
1780 goto err_out;
8463daf1
MG		 1781 err = mlx5_esw_offloads_pair(esw, peer_esw);
1782 if (err)
1783 goto err_peer;
ac004b83
RD		 1784
1785 err = mlx5_esw_offloads_pair(peer_esw, esw);
1786 if (err)
1787 goto err_pair;
1788
1789 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
1790 break;
1791
1792 case ESW_OFFLOADS_DEVCOM_UNPAIR:
1793 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
1794 break;
1795
1796 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
1797 mlx5_esw_offloads_unpair(peer_esw);
1798 mlx5_esw_offloads_unpair(esw);
8463daf1 1799 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 1800 break;
1801 }
1802
1803 return 0;
1804
1805err_pair:
1806 mlx5_esw_offloads_unpair(esw);
8463daf1
MG		 1807err_peer:
1808 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 1809err_out:
1810 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
1811 event, err);
1812 return err;
1813}
1814
1815static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
1816{
1817 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1818
04de7dda
RD		 1819 INIT_LIST_HEAD(&esw->offloads.peer_flows);
1820 mutex_init(&esw->offloads.peer_mutex);
1821
ac004b83
RD		 1822 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1823 return;
1824
1825 mlx5_devcom_register_component(devcom,
1826 MLX5_DEVCOM_ESW_OFFLOADS,
1827 mlx5_esw_offloads_devcom_event,
1828 esw);
1829
1830 mlx5_devcom_send_event(devcom,
1831 MLX5_DEVCOM_ESW_OFFLOADS,
1832 ESW_OFFLOADS_DEVCOM_PAIR, esw);
1833}
1834
1835static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
1836{
1837 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1838
1839 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1840 return;
1841
1842 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
1843 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
1844
1845 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1846}
1847
18486737
EB		 1848static int esw_vport_ingress_prio_tag_config(struct mlx5_eswitch *esw,
1849 struct mlx5_vport *vport)
1850{
18486737
EB		 1851 struct mlx5_flow_act flow_act = {0};
1852 struct mlx5_flow_spec *spec;
1853 int err = 0;
1854
1855 /* For prio tag mode, there is only 1 FTEs:
7445cfb1
JL		 1856 * 1) Untagged packets - push prio tag VLAN and modify metadata if
1857 * required, allow
18486737
EB		 1858 * Unmatched traffic is allowed by default
1859 */
18486737 1860 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
b7826076
PP		 1861 if (!spec)
1862 return -ENOMEM;
18486737
EB		 1863
1864 /* Untagged packets - push prio tag VLAN, allow */
1865 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.cvlan_tag);
1866 MLX5_SET(fte_match_param, spec->match_value, outer_headers.cvlan_tag, 0);
1867 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1868 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
1869 MLX5_FLOW_CONTEXT_ACTION_ALLOW;
1870 flow_act.vlan[0].ethtype = ETH_P_8021Q;
1871 flow_act.vlan[0].vid = 0;
1872 flow_act.vlan[0].prio = 0;
7445cfb1 1873
d68316b5 1874 if (vport->ingress.offloads.modify_metadata_rule) {
7445cfb1 1875 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
d68316b5 1876 flow_act.modify_hdr = vport->ingress.offloads.modify_metadata;
7445cfb1
JL		 1877 }
1878
18486737
EB		 1879 vport->ingress.allow_rule =
1880 mlx5_add_flow_rules(vport->ingress.acl, spec,
1881 &flow_act, NULL, 0);
1882 if (IS_ERR(vport->ingress.allow_rule)) {
1883 err = PTR_ERR(vport->ingress.allow_rule);
1884 esw_warn(esw->dev,
1885 "vport[%d] configure ingress untagged allow rule, err(%d)\n",
1886 vport->vport, err);
1887 vport->ingress.allow_rule = NULL;
18486737
EB		 1888 }
1889
18486737 1890 kvfree(spec);
18486737
EB		 1891 return err;
1892}
1893
7445cfb1
JL		 1894static int esw_vport_add_ingress_acl_modify_metadata(struct mlx5_eswitch *esw,
1895 struct mlx5_vport *vport)
1896{
1897 u8 action[MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)] = {};
1898 struct mlx5_flow_act flow_act = {};
7445cfb1 1899 int err = 0;
0f0d3827
PB		 1900 u32 key;
1901
1902 key = mlx5_eswitch_get_vport_metadata_for_match(esw, vport->vport);
1903 key >>= ESW_SOURCE_PORT_METADATA_OFFSET;
7445cfb1
JL		 1904
1905 MLX5_SET(set_action_in, action, action_type, MLX5_ACTION_TYPE_SET);
0f0d3827
PB		 1906 MLX5_SET(set_action_in, action, field,
1907 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0);
1908 MLX5_SET(set_action_in, action, data, key);
1909 MLX5_SET(set_action_in, action, offset,
1910 ESW_SOURCE_PORT_METADATA_OFFSET);
1911 MLX5_SET(set_action_in, action, length,
1912 ESW_SOURCE_PORT_METADATA_BITS);
7445cfb1 1913
d68316b5 1914 vport->ingress.offloads.modify_metadata =
2b688ea5
MG		 1915 mlx5_modify_header_alloc(esw->dev, MLX5_FLOW_NAMESPACE_ESW_INGRESS,
1916 1, action);
d68316b5
PP		 1917 if (IS_ERR(vport->ingress.offloads.modify_metadata)) {
1918 err = PTR_ERR(vport->ingress.offloads.modify_metadata);
7445cfb1
JL		 1919 esw_warn(esw->dev,
1920 "failed to alloc modify header for vport %d ingress acl (%d)\n",
1921 vport->vport, err);
1922 return err;
1923 }
1924
1925 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_MOD_HDR | MLX5_FLOW_CONTEXT_ACTION_ALLOW;
d68316b5
PP		 1926 flow_act.modify_hdr = vport->ingress.offloads.modify_metadata;
1927 vport->ingress.offloads.modify_metadata_rule =
1928 mlx5_add_flow_rules(vport->ingress.acl,
5c2aa8ae 1929 NULL, &flow_act, NULL, 0);
d68316b5
PP		 1930 if (IS_ERR(vport->ingress.offloads.modify_metadata_rule)) {
1931 err = PTR_ERR(vport->ingress.offloads.modify_metadata_rule);
7445cfb1
JL		 1932 esw_warn(esw->dev,
1933 "failed to add setting metadata rule for vport %d ingress acl, err(%d)\n",
1934 vport->vport, err);
b7826076 1935 mlx5_modify_header_dealloc(esw->dev, vport->ingress.offloads.modify_metadata);
d68316b5 1936 vport->ingress.offloads.modify_metadata_rule = NULL;
7445cfb1 1937 }
7445cfb1
JL		 1938 return err;
1939}
1940
a962d7a6
PP		 1941static void esw_vport_del_ingress_acl_modify_metadata(struct mlx5_eswitch *esw,
1942 struct mlx5_vport *vport)
7445cfb1 1943{
d68316b5
PP		 1944 if (vport->ingress.offloads.modify_metadata_rule) {
1945 mlx5_del_flow_rules(vport->ingress.offloads.modify_metadata_rule);
1946 mlx5_modify_header_dealloc(esw->dev, vport->ingress.offloads.modify_metadata);
7445cfb1 1947
d68316b5 1948 vport->ingress.offloads.modify_metadata_rule = NULL;
7445cfb1
JL		 1949 }
1950}
1951
10652f39
PP		 1952static int esw_vport_create_ingress_acl_group(struct mlx5_eswitch *esw,
1953 struct mlx5_vport *vport)
18486737 1954{
10652f39
PP		 1955 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1956 struct mlx5_flow_group *g;
b7826076 1957 void *match_criteria;
10652f39 1958 u32 *flow_group_in;
b7826076 1959 u32 flow_index = 0;
10652f39 1960 int ret = 0;
18486737 1961
10652f39
PP		 1962 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1963 if (!flow_group_in)
1964 return -ENOMEM;
18486737 1965
b7826076
PP		 1966 if (esw_check_ingress_prio_tag_enabled(esw, vport)) {
1967 /* This group is to hold FTE to match untagged packets when prio_tag
1968 * is enabled.
1969 */
1970 memset(flow_group_in, 0, inlen);
18486737 1971
b7826076
PP		 1972 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1973 flow_group_in, match_criteria);
1974 MLX5_SET(create_flow_group_in, flow_group_in,
1975 match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1976 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.cvlan_tag);
1977 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, flow_index);
1978 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, flow_index);
1979
1980 g = mlx5_create_flow_group(vport->ingress.acl, flow_group_in);
1981 if (IS_ERR(g)) {
1982 ret = PTR_ERR(g);
1983 esw_warn(esw->dev, "vport[%d] ingress create untagged flow group, err(%d)\n",
1984 vport->vport, ret);
1985 goto prio_tag_err;
1986 }
1987 vport->ingress.offloads.metadata_prio_tag_grp = g;
1988 flow_index++;
1989 }
1990
1991 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1992 /* This group holds an FTE with no matches for add metadata for
1993 * tagged packets, if prio-tag is enabled (as a fallthrough),
1994 * or all traffic in case prio-tag is disabled.
1995 */
1996 memset(flow_group_in, 0, inlen);
1997 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, flow_index);
1998 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, flow_index);
1999
2000 g = mlx5_create_flow_group(vport->ingress.acl, flow_group_in);
2001 if (IS_ERR(g)) {
2002 ret = PTR_ERR(g);
2003 esw_warn(esw->dev, "vport[%d] ingress create drop flow group, err(%d)\n",
2004 vport->vport, ret);
2005 goto metadata_err;
2006 }
2007 vport->ingress.offloads.metadata_allmatch_grp = g;
2008 }
2009
2010 kvfree(flow_group_in);
2011 return 0;
2012
2013metadata_err:
2014 if (!IS_ERR_OR_NULL(vport->ingress.offloads.metadata_prio_tag_grp)) {
2015 mlx5_destroy_flow_group(vport->ingress.offloads.metadata_prio_tag_grp);
2016 vport->ingress.offloads.metadata_prio_tag_grp = NULL;
18486737 2017 }
b7826076 2018prio_tag_err:
10652f39
PP		 2019 kvfree(flow_group_in);
2020 return ret;
2021}
18486737 2022
10652f39
PP		 2023static void esw_vport_destroy_ingress_acl_group(struct mlx5_vport *vport)
2024{
b7826076
PP		 2025 if (vport->ingress.offloads.metadata_allmatch_grp) {
2026 mlx5_destroy_flow_group(vport->ingress.offloads.metadata_allmatch_grp);
2027 vport->ingress.offloads.metadata_allmatch_grp = NULL;
2028 }
2029
2030 if (vport->ingress.offloads.metadata_prio_tag_grp) {
2031 mlx5_destroy_flow_group(vport->ingress.offloads.metadata_prio_tag_grp);
2032 vport->ingress.offloads.metadata_prio_tag_grp = NULL;
10652f39 2033 }
18486737
EB		 2034}
2035
b1a3380a
VP		 2036static int esw_vport_ingress_config(struct mlx5_eswitch *esw,
2037 struct mlx5_vport *vport)
18486737 2038{
b7826076 2039 int num_ftes = 0;
18486737
EB		 2040 int err;
2041
7445cfb1 2042 if (!mlx5_eswitch_vport_match_metadata_enabled(esw) &&
b7826076 2043 !esw_check_ingress_prio_tag_enabled(esw, vport))
7445cfb1
JL		 2044 return 0;
2045
2046 esw_vport_cleanup_ingress_rules(esw, vport);
b7826076
PP		 2047
2048 if (mlx5_eswitch_vport_match_metadata_enabled(esw))
2049 num_ftes++;
2050 if (esw_check_ingress_prio_tag_enabled(esw, vport))
2051 num_ftes++;
2052
2053 err = esw_vport_create_ingress_acl_table(esw, vport, num_ftes);
7445cfb1
JL		 2054 if (err) {
2055 esw_warn(esw->dev,
2056 "failed to enable ingress acl (%d) on vport[%d]\n",
2057 err, vport->vport);
2058 return err;
2059 }
2060
10652f39
PP		 2061 err = esw_vport_create_ingress_acl_group(esw, vport);
2062 if (err)
2063 goto group_err;
2064
7445cfb1
JL		 2065 esw_debug(esw->dev,
2066 "vport[%d] configure ingress rules\n", vport->vport);
2067
2068 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
2069 err = esw_vport_add_ingress_acl_modify_metadata(esw, vport);
2070 if (err)
10652f39 2071 goto metadata_err;
7445cfb1
JL		 2072 }
2073
b7826076 2074 if (esw_check_ingress_prio_tag_enabled(esw, vport)) {
786ef904 2075 err = esw_vport_ingress_prio_tag_config(esw, vport);
18486737 2076 if (err)
10652f39 2077 goto prio_tag_err;
7445cfb1 2078 }
10652f39 2079 return 0;
7445cfb1 2080
10652f39
PP		 2081prio_tag_err:
2082 esw_vport_del_ingress_acl_modify_metadata(esw, vport);
2083metadata_err:
10652f39
PP		 2084 esw_vport_destroy_ingress_acl_group(vport);
2085group_err:
2086 esw_vport_destroy_ingress_acl_table(vport);
7445cfb1
JL		 2087 return err;
2088}
2089
6d94e610
VP		 2090static int esw_vport_egress_config(struct mlx5_eswitch *esw,
2091 struct mlx5_vport *vport)
2092{
2093 int err;
2094
2095 if (!MLX5_CAP_GEN(esw->dev, prio_tag_required))
2096 return 0;
2097
2098 esw_vport_cleanup_egress_rules(esw, vport);
2099
2100 err = esw_vport_enable_egress_acl(esw, vport);
2101 if (err)
2102 return err;
2103
fdde49e0
PP		 2104 /* For prio tag mode, there is only 1 FTEs:
2105 * 1) prio tag packets - pop the prio tag VLAN, allow
2106 * Unmatched traffic is allowed by default
2107 */
2108 esw_debug(esw->dev,
2109 "vport[%d] configure prio tag egress rules\n", vport->vport);
6d94e610 2110
fdde49e0
PP		 2111 /* prio tag vlan rule - pop it so VF receives untagged packets */
2112 err = mlx5_esw_create_vport_egress_acl_vlan(esw, vport, 0,
2113 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP |
2114 MLX5_FLOW_CONTEXT_ACTION_ALLOW);
7445cfb1 2115 if (err)
6d94e610
VP		 2116 esw_vport_disable_egress_acl(esw, vport);
2117
7445cfb1
JL		 2118 return err;
2119}
2120
92ab1eb3
JL		 2121static bool
2122esw_check_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
2123{
2124 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
2125 return false;
2126
2127 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
2128 MLX5_FDB_TO_VPORT_REG_C_0))
2129 return false;
2130
2131 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source))
2132 return false;
2133
2134 if (mlx5_core_is_ecpf_esw_manager(esw->dev) ||
2135 mlx5_ecpf_vport_exists(esw->dev))
2136 return false;
2137
2138 return true;
2139}
2140
1e62e222
MD		 2141static bool
2142esw_check_vport_match_metadata_mandatory(const struct mlx5_eswitch *esw)
2143{
2144 return mlx5_core_mp_enabled(esw->dev);
2145}
2146
2147static bool esw_use_vport_metadata(const struct mlx5_eswitch *esw)
2148{
2149 return esw_check_vport_match_metadata_mandatory(esw) &&
2150 esw_check_vport_match_metadata_supported(esw);
2151}
2152
748da30b 2153int
89a0f1fb
PP		 2154esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
2155 struct mlx5_vport *vport)
7445cfb1 2156{
7445cfb1
JL		 2157 int err;
2158
89a0f1fb
PP		 2159 err = esw_vport_ingress_config(esw, vport);
2160 if (err)
2161 return err;
7445cfb1 2162
89a0f1fb
PP		 2163 if (mlx5_eswitch_is_vf_vport(esw, vport->vport)) {
2164 err = esw_vport_egress_config(esw, vport);
a962d7a6 2165 if (err) {
10652f39 2166 esw_vport_cleanup_ingress_rules(esw, vport);
b7826076
PP		 2167 esw_vport_del_ingress_acl_modify_metadata(esw, vport);
2168 esw_vport_destroy_ingress_acl_group(vport);
10652f39 2169 esw_vport_destroy_ingress_acl_table(vport);
7445cfb1 2170 }
18486737 2171 }
89a0f1fb
PP		 2172 return err;
2173}
18486737 2174
748da30b 2175void
89a0f1fb
PP		 2176esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
2177 struct mlx5_vport *vport)
2178{
2179 esw_vport_disable_egress_acl(esw, vport);
10652f39 2180 esw_vport_cleanup_ingress_rules(esw, vport);
b7826076 2181 esw_vport_del_ingress_acl_modify_metadata(esw, vport);
10652f39
PP		 2182 esw_vport_destroy_ingress_acl_group(vport);
2183 esw_vport_destroy_ingress_acl_table(vport);
89a0f1fb 2184}
7445cfb1 2185
748da30b 2186static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
7445cfb1
JL		 2187{
2188 struct mlx5_vport *vport;
7445cfb1 2189 int err;
18486737 2190
1e62e222 2191 if (esw_use_vport_metadata(esw))
92ab1eb3 2192 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
18486737 2193
748da30b
VP		 2194 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
2195 err = esw_vport_create_offloads_acl_tables(esw, vport);
2196 if (err)
2197 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
18486737
EB		 2198 return err;
2199}
2200
748da30b 2201static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
18486737 2202{
786ef904 2203 struct mlx5_vport *vport;
7445cfb1 2204
748da30b
VP		 2205 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
2206 esw_vport_destroy_offloads_acl_tables(esw, vport);
7445cfb1 2207 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
18486737
EB		 2208}
2209
062f4bf4 2210static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
6ed1803a 2211{
062f4bf4
BW		 2212 int num_vfs = esw->esw_funcs.num_vfs;
2213 int total_vports;
6ed1803a
MB		 2214 int err;
2215
062f4bf4
BW		 2216 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
2217 total_vports = esw->total_vports;
2218 else
2219 total_vports = num_vfs + MLX5_SPECIAL_VPORTS(esw->dev);
2220
5c1d260e 2221 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
f8d1edda
PP		 2222 mutex_init(&esw->fdb_table.offloads.vports.lock);
2223 hash_init(esw->fdb_table.offloads.vports.table);
e52c2802 2224
748da30b 2225 err = esw_create_uplink_offloads_acl_tables(esw);
7445cfb1 2226 if (err)
f8d1edda 2227 goto create_acl_err;
18486737 2228
11b717d6 2229 err = esw_create_offloads_table(esw, total_vports);
c930a3ad 2230 if (err)
11b717d6 2231 goto create_offloads_err;
c930a3ad 2232
11b717d6 2233 err = esw_create_restore_table(esw);
c930a3ad 2234 if (err)
11b717d6
PB		 2235 goto create_restore_err;
2236
2237 err = esw_create_offloads_fdb_tables(esw, total_vports);
2238 if (err)
2239 goto create_fdb_err;
c930a3ad 2240
062f4bf4 2241 err = esw_create_vport_rx_group(esw, total_vports);
c930a3ad
OG		 2242 if (err)
2243 goto create_fg_err;
2244
2245 return 0;
2246
2247create_fg_err:
1967ce6e 2248 esw_destroy_offloads_fdb_tables(esw);
7445cfb1 2249create_fdb_err:
11b717d6
PB		 2250 esw_destroy_restore_table(esw);
2251create_restore_err:
2252 esw_destroy_offloads_table(esw);
2253create_offloads_err:
748da30b 2254 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda
PP		 2255create_acl_err:
2256 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
c930a3ad
OG		 2257 return err;
2258}
2259
eca8cc38
BW		 2260static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
2261{
2262 esw_destroy_vport_rx_group(esw);
eca8cc38 2263 esw_destroy_offloads_fdb_tables(esw);
11b717d6
PB		 2264 esw_destroy_restore_table(esw);
2265 esw_destroy_offloads_table(esw);
748da30b 2266 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda 2267 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
eca8cc38
BW		 2268}
2269
7e736f9a
PP		 2270static void
2271esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
a3888f33 2272{
5ccf2770 2273 bool host_pf_disabled;
7e736f9a 2274 u16 new_num_vfs;
a3888f33 2275
7e736f9a
PP		 2276 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
2277 host_params_context.host_num_of_vfs);
5ccf2770
BW		 2278 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
2279 host_params_context.host_pf_disabled);
a3888f33 2280
7e736f9a
PP		 2281 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
2282 return;
a3888f33
BW		 2283
2284 /* Number of VFs can only change from "0 to x" or "x to 0". */
cd56f929 2285 if (esw->esw_funcs.num_vfs > 0) {
23bb50cf 2286 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
a3888f33 2287 } else {
7e736f9a 2288 int err;
a3888f33 2289
23bb50cf
BW		 2290 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
2291 MLX5_VPORT_UC_ADDR_CHANGE);
a3888f33 2292 if (err)
7e736f9a 2293 return;
a3888f33 2294 }
7e736f9a 2295 esw->esw_funcs.num_vfs = new_num_vfs;
a3888f33
BW		 2296}
2297
7e736f9a 2298static void esw_functions_changed_event_handler(struct work_struct *work)
ac35dcd6 2299{
7e736f9a
PP		 2300 struct mlx5_host_work *host_work;
2301 struct mlx5_eswitch *esw;
dd28087c 2302 const u32 *out;
ac35dcd6 2303
7e736f9a
PP		 2304 host_work = container_of(work, struct mlx5_host_work, work);
2305 esw = host_work->esw;
a3888f33 2306
dd28087c
PP		 2307 out = mlx5_esw_query_functions(esw->dev);
2308 if (IS_ERR(out))
7e736f9a 2309 goto out;
a3888f33 2310
7e736f9a 2311 esw_vfs_changed_event_handler(esw, out);
dd28087c 2312 kvfree(out);
a3888f33 2313out:
ac35dcd6
VP		 2314 kfree(host_work);
2315}
2316
16fff98a 2317int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
a3888f33 2318{
cd56f929 2319 struct mlx5_esw_functions *esw_funcs;
a3888f33 2320 struct mlx5_host_work *host_work;
a3888f33
BW		 2321 struct mlx5_eswitch *esw;
2322
2323 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
2324 if (!host_work)
2325 return NOTIFY_DONE;
2326
cd56f929
VP		 2327 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
2328 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
a3888f33
BW		 2329
2330 host_work->esw = esw;
2331
062f4bf4 2332 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
a3888f33
BW		 2333 queue_work(esw->work_queue, &host_work->work);
2334
2335 return NOTIFY_OK;
2336}
2337
5896b972 2338int esw_offloads_enable(struct mlx5_eswitch *esw)
eca8cc38 2339{
3b83b6c2
DL		 2340 struct mlx5_vport *vport;
2341 int err, i;
eca8cc38 2342
9a64144d
MG		 2343 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat) &&
2344 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, decap))
2345 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC;
2346 else
2347 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2348
2bb72e7e 2349 mutex_init(&esw->offloads.termtbl_mutex);
8463daf1 2350 mlx5_rdma_enable_roce(esw->dev);
eca8cc38 2351
332bd3a5
PP		 2352 err = esw_set_passing_vport_metadata(esw, true);
2353 if (err)
2354 goto err_vport_metadata;
c1286050 2355
7983a675
PB		 2356 err = esw_offloads_steering_init(esw);
2357 if (err)
2358 goto err_steering_init;
2359
3b83b6c2
DL		 2360 /* Representor will control the vport link state */
2361 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
2362 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2363
c2d7712c
BW		 2364 /* Uplink vport rep must load first. */
2365 err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK);
925a6acc 2366 if (err)
c2d7712c 2367 goto err_uplink;
c1286050 2368
c2d7712c 2369 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
eca8cc38 2370 if (err)
c2d7712c 2371 goto err_vports;
eca8cc38
BW		 2372
2373 esw_offloads_devcom_init(esw);
a3888f33 2374
eca8cc38
BW		 2375 return 0;
2376
925a6acc 2377err_vports:
c2d7712c
BW		 2378 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
2379err_uplink:
7983a675 2380 esw_offloads_steering_cleanup(esw);
79949985
PP		 2381err_steering_init:
2382 esw_set_passing_vport_metadata(esw, false);
7983a675 2383err_vport_metadata:
8463daf1 2384 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2385 mutex_destroy(&esw->offloads.termtbl_mutex);
eca8cc38
BW		 2386 return err;
2387}
2388
db7ff19e
EB		 2389static int esw_offloads_stop(struct mlx5_eswitch *esw,
2390 struct netlink_ext_ack *extack)
c930a3ad 2391{
062f4bf4 2392 int err, err1;
c930a3ad 2393
8e0aa4bc
PP		 2394 mlx5_eswitch_disable_locked(esw, false);
2395 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2396 MLX5_ESWITCH_IGNORE_NUM_VFS);
6c419ba8 2397 if (err) {
8c98ee77 2398 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
8e0aa4bc
PP		 2399 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2400 MLX5_ESWITCH_IGNORE_NUM_VFS);
8c98ee77
EB		 2401 if (err1) {
2402 NL_SET_ERR_MSG_MOD(extack,
2403 "Failed setting eswitch back to offloads");
2404 }
6c419ba8 2405 }
c930a3ad
OG		 2406
2407 return err;
2408}
2409
5896b972 2410void esw_offloads_disable(struct mlx5_eswitch *esw)
c930a3ad 2411{
ac004b83 2412 esw_offloads_devcom_cleanup(esw);
5896b972 2413 mlx5_eswitch_disable_pf_vf_vports(esw);
c2d7712c 2414 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
332bd3a5 2415 esw_set_passing_vport_metadata(esw, false);
eca8cc38 2416 esw_offloads_steering_cleanup(esw);
8463daf1 2417 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 2418 mutex_destroy(&esw->offloads.termtbl_mutex);
9a64144d 2419 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
c930a3ad
OG		 2420}
2421
ef78618b 2422static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
c930a3ad
OG		 2423{
2424 switch (mode) {
2425 case DEVLINK_ESWITCH_MODE_LEGACY:
f6455de0 2426 *mlx5_mode = MLX5_ESWITCH_LEGACY;
c930a3ad
OG		 2427 break;
2428 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
f6455de0 2429 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
c930a3ad
OG		 2430 break;
2431 default:
2432 return -EINVAL;
2433 }
2434
2435 return 0;
2436}
2437
ef78618b
OG		 2438static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
2439{
2440 switch (mlx5_mode) {
f6455de0 2441 case MLX5_ESWITCH_LEGACY:
ef78618b
OG		 2442 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
2443 break;
f6455de0 2444 case MLX5_ESWITCH_OFFLOADS:
ef78618b
OG		 2445 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
2446 break;
2447 default:
2448 return -EINVAL;
2449 }
2450
2451 return 0;
2452}
2453
bffaa916
RD		 2454static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
2455{
2456 switch (mode) {
2457 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
2458 *mlx5_mode = MLX5_INLINE_MODE_NONE;
2459 break;
2460 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
2461 *mlx5_mode = MLX5_INLINE_MODE_L2;
2462 break;
2463 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
2464 *mlx5_mode = MLX5_INLINE_MODE_IP;
2465 break;
2466 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
2467 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
2468 break;
2469 default:
2470 return -EINVAL;
2471 }
2472
2473 return 0;
2474}
2475
2476static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
2477{
2478 switch (mlx5_mode) {
2479 case MLX5_INLINE_MODE_NONE:
2480 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
2481 break;
2482 case MLX5_INLINE_MODE_L2:
2483 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
2484 break;
2485 case MLX5_INLINE_MODE_IP:
2486 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
2487 break;
2488 case MLX5_INLINE_MODE_TCP_UDP:
2489 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
2490 break;
2491 default:
2492 return -EINVAL;
2493 }
2494
2495 return 0;
2496}
2497
0e6fa491 2498static int mlx5_eswitch_check(const struct mlx5_core_dev *dev)
feae9087 2499{
9d1cef19
OG		 2500 if (MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2501 return -EOPNOTSUPP;
c930a3ad 2502
733d3e54
OG		 2503 if(!MLX5_ESWITCH_MANAGER(dev))
2504 return -EPERM;
c930a3ad 2505
9d1cef19
OG		 2506 return 0;
2507}
2508
ae24432c
PP		 2509static int eswitch_devlink_esw_mode_check(const struct mlx5_eswitch *esw)
2510{
2511 /* devlink commands in NONE eswitch mode are currently supported only
2512 * on ECPF.
2513 */
2514 return (esw->mode == MLX5_ESWITCH_NONE &&
2515 !mlx5_core_is_ecpf_esw_manager(esw->dev)) ? -EOPNOTSUPP : 0;
2516}
2517
db7ff19e
EB		 2518int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
2519 struct netlink_ext_ack *extack)
9d1cef19
OG		 2520{
2521 struct mlx5_core_dev *dev = devlink_priv(devlink);
8e0aa4bc 2522 struct mlx5_eswitch *esw = dev->priv.eswitch;
9d1cef19
OG		 2523 u16 cur_mlx5_mode, mlx5_mode = 0;
2524 int err;
2525
0e6fa491 2526 err = mlx5_eswitch_check(dev);
9d1cef19
OG		 2527 if (err)
2528 return err;
2529
ef78618b 2530 if (esw_mode_from_devlink(mode, &mlx5_mode))
c930a3ad
OG		 2531 return -EINVAL;
2532
8e0aa4bc
PP		 2533 mutex_lock(&esw->mode_lock);
2534 err = eswitch_devlink_esw_mode_check(esw);
2535 if (err)
2536 goto unlock;
2537
2538 cur_mlx5_mode = esw->mode;
2539
c930a3ad 2540 if (cur_mlx5_mode == mlx5_mode)
8e0aa4bc 2541 goto unlock;
c930a3ad
OG		 2542
2543 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
8e0aa4bc 2544 err = esw_offloads_start(esw, extack);
c930a3ad 2545 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
8e0aa4bc 2546 err = esw_offloads_stop(esw, extack);
c930a3ad 2547 else
8e0aa4bc
PP		 2548 err = -EINVAL;
2549
2550unlock:
2551 mutex_unlock(&esw->mode_lock);
2552 return err;
feae9087
OG		 2553}
2554
2555int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
2556{
9d1cef19 2557 struct mlx5_core_dev *dev = devlink_priv(devlink);
8e0aa4bc 2558 struct mlx5_eswitch *esw = dev->priv.eswitch;
9d1cef19 2559 int err;
c930a3ad 2560
0e6fa491 2561 err = mlx5_eswitch_check(dev);
9d1cef19
OG		 2562 if (err)
2563 return err;
c930a3ad 2564
8e0aa4bc 2565 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2566 err = eswitch_devlink_esw_mode_check(dev->priv.eswitch);
2567 if (err)
8e0aa4bc 2568 goto unlock;
ae24432c 2569
8e0aa4bc
PP		 2570 err = esw_mode_to_devlink(esw->mode, mode);
2571unlock:
2572 mutex_unlock(&esw->mode_lock);
2573 return err;
feae9087 2574}
127ea380 2575
db7ff19e
EB		 2576int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
2577 struct netlink_ext_ack *extack)
bffaa916
RD		 2578{
2579 struct mlx5_core_dev *dev = devlink_priv(devlink);
2580 struct mlx5_eswitch *esw = dev->priv.eswitch;
db68cc56 2581 int err, vport, num_vport;
bffaa916
RD		 2582 u8 mlx5_mode;
2583
0e6fa491 2584 err = mlx5_eswitch_check(dev);
9d1cef19
OG		 2585 if (err)
2586 return err;
bffaa916 2587
8e0aa4bc 2588 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2589 err = eswitch_devlink_esw_mode_check(esw);
2590 if (err)
8e0aa4bc 2591 goto out;
ae24432c 2592
c415f704
OG		 2593 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2594 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2595 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
8e0aa4bc 2596 goto out;
c415f704
OG		 2597 /* fall through */
2598 case MLX5_CAP_INLINE_MODE_L2:
8c98ee77 2599 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
8e0aa4bc
PP		 2600 err = -EOPNOTSUPP;
2601 goto out;
c415f704
OG		 2602 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2603 break;
2604 }
bffaa916 2605
525e84be 2606 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 2607 NL_SET_ERR_MSG_MOD(extack,
2608 "Can't set inline mode when flows are configured");
8e0aa4bc
PP		 2609 err = -EOPNOTSUPP;
2610 goto out;
375f51e2
RD		 2611 }
2612
bffaa916
RD		 2613 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
2614 if (err)
2615 goto out;
2616
411ec9e0 2617 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
bffaa916
RD		 2618 err = mlx5_modify_nic_vport_min_inline(dev, vport, mlx5_mode);
2619 if (err) {
8c98ee77
EB		 2620 NL_SET_ERR_MSG_MOD(extack,
2621 "Failed to set min inline on vport");
bffaa916
RD		 2622 goto revert_inline_mode;
2623 }
2624 }
2625
2626 esw->offloads.inline_mode = mlx5_mode;
8e0aa4bc 2627 mutex_unlock(&esw->mode_lock);
bffaa916
RD		 2628 return 0;
2629
2630revert_inline_mode:
db68cc56 2631 num_vport = --vport;
411ec9e0 2632 mlx5_esw_for_each_host_func_vport_reverse(esw, vport, num_vport)
bffaa916
RD		 2633 mlx5_modify_nic_vport_min_inline(dev,
2634 vport,
2635 esw->offloads.inline_mode);
2636out:
8e0aa4bc 2637 mutex_unlock(&esw->mode_lock);
bffaa916
RD		 2638 return err;
2639}
2640
2641int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
2642{
2643 struct mlx5_core_dev *dev = devlink_priv(devlink);
2644 struct mlx5_eswitch *esw = dev->priv.eswitch;
9d1cef19 2645 int err;
bffaa916 2646
0e6fa491 2647 err = mlx5_eswitch_check(dev);
9d1cef19
OG		 2648 if (err)
2649 return err;
bffaa916 2650
8e0aa4bc 2651 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2652 err = eswitch_devlink_esw_mode_check(esw);
2653 if (err)
8e0aa4bc 2654 goto unlock;
ae24432c 2655
8e0aa4bc
PP		 2656 err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
2657unlock:
2658 mutex_unlock(&esw->mode_lock);
2659 return err;
bffaa916
RD		 2660}
2661
98fdbea5
LR		 2662int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
2663 enum devlink_eswitch_encap_mode encap,
db7ff19e 2664 struct netlink_ext_ack *extack)
7768d197
RD		 2665{
2666 struct mlx5_core_dev *dev = devlink_priv(devlink);
2667 struct mlx5_eswitch *esw = dev->priv.eswitch;
2668 int err;
2669
0e6fa491 2670 err = mlx5_eswitch_check(dev);
9d1cef19
OG		 2671 if (err)
2672 return err;
7768d197 2673
8e0aa4bc 2674 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2675 err = eswitch_devlink_esw_mode_check(esw);
2676 if (err)
8e0aa4bc 2677 goto unlock;
ae24432c 2678
7768d197 2679 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
60786f09 2680 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
8e0aa4bc
PP		 2681 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
2682 err = -EOPNOTSUPP;
2683 goto unlock;
2684 }
7768d197 2685
8e0aa4bc
PP		 2686 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
2687 err = -EOPNOTSUPP;
2688 goto unlock;
2689 }
7768d197 2690
f6455de0 2691 if (esw->mode == MLX5_ESWITCH_LEGACY) {
7768d197 2692 esw->offloads.encap = encap;
8e0aa4bc 2693 goto unlock;
7768d197
RD		 2694 }
2695
2696 if (esw->offloads.encap == encap)
8e0aa4bc 2697 goto unlock;
7768d197 2698
525e84be 2699 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 2700 NL_SET_ERR_MSG_MOD(extack,
2701 "Can't set encapsulation when flows are configured");
8e0aa4bc
PP		 2702 err = -EOPNOTSUPP;
2703 goto unlock;
7768d197
RD		 2704 }
2705
e52c2802 2706 esw_destroy_offloads_fdb_tables(esw);
7768d197
RD		 2707
2708 esw->offloads.encap = encap;
e52c2802
PB		 2709
2710 err = esw_create_offloads_fdb_tables(esw, esw->nvports);
2711
7768d197 2712 if (err) {
8c98ee77
EB		 2713 NL_SET_ERR_MSG_MOD(extack,
2714 "Failed re-creating fast FDB table");
7768d197 2715 esw->offloads.encap = !encap;
e52c2802 2716 (void)esw_create_offloads_fdb_tables(esw, esw->nvports);
7768d197 2717 }
e52c2802 2718
8e0aa4bc
PP		 2719unlock:
2720 mutex_unlock(&esw->mode_lock);
7768d197
RD		 2721 return err;
2722}
2723
98fdbea5
LR		 2724int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
2725 enum devlink_eswitch_encap_mode *encap)
7768d197
RD		 2726{
2727 struct mlx5_core_dev *dev = devlink_priv(devlink);
2728 struct mlx5_eswitch *esw = dev->priv.eswitch;
9d1cef19 2729 int err;
7768d197 2730
0e6fa491 2731 err = mlx5_eswitch_check(dev);
9d1cef19
OG		 2732 if (err)
2733 return err;
7768d197 2734
8e0aa4bc 2735 mutex_lock(&esw->mode_lock);
ae24432c
PP		 2736 err = eswitch_devlink_esw_mode_check(esw);
2737 if (err)
8e0aa4bc 2738 goto unlock;
ae24432c 2739
7768d197 2740 *encap = esw->offloads.encap;
8e0aa4bc
PP		 2741unlock:
2742 mutex_unlock(&esw->mode_lock);
7768d197
RD		 2743 return 0;
2744}
2745
c2d7712c
BW		 2746static bool
2747mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
2748{
2749 /* Currently, only ECPF based device has representor for host PF. */
2750 if (vport_num == MLX5_VPORT_PF &&
2751 !mlx5_core_is_ecpf_esw_manager(esw->dev))
2752 return false;
2753
2754 if (vport_num == MLX5_VPORT_ECPF &&
2755 !mlx5_ecpf_vport_exists(esw->dev))
2756 return false;
2757
2758 return true;
2759}
2760
f8e8fa02 2761void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
8693115a 2762 const struct mlx5_eswitch_rep_ops *ops,
f8e8fa02 2763 u8 rep_type)
127ea380 2764{
8693115a 2765 struct mlx5_eswitch_rep_data *rep_data;
f8e8fa02
BW		 2766 struct mlx5_eswitch_rep *rep;
2767 int i;
9deb2241 2768
8693115a 2769 esw->offloads.rep_ops[rep_type] = ops;
f8e8fa02 2770 mlx5_esw_for_all_reps(esw, i, rep) {
c2d7712c
BW		 2771 if (likely(mlx5_eswitch_vport_has_rep(esw, i))) {
2772 rep_data = &rep->rep_data[rep_type];
2773 atomic_set(&rep_data->state, REP_REGISTERED);
2774 }
f8e8fa02 2775 }
127ea380 2776}
f8e8fa02 2777EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
127ea380 2778
f8e8fa02 2779void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
127ea380 2780{
cb67b832 2781 struct mlx5_eswitch_rep *rep;
f8e8fa02 2782 int i;
cb67b832 2783
f6455de0 2784 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
062f4bf4 2785 __unload_reps_all_vport(esw, rep_type);
127ea380 2786
f8e8fa02 2787 mlx5_esw_for_all_reps(esw, i, rep)
8693115a 2788 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
127ea380 2789}
f8e8fa02 2790EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
726293f1 2791
a4b97ab4 2792void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
726293f1 2793{
726293f1
HHZ		 2794 struct mlx5_eswitch_rep *rep;
2795
879c8f84 2796 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
8693115a 2797 return rep->rep_data[rep_type].priv;
726293f1 2798}
22215908
MB		 2799
2800void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
02f3afd9 2801 u16 vport,
22215908
MB		 2802 u8 rep_type)
2803{
22215908
MB		 2804 struct mlx5_eswitch_rep *rep;
2805
879c8f84 2806 rep = mlx5_eswitch_get_rep(esw, vport);
22215908 2807
8693115a
PP		 2808 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2809 esw->offloads.rep_ops[rep_type]->get_proto_dev)
2810 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
22215908
MB		 2811 return NULL;
2812}
57cbd893 2813EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
22215908
MB		 2814
2815void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
2816{
879c8f84 2817 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
22215908 2818}
57cbd893
MB		 2819EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
2820
2821struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
02f3afd9 2822 u16 vport)
57cbd893 2823{
879c8f84 2824 return mlx5_eswitch_get_rep(esw, vport);
57cbd893
MB		 2825}
2826EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
91d6291c
PP		 2827
2828bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num)
2829{
2830 return vport_num >= MLX5_VPORT_FIRST_VF &&
2831 vport_num <= esw->dev->priv.sriov.max_vfs;
2832}
7445cfb1 2833
5b7cb745
PB		 2834bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
2835{
2836 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
2837}
2838EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
2839
7445cfb1
JL		 2840bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
2841{
2842 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
2843}
2844EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
2845
0f0d3827 2846u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
7445cfb1
JL		 2847 u16 vport_num)
2848{
0f0d3827
PB		 2849 u32 vport_num_mask = GENMASK(ESW_VPORT_BITS - 1, 0);
2850 u32 vhca_id_mask = GENMASK(ESW_VHCA_ID_BITS - 1, 0);
2851 u32 vhca_id = MLX5_CAP_GEN(esw->dev, vhca_id);
2852 u32 val;
2853
2854 /* Make sure the vhca_id fits the ESW_VHCA_ID_BITS */
2855 WARN_ON_ONCE(vhca_id >= BIT(ESW_VHCA_ID_BITS));
2856
2857 /* Trim vhca_id to ESW_VHCA_ID_BITS */
2858 vhca_id &= vhca_id_mask;
2859
2860 /* Make sure pf and ecpf map to end of ESW_VPORT_BITS range so they
2861 * don't overlap with VF numbers, and themselves, after trimming.
2862 */
2863 WARN_ON_ONCE((MLX5_VPORT_UPLINK & vport_num_mask) <
2864 vport_num_mask - 1);
2865 WARN_ON_ONCE((MLX5_VPORT_ECPF & vport_num_mask) <
2866 vport_num_mask - 1);
2867 WARN_ON_ONCE((MLX5_VPORT_UPLINK & vport_num_mask) ==
2868 (MLX5_VPORT_ECPF & vport_num_mask));
2869
2870 /* Make sure that the VF vport_num fits ESW_VPORT_BITS and don't
2871 * overlap with pf and ecpf.
2872 */
2873 if (vport_num != MLX5_VPORT_UPLINK &&
2874 vport_num != MLX5_VPORT_ECPF)
2875 WARN_ON_ONCE(vport_num >= vport_num_mask - 1);
2876
2877 /* We can now trim vport_num to ESW_VPORT_BITS */
2878 vport_num &= vport_num_mask;
2879
2880 val = (vhca_id << ESW_VPORT_BITS) | vport_num;
2881 return val << (32 - ESW_SOURCE_PORT_METADATA_BITS);
7445cfb1
JL		 2882}
2883EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
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