]> git.ipfire.org Git - people/arne_f/kernel.git/blame - drivers/net/ethernet/mellanox/mlx5/core/main.c
projects / people / arne_f / kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net/mlx5_core: Use accessor functions to read from device memory
[people/arne_f/kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <asm-generic/kmap_types.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e126ba97
EC		 42#include <linux/mlx5/driver.h>
43#include <linux/mlx5/cq.h>
44#include <linux/mlx5/qp.h>
45#include <linux/mlx5/srq.h>
46#include <linux/debugfs.h>
f66f049f 47#include <linux/kmod.h>
b775516b 48#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 49#include "mlx5_core.h"
50
e126ba97 51MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 52MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 53MODULE_LICENSE("Dual BSD/GPL");
54MODULE_VERSION(DRIVER_VERSION);
55
56int mlx5_core_debug_mask;
57module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
58MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
59
9603b61d
JM		 60#define MLX5_DEFAULT_PROF 2
61static int prof_sel = MLX5_DEFAULT_PROF;
62module_param_named(prof_sel, prof_sel, int, 0444);
63MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
64
e126ba97 65struct workqueue_struct *mlx5_core_wq;
9603b61d
JM		 66static LIST_HEAD(intf_list);
67static LIST_HEAD(dev_list);
68static DEFINE_MUTEX(intf_mutex);
69
70struct mlx5_device_context {
71 struct list_head list;
72 struct mlx5_interface *intf;
73 void *context;
74};
75
76static struct mlx5_profile profile[] = {
77 [0] = {
78 .mask = 0,
79 },
80 [1] = {
81 .mask = MLX5_PROF_MASK_QP_SIZE,
82 .log_max_qp = 12,
83 },
84 [2] = {
85 .mask = MLX5_PROF_MASK_QP_SIZE |
86 MLX5_PROF_MASK_MR_CACHE,
87 .log_max_qp = 17,
88 .mr_cache[0] = {
89 .size = 500,
90 .limit = 250
91 },
92 .mr_cache[1] = {
93 .size = 500,
94 .limit = 250
95 },
96 .mr_cache[2] = {
97 .size = 500,
98 .limit = 250
99 },
100 .mr_cache[3] = {
101 .size = 500,
102 .limit = 250
103 },
104 .mr_cache[4] = {
105 .size = 500,
106 .limit = 250
107 },
108 .mr_cache[5] = {
109 .size = 500,
110 .limit = 250
111 },
112 .mr_cache[6] = {
113 .size = 500,
114 .limit = 250
115 },
116 .mr_cache[7] = {
117 .size = 500,
118 .limit = 250
119 },
120 .mr_cache[8] = {
121 .size = 500,
122 .limit = 250
123 },
124 .mr_cache[9] = {
125 .size = 500,
126 .limit = 250
127 },
128 .mr_cache[10] = {
129 .size = 500,
130 .limit = 250
131 },
132 .mr_cache[11] = {
133 .size = 500,
134 .limit = 250
135 },
136 .mr_cache[12] = {
137 .size = 64,
138 .limit = 32
139 },
140 .mr_cache[13] = {
141 .size = 32,
142 .limit = 16
143 },
144 .mr_cache[14] = {
145 .size = 16,
146 .limit = 8
147 },
148 .mr_cache[15] = {
149 .size = 8,
150 .limit = 4
151 },
152 },
153};
e126ba97
EC		 154
155static int set_dma_caps(struct pci_dev *pdev)
156{
157 int err;
158
159 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
160 if (err) {
1a91de28 161 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 162 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
163 if (err) {
1a91de28 164 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 165 return err;
166 }
167 }
168
169 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
170 if (err) {
171 dev_warn(&pdev->dev,
1a91de28 172 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 173 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
174 if (err) {
175 dev_err(&pdev->dev,
1a91de28 176 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 177 return err;
178 }
179 }
180
181 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
182 return err;
183}
184
185static int request_bar(struct pci_dev *pdev)
186{
187 int err = 0;
188
189 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 190 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 191 return -ENODEV;
192 }
193
194 err = pci_request_regions(pdev, DRIVER_NAME);
195 if (err)
196 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
197
198 return err;
199}
200
201static void release_bar(struct pci_dev *pdev)
202{
203 pci_release_regions(pdev);
204}
205
206static int mlx5_enable_msix(struct mlx5_core_dev *dev)
207{
db058a18
SM		 208 struct mlx5_priv *priv = &dev->priv;
209 struct mlx5_eq_table *table = &priv->eq_table;
938fe83c 210 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
e126ba97 211 int nvec;
e126ba97
EC		 212 int i;
213
938fe83c
SM		 214 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
215 MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 216 nvec = min_t(int, nvec, num_eqs);
217 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
218 return -ENOMEM;
219
db058a18
SM		 220 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
221
222 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
223 if (!priv->msix_arr || !priv->irq_info)
224 goto err_free_msix;
e126ba97
EC		 225
226 for (i = 0; i < nvec; i++)
db058a18 227 priv->msix_arr[i].entry = i;
e126ba97 228
db058a18 229 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
3a9e161a 230 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 231 if (nvec < 0)
232 return nvec;
e126ba97 233
f3c9407b 234 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 235
236 return 0;
db058a18
SM		 237
238err_free_msix:
239 kfree(priv->irq_info);
240 kfree(priv->msix_arr);
241 return -ENOMEM;
e126ba97
EC		 242}
243
244static void mlx5_disable_msix(struct mlx5_core_dev *dev)
245{
db058a18 246 struct mlx5_priv *priv = &dev->priv;
e126ba97
EC		 247
248 pci_disable_msix(dev->pdev);
db058a18
SM		 249 kfree(priv->irq_info);
250 kfree(priv->msix_arr);
e126ba97
EC		 251}
252
253struct mlx5_reg_host_endianess {
254 u8 he;
255 u8 rsvd[15];
256};
257
87b8de49
EC		 258
259#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
260
261enum {
c7a08ac7
EC		 262 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
263 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 264};
265
c7a08ac7
EC		 266static u16 to_fw_pkey_sz(u32 size)
267{
268 switch (size) {
269 case 128:
270 return 0;
271 case 256:
272 return 1;
273 case 512:
274 return 2;
275 case 1024:
276 return 3;
277 case 2048:
278 return 4;
279 case 4096:
280 return 5;
281 default:
282 pr_warn("invalid pkey table size %d\n", size);
283 return 0;
284 }
285}
286
938fe83c
SM		 287int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
288 enum mlx5_cap_mode cap_mode)
c7a08ac7 289{
b775516b
EC		 290 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
291 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
938fe83c
SM		 292 void *out, *hca_caps;
293 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
e126ba97
EC		 294 int err;
295
b775516b
EC		 296 memset(in, 0, sizeof(in));
297 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 298 if (!out)
e126ba97 299 return -ENOMEM;
938fe83c 300
b775516b
EC		 301 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
302 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
303 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
304 if (err)
305 goto query_ex;
e126ba97 306
b775516b 307 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7 308 if (err) {
938fe83c
SM		 309 mlx5_core_warn(dev,
310 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
311 cap_type, cap_mode, err);
e126ba97
EC		 312 goto query_ex;
313 }
c7a08ac7 314
938fe83c
SM		 315 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
316
317 switch (cap_mode) {
318 case HCA_CAP_OPMOD_GET_MAX:
319 memcpy(dev->hca_caps_max[cap_type], hca_caps,
320 MLX5_UN_SZ_BYTES(hca_cap_union));
321 break;
322 case HCA_CAP_OPMOD_GET_CUR:
323 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
324 MLX5_UN_SZ_BYTES(hca_cap_union));
325 break;
326 default:
327 mlx5_core_warn(dev,
328 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
329 cap_type, cap_mode);
330 err = -EINVAL;
331 break;
332 }
c7a08ac7
EC		 333query_ex:
334 kfree(out);
335 return err;
336}
337
b775516b 338static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
c7a08ac7 339{
b775516b 340 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
c7a08ac7
EC		 341 int err;
342
b775516b 343 memset(out, 0, sizeof(out));
e126ba97 344
b775516b
EC		 345 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
346 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
e126ba97 347 if (err)
c7a08ac7 348 return err;
e126ba97 349
b775516b 350 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 351
352 return err;
353}
354
355static int handle_hca_cap(struct mlx5_core_dev *dev)
356{
b775516b 357 void *set_ctx = NULL;
c7a08ac7 358 struct mlx5_profile *prof = dev->profile;
c7a08ac7 359 int err = -ENOMEM;
b775516b 360 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
938fe83c 361 void *set_hca_cap;
c7a08ac7 362
b775516b 363 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 364 if (!set_ctx)
e126ba97 365 goto query_ex;
e126ba97 366
938fe83c 367 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
c7a08ac7 368 if (err)
e126ba97 369 goto query_ex;
e126ba97 370
938fe83c 371 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
e126ba97
EC		 372 if (err)
373 goto query_ex;
374
938fe83c
SM		 375 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
376 capability);
377 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
378 MLX5_ST_SZ_BYTES(cmd_hca_cap));
379
380 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
707c4602 381 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
938fe83c 382 128);
c7a08ac7 383 /* we limit the size of the pkey table to 128 entries for now */
938fe83c
SM		 384 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
385 to_fw_pkey_sz(128));
c7a08ac7
EC		 386
387 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
938fe83c
SM		 388 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
389 prof->log_max_qp);
c7a08ac7 390
938fe83c
SM		 391 /* disable cmdif checksum */
392 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
c7a08ac7 393
fe1e1876
CS		 394 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
395
b775516b 396 err = set_caps(dev, set_ctx, set_sz);
c7a08ac7 397
e126ba97 398query_ex:
e126ba97 399 kfree(set_ctx);
e126ba97
EC		 400 return err;
401}
402
403static int set_hca_ctrl(struct mlx5_core_dev *dev)
404{
405 struct mlx5_reg_host_endianess he_in;
406 struct mlx5_reg_host_endianess he_out;
407 int err;
408
409 memset(&he_in, 0, sizeof(he_in));
410 he_in.he = MLX5_SET_HOST_ENDIANNESS;
411 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
412 &he_out, sizeof(he_out),
413 MLX5_REG_HOST_ENDIANNESS, 0, 1);
414 return err;
415}
416
cd23b14b
EC		 417static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
418{
419 int err;
420 struct mlx5_enable_hca_mbox_in in;
421 struct mlx5_enable_hca_mbox_out out;
422
423 memset(&in, 0, sizeof(in));
424 memset(&out, 0, sizeof(out));
425 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
426 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
427 if (err)
428 return err;
429
430 if (out.hdr.status)
431 return mlx5_cmd_status_to_err(&out.hdr);
432
433 return 0;
434}
435
436static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
437{
438 int err;
439 struct mlx5_disable_hca_mbox_in in;
440 struct mlx5_disable_hca_mbox_out out;
441
442 memset(&in, 0, sizeof(in));
443 memset(&out, 0, sizeof(out));
444 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
445 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
446 if (err)
447 return err;
448
449 if (out.hdr.status)
450 return mlx5_cmd_status_to_err(&out.hdr);
451
452 return 0;
453}
454
db058a18
SM		 455static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
456{
457 struct mlx5_priv *priv = &mdev->priv;
458 struct msix_entry *msix = priv->msix_arr;
459 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
311c7c71 460 int numa_node = priv->numa_node;
db058a18
SM		 461 int err;
462
463 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
464 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
465 return -ENOMEM;
466 }
467
dda922c8
DM		 468 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
469 priv->irq_info[i].mask);
db058a18
SM		 470
471 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
472 if (err) {
473 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
474 irq);
475 goto err_clear_mask;
476 }
477
478 return 0;
479
480err_clear_mask:
481 free_cpumask_var(priv->irq_info[i].mask);
482 return err;
483}
484
485static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
486{
487 struct mlx5_priv *priv = &mdev->priv;
488 struct msix_entry *msix = priv->msix_arr;
489 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
490
491 irq_set_affinity_hint(irq, NULL);
492 free_cpumask_var(priv->irq_info[i].mask);
493}
494
495static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
496{
497 int err;
498 int i;
499
500 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
501 err = mlx5_irq_set_affinity_hint(mdev, i);
502 if (err)
503 goto err_out;
504 }
505
506 return 0;
507
508err_out:
509 for (i--; i >= 0; i--)
510 mlx5_irq_clear_affinity_hint(mdev, i);
511
512 return err;
513}
514
515static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
516{
517 int i;
518
519 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
520 mlx5_irq_clear_affinity_hint(mdev, i);
521}
522
233d05d2
SM		 523int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
524{
525 struct mlx5_eq_table *table = &dev->priv.eq_table;
526 struct mlx5_eq *eq, *n;
527 int err = -ENOENT;
528
529 spin_lock(&table->lock);
530 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
531 if (eq->index == vector) {
532 *eqn = eq->eqn;
533 *irqn = eq->irqn;
534 err = 0;
535 break;
536 }
537 }
538 spin_unlock(&table->lock);
539
540 return err;
541}
542EXPORT_SYMBOL(mlx5_vector2eqn);
543
544static void free_comp_eqs(struct mlx5_core_dev *dev)
545{
546 struct mlx5_eq_table *table = &dev->priv.eq_table;
547 struct mlx5_eq *eq, *n;
548
549 spin_lock(&table->lock);
550 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
551 list_del(&eq->list);
552 spin_unlock(&table->lock);
553 if (mlx5_destroy_unmap_eq(dev, eq))
554 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
555 eq->eqn);
556 kfree(eq);
557 spin_lock(&table->lock);
558 }
559 spin_unlock(&table->lock);
560}
561
562static int alloc_comp_eqs(struct mlx5_core_dev *dev)
563{
564 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 565 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 566 struct mlx5_eq *eq;
567 int ncomp_vec;
568 int nent;
569 int err;
570 int i;
571
572 INIT_LIST_HEAD(&table->comp_eqs_list);
573 ncomp_vec = table->num_comp_vectors;
574 nent = MLX5_COMP_EQ_SIZE;
575 for (i = 0; i < ncomp_vec; i++) {
576 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
577 if (!eq) {
578 err = -ENOMEM;
579 goto clean;
580 }
581
db058a18 582 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 583 err = mlx5_create_map_eq(dev, eq,
584 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
585 name, &dev->priv.uuari.uars[0]);
586 if (err) {
587 kfree(eq);
588 goto clean;
589 }
590 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
591 eq->index = i;
592 spin_lock(&table->lock);
593 list_add_tail(&eq->list, &table->comp_eqs_list);
594 spin_unlock(&table->lock);
595 }
596
597 return 0;
598
599clean:
600 free_comp_eqs(dev);
601 return err;
602}
603
f62b8bb8
AV		 604#ifdef CONFIG_MLX5_CORE_EN
605static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
606{
607 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
608 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
609 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
610 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
611 int err;
612 u32 sup_issi;
613
614 memset(query_in, 0, sizeof(query_in));
615 memset(query_out, 0, sizeof(query_out));
616
617 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
618
619 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
620 query_out, sizeof(query_out));
621 if (err) {
622 if (((struct mlx5_outbox_hdr *)query_out)->status ==
623 MLX5_CMD_STAT_BAD_OP_ERR) {
624 pr_debug("Only ISSI 0 is supported\n");
625 return 0;
626 }
627
628 pr_err("failed to query ISSI\n");
629 return err;
630 }
631
632 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
633
634 if (sup_issi & (1 << 1)) {
635 memset(set_in, 0, sizeof(set_in));
636 memset(set_out, 0, sizeof(set_out));
637
638 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
639 MLX5_SET(set_issi_in, set_in, current_issi, 1);
640
641 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
642 set_out, sizeof(set_out));
643 if (err) {
644 pr_err("failed to set ISSI=1\n");
645 return err;
646 }
647
648 dev->issi = 1;
649
650 return 0;
e74a1db0 651 } else if (sup_issi & (1 << 0) || !sup_issi) {
f62b8bb8
AV		 652 return 0;
653 }
654
655 return -ENOTSUPP;
656}
657#endif
658
88a85f99
AS		 659static int map_bf_area(struct mlx5_core_dev *dev)
660{
661 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
662 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
663
664 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
665
666 return dev->priv.bf_mapping ? 0 : -ENOMEM;
667}
668
669static void unmap_bf_area(struct mlx5_core_dev *dev)
670{
671 if (dev->priv.bf_mapping)
672 io_mapping_free(dev->priv.bf_mapping);
673}
674
a31208b1
MD		 675static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
676{
677 struct mlx5_device_context *dev_ctx;
678 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
679
680 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
681 if (!dev_ctx)
682 return;
683
684 dev_ctx->intf = intf;
685 dev_ctx->context = intf->add(dev);
686
687 if (dev_ctx->context) {
688 spin_lock_irq(&priv->ctx_lock);
689 list_add_tail(&dev_ctx->list, &priv->ctx_list);
690 spin_unlock_irq(&priv->ctx_lock);
691 } else {
692 kfree(dev_ctx);
693 }
694}
695
696static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
697{
698 struct mlx5_device_context *dev_ctx;
699 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
700
701 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
702 if (dev_ctx->intf == intf) {
703 spin_lock_irq(&priv->ctx_lock);
704 list_del(&dev_ctx->list);
705 spin_unlock_irq(&priv->ctx_lock);
706
707 intf->remove(dev, dev_ctx->context);
708 kfree(dev_ctx);
709 return;
710 }
711}
712
713static int mlx5_register_device(struct mlx5_core_dev *dev)
e126ba97
EC		 714{
715 struct mlx5_priv *priv = &dev->priv;
a31208b1
MD		 716 struct mlx5_interface *intf;
717
718 mutex_lock(&intf_mutex);
719 list_add_tail(&priv->dev_list, &dev_list);
720 list_for_each_entry(intf, &intf_list, list)
721 mlx5_add_device(intf, priv);
722 mutex_unlock(&intf_mutex);
723
724 return 0;
725}
726
727static void mlx5_unregister_device(struct mlx5_core_dev *dev)
728{
729 struct mlx5_priv *priv = &dev->priv;
730 struct mlx5_interface *intf;
731
732 mutex_lock(&intf_mutex);
733 list_for_each_entry(intf, &intf_list, list)
734 mlx5_remove_device(intf, priv);
735 list_del(&priv->dev_list);
736 mutex_unlock(&intf_mutex);
737}
738
739int mlx5_register_interface(struct mlx5_interface *intf)
740{
741 struct mlx5_priv *priv;
742
743 if (!intf->add || !intf->remove)
744 return -EINVAL;
745
746 mutex_lock(&intf_mutex);
747 list_add_tail(&intf->list, &intf_list);
748 list_for_each_entry(priv, &dev_list, dev_list)
749 mlx5_add_device(intf, priv);
750 mutex_unlock(&intf_mutex);
751
752 return 0;
753}
754EXPORT_SYMBOL(mlx5_register_interface);
755
756void mlx5_unregister_interface(struct mlx5_interface *intf)
757{
758 struct mlx5_priv *priv;
759
760 mutex_lock(&intf_mutex);
761 list_for_each_entry(priv, &dev_list, dev_list)
762 mlx5_remove_device(intf, priv);
763 list_del(&intf->list);
764 mutex_unlock(&intf_mutex);
765}
766EXPORT_SYMBOL(mlx5_unregister_interface);
767
768void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
769{
770 struct mlx5_priv *priv = &mdev->priv;
771 struct mlx5_device_context *dev_ctx;
772 unsigned long flags;
773 void *result = NULL;
774
775 spin_lock_irqsave(&priv->ctx_lock, flags);
776
777 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
778 if ((dev_ctx->intf->protocol == protocol) &&
779 dev_ctx->intf->get_dev) {
780 result = dev_ctx->intf->get_dev(dev_ctx->context);
781 break;
782 }
783
784 spin_unlock_irqrestore(&priv->ctx_lock, flags);
785
786 return result;
787}
788EXPORT_SYMBOL(mlx5_get_protocol_dev);
789
790static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
791{
792 struct pci_dev *pdev = dev->pdev;
793 int err = 0;
e126ba97 794
e126ba97
EC		 795 pci_set_drvdata(dev->pdev, dev);
796 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
797 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
798
799 mutex_init(&priv->pgdir_mutex);
800 INIT_LIST_HEAD(&priv->pgdir_list);
801 spin_lock_init(&priv->mkey_lock);
802
311c7c71
SM		 803 mutex_init(&priv->alloc_mutex);
804
805 priv->numa_node = dev_to_node(&dev->pdev->dev);
806
e126ba97
EC		 807 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
808 if (!priv->dbg_root)
809 return -ENOMEM;
810
811 err = pci_enable_device(pdev);
812 if (err) {
1a91de28 813 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 814 goto err_dbg;
815 }
816
817 err = request_bar(pdev);
818 if (err) {
1a91de28 819 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 820 goto err_disable;
821 }
822
823 pci_set_master(pdev);
824
825 err = set_dma_caps(pdev);
826 if (err) {
827 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
828 goto err_clr_master;
829 }
830
831 dev->iseg_base = pci_resource_start(dev->pdev, 0);
832 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
833 if (!dev->iseg) {
834 err = -ENOMEM;
835 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
836 goto err_clr_master;
837 }
a31208b1
MD		 838
839 return 0;
840
841err_clr_master:
842 pci_clear_master(dev->pdev);
843 release_bar(dev->pdev);
844err_disable:
845 pci_disable_device(dev->pdev);
846
847err_dbg:
848 debugfs_remove(priv->dbg_root);
849 return err;
850}
851
852static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
853{
854 iounmap(dev->iseg);
855 pci_clear_master(dev->pdev);
856 release_bar(dev->pdev);
857 pci_disable_device(dev->pdev);
858 debugfs_remove(priv->dbg_root);
859}
860
861#define MLX5_IB_MOD "mlx5_ib"
862static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
863{
864 struct pci_dev *pdev = dev->pdev;
865 int err;
866
e126ba97
EC		 867 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
868 fw_rev_min(dev), fw_rev_sub(dev));
869
870 err = mlx5_cmd_init(dev);
871 if (err) {
872 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
a31208b1 873 return err;
e126ba97
EC		 874 }
875
876 mlx5_pagealloc_init(dev);
cd23b14b
EC		 877
878 err = mlx5_core_enable_hca(dev);
879 if (err) {
880 dev_err(&pdev->dev, "enable hca failed\n");
881 goto err_pagealloc_cleanup;
882 }
883
f62b8bb8
AV		 884#ifdef CONFIG_MLX5_CORE_EN
885 err = mlx5_core_set_issi(dev);
886 if (err) {
887 dev_err(&pdev->dev, "failed to set issi\n");
888 goto err_disable_hca;
889 }
890#endif
891
cd23b14b
EC		 892 err = mlx5_satisfy_startup_pages(dev, 1);
893 if (err) {
894 dev_err(&pdev->dev, "failed to allocate boot pages\n");
895 goto err_disable_hca;
896 }
897
e126ba97
EC		 898 err = set_hca_ctrl(dev);
899 if (err) {
900 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 901 goto reclaim_boot_pages;
e126ba97
EC		 902 }
903
904 err = handle_hca_cap(dev);
905 if (err) {
906 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 907 goto reclaim_boot_pages;
e126ba97
EC		 908 }
909
cd23b14b 910 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 911 if (err) {
cd23b14b
EC		 912 dev_err(&pdev->dev, "failed to allocate init pages\n");
913 goto reclaim_boot_pages;
e126ba97
EC		 914 }
915
916 err = mlx5_pagealloc_start(dev);
917 if (err) {
918 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 919 goto reclaim_boot_pages;
e126ba97
EC		 920 }
921
922 err = mlx5_cmd_init_hca(dev);
923 if (err) {
924 dev_err(&pdev->dev, "init hca failed\n");
925 goto err_pagealloc_stop;
926 }
927
928 mlx5_start_health_poll(dev);
929
938fe83c 930 err = mlx5_query_hca_caps(dev);
e126ba97
EC		 931 if (err) {
932 dev_err(&pdev->dev, "query hca failed\n");
933 goto err_stop_poll;
934 }
935
211e6c80 936 err = mlx5_query_board_id(dev);
e126ba97 937 if (err) {
211e6c80 938 dev_err(&pdev->dev, "query board id failed\n");
e126ba97
EC		 939 goto err_stop_poll;
940 }
941
942 err = mlx5_enable_msix(dev);
943 if (err) {
944 dev_err(&pdev->dev, "enable msix failed\n");
945 goto err_stop_poll;
946 }
947
948 err = mlx5_eq_init(dev);
949 if (err) {
950 dev_err(&pdev->dev, "failed to initialize eq\n");
951 goto disable_msix;
952 }
953
954 err = mlx5_alloc_uuars(dev, &priv->uuari);
955 if (err) {
956 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
957 goto err_eq_cleanup;
958 }
959
960 err = mlx5_start_eqs(dev);
961 if (err) {
962 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
963 goto err_free_uar;
964 }
965
233d05d2
SM		 966 err = alloc_comp_eqs(dev);
967 if (err) {
968 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
969 goto err_stop_eqs;
970 }
971
88a85f99
AS		 972 if (map_bf_area(dev))
973 dev_err(&pdev->dev, "Failed to map blue flame area\n");
974
db058a18
SM		 975 err = mlx5_irq_set_affinity_hints(dev);
976 if (err) {
977 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
88a85f99 978 goto err_unmap_bf_area;
db058a18
SM		 979 }
980
e126ba97
EC		 981 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
982
983 mlx5_init_cq_table(dev);
984 mlx5_init_qp_table(dev);
985 mlx5_init_srq_table(dev);
3bcdb17a 986 mlx5_init_mr_table(dev);
e126ba97 987
a31208b1
MD		 988 err = mlx5_register_device(dev);
989 if (err) {
990 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
991 goto err_reg_dev;
992 }
993
994 err = request_module_nowait(MLX5_IB_MOD);
995 if (err)
996 pr_info("failed request module on %s\n", MLX5_IB_MOD);
997
e126ba97
EC		 998 return 0;
999
a31208b1
MD		 1000err_reg_dev:
1001 mlx5_cleanup_mr_table(dev);
1002 mlx5_cleanup_srq_table(dev);
1003 mlx5_cleanup_qp_table(dev);
1004 mlx5_cleanup_cq_table(dev);
1005 mlx5_irq_clear_affinity_hints(dev);
1006
88a85f99
AS		 1007err_unmap_bf_area:
1008 unmap_bf_area(dev);
1009
db058a18
SM		 1010 free_comp_eqs(dev);
1011
233d05d2
SM		 1012err_stop_eqs:
1013 mlx5_stop_eqs(dev);
1014
e126ba97
EC		 1015err_free_uar:
1016 mlx5_free_uuars(dev, &priv->uuari);
1017
1018err_eq_cleanup:
1019 mlx5_eq_cleanup(dev);
1020
1021disable_msix:
1022 mlx5_disable_msix(dev);
1023
1024err_stop_poll:
1025 mlx5_stop_health_poll(dev);
1bde6e30
EC		 1026 if (mlx5_cmd_teardown_hca(dev)) {
1027 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1028 return err;
1029 }
e126ba97
EC		 1030
1031err_pagealloc_stop:
1032 mlx5_pagealloc_stop(dev);
1033
cd23b14b 1034reclaim_boot_pages:
e126ba97
EC		 1035 mlx5_reclaim_startup_pages(dev);
1036
cd23b14b
EC		 1037err_disable_hca:
1038 mlx5_core_disable_hca(dev);
1039
e126ba97
EC		 1040err_pagealloc_cleanup:
1041 mlx5_pagealloc_cleanup(dev);
1042 mlx5_cmd_cleanup(dev);
1043
e126ba97
EC		 1044 return err;
1045}
e126ba97 1046
a31208b1 1047static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
e126ba97 1048{
e126ba97 1049
a31208b1
MD		 1050 mlx5_unregister_device(dev);
1051 mlx5_cleanup_mr_table(dev);
e126ba97
EC		 1052 mlx5_cleanup_srq_table(dev);
1053 mlx5_cleanup_qp_table(dev);
1054 mlx5_cleanup_cq_table(dev);
db058a18 1055 mlx5_irq_clear_affinity_hints(dev);
88a85f99 1056 unmap_bf_area(dev);
233d05d2 1057 free_comp_eqs(dev);
e126ba97
EC		 1058 mlx5_stop_eqs(dev);
1059 mlx5_free_uuars(dev, &priv->uuari);
1060 mlx5_eq_cleanup(dev);
1061 mlx5_disable_msix(dev);
1062 mlx5_stop_health_poll(dev);
1bde6e30
EC		 1063 if (mlx5_cmd_teardown_hca(dev)) {
1064 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
a31208b1 1065 return 1;
1bde6e30 1066 }
e126ba97
EC		 1067 mlx5_pagealloc_stop(dev);
1068 mlx5_reclaim_startup_pages(dev);
cd23b14b 1069 mlx5_core_disable_hca(dev);
e126ba97
EC		 1070 mlx5_pagealloc_cleanup(dev);
1071 mlx5_cmd_cleanup(dev);
9603b61d
JM		 1072
1073 return 0;
1074}
64613d94 1075
9603b61d 1076static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
4d2f9bbb 1077 unsigned long param)
9603b61d
JM		 1078{
1079 struct mlx5_priv *priv = &dev->priv;
1080 struct mlx5_device_context *dev_ctx;
1081 unsigned long flags;
1082
1083 spin_lock_irqsave(&priv->ctx_lock, flags);
1084
1085 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1086 if (dev_ctx->intf->event)
4d2f9bbb 1087 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
9603b61d
JM		 1088
1089 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1090}
1091
1092struct mlx5_core_event_handler {
1093 void (*event)(struct mlx5_core_dev *dev,
1094 enum mlx5_dev_event event,
1095 void *data);
1096};
1097
f66f049f 1098
9603b61d
JM		 1099static int init_one(struct pci_dev *pdev,
1100 const struct pci_device_id *id)
1101{
1102 struct mlx5_core_dev *dev;
1103 struct mlx5_priv *priv;
1104 int err;
1105
1106 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1107 if (!dev) {
1108 dev_err(&pdev->dev, "kzalloc failed\n");
1109 return -ENOMEM;
1110 }
1111 priv = &dev->priv;
1112
1113 pci_set_drvdata(pdev, dev);
1114
1115 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1116 pr_warn("selected profile out of range, selecting default (%d)\n",
1117 MLX5_DEFAULT_PROF);
1118 prof_sel = MLX5_DEFAULT_PROF;
1119 }
1120 dev->profile = &profile[prof_sel];
a31208b1 1121 dev->pdev = pdev;
9603b61d
JM		 1122 dev->event = mlx5_core_event;
1123
364d1798
EC		 1124 INIT_LIST_HEAD(&priv->ctx_list);
1125 spin_lock_init(&priv->ctx_lock);
a31208b1 1126 err = mlx5_pci_init(dev, priv);
9603b61d 1127 if (err) {
a31208b1
MD		 1128 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1129 goto clean_dev;
9603b61d
JM		 1130 }
1131
a31208b1 1132 err = mlx5_load_one(dev, priv);
9603b61d 1133 if (err) {
a31208b1
MD		 1134 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1135 goto close_pci;
9603b61d
JM		 1136 }
1137
1138 return 0;
1139
a31208b1
MD		 1140close_pci:
1141 mlx5_pci_close(dev, priv);
1142clean_dev:
1143 pci_set_drvdata(pdev, NULL);
9603b61d 1144 kfree(dev);
a31208b1 1145
9603b61d
JM		 1146 return err;
1147}
a31208b1 1148
9603b61d
JM		 1149static void remove_one(struct pci_dev *pdev)
1150{
1151 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
a31208b1 1152 struct mlx5_priv *priv = &dev->priv;
9603b61d 1153
a31208b1
MD		 1154 if (mlx5_unload_one(dev, priv)) {
1155 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1156 return;
1157 }
1158 mlx5_pci_close(dev, priv);
1159 pci_set_drvdata(pdev, NULL);
9603b61d
JM		 1160 kfree(dev);
1161}
1162
1163static const struct pci_device_id mlx5_core_pci_table[] = {
1c755cc5
OG		 1164 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1165 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1166 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1167 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1168 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1169 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
9603b61d
JM		 1170 { 0, }
1171};
1172
1173MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1174
1175static struct pci_driver mlx5_core_driver = {
1176 .name = DRIVER_NAME,
1177 .id_table = mlx5_core_pci_table,
1178 .probe = init_one,
1179 .remove = remove_one
1180};
e126ba97
EC		 1181
1182static int __init init(void)
1183{
1184 int err;
1185
1186 mlx5_register_debugfs();
1187 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
1188 if (!mlx5_core_wq) {
1189 err = -ENOMEM;
1190 goto err_debug;
1191 }
1192 mlx5_health_init();
1193
9603b61d
JM		 1194 err = pci_register_driver(&mlx5_core_driver);
1195 if (err)
1196 goto err_health;
1197
f62b8bb8
AV		 1198#ifdef CONFIG_MLX5_CORE_EN
1199 mlx5e_init();
1200#endif
1201
e126ba97
EC		 1202 return 0;
1203
9603b61d
JM		 1204err_health:
1205 mlx5_health_cleanup();
1206 destroy_workqueue(mlx5_core_wq);
e126ba97
EC		 1207err_debug:
1208 mlx5_unregister_debugfs();
1209 return err;
1210}
1211
1212static void __exit cleanup(void)
1213{
f62b8bb8
AV		 1214#ifdef CONFIG_MLX5_CORE_EN
1215 mlx5e_cleanup();
1216#endif
9603b61d 1217 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1218 mlx5_health_cleanup();
1219 destroy_workqueue(mlx5_core_wq);
1220 mlx5_unregister_debugfs();
1221}
1222
1223module_init(init);
1224module_exit(cleanup);
Arne's tree of linux kernel.