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net/mlx5_core: Enable XRCs and SRQs when using ISSI > 0
[people/arne_f/kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <asm-generic/kmap_types.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e126ba97
EC		 42#include <linux/mlx5/driver.h>
43#include <linux/mlx5/cq.h>
44#include <linux/mlx5/qp.h>
45#include <linux/mlx5/srq.h>
46#include <linux/debugfs.h>
f66f049f 47#include <linux/kmod.h>
b775516b 48#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 49#include "mlx5_core.h"
50
e126ba97 51MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 52MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 53MODULE_LICENSE("Dual BSD/GPL");
54MODULE_VERSION(DRIVER_VERSION);
55
56int mlx5_core_debug_mask;
57module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
58MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
59
9603b61d
JM		 60#define MLX5_DEFAULT_PROF 2
61static int prof_sel = MLX5_DEFAULT_PROF;
62module_param_named(prof_sel, prof_sel, int, 0444);
63MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
64
e126ba97 65struct workqueue_struct *mlx5_core_wq;
9603b61d
JM		 66static LIST_HEAD(intf_list);
67static LIST_HEAD(dev_list);
68static DEFINE_MUTEX(intf_mutex);
69
70struct mlx5_device_context {
71 struct list_head list;
72 struct mlx5_interface *intf;
73 void *context;
74};
75
76static struct mlx5_profile profile[] = {
77 [0] = {
78 .mask = 0,
79 },
80 [1] = {
81 .mask = MLX5_PROF_MASK_QP_SIZE,
82 .log_max_qp = 12,
83 },
84 [2] = {
85 .mask = MLX5_PROF_MASK_QP_SIZE |
86 MLX5_PROF_MASK_MR_CACHE,
87 .log_max_qp = 17,
88 .mr_cache[0] = {
89 .size = 500,
90 .limit = 250
91 },
92 .mr_cache[1] = {
93 .size = 500,
94 .limit = 250
95 },
96 .mr_cache[2] = {
97 .size = 500,
98 .limit = 250
99 },
100 .mr_cache[3] = {
101 .size = 500,
102 .limit = 250
103 },
104 .mr_cache[4] = {
105 .size = 500,
106 .limit = 250
107 },
108 .mr_cache[5] = {
109 .size = 500,
110 .limit = 250
111 },
112 .mr_cache[6] = {
113 .size = 500,
114 .limit = 250
115 },
116 .mr_cache[7] = {
117 .size = 500,
118 .limit = 250
119 },
120 .mr_cache[8] = {
121 .size = 500,
122 .limit = 250
123 },
124 .mr_cache[9] = {
125 .size = 500,
126 .limit = 250
127 },
128 .mr_cache[10] = {
129 .size = 500,
130 .limit = 250
131 },
132 .mr_cache[11] = {
133 .size = 500,
134 .limit = 250
135 },
136 .mr_cache[12] = {
137 .size = 64,
138 .limit = 32
139 },
140 .mr_cache[13] = {
141 .size = 32,
142 .limit = 16
143 },
144 .mr_cache[14] = {
145 .size = 16,
146 .limit = 8
147 },
148 .mr_cache[15] = {
149 .size = 8,
150 .limit = 4
151 },
152 },
153};
e126ba97
EC		 154
155static int set_dma_caps(struct pci_dev *pdev)
156{
157 int err;
158
159 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
160 if (err) {
1a91de28 161 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 162 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
163 if (err) {
1a91de28 164 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 165 return err;
166 }
167 }
168
169 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
170 if (err) {
171 dev_warn(&pdev->dev,
1a91de28 172 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 173 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
174 if (err) {
175 dev_err(&pdev->dev,
1a91de28 176 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 177 return err;
178 }
179 }
180
181 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
182 return err;
183}
184
185static int request_bar(struct pci_dev *pdev)
186{
187 int err = 0;
188
189 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 190 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 191 return -ENODEV;
192 }
193
194 err = pci_request_regions(pdev, DRIVER_NAME);
195 if (err)
196 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
197
198 return err;
199}
200
201static void release_bar(struct pci_dev *pdev)
202{
203 pci_release_regions(pdev);
204}
205
206static int mlx5_enable_msix(struct mlx5_core_dev *dev)
207{
db058a18
SM		 208 struct mlx5_priv *priv = &dev->priv;
209 struct mlx5_eq_table *table = &priv->eq_table;
938fe83c 210 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
e126ba97 211 int nvec;
e126ba97
EC		 212 int i;
213
938fe83c
SM		 214 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
215 MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 216 nvec = min_t(int, nvec, num_eqs);
217 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
218 return -ENOMEM;
219
db058a18
SM		 220 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
221
222 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
223 if (!priv->msix_arr || !priv->irq_info)
224 goto err_free_msix;
e126ba97
EC		 225
226 for (i = 0; i < nvec; i++)
db058a18 227 priv->msix_arr[i].entry = i;
e126ba97 228
db058a18 229 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
3a9e161a 230 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 231 if (nvec < 0)
232 return nvec;
e126ba97 233
f3c9407b 234 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 235
236 return 0;
db058a18
SM		 237
238err_free_msix:
239 kfree(priv->irq_info);
240 kfree(priv->msix_arr);
241 return -ENOMEM;
e126ba97
EC		 242}
243
244static void mlx5_disable_msix(struct mlx5_core_dev *dev)
245{
db058a18 246 struct mlx5_priv *priv = &dev->priv;
e126ba97
EC		 247
248 pci_disable_msix(dev->pdev);
db058a18
SM		 249 kfree(priv->irq_info);
250 kfree(priv->msix_arr);
e126ba97
EC		 251}
252
253struct mlx5_reg_host_endianess {
254 u8 he;
255 u8 rsvd[15];
256};
257
87b8de49
EC		 258
259#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
260
261enum {
c7a08ac7
EC		 262 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
263 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 264};
265
c7a08ac7
EC		 266static u16 to_fw_pkey_sz(u32 size)
267{
268 switch (size) {
269 case 128:
270 return 0;
271 case 256:
272 return 1;
273 case 512:
274 return 2;
275 case 1024:
276 return 3;
277 case 2048:
278 return 4;
279 case 4096:
280 return 5;
281 default:
282 pr_warn("invalid pkey table size %d\n", size);
283 return 0;
284 }
285}
286
938fe83c 287static u16 to_sw_pkey_sz(int pkey_sz)
c7a08ac7 288{
938fe83c 289 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
c7a08ac7 290 return 0;
87b8de49 291
938fe83c 292 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
c7a08ac7
EC		 293}
294
938fe83c
SM		 295int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
296 enum mlx5_cap_mode cap_mode)
c7a08ac7 297{
b775516b
EC		 298 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
299 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
938fe83c
SM		 300 void *out, *hca_caps;
301 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
e126ba97
EC		 302 int err;
303
b775516b
EC		 304 memset(in, 0, sizeof(in));
305 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 306 if (!out)
e126ba97 307 return -ENOMEM;
938fe83c 308
b775516b
EC		 309 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
310 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
311 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
312 if (err)
313 goto query_ex;
e126ba97 314
b775516b 315 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7 316 if (err) {
938fe83c
SM		 317 mlx5_core_warn(dev,
318 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
319 cap_type, cap_mode, err);
e126ba97
EC		 320 goto query_ex;
321 }
c7a08ac7 322
938fe83c
SM		 323 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
324
325 switch (cap_mode) {
326 case HCA_CAP_OPMOD_GET_MAX:
327 memcpy(dev->hca_caps_max[cap_type], hca_caps,
328 MLX5_UN_SZ_BYTES(hca_cap_union));
329 break;
330 case HCA_CAP_OPMOD_GET_CUR:
331 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
332 MLX5_UN_SZ_BYTES(hca_cap_union));
333 break;
334 default:
335 mlx5_core_warn(dev,
336 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
337 cap_type, cap_mode);
338 err = -EINVAL;
339 break;
340 }
c7a08ac7
EC		 341query_ex:
342 kfree(out);
343 return err;
344}
345
b775516b 346static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
c7a08ac7 347{
b775516b 348 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
c7a08ac7
EC		 349 int err;
350
b775516b 351 memset(out, 0, sizeof(out));
e126ba97 352
b775516b
EC		 353 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
354 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
e126ba97 355 if (err)
c7a08ac7 356 return err;
e126ba97 357
b775516b 358 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 359
360 return err;
361}
362
363static int handle_hca_cap(struct mlx5_core_dev *dev)
364{
b775516b 365 void *set_ctx = NULL;
c7a08ac7 366 struct mlx5_profile *prof = dev->profile;
c7a08ac7 367 int err = -ENOMEM;
b775516b 368 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
938fe83c 369 void *set_hca_cap;
c7a08ac7 370
b775516b 371 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 372 if (!set_ctx)
e126ba97 373 goto query_ex;
e126ba97 374
938fe83c 375 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
c7a08ac7 376 if (err)
e126ba97 377 goto query_ex;
e126ba97 378
938fe83c 379 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
e126ba97
EC		 380 if (err)
381 goto query_ex;
382
938fe83c
SM		 383 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
384 capability);
385 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
386 MLX5_ST_SZ_BYTES(cmd_hca_cap));
387
388 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
389 to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
390 128);
c7a08ac7 391 /* we limit the size of the pkey table to 128 entries for now */
938fe83c
SM		 392 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
393 to_fw_pkey_sz(128));
c7a08ac7
EC		 394
395 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
938fe83c
SM		 396 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
397 prof->log_max_qp);
c7a08ac7 398
938fe83c
SM		 399 /* disable cmdif checksum */
400 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
c7a08ac7 401
b775516b 402 err = set_caps(dev, set_ctx, set_sz);
c7a08ac7 403
e126ba97 404query_ex:
e126ba97 405 kfree(set_ctx);
e126ba97
EC		 406 return err;
407}
408
409static int set_hca_ctrl(struct mlx5_core_dev *dev)
410{
411 struct mlx5_reg_host_endianess he_in;
412 struct mlx5_reg_host_endianess he_out;
413 int err;
414
415 memset(&he_in, 0, sizeof(he_in));
416 he_in.he = MLX5_SET_HOST_ENDIANNESS;
417 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
418 &he_out, sizeof(he_out),
419 MLX5_REG_HOST_ENDIANNESS, 0, 1);
420 return err;
421}
422
cd23b14b
EC		 423static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
424{
425 int err;
426 struct mlx5_enable_hca_mbox_in in;
427 struct mlx5_enable_hca_mbox_out out;
428
429 memset(&in, 0, sizeof(in));
430 memset(&out, 0, sizeof(out));
431 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
432 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
433 if (err)
434 return err;
435
436 if (out.hdr.status)
437 return mlx5_cmd_status_to_err(&out.hdr);
438
439 return 0;
440}
441
442static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
443{
444 int err;
445 struct mlx5_disable_hca_mbox_in in;
446 struct mlx5_disable_hca_mbox_out out;
447
448 memset(&in, 0, sizeof(in));
449 memset(&out, 0, sizeof(out));
450 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
451 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
452 if (err)
453 return err;
454
455 if (out.hdr.status)
456 return mlx5_cmd_status_to_err(&out.hdr);
457
458 return 0;
459}
460
db058a18
SM		 461static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
462{
463 struct mlx5_priv *priv = &mdev->priv;
464 struct msix_entry *msix = priv->msix_arr;
465 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
466 int numa_node = dev_to_node(&mdev->pdev->dev);
467 int err;
468
469 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
470 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
471 return -ENOMEM;
472 }
473
dda922c8
DM		 474 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
475 priv->irq_info[i].mask);
db058a18
SM		 476
477 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
478 if (err) {
479 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
480 irq);
481 goto err_clear_mask;
482 }
483
484 return 0;
485
486err_clear_mask:
487 free_cpumask_var(priv->irq_info[i].mask);
488 return err;
489}
490
491static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
492{
493 struct mlx5_priv *priv = &mdev->priv;
494 struct msix_entry *msix = priv->msix_arr;
495 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
496
497 irq_set_affinity_hint(irq, NULL);
498 free_cpumask_var(priv->irq_info[i].mask);
499}
500
501static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
502{
503 int err;
504 int i;
505
506 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
507 err = mlx5_irq_set_affinity_hint(mdev, i);
508 if (err)
509 goto err_out;
510 }
511
512 return 0;
513
514err_out:
515 for (i--; i >= 0; i--)
516 mlx5_irq_clear_affinity_hint(mdev, i);
517
518 return err;
519}
520
521static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
522{
523 int i;
524
525 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
526 mlx5_irq_clear_affinity_hint(mdev, i);
527}
528
233d05d2
SM		 529int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
530{
531 struct mlx5_eq_table *table = &dev->priv.eq_table;
532 struct mlx5_eq *eq, *n;
533 int err = -ENOENT;
534
535 spin_lock(&table->lock);
536 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
537 if (eq->index == vector) {
538 *eqn = eq->eqn;
539 *irqn = eq->irqn;
540 err = 0;
541 break;
542 }
543 }
544 spin_unlock(&table->lock);
545
546 return err;
547}
548EXPORT_SYMBOL(mlx5_vector2eqn);
549
550static void free_comp_eqs(struct mlx5_core_dev *dev)
551{
552 struct mlx5_eq_table *table = &dev->priv.eq_table;
553 struct mlx5_eq *eq, *n;
554
555 spin_lock(&table->lock);
556 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
557 list_del(&eq->list);
558 spin_unlock(&table->lock);
559 if (mlx5_destroy_unmap_eq(dev, eq))
560 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
561 eq->eqn);
562 kfree(eq);
563 spin_lock(&table->lock);
564 }
565 spin_unlock(&table->lock);
566}
567
568static int alloc_comp_eqs(struct mlx5_core_dev *dev)
569{
570 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 571 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 572 struct mlx5_eq *eq;
573 int ncomp_vec;
574 int nent;
575 int err;
576 int i;
577
578 INIT_LIST_HEAD(&table->comp_eqs_list);
579 ncomp_vec = table->num_comp_vectors;
580 nent = MLX5_COMP_EQ_SIZE;
581 for (i = 0; i < ncomp_vec; i++) {
582 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
583 if (!eq) {
584 err = -ENOMEM;
585 goto clean;
586 }
587
db058a18 588 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 589 err = mlx5_create_map_eq(dev, eq,
590 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
591 name, &dev->priv.uuari.uars[0]);
592 if (err) {
593 kfree(eq);
594 goto clean;
595 }
596 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
597 eq->index = i;
598 spin_lock(&table->lock);
599 list_add_tail(&eq->list, &table->comp_eqs_list);
600 spin_unlock(&table->lock);
601 }
602
603 return 0;
604
605clean:
606 free_comp_eqs(dev);
607 return err;
608}
609
f62b8bb8
AV		 610#ifdef CONFIG_MLX5_CORE_EN
611static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
612{
613 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
614 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
615 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
616 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
617 int err;
618 u32 sup_issi;
619
620 memset(query_in, 0, sizeof(query_in));
621 memset(query_out, 0, sizeof(query_out));
622
623 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
624
625 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
626 query_out, sizeof(query_out));
627 if (err) {
628 if (((struct mlx5_outbox_hdr *)query_out)->status ==
629 MLX5_CMD_STAT_BAD_OP_ERR) {
630 pr_debug("Only ISSI 0 is supported\n");
631 return 0;
632 }
633
634 pr_err("failed to query ISSI\n");
635 return err;
636 }
637
638 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
639
640 if (sup_issi & (1 << 1)) {
641 memset(set_in, 0, sizeof(set_in));
642 memset(set_out, 0, sizeof(set_out));
643
644 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
645 MLX5_SET(set_issi_in, set_in, current_issi, 1);
646
647 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
648 set_out, sizeof(set_out));
649 if (err) {
650 pr_err("failed to set ISSI=1\n");
651 return err;
652 }
653
654 dev->issi = 1;
655
656 return 0;
657 } else if (sup_issi & (1 << 0)) {
658 return 0;
659 }
660
661 return -ENOTSUPP;
662}
663#endif
664
9603b61d 665static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
e126ba97
EC		 666{
667 struct mlx5_priv *priv = &dev->priv;
668 int err;
669
670 dev->pdev = pdev;
671 pci_set_drvdata(dev->pdev, dev);
672 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
673 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
674
675 mutex_init(&priv->pgdir_mutex);
676 INIT_LIST_HEAD(&priv->pgdir_list);
677 spin_lock_init(&priv->mkey_lock);
678
679 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
680 if (!priv->dbg_root)
681 return -ENOMEM;
682
683 err = pci_enable_device(pdev);
684 if (err) {
1a91de28 685 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 686 goto err_dbg;
687 }
688
689 err = request_bar(pdev);
690 if (err) {
1a91de28 691 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 692 goto err_disable;
693 }
694
695 pci_set_master(pdev);
696
697 err = set_dma_caps(pdev);
698 if (err) {
699 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
700 goto err_clr_master;
701 }
702
703 dev->iseg_base = pci_resource_start(dev->pdev, 0);
704 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
705 if (!dev->iseg) {
706 err = -ENOMEM;
707 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
708 goto err_clr_master;
709 }
710 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
711 fw_rev_min(dev), fw_rev_sub(dev));
712
713 err = mlx5_cmd_init(dev);
714 if (err) {
715 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
716 goto err_unmap;
717 }
718
719 mlx5_pagealloc_init(dev);
cd23b14b
EC		 720
721 err = mlx5_core_enable_hca(dev);
722 if (err) {
723 dev_err(&pdev->dev, "enable hca failed\n");
724 goto err_pagealloc_cleanup;
725 }
726
f62b8bb8
AV		 727#ifdef CONFIG_MLX5_CORE_EN
728 err = mlx5_core_set_issi(dev);
729 if (err) {
730 dev_err(&pdev->dev, "failed to set issi\n");
731 goto err_disable_hca;
732 }
733#endif
734
cd23b14b
EC		 735 err = mlx5_satisfy_startup_pages(dev, 1);
736 if (err) {
737 dev_err(&pdev->dev, "failed to allocate boot pages\n");
738 goto err_disable_hca;
739 }
740
e126ba97
EC		 741 err = set_hca_ctrl(dev);
742 if (err) {
743 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 744 goto reclaim_boot_pages;
e126ba97
EC		 745 }
746
747 err = handle_hca_cap(dev);
748 if (err) {
749 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 750 goto reclaim_boot_pages;
e126ba97
EC		 751 }
752
cd23b14b 753 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 754 if (err) {
cd23b14b
EC		 755 dev_err(&pdev->dev, "failed to allocate init pages\n");
756 goto reclaim_boot_pages;
e126ba97
EC		 757 }
758
759 err = mlx5_pagealloc_start(dev);
760 if (err) {
761 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 762 goto reclaim_boot_pages;
e126ba97
EC		 763 }
764
765 err = mlx5_cmd_init_hca(dev);
766 if (err) {
767 dev_err(&pdev->dev, "init hca failed\n");
768 goto err_pagealloc_stop;
769 }
770
771 mlx5_start_health_poll(dev);
772
938fe83c 773 err = mlx5_query_hca_caps(dev);
e126ba97
EC		 774 if (err) {
775 dev_err(&pdev->dev, "query hca failed\n");
776 goto err_stop_poll;
777 }
778
779 err = mlx5_cmd_query_adapter(dev);
780 if (err) {
781 dev_err(&pdev->dev, "query adapter failed\n");
782 goto err_stop_poll;
783 }
784
785 err = mlx5_enable_msix(dev);
786 if (err) {
787 dev_err(&pdev->dev, "enable msix failed\n");
788 goto err_stop_poll;
789 }
790
791 err = mlx5_eq_init(dev);
792 if (err) {
793 dev_err(&pdev->dev, "failed to initialize eq\n");
794 goto disable_msix;
795 }
796
797 err = mlx5_alloc_uuars(dev, &priv->uuari);
798 if (err) {
799 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
800 goto err_eq_cleanup;
801 }
802
803 err = mlx5_start_eqs(dev);
804 if (err) {
805 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
806 goto err_free_uar;
807 }
808
233d05d2
SM		 809 err = alloc_comp_eqs(dev);
810 if (err) {
811 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
812 goto err_stop_eqs;
813 }
814
db058a18
SM		 815 err = mlx5_irq_set_affinity_hints(dev);
816 if (err) {
817 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
818 goto err_free_comp_eqs;
819 }
820
e126ba97
EC		 821 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
822
823 mlx5_init_cq_table(dev);
824 mlx5_init_qp_table(dev);
825 mlx5_init_srq_table(dev);
3bcdb17a 826 mlx5_init_mr_table(dev);
e126ba97
EC		 827
828 return 0;
829
db058a18
SM		 830err_free_comp_eqs:
831 free_comp_eqs(dev);
832
233d05d2
SM		 833err_stop_eqs:
834 mlx5_stop_eqs(dev);
835
e126ba97
EC		 836err_free_uar:
837 mlx5_free_uuars(dev, &priv->uuari);
838
839err_eq_cleanup:
840 mlx5_eq_cleanup(dev);
841
842disable_msix:
843 mlx5_disable_msix(dev);
844
845err_stop_poll:
846 mlx5_stop_health_poll(dev);
1bde6e30
EC		 847 if (mlx5_cmd_teardown_hca(dev)) {
848 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
849 return err;
850 }
e126ba97
EC		 851
852err_pagealloc_stop:
853 mlx5_pagealloc_stop(dev);
854
cd23b14b 855reclaim_boot_pages:
e126ba97
EC		 856 mlx5_reclaim_startup_pages(dev);
857
cd23b14b
EC		 858err_disable_hca:
859 mlx5_core_disable_hca(dev);
860
e126ba97
EC		 861err_pagealloc_cleanup:
862 mlx5_pagealloc_cleanup(dev);
863 mlx5_cmd_cleanup(dev);
864
865err_unmap:
866 iounmap(dev->iseg);
867
868err_clr_master:
869 pci_clear_master(dev->pdev);
870 release_bar(dev->pdev);
871
872err_disable:
873 pci_disable_device(dev->pdev);
874
875err_dbg:
876 debugfs_remove(priv->dbg_root);
877 return err;
878}
e126ba97 879
9603b61d 880static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
e126ba97
EC		 881{
882 struct mlx5_priv *priv = &dev->priv;
883
884 mlx5_cleanup_srq_table(dev);
885 mlx5_cleanup_qp_table(dev);
886 mlx5_cleanup_cq_table(dev);
db058a18 887 mlx5_irq_clear_affinity_hints(dev);
233d05d2 888 free_comp_eqs(dev);
e126ba97
EC		 889 mlx5_stop_eqs(dev);
890 mlx5_free_uuars(dev, &priv->uuari);
891 mlx5_eq_cleanup(dev);
892 mlx5_disable_msix(dev);
893 mlx5_stop_health_poll(dev);
1bde6e30
EC		 894 if (mlx5_cmd_teardown_hca(dev)) {
895 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
896 return;
897 }
e126ba97
EC		 898 mlx5_pagealloc_stop(dev);
899 mlx5_reclaim_startup_pages(dev);
cd23b14b 900 mlx5_core_disable_hca(dev);
e126ba97
EC		 901 mlx5_pagealloc_cleanup(dev);
902 mlx5_cmd_cleanup(dev);
903 iounmap(dev->iseg);
904 pci_clear_master(dev->pdev);
905 release_bar(dev->pdev);
906 pci_disable_device(dev->pdev);
907 debugfs_remove(priv->dbg_root);
908}
9603b61d
JM		 909
910static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
911{
912 struct mlx5_device_context *dev_ctx;
913 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
914
915 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
916 if (!dev_ctx) {
917 pr_warn("mlx5_add_device: alloc context failed\n");
918 return;
919 }
920
921 dev_ctx->intf = intf;
922 dev_ctx->context = intf->add(dev);
923
924 if (dev_ctx->context) {
925 spin_lock_irq(&priv->ctx_lock);
926 list_add_tail(&dev_ctx->list, &priv->ctx_list);
927 spin_unlock_irq(&priv->ctx_lock);
928 } else {
929 kfree(dev_ctx);
930 }
931}
932
933static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
934{
935 struct mlx5_device_context *dev_ctx;
936 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
937
938 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
939 if (dev_ctx->intf == intf) {
940 spin_lock_irq(&priv->ctx_lock);
941 list_del(&dev_ctx->list);
942 spin_unlock_irq(&priv->ctx_lock);
943
944 intf->remove(dev, dev_ctx->context);
945 kfree(dev_ctx);
946 return;
947 }
948}
949static int mlx5_register_device(struct mlx5_core_dev *dev)
950{
951 struct mlx5_priv *priv = &dev->priv;
952 struct mlx5_interface *intf;
953
954 mutex_lock(&intf_mutex);
955 list_add_tail(&priv->dev_list, &dev_list);
956 list_for_each_entry(intf, &intf_list, list)
957 mlx5_add_device(intf, priv);
958 mutex_unlock(&intf_mutex);
959
960 return 0;
961}
962static void mlx5_unregister_device(struct mlx5_core_dev *dev)
963{
964 struct mlx5_priv *priv = &dev->priv;
965 struct mlx5_interface *intf;
966
967 mutex_lock(&intf_mutex);
968 list_for_each_entry(intf, &intf_list, list)
969 mlx5_remove_device(intf, priv);
970 list_del(&priv->dev_list);
971 mutex_unlock(&intf_mutex);
972}
973
974int mlx5_register_interface(struct mlx5_interface *intf)
975{
976 struct mlx5_priv *priv;
977
978 if (!intf->add || !intf->remove)
979 return -EINVAL;
980
981 mutex_lock(&intf_mutex);
982 list_add_tail(&intf->list, &intf_list);
983 list_for_each_entry(priv, &dev_list, dev_list)
984 mlx5_add_device(intf, priv);
985 mutex_unlock(&intf_mutex);
986
987 return 0;
988}
989EXPORT_SYMBOL(mlx5_register_interface);
990
991void mlx5_unregister_interface(struct mlx5_interface *intf)
992{
993 struct mlx5_priv *priv;
994
995 mutex_lock(&intf_mutex);
996 list_for_each_entry(priv, &dev_list, dev_list)
997 mlx5_remove_device(intf, priv);
998 list_del(&intf->list);
999 mutex_unlock(&intf_mutex);
1000}
1001EXPORT_SYMBOL(mlx5_unregister_interface);
1002
64613d94
SM		 1003void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
1004{
1005 struct mlx5_priv *priv = &mdev->priv;
1006 struct mlx5_device_context *dev_ctx;
1007 unsigned long flags;
1008 void *result = NULL;
1009
1010 spin_lock_irqsave(&priv->ctx_lock, flags);
1011
1012 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
1013 if ((dev_ctx->intf->protocol == protocol) &&
1014 dev_ctx->intf->get_dev) {
1015 result = dev_ctx->intf->get_dev(dev_ctx->context);
1016 break;
1017 }
1018
1019 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1020
1021 return result;
1022}
1023EXPORT_SYMBOL(mlx5_get_protocol_dev);
1024
9603b61d 1025static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
4d2f9bbb 1026 unsigned long param)
9603b61d
JM		 1027{
1028 struct mlx5_priv *priv = &dev->priv;
1029 struct mlx5_device_context *dev_ctx;
1030 unsigned long flags;
1031
1032 spin_lock_irqsave(&priv->ctx_lock, flags);
1033
1034 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1035 if (dev_ctx->intf->event)
4d2f9bbb 1036 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
9603b61d
JM		 1037
1038 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1039}
1040
1041struct mlx5_core_event_handler {
1042 void (*event)(struct mlx5_core_dev *dev,
1043 enum mlx5_dev_event event,
1044 void *data);
1045};
1046
f66f049f
EC		 1047#define MLX5_IB_MOD "mlx5_ib"
1048
9603b61d
JM		 1049static int init_one(struct pci_dev *pdev,
1050 const struct pci_device_id *id)
1051{
1052 struct mlx5_core_dev *dev;
1053 struct mlx5_priv *priv;
1054 int err;
1055
1056 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1057 if (!dev) {
1058 dev_err(&pdev->dev, "kzalloc failed\n");
1059 return -ENOMEM;
1060 }
1061 priv = &dev->priv;
1062
1063 pci_set_drvdata(pdev, dev);
1064
1065 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1066 pr_warn("selected profile out of range, selecting default (%d)\n",
1067 MLX5_DEFAULT_PROF);
1068 prof_sel = MLX5_DEFAULT_PROF;
1069 }
1070 dev->profile = &profile[prof_sel];
1071 dev->event = mlx5_core_event;
1072
364d1798
EC		 1073 INIT_LIST_HEAD(&priv->ctx_list);
1074 spin_lock_init(&priv->ctx_lock);
9603b61d
JM		 1075 err = mlx5_dev_init(dev, pdev);
1076 if (err) {
1077 dev_err(&pdev->dev, "mlx5_dev_init failed %d\n", err);
1078 goto out;
1079 }
1080
9603b61d
JM		 1081 err = mlx5_register_device(dev);
1082 if (err) {
1083 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1084 goto out_init;
1085 }
1086
f66f049f
EC		 1087 err = request_module_nowait(MLX5_IB_MOD);
1088 if (err)
1089 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1090
9603b61d
JM		 1091 return 0;
1092
1093out_init:
1094 mlx5_dev_cleanup(dev);
1095out:
1096 kfree(dev);
1097 return err;
1098}
1099static void remove_one(struct pci_dev *pdev)
1100{
1101 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1102
1103 mlx5_unregister_device(dev);
1104 mlx5_dev_cleanup(dev);
1105 kfree(dev);
1106}
1107
1108static const struct pci_device_id mlx5_core_pci_table[] = {
1c755cc5
OG		 1109 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1110 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1111 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1112 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1113 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1114 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
9603b61d
JM		 1115 { 0, }
1116};
1117
1118MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1119
1120static struct pci_driver mlx5_core_driver = {
1121 .name = DRIVER_NAME,
1122 .id_table = mlx5_core_pci_table,
1123 .probe = init_one,
1124 .remove = remove_one
1125};
e126ba97
EC		 1126
1127static int __init init(void)
1128{
1129 int err;
1130
1131 mlx5_register_debugfs();
1132 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
1133 if (!mlx5_core_wq) {
1134 err = -ENOMEM;
1135 goto err_debug;
1136 }
1137 mlx5_health_init();
1138
9603b61d
JM		 1139 err = pci_register_driver(&mlx5_core_driver);
1140 if (err)
1141 goto err_health;
1142
f62b8bb8
AV		 1143#ifdef CONFIG_MLX5_CORE_EN
1144 mlx5e_init();
1145#endif
1146
e126ba97
EC		 1147 return 0;
1148
9603b61d
JM		 1149err_health:
1150 mlx5_health_cleanup();
1151 destroy_workqueue(mlx5_core_wq);
e126ba97
EC		 1152err_debug:
1153 mlx5_unregister_debugfs();
1154 return err;
1155}
1156
1157static void __exit cleanup(void)
1158{
f62b8bb8
AV		 1159#ifdef CONFIG_MLX5_CORE_EN
1160 mlx5e_cleanup();
1161#endif
9603b61d 1162 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1163 mlx5_health_cleanup();
1164 destroy_workqueue(mlx5_core_wq);
1165 mlx5_unregister_debugfs();
1166}
1167
1168module_init(init);
1169module_exit(cleanup);
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