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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
adec640e | 33 | #include <linux/highmem.h> |
e126ba97 EC |
34 | #include <linux/module.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/io-mapping.h> | |
db058a18 | 41 | #include <linux/interrupt.h> |
e3297246 | 42 | #include <linux/delay.h> |
e126ba97 EC |
43 | #include <linux/mlx5/driver.h> |
44 | #include <linux/mlx5/cq.h> | |
45 | #include <linux/mlx5/qp.h> | |
46 | #include <linux/mlx5/srq.h> | |
47 | #include <linux/debugfs.h> | |
f66f049f | 48 | #include <linux/kmod.h> |
89d44f0a | 49 | #include <linux/delay.h> |
b775516b | 50 | #include <linux/mlx5/mlx5_ifc.h> |
5a7b27eb MG |
51 | #ifdef CONFIG_RFS_ACCEL |
52 | #include <linux/cpu_rmap.h> | |
53 | #endif | |
feae9087 | 54 | #include <net/devlink.h> |
e126ba97 | 55 | #include "mlx5_core.h" |
86d722ad | 56 | #include "fs_core.h" |
073bb189 SM |
57 | #ifdef CONFIG_MLX5_CORE_EN |
58 | #include "eswitch.h" | |
59 | #endif | |
e126ba97 | 60 | |
e126ba97 | 61 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); |
4ae6c18c | 62 | MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); |
e126ba97 EC |
63 | MODULE_LICENSE("Dual BSD/GPL"); |
64 | MODULE_VERSION(DRIVER_VERSION); | |
65 | ||
66 | int mlx5_core_debug_mask; | |
67 | module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644); | |
68 | MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); | |
69 | ||
9603b61d JM |
70 | #define MLX5_DEFAULT_PROF 2 |
71 | static int prof_sel = MLX5_DEFAULT_PROF; | |
72 | module_param_named(prof_sel, prof_sel, int, 0444); | |
73 | MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); | |
74 | ||
9603b61d JM |
75 | static LIST_HEAD(intf_list); |
76 | static LIST_HEAD(dev_list); | |
77 | static DEFINE_MUTEX(intf_mutex); | |
78 | ||
79 | struct mlx5_device_context { | |
80 | struct list_head list; | |
81 | struct mlx5_interface *intf; | |
82 | void *context; | |
83 | }; | |
84 | ||
f91e6d89 EBE |
85 | enum { |
86 | MLX5_ATOMIC_REQ_MODE_BE = 0x0, | |
87 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, | |
88 | }; | |
89 | ||
9603b61d JM |
90 | static struct mlx5_profile profile[] = { |
91 | [0] = { | |
92 | .mask = 0, | |
93 | }, | |
94 | [1] = { | |
95 | .mask = MLX5_PROF_MASK_QP_SIZE, | |
96 | .log_max_qp = 12, | |
97 | }, | |
98 | [2] = { | |
99 | .mask = MLX5_PROF_MASK_QP_SIZE | | |
100 | MLX5_PROF_MASK_MR_CACHE, | |
101 | .log_max_qp = 17, | |
102 | .mr_cache[0] = { | |
103 | .size = 500, | |
104 | .limit = 250 | |
105 | }, | |
106 | .mr_cache[1] = { | |
107 | .size = 500, | |
108 | .limit = 250 | |
109 | }, | |
110 | .mr_cache[2] = { | |
111 | .size = 500, | |
112 | .limit = 250 | |
113 | }, | |
114 | .mr_cache[3] = { | |
115 | .size = 500, | |
116 | .limit = 250 | |
117 | }, | |
118 | .mr_cache[4] = { | |
119 | .size = 500, | |
120 | .limit = 250 | |
121 | }, | |
122 | .mr_cache[5] = { | |
123 | .size = 500, | |
124 | .limit = 250 | |
125 | }, | |
126 | .mr_cache[6] = { | |
127 | .size = 500, | |
128 | .limit = 250 | |
129 | }, | |
130 | .mr_cache[7] = { | |
131 | .size = 500, | |
132 | .limit = 250 | |
133 | }, | |
134 | .mr_cache[8] = { | |
135 | .size = 500, | |
136 | .limit = 250 | |
137 | }, | |
138 | .mr_cache[9] = { | |
139 | .size = 500, | |
140 | .limit = 250 | |
141 | }, | |
142 | .mr_cache[10] = { | |
143 | .size = 500, | |
144 | .limit = 250 | |
145 | }, | |
146 | .mr_cache[11] = { | |
147 | .size = 500, | |
148 | .limit = 250 | |
149 | }, | |
150 | .mr_cache[12] = { | |
151 | .size = 64, | |
152 | .limit = 32 | |
153 | }, | |
154 | .mr_cache[13] = { | |
155 | .size = 32, | |
156 | .limit = 16 | |
157 | }, | |
158 | .mr_cache[14] = { | |
159 | .size = 16, | |
160 | .limit = 8 | |
161 | }, | |
162 | .mr_cache[15] = { | |
163 | .size = 8, | |
164 | .limit = 4 | |
165 | }, | |
166 | }, | |
167 | }; | |
e126ba97 | 168 | |
e3297246 EC |
169 | #define FW_INIT_TIMEOUT_MILI 2000 |
170 | #define FW_INIT_WAIT_MS 2 | |
171 | ||
172 | static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) | |
173 | { | |
174 | unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); | |
175 | int err = 0; | |
176 | ||
177 | while (fw_initializing(dev)) { | |
178 | if (time_after(jiffies, end)) { | |
179 | err = -EBUSY; | |
180 | break; | |
181 | } | |
182 | msleep(FW_INIT_WAIT_MS); | |
183 | } | |
184 | ||
185 | return err; | |
186 | } | |
187 | ||
e126ba97 EC |
188 | static int set_dma_caps(struct pci_dev *pdev) |
189 | { | |
190 | int err; | |
191 | ||
192 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
193 | if (err) { | |
1a91de28 | 194 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); |
e126ba97 EC |
195 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
196 | if (err) { | |
1a91de28 | 197 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); |
e126ba97 EC |
198 | return err; |
199 | } | |
200 | } | |
201 | ||
202 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
203 | if (err) { | |
204 | dev_warn(&pdev->dev, | |
1a91de28 | 205 | "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); |
e126ba97 EC |
206 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
207 | if (err) { | |
208 | dev_err(&pdev->dev, | |
1a91de28 | 209 | "Can't set consistent PCI DMA mask, aborting\n"); |
e126ba97 EC |
210 | return err; |
211 | } | |
212 | } | |
213 | ||
214 | dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); | |
215 | return err; | |
216 | } | |
217 | ||
89d44f0a MD |
218 | static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) |
219 | { | |
220 | struct pci_dev *pdev = dev->pdev; | |
221 | int err = 0; | |
222 | ||
223 | mutex_lock(&dev->pci_status_mutex); | |
224 | if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { | |
225 | err = pci_enable_device(pdev); | |
226 | if (!err) | |
227 | dev->pci_status = MLX5_PCI_STATUS_ENABLED; | |
228 | } | |
229 | mutex_unlock(&dev->pci_status_mutex); | |
230 | ||
231 | return err; | |
232 | } | |
233 | ||
234 | static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) | |
235 | { | |
236 | struct pci_dev *pdev = dev->pdev; | |
237 | ||
238 | mutex_lock(&dev->pci_status_mutex); | |
239 | if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { | |
240 | pci_disable_device(pdev); | |
241 | dev->pci_status = MLX5_PCI_STATUS_DISABLED; | |
242 | } | |
243 | mutex_unlock(&dev->pci_status_mutex); | |
244 | } | |
245 | ||
e126ba97 EC |
246 | static int request_bar(struct pci_dev *pdev) |
247 | { | |
248 | int err = 0; | |
249 | ||
250 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
1a91de28 | 251 | dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); |
e126ba97 EC |
252 | return -ENODEV; |
253 | } | |
254 | ||
255 | err = pci_request_regions(pdev, DRIVER_NAME); | |
256 | if (err) | |
257 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); | |
258 | ||
259 | return err; | |
260 | } | |
261 | ||
262 | static void release_bar(struct pci_dev *pdev) | |
263 | { | |
264 | pci_release_regions(pdev); | |
265 | } | |
266 | ||
267 | static int mlx5_enable_msix(struct mlx5_core_dev *dev) | |
268 | { | |
db058a18 SM |
269 | struct mlx5_priv *priv = &dev->priv; |
270 | struct mlx5_eq_table *table = &priv->eq_table; | |
938fe83c | 271 | int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); |
e126ba97 | 272 | int nvec; |
e126ba97 EC |
273 | int i; |
274 | ||
938fe83c SM |
275 | nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() + |
276 | MLX5_EQ_VEC_COMP_BASE; | |
e126ba97 EC |
277 | nvec = min_t(int, nvec, num_eqs); |
278 | if (nvec <= MLX5_EQ_VEC_COMP_BASE) | |
279 | return -ENOMEM; | |
280 | ||
db058a18 SM |
281 | priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL); |
282 | ||
283 | priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL); | |
284 | if (!priv->msix_arr || !priv->irq_info) | |
285 | goto err_free_msix; | |
e126ba97 EC |
286 | |
287 | for (i = 0; i < nvec; i++) | |
db058a18 | 288 | priv->msix_arr[i].entry = i; |
e126ba97 | 289 | |
db058a18 | 290 | nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, |
3a9e161a | 291 | MLX5_EQ_VEC_COMP_BASE + 1, nvec); |
f3c9407b AG |
292 | if (nvec < 0) |
293 | return nvec; | |
e126ba97 | 294 | |
f3c9407b | 295 | table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; |
e126ba97 EC |
296 | |
297 | return 0; | |
db058a18 SM |
298 | |
299 | err_free_msix: | |
300 | kfree(priv->irq_info); | |
301 | kfree(priv->msix_arr); | |
302 | return -ENOMEM; | |
e126ba97 EC |
303 | } |
304 | ||
305 | static void mlx5_disable_msix(struct mlx5_core_dev *dev) | |
306 | { | |
db058a18 | 307 | struct mlx5_priv *priv = &dev->priv; |
e126ba97 EC |
308 | |
309 | pci_disable_msix(dev->pdev); | |
db058a18 SM |
310 | kfree(priv->irq_info); |
311 | kfree(priv->msix_arr); | |
e126ba97 EC |
312 | } |
313 | ||
314 | struct mlx5_reg_host_endianess { | |
315 | u8 he; | |
316 | u8 rsvd[15]; | |
317 | }; | |
318 | ||
87b8de49 EC |
319 | |
320 | #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) | |
321 | ||
322 | enum { | |
c7a08ac7 EC |
323 | MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | |
324 | MLX5_DEV_CAP_FLAG_DCT, | |
87b8de49 EC |
325 | }; |
326 | ||
c7a08ac7 EC |
327 | static u16 to_fw_pkey_sz(u32 size) |
328 | { | |
329 | switch (size) { | |
330 | case 128: | |
331 | return 0; | |
332 | case 256: | |
333 | return 1; | |
334 | case 512: | |
335 | return 2; | |
336 | case 1024: | |
337 | return 3; | |
338 | case 2048: | |
339 | return 4; | |
340 | case 4096: | |
341 | return 5; | |
342 | default: | |
343 | pr_warn("invalid pkey table size %d\n", size); | |
344 | return 0; | |
345 | } | |
346 | } | |
347 | ||
b06e7de8 LR |
348 | static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, |
349 | enum mlx5_cap_type cap_type, | |
350 | enum mlx5_cap_mode cap_mode) | |
c7a08ac7 | 351 | { |
b775516b EC |
352 | u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; |
353 | int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); | |
938fe83c SM |
354 | void *out, *hca_caps; |
355 | u16 opmod = (cap_type << 1) | (cap_mode & 0x01); | |
e126ba97 EC |
356 | int err; |
357 | ||
b775516b EC |
358 | memset(in, 0, sizeof(in)); |
359 | out = kzalloc(out_sz, GFP_KERNEL); | |
c7a08ac7 | 360 | if (!out) |
e126ba97 | 361 | return -ENOMEM; |
938fe83c | 362 | |
b775516b EC |
363 | MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); |
364 | MLX5_SET(query_hca_cap_in, in, op_mod, opmod); | |
365 | err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); | |
366 | if (err) | |
367 | goto query_ex; | |
e126ba97 | 368 | |
b775516b | 369 | err = mlx5_cmd_status_to_err_v2(out); |
c7a08ac7 | 370 | if (err) { |
938fe83c SM |
371 | mlx5_core_warn(dev, |
372 | "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", | |
373 | cap_type, cap_mode, err); | |
e126ba97 EC |
374 | goto query_ex; |
375 | } | |
c7a08ac7 | 376 | |
938fe83c SM |
377 | hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); |
378 | ||
379 | switch (cap_mode) { | |
380 | case HCA_CAP_OPMOD_GET_MAX: | |
381 | memcpy(dev->hca_caps_max[cap_type], hca_caps, | |
382 | MLX5_UN_SZ_BYTES(hca_cap_union)); | |
383 | break; | |
384 | case HCA_CAP_OPMOD_GET_CUR: | |
385 | memcpy(dev->hca_caps_cur[cap_type], hca_caps, | |
386 | MLX5_UN_SZ_BYTES(hca_cap_union)); | |
387 | break; | |
388 | default: | |
389 | mlx5_core_warn(dev, | |
390 | "Tried to query dev cap type(%x) with wrong opmode(%x)\n", | |
391 | cap_type, cap_mode); | |
392 | err = -EINVAL; | |
393 | break; | |
394 | } | |
c7a08ac7 EC |
395 | query_ex: |
396 | kfree(out); | |
397 | return err; | |
398 | } | |
399 | ||
b06e7de8 LR |
400 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) |
401 | { | |
402 | int ret; | |
403 | ||
404 | ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); | |
405 | if (ret) | |
406 | return ret; | |
407 | return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); | |
408 | } | |
409 | ||
f91e6d89 | 410 | static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) |
c7a08ac7 | 411 | { |
b775516b | 412 | u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)]; |
c7a08ac7 EC |
413 | int err; |
414 | ||
b775516b | 415 | memset(out, 0, sizeof(out)); |
e126ba97 | 416 | |
b775516b | 417 | MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); |
f91e6d89 | 418 | MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); |
b775516b | 419 | err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); |
e126ba97 | 420 | if (err) |
c7a08ac7 | 421 | return err; |
e126ba97 | 422 | |
b775516b | 423 | err = mlx5_cmd_status_to_err_v2(out); |
c7a08ac7 EC |
424 | |
425 | return err; | |
426 | } | |
427 | ||
f91e6d89 EBE |
428 | static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) |
429 | { | |
430 | void *set_ctx; | |
431 | void *set_hca_cap; | |
432 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); | |
433 | int req_endianness; | |
434 | int err; | |
435 | ||
436 | if (MLX5_CAP_GEN(dev, atomic)) { | |
b06e7de8 | 437 | err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); |
f91e6d89 EBE |
438 | if (err) |
439 | return err; | |
440 | } else { | |
441 | return 0; | |
442 | } | |
443 | ||
444 | req_endianness = | |
445 | MLX5_CAP_ATOMIC(dev, | |
446 | supported_atomic_req_8B_endianess_mode_1); | |
447 | ||
448 | if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) | |
449 | return 0; | |
450 | ||
451 | set_ctx = kzalloc(set_sz, GFP_KERNEL); | |
452 | if (!set_ctx) | |
453 | return -ENOMEM; | |
454 | ||
455 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); | |
456 | ||
457 | /* Set requestor to host endianness */ | |
458 | MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode, | |
459 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); | |
460 | ||
461 | err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); | |
462 | ||
463 | kfree(set_ctx); | |
464 | return err; | |
465 | } | |
466 | ||
c7a08ac7 EC |
467 | static int handle_hca_cap(struct mlx5_core_dev *dev) |
468 | { | |
b775516b | 469 | void *set_ctx = NULL; |
c7a08ac7 | 470 | struct mlx5_profile *prof = dev->profile; |
c7a08ac7 | 471 | int err = -ENOMEM; |
b775516b | 472 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
938fe83c | 473 | void *set_hca_cap; |
c7a08ac7 | 474 | |
b775516b | 475 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
c7a08ac7 | 476 | if (!set_ctx) |
e126ba97 | 477 | goto query_ex; |
e126ba97 | 478 | |
b06e7de8 | 479 | err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); |
e126ba97 EC |
480 | if (err) |
481 | goto query_ex; | |
482 | ||
938fe83c SM |
483 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, |
484 | capability); | |
485 | memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL], | |
486 | MLX5_ST_SZ_BYTES(cmd_hca_cap)); | |
487 | ||
488 | mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", | |
707c4602 | 489 | mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), |
938fe83c | 490 | 128); |
c7a08ac7 | 491 | /* we limit the size of the pkey table to 128 entries for now */ |
938fe83c SM |
492 | MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, |
493 | to_fw_pkey_sz(128)); | |
c7a08ac7 EC |
494 | |
495 | if (prof->mask & MLX5_PROF_MASK_QP_SIZE) | |
938fe83c SM |
496 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, |
497 | prof->log_max_qp); | |
c7a08ac7 | 498 | |
938fe83c SM |
499 | /* disable cmdif checksum */ |
500 | MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); | |
c7a08ac7 | 501 | |
fe1e1876 CS |
502 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); |
503 | ||
f91e6d89 EBE |
504 | err = set_caps(dev, set_ctx, set_sz, |
505 | MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); | |
c7a08ac7 | 506 | |
e126ba97 | 507 | query_ex: |
e126ba97 | 508 | kfree(set_ctx); |
e126ba97 EC |
509 | return err; |
510 | } | |
511 | ||
512 | static int set_hca_ctrl(struct mlx5_core_dev *dev) | |
513 | { | |
514 | struct mlx5_reg_host_endianess he_in; | |
515 | struct mlx5_reg_host_endianess he_out; | |
516 | int err; | |
517 | ||
fc50db98 EC |
518 | if (!mlx5_core_is_pf(dev)) |
519 | return 0; | |
520 | ||
e126ba97 EC |
521 | memset(&he_in, 0, sizeof(he_in)); |
522 | he_in.he = MLX5_SET_HOST_ENDIANNESS; | |
523 | err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), | |
524 | &he_out, sizeof(he_out), | |
525 | MLX5_REG_HOST_ENDIANNESS, 0, 1); | |
526 | return err; | |
527 | } | |
528 | ||
0b107106 | 529 | int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 530 | { |
0b107106 EC |
531 | u32 out[MLX5_ST_SZ_DW(enable_hca_out)]; |
532 | u32 in[MLX5_ST_SZ_DW(enable_hca_in)]; | |
cd23b14b | 533 | int err; |
cd23b14b | 534 | |
0b107106 EC |
535 | memset(in, 0, sizeof(in)); |
536 | MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); | |
537 | MLX5_SET(enable_hca_in, in, function_id, func_id); | |
538 | memset(out, 0, sizeof(out)); | |
539 | ||
cd23b14b EC |
540 | err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); |
541 | if (err) | |
542 | return err; | |
543 | ||
0b107106 | 544 | return mlx5_cmd_status_to_err_v2(out); |
cd23b14b EC |
545 | } |
546 | ||
0b107106 | 547 | int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 548 | { |
0b107106 EC |
549 | u32 out[MLX5_ST_SZ_DW(disable_hca_out)]; |
550 | u32 in[MLX5_ST_SZ_DW(disable_hca_in)]; | |
cd23b14b | 551 | int err; |
cd23b14b | 552 | |
0b107106 EC |
553 | memset(in, 0, sizeof(in)); |
554 | MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); | |
555 | MLX5_SET(disable_hca_in, in, function_id, func_id); | |
556 | memset(out, 0, sizeof(out)); | |
557 | err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); | |
cd23b14b EC |
558 | if (err) |
559 | return err; | |
560 | ||
0b107106 | 561 | return mlx5_cmd_status_to_err_v2(out); |
cd23b14b EC |
562 | } |
563 | ||
b0844444 EBE |
564 | cycle_t mlx5_read_internal_timer(struct mlx5_core_dev *dev) |
565 | { | |
566 | u32 timer_h, timer_h1, timer_l; | |
567 | ||
568 | timer_h = ioread32be(&dev->iseg->internal_timer_h); | |
569 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
570 | timer_h1 = ioread32be(&dev->iseg->internal_timer_h); | |
571 | if (timer_h != timer_h1) /* wrap around */ | |
572 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
573 | ||
574 | return (cycle_t)timer_l | (cycle_t)timer_h1 << 32; | |
575 | } | |
576 | ||
db058a18 SM |
577 | static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i) |
578 | { | |
579 | struct mlx5_priv *priv = &mdev->priv; | |
580 | struct msix_entry *msix = priv->msix_arr; | |
581 | int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector; | |
311c7c71 | 582 | int numa_node = priv->numa_node; |
db058a18 SM |
583 | int err; |
584 | ||
585 | if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) { | |
586 | mlx5_core_warn(mdev, "zalloc_cpumask_var failed"); | |
587 | return -ENOMEM; | |
588 | } | |
589 | ||
dda922c8 DM |
590 | cpumask_set_cpu(cpumask_local_spread(i, numa_node), |
591 | priv->irq_info[i].mask); | |
db058a18 SM |
592 | |
593 | err = irq_set_affinity_hint(irq, priv->irq_info[i].mask); | |
594 | if (err) { | |
595 | mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x", | |
596 | irq); | |
597 | goto err_clear_mask; | |
598 | } | |
599 | ||
600 | return 0; | |
601 | ||
602 | err_clear_mask: | |
603 | free_cpumask_var(priv->irq_info[i].mask); | |
604 | return err; | |
605 | } | |
606 | ||
607 | static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i) | |
608 | { | |
609 | struct mlx5_priv *priv = &mdev->priv; | |
610 | struct msix_entry *msix = priv->msix_arr; | |
611 | int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector; | |
612 | ||
613 | irq_set_affinity_hint(irq, NULL); | |
614 | free_cpumask_var(priv->irq_info[i].mask); | |
615 | } | |
616 | ||
617 | static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev) | |
618 | { | |
619 | int err; | |
620 | int i; | |
621 | ||
622 | for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) { | |
623 | err = mlx5_irq_set_affinity_hint(mdev, i); | |
624 | if (err) | |
625 | goto err_out; | |
626 | } | |
627 | ||
628 | return 0; | |
629 | ||
630 | err_out: | |
631 | for (i--; i >= 0; i--) | |
632 | mlx5_irq_clear_affinity_hint(mdev, i); | |
633 | ||
634 | return err; | |
635 | } | |
636 | ||
637 | static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev) | |
638 | { | |
639 | int i; | |
640 | ||
641 | for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) | |
642 | mlx5_irq_clear_affinity_hint(mdev, i); | |
643 | } | |
644 | ||
0b6e26ce DT |
645 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
646 | unsigned int *irqn) | |
233d05d2 SM |
647 | { |
648 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
649 | struct mlx5_eq *eq, *n; | |
650 | int err = -ENOENT; | |
651 | ||
652 | spin_lock(&table->lock); | |
653 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
654 | if (eq->index == vector) { | |
655 | *eqn = eq->eqn; | |
656 | *irqn = eq->irqn; | |
657 | err = 0; | |
658 | break; | |
659 | } | |
660 | } | |
661 | spin_unlock(&table->lock); | |
662 | ||
663 | return err; | |
664 | } | |
665 | EXPORT_SYMBOL(mlx5_vector2eqn); | |
666 | ||
94c6825e MB |
667 | struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn) |
668 | { | |
669 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
670 | struct mlx5_eq *eq; | |
671 | ||
672 | spin_lock(&table->lock); | |
673 | list_for_each_entry(eq, &table->comp_eqs_list, list) | |
674 | if (eq->eqn == eqn) { | |
675 | spin_unlock(&table->lock); | |
676 | return eq; | |
677 | } | |
678 | ||
679 | spin_unlock(&table->lock); | |
680 | ||
681 | return ERR_PTR(-ENOENT); | |
682 | } | |
683 | ||
233d05d2 SM |
684 | static void free_comp_eqs(struct mlx5_core_dev *dev) |
685 | { | |
686 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
687 | struct mlx5_eq *eq, *n; | |
688 | ||
5a7b27eb MG |
689 | #ifdef CONFIG_RFS_ACCEL |
690 | if (dev->rmap) { | |
691 | free_irq_cpu_rmap(dev->rmap); | |
692 | dev->rmap = NULL; | |
693 | } | |
694 | #endif | |
233d05d2 SM |
695 | spin_lock(&table->lock); |
696 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
697 | list_del(&eq->list); | |
698 | spin_unlock(&table->lock); | |
699 | if (mlx5_destroy_unmap_eq(dev, eq)) | |
700 | mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", | |
701 | eq->eqn); | |
702 | kfree(eq); | |
703 | spin_lock(&table->lock); | |
704 | } | |
705 | spin_unlock(&table->lock); | |
706 | } | |
707 | ||
708 | static int alloc_comp_eqs(struct mlx5_core_dev *dev) | |
709 | { | |
710 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
db058a18 | 711 | char name[MLX5_MAX_IRQ_NAME]; |
233d05d2 SM |
712 | struct mlx5_eq *eq; |
713 | int ncomp_vec; | |
714 | int nent; | |
715 | int err; | |
716 | int i; | |
717 | ||
718 | INIT_LIST_HEAD(&table->comp_eqs_list); | |
719 | ncomp_vec = table->num_comp_vectors; | |
720 | nent = MLX5_COMP_EQ_SIZE; | |
5a7b27eb MG |
721 | #ifdef CONFIG_RFS_ACCEL |
722 | dev->rmap = alloc_irq_cpu_rmap(ncomp_vec); | |
723 | if (!dev->rmap) | |
724 | return -ENOMEM; | |
725 | #endif | |
233d05d2 SM |
726 | for (i = 0; i < ncomp_vec; i++) { |
727 | eq = kzalloc(sizeof(*eq), GFP_KERNEL); | |
728 | if (!eq) { | |
729 | err = -ENOMEM; | |
730 | goto clean; | |
731 | } | |
732 | ||
5a7b27eb MG |
733 | #ifdef CONFIG_RFS_ACCEL |
734 | irq_cpu_rmap_add(dev->rmap, | |
735 | dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector); | |
736 | #endif | |
db058a18 | 737 | snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); |
233d05d2 SM |
738 | err = mlx5_create_map_eq(dev, eq, |
739 | i + MLX5_EQ_VEC_COMP_BASE, nent, 0, | |
740 | name, &dev->priv.uuari.uars[0]); | |
741 | if (err) { | |
742 | kfree(eq); | |
743 | goto clean; | |
744 | } | |
745 | mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); | |
746 | eq->index = i; | |
747 | spin_lock(&table->lock); | |
748 | list_add_tail(&eq->list, &table->comp_eqs_list); | |
749 | spin_unlock(&table->lock); | |
750 | } | |
751 | ||
752 | return 0; | |
753 | ||
754 | clean: | |
755 | free_comp_eqs(dev); | |
756 | return err; | |
757 | } | |
758 | ||
f62b8bb8 AV |
759 | static int mlx5_core_set_issi(struct mlx5_core_dev *dev) |
760 | { | |
761 | u32 query_in[MLX5_ST_SZ_DW(query_issi_in)]; | |
762 | u32 query_out[MLX5_ST_SZ_DW(query_issi_out)]; | |
763 | u32 set_in[MLX5_ST_SZ_DW(set_issi_in)]; | |
764 | u32 set_out[MLX5_ST_SZ_DW(set_issi_out)]; | |
765 | int err; | |
766 | u32 sup_issi; | |
767 | ||
768 | memset(query_in, 0, sizeof(query_in)); | |
769 | memset(query_out, 0, sizeof(query_out)); | |
770 | ||
771 | MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); | |
772 | ||
773 | err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in), | |
774 | query_out, sizeof(query_out)); | |
775 | if (err) { | |
776 | if (((struct mlx5_outbox_hdr *)query_out)->status == | |
777 | MLX5_CMD_STAT_BAD_OP_ERR) { | |
778 | pr_debug("Only ISSI 0 is supported\n"); | |
779 | return 0; | |
780 | } | |
781 | ||
782 | pr_err("failed to query ISSI\n"); | |
783 | return err; | |
784 | } | |
785 | ||
786 | sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); | |
787 | ||
788 | if (sup_issi & (1 << 1)) { | |
789 | memset(set_in, 0, sizeof(set_in)); | |
790 | memset(set_out, 0, sizeof(set_out)); | |
791 | ||
792 | MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); | |
793 | MLX5_SET(set_issi_in, set_in, current_issi, 1); | |
794 | ||
795 | err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in), | |
796 | set_out, sizeof(set_out)); | |
797 | if (err) { | |
798 | pr_err("failed to set ISSI=1\n"); | |
799 | return err; | |
800 | } | |
801 | ||
802 | dev->issi = 1; | |
803 | ||
804 | return 0; | |
e74a1db0 | 805 | } else if (sup_issi & (1 << 0) || !sup_issi) { |
f62b8bb8 AV |
806 | return 0; |
807 | } | |
808 | ||
809 | return -ENOTSUPP; | |
810 | } | |
f62b8bb8 | 811 | |
a31208b1 MD |
812 | static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv) |
813 | { | |
814 | struct mlx5_device_context *dev_ctx; | |
815 | struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); | |
816 | ||
817 | dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL); | |
818 | if (!dev_ctx) | |
819 | return; | |
820 | ||
821 | dev_ctx->intf = intf; | |
822 | dev_ctx->context = intf->add(dev); | |
823 | ||
824 | if (dev_ctx->context) { | |
825 | spin_lock_irq(&priv->ctx_lock); | |
826 | list_add_tail(&dev_ctx->list, &priv->ctx_list); | |
827 | spin_unlock_irq(&priv->ctx_lock); | |
828 | } else { | |
829 | kfree(dev_ctx); | |
830 | } | |
831 | } | |
832 | ||
833 | static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv) | |
834 | { | |
835 | struct mlx5_device_context *dev_ctx; | |
836 | struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); | |
837 | ||
838 | list_for_each_entry(dev_ctx, &priv->ctx_list, list) | |
839 | if (dev_ctx->intf == intf) { | |
840 | spin_lock_irq(&priv->ctx_lock); | |
841 | list_del(&dev_ctx->list); | |
842 | spin_unlock_irq(&priv->ctx_lock); | |
843 | ||
844 | intf->remove(dev, dev_ctx->context); | |
845 | kfree(dev_ctx); | |
846 | return; | |
847 | } | |
848 | } | |
849 | ||
850 | static int mlx5_register_device(struct mlx5_core_dev *dev) | |
e126ba97 EC |
851 | { |
852 | struct mlx5_priv *priv = &dev->priv; | |
a31208b1 MD |
853 | struct mlx5_interface *intf; |
854 | ||
855 | mutex_lock(&intf_mutex); | |
856 | list_add_tail(&priv->dev_list, &dev_list); | |
857 | list_for_each_entry(intf, &intf_list, list) | |
858 | mlx5_add_device(intf, priv); | |
859 | mutex_unlock(&intf_mutex); | |
860 | ||
861 | return 0; | |
862 | } | |
863 | ||
864 | static void mlx5_unregister_device(struct mlx5_core_dev *dev) | |
865 | { | |
866 | struct mlx5_priv *priv = &dev->priv; | |
867 | struct mlx5_interface *intf; | |
868 | ||
869 | mutex_lock(&intf_mutex); | |
870 | list_for_each_entry(intf, &intf_list, list) | |
871 | mlx5_remove_device(intf, priv); | |
872 | list_del(&priv->dev_list); | |
873 | mutex_unlock(&intf_mutex); | |
874 | } | |
875 | ||
876 | int mlx5_register_interface(struct mlx5_interface *intf) | |
877 | { | |
878 | struct mlx5_priv *priv; | |
879 | ||
880 | if (!intf->add || !intf->remove) | |
881 | return -EINVAL; | |
882 | ||
883 | mutex_lock(&intf_mutex); | |
884 | list_add_tail(&intf->list, &intf_list); | |
885 | list_for_each_entry(priv, &dev_list, dev_list) | |
886 | mlx5_add_device(intf, priv); | |
887 | mutex_unlock(&intf_mutex); | |
888 | ||
889 | return 0; | |
890 | } | |
891 | EXPORT_SYMBOL(mlx5_register_interface); | |
892 | ||
893 | void mlx5_unregister_interface(struct mlx5_interface *intf) | |
894 | { | |
895 | struct mlx5_priv *priv; | |
896 | ||
897 | mutex_lock(&intf_mutex); | |
898 | list_for_each_entry(priv, &dev_list, dev_list) | |
899 | mlx5_remove_device(intf, priv); | |
900 | list_del(&intf->list); | |
901 | mutex_unlock(&intf_mutex); | |
902 | } | |
903 | EXPORT_SYMBOL(mlx5_unregister_interface); | |
904 | ||
905 | void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol) | |
906 | { | |
907 | struct mlx5_priv *priv = &mdev->priv; | |
908 | struct mlx5_device_context *dev_ctx; | |
909 | unsigned long flags; | |
910 | void *result = NULL; | |
911 | ||
912 | spin_lock_irqsave(&priv->ctx_lock, flags); | |
913 | ||
914 | list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list) | |
915 | if ((dev_ctx->intf->protocol == protocol) && | |
916 | dev_ctx->intf->get_dev) { | |
917 | result = dev_ctx->intf->get_dev(dev_ctx->context); | |
918 | break; | |
919 | } | |
920 | ||
921 | spin_unlock_irqrestore(&priv->ctx_lock, flags); | |
922 | ||
923 | return result; | |
924 | } | |
925 | EXPORT_SYMBOL(mlx5_get_protocol_dev); | |
926 | ||
927 | static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) | |
928 | { | |
929 | struct pci_dev *pdev = dev->pdev; | |
930 | int err = 0; | |
e126ba97 | 931 | |
e126ba97 EC |
932 | pci_set_drvdata(dev->pdev, dev); |
933 | strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); | |
934 | priv->name[MLX5_MAX_NAME_LEN - 1] = 0; | |
935 | ||
936 | mutex_init(&priv->pgdir_mutex); | |
937 | INIT_LIST_HEAD(&priv->pgdir_list); | |
938 | spin_lock_init(&priv->mkey_lock); | |
939 | ||
311c7c71 SM |
940 | mutex_init(&priv->alloc_mutex); |
941 | ||
942 | priv->numa_node = dev_to_node(&dev->pdev->dev); | |
943 | ||
e126ba97 EC |
944 | priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root); |
945 | if (!priv->dbg_root) | |
946 | return -ENOMEM; | |
947 | ||
89d44f0a | 948 | err = mlx5_pci_enable_device(dev); |
e126ba97 | 949 | if (err) { |
1a91de28 | 950 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
e126ba97 EC |
951 | goto err_dbg; |
952 | } | |
953 | ||
954 | err = request_bar(pdev); | |
955 | if (err) { | |
1a91de28 | 956 | dev_err(&pdev->dev, "error requesting BARs, aborting\n"); |
e126ba97 EC |
957 | goto err_disable; |
958 | } | |
959 | ||
960 | pci_set_master(pdev); | |
961 | ||
962 | err = set_dma_caps(pdev); | |
963 | if (err) { | |
964 | dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n"); | |
965 | goto err_clr_master; | |
966 | } | |
967 | ||
968 | dev->iseg_base = pci_resource_start(dev->pdev, 0); | |
969 | dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); | |
970 | if (!dev->iseg) { | |
971 | err = -ENOMEM; | |
972 | dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n"); | |
973 | goto err_clr_master; | |
974 | } | |
a31208b1 MD |
975 | |
976 | return 0; | |
977 | ||
978 | err_clr_master: | |
979 | pci_clear_master(dev->pdev); | |
980 | release_bar(dev->pdev); | |
981 | err_disable: | |
89d44f0a | 982 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
983 | |
984 | err_dbg: | |
985 | debugfs_remove(priv->dbg_root); | |
986 | return err; | |
987 | } | |
988 | ||
989 | static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) | |
990 | { | |
991 | iounmap(dev->iseg); | |
992 | pci_clear_master(dev->pdev); | |
993 | release_bar(dev->pdev); | |
89d44f0a | 994 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
995 | debugfs_remove(priv->dbg_root); |
996 | } | |
997 | ||
998 | #define MLX5_IB_MOD "mlx5_ib" | |
999 | static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv) | |
1000 | { | |
1001 | struct pci_dev *pdev = dev->pdev; | |
1002 | int err; | |
1003 | ||
89d44f0a | 1004 | mutex_lock(&dev->intf_state_mutex); |
5fc7197d | 1005 | if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
89d44f0a MD |
1006 | dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", |
1007 | __func__); | |
1008 | goto out; | |
1009 | } | |
1010 | ||
e126ba97 EC |
1011 | dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), |
1012 | fw_rev_min(dev), fw_rev_sub(dev)); | |
1013 | ||
89d44f0a MD |
1014 | /* on load removing any previous indication of internal error, device is |
1015 | * up | |
1016 | */ | |
1017 | dev->state = MLX5_DEVICE_STATE_UP; | |
1018 | ||
e126ba97 EC |
1019 | err = mlx5_cmd_init(dev); |
1020 | if (err) { | |
1021 | dev_err(&pdev->dev, "Failed initializing command interface, aborting\n"); | |
89d44f0a | 1022 | goto out_err; |
e126ba97 EC |
1023 | } |
1024 | ||
e3297246 EC |
1025 | err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); |
1026 | if (err) { | |
1027 | dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n", | |
1028 | FW_INIT_TIMEOUT_MILI); | |
1029 | goto out_err; | |
1030 | } | |
1031 | ||
e126ba97 | 1032 | mlx5_pagealloc_init(dev); |
cd23b14b | 1033 | |
0b107106 | 1034 | err = mlx5_core_enable_hca(dev, 0); |
cd23b14b EC |
1035 | if (err) { |
1036 | dev_err(&pdev->dev, "enable hca failed\n"); | |
1037 | goto err_pagealloc_cleanup; | |
1038 | } | |
1039 | ||
f62b8bb8 AV |
1040 | err = mlx5_core_set_issi(dev); |
1041 | if (err) { | |
1042 | dev_err(&pdev->dev, "failed to set issi\n"); | |
1043 | goto err_disable_hca; | |
1044 | } | |
f62b8bb8 | 1045 | |
cd23b14b EC |
1046 | err = mlx5_satisfy_startup_pages(dev, 1); |
1047 | if (err) { | |
1048 | dev_err(&pdev->dev, "failed to allocate boot pages\n"); | |
1049 | goto err_disable_hca; | |
1050 | } | |
1051 | ||
e126ba97 EC |
1052 | err = set_hca_ctrl(dev); |
1053 | if (err) { | |
1054 | dev_err(&pdev->dev, "set_hca_ctrl failed\n"); | |
cd23b14b | 1055 | goto reclaim_boot_pages; |
e126ba97 EC |
1056 | } |
1057 | ||
1058 | err = handle_hca_cap(dev); | |
1059 | if (err) { | |
1060 | dev_err(&pdev->dev, "handle_hca_cap failed\n"); | |
cd23b14b | 1061 | goto reclaim_boot_pages; |
e126ba97 EC |
1062 | } |
1063 | ||
f91e6d89 EBE |
1064 | err = handle_hca_cap_atomic(dev); |
1065 | if (err) { | |
1066 | dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n"); | |
1067 | goto reclaim_boot_pages; | |
e126ba97 EC |
1068 | } |
1069 | ||
cd23b14b | 1070 | err = mlx5_satisfy_startup_pages(dev, 0); |
e126ba97 | 1071 | if (err) { |
cd23b14b EC |
1072 | dev_err(&pdev->dev, "failed to allocate init pages\n"); |
1073 | goto reclaim_boot_pages; | |
e126ba97 EC |
1074 | } |
1075 | ||
1076 | err = mlx5_pagealloc_start(dev); | |
1077 | if (err) { | |
1078 | dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n"); | |
cd23b14b | 1079 | goto reclaim_boot_pages; |
e126ba97 EC |
1080 | } |
1081 | ||
1082 | err = mlx5_cmd_init_hca(dev); | |
1083 | if (err) { | |
1084 | dev_err(&pdev->dev, "init hca failed\n"); | |
1085 | goto err_pagealloc_stop; | |
1086 | } | |
1087 | ||
1088 | mlx5_start_health_poll(dev); | |
1089 | ||
938fe83c | 1090 | err = mlx5_query_hca_caps(dev); |
e126ba97 EC |
1091 | if (err) { |
1092 | dev_err(&pdev->dev, "query hca failed\n"); | |
1093 | goto err_stop_poll; | |
1094 | } | |
1095 | ||
211e6c80 | 1096 | err = mlx5_query_board_id(dev); |
e126ba97 | 1097 | if (err) { |
211e6c80 | 1098 | dev_err(&pdev->dev, "query board id failed\n"); |
e126ba97 EC |
1099 | goto err_stop_poll; |
1100 | } | |
1101 | ||
1102 | err = mlx5_enable_msix(dev); | |
1103 | if (err) { | |
1104 | dev_err(&pdev->dev, "enable msix failed\n"); | |
1105 | goto err_stop_poll; | |
1106 | } | |
1107 | ||
1108 | err = mlx5_eq_init(dev); | |
1109 | if (err) { | |
1110 | dev_err(&pdev->dev, "failed to initialize eq\n"); | |
1111 | goto disable_msix; | |
1112 | } | |
1113 | ||
1114 | err = mlx5_alloc_uuars(dev, &priv->uuari); | |
1115 | if (err) { | |
1116 | dev_err(&pdev->dev, "Failed allocating uar, aborting\n"); | |
1117 | goto err_eq_cleanup; | |
1118 | } | |
1119 | ||
1120 | err = mlx5_start_eqs(dev); | |
1121 | if (err) { | |
1122 | dev_err(&pdev->dev, "Failed to start pages and async EQs\n"); | |
1123 | goto err_free_uar; | |
1124 | } | |
1125 | ||
233d05d2 SM |
1126 | err = alloc_comp_eqs(dev); |
1127 | if (err) { | |
1128 | dev_err(&pdev->dev, "Failed to alloc completion EQs\n"); | |
1129 | goto err_stop_eqs; | |
1130 | } | |
1131 | ||
db058a18 | 1132 | err = mlx5_irq_set_affinity_hints(dev); |
0ba42241 | 1133 | if (err) |
db058a18 | 1134 | dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n"); |
db058a18 | 1135 | |
e126ba97 EC |
1136 | MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); |
1137 | ||
1138 | mlx5_init_cq_table(dev); | |
1139 | mlx5_init_qp_table(dev); | |
1140 | mlx5_init_srq_table(dev); | |
a606b0f6 | 1141 | mlx5_init_mkey_table(dev); |
e126ba97 | 1142 | |
86d722ad MG |
1143 | err = mlx5_init_fs(dev); |
1144 | if (err) { | |
1145 | dev_err(&pdev->dev, "Failed to init flow steering\n"); | |
1146 | goto err_fs; | |
1147 | } | |
1466cc5b YP |
1148 | |
1149 | err = mlx5_init_rl_table(dev); | |
1150 | if (err) { | |
1151 | dev_err(&pdev->dev, "Failed to init rate limiting\n"); | |
1152 | goto err_rl; | |
1153 | } | |
1154 | ||
073bb189 SM |
1155 | #ifdef CONFIG_MLX5_CORE_EN |
1156 | err = mlx5_eswitch_init(dev); | |
1157 | if (err) { | |
1158 | dev_err(&pdev->dev, "eswitch init failed %d\n", err); | |
1159 | goto err_reg_dev; | |
1160 | } | |
1161 | #endif | |
1162 | ||
fc50db98 EC |
1163 | err = mlx5_sriov_init(dev); |
1164 | if (err) { | |
1165 | dev_err(&pdev->dev, "sriov init failed %d\n", err); | |
1166 | goto err_sriov; | |
1167 | } | |
1168 | ||
a31208b1 MD |
1169 | err = mlx5_register_device(dev); |
1170 | if (err) { | |
1171 | dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); | |
1172 | goto err_reg_dev; | |
1173 | } | |
1174 | ||
1175 | err = request_module_nowait(MLX5_IB_MOD); | |
1176 | if (err) | |
1177 | pr_info("failed request module on %s\n", MLX5_IB_MOD); | |
1178 | ||
5fc7197d MD |
1179 | clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state); |
1180 | set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); | |
89d44f0a MD |
1181 | out: |
1182 | mutex_unlock(&dev->intf_state_mutex); | |
1183 | ||
e126ba97 EC |
1184 | return 0; |
1185 | ||
fc50db98 EC |
1186 | err_sriov: |
1187 | if (mlx5_sriov_cleanup(dev)) | |
1188 | dev_err(&dev->pdev->dev, "sriov cleanup failed\n"); | |
1189 | ||
073bb189 SM |
1190 | #ifdef CONFIG_MLX5_CORE_EN |
1191 | mlx5_eswitch_cleanup(dev->priv.eswitch); | |
1192 | #endif | |
a31208b1 | 1193 | err_reg_dev: |
1466cc5b YP |
1194 | mlx5_cleanup_rl_table(dev); |
1195 | err_rl: | |
86d722ad MG |
1196 | mlx5_cleanup_fs(dev); |
1197 | err_fs: | |
a606b0f6 | 1198 | mlx5_cleanup_mkey_table(dev); |
a31208b1 MD |
1199 | mlx5_cleanup_srq_table(dev); |
1200 | mlx5_cleanup_qp_table(dev); | |
1201 | mlx5_cleanup_cq_table(dev); | |
1202 | mlx5_irq_clear_affinity_hints(dev); | |
db058a18 SM |
1203 | free_comp_eqs(dev); |
1204 | ||
233d05d2 SM |
1205 | err_stop_eqs: |
1206 | mlx5_stop_eqs(dev); | |
1207 | ||
e126ba97 EC |
1208 | err_free_uar: |
1209 | mlx5_free_uuars(dev, &priv->uuari); | |
1210 | ||
1211 | err_eq_cleanup: | |
1212 | mlx5_eq_cleanup(dev); | |
1213 | ||
1214 | disable_msix: | |
1215 | mlx5_disable_msix(dev); | |
1216 | ||
1217 | err_stop_poll: | |
1218 | mlx5_stop_health_poll(dev); | |
1bde6e30 EC |
1219 | if (mlx5_cmd_teardown_hca(dev)) { |
1220 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); | |
89d44f0a | 1221 | goto out_err; |
1bde6e30 | 1222 | } |
e126ba97 EC |
1223 | |
1224 | err_pagealloc_stop: | |
1225 | mlx5_pagealloc_stop(dev); | |
1226 | ||
cd23b14b | 1227 | reclaim_boot_pages: |
e126ba97 EC |
1228 | mlx5_reclaim_startup_pages(dev); |
1229 | ||
cd23b14b | 1230 | err_disable_hca: |
0b107106 | 1231 | mlx5_core_disable_hca(dev, 0); |
cd23b14b | 1232 | |
e126ba97 EC |
1233 | err_pagealloc_cleanup: |
1234 | mlx5_pagealloc_cleanup(dev); | |
1235 | mlx5_cmd_cleanup(dev); | |
1236 | ||
89d44f0a MD |
1237 | out_err: |
1238 | dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; | |
1239 | mutex_unlock(&dev->intf_state_mutex); | |
1240 | ||
e126ba97 EC |
1241 | return err; |
1242 | } | |
e126ba97 | 1243 | |
a31208b1 | 1244 | static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
e126ba97 | 1245 | { |
89d44f0a | 1246 | int err = 0; |
e126ba97 | 1247 | |
fc50db98 EC |
1248 | err = mlx5_sriov_cleanup(dev); |
1249 | if (err) { | |
1250 | dev_warn(&dev->pdev->dev, "%s: sriov cleanup failed - abort\n", | |
1251 | __func__); | |
1252 | return err; | |
1253 | } | |
1254 | ||
89d44f0a | 1255 | mutex_lock(&dev->intf_state_mutex); |
5fc7197d | 1256 | if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) { |
89d44f0a MD |
1257 | dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", |
1258 | __func__); | |
1259 | goto out; | |
1260 | } | |
a31208b1 | 1261 | mlx5_unregister_device(dev); |
073bb189 SM |
1262 | #ifdef CONFIG_MLX5_CORE_EN |
1263 | mlx5_eswitch_cleanup(dev->priv.eswitch); | |
1264 | #endif | |
1265 | ||
1466cc5b | 1266 | mlx5_cleanup_rl_table(dev); |
86d722ad | 1267 | mlx5_cleanup_fs(dev); |
a606b0f6 | 1268 | mlx5_cleanup_mkey_table(dev); |
e126ba97 EC |
1269 | mlx5_cleanup_srq_table(dev); |
1270 | mlx5_cleanup_qp_table(dev); | |
1271 | mlx5_cleanup_cq_table(dev); | |
db058a18 | 1272 | mlx5_irq_clear_affinity_hints(dev); |
233d05d2 | 1273 | free_comp_eqs(dev); |
e126ba97 EC |
1274 | mlx5_stop_eqs(dev); |
1275 | mlx5_free_uuars(dev, &priv->uuari); | |
1276 | mlx5_eq_cleanup(dev); | |
1277 | mlx5_disable_msix(dev); | |
1278 | mlx5_stop_health_poll(dev); | |
ac6ea6e8 EC |
1279 | err = mlx5_cmd_teardown_hca(dev); |
1280 | if (err) { | |
1bde6e30 | 1281 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); |
ac6ea6e8 | 1282 | goto out; |
1bde6e30 | 1283 | } |
e126ba97 EC |
1284 | mlx5_pagealloc_stop(dev); |
1285 | mlx5_reclaim_startup_pages(dev); | |
0b107106 | 1286 | mlx5_core_disable_hca(dev, 0); |
e126ba97 EC |
1287 | mlx5_pagealloc_cleanup(dev); |
1288 | mlx5_cmd_cleanup(dev); | |
9603b61d | 1289 | |
ac6ea6e8 | 1290 | out: |
5fc7197d MD |
1291 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
1292 | set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state); | |
89d44f0a | 1293 | mutex_unlock(&dev->intf_state_mutex); |
ac6ea6e8 | 1294 | return err; |
9603b61d | 1295 | } |
64613d94 | 1296 | |
89d44f0a | 1297 | void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, |
ac6ea6e8 | 1298 | unsigned long param) |
9603b61d JM |
1299 | { |
1300 | struct mlx5_priv *priv = &dev->priv; | |
1301 | struct mlx5_device_context *dev_ctx; | |
1302 | unsigned long flags; | |
1303 | ||
1304 | spin_lock_irqsave(&priv->ctx_lock, flags); | |
1305 | ||
1306 | list_for_each_entry(dev_ctx, &priv->ctx_list, list) | |
1307 | if (dev_ctx->intf->event) | |
4d2f9bbb | 1308 | dev_ctx->intf->event(dev, dev_ctx->context, event, param); |
9603b61d JM |
1309 | |
1310 | spin_unlock_irqrestore(&priv->ctx_lock, flags); | |
1311 | } | |
1312 | ||
1313 | struct mlx5_core_event_handler { | |
1314 | void (*event)(struct mlx5_core_dev *dev, | |
1315 | enum mlx5_dev_event event, | |
1316 | void *data); | |
1317 | }; | |
1318 | ||
feae9087 OG |
1319 | static const struct devlink_ops mlx5_devlink_ops = { |
1320 | #ifdef CONFIG_MLX5_CORE_EN | |
1321 | .eswitch_mode_set = mlx5_devlink_eswitch_mode_set, | |
1322 | .eswitch_mode_get = mlx5_devlink_eswitch_mode_get, | |
1323 | #endif | |
1324 | }; | |
f66f049f | 1325 | |
9603b61d JM |
1326 | static int init_one(struct pci_dev *pdev, |
1327 | const struct pci_device_id *id) | |
1328 | { | |
1329 | struct mlx5_core_dev *dev; | |
feae9087 | 1330 | struct devlink *devlink; |
9603b61d JM |
1331 | struct mlx5_priv *priv; |
1332 | int err; | |
1333 | ||
feae9087 OG |
1334 | devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev)); |
1335 | if (!devlink) { | |
9603b61d JM |
1336 | dev_err(&pdev->dev, "kzalloc failed\n"); |
1337 | return -ENOMEM; | |
1338 | } | |
feae9087 OG |
1339 | |
1340 | dev = devlink_priv(devlink); | |
9603b61d | 1341 | priv = &dev->priv; |
fc50db98 | 1342 | priv->pci_dev_data = id->driver_data; |
9603b61d JM |
1343 | |
1344 | pci_set_drvdata(pdev, dev); | |
1345 | ||
1346 | if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) { | |
1347 | pr_warn("selected profile out of range, selecting default (%d)\n", | |
1348 | MLX5_DEFAULT_PROF); | |
1349 | prof_sel = MLX5_DEFAULT_PROF; | |
1350 | } | |
1351 | dev->profile = &profile[prof_sel]; | |
a31208b1 | 1352 | dev->pdev = pdev; |
9603b61d JM |
1353 | dev->event = mlx5_core_event; |
1354 | ||
364d1798 EC |
1355 | INIT_LIST_HEAD(&priv->ctx_list); |
1356 | spin_lock_init(&priv->ctx_lock); | |
89d44f0a MD |
1357 | mutex_init(&dev->pci_status_mutex); |
1358 | mutex_init(&dev->intf_state_mutex); | |
a31208b1 | 1359 | err = mlx5_pci_init(dev, priv); |
9603b61d | 1360 | if (err) { |
a31208b1 MD |
1361 | dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err); |
1362 | goto clean_dev; | |
9603b61d JM |
1363 | } |
1364 | ||
ac6ea6e8 EC |
1365 | err = mlx5_health_init(dev); |
1366 | if (err) { | |
1367 | dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err); | |
1368 | goto close_pci; | |
1369 | } | |
1370 | ||
a31208b1 | 1371 | err = mlx5_load_one(dev, priv); |
9603b61d | 1372 | if (err) { |
a31208b1 | 1373 | dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err); |
ac6ea6e8 | 1374 | goto clean_health; |
9603b61d JM |
1375 | } |
1376 | ||
feae9087 OG |
1377 | err = devlink_register(devlink, &pdev->dev); |
1378 | if (err) | |
1379 | goto clean_load; | |
1380 | ||
9603b61d JM |
1381 | return 0; |
1382 | ||
feae9087 OG |
1383 | clean_load: |
1384 | mlx5_unload_one(dev, priv); | |
ac6ea6e8 EC |
1385 | clean_health: |
1386 | mlx5_health_cleanup(dev); | |
a31208b1 MD |
1387 | close_pci: |
1388 | mlx5_pci_close(dev, priv); | |
1389 | clean_dev: | |
1390 | pci_set_drvdata(pdev, NULL); | |
feae9087 | 1391 | devlink_free(devlink); |
a31208b1 | 1392 | |
9603b61d JM |
1393 | return err; |
1394 | } | |
a31208b1 | 1395 | |
9603b61d JM |
1396 | static void remove_one(struct pci_dev *pdev) |
1397 | { | |
1398 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
feae9087 | 1399 | struct devlink *devlink = priv_to_devlink(dev); |
a31208b1 | 1400 | struct mlx5_priv *priv = &dev->priv; |
9603b61d | 1401 | |
feae9087 | 1402 | devlink_unregister(devlink); |
a31208b1 MD |
1403 | if (mlx5_unload_one(dev, priv)) { |
1404 | dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); | |
ac6ea6e8 | 1405 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1406 | return; |
1407 | } | |
ac6ea6e8 | 1408 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1409 | mlx5_pci_close(dev, priv); |
1410 | pci_set_drvdata(pdev, NULL); | |
feae9087 | 1411 | devlink_free(devlink); |
9603b61d JM |
1412 | } |
1413 | ||
89d44f0a MD |
1414 | static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, |
1415 | pci_channel_state_t state) | |
1416 | { | |
1417 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1418 | struct mlx5_priv *priv = &dev->priv; | |
1419 | ||
1420 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1421 | mlx5_enter_error_state(dev); | |
1422 | mlx5_unload_one(dev, priv); | |
1423 | mlx5_pci_disable_device(dev); | |
1424 | return state == pci_channel_io_perm_failure ? | |
1425 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
1426 | } | |
1427 | ||
1428 | static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) | |
1429 | { | |
1430 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1431 | int err = 0; | |
1432 | ||
1433 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1434 | ||
1435 | err = mlx5_pci_enable_device(dev); | |
1436 | if (err) { | |
1437 | dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" | |
1438 | , __func__, err); | |
1439 | return PCI_ERS_RESULT_DISCONNECT; | |
1440 | } | |
1441 | pci_set_master(pdev); | |
1442 | pci_set_power_state(pdev, PCI_D0); | |
1443 | pci_restore_state(pdev); | |
1444 | ||
1445 | return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; | |
1446 | } | |
1447 | ||
1448 | void mlx5_disable_device(struct mlx5_core_dev *dev) | |
1449 | { | |
1450 | mlx5_pci_err_detected(dev->pdev, 0); | |
1451 | } | |
1452 | ||
d57847dc DJ |
1453 | /* wait for the device to show vital signs by waiting |
1454 | * for the health counter to start counting. | |
89d44f0a | 1455 | */ |
d57847dc | 1456 | static int wait_vital(struct pci_dev *pdev) |
89d44f0a MD |
1457 | { |
1458 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1459 | struct mlx5_core_health *health = &dev->priv.health; | |
1460 | const int niter = 100; | |
d57847dc | 1461 | u32 last_count = 0; |
89d44f0a | 1462 | u32 count; |
89d44f0a MD |
1463 | int i; |
1464 | ||
89d44f0a MD |
1465 | for (i = 0; i < niter; i++) { |
1466 | count = ioread32be(health->health_counter); | |
1467 | if (count && count != 0xffffffff) { | |
d57847dc DJ |
1468 | if (last_count && last_count != count) { |
1469 | dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); | |
1470 | return 0; | |
1471 | } | |
1472 | last_count = count; | |
89d44f0a MD |
1473 | } |
1474 | msleep(50); | |
1475 | } | |
1476 | ||
d57847dc | 1477 | return -ETIMEDOUT; |
89d44f0a MD |
1478 | } |
1479 | ||
1480 | static void mlx5_pci_resume(struct pci_dev *pdev) | |
1481 | { | |
1482 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1483 | struct mlx5_priv *priv = &dev->priv; | |
1484 | int err; | |
1485 | ||
1486 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1487 | ||
1488 | pci_save_state(pdev); | |
d57847dc DJ |
1489 | err = wait_vital(pdev); |
1490 | if (err) { | |
1491 | dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__); | |
1492 | return; | |
1493 | } | |
89d44f0a MD |
1494 | |
1495 | err = mlx5_load_one(dev, priv); | |
1496 | if (err) | |
1497 | dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" | |
1498 | , __func__, err); | |
1499 | else | |
1500 | dev_info(&pdev->dev, "%s: device recovered\n", __func__); | |
1501 | } | |
1502 | ||
1503 | static const struct pci_error_handlers mlx5_err_handler = { | |
1504 | .error_detected = mlx5_pci_err_detected, | |
1505 | .slot_reset = mlx5_pci_slot_reset, | |
1506 | .resume = mlx5_pci_resume | |
1507 | }; | |
1508 | ||
5fc7197d MD |
1509 | static void shutdown(struct pci_dev *pdev) |
1510 | { | |
1511 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1512 | struct mlx5_priv *priv = &dev->priv; | |
1513 | ||
1514 | dev_info(&pdev->dev, "Shutdown was called\n"); | |
1515 | /* Notify mlx5 clients that the kernel is being shut down */ | |
1516 | set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state); | |
1517 | mlx5_unload_one(dev, priv); | |
1518 | mlx5_pci_disable_device(dev); | |
1519 | } | |
1520 | ||
9603b61d | 1521 | static const struct pci_device_id mlx5_core_pci_table[] = { |
fc50db98 EC |
1522 | { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */ |
1523 | { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ | |
1524 | { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */ | |
1525 | { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ | |
1526 | { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */ | |
1527 | { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ | |
7092fe86 | 1528 | { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ |
64dbbdfe | 1529 | { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ |
7092fe86 | 1530 | { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5, PCIe 4.0 */ |
9603b61d JM |
1531 | { 0, } |
1532 | }; | |
1533 | ||
1534 | MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); | |
1535 | ||
1536 | static struct pci_driver mlx5_core_driver = { | |
1537 | .name = DRIVER_NAME, | |
1538 | .id_table = mlx5_core_pci_table, | |
1539 | .probe = init_one, | |
89d44f0a | 1540 | .remove = remove_one, |
5fc7197d | 1541 | .shutdown = shutdown, |
fc50db98 EC |
1542 | .err_handler = &mlx5_err_handler, |
1543 | .sriov_configure = mlx5_core_sriov_configure, | |
9603b61d | 1544 | }; |
e126ba97 EC |
1545 | |
1546 | static int __init init(void) | |
1547 | { | |
1548 | int err; | |
1549 | ||
1550 | mlx5_register_debugfs(); | |
e126ba97 | 1551 | |
9603b61d JM |
1552 | err = pci_register_driver(&mlx5_core_driver); |
1553 | if (err) | |
ac6ea6e8 | 1554 | goto err_debug; |
9603b61d | 1555 | |
f62b8bb8 AV |
1556 | #ifdef CONFIG_MLX5_CORE_EN |
1557 | mlx5e_init(); | |
1558 | #endif | |
1559 | ||
e126ba97 EC |
1560 | return 0; |
1561 | ||
e126ba97 EC |
1562 | err_debug: |
1563 | mlx5_unregister_debugfs(); | |
1564 | return err; | |
1565 | } | |
1566 | ||
1567 | static void __exit cleanup(void) | |
1568 | { | |
f62b8bb8 AV |
1569 | #ifdef CONFIG_MLX5_CORE_EN |
1570 | mlx5e_cleanup(); | |
1571 | #endif | |
9603b61d | 1572 | pci_unregister_driver(&mlx5_core_driver); |
e126ba97 EC |
1573 | mlx5_unregister_debugfs(); |
1574 | } | |
1575 | ||
1576 | module_init(init); | |
1577 | module_exit(cleanup); |