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alx: remove pointless assignment
[people/arne_f/kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
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e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e3297246 42#include <linux/delay.h>
e126ba97
EC		 43#include <linux/mlx5/driver.h>
44#include <linux/mlx5/cq.h>
45#include <linux/mlx5/qp.h>
46#include <linux/mlx5/srq.h>
47#include <linux/debugfs.h>
f66f049f 48#include <linux/kmod.h>
89d44f0a 49#include <linux/delay.h>
b775516b 50#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 51#include "mlx5_core.h"
52
e126ba97 53MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 54MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRIVER_VERSION);
57
58int mlx5_core_debug_mask;
59module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
60MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
61
9603b61d
JM		 62#define MLX5_DEFAULT_PROF 2
63static int prof_sel = MLX5_DEFAULT_PROF;
64module_param_named(prof_sel, prof_sel, int, 0444);
65MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
66
9603b61d
JM		 67static LIST_HEAD(intf_list);
68static LIST_HEAD(dev_list);
69static DEFINE_MUTEX(intf_mutex);
70
71struct mlx5_device_context {
72 struct list_head list;
73 struct mlx5_interface *intf;
74 void *context;
75};
76
77static struct mlx5_profile profile[] = {
78 [0] = {
79 .mask = 0,
80 },
81 [1] = {
82 .mask = MLX5_PROF_MASK_QP_SIZE,
83 .log_max_qp = 12,
84 },
85 [2] = {
86 .mask = MLX5_PROF_MASK_QP_SIZE |
87 MLX5_PROF_MASK_MR_CACHE,
88 .log_max_qp = 17,
89 .mr_cache[0] = {
90 .size = 500,
91 .limit = 250
92 },
93 .mr_cache[1] = {
94 .size = 500,
95 .limit = 250
96 },
97 .mr_cache[2] = {
98 .size = 500,
99 .limit = 250
100 },
101 .mr_cache[3] = {
102 .size = 500,
103 .limit = 250
104 },
105 .mr_cache[4] = {
106 .size = 500,
107 .limit = 250
108 },
109 .mr_cache[5] = {
110 .size = 500,
111 .limit = 250
112 },
113 .mr_cache[6] = {
114 .size = 500,
115 .limit = 250
116 },
117 .mr_cache[7] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[8] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[9] = {
126 .size = 500,
127 .limit = 250
128 },
129 .mr_cache[10] = {
130 .size = 500,
131 .limit = 250
132 },
133 .mr_cache[11] = {
134 .size = 500,
135 .limit = 250
136 },
137 .mr_cache[12] = {
138 .size = 64,
139 .limit = 32
140 },
141 .mr_cache[13] = {
142 .size = 32,
143 .limit = 16
144 },
145 .mr_cache[14] = {
146 .size = 16,
147 .limit = 8
148 },
149 .mr_cache[15] = {
150 .size = 8,
151 .limit = 4
152 },
153 },
154};
e126ba97 155
e3297246
EC		 156#define FW_INIT_TIMEOUT_MILI 2000
157#define FW_INIT_WAIT_MS 2
158
159static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
160{
161 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
162 int err = 0;
163
164 while (fw_initializing(dev)) {
165 if (time_after(jiffies, end)) {
166 err = -EBUSY;
167 break;
168 }
169 msleep(FW_INIT_WAIT_MS);
170 }
171
172 return err;
173}
174
e126ba97
EC		 175static int set_dma_caps(struct pci_dev *pdev)
176{
177 int err;
178
179 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
180 if (err) {
1a91de28 181 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 182 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
183 if (err) {
1a91de28 184 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 185 return err;
186 }
187 }
188
189 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
190 if (err) {
191 dev_warn(&pdev->dev,
1a91de28 192 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 193 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
194 if (err) {
195 dev_err(&pdev->dev,
1a91de28 196 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 197 return err;
198 }
199 }
200
201 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
202 return err;
203}
204
89d44f0a
MD		 205static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
206{
207 struct pci_dev *pdev = dev->pdev;
208 int err = 0;
209
210 mutex_lock(&dev->pci_status_mutex);
211 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
212 err = pci_enable_device(pdev);
213 if (!err)
214 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
215 }
216 mutex_unlock(&dev->pci_status_mutex);
217
218 return err;
219}
220
221static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
222{
223 struct pci_dev *pdev = dev->pdev;
224
225 mutex_lock(&dev->pci_status_mutex);
226 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
227 pci_disable_device(pdev);
228 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
229 }
230 mutex_unlock(&dev->pci_status_mutex);
231}
232
e126ba97
EC		 233static int request_bar(struct pci_dev *pdev)
234{
235 int err = 0;
236
237 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 238 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 239 return -ENODEV;
240 }
241
242 err = pci_request_regions(pdev, DRIVER_NAME);
243 if (err)
244 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
245
246 return err;
247}
248
249static void release_bar(struct pci_dev *pdev)
250{
251 pci_release_regions(pdev);
252}
253
254static int mlx5_enable_msix(struct mlx5_core_dev *dev)
255{
db058a18
SM		 256 struct mlx5_priv *priv = &dev->priv;
257 struct mlx5_eq_table *table = &priv->eq_table;
938fe83c 258 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
e126ba97 259 int nvec;
e126ba97
EC		 260 int i;
261
938fe83c
SM		 262 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
263 MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 264 nvec = min_t(int, nvec, num_eqs);
265 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
266 return -ENOMEM;
267
db058a18
SM		 268 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
269
270 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
271 if (!priv->msix_arr || !priv->irq_info)
272 goto err_free_msix;
e126ba97
EC		 273
274 for (i = 0; i < nvec; i++)
db058a18 275 priv->msix_arr[i].entry = i;
e126ba97 276
db058a18 277 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
3a9e161a 278 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 279 if (nvec < 0)
280 return nvec;
e126ba97 281
f3c9407b 282 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 283
284 return 0;
db058a18
SM		 285
286err_free_msix:
287 kfree(priv->irq_info);
288 kfree(priv->msix_arr);
289 return -ENOMEM;
e126ba97
EC		 290}
291
292static void mlx5_disable_msix(struct mlx5_core_dev *dev)
293{
db058a18 294 struct mlx5_priv *priv = &dev->priv;
e126ba97
EC		 295
296 pci_disable_msix(dev->pdev);
db058a18
SM		 297 kfree(priv->irq_info);
298 kfree(priv->msix_arr);
e126ba97
EC		 299}
300
301struct mlx5_reg_host_endianess {
302 u8 he;
303 u8 rsvd[15];
304};
305
87b8de49
EC		 306
307#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
308
309enum {
c7a08ac7
EC		 310 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
311 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 312};
313
c7a08ac7
EC		 314static u16 to_fw_pkey_sz(u32 size)
315{
316 switch (size) {
317 case 128:
318 return 0;
319 case 256:
320 return 1;
321 case 512:
322 return 2;
323 case 1024:
324 return 3;
325 case 2048:
326 return 4;
327 case 4096:
328 return 5;
329 default:
330 pr_warn("invalid pkey table size %d\n", size);
331 return 0;
332 }
333}
334
938fe83c
SM		 335int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
336 enum mlx5_cap_mode cap_mode)
c7a08ac7 337{
b775516b
EC		 338 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
339 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
938fe83c
SM		 340 void *out, *hca_caps;
341 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
e126ba97
EC		 342 int err;
343
b775516b
EC		 344 memset(in, 0, sizeof(in));
345 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 346 if (!out)
e126ba97 347 return -ENOMEM;
938fe83c 348
b775516b
EC		 349 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
350 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
351 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
352 if (err)
353 goto query_ex;
e126ba97 354
b775516b 355 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7 356 if (err) {
938fe83c
SM		 357 mlx5_core_warn(dev,
358 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
359 cap_type, cap_mode, err);
e126ba97
EC		 360 goto query_ex;
361 }
c7a08ac7 362
938fe83c
SM		 363 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
364
365 switch (cap_mode) {
366 case HCA_CAP_OPMOD_GET_MAX:
367 memcpy(dev->hca_caps_max[cap_type], hca_caps,
368 MLX5_UN_SZ_BYTES(hca_cap_union));
369 break;
370 case HCA_CAP_OPMOD_GET_CUR:
371 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
372 MLX5_UN_SZ_BYTES(hca_cap_union));
373 break;
374 default:
375 mlx5_core_warn(dev,
376 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
377 cap_type, cap_mode);
378 err = -EINVAL;
379 break;
380 }
c7a08ac7
EC		 381query_ex:
382 kfree(out);
383 return err;
384}
385
b775516b 386static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
c7a08ac7 387{
b775516b 388 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
c7a08ac7
EC		 389 int err;
390
b775516b 391 memset(out, 0, sizeof(out));
e126ba97 392
b775516b
EC		 393 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
394 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
e126ba97 395 if (err)
c7a08ac7 396 return err;
e126ba97 397
b775516b 398 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 399
400 return err;
401}
402
403static int handle_hca_cap(struct mlx5_core_dev *dev)
404{
b775516b 405 void *set_ctx = NULL;
c7a08ac7 406 struct mlx5_profile *prof = dev->profile;
c7a08ac7 407 int err = -ENOMEM;
b775516b 408 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
938fe83c 409 void *set_hca_cap;
c7a08ac7 410
b775516b 411 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 412 if (!set_ctx)
e126ba97 413 goto query_ex;
e126ba97 414
938fe83c 415 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
c7a08ac7 416 if (err)
e126ba97 417 goto query_ex;
e126ba97 418
938fe83c 419 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
e126ba97
EC		 420 if (err)
421 goto query_ex;
422
938fe83c
SM		 423 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
424 capability);
425 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
426 MLX5_ST_SZ_BYTES(cmd_hca_cap));
427
428 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
707c4602 429 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
938fe83c 430 128);
c7a08ac7 431 /* we limit the size of the pkey table to 128 entries for now */
938fe83c
SM		 432 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
433 to_fw_pkey_sz(128));
c7a08ac7
EC		 434
435 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
938fe83c
SM		 436 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
437 prof->log_max_qp);
c7a08ac7 438
938fe83c
SM		 439 /* disable cmdif checksum */
440 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
c7a08ac7 441
fe1e1876
CS		 442 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
443
b775516b 444 err = set_caps(dev, set_ctx, set_sz);
c7a08ac7 445
e126ba97 446query_ex:
e126ba97 447 kfree(set_ctx);
e126ba97
EC		 448 return err;
449}
450
451static int set_hca_ctrl(struct mlx5_core_dev *dev)
452{
453 struct mlx5_reg_host_endianess he_in;
454 struct mlx5_reg_host_endianess he_out;
455 int err;
456
457 memset(&he_in, 0, sizeof(he_in));
458 he_in.he = MLX5_SET_HOST_ENDIANNESS;
459 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
460 &he_out, sizeof(he_out),
461 MLX5_REG_HOST_ENDIANNESS, 0, 1);
462 return err;
463}
464
cd23b14b
EC		 465static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
466{
467 int err;
468 struct mlx5_enable_hca_mbox_in in;
469 struct mlx5_enable_hca_mbox_out out;
470
471 memset(&in, 0, sizeof(in));
472 memset(&out, 0, sizeof(out));
473 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
474 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
475 if (err)
476 return err;
477
478 if (out.hdr.status)
479 return mlx5_cmd_status_to_err(&out.hdr);
480
481 return 0;
482}
483
484static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
485{
486 int err;
487 struct mlx5_disable_hca_mbox_in in;
488 struct mlx5_disable_hca_mbox_out out;
489
490 memset(&in, 0, sizeof(in));
491 memset(&out, 0, sizeof(out));
492 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
493 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
494 if (err)
495 return err;
496
497 if (out.hdr.status)
498 return mlx5_cmd_status_to_err(&out.hdr);
499
500 return 0;
501}
502
db058a18
SM		 503static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
504{
505 struct mlx5_priv *priv = &mdev->priv;
506 struct msix_entry *msix = priv->msix_arr;
507 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
311c7c71 508 int numa_node = priv->numa_node;
db058a18
SM		 509 int err;
510
511 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
512 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
513 return -ENOMEM;
514 }
515
dda922c8
DM		 516 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
517 priv->irq_info[i].mask);
db058a18
SM		 518
519 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
520 if (err) {
521 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
522 irq);
523 goto err_clear_mask;
524 }
525
526 return 0;
527
528err_clear_mask:
529 free_cpumask_var(priv->irq_info[i].mask);
530 return err;
531}
532
533static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
534{
535 struct mlx5_priv *priv = &mdev->priv;
536 struct msix_entry *msix = priv->msix_arr;
537 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
538
539 irq_set_affinity_hint(irq, NULL);
540 free_cpumask_var(priv->irq_info[i].mask);
541}
542
543static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
544{
545 int err;
546 int i;
547
548 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
549 err = mlx5_irq_set_affinity_hint(mdev, i);
550 if (err)
551 goto err_out;
552 }
553
554 return 0;
555
556err_out:
557 for (i--; i >= 0; i--)
558 mlx5_irq_clear_affinity_hint(mdev, i);
559
560 return err;
561}
562
563static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
564{
565 int i;
566
567 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
568 mlx5_irq_clear_affinity_hint(mdev, i);
569}
570
233d05d2
SM		 571int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
572{
573 struct mlx5_eq_table *table = &dev->priv.eq_table;
574 struct mlx5_eq *eq, *n;
575 int err = -ENOENT;
576
577 spin_lock(&table->lock);
578 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
579 if (eq->index == vector) {
580 *eqn = eq->eqn;
581 *irqn = eq->irqn;
582 err = 0;
583 break;
584 }
585 }
586 spin_unlock(&table->lock);
587
588 return err;
589}
590EXPORT_SYMBOL(mlx5_vector2eqn);
591
592static void free_comp_eqs(struct mlx5_core_dev *dev)
593{
594 struct mlx5_eq_table *table = &dev->priv.eq_table;
595 struct mlx5_eq *eq, *n;
596
597 spin_lock(&table->lock);
598 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
599 list_del(&eq->list);
600 spin_unlock(&table->lock);
601 if (mlx5_destroy_unmap_eq(dev, eq))
602 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
603 eq->eqn);
604 kfree(eq);
605 spin_lock(&table->lock);
606 }
607 spin_unlock(&table->lock);
608}
609
610static int alloc_comp_eqs(struct mlx5_core_dev *dev)
611{
612 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 613 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 614 struct mlx5_eq *eq;
615 int ncomp_vec;
616 int nent;
617 int err;
618 int i;
619
620 INIT_LIST_HEAD(&table->comp_eqs_list);
621 ncomp_vec = table->num_comp_vectors;
622 nent = MLX5_COMP_EQ_SIZE;
623 for (i = 0; i < ncomp_vec; i++) {
624 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
625 if (!eq) {
626 err = -ENOMEM;
627 goto clean;
628 }
629
db058a18 630 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 631 err = mlx5_create_map_eq(dev, eq,
632 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
633 name, &dev->priv.uuari.uars[0]);
634 if (err) {
635 kfree(eq);
636 goto clean;
637 }
638 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
639 eq->index = i;
640 spin_lock(&table->lock);
641 list_add_tail(&eq->list, &table->comp_eqs_list);
642 spin_unlock(&table->lock);
643 }
644
645 return 0;
646
647clean:
648 free_comp_eqs(dev);
649 return err;
650}
651
f62b8bb8
AV		 652#ifdef CONFIG_MLX5_CORE_EN
653static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
654{
655 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
656 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
657 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
658 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
659 int err;
660 u32 sup_issi;
661
662 memset(query_in, 0, sizeof(query_in));
663 memset(query_out, 0, sizeof(query_out));
664
665 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
666
667 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
668 query_out, sizeof(query_out));
669 if (err) {
670 if (((struct mlx5_outbox_hdr *)query_out)->status ==
671 MLX5_CMD_STAT_BAD_OP_ERR) {
672 pr_debug("Only ISSI 0 is supported\n");
673 return 0;
674 }
675
676 pr_err("failed to query ISSI\n");
677 return err;
678 }
679
680 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
681
682 if (sup_issi & (1 << 1)) {
683 memset(set_in, 0, sizeof(set_in));
684 memset(set_out, 0, sizeof(set_out));
685
686 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
687 MLX5_SET(set_issi_in, set_in, current_issi, 1);
688
689 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
690 set_out, sizeof(set_out));
691 if (err) {
692 pr_err("failed to set ISSI=1\n");
693 return err;
694 }
695
696 dev->issi = 1;
697
698 return 0;
e74a1db0 699 } else if (sup_issi & (1 << 0) || !sup_issi) {
f62b8bb8
AV		 700 return 0;
701 }
702
703 return -ENOTSUPP;
704}
705#endif
706
88a85f99
AS		 707static int map_bf_area(struct mlx5_core_dev *dev)
708{
709 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
710 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
711
712 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
713
714 return dev->priv.bf_mapping ? 0 : -ENOMEM;
715}
716
717static void unmap_bf_area(struct mlx5_core_dev *dev)
718{
719 if (dev->priv.bf_mapping)
720 io_mapping_free(dev->priv.bf_mapping);
721}
722
a31208b1
MD		 723static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
724{
725 struct mlx5_device_context *dev_ctx;
726 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
727
728 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
729 if (!dev_ctx)
730 return;
731
732 dev_ctx->intf = intf;
733 dev_ctx->context = intf->add(dev);
734
735 if (dev_ctx->context) {
736 spin_lock_irq(&priv->ctx_lock);
737 list_add_tail(&dev_ctx->list, &priv->ctx_list);
738 spin_unlock_irq(&priv->ctx_lock);
739 } else {
740 kfree(dev_ctx);
741 }
742}
743
744static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
745{
746 struct mlx5_device_context *dev_ctx;
747 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
748
749 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
750 if (dev_ctx->intf == intf) {
751 spin_lock_irq(&priv->ctx_lock);
752 list_del(&dev_ctx->list);
753 spin_unlock_irq(&priv->ctx_lock);
754
755 intf->remove(dev, dev_ctx->context);
756 kfree(dev_ctx);
757 return;
758 }
759}
760
761static int mlx5_register_device(struct mlx5_core_dev *dev)
e126ba97
EC		 762{
763 struct mlx5_priv *priv = &dev->priv;
a31208b1
MD		 764 struct mlx5_interface *intf;
765
766 mutex_lock(&intf_mutex);
767 list_add_tail(&priv->dev_list, &dev_list);
768 list_for_each_entry(intf, &intf_list, list)
769 mlx5_add_device(intf, priv);
770 mutex_unlock(&intf_mutex);
771
772 return 0;
773}
774
775static void mlx5_unregister_device(struct mlx5_core_dev *dev)
776{
777 struct mlx5_priv *priv = &dev->priv;
778 struct mlx5_interface *intf;
779
780 mutex_lock(&intf_mutex);
781 list_for_each_entry(intf, &intf_list, list)
782 mlx5_remove_device(intf, priv);
783 list_del(&priv->dev_list);
784 mutex_unlock(&intf_mutex);
785}
786
787int mlx5_register_interface(struct mlx5_interface *intf)
788{
789 struct mlx5_priv *priv;
790
791 if (!intf->add || !intf->remove)
792 return -EINVAL;
793
794 mutex_lock(&intf_mutex);
795 list_add_tail(&intf->list, &intf_list);
796 list_for_each_entry(priv, &dev_list, dev_list)
797 mlx5_add_device(intf, priv);
798 mutex_unlock(&intf_mutex);
799
800 return 0;
801}
802EXPORT_SYMBOL(mlx5_register_interface);
803
804void mlx5_unregister_interface(struct mlx5_interface *intf)
805{
806 struct mlx5_priv *priv;
807
808 mutex_lock(&intf_mutex);
809 list_for_each_entry(priv, &dev_list, dev_list)
810 mlx5_remove_device(intf, priv);
811 list_del(&intf->list);
812 mutex_unlock(&intf_mutex);
813}
814EXPORT_SYMBOL(mlx5_unregister_interface);
815
816void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
817{
818 struct mlx5_priv *priv = &mdev->priv;
819 struct mlx5_device_context *dev_ctx;
820 unsigned long flags;
821 void *result = NULL;
822
823 spin_lock_irqsave(&priv->ctx_lock, flags);
824
825 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
826 if ((dev_ctx->intf->protocol == protocol) &&
827 dev_ctx->intf->get_dev) {
828 result = dev_ctx->intf->get_dev(dev_ctx->context);
829 break;
830 }
831
832 spin_unlock_irqrestore(&priv->ctx_lock, flags);
833
834 return result;
835}
836EXPORT_SYMBOL(mlx5_get_protocol_dev);
837
838static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
839{
840 struct pci_dev *pdev = dev->pdev;
841 int err = 0;
e126ba97 842
e126ba97
EC		 843 pci_set_drvdata(dev->pdev, dev);
844 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
845 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
846
847 mutex_init(&priv->pgdir_mutex);
848 INIT_LIST_HEAD(&priv->pgdir_list);
849 spin_lock_init(&priv->mkey_lock);
850
311c7c71
SM		 851 mutex_init(&priv->alloc_mutex);
852
853 priv->numa_node = dev_to_node(&dev->pdev->dev);
854
e126ba97
EC		 855 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
856 if (!priv->dbg_root)
857 return -ENOMEM;
858
89d44f0a 859 err = mlx5_pci_enable_device(dev);
e126ba97 860 if (err) {
1a91de28 861 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 862 goto err_dbg;
863 }
864
865 err = request_bar(pdev);
866 if (err) {
1a91de28 867 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 868 goto err_disable;
869 }
870
871 pci_set_master(pdev);
872
873 err = set_dma_caps(pdev);
874 if (err) {
875 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
876 goto err_clr_master;
877 }
878
879 dev->iseg_base = pci_resource_start(dev->pdev, 0);
880 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
881 if (!dev->iseg) {
882 err = -ENOMEM;
883 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
884 goto err_clr_master;
885 }
a31208b1
MD		 886
887 return 0;
888
889err_clr_master:
890 pci_clear_master(dev->pdev);
891 release_bar(dev->pdev);
892err_disable:
89d44f0a 893 mlx5_pci_disable_device(dev);
a31208b1
MD		 894
895err_dbg:
896 debugfs_remove(priv->dbg_root);
897 return err;
898}
899
900static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
901{
902 iounmap(dev->iseg);
903 pci_clear_master(dev->pdev);
904 release_bar(dev->pdev);
89d44f0a 905 mlx5_pci_disable_device(dev);
a31208b1
MD		 906 debugfs_remove(priv->dbg_root);
907}
908
909#define MLX5_IB_MOD "mlx5_ib"
910static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
911{
912 struct pci_dev *pdev = dev->pdev;
913 int err;
914
89d44f0a
MD		 915 mutex_lock(&dev->intf_state_mutex);
916 if (dev->interface_state == MLX5_INTERFACE_STATE_UP) {
917 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
918 __func__);
919 goto out;
920 }
921
e126ba97
EC		 922 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
923 fw_rev_min(dev), fw_rev_sub(dev));
924
89d44f0a
MD		 925 /* on load removing any previous indication of internal error, device is
926 * up
927 */
928 dev->state = MLX5_DEVICE_STATE_UP;
929
e126ba97
EC		 930 err = mlx5_cmd_init(dev);
931 if (err) {
932 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
89d44f0a 933 goto out_err;
e126ba97
EC		 934 }
935
e3297246
EC		 936 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
937 if (err) {
938 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
939 FW_INIT_TIMEOUT_MILI);
940 goto out_err;
941 }
942
e126ba97 943 mlx5_pagealloc_init(dev);
cd23b14b
EC		 944
945 err = mlx5_core_enable_hca(dev);
946 if (err) {
947 dev_err(&pdev->dev, "enable hca failed\n");
948 goto err_pagealloc_cleanup;
949 }
950
f62b8bb8
AV		 951#ifdef CONFIG_MLX5_CORE_EN
952 err = mlx5_core_set_issi(dev);
953 if (err) {
954 dev_err(&pdev->dev, "failed to set issi\n");
955 goto err_disable_hca;
956 }
957#endif
958
cd23b14b
EC		 959 err = mlx5_satisfy_startup_pages(dev, 1);
960 if (err) {
961 dev_err(&pdev->dev, "failed to allocate boot pages\n");
962 goto err_disable_hca;
963 }
964
e126ba97
EC		 965 err = set_hca_ctrl(dev);
966 if (err) {
967 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 968 goto reclaim_boot_pages;
e126ba97
EC		 969 }
970
971 err = handle_hca_cap(dev);
972 if (err) {
973 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 974 goto reclaim_boot_pages;
e126ba97
EC		 975 }
976
cd23b14b 977 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 978 if (err) {
cd23b14b
EC		 979 dev_err(&pdev->dev, "failed to allocate init pages\n");
980 goto reclaim_boot_pages;
e126ba97
EC		 981 }
982
983 err = mlx5_pagealloc_start(dev);
984 if (err) {
985 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 986 goto reclaim_boot_pages;
e126ba97
EC		 987 }
988
989 err = mlx5_cmd_init_hca(dev);
990 if (err) {
991 dev_err(&pdev->dev, "init hca failed\n");
992 goto err_pagealloc_stop;
993 }
994
995 mlx5_start_health_poll(dev);
996
938fe83c 997 err = mlx5_query_hca_caps(dev);
e126ba97
EC		 998 if (err) {
999 dev_err(&pdev->dev, "query hca failed\n");
1000 goto err_stop_poll;
1001 }
1002
211e6c80 1003 err = mlx5_query_board_id(dev);
e126ba97 1004 if (err) {
211e6c80 1005 dev_err(&pdev->dev, "query board id failed\n");
e126ba97
EC		 1006 goto err_stop_poll;
1007 }
1008
1009 err = mlx5_enable_msix(dev);
1010 if (err) {
1011 dev_err(&pdev->dev, "enable msix failed\n");
1012 goto err_stop_poll;
1013 }
1014
1015 err = mlx5_eq_init(dev);
1016 if (err) {
1017 dev_err(&pdev->dev, "failed to initialize eq\n");
1018 goto disable_msix;
1019 }
1020
1021 err = mlx5_alloc_uuars(dev, &priv->uuari);
1022 if (err) {
1023 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1024 goto err_eq_cleanup;
1025 }
1026
1027 err = mlx5_start_eqs(dev);
1028 if (err) {
1029 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1030 goto err_free_uar;
1031 }
1032
233d05d2
SM		 1033 err = alloc_comp_eqs(dev);
1034 if (err) {
1035 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1036 goto err_stop_eqs;
1037 }
1038
88a85f99
AS		 1039 if (map_bf_area(dev))
1040 dev_err(&pdev->dev, "Failed to map blue flame area\n");
1041
db058a18
SM		 1042 err = mlx5_irq_set_affinity_hints(dev);
1043 if (err) {
1044 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
88a85f99 1045 goto err_unmap_bf_area;
db058a18
SM		 1046 }
1047
e126ba97
EC		 1048 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1049
1050 mlx5_init_cq_table(dev);
1051 mlx5_init_qp_table(dev);
1052 mlx5_init_srq_table(dev);
3bcdb17a 1053 mlx5_init_mr_table(dev);
e126ba97 1054
a31208b1
MD		 1055 err = mlx5_register_device(dev);
1056 if (err) {
1057 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1058 goto err_reg_dev;
1059 }
1060
1061 err = request_module_nowait(MLX5_IB_MOD);
1062 if (err)
1063 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1064
89d44f0a
MD		 1065 dev->interface_state = MLX5_INTERFACE_STATE_UP;
1066out:
1067 mutex_unlock(&dev->intf_state_mutex);
1068
e126ba97
EC		 1069 return 0;
1070
a31208b1
MD		 1071err_reg_dev:
1072 mlx5_cleanup_mr_table(dev);
1073 mlx5_cleanup_srq_table(dev);
1074 mlx5_cleanup_qp_table(dev);
1075 mlx5_cleanup_cq_table(dev);
1076 mlx5_irq_clear_affinity_hints(dev);
1077
88a85f99
AS		 1078err_unmap_bf_area:
1079 unmap_bf_area(dev);
1080
db058a18
SM		 1081 free_comp_eqs(dev);
1082
233d05d2
SM		 1083err_stop_eqs:
1084 mlx5_stop_eqs(dev);
1085
e126ba97
EC		 1086err_free_uar:
1087 mlx5_free_uuars(dev, &priv->uuari);
1088
1089err_eq_cleanup:
1090 mlx5_eq_cleanup(dev);
1091
1092disable_msix:
1093 mlx5_disable_msix(dev);
1094
1095err_stop_poll:
1096 mlx5_stop_health_poll(dev);
1bde6e30
EC		 1097 if (mlx5_cmd_teardown_hca(dev)) {
1098 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
89d44f0a 1099 goto out_err;
1bde6e30 1100 }
e126ba97
EC		 1101
1102err_pagealloc_stop:
1103 mlx5_pagealloc_stop(dev);
1104
cd23b14b 1105reclaim_boot_pages:
e126ba97
EC		 1106 mlx5_reclaim_startup_pages(dev);
1107
cd23b14b
EC		 1108err_disable_hca:
1109 mlx5_core_disable_hca(dev);
1110
e126ba97
EC		 1111err_pagealloc_cleanup:
1112 mlx5_pagealloc_cleanup(dev);
1113 mlx5_cmd_cleanup(dev);
1114
89d44f0a
MD		 1115out_err:
1116 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1117 mutex_unlock(&dev->intf_state_mutex);
1118
e126ba97
EC		 1119 return err;
1120}
e126ba97 1121
a31208b1 1122static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
e126ba97 1123{
89d44f0a 1124 int err = 0;
e126ba97 1125
89d44f0a
MD		 1126 mutex_lock(&dev->intf_state_mutex);
1127 if (dev->interface_state == MLX5_INTERFACE_STATE_DOWN) {
1128 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1129 __func__);
1130 goto out;
1131 }
a31208b1
MD		 1132 mlx5_unregister_device(dev);
1133 mlx5_cleanup_mr_table(dev);
e126ba97
EC		 1134 mlx5_cleanup_srq_table(dev);
1135 mlx5_cleanup_qp_table(dev);
1136 mlx5_cleanup_cq_table(dev);
db058a18 1137 mlx5_irq_clear_affinity_hints(dev);
88a85f99 1138 unmap_bf_area(dev);
233d05d2 1139 free_comp_eqs(dev);
e126ba97
EC		 1140 mlx5_stop_eqs(dev);
1141 mlx5_free_uuars(dev, &priv->uuari);
1142 mlx5_eq_cleanup(dev);
1143 mlx5_disable_msix(dev);
1144 mlx5_stop_health_poll(dev);
ac6ea6e8
EC		 1145 err = mlx5_cmd_teardown_hca(dev);
1146 if (err) {
1bde6e30 1147 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
ac6ea6e8 1148 goto out;
1bde6e30 1149 }
e126ba97
EC		 1150 mlx5_pagealloc_stop(dev);
1151 mlx5_reclaim_startup_pages(dev);
cd23b14b 1152 mlx5_core_disable_hca(dev);
e126ba97
EC		 1153 mlx5_pagealloc_cleanup(dev);
1154 mlx5_cmd_cleanup(dev);
9603b61d 1155
ac6ea6e8 1156out:
89d44f0a
MD		 1157 dev->interface_state = MLX5_INTERFACE_STATE_DOWN;
1158 mutex_unlock(&dev->intf_state_mutex);
ac6ea6e8 1159 return err;
9603b61d 1160}
64613d94 1161
89d44f0a 1162void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
ac6ea6e8 1163 unsigned long param)
9603b61d
JM		 1164{
1165 struct mlx5_priv *priv = &dev->priv;
1166 struct mlx5_device_context *dev_ctx;
1167 unsigned long flags;
1168
1169 spin_lock_irqsave(&priv->ctx_lock, flags);
1170
1171 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1172 if (dev_ctx->intf->event)
4d2f9bbb 1173 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
9603b61d
JM		 1174
1175 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1176}
1177
1178struct mlx5_core_event_handler {
1179 void (*event)(struct mlx5_core_dev *dev,
1180 enum mlx5_dev_event event,
1181 void *data);
1182};
1183
f66f049f 1184
9603b61d
JM		 1185static int init_one(struct pci_dev *pdev,
1186 const struct pci_device_id *id)
1187{
1188 struct mlx5_core_dev *dev;
1189 struct mlx5_priv *priv;
1190 int err;
1191
1192 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1193 if (!dev) {
1194 dev_err(&pdev->dev, "kzalloc failed\n");
1195 return -ENOMEM;
1196 }
1197 priv = &dev->priv;
1198
1199 pci_set_drvdata(pdev, dev);
1200
1201 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1202 pr_warn("selected profile out of range, selecting default (%d)\n",
1203 MLX5_DEFAULT_PROF);
1204 prof_sel = MLX5_DEFAULT_PROF;
1205 }
1206 dev->profile = &profile[prof_sel];
a31208b1 1207 dev->pdev = pdev;
9603b61d
JM		 1208 dev->event = mlx5_core_event;
1209
364d1798
EC		 1210 INIT_LIST_HEAD(&priv->ctx_list);
1211 spin_lock_init(&priv->ctx_lock);
89d44f0a
MD		 1212 mutex_init(&dev->pci_status_mutex);
1213 mutex_init(&dev->intf_state_mutex);
a31208b1 1214 err = mlx5_pci_init(dev, priv);
9603b61d 1215 if (err) {
a31208b1
MD		 1216 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1217 goto clean_dev;
9603b61d
JM		 1218 }
1219
ac6ea6e8
EC		 1220 err = mlx5_health_init(dev);
1221 if (err) {
1222 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1223 goto close_pci;
1224 }
1225
a31208b1 1226 err = mlx5_load_one(dev, priv);
9603b61d 1227 if (err) {
a31208b1 1228 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
ac6ea6e8 1229 goto clean_health;
9603b61d
JM		 1230 }
1231
1232 return 0;
1233
ac6ea6e8
EC		 1234clean_health:
1235 mlx5_health_cleanup(dev);
a31208b1
MD		 1236close_pci:
1237 mlx5_pci_close(dev, priv);
1238clean_dev:
1239 pci_set_drvdata(pdev, NULL);
9603b61d 1240 kfree(dev);
a31208b1 1241
9603b61d
JM		 1242 return err;
1243}
a31208b1 1244
9603b61d
JM		 1245static void remove_one(struct pci_dev *pdev)
1246{
1247 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
a31208b1 1248 struct mlx5_priv *priv = &dev->priv;
9603b61d 1249
a31208b1
MD		 1250 if (mlx5_unload_one(dev, priv)) {
1251 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
ac6ea6e8 1252 mlx5_health_cleanup(dev);
a31208b1
MD		 1253 return;
1254 }
ac6ea6e8 1255 mlx5_health_cleanup(dev);
a31208b1
MD		 1256 mlx5_pci_close(dev, priv);
1257 pci_set_drvdata(pdev, NULL);
9603b61d
JM		 1258 kfree(dev);
1259}
1260
89d44f0a
MD		 1261static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1262 pci_channel_state_t state)
1263{
1264 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1265 struct mlx5_priv *priv = &dev->priv;
1266
1267 dev_info(&pdev->dev, "%s was called\n", __func__);
1268 mlx5_enter_error_state(dev);
1269 mlx5_unload_one(dev, priv);
1270 mlx5_pci_disable_device(dev);
1271 return state == pci_channel_io_perm_failure ?
1272 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1273}
1274
1275static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1276{
1277 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1278 int err = 0;
1279
1280 dev_info(&pdev->dev, "%s was called\n", __func__);
1281
1282 err = mlx5_pci_enable_device(dev);
1283 if (err) {
1284 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1285 , __func__, err);
1286 return PCI_ERS_RESULT_DISCONNECT;
1287 }
1288 pci_set_master(pdev);
1289 pci_set_power_state(pdev, PCI_D0);
1290 pci_restore_state(pdev);
1291
1292 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1293}
1294
1295void mlx5_disable_device(struct mlx5_core_dev *dev)
1296{
1297 mlx5_pci_err_detected(dev->pdev, 0);
1298}
1299
1300/* wait for the device to show vital signs. For now we check
1301 * that we can read the device ID and that the health buffer
1302 * shows a non zero value which is different than 0xffffffff
1303 */
1304static void wait_vital(struct pci_dev *pdev)
1305{
1306 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1307 struct mlx5_core_health *health = &dev->priv.health;
1308 const int niter = 100;
1309 u32 count;
1310 u16 did;
1311 int i;
1312
1313 /* Wait for firmware to be ready after reset */
1314 msleep(1000);
1315 for (i = 0; i < niter; i++) {
1316 if (pci_read_config_word(pdev, 2, &did)) {
1317 dev_warn(&pdev->dev, "failed reading config word\n");
1318 break;
1319 }
1320 if (did == pdev->device) {
1321 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
1322 break;
1323 }
1324 msleep(50);
1325 }
1326 if (i == niter)
1327 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1328
1329 for (i = 0; i < niter; i++) {
1330 count = ioread32be(health->health_counter);
1331 if (count && count != 0xffffffff) {
1332 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1333 break;
1334 }
1335 msleep(50);
1336 }
1337
1338 if (i == niter)
1339 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1340}
1341
1342static void mlx5_pci_resume(struct pci_dev *pdev)
1343{
1344 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1345 struct mlx5_priv *priv = &dev->priv;
1346 int err;
1347
1348 dev_info(&pdev->dev, "%s was called\n", __func__);
1349
1350 pci_save_state(pdev);
1351 wait_vital(pdev);
1352
1353 err = mlx5_load_one(dev, priv);
1354 if (err)
1355 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1356 , __func__, err);
1357 else
1358 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1359}
1360
1361static const struct pci_error_handlers mlx5_err_handler = {
1362 .error_detected = mlx5_pci_err_detected,
1363 .slot_reset = mlx5_pci_slot_reset,
1364 .resume = mlx5_pci_resume
1365};
1366
9603b61d 1367static const struct pci_device_id mlx5_core_pci_table[] = {
1c755cc5
OG		 1368 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1369 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1370 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1371 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1372 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1373 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
9603b61d
JM		 1374 { 0, }
1375};
1376
1377MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1378
1379static struct pci_driver mlx5_core_driver = {
1380 .name = DRIVER_NAME,
1381 .id_table = mlx5_core_pci_table,
1382 .probe = init_one,
89d44f0a
MD		 1383 .remove = remove_one,
1384 .err_handler = &mlx5_err_handler
9603b61d 1385};
e126ba97
EC		 1386
1387static int __init init(void)
1388{
1389 int err;
1390
1391 mlx5_register_debugfs();
e126ba97 1392
9603b61d
JM		 1393 err = pci_register_driver(&mlx5_core_driver);
1394 if (err)
ac6ea6e8 1395 goto err_debug;
9603b61d 1396
f62b8bb8
AV		 1397#ifdef CONFIG_MLX5_CORE_EN
1398 mlx5e_init();
1399#endif
1400
e126ba97
EC		 1401 return 0;
1402
e126ba97
EC		 1403err_debug:
1404 mlx5_unregister_debugfs();
1405 return err;
1406}
1407
1408static void __exit cleanup(void)
1409{
f62b8bb8
AV		 1410#ifdef CONFIG_MLX5_CORE_EN
1411 mlx5e_cleanup();
1412#endif
9603b61d 1413 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1414 mlx5_unregister_debugfs();
1415}
1416
1417module_init(init);
1418module_exit(cleanup);
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