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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
adec640e | 33 | #include <linux/highmem.h> |
e126ba97 EC |
34 | #include <linux/module.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/io-mapping.h> | |
db058a18 | 41 | #include <linux/interrupt.h> |
e3297246 | 42 | #include <linux/delay.h> |
e126ba97 EC |
43 | #include <linux/mlx5/driver.h> |
44 | #include <linux/mlx5/cq.h> | |
45 | #include <linux/mlx5/qp.h> | |
46 | #include <linux/mlx5/srq.h> | |
47 | #include <linux/debugfs.h> | |
f66f049f | 48 | #include <linux/kmod.h> |
89d44f0a | 49 | #include <linux/delay.h> |
b775516b | 50 | #include <linux/mlx5/mlx5_ifc.h> |
5a7b27eb MG |
51 | #ifdef CONFIG_RFS_ACCEL |
52 | #include <linux/cpu_rmap.h> | |
53 | #endif | |
feae9087 | 54 | #include <net/devlink.h> |
e126ba97 | 55 | #include "mlx5_core.h" |
86d722ad | 56 | #include "fs_core.h" |
073bb189 SM |
57 | #ifdef CONFIG_MLX5_CORE_EN |
58 | #include "eswitch.h" | |
59 | #endif | |
e126ba97 | 60 | |
e126ba97 | 61 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); |
4ae6c18c | 62 | MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); |
e126ba97 EC |
63 | MODULE_LICENSE("Dual BSD/GPL"); |
64 | MODULE_VERSION(DRIVER_VERSION); | |
65 | ||
66 | int mlx5_core_debug_mask; | |
67 | module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644); | |
68 | MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); | |
69 | ||
9603b61d JM |
70 | #define MLX5_DEFAULT_PROF 2 |
71 | static int prof_sel = MLX5_DEFAULT_PROF; | |
72 | module_param_named(prof_sel, prof_sel, int, 0444); | |
73 | MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); | |
74 | ||
9603b61d | 75 | static LIST_HEAD(intf_list); |
7907f23a AH |
76 | |
77 | LIST_HEAD(mlx5_dev_list); | |
78 | DEFINE_MUTEX(mlx5_intf_mutex); | |
9603b61d JM |
79 | |
80 | struct mlx5_device_context { | |
81 | struct list_head list; | |
82 | struct mlx5_interface *intf; | |
83 | void *context; | |
84 | }; | |
85 | ||
f91e6d89 EBE |
86 | enum { |
87 | MLX5_ATOMIC_REQ_MODE_BE = 0x0, | |
88 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, | |
89 | }; | |
90 | ||
9603b61d JM |
91 | static struct mlx5_profile profile[] = { |
92 | [0] = { | |
93 | .mask = 0, | |
94 | }, | |
95 | [1] = { | |
96 | .mask = MLX5_PROF_MASK_QP_SIZE, | |
97 | .log_max_qp = 12, | |
98 | }, | |
99 | [2] = { | |
100 | .mask = MLX5_PROF_MASK_QP_SIZE | | |
101 | MLX5_PROF_MASK_MR_CACHE, | |
102 | .log_max_qp = 17, | |
103 | .mr_cache[0] = { | |
104 | .size = 500, | |
105 | .limit = 250 | |
106 | }, | |
107 | .mr_cache[1] = { | |
108 | .size = 500, | |
109 | .limit = 250 | |
110 | }, | |
111 | .mr_cache[2] = { | |
112 | .size = 500, | |
113 | .limit = 250 | |
114 | }, | |
115 | .mr_cache[3] = { | |
116 | .size = 500, | |
117 | .limit = 250 | |
118 | }, | |
119 | .mr_cache[4] = { | |
120 | .size = 500, | |
121 | .limit = 250 | |
122 | }, | |
123 | .mr_cache[5] = { | |
124 | .size = 500, | |
125 | .limit = 250 | |
126 | }, | |
127 | .mr_cache[6] = { | |
128 | .size = 500, | |
129 | .limit = 250 | |
130 | }, | |
131 | .mr_cache[7] = { | |
132 | .size = 500, | |
133 | .limit = 250 | |
134 | }, | |
135 | .mr_cache[8] = { | |
136 | .size = 500, | |
137 | .limit = 250 | |
138 | }, | |
139 | .mr_cache[9] = { | |
140 | .size = 500, | |
141 | .limit = 250 | |
142 | }, | |
143 | .mr_cache[10] = { | |
144 | .size = 500, | |
145 | .limit = 250 | |
146 | }, | |
147 | .mr_cache[11] = { | |
148 | .size = 500, | |
149 | .limit = 250 | |
150 | }, | |
151 | .mr_cache[12] = { | |
152 | .size = 64, | |
153 | .limit = 32 | |
154 | }, | |
155 | .mr_cache[13] = { | |
156 | .size = 32, | |
157 | .limit = 16 | |
158 | }, | |
159 | .mr_cache[14] = { | |
160 | .size = 16, | |
161 | .limit = 8 | |
162 | }, | |
163 | .mr_cache[15] = { | |
164 | .size = 8, | |
165 | .limit = 4 | |
166 | }, | |
167 | }, | |
168 | }; | |
e126ba97 | 169 | |
e3297246 EC |
170 | #define FW_INIT_TIMEOUT_MILI 2000 |
171 | #define FW_INIT_WAIT_MS 2 | |
172 | ||
173 | static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) | |
174 | { | |
175 | unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); | |
176 | int err = 0; | |
177 | ||
178 | while (fw_initializing(dev)) { | |
179 | if (time_after(jiffies, end)) { | |
180 | err = -EBUSY; | |
181 | break; | |
182 | } | |
183 | msleep(FW_INIT_WAIT_MS); | |
184 | } | |
185 | ||
186 | return err; | |
187 | } | |
188 | ||
e126ba97 EC |
189 | static int set_dma_caps(struct pci_dev *pdev) |
190 | { | |
191 | int err; | |
192 | ||
193 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
194 | if (err) { | |
1a91de28 | 195 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); |
e126ba97 EC |
196 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
197 | if (err) { | |
1a91de28 | 198 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); |
e126ba97 EC |
199 | return err; |
200 | } | |
201 | } | |
202 | ||
203 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
204 | if (err) { | |
205 | dev_warn(&pdev->dev, | |
1a91de28 | 206 | "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); |
e126ba97 EC |
207 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
208 | if (err) { | |
209 | dev_err(&pdev->dev, | |
1a91de28 | 210 | "Can't set consistent PCI DMA mask, aborting\n"); |
e126ba97 EC |
211 | return err; |
212 | } | |
213 | } | |
214 | ||
215 | dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); | |
216 | return err; | |
217 | } | |
218 | ||
89d44f0a MD |
219 | static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) |
220 | { | |
221 | struct pci_dev *pdev = dev->pdev; | |
222 | int err = 0; | |
223 | ||
224 | mutex_lock(&dev->pci_status_mutex); | |
225 | if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { | |
226 | err = pci_enable_device(pdev); | |
227 | if (!err) | |
228 | dev->pci_status = MLX5_PCI_STATUS_ENABLED; | |
229 | } | |
230 | mutex_unlock(&dev->pci_status_mutex); | |
231 | ||
232 | return err; | |
233 | } | |
234 | ||
235 | static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) | |
236 | { | |
237 | struct pci_dev *pdev = dev->pdev; | |
238 | ||
239 | mutex_lock(&dev->pci_status_mutex); | |
240 | if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { | |
241 | pci_disable_device(pdev); | |
242 | dev->pci_status = MLX5_PCI_STATUS_DISABLED; | |
243 | } | |
244 | mutex_unlock(&dev->pci_status_mutex); | |
245 | } | |
246 | ||
e126ba97 EC |
247 | static int request_bar(struct pci_dev *pdev) |
248 | { | |
249 | int err = 0; | |
250 | ||
251 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
1a91de28 | 252 | dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); |
e126ba97 EC |
253 | return -ENODEV; |
254 | } | |
255 | ||
256 | err = pci_request_regions(pdev, DRIVER_NAME); | |
257 | if (err) | |
258 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); | |
259 | ||
260 | return err; | |
261 | } | |
262 | ||
263 | static void release_bar(struct pci_dev *pdev) | |
264 | { | |
265 | pci_release_regions(pdev); | |
266 | } | |
267 | ||
268 | static int mlx5_enable_msix(struct mlx5_core_dev *dev) | |
269 | { | |
db058a18 SM |
270 | struct mlx5_priv *priv = &dev->priv; |
271 | struct mlx5_eq_table *table = &priv->eq_table; | |
938fe83c | 272 | int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); |
e126ba97 | 273 | int nvec; |
e126ba97 EC |
274 | int i; |
275 | ||
938fe83c SM |
276 | nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() + |
277 | MLX5_EQ_VEC_COMP_BASE; | |
e126ba97 EC |
278 | nvec = min_t(int, nvec, num_eqs); |
279 | if (nvec <= MLX5_EQ_VEC_COMP_BASE) | |
280 | return -ENOMEM; | |
281 | ||
db058a18 SM |
282 | priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL); |
283 | ||
284 | priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL); | |
285 | if (!priv->msix_arr || !priv->irq_info) | |
286 | goto err_free_msix; | |
e126ba97 EC |
287 | |
288 | for (i = 0; i < nvec; i++) | |
db058a18 | 289 | priv->msix_arr[i].entry = i; |
e126ba97 | 290 | |
db058a18 | 291 | nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, |
3a9e161a | 292 | MLX5_EQ_VEC_COMP_BASE + 1, nvec); |
f3c9407b AG |
293 | if (nvec < 0) |
294 | return nvec; | |
e126ba97 | 295 | |
f3c9407b | 296 | table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; |
e126ba97 EC |
297 | |
298 | return 0; | |
db058a18 SM |
299 | |
300 | err_free_msix: | |
301 | kfree(priv->irq_info); | |
302 | kfree(priv->msix_arr); | |
303 | return -ENOMEM; | |
e126ba97 EC |
304 | } |
305 | ||
306 | static void mlx5_disable_msix(struct mlx5_core_dev *dev) | |
307 | { | |
db058a18 | 308 | struct mlx5_priv *priv = &dev->priv; |
e126ba97 EC |
309 | |
310 | pci_disable_msix(dev->pdev); | |
db058a18 SM |
311 | kfree(priv->irq_info); |
312 | kfree(priv->msix_arr); | |
e126ba97 EC |
313 | } |
314 | ||
315 | struct mlx5_reg_host_endianess { | |
316 | u8 he; | |
317 | u8 rsvd[15]; | |
318 | }; | |
319 | ||
87b8de49 EC |
320 | |
321 | #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) | |
322 | ||
323 | enum { | |
c7a08ac7 EC |
324 | MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | |
325 | MLX5_DEV_CAP_FLAG_DCT, | |
87b8de49 EC |
326 | }; |
327 | ||
2974ab6e | 328 | static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) |
c7a08ac7 EC |
329 | { |
330 | switch (size) { | |
331 | case 128: | |
332 | return 0; | |
333 | case 256: | |
334 | return 1; | |
335 | case 512: | |
336 | return 2; | |
337 | case 1024: | |
338 | return 3; | |
339 | case 2048: | |
340 | return 4; | |
341 | case 4096: | |
342 | return 5; | |
343 | default: | |
2974ab6e | 344 | mlx5_core_warn(dev, "invalid pkey table size %d\n", size); |
c7a08ac7 EC |
345 | return 0; |
346 | } | |
347 | } | |
348 | ||
b06e7de8 LR |
349 | static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, |
350 | enum mlx5_cap_type cap_type, | |
351 | enum mlx5_cap_mode cap_mode) | |
c7a08ac7 | 352 | { |
b775516b EC |
353 | u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; |
354 | int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); | |
938fe83c SM |
355 | void *out, *hca_caps; |
356 | u16 opmod = (cap_type << 1) | (cap_mode & 0x01); | |
e126ba97 EC |
357 | int err; |
358 | ||
b775516b EC |
359 | memset(in, 0, sizeof(in)); |
360 | out = kzalloc(out_sz, GFP_KERNEL); | |
c7a08ac7 | 361 | if (!out) |
e126ba97 | 362 | return -ENOMEM; |
938fe83c | 363 | |
b775516b EC |
364 | MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); |
365 | MLX5_SET(query_hca_cap_in, in, op_mod, opmod); | |
366 | err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); | |
c7a08ac7 | 367 | if (err) { |
938fe83c SM |
368 | mlx5_core_warn(dev, |
369 | "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", | |
370 | cap_type, cap_mode, err); | |
e126ba97 EC |
371 | goto query_ex; |
372 | } | |
c7a08ac7 | 373 | |
938fe83c SM |
374 | hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); |
375 | ||
376 | switch (cap_mode) { | |
377 | case HCA_CAP_OPMOD_GET_MAX: | |
378 | memcpy(dev->hca_caps_max[cap_type], hca_caps, | |
379 | MLX5_UN_SZ_BYTES(hca_cap_union)); | |
380 | break; | |
381 | case HCA_CAP_OPMOD_GET_CUR: | |
382 | memcpy(dev->hca_caps_cur[cap_type], hca_caps, | |
383 | MLX5_UN_SZ_BYTES(hca_cap_union)); | |
384 | break; | |
385 | default: | |
386 | mlx5_core_warn(dev, | |
387 | "Tried to query dev cap type(%x) with wrong opmode(%x)\n", | |
388 | cap_type, cap_mode); | |
389 | err = -EINVAL; | |
390 | break; | |
391 | } | |
c7a08ac7 EC |
392 | query_ex: |
393 | kfree(out); | |
394 | return err; | |
395 | } | |
396 | ||
b06e7de8 LR |
397 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) |
398 | { | |
399 | int ret; | |
400 | ||
401 | ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); | |
402 | if (ret) | |
403 | return ret; | |
404 | return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); | |
405 | } | |
406 | ||
f91e6d89 | 407 | static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) |
c7a08ac7 | 408 | { |
c4f287c4 | 409 | u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; |
e126ba97 | 410 | |
b775516b | 411 | MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); |
f91e6d89 | 412 | MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); |
c4f287c4 | 413 | return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); |
c7a08ac7 EC |
414 | } |
415 | ||
f91e6d89 EBE |
416 | static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) |
417 | { | |
418 | void *set_ctx; | |
419 | void *set_hca_cap; | |
420 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); | |
421 | int req_endianness; | |
422 | int err; | |
423 | ||
424 | if (MLX5_CAP_GEN(dev, atomic)) { | |
b06e7de8 | 425 | err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); |
f91e6d89 EBE |
426 | if (err) |
427 | return err; | |
428 | } else { | |
429 | return 0; | |
430 | } | |
431 | ||
432 | req_endianness = | |
433 | MLX5_CAP_ATOMIC(dev, | |
434 | supported_atomic_req_8B_endianess_mode_1); | |
435 | ||
436 | if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) | |
437 | return 0; | |
438 | ||
439 | set_ctx = kzalloc(set_sz, GFP_KERNEL); | |
440 | if (!set_ctx) | |
441 | return -ENOMEM; | |
442 | ||
443 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); | |
444 | ||
445 | /* Set requestor to host endianness */ | |
446 | MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode, | |
447 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); | |
448 | ||
449 | err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); | |
450 | ||
451 | kfree(set_ctx); | |
452 | return err; | |
453 | } | |
454 | ||
c7a08ac7 EC |
455 | static int handle_hca_cap(struct mlx5_core_dev *dev) |
456 | { | |
b775516b | 457 | void *set_ctx = NULL; |
c7a08ac7 | 458 | struct mlx5_profile *prof = dev->profile; |
c7a08ac7 | 459 | int err = -ENOMEM; |
b775516b | 460 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
938fe83c | 461 | void *set_hca_cap; |
c7a08ac7 | 462 | |
b775516b | 463 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
c7a08ac7 | 464 | if (!set_ctx) |
e126ba97 | 465 | goto query_ex; |
e126ba97 | 466 | |
b06e7de8 | 467 | err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); |
e126ba97 EC |
468 | if (err) |
469 | goto query_ex; | |
470 | ||
938fe83c SM |
471 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, |
472 | capability); | |
473 | memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL], | |
474 | MLX5_ST_SZ_BYTES(cmd_hca_cap)); | |
475 | ||
476 | mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", | |
707c4602 | 477 | mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), |
938fe83c | 478 | 128); |
c7a08ac7 | 479 | /* we limit the size of the pkey table to 128 entries for now */ |
938fe83c | 480 | MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, |
2974ab6e | 481 | to_fw_pkey_sz(dev, 128)); |
c7a08ac7 EC |
482 | |
483 | if (prof->mask & MLX5_PROF_MASK_QP_SIZE) | |
938fe83c SM |
484 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, |
485 | prof->log_max_qp); | |
c7a08ac7 | 486 | |
938fe83c SM |
487 | /* disable cmdif checksum */ |
488 | MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); | |
c7a08ac7 | 489 | |
fe1e1876 CS |
490 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); |
491 | ||
f91e6d89 EBE |
492 | err = set_caps(dev, set_ctx, set_sz, |
493 | MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); | |
c7a08ac7 | 494 | |
e126ba97 | 495 | query_ex: |
e126ba97 | 496 | kfree(set_ctx); |
e126ba97 EC |
497 | return err; |
498 | } | |
499 | ||
500 | static int set_hca_ctrl(struct mlx5_core_dev *dev) | |
501 | { | |
502 | struct mlx5_reg_host_endianess he_in; | |
503 | struct mlx5_reg_host_endianess he_out; | |
504 | int err; | |
505 | ||
fc50db98 EC |
506 | if (!mlx5_core_is_pf(dev)) |
507 | return 0; | |
508 | ||
e126ba97 EC |
509 | memset(&he_in, 0, sizeof(he_in)); |
510 | he_in.he = MLX5_SET_HOST_ENDIANNESS; | |
511 | err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), | |
512 | &he_out, sizeof(he_out), | |
513 | MLX5_REG_HOST_ENDIANNESS, 0, 1); | |
514 | return err; | |
515 | } | |
516 | ||
0b107106 | 517 | int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 518 | { |
c4f287c4 SM |
519 | u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; |
520 | u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; | |
cd23b14b | 521 | |
0b107106 EC |
522 | MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); |
523 | MLX5_SET(enable_hca_in, in, function_id, func_id); | |
c4f287c4 | 524 | return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); |
cd23b14b EC |
525 | } |
526 | ||
0b107106 | 527 | int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 528 | { |
c4f287c4 SM |
529 | u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; |
530 | u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; | |
cd23b14b | 531 | |
0b107106 EC |
532 | MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); |
533 | MLX5_SET(disable_hca_in, in, function_id, func_id); | |
c4f287c4 | 534 | return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); |
cd23b14b EC |
535 | } |
536 | ||
b0844444 EBE |
537 | cycle_t mlx5_read_internal_timer(struct mlx5_core_dev *dev) |
538 | { | |
539 | u32 timer_h, timer_h1, timer_l; | |
540 | ||
541 | timer_h = ioread32be(&dev->iseg->internal_timer_h); | |
542 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
543 | timer_h1 = ioread32be(&dev->iseg->internal_timer_h); | |
544 | if (timer_h != timer_h1) /* wrap around */ | |
545 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
546 | ||
547 | return (cycle_t)timer_l | (cycle_t)timer_h1 << 32; | |
548 | } | |
549 | ||
db058a18 SM |
550 | static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i) |
551 | { | |
552 | struct mlx5_priv *priv = &mdev->priv; | |
553 | struct msix_entry *msix = priv->msix_arr; | |
554 | int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector; | |
311c7c71 | 555 | int numa_node = priv->numa_node; |
db058a18 SM |
556 | int err; |
557 | ||
558 | if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) { | |
559 | mlx5_core_warn(mdev, "zalloc_cpumask_var failed"); | |
560 | return -ENOMEM; | |
561 | } | |
562 | ||
dda922c8 DM |
563 | cpumask_set_cpu(cpumask_local_spread(i, numa_node), |
564 | priv->irq_info[i].mask); | |
db058a18 SM |
565 | |
566 | err = irq_set_affinity_hint(irq, priv->irq_info[i].mask); | |
567 | if (err) { | |
568 | mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x", | |
569 | irq); | |
570 | goto err_clear_mask; | |
571 | } | |
572 | ||
573 | return 0; | |
574 | ||
575 | err_clear_mask: | |
576 | free_cpumask_var(priv->irq_info[i].mask); | |
577 | return err; | |
578 | } | |
579 | ||
580 | static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i) | |
581 | { | |
582 | struct mlx5_priv *priv = &mdev->priv; | |
583 | struct msix_entry *msix = priv->msix_arr; | |
584 | int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector; | |
585 | ||
586 | irq_set_affinity_hint(irq, NULL); | |
587 | free_cpumask_var(priv->irq_info[i].mask); | |
588 | } | |
589 | ||
590 | static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev) | |
591 | { | |
592 | int err; | |
593 | int i; | |
594 | ||
595 | for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) { | |
596 | err = mlx5_irq_set_affinity_hint(mdev, i); | |
597 | if (err) | |
598 | goto err_out; | |
599 | } | |
600 | ||
601 | return 0; | |
602 | ||
603 | err_out: | |
604 | for (i--; i >= 0; i--) | |
605 | mlx5_irq_clear_affinity_hint(mdev, i); | |
606 | ||
607 | return err; | |
608 | } | |
609 | ||
610 | static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev) | |
611 | { | |
612 | int i; | |
613 | ||
614 | for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) | |
615 | mlx5_irq_clear_affinity_hint(mdev, i); | |
616 | } | |
617 | ||
0b6e26ce DT |
618 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
619 | unsigned int *irqn) | |
233d05d2 SM |
620 | { |
621 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
622 | struct mlx5_eq *eq, *n; | |
623 | int err = -ENOENT; | |
624 | ||
625 | spin_lock(&table->lock); | |
626 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
627 | if (eq->index == vector) { | |
628 | *eqn = eq->eqn; | |
629 | *irqn = eq->irqn; | |
630 | err = 0; | |
631 | break; | |
632 | } | |
633 | } | |
634 | spin_unlock(&table->lock); | |
635 | ||
636 | return err; | |
637 | } | |
638 | EXPORT_SYMBOL(mlx5_vector2eqn); | |
639 | ||
94c6825e MB |
640 | struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn) |
641 | { | |
642 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
643 | struct mlx5_eq *eq; | |
644 | ||
645 | spin_lock(&table->lock); | |
646 | list_for_each_entry(eq, &table->comp_eqs_list, list) | |
647 | if (eq->eqn == eqn) { | |
648 | spin_unlock(&table->lock); | |
649 | return eq; | |
650 | } | |
651 | ||
652 | spin_unlock(&table->lock); | |
653 | ||
654 | return ERR_PTR(-ENOENT); | |
655 | } | |
656 | ||
233d05d2 SM |
657 | static void free_comp_eqs(struct mlx5_core_dev *dev) |
658 | { | |
659 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
660 | struct mlx5_eq *eq, *n; | |
661 | ||
5a7b27eb MG |
662 | #ifdef CONFIG_RFS_ACCEL |
663 | if (dev->rmap) { | |
664 | free_irq_cpu_rmap(dev->rmap); | |
665 | dev->rmap = NULL; | |
666 | } | |
667 | #endif | |
233d05d2 SM |
668 | spin_lock(&table->lock); |
669 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
670 | list_del(&eq->list); | |
671 | spin_unlock(&table->lock); | |
672 | if (mlx5_destroy_unmap_eq(dev, eq)) | |
673 | mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", | |
674 | eq->eqn); | |
675 | kfree(eq); | |
676 | spin_lock(&table->lock); | |
677 | } | |
678 | spin_unlock(&table->lock); | |
679 | } | |
680 | ||
681 | static int alloc_comp_eqs(struct mlx5_core_dev *dev) | |
682 | { | |
683 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
db058a18 | 684 | char name[MLX5_MAX_IRQ_NAME]; |
233d05d2 SM |
685 | struct mlx5_eq *eq; |
686 | int ncomp_vec; | |
687 | int nent; | |
688 | int err; | |
689 | int i; | |
690 | ||
691 | INIT_LIST_HEAD(&table->comp_eqs_list); | |
692 | ncomp_vec = table->num_comp_vectors; | |
693 | nent = MLX5_COMP_EQ_SIZE; | |
5a7b27eb MG |
694 | #ifdef CONFIG_RFS_ACCEL |
695 | dev->rmap = alloc_irq_cpu_rmap(ncomp_vec); | |
696 | if (!dev->rmap) | |
697 | return -ENOMEM; | |
698 | #endif | |
233d05d2 SM |
699 | for (i = 0; i < ncomp_vec; i++) { |
700 | eq = kzalloc(sizeof(*eq), GFP_KERNEL); | |
701 | if (!eq) { | |
702 | err = -ENOMEM; | |
703 | goto clean; | |
704 | } | |
705 | ||
5a7b27eb MG |
706 | #ifdef CONFIG_RFS_ACCEL |
707 | irq_cpu_rmap_add(dev->rmap, | |
708 | dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector); | |
709 | #endif | |
db058a18 | 710 | snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); |
233d05d2 SM |
711 | err = mlx5_create_map_eq(dev, eq, |
712 | i + MLX5_EQ_VEC_COMP_BASE, nent, 0, | |
713 | name, &dev->priv.uuari.uars[0]); | |
714 | if (err) { | |
715 | kfree(eq); | |
716 | goto clean; | |
717 | } | |
718 | mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); | |
719 | eq->index = i; | |
720 | spin_lock(&table->lock); | |
721 | list_add_tail(&eq->list, &table->comp_eqs_list); | |
722 | spin_unlock(&table->lock); | |
723 | } | |
724 | ||
725 | return 0; | |
726 | ||
727 | clean: | |
728 | free_comp_eqs(dev); | |
729 | return err; | |
730 | } | |
731 | ||
f62b8bb8 AV |
732 | static int mlx5_core_set_issi(struct mlx5_core_dev *dev) |
733 | { | |
c4f287c4 SM |
734 | u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; |
735 | u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; | |
f62b8bb8 | 736 | u32 sup_issi; |
c4f287c4 | 737 | int err; |
f62b8bb8 AV |
738 | |
739 | MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); | |
c4f287c4 SM |
740 | err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), |
741 | query_out, sizeof(query_out)); | |
f62b8bb8 | 742 | if (err) { |
c4f287c4 SM |
743 | u32 syndrome; |
744 | u8 status; | |
745 | ||
746 | mlx5_cmd_mbox_status(query_out, &status, &syndrome); | |
747 | if (status == MLX5_CMD_STAT_BAD_OP_ERR) { | |
f62b8bb8 AV |
748 | pr_debug("Only ISSI 0 is supported\n"); |
749 | return 0; | |
750 | } | |
751 | ||
c4f287c4 | 752 | pr_err("failed to query ISSI err(%d)\n", err); |
f62b8bb8 AV |
753 | return err; |
754 | } | |
755 | ||
756 | sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); | |
757 | ||
758 | if (sup_issi & (1 << 1)) { | |
c4f287c4 SM |
759 | u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; |
760 | u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; | |
f62b8bb8 AV |
761 | |
762 | MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); | |
763 | MLX5_SET(set_issi_in, set_in, current_issi, 1); | |
c4f287c4 SM |
764 | err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), |
765 | set_out, sizeof(set_out)); | |
f62b8bb8 | 766 | if (err) { |
c4f287c4 | 767 | pr_err("failed to set ISSI=1 err(%d)\n", err); |
f62b8bb8 AV |
768 | return err; |
769 | } | |
770 | ||
771 | dev->issi = 1; | |
772 | ||
773 | return 0; | |
e74a1db0 | 774 | } else if (sup_issi & (1 << 0) || !sup_issi) { |
f62b8bb8 AV |
775 | return 0; |
776 | } | |
777 | ||
778 | return -ENOTSUPP; | |
779 | } | |
f62b8bb8 | 780 | |
a31208b1 MD |
781 | static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv) |
782 | { | |
783 | struct mlx5_device_context *dev_ctx; | |
784 | struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); | |
785 | ||
917b41aa AH |
786 | if (!mlx5_lag_intf_add(intf, priv)) |
787 | return; | |
788 | ||
a31208b1 MD |
789 | dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL); |
790 | if (!dev_ctx) | |
791 | return; | |
792 | ||
793 | dev_ctx->intf = intf; | |
794 | dev_ctx->context = intf->add(dev); | |
795 | ||
796 | if (dev_ctx->context) { | |
797 | spin_lock_irq(&priv->ctx_lock); | |
798 | list_add_tail(&dev_ctx->list, &priv->ctx_list); | |
799 | spin_unlock_irq(&priv->ctx_lock); | |
800 | } else { | |
801 | kfree(dev_ctx); | |
802 | } | |
803 | } | |
804 | ||
805 | static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv) | |
806 | { | |
807 | struct mlx5_device_context *dev_ctx; | |
808 | struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); | |
809 | ||
810 | list_for_each_entry(dev_ctx, &priv->ctx_list, list) | |
811 | if (dev_ctx->intf == intf) { | |
812 | spin_lock_irq(&priv->ctx_lock); | |
813 | list_del(&dev_ctx->list); | |
814 | spin_unlock_irq(&priv->ctx_lock); | |
815 | ||
816 | intf->remove(dev, dev_ctx->context); | |
817 | kfree(dev_ctx); | |
818 | return; | |
819 | } | |
820 | } | |
821 | ||
822 | static int mlx5_register_device(struct mlx5_core_dev *dev) | |
e126ba97 EC |
823 | { |
824 | struct mlx5_priv *priv = &dev->priv; | |
a31208b1 MD |
825 | struct mlx5_interface *intf; |
826 | ||
7907f23a AH |
827 | mutex_lock(&mlx5_intf_mutex); |
828 | list_add_tail(&priv->dev_list, &mlx5_dev_list); | |
a31208b1 MD |
829 | list_for_each_entry(intf, &intf_list, list) |
830 | mlx5_add_device(intf, priv); | |
7907f23a | 831 | mutex_unlock(&mlx5_intf_mutex); |
a31208b1 MD |
832 | |
833 | return 0; | |
834 | } | |
835 | ||
836 | static void mlx5_unregister_device(struct mlx5_core_dev *dev) | |
837 | { | |
838 | struct mlx5_priv *priv = &dev->priv; | |
839 | struct mlx5_interface *intf; | |
840 | ||
7907f23a | 841 | mutex_lock(&mlx5_intf_mutex); |
a31208b1 MD |
842 | list_for_each_entry(intf, &intf_list, list) |
843 | mlx5_remove_device(intf, priv); | |
844 | list_del(&priv->dev_list); | |
7907f23a | 845 | mutex_unlock(&mlx5_intf_mutex); |
a31208b1 MD |
846 | } |
847 | ||
848 | int mlx5_register_interface(struct mlx5_interface *intf) | |
849 | { | |
850 | struct mlx5_priv *priv; | |
851 | ||
852 | if (!intf->add || !intf->remove) | |
853 | return -EINVAL; | |
854 | ||
7907f23a | 855 | mutex_lock(&mlx5_intf_mutex); |
a31208b1 | 856 | list_add_tail(&intf->list, &intf_list); |
7907f23a | 857 | list_for_each_entry(priv, &mlx5_dev_list, dev_list) |
a31208b1 | 858 | mlx5_add_device(intf, priv); |
7907f23a | 859 | mutex_unlock(&mlx5_intf_mutex); |
a31208b1 MD |
860 | |
861 | return 0; | |
862 | } | |
863 | EXPORT_SYMBOL(mlx5_register_interface); | |
864 | ||
865 | void mlx5_unregister_interface(struct mlx5_interface *intf) | |
866 | { | |
867 | struct mlx5_priv *priv; | |
868 | ||
7907f23a AH |
869 | mutex_lock(&mlx5_intf_mutex); |
870 | list_for_each_entry(priv, &mlx5_dev_list, dev_list) | |
a31208b1 MD |
871 | mlx5_remove_device(intf, priv); |
872 | list_del(&intf->list); | |
7907f23a | 873 | mutex_unlock(&mlx5_intf_mutex); |
a31208b1 MD |
874 | } |
875 | EXPORT_SYMBOL(mlx5_unregister_interface); | |
876 | ||
877 | void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol) | |
878 | { | |
879 | struct mlx5_priv *priv = &mdev->priv; | |
880 | struct mlx5_device_context *dev_ctx; | |
881 | unsigned long flags; | |
882 | void *result = NULL; | |
883 | ||
884 | spin_lock_irqsave(&priv->ctx_lock, flags); | |
885 | ||
886 | list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list) | |
887 | if ((dev_ctx->intf->protocol == protocol) && | |
888 | dev_ctx->intf->get_dev) { | |
889 | result = dev_ctx->intf->get_dev(dev_ctx->context); | |
890 | break; | |
891 | } | |
892 | ||
893 | spin_unlock_irqrestore(&priv->ctx_lock, flags); | |
894 | ||
895 | return result; | |
896 | } | |
897 | EXPORT_SYMBOL(mlx5_get_protocol_dev); | |
898 | ||
7907f23a AH |
899 | /* Must be called with intf_mutex held */ |
900 | void mlx5_add_dev_by_protocol(struct mlx5_core_dev *dev, int protocol) | |
901 | { | |
902 | struct mlx5_interface *intf; | |
903 | ||
904 | list_for_each_entry(intf, &intf_list, list) | |
905 | if (intf->protocol == protocol) { | |
906 | mlx5_add_device(intf, &dev->priv); | |
907 | break; | |
908 | } | |
909 | } | |
910 | ||
911 | /* Must be called with intf_mutex held */ | |
912 | void mlx5_remove_dev_by_protocol(struct mlx5_core_dev *dev, int protocol) | |
913 | { | |
914 | struct mlx5_interface *intf; | |
915 | ||
916 | list_for_each_entry(intf, &intf_list, list) | |
917 | if (intf->protocol == protocol) { | |
918 | mlx5_remove_device(intf, &dev->priv); | |
919 | break; | |
920 | } | |
921 | } | |
922 | ||
a31208b1 MD |
923 | static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
924 | { | |
925 | struct pci_dev *pdev = dev->pdev; | |
926 | int err = 0; | |
e126ba97 | 927 | |
e126ba97 EC |
928 | pci_set_drvdata(dev->pdev, dev); |
929 | strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); | |
930 | priv->name[MLX5_MAX_NAME_LEN - 1] = 0; | |
931 | ||
932 | mutex_init(&priv->pgdir_mutex); | |
933 | INIT_LIST_HEAD(&priv->pgdir_list); | |
934 | spin_lock_init(&priv->mkey_lock); | |
935 | ||
311c7c71 SM |
936 | mutex_init(&priv->alloc_mutex); |
937 | ||
938 | priv->numa_node = dev_to_node(&dev->pdev->dev); | |
939 | ||
e126ba97 EC |
940 | priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root); |
941 | if (!priv->dbg_root) | |
942 | return -ENOMEM; | |
943 | ||
89d44f0a | 944 | err = mlx5_pci_enable_device(dev); |
e126ba97 | 945 | if (err) { |
1a91de28 | 946 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
e126ba97 EC |
947 | goto err_dbg; |
948 | } | |
949 | ||
950 | err = request_bar(pdev); | |
951 | if (err) { | |
1a91de28 | 952 | dev_err(&pdev->dev, "error requesting BARs, aborting\n"); |
e126ba97 EC |
953 | goto err_disable; |
954 | } | |
955 | ||
956 | pci_set_master(pdev); | |
957 | ||
958 | err = set_dma_caps(pdev); | |
959 | if (err) { | |
960 | dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n"); | |
961 | goto err_clr_master; | |
962 | } | |
963 | ||
964 | dev->iseg_base = pci_resource_start(dev->pdev, 0); | |
965 | dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); | |
966 | if (!dev->iseg) { | |
967 | err = -ENOMEM; | |
968 | dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n"); | |
969 | goto err_clr_master; | |
970 | } | |
a31208b1 MD |
971 | |
972 | return 0; | |
973 | ||
974 | err_clr_master: | |
975 | pci_clear_master(dev->pdev); | |
976 | release_bar(dev->pdev); | |
977 | err_disable: | |
89d44f0a | 978 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
979 | |
980 | err_dbg: | |
981 | debugfs_remove(priv->dbg_root); | |
982 | return err; | |
983 | } | |
984 | ||
985 | static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) | |
986 | { | |
987 | iounmap(dev->iseg); | |
988 | pci_clear_master(dev->pdev); | |
989 | release_bar(dev->pdev); | |
89d44f0a | 990 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
991 | debugfs_remove(priv->dbg_root); |
992 | } | |
993 | ||
994 | #define MLX5_IB_MOD "mlx5_ib" | |
995 | static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv) | |
996 | { | |
997 | struct pci_dev *pdev = dev->pdev; | |
998 | int err; | |
999 | ||
89d44f0a | 1000 | mutex_lock(&dev->intf_state_mutex); |
5fc7197d | 1001 | if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
89d44f0a MD |
1002 | dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", |
1003 | __func__); | |
1004 | goto out; | |
1005 | } | |
1006 | ||
e126ba97 EC |
1007 | dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), |
1008 | fw_rev_min(dev), fw_rev_sub(dev)); | |
1009 | ||
89d44f0a MD |
1010 | /* on load removing any previous indication of internal error, device is |
1011 | * up | |
1012 | */ | |
1013 | dev->state = MLX5_DEVICE_STATE_UP; | |
1014 | ||
e126ba97 EC |
1015 | err = mlx5_cmd_init(dev); |
1016 | if (err) { | |
1017 | dev_err(&pdev->dev, "Failed initializing command interface, aborting\n"); | |
89d44f0a | 1018 | goto out_err; |
e126ba97 EC |
1019 | } |
1020 | ||
e3297246 EC |
1021 | err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); |
1022 | if (err) { | |
1023 | dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n", | |
1024 | FW_INIT_TIMEOUT_MILI); | |
1025 | goto out_err; | |
1026 | } | |
1027 | ||
e126ba97 | 1028 | mlx5_pagealloc_init(dev); |
cd23b14b | 1029 | |
0b107106 | 1030 | err = mlx5_core_enable_hca(dev, 0); |
cd23b14b EC |
1031 | if (err) { |
1032 | dev_err(&pdev->dev, "enable hca failed\n"); | |
1033 | goto err_pagealloc_cleanup; | |
1034 | } | |
1035 | ||
f62b8bb8 AV |
1036 | err = mlx5_core_set_issi(dev); |
1037 | if (err) { | |
1038 | dev_err(&pdev->dev, "failed to set issi\n"); | |
1039 | goto err_disable_hca; | |
1040 | } | |
f62b8bb8 | 1041 | |
cd23b14b EC |
1042 | err = mlx5_satisfy_startup_pages(dev, 1); |
1043 | if (err) { | |
1044 | dev_err(&pdev->dev, "failed to allocate boot pages\n"); | |
1045 | goto err_disable_hca; | |
1046 | } | |
1047 | ||
e126ba97 EC |
1048 | err = set_hca_ctrl(dev); |
1049 | if (err) { | |
1050 | dev_err(&pdev->dev, "set_hca_ctrl failed\n"); | |
cd23b14b | 1051 | goto reclaim_boot_pages; |
e126ba97 EC |
1052 | } |
1053 | ||
1054 | err = handle_hca_cap(dev); | |
1055 | if (err) { | |
1056 | dev_err(&pdev->dev, "handle_hca_cap failed\n"); | |
cd23b14b | 1057 | goto reclaim_boot_pages; |
e126ba97 EC |
1058 | } |
1059 | ||
f91e6d89 EBE |
1060 | err = handle_hca_cap_atomic(dev); |
1061 | if (err) { | |
1062 | dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n"); | |
1063 | goto reclaim_boot_pages; | |
e126ba97 EC |
1064 | } |
1065 | ||
cd23b14b | 1066 | err = mlx5_satisfy_startup_pages(dev, 0); |
e126ba97 | 1067 | if (err) { |
cd23b14b EC |
1068 | dev_err(&pdev->dev, "failed to allocate init pages\n"); |
1069 | goto reclaim_boot_pages; | |
e126ba97 EC |
1070 | } |
1071 | ||
1072 | err = mlx5_pagealloc_start(dev); | |
1073 | if (err) { | |
1074 | dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n"); | |
cd23b14b | 1075 | goto reclaim_boot_pages; |
e126ba97 EC |
1076 | } |
1077 | ||
1078 | err = mlx5_cmd_init_hca(dev); | |
1079 | if (err) { | |
1080 | dev_err(&pdev->dev, "init hca failed\n"); | |
1081 | goto err_pagealloc_stop; | |
1082 | } | |
1083 | ||
1084 | mlx5_start_health_poll(dev); | |
1085 | ||
938fe83c | 1086 | err = mlx5_query_hca_caps(dev); |
e126ba97 EC |
1087 | if (err) { |
1088 | dev_err(&pdev->dev, "query hca failed\n"); | |
1089 | goto err_stop_poll; | |
1090 | } | |
1091 | ||
211e6c80 | 1092 | err = mlx5_query_board_id(dev); |
e126ba97 | 1093 | if (err) { |
211e6c80 | 1094 | dev_err(&pdev->dev, "query board id failed\n"); |
e126ba97 EC |
1095 | goto err_stop_poll; |
1096 | } | |
1097 | ||
1098 | err = mlx5_enable_msix(dev); | |
1099 | if (err) { | |
1100 | dev_err(&pdev->dev, "enable msix failed\n"); | |
1101 | goto err_stop_poll; | |
1102 | } | |
1103 | ||
1104 | err = mlx5_eq_init(dev); | |
1105 | if (err) { | |
1106 | dev_err(&pdev->dev, "failed to initialize eq\n"); | |
1107 | goto disable_msix; | |
1108 | } | |
1109 | ||
1110 | err = mlx5_alloc_uuars(dev, &priv->uuari); | |
1111 | if (err) { | |
1112 | dev_err(&pdev->dev, "Failed allocating uar, aborting\n"); | |
1113 | goto err_eq_cleanup; | |
1114 | } | |
1115 | ||
1116 | err = mlx5_start_eqs(dev); | |
1117 | if (err) { | |
1118 | dev_err(&pdev->dev, "Failed to start pages and async EQs\n"); | |
1119 | goto err_free_uar; | |
1120 | } | |
1121 | ||
233d05d2 SM |
1122 | err = alloc_comp_eqs(dev); |
1123 | if (err) { | |
1124 | dev_err(&pdev->dev, "Failed to alloc completion EQs\n"); | |
1125 | goto err_stop_eqs; | |
1126 | } | |
1127 | ||
db058a18 | 1128 | err = mlx5_irq_set_affinity_hints(dev); |
0ba42241 | 1129 | if (err) |
db058a18 | 1130 | dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n"); |
db058a18 | 1131 | |
e126ba97 EC |
1132 | MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); |
1133 | ||
1134 | mlx5_init_cq_table(dev); | |
1135 | mlx5_init_qp_table(dev); | |
1136 | mlx5_init_srq_table(dev); | |
a606b0f6 | 1137 | mlx5_init_mkey_table(dev); |
e126ba97 | 1138 | |
86d722ad MG |
1139 | err = mlx5_init_fs(dev); |
1140 | if (err) { | |
1141 | dev_err(&pdev->dev, "Failed to init flow steering\n"); | |
1142 | goto err_fs; | |
1143 | } | |
1466cc5b YP |
1144 | |
1145 | err = mlx5_init_rl_table(dev); | |
1146 | if (err) { | |
1147 | dev_err(&pdev->dev, "Failed to init rate limiting\n"); | |
1148 | goto err_rl; | |
1149 | } | |
1150 | ||
073bb189 SM |
1151 | #ifdef CONFIG_MLX5_CORE_EN |
1152 | err = mlx5_eswitch_init(dev); | |
1153 | if (err) { | |
1154 | dev_err(&pdev->dev, "eswitch init failed %d\n", err); | |
1155 | goto err_reg_dev; | |
1156 | } | |
1157 | #endif | |
1158 | ||
fc50db98 EC |
1159 | err = mlx5_sriov_init(dev); |
1160 | if (err) { | |
1161 | dev_err(&pdev->dev, "sriov init failed %d\n", err); | |
1162 | goto err_sriov; | |
1163 | } | |
1164 | ||
a31208b1 MD |
1165 | err = mlx5_register_device(dev); |
1166 | if (err) { | |
1167 | dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); | |
1168 | goto err_reg_dev; | |
1169 | } | |
1170 | ||
1171 | err = request_module_nowait(MLX5_IB_MOD); | |
1172 | if (err) | |
1173 | pr_info("failed request module on %s\n", MLX5_IB_MOD); | |
1174 | ||
5fc7197d MD |
1175 | clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state); |
1176 | set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); | |
89d44f0a MD |
1177 | out: |
1178 | mutex_unlock(&dev->intf_state_mutex); | |
1179 | ||
e126ba97 EC |
1180 | return 0; |
1181 | ||
fc50db98 | 1182 | err_sriov: |
6b6adee3 | 1183 | mlx5_sriov_cleanup(dev); |
fc50db98 | 1184 | |
073bb189 SM |
1185 | #ifdef CONFIG_MLX5_CORE_EN |
1186 | mlx5_eswitch_cleanup(dev->priv.eswitch); | |
1187 | #endif | |
a31208b1 | 1188 | err_reg_dev: |
1466cc5b YP |
1189 | mlx5_cleanup_rl_table(dev); |
1190 | err_rl: | |
86d722ad MG |
1191 | mlx5_cleanup_fs(dev); |
1192 | err_fs: | |
a606b0f6 | 1193 | mlx5_cleanup_mkey_table(dev); |
a31208b1 MD |
1194 | mlx5_cleanup_srq_table(dev); |
1195 | mlx5_cleanup_qp_table(dev); | |
1196 | mlx5_cleanup_cq_table(dev); | |
1197 | mlx5_irq_clear_affinity_hints(dev); | |
db058a18 SM |
1198 | free_comp_eqs(dev); |
1199 | ||
233d05d2 SM |
1200 | err_stop_eqs: |
1201 | mlx5_stop_eqs(dev); | |
1202 | ||
e126ba97 EC |
1203 | err_free_uar: |
1204 | mlx5_free_uuars(dev, &priv->uuari); | |
1205 | ||
1206 | err_eq_cleanup: | |
1207 | mlx5_eq_cleanup(dev); | |
1208 | ||
1209 | disable_msix: | |
1210 | mlx5_disable_msix(dev); | |
1211 | ||
1212 | err_stop_poll: | |
1213 | mlx5_stop_health_poll(dev); | |
1bde6e30 EC |
1214 | if (mlx5_cmd_teardown_hca(dev)) { |
1215 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); | |
89d44f0a | 1216 | goto out_err; |
1bde6e30 | 1217 | } |
e126ba97 EC |
1218 | |
1219 | err_pagealloc_stop: | |
1220 | mlx5_pagealloc_stop(dev); | |
1221 | ||
cd23b14b | 1222 | reclaim_boot_pages: |
e126ba97 EC |
1223 | mlx5_reclaim_startup_pages(dev); |
1224 | ||
cd23b14b | 1225 | err_disable_hca: |
0b107106 | 1226 | mlx5_core_disable_hca(dev, 0); |
cd23b14b | 1227 | |
e126ba97 EC |
1228 | err_pagealloc_cleanup: |
1229 | mlx5_pagealloc_cleanup(dev); | |
1230 | mlx5_cmd_cleanup(dev); | |
1231 | ||
89d44f0a MD |
1232 | out_err: |
1233 | dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; | |
1234 | mutex_unlock(&dev->intf_state_mutex); | |
1235 | ||
e126ba97 EC |
1236 | return err; |
1237 | } | |
e126ba97 | 1238 | |
a31208b1 | 1239 | static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
e126ba97 | 1240 | { |
89d44f0a | 1241 | int err = 0; |
e126ba97 | 1242 | |
89d44f0a | 1243 | mutex_lock(&dev->intf_state_mutex); |
5fc7197d | 1244 | if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) { |
89d44f0a MD |
1245 | dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", |
1246 | __func__); | |
1247 | goto out; | |
1248 | } | |
6b6adee3 MHY |
1249 | |
1250 | mlx5_sriov_cleanup(dev); | |
a31208b1 | 1251 | mlx5_unregister_device(dev); |
073bb189 SM |
1252 | #ifdef CONFIG_MLX5_CORE_EN |
1253 | mlx5_eswitch_cleanup(dev->priv.eswitch); | |
1254 | #endif | |
1255 | ||
1466cc5b | 1256 | mlx5_cleanup_rl_table(dev); |
86d722ad | 1257 | mlx5_cleanup_fs(dev); |
a606b0f6 | 1258 | mlx5_cleanup_mkey_table(dev); |
e126ba97 EC |
1259 | mlx5_cleanup_srq_table(dev); |
1260 | mlx5_cleanup_qp_table(dev); | |
1261 | mlx5_cleanup_cq_table(dev); | |
db058a18 | 1262 | mlx5_irq_clear_affinity_hints(dev); |
233d05d2 | 1263 | free_comp_eqs(dev); |
e126ba97 EC |
1264 | mlx5_stop_eqs(dev); |
1265 | mlx5_free_uuars(dev, &priv->uuari); | |
1266 | mlx5_eq_cleanup(dev); | |
1267 | mlx5_disable_msix(dev); | |
1268 | mlx5_stop_health_poll(dev); | |
ac6ea6e8 EC |
1269 | err = mlx5_cmd_teardown_hca(dev); |
1270 | if (err) { | |
1bde6e30 | 1271 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); |
ac6ea6e8 | 1272 | goto out; |
1bde6e30 | 1273 | } |
e126ba97 EC |
1274 | mlx5_pagealloc_stop(dev); |
1275 | mlx5_reclaim_startup_pages(dev); | |
0b107106 | 1276 | mlx5_core_disable_hca(dev, 0); |
e126ba97 EC |
1277 | mlx5_pagealloc_cleanup(dev); |
1278 | mlx5_cmd_cleanup(dev); | |
9603b61d | 1279 | |
ac6ea6e8 | 1280 | out: |
5fc7197d MD |
1281 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
1282 | set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state); | |
89d44f0a | 1283 | mutex_unlock(&dev->intf_state_mutex); |
ac6ea6e8 | 1284 | return err; |
9603b61d | 1285 | } |
64613d94 | 1286 | |
89d44f0a | 1287 | void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, |
ac6ea6e8 | 1288 | unsigned long param) |
9603b61d JM |
1289 | { |
1290 | struct mlx5_priv *priv = &dev->priv; | |
1291 | struct mlx5_device_context *dev_ctx; | |
1292 | unsigned long flags; | |
1293 | ||
1294 | spin_lock_irqsave(&priv->ctx_lock, flags); | |
1295 | ||
1296 | list_for_each_entry(dev_ctx, &priv->ctx_list, list) | |
1297 | if (dev_ctx->intf->event) | |
4d2f9bbb | 1298 | dev_ctx->intf->event(dev, dev_ctx->context, event, param); |
9603b61d JM |
1299 | |
1300 | spin_unlock_irqrestore(&priv->ctx_lock, flags); | |
1301 | } | |
1302 | ||
1303 | struct mlx5_core_event_handler { | |
1304 | void (*event)(struct mlx5_core_dev *dev, | |
1305 | enum mlx5_dev_event event, | |
1306 | void *data); | |
1307 | }; | |
1308 | ||
feae9087 OG |
1309 | static const struct devlink_ops mlx5_devlink_ops = { |
1310 | #ifdef CONFIG_MLX5_CORE_EN | |
1311 | .eswitch_mode_set = mlx5_devlink_eswitch_mode_set, | |
1312 | .eswitch_mode_get = mlx5_devlink_eswitch_mode_get, | |
1313 | #endif | |
1314 | }; | |
f66f049f | 1315 | |
9603b61d JM |
1316 | static int init_one(struct pci_dev *pdev, |
1317 | const struct pci_device_id *id) | |
1318 | { | |
1319 | struct mlx5_core_dev *dev; | |
feae9087 | 1320 | struct devlink *devlink; |
9603b61d JM |
1321 | struct mlx5_priv *priv; |
1322 | int err; | |
1323 | ||
feae9087 OG |
1324 | devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev)); |
1325 | if (!devlink) { | |
9603b61d JM |
1326 | dev_err(&pdev->dev, "kzalloc failed\n"); |
1327 | return -ENOMEM; | |
1328 | } | |
feae9087 OG |
1329 | |
1330 | dev = devlink_priv(devlink); | |
9603b61d | 1331 | priv = &dev->priv; |
fc50db98 | 1332 | priv->pci_dev_data = id->driver_data; |
9603b61d JM |
1333 | |
1334 | pci_set_drvdata(pdev, dev); | |
1335 | ||
1336 | if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) { | |
2974ab6e SM |
1337 | mlx5_core_warn(dev, |
1338 | "selected profile out of range, selecting default (%d)\n", | |
1339 | MLX5_DEFAULT_PROF); | |
9603b61d JM |
1340 | prof_sel = MLX5_DEFAULT_PROF; |
1341 | } | |
1342 | dev->profile = &profile[prof_sel]; | |
a31208b1 | 1343 | dev->pdev = pdev; |
9603b61d JM |
1344 | dev->event = mlx5_core_event; |
1345 | ||
364d1798 EC |
1346 | INIT_LIST_HEAD(&priv->ctx_list); |
1347 | spin_lock_init(&priv->ctx_lock); | |
89d44f0a MD |
1348 | mutex_init(&dev->pci_status_mutex); |
1349 | mutex_init(&dev->intf_state_mutex); | |
a31208b1 | 1350 | err = mlx5_pci_init(dev, priv); |
9603b61d | 1351 | if (err) { |
a31208b1 MD |
1352 | dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err); |
1353 | goto clean_dev; | |
9603b61d JM |
1354 | } |
1355 | ||
ac6ea6e8 EC |
1356 | err = mlx5_health_init(dev); |
1357 | if (err) { | |
1358 | dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err); | |
1359 | goto close_pci; | |
1360 | } | |
1361 | ||
a31208b1 | 1362 | err = mlx5_load_one(dev, priv); |
9603b61d | 1363 | if (err) { |
a31208b1 | 1364 | dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err); |
ac6ea6e8 | 1365 | goto clean_health; |
9603b61d JM |
1366 | } |
1367 | ||
feae9087 OG |
1368 | err = devlink_register(devlink, &pdev->dev); |
1369 | if (err) | |
1370 | goto clean_load; | |
1371 | ||
9603b61d JM |
1372 | return 0; |
1373 | ||
feae9087 OG |
1374 | clean_load: |
1375 | mlx5_unload_one(dev, priv); | |
ac6ea6e8 EC |
1376 | clean_health: |
1377 | mlx5_health_cleanup(dev); | |
a31208b1 MD |
1378 | close_pci: |
1379 | mlx5_pci_close(dev, priv); | |
1380 | clean_dev: | |
1381 | pci_set_drvdata(pdev, NULL); | |
feae9087 | 1382 | devlink_free(devlink); |
a31208b1 | 1383 | |
9603b61d JM |
1384 | return err; |
1385 | } | |
a31208b1 | 1386 | |
9603b61d JM |
1387 | static void remove_one(struct pci_dev *pdev) |
1388 | { | |
1389 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
feae9087 | 1390 | struct devlink *devlink = priv_to_devlink(dev); |
a31208b1 | 1391 | struct mlx5_priv *priv = &dev->priv; |
9603b61d | 1392 | |
feae9087 | 1393 | devlink_unregister(devlink); |
a31208b1 MD |
1394 | if (mlx5_unload_one(dev, priv)) { |
1395 | dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); | |
ac6ea6e8 | 1396 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1397 | return; |
1398 | } | |
ac6ea6e8 | 1399 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1400 | mlx5_pci_close(dev, priv); |
1401 | pci_set_drvdata(pdev, NULL); | |
feae9087 | 1402 | devlink_free(devlink); |
9603b61d JM |
1403 | } |
1404 | ||
89d44f0a MD |
1405 | static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, |
1406 | pci_channel_state_t state) | |
1407 | { | |
1408 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1409 | struct mlx5_priv *priv = &dev->priv; | |
1410 | ||
1411 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1412 | mlx5_enter_error_state(dev); | |
1413 | mlx5_unload_one(dev, priv); | |
1061c90f | 1414 | pci_save_state(pdev); |
89d44f0a MD |
1415 | mlx5_pci_disable_device(dev); |
1416 | return state == pci_channel_io_perm_failure ? | |
1417 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
1418 | } | |
1419 | ||
d57847dc DJ |
1420 | /* wait for the device to show vital signs by waiting |
1421 | * for the health counter to start counting. | |
89d44f0a | 1422 | */ |
d57847dc | 1423 | static int wait_vital(struct pci_dev *pdev) |
89d44f0a MD |
1424 | { |
1425 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1426 | struct mlx5_core_health *health = &dev->priv.health; | |
1427 | const int niter = 100; | |
d57847dc | 1428 | u32 last_count = 0; |
89d44f0a | 1429 | u32 count; |
89d44f0a MD |
1430 | int i; |
1431 | ||
89d44f0a MD |
1432 | for (i = 0; i < niter; i++) { |
1433 | count = ioread32be(health->health_counter); | |
1434 | if (count && count != 0xffffffff) { | |
d57847dc DJ |
1435 | if (last_count && last_count != count) { |
1436 | dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); | |
1437 | return 0; | |
1438 | } | |
1439 | last_count = count; | |
89d44f0a MD |
1440 | } |
1441 | msleep(50); | |
1442 | } | |
1443 | ||
d57847dc | 1444 | return -ETIMEDOUT; |
89d44f0a MD |
1445 | } |
1446 | ||
1061c90f | 1447 | static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) |
89d44f0a MD |
1448 | { |
1449 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
89d44f0a MD |
1450 | int err; |
1451 | ||
1452 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1453 | ||
1061c90f | 1454 | err = mlx5_pci_enable_device(dev); |
d57847dc | 1455 | if (err) { |
1061c90f MHY |
1456 | dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" |
1457 | , __func__, err); | |
1458 | return PCI_ERS_RESULT_DISCONNECT; | |
1459 | } | |
1460 | ||
1461 | pci_set_master(pdev); | |
1462 | pci_restore_state(pdev); | |
1463 | ||
1464 | if (wait_vital(pdev)) { | |
d57847dc | 1465 | dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__); |
1061c90f | 1466 | return PCI_ERS_RESULT_DISCONNECT; |
d57847dc | 1467 | } |
89d44f0a | 1468 | |
1061c90f MHY |
1469 | return PCI_ERS_RESULT_RECOVERED; |
1470 | } | |
1471 | ||
1472 | void mlx5_disable_device(struct mlx5_core_dev *dev) | |
1473 | { | |
1474 | mlx5_pci_err_detected(dev->pdev, 0); | |
1475 | } | |
1476 | ||
1477 | static void mlx5_pci_resume(struct pci_dev *pdev) | |
1478 | { | |
1479 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1480 | struct mlx5_priv *priv = &dev->priv; | |
1481 | int err; | |
1482 | ||
1483 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1484 | ||
89d44f0a MD |
1485 | err = mlx5_load_one(dev, priv); |
1486 | if (err) | |
1487 | dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" | |
1488 | , __func__, err); | |
1489 | else | |
1490 | dev_info(&pdev->dev, "%s: device recovered\n", __func__); | |
1491 | } | |
1492 | ||
1493 | static const struct pci_error_handlers mlx5_err_handler = { | |
1494 | .error_detected = mlx5_pci_err_detected, | |
1495 | .slot_reset = mlx5_pci_slot_reset, | |
1496 | .resume = mlx5_pci_resume | |
1497 | }; | |
1498 | ||
5fc7197d MD |
1499 | static void shutdown(struct pci_dev *pdev) |
1500 | { | |
1501 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1502 | struct mlx5_priv *priv = &dev->priv; | |
1503 | ||
1504 | dev_info(&pdev->dev, "Shutdown was called\n"); | |
1505 | /* Notify mlx5 clients that the kernel is being shut down */ | |
1506 | set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state); | |
1507 | mlx5_unload_one(dev, priv); | |
1508 | mlx5_pci_disable_device(dev); | |
1509 | } | |
1510 | ||
9603b61d | 1511 | static const struct pci_device_id mlx5_core_pci_table[] = { |
fc50db98 EC |
1512 | { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */ |
1513 | { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ | |
1514 | { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */ | |
1515 | { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ | |
1516 | { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */ | |
1517 | { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ | |
7092fe86 | 1518 | { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ |
64dbbdfe | 1519 | { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ |
7092fe86 | 1520 | { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5, PCIe 4.0 */ |
9603b61d JM |
1521 | { 0, } |
1522 | }; | |
1523 | ||
1524 | MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); | |
1525 | ||
1526 | static struct pci_driver mlx5_core_driver = { | |
1527 | .name = DRIVER_NAME, | |
1528 | .id_table = mlx5_core_pci_table, | |
1529 | .probe = init_one, | |
89d44f0a | 1530 | .remove = remove_one, |
5fc7197d | 1531 | .shutdown = shutdown, |
fc50db98 EC |
1532 | .err_handler = &mlx5_err_handler, |
1533 | .sriov_configure = mlx5_core_sriov_configure, | |
9603b61d | 1534 | }; |
e126ba97 EC |
1535 | |
1536 | static int __init init(void) | |
1537 | { | |
1538 | int err; | |
1539 | ||
1540 | mlx5_register_debugfs(); | |
e126ba97 | 1541 | |
9603b61d JM |
1542 | err = pci_register_driver(&mlx5_core_driver); |
1543 | if (err) | |
ac6ea6e8 | 1544 | goto err_debug; |
9603b61d | 1545 | |
f62b8bb8 AV |
1546 | #ifdef CONFIG_MLX5_CORE_EN |
1547 | mlx5e_init(); | |
1548 | #endif | |
1549 | ||
e126ba97 EC |
1550 | return 0; |
1551 | ||
e126ba97 EC |
1552 | err_debug: |
1553 | mlx5_unregister_debugfs(); | |
1554 | return err; | |
1555 | } | |
1556 | ||
1557 | static void __exit cleanup(void) | |
1558 | { | |
f62b8bb8 AV |
1559 | #ifdef CONFIG_MLX5_CORE_EN |
1560 | mlx5e_cleanup(); | |
1561 | #endif | |
9603b61d | 1562 | pci_unregister_driver(&mlx5_core_driver); |
e126ba97 EC |
1563 | mlx5_unregister_debugfs(); |
1564 | } | |
1565 | ||
1566 | module_init(init); | |
1567 | module_exit(cleanup); |