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net/mlx5: Introduce attach/detach to interface API
[people/arne_f/kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e3297246 42#include <linux/delay.h>
e126ba97
EC		 43#include <linux/mlx5/driver.h>
44#include <linux/mlx5/cq.h>
45#include <linux/mlx5/qp.h>
46#include <linux/mlx5/srq.h>
47#include <linux/debugfs.h>
f66f049f 48#include <linux/kmod.h>
89d44f0a 49#include <linux/delay.h>
b775516b 50#include <linux/mlx5/mlx5_ifc.h>
5a7b27eb
MG		 51#ifdef CONFIG_RFS_ACCEL
52#include <linux/cpu_rmap.h>
53#endif
feae9087 54#include <net/devlink.h>
e126ba97 55#include "mlx5_core.h"
86d722ad 56#include "fs_core.h"
073bb189
SM		 57#ifdef CONFIG_MLX5_CORE_EN
58#include "eswitch.h"
59#endif
e126ba97 60
e126ba97 61MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 62MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 63MODULE_LICENSE("Dual BSD/GPL");
64MODULE_VERSION(DRIVER_VERSION);
65
66int mlx5_core_debug_mask;
67module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
68MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
69
9603b61d
JM		 70#define MLX5_DEFAULT_PROF 2
71static int prof_sel = MLX5_DEFAULT_PROF;
72module_param_named(prof_sel, prof_sel, int, 0444);
73MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
74
9603b61d 75static LIST_HEAD(intf_list);
7907f23a
AH		 76
77LIST_HEAD(mlx5_dev_list);
78DEFINE_MUTEX(mlx5_intf_mutex);
9603b61d
JM		 79
80struct mlx5_device_context {
81 struct list_head list;
82 struct mlx5_interface *intf;
83 void *context;
737a234b 84 unsigned long state;
9603b61d
JM		 85};
86
f91e6d89
EBE		 87enum {
88 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
89 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
90};
91
9603b61d
JM		 92static struct mlx5_profile profile[] = {
93 [0] = {
94 .mask = 0,
95 },
96 [1] = {
97 .mask = MLX5_PROF_MASK_QP_SIZE,
98 .log_max_qp = 12,
99 },
100 [2] = {
101 .mask = MLX5_PROF_MASK_QP_SIZE |
102 MLX5_PROF_MASK_MR_CACHE,
103 .log_max_qp = 17,
104 .mr_cache[0] = {
105 .size = 500,
106 .limit = 250
107 },
108 .mr_cache[1] = {
109 .size = 500,
110 .limit = 250
111 },
112 .mr_cache[2] = {
113 .size = 500,
114 .limit = 250
115 },
116 .mr_cache[3] = {
117 .size = 500,
118 .limit = 250
119 },
120 .mr_cache[4] = {
121 .size = 500,
122 .limit = 250
123 },
124 .mr_cache[5] = {
125 .size = 500,
126 .limit = 250
127 },
128 .mr_cache[6] = {
129 .size = 500,
130 .limit = 250
131 },
132 .mr_cache[7] = {
133 .size = 500,
134 .limit = 250
135 },
136 .mr_cache[8] = {
137 .size = 500,
138 .limit = 250
139 },
140 .mr_cache[9] = {
141 .size = 500,
142 .limit = 250
143 },
144 .mr_cache[10] = {
145 .size = 500,
146 .limit = 250
147 },
148 .mr_cache[11] = {
149 .size = 500,
150 .limit = 250
151 },
152 .mr_cache[12] = {
153 .size = 64,
154 .limit = 32
155 },
156 .mr_cache[13] = {
157 .size = 32,
158 .limit = 16
159 },
160 .mr_cache[14] = {
161 .size = 16,
162 .limit = 8
163 },
164 .mr_cache[15] = {
165 .size = 8,
166 .limit = 4
167 },
168 },
169};
e126ba97 170
e3297246
EC		 171#define FW_INIT_TIMEOUT_MILI 2000
172#define FW_INIT_WAIT_MS 2
173
174static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
175{
176 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
177 int err = 0;
178
179 while (fw_initializing(dev)) {
180 if (time_after(jiffies, end)) {
181 err = -EBUSY;
182 break;
183 }
184 msleep(FW_INIT_WAIT_MS);
185 }
186
187 return err;
188}
189
e126ba97
EC		 190static int set_dma_caps(struct pci_dev *pdev)
191{
192 int err;
193
194 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
195 if (err) {
1a91de28 196 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 197 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
198 if (err) {
1a91de28 199 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 200 return err;
201 }
202 }
203
204 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
205 if (err) {
206 dev_warn(&pdev->dev,
1a91de28 207 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 208 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
209 if (err) {
210 dev_err(&pdev->dev,
1a91de28 211 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 212 return err;
213 }
214 }
215
216 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
217 return err;
218}
219
89d44f0a
MD		 220static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
221{
222 struct pci_dev *pdev = dev->pdev;
223 int err = 0;
224
225 mutex_lock(&dev->pci_status_mutex);
226 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
227 err = pci_enable_device(pdev);
228 if (!err)
229 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
230 }
231 mutex_unlock(&dev->pci_status_mutex);
232
233 return err;
234}
235
236static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
237{
238 struct pci_dev *pdev = dev->pdev;
239
240 mutex_lock(&dev->pci_status_mutex);
241 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
242 pci_disable_device(pdev);
243 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
244 }
245 mutex_unlock(&dev->pci_status_mutex);
246}
247
e126ba97
EC		 248static int request_bar(struct pci_dev *pdev)
249{
250 int err = 0;
251
252 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 253 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 254 return -ENODEV;
255 }
256
257 err = pci_request_regions(pdev, DRIVER_NAME);
258 if (err)
259 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
260
261 return err;
262}
263
264static void release_bar(struct pci_dev *pdev)
265{
266 pci_release_regions(pdev);
267}
268
269static int mlx5_enable_msix(struct mlx5_core_dev *dev)
270{
db058a18
SM		 271 struct mlx5_priv *priv = &dev->priv;
272 struct mlx5_eq_table *table = &priv->eq_table;
938fe83c 273 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
e126ba97 274 int nvec;
e126ba97
EC		 275 int i;
276
938fe83c
SM		 277 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
278 MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 279 nvec = min_t(int, nvec, num_eqs);
280 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
281 return -ENOMEM;
282
db058a18
SM		 283 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
284
285 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
286 if (!priv->msix_arr || !priv->irq_info)
287 goto err_free_msix;
e126ba97
EC		 288
289 for (i = 0; i < nvec; i++)
db058a18 290 priv->msix_arr[i].entry = i;
e126ba97 291
db058a18 292 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
3a9e161a 293 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 294 if (nvec < 0)
295 return nvec;
e126ba97 296
f3c9407b 297 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 298
299 return 0;
db058a18
SM		 300
301err_free_msix:
302 kfree(priv->irq_info);
303 kfree(priv->msix_arr);
304 return -ENOMEM;
e126ba97
EC		 305}
306
307static void mlx5_disable_msix(struct mlx5_core_dev *dev)
308{
db058a18 309 struct mlx5_priv *priv = &dev->priv;
e126ba97
EC		 310
311 pci_disable_msix(dev->pdev);
db058a18
SM		 312 kfree(priv->irq_info);
313 kfree(priv->msix_arr);
e126ba97
EC		 314}
315
316struct mlx5_reg_host_endianess {
317 u8 he;
318 u8 rsvd[15];
319};
320
87b8de49
EC		 321
322#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
323
324enum {
c7a08ac7
EC		 325 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
326 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 327};
328
2974ab6e 329static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
c7a08ac7
EC		 330{
331 switch (size) {
332 case 128:
333 return 0;
334 case 256:
335 return 1;
336 case 512:
337 return 2;
338 case 1024:
339 return 3;
340 case 2048:
341 return 4;
342 case 4096:
343 return 5;
344 default:
2974ab6e 345 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
c7a08ac7
EC		 346 return 0;
347 }
348}
349
b06e7de8
LR		 350static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
351 enum mlx5_cap_type cap_type,
352 enum mlx5_cap_mode cap_mode)
c7a08ac7 353{
b775516b
EC		 354 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
355 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
938fe83c
SM		 356 void *out, *hca_caps;
357 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
e126ba97
EC		 358 int err;
359
b775516b
EC		 360 memset(in, 0, sizeof(in));
361 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 362 if (!out)
e126ba97 363 return -ENOMEM;
938fe83c 364
b775516b
EC		 365 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
366 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
367 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
c7a08ac7 368 if (err) {
938fe83c
SM		 369 mlx5_core_warn(dev,
370 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
371 cap_type, cap_mode, err);
e126ba97
EC		 372 goto query_ex;
373 }
c7a08ac7 374
938fe83c
SM		 375 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
376
377 switch (cap_mode) {
378 case HCA_CAP_OPMOD_GET_MAX:
379 memcpy(dev->hca_caps_max[cap_type], hca_caps,
380 MLX5_UN_SZ_BYTES(hca_cap_union));
381 break;
382 case HCA_CAP_OPMOD_GET_CUR:
383 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
384 MLX5_UN_SZ_BYTES(hca_cap_union));
385 break;
386 default:
387 mlx5_core_warn(dev,
388 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
389 cap_type, cap_mode);
390 err = -EINVAL;
391 break;
392 }
c7a08ac7
EC		 393query_ex:
394 kfree(out);
395 return err;
396}
397
b06e7de8
LR		 398int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
399{
400 int ret;
401
402 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
403 if (ret)
404 return ret;
405 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
406}
407
f91e6d89 408static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
c7a08ac7 409{
c4f287c4 410 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
e126ba97 411
b775516b 412 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
f91e6d89 413 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
c4f287c4 414 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
c7a08ac7
EC		 415}
416
f91e6d89
EBE		 417static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
418{
419 void *set_ctx;
420 void *set_hca_cap;
421 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
422 int req_endianness;
423 int err;
424
425 if (MLX5_CAP_GEN(dev, atomic)) {
b06e7de8 426 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
f91e6d89
EBE		 427 if (err)
428 return err;
429 } else {
430 return 0;
431 }
432
433 req_endianness =
434 MLX5_CAP_ATOMIC(dev,
435 supported_atomic_req_8B_endianess_mode_1);
436
437 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
438 return 0;
439
440 set_ctx = kzalloc(set_sz, GFP_KERNEL);
441 if (!set_ctx)
442 return -ENOMEM;
443
444 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
445
446 /* Set requestor to host endianness */
447 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
448 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
449
450 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
451
452 kfree(set_ctx);
453 return err;
454}
455
c7a08ac7
EC		 456static int handle_hca_cap(struct mlx5_core_dev *dev)
457{
b775516b 458 void *set_ctx = NULL;
c7a08ac7 459 struct mlx5_profile *prof = dev->profile;
c7a08ac7 460 int err = -ENOMEM;
b775516b 461 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
938fe83c 462 void *set_hca_cap;
c7a08ac7 463
b775516b 464 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 465 if (!set_ctx)
e126ba97 466 goto query_ex;
e126ba97 467
b06e7de8 468 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
e126ba97
EC		 469 if (err)
470 goto query_ex;
471
938fe83c
SM		 472 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
473 capability);
474 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
475 MLX5_ST_SZ_BYTES(cmd_hca_cap));
476
477 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
707c4602 478 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
938fe83c 479 128);
c7a08ac7 480 /* we limit the size of the pkey table to 128 entries for now */
938fe83c 481 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
2974ab6e 482 to_fw_pkey_sz(dev, 128));
c7a08ac7
EC		 483
484 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
938fe83c
SM		 485 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
486 prof->log_max_qp);
c7a08ac7 487
938fe83c
SM		 488 /* disable cmdif checksum */
489 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
c7a08ac7 490
fe1e1876
CS		 491 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
492
f91e6d89
EBE		 493 err = set_caps(dev, set_ctx, set_sz,
494 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
c7a08ac7 495
e126ba97 496query_ex:
e126ba97 497 kfree(set_ctx);
e126ba97
EC		 498 return err;
499}
500
501static int set_hca_ctrl(struct mlx5_core_dev *dev)
502{
503 struct mlx5_reg_host_endianess he_in;
504 struct mlx5_reg_host_endianess he_out;
505 int err;
506
fc50db98
EC		 507 if (!mlx5_core_is_pf(dev))
508 return 0;
509
e126ba97
EC		 510 memset(&he_in, 0, sizeof(he_in));
511 he_in.he = MLX5_SET_HOST_ENDIANNESS;
512 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
513 &he_out, sizeof(he_out),
514 MLX5_REG_HOST_ENDIANNESS, 0, 1);
515 return err;
516}
517
0b107106 518int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
cd23b14b 519{
c4f287c4
SM		 520 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
521 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
cd23b14b 522
0b107106
EC		 523 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
524 MLX5_SET(enable_hca_in, in, function_id, func_id);
c4f287c4 525 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
cd23b14b
EC		 526}
527
0b107106 528int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
cd23b14b 529{
c4f287c4
SM		 530 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
531 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
cd23b14b 532
0b107106
EC		 533 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
534 MLX5_SET(disable_hca_in, in, function_id, func_id);
c4f287c4 535 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
cd23b14b
EC		 536}
537
b0844444
EBE		 538cycle_t mlx5_read_internal_timer(struct mlx5_core_dev *dev)
539{
540 u32 timer_h, timer_h1, timer_l;
541
542 timer_h = ioread32be(&dev->iseg->internal_timer_h);
543 timer_l = ioread32be(&dev->iseg->internal_timer_l);
544 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
545 if (timer_h != timer_h1) /* wrap around */
546 timer_l = ioread32be(&dev->iseg->internal_timer_l);
547
548 return (cycle_t)timer_l | (cycle_t)timer_h1 << 32;
549}
550
db058a18
SM		 551static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
552{
553 struct mlx5_priv *priv = &mdev->priv;
554 struct msix_entry *msix = priv->msix_arr;
555 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
311c7c71 556 int numa_node = priv->numa_node;
db058a18
SM		 557 int err;
558
559 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
560 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
561 return -ENOMEM;
562 }
563
dda922c8
DM		 564 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
565 priv->irq_info[i].mask);
db058a18
SM		 566
567 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
568 if (err) {
569 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
570 irq);
571 goto err_clear_mask;
572 }
573
574 return 0;
575
576err_clear_mask:
577 free_cpumask_var(priv->irq_info[i].mask);
578 return err;
579}
580
581static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
582{
583 struct mlx5_priv *priv = &mdev->priv;
584 struct msix_entry *msix = priv->msix_arr;
585 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
586
587 irq_set_affinity_hint(irq, NULL);
588 free_cpumask_var(priv->irq_info[i].mask);
589}
590
591static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
592{
593 int err;
594 int i;
595
596 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
597 err = mlx5_irq_set_affinity_hint(mdev, i);
598 if (err)
599 goto err_out;
600 }
601
602 return 0;
603
604err_out:
605 for (i--; i >= 0; i--)
606 mlx5_irq_clear_affinity_hint(mdev, i);
607
608 return err;
609}
610
611static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
612{
613 int i;
614
615 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
616 mlx5_irq_clear_affinity_hint(mdev, i);
617}
618
0b6e26ce
DT		 619int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
620 unsigned int *irqn)
233d05d2
SM		 621{
622 struct mlx5_eq_table *table = &dev->priv.eq_table;
623 struct mlx5_eq *eq, *n;
624 int err = -ENOENT;
625
626 spin_lock(&table->lock);
627 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
628 if (eq->index == vector) {
629 *eqn = eq->eqn;
630 *irqn = eq->irqn;
631 err = 0;
632 break;
633 }
634 }
635 spin_unlock(&table->lock);
636
637 return err;
638}
639EXPORT_SYMBOL(mlx5_vector2eqn);
640
94c6825e
MB		 641struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
642{
643 struct mlx5_eq_table *table = &dev->priv.eq_table;
644 struct mlx5_eq *eq;
645
646 spin_lock(&table->lock);
647 list_for_each_entry(eq, &table->comp_eqs_list, list)
648 if (eq->eqn == eqn) {
649 spin_unlock(&table->lock);
650 return eq;
651 }
652
653 spin_unlock(&table->lock);
654
655 return ERR_PTR(-ENOENT);
656}
657
233d05d2
SM		 658static void free_comp_eqs(struct mlx5_core_dev *dev)
659{
660 struct mlx5_eq_table *table = &dev->priv.eq_table;
661 struct mlx5_eq *eq, *n;
662
5a7b27eb
MG		 663#ifdef CONFIG_RFS_ACCEL
664 if (dev->rmap) {
665 free_irq_cpu_rmap(dev->rmap);
666 dev->rmap = NULL;
667 }
668#endif
233d05d2
SM		 669 spin_lock(&table->lock);
670 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
671 list_del(&eq->list);
672 spin_unlock(&table->lock);
673 if (mlx5_destroy_unmap_eq(dev, eq))
674 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
675 eq->eqn);
676 kfree(eq);
677 spin_lock(&table->lock);
678 }
679 spin_unlock(&table->lock);
680}
681
682static int alloc_comp_eqs(struct mlx5_core_dev *dev)
683{
684 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 685 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 686 struct mlx5_eq *eq;
687 int ncomp_vec;
688 int nent;
689 int err;
690 int i;
691
692 INIT_LIST_HEAD(&table->comp_eqs_list);
693 ncomp_vec = table->num_comp_vectors;
694 nent = MLX5_COMP_EQ_SIZE;
5a7b27eb
MG		 695#ifdef CONFIG_RFS_ACCEL
696 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
697 if (!dev->rmap)
698 return -ENOMEM;
699#endif
233d05d2
SM		 700 for (i = 0; i < ncomp_vec; i++) {
701 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
702 if (!eq) {
703 err = -ENOMEM;
704 goto clean;
705 }
706
5a7b27eb
MG		 707#ifdef CONFIG_RFS_ACCEL
708 irq_cpu_rmap_add(dev->rmap,
709 dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector);
710#endif
db058a18 711 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 712 err = mlx5_create_map_eq(dev, eq,
713 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
714 name, &dev->priv.uuari.uars[0]);
715 if (err) {
716 kfree(eq);
717 goto clean;
718 }
719 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
720 eq->index = i;
721 spin_lock(&table->lock);
722 list_add_tail(&eq->list, &table->comp_eqs_list);
723 spin_unlock(&table->lock);
724 }
725
726 return 0;
727
728clean:
729 free_comp_eqs(dev);
730 return err;
731}
732
f62b8bb8
AV		 733static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
734{
c4f287c4
SM		 735 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
736 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
f62b8bb8 737 u32 sup_issi;
c4f287c4 738 int err;
f62b8bb8
AV		 739
740 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
c4f287c4
SM		 741 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
742 query_out, sizeof(query_out));
f62b8bb8 743 if (err) {
c4f287c4
SM		 744 u32 syndrome;
745 u8 status;
746
747 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
748 if (status == MLX5_CMD_STAT_BAD_OP_ERR) {
f62b8bb8
AV		 749 pr_debug("Only ISSI 0 is supported\n");
750 return 0;
751 }
752
c4f287c4 753 pr_err("failed to query ISSI err(%d)\n", err);
f62b8bb8
AV		 754 return err;
755 }
756
757 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
758
759 if (sup_issi & (1 << 1)) {
c4f287c4
SM		 760 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
761 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
f62b8bb8
AV		 762
763 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
764 MLX5_SET(set_issi_in, set_in, current_issi, 1);
c4f287c4
SM		 765 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
766 set_out, sizeof(set_out));
f62b8bb8 767 if (err) {
c4f287c4 768 pr_err("failed to set ISSI=1 err(%d)\n", err);
f62b8bb8
AV		 769 return err;
770 }
771
772 dev->issi = 1;
773
774 return 0;
e74a1db0 775 } else if (sup_issi & (1 << 0) || !sup_issi) {
f62b8bb8
AV		 776 return 0;
777 }
778
779 return -ENOTSUPP;
780}
f62b8bb8 781
737a234b
MHY		 782enum {
783 MLX5_INTERFACE_ADDED,
784 MLX5_INTERFACE_ATTACHED,
785};
786
a31208b1
MD		 787static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
788{
789 struct mlx5_device_context *dev_ctx;
790 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
791
917b41aa
AH		 792 if (!mlx5_lag_intf_add(intf, priv))
793 return;
794
737a234b 795 dev_ctx = kzalloc(sizeof(*dev_ctx), GFP_KERNEL);
a31208b1
MD		 796 if (!dev_ctx)
797 return;
798
737a234b 799 dev_ctx->intf = intf;
a31208b1 800 dev_ctx->context = intf->add(dev);
737a234b
MHY		 801 set_bit(MLX5_INTERFACE_ADDED, &dev_ctx->state);
802 if (intf->attach)
803 set_bit(MLX5_INTERFACE_ATTACHED, &dev_ctx->state);
a31208b1
MD		 804
805 if (dev_ctx->context) {
806 spin_lock_irq(&priv->ctx_lock);
807 list_add_tail(&dev_ctx->list, &priv->ctx_list);
808 spin_unlock_irq(&priv->ctx_lock);
809 } else {
810 kfree(dev_ctx);
811 }
812}
813
737a234b
MHY		 814static struct mlx5_device_context *mlx5_get_device(struct mlx5_interface *intf,
815 struct mlx5_priv *priv)
816{
817 struct mlx5_device_context *dev_ctx;
818
819 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
820 if (dev_ctx->intf == intf)
821 return dev_ctx;
822 return NULL;
823}
824
a31208b1
MD		 825static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
826{
827 struct mlx5_device_context *dev_ctx;
828 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
829
737a234b
MHY		 830 dev_ctx = mlx5_get_device(intf, priv);
831 if (!dev_ctx)
832 return;
833
834 spin_lock_irq(&priv->ctx_lock);
835 list_del(&dev_ctx->list);
836 spin_unlock_irq(&priv->ctx_lock);
837
838 if (test_bit(MLX5_INTERFACE_ADDED, &dev_ctx->state))
839 intf->remove(dev, dev_ctx->context);
a31208b1 840
737a234b
MHY		 841 kfree(dev_ctx);
842}
843
844static void mlx5_attach_interface(struct mlx5_interface *intf, struct mlx5_priv *priv)
845{
846 struct mlx5_device_context *dev_ctx;
847 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
848
849 dev_ctx = mlx5_get_device(intf, priv);
850 if (!dev_ctx)
851 return;
852
853 if (intf->attach) {
854 if (test_bit(MLX5_INTERFACE_ATTACHED, &dev_ctx->state))
a31208b1 855 return;
737a234b
MHY		 856 intf->attach(dev, dev_ctx->context);
857 set_bit(MLX5_INTERFACE_ATTACHED, &dev_ctx->state);
858 } else {
859 if (test_bit(MLX5_INTERFACE_ADDED, &dev_ctx->state))
860 return;
861 dev_ctx->context = intf->add(dev);
862 set_bit(MLX5_INTERFACE_ADDED, &dev_ctx->state);
863 }
864}
865
866static void mlx5_attach_device(struct mlx5_core_dev *dev)
867{
868 struct mlx5_priv *priv = &dev->priv;
869 struct mlx5_interface *intf;
870
871 mutex_lock(&mlx5_intf_mutex);
872 list_for_each_entry(intf, &intf_list, list)
873 mlx5_attach_interface(intf, priv);
874 mutex_unlock(&mlx5_intf_mutex);
875}
876
877static void mlx5_detach_interface(struct mlx5_interface *intf, struct mlx5_priv *priv)
878{
879 struct mlx5_device_context *dev_ctx;
880 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
881
882 dev_ctx = mlx5_get_device(intf, priv);
883 if (!dev_ctx)
884 return;
885
886 if (intf->detach) {
887 if (!test_bit(MLX5_INTERFACE_ATTACHED, &dev_ctx->state))
888 return;
889 intf->detach(dev, dev_ctx->context);
890 clear_bit(MLX5_INTERFACE_ATTACHED, &dev_ctx->state);
891 } else {
892 if (!test_bit(MLX5_INTERFACE_ADDED, &dev_ctx->state))
893 return;
894 intf->remove(dev, dev_ctx->context);
895 clear_bit(MLX5_INTERFACE_ADDED, &dev_ctx->state);
896 }
897}
898
899static void mlx5_detach_device(struct mlx5_core_dev *dev)
900{
901 struct mlx5_priv *priv = &dev->priv;
902 struct mlx5_interface *intf;
903
904 mutex_lock(&mlx5_intf_mutex);
905 list_for_each_entry(intf, &intf_list, list)
906 mlx5_detach_interface(intf, priv);
907 mutex_unlock(&mlx5_intf_mutex);
908}
909
910static bool mlx5_device_registered(struct mlx5_core_dev *dev)
911{
912 struct mlx5_priv *priv;
913 bool found = false;
914
915 mutex_lock(&mlx5_intf_mutex);
916 list_for_each_entry(priv, &mlx5_dev_list, dev_list)
917 if (priv == &dev->priv)
918 found = true;
919 mutex_unlock(&mlx5_intf_mutex);
920
921 return found;
a31208b1
MD		 922}
923
924static int mlx5_register_device(struct mlx5_core_dev *dev)
e126ba97
EC		 925{
926 struct mlx5_priv *priv = &dev->priv;
a31208b1
MD		 927 struct mlx5_interface *intf;
928
7907f23a
AH		 929 mutex_lock(&mlx5_intf_mutex);
930 list_add_tail(&priv->dev_list, &mlx5_dev_list);
a31208b1
MD		 931 list_for_each_entry(intf, &intf_list, list)
932 mlx5_add_device(intf, priv);
7907f23a 933 mutex_unlock(&mlx5_intf_mutex);
a31208b1
MD		 934
935 return 0;
936}
937
938static void mlx5_unregister_device(struct mlx5_core_dev *dev)
939{
940 struct mlx5_priv *priv = &dev->priv;
941 struct mlx5_interface *intf;
942
7907f23a 943 mutex_lock(&mlx5_intf_mutex);
a31208b1
MD		 944 list_for_each_entry(intf, &intf_list, list)
945 mlx5_remove_device(intf, priv);
946 list_del(&priv->dev_list);
7907f23a 947 mutex_unlock(&mlx5_intf_mutex);
a31208b1
MD		 948}
949
950int mlx5_register_interface(struct mlx5_interface *intf)
951{
952 struct mlx5_priv *priv;
953
954 if (!intf->add || !intf->remove)
955 return -EINVAL;
956
7907f23a 957 mutex_lock(&mlx5_intf_mutex);
a31208b1 958 list_add_tail(&intf->list, &intf_list);
7907f23a 959 list_for_each_entry(priv, &mlx5_dev_list, dev_list)
a31208b1 960 mlx5_add_device(intf, priv);
7907f23a 961 mutex_unlock(&mlx5_intf_mutex);
a31208b1
MD		 962
963 return 0;
964}
965EXPORT_SYMBOL(mlx5_register_interface);
966
967void mlx5_unregister_interface(struct mlx5_interface *intf)
968{
969 struct mlx5_priv *priv;
970
7907f23a
AH		 971 mutex_lock(&mlx5_intf_mutex);
972 list_for_each_entry(priv, &mlx5_dev_list, dev_list)
a31208b1
MD		 973 mlx5_remove_device(intf, priv);
974 list_del(&intf->list);
7907f23a 975 mutex_unlock(&mlx5_intf_mutex);
a31208b1
MD		 976}
977EXPORT_SYMBOL(mlx5_unregister_interface);
978
979void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
980{
981 struct mlx5_priv *priv = &mdev->priv;
982 struct mlx5_device_context *dev_ctx;
983 unsigned long flags;
984 void *result = NULL;
985
986 spin_lock_irqsave(&priv->ctx_lock, flags);
987
988 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
989 if ((dev_ctx->intf->protocol == protocol) &&
990 dev_ctx->intf->get_dev) {
991 result = dev_ctx->intf->get_dev(dev_ctx->context);
992 break;
993 }
994
995 spin_unlock_irqrestore(&priv->ctx_lock, flags);
996
997 return result;
998}
999EXPORT_SYMBOL(mlx5_get_protocol_dev);
1000
7907f23a
AH		 1001/* Must be called with intf_mutex held */
1002void mlx5_add_dev_by_protocol(struct mlx5_core_dev *dev, int protocol)
1003{
1004 struct mlx5_interface *intf;
1005
1006 list_for_each_entry(intf, &intf_list, list)
1007 if (intf->protocol == protocol) {
1008 mlx5_add_device(intf, &dev->priv);
1009 break;
1010 }
1011}
1012
1013/* Must be called with intf_mutex held */
1014void mlx5_remove_dev_by_protocol(struct mlx5_core_dev *dev, int protocol)
1015{
1016 struct mlx5_interface *intf;
1017
1018 list_for_each_entry(intf, &intf_list, list)
1019 if (intf->protocol == protocol) {
1020 mlx5_remove_device(intf, &dev->priv);
1021 break;
1022 }
1023}
1024
a31208b1
MD		 1025static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1026{
1027 struct pci_dev *pdev = dev->pdev;
1028 int err = 0;
e126ba97 1029
e126ba97
EC		 1030 pci_set_drvdata(dev->pdev, dev);
1031 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
1032 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
1033
1034 mutex_init(&priv->pgdir_mutex);
1035 INIT_LIST_HEAD(&priv->pgdir_list);
1036 spin_lock_init(&priv->mkey_lock);
1037
311c7c71
SM		 1038 mutex_init(&priv->alloc_mutex);
1039
1040 priv->numa_node = dev_to_node(&dev->pdev->dev);
1041
e126ba97
EC		 1042 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
1043 if (!priv->dbg_root)
1044 return -ENOMEM;
1045
89d44f0a 1046 err = mlx5_pci_enable_device(dev);
e126ba97 1047 if (err) {
1a91de28 1048 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 1049 goto err_dbg;
1050 }
1051
1052 err = request_bar(pdev);
1053 if (err) {
1a91de28 1054 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 1055 goto err_disable;
1056 }
1057
1058 pci_set_master(pdev);
1059
1060 err = set_dma_caps(pdev);
1061 if (err) {
1062 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
1063 goto err_clr_master;
1064 }
1065
1066 dev->iseg_base = pci_resource_start(dev->pdev, 0);
1067 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
1068 if (!dev->iseg) {
1069 err = -ENOMEM;
1070 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
1071 goto err_clr_master;
1072 }
a31208b1
MD		 1073
1074 return 0;
1075
1076err_clr_master:
1077 pci_clear_master(dev->pdev);
1078 release_bar(dev->pdev);
1079err_disable:
89d44f0a 1080 mlx5_pci_disable_device(dev);
a31208b1
MD		 1081
1082err_dbg:
1083 debugfs_remove(priv->dbg_root);
1084 return err;
1085}
1086
1087static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1088{
1089 iounmap(dev->iseg);
1090 pci_clear_master(dev->pdev);
1091 release_bar(dev->pdev);
89d44f0a 1092 mlx5_pci_disable_device(dev);
a31208b1
MD		 1093 debugfs_remove(priv->dbg_root);
1094}
1095
1096#define MLX5_IB_MOD "mlx5_ib"
1097static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1098{
1099 struct pci_dev *pdev = dev->pdev;
1100 int err;
1101
89d44f0a 1102 mutex_lock(&dev->intf_state_mutex);
5fc7197d 1103 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
89d44f0a
MD		 1104 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
1105 __func__);
1106 goto out;
1107 }
1108
e126ba97
EC		 1109 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1110 fw_rev_min(dev), fw_rev_sub(dev));
1111
89d44f0a
MD		 1112 /* on load removing any previous indication of internal error, device is
1113 * up
1114 */
1115 dev->state = MLX5_DEVICE_STATE_UP;
1116
e126ba97
EC		 1117 err = mlx5_cmd_init(dev);
1118 if (err) {
1119 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
89d44f0a 1120 goto out_err;
e126ba97
EC		 1121 }
1122
e3297246
EC		 1123 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1124 if (err) {
1125 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1126 FW_INIT_TIMEOUT_MILI);
1127 goto out_err;
1128 }
1129
e126ba97 1130 mlx5_pagealloc_init(dev);
cd23b14b 1131
0b107106 1132 err = mlx5_core_enable_hca(dev, 0);
cd23b14b
EC		 1133 if (err) {
1134 dev_err(&pdev->dev, "enable hca failed\n");
1135 goto err_pagealloc_cleanup;
1136 }
1137
f62b8bb8
AV		 1138 err = mlx5_core_set_issi(dev);
1139 if (err) {
1140 dev_err(&pdev->dev, "failed to set issi\n");
1141 goto err_disable_hca;
1142 }
f62b8bb8 1143
cd23b14b
EC		 1144 err = mlx5_satisfy_startup_pages(dev, 1);
1145 if (err) {
1146 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1147 goto err_disable_hca;
1148 }
1149
e126ba97
EC		 1150 err = set_hca_ctrl(dev);
1151 if (err) {
1152 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 1153 goto reclaim_boot_pages;
e126ba97
EC		 1154 }
1155
1156 err = handle_hca_cap(dev);
1157 if (err) {
1158 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 1159 goto reclaim_boot_pages;
e126ba97
EC		 1160 }
1161
f91e6d89
EBE		 1162 err = handle_hca_cap_atomic(dev);
1163 if (err) {
1164 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1165 goto reclaim_boot_pages;
e126ba97
EC		 1166 }
1167
cd23b14b 1168 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 1169 if (err) {
cd23b14b
EC		 1170 dev_err(&pdev->dev, "failed to allocate init pages\n");
1171 goto reclaim_boot_pages;
e126ba97
EC		 1172 }
1173
1174 err = mlx5_pagealloc_start(dev);
1175 if (err) {
1176 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 1177 goto reclaim_boot_pages;
e126ba97
EC		 1178 }
1179
1180 err = mlx5_cmd_init_hca(dev);
1181 if (err) {
1182 dev_err(&pdev->dev, "init hca failed\n");
1183 goto err_pagealloc_stop;
1184 }
1185
1186 mlx5_start_health_poll(dev);
1187
938fe83c 1188 err = mlx5_query_hca_caps(dev);
e126ba97
EC		 1189 if (err) {
1190 dev_err(&pdev->dev, "query hca failed\n");
1191 goto err_stop_poll;
1192 }
1193
211e6c80 1194 err = mlx5_query_board_id(dev);
e126ba97 1195 if (err) {
211e6c80 1196 dev_err(&pdev->dev, "query board id failed\n");
e126ba97
EC		 1197 goto err_stop_poll;
1198 }
1199
1200 err = mlx5_enable_msix(dev);
1201 if (err) {
1202 dev_err(&pdev->dev, "enable msix failed\n");
1203 goto err_stop_poll;
1204 }
1205
1206 err = mlx5_eq_init(dev);
1207 if (err) {
1208 dev_err(&pdev->dev, "failed to initialize eq\n");
1209 goto disable_msix;
1210 }
1211
1212 err = mlx5_alloc_uuars(dev, &priv->uuari);
1213 if (err) {
1214 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1215 goto err_eq_cleanup;
1216 }
1217
1218 err = mlx5_start_eqs(dev);
1219 if (err) {
1220 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1221 goto err_free_uar;
1222 }
1223
233d05d2
SM		 1224 err = alloc_comp_eqs(dev);
1225 if (err) {
1226 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1227 goto err_stop_eqs;
1228 }
1229
db058a18 1230 err = mlx5_irq_set_affinity_hints(dev);
0ba42241 1231 if (err)
db058a18 1232 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
db058a18 1233
e126ba97
EC		 1234 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1235
1236 mlx5_init_cq_table(dev);
1237 mlx5_init_qp_table(dev);
1238 mlx5_init_srq_table(dev);
a606b0f6 1239 mlx5_init_mkey_table(dev);
e126ba97 1240
86d722ad
MG		 1241 err = mlx5_init_fs(dev);
1242 if (err) {
1243 dev_err(&pdev->dev, "Failed to init flow steering\n");
1244 goto err_fs;
1245 }
1466cc5b
YP		 1246
1247 err = mlx5_init_rl_table(dev);
1248 if (err) {
1249 dev_err(&pdev->dev, "Failed to init rate limiting\n");
1250 goto err_rl;
1251 }
1252
073bb189
SM		 1253#ifdef CONFIG_MLX5_CORE_EN
1254 err = mlx5_eswitch_init(dev);
1255 if (err) {
1256 dev_err(&pdev->dev, "eswitch init failed %d\n", err);
1257 goto err_reg_dev;
1258 }
1259#endif
1260
fc50db98
EC		 1261 err = mlx5_sriov_init(dev);
1262 if (err) {
1263 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1264 goto err_sriov;
1265 }
1266
737a234b
MHY		 1267 if (mlx5_device_registered(dev)) {
1268 mlx5_attach_device(dev);
1269 } else {
1270 err = mlx5_register_device(dev);
1271 if (err) {
1272 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1273 goto err_reg_dev;
1274 }
a31208b1
MD		 1275 }
1276
5fc7197d
MD		 1277 clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1278 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
89d44f0a
MD		 1279out:
1280 mutex_unlock(&dev->intf_state_mutex);
1281
e126ba97
EC		 1282 return 0;
1283
fc50db98 1284err_sriov:
6b6adee3 1285 mlx5_sriov_cleanup(dev);
fc50db98 1286
073bb189
SM		 1287#ifdef CONFIG_MLX5_CORE_EN
1288 mlx5_eswitch_cleanup(dev->priv.eswitch);
1289#endif
a31208b1 1290err_reg_dev:
1466cc5b
YP		 1291 mlx5_cleanup_rl_table(dev);
1292err_rl:
86d722ad
MG		 1293 mlx5_cleanup_fs(dev);
1294err_fs:
a606b0f6 1295 mlx5_cleanup_mkey_table(dev);
a31208b1
MD		 1296 mlx5_cleanup_srq_table(dev);
1297 mlx5_cleanup_qp_table(dev);
1298 mlx5_cleanup_cq_table(dev);
1299 mlx5_irq_clear_affinity_hints(dev);
db058a18
SM		 1300 free_comp_eqs(dev);
1301
233d05d2
SM		 1302err_stop_eqs:
1303 mlx5_stop_eqs(dev);
1304
e126ba97
EC		 1305err_free_uar:
1306 mlx5_free_uuars(dev, &priv->uuari);
1307
1308err_eq_cleanup:
1309 mlx5_eq_cleanup(dev);
1310
1311disable_msix:
1312 mlx5_disable_msix(dev);
1313
1314err_stop_poll:
1315 mlx5_stop_health_poll(dev);
1bde6e30
EC		 1316 if (mlx5_cmd_teardown_hca(dev)) {
1317 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
89d44f0a 1318 goto out_err;
1bde6e30 1319 }
e126ba97
EC		 1320
1321err_pagealloc_stop:
1322 mlx5_pagealloc_stop(dev);
1323
cd23b14b 1324reclaim_boot_pages:
e126ba97
EC		 1325 mlx5_reclaim_startup_pages(dev);
1326
cd23b14b 1327err_disable_hca:
0b107106 1328 mlx5_core_disable_hca(dev, 0);
cd23b14b 1329
e126ba97
EC		 1330err_pagealloc_cleanup:
1331 mlx5_pagealloc_cleanup(dev);
1332 mlx5_cmd_cleanup(dev);
1333
89d44f0a
MD		 1334out_err:
1335 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1336 mutex_unlock(&dev->intf_state_mutex);
1337
e126ba97
EC		 1338 return err;
1339}
e126ba97 1340
a31208b1 1341static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
e126ba97 1342{
89d44f0a 1343 int err = 0;
e126ba97 1344
89d44f0a 1345 mutex_lock(&dev->intf_state_mutex);
5fc7197d 1346 if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) {
89d44f0a
MD		 1347 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1348 __func__);
1349 goto out;
1350 }
6b6adee3 1351
737a234b
MHY		 1352 if (mlx5_device_registered(dev))
1353 mlx5_detach_device(dev);
1354
6b6adee3 1355 mlx5_sriov_cleanup(dev);
073bb189
SM		 1356#ifdef CONFIG_MLX5_CORE_EN
1357 mlx5_eswitch_cleanup(dev->priv.eswitch);
1358#endif
1466cc5b 1359 mlx5_cleanup_rl_table(dev);
86d722ad 1360 mlx5_cleanup_fs(dev);
a606b0f6 1361 mlx5_cleanup_mkey_table(dev);
e126ba97
EC		 1362 mlx5_cleanup_srq_table(dev);
1363 mlx5_cleanup_qp_table(dev);
1364 mlx5_cleanup_cq_table(dev);
db058a18 1365 mlx5_irq_clear_affinity_hints(dev);
233d05d2 1366 free_comp_eqs(dev);
e126ba97
EC		 1367 mlx5_stop_eqs(dev);
1368 mlx5_free_uuars(dev, &priv->uuari);
1369 mlx5_eq_cleanup(dev);
1370 mlx5_disable_msix(dev);
1371 mlx5_stop_health_poll(dev);
ac6ea6e8
EC		 1372 err = mlx5_cmd_teardown_hca(dev);
1373 if (err) {
1bde6e30 1374 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
ac6ea6e8 1375 goto out;
1bde6e30 1376 }
e126ba97
EC		 1377 mlx5_pagealloc_stop(dev);
1378 mlx5_reclaim_startup_pages(dev);
0b107106 1379 mlx5_core_disable_hca(dev, 0);
e126ba97
EC		 1380 mlx5_pagealloc_cleanup(dev);
1381 mlx5_cmd_cleanup(dev);
9603b61d 1382
ac6ea6e8 1383out:
5fc7197d
MD		 1384 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1385 set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
89d44f0a 1386 mutex_unlock(&dev->intf_state_mutex);
ac6ea6e8 1387 return err;
9603b61d 1388}
64613d94 1389
89d44f0a 1390void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
ac6ea6e8 1391 unsigned long param)
9603b61d
JM		 1392{
1393 struct mlx5_priv *priv = &dev->priv;
1394 struct mlx5_device_context *dev_ctx;
1395 unsigned long flags;
1396
1397 spin_lock_irqsave(&priv->ctx_lock, flags);
1398
1399 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1400 if (dev_ctx->intf->event)
4d2f9bbb 1401 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
9603b61d
JM		 1402
1403 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1404}
1405
1406struct mlx5_core_event_handler {
1407 void (*event)(struct mlx5_core_dev *dev,
1408 enum mlx5_dev_event event,
1409 void *data);
1410};
1411
feae9087
OG		 1412static const struct devlink_ops mlx5_devlink_ops = {
1413#ifdef CONFIG_MLX5_CORE_EN
1414 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1415 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1416#endif
1417};
f66f049f 1418
9603b61d
JM		 1419static int init_one(struct pci_dev *pdev,
1420 const struct pci_device_id *id)
1421{
1422 struct mlx5_core_dev *dev;
feae9087 1423 struct devlink *devlink;
9603b61d
JM		 1424 struct mlx5_priv *priv;
1425 int err;
1426
feae9087
OG		 1427 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1428 if (!devlink) {
9603b61d
JM		 1429 dev_err(&pdev->dev, "kzalloc failed\n");
1430 return -ENOMEM;
1431 }
feae9087
OG		 1432
1433 dev = devlink_priv(devlink);
9603b61d 1434 priv = &dev->priv;
fc50db98 1435 priv->pci_dev_data = id->driver_data;
9603b61d
JM		 1436
1437 pci_set_drvdata(pdev, dev);
1438
1439 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
2974ab6e
SM		 1440 mlx5_core_warn(dev,
1441 "selected profile out of range, selecting default (%d)\n",
1442 MLX5_DEFAULT_PROF);
9603b61d
JM		 1443 prof_sel = MLX5_DEFAULT_PROF;
1444 }
1445 dev->profile = &profile[prof_sel];
a31208b1 1446 dev->pdev = pdev;
9603b61d
JM		 1447 dev->event = mlx5_core_event;
1448
364d1798
EC		 1449 INIT_LIST_HEAD(&priv->ctx_list);
1450 spin_lock_init(&priv->ctx_lock);
89d44f0a
MD		 1451 mutex_init(&dev->pci_status_mutex);
1452 mutex_init(&dev->intf_state_mutex);
a31208b1 1453 err = mlx5_pci_init(dev, priv);
9603b61d 1454 if (err) {
a31208b1
MD		 1455 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1456 goto clean_dev;
9603b61d
JM		 1457 }
1458
ac6ea6e8
EC		 1459 err = mlx5_health_init(dev);
1460 if (err) {
1461 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1462 goto close_pci;
1463 }
1464
a31208b1 1465 err = mlx5_load_one(dev, priv);
9603b61d 1466 if (err) {
a31208b1 1467 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
ac6ea6e8 1468 goto clean_health;
9603b61d 1469 }
737a234b
MHY		 1470 err = request_module_nowait(MLX5_IB_MOD);
1471 if (err)
1472 pr_info("failed request module on %s\n", MLX5_IB_MOD);
9603b61d 1473
feae9087
OG		 1474 err = devlink_register(devlink, &pdev->dev);
1475 if (err)
1476 goto clean_load;
1477
9603b61d
JM		 1478 return 0;
1479
feae9087
OG		 1480clean_load:
1481 mlx5_unload_one(dev, priv);
ac6ea6e8
EC		 1482clean_health:
1483 mlx5_health_cleanup(dev);
a31208b1
MD		 1484close_pci:
1485 mlx5_pci_close(dev, priv);
1486clean_dev:
1487 pci_set_drvdata(pdev, NULL);
feae9087 1488 devlink_free(devlink);
a31208b1 1489
9603b61d
JM		 1490 return err;
1491}
a31208b1 1492
9603b61d
JM		 1493static void remove_one(struct pci_dev *pdev)
1494{
1495 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
feae9087 1496 struct devlink *devlink = priv_to_devlink(dev);
a31208b1 1497 struct mlx5_priv *priv = &dev->priv;
9603b61d 1498
feae9087 1499 devlink_unregister(devlink);
737a234b
MHY		 1500 mlx5_unregister_device(dev);
1501
a31208b1
MD		 1502 if (mlx5_unload_one(dev, priv)) {
1503 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
ac6ea6e8 1504 mlx5_health_cleanup(dev);
a31208b1
MD		 1505 return;
1506 }
737a234b 1507
ac6ea6e8 1508 mlx5_health_cleanup(dev);
a31208b1
MD		 1509 mlx5_pci_close(dev, priv);
1510 pci_set_drvdata(pdev, NULL);
feae9087 1511 devlink_free(devlink);
9603b61d
JM		 1512}
1513
89d44f0a
MD		 1514static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1515 pci_channel_state_t state)
1516{
1517 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1518 struct mlx5_priv *priv = &dev->priv;
1519
1520 dev_info(&pdev->dev, "%s was called\n", __func__);
1521 mlx5_enter_error_state(dev);
1522 mlx5_unload_one(dev, priv);
1061c90f 1523 pci_save_state(pdev);
89d44f0a
MD		 1524 mlx5_pci_disable_device(dev);
1525 return state == pci_channel_io_perm_failure ?
1526 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1527}
1528
d57847dc
DJ		 1529/* wait for the device to show vital signs by waiting
1530 * for the health counter to start counting.
89d44f0a 1531 */
d57847dc 1532static int wait_vital(struct pci_dev *pdev)
89d44f0a
MD		 1533{
1534 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1535 struct mlx5_core_health *health = &dev->priv.health;
1536 const int niter = 100;
d57847dc 1537 u32 last_count = 0;
89d44f0a 1538 u32 count;
89d44f0a
MD		 1539 int i;
1540
89d44f0a
MD		 1541 for (i = 0; i < niter; i++) {
1542 count = ioread32be(health->health_counter);
1543 if (count && count != 0xffffffff) {
d57847dc
DJ		 1544 if (last_count && last_count != count) {
1545 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1546 return 0;
1547 }
1548 last_count = count;
89d44f0a
MD		 1549 }
1550 msleep(50);
1551 }
1552
d57847dc 1553 return -ETIMEDOUT;
89d44f0a
MD		 1554}
1555
1061c90f 1556static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
89d44f0a
MD		 1557{
1558 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
89d44f0a
MD		 1559 int err;
1560
1561 dev_info(&pdev->dev, "%s was called\n", __func__);
1562
1061c90f 1563 err = mlx5_pci_enable_device(dev);
d57847dc 1564 if (err) {
1061c90f
MHY		 1565 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1566 , __func__, err);
1567 return PCI_ERS_RESULT_DISCONNECT;
1568 }
1569
1570 pci_set_master(pdev);
1571 pci_restore_state(pdev);
1572
1573 if (wait_vital(pdev)) {
d57847dc 1574 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1061c90f 1575 return PCI_ERS_RESULT_DISCONNECT;
d57847dc 1576 }
89d44f0a 1577
1061c90f
MHY		 1578 return PCI_ERS_RESULT_RECOVERED;
1579}
1580
1581void mlx5_disable_device(struct mlx5_core_dev *dev)
1582{
1583 mlx5_pci_err_detected(dev->pdev, 0);
1584}
1585
1586static void mlx5_pci_resume(struct pci_dev *pdev)
1587{
1588 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1589 struct mlx5_priv *priv = &dev->priv;
1590 int err;
1591
1592 dev_info(&pdev->dev, "%s was called\n", __func__);
1593
89d44f0a
MD		 1594 err = mlx5_load_one(dev, priv);
1595 if (err)
1596 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1597 , __func__, err);
1598 else
1599 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1600}
1601
1602static const struct pci_error_handlers mlx5_err_handler = {
1603 .error_detected = mlx5_pci_err_detected,
1604 .slot_reset = mlx5_pci_slot_reset,
1605 .resume = mlx5_pci_resume
1606};
1607
5fc7197d
MD		 1608static void shutdown(struct pci_dev *pdev)
1609{
1610 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1611 struct mlx5_priv *priv = &dev->priv;
1612
1613 dev_info(&pdev->dev, "Shutdown was called\n");
1614 /* Notify mlx5 clients that the kernel is being shut down */
1615 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state);
1616 mlx5_unload_one(dev, priv);
1617 mlx5_pci_disable_device(dev);
1618}
1619
9603b61d 1620static const struct pci_device_id mlx5_core_pci_table[] = {
fc50db98
EC		 1621 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1622 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1623 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1624 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1625 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1626 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
7092fe86 1627 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
64dbbdfe 1628 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
7092fe86 1629 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5, PCIe 4.0 */
9603b61d
JM		 1630 { 0, }
1631};
1632
1633MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1634
1635static struct pci_driver mlx5_core_driver = {
1636 .name = DRIVER_NAME,
1637 .id_table = mlx5_core_pci_table,
1638 .probe = init_one,
89d44f0a 1639 .remove = remove_one,
5fc7197d 1640 .shutdown = shutdown,
fc50db98
EC		 1641 .err_handler = &mlx5_err_handler,
1642 .sriov_configure = mlx5_core_sriov_configure,
9603b61d 1643};
e126ba97
EC		 1644
1645static int __init init(void)
1646{
1647 int err;
1648
1649 mlx5_register_debugfs();
e126ba97 1650
9603b61d
JM		 1651 err = pci_register_driver(&mlx5_core_driver);
1652 if (err)
ac6ea6e8 1653 goto err_debug;
9603b61d 1654
f62b8bb8
AV		 1655#ifdef CONFIG_MLX5_CORE_EN
1656 mlx5e_init();
1657#endif
1658
e126ba97
EC		 1659 return 0;
1660
e126ba97
EC		 1661err_debug:
1662 mlx5_unregister_debugfs();
1663 return err;
1664}
1665
1666static void __exit cleanup(void)
1667{
f62b8bb8
AV		 1668#ifdef CONFIG_MLX5_CORE_EN
1669 mlx5e_cleanup();
1670#endif
9603b61d 1671 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1672 mlx5_unregister_debugfs();
1673}
1674
1675module_init(init);
1676module_exit(cleanup);
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