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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
adec640e | 33 | #include <linux/highmem.h> |
e126ba97 EC |
34 | #include <linux/module.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/io-mapping.h> | |
db058a18 | 41 | #include <linux/interrupt.h> |
e3297246 | 42 | #include <linux/delay.h> |
e126ba97 EC |
43 | #include <linux/mlx5/driver.h> |
44 | #include <linux/mlx5/cq.h> | |
45 | #include <linux/mlx5/qp.h> | |
46 | #include <linux/mlx5/srq.h> | |
47 | #include <linux/debugfs.h> | |
f66f049f | 48 | #include <linux/kmod.h> |
b775516b | 49 | #include <linux/mlx5/mlx5_ifc.h> |
5a7b27eb MG |
50 | #ifdef CONFIG_RFS_ACCEL |
51 | #include <linux/cpu_rmap.h> | |
52 | #endif | |
feae9087 | 53 | #include <net/devlink.h> |
e126ba97 | 54 | #include "mlx5_core.h" |
86d722ad | 55 | #include "fs_core.h" |
073bb189 SM |
56 | #ifdef CONFIG_MLX5_CORE_EN |
57 | #include "eswitch.h" | |
58 | #endif | |
e126ba97 | 59 | |
e126ba97 | 60 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); |
4ae6c18c | 61 | MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); |
e126ba97 EC |
62 | MODULE_LICENSE("Dual BSD/GPL"); |
63 | MODULE_VERSION(DRIVER_VERSION); | |
64 | ||
f663ad98 KH |
65 | unsigned int mlx5_core_debug_mask; |
66 | module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); | |
e126ba97 EC |
67 | MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); |
68 | ||
9603b61d | 69 | #define MLX5_DEFAULT_PROF 2 |
f663ad98 KH |
70 | static unsigned int prof_sel = MLX5_DEFAULT_PROF; |
71 | module_param_named(prof_sel, prof_sel, uint, 0444); | |
9603b61d JM |
72 | MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); |
73 | ||
f91e6d89 EBE |
74 | enum { |
75 | MLX5_ATOMIC_REQ_MODE_BE = 0x0, | |
76 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, | |
77 | }; | |
78 | ||
9603b61d JM |
79 | static struct mlx5_profile profile[] = { |
80 | [0] = { | |
81 | .mask = 0, | |
82 | }, | |
83 | [1] = { | |
84 | .mask = MLX5_PROF_MASK_QP_SIZE, | |
85 | .log_max_qp = 12, | |
86 | }, | |
87 | [2] = { | |
88 | .mask = MLX5_PROF_MASK_QP_SIZE | | |
89 | MLX5_PROF_MASK_MR_CACHE, | |
90 | .log_max_qp = 17, | |
91 | .mr_cache[0] = { | |
92 | .size = 500, | |
93 | .limit = 250 | |
94 | }, | |
95 | .mr_cache[1] = { | |
96 | .size = 500, | |
97 | .limit = 250 | |
98 | }, | |
99 | .mr_cache[2] = { | |
100 | .size = 500, | |
101 | .limit = 250 | |
102 | }, | |
103 | .mr_cache[3] = { | |
104 | .size = 500, | |
105 | .limit = 250 | |
106 | }, | |
107 | .mr_cache[4] = { | |
108 | .size = 500, | |
109 | .limit = 250 | |
110 | }, | |
111 | .mr_cache[5] = { | |
112 | .size = 500, | |
113 | .limit = 250 | |
114 | }, | |
115 | .mr_cache[6] = { | |
116 | .size = 500, | |
117 | .limit = 250 | |
118 | }, | |
119 | .mr_cache[7] = { | |
120 | .size = 500, | |
121 | .limit = 250 | |
122 | }, | |
123 | .mr_cache[8] = { | |
124 | .size = 500, | |
125 | .limit = 250 | |
126 | }, | |
127 | .mr_cache[9] = { | |
128 | .size = 500, | |
129 | .limit = 250 | |
130 | }, | |
131 | .mr_cache[10] = { | |
132 | .size = 500, | |
133 | .limit = 250 | |
134 | }, | |
135 | .mr_cache[11] = { | |
136 | .size = 500, | |
137 | .limit = 250 | |
138 | }, | |
139 | .mr_cache[12] = { | |
140 | .size = 64, | |
141 | .limit = 32 | |
142 | }, | |
143 | .mr_cache[13] = { | |
144 | .size = 32, | |
145 | .limit = 16 | |
146 | }, | |
147 | .mr_cache[14] = { | |
148 | .size = 16, | |
149 | .limit = 8 | |
150 | }, | |
151 | .mr_cache[15] = { | |
152 | .size = 8, | |
153 | .limit = 4 | |
154 | }, | |
155 | }, | |
156 | }; | |
e126ba97 | 157 | |
e3297246 EC |
158 | #define FW_INIT_TIMEOUT_MILI 2000 |
159 | #define FW_INIT_WAIT_MS 2 | |
160 | ||
161 | static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) | |
162 | { | |
163 | unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); | |
164 | int err = 0; | |
165 | ||
166 | while (fw_initializing(dev)) { | |
167 | if (time_after(jiffies, end)) { | |
168 | err = -EBUSY; | |
169 | break; | |
170 | } | |
171 | msleep(FW_INIT_WAIT_MS); | |
172 | } | |
173 | ||
174 | return err; | |
175 | } | |
176 | ||
e126ba97 EC |
177 | static int set_dma_caps(struct pci_dev *pdev) |
178 | { | |
179 | int err; | |
180 | ||
181 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
182 | if (err) { | |
1a91de28 | 183 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); |
e126ba97 EC |
184 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
185 | if (err) { | |
1a91de28 | 186 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); |
e126ba97 EC |
187 | return err; |
188 | } | |
189 | } | |
190 | ||
191 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
192 | if (err) { | |
193 | dev_warn(&pdev->dev, | |
1a91de28 | 194 | "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); |
e126ba97 EC |
195 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
196 | if (err) { | |
197 | dev_err(&pdev->dev, | |
1a91de28 | 198 | "Can't set consistent PCI DMA mask, aborting\n"); |
e126ba97 EC |
199 | return err; |
200 | } | |
201 | } | |
202 | ||
203 | dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); | |
204 | return err; | |
205 | } | |
206 | ||
89d44f0a MD |
207 | static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) |
208 | { | |
209 | struct pci_dev *pdev = dev->pdev; | |
210 | int err = 0; | |
211 | ||
212 | mutex_lock(&dev->pci_status_mutex); | |
213 | if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { | |
214 | err = pci_enable_device(pdev); | |
215 | if (!err) | |
216 | dev->pci_status = MLX5_PCI_STATUS_ENABLED; | |
217 | } | |
218 | mutex_unlock(&dev->pci_status_mutex); | |
219 | ||
220 | return err; | |
221 | } | |
222 | ||
223 | static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) | |
224 | { | |
225 | struct pci_dev *pdev = dev->pdev; | |
226 | ||
227 | mutex_lock(&dev->pci_status_mutex); | |
228 | if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { | |
229 | pci_disable_device(pdev); | |
230 | dev->pci_status = MLX5_PCI_STATUS_DISABLED; | |
231 | } | |
232 | mutex_unlock(&dev->pci_status_mutex); | |
233 | } | |
234 | ||
e126ba97 EC |
235 | static int request_bar(struct pci_dev *pdev) |
236 | { | |
237 | int err = 0; | |
238 | ||
239 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
1a91de28 | 240 | dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); |
e126ba97 EC |
241 | return -ENODEV; |
242 | } | |
243 | ||
244 | err = pci_request_regions(pdev, DRIVER_NAME); | |
245 | if (err) | |
246 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); | |
247 | ||
248 | return err; | |
249 | } | |
250 | ||
251 | static void release_bar(struct pci_dev *pdev) | |
252 | { | |
253 | pci_release_regions(pdev); | |
254 | } | |
255 | ||
256 | static int mlx5_enable_msix(struct mlx5_core_dev *dev) | |
257 | { | |
db058a18 SM |
258 | struct mlx5_priv *priv = &dev->priv; |
259 | struct mlx5_eq_table *table = &priv->eq_table; | |
938fe83c | 260 | int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); |
e126ba97 | 261 | int nvec; |
e126ba97 EC |
262 | int i; |
263 | ||
938fe83c SM |
264 | nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() + |
265 | MLX5_EQ_VEC_COMP_BASE; | |
e126ba97 EC |
266 | nvec = min_t(int, nvec, num_eqs); |
267 | if (nvec <= MLX5_EQ_VEC_COMP_BASE) | |
268 | return -ENOMEM; | |
269 | ||
db058a18 SM |
270 | priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL); |
271 | ||
272 | priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL); | |
273 | if (!priv->msix_arr || !priv->irq_info) | |
274 | goto err_free_msix; | |
e126ba97 EC |
275 | |
276 | for (i = 0; i < nvec; i++) | |
db058a18 | 277 | priv->msix_arr[i].entry = i; |
e126ba97 | 278 | |
db058a18 | 279 | nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, |
3a9e161a | 280 | MLX5_EQ_VEC_COMP_BASE + 1, nvec); |
f3c9407b AG |
281 | if (nvec < 0) |
282 | return nvec; | |
e126ba97 | 283 | |
f3c9407b | 284 | table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; |
e126ba97 EC |
285 | |
286 | return 0; | |
db058a18 SM |
287 | |
288 | err_free_msix: | |
289 | kfree(priv->irq_info); | |
290 | kfree(priv->msix_arr); | |
291 | return -ENOMEM; | |
e126ba97 EC |
292 | } |
293 | ||
294 | static void mlx5_disable_msix(struct mlx5_core_dev *dev) | |
295 | { | |
db058a18 | 296 | struct mlx5_priv *priv = &dev->priv; |
e126ba97 EC |
297 | |
298 | pci_disable_msix(dev->pdev); | |
db058a18 SM |
299 | kfree(priv->irq_info); |
300 | kfree(priv->msix_arr); | |
e126ba97 EC |
301 | } |
302 | ||
303 | struct mlx5_reg_host_endianess { | |
304 | u8 he; | |
305 | u8 rsvd[15]; | |
306 | }; | |
307 | ||
87b8de49 EC |
308 | |
309 | #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) | |
310 | ||
311 | enum { | |
c7a08ac7 EC |
312 | MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | |
313 | MLX5_DEV_CAP_FLAG_DCT, | |
87b8de49 EC |
314 | }; |
315 | ||
2974ab6e | 316 | static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) |
c7a08ac7 EC |
317 | { |
318 | switch (size) { | |
319 | case 128: | |
320 | return 0; | |
321 | case 256: | |
322 | return 1; | |
323 | case 512: | |
324 | return 2; | |
325 | case 1024: | |
326 | return 3; | |
327 | case 2048: | |
328 | return 4; | |
329 | case 4096: | |
330 | return 5; | |
331 | default: | |
2974ab6e | 332 | mlx5_core_warn(dev, "invalid pkey table size %d\n", size); |
c7a08ac7 EC |
333 | return 0; |
334 | } | |
335 | } | |
336 | ||
b06e7de8 LR |
337 | static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, |
338 | enum mlx5_cap_type cap_type, | |
339 | enum mlx5_cap_mode cap_mode) | |
c7a08ac7 | 340 | { |
b775516b EC |
341 | u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; |
342 | int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); | |
938fe83c SM |
343 | void *out, *hca_caps; |
344 | u16 opmod = (cap_type << 1) | (cap_mode & 0x01); | |
e126ba97 EC |
345 | int err; |
346 | ||
b775516b EC |
347 | memset(in, 0, sizeof(in)); |
348 | out = kzalloc(out_sz, GFP_KERNEL); | |
c7a08ac7 | 349 | if (!out) |
e126ba97 | 350 | return -ENOMEM; |
938fe83c | 351 | |
b775516b EC |
352 | MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); |
353 | MLX5_SET(query_hca_cap_in, in, op_mod, opmod); | |
354 | err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); | |
c7a08ac7 | 355 | if (err) { |
938fe83c SM |
356 | mlx5_core_warn(dev, |
357 | "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", | |
358 | cap_type, cap_mode, err); | |
e126ba97 EC |
359 | goto query_ex; |
360 | } | |
c7a08ac7 | 361 | |
938fe83c SM |
362 | hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); |
363 | ||
364 | switch (cap_mode) { | |
365 | case HCA_CAP_OPMOD_GET_MAX: | |
366 | memcpy(dev->hca_caps_max[cap_type], hca_caps, | |
367 | MLX5_UN_SZ_BYTES(hca_cap_union)); | |
368 | break; | |
369 | case HCA_CAP_OPMOD_GET_CUR: | |
370 | memcpy(dev->hca_caps_cur[cap_type], hca_caps, | |
371 | MLX5_UN_SZ_BYTES(hca_cap_union)); | |
372 | break; | |
373 | default: | |
374 | mlx5_core_warn(dev, | |
375 | "Tried to query dev cap type(%x) with wrong opmode(%x)\n", | |
376 | cap_type, cap_mode); | |
377 | err = -EINVAL; | |
378 | break; | |
379 | } | |
c7a08ac7 EC |
380 | query_ex: |
381 | kfree(out); | |
382 | return err; | |
383 | } | |
384 | ||
b06e7de8 LR |
385 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) |
386 | { | |
387 | int ret; | |
388 | ||
389 | ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); | |
390 | if (ret) | |
391 | return ret; | |
392 | return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); | |
393 | } | |
394 | ||
f91e6d89 | 395 | static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) |
c7a08ac7 | 396 | { |
c4f287c4 | 397 | u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; |
e126ba97 | 398 | |
b775516b | 399 | MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); |
f91e6d89 | 400 | MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); |
c4f287c4 | 401 | return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); |
c7a08ac7 EC |
402 | } |
403 | ||
f91e6d89 EBE |
404 | static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) |
405 | { | |
406 | void *set_ctx; | |
407 | void *set_hca_cap; | |
408 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); | |
409 | int req_endianness; | |
410 | int err; | |
411 | ||
412 | if (MLX5_CAP_GEN(dev, atomic)) { | |
b06e7de8 | 413 | err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); |
f91e6d89 EBE |
414 | if (err) |
415 | return err; | |
416 | } else { | |
417 | return 0; | |
418 | } | |
419 | ||
420 | req_endianness = | |
421 | MLX5_CAP_ATOMIC(dev, | |
422 | supported_atomic_req_8B_endianess_mode_1); | |
423 | ||
424 | if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) | |
425 | return 0; | |
426 | ||
427 | set_ctx = kzalloc(set_sz, GFP_KERNEL); | |
428 | if (!set_ctx) | |
429 | return -ENOMEM; | |
430 | ||
431 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); | |
432 | ||
433 | /* Set requestor to host endianness */ | |
434 | MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode, | |
435 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); | |
436 | ||
437 | err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); | |
438 | ||
439 | kfree(set_ctx); | |
440 | return err; | |
441 | } | |
442 | ||
c7a08ac7 EC |
443 | static int handle_hca_cap(struct mlx5_core_dev *dev) |
444 | { | |
b775516b | 445 | void *set_ctx = NULL; |
c7a08ac7 | 446 | struct mlx5_profile *prof = dev->profile; |
c7a08ac7 | 447 | int err = -ENOMEM; |
b775516b | 448 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
938fe83c | 449 | void *set_hca_cap; |
c7a08ac7 | 450 | |
b775516b | 451 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
c7a08ac7 | 452 | if (!set_ctx) |
e126ba97 | 453 | goto query_ex; |
e126ba97 | 454 | |
b06e7de8 | 455 | err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); |
e126ba97 EC |
456 | if (err) |
457 | goto query_ex; | |
458 | ||
938fe83c SM |
459 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, |
460 | capability); | |
461 | memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL], | |
462 | MLX5_ST_SZ_BYTES(cmd_hca_cap)); | |
463 | ||
464 | mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", | |
707c4602 | 465 | mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), |
938fe83c | 466 | 128); |
c7a08ac7 | 467 | /* we limit the size of the pkey table to 128 entries for now */ |
938fe83c | 468 | MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, |
2974ab6e | 469 | to_fw_pkey_sz(dev, 128)); |
c7a08ac7 EC |
470 | |
471 | if (prof->mask & MLX5_PROF_MASK_QP_SIZE) | |
938fe83c SM |
472 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, |
473 | prof->log_max_qp); | |
c7a08ac7 | 474 | |
938fe83c SM |
475 | /* disable cmdif checksum */ |
476 | MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); | |
c7a08ac7 | 477 | |
fe1e1876 CS |
478 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); |
479 | ||
f91e6d89 EBE |
480 | err = set_caps(dev, set_ctx, set_sz, |
481 | MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); | |
c7a08ac7 | 482 | |
e126ba97 | 483 | query_ex: |
e126ba97 | 484 | kfree(set_ctx); |
e126ba97 EC |
485 | return err; |
486 | } | |
487 | ||
488 | static int set_hca_ctrl(struct mlx5_core_dev *dev) | |
489 | { | |
490 | struct mlx5_reg_host_endianess he_in; | |
491 | struct mlx5_reg_host_endianess he_out; | |
492 | int err; | |
493 | ||
fc50db98 EC |
494 | if (!mlx5_core_is_pf(dev)) |
495 | return 0; | |
496 | ||
e126ba97 EC |
497 | memset(&he_in, 0, sizeof(he_in)); |
498 | he_in.he = MLX5_SET_HOST_ENDIANNESS; | |
499 | err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), | |
500 | &he_out, sizeof(he_out), | |
501 | MLX5_REG_HOST_ENDIANNESS, 0, 1); | |
502 | return err; | |
503 | } | |
504 | ||
0b107106 | 505 | int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 506 | { |
c4f287c4 SM |
507 | u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; |
508 | u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; | |
cd23b14b | 509 | |
0b107106 EC |
510 | MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); |
511 | MLX5_SET(enable_hca_in, in, function_id, func_id); | |
c4f287c4 | 512 | return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); |
cd23b14b EC |
513 | } |
514 | ||
0b107106 | 515 | int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 516 | { |
c4f287c4 SM |
517 | u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; |
518 | u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; | |
cd23b14b | 519 | |
0b107106 EC |
520 | MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); |
521 | MLX5_SET(disable_hca_in, in, function_id, func_id); | |
c4f287c4 | 522 | return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); |
cd23b14b EC |
523 | } |
524 | ||
b0844444 EBE |
525 | cycle_t mlx5_read_internal_timer(struct mlx5_core_dev *dev) |
526 | { | |
527 | u32 timer_h, timer_h1, timer_l; | |
528 | ||
529 | timer_h = ioread32be(&dev->iseg->internal_timer_h); | |
530 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
531 | timer_h1 = ioread32be(&dev->iseg->internal_timer_h); | |
532 | if (timer_h != timer_h1) /* wrap around */ | |
533 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
534 | ||
535 | return (cycle_t)timer_l | (cycle_t)timer_h1 << 32; | |
536 | } | |
537 | ||
db058a18 SM |
538 | static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i) |
539 | { | |
540 | struct mlx5_priv *priv = &mdev->priv; | |
541 | struct msix_entry *msix = priv->msix_arr; | |
542 | int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector; | |
311c7c71 | 543 | int numa_node = priv->numa_node; |
db058a18 SM |
544 | int err; |
545 | ||
546 | if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) { | |
547 | mlx5_core_warn(mdev, "zalloc_cpumask_var failed"); | |
548 | return -ENOMEM; | |
549 | } | |
550 | ||
dda922c8 DM |
551 | cpumask_set_cpu(cpumask_local_spread(i, numa_node), |
552 | priv->irq_info[i].mask); | |
db058a18 SM |
553 | |
554 | err = irq_set_affinity_hint(irq, priv->irq_info[i].mask); | |
555 | if (err) { | |
556 | mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x", | |
557 | irq); | |
558 | goto err_clear_mask; | |
559 | } | |
560 | ||
561 | return 0; | |
562 | ||
563 | err_clear_mask: | |
564 | free_cpumask_var(priv->irq_info[i].mask); | |
565 | return err; | |
566 | } | |
567 | ||
568 | static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i) | |
569 | { | |
570 | struct mlx5_priv *priv = &mdev->priv; | |
571 | struct msix_entry *msix = priv->msix_arr; | |
572 | int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector; | |
573 | ||
574 | irq_set_affinity_hint(irq, NULL); | |
575 | free_cpumask_var(priv->irq_info[i].mask); | |
576 | } | |
577 | ||
578 | static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev) | |
579 | { | |
580 | int err; | |
581 | int i; | |
582 | ||
583 | for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) { | |
584 | err = mlx5_irq_set_affinity_hint(mdev, i); | |
585 | if (err) | |
586 | goto err_out; | |
587 | } | |
588 | ||
589 | return 0; | |
590 | ||
591 | err_out: | |
592 | for (i--; i >= 0; i--) | |
593 | mlx5_irq_clear_affinity_hint(mdev, i); | |
594 | ||
595 | return err; | |
596 | } | |
597 | ||
598 | static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev) | |
599 | { | |
600 | int i; | |
601 | ||
602 | for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) | |
603 | mlx5_irq_clear_affinity_hint(mdev, i); | |
604 | } | |
605 | ||
0b6e26ce DT |
606 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
607 | unsigned int *irqn) | |
233d05d2 SM |
608 | { |
609 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
610 | struct mlx5_eq *eq, *n; | |
611 | int err = -ENOENT; | |
612 | ||
613 | spin_lock(&table->lock); | |
614 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
615 | if (eq->index == vector) { | |
616 | *eqn = eq->eqn; | |
617 | *irqn = eq->irqn; | |
618 | err = 0; | |
619 | break; | |
620 | } | |
621 | } | |
622 | spin_unlock(&table->lock); | |
623 | ||
624 | return err; | |
625 | } | |
626 | EXPORT_SYMBOL(mlx5_vector2eqn); | |
627 | ||
94c6825e MB |
628 | struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn) |
629 | { | |
630 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
631 | struct mlx5_eq *eq; | |
632 | ||
633 | spin_lock(&table->lock); | |
634 | list_for_each_entry(eq, &table->comp_eqs_list, list) | |
635 | if (eq->eqn == eqn) { | |
636 | spin_unlock(&table->lock); | |
637 | return eq; | |
638 | } | |
639 | ||
640 | spin_unlock(&table->lock); | |
641 | ||
642 | return ERR_PTR(-ENOENT); | |
643 | } | |
644 | ||
233d05d2 SM |
645 | static void free_comp_eqs(struct mlx5_core_dev *dev) |
646 | { | |
647 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
648 | struct mlx5_eq *eq, *n; | |
649 | ||
5a7b27eb MG |
650 | #ifdef CONFIG_RFS_ACCEL |
651 | if (dev->rmap) { | |
652 | free_irq_cpu_rmap(dev->rmap); | |
653 | dev->rmap = NULL; | |
654 | } | |
655 | #endif | |
233d05d2 SM |
656 | spin_lock(&table->lock); |
657 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
658 | list_del(&eq->list); | |
659 | spin_unlock(&table->lock); | |
660 | if (mlx5_destroy_unmap_eq(dev, eq)) | |
661 | mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", | |
662 | eq->eqn); | |
663 | kfree(eq); | |
664 | spin_lock(&table->lock); | |
665 | } | |
666 | spin_unlock(&table->lock); | |
667 | } | |
668 | ||
669 | static int alloc_comp_eqs(struct mlx5_core_dev *dev) | |
670 | { | |
671 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
db058a18 | 672 | char name[MLX5_MAX_IRQ_NAME]; |
233d05d2 SM |
673 | struct mlx5_eq *eq; |
674 | int ncomp_vec; | |
675 | int nent; | |
676 | int err; | |
677 | int i; | |
678 | ||
679 | INIT_LIST_HEAD(&table->comp_eqs_list); | |
680 | ncomp_vec = table->num_comp_vectors; | |
681 | nent = MLX5_COMP_EQ_SIZE; | |
5a7b27eb MG |
682 | #ifdef CONFIG_RFS_ACCEL |
683 | dev->rmap = alloc_irq_cpu_rmap(ncomp_vec); | |
684 | if (!dev->rmap) | |
685 | return -ENOMEM; | |
686 | #endif | |
233d05d2 SM |
687 | for (i = 0; i < ncomp_vec; i++) { |
688 | eq = kzalloc(sizeof(*eq), GFP_KERNEL); | |
689 | if (!eq) { | |
690 | err = -ENOMEM; | |
691 | goto clean; | |
692 | } | |
693 | ||
5a7b27eb MG |
694 | #ifdef CONFIG_RFS_ACCEL |
695 | irq_cpu_rmap_add(dev->rmap, | |
696 | dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector); | |
697 | #endif | |
db058a18 | 698 | snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); |
233d05d2 SM |
699 | err = mlx5_create_map_eq(dev, eq, |
700 | i + MLX5_EQ_VEC_COMP_BASE, nent, 0, | |
701 | name, &dev->priv.uuari.uars[0]); | |
702 | if (err) { | |
703 | kfree(eq); | |
704 | goto clean; | |
705 | } | |
706 | mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); | |
707 | eq->index = i; | |
708 | spin_lock(&table->lock); | |
709 | list_add_tail(&eq->list, &table->comp_eqs_list); | |
710 | spin_unlock(&table->lock); | |
711 | } | |
712 | ||
713 | return 0; | |
714 | ||
715 | clean: | |
716 | free_comp_eqs(dev); | |
717 | return err; | |
718 | } | |
719 | ||
f62b8bb8 AV |
720 | static int mlx5_core_set_issi(struct mlx5_core_dev *dev) |
721 | { | |
c4f287c4 SM |
722 | u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; |
723 | u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; | |
f62b8bb8 | 724 | u32 sup_issi; |
c4f287c4 | 725 | int err; |
f62b8bb8 AV |
726 | |
727 | MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); | |
c4f287c4 SM |
728 | err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), |
729 | query_out, sizeof(query_out)); | |
f62b8bb8 | 730 | if (err) { |
c4f287c4 SM |
731 | u32 syndrome; |
732 | u8 status; | |
733 | ||
734 | mlx5_cmd_mbox_status(query_out, &status, &syndrome); | |
735 | if (status == MLX5_CMD_STAT_BAD_OP_ERR) { | |
f62b8bb8 AV |
736 | pr_debug("Only ISSI 0 is supported\n"); |
737 | return 0; | |
738 | } | |
739 | ||
c4f287c4 | 740 | pr_err("failed to query ISSI err(%d)\n", err); |
f62b8bb8 AV |
741 | return err; |
742 | } | |
743 | ||
744 | sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); | |
745 | ||
746 | if (sup_issi & (1 << 1)) { | |
c4f287c4 SM |
747 | u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; |
748 | u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; | |
f62b8bb8 AV |
749 | |
750 | MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); | |
751 | MLX5_SET(set_issi_in, set_in, current_issi, 1); | |
c4f287c4 SM |
752 | err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), |
753 | set_out, sizeof(set_out)); | |
f62b8bb8 | 754 | if (err) { |
c4f287c4 | 755 | pr_err("failed to set ISSI=1 err(%d)\n", err); |
f62b8bb8 AV |
756 | return err; |
757 | } | |
758 | ||
759 | dev->issi = 1; | |
760 | ||
761 | return 0; | |
e74a1db0 | 762 | } else if (sup_issi & (1 << 0) || !sup_issi) { |
f62b8bb8 AV |
763 | return 0; |
764 | } | |
765 | ||
766 | return -ENOTSUPP; | |
767 | } | |
f62b8bb8 | 768 | |
7907f23a | 769 | |
a31208b1 MD |
770 | static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
771 | { | |
772 | struct pci_dev *pdev = dev->pdev; | |
773 | int err = 0; | |
e126ba97 | 774 | |
e126ba97 EC |
775 | pci_set_drvdata(dev->pdev, dev); |
776 | strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); | |
777 | priv->name[MLX5_MAX_NAME_LEN - 1] = 0; | |
778 | ||
779 | mutex_init(&priv->pgdir_mutex); | |
780 | INIT_LIST_HEAD(&priv->pgdir_list); | |
781 | spin_lock_init(&priv->mkey_lock); | |
782 | ||
311c7c71 SM |
783 | mutex_init(&priv->alloc_mutex); |
784 | ||
785 | priv->numa_node = dev_to_node(&dev->pdev->dev); | |
786 | ||
e126ba97 EC |
787 | priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root); |
788 | if (!priv->dbg_root) | |
789 | return -ENOMEM; | |
790 | ||
89d44f0a | 791 | err = mlx5_pci_enable_device(dev); |
e126ba97 | 792 | if (err) { |
1a91de28 | 793 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
e126ba97 EC |
794 | goto err_dbg; |
795 | } | |
796 | ||
797 | err = request_bar(pdev); | |
798 | if (err) { | |
1a91de28 | 799 | dev_err(&pdev->dev, "error requesting BARs, aborting\n"); |
e126ba97 EC |
800 | goto err_disable; |
801 | } | |
802 | ||
803 | pci_set_master(pdev); | |
804 | ||
805 | err = set_dma_caps(pdev); | |
806 | if (err) { | |
807 | dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n"); | |
808 | goto err_clr_master; | |
809 | } | |
810 | ||
811 | dev->iseg_base = pci_resource_start(dev->pdev, 0); | |
812 | dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); | |
813 | if (!dev->iseg) { | |
814 | err = -ENOMEM; | |
815 | dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n"); | |
816 | goto err_clr_master; | |
817 | } | |
a31208b1 MD |
818 | |
819 | return 0; | |
820 | ||
821 | err_clr_master: | |
822 | pci_clear_master(dev->pdev); | |
823 | release_bar(dev->pdev); | |
824 | err_disable: | |
89d44f0a | 825 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
826 | |
827 | err_dbg: | |
828 | debugfs_remove(priv->dbg_root); | |
829 | return err; | |
830 | } | |
831 | ||
832 | static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) | |
833 | { | |
834 | iounmap(dev->iseg); | |
835 | pci_clear_master(dev->pdev); | |
836 | release_bar(dev->pdev); | |
89d44f0a | 837 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
838 | debugfs_remove(priv->dbg_root); |
839 | } | |
840 | ||
59211bd3 MHY |
841 | static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
842 | { | |
843 | struct pci_dev *pdev = dev->pdev; | |
844 | int err; | |
845 | ||
59211bd3 MHY |
846 | err = mlx5_query_board_id(dev); |
847 | if (err) { | |
848 | dev_err(&pdev->dev, "query board id failed\n"); | |
849 | goto out; | |
850 | } | |
851 | ||
852 | err = mlx5_eq_init(dev); | |
853 | if (err) { | |
854 | dev_err(&pdev->dev, "failed to initialize eq\n"); | |
855 | goto out; | |
856 | } | |
857 | ||
858 | MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); | |
859 | ||
860 | err = mlx5_init_cq_table(dev); | |
861 | if (err) { | |
862 | dev_err(&pdev->dev, "failed to initialize cq table\n"); | |
863 | goto err_eq_cleanup; | |
864 | } | |
865 | ||
866 | mlx5_init_qp_table(dev); | |
867 | ||
868 | mlx5_init_srq_table(dev); | |
869 | ||
870 | mlx5_init_mkey_table(dev); | |
871 | ||
872 | err = mlx5_init_rl_table(dev); | |
873 | if (err) { | |
874 | dev_err(&pdev->dev, "Failed to init rate limiting\n"); | |
875 | goto err_tables_cleanup; | |
876 | } | |
877 | ||
c2d6e31a MHY |
878 | #ifdef CONFIG_MLX5_CORE_EN |
879 | err = mlx5_eswitch_init(dev); | |
880 | if (err) { | |
881 | dev_err(&pdev->dev, "Failed to init eswitch %d\n", err); | |
882 | goto err_rl_cleanup; | |
883 | } | |
884 | #endif | |
885 | ||
886 | err = mlx5_sriov_init(dev); | |
887 | if (err) { | |
888 | dev_err(&pdev->dev, "Failed to init sriov %d\n", err); | |
889 | goto err_eswitch_cleanup; | |
890 | } | |
891 | ||
59211bd3 MHY |
892 | return 0; |
893 | ||
c2d6e31a MHY |
894 | err_eswitch_cleanup: |
895 | #ifdef CONFIG_MLX5_CORE_EN | |
896 | mlx5_eswitch_cleanup(dev->priv.eswitch); | |
897 | ||
898 | err_rl_cleanup: | |
899 | #endif | |
900 | mlx5_cleanup_rl_table(dev); | |
901 | ||
59211bd3 MHY |
902 | err_tables_cleanup: |
903 | mlx5_cleanup_mkey_table(dev); | |
904 | mlx5_cleanup_srq_table(dev); | |
905 | mlx5_cleanup_qp_table(dev); | |
906 | mlx5_cleanup_cq_table(dev); | |
907 | ||
908 | err_eq_cleanup: | |
909 | mlx5_eq_cleanup(dev); | |
910 | ||
911 | out: | |
912 | return err; | |
913 | } | |
914 | ||
915 | static void mlx5_cleanup_once(struct mlx5_core_dev *dev) | |
916 | { | |
c2d6e31a MHY |
917 | mlx5_sriov_cleanup(dev); |
918 | #ifdef CONFIG_MLX5_CORE_EN | |
919 | mlx5_eswitch_cleanup(dev->priv.eswitch); | |
920 | #endif | |
59211bd3 MHY |
921 | mlx5_cleanup_rl_table(dev); |
922 | mlx5_cleanup_mkey_table(dev); | |
923 | mlx5_cleanup_srq_table(dev); | |
924 | mlx5_cleanup_qp_table(dev); | |
925 | mlx5_cleanup_cq_table(dev); | |
926 | mlx5_eq_cleanup(dev); | |
927 | } | |
928 | ||
929 | static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, | |
930 | bool boot) | |
a31208b1 MD |
931 | { |
932 | struct pci_dev *pdev = dev->pdev; | |
933 | int err; | |
934 | ||
89d44f0a | 935 | mutex_lock(&dev->intf_state_mutex); |
5fc7197d | 936 | if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
89d44f0a MD |
937 | dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", |
938 | __func__); | |
939 | goto out; | |
940 | } | |
941 | ||
e126ba97 EC |
942 | dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), |
943 | fw_rev_min(dev), fw_rev_sub(dev)); | |
944 | ||
89d44f0a MD |
945 | /* on load removing any previous indication of internal error, device is |
946 | * up | |
947 | */ | |
948 | dev->state = MLX5_DEVICE_STATE_UP; | |
949 | ||
e126ba97 EC |
950 | err = mlx5_cmd_init(dev); |
951 | if (err) { | |
952 | dev_err(&pdev->dev, "Failed initializing command interface, aborting\n"); | |
89d44f0a | 953 | goto out_err; |
e126ba97 EC |
954 | } |
955 | ||
e3297246 EC |
956 | err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); |
957 | if (err) { | |
958 | dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n", | |
959 | FW_INIT_TIMEOUT_MILI); | |
960 | goto out_err; | |
961 | } | |
962 | ||
0b107106 | 963 | err = mlx5_core_enable_hca(dev, 0); |
cd23b14b EC |
964 | if (err) { |
965 | dev_err(&pdev->dev, "enable hca failed\n"); | |
59211bd3 | 966 | goto err_cmd_cleanup; |
cd23b14b EC |
967 | } |
968 | ||
f62b8bb8 AV |
969 | err = mlx5_core_set_issi(dev); |
970 | if (err) { | |
971 | dev_err(&pdev->dev, "failed to set issi\n"); | |
972 | goto err_disable_hca; | |
973 | } | |
f62b8bb8 | 974 | |
cd23b14b EC |
975 | err = mlx5_satisfy_startup_pages(dev, 1); |
976 | if (err) { | |
977 | dev_err(&pdev->dev, "failed to allocate boot pages\n"); | |
978 | goto err_disable_hca; | |
979 | } | |
980 | ||
e126ba97 EC |
981 | err = set_hca_ctrl(dev); |
982 | if (err) { | |
983 | dev_err(&pdev->dev, "set_hca_ctrl failed\n"); | |
cd23b14b | 984 | goto reclaim_boot_pages; |
e126ba97 EC |
985 | } |
986 | ||
987 | err = handle_hca_cap(dev); | |
988 | if (err) { | |
989 | dev_err(&pdev->dev, "handle_hca_cap failed\n"); | |
cd23b14b | 990 | goto reclaim_boot_pages; |
e126ba97 EC |
991 | } |
992 | ||
f91e6d89 EBE |
993 | err = handle_hca_cap_atomic(dev); |
994 | if (err) { | |
995 | dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n"); | |
996 | goto reclaim_boot_pages; | |
e126ba97 EC |
997 | } |
998 | ||
cd23b14b | 999 | err = mlx5_satisfy_startup_pages(dev, 0); |
e126ba97 | 1000 | if (err) { |
cd23b14b EC |
1001 | dev_err(&pdev->dev, "failed to allocate init pages\n"); |
1002 | goto reclaim_boot_pages; | |
e126ba97 EC |
1003 | } |
1004 | ||
1005 | err = mlx5_pagealloc_start(dev); | |
1006 | if (err) { | |
1007 | dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n"); | |
cd23b14b | 1008 | goto reclaim_boot_pages; |
e126ba97 EC |
1009 | } |
1010 | ||
1011 | err = mlx5_cmd_init_hca(dev); | |
1012 | if (err) { | |
1013 | dev_err(&pdev->dev, "init hca failed\n"); | |
1014 | goto err_pagealloc_stop; | |
1015 | } | |
1016 | ||
1017 | mlx5_start_health_poll(dev); | |
1018 | ||
bba1574c DJ |
1019 | err = mlx5_query_hca_caps(dev); |
1020 | if (err) { | |
1021 | dev_err(&pdev->dev, "query hca failed\n"); | |
1022 | goto err_stop_poll; | |
1023 | } | |
1024 | ||
59211bd3 MHY |
1025 | if (boot && mlx5_init_once(dev, priv)) { |
1026 | dev_err(&pdev->dev, "sw objs init failed\n"); | |
e126ba97 EC |
1027 | goto err_stop_poll; |
1028 | } | |
1029 | ||
1030 | err = mlx5_enable_msix(dev); | |
1031 | if (err) { | |
1032 | dev_err(&pdev->dev, "enable msix failed\n"); | |
59211bd3 | 1033 | goto err_cleanup_once; |
e126ba97 EC |
1034 | } |
1035 | ||
1036 | err = mlx5_alloc_uuars(dev, &priv->uuari); | |
1037 | if (err) { | |
1038 | dev_err(&pdev->dev, "Failed allocating uar, aborting\n"); | |
59211bd3 | 1039 | goto err_disable_msix; |
e126ba97 EC |
1040 | } |
1041 | ||
1042 | err = mlx5_start_eqs(dev); | |
1043 | if (err) { | |
1044 | dev_err(&pdev->dev, "Failed to start pages and async EQs\n"); | |
1045 | goto err_free_uar; | |
1046 | } | |
1047 | ||
233d05d2 SM |
1048 | err = alloc_comp_eqs(dev); |
1049 | if (err) { | |
1050 | dev_err(&pdev->dev, "Failed to alloc completion EQs\n"); | |
1051 | goto err_stop_eqs; | |
1052 | } | |
1053 | ||
db058a18 | 1054 | err = mlx5_irq_set_affinity_hints(dev); |
59211bd3 | 1055 | if (err) { |
db058a18 | 1056 | dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n"); |
59211bd3 MHY |
1057 | goto err_affinity_hints; |
1058 | } | |
e126ba97 | 1059 | |
86d722ad MG |
1060 | err = mlx5_init_fs(dev); |
1061 | if (err) { | |
1062 | dev_err(&pdev->dev, "Failed to init flow steering\n"); | |
1063 | goto err_fs; | |
1064 | } | |
1466cc5b | 1065 | |
073bb189 | 1066 | #ifdef CONFIG_MLX5_CORE_EN |
c2d6e31a | 1067 | mlx5_eswitch_attach(dev->priv.eswitch); |
073bb189 SM |
1068 | #endif |
1069 | ||
c2d6e31a | 1070 | err = mlx5_sriov_attach(dev); |
fc50db98 EC |
1071 | if (err) { |
1072 | dev_err(&pdev->dev, "sriov init failed %d\n", err); | |
1073 | goto err_sriov; | |
1074 | } | |
1075 | ||
737a234b MHY |
1076 | if (mlx5_device_registered(dev)) { |
1077 | mlx5_attach_device(dev); | |
1078 | } else { | |
1079 | err = mlx5_register_device(dev); | |
1080 | if (err) { | |
1081 | dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); | |
1082 | goto err_reg_dev; | |
1083 | } | |
a31208b1 MD |
1084 | } |
1085 | ||
5fc7197d MD |
1086 | clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state); |
1087 | set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); | |
89d44f0a MD |
1088 | out: |
1089 | mutex_unlock(&dev->intf_state_mutex); | |
1090 | ||
e126ba97 EC |
1091 | return 0; |
1092 | ||
59211bd3 | 1093 | err_reg_dev: |
c2d6e31a | 1094 | mlx5_sriov_detach(dev); |
fc50db98 | 1095 | |
59211bd3 | 1096 | err_sriov: |
073bb189 | 1097 | #ifdef CONFIG_MLX5_CORE_EN |
c2d6e31a | 1098 | mlx5_eswitch_detach(dev->priv.eswitch); |
073bb189 | 1099 | #endif |
86d722ad | 1100 | mlx5_cleanup_fs(dev); |
59211bd3 | 1101 | |
86d722ad | 1102 | err_fs: |
a31208b1 | 1103 | mlx5_irq_clear_affinity_hints(dev); |
59211bd3 MHY |
1104 | |
1105 | err_affinity_hints: | |
db058a18 SM |
1106 | free_comp_eqs(dev); |
1107 | ||
233d05d2 SM |
1108 | err_stop_eqs: |
1109 | mlx5_stop_eqs(dev); | |
1110 | ||
e126ba97 EC |
1111 | err_free_uar: |
1112 | mlx5_free_uuars(dev, &priv->uuari); | |
1113 | ||
59211bd3 | 1114 | err_disable_msix: |
e126ba97 EC |
1115 | mlx5_disable_msix(dev); |
1116 | ||
59211bd3 MHY |
1117 | err_cleanup_once: |
1118 | if (boot) | |
1119 | mlx5_cleanup_once(dev); | |
1120 | ||
e126ba97 EC |
1121 | err_stop_poll: |
1122 | mlx5_stop_health_poll(dev); | |
1bde6e30 EC |
1123 | if (mlx5_cmd_teardown_hca(dev)) { |
1124 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); | |
89d44f0a | 1125 | goto out_err; |
1bde6e30 | 1126 | } |
e126ba97 EC |
1127 | |
1128 | err_pagealloc_stop: | |
1129 | mlx5_pagealloc_stop(dev); | |
1130 | ||
cd23b14b | 1131 | reclaim_boot_pages: |
e126ba97 EC |
1132 | mlx5_reclaim_startup_pages(dev); |
1133 | ||
cd23b14b | 1134 | err_disable_hca: |
0b107106 | 1135 | mlx5_core_disable_hca(dev, 0); |
cd23b14b | 1136 | |
59211bd3 | 1137 | err_cmd_cleanup: |
e126ba97 EC |
1138 | mlx5_cmd_cleanup(dev); |
1139 | ||
89d44f0a MD |
1140 | out_err: |
1141 | dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; | |
1142 | mutex_unlock(&dev->intf_state_mutex); | |
1143 | ||
e126ba97 EC |
1144 | return err; |
1145 | } | |
e126ba97 | 1146 | |
59211bd3 MHY |
1147 | static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, |
1148 | bool cleanup) | |
e126ba97 | 1149 | { |
89d44f0a | 1150 | int err = 0; |
e126ba97 | 1151 | |
89d44f0a | 1152 | mutex_lock(&dev->intf_state_mutex); |
5fc7197d | 1153 | if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) { |
89d44f0a MD |
1154 | dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", |
1155 | __func__); | |
59211bd3 MHY |
1156 | if (cleanup) |
1157 | mlx5_cleanup_once(dev); | |
89d44f0a MD |
1158 | goto out; |
1159 | } | |
6b6adee3 | 1160 | |
737a234b MHY |
1161 | if (mlx5_device_registered(dev)) |
1162 | mlx5_detach_device(dev); | |
1163 | ||
c2d6e31a | 1164 | mlx5_sriov_detach(dev); |
073bb189 | 1165 | #ifdef CONFIG_MLX5_CORE_EN |
c2d6e31a | 1166 | mlx5_eswitch_detach(dev->priv.eswitch); |
073bb189 | 1167 | #endif |
86d722ad | 1168 | mlx5_cleanup_fs(dev); |
db058a18 | 1169 | mlx5_irq_clear_affinity_hints(dev); |
233d05d2 | 1170 | free_comp_eqs(dev); |
e126ba97 EC |
1171 | mlx5_stop_eqs(dev); |
1172 | mlx5_free_uuars(dev, &priv->uuari); | |
e126ba97 | 1173 | mlx5_disable_msix(dev); |
59211bd3 MHY |
1174 | if (cleanup) |
1175 | mlx5_cleanup_once(dev); | |
e126ba97 | 1176 | mlx5_stop_health_poll(dev); |
ac6ea6e8 EC |
1177 | err = mlx5_cmd_teardown_hca(dev); |
1178 | if (err) { | |
1bde6e30 | 1179 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); |
ac6ea6e8 | 1180 | goto out; |
1bde6e30 | 1181 | } |
e126ba97 EC |
1182 | mlx5_pagealloc_stop(dev); |
1183 | mlx5_reclaim_startup_pages(dev); | |
0b107106 | 1184 | mlx5_core_disable_hca(dev, 0); |
e126ba97 | 1185 | mlx5_cmd_cleanup(dev); |
9603b61d | 1186 | |
ac6ea6e8 | 1187 | out: |
5fc7197d MD |
1188 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
1189 | set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state); | |
89d44f0a | 1190 | mutex_unlock(&dev->intf_state_mutex); |
ac6ea6e8 | 1191 | return err; |
9603b61d | 1192 | } |
64613d94 | 1193 | |
9603b61d JM |
1194 | struct mlx5_core_event_handler { |
1195 | void (*event)(struct mlx5_core_dev *dev, | |
1196 | enum mlx5_dev_event event, | |
1197 | void *data); | |
1198 | }; | |
1199 | ||
feae9087 OG |
1200 | static const struct devlink_ops mlx5_devlink_ops = { |
1201 | #ifdef CONFIG_MLX5_CORE_EN | |
1202 | .eswitch_mode_set = mlx5_devlink_eswitch_mode_set, | |
1203 | .eswitch_mode_get = mlx5_devlink_eswitch_mode_get, | |
1204 | #endif | |
1205 | }; | |
f66f049f | 1206 | |
59211bd3 | 1207 | #define MLX5_IB_MOD "mlx5_ib" |
9603b61d JM |
1208 | static int init_one(struct pci_dev *pdev, |
1209 | const struct pci_device_id *id) | |
1210 | { | |
1211 | struct mlx5_core_dev *dev; | |
feae9087 | 1212 | struct devlink *devlink; |
9603b61d JM |
1213 | struct mlx5_priv *priv; |
1214 | int err; | |
1215 | ||
feae9087 OG |
1216 | devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev)); |
1217 | if (!devlink) { | |
9603b61d JM |
1218 | dev_err(&pdev->dev, "kzalloc failed\n"); |
1219 | return -ENOMEM; | |
1220 | } | |
feae9087 OG |
1221 | |
1222 | dev = devlink_priv(devlink); | |
9603b61d | 1223 | priv = &dev->priv; |
fc50db98 | 1224 | priv->pci_dev_data = id->driver_data; |
9603b61d JM |
1225 | |
1226 | pci_set_drvdata(pdev, dev); | |
1227 | ||
0e97a340 HN |
1228 | dev->pdev = pdev; |
1229 | dev->event = mlx5_core_event; | |
9603b61d | 1230 | dev->profile = &profile[prof_sel]; |
9603b61d | 1231 | |
364d1798 EC |
1232 | INIT_LIST_HEAD(&priv->ctx_list); |
1233 | spin_lock_init(&priv->ctx_lock); | |
89d44f0a MD |
1234 | mutex_init(&dev->pci_status_mutex); |
1235 | mutex_init(&dev->intf_state_mutex); | |
a31208b1 | 1236 | err = mlx5_pci_init(dev, priv); |
9603b61d | 1237 | if (err) { |
a31208b1 MD |
1238 | dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err); |
1239 | goto clean_dev; | |
9603b61d JM |
1240 | } |
1241 | ||
ac6ea6e8 EC |
1242 | err = mlx5_health_init(dev); |
1243 | if (err) { | |
1244 | dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err); | |
1245 | goto close_pci; | |
1246 | } | |
1247 | ||
59211bd3 MHY |
1248 | mlx5_pagealloc_init(dev); |
1249 | ||
1250 | err = mlx5_load_one(dev, priv, true); | |
9603b61d | 1251 | if (err) { |
a31208b1 | 1252 | dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err); |
ac6ea6e8 | 1253 | goto clean_health; |
9603b61d | 1254 | } |
59211bd3 | 1255 | |
737a234b MHY |
1256 | err = request_module_nowait(MLX5_IB_MOD); |
1257 | if (err) | |
1258 | pr_info("failed request module on %s\n", MLX5_IB_MOD); | |
9603b61d | 1259 | |
feae9087 OG |
1260 | err = devlink_register(devlink, &pdev->dev); |
1261 | if (err) | |
1262 | goto clean_load; | |
1263 | ||
9603b61d JM |
1264 | return 0; |
1265 | ||
feae9087 | 1266 | clean_load: |
59211bd3 | 1267 | mlx5_unload_one(dev, priv, true); |
ac6ea6e8 | 1268 | clean_health: |
59211bd3 | 1269 | mlx5_pagealloc_cleanup(dev); |
ac6ea6e8 | 1270 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1271 | close_pci: |
1272 | mlx5_pci_close(dev, priv); | |
1273 | clean_dev: | |
1274 | pci_set_drvdata(pdev, NULL); | |
feae9087 | 1275 | devlink_free(devlink); |
a31208b1 | 1276 | |
9603b61d JM |
1277 | return err; |
1278 | } | |
a31208b1 | 1279 | |
9603b61d JM |
1280 | static void remove_one(struct pci_dev *pdev) |
1281 | { | |
1282 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
feae9087 | 1283 | struct devlink *devlink = priv_to_devlink(dev); |
a31208b1 | 1284 | struct mlx5_priv *priv = &dev->priv; |
9603b61d | 1285 | |
feae9087 | 1286 | devlink_unregister(devlink); |
737a234b MHY |
1287 | mlx5_unregister_device(dev); |
1288 | ||
59211bd3 | 1289 | if (mlx5_unload_one(dev, priv, true)) { |
a31208b1 | 1290 | dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); |
ac6ea6e8 | 1291 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1292 | return; |
1293 | } | |
737a234b | 1294 | |
59211bd3 | 1295 | mlx5_pagealloc_cleanup(dev); |
ac6ea6e8 | 1296 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1297 | mlx5_pci_close(dev, priv); |
1298 | pci_set_drvdata(pdev, NULL); | |
feae9087 | 1299 | devlink_free(devlink); |
9603b61d JM |
1300 | } |
1301 | ||
89d44f0a MD |
1302 | static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, |
1303 | pci_channel_state_t state) | |
1304 | { | |
1305 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1306 | struct mlx5_priv *priv = &dev->priv; | |
1307 | ||
1308 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
04c0c1ab | 1309 | |
89d44f0a | 1310 | mlx5_enter_error_state(dev); |
59211bd3 | 1311 | mlx5_unload_one(dev, priv, false); |
05ac2c0b MHY |
1312 | /* In case of kernel call save the pci state and drain health wq */ |
1313 | if (state) { | |
1314 | pci_save_state(pdev); | |
1315 | mlx5_drain_health_wq(dev); | |
1316 | mlx5_pci_disable_device(dev); | |
1317 | } | |
1318 | ||
89d44f0a MD |
1319 | return state == pci_channel_io_perm_failure ? |
1320 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
1321 | } | |
1322 | ||
d57847dc DJ |
1323 | /* wait for the device to show vital signs by waiting |
1324 | * for the health counter to start counting. | |
89d44f0a | 1325 | */ |
d57847dc | 1326 | static int wait_vital(struct pci_dev *pdev) |
89d44f0a MD |
1327 | { |
1328 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1329 | struct mlx5_core_health *health = &dev->priv.health; | |
1330 | const int niter = 100; | |
d57847dc | 1331 | u32 last_count = 0; |
89d44f0a | 1332 | u32 count; |
89d44f0a MD |
1333 | int i; |
1334 | ||
89d44f0a MD |
1335 | for (i = 0; i < niter; i++) { |
1336 | count = ioread32be(health->health_counter); | |
1337 | if (count && count != 0xffffffff) { | |
d57847dc DJ |
1338 | if (last_count && last_count != count) { |
1339 | dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); | |
1340 | return 0; | |
1341 | } | |
1342 | last_count = count; | |
89d44f0a MD |
1343 | } |
1344 | msleep(50); | |
1345 | } | |
1346 | ||
d57847dc | 1347 | return -ETIMEDOUT; |
89d44f0a MD |
1348 | } |
1349 | ||
1061c90f | 1350 | static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) |
89d44f0a MD |
1351 | { |
1352 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
89d44f0a MD |
1353 | int err; |
1354 | ||
1355 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1356 | ||
1061c90f | 1357 | err = mlx5_pci_enable_device(dev); |
d57847dc | 1358 | if (err) { |
1061c90f MHY |
1359 | dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" |
1360 | , __func__, err); | |
1361 | return PCI_ERS_RESULT_DISCONNECT; | |
1362 | } | |
1363 | ||
1364 | pci_set_master(pdev); | |
1365 | pci_restore_state(pdev); | |
1366 | ||
1367 | if (wait_vital(pdev)) { | |
d57847dc | 1368 | dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__); |
1061c90f | 1369 | return PCI_ERS_RESULT_DISCONNECT; |
d57847dc | 1370 | } |
89d44f0a | 1371 | |
1061c90f MHY |
1372 | return PCI_ERS_RESULT_RECOVERED; |
1373 | } | |
1374 | ||
1061c90f MHY |
1375 | static void mlx5_pci_resume(struct pci_dev *pdev) |
1376 | { | |
1377 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1378 | struct mlx5_priv *priv = &dev->priv; | |
1379 | int err; | |
1380 | ||
1381 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1382 | ||
59211bd3 | 1383 | err = mlx5_load_one(dev, priv, false); |
89d44f0a MD |
1384 | if (err) |
1385 | dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" | |
1386 | , __func__, err); | |
1387 | else | |
1388 | dev_info(&pdev->dev, "%s: device recovered\n", __func__); | |
1389 | } | |
1390 | ||
1391 | static const struct pci_error_handlers mlx5_err_handler = { | |
1392 | .error_detected = mlx5_pci_err_detected, | |
1393 | .slot_reset = mlx5_pci_slot_reset, | |
1394 | .resume = mlx5_pci_resume | |
1395 | }; | |
1396 | ||
5fc7197d MD |
1397 | static void shutdown(struct pci_dev *pdev) |
1398 | { | |
1399 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1400 | struct mlx5_priv *priv = &dev->priv; | |
1401 | ||
1402 | dev_info(&pdev->dev, "Shutdown was called\n"); | |
1403 | /* Notify mlx5 clients that the kernel is being shut down */ | |
1404 | set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state); | |
59211bd3 | 1405 | mlx5_unload_one(dev, priv, false); |
5fc7197d MD |
1406 | mlx5_pci_disable_device(dev); |
1407 | } | |
1408 | ||
9603b61d | 1409 | static const struct pci_device_id mlx5_core_pci_table[] = { |
fc50db98 EC |
1410 | { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */ |
1411 | { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ | |
1412 | { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */ | |
1413 | { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ | |
1414 | { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */ | |
1415 | { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ | |
7092fe86 | 1416 | { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ |
64dbbdfe | 1417 | { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ |
7092fe86 | 1418 | { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5, PCIe 4.0 */ |
9603b61d JM |
1419 | { 0, } |
1420 | }; | |
1421 | ||
1422 | MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); | |
1423 | ||
04c0c1ab MHY |
1424 | void mlx5_disable_device(struct mlx5_core_dev *dev) |
1425 | { | |
1426 | mlx5_pci_err_detected(dev->pdev, 0); | |
1427 | } | |
1428 | ||
1429 | void mlx5_recover_device(struct mlx5_core_dev *dev) | |
1430 | { | |
1431 | mlx5_pci_disable_device(dev); | |
1432 | if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) | |
1433 | mlx5_pci_resume(dev->pdev); | |
1434 | } | |
1435 | ||
9603b61d JM |
1436 | static struct pci_driver mlx5_core_driver = { |
1437 | .name = DRIVER_NAME, | |
1438 | .id_table = mlx5_core_pci_table, | |
1439 | .probe = init_one, | |
89d44f0a | 1440 | .remove = remove_one, |
5fc7197d | 1441 | .shutdown = shutdown, |
fc50db98 EC |
1442 | .err_handler = &mlx5_err_handler, |
1443 | .sriov_configure = mlx5_core_sriov_configure, | |
9603b61d | 1444 | }; |
e126ba97 | 1445 | |
f663ad98 KH |
1446 | static void mlx5_core_verify_params(void) |
1447 | { | |
1448 | if (prof_sel >= ARRAY_SIZE(profile)) { | |
1449 | pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", | |
1450 | prof_sel, | |
1451 | ARRAY_SIZE(profile) - 1, | |
1452 | MLX5_DEFAULT_PROF); | |
1453 | prof_sel = MLX5_DEFAULT_PROF; | |
1454 | } | |
1455 | } | |
1456 | ||
e126ba97 EC |
1457 | static int __init init(void) |
1458 | { | |
1459 | int err; | |
1460 | ||
f663ad98 | 1461 | mlx5_core_verify_params(); |
e126ba97 | 1462 | mlx5_register_debugfs(); |
e126ba97 | 1463 | |
9603b61d JM |
1464 | err = pci_register_driver(&mlx5_core_driver); |
1465 | if (err) | |
ac6ea6e8 | 1466 | goto err_debug; |
9603b61d | 1467 | |
f62b8bb8 AV |
1468 | #ifdef CONFIG_MLX5_CORE_EN |
1469 | mlx5e_init(); | |
1470 | #endif | |
1471 | ||
e126ba97 EC |
1472 | return 0; |
1473 | ||
e126ba97 EC |
1474 | err_debug: |
1475 | mlx5_unregister_debugfs(); | |
1476 | return err; | |
1477 | } | |
1478 | ||
1479 | static void __exit cleanup(void) | |
1480 | { | |
f62b8bb8 AV |
1481 | #ifdef CONFIG_MLX5_CORE_EN |
1482 | mlx5e_cleanup(); | |
1483 | #endif | |
9603b61d | 1484 | pci_unregister_driver(&mlx5_core_driver); |
e126ba97 EC |
1485 | mlx5_unregister_debugfs(); |
1486 | } | |
1487 | ||
1488 | module_init(init); | |
1489 | module_exit(cleanup); |