[thirdparty/kernel/stable.git] / drivers / net / ethernet / pensando / ionic / ionic_dev.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */

#ifndef _IONIC_DEV_H_
#define _IONIC_DEV_H_

#include <linux/atomic.h>
#include <linux/mutex.h>
#include <linux/workqueue.h>
#include <linux/skbuff.h>
#include <linux/bpf_trace.h>

#include "ionic_if.h"
#include "ionic_regs.h"

#define IONIC_MAX_TX_DESC		8192
#define IONIC_MAX_RX_DESC		16384
#define IONIC_MIN_TXRX_DESC		64
#define IONIC_DEF_TXRX_DESC		4096
#define IONIC_RX_FILL_THRESHOLD		16
#define IONIC_RX_FILL_DIV		8
#define IONIC_TSO_DESCS_NEEDED		44 /* 64K TSO @1500B */
#define IONIC_LIFS_MAX			1024
#define IONIC_WATCHDOG_SECS		5
#define IONIC_ITR_COAL_USEC_DEFAULT	64

#define IONIC_DEV_CMD_REG_VERSION	1
#define IONIC_DEV_INFO_REG_COUNT	32
#define IONIC_DEV_CMD_REG_COUNT		32

#define IONIC_NAPI_DEADLINE		(HZ / 200)	/* 5ms */
#define IONIC_ADMIN_DOORBELL_DEADLINE	(HZ / 2)	/* 500ms */
#define IONIC_TX_DOORBELL_DEADLINE	(HZ / 100)	/* 10ms */
#define IONIC_RX_MIN_DOORBELL_DEADLINE	(HZ / 100)	/* 10ms */
#define IONIC_RX_MAX_DOORBELL_DEADLINE	(HZ * 5)	/* 5s */

struct ionic_dev_bar {
	void __iomem *vaddr;
	phys_addr_t bus_addr;
	unsigned long len;
	int res_index;
};

#ifndef __CHECKER__
/* Registers */
static_assert(sizeof(struct ionic_intr) == 32);

static_assert(sizeof(struct ionic_doorbell) == 8);
static_assert(sizeof(struct ionic_intr_status) == 8);
static_assert(sizeof(union ionic_dev_regs) == 4096);
static_assert(sizeof(union ionic_dev_info_regs) == 2048);
static_assert(sizeof(union ionic_dev_cmd_regs) == 2048);
static_assert(sizeof(struct ionic_lif_stats) == 1024);

static_assert(sizeof(struct ionic_admin_cmd) == 64);
static_assert(sizeof(struct ionic_admin_comp) == 16);
static_assert(sizeof(struct ionic_nop_cmd) == 64);
static_assert(sizeof(struct ionic_nop_comp) == 16);

/* Device commands */
static_assert(sizeof(struct ionic_dev_identify_cmd) == 64);
static_assert(sizeof(struct ionic_dev_identify_comp) == 16);
static_assert(sizeof(struct ionic_dev_init_cmd) == 64);
static_assert(sizeof(struct ionic_dev_init_comp) == 16);
static_assert(sizeof(struct ionic_dev_reset_cmd) == 64);
static_assert(sizeof(struct ionic_dev_reset_comp) == 16);
static_assert(sizeof(struct ionic_dev_getattr_cmd) == 64);
static_assert(sizeof(struct ionic_dev_getattr_comp) == 16);
static_assert(sizeof(struct ionic_dev_setattr_cmd) == 64);
static_assert(sizeof(struct ionic_dev_setattr_comp) == 16);
static_assert(sizeof(struct ionic_lif_setphc_cmd) == 64);

/* Port commands */
static_assert(sizeof(struct ionic_port_identify_cmd) == 64);
static_assert(sizeof(struct ionic_port_identify_comp) == 16);
static_assert(sizeof(struct ionic_port_init_cmd) == 64);
static_assert(sizeof(struct ionic_port_init_comp) == 16);
static_assert(sizeof(struct ionic_port_reset_cmd) == 64);
static_assert(sizeof(struct ionic_port_reset_comp) == 16);
static_assert(sizeof(struct ionic_port_getattr_cmd) == 64);
static_assert(sizeof(struct ionic_port_getattr_comp) == 16);
static_assert(sizeof(struct ionic_port_setattr_cmd) == 64);
static_assert(sizeof(struct ionic_port_setattr_comp) == 16);

/* LIF commands */
static_assert(sizeof(struct ionic_lif_init_cmd) == 64);
static_assert(sizeof(struct ionic_lif_init_comp) == 16);
static_assert(sizeof(struct ionic_lif_reset_cmd) == 64);
static_assert(sizeof(ionic_lif_reset_comp) == 16);
static_assert(sizeof(struct ionic_lif_getattr_cmd) == 64);
static_assert(sizeof(struct ionic_lif_getattr_comp) == 16);
static_assert(sizeof(struct ionic_lif_setattr_cmd) == 64);
static_assert(sizeof(struct ionic_lif_setattr_comp) == 16);

static_assert(sizeof(struct ionic_q_init_cmd) == 64);
static_assert(sizeof(struct ionic_q_init_comp) == 16);
static_assert(sizeof(struct ionic_q_control_cmd) == 64);
static_assert(sizeof(ionic_q_control_comp) == 16);
static_assert(sizeof(struct ionic_q_identify_cmd) == 64);
static_assert(sizeof(struct ionic_q_identify_comp) == 16);

static_assert(sizeof(struct ionic_rx_mode_set_cmd) == 64);
static_assert(sizeof(ionic_rx_mode_set_comp) == 16);
static_assert(sizeof(struct ionic_rx_filter_add_cmd) == 64);
static_assert(sizeof(struct ionic_rx_filter_add_comp) == 16);
static_assert(sizeof(struct ionic_rx_filter_del_cmd) == 64);
static_assert(sizeof(ionic_rx_filter_del_comp) == 16);

/* RDMA commands */
static_assert(sizeof(struct ionic_rdma_reset_cmd) == 64);
static_assert(sizeof(struct ionic_rdma_queue_cmd) == 64);

/* Events */
static_assert(sizeof(struct ionic_notifyq_cmd) == 4);
static_assert(sizeof(union ionic_notifyq_comp) == 64);
static_assert(sizeof(struct ionic_notifyq_event) == 64);
static_assert(sizeof(struct ionic_link_change_event) == 64);
static_assert(sizeof(struct ionic_reset_event) == 64);
static_assert(sizeof(struct ionic_heartbeat_event) == 64);
static_assert(sizeof(struct ionic_log_event) == 64);

/* I/O */
static_assert(sizeof(struct ionic_txq_desc) == 16);
static_assert(sizeof(struct ionic_txq_sg_desc) == 128);
static_assert(sizeof(struct ionic_txq_comp) == 16);

static_assert(sizeof(struct ionic_rxq_desc) == 16);
static_assert(sizeof(struct ionic_rxq_sg_desc) == 128);
static_assert(sizeof(struct ionic_rxq_comp) == 16);

/* SR/IOV */
static_assert(sizeof(struct ionic_vf_setattr_cmd) == 64);
static_assert(sizeof(struct ionic_vf_setattr_comp) == 16);
static_assert(sizeof(struct ionic_vf_getattr_cmd) == 64);
static_assert(sizeof(struct ionic_vf_getattr_comp) == 16);
static_assert(sizeof(struct ionic_vf_ctrl_cmd) == 64);
static_assert(sizeof(struct ionic_vf_ctrl_comp) == 16);
#endif /* __CHECKER__ */

struct ionic_devinfo {
	u8 asic_type;
	u8 asic_rev;
	char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN + 1];
	char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN + 1];
};

struct ionic_dev {
	union ionic_dev_info_regs __iomem *dev_info_regs;
	union ionic_dev_cmd_regs __iomem *dev_cmd_regs;
	struct ionic_hwstamp_regs __iomem *hwstamp_regs;

	atomic_long_t last_check_time;
	unsigned long last_hb_time;
	u32 last_fw_hb;
	bool fw_hb_ready;
	bool fw_status_ready;
	u8 fw_generation;
	u8 opcode;

	u64 __iomem *db_pages;
	dma_addr_t phy_db_pages;

	struct ionic_intr __iomem *intr_ctrl;
	u64 __iomem *intr_status;

	struct mutex cmb_inuse_lock; /* for cmb_inuse */
	unsigned long *cmb_inuse;
	dma_addr_t phy_cmb_pages;
	u32 cmb_npages;

	u32 port_info_sz;
	struct ionic_port_info *port_info;
	dma_addr_t port_info_pa;

	struct ionic_devinfo dev_info;
};

struct ionic_cq_info {
	union {
		void *cq_desc;
		struct ionic_admin_comp *admincq;
		struct ionic_notifyq_event *notifyq;
	};
};

struct ionic_queue;
struct ionic_qcq;
struct ionic_desc_info;

typedef void (*ionic_desc_cb)(struct ionic_queue *q,
			      struct ionic_desc_info *desc_info,
			      struct ionic_cq_info *cq_info, void *cb_arg);

#define IONIC_MAX_BUF_LEN			((u16)-1)
#define IONIC_PAGE_SIZE				PAGE_SIZE
#define IONIC_PAGE_SPLIT_SZ			(PAGE_SIZE / 2)
#define IONIC_PAGE_GFP_MASK			(GFP_ATOMIC | __GFP_NOWARN |\
						 __GFP_COMP | __GFP_MEMALLOC)

#define IONIC_XDP_MAX_LINEAR_MTU	(IONIC_PAGE_SIZE -	\
					 (VLAN_ETH_HLEN +	\
					  XDP_PACKET_HEADROOM +	\
					  SKB_DATA_ALIGN(sizeof(struct skb_shared_info))))

struct ionic_buf_info {
	struct page *page;
	dma_addr_t dma_addr;
	u32 page_offset;
	u32 len;
};

#define IONIC_MAX_FRAGS			(1 + IONIC_TX_MAX_SG_ELEMS_V1)

struct ionic_desc_info {
	union {
		void *desc;
		struct ionic_txq_desc *txq_desc;
		struct ionic_rxq_desc *rxq_desc;
		struct ionic_admin_cmd *adminq_desc;
	};
	void __iomem *cmb_desc;
	union {
		void *sg_desc;
		struct ionic_txq_sg_desc *txq_sg_desc;
		struct ionic_rxq_sg_desc *rxq_sgl_desc;
	};
	unsigned int bytes;
	unsigned int nbufs;
	struct ionic_buf_info bufs[MAX_SKB_FRAGS + 1];
	ionic_desc_cb cb;
	void *cb_arg;
	struct xdp_frame *xdpf;
	enum xdp_action act;
};

#define IONIC_QUEUE_NAME_MAX_SZ		16

struct ionic_queue {
	struct device *dev;
	struct ionic_lif *lif;
	struct ionic_desc_info *info;
	u64 dbval;
	unsigned long dbell_deadline;
	unsigned long dbell_jiffies;
	u16 head_idx;
	u16 tail_idx;
	unsigned int index;
	unsigned int num_descs;
	unsigned int max_sg_elems;
	u64 features;
	u64 drop;
	struct ionic_dev *idev;
	unsigned int type;
	unsigned int hw_index;
	unsigned int hw_type;
	union {
		void *base;
		struct ionic_txq_desc *txq;
		struct ionic_rxq_desc *rxq;
		struct ionic_admin_cmd *adminq;
	};
	void __iomem *cmb_base;
	union {
		void *sg_base;
		struct ionic_txq_sg_desc *txq_sgl;
		struct ionic_rxq_sg_desc *rxq_sgl;
	};
	struct xdp_rxq_info *xdp_rxq_info;
	struct ionic_queue *partner;
	bool xdp_flush;
	dma_addr_t base_pa;
	dma_addr_t cmb_base_pa;
	dma_addr_t sg_base_pa;
	unsigned int desc_size;
	unsigned int sg_desc_size;
	unsigned int pid;
	char name[IONIC_QUEUE_NAME_MAX_SZ];
} ____cacheline_aligned_in_smp;

#define IONIC_INTR_INDEX_NOT_ASSIGNED	-1
#define IONIC_INTR_NAME_MAX_SZ		32

struct ionic_intr_info {
	char name[IONIC_INTR_NAME_MAX_SZ];
	u64 rearm_count;
	unsigned int index;
	unsigned int vector;
	unsigned int cpu;
	u32 dim_coal_hw;
	cpumask_t affinity_mask;
};

struct ionic_cq {
	struct ionic_lif *lif;
	struct ionic_cq_info *info;
	struct ionic_queue *bound_q;
	struct ionic_intr_info *bound_intr;
	u16 tail_idx;
	bool done_color;
	unsigned int num_descs;
	unsigned int desc_size;
	void *base;
	dma_addr_t base_pa;
} ____cacheline_aligned_in_smp;

struct ionic;

static inline void ionic_intr_init(struct ionic_dev *idev,
				   struct ionic_intr_info *intr,
				   unsigned long index)
{
	ionic_intr_clean(idev->intr_ctrl, index);
	intr->index = index;
}

static inline unsigned int ionic_q_space_avail(struct ionic_queue *q)
{
	unsigned int avail = q->tail_idx;

	if (q->head_idx >= avail)
		avail += q->num_descs - q->head_idx - 1;
	else
		avail -= q->head_idx + 1;

	return avail;
}

static inline bool ionic_q_has_space(struct ionic_queue *q, unsigned int want)
{
	return ionic_q_space_avail(q) >= want;
}

void ionic_init_devinfo(struct ionic *ionic);
int ionic_dev_setup(struct ionic *ionic);
void ionic_dev_teardown(struct ionic *ionic);

void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd);
u8 ionic_dev_cmd_status(struct ionic_dev *idev);
bool ionic_dev_cmd_done(struct ionic_dev *idev);
void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp);

void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver);
void ionic_dev_cmd_init(struct ionic_dev *idev);
void ionic_dev_cmd_reset(struct ionic_dev *idev);

void ionic_dev_cmd_port_identify(struct ionic_dev *idev);
void ionic_dev_cmd_port_init(struct ionic_dev *idev);
void ionic_dev_cmd_port_reset(struct ionic_dev *idev);
void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state);
void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed);
void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable);
void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type);
void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type);

int ionic_set_vf_config(struct ionic *ionic, int vf,
			struct ionic_vf_setattr_cmd *vfc);

void ionic_dev_cmd_queue_identify(struct ionic_dev *idev,
				  u16 lif_type, u8 qtype, u8 qver);
void ionic_vf_start(struct ionic *ionic);
void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver);
void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index,
			    dma_addr_t addr);
void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index);
void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq,
			       u16 lif_index, u16 intr_index);

int ionic_db_page_num(struct ionic_lif *lif, int pid);

int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr, int order);
void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order);

int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,
		  struct ionic_intr_info *intr,
		  unsigned int num_descs, size_t desc_size);
void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa);
void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q);
typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, struct ionic_cq_info *cq_info);
typedef void (*ionic_cq_done_cb)(void *done_arg);
unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do,
			      ionic_cq_cb cb, ionic_cq_done_cb done_cb,
			      void *done_arg);
unsigned int ionic_tx_cq_service(struct ionic_cq *cq, unsigned int work_to_do);

int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
		 struct ionic_queue *q, unsigned int index, const char *name,
		 unsigned int num_descs, size_t desc_size,
		 size_t sg_desc_size, unsigned int pid);
void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa);
void ionic_q_cmb_map(struct ionic_queue *q, void __iomem *base, dma_addr_t base_pa);
void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa);
void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb,
		  void *cb_arg);
void ionic_q_service(struct ionic_queue *q, struct ionic_cq_info *cq_info,
		     unsigned int stop_index);
int ionic_heartbeat_check(struct ionic *ionic);
bool ionic_is_fw_running(struct ionic_dev *idev);

bool ionic_adminq_poke_doorbell(struct ionic_queue *q);
bool ionic_txq_poke_doorbell(struct ionic_queue *q);
bool ionic_rxq_poke_doorbell(struct ionic_queue *q);

#endif /* _IONIC_DEV_H_ */
Commit	Line	Data
fbfb8031 SN	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
	3
	4	#ifndef _IONIC_DEV_H_
	5	#define _IONIC_DEV_H_
	6
b2b9a8d7	7	#include <linux/atomic.h>
fbfb8031 SN	8	#include <linux/mutex.h>
fbfb8031 SN	9	#include <linux/workqueue.h>
529cdfd5	10	#include <linux/skbuff.h>
180e35cd	11	#include <linux/bpf_trace.h>
fbfb8031 SN	12
	13	#include "ionic_if.h"
	14	#include "ionic_regs.h"
	15
5b3f3f2a SN	16	#define IONIC_MAX_TX_DESC 8192
5b3f3f2a SN	17	#define IONIC_MAX_RX_DESC 16384
a8205ab6	18	#define IONIC_MIN_TXRX_DESC 64
4d03e00a	19	#define IONIC_DEF_TXRX_DESC 4096
a8205ab6 SN	20	#define IONIC_RX_FILL_THRESHOLD 16
a8205ab6 SN	21	#define IONIC_RX_FILL_DIV 8
061b9bed	22	#define IONIC_TSO_DESCS_NEEDED 44 /* 64K TSO @1500B */
1a58e196	23	#define IONIC_LIFS_MAX 1024
089406bc	24	#define IONIC_WATCHDOG_SECS 5
8c15440b	25	#define IONIC_ITR_COAL_USEC_DEFAULT 64
1a58e196	26
4d03e00a SN	27	#define IONIC_DEV_CMD_REG_VERSION 1
	28	#define IONIC_DEV_INFO_REG_COUNT 32
	29	#define IONIC_DEV_CMD_REG_COUNT 32
	30
b69585bf AH	31	#define IONIC_NAPI_DEADLINE (HZ / 200) /* 5ms */
	32	#define IONIC_ADMIN_DOORBELL_DEADLINE (HZ / 2) /* 500ms */
	33	#define IONIC_TX_DOORBELL_DEADLINE (HZ / 100) /* 10ms */
	34	#define IONIC_RX_MIN_DOORBELL_DEADLINE (HZ / 100) /* 10ms */
	35	#define IONIC_RX_MAX_DOORBELL_DEADLINE (HZ * 5) /* 5s */
	36
fbfb8031 SN	37	struct ionic_dev_bar {
	38	void __iomem *vaddr;
	39	phys_addr_t bus_addr;
	40	unsigned long len;
	41	int res_index;
	42	};
	43
d701ec32	44	#ifndef __CHECKER__
fbfb8031 SN	45	/* Registers */
	46	static_assert(sizeof(struct ionic_intr) == 32);
	47
	48	static_assert(sizeof(struct ionic_doorbell) == 8);
	49	static_assert(sizeof(struct ionic_intr_status) == 8);
	50	static_assert(sizeof(union ionic_dev_regs) == 4096);
	51	static_assert(sizeof(union ionic_dev_info_regs) == 2048);
	52	static_assert(sizeof(union ionic_dev_cmd_regs) == 2048);
	53	static_assert(sizeof(struct ionic_lif_stats) == 1024);
	54
	55	static_assert(sizeof(struct ionic_admin_cmd) == 64);
	56	static_assert(sizeof(struct ionic_admin_comp) == 16);
	57	static_assert(sizeof(struct ionic_nop_cmd) == 64);
	58	static_assert(sizeof(struct ionic_nop_comp) == 16);
	59
	60	/* Device commands */
	61	static_assert(sizeof(struct ionic_dev_identify_cmd) == 64);
	62	static_assert(sizeof(struct ionic_dev_identify_comp) == 16);
	63	static_assert(sizeof(struct ionic_dev_init_cmd) == 64);
	64	static_assert(sizeof(struct ionic_dev_init_comp) == 16);
	65	static_assert(sizeof(struct ionic_dev_reset_cmd) == 64);
	66	static_assert(sizeof(struct ionic_dev_reset_comp) == 16);
	67	static_assert(sizeof(struct ionic_dev_getattr_cmd) == 64);
	68	static_assert(sizeof(struct ionic_dev_getattr_comp) == 16);
	69	static_assert(sizeof(struct ionic_dev_setattr_cmd) == 64);
	70	static_assert(sizeof(struct ionic_dev_setattr_comp) == 16);
3da25843	71	static_assert(sizeof(struct ionic_lif_setphc_cmd) == 64);
fbfb8031 SN	72
	73	/* Port commands */
	74	static_assert(sizeof(struct ionic_port_identify_cmd) == 64);
	75	static_assert(sizeof(struct ionic_port_identify_comp) == 16);
	76	static_assert(sizeof(struct ionic_port_init_cmd) == 64);
	77	static_assert(sizeof(struct ionic_port_init_comp) == 16);
	78	static_assert(sizeof(struct ionic_port_reset_cmd) == 64);
	79	static_assert(sizeof(struct ionic_port_reset_comp) == 16);
	80	static_assert(sizeof(struct ionic_port_getattr_cmd) == 64);
	81	static_assert(sizeof(struct ionic_port_getattr_comp) == 16);
	82	static_assert(sizeof(struct ionic_port_setattr_cmd) == 64);
	83	static_assert(sizeof(struct ionic_port_setattr_comp) == 16);
	84
	85	/* LIF commands */
	86	static_assert(sizeof(struct ionic_lif_init_cmd) == 64);
	87	static_assert(sizeof(struct ionic_lif_init_comp) == 16);
	88	static_assert(sizeof(struct ionic_lif_reset_cmd) == 64);
	89	static_assert(sizeof(ionic_lif_reset_comp) == 16);
	90	static_assert(sizeof(struct ionic_lif_getattr_cmd) == 64);
	91	static_assert(sizeof(struct ionic_lif_getattr_comp) == 16);
	92	static_assert(sizeof(struct ionic_lif_setattr_cmd) == 64);
	93	static_assert(sizeof(struct ionic_lif_setattr_comp) == 16);
	94
	95	static_assert(sizeof(struct ionic_q_init_cmd) == 64);
	96	static_assert(sizeof(struct ionic_q_init_comp) == 16);
	97	static_assert(sizeof(struct ionic_q_control_cmd) == 64);
	98	static_assert(sizeof(ionic_q_control_comp) == 16);
5b3f3f2a SN	99	static_assert(sizeof(struct ionic_q_identify_cmd) == 64);
5b3f3f2a SN	100	static_assert(sizeof(struct ionic_q_identify_comp) == 16);
fbfb8031 SN	101
	102	static_assert(sizeof(struct ionic_rx_mode_set_cmd) == 64);
	103	static_assert(sizeof(ionic_rx_mode_set_comp) == 16);
	104	static_assert(sizeof(struct ionic_rx_filter_add_cmd) == 64);
	105	static_assert(sizeof(struct ionic_rx_filter_add_comp) == 16);
	106	static_assert(sizeof(struct ionic_rx_filter_del_cmd) == 64);
	107	static_assert(sizeof(ionic_rx_filter_del_comp) == 16);
	108
	109	/* RDMA commands */
	110	static_assert(sizeof(struct ionic_rdma_reset_cmd) == 64);
	111	static_assert(sizeof(struct ionic_rdma_queue_cmd) == 64);
	112
	113	/* Events */
	114	static_assert(sizeof(struct ionic_notifyq_cmd) == 4);
	115	static_assert(sizeof(union ionic_notifyq_comp) == 64);
	116	static_assert(sizeof(struct ionic_notifyq_event) == 64);
	117	static_assert(sizeof(struct ionic_link_change_event) == 64);
	118	static_assert(sizeof(struct ionic_reset_event) == 64);
	119	static_assert(sizeof(struct ionic_heartbeat_event) == 64);
	120	static_assert(sizeof(struct ionic_log_event) == 64);
	121
	122	/* I/O */
	123	static_assert(sizeof(struct ionic_txq_desc) == 16);
	124	static_assert(sizeof(struct ionic_txq_sg_desc) == 128);
	125	static_assert(sizeof(struct ionic_txq_comp) == 16);
	126
	127	static_assert(sizeof(struct ionic_rxq_desc) == 16);
	128	static_assert(sizeof(struct ionic_rxq_sg_desc) == 128);
	129	static_assert(sizeof(struct ionic_rxq_comp) == 16);
	130
fbb39807 SN	131	/* SR/IOV */
	132	static_assert(sizeof(struct ionic_vf_setattr_cmd) == 64);
	133	static_assert(sizeof(struct ionic_vf_setattr_comp) == 16);
	134	static_assert(sizeof(struct ionic_vf_getattr_cmd) == 64);
	135	static_assert(sizeof(struct ionic_vf_getattr_comp) == 16);
f43a96d9 SN	136	static_assert(sizeof(struct ionic_vf_ctrl_cmd) == 64);
f43a96d9 SN	137	static_assert(sizeof(struct ionic_vf_ctrl_comp) == 16);
d701ec32	138	#endif /* __CHECKER__ */
fbb39807	139
fbfb8031 SN	140	struct ionic_devinfo {
	141	u8 asic_type;
	142	u8 asic_rev;
	143	char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN + 1];
	144	char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN + 1];
	145	};
	146
	147	struct ionic_dev {
	148	union ionic_dev_info_regs __iomem *dev_info_regs;
	149	union ionic_dev_cmd_regs __iomem *dev_cmd_regs;
61db421d	150	struct ionic_hwstamp_regs __iomem *hwstamp_regs;
fbfb8031	151
b2b9a8d7	152	atomic_long_t last_check_time;
97ca4865	153	unsigned long last_hb_time;
b2b9a8d7 SN	154	u32 last_fw_hb;
	155	bool fw_hb_ready;
	156	bool fw_status_ready;
d2662072	157	u8 fw_generation;
24f11024	158	u8 opcode;
97ca4865	159
fbfb8031 SN	160	u64 __iomem *db_pages;
	161	dma_addr_t phy_db_pages;
	162
	163	struct ionic_intr __iomem *intr_ctrl;
	164	u64 __iomem *intr_status;
	165
40bc471d SN	166	struct mutex cmb_inuse_lock; /* for cmb_inuse */
	167	unsigned long *cmb_inuse;
	168	dma_addr_t phy_cmb_pages;
	169	u32 cmb_npages;
	170
04436595 SN	171	u32 port_info_sz;
	172	struct ionic_port_info *port_info;
	173	dma_addr_t port_info_pa;
	174
fbfb8031 SN	175	struct ionic_devinfo dev_info;
	176	};
	177
1d062b7b	178	struct ionic_cq_info {
f1d2e894 SN	179	union {
f1d2e894 SN	180	void *cq_desc;
f1d2e894 SN	181	struct ionic_admin_comp *admincq;
	182	struct ionic_notifyq_event *notifyq;
	183	};
1d062b7b SN	184	};
	185
	186	struct ionic_queue;
	187	struct ionic_qcq;
	188	struct ionic_desc_info;
	189
	190	typedef void (ionic_desc_cb)(struct ionic_queue q,
	191	struct ionic_desc_info *desc_info,
	192	struct ionic_cq_info cq_info, void cb_arg);
	193
8f6b846b	194	#define IONIC_MAX_BUF_LEN ((u16)-1)
4b0a7539 SN	195	#define IONIC_PAGE_SIZE PAGE_SIZE
	196	#define IONIC_PAGE_SPLIT_SZ (PAGE_SIZE / 2)
	197	#define IONIC_PAGE_GFP_MASK (GFP_ATOMIC \| __GFP_NOWARN \|\
	198	__GFP_COMP \| __GFP_MEMALLOC)
	199
180e35cd SN	200	#define IONIC_XDP_MAX_LINEAR_MTU (IONIC_PAGE_SIZE - \
	201	(VLAN_ETH_HLEN + \
	202	XDP_PACKET_HEADROOM + \
	203	SKB_DATA_ALIGN(sizeof(struct skb_shared_info))))
	204
4b0a7539	205	struct ionic_buf_info {
08f2e4b2 SN	206	struct page *page;
08f2e4b2 SN	207	dma_addr_t dma_addr;
4b0a7539	208	u32 page_offset;
5b039241	209	u32 len;
08f2e4b2 SN	210	};
08f2e4b2 SN	211
5b039241 SN	212	#define IONIC_MAX_FRAGS (1 + IONIC_TX_MAX_SG_ELEMS_V1)
5b039241 SN	213
1d062b7b	214	struct ionic_desc_info {
f1d2e894 SN	215	union {
	216	void *desc;
	217	struct ionic_txq_desc *txq_desc;
	218	struct ionic_rxq_desc *rxq_desc;
	219	struct ionic_admin_cmd *adminq_desc;
	220	};
40bc471d	221	void __iomem *cmb_desc;
f1d2e894 SN	222	union {
	223	void *sg_desc;
	224	struct ionic_txq_sg_desc *txq_sg_desc;
	225	struct ionic_rxq_sg_desc *rxq_sgl_desc;
	226	};
633eddf1	227	unsigned int bytes;
4b0a7539	228	unsigned int nbufs;
529cdfd5	229	struct ionic_buf_info bufs[MAX_SKB_FRAGS + 1];
1d062b7b SN	230	ionic_desc_cb cb;
1d062b7b SN	231	void *cb_arg;
8eeed837 SN	232	struct xdp_frame *xdpf;
8eeed837 SN	233	enum xdp_action act;
1d062b7b SN	234	};
1d062b7b SN	235
0ceb3860	236	#define IONIC_QUEUE_NAME_MAX_SZ 16
1d062b7b SN	237
1d062b7b SN	238	struct ionic_queue {
f1d2e894	239	struct device *dev;
1d062b7b SN	240	struct ionic_lif *lif;
1d062b7b SN	241	struct ionic_desc_info *info;
f37bc346	242	u64 dbval;
b69585bf AH	243	unsigned long dbell_deadline;
b69585bf AH	244	unsigned long dbell_jiffies;
f1d2e894 SN	245	u16 head_idx;
f1d2e894 SN	246	u16 tail_idx;
1d062b7b	247	unsigned int index;
0c1d175b	248	unsigned int num_descs;
f37bc346	249	unsigned int max_sg_elems;
a8771bfe	250	u64 features;
0c1d175b SN	251	u64 drop;
0c1d175b SN	252	struct ionic_dev *idev;
1d062b7b SN	253	unsigned int type;
	254	unsigned int hw_index;
	255	unsigned int hw_type;
f1d2e894 SN	256	union {
	257	void *base;
	258	struct ionic_txq_desc *txq;
	259	struct ionic_rxq_desc *rxq;
	260	struct ionic_admin_cmd *adminq;
	261	};
40bc471d	262	void __iomem *cmb_base;
f1d2e894 SN	263	union {
	264	void *sg_base;
	265	struct ionic_txq_sg_desc *txq_sgl;
	266	struct ionic_rxq_sg_desc *rxq_sgl;
	267	};
180e35cd	268	struct xdp_rxq_info *xdp_rxq_info;
8eeed837	269	struct ionic_queue *partner;
587fc3f0	270	bool xdp_flush;
1d062b7b	271	dma_addr_t base_pa;
40bc471d	272	dma_addr_t cmb_base_pa;
1d062b7b	273	dma_addr_t sg_base_pa;
1d062b7b SN	274	unsigned int desc_size;
	275	unsigned int sg_desc_size;
	276	unsigned int pid;
c06107ca	277	char name[IONIC_QUEUE_NAME_MAX_SZ];
f37bc346	278	} ____cacheline_aligned_in_smp;
1d062b7b	279
c06107ca SN	280	#define IONIC_INTR_INDEX_NOT_ASSIGNED -1
c06107ca SN	281	#define IONIC_INTR_NAME_MAX_SZ 32
6461b446 SN	282
6461b446 SN	283	struct ionic_intr_info {
c06107ca	284	char name[IONIC_INTR_NAME_MAX_SZ];
5858036c	285	u64 rearm_count;
6461b446 SN	286	unsigned int index;
6461b446 SN	287	unsigned int vector;
6461b446	288	unsigned int cpu;
04a83459	289	u32 dim_coal_hw;
5858036c	290	cpumask_t affinity_mask;
6461b446 SN	291	};
6461b446 SN	292
1d062b7b	293	struct ionic_cq {
1d062b7b SN	294	struct ionic_lif *lif;
1d062b7b SN	295	struct ionic_cq_info *info;
1d062b7b SN	296	struct ionic_queue *bound_q;
1d062b7b SN	297	struct ionic_intr_info *bound_intr;
f1d2e894	298	u16 tail_idx;
1d062b7b SN	299	bool done_color;
1d062b7b SN	300	unsigned int num_descs;
1d062b7b	301	unsigned int desc_size;
0c1d175b SN	302	void *base;
0c1d175b SN	303	dma_addr_t base_pa;
f37bc346	304	} ____cacheline_aligned_in_smp;
1d062b7b	305
fbfb8031 SN	306	struct ionic;
fbfb8031 SN	307
6461b446 SN	308	static inline void ionic_intr_init(struct ionic_dev *idev,
	309	struct ionic_intr_info *intr,
	310	unsigned long index)
	311	{
	312	ionic_intr_clean(idev->intr_ctrl, index);
	313	intr->index = index;
	314	}
	315
1d062b7b SN	316	static inline unsigned int ionic_q_space_avail(struct ionic_queue *q)
1d062b7b SN	317	{
f1d2e894	318	unsigned int avail = q->tail_idx;
1d062b7b	319
f1d2e894 SN	320	if (q->head_idx >= avail)
f1d2e894 SN	321	avail += q->num_descs - q->head_idx - 1;
1d062b7b	322	else
f1d2e894	323	avail -= q->head_idx + 1;
1d062b7b SN	324
	325	return avail;
	326	}
	327
	328	static inline bool ionic_q_has_space(struct ionic_queue *q, unsigned int want)
	329	{
	330	return ionic_q_space_avail(q) >= want;
	331	}
	332
fbfb8031 SN	333	void ionic_init_devinfo(struct ionic *ionic);
fbfb8031 SN	334	int ionic_dev_setup(struct ionic *ionic);
40bc471d	335	void ionic_dev_teardown(struct ionic *ionic);
fbfb8031 SN	336
	337	void ionic_dev_cmd_go(struct ionic_dev idev, union ionic_dev_cmd cmd);
	338	u8 ionic_dev_cmd_status(struct ionic_dev *idev);
	339	bool ionic_dev_cmd_done(struct ionic_dev *idev);
	340	void ionic_dev_cmd_comp(struct ionic_dev idev, union ionic_dev_cmd_comp comp);
	341
	342	void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver);
	343	void ionic_dev_cmd_init(struct ionic_dev *idev);
	344	void ionic_dev_cmd_reset(struct ionic_dev *idev);
	345
04436595 SN	346	void ionic_dev_cmd_port_identify(struct ionic_dev *idev);
	347	void ionic_dev_cmd_port_init(struct ionic_dev *idev);
	348	void ionic_dev_cmd_port_reset(struct ionic_dev *idev);
	349	void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state);
	350	void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed);
	351	void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable);
	352	void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type);
	353	void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type);
	354
36197d82 SN	355	int ionic_set_vf_config(struct ionic *ionic, int vf,
36197d82 SN	356	struct ionic_vf_setattr_cmd *vfc);
15e54faa	357
5b3f3f2a SN	358	void ionic_dev_cmd_queue_identify(struct ionic_dev *idev,
5b3f3f2a SN	359	u16 lif_type, u8 qtype, u8 qver);
f43a96d9	360	void ionic_vf_start(struct ionic *ionic);
1a58e196 SN	361	void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver);
	362	void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index,
	363	dma_addr_t addr);
	364	void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index);
1d062b7b SN	365	void ionic_dev_cmd_adminq_init(struct ionic_dev idev, struct ionic_qcq qcq,
1d062b7b SN	366	u16 lif_index, u16 intr_index);
1a58e196	367
6461b446 SN	368	int ionic_db_page_num(struct ionic_lif *lif, int pid);
6461b446 SN	369
40bc471d SN	370	int ionic_get_cmb(struct ionic_lif lif, u32 pgid, phys_addr_t *pgaddr, int order);
	371	void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order);
	372
1d062b7b SN	373	int ionic_cq_init(struct ionic_lif lif, struct ionic_cq cq,
	374	struct ionic_intr_info *intr,
	375	unsigned int num_descs, size_t desc_size);
	376	void ionic_cq_map(struct ionic_cq cq, void base, dma_addr_t base_pa);
	377	void ionic_cq_bind(struct ionic_cq cq, struct ionic_queue q);
	378	typedef bool (ionic_cq_cb)(struct ionic_cq cq, struct ionic_cq_info *cq_info);
	379	typedef void (ionic_cq_done_cb)(void done_arg);
	380	unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do,
	381	ionic_cq_cb cb, ionic_cq_done_cb done_cb,
	382	void *done_arg);
061b9bed	383	unsigned int ionic_tx_cq_service(struct ionic_cq *cq, unsigned int work_to_do);
1d062b7b SN	384
	385	int ionic_q_init(struct ionic_lif lif, struct ionic_dev idev,
	386	struct ionic_queue q, unsigned int index, const char name,
	387	unsigned int num_descs, size_t desc_size,
	388	size_t sg_desc_size, unsigned int pid);
	389	void ionic_q_map(struct ionic_queue q, void base, dma_addr_t base_pa);
40bc471d	390	void ionic_q_cmb_map(struct ionic_queue q, void __iomem base, dma_addr_t base_pa);
1d062b7b SN	391	void ionic_q_sg_map(struct ionic_queue q, void base, dma_addr_t base_pa);
	392	void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb,
	393	void *cb_arg);
1d062b7b SN	394	void ionic_q_service(struct ionic_queue q, struct ionic_cq_info cq_info,
1d062b7b SN	395	unsigned int stop_index);
97ca4865	396	int ionic_heartbeat_check(struct ionic *ionic);
b8fd0271	397	bool ionic_is_fw_running(struct ionic_dev *idev);
1d062b7b	398
b69585bf AH	399	bool ionic_adminq_poke_doorbell(struct ionic_queue *q);
	400	bool ionic_txq_poke_doorbell(struct ionic_queue *q);
	401	bool ionic_rxq_poke_doorbell(struct ionic_queue *q);
	402
fbfb8031	403	#endif /* _IONIC_DEV_H_ */