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fe56b9e6 | 1 | /* QLogic qed NIC Driver |
e8f1cb50 | 2 | * Copyright (c) 2015-2017 QLogic Corporation |
fe56b9e6 | 3 | * |
e8f1cb50 MY |
4 | * This software is available to you under a choice of one of two |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and /or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
fe56b9e6 YM |
31 | */ |
32 | ||
33 | #ifndef _QED_HSI_H | |
34 | #define _QED_HSI_H | |
35 | ||
36 | #include <linux/types.h> | |
37 | #include <linux/io.h> | |
38 | #include <linux/bitops.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/kernel.h> | |
41 | #include <linux/list.h> | |
42 | #include <linux/slab.h> | |
43 | #include <linux/qed/common_hsi.h> | |
7a9b6b8f YM |
44 | #include <linux/qed/storage_common.h> |
45 | #include <linux/qed/tcp_common.h> | |
1e128c81 | 46 | #include <linux/qed/fcoe_common.h> |
25c089d7 | 47 | #include <linux/qed/eth_common.h> |
7a9b6b8f | 48 | #include <linux/qed/iscsi_common.h> |
67b40dcc | 49 | #include <linux/qed/iwarp_common.h> |
7a9b6b8f YM |
50 | #include <linux/qed/rdma_common.h> |
51 | #include <linux/qed/roce_common.h> | |
1e128c81 | 52 | #include <linux/qed/qed_fcoe_if.h> |
fe56b9e6 YM |
53 | |
54 | struct qed_hwfn; | |
55 | struct qed_ptt; | |
fe56b9e6 | 56 | |
a2e7699e | 57 | /* Opcodes for the event ring */ |
fe56b9e6 YM |
58 | enum common_event_opcode { |
59 | COMMON_EVENT_PF_START, | |
60 | COMMON_EVENT_PF_STOP, | |
1408cc1f | 61 | COMMON_EVENT_VF_START, |
0b55e27d | 62 | COMMON_EVENT_VF_STOP, |
37bff2b9 | 63 | COMMON_EVENT_VF_PF_CHANNEL, |
351a4ded YM |
64 | COMMON_EVENT_VF_FLR, |
65 | COMMON_EVENT_PF_UPDATE, | |
66 | COMMON_EVENT_MALICIOUS_VF, | |
67 | COMMON_EVENT_RL_UPDATE, | |
fc48b7a6 | 68 | COMMON_EVENT_EMPTY, |
fe56b9e6 YM |
69 | MAX_COMMON_EVENT_OPCODE |
70 | }; | |
71 | ||
72 | /* Common Ramrod Command IDs */ | |
73 | enum common_ramrod_cmd_id { | |
74 | COMMON_RAMROD_UNUSED, | |
351a4ded YM |
75 | COMMON_RAMROD_PF_START, |
76 | COMMON_RAMROD_PF_STOP, | |
1408cc1f | 77 | COMMON_RAMROD_VF_START, |
0b55e27d | 78 | COMMON_RAMROD_VF_STOP, |
464f6645 | 79 | COMMON_RAMROD_PF_UPDATE, |
351a4ded | 80 | COMMON_RAMROD_RL_UPDATE, |
fc48b7a6 | 81 | COMMON_RAMROD_EMPTY, |
fe56b9e6 YM |
82 | MAX_COMMON_RAMROD_CMD_ID |
83 | }; | |
84 | ||
a2e7699e TT |
85 | /* How ll2 should deal with packet upon errors */ |
86 | enum core_error_handle { | |
87 | LL2_DROP_PACKET, | |
88 | LL2_DO_NOTHING, | |
89 | LL2_ASSERT, | |
90 | MAX_CORE_ERROR_HANDLE | |
91 | }; | |
92 | ||
93 | /* Opcodes for the event ring */ | |
94 | enum core_event_opcode { | |
95 | CORE_EVENT_TX_QUEUE_START, | |
96 | CORE_EVENT_TX_QUEUE_STOP, | |
97 | CORE_EVENT_RX_QUEUE_START, | |
98 | CORE_EVENT_RX_QUEUE_STOP, | |
99 | CORE_EVENT_RX_QUEUE_FLUSH, | |
da090917 | 100 | CORE_EVENT_TX_QUEUE_UPDATE, |
a2e7699e TT |
101 | MAX_CORE_EVENT_OPCODE |
102 | }; | |
103 | ||
104 | /* The L4 pseudo checksum mode for Core */ | |
105 | enum core_l4_pseudo_checksum_mode { | |
106 | CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH, | |
107 | CORE_L4_PSEUDO_CSUM_ZERO_LENGTH, | |
108 | MAX_CORE_L4_PSEUDO_CHECKSUM_MODE | |
109 | }; | |
110 | ||
111 | /* Light-L2 RX Producers in Tstorm RAM */ | |
112 | struct core_ll2_port_stats { | |
113 | struct regpair gsi_invalid_hdr; | |
114 | struct regpair gsi_invalid_pkt_length; | |
115 | struct regpair gsi_unsupported_pkt_typ; | |
116 | struct regpair gsi_crcchksm_error; | |
117 | }; | |
118 | ||
119 | /* Ethernet TX Per Queue Stats */ | |
120 | struct core_ll2_pstorm_per_queue_stat { | |
121 | struct regpair sent_ucast_bytes; | |
122 | struct regpair sent_mcast_bytes; | |
123 | struct regpair sent_bcast_bytes; | |
124 | struct regpair sent_ucast_pkts; | |
125 | struct regpair sent_mcast_pkts; | |
126 | struct regpair sent_bcast_pkts; | |
127 | }; | |
128 | ||
129 | /* Light-L2 RX Producers in Tstorm RAM */ | |
130 | struct core_ll2_rx_prod { | |
131 | __le16 bd_prod; | |
132 | __le16 cqe_prod; | |
133 | __le32 reserved; | |
134 | }; | |
135 | ||
136 | struct core_ll2_tstorm_per_queue_stat { | |
137 | struct regpair packet_too_big_discard; | |
138 | struct regpair no_buff_discard; | |
139 | }; | |
140 | ||
141 | struct core_ll2_ustorm_per_queue_stat { | |
142 | struct regpair rcv_ucast_bytes; | |
143 | struct regpair rcv_mcast_bytes; | |
144 | struct regpair rcv_bcast_bytes; | |
145 | struct regpair rcv_ucast_pkts; | |
146 | struct regpair rcv_mcast_pkts; | |
147 | struct regpair rcv_bcast_pkts; | |
148 | }; | |
149 | ||
150 | /* Core Ramrod Command IDs (light L2) */ | |
151 | enum core_ramrod_cmd_id { | |
152 | CORE_RAMROD_UNUSED, | |
153 | CORE_RAMROD_RX_QUEUE_START, | |
154 | CORE_RAMROD_TX_QUEUE_START, | |
155 | CORE_RAMROD_RX_QUEUE_STOP, | |
156 | CORE_RAMROD_TX_QUEUE_STOP, | |
157 | CORE_RAMROD_RX_QUEUE_FLUSH, | |
da090917 | 158 | CORE_RAMROD_TX_QUEUE_UPDATE, |
a2e7699e TT |
159 | MAX_CORE_RAMROD_CMD_ID |
160 | }; | |
161 | ||
162 | /* Core RX CQE Type for Light L2 */ | |
163 | enum core_roce_flavor_type { | |
164 | CORE_ROCE, | |
165 | CORE_RROCE, | |
166 | MAX_CORE_ROCE_FLAVOR_TYPE | |
167 | }; | |
168 | ||
169 | /* Specifies how ll2 should deal with packets errors: packet_too_big and | |
170 | * no_buff. | |
171 | */ | |
172 | struct core_rx_action_on_error { | |
173 | u8 error_type; | |
174 | #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3 | |
175 | #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0 | |
176 | #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3 | |
177 | #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2 | |
178 | #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF | |
179 | #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4 | |
180 | }; | |
181 | ||
182 | /* Core RX BD for Light L2 */ | |
183 | struct core_rx_bd { | |
184 | struct regpair addr; | |
185 | __le16 reserved[4]; | |
186 | }; | |
187 | ||
188 | /* Core RX CM offload BD for Light L2 */ | |
189 | struct core_rx_bd_with_buff_len { | |
190 | struct regpair addr; | |
191 | __le16 buff_length; | |
192 | __le16 reserved[3]; | |
193 | }; | |
194 | ||
195 | /* Core RX CM offload BD for Light L2 */ | |
196 | union core_rx_bd_union { | |
197 | struct core_rx_bd rx_bd; | |
198 | struct core_rx_bd_with_buff_len rx_bd_with_len; | |
199 | }; | |
200 | ||
201 | /* Opaque Data for Light L2 RX CQE */ | |
202 | struct core_rx_cqe_opaque_data { | |
203 | __le32 data[2]; | |
204 | }; | |
205 | ||
206 | /* Core RX CQE Type for Light L2 */ | |
207 | enum core_rx_cqe_type { | |
208 | CORE_RX_CQE_ILLEGAL_TYPE, | |
209 | CORE_RX_CQE_TYPE_REGULAR, | |
210 | CORE_RX_CQE_TYPE_GSI_OFFLOAD, | |
211 | CORE_RX_CQE_TYPE_SLOW_PATH, | |
212 | MAX_CORE_RX_CQE_TYPE | |
213 | }; | |
214 | ||
215 | /* Core RX CQE for Light L2 */ | |
216 | struct core_rx_fast_path_cqe { | |
217 | u8 type; | |
218 | u8 placement_offset; | |
219 | struct parsing_and_err_flags parse_flags; | |
220 | __le16 packet_length; | |
221 | __le16 vlan; | |
222 | struct core_rx_cqe_opaque_data opaque_data; | |
223 | struct parsing_err_flags err_flags; | |
224 | __le16 reserved0; | |
225 | __le32 reserved1[3]; | |
226 | }; | |
227 | ||
228 | /* Core Rx CM offload CQE */ | |
229 | struct core_rx_gsi_offload_cqe { | |
230 | u8 type; | |
231 | u8 data_length_error; | |
232 | struct parsing_and_err_flags parse_flags; | |
233 | __le16 data_length; | |
234 | __le16 vlan; | |
235 | __le32 src_mac_addrhi; | |
236 | __le16 src_mac_addrlo; | |
237 | __le16 qp_id; | |
da090917 TT |
238 | __le32 src_qp; |
239 | __le32 reserved[3]; | |
a2e7699e TT |
240 | }; |
241 | ||
242 | /* Core RX CQE for Light L2 */ | |
243 | struct core_rx_slow_path_cqe { | |
244 | u8 type; | |
245 | u8 ramrod_cmd_id; | |
246 | __le16 echo; | |
247 | struct core_rx_cqe_opaque_data opaque_data; | |
248 | __le32 reserved1[5]; | |
249 | }; | |
250 | ||
251 | /* Core RX CM offload BD for Light L2 */ | |
252 | union core_rx_cqe_union { | |
253 | struct core_rx_fast_path_cqe rx_cqe_fp; | |
254 | struct core_rx_gsi_offload_cqe rx_cqe_gsi; | |
255 | struct core_rx_slow_path_cqe rx_cqe_sp; | |
256 | }; | |
257 | ||
258 | /* Ramrod data for rx queue start ramrod */ | |
259 | struct core_rx_start_ramrod_data { | |
260 | struct regpair bd_base; | |
261 | struct regpair cqe_pbl_addr; | |
262 | __le16 mtu; | |
263 | __le16 sb_id; | |
264 | u8 sb_index; | |
265 | u8 complete_cqe_flg; | |
266 | u8 complete_event_flg; | |
267 | u8 drop_ttl0_flg; | |
268 | __le16 num_of_pbl_pages; | |
da090917 TT |
269 | u8 inner_vlan_stripping_en; |
270 | u8 report_outer_vlan; | |
a2e7699e TT |
271 | u8 queue_id; |
272 | u8 main_func_queue; | |
273 | u8 mf_si_bcast_accept_all; | |
274 | u8 mf_si_mcast_accept_all; | |
275 | struct core_rx_action_on_error action_on_error; | |
276 | u8 gsi_offload_flag; | |
da090917 | 277 | u8 reserved[6]; |
a2e7699e TT |
278 | }; |
279 | ||
280 | /* Ramrod data for rx queue stop ramrod */ | |
281 | struct core_rx_stop_ramrod_data { | |
282 | u8 complete_cqe_flg; | |
283 | u8 complete_event_flg; | |
284 | u8 queue_id; | |
285 | u8 reserved1; | |
286 | __le16 reserved2[2]; | |
287 | }; | |
288 | ||
289 | /* Flags for Core TX BD */ | |
290 | struct core_tx_bd_data { | |
291 | __le16 as_bitfield; | |
292 | #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1 | |
293 | #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0 | |
294 | #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1 | |
295 | #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1 | |
296 | #define CORE_TX_BD_DATA_START_BD_MASK 0x1 | |
297 | #define CORE_TX_BD_DATA_START_BD_SHIFT 2 | |
298 | #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1 | |
299 | #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3 | |
300 | #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1 | |
301 | #define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4 | |
302 | #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1 | |
303 | #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5 | |
304 | #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1 | |
305 | #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6 | |
306 | #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1 | |
307 | #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7 | |
308 | #define CORE_TX_BD_DATA_NBDS_MASK 0xF | |
309 | #define CORE_TX_BD_DATA_NBDS_SHIFT 8 | |
310 | #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1 | |
311 | #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12 | |
312 | #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1 | |
313 | #define CORE_TX_BD_DATA_IP_LEN_SHIFT 13 | |
da090917 TT |
314 | #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1 |
315 | #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT 14 | |
316 | #define CORE_TX_BD_DATA_RESERVED0_MASK 0x1 | |
317 | #define CORE_TX_BD_DATA_RESERVED0_SHIFT 15 | |
a2e7699e TT |
318 | }; |
319 | ||
320 | /* Core TX BD for Light L2 */ | |
321 | struct core_tx_bd { | |
322 | struct regpair addr; | |
323 | __le16 nbytes; | |
324 | __le16 nw_vlan_or_lb_echo; | |
325 | struct core_tx_bd_data bd_data; | |
326 | __le16 bitfield1; | |
327 | #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF | |
328 | #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0 | |
329 | #define CORE_TX_BD_TX_DST_MASK 0x3 | |
330 | #define CORE_TX_BD_TX_DST_SHIFT 14 | |
331 | }; | |
332 | ||
333 | /* Light L2 TX Destination */ | |
334 | enum core_tx_dest { | |
335 | CORE_TX_DEST_NW, | |
336 | CORE_TX_DEST_LB, | |
337 | CORE_TX_DEST_RESERVED, | |
338 | CORE_TX_DEST_DROP, | |
339 | MAX_CORE_TX_DEST | |
340 | }; | |
341 | ||
342 | /* Ramrod data for tx queue start ramrod */ | |
343 | struct core_tx_start_ramrod_data { | |
344 | struct regpair pbl_base_addr; | |
345 | __le16 mtu; | |
346 | __le16 sb_id; | |
347 | u8 sb_index; | |
348 | u8 stats_en; | |
349 | u8 stats_id; | |
350 | u8 conn_type; | |
351 | __le16 pbl_size; | |
352 | __le16 qm_pq_id; | |
353 | u8 gsi_offload_flag; | |
354 | u8 resrved[3]; | |
355 | }; | |
356 | ||
357 | /* Ramrod data for tx queue stop ramrod */ | |
358 | struct core_tx_stop_ramrod_data { | |
359 | __le32 reserved0[2]; | |
360 | }; | |
361 | ||
da090917 TT |
362 | /* Ramrod data for tx queue update ramrod */ |
363 | struct core_tx_update_ramrod_data { | |
364 | u8 update_qm_pq_id_flg; | |
365 | u8 reserved0; | |
366 | __le16 qm_pq_id; | |
367 | __le32 reserved1[1]; | |
368 | }; | |
369 | ||
a2e7699e TT |
370 | /* Enum flag for what type of dcb data to update */ |
371 | enum dcb_dscp_update_mode { | |
372 | DONT_UPDATE_DCB_DSCP, | |
373 | UPDATE_DCB, | |
374 | UPDATE_DSCP, | |
375 | UPDATE_DCB_DSCP, | |
376 | MAX_DCB_DSCP_UPDATE_MODE | |
377 | }; | |
378 | ||
fe56b9e6 YM |
379 | /* The core storm context for the Ystorm */ |
380 | struct ystorm_core_conn_st_ctx { | |
381 | __le32 reserved[4]; | |
382 | }; | |
383 | ||
384 | /* The core storm context for the Pstorm */ | |
385 | struct pstorm_core_conn_st_ctx { | |
386 | __le32 reserved[4]; | |
387 | }; | |
388 | ||
389 | /* Core Slowpath Connection storm context of Xstorm */ | |
390 | struct xstorm_core_conn_st_ctx { | |
351a4ded YM |
391 | __le32 spq_base_lo; |
392 | __le32 spq_base_hi; | |
393 | struct regpair consolid_base_addr; | |
394 | __le16 spq_cons; | |
395 | __le16 consolid_cons; | |
396 | __le32 reserved0[55]; | |
fe56b9e6 YM |
397 | }; |
398 | ||
21dd79e8 | 399 | struct e4_xstorm_core_conn_ag_ctx { |
351a4ded | 400 | u8 reserved0; |
da090917 | 401 | u8 state; |
351a4ded | 402 | u8 flags0; |
21dd79e8 TT |
403 | #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
404 | #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
405 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1 | |
406 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1 | |
407 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1 | |
408 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2 | |
409 | #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
410 | #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
411 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1 | |
412 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4 | |
413 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1 | |
414 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5 | |
415 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 | |
416 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6 | |
417 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 | |
418 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7 | |
fe56b9e6 | 419 | u8 flags1; |
21dd79e8 TT |
420 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 |
421 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0 | |
422 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 | |
423 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1 | |
424 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 | |
425 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2 | |
426 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 | |
427 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3 | |
428 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 | |
429 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4 | |
430 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 | |
431 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5 | |
432 | #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 | |
433 | #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 | |
434 | #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 | |
435 | #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 | |
fe56b9e6 | 436 | u8 flags2; |
21dd79e8 TT |
437 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 |
438 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0 | |
439 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 | |
440 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2 | |
441 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 | |
442 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4 | |
443 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 | |
444 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6 | |
fe56b9e6 | 445 | u8 flags3; |
21dd79e8 TT |
446 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 |
447 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0 | |
448 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 | |
449 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2 | |
450 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 | |
451 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4 | |
452 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 | |
453 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6 | |
fe56b9e6 | 454 | u8 flags4; |
21dd79e8 TT |
455 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 |
456 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0 | |
457 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 | |
458 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2 | |
459 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 | |
460 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4 | |
461 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 | |
462 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6 | |
fe56b9e6 | 463 | u8 flags5; |
21dd79e8 TT |
464 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 |
465 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0 | |
466 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 | |
467 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2 | |
468 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 | |
469 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4 | |
470 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 | |
471 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6 | |
fe56b9e6 | 472 | u8 flags6; |
21dd79e8 TT |
473 | #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 |
474 | #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0 | |
475 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3 | |
476 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2 | |
477 | #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 | |
478 | #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4 | |
479 | #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 | |
480 | #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 | |
fe56b9e6 | 481 | u8 flags7; |
21dd79e8 TT |
482 | #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 |
483 | #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 | |
484 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 | |
485 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2 | |
486 | #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 | |
487 | #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
488 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 | |
489 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6 | |
490 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
491 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7 | |
fe56b9e6 | 492 | u8 flags8; |
21dd79e8 TT |
493 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 |
494 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0 | |
495 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 | |
496 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1 | |
497 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 | |
498 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2 | |
499 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 | |
500 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3 | |
501 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 | |
502 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4 | |
503 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 | |
504 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5 | |
505 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 | |
506 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6 | |
507 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 | |
508 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7 | |
fe56b9e6 | 509 | u8 flags9; |
21dd79e8 TT |
510 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 |
511 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0 | |
512 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 | |
513 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1 | |
514 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 | |
515 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2 | |
516 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 | |
517 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3 | |
518 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 | |
519 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4 | |
520 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 | |
521 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5 | |
522 | #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 | |
523 | #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6 | |
524 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1 | |
525 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7 | |
fe56b9e6 | 526 | u8 flags10; |
21dd79e8 TT |
527 | #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 |
528 | #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 | |
529 | #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 | |
530 | #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 | |
531 | #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 | |
532 | #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 | |
533 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 | |
534 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3 | |
535 | #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
536 | #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
537 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 | |
538 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5 | |
539 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 | |
540 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6 | |
541 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 | |
542 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7 | |
fe56b9e6 | 543 | u8 flags11; |
21dd79e8 TT |
544 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 |
545 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0 | |
546 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 | |
547 | #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1 | |
548 | #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 | |
549 | #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 | |
550 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
551 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
552 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
553 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
554 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
555 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5 | |
556 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
557 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
558 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 | |
559 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7 | |
fe56b9e6 | 560 | u8 flags12; |
21dd79e8 TT |
561 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 |
562 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0 | |
563 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 | |
564 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1 | |
565 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
566 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
567 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
568 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
569 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 | |
570 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4 | |
571 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
572 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
573 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 | |
574 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6 | |
575 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 | |
576 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7 | |
fe56b9e6 | 577 | u8 flags13; |
21dd79e8 TT |
578 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 |
579 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0 | |
580 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 | |
581 | #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1 | |
582 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 | |
583 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 | |
584 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 | |
585 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 | |
586 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
587 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
588 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 | |
589 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 | |
590 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
591 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
592 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
593 | #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
fe56b9e6 | 594 | u8 flags14; |
21dd79e8 TT |
595 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 |
596 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0 | |
597 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 | |
598 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1 | |
599 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 | |
600 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2 | |
601 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 | |
602 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3 | |
603 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 | |
604 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4 | |
605 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 | |
606 | #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5 | |
607 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 | |
608 | #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6 | |
351a4ded YM |
609 | u8 byte2; |
610 | __le16 physical_q0; | |
611 | __le16 consolid_prod; | |
612 | __le16 reserved16; | |
613 | __le16 tx_bd_cons; | |
614 | __le16 tx_bd_or_spq_prod; | |
50bc60cb | 615 | __le16 updated_qm_pq_id; |
351a4ded YM |
616 | __le16 conn_dpi; |
617 | u8 byte3; | |
618 | u8 byte4; | |
619 | u8 byte5; | |
620 | u8 byte6; | |
621 | __le32 reg0; | |
622 | __le32 reg1; | |
623 | __le32 reg2; | |
624 | __le32 reg3; | |
625 | __le32 reg4; | |
626 | __le32 reg5; | |
627 | __le32 reg6; | |
628 | __le16 word7; | |
629 | __le16 word8; | |
630 | __le16 word9; | |
631 | __le16 word10; | |
632 | __le32 reg7; | |
633 | __le32 reg8; | |
634 | __le32 reg9; | |
635 | u8 byte7; | |
636 | u8 byte8; | |
637 | u8 byte9; | |
638 | u8 byte10; | |
639 | u8 byte11; | |
640 | u8 byte12; | |
641 | u8 byte13; | |
642 | u8 byte14; | |
643 | u8 byte15; | |
7b6859fb | 644 | u8 e5_reserved; |
351a4ded YM |
645 | __le16 word11; |
646 | __le32 reg10; | |
647 | __le32 reg11; | |
648 | __le32 reg12; | |
649 | __le32 reg13; | |
650 | __le32 reg14; | |
651 | __le32 reg15; | |
652 | __le32 reg16; | |
653 | __le32 reg17; | |
654 | __le32 reg18; | |
655 | __le32 reg19; | |
656 | __le16 word12; | |
657 | __le16 word13; | |
658 | __le16 word14; | |
659 | __le16 word15; | |
fe56b9e6 YM |
660 | }; |
661 | ||
21dd79e8 | 662 | struct e4_tstorm_core_conn_ag_ctx { |
351a4ded YM |
663 | u8 byte0; |
664 | u8 byte1; | |
665 | u8 flags0; | |
21dd79e8 TT |
666 | #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 |
667 | #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 | |
668 | #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 | |
669 | #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 | |
670 | #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 | |
671 | #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2 | |
672 | #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 | |
673 | #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3 | |
674 | #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 | |
675 | #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4 | |
676 | #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 | |
677 | #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5 | |
678 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 | |
679 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6 | |
fc48b7a6 | 680 | u8 flags1; |
21dd79e8 TT |
681 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 |
682 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0 | |
683 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 | |
684 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2 | |
685 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 | |
686 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4 | |
687 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 | |
688 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6 | |
fc48b7a6 | 689 | u8 flags2; |
21dd79e8 TT |
690 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 |
691 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0 | |
692 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 | |
693 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2 | |
694 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 | |
695 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4 | |
696 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 | |
697 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6 | |
fc48b7a6 | 698 | u8 flags3; |
21dd79e8 TT |
699 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 |
700 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0 | |
701 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 | |
702 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2 | |
703 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 | |
704 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4 | |
705 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
706 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5 | |
707 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 | |
708 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6 | |
709 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 | |
710 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7 | |
fc48b7a6 | 711 | u8 flags4; |
21dd79e8 TT |
712 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 |
713 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0 | |
714 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 | |
715 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1 | |
716 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 | |
717 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2 | |
718 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 | |
719 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3 | |
720 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 | |
721 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4 | |
722 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 | |
723 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5 | |
724 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 | |
725 | #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6 | |
726 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
727 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
fc48b7a6 | 728 | u8 flags5; |
21dd79e8 TT |
729 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 |
730 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
731 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
732 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
733 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
734 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
735 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
736 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
737 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
738 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
739 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
740 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
741 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
742 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
743 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
744 | #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
351a4ded YM |
745 | __le32 reg0; |
746 | __le32 reg1; | |
747 | __le32 reg2; | |
748 | __le32 reg3; | |
749 | __le32 reg4; | |
750 | __le32 reg5; | |
751 | __le32 reg6; | |
752 | __le32 reg7; | |
753 | __le32 reg8; | |
754 | u8 byte2; | |
755 | u8 byte3; | |
756 | __le16 word0; | |
757 | u8 byte4; | |
758 | u8 byte5; | |
759 | __le16 word1; | |
760 | __le16 word2; | |
761 | __le16 word3; | |
762 | __le32 reg9; | |
763 | __le32 reg10; | |
fc48b7a6 YM |
764 | }; |
765 | ||
21dd79e8 | 766 | struct e4_ustorm_core_conn_ag_ctx { |
351a4ded YM |
767 | u8 reserved; |
768 | u8 byte1; | |
769 | u8 flags0; | |
21dd79e8 TT |
770 | #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 |
771 | #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 | |
772 | #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 | |
773 | #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 | |
774 | #define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 | |
775 | #define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 | |
776 | #define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 | |
777 | #define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 | |
778 | #define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 | |
779 | #define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 | |
fc48b7a6 | 780 | u8 flags1; |
21dd79e8 TT |
781 | #define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 |
782 | #define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0 | |
783 | #define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 | |
784 | #define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2 | |
785 | #define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 | |
786 | #define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4 | |
787 | #define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 | |
788 | #define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6 | |
fc48b7a6 | 789 | u8 flags2; |
21dd79e8 TT |
790 | #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 |
791 | #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 | |
792 | #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
793 | #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 | |
794 | #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 | |
795 | #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 | |
796 | #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 | |
797 | #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3 | |
798 | #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 | |
799 | #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4 | |
800 | #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 | |
801 | #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5 | |
802 | #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 | |
803 | #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6 | |
804 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
805 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
fc48b7a6 | 806 | u8 flags3; |
21dd79e8 TT |
807 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 |
808 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
809 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
810 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
811 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
812 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
813 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
814 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
815 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
816 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
817 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
818 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
819 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
820 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
821 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
822 | #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
351a4ded YM |
823 | u8 byte2; |
824 | u8 byte3; | |
825 | __le16 word0; | |
826 | __le16 word1; | |
827 | __le32 rx_producers; | |
828 | __le32 reg1; | |
829 | __le32 reg2; | |
830 | __le32 reg3; | |
831 | __le16 word2; | |
832 | __le16 word3; | |
fc48b7a6 YM |
833 | }; |
834 | ||
fe56b9e6 YM |
835 | /* The core storm context for the Mstorm */ |
836 | struct mstorm_core_conn_st_ctx { | |
837 | __le32 reserved[24]; | |
838 | }; | |
839 | ||
840 | /* The core storm context for the Ustorm */ | |
841 | struct ustorm_core_conn_st_ctx { | |
842 | __le32 reserved[4]; | |
843 | }; | |
844 | ||
845 | /* core connection context */ | |
21dd79e8 | 846 | struct e4_core_conn_context { |
351a4ded | 847 | struct ystorm_core_conn_st_ctx ystorm_st_context; |
a2e7699e TT |
848 | struct regpair ystorm_st_padding[2]; |
849 | struct pstorm_core_conn_st_ctx pstorm_st_context; | |
850 | struct regpair pstorm_st_padding[2]; | |
851 | struct xstorm_core_conn_st_ctx xstorm_st_context; | |
21dd79e8 TT |
852 | struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context; |
853 | struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context; | |
854 | struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context; | |
a2e7699e TT |
855 | struct mstorm_core_conn_st_ctx mstorm_st_context; |
856 | struct ustorm_core_conn_st_ctx ustorm_st_context; | |
857 | struct regpair ustorm_st_padding[2]; | |
be086e7c MY |
858 | }; |
859 | ||
351a4ded YM |
860 | struct eth_mstorm_per_pf_stat { |
861 | struct regpair gre_discard_pkts; | |
862 | struct regpair vxlan_discard_pkts; | |
863 | struct regpair geneve_discard_pkts; | |
864 | struct regpair lb_discard_pkts; | |
fe56b9e6 YM |
865 | }; |
866 | ||
9df2ed04 | 867 | struct eth_mstorm_per_queue_stat { |
351a4ded YM |
868 | struct regpair ttl0_discard; |
869 | struct regpair packet_too_big_discard; | |
870 | struct regpair no_buff_discard; | |
871 | struct regpair not_active_discard; | |
872 | struct regpair tpa_coalesced_pkts; | |
873 | struct regpair tpa_coalesced_events; | |
874 | struct regpair tpa_aborts_num; | |
875 | struct regpair tpa_coalesced_bytes; | |
876 | }; | |
877 | ||
878 | /* Ethernet TX Per PF */ | |
879 | struct eth_pstorm_per_pf_stat { | |
880 | struct regpair sent_lb_ucast_bytes; | |
881 | struct regpair sent_lb_mcast_bytes; | |
882 | struct regpair sent_lb_bcast_bytes; | |
883 | struct regpair sent_lb_ucast_pkts; | |
884 | struct regpair sent_lb_mcast_pkts; | |
885 | struct regpair sent_lb_bcast_pkts; | |
886 | struct regpair sent_gre_bytes; | |
887 | struct regpair sent_vxlan_bytes; | |
888 | struct regpair sent_geneve_bytes; | |
889 | struct regpair sent_gre_pkts; | |
890 | struct regpair sent_vxlan_pkts; | |
891 | struct regpair sent_geneve_pkts; | |
892 | struct regpair gre_drop_pkts; | |
893 | struct regpair vxlan_drop_pkts; | |
894 | struct regpair geneve_drop_pkts; | |
895 | }; | |
896 | ||
897 | /* Ethernet TX Per Queue Stats */ | |
898 | struct eth_pstorm_per_queue_stat { | |
899 | struct regpair sent_ucast_bytes; | |
900 | struct regpair sent_mcast_bytes; | |
901 | struct regpair sent_bcast_bytes; | |
902 | struct regpair sent_ucast_pkts; | |
903 | struct regpair sent_mcast_pkts; | |
904 | struct regpair sent_bcast_pkts; | |
905 | struct regpair error_drop_pkts; | |
906 | }; | |
907 | ||
908 | /* ETH Rx producers data */ | |
909 | struct eth_rx_rate_limit { | |
910 | __le16 mult; | |
911 | __le16 cnst; | |
912 | u8 add_sub_cnst; | |
913 | u8 reserved0; | |
914 | __le16 reserved1; | |
9df2ed04 MC |
915 | }; |
916 | ||
351a4ded YM |
917 | struct eth_ustorm_per_pf_stat { |
918 | struct regpair rcv_lb_ucast_bytes; | |
919 | struct regpair rcv_lb_mcast_bytes; | |
920 | struct regpair rcv_lb_bcast_bytes; | |
921 | struct regpair rcv_lb_ucast_pkts; | |
922 | struct regpair rcv_lb_mcast_pkts; | |
923 | struct regpair rcv_lb_bcast_pkts; | |
924 | struct regpair rcv_gre_bytes; | |
925 | struct regpair rcv_vxlan_bytes; | |
926 | struct regpair rcv_geneve_bytes; | |
927 | struct regpair rcv_gre_pkts; | |
928 | struct regpair rcv_vxlan_pkts; | |
929 | struct regpair rcv_geneve_pkts; | |
9df2ed04 MC |
930 | }; |
931 | ||
932 | struct eth_ustorm_per_queue_stat { | |
351a4ded YM |
933 | struct regpair rcv_ucast_bytes; |
934 | struct regpair rcv_mcast_bytes; | |
935 | struct regpair rcv_bcast_bytes; | |
936 | struct regpair rcv_ucast_pkts; | |
937 | struct regpair rcv_mcast_pkts; | |
938 | struct regpair rcv_bcast_pkts; | |
9df2ed04 MC |
939 | }; |
940 | ||
a2e7699e TT |
941 | /* Event Ring VF-PF Channel data */ |
942 | struct vf_pf_channel_eqe_data { | |
943 | struct regpair msg_addr; | |
944 | }; | |
945 | ||
946 | /* Event Ring malicious VF data */ | |
947 | struct malicious_vf_eqe_data { | |
948 | u8 vf_id; | |
949 | u8 err_id; | |
950 | __le16 reserved[3]; | |
951 | }; | |
952 | ||
953 | /* Event Ring initial cleanup data */ | |
954 | struct initial_cleanup_eqe_data { | |
955 | u8 vf_id; | |
956 | u8 reserved[7]; | |
957 | }; | |
958 | ||
959 | /* Event Data Union */ | |
960 | union event_ring_data { | |
961 | u8 bytes[8]; | |
962 | struct vf_pf_channel_eqe_data vf_pf_channel; | |
963 | struct iscsi_eqe_data iscsi_info; | |
da090917 | 964 | struct iscsi_connect_done_results iscsi_conn_done_info; |
a2e7699e TT |
965 | union rdma_eqe_data rdma_data; |
966 | struct malicious_vf_eqe_data malicious_vf; | |
967 | struct initial_cleanup_eqe_data vf_init_cleanup; | |
968 | }; | |
969 | ||
970 | /* Event Ring Entry */ | |
971 | struct event_ring_entry { | |
972 | u8 protocol_id; | |
973 | u8 opcode; | |
974 | __le16 reserved0; | |
975 | __le16 echo; | |
976 | u8 fw_return_code; | |
977 | u8 flags; | |
978 | #define EVENT_RING_ENTRY_ASYNC_MASK 0x1 | |
979 | #define EVENT_RING_ENTRY_ASYNC_SHIFT 0 | |
980 | #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F | |
981 | #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1 | |
982 | union event_ring_data data; | |
983 | }; | |
984 | ||
fe56b9e6 YM |
985 | /* Event Ring Next Page Address */ |
986 | struct event_ring_next_addr { | |
351a4ded YM |
987 | struct regpair addr; |
988 | __le32 reserved[2]; | |
fe56b9e6 YM |
989 | }; |
990 | ||
351a4ded | 991 | /* Event Ring Element */ |
fe56b9e6 | 992 | union event_ring_element { |
351a4ded YM |
993 | struct event_ring_entry entry; |
994 | struct event_ring_next_addr next_addr; | |
995 | }; | |
996 | ||
a2e7699e | 997 | /* Ports mode */ |
be086e7c MY |
998 | enum fw_flow_ctrl_mode { |
999 | flow_ctrl_pause, | |
1000 | flow_ctrl_pfc, | |
1001 | MAX_FW_FLOW_CTRL_MODE | |
1002 | }; | |
1003 | ||
da090917 TT |
1004 | /* GFT profile type */ |
1005 | enum gft_profile_type { | |
1006 | GFT_PROFILE_TYPE_4_TUPLE, | |
1007 | GFT_PROFILE_TYPE_L4_DST_PORT, | |
50bc60cb MK |
1008 | GFT_PROFILE_TYPE_IP_DST_ADDR, |
1009 | GFT_PROFILE_TYPE_IP_SRC_ADDR, | |
1010 | GFT_PROFILE_TYPE_TUNNEL_TYPE, | |
da090917 TT |
1011 | MAX_GFT_PROFILE_TYPE |
1012 | }; | |
1013 | ||
351a4ded YM |
1014 | /* Major and Minor hsi Versions */ |
1015 | struct hsi_fp_ver_struct { | |
1016 | u8 minor_ver_arr[2]; | |
1017 | u8 major_ver_arr[2]; | |
fe56b9e6 YM |
1018 | }; |
1019 | ||
7b6859fb | 1020 | enum iwarp_ll2_tx_queues { |
a2e7699e | 1021 | IWARP_LL2_IN_ORDER_TX_QUEUE = 1, |
7b6859fb MY |
1022 | IWARP_LL2_ALIGNED_TX_QUEUE, |
1023 | IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE, | |
1024 | IWARP_LL2_ERROR, | |
1025 | MAX_IWARP_LL2_TX_QUEUES | |
1026 | }; | |
1027 | ||
a2e7699e | 1028 | /* Malicious VF error ID */ |
05fafbfb YM |
1029 | enum malicious_vf_error_id { |
1030 | MALICIOUS_VF_NO_ERROR, | |
1031 | VF_PF_CHANNEL_NOT_READY, | |
1032 | VF_ZONE_MSG_NOT_VALID, | |
1033 | VF_ZONE_FUNC_NOT_ENABLED, | |
1034 | ETH_PACKET_TOO_SMALL, | |
1035 | ETH_ILLEGAL_VLAN_MODE, | |
1036 | ETH_MTU_VIOLATION, | |
1037 | ETH_ILLEGAL_INBAND_TAGS, | |
1038 | ETH_VLAN_INSERT_AND_INBAND_VLAN, | |
1039 | ETH_ILLEGAL_NBDS, | |
1040 | ETH_FIRST_BD_WO_SOP, | |
1041 | ETH_INSUFFICIENT_BDS, | |
1042 | ETH_ILLEGAL_LSO_HDR_NBDS, | |
1043 | ETH_ILLEGAL_LSO_MSS, | |
1044 | ETH_ZERO_SIZE_BD, | |
1045 | ETH_ILLEGAL_LSO_HDR_LEN, | |
1046 | ETH_INSUFFICIENT_PAYLOAD, | |
1047 | ETH_EDPM_OUT_OF_SYNC, | |
1048 | ETH_TUNN_IPV6_EXT_NBD_ERR, | |
1049 | ETH_CONTROL_PACKET_VIOLATION, | |
be086e7c | 1050 | ETH_ANTI_SPOOFING_ERR, |
da090917 | 1051 | ETH_PACKET_SIZE_TOO_LARGE, |
05fafbfb YM |
1052 | MAX_MALICIOUS_VF_ERROR_ID |
1053 | }; | |
1054 | ||
a2e7699e | 1055 | /* Mstorm non-triggering VF zone */ |
1408cc1f YM |
1056 | struct mstorm_non_trigger_vf_zone { |
1057 | struct eth_mstorm_per_queue_stat eth_queue_stat; | |
05fafbfb | 1058 | struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD]; |
1408cc1f YM |
1059 | }; |
1060 | ||
351a4ded | 1061 | /* Mstorm VF zone */ |
1408cc1f YM |
1062 | struct mstorm_vf_zone { |
1063 | struct mstorm_non_trigger_vf_zone non_trigger; | |
1064 | }; | |
1065 | ||
da090917 TT |
1066 | /* vlan header including TPID and TCI fields */ |
1067 | struct vlan_header { | |
1068 | __le16 tpid; | |
1069 | __le16 tci; | |
1070 | }; | |
1071 | ||
1072 | /* outer tag configurations */ | |
1073 | struct outer_tag_config_struct { | |
1074 | u8 enable_stag_pri_change; | |
1075 | u8 pri_map_valid; | |
1076 | u8 reserved[2]; | |
1077 | struct vlan_header outer_tag; | |
1078 | u8 inner_to_outer_pri_map[8]; | |
1079 | }; | |
1080 | ||
351a4ded | 1081 | /* personality per PF */ |
fe56b9e6 | 1082 | enum personality_type { |
fc48b7a6 | 1083 | BAD_PERSONALITY_TYP, |
c5ac9319 | 1084 | PERSONALITY_ISCSI, |
1e128c81 | 1085 | PERSONALITY_FCOE, |
351a4ded | 1086 | PERSONALITY_RDMA_AND_ETH, |
7b6859fb | 1087 | PERSONALITY_RDMA, |
fc48b7a6 | 1088 | PERSONALITY_CORE, |
351a4ded | 1089 | PERSONALITY_ETH, |
a2e7699e | 1090 | PERSONALITY_RESERVED, |
fe56b9e6 YM |
1091 | MAX_PERSONALITY_TYPE |
1092 | }; | |
1093 | ||
351a4ded | 1094 | /* tunnel configuration */ |
fe56b9e6 | 1095 | struct pf_start_tunnel_config { |
351a4ded YM |
1096 | u8 set_vxlan_udp_port_flg; |
1097 | u8 set_geneve_udp_port_flg; | |
351a4ded YM |
1098 | u8 tunnel_clss_vxlan; |
1099 | u8 tunnel_clss_l2geneve; | |
1100 | u8 tunnel_clss_ipgeneve; | |
1101 | u8 tunnel_clss_l2gre; | |
1102 | u8 tunnel_clss_ipgre; | |
7b6859fb | 1103 | u8 reserved; |
351a4ded YM |
1104 | __le16 vxlan_udp_port; |
1105 | __le16 geneve_udp_port; | |
fe56b9e6 YM |
1106 | }; |
1107 | ||
1108 | /* Ramrod data for PF start ramrod */ | |
1109 | struct pf_start_ramrod_data { | |
351a4ded YM |
1110 | struct regpair event_ring_pbl_addr; |
1111 | struct regpair consolid_q_pbl_addr; | |
1112 | struct pf_start_tunnel_config tunnel_config; | |
1113 | __le16 event_ring_sb_id; | |
1114 | u8 base_vf_id; | |
1115 | u8 num_vfs; | |
1116 | u8 event_ring_num_pages; | |
1117 | u8 event_ring_sb_index; | |
1118 | u8 path_id; | |
1119 | u8 warning_as_error; | |
1120 | u8 dont_log_ramrods; | |
1121 | u8 personality; | |
1122 | __le16 log_type_mask; | |
1123 | u8 mf_mode; | |
1124 | u8 integ_phase; | |
1125 | u8 allow_npar_tx_switching; | |
da090917 | 1126 | u8 reserved0; |
351a4ded | 1127 | struct hsi_fp_ver_struct hsi_fp_ver; |
da090917 | 1128 | struct outer_tag_config_struct outer_tag_config; |
351a4ded YM |
1129 | }; |
1130 | ||
a2e7699e | 1131 | /* Data for port update ramrod */ |
39651abd SRK |
1132 | struct protocol_dcb_data { |
1133 | u8 dcb_enable_flag; | |
da090917 | 1134 | u8 dscp_enable_flag; |
39651abd SRK |
1135 | u8 dcb_priority; |
1136 | u8 dcb_tc; | |
da090917 | 1137 | u8 dscp_val; |
50bc60cb | 1138 | u8 dcb_dont_add_vlan0; |
39651abd SRK |
1139 | }; |
1140 | ||
a2e7699e | 1141 | /* Update tunnel configuration */ |
464f6645 | 1142 | struct pf_update_tunnel_config { |
351a4ded | 1143 | u8 update_rx_pf_clss; |
05fafbfb YM |
1144 | u8 update_rx_def_ucast_clss; |
1145 | u8 update_rx_def_non_ucast_clss; | |
351a4ded YM |
1146 | u8 set_vxlan_udp_port_flg; |
1147 | u8 set_geneve_udp_port_flg; | |
351a4ded YM |
1148 | u8 tunnel_clss_vxlan; |
1149 | u8 tunnel_clss_l2geneve; | |
1150 | u8 tunnel_clss_ipgeneve; | |
1151 | u8 tunnel_clss_l2gre; | |
1152 | u8 tunnel_clss_ipgre; | |
1153 | __le16 vxlan_udp_port; | |
1154 | __le16 geneve_udp_port; | |
7b6859fb | 1155 | __le16 reserved; |
464f6645 MC |
1156 | }; |
1157 | ||
a2e7699e | 1158 | /* Data for port update ramrod */ |
464f6645 | 1159 | struct pf_update_ramrod_data { |
7b6859fb MY |
1160 | u8 update_eth_dcb_data_mode; |
1161 | u8 update_fcoe_dcb_data_mode; | |
1162 | u8 update_iscsi_dcb_data_mode; | |
1163 | u8 update_roce_dcb_data_mode; | |
1164 | u8 update_rroce_dcb_data_mode; | |
1165 | u8 update_iwarp_dcb_data_mode; | |
39651abd | 1166 | u8 update_mf_vlan_flag; |
da090917 | 1167 | u8 update_enable_stag_pri_change; |
39651abd SRK |
1168 | struct protocol_dcb_data eth_dcb_data; |
1169 | struct protocol_dcb_data fcoe_dcb_data; | |
1170 | struct protocol_dcb_data iscsi_dcb_data; | |
1171 | struct protocol_dcb_data roce_dcb_data; | |
05fafbfb | 1172 | struct protocol_dcb_data rroce_dcb_data; |
351a4ded YM |
1173 | struct protocol_dcb_data iwarp_dcb_data; |
1174 | __le16 mf_vlan; | |
da090917 TT |
1175 | u8 enable_stag_pri_change; |
1176 | u8 reserved; | |
351a4ded | 1177 | struct pf_update_tunnel_config tunnel_config; |
464f6645 MC |
1178 | }; |
1179 | ||
351a4ded | 1180 | /* Ports mode */ |
fe56b9e6 | 1181 | enum ports_mode { |
351a4ded YM |
1182 | ENGX2_PORTX1, |
1183 | ENGX2_PORTX2, | |
1184 | ENGX1_PORTX1, | |
1185 | ENGX1_PORTX2, | |
1186 | ENGX1_PORTX4, | |
fe56b9e6 YM |
1187 | MAX_PORTS_MODE |
1188 | }; | |
1189 | ||
351a4ded YM |
1190 | /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */ |
1191 | enum protocol_version_array_key { | |
1192 | ETH_VER_KEY = 0, | |
1193 | ROCE_VER_KEY, | |
1194 | MAX_PROTOCOL_VERSION_ARRAY_KEY | |
1195 | }; | |
1196 | ||
a2e7699e | 1197 | /* RDMA TX Stats */ |
05fafbfb YM |
1198 | struct rdma_sent_stats { |
1199 | struct regpair sent_bytes; | |
1200 | struct regpair sent_pkts; | |
1201 | }; | |
1202 | ||
a2e7699e | 1203 | /* Pstorm non-triggering VF zone */ |
1408cc1f YM |
1204 | struct pstorm_non_trigger_vf_zone { |
1205 | struct eth_pstorm_per_queue_stat eth_queue_stat; | |
05fafbfb | 1206 | struct rdma_sent_stats rdma_stats; |
1408cc1f YM |
1207 | }; |
1208 | ||
351a4ded | 1209 | /* Pstorm VF zone */ |
1408cc1f YM |
1210 | struct pstorm_vf_zone { |
1211 | struct pstorm_non_trigger_vf_zone non_trigger; | |
1212 | struct regpair reserved[7]; | |
1213 | }; | |
1214 | ||
fe56b9e6 YM |
1215 | /* Ramrod Header of SPQE */ |
1216 | struct ramrod_header { | |
351a4ded YM |
1217 | __le32 cid; |
1218 | u8 cmd_id; | |
1219 | u8 protocol_id; | |
1220 | __le16 echo; | |
fe56b9e6 YM |
1221 | }; |
1222 | ||
a2e7699e | 1223 | /* RDMA RX Stats */ |
05fafbfb YM |
1224 | struct rdma_rcv_stats { |
1225 | struct regpair rcv_bytes; | |
1226 | struct regpair rcv_pkts; | |
1227 | }; | |
1228 | ||
da090917 TT |
1229 | /* Data for update QCN/DCQCN RL ramrod */ |
1230 | struct rl_update_ramrod_data { | |
1231 | u8 qcn_update_param_flg; | |
1232 | u8 dcqcn_update_param_flg; | |
1233 | u8 rl_init_flg; | |
1234 | u8 rl_start_flg; | |
1235 | u8 rl_stop_flg; | |
1236 | u8 rl_id_first; | |
1237 | u8 rl_id_last; | |
1238 | u8 rl_dc_qcn_flg; | |
1239 | __le32 rl_bc_rate; | |
1240 | __le16 rl_max_rate; | |
1241 | __le16 rl_r_ai; | |
1242 | __le16 rl_r_hai; | |
1243 | __le16 dcqcn_g; | |
1244 | __le32 dcqcn_k_us; | |
1245 | __le32 dcqcn_timeuot_us; | |
1246 | __le32 qcn_timeuot_us; | |
1247 | __le32 reserved[2]; | |
1248 | }; | |
1249 | ||
a2e7699e | 1250 | /* Slowpath Element (SPQE) */ |
fe56b9e6 | 1251 | struct slow_path_element { |
351a4ded YM |
1252 | struct ramrod_header hdr; |
1253 | struct regpair data_ptr; | |
1254 | }; | |
1255 | ||
1256 | /* Tstorm non-triggering VF zone */ | |
1257 | struct tstorm_non_trigger_vf_zone { | |
05fafbfb | 1258 | struct rdma_rcv_stats rdma_stats; |
fe56b9e6 YM |
1259 | }; |
1260 | ||
1261 | struct tstorm_per_port_stat { | |
351a4ded YM |
1262 | struct regpair trunc_error_discard; |
1263 | struct regpair mac_error_discard; | |
1264 | struct regpair mftag_filter_discard; | |
1265 | struct regpair eth_mac_filter_discard; | |
05fafbfb YM |
1266 | struct regpair ll2_mac_filter_discard; |
1267 | struct regpair ll2_conn_disabled_discard; | |
1268 | struct regpair iscsi_irregular_pkt; | |
be086e7c | 1269 | struct regpair fcoe_irregular_pkt; |
05fafbfb | 1270 | struct regpair roce_irregular_pkt; |
7b6859fb | 1271 | struct regpair iwarp_irregular_pkt; |
351a4ded | 1272 | struct regpair eth_irregular_pkt; |
da090917 | 1273 | struct regpair toe_irregular_pkt; |
05fafbfb | 1274 | struct regpair preroce_irregular_pkt; |
351a4ded YM |
1275 | struct regpair eth_gre_tunn_filter_discard; |
1276 | struct regpair eth_vxlan_tunn_filter_discard; | |
1277 | struct regpair eth_geneve_tunn_filter_discard; | |
da090917 | 1278 | struct regpair eth_gft_drop_pkt; |
fe56b9e6 YM |
1279 | }; |
1280 | ||
351a4ded YM |
1281 | /* Tstorm VF zone */ |
1282 | struct tstorm_vf_zone { | |
1283 | struct tstorm_non_trigger_vf_zone non_trigger; | |
1284 | }; | |
1285 | ||
1286 | /* Tunnel classification scheme */ | |
1287 | enum tunnel_clss { | |
1288 | TUNNEL_CLSS_MAC_VLAN = 0, | |
1289 | TUNNEL_CLSS_MAC_VNI, | |
1290 | TUNNEL_CLSS_INNER_MAC_VLAN, | |
1291 | TUNNEL_CLSS_INNER_MAC_VNI, | |
1292 | TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE, | |
1293 | MAX_TUNNEL_CLSS | |
1294 | }; | |
1295 | ||
1296 | /* Ustorm non-triggering VF zone */ | |
1408cc1f YM |
1297 | struct ustorm_non_trigger_vf_zone { |
1298 | struct eth_ustorm_per_queue_stat eth_queue_stat; | |
1299 | struct regpair vf_pf_msg_addr; | |
1300 | }; | |
1301 | ||
351a4ded | 1302 | /* Ustorm triggering VF zone */ |
1408cc1f YM |
1303 | struct ustorm_trigger_vf_zone { |
1304 | u8 vf_pf_msg_valid; | |
1305 | u8 reserved[7]; | |
1306 | }; | |
1307 | ||
351a4ded | 1308 | /* Ustorm VF zone */ |
1408cc1f YM |
1309 | struct ustorm_vf_zone { |
1310 | struct ustorm_non_trigger_vf_zone non_trigger; | |
1311 | struct ustorm_trigger_vf_zone trigger; | |
1312 | }; | |
1313 | ||
351a4ded YM |
1314 | /* VF-PF channel data */ |
1315 | struct vf_pf_channel_data { | |
1316 | __le32 ready; | |
1317 | u8 valid; | |
1318 | u8 reserved0; | |
1319 | __le16 reserved1; | |
1320 | }; | |
1321 | ||
1322 | /* Ramrod data for VF start ramrod */ | |
1408cc1f YM |
1323 | struct vf_start_ramrod_data { |
1324 | u8 vf_id; | |
1325 | u8 enable_flr_ack; | |
1326 | __le16 opaque_fid; | |
1327 | u8 personality; | |
351a4ded YM |
1328 | u8 reserved[7]; |
1329 | struct hsi_fp_ver_struct hsi_fp_ver; | |
1330 | ||
1408cc1f YM |
1331 | }; |
1332 | ||
351a4ded | 1333 | /* Ramrod data for VF start ramrod */ |
0b55e27d YM |
1334 | struct vf_stop_ramrod_data { |
1335 | u8 vf_id; | |
1336 | u8 reserved0; | |
1337 | __le16 reserved1; | |
1338 | __le32 reserved2; | |
1339 | }; | |
1340 | ||
a2e7699e | 1341 | /* VF zone size mode */ |
05fafbfb YM |
1342 | enum vf_zone_size_mode { |
1343 | VF_ZONE_SIZE_MODE_DEFAULT, | |
1344 | VF_ZONE_SIZE_MODE_DOUBLE, | |
1345 | VF_ZONE_SIZE_MODE_QUAD, | |
1346 | MAX_VF_ZONE_SIZE_MODE | |
1347 | }; | |
1348 | ||
a2e7699e | 1349 | /* Attentions status block */ |
fe56b9e6 | 1350 | struct atten_status_block { |
351a4ded YM |
1351 | __le32 atten_bits; |
1352 | __le32 atten_ack; | |
1353 | __le16 reserved0; | |
1354 | __le16 sb_index; | |
1355 | __le32 reserved1; | |
1356 | }; | |
1357 | ||
351a4ded YM |
1358 | /* DMAE command */ |
1359 | struct dmae_cmd { | |
1360 | __le32 opcode; | |
1361 | #define DMAE_CMD_SRC_MASK 0x1 | |
1362 | #define DMAE_CMD_SRC_SHIFT 0 | |
1363 | #define DMAE_CMD_DST_MASK 0x3 | |
1364 | #define DMAE_CMD_DST_SHIFT 1 | |
1365 | #define DMAE_CMD_C_DST_MASK 0x1 | |
1366 | #define DMAE_CMD_C_DST_SHIFT 3 | |
1367 | #define DMAE_CMD_CRC_RESET_MASK 0x1 | |
1368 | #define DMAE_CMD_CRC_RESET_SHIFT 4 | |
1369 | #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1 | |
1370 | #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5 | |
1371 | #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1 | |
1372 | #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6 | |
1373 | #define DMAE_CMD_COMP_FUNC_MASK 0x1 | |
1374 | #define DMAE_CMD_COMP_FUNC_SHIFT 7 | |
1375 | #define DMAE_CMD_COMP_WORD_EN_MASK 0x1 | |
1376 | #define DMAE_CMD_COMP_WORD_EN_SHIFT 8 | |
1377 | #define DMAE_CMD_COMP_CRC_EN_MASK 0x1 | |
1378 | #define DMAE_CMD_COMP_CRC_EN_SHIFT 9 | |
1379 | #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7 | |
1380 | #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10 | |
1381 | #define DMAE_CMD_RESERVED1_MASK 0x1 | |
1382 | #define DMAE_CMD_RESERVED1_SHIFT 13 | |
1383 | #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3 | |
1384 | #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14 | |
1385 | #define DMAE_CMD_ERR_HANDLING_MASK 0x3 | |
1386 | #define DMAE_CMD_ERR_HANDLING_SHIFT 16 | |
1387 | #define DMAE_CMD_PORT_ID_MASK 0x3 | |
1388 | #define DMAE_CMD_PORT_ID_SHIFT 18 | |
1389 | #define DMAE_CMD_SRC_PF_ID_MASK 0xF | |
1390 | #define DMAE_CMD_SRC_PF_ID_SHIFT 20 | |
1391 | #define DMAE_CMD_DST_PF_ID_MASK 0xF | |
1392 | #define DMAE_CMD_DST_PF_ID_SHIFT 24 | |
1393 | #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1 | |
1394 | #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28 | |
1395 | #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1 | |
1396 | #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29 | |
1397 | #define DMAE_CMD_RESERVED2_MASK 0x3 | |
1398 | #define DMAE_CMD_RESERVED2_SHIFT 30 | |
1399 | __le32 src_addr_lo; | |
1400 | __le32 src_addr_hi; | |
1401 | __le32 dst_addr_lo; | |
1402 | __le32 dst_addr_hi; | |
1403 | __le16 length_dw; | |
1404 | __le16 opcode_b; | |
1405 | #define DMAE_CMD_SRC_VF_ID_MASK 0xFF | |
1406 | #define DMAE_CMD_SRC_VF_ID_SHIFT 0 | |
1407 | #define DMAE_CMD_DST_VF_ID_MASK 0xFF | |
1408 | #define DMAE_CMD_DST_VF_ID_SHIFT 8 | |
1409 | __le32 comp_addr_lo; | |
1410 | __le32 comp_addr_hi; | |
1411 | __le32 comp_val; | |
1412 | __le32 crc32; | |
1413 | __le32 crc_32_c; | |
1414 | __le16 crc16; | |
1415 | __le16 crc16_c; | |
1416 | __le16 crc10; | |
1417 | __le16 reserved; | |
1418 | __le16 xsum16; | |
1419 | __le16 xsum8; | |
1420 | }; | |
1421 | ||
1422 | enum dmae_cmd_comp_crc_en_enum { | |
1423 | dmae_cmd_comp_crc_disabled, | |
1424 | dmae_cmd_comp_crc_enabled, | |
1425 | MAX_DMAE_CMD_COMP_CRC_EN_ENUM | |
1426 | }; | |
1427 | ||
1428 | enum dmae_cmd_comp_func_enum { | |
1429 | dmae_cmd_comp_func_to_src, | |
1430 | dmae_cmd_comp_func_to_dst, | |
1431 | MAX_DMAE_CMD_COMP_FUNC_ENUM | |
1432 | }; | |
1433 | ||
1434 | enum dmae_cmd_comp_word_en_enum { | |
1435 | dmae_cmd_comp_word_disabled, | |
1436 | dmae_cmd_comp_word_enabled, | |
1437 | MAX_DMAE_CMD_COMP_WORD_EN_ENUM | |
1438 | }; | |
1439 | ||
1440 | enum dmae_cmd_c_dst_enum { | |
1441 | dmae_cmd_c_dst_pcie, | |
1442 | dmae_cmd_c_dst_grc, | |
1443 | MAX_DMAE_CMD_C_DST_ENUM | |
1444 | }; | |
1445 | ||
1446 | enum dmae_cmd_dst_enum { | |
1447 | dmae_cmd_dst_none_0, | |
1448 | dmae_cmd_dst_pcie, | |
1449 | dmae_cmd_dst_grc, | |
1450 | dmae_cmd_dst_none_3, | |
1451 | MAX_DMAE_CMD_DST_ENUM | |
1452 | }; | |
1453 | ||
1454 | enum dmae_cmd_error_handling_enum { | |
1455 | dmae_cmd_error_handling_send_regular_comp, | |
1456 | dmae_cmd_error_handling_send_comp_with_err, | |
1457 | dmae_cmd_error_handling_dont_send_comp, | |
1458 | MAX_DMAE_CMD_ERROR_HANDLING_ENUM | |
1459 | }; | |
1460 | ||
1461 | enum dmae_cmd_src_enum { | |
1462 | dmae_cmd_src_pcie, | |
1463 | dmae_cmd_src_grc, | |
1464 | MAX_DMAE_CMD_SRC_ENUM | |
1465 | }; | |
1466 | ||
21dd79e8 | 1467 | struct e4_mstorm_core_conn_ag_ctx { |
7b6859fb MY |
1468 | u8 byte0; |
1469 | u8 byte1; | |
1470 | u8 flags0; | |
21dd79e8 TT |
1471 | #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 |
1472 | #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 | |
1473 | #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 | |
1474 | #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 | |
1475 | #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 | |
1476 | #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 | |
1477 | #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 | |
1478 | #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 | |
1479 | #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 | |
1480 | #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 | |
7b6859fb | 1481 | u8 flags1; |
21dd79e8 TT |
1482 | #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 |
1483 | #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 | |
1484 | #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
1485 | #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 | |
1486 | #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 | |
1487 | #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 | |
1488 | #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
1489 | #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
1490 | #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
1491 | #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
1492 | #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
1493 | #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
1494 | #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
1495 | #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
1496 | #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
1497 | #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
7b6859fb MY |
1498 | __le16 word0; |
1499 | __le16 word1; | |
1500 | __le32 reg0; | |
1501 | __le32 reg1; | |
1502 | }; | |
1503 | ||
21dd79e8 | 1504 | struct e4_ystorm_core_conn_ag_ctx { |
7b6859fb MY |
1505 | u8 byte0; |
1506 | u8 byte1; | |
1507 | u8 flags0; | |
21dd79e8 TT |
1508 | #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 |
1509 | #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 | |
1510 | #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 | |
1511 | #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 | |
1512 | #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 | |
1513 | #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 | |
1514 | #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 | |
1515 | #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 | |
1516 | #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 | |
1517 | #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 | |
7b6859fb | 1518 | u8 flags1; |
21dd79e8 TT |
1519 | #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 |
1520 | #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 | |
1521 | #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
1522 | #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 | |
1523 | #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 | |
1524 | #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 | |
1525 | #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
1526 | #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
1527 | #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
1528 | #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
1529 | #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
1530 | #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
1531 | #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
1532 | #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
1533 | #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
1534 | #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
7b6859fb MY |
1535 | u8 byte2; |
1536 | u8 byte3; | |
1537 | __le16 word0; | |
1538 | __le32 reg0; | |
1539 | __le32 reg1; | |
1540 | __le16 word1; | |
1541 | __le16 word2; | |
1542 | __le16 word3; | |
1543 | __le16 word4; | |
1544 | __le32 reg2; | |
1545 | __le32 reg3; | |
1546 | }; | |
1547 | ||
351a4ded YM |
1548 | /* IGU cleanup command */ |
1549 | struct igu_cleanup { | |
1550 | __le32 sb_id_and_flags; | |
1551 | #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF | |
1552 | #define IGU_CLEANUP_RESERVED0_SHIFT 0 | |
1553 | #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1 | |
1554 | #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27 | |
1555 | #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7 | |
1556 | #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28 | |
1557 | #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1 | |
1558 | #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31 | |
1559 | __le32 reserved1; | |
1560 | }; | |
1561 | ||
1562 | /* IGU firmware driver command */ | |
1563 | union igu_command { | |
1564 | struct igu_prod_cons_update prod_cons_update; | |
1565 | struct igu_cleanup cleanup; | |
1566 | }; | |
1567 | ||
1568 | /* IGU firmware driver command */ | |
1569 | struct igu_command_reg_ctrl { | |
1570 | __le16 opaque_fid; | |
1571 | __le16 igu_command_reg_ctrl_fields; | |
1572 | #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF | |
1573 | #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0 | |
1574 | #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7 | |
1575 | #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12 | |
1576 | #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1 | |
1577 | #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15 | |
1578 | }; | |
1579 | ||
1580 | /* IGU mapping line structure */ | |
1581 | struct igu_mapping_line { | |
1582 | __le32 igu_mapping_line_fields; | |
1583 | #define IGU_MAPPING_LINE_VALID_MASK 0x1 | |
1584 | #define IGU_MAPPING_LINE_VALID_SHIFT 0 | |
1585 | #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF | |
1586 | #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1 | |
1587 | #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF | |
1588 | #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9 | |
1589 | #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 | |
1590 | #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17 | |
1591 | #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F | |
1592 | #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18 | |
1593 | #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF | |
1594 | #define IGU_MAPPING_LINE_RESERVED_SHIFT 24 | |
1595 | }; | |
1596 | ||
1597 | /* IGU MSIX line structure */ | |
1598 | struct igu_msix_vector { | |
1599 | struct regpair address; | |
1600 | __le32 data; | |
1601 | __le32 msix_vector_fields; | |
1602 | #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1 | |
1603 | #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0 | |
1604 | #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF | |
1605 | #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1 | |
1606 | #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF | |
1607 | #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16 | |
1608 | #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF | |
1609 | #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24 | |
1610 | }; | |
351a4ded YM |
1611 | /* per encapsulation type enabling flags */ |
1612 | struct prs_reg_encapsulation_type_en { | |
1613 | u8 flags; | |
1614 | #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1 | |
1615 | #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0 | |
1616 | #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1 | |
1617 | #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1 | |
1618 | #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1 | |
1619 | #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2 | |
1620 | #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1 | |
1621 | #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3 | |
1622 | #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1 | |
1623 | #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4 | |
1624 | #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1 | |
1625 | #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5 | |
1626 | #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3 | |
1627 | #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6 | |
1628 | }; | |
1629 | ||
1630 | enum pxp_tph_st_hint { | |
1631 | TPH_ST_HINT_BIDIR, | |
1632 | TPH_ST_HINT_REQUESTER, | |
1633 | TPH_ST_HINT_TARGET, | |
1634 | TPH_ST_HINT_TARGET_PRIO, | |
1635 | MAX_PXP_TPH_ST_HINT | |
1636 | }; | |
1637 | ||
1638 | /* QM hardware structure of enable bypass credit mask */ | |
1639 | struct qm_rf_bypass_mask { | |
1640 | u8 flags; | |
1641 | #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1 | |
1642 | #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0 | |
1643 | #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1 | |
1644 | #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1 | |
1645 | #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1 | |
1646 | #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2 | |
1647 | #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1 | |
1648 | #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3 | |
1649 | #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1 | |
1650 | #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4 | |
1651 | #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1 | |
1652 | #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5 | |
1653 | #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1 | |
1654 | #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6 | |
1655 | #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1 | |
1656 | #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7 | |
1657 | }; | |
1658 | ||
1659 | /* QM hardware structure of opportunistic credit mask */ | |
1660 | struct qm_rf_opportunistic_mask { | |
1661 | __le16 flags; | |
1662 | #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1 | |
1663 | #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0 | |
1664 | #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1 | |
1665 | #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1 | |
1666 | #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1 | |
1667 | #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2 | |
1668 | #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1 | |
1669 | #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3 | |
1670 | #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1 | |
1671 | #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4 | |
1672 | #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1 | |
1673 | #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5 | |
1674 | #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1 | |
1675 | #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6 | |
1676 | #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1 | |
1677 | #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7 | |
1678 | #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1 | |
1679 | #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8 | |
1680 | #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F | |
1681 | #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9 | |
1682 | }; | |
1683 | ||
1684 | /* QM hardware structure of QM map memory */ | |
21dd79e8 | 1685 | struct qm_rf_pq_map_e4 { |
351a4ded | 1686 | __le32 reg; |
21dd79e8 TT |
1687 | #define QM_RF_PQ_MAP_E4_PQ_VALID_MASK 0x1 |
1688 | #define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT 0 | |
1689 | #define QM_RF_PQ_MAP_E4_RL_ID_MASK 0xFF | |
1690 | #define QM_RF_PQ_MAP_E4_RL_ID_SHIFT 1 | |
1691 | #define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK 0x1FF | |
1692 | #define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT 9 | |
1693 | #define QM_RF_PQ_MAP_E4_VOQ_MASK 0x1F | |
1694 | #define QM_RF_PQ_MAP_E4_VOQ_SHIFT 18 | |
1695 | #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK 0x3 | |
1696 | #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT 23 | |
1697 | #define QM_RF_PQ_MAP_E4_RL_VALID_MASK 0x1 | |
1698 | #define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT 25 | |
1699 | #define QM_RF_PQ_MAP_E4_RESERVED_MASK 0x3F | |
1700 | #define QM_RF_PQ_MAP_E4_RESERVED_SHIFT 26 | |
351a4ded YM |
1701 | }; |
1702 | ||
1703 | /* Completion params for aggregated interrupt completion */ | |
1704 | struct sdm_agg_int_comp_params { | |
1705 | __le16 params; | |
1706 | #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F | |
1707 | #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0 | |
1708 | #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1 | |
1709 | #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6 | |
1710 | #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF | |
1711 | #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7 | |
1712 | }; | |
1713 | ||
1714 | /* SDM operation gen command (generate aggregative interrupt) */ | |
1715 | struct sdm_op_gen { | |
1716 | __le32 command; | |
1717 | #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF | |
1718 | #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 | |
1719 | #define SDM_OP_GEN_COMP_TYPE_MASK 0xF | |
1720 | #define SDM_OP_GEN_COMP_TYPE_SHIFT 16 | |
1721 | #define SDM_OP_GEN_RESERVED_MASK 0xFFF | |
1722 | #define SDM_OP_GEN_RESERVED_SHIFT 20 | |
1723 | }; | |
1724 | ||
351a4ded YM |
1725 | /****************************************/ |
1726 | /* Debug Tools HSI constants and macros */ | |
1727 | /****************************************/ | |
1728 | ||
fe56b9e6 | 1729 | enum block_addr { |
351a4ded YM |
1730 | GRCBASE_GRC = 0x50000, |
1731 | GRCBASE_MISCS = 0x9000, | |
1732 | GRCBASE_MISC = 0x8000, | |
1733 | GRCBASE_DBU = 0xa000, | |
1734 | GRCBASE_PGLUE_B = 0x2a8000, | |
1735 | GRCBASE_CNIG = 0x218000, | |
1736 | GRCBASE_CPMU = 0x30000, | |
1737 | GRCBASE_NCSI = 0x40000, | |
1738 | GRCBASE_OPTE = 0x53000, | |
1739 | GRCBASE_BMB = 0x540000, | |
1740 | GRCBASE_PCIE = 0x54000, | |
1741 | GRCBASE_MCP = 0xe00000, | |
1742 | GRCBASE_MCP2 = 0x52000, | |
1743 | GRCBASE_PSWHST = 0x2a0000, | |
1744 | GRCBASE_PSWHST2 = 0x29e000, | |
1745 | GRCBASE_PSWRD = 0x29c000, | |
1746 | GRCBASE_PSWRD2 = 0x29d000, | |
1747 | GRCBASE_PSWWR = 0x29a000, | |
1748 | GRCBASE_PSWWR2 = 0x29b000, | |
1749 | GRCBASE_PSWRQ = 0x280000, | |
1750 | GRCBASE_PSWRQ2 = 0x240000, | |
1751 | GRCBASE_PGLCS = 0x0, | |
1752 | GRCBASE_DMAE = 0xc000, | |
1753 | GRCBASE_PTU = 0x560000, | |
1754 | GRCBASE_TCM = 0x1180000, | |
1755 | GRCBASE_MCM = 0x1200000, | |
1756 | GRCBASE_UCM = 0x1280000, | |
1757 | GRCBASE_XCM = 0x1000000, | |
1758 | GRCBASE_YCM = 0x1080000, | |
1759 | GRCBASE_PCM = 0x1100000, | |
1760 | GRCBASE_QM = 0x2f0000, | |
1761 | GRCBASE_TM = 0x2c0000, | |
1762 | GRCBASE_DORQ = 0x100000, | |
1763 | GRCBASE_BRB = 0x340000, | |
1764 | GRCBASE_SRC = 0x238000, | |
1765 | GRCBASE_PRS = 0x1f0000, | |
1766 | GRCBASE_TSDM = 0xfb0000, | |
1767 | GRCBASE_MSDM = 0xfc0000, | |
1768 | GRCBASE_USDM = 0xfd0000, | |
1769 | GRCBASE_XSDM = 0xf80000, | |
1770 | GRCBASE_YSDM = 0xf90000, | |
1771 | GRCBASE_PSDM = 0xfa0000, | |
1772 | GRCBASE_TSEM = 0x1700000, | |
1773 | GRCBASE_MSEM = 0x1800000, | |
1774 | GRCBASE_USEM = 0x1900000, | |
1775 | GRCBASE_XSEM = 0x1400000, | |
1776 | GRCBASE_YSEM = 0x1500000, | |
1777 | GRCBASE_PSEM = 0x1600000, | |
1778 | GRCBASE_RSS = 0x238800, | |
1779 | GRCBASE_TMLD = 0x4d0000, | |
1780 | GRCBASE_MULD = 0x4e0000, | |
1781 | GRCBASE_YULD = 0x4c8000, | |
1782 | GRCBASE_XYLD = 0x4c0000, | |
da090917 TT |
1783 | GRCBASE_PTLD = 0x5a0000, |
1784 | GRCBASE_YPLD = 0x5c0000, | |
351a4ded YM |
1785 | GRCBASE_PRM = 0x230000, |
1786 | GRCBASE_PBF_PB1 = 0xda0000, | |
1787 | GRCBASE_PBF_PB2 = 0xda4000, | |
1788 | GRCBASE_RPB = 0x23c000, | |
1789 | GRCBASE_BTB = 0xdb0000, | |
1790 | GRCBASE_PBF = 0xd80000, | |
1791 | GRCBASE_RDIF = 0x300000, | |
1792 | GRCBASE_TDIF = 0x310000, | |
1793 | GRCBASE_CDU = 0x580000, | |
1794 | GRCBASE_CCFC = 0x2e0000, | |
1795 | GRCBASE_TCFC = 0x2d0000, | |
1796 | GRCBASE_IGU = 0x180000, | |
1797 | GRCBASE_CAU = 0x1c0000, | |
7b6859fb MY |
1798 | GRCBASE_RGFS = 0xf00000, |
1799 | GRCBASE_RGSRC = 0x320000, | |
1800 | GRCBASE_TGFS = 0xd00000, | |
1801 | GRCBASE_TGSRC = 0x322000, | |
351a4ded YM |
1802 | GRCBASE_UMAC = 0x51000, |
1803 | GRCBASE_XMAC = 0x210000, | |
1804 | GRCBASE_DBG = 0x10000, | |
1805 | GRCBASE_NIG = 0x500000, | |
1806 | GRCBASE_WOL = 0x600000, | |
1807 | GRCBASE_BMBN = 0x610000, | |
1808 | GRCBASE_IPC = 0x20000, | |
1809 | GRCBASE_NWM = 0x800000, | |
1810 | GRCBASE_NWS = 0x700000, | |
1811 | GRCBASE_MS = 0x6a0000, | |
1812 | GRCBASE_PHY_PCIE = 0x620000, | |
1813 | GRCBASE_LED = 0x6b8000, | |
be086e7c | 1814 | GRCBASE_AVS_WRAP = 0x6b0000, |
da090917 | 1815 | GRCBASE_PXPREQBUS = 0x56000, |
351a4ded YM |
1816 | GRCBASE_MISC_AEU = 0x8000, |
1817 | GRCBASE_BAR0_MAP = 0x1c00000, | |
fe56b9e6 YM |
1818 | MAX_BLOCK_ADDR |
1819 | }; | |
1820 | ||
1821 | enum block_id { | |
1822 | BLOCK_GRC, | |
1823 | BLOCK_MISCS, | |
1824 | BLOCK_MISC, | |
1825 | BLOCK_DBU, | |
1826 | BLOCK_PGLUE_B, | |
1827 | BLOCK_CNIG, | |
1828 | BLOCK_CPMU, | |
1829 | BLOCK_NCSI, | |
1830 | BLOCK_OPTE, | |
1831 | BLOCK_BMB, | |
1832 | BLOCK_PCIE, | |
1833 | BLOCK_MCP, | |
1834 | BLOCK_MCP2, | |
1835 | BLOCK_PSWHST, | |
1836 | BLOCK_PSWHST2, | |
1837 | BLOCK_PSWRD, | |
1838 | BLOCK_PSWRD2, | |
1839 | BLOCK_PSWWR, | |
1840 | BLOCK_PSWWR2, | |
1841 | BLOCK_PSWRQ, | |
1842 | BLOCK_PSWRQ2, | |
1843 | BLOCK_PGLCS, | |
fe56b9e6 | 1844 | BLOCK_DMAE, |
351a4ded | 1845 | BLOCK_PTU, |
fe56b9e6 YM |
1846 | BLOCK_TCM, |
1847 | BLOCK_MCM, | |
1848 | BLOCK_UCM, | |
1849 | BLOCK_XCM, | |
1850 | BLOCK_YCM, | |
1851 | BLOCK_PCM, | |
1852 | BLOCK_QM, | |
1853 | BLOCK_TM, | |
1854 | BLOCK_DORQ, | |
1855 | BLOCK_BRB, | |
1856 | BLOCK_SRC, | |
1857 | BLOCK_PRS, | |
1858 | BLOCK_TSDM, | |
1859 | BLOCK_MSDM, | |
1860 | BLOCK_USDM, | |
1861 | BLOCK_XSDM, | |
1862 | BLOCK_YSDM, | |
1863 | BLOCK_PSDM, | |
1864 | BLOCK_TSEM, | |
1865 | BLOCK_MSEM, | |
1866 | BLOCK_USEM, | |
1867 | BLOCK_XSEM, | |
1868 | BLOCK_YSEM, | |
1869 | BLOCK_PSEM, | |
1870 | BLOCK_RSS, | |
1871 | BLOCK_TMLD, | |
1872 | BLOCK_MULD, | |
1873 | BLOCK_YULD, | |
1874 | BLOCK_XYLD, | |
7b6859fb MY |
1875 | BLOCK_PTLD, |
1876 | BLOCK_YPLD, | |
fe56b9e6 YM |
1877 | BLOCK_PRM, |
1878 | BLOCK_PBF_PB1, | |
1879 | BLOCK_PBF_PB2, | |
1880 | BLOCK_RPB, | |
1881 | BLOCK_BTB, | |
1882 | BLOCK_PBF, | |
1883 | BLOCK_RDIF, | |
1884 | BLOCK_TDIF, | |
1885 | BLOCK_CDU, | |
1886 | BLOCK_CCFC, | |
1887 | BLOCK_TCFC, | |
1888 | BLOCK_IGU, | |
1889 | BLOCK_CAU, | |
7b6859fb MY |
1890 | BLOCK_RGFS, |
1891 | BLOCK_RGSRC, | |
1892 | BLOCK_TGFS, | |
1893 | BLOCK_TGSRC, | |
fe56b9e6 YM |
1894 | BLOCK_UMAC, |
1895 | BLOCK_XMAC, | |
1896 | BLOCK_DBG, | |
1897 | BLOCK_NIG, | |
1898 | BLOCK_WOL, | |
1899 | BLOCK_BMBN, | |
1900 | BLOCK_IPC, | |
1901 | BLOCK_NWM, | |
1902 | BLOCK_NWS, | |
1903 | BLOCK_MS, | |
1904 | BLOCK_PHY_PCIE, | |
351a4ded | 1905 | BLOCK_LED, |
be086e7c | 1906 | BLOCK_AVS_WRAP, |
da090917 | 1907 | BLOCK_PXPREQBUS, |
fe56b9e6 YM |
1908 | BLOCK_MISC_AEU, |
1909 | BLOCK_BAR0_MAP, | |
1910 | MAX_BLOCK_ID | |
1911 | }; | |
1912 | ||
351a4ded YM |
1913 | /* binary debug buffer types */ |
1914 | enum bin_dbg_buffer_type { | |
1915 | BIN_BUF_DBG_MODE_TREE, | |
1916 | BIN_BUF_DBG_DUMP_REG, | |
1917 | BIN_BUF_DBG_DUMP_MEM, | |
1918 | BIN_BUF_DBG_IDLE_CHK_REGS, | |
1919 | BIN_BUF_DBG_IDLE_CHK_IMMS, | |
1920 | BIN_BUF_DBG_IDLE_CHK_RULES, | |
1921 | BIN_BUF_DBG_IDLE_CHK_PARSING_DATA, | |
1922 | BIN_BUF_DBG_ATTN_BLOCKS, | |
1923 | BIN_BUF_DBG_ATTN_REGS, | |
1924 | BIN_BUF_DBG_ATTN_INDEXES, | |
1925 | BIN_BUF_DBG_ATTN_NAME_OFFSETS, | |
7b6859fb MY |
1926 | BIN_BUF_DBG_BUS_BLOCKS, |
1927 | BIN_BUF_DBG_BUS_LINES, | |
1928 | BIN_BUF_DBG_BUS_BLOCKS_USER_DATA, | |
1929 | BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS, | |
351a4ded YM |
1930 | BIN_BUF_DBG_PARSING_STRINGS, |
1931 | MAX_BIN_DBG_BUFFER_TYPE | |
fe56b9e6 YM |
1932 | }; |
1933 | ||
fe56b9e6 | 1934 | |
351a4ded YM |
1935 | /* Attention bit mapping */ |
1936 | struct dbg_attn_bit_mapping { | |
50bc60cb | 1937 | u16 data; |
351a4ded YM |
1938 | #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF |
1939 | #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0 | |
1940 | #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1 | |
1941 | #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15 | |
fe56b9e6 YM |
1942 | }; |
1943 | ||
351a4ded YM |
1944 | /* Attention block per-type data */ |
1945 | struct dbg_attn_block_type_data { | |
50bc60cb MK |
1946 | u16 names_offset; |
1947 | u16 reserved1; | |
351a4ded YM |
1948 | u8 num_regs; |
1949 | u8 reserved2; | |
50bc60cb MK |
1950 | u16 regs_offset; |
1951 | ||
fe56b9e6 YM |
1952 | }; |
1953 | ||
351a4ded YM |
1954 | /* Block attentions */ |
1955 | struct dbg_attn_block { | |
1956 | struct dbg_attn_block_type_data per_type_data[2]; | |
fe56b9e6 YM |
1957 | }; |
1958 | ||
351a4ded YM |
1959 | /* Attention register result */ |
1960 | struct dbg_attn_reg_result { | |
50bc60cb | 1961 | u32 data; |
351a4ded YM |
1962 | #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF |
1963 | #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0 | |
be086e7c MY |
1964 | #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF |
1965 | #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24 | |
50bc60cb MK |
1966 | u16 block_attn_offset; |
1967 | u16 reserved; | |
1968 | u32 sts_val; | |
1969 | u32 mask_val; | |
351a4ded YM |
1970 | }; |
1971 | ||
1972 | /* Attention block result */ | |
1973 | struct dbg_attn_block_result { | |
1974 | u8 block_id; | |
1975 | u8 data; | |
1976 | #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3 | |
1977 | #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0 | |
1978 | #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F | |
1979 | #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2 | |
50bc60cb | 1980 | u16 names_offset; |
351a4ded YM |
1981 | struct dbg_attn_reg_result reg_results[15]; |
1982 | }; | |
1983 | ||
a2e7699e | 1984 | /* Mode header */ |
351a4ded | 1985 | struct dbg_mode_hdr { |
50bc60cb | 1986 | u16 data; |
351a4ded YM |
1987 | #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1 |
1988 | #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0 | |
1989 | #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF | |
1990 | #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1 | |
1991 | }; | |
1992 | ||
1993 | /* Attention register */ | |
1994 | struct dbg_attn_reg { | |
1995 | struct dbg_mode_hdr mode; | |
50bc60cb MK |
1996 | u16 block_attn_offset; |
1997 | u32 data; | |
351a4ded YM |
1998 | #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF |
1999 | #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0 | |
be086e7c MY |
2000 | #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF |
2001 | #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24 | |
50bc60cb MK |
2002 | u32 sts_clr_address; |
2003 | u32 mask_address; | |
351a4ded YM |
2004 | }; |
2005 | ||
a2e7699e | 2006 | /* Attention types */ |
351a4ded YM |
2007 | enum dbg_attn_type { |
2008 | ATTN_TYPE_INTERRUPT, | |
2009 | ATTN_TYPE_PARITY, | |
2010 | MAX_DBG_ATTN_TYPE | |
2011 | }; | |
2012 | ||
a2e7699e | 2013 | /* Debug Bus block data */ |
7b6859fb MY |
2014 | struct dbg_bus_block { |
2015 | u8 num_of_lines; | |
2016 | u8 has_latency_events; | |
50bc60cb | 2017 | u16 lines_offset; |
7b6859fb MY |
2018 | }; |
2019 | ||
a2e7699e | 2020 | /* Debug Bus block user data */ |
7b6859fb MY |
2021 | struct dbg_bus_block_user_data { |
2022 | u8 num_of_lines; | |
2023 | u8 has_latency_events; | |
50bc60cb | 2024 | u16 names_offset; |
7b6859fb MY |
2025 | }; |
2026 | ||
a2e7699e | 2027 | /* Block Debug line data */ |
7b6859fb MY |
2028 | struct dbg_bus_line { |
2029 | u8 data; | |
a2e7699e TT |
2030 | #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF |
2031 | #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0 | |
2032 | #define DBG_BUS_LINE_IS_256B_MASK 0x1 | |
2033 | #define DBG_BUS_LINE_IS_256B_SHIFT 4 | |
2034 | #define DBG_BUS_LINE_RESERVED_MASK 0x7 | |
2035 | #define DBG_BUS_LINE_RESERVED_SHIFT 5 | |
7b6859fb MY |
2036 | u8 group_sizes; |
2037 | }; | |
2038 | ||
a2e7699e | 2039 | /* Condition header for registers dump */ |
c965db44 TT |
2040 | struct dbg_dump_cond_hdr { |
2041 | struct dbg_mode_hdr mode; /* Mode header */ | |
2042 | u8 block_id; /* block ID */ | |
2043 | u8 data_size; /* size in dwords of the data following this header */ | |
2044 | }; | |
2045 | ||
a2e7699e | 2046 | /* Memory data for registers dump */ |
c965db44 | 2047 | struct dbg_dump_mem { |
50bc60cb | 2048 | u32 dword0; |
a2e7699e TT |
2049 | #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF |
2050 | #define DBG_DUMP_MEM_ADDRESS_SHIFT 0 | |
2051 | #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF | |
2052 | #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24 | |
50bc60cb | 2053 | u32 dword1; |
a2e7699e TT |
2054 | #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF |
2055 | #define DBG_DUMP_MEM_LENGTH_SHIFT 0 | |
2056 | #define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1 | |
2057 | #define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24 | |
2058 | #define DBG_DUMP_MEM_RESERVED_MASK 0x7F | |
2059 | #define DBG_DUMP_MEM_RESERVED_SHIFT 25 | |
c965db44 TT |
2060 | }; |
2061 | ||
a2e7699e | 2062 | /* Register data for registers dump */ |
c965db44 | 2063 | struct dbg_dump_reg { |
50bc60cb | 2064 | u32 data; |
a2e7699e TT |
2065 | #define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF |
2066 | #define DBG_DUMP_REG_ADDRESS_SHIFT 0 | |
2067 | #define DBG_DUMP_REG_WIDE_BUS_MASK 0x1 | |
2068 | #define DBG_DUMP_REG_WIDE_BUS_SHIFT 23 | |
2069 | #define DBG_DUMP_REG_LENGTH_MASK 0xFF | |
2070 | #define DBG_DUMP_REG_LENGTH_SHIFT 24 | |
c965db44 TT |
2071 | }; |
2072 | ||
a2e7699e | 2073 | /* Split header for registers dump */ |
c965db44 | 2074 | struct dbg_dump_split_hdr { |
50bc60cb | 2075 | u32 hdr; |
a2e7699e TT |
2076 | #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF |
2077 | #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0 | |
2078 | #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF | |
2079 | #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24 | |
c965db44 TT |
2080 | }; |
2081 | ||
a2e7699e | 2082 | /* Condition header for idle check */ |
c965db44 TT |
2083 | struct dbg_idle_chk_cond_hdr { |
2084 | struct dbg_mode_hdr mode; /* Mode header */ | |
50bc60cb | 2085 | u16 data_size; /* size in dwords of the data following this header */ |
c965db44 TT |
2086 | }; |
2087 | ||
2088 | /* Idle Check condition register */ | |
2089 | struct dbg_idle_chk_cond_reg { | |
50bc60cb | 2090 | u32 data; |
a2e7699e TT |
2091 | #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF |
2092 | #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0 | |
2093 | #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1 | |
2094 | #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23 | |
2095 | #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF | |
2096 | #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24 | |
50bc60cb | 2097 | u16 num_entries; |
7b6859fb MY |
2098 | u8 entry_size; |
2099 | u8 start_entry; | |
c965db44 TT |
2100 | }; |
2101 | ||
2102 | /* Idle Check info register */ | |
2103 | struct dbg_idle_chk_info_reg { | |
50bc60cb | 2104 | u32 data; |
a2e7699e TT |
2105 | #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF |
2106 | #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0 | |
2107 | #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1 | |
2108 | #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23 | |
2109 | #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF | |
2110 | #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24 | |
50bc60cb | 2111 | u16 size; /* register size in dwords */ |
c965db44 TT |
2112 | struct dbg_mode_hdr mode; /* Mode header */ |
2113 | }; | |
2114 | ||
2115 | /* Idle Check register */ | |
2116 | union dbg_idle_chk_reg { | |
2117 | struct dbg_idle_chk_cond_reg cond_reg; /* condition register */ | |
2118 | struct dbg_idle_chk_info_reg info_reg; /* info register */ | |
2119 | }; | |
2120 | ||
2121 | /* Idle Check result header */ | |
2122 | struct dbg_idle_chk_result_hdr { | |
50bc60cb MK |
2123 | u16 rule_id; /* Failing rule index */ |
2124 | u16 mem_entry_id; /* Failing memory entry index */ | |
c965db44 TT |
2125 | u8 num_dumped_cond_regs; /* number of dumped condition registers */ |
2126 | u8 num_dumped_info_regs; /* number of dumped condition registers */ | |
2127 | u8 severity; /* from dbg_idle_chk_severity_types enum */ | |
2128 | u8 reserved; | |
2129 | }; | |
2130 | ||
2131 | /* Idle Check result register header */ | |
2132 | struct dbg_idle_chk_result_reg_hdr { | |
2133 | u8 data; | |
2134 | #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1 | |
2135 | #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0 | |
2136 | #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F | |
2137 | #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1 | |
2138 | u8 start_entry; /* index of the first checked entry */ | |
50bc60cb | 2139 | u16 size; /* register size in dwords */ |
c965db44 TT |
2140 | }; |
2141 | ||
2142 | /* Idle Check rule */ | |
2143 | struct dbg_idle_chk_rule { | |
50bc60cb | 2144 | u16 rule_id; /* Idle Check rule ID */ |
c965db44 TT |
2145 | u8 severity; /* value from dbg_idle_chk_severity_types enum */ |
2146 | u8 cond_id; /* Condition ID */ | |
2147 | u8 num_cond_regs; /* number of condition registers */ | |
2148 | u8 num_info_regs; /* number of info registers */ | |
2149 | u8 num_imms; /* number of immediates in the condition */ | |
2150 | u8 reserved1; | |
50bc60cb MK |
2151 | u16 reg_offset; /* offset of this rules registers in the idle check |
2152 | * register array (in dbg_idle_chk_reg units). | |
2153 | */ | |
2154 | u16 imm_offset; /* offset of this rules immediate values in the | |
2155 | * immediate values array (in dwords). | |
2156 | */ | |
c965db44 TT |
2157 | }; |
2158 | ||
2159 | /* Idle Check rule parsing data */ | |
2160 | struct dbg_idle_chk_rule_parsing_data { | |
50bc60cb | 2161 | u32 data; |
a2e7699e TT |
2162 | #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1 |
2163 | #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0 | |
2164 | #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF | |
2165 | #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1 | |
c965db44 TT |
2166 | }; |
2167 | ||
a2e7699e | 2168 | /* Idle check severity types */ |
c965db44 TT |
2169 | enum dbg_idle_chk_severity_types { |
2170 | /* idle check failure should cause an error */ | |
2171 | IDLE_CHK_SEVERITY_ERROR, | |
2172 | /* idle check failure should cause an error only if theres no traffic */ | |
2173 | IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC, | |
2174 | /* idle check failure should cause a warning */ | |
2175 | IDLE_CHK_SEVERITY_WARNING, | |
2176 | MAX_DBG_IDLE_CHK_SEVERITY_TYPES | |
2177 | }; | |
2178 | ||
2179 | /* Debug Bus block data */ | |
2180 | struct dbg_bus_block_data { | |
50bc60cb | 2181 | u16 data; |
a2e7699e TT |
2182 | #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF |
2183 | #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0 | |
2184 | #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF | |
2185 | #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4 | |
2186 | #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF | |
2187 | #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8 | |
2188 | #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF | |
2189 | #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12 | |
7b6859fb MY |
2190 | u8 line_num; |
2191 | u8 hw_id; | |
c965db44 TT |
2192 | }; |
2193 | ||
2194 | /* Debug Bus Clients */ | |
2195 | enum dbg_bus_clients { | |
2196 | DBG_BUS_CLIENT_RBCN, | |
2197 | DBG_BUS_CLIENT_RBCP, | |
2198 | DBG_BUS_CLIENT_RBCR, | |
2199 | DBG_BUS_CLIENT_RBCT, | |
2200 | DBG_BUS_CLIENT_RBCU, | |
2201 | DBG_BUS_CLIENT_RBCF, | |
2202 | DBG_BUS_CLIENT_RBCX, | |
2203 | DBG_BUS_CLIENT_RBCS, | |
2204 | DBG_BUS_CLIENT_RBCH, | |
2205 | DBG_BUS_CLIENT_RBCZ, | |
2206 | DBG_BUS_CLIENT_OTHER_ENGINE, | |
2207 | DBG_BUS_CLIENT_TIMESTAMP, | |
2208 | DBG_BUS_CLIENT_CPU, | |
2209 | DBG_BUS_CLIENT_RBCY, | |
2210 | DBG_BUS_CLIENT_RBCQ, | |
2211 | DBG_BUS_CLIENT_RBCM, | |
2212 | DBG_BUS_CLIENT_RBCB, | |
2213 | DBG_BUS_CLIENT_RBCW, | |
2214 | DBG_BUS_CLIENT_RBCV, | |
2215 | MAX_DBG_BUS_CLIENTS | |
2216 | }; | |
2217 | ||
a2e7699e | 2218 | /* Debug Bus constraint operation types */ |
be086e7c MY |
2219 | enum dbg_bus_constraint_ops { |
2220 | DBG_BUS_CONSTRAINT_OP_EQ, | |
2221 | DBG_BUS_CONSTRAINT_OP_NE, | |
2222 | DBG_BUS_CONSTRAINT_OP_LT, | |
2223 | DBG_BUS_CONSTRAINT_OP_LTC, | |
2224 | DBG_BUS_CONSTRAINT_OP_LE, | |
2225 | DBG_BUS_CONSTRAINT_OP_LEC, | |
2226 | DBG_BUS_CONSTRAINT_OP_GT, | |
2227 | DBG_BUS_CONSTRAINT_OP_GTC, | |
2228 | DBG_BUS_CONSTRAINT_OP_GE, | |
2229 | DBG_BUS_CONSTRAINT_OP_GEC, | |
2230 | MAX_DBG_BUS_CONSTRAINT_OPS | |
2231 | }; | |
2232 | ||
a2e7699e | 2233 | /* Debug Bus trigger state data */ |
7b6859fb MY |
2234 | struct dbg_bus_trigger_state_data { |
2235 | u8 data; | |
a2e7699e TT |
2236 | #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF |
2237 | #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0 | |
2238 | #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF | |
2239 | #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4 | |
7b6859fb MY |
2240 | }; |
2241 | ||
c965db44 TT |
2242 | /* Debug Bus memory address */ |
2243 | struct dbg_bus_mem_addr { | |
50bc60cb MK |
2244 | u32 lo; |
2245 | u32 hi; | |
c965db44 TT |
2246 | }; |
2247 | ||
2248 | /* Debug Bus PCI buffer data */ | |
2249 | struct dbg_bus_pci_buf_data { | |
2250 | struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */ | |
2251 | struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */ | |
50bc60cb | 2252 | u32 size; /* PCI buffer size in bytes */ |
c965db44 TT |
2253 | }; |
2254 | ||
2255 | /* Debug Bus Storm EID range filter params */ | |
2256 | struct dbg_bus_storm_eid_range_params { | |
2257 | u8 min; /* Minimal event ID to filter on */ | |
2258 | u8 max; /* Maximal event ID to filter on */ | |
2259 | }; | |
2260 | ||
2261 | /* Debug Bus Storm EID mask filter params */ | |
2262 | struct dbg_bus_storm_eid_mask_params { | |
2263 | u8 val; /* Event ID value */ | |
2264 | u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */ | |
2265 | }; | |
2266 | ||
2267 | /* Debug Bus Storm EID filter params */ | |
2268 | union dbg_bus_storm_eid_params { | |
2269 | struct dbg_bus_storm_eid_range_params range; | |
2270 | struct dbg_bus_storm_eid_mask_params mask; | |
2271 | }; | |
2272 | ||
2273 | /* Debug Bus Storm data */ | |
2274 | struct dbg_bus_storm_data { | |
7b6859fb MY |
2275 | u8 enabled; |
2276 | u8 mode; | |
c965db44 TT |
2277 | u8 hw_id; |
2278 | u8 eid_filter_en; | |
2279 | u8 eid_range_not_mask; | |
2280 | u8 cid_filter_en; | |
2281 | union dbg_bus_storm_eid_params eid_filter_params; | |
50bc60cb | 2282 | u32 cid; |
c965db44 TT |
2283 | }; |
2284 | ||
2285 | /* Debug Bus data */ | |
2286 | struct dbg_bus_data { | |
50bc60cb | 2287 | u32 app_version; |
7b6859fb MY |
2288 | u8 state; |
2289 | u8 hw_dwords; | |
50bc60cb | 2290 | u16 hw_id_mask; |
7b6859fb MY |
2291 | u8 num_enabled_blocks; |
2292 | u8 num_enabled_storms; | |
2293 | u8 target; | |
2294 | u8 one_shot_en; | |
2295 | u8 grc_input_en; | |
2296 | u8 timestamp_input_en; | |
2297 | u8 filter_en; | |
2298 | u8 adding_filter; | |
2299 | u8 filter_pre_trigger; | |
2300 | u8 filter_post_trigger; | |
50bc60cb | 2301 | u16 reserved; |
7b6859fb MY |
2302 | u8 trigger_en; |
2303 | struct dbg_bus_trigger_state_data trigger_states[3]; | |
2304 | u8 next_trigger_state; | |
2305 | u8 next_constraint_id; | |
2306 | u8 unify_inputs; | |
2307 | u8 rcv_from_other_engine; | |
2308 | struct dbg_bus_pci_buf_data pci_buf; | |
2309 | struct dbg_bus_block_data blocks[88]; | |
2310 | struct dbg_bus_storm_data storms[6]; | |
c965db44 TT |
2311 | }; |
2312 | ||
a2e7699e | 2313 | /* Debug bus filter types */ |
be086e7c MY |
2314 | enum dbg_bus_filter_types { |
2315 | DBG_BUS_FILTER_TYPE_OFF, | |
2316 | DBG_BUS_FILTER_TYPE_PRE, | |
2317 | DBG_BUS_FILTER_TYPE_POST, | |
2318 | DBG_BUS_FILTER_TYPE_ON, | |
2319 | MAX_DBG_BUS_FILTER_TYPES | |
2320 | }; | |
2321 | ||
c965db44 TT |
2322 | /* Debug bus frame modes */ |
2323 | enum dbg_bus_frame_modes { | |
2324 | DBG_BUS_FRAME_MODE_0HW_4ST = 0, /* 0 HW dwords, 4 Storm dwords */ | |
2325 | DBG_BUS_FRAME_MODE_4HW_0ST = 3, /* 4 HW dwords, 0 Storm dwords */ | |
2326 | DBG_BUS_FRAME_MODE_8HW_0ST = 4, /* 8 HW dwords, 0 Storm dwords */ | |
2327 | MAX_DBG_BUS_FRAME_MODES | |
2328 | }; | |
2329 | ||
a2e7699e | 2330 | /* Debug bus other engine mode */ |
be086e7c MY |
2331 | enum dbg_bus_other_engine_modes { |
2332 | DBG_BUS_OTHER_ENGINE_MODE_NONE, | |
2333 | DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX, | |
2334 | DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX, | |
2335 | DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX, | |
2336 | DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX, | |
2337 | MAX_DBG_BUS_OTHER_ENGINE_MODES | |
2338 | }; | |
2339 | ||
a2e7699e | 2340 | /* Debug bus post-trigger recording types */ |
be086e7c MY |
2341 | enum dbg_bus_post_trigger_types { |
2342 | DBG_BUS_POST_TRIGGER_RECORD, | |
2343 | DBG_BUS_POST_TRIGGER_DROP, | |
2344 | MAX_DBG_BUS_POST_TRIGGER_TYPES | |
2345 | }; | |
2346 | ||
a2e7699e | 2347 | /* Debug bus pre-trigger recording types */ |
be086e7c MY |
2348 | enum dbg_bus_pre_trigger_types { |
2349 | DBG_BUS_PRE_TRIGGER_START_FROM_ZERO, | |
2350 | DBG_BUS_PRE_TRIGGER_NUM_CHUNKS, | |
2351 | DBG_BUS_PRE_TRIGGER_DROP, | |
2352 | MAX_DBG_BUS_PRE_TRIGGER_TYPES | |
2353 | }; | |
2354 | ||
a2e7699e | 2355 | /* Debug bus SEMI frame modes */ |
be086e7c | 2356 | enum dbg_bus_semi_frame_modes { |
a2e7699e TT |
2357 | DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0, |
2358 | DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3, | |
be086e7c MY |
2359 | MAX_DBG_BUS_SEMI_FRAME_MODES |
2360 | }; | |
2361 | ||
c965db44 TT |
2362 | /* Debug bus states */ |
2363 | enum dbg_bus_states { | |
7b6859fb MY |
2364 | DBG_BUS_STATE_IDLE, |
2365 | DBG_BUS_STATE_READY, | |
2366 | DBG_BUS_STATE_RECORDING, | |
2367 | DBG_BUS_STATE_STOPPED, | |
c965db44 TT |
2368 | MAX_DBG_BUS_STATES |
2369 | }; | |
2370 | ||
a2e7699e | 2371 | /* Debug Bus Storm modes */ |
be086e7c MY |
2372 | enum dbg_bus_storm_modes { |
2373 | DBG_BUS_STORM_MODE_PRINTF, | |
2374 | DBG_BUS_STORM_MODE_PRAM_ADDR, | |
2375 | DBG_BUS_STORM_MODE_DRA_RW, | |
2376 | DBG_BUS_STORM_MODE_DRA_W, | |
2377 | DBG_BUS_STORM_MODE_LD_ST_ADDR, | |
2378 | DBG_BUS_STORM_MODE_DRA_FSM, | |
2379 | DBG_BUS_STORM_MODE_RH, | |
2380 | DBG_BUS_STORM_MODE_FOC, | |
2381 | DBG_BUS_STORM_MODE_EXT_STORE, | |
2382 | MAX_DBG_BUS_STORM_MODES | |
2383 | }; | |
2384 | ||
c965db44 TT |
2385 | /* Debug bus target IDs */ |
2386 | enum dbg_bus_targets { | |
c965db44 | 2387 | DBG_BUS_TARGET_ID_INT_BUF, |
c965db44 | 2388 | DBG_BUS_TARGET_ID_NIG, |
c965db44 TT |
2389 | DBG_BUS_TARGET_ID_PCI, |
2390 | MAX_DBG_BUS_TARGETS | |
2391 | }; | |
2392 | ||
2393 | /* GRC Dump data */ | |
2394 | struct dbg_grc_data { | |
be086e7c MY |
2395 | u8 params_initialized; |
2396 | u8 reserved1; | |
50bc60cb MK |
2397 | u16 reserved2; |
2398 | u32 param_val[48]; | |
c965db44 TT |
2399 | }; |
2400 | ||
2401 | /* Debug GRC params */ | |
2402 | enum dbg_grc_params { | |
7b6859fb MY |
2403 | DBG_GRC_PARAM_DUMP_TSTORM, |
2404 | DBG_GRC_PARAM_DUMP_MSTORM, | |
2405 | DBG_GRC_PARAM_DUMP_USTORM, | |
2406 | DBG_GRC_PARAM_DUMP_XSTORM, | |
2407 | DBG_GRC_PARAM_DUMP_YSTORM, | |
2408 | DBG_GRC_PARAM_DUMP_PSTORM, | |
2409 | DBG_GRC_PARAM_DUMP_REGS, | |
2410 | DBG_GRC_PARAM_DUMP_RAM, | |
2411 | DBG_GRC_PARAM_DUMP_PBUF, | |
2412 | DBG_GRC_PARAM_DUMP_IOR, | |
2413 | DBG_GRC_PARAM_DUMP_VFC, | |
2414 | DBG_GRC_PARAM_DUMP_CM_CTX, | |
2415 | DBG_GRC_PARAM_DUMP_PXP, | |
2416 | DBG_GRC_PARAM_DUMP_RSS, | |
2417 | DBG_GRC_PARAM_DUMP_CAU, | |
2418 | DBG_GRC_PARAM_DUMP_QM, | |
2419 | DBG_GRC_PARAM_DUMP_MCP, | |
50bc60cb | 2420 | DBG_GRC_PARAM_MCP_TRACE_META_SIZE, |
7b6859fb MY |
2421 | DBG_GRC_PARAM_DUMP_CFC, |
2422 | DBG_GRC_PARAM_DUMP_IGU, | |
2423 | DBG_GRC_PARAM_DUMP_BRB, | |
2424 | DBG_GRC_PARAM_DUMP_BTB, | |
2425 | DBG_GRC_PARAM_DUMP_BMB, | |
2426 | DBG_GRC_PARAM_DUMP_NIG, | |
2427 | DBG_GRC_PARAM_DUMP_MULD, | |
2428 | DBG_GRC_PARAM_DUMP_PRS, | |
2429 | DBG_GRC_PARAM_DUMP_DMAE, | |
2430 | DBG_GRC_PARAM_DUMP_TM, | |
2431 | DBG_GRC_PARAM_DUMP_SDM, | |
2432 | DBG_GRC_PARAM_DUMP_DIF, | |
2433 | DBG_GRC_PARAM_DUMP_STATIC, | |
2434 | DBG_GRC_PARAM_UNSTALL, | |
2435 | DBG_GRC_PARAM_NUM_LCIDS, | |
2436 | DBG_GRC_PARAM_NUM_LTIDS, | |
c965db44 | 2437 | DBG_GRC_PARAM_EXCLUDE_ALL, |
c965db44 | 2438 | DBG_GRC_PARAM_CRASH, |
c965db44 | 2439 | DBG_GRC_PARAM_PARITY_SAFE, |
7b6859fb MY |
2440 | DBG_GRC_PARAM_DUMP_CM, |
2441 | DBG_GRC_PARAM_DUMP_PHY, | |
be086e7c MY |
2442 | DBG_GRC_PARAM_NO_MCP, |
2443 | DBG_GRC_PARAM_NO_FW_VER, | |
c965db44 TT |
2444 | MAX_DBG_GRC_PARAMS |
2445 | }; | |
2446 | ||
2447 | /* Debug reset registers */ | |
2448 | enum dbg_reset_regs { | |
2449 | DBG_RESET_REG_MISCS_PL_UA, | |
2450 | DBG_RESET_REG_MISCS_PL_HV, | |
2451 | DBG_RESET_REG_MISCS_PL_HV_2, | |
2452 | DBG_RESET_REG_MISC_PL_UA, | |
2453 | DBG_RESET_REG_MISC_PL_HV, | |
2454 | DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, | |
2455 | DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, | |
2456 | DBG_RESET_REG_MISC_PL_PDA_VAUX, | |
2457 | MAX_DBG_RESET_REGS | |
2458 | }; | |
2459 | ||
351a4ded YM |
2460 | /* Debug status codes */ |
2461 | enum dbg_status { | |
2462 | DBG_STATUS_OK, | |
2463 | DBG_STATUS_APP_VERSION_NOT_SET, | |
2464 | DBG_STATUS_UNSUPPORTED_APP_VERSION, | |
2465 | DBG_STATUS_DBG_BLOCK_NOT_RESET, | |
2466 | DBG_STATUS_INVALID_ARGS, | |
2467 | DBG_STATUS_OUTPUT_ALREADY_SET, | |
2468 | DBG_STATUS_INVALID_PCI_BUF_SIZE, | |
2469 | DBG_STATUS_PCI_BUF_ALLOC_FAILED, | |
2470 | DBG_STATUS_PCI_BUF_NOT_ALLOCATED, | |
2471 | DBG_STATUS_TOO_MANY_INPUTS, | |
2472 | DBG_STATUS_INPUT_OVERLAP, | |
2473 | DBG_STATUS_HW_ONLY_RECORDING, | |
2474 | DBG_STATUS_STORM_ALREADY_ENABLED, | |
2475 | DBG_STATUS_STORM_NOT_ENABLED, | |
2476 | DBG_STATUS_BLOCK_ALREADY_ENABLED, | |
2477 | DBG_STATUS_BLOCK_NOT_ENABLED, | |
2478 | DBG_STATUS_NO_INPUT_ENABLED, | |
2479 | DBG_STATUS_NO_FILTER_TRIGGER_64B, | |
2480 | DBG_STATUS_FILTER_ALREADY_ENABLED, | |
2481 | DBG_STATUS_TRIGGER_ALREADY_ENABLED, | |
2482 | DBG_STATUS_TRIGGER_NOT_ENABLED, | |
2483 | DBG_STATUS_CANT_ADD_CONSTRAINT, | |
2484 | DBG_STATUS_TOO_MANY_TRIGGER_STATES, | |
2485 | DBG_STATUS_TOO_MANY_CONSTRAINTS, | |
2486 | DBG_STATUS_RECORDING_NOT_STARTED, | |
2487 | DBG_STATUS_DATA_DIDNT_TRIGGER, | |
2488 | DBG_STATUS_NO_DATA_RECORDED, | |
2489 | DBG_STATUS_DUMP_BUF_TOO_SMALL, | |
2490 | DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED, | |
2491 | DBG_STATUS_UNKNOWN_CHIP, | |
2492 | DBG_STATUS_VIRT_MEM_ALLOC_FAILED, | |
2493 | DBG_STATUS_BLOCK_IN_RESET, | |
2494 | DBG_STATUS_INVALID_TRACE_SIGNATURE, | |
2495 | DBG_STATUS_INVALID_NVRAM_BUNDLE, | |
2496 | DBG_STATUS_NVRAM_GET_IMAGE_FAILED, | |
2497 | DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE, | |
2498 | DBG_STATUS_NVRAM_READ_FAILED, | |
2499 | DBG_STATUS_IDLE_CHK_PARSE_FAILED, | |
2500 | DBG_STATUS_MCP_TRACE_BAD_DATA, | |
2501 | DBG_STATUS_MCP_TRACE_NO_META, | |
2502 | DBG_STATUS_MCP_COULD_NOT_HALT, | |
2503 | DBG_STATUS_MCP_COULD_NOT_RESUME, | |
da090917 | 2504 | DBG_STATUS_RESERVED2, |
351a4ded YM |
2505 | DBG_STATUS_SEMI_FIFO_NOT_EMPTY, |
2506 | DBG_STATUS_IGU_FIFO_BAD_DATA, | |
2507 | DBG_STATUS_MCP_COULD_NOT_MASK_PRTY, | |
2508 | DBG_STATUS_FW_ASSERTS_PARSE_FAILED, | |
2509 | DBG_STATUS_REG_FIFO_BAD_DATA, | |
2510 | DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA, | |
2511 | DBG_STATUS_DBG_ARRAY_NOT_SET, | |
7b6859fb MY |
2512 | DBG_STATUS_FILTER_BUG, |
2513 | DBG_STATUS_NON_MATCHING_LINES, | |
2514 | DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET, | |
2515 | DBG_STATUS_DBG_BUS_IN_USE, | |
351a4ded | 2516 | MAX_DBG_STATUS |
fe56b9e6 YM |
2517 | }; |
2518 | ||
c965db44 TT |
2519 | /* Debug Storms IDs */ |
2520 | enum dbg_storms { | |
2521 | DBG_TSTORM_ID, | |
2522 | DBG_MSTORM_ID, | |
2523 | DBG_USTORM_ID, | |
2524 | DBG_XSTORM_ID, | |
2525 | DBG_YSTORM_ID, | |
2526 | DBG_PSTORM_ID, | |
2527 | MAX_DBG_STORMS | |
2528 | }; | |
2529 | ||
2530 | /* Idle Check data */ | |
2531 | struct idle_chk_data { | |
50bc60cb | 2532 | u32 buf_size; |
7b6859fb | 2533 | u8 buf_size_set; |
c965db44 | 2534 | u8 reserved1; |
50bc60cb | 2535 | u16 reserved2; |
c965db44 TT |
2536 | }; |
2537 | ||
2538 | /* Debug Tools data (per HW function) */ | |
2539 | struct dbg_tools_data { | |
7b6859fb MY |
2540 | struct dbg_grc_data grc; |
2541 | struct dbg_bus_data bus; | |
2542 | struct idle_chk_data idle_chk; | |
2543 | u8 mode_enable[40]; | |
2544 | u8 block_in_reset[88]; | |
2545 | u8 chip_id; | |
2546 | u8 platform_id; | |
2547 | u8 initialized; | |
da090917 | 2548 | u8 use_dmae; |
50bc60cb | 2549 | u32 num_regs_read; |
c965db44 TT |
2550 | }; |
2551 | ||
351a4ded YM |
2552 | /********************************/ |
2553 | /* HSI Init Functions constants */ | |
2554 | /********************************/ | |
2555 | ||
2556 | /* Number of VLAN priorities */ | |
2557 | #define NUM_OF_VLAN_PRIORITIES 8 | |
2558 | ||
a2e7699e | 2559 | /* BRB RAM init requirements */ |
05fafbfb | 2560 | struct init_brb_ram_req { |
50bc60cb MK |
2561 | u32 guranteed_per_tc; |
2562 | u32 headroom_per_tc; | |
2563 | u32 min_pkt_size; | |
2564 | u32 max_ports_per_engine; | |
05fafbfb YM |
2565 | u8 num_active_tcs[MAX_NUM_PORTS]; |
2566 | }; | |
2567 | ||
a2e7699e | 2568 | /* ETS per-TC init requirements */ |
05fafbfb YM |
2569 | struct init_ets_tc_req { |
2570 | u8 use_sp; | |
2571 | u8 use_wfq; | |
50bc60cb | 2572 | u16 weight; |
05fafbfb YM |
2573 | }; |
2574 | ||
a2e7699e | 2575 | /* ETS init requirements */ |
05fafbfb | 2576 | struct init_ets_req { |
50bc60cb | 2577 | u32 mtu; |
05fafbfb YM |
2578 | struct init_ets_tc_req tc_req[NUM_OF_TCS]; |
2579 | }; | |
2580 | ||
a2e7699e | 2581 | /* NIG LB RL init requirements */ |
05fafbfb | 2582 | struct init_nig_lb_rl_req { |
50bc60cb MK |
2583 | u16 lb_mac_rate; |
2584 | u16 lb_rate; | |
2585 | u32 mtu; | |
2586 | u16 tc_rate[NUM_OF_PHYS_TCS]; | |
05fafbfb YM |
2587 | }; |
2588 | ||
a2e7699e | 2589 | /* NIG TC mapping for each priority */ |
05fafbfb YM |
2590 | struct init_nig_pri_tc_map_entry { |
2591 | u8 tc_id; | |
2592 | u8 valid; | |
2593 | }; | |
2594 | ||
a2e7699e | 2595 | /* NIG priority to TC map init requirements */ |
05fafbfb YM |
2596 | struct init_nig_pri_tc_map_req { |
2597 | struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES]; | |
2598 | }; | |
2599 | ||
a2e7699e | 2600 | /* QM per-port init parameters */ |
351a4ded YM |
2601 | struct init_qm_port_params { |
2602 | u8 active; | |
2603 | u8 active_phys_tcs; | |
50bc60cb MK |
2604 | u16 num_pbf_cmd_lines; |
2605 | u16 num_btb_blocks; | |
2606 | u16 reserved; | |
fe56b9e6 YM |
2607 | }; |
2608 | ||
351a4ded YM |
2609 | /* QM per-PQ init parameters */ |
2610 | struct init_qm_pq_params { | |
2611 | u8 vport_id; | |
2612 | u8 tc_id; | |
2613 | u8 wrr_group; | |
2614 | u8 rl_valid; | |
50bc60cb MK |
2615 | u8 port_id; |
2616 | u8 reserved0; | |
2617 | u16 reserved1; | |
351a4ded YM |
2618 | }; |
2619 | ||
2620 | /* QM per-vport init parameters */ | |
2621 | struct init_qm_vport_params { | |
50bc60cb MK |
2622 | u32 vport_rl; |
2623 | u16 vport_wfq; | |
2624 | u16 first_tx_pq_id[NUM_OF_TCS]; | |
351a4ded YM |
2625 | }; |
2626 | ||
2627 | /**************************************/ | |
2628 | /* Init Tool HSI constants and macros */ | |
2629 | /**************************************/ | |
2630 | ||
2631 | /* Width of GRC address in bits (addresses are specified in dwords) */ | |
2632 | #define GRC_ADDR_BITS 23 | |
05fafbfb | 2633 | #define MAX_GRC_ADDR (BIT(GRC_ADDR_BITS) - 1) |
351a4ded YM |
2634 | |
2635 | /* indicates an init that should be applied to any phase ID */ | |
2636 | #define ANY_PHASE_ID 0xffff | |
2637 | ||
2638 | /* Max size in dwords of a zipped array */ | |
2639 | #define MAX_ZIPPED_SIZE 8192 | |
7b6859fb MY |
2640 | enum chip_ids { |
2641 | CHIP_BB, | |
2642 | CHIP_K2, | |
2643 | CHIP_RESERVED, | |
2644 | MAX_CHIP_IDS | |
2645 | }; | |
351a4ded | 2646 | |
c965db44 | 2647 | struct fw_asserts_ram_section { |
50bc60cb MK |
2648 | u16 section_ram_line_offset; |
2649 | u16 section_ram_line_size; | |
c965db44 TT |
2650 | u8 list_dword_offset; |
2651 | u8 list_element_dword_size; | |
2652 | u8 list_num_elements; | |
2653 | u8 list_next_index_dword_offset; | |
2654 | }; | |
2655 | ||
2656 | struct fw_ver_num { | |
7b6859fb MY |
2657 | u8 major; |
2658 | u8 minor; | |
2659 | u8 rev; | |
2660 | u8 eng; | |
c965db44 TT |
2661 | }; |
2662 | ||
2663 | struct fw_ver_info { | |
7b6859fb MY |
2664 | __le16 tools_ver; |
2665 | u8 image_id; | |
c965db44 | 2666 | u8 reserved1; |
7b6859fb MY |
2667 | struct fw_ver_num num; |
2668 | __le32 timestamp; | |
c965db44 TT |
2669 | __le32 reserved2; |
2670 | }; | |
2671 | ||
2672 | struct fw_info { | |
2673 | struct fw_ver_info ver; | |
2674 | struct fw_asserts_ram_section fw_asserts_section; | |
2675 | }; | |
2676 | ||
2677 | struct fw_info_location { | |
2678 | __le32 grc_addr; | |
2679 | __le32 size; | |
2680 | }; | |
2681 | ||
fe56b9e6 | 2682 | enum init_modes { |
351a4ded | 2683 | MODE_RESERVED, |
9c79ddaa | 2684 | MODE_BB, |
c965db44 | 2685 | MODE_K2, |
fe56b9e6 | 2686 | MODE_ASIC, |
c965db44 | 2687 | MODE_RESERVED2, |
fe56b9e6 YM |
2688 | MODE_RESERVED3, |
2689 | MODE_RESERVED4, | |
2690 | MODE_RESERVED5, | |
2691 | MODE_SF, | |
2692 | MODE_MF_SD, | |
2693 | MODE_MF_SI, | |
2694 | MODE_PORTS_PER_ENG_1, | |
2695 | MODE_PORTS_PER_ENG_2, | |
2696 | MODE_PORTS_PER_ENG_4, | |
fe56b9e6 | 2697 | MODE_100G, |
c965db44 | 2698 | MODE_RESERVED6, |
fe56b9e6 YM |
2699 | MAX_INIT_MODES |
2700 | }; | |
2701 | ||
2702 | enum init_phases { | |
2703 | PHASE_ENGINE, | |
2704 | PHASE_PORT, | |
2705 | PHASE_PF, | |
1408cc1f | 2706 | PHASE_VF, |
fe56b9e6 YM |
2707 | PHASE_QM_PF, |
2708 | MAX_INIT_PHASES | |
2709 | }; | |
2710 | ||
351a4ded YM |
2711 | enum init_split_types { |
2712 | SPLIT_TYPE_NONE, | |
2713 | SPLIT_TYPE_PORT, | |
2714 | SPLIT_TYPE_PF, | |
2715 | SPLIT_TYPE_PORT_PF, | |
2716 | SPLIT_TYPE_VF, | |
2717 | MAX_INIT_SPLIT_TYPES | |
fe56b9e6 YM |
2718 | }; |
2719 | ||
fe56b9e6 YM |
2720 | /* Binary buffer header */ |
2721 | struct bin_buffer_hdr { | |
50bc60cb MK |
2722 | u32 offset; |
2723 | u32 length; | |
fe56b9e6 YM |
2724 | }; |
2725 | ||
a2e7699e | 2726 | /* Binary init buffer types */ |
351a4ded | 2727 | enum bin_init_buffer_type { |
05fafbfb | 2728 | BIN_BUF_INIT_FW_VER_INFO, |
351a4ded YM |
2729 | BIN_BUF_INIT_CMD, |
2730 | BIN_BUF_INIT_VAL, | |
2731 | BIN_BUF_INIT_MODE_TREE, | |
05fafbfb | 2732 | BIN_BUF_INIT_IRO, |
351a4ded | 2733 | MAX_BIN_INIT_BUFFER_TYPE |
fe56b9e6 YM |
2734 | }; |
2735 | ||
351a4ded | 2736 | /* init array header: raw */ |
fe56b9e6 | 2737 | struct init_array_raw_hdr { |
50bc60cb | 2738 | u32 data; |
351a4ded YM |
2739 | #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF |
2740 | #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0 | |
2741 | #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF | |
2742 | #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4 | |
fe56b9e6 YM |
2743 | }; |
2744 | ||
351a4ded | 2745 | /* init array header: standard */ |
fe56b9e6 | 2746 | struct init_array_standard_hdr { |
50bc60cb | 2747 | u32 data; |
351a4ded YM |
2748 | #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF |
2749 | #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0 | |
2750 | #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF | |
2751 | #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4 | |
fe56b9e6 YM |
2752 | }; |
2753 | ||
351a4ded | 2754 | /* init array header: zipped */ |
fe56b9e6 | 2755 | struct init_array_zipped_hdr { |
50bc60cb | 2756 | u32 data; |
351a4ded YM |
2757 | #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF |
2758 | #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0 | |
2759 | #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF | |
2760 | #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4 | |
fe56b9e6 YM |
2761 | }; |
2762 | ||
351a4ded | 2763 | /* init array header: pattern */ |
fe56b9e6 | 2764 | struct init_array_pattern_hdr { |
50bc60cb | 2765 | u32 data; |
351a4ded YM |
2766 | #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF |
2767 | #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0 | |
2768 | #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF | |
2769 | #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4 | |
2770 | #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF | |
2771 | #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8 | |
fe56b9e6 YM |
2772 | }; |
2773 | ||
351a4ded | 2774 | /* init array header union */ |
fe56b9e6 | 2775 | union init_array_hdr { |
351a4ded YM |
2776 | struct init_array_raw_hdr raw; |
2777 | struct init_array_standard_hdr standard; | |
2778 | struct init_array_zipped_hdr zipped; | |
2779 | struct init_array_pattern_hdr pattern; | |
fe56b9e6 YM |
2780 | }; |
2781 | ||
351a4ded | 2782 | /* init array types */ |
fe56b9e6 | 2783 | enum init_array_types { |
351a4ded YM |
2784 | INIT_ARR_STANDARD, |
2785 | INIT_ARR_ZIPPED, | |
2786 | INIT_ARR_PATTERN, | |
fe56b9e6 YM |
2787 | MAX_INIT_ARRAY_TYPES |
2788 | }; | |
2789 | ||
2790 | /* init operation: callback */ | |
2791 | struct init_callback_op { | |
50bc60cb | 2792 | u32 op_data; |
351a4ded YM |
2793 | #define INIT_CALLBACK_OP_OP_MASK 0xF |
2794 | #define INIT_CALLBACK_OP_OP_SHIFT 0 | |
2795 | #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF | |
2796 | #define INIT_CALLBACK_OP_RESERVED_SHIFT 4 | |
50bc60cb MK |
2797 | u16 callback_id; |
2798 | u16 block_id; | |
fe56b9e6 YM |
2799 | }; |
2800 | ||
fe56b9e6 YM |
2801 | /* init operation: delay */ |
2802 | struct init_delay_op { | |
50bc60cb | 2803 | u32 op_data; |
351a4ded YM |
2804 | #define INIT_DELAY_OP_OP_MASK 0xF |
2805 | #define INIT_DELAY_OP_OP_SHIFT 0 | |
2806 | #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF | |
2807 | #define INIT_DELAY_OP_RESERVED_SHIFT 4 | |
50bc60cb | 2808 | u32 delay; |
fe56b9e6 YM |
2809 | }; |
2810 | ||
2811 | /* init operation: if_mode */ | |
2812 | struct init_if_mode_op { | |
50bc60cb | 2813 | u32 op_data; |
351a4ded YM |
2814 | #define INIT_IF_MODE_OP_OP_MASK 0xF |
2815 | #define INIT_IF_MODE_OP_OP_SHIFT 0 | |
2816 | #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF | |
2817 | #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4 | |
2818 | #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF | |
2819 | #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16 | |
50bc60cb MK |
2820 | u16 reserved2; |
2821 | u16 modes_buf_offset; | |
fe56b9e6 YM |
2822 | }; |
2823 | ||
351a4ded | 2824 | /* init operation: if_phase */ |
fe56b9e6 | 2825 | struct init_if_phase_op { |
50bc60cb | 2826 | u32 op_data; |
351a4ded YM |
2827 | #define INIT_IF_PHASE_OP_OP_MASK 0xF |
2828 | #define INIT_IF_PHASE_OP_OP_SHIFT 0 | |
2829 | #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1 | |
2830 | #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4 | |
2831 | #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF | |
2832 | #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5 | |
2833 | #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF | |
2834 | #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16 | |
50bc60cb | 2835 | u32 phase_data; |
351a4ded YM |
2836 | #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF |
2837 | #define INIT_IF_PHASE_OP_PHASE_SHIFT 0 | |
2838 | #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF | |
2839 | #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8 | |
2840 | #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF | |
2841 | #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16 | |
fe56b9e6 YM |
2842 | }; |
2843 | ||
2844 | /* init mode operators */ | |
2845 | enum init_mode_ops { | |
351a4ded YM |
2846 | INIT_MODE_OP_NOT, |
2847 | INIT_MODE_OP_OR, | |
2848 | INIT_MODE_OP_AND, | |
fe56b9e6 YM |
2849 | MAX_INIT_MODE_OPS |
2850 | }; | |
2851 | ||
2852 | /* init operation: raw */ | |
2853 | struct init_raw_op { | |
50bc60cb | 2854 | u32 op_data; |
351a4ded YM |
2855 | #define INIT_RAW_OP_OP_MASK 0xF |
2856 | #define INIT_RAW_OP_OP_SHIFT 0 | |
2857 | #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF | |
2858 | #define INIT_RAW_OP_PARAM1_SHIFT 4 | |
50bc60cb | 2859 | u32 param2; |
fe56b9e6 YM |
2860 | }; |
2861 | ||
2862 | /* init array params */ | |
2863 | struct init_op_array_params { | |
50bc60cb MK |
2864 | u16 size; |
2865 | u16 offset; | |
fe56b9e6 YM |
2866 | }; |
2867 | ||
2868 | /* Write init operation arguments */ | |
2869 | union init_write_args { | |
50bc60cb MK |
2870 | u32 inline_val; |
2871 | u32 zeros_count; | |
2872 | u32 array_offset; | |
351a4ded | 2873 | struct init_op_array_params runtime; |
fe56b9e6 YM |
2874 | }; |
2875 | ||
2876 | /* init operation: write */ | |
2877 | struct init_write_op { | |
50bc60cb | 2878 | u32 data; |
351a4ded YM |
2879 | #define INIT_WRITE_OP_OP_MASK 0xF |
2880 | #define INIT_WRITE_OP_OP_SHIFT 0 | |
2881 | #define INIT_WRITE_OP_SOURCE_MASK 0x7 | |
2882 | #define INIT_WRITE_OP_SOURCE_SHIFT 4 | |
2883 | #define INIT_WRITE_OP_RESERVED_MASK 0x1 | |
2884 | #define INIT_WRITE_OP_RESERVED_SHIFT 7 | |
2885 | #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1 | |
2886 | #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8 | |
2887 | #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF | |
2888 | #define INIT_WRITE_OP_ADDRESS_SHIFT 9 | |
2889 | union init_write_args args; | |
fe56b9e6 YM |
2890 | }; |
2891 | ||
2892 | /* init operation: read */ | |
2893 | struct init_read_op { | |
50bc60cb | 2894 | u32 op_data; |
351a4ded YM |
2895 | #define INIT_READ_OP_OP_MASK 0xF |
2896 | #define INIT_READ_OP_OP_SHIFT 0 | |
2897 | #define INIT_READ_OP_POLL_TYPE_MASK 0xF | |
2898 | #define INIT_READ_OP_POLL_TYPE_SHIFT 4 | |
2899 | #define INIT_READ_OP_RESERVED_MASK 0x1 | |
2900 | #define INIT_READ_OP_RESERVED_SHIFT 8 | |
2901 | #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF | |
2902 | #define INIT_READ_OP_ADDRESS_SHIFT 9 | |
50bc60cb | 2903 | u32 expected_val; |
fe56b9e6 YM |
2904 | }; |
2905 | ||
2906 | /* Init operations union */ | |
2907 | union init_op { | |
351a4ded YM |
2908 | struct init_raw_op raw; |
2909 | struct init_write_op write; | |
2910 | struct init_read_op read; | |
2911 | struct init_if_mode_op if_mode; | |
2912 | struct init_if_phase_op if_phase; | |
2913 | struct init_callback_op callback; | |
2914 | struct init_delay_op delay; | |
fe56b9e6 YM |
2915 | }; |
2916 | ||
2917 | /* Init command operation types */ | |
2918 | enum init_op_types { | |
351a4ded YM |
2919 | INIT_OP_READ, |
2920 | INIT_OP_WRITE, | |
fe56b9e6 YM |
2921 | INIT_OP_IF_MODE, |
2922 | INIT_OP_IF_PHASE, | |
351a4ded YM |
2923 | INIT_OP_DELAY, |
2924 | INIT_OP_CALLBACK, | |
fe56b9e6 YM |
2925 | MAX_INIT_OP_TYPES |
2926 | }; | |
2927 | ||
351a4ded | 2928 | /* init polling types */ |
fc48b7a6 | 2929 | enum init_poll_types { |
351a4ded YM |
2930 | INIT_POLL_NONE, |
2931 | INIT_POLL_EQ, | |
2932 | INIT_POLL_OR, | |
2933 | INIT_POLL_AND, | |
fc48b7a6 YM |
2934 | MAX_INIT_POLL_TYPES |
2935 | }; | |
2936 | ||
fe56b9e6 YM |
2937 | /* init source types */ |
2938 | enum init_source_types { | |
351a4ded YM |
2939 | INIT_SRC_INLINE, |
2940 | INIT_SRC_ZEROS, | |
2941 | INIT_SRC_ARRAY, | |
2942 | INIT_SRC_RUNTIME, | |
fe56b9e6 YM |
2943 | MAX_INIT_SOURCE_TYPES |
2944 | }; | |
2945 | ||
2946 | /* Internal RAM Offsets macro data */ | |
2947 | struct iro { | |
50bc60cb MK |
2948 | u32 base; |
2949 | u16 m1; | |
2950 | u16 m2; | |
2951 | u16 m3; | |
2952 | u16 size; | |
fe56b9e6 YM |
2953 | }; |
2954 | ||
c965db44 | 2955 | /***************************** Public Functions *******************************/ |
a2e7699e | 2956 | |
c965db44 TT |
2957 | /** |
2958 | * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug | |
2959 | * arrays. | |
2960 | * | |
2961 | * @param bin_ptr - a pointer to the binary data with debug arrays. | |
2962 | */ | |
2963 | enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr); | |
7b6859fb | 2964 | |
da090917 TT |
2965 | /** |
2966 | * @brief qed_read_regs - Reads registers into a buffer (using GRC). | |
2967 | * | |
2968 | * @param p_hwfn - HW device data | |
2969 | * @param p_ptt - Ptt window used for writing the registers. | |
2970 | * @param buf - Destination buffer. | |
2971 | * @param addr - Source GRC address in dwords. | |
2972 | * @param len - Number of registers to read. | |
2973 | */ | |
2974 | void qed_read_regs(struct qed_hwfn *p_hwfn, | |
2975 | struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len); | |
2976 | ||
be086e7c MY |
2977 | /** |
2978 | * @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their | |
2979 | * default value. | |
2980 | * | |
2981 | * @param p_hwfn - HW device data | |
2982 | */ | |
2983 | void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn); | |
c965db44 TT |
2984 | /** |
2985 | * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for | |
2986 | * GRC Dump. | |
2987 | * | |
2988 | * @param p_hwfn - HW device data | |
2989 | * @param p_ptt - Ptt window used for writing the registers. | |
2990 | * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump | |
2991 | * data. | |
2992 | * | |
2993 | * @return error if one of the following holds: | |
2994 | * - the version wasn't set | |
2995 | * Otherwise, returns ok. | |
2996 | */ | |
2997 | enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn, | |
2998 | struct qed_ptt *p_ptt, | |
2999 | u32 *buf_size); | |
7b6859fb | 3000 | |
c965db44 TT |
3001 | /** |
3002 | * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer. | |
3003 | * | |
3004 | * @param p_hwfn - HW device data | |
3005 | * @param p_ptt - Ptt window used for writing the registers. | |
3006 | * @param dump_buf - Pointer to write the collected GRC data into. | |
3007 | * @param buf_size_in_dwords - Size of the specified buffer in dwords. | |
3008 | * @param num_dumped_dwords - OUT: number of dumped dwords. | |
3009 | * | |
3010 | * @return error if one of the following holds: | |
3011 | * - the version wasn't set | |
3012 | * - the specified dump buffer is too small | |
3013 | * Otherwise, returns ok. | |
3014 | */ | |
3015 | enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn, | |
3016 | struct qed_ptt *p_ptt, | |
3017 | u32 *dump_buf, | |
3018 | u32 buf_size_in_dwords, | |
3019 | u32 *num_dumped_dwords); | |
7b6859fb | 3020 | |
c965db44 TT |
3021 | /** |
3022 | * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size | |
3023 | * for idle check results. | |
3024 | * | |
3025 | * @param p_hwfn - HW device data | |
3026 | * @param p_ptt - Ptt window used for writing the registers. | |
3027 | * @param buf_size - OUT: required buffer size (in dwords) for the idle check | |
3028 | * data. | |
3029 | * | |
3030 | * @return error if one of the following holds: | |
3031 | * - the version wasn't set | |
3032 | * Otherwise, returns ok. | |
3033 | */ | |
3034 | enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn, | |
3035 | struct qed_ptt *p_ptt, | |
3036 | u32 *buf_size); | |
7b6859fb | 3037 | |
c965db44 TT |
3038 | /** |
3039 | * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results | |
3040 | * into the specified buffer. | |
3041 | * | |
3042 | * @param p_hwfn - HW device data | |
3043 | * @param p_ptt - Ptt window used for writing the registers. | |
3044 | * @param dump_buf - Pointer to write the idle check data into. | |
3045 | * @param buf_size_in_dwords - Size of the specified buffer in dwords. | |
3046 | * @param num_dumped_dwords - OUT: number of dumped dwords. | |
3047 | * | |
3048 | * @return error if one of the following holds: | |
3049 | * - the version wasn't set | |
3050 | * - the specified buffer is too small | |
3051 | * Otherwise, returns ok. | |
3052 | */ | |
3053 | enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn, | |
3054 | struct qed_ptt *p_ptt, | |
3055 | u32 *dump_buf, | |
3056 | u32 buf_size_in_dwords, | |
3057 | u32 *num_dumped_dwords); | |
7b6859fb | 3058 | |
c965db44 TT |
3059 | /** |
3060 | * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size | |
3061 | * for mcp trace results. | |
3062 | * | |
3063 | * @param p_hwfn - HW device data | |
3064 | * @param p_ptt - Ptt window used for writing the registers. | |
3065 | * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data. | |
3066 | * | |
3067 | * @return error if one of the following holds: | |
3068 | * - the version wasn't set | |
3069 | * - the trace data in MCP scratchpad contain an invalid signature | |
3070 | * - the bundle ID in NVRAM is invalid | |
3071 | * - the trace meta data cannot be found (in NVRAM or image file) | |
3072 | * Otherwise, returns ok. | |
3073 | */ | |
3074 | enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn, | |
3075 | struct qed_ptt *p_ptt, | |
3076 | u32 *buf_size); | |
7b6859fb | 3077 | |
c965db44 TT |
3078 | /** |
3079 | * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results | |
3080 | * into the specified buffer. | |
3081 | * | |
3082 | * @param p_hwfn - HW device data | |
3083 | * @param p_ptt - Ptt window used for writing the registers. | |
3084 | * @param dump_buf - Pointer to write the mcp trace data into. | |
3085 | * @param buf_size_in_dwords - Size of the specified buffer in dwords. | |
3086 | * @param num_dumped_dwords - OUT: number of dumped dwords. | |
3087 | * | |
3088 | * @return error if one of the following holds: | |
3089 | * - the version wasn't set | |
3090 | * - the specified buffer is too small | |
3091 | * - the trace data in MCP scratchpad contain an invalid signature | |
3092 | * - the bundle ID in NVRAM is invalid | |
3093 | * - the trace meta data cannot be found (in NVRAM or image file) | |
3094 | * - the trace meta data cannot be read (from NVRAM or image file) | |
3095 | * Otherwise, returns ok. | |
3096 | */ | |
3097 | enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn, | |
3098 | struct qed_ptt *p_ptt, | |
3099 | u32 *dump_buf, | |
3100 | u32 buf_size_in_dwords, | |
3101 | u32 *num_dumped_dwords); | |
7b6859fb | 3102 | |
c965db44 TT |
3103 | /** |
3104 | * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size | |
3105 | * for grc trace fifo results. | |
3106 | * | |
3107 | * @param p_hwfn - HW device data | |
3108 | * @param p_ptt - Ptt window used for writing the registers. | |
3109 | * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data. | |
3110 | * | |
3111 | * @return error if one of the following holds: | |
3112 | * - the version wasn't set | |
3113 | * Otherwise, returns ok. | |
3114 | */ | |
3115 | enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, | |
3116 | struct qed_ptt *p_ptt, | |
3117 | u32 *buf_size); | |
7b6859fb | 3118 | |
c965db44 TT |
3119 | /** |
3120 | * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into | |
3121 | * the specified buffer. | |
3122 | * | |
3123 | * @param p_hwfn - HW device data | |
3124 | * @param p_ptt - Ptt window used for writing the registers. | |
3125 | * @param dump_buf - Pointer to write the reg fifo data into. | |
3126 | * @param buf_size_in_dwords - Size of the specified buffer in dwords. | |
3127 | * @param num_dumped_dwords - OUT: number of dumped dwords. | |
3128 | * | |
3129 | * @return error if one of the following holds: | |
3130 | * - the version wasn't set | |
3131 | * - the specified buffer is too small | |
3132 | * - DMAE transaction failed | |
3133 | * Otherwise, returns ok. | |
3134 | */ | |
3135 | enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn, | |
3136 | struct qed_ptt *p_ptt, | |
3137 | u32 *dump_buf, | |
3138 | u32 buf_size_in_dwords, | |
3139 | u32 *num_dumped_dwords); | |
7b6859fb | 3140 | |
c965db44 TT |
3141 | /** |
3142 | * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size | |
3143 | * for the IGU fifo results. | |
3144 | * | |
3145 | * @param p_hwfn - HW device data | |
3146 | * @param p_ptt - Ptt window used for writing the registers. | |
3147 | * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo | |
3148 | * data. | |
3149 | * | |
3150 | * @return error if one of the following holds: | |
3151 | * - the version wasn't set | |
3152 | * Otherwise, returns ok. | |
3153 | */ | |
3154 | enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, | |
3155 | struct qed_ptt *p_ptt, | |
3156 | u32 *buf_size); | |
7b6859fb | 3157 | |
c965db44 TT |
3158 | /** |
3159 | * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into | |
3160 | * the specified buffer. | |
3161 | * | |
3162 | * @param p_hwfn - HW device data | |
3163 | * @param p_ptt - Ptt window used for writing the registers. | |
3164 | * @param dump_buf - Pointer to write the IGU fifo data into. | |
3165 | * @param buf_size_in_dwords - Size of the specified buffer in dwords. | |
3166 | * @param num_dumped_dwords - OUT: number of dumped dwords. | |
3167 | * | |
3168 | * @return error if one of the following holds: | |
3169 | * - the version wasn't set | |
3170 | * - the specified buffer is too small | |
3171 | * - DMAE transaction failed | |
3172 | * Otherwise, returns ok. | |
3173 | */ | |
3174 | enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn, | |
3175 | struct qed_ptt *p_ptt, | |
3176 | u32 *dump_buf, | |
3177 | u32 buf_size_in_dwords, | |
3178 | u32 *num_dumped_dwords); | |
7b6859fb | 3179 | |
c965db44 TT |
3180 | /** |
3181 | * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required | |
3182 | * buffer size for protection override window results. | |
3183 | * | |
3184 | * @param p_hwfn - HW device data | |
3185 | * @param p_ptt - Ptt window used for writing the registers. | |
3186 | * @param buf_size - OUT: required buffer size (in dwords) for protection | |
3187 | * override data. | |
3188 | * | |
3189 | * @return error if one of the following holds: | |
3190 | * - the version wasn't set | |
3191 | * Otherwise, returns ok. | |
3192 | */ | |
3193 | enum dbg_status | |
3194 | qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn, | |
3195 | struct qed_ptt *p_ptt, | |
3196 | u32 *buf_size); | |
3197 | /** | |
3198 | * @brief qed_dbg_protection_override_dump - Reads protection override window | |
3199 | * entries and writes the results into the specified buffer. | |
3200 | * | |
3201 | * @param p_hwfn - HW device data | |
3202 | * @param p_ptt - Ptt window used for writing the registers. | |
3203 | * @param dump_buf - Pointer to write the protection override data into. | |
3204 | * @param buf_size_in_dwords - Size of the specified buffer in dwords. | |
3205 | * @param num_dumped_dwords - OUT: number of dumped dwords. | |
3206 | * | |
3207 | * @return error if one of the following holds: | |
3208 | * - the version wasn't set | |
3209 | * - the specified buffer is too small | |
3210 | * - DMAE transaction failed | |
3211 | * Otherwise, returns ok. | |
3212 | */ | |
3213 | enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn, | |
3214 | struct qed_ptt *p_ptt, | |
3215 | u32 *dump_buf, | |
3216 | u32 buf_size_in_dwords, | |
3217 | u32 *num_dumped_dwords); | |
3218 | /** | |
3219 | * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer | |
3220 | * size for FW Asserts results. | |
3221 | * | |
3222 | * @param p_hwfn - HW device data | |
3223 | * @param p_ptt - Ptt window used for writing the registers. | |
3224 | * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data. | |
3225 | * | |
3226 | * @return error if one of the following holds: | |
3227 | * - the version wasn't set | |
3228 | * Otherwise, returns ok. | |
3229 | */ | |
3230 | enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn, | |
3231 | struct qed_ptt *p_ptt, | |
3232 | u32 *buf_size); | |
3233 | /** | |
3234 | * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results | |
3235 | * into the specified buffer. | |
3236 | * | |
3237 | * @param p_hwfn - HW device data | |
3238 | * @param p_ptt - Ptt window used for writing the registers. | |
3239 | * @param dump_buf - Pointer to write the FW Asserts data into. | |
3240 | * @param buf_size_in_dwords - Size of the specified buffer in dwords. | |
3241 | * @param num_dumped_dwords - OUT: number of dumped dwords. | |
3242 | * | |
3243 | * @return error if one of the following holds: | |
3244 | * - the version wasn't set | |
3245 | * - the specified buffer is too small | |
3246 | * Otherwise, returns ok. | |
3247 | */ | |
3248 | enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn, | |
3249 | struct qed_ptt *p_ptt, | |
3250 | u32 *dump_buf, | |
3251 | u32 buf_size_in_dwords, | |
3252 | u32 *num_dumped_dwords); | |
0ebbd1c8 MY |
3253 | |
3254 | /** | |
3255 | * @brief qed_dbg_read_attn - Reads the attention registers of the specified | |
3256 | * block and type, and writes the results into the specified buffer. | |
3257 | * | |
3258 | * @param p_hwfn - HW device data | |
3259 | * @param p_ptt - Ptt window used for writing the registers. | |
3260 | * @param block - Block ID. | |
3261 | * @param attn_type - Attention type. | |
3262 | * @param clear_status - Indicates if the attention status should be cleared. | |
3263 | * @param results - OUT: Pointer to write the read results into | |
3264 | * | |
3265 | * @return error if one of the following holds: | |
3266 | * - the version wasn't set | |
3267 | * Otherwise, returns ok. | |
3268 | */ | |
3269 | enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn, | |
3270 | struct qed_ptt *p_ptt, | |
3271 | enum block_id block, | |
3272 | enum dbg_attn_type attn_type, | |
3273 | bool clear_status, | |
3274 | struct dbg_attn_block_result *results); | |
3275 | ||
351a4ded | 3276 | /** |
c965db44 TT |
3277 | * @brief qed_dbg_print_attn - Prints attention registers values in the |
3278 | * specified results struct. | |
351a4ded YM |
3279 | * |
3280 | * @param p_hwfn | |
3281 | * @param results - Pointer to the attention read results | |
3282 | * | |
3283 | * @return error if one of the following holds: | |
3284 | * - the version wasn't set | |
3285 | * Otherwise, returns ok. | |
3286 | */ | |
3287 | enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn, | |
3288 | struct dbg_attn_block_result *results); | |
fe56b9e6 | 3289 | |
c965db44 TT |
3290 | /******************************** Constants **********************************/ |
3291 | ||
351a4ded | 3292 | #define MAX_NAME_LEN 16 |
fe56b9e6 | 3293 | |
c965db44 | 3294 | /***************************** Public Functions *******************************/ |
a2e7699e | 3295 | |
c965db44 TT |
3296 | /** |
3297 | * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with | |
3298 | * debug arrays. | |
3299 | * | |
3300 | * @param bin_ptr - a pointer to the binary data with debug arrays. | |
3301 | */ | |
3302 | enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr); | |
7b6859fb | 3303 | |
c965db44 TT |
3304 | /** |
3305 | * @brief qed_dbg_get_status_str - Returns a string for the specified status. | |
3306 | * | |
3307 | * @param status - a debug status code. | |
3308 | * | |
3309 | * @return a string for the specified status | |
3310 | */ | |
3311 | const char *qed_dbg_get_status_str(enum dbg_status status); | |
7b6859fb | 3312 | |
c965db44 TT |
3313 | /** |
3314 | * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size | |
3315 | * for idle check results (in bytes). | |
3316 | * | |
3317 | * @param p_hwfn - HW device data | |
3318 | * @param dump_buf - idle check dump buffer. | |
3319 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3320 | * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed | |
3321 | * results. | |
3322 | * | |
3323 | * @return error if the parsing fails, ok otherwise. | |
3324 | */ | |
3325 | enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn, | |
3326 | u32 *dump_buf, | |
3327 | u32 num_dumped_dwords, | |
3328 | u32 *results_buf_size); | |
3329 | /** | |
3330 | * @brief qed_print_idle_chk_results - Prints idle check results | |
3331 | * | |
3332 | * @param p_hwfn - HW device data | |
3333 | * @param dump_buf - idle check dump buffer. | |
3334 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3335 | * @param results_buf - buffer for printing the idle check results. | |
3336 | * @param num_errors - OUT: number of errors found in idle check. | |
3337 | * @param num_warnings - OUT: number of warnings found in idle check. | |
3338 | * | |
3339 | * @return error if the parsing fails, ok otherwise. | |
3340 | */ | |
3341 | enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn, | |
3342 | u32 *dump_buf, | |
3343 | u32 num_dumped_dwords, | |
3344 | char *results_buf, | |
3345 | u32 *num_errors, | |
3346 | u32 *num_warnings); | |
7b6859fb | 3347 | |
da090917 TT |
3348 | /** |
3349 | * @brief qed_dbg_mcp_trace_set_meta_data - Sets a pointer to the MCP Trace | |
3350 | * meta data. | |
3351 | * | |
3352 | * Needed in case the MCP Trace dump doesn't contain the meta data (e.g. due to | |
3353 | * no NVRAM access). | |
3354 | * | |
3355 | * @param data - pointer to MCP Trace meta data | |
3356 | * @param size - size of MCP Trace meta data in dwords | |
3357 | */ | |
3358 | void qed_dbg_mcp_trace_set_meta_data(u32 *data, u32 size); | |
3359 | ||
c965db44 TT |
3360 | /** |
3361 | * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size | |
3362 | * for MCP Trace results (in bytes). | |
3363 | * | |
3364 | * @param p_hwfn - HW device data | |
3365 | * @param dump_buf - MCP Trace dump buffer. | |
3366 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3367 | * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed | |
3368 | * results. | |
3369 | * | |
3370 | * @return error if the parsing fails, ok otherwise. | |
3371 | */ | |
3372 | enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn, | |
3373 | u32 *dump_buf, | |
3374 | u32 num_dumped_dwords, | |
3375 | u32 *results_buf_size); | |
7b6859fb | 3376 | |
c965db44 TT |
3377 | /** |
3378 | * @brief qed_print_mcp_trace_results - Prints MCP Trace results | |
3379 | * | |
3380 | * @param p_hwfn - HW device data | |
3381 | * @param dump_buf - mcp trace dump buffer, starting from the header. | |
3382 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3383 | * @param results_buf - buffer for printing the mcp trace results. | |
3384 | * | |
3385 | * @return error if the parsing fails, ok otherwise. | |
3386 | */ | |
3387 | enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn, | |
3388 | u32 *dump_buf, | |
3389 | u32 num_dumped_dwords, | |
3390 | char *results_buf); | |
7b6859fb | 3391 | |
50bc60cb MK |
3392 | /** |
3393 | * @brief print_mcp_trace_line - Prints MCP Trace results for a single line | |
3394 | * | |
3395 | * @param dump_buf - mcp trace dump buffer, starting from the header. | |
3396 | * @param num_dumped_bytes - number of bytes that were dumped. | |
3397 | * @param results_buf - buffer for printing the mcp trace results. | |
3398 | * | |
3399 | * @return error if the parsing fails, ok otherwise. | |
3400 | */ | |
3401 | enum dbg_status qed_print_mcp_trace_line(u8 *dump_buf, | |
3402 | u32 num_dumped_bytes, | |
3403 | char *results_buf); | |
3404 | ||
c965db44 TT |
3405 | /** |
3406 | * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size | |
3407 | * for reg_fifo results (in bytes). | |
3408 | * | |
3409 | * @param p_hwfn - HW device data | |
3410 | * @param dump_buf - reg fifo dump buffer. | |
3411 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3412 | * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed | |
3413 | * results. | |
3414 | * | |
3415 | * @return error if the parsing fails, ok otherwise. | |
3416 | */ | |
3417 | enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn, | |
3418 | u32 *dump_buf, | |
3419 | u32 num_dumped_dwords, | |
3420 | u32 *results_buf_size); | |
7b6859fb | 3421 | |
c965db44 TT |
3422 | /** |
3423 | * @brief qed_print_reg_fifo_results - Prints reg fifo results | |
3424 | * | |
3425 | * @param p_hwfn - HW device data | |
3426 | * @param dump_buf - reg fifo dump buffer, starting from the header. | |
3427 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3428 | * @param results_buf - buffer for printing the reg fifo results. | |
3429 | * | |
3430 | * @return error if the parsing fails, ok otherwise. | |
3431 | */ | |
3432 | enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn, | |
3433 | u32 *dump_buf, | |
3434 | u32 num_dumped_dwords, | |
3435 | char *results_buf); | |
7b6859fb | 3436 | |
c965db44 TT |
3437 | /** |
3438 | * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size | |
3439 | * for igu_fifo results (in bytes). | |
3440 | * | |
3441 | * @param p_hwfn - HW device data | |
3442 | * @param dump_buf - IGU fifo dump buffer. | |
3443 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3444 | * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed | |
3445 | * results. | |
3446 | * | |
3447 | * @return error if the parsing fails, ok otherwise. | |
3448 | */ | |
3449 | enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn, | |
3450 | u32 *dump_buf, | |
3451 | u32 num_dumped_dwords, | |
3452 | u32 *results_buf_size); | |
7b6859fb | 3453 | |
c965db44 TT |
3454 | /** |
3455 | * @brief qed_print_igu_fifo_results - Prints IGU fifo results | |
3456 | * | |
3457 | * @param p_hwfn - HW device data | |
3458 | * @param dump_buf - IGU fifo dump buffer, starting from the header. | |
3459 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3460 | * @param results_buf - buffer for printing the IGU fifo results. | |
3461 | * | |
3462 | * @return error if the parsing fails, ok otherwise. | |
3463 | */ | |
3464 | enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn, | |
3465 | u32 *dump_buf, | |
3466 | u32 num_dumped_dwords, | |
3467 | char *results_buf); | |
7b6859fb | 3468 | |
c965db44 TT |
3469 | /** |
3470 | * @brief qed_get_protection_override_results_buf_size - Returns the required | |
3471 | * buffer size for protection override results (in bytes). | |
3472 | * | |
3473 | * @param p_hwfn - HW device data | |
3474 | * @param dump_buf - protection override dump buffer. | |
3475 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3476 | * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed | |
3477 | * results. | |
3478 | * | |
3479 | * @return error if the parsing fails, ok otherwise. | |
3480 | */ | |
3481 | enum dbg_status | |
3482 | qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn, | |
3483 | u32 *dump_buf, | |
3484 | u32 num_dumped_dwords, | |
3485 | u32 *results_buf_size); | |
7b6859fb | 3486 | |
c965db44 TT |
3487 | /** |
3488 | * @brief qed_print_protection_override_results - Prints protection override | |
3489 | * results. | |
3490 | * | |
3491 | * @param p_hwfn - HW device data | |
3492 | * @param dump_buf - protection override dump buffer, starting from the header. | |
3493 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3494 | * @param results_buf - buffer for printing the reg fifo results. | |
3495 | * | |
3496 | * @return error if the parsing fails, ok otherwise. | |
3497 | */ | |
3498 | enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn, | |
3499 | u32 *dump_buf, | |
3500 | u32 num_dumped_dwords, | |
3501 | char *results_buf); | |
7b6859fb | 3502 | |
c965db44 TT |
3503 | /** |
3504 | * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size | |
3505 | * for FW Asserts results (in bytes). | |
3506 | * | |
3507 | * @param p_hwfn - HW device data | |
3508 | * @param dump_buf - FW Asserts dump buffer. | |
3509 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3510 | * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed | |
3511 | * results. | |
3512 | * | |
3513 | * @return error if the parsing fails, ok otherwise. | |
3514 | */ | |
3515 | enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn, | |
3516 | u32 *dump_buf, | |
3517 | u32 num_dumped_dwords, | |
3518 | u32 *results_buf_size); | |
7b6859fb | 3519 | |
c965db44 TT |
3520 | /** |
3521 | * @brief qed_print_fw_asserts_results - Prints FW Asserts results | |
3522 | * | |
3523 | * @param p_hwfn - HW device data | |
3524 | * @param dump_buf - FW Asserts dump buffer, starting from the header. | |
3525 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3526 | * @param results_buf - buffer for printing the FW Asserts results. | |
3527 | * | |
3528 | * @return error if the parsing fails, ok otherwise. | |
3529 | */ | |
3530 | enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn, | |
3531 | u32 *dump_buf, | |
3532 | u32 num_dumped_dwords, | |
3533 | char *results_buf); | |
7b6859fb | 3534 | |
0ebbd1c8 MY |
3535 | /** |
3536 | * @brief qed_dbg_parse_attn - Parses and prints attention registers values in | |
3537 | * the specified results struct. | |
3538 | * | |
3539 | * @param p_hwfn - HW device data | |
3540 | * @param results - Pointer to the attention read results | |
3541 | * | |
3542 | * @return error if one of the following holds: | |
3543 | * - the version wasn't set | |
3544 | * Otherwise, returns ok. | |
3545 | */ | |
3546 | enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn, | |
3547 | struct dbg_attn_block_result *results); | |
3548 | ||
7b6859fb MY |
3549 | /* Debug Bus blocks */ |
3550 | static const u32 dbg_bus_blocks[] = { | |
3551 | 0x0000000f, /* grc, bb, 15 lines */ | |
3552 | 0x0000000f, /* grc, k2, 15 lines */ | |
3553 | 0x00000000, | |
3554 | 0x00000000, /* miscs, bb, 0 lines */ | |
3555 | 0x00000000, /* miscs, k2, 0 lines */ | |
3556 | 0x00000000, | |
3557 | 0x00000000, /* misc, bb, 0 lines */ | |
3558 | 0x00000000, /* misc, k2, 0 lines */ | |
3559 | 0x00000000, | |
3560 | 0x00000000, /* dbu, bb, 0 lines */ | |
3561 | 0x00000000, /* dbu, k2, 0 lines */ | |
3562 | 0x00000000, | |
3563 | 0x000f0127, /* pglue_b, bb, 39 lines */ | |
3564 | 0x0036012a, /* pglue_b, k2, 42 lines */ | |
3565 | 0x00000000, | |
3566 | 0x00000000, /* cnig, bb, 0 lines */ | |
3567 | 0x00120102, /* cnig, k2, 2 lines */ | |
3568 | 0x00000000, | |
3569 | 0x00000000, /* cpmu, bb, 0 lines */ | |
3570 | 0x00000000, /* cpmu, k2, 0 lines */ | |
3571 | 0x00000000, | |
3572 | 0x00000001, /* ncsi, bb, 1 lines */ | |
3573 | 0x00000001, /* ncsi, k2, 1 lines */ | |
3574 | 0x00000000, | |
3575 | 0x00000000, /* opte, bb, 0 lines */ | |
3576 | 0x00000000, /* opte, k2, 0 lines */ | |
3577 | 0x00000000, | |
3578 | 0x00600085, /* bmb, bb, 133 lines */ | |
3579 | 0x00600085, /* bmb, k2, 133 lines */ | |
3580 | 0x00000000, | |
3581 | 0x00000000, /* pcie, bb, 0 lines */ | |
3582 | 0x00e50033, /* pcie, k2, 51 lines */ | |
3583 | 0x00000000, | |
3584 | 0x00000000, /* mcp, bb, 0 lines */ | |
3585 | 0x00000000, /* mcp, k2, 0 lines */ | |
3586 | 0x00000000, | |
3587 | 0x01180009, /* mcp2, bb, 9 lines */ | |
3588 | 0x01180009, /* mcp2, k2, 9 lines */ | |
3589 | 0x00000000, | |
3590 | 0x01210104, /* pswhst, bb, 4 lines */ | |
3591 | 0x01210104, /* pswhst, k2, 4 lines */ | |
3592 | 0x00000000, | |
3593 | 0x01250103, /* pswhst2, bb, 3 lines */ | |
3594 | 0x01250103, /* pswhst2, k2, 3 lines */ | |
3595 | 0x00000000, | |
3596 | 0x00340101, /* pswrd, bb, 1 lines */ | |
3597 | 0x00340101, /* pswrd, k2, 1 lines */ | |
3598 | 0x00000000, | |
3599 | 0x01280119, /* pswrd2, bb, 25 lines */ | |
3600 | 0x01280119, /* pswrd2, k2, 25 lines */ | |
3601 | 0x00000000, | |
3602 | 0x01410109, /* pswwr, bb, 9 lines */ | |
3603 | 0x01410109, /* pswwr, k2, 9 lines */ | |
3604 | 0x00000000, | |
3605 | 0x00000000, /* pswwr2, bb, 0 lines */ | |
3606 | 0x00000000, /* pswwr2, k2, 0 lines */ | |
3607 | 0x00000000, | |
3608 | 0x001c0001, /* pswrq, bb, 1 lines */ | |
3609 | 0x001c0001, /* pswrq, k2, 1 lines */ | |
3610 | 0x00000000, | |
3611 | 0x014a0015, /* pswrq2, bb, 21 lines */ | |
3612 | 0x014a0015, /* pswrq2, k2, 21 lines */ | |
3613 | 0x00000000, | |
3614 | 0x00000000, /* pglcs, bb, 0 lines */ | |
3615 | 0x00120006, /* pglcs, k2, 6 lines */ | |
3616 | 0x00000000, | |
3617 | 0x00100001, /* dmae, bb, 1 lines */ | |
3618 | 0x00100001, /* dmae, k2, 1 lines */ | |
3619 | 0x00000000, | |
3620 | 0x015f0105, /* ptu, bb, 5 lines */ | |
3621 | 0x015f0105, /* ptu, k2, 5 lines */ | |
3622 | 0x00000000, | |
3623 | 0x01640120, /* tcm, bb, 32 lines */ | |
3624 | 0x01640120, /* tcm, k2, 32 lines */ | |
3625 | 0x00000000, | |
3626 | 0x01640120, /* mcm, bb, 32 lines */ | |
3627 | 0x01640120, /* mcm, k2, 32 lines */ | |
3628 | 0x00000000, | |
3629 | 0x01640120, /* ucm, bb, 32 lines */ | |
3630 | 0x01640120, /* ucm, k2, 32 lines */ | |
3631 | 0x00000000, | |
3632 | 0x01640120, /* xcm, bb, 32 lines */ | |
3633 | 0x01640120, /* xcm, k2, 32 lines */ | |
3634 | 0x00000000, | |
3635 | 0x01640120, /* ycm, bb, 32 lines */ | |
3636 | 0x01640120, /* ycm, k2, 32 lines */ | |
3637 | 0x00000000, | |
3638 | 0x01640120, /* pcm, bb, 32 lines */ | |
3639 | 0x01640120, /* pcm, k2, 32 lines */ | |
3640 | 0x00000000, | |
3641 | 0x01840062, /* qm, bb, 98 lines */ | |
3642 | 0x01840062, /* qm, k2, 98 lines */ | |
3643 | 0x00000000, | |
3644 | 0x01e60021, /* tm, bb, 33 lines */ | |
3645 | 0x01e60021, /* tm, k2, 33 lines */ | |
3646 | 0x00000000, | |
3647 | 0x02070107, /* dorq, bb, 7 lines */ | |
3648 | 0x02070107, /* dorq, k2, 7 lines */ | |
3649 | 0x00000000, | |
3650 | 0x00600185, /* brb, bb, 133 lines */ | |
3651 | 0x00600185, /* brb, k2, 133 lines */ | |
3652 | 0x00000000, | |
3653 | 0x020e0019, /* src, bb, 25 lines */ | |
3654 | 0x020c001a, /* src, k2, 26 lines */ | |
3655 | 0x00000000, | |
3656 | 0x02270104, /* prs, bb, 4 lines */ | |
3657 | 0x02270104, /* prs, k2, 4 lines */ | |
3658 | 0x00000000, | |
3659 | 0x022b0133, /* tsdm, bb, 51 lines */ | |
3660 | 0x022b0133, /* tsdm, k2, 51 lines */ | |
3661 | 0x00000000, | |
3662 | 0x022b0133, /* msdm, bb, 51 lines */ | |
3663 | 0x022b0133, /* msdm, k2, 51 lines */ | |
3664 | 0x00000000, | |
3665 | 0x022b0133, /* usdm, bb, 51 lines */ | |
3666 | 0x022b0133, /* usdm, k2, 51 lines */ | |
3667 | 0x00000000, | |
3668 | 0x022b0133, /* xsdm, bb, 51 lines */ | |
3669 | 0x022b0133, /* xsdm, k2, 51 lines */ | |
3670 | 0x00000000, | |
3671 | 0x022b0133, /* ysdm, bb, 51 lines */ | |
3672 | 0x022b0133, /* ysdm, k2, 51 lines */ | |
3673 | 0x00000000, | |
3674 | 0x022b0133, /* psdm, bb, 51 lines */ | |
3675 | 0x022b0133, /* psdm, k2, 51 lines */ | |
3676 | 0x00000000, | |
3677 | 0x025e010c, /* tsem, bb, 12 lines */ | |
3678 | 0x025e010c, /* tsem, k2, 12 lines */ | |
3679 | 0x00000000, | |
3680 | 0x025e010c, /* msem, bb, 12 lines */ | |
3681 | 0x025e010c, /* msem, k2, 12 lines */ | |
3682 | 0x00000000, | |
3683 | 0x025e010c, /* usem, bb, 12 lines */ | |
3684 | 0x025e010c, /* usem, k2, 12 lines */ | |
3685 | 0x00000000, | |
3686 | 0x025e010c, /* xsem, bb, 12 lines */ | |
3687 | 0x025e010c, /* xsem, k2, 12 lines */ | |
3688 | 0x00000000, | |
3689 | 0x025e010c, /* ysem, bb, 12 lines */ | |
3690 | 0x025e010c, /* ysem, k2, 12 lines */ | |
3691 | 0x00000000, | |
3692 | 0x025e010c, /* psem, bb, 12 lines */ | |
3693 | 0x025e010c, /* psem, k2, 12 lines */ | |
3694 | 0x00000000, | |
3695 | 0x026a000d, /* rss, bb, 13 lines */ | |
3696 | 0x026a000d, /* rss, k2, 13 lines */ | |
3697 | 0x00000000, | |
3698 | 0x02770106, /* tmld, bb, 6 lines */ | |
3699 | 0x02770106, /* tmld, k2, 6 lines */ | |
3700 | 0x00000000, | |
3701 | 0x027d0106, /* muld, bb, 6 lines */ | |
3702 | 0x027d0106, /* muld, k2, 6 lines */ | |
3703 | 0x00000000, | |
3704 | 0x02770005, /* yuld, bb, 5 lines */ | |
3705 | 0x02770005, /* yuld, k2, 5 lines */ | |
3706 | 0x00000000, | |
3707 | 0x02830107, /* xyld, bb, 7 lines */ | |
3708 | 0x027d0107, /* xyld, k2, 7 lines */ | |
3709 | 0x00000000, | |
3710 | 0x00000000, /* ptld, bb, 0 lines */ | |
3711 | 0x00000000, /* ptld, k2, 0 lines */ | |
3712 | 0x00000000, | |
3713 | 0x00000000, /* ypld, bb, 0 lines */ | |
3714 | 0x00000000, /* ypld, k2, 0 lines */ | |
3715 | 0x00000000, | |
3716 | 0x028a010e, /* prm, bb, 14 lines */ | |
3717 | 0x02980110, /* prm, k2, 16 lines */ | |
3718 | 0x00000000, | |
3719 | 0x02a8000d, /* pbf_pb1, bb, 13 lines */ | |
3720 | 0x02a8000d, /* pbf_pb1, k2, 13 lines */ | |
3721 | 0x00000000, | |
3722 | 0x02a8000d, /* pbf_pb2, bb, 13 lines */ | |
3723 | 0x02a8000d, /* pbf_pb2, k2, 13 lines */ | |
3724 | 0x00000000, | |
3725 | 0x02a8000d, /* rpb, bb, 13 lines */ | |
3726 | 0x02a8000d, /* rpb, k2, 13 lines */ | |
3727 | 0x00000000, | |
3728 | 0x00600185, /* btb, bb, 133 lines */ | |
3729 | 0x00600185, /* btb, k2, 133 lines */ | |
3730 | 0x00000000, | |
3731 | 0x02b50117, /* pbf, bb, 23 lines */ | |
3732 | 0x02b50117, /* pbf, k2, 23 lines */ | |
3733 | 0x00000000, | |
3734 | 0x02cc0006, /* rdif, bb, 6 lines */ | |
3735 | 0x02cc0006, /* rdif, k2, 6 lines */ | |
3736 | 0x00000000, | |
3737 | 0x02d20006, /* tdif, bb, 6 lines */ | |
3738 | 0x02d20006, /* tdif, k2, 6 lines */ | |
3739 | 0x00000000, | |
3740 | 0x02d80003, /* cdu, bb, 3 lines */ | |
3741 | 0x02db000e, /* cdu, k2, 14 lines */ | |
3742 | 0x00000000, | |
3743 | 0x02e9010d, /* ccfc, bb, 13 lines */ | |
3744 | 0x02f60117, /* ccfc, k2, 23 lines */ | |
3745 | 0x00000000, | |
3746 | 0x02e9010d, /* tcfc, bb, 13 lines */ | |
3747 | 0x02f60117, /* tcfc, k2, 23 lines */ | |
3748 | 0x00000000, | |
3749 | 0x030d0133, /* igu, bb, 51 lines */ | |
3750 | 0x030d0133, /* igu, k2, 51 lines */ | |
3751 | 0x00000000, | |
3752 | 0x03400106, /* cau, bb, 6 lines */ | |
3753 | 0x03400106, /* cau, k2, 6 lines */ | |
3754 | 0x00000000, | |
3755 | 0x00000000, /* rgfs, bb, 0 lines */ | |
3756 | 0x00000000, /* rgfs, k2, 0 lines */ | |
3757 | 0x00000000, | |
3758 | 0x00000000, /* rgsrc, bb, 0 lines */ | |
3759 | 0x00000000, /* rgsrc, k2, 0 lines */ | |
3760 | 0x00000000, | |
3761 | 0x00000000, /* tgfs, bb, 0 lines */ | |
3762 | 0x00000000, /* tgfs, k2, 0 lines */ | |
3763 | 0x00000000, | |
3764 | 0x00000000, /* tgsrc, bb, 0 lines */ | |
3765 | 0x00000000, /* tgsrc, k2, 0 lines */ | |
3766 | 0x00000000, | |
3767 | 0x00000000, /* umac, bb, 0 lines */ | |
3768 | 0x00120006, /* umac, k2, 6 lines */ | |
3769 | 0x00000000, | |
3770 | 0x00000000, /* xmac, bb, 0 lines */ | |
3771 | 0x00000000, /* xmac, k2, 0 lines */ | |
3772 | 0x00000000, | |
3773 | 0x00000000, /* dbg, bb, 0 lines */ | |
3774 | 0x00000000, /* dbg, k2, 0 lines */ | |
3775 | 0x00000000, | |
3776 | 0x0346012b, /* nig, bb, 43 lines */ | |
3777 | 0x0346011d, /* nig, k2, 29 lines */ | |
3778 | 0x00000000, | |
3779 | 0x00000000, /* wol, bb, 0 lines */ | |
3780 | 0x001c0002, /* wol, k2, 2 lines */ | |
3781 | 0x00000000, | |
3782 | 0x00000000, /* bmbn, bb, 0 lines */ | |
3783 | 0x00210008, /* bmbn, k2, 8 lines */ | |
3784 | 0x00000000, | |
3785 | 0x00000000, /* ipc, bb, 0 lines */ | |
3786 | 0x00000000, /* ipc, k2, 0 lines */ | |
3787 | 0x00000000, | |
3788 | 0x00000000, /* nwm, bb, 0 lines */ | |
3789 | 0x0371000b, /* nwm, k2, 11 lines */ | |
3790 | 0x00000000, | |
3791 | 0x00000000, /* nws, bb, 0 lines */ | |
3792 | 0x037c0009, /* nws, k2, 9 lines */ | |
3793 | 0x00000000, | |
3794 | 0x00000000, /* ms, bb, 0 lines */ | |
3795 | 0x00120004, /* ms, k2, 4 lines */ | |
3796 | 0x00000000, | |
3797 | 0x00000000, /* phy_pcie, bb, 0 lines */ | |
3798 | 0x00e5001a, /* phy_pcie, k2, 26 lines */ | |
3799 | 0x00000000, | |
3800 | 0x00000000, /* led, bb, 0 lines */ | |
3801 | 0x00000000, /* led, k2, 0 lines */ | |
3802 | 0x00000000, | |
3803 | 0x00000000, /* avs_wrap, bb, 0 lines */ | |
3804 | 0x00000000, /* avs_wrap, k2, 0 lines */ | |
3805 | 0x00000000, | |
3806 | 0x00000000, /* bar0_map, bb, 0 lines */ | |
3807 | 0x00000000, /* bar0_map, k2, 0 lines */ | |
3808 | 0x00000000, | |
da090917 TT |
3809 | 0x00000000, /* bar0_map, bb, 0 lines */ |
3810 | 0x00000000, /* bar0_map, k2, 0 lines */ | |
3811 | 0x00000000, | |
7b6859fb MY |
3812 | }; |
3813 | ||
fe56b9e6 | 3814 | /* Win 2 */ |
05fafbfb | 3815 | #define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL |
351a4ded | 3816 | |
fe56b9e6 | 3817 | /* Win 3 */ |
05fafbfb | 3818 | #define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL |
351a4ded | 3819 | |
fe56b9e6 | 3820 | /* Win 4 */ |
05fafbfb | 3821 | #define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL |
351a4ded | 3822 | |
fe56b9e6 | 3823 | /* Win 5 */ |
05fafbfb | 3824 | #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL |
351a4ded | 3825 | |
fe56b9e6 | 3826 | /* Win 6 */ |
05fafbfb | 3827 | #define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL |
351a4ded | 3828 | |
fe56b9e6 | 3829 | /* Win 7 */ |
05fafbfb | 3830 | #define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL |
351a4ded | 3831 | |
fe56b9e6 | 3832 | /* Win 8 */ |
05fafbfb | 3833 | #define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL |
351a4ded | 3834 | |
fe56b9e6 | 3835 | /* Win 9 */ |
05fafbfb | 3836 | #define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL |
351a4ded | 3837 | |
fe56b9e6 | 3838 | /* Win 10 */ |
05fafbfb | 3839 | #define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL |
351a4ded | 3840 | |
fe56b9e6 | 3841 | /* Win 11 */ |
05fafbfb | 3842 | #define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL |
fe56b9e6 YM |
3843 | |
3844 | /** | |
3845 | * @brief qed_qm_pf_mem_size - prepare QM ILT sizes | |
3846 | * | |
3847 | * Returns the required host memory size in 4KB units. | |
3848 | * Must be called before all QM init HSI functions. | |
3849 | * | |
351a4ded YM |
3850 | * @param num_pf_cids - number of connections used by this PF |
3851 | * @param num_vf_cids - number of connections used by VFs of this PF | |
3852 | * @param num_tids - number of tasks used by this PF | |
3853 | * @param num_pf_pqs - number of PQs used by this PF | |
3854 | * @param num_vf_pqs - number of PQs used by VFs of this PF | |
fe56b9e6 YM |
3855 | * |
3856 | * @return The required host memory size in 4KB units. | |
3857 | */ | |
da090917 | 3858 | u32 qed_qm_pf_mem_size(u32 num_pf_cids, |
351a4ded YM |
3859 | u32 num_vf_cids, |
3860 | u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs); | |
fe56b9e6 YM |
3861 | |
3862 | struct qed_qm_common_rt_init_params { | |
351a4ded YM |
3863 | u8 max_ports_per_engine; |
3864 | u8 max_phys_tcs_per_port; | |
3865 | bool pf_rl_en; | |
3866 | bool pf_wfq_en; | |
3867 | bool vport_rl_en; | |
3868 | bool vport_wfq_en; | |
3869 | struct init_qm_port_params *port_params; | |
fe56b9e6 YM |
3870 | }; |
3871 | ||
351a4ded YM |
3872 | int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn, |
3873 | struct qed_qm_common_rt_init_params *p_params); | |
3874 | ||
3875 | struct qed_qm_pf_rt_init_params { | |
3876 | u8 port_id; | |
3877 | u8 pf_id; | |
3878 | u8 max_phys_tcs_per_port; | |
da090917 | 3879 | bool is_pf_loading; |
351a4ded YM |
3880 | u32 num_pf_cids; |
3881 | u32 num_vf_cids; | |
3882 | u32 num_tids; | |
3883 | u16 start_pq; | |
3884 | u16 num_pf_pqs; | |
3885 | u16 num_vf_pqs; | |
3886 | u8 start_vport; | |
3887 | u8 num_vports; | |
05fafbfb | 3888 | u16 pf_wfq; |
351a4ded | 3889 | u32 pf_rl; |
da090917 | 3890 | u32 link_speed; |
351a4ded YM |
3891 | struct init_qm_pq_params *pq_params; |
3892 | struct init_qm_vport_params *vport_params; | |
3893 | }; | |
3894 | ||
3895 | int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn, | |
3896 | struct qed_ptt *p_ptt, | |
3897 | struct qed_qm_pf_rt_init_params *p_params); | |
3898 | ||
fe56b9e6 | 3899 | /** |
351a4ded | 3900 | * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF |
fe56b9e6 YM |
3901 | * |
3902 | * @param p_hwfn | |
351a4ded YM |
3903 | * @param p_ptt - ptt window used for writing the registers |
3904 | * @param pf_id - PF ID | |
3905 | * @param pf_wfq - WFQ weight. Must be non-zero. | |
fe56b9e6 YM |
3906 | * |
3907 | * @return 0 on success, -1 on error. | |
3908 | */ | |
351a4ded YM |
3909 | int qed_init_pf_wfq(struct qed_hwfn *p_hwfn, |
3910 | struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq); | |
fe56b9e6 YM |
3911 | |
3912 | /** | |
351a4ded | 3913 | * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF |
fe56b9e6 YM |
3914 | * |
3915 | * @param p_hwfn | |
351a4ded YM |
3916 | * @param p_ptt - ptt window used for writing the registers |
3917 | * @param pf_id - PF ID | |
3918 | * @param pf_rl - rate limit in Mb/sec units | |
fe56b9e6 YM |
3919 | * |
3920 | * @return 0 on success, -1 on error. | |
3921 | */ | |
351a4ded YM |
3922 | int qed_init_pf_rl(struct qed_hwfn *p_hwfn, |
3923 | struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl); | |
fe56b9e6 YM |
3924 | |
3925 | /** | |
351a4ded | 3926 | * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT |
fe56b9e6 YM |
3927 | * |
3928 | * @param p_hwfn | |
351a4ded YM |
3929 | * @param p_ptt - ptt window used for writing the registers |
3930 | * @param first_tx_pq_id- An array containing the first Tx PQ ID associated | |
3931 | * with the VPORT for each TC. This array is filled by | |
3932 | * qed_qm_pf_rt_init | |
3933 | * @param vport_wfq - WFQ weight. Must be non-zero. | |
fe56b9e6 YM |
3934 | * |
3935 | * @return 0 on success, -1 on error. | |
3936 | */ | |
351a4ded YM |
3937 | int qed_init_vport_wfq(struct qed_hwfn *p_hwfn, |
3938 | struct qed_ptt *p_ptt, | |
3939 | u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq); | |
fe56b9e6 | 3940 | |
351a4ded YM |
3941 | /** |
3942 | * @brief qed_init_vport_rl - Initializes the rate limit of the specified VPORT | |
3943 | * | |
3944 | * @param p_hwfn | |
3945 | * @param p_ptt - ptt window used for writing the registers | |
3946 | * @param vport_id - VPORT ID | |
3947 | * @param vport_rl - rate limit in Mb/sec units | |
da090917 | 3948 | * @param link_speed - link speed in Mbps. |
351a4ded YM |
3949 | * |
3950 | * @return 0 on success, -1 on error. | |
3951 | */ | |
3952 | int qed_init_vport_rl(struct qed_hwfn *p_hwfn, | |
da090917 TT |
3953 | struct qed_ptt *p_ptt, |
3954 | u8 vport_id, u32 vport_rl, u32 link_speed); | |
3955 | ||
fe56b9e6 YM |
3956 | /** |
3957 | * @brief qed_send_qm_stop_cmd Sends a stop command to the QM | |
3958 | * | |
3959 | * @param p_hwfn | |
351a4ded | 3960 | * @param p_ptt |
fe56b9e6 | 3961 | * @param is_release_cmd - true for release, false for stop. |
351a4ded YM |
3962 | * @param is_tx_pq - true for Tx PQs, false for Other PQs. |
3963 | * @param start_pq - first PQ ID to stop | |
3964 | * @param num_pqs - Number of PQs to stop, starting from start_pq. | |
fe56b9e6 | 3965 | * |
da090917 TT |
3966 | * @return bool, true if successful, false if timeout occurred while waiting for |
3967 | * QM command done. | |
fe56b9e6 | 3968 | */ |
351a4ded YM |
3969 | bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn, |
3970 | struct qed_ptt *p_ptt, | |
3971 | bool is_release_cmd, | |
3972 | bool is_tx_pq, u16 start_pq, u16 num_pqs); | |
fe56b9e6 | 3973 | |
351a4ded YM |
3974 | /** |
3975 | * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port | |
3976 | * | |
da090917 | 3977 | * @param p_hwfn |
351a4ded YM |
3978 | * @param p_ptt - ptt window used for writing the registers. |
3979 | * @param dest_port - vxlan destination udp port. | |
3980 | */ | |
464f6645 | 3981 | void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn, |
351a4ded YM |
3982 | struct qed_ptt *p_ptt, u16 dest_port); |
3983 | ||
3984 | /** | |
3985 | * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW | |
3986 | * | |
da090917 | 3987 | * @param p_hwfn |
351a4ded YM |
3988 | * @param p_ptt - ptt window used for writing the registers. |
3989 | * @param vxlan_enable - vxlan enable flag. | |
3990 | */ | |
464f6645 MC |
3991 | void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn, |
3992 | struct qed_ptt *p_ptt, bool vxlan_enable); | |
351a4ded YM |
3993 | |
3994 | /** | |
3995 | * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW | |
3996 | * | |
da090917 | 3997 | * @param p_hwfn |
351a4ded YM |
3998 | * @param p_ptt - ptt window used for writing the registers. |
3999 | * @param eth_gre_enable - eth GRE enable enable flag. | |
4000 | * @param ip_gre_enable - IP GRE enable enable flag. | |
4001 | */ | |
464f6645 | 4002 | void qed_set_gre_enable(struct qed_hwfn *p_hwfn, |
351a4ded YM |
4003 | struct qed_ptt *p_ptt, |
4004 | bool eth_gre_enable, bool ip_gre_enable); | |
4005 | ||
4006 | /** | |
4007 | * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port | |
4008 | * | |
da090917 | 4009 | * @param p_hwfn |
351a4ded YM |
4010 | * @param p_ptt - ptt window used for writing the registers. |
4011 | * @param dest_port - geneve destination udp port. | |
4012 | */ | |
464f6645 MC |
4013 | void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn, |
4014 | struct qed_ptt *p_ptt, u16 dest_port); | |
351a4ded YM |
4015 | |
4016 | /** | |
4017 | * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW | |
4018 | * | |
4019 | * @param p_ptt - ptt window used for writing the registers. | |
4020 | * @param eth_geneve_enable - eth GENEVE enable enable flag. | |
4021 | * @param ip_geneve_enable - IP GENEVE enable enable flag. | |
4022 | */ | |
464f6645 | 4023 | void qed_set_geneve_enable(struct qed_hwfn *p_hwfn, |
351a4ded YM |
4024 | struct qed_ptt *p_ptt, |
4025 | bool eth_geneve_enable, bool ip_geneve_enable); | |
da090917 | 4026 | |
50bc60cb MK |
4027 | void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn, |
4028 | struct qed_ptt *p_ptt, bool enable); | |
4029 | ||
da090917 TT |
4030 | /** |
4031 | * @brief qed_gft_disable - Disable GFT | |
4032 | * | |
4033 | * @param p_hwfn | |
4034 | * @param p_ptt - ptt window used for writing the registers. | |
4035 | * @param pf_id - pf on which to disable GFT. | |
4036 | */ | |
4037 | void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id); | |
4038 | ||
4039 | /** | |
4040 | * @brief qed_gft_config - Enable and configure HW for GFT | |
4041 | * | |
4042 | * @param p_hwfn | |
4043 | * @param p_ptt - ptt window used for writing the registers. | |
4044 | * @param pf_id - pf on which to enable GFT. | |
4045 | * @param tcp - set profile tcp packets. | |
4046 | * @param udp - set profile udp packet. | |
4047 | * @param ipv4 - set profile ipv4 packet. | |
4048 | * @param ipv6 - set profile ipv6 packet. | |
4049 | * @param profile_type - define packet same fields. Use enum gft_profile_type. | |
4050 | */ | |
4051 | void qed_gft_config(struct qed_hwfn *p_hwfn, | |
4052 | struct qed_ptt *p_ptt, | |
4053 | u16 pf_id, | |
4054 | bool tcp, | |
4055 | bool udp, | |
4056 | bool ipv4, bool ipv6, enum gft_profile_type profile_type); | |
4057 | ||
4058 | /** | |
4059 | * @brief qed_enable_context_validation - Enable and configure context | |
4060 | * validation. | |
4061 | * | |
4062 | * @param p_hwfn | |
4063 | * @param p_ptt - ptt window used for writing the registers. | |
4064 | */ | |
4065 | void qed_enable_context_validation(struct qed_hwfn *p_hwfn, | |
4066 | struct qed_ptt *p_ptt); | |
4067 | ||
4068 | /** | |
4069 | * @brief qed_calc_session_ctx_validation - Calcualte validation byte for | |
4070 | * session context. | |
4071 | * | |
4072 | * @param p_ctx_mem - pointer to context memory. | |
4073 | * @param ctx_size - context size. | |
4074 | * @param ctx_type - context type. | |
4075 | * @param cid - context cid. | |
4076 | */ | |
4077 | void qed_calc_session_ctx_validation(void *p_ctx_mem, | |
4078 | u16 ctx_size, u8 ctx_type, u32 cid); | |
4079 | ||
4080 | /** | |
4081 | * @brief qed_calc_task_ctx_validation - Calcualte validation byte for task | |
4082 | * context. | |
4083 | * | |
4084 | * @param p_ctx_mem - pointer to context memory. | |
4085 | * @param ctx_size - context size. | |
4086 | * @param ctx_type - context type. | |
4087 | * @param tid - context tid. | |
4088 | */ | |
4089 | void qed_calc_task_ctx_validation(void *p_ctx_mem, | |
4090 | u16 ctx_size, u8 ctx_type, u32 tid); | |
4091 | ||
4092 | /** | |
4093 | * @brief qed_memset_session_ctx - Memset session context to 0 while | |
4094 | * preserving validation bytes. | |
4095 | * | |
4096 | * @param p_hwfn - | |
4097 | * @param p_ctx_mem - pointer to context memory. | |
4098 | * @param ctx_size - size to initialzie. | |
4099 | * @param ctx_type - context type. | |
4100 | */ | |
4101 | void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type); | |
4102 | ||
4103 | /** | |
4104 | * @brief qed_memset_task_ctx - Memset task context to 0 while preserving | |
4105 | * validation bytes. | |
4106 | * | |
4107 | * @param p_ctx_mem - pointer to context memory. | |
4108 | * @param ctx_size - size to initialzie. | |
4109 | * @param ctx_type - context type. | |
4110 | */ | |
4111 | void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type); | |
351a4ded | 4112 | |
a2e7699e TT |
4113 | /* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */ |
4114 | #define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base) | |
4115 | #define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size) | |
4116 | ||
4117 | /* Tstorm port statistics */ | |
4118 | #define TSTORM_PORT_STAT_OFFSET(port_id) \ | |
351a4ded | 4119 | (IRO[1].base + ((port_id) * IRO[1].m1)) |
a2e7699e TT |
4120 | #define TSTORM_PORT_STAT_SIZE (IRO[1].size) |
4121 | ||
4122 | /* Tstorm ll2 port statistics */ | |
05fafbfb YM |
4123 | #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \ |
4124 | (IRO[2].base + ((port_id) * IRO[2].m1)) | |
4125 | #define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size) | |
a2e7699e TT |
4126 | |
4127 | /* Ustorm VF-PF Channel ready flag */ | |
4128 | #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \ | |
351a4ded | 4129 | (IRO[3].base + ((vf_id) * IRO[3].m1)) |
a2e7699e TT |
4130 | #define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size) |
4131 | ||
4132 | /* Ustorm Final flr cleanup ack */ | |
4133 | #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \ | |
4134 | (IRO[4].base + ((pf_id) * IRO[4].m1)) | |
4135 | #define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size) | |
4136 | ||
4137 | /* Ustorm Event ring consumer */ | |
4138 | #define USTORM_EQE_CONS_OFFSET(pf_id) \ | |
351a4ded | 4139 | (IRO[5].base + ((pf_id) * IRO[5].m1)) |
a2e7699e TT |
4140 | #define USTORM_EQE_CONS_SIZE (IRO[5].size) |
4141 | ||
4142 | /* Ustorm eth queue zone */ | |
4143 | #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \ | |
351a4ded | 4144 | (IRO[6].base + ((queue_zone_id) * IRO[6].m1)) |
a2e7699e TT |
4145 | #define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size) |
4146 | ||
4147 | /* Ustorm Common Queue ring consumer */ | |
4148 | #define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \ | |
351a4ded | 4149 | (IRO[7].base + ((queue_zone_id) * IRO[7].m1)) |
a2e7699e TT |
4150 | #define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size) |
4151 | ||
da090917 TT |
4152 | /* Xstorm Integration Test Data */ |
4153 | #define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[8].base) | |
4154 | #define XSTORM_INTEG_TEST_DATA_SIZE (IRO[8].size) | |
4155 | ||
4156 | /* Ystorm Integration Test Data */ | |
4157 | #define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base) | |
4158 | #define YSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size) | |
4159 | ||
4160 | /* Pstorm Integration Test Data */ | |
4161 | #define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base) | |
4162 | #define PSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size) | |
4163 | ||
4164 | /* Tstorm Integration Test Data */ | |
4165 | #define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base) | |
4166 | #define TSTORM_INTEG_TEST_DATA_SIZE (IRO[11].size) | |
4167 | ||
4168 | /* Mstorm Integration Test Data */ | |
4169 | #define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base) | |
4170 | #define MSTORM_INTEG_TEST_DATA_SIZE (IRO[12].size) | |
4171 | ||
4172 | /* Ustorm Integration Test Data */ | |
4173 | #define USTORM_INTEG_TEST_DATA_OFFSET (IRO[13].base) | |
4174 | #define USTORM_INTEG_TEST_DATA_SIZE (IRO[13].size) | |
4175 | ||
a2e7699e | 4176 | /* Tstorm producers */ |
05fafbfb | 4177 | #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \ |
a2e7699e | 4178 | (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1)) |
05fafbfb | 4179 | #define TSTORM_LL2_RX_PRODS_SIZE (IRO[14].size) |
a2e7699e TT |
4180 | |
4181 | /* Tstorm LightL2 queue statistics */ | |
05fafbfb YM |
4182 | #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \ |
4183 | (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1)) | |
4184 | #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[15].size) | |
a2e7699e TT |
4185 | |
4186 | /* Ustorm LiteL2 queue statistics */ | |
05fafbfb | 4187 | #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \ |
a2e7699e | 4188 | (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1)) |
05fafbfb | 4189 | #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[16].size) |
a2e7699e TT |
4190 | |
4191 | /* Pstorm LiteL2 queue statistics */ | |
05fafbfb | 4192 | #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \ |
a2e7699e TT |
4193 | (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1)) |
4194 | #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[17].size) | |
4195 | ||
4196 | /* Mstorm queue statistics */ | |
4197 | #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \ | |
351a4ded | 4198 | (IRO[18].base + ((stat_counter_id) * IRO[18].m1)) |
a2e7699e TT |
4199 | #define MSTORM_QUEUE_STAT_SIZE (IRO[18].size) |
4200 | ||
4201 | /* Mstorm ETH PF queues producers */ | |
4202 | #define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \ | |
351a4ded | 4203 | (IRO[19].base + ((queue_id) * IRO[19].m1)) |
a2e7699e TT |
4204 | #define MSTORM_ETH_PF_PRODS_SIZE (IRO[19].size) |
4205 | ||
4206 | /* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size | |
4207 | * mode. | |
4208 | */ | |
05fafbfb | 4209 | #define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \ |
a2e7699e | 4210 | (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2)) |
05fafbfb | 4211 | #define MSTORM_ETH_VF_PRODS_SIZE (IRO[20].size) |
a2e7699e TT |
4212 | |
4213 | /* TPA agregation timeout in us resolution (on ASIC) */ | |
4214 | #define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[21].base) | |
4215 | #define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[21].size) | |
4216 | ||
4217 | /* Mstorm pf statistics */ | |
4218 | #define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \ | |
05fafbfb | 4219 | (IRO[22].base + ((pf_id) * IRO[22].m1)) |
a2e7699e TT |
4220 | #define MSTORM_ETH_PF_STAT_SIZE (IRO[22].size) |
4221 | ||
4222 | /* Ustorm queue statistics */ | |
4223 | #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \ | |
05fafbfb | 4224 | (IRO[23].base + ((stat_counter_id) * IRO[23].m1)) |
a2e7699e TT |
4225 | #define USTORM_QUEUE_STAT_SIZE (IRO[23].size) |
4226 | ||
4227 | /* Ustorm pf statistics */ | |
4228 | #define USTORM_ETH_PF_STAT_OFFSET(pf_id)\ | |
05fafbfb | 4229 | (IRO[24].base + ((pf_id) * IRO[24].m1)) |
a2e7699e TT |
4230 | #define USTORM_ETH_PF_STAT_SIZE (IRO[24].size) |
4231 | ||
4232 | /* Pstorm queue statistics */ | |
4233 | #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \ | |
05fafbfb | 4234 | (IRO[25].base + ((stat_counter_id) * IRO[25].m1)) |
a2e7699e TT |
4235 | #define PSTORM_QUEUE_STAT_SIZE (IRO[25].size) |
4236 | ||
4237 | /* Pstorm pf statistics */ | |
4238 | #define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \ | |
05fafbfb | 4239 | (IRO[26].base + ((pf_id) * IRO[26].m1)) |
a2e7699e TT |
4240 | #define PSTORM_ETH_PF_STAT_SIZE (IRO[26].size) |
4241 | ||
4242 | /* Control frame's EthType configuration for TX control frame security */ | |
4243 | #define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(eth_type_id) \ | |
4244 | (IRO[27].base + ((eth_type_id) * IRO[27].m1)) | |
4245 | #define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[27].size) | |
4246 | ||
4247 | /* Tstorm last parser message */ | |
4248 | #define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[28].base) | |
4249 | #define TSTORM_ETH_PRS_INPUT_SIZE (IRO[28].size) | |
4250 | ||
4251 | /* Tstorm Eth limit Rx rate */ | |
4252 | #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \ | |
05fafbfb | 4253 | (IRO[29].base + ((pf_id) * IRO[29].m1)) |
a2e7699e TT |
4254 | #define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size) |
4255 | ||
4256 | /* Xstorm queue zone */ | |
4257 | #define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \ | |
05fafbfb | 4258 | (IRO[30].base + ((queue_id) * IRO[30].m1)) |
a2e7699e TT |
4259 | #define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size) |
4260 | ||
da090917 TT |
4261 | /* Ystorm cqe producer */ |
4262 | #define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \ | |
4263 | (IRO[31].base + ((rss_id) * IRO[31].m1)) | |
4264 | #define YSTORM_TOE_CQ_PROD_SIZE (IRO[31].size) | |
4265 | ||
4266 | /* Ustorm cqe producer */ | |
4267 | #define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \ | |
4268 | (IRO[32].base + ((rss_id) * IRO[32].m1)) | |
4269 | #define USTORM_TOE_CQ_PROD_SIZE (IRO[32].size) | |
4270 | ||
4271 | /* Ustorm grq producer */ | |
4272 | #define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \ | |
4273 | (IRO[33].base + ((pf_id) * IRO[33].m1)) | |
4274 | #define USTORM_TOE_GRQ_PROD_SIZE (IRO[33].size) | |
4275 | ||
a2e7699e | 4276 | /* Tstorm cmdq-cons of given command queue-id */ |
05fafbfb | 4277 | #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \ |
a2e7699e TT |
4278 | (IRO[34].base + ((cmdq_queue_id) * IRO[34].m1)) |
4279 | #define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size) | |
4280 | ||
4281 | /* Tstorm (reflects M-Storm) bdq-external-producer of given function ID, | |
4282 | * BDqueue-id. | |
4283 | */ | |
05fafbfb | 4284 | #define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \ |
a2e7699e TT |
4285 | (IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2)) |
4286 | #define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size) | |
4287 | ||
4288 | /* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */ | |
05fafbfb | 4289 | #define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \ |
a2e7699e TT |
4290 | (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2)) |
4291 | #define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size) | |
4292 | ||
4293 | /* Tstorm iSCSI RX stats */ | |
05fafbfb | 4294 | #define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \ |
a2e7699e TT |
4295 | (IRO[37].base + ((pf_id) * IRO[37].m1)) |
4296 | #define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size) | |
4297 | ||
4298 | /* Mstorm iSCSI RX stats */ | |
05fafbfb | 4299 | #define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \ |
a2e7699e TT |
4300 | (IRO[38].base + ((pf_id) * IRO[38].m1)) |
4301 | #define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size) | |
4302 | ||
4303 | /* Ustorm iSCSI RX stats */ | |
05fafbfb | 4304 | #define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \ |
a2e7699e TT |
4305 | (IRO[39].base + ((pf_id) * IRO[39].m1)) |
4306 | #define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size) | |
4307 | ||
4308 | /* Xstorm iSCSI TX stats */ | |
05fafbfb | 4309 | #define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \ |
a2e7699e TT |
4310 | (IRO[40].base + ((pf_id) * IRO[40].m1)) |
4311 | #define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size) | |
4312 | ||
4313 | /* Ystorm iSCSI TX stats */ | |
05fafbfb | 4314 | #define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \ |
a2e7699e TT |
4315 | (IRO[41].base + ((pf_id) * IRO[41].m1)) |
4316 | #define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size) | |
4317 | ||
4318 | /* Pstorm iSCSI TX stats */ | |
05fafbfb | 4319 | #define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \ |
a2e7699e TT |
4320 | (IRO[42].base + ((pf_id) * IRO[42].m1)) |
4321 | #define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size) | |
4322 | ||
4323 | /* Tstorm FCoE RX stats */ | |
1e128c81 | 4324 | #define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \ |
a2e7699e | 4325 | (IRO[43].base + ((pf_id) * IRO[43].m1)) |
da090917 | 4326 | #define TSTORM_FCOE_RX_STATS_SIZE (IRO[43].size) |
a2e7699e TT |
4327 | |
4328 | /* Pstorm FCoE TX stats */ | |
1e128c81 AE |
4329 | #define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \ |
4330 | (IRO[44].base + ((pf_id) * IRO[44].m1)) | |
da090917 | 4331 | #define PSTORM_FCOE_TX_STATS_SIZE (IRO[44].size) |
05fafbfb | 4332 | |
a2e7699e TT |
4333 | /* Pstorm RDMA queue statistics */ |
4334 | #define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \ | |
4335 | (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1)) | |
4336 | #define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size) | |
4337 | ||
4338 | /* Tstorm RDMA queue statistics */ | |
4339 | #define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \ | |
4340 | (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1)) | |
4341 | #define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size) | |
4342 | ||
da090917 TT |
4343 | /* Xstorm iWARP rxmit stats */ |
4344 | #define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) \ | |
4345 | (IRO[47].base + ((pf_id) * IRO[47].m1)) | |
4346 | #define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[47].size) | |
4347 | ||
4348 | /* Tstorm RoCE Event Statistics */ | |
4349 | #define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) \ | |
4350 | (IRO[48].base + ((roce_pf_id) * IRO[48].m1)) | |
4351 | #define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[48].size) | |
4352 | ||
4353 | /* DCQCN Received Statistics */ | |
4354 | #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) \ | |
4355 | (IRO[49].base + ((roce_pf_id) * IRO[49].m1)) | |
4356 | #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE (IRO[49].size) | |
4357 | ||
4358 | /* DCQCN Sent Statistics */ | |
4359 | #define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) \ | |
4360 | (IRO[50].base + ((roce_pf_id) * IRO[50].m1)) | |
4361 | #define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE (IRO[50].size) | |
4362 | ||
4363 | static const struct iro iro_arr[51] = { | |
351a4ded | 4364 | {0x0, 0x0, 0x0, 0x0, 0x8}, |
da090917 TT |
4365 | {0x4cb8, 0x88, 0x0, 0x0, 0x88}, |
4366 | {0x6530, 0x20, 0x0, 0x0, 0x20}, | |
351a4ded YM |
4367 | {0xb00, 0x8, 0x0, 0x0, 0x4}, |
4368 | {0xa80, 0x8, 0x0, 0x0, 0x4}, | |
4369 | {0x0, 0x8, 0x0, 0x0, 0x2}, | |
4370 | {0x80, 0x8, 0x0, 0x0, 0x4}, | |
4371 | {0x84, 0x8, 0x0, 0x0, 0x2}, | |
da090917 | 4372 | {0x4c48, 0x0, 0x0, 0x0, 0x78}, |
50bc60cb MK |
4373 | {0x3e38, 0x0, 0x0, 0x0, 0x78}, |
4374 | {0x2b78, 0x0, 0x0, 0x0, 0x78}, | |
7b6859fb | 4375 | {0x4c40, 0x0, 0x0, 0x0, 0x78}, |
da090917 TT |
4376 | {0x4998, 0x0, 0x0, 0x0, 0x78}, |
4377 | {0x7f50, 0x0, 0x0, 0x0, 0x78}, | |
351a4ded | 4378 | {0xa28, 0x8, 0x0, 0x0, 0x8}, |
da090917 TT |
4379 | {0x6210, 0x10, 0x0, 0x0, 0x10}, |
4380 | {0xb820, 0x30, 0x0, 0x0, 0x30}, | |
4381 | {0x96c0, 0x30, 0x0, 0x0, 0x30}, | |
4382 | {0x4b68, 0x80, 0x0, 0x0, 0x40}, | |
351a4ded | 4383 | {0x1f8, 0x4, 0x0, 0x0, 0x4}, |
da090917 TT |
4384 | {0x53a8, 0x80, 0x4, 0x0, 0x4}, |
4385 | {0xc7d0, 0x0, 0x0, 0x0, 0x4}, | |
4386 | {0x4ba8, 0x80, 0x0, 0x0, 0x20}, | |
4387 | {0x8158, 0x40, 0x0, 0x0, 0x30}, | |
4388 | {0xe770, 0x60, 0x0, 0x0, 0x60}, | |
50bc60cb | 4389 | {0x2d10, 0x80, 0x0, 0x0, 0x38}, |
da090917 | 4390 | {0xf2b8, 0x78, 0x0, 0x0, 0x78}, |
351a4ded | 4391 | {0x1f8, 0x4, 0x0, 0x0, 0x4}, |
da090917 TT |
4392 | {0xaf20, 0x0, 0x0, 0x0, 0xf0}, |
4393 | {0xb010, 0x8, 0x0, 0x0, 0x8}, | |
351a4ded YM |
4394 | {0x1f8, 0x8, 0x0, 0x0, 0x8}, |
4395 | {0xac0, 0x8, 0x0, 0x0, 0x8}, | |
4396 | {0x2578, 0x8, 0x0, 0x0, 0x8}, | |
4397 | {0x24f8, 0x8, 0x0, 0x0, 0x8}, | |
4398 | {0x0, 0x8, 0x0, 0x0, 0x8}, | |
da090917 TT |
4399 | {0x400, 0x18, 0x8, 0x0, 0x8}, |
4400 | {0xb78, 0x18, 0x8, 0x0, 0x2}, | |
4401 | {0xd898, 0x50, 0x0, 0x0, 0x3c}, | |
4402 | {0x12908, 0x18, 0x0, 0x0, 0x10}, | |
4403 | {0x11aa8, 0x40, 0x0, 0x0, 0x18}, | |
4404 | {0xa588, 0x50, 0x0, 0x0, 0x20}, | |
4405 | {0x8700, 0x40, 0x0, 0x0, 0x28}, | |
4406 | {0x10300, 0x18, 0x0, 0x0, 0x10}, | |
4407 | {0xde48, 0x48, 0x0, 0x0, 0x38}, | |
4408 | {0x10768, 0x20, 0x0, 0x0, 0x20}, | |
50bc60cb | 4409 | {0x2d48, 0x80, 0x0, 0x0, 0x10}, |
da090917 TT |
4410 | {0x5048, 0x10, 0x0, 0x0, 0x10}, |
4411 | {0xc9b8, 0x30, 0x0, 0x0, 0x10}, | |
50bc60cb | 4412 | {0xed90, 0x10, 0x0, 0x0, 0x10}, |
da090917 TT |
4413 | {0xa3a0, 0x10, 0x0, 0x0, 0x10}, |
4414 | {0x13108, 0x8, 0x0, 0x0, 0x8}, | |
fe56b9e6 YM |
4415 | }; |
4416 | ||
4417 | /* Runtime array offsets */ | |
da090917 TT |
4418 | #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0 |
4419 | #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1 | |
4420 | #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2 | |
4421 | #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3 | |
4422 | #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4 | |
4423 | #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5 | |
4424 | #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6 | |
4425 | #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7 | |
4426 | #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8 | |
4427 | #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9 | |
4428 | #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10 | |
4429 | #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11 | |
4430 | #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12 | |
4431 | #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13 | |
4432 | #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14 | |
4433 | #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15 | |
4434 | #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16 | |
4435 | #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17 | |
4436 | #define DORQ_REG_GLB_MAX_ICID_0_RT_OFFSET 18 | |
4437 | #define DORQ_REG_GLB_MAX_ICID_1_RT_OFFSET 19 | |
4438 | #define DORQ_REG_GLB_RANGE2CONN_TYPE_0_RT_OFFSET 20 | |
4439 | #define DORQ_REG_GLB_RANGE2CONN_TYPE_1_RT_OFFSET 21 | |
4440 | #define DORQ_REG_PRV_PF_MAX_ICID_2_RT_OFFSET 22 | |
4441 | #define DORQ_REG_PRV_PF_MAX_ICID_3_RT_OFFSET 23 | |
4442 | #define DORQ_REG_PRV_PF_MAX_ICID_4_RT_OFFSET 24 | |
4443 | #define DORQ_REG_PRV_PF_MAX_ICID_5_RT_OFFSET 25 | |
4444 | #define DORQ_REG_PRV_VF_MAX_ICID_2_RT_OFFSET 26 | |
4445 | #define DORQ_REG_PRV_VF_MAX_ICID_3_RT_OFFSET 27 | |
4446 | #define DORQ_REG_PRV_VF_MAX_ICID_4_RT_OFFSET 28 | |
4447 | #define DORQ_REG_PRV_VF_MAX_ICID_5_RT_OFFSET 29 | |
4448 | #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_2_RT_OFFSET 30 | |
4449 | #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_3_RT_OFFSET 31 | |
4450 | #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_4_RT_OFFSET 32 | |
4451 | #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_5_RT_OFFSET 33 | |
4452 | #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_2_RT_OFFSET 34 | |
4453 | #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_3_RT_OFFSET 35 | |
4454 | #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_4_RT_OFFSET 36 | |
4455 | #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_5_RT_OFFSET 37 | |
4456 | #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 38 | |
4457 | #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 39 | |
4458 | #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 40 | |
4459 | #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 41 | |
4460 | #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 42 | |
4461 | #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 43 | |
4462 | #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 44 | |
4463 | #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 45 | |
4464 | #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 1024 | |
4465 | #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1069 | |
4466 | #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 1024 | |
4467 | #define CAU_REG_PI_MEMORY_RT_OFFSET 2093 | |
4468 | #define CAU_REG_PI_MEMORY_RT_SIZE 4416 | |
4469 | #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6509 | |
4470 | #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6510 | |
4471 | #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6511 | |
4472 | #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6512 | |
4473 | #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6513 | |
4474 | #define PRS_REG_SEARCH_TCP_RT_OFFSET 6514 | |
4475 | #define PRS_REG_SEARCH_FCOE_RT_OFFSET 6515 | |
4476 | #define PRS_REG_SEARCH_ROCE_RT_OFFSET 6516 | |
4477 | #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6517 | |
4478 | #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6518 | |
4479 | #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6519 | |
4480 | #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6520 | |
4481 | #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6521 | |
4482 | #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6522 | |
4483 | #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6523 | |
4484 | #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6524 | |
4485 | #define SRC_REG_FIRSTFREE_RT_OFFSET 6525 | |
4486 | #define SRC_REG_FIRSTFREE_RT_SIZE 2 | |
4487 | #define SRC_REG_LASTFREE_RT_OFFSET 6527 | |
4488 | #define SRC_REG_LASTFREE_RT_SIZE 2 | |
4489 | #define SRC_REG_COUNTFREE_RT_OFFSET 6529 | |
4490 | #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6530 | |
4491 | #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6531 | |
4492 | #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6532 | |
4493 | #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6533 | |
4494 | #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6534 | |
4495 | #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6535 | |
4496 | #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6536 | |
4497 | #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6537 | |
4498 | #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6538 | |
4499 | #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6539 | |
4500 | #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6540 | |
4501 | #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6541 | |
4502 | #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6542 | |
4503 | #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6543 | |
4504 | #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6544 | |
4505 | #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6545 | |
4506 | #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6546 | |
4507 | #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6547 | |
4508 | #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6548 | |
4509 | #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6549 | |
4510 | #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6550 | |
4511 | #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6551 | |
4512 | #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6552 | |
4513 | #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6553 | |
4514 | #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6554 | |
4515 | #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6555 | |
4516 | #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6556 | |
4517 | #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6557 | |
4518 | #define PSWRQ2_REG_VF_BASE_RT_OFFSET 6558 | |
4519 | #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6559 | |
4520 | #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6560 | |
4521 | #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6561 | |
4522 | #define PSWRQ2_REG_TGSRC_FIRST_ILT_RT_OFFSET 6562 | |
4523 | #define PSWRQ2_REG_RGSRC_FIRST_ILT_RT_OFFSET 6563 | |
4524 | #define PSWRQ2_REG_TGSRC_LAST_ILT_RT_OFFSET 6564 | |
4525 | #define PSWRQ2_REG_RGSRC_LAST_ILT_RT_OFFSET 6565 | |
4526 | #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6566 | |
4527 | #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 26414 | |
4528 | #define PGLUE_REG_B_VF_BASE_RT_OFFSET 32980 | |
4529 | #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 32981 | |
4530 | #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 32982 | |
4531 | #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 32983 | |
4532 | #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 32984 | |
4533 | #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 32985 | |
4534 | #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 32986 | |
4535 | #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 32987 | |
4536 | #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 32988 | |
4537 | #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 32989 | |
4538 | #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 32990 | |
4539 | #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 32991 | |
4540 | #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 32992 | |
4541 | #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416 | |
4542 | #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 33408 | |
4543 | #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 608 | |
4544 | #define QM_REG_MAXPQSIZE_0_RT_OFFSET 34016 | |
4545 | #define QM_REG_MAXPQSIZE_1_RT_OFFSET 34017 | |
4546 | #define QM_REG_MAXPQSIZE_2_RT_OFFSET 34018 | |
4547 | #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 34019 | |
4548 | #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 34020 | |
4549 | #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 34021 | |
4550 | #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 34022 | |
4551 | #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 34023 | |
4552 | #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 34024 | |
4553 | #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 34025 | |
4554 | #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 34026 | |
4555 | #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 34027 | |
4556 | #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 34028 | |
4557 | #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 34029 | |
4558 | #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 34030 | |
4559 | #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 34031 | |
4560 | #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 34032 | |
4561 | #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 34033 | |
4562 | #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 34034 | |
4563 | #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 34035 | |
4564 | #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 34036 | |
4565 | #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 34037 | |
4566 | #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 34038 | |
4567 | #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 34039 | |
4568 | #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 34040 | |
4569 | #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 34041 | |
4570 | #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 34042 | |
4571 | #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 34043 | |
4572 | #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 34044 | |
4573 | #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 34045 | |
4574 | #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 34046 | |
4575 | #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 34047 | |
4576 | #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 34048 | |
4577 | #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 34049 | |
4578 | #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 34050 | |
4579 | #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 34051 | |
4580 | #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 34052 | |
4581 | #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 34053 | |
4582 | #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 34054 | |
4583 | #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 34055 | |
4584 | #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 34056 | |
4585 | #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 34057 | |
4586 | #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 34058 | |
4587 | #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 34059 | |
4588 | #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 34060 | |
4589 | #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 34061 | |
4590 | #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 34062 | |
4591 | #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 34063 | |
4592 | #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 34064 | |
4593 | #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 34065 | |
4594 | #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 34066 | |
4595 | #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 34067 | |
4596 | #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 34068 | |
4597 | #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 34069 | |
4598 | #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 34070 | |
4599 | #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 34071 | |
4600 | #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 34072 | |
4601 | #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 34073 | |
4602 | #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 34074 | |
4603 | #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 34075 | |
4604 | #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 34076 | |
4605 | #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 34077 | |
4606 | #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 34078 | |
4607 | #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 34079 | |
4608 | #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 34080 | |
4609 | #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 34081 | |
4610 | #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 34082 | |
4611 | #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 34083 | |
4612 | #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128 | |
4613 | #define QM_REG_PTRTBLOTHER_RT_OFFSET 34211 | |
4614 | #define QM_REG_PTRTBLOTHER_RT_SIZE 256 | |
4615 | #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 34467 | |
4616 | #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 34468 | |
4617 | #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 34469 | |
4618 | #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 34470 | |
4619 | #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 34471 | |
4620 | #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 34472 | |
4621 | #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 34473 | |
4622 | #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 34474 | |
4623 | #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 34475 | |
4624 | #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 34476 | |
4625 | #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 34477 | |
4626 | #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 34478 | |
4627 | #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 34479 | |
4628 | #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 34480 | |
4629 | #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 34481 | |
4630 | #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 34482 | |
4631 | #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 34483 | |
4632 | #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 34484 | |
4633 | #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 34485 | |
4634 | #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 34486 | |
4635 | #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 34487 | |
4636 | #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 34488 | |
4637 | #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 34489 | |
4638 | #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 34490 | |
4639 | #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 34491 | |
4640 | #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 34492 | |
4641 | #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 34493 | |
4642 | #define QM_REG_PQTX2PF_0_RT_OFFSET 34494 | |
4643 | #define QM_REG_PQTX2PF_1_RT_OFFSET 34495 | |
4644 | #define QM_REG_PQTX2PF_2_RT_OFFSET 34496 | |
4645 | #define QM_REG_PQTX2PF_3_RT_OFFSET 34497 | |
4646 | #define QM_REG_PQTX2PF_4_RT_OFFSET 34498 | |
4647 | #define QM_REG_PQTX2PF_5_RT_OFFSET 34499 | |
4648 | #define QM_REG_PQTX2PF_6_RT_OFFSET 34500 | |
4649 | #define QM_REG_PQTX2PF_7_RT_OFFSET 34501 | |
4650 | #define QM_REG_PQTX2PF_8_RT_OFFSET 34502 | |
4651 | #define QM_REG_PQTX2PF_9_RT_OFFSET 34503 | |
4652 | #define QM_REG_PQTX2PF_10_RT_OFFSET 34504 | |
4653 | #define QM_REG_PQTX2PF_11_RT_OFFSET 34505 | |
4654 | #define QM_REG_PQTX2PF_12_RT_OFFSET 34506 | |
4655 | #define QM_REG_PQTX2PF_13_RT_OFFSET 34507 | |
4656 | #define QM_REG_PQTX2PF_14_RT_OFFSET 34508 | |
4657 | #define QM_REG_PQTX2PF_15_RT_OFFSET 34509 | |
4658 | #define QM_REG_PQTX2PF_16_RT_OFFSET 34510 | |
4659 | #define QM_REG_PQTX2PF_17_RT_OFFSET 34511 | |
4660 | #define QM_REG_PQTX2PF_18_RT_OFFSET 34512 | |
4661 | #define QM_REG_PQTX2PF_19_RT_OFFSET 34513 | |
4662 | #define QM_REG_PQTX2PF_20_RT_OFFSET 34514 | |
4663 | #define QM_REG_PQTX2PF_21_RT_OFFSET 34515 | |
4664 | #define QM_REG_PQTX2PF_22_RT_OFFSET 34516 | |
4665 | #define QM_REG_PQTX2PF_23_RT_OFFSET 34517 | |
4666 | #define QM_REG_PQTX2PF_24_RT_OFFSET 34518 | |
4667 | #define QM_REG_PQTX2PF_25_RT_OFFSET 34519 | |
4668 | #define QM_REG_PQTX2PF_26_RT_OFFSET 34520 | |
4669 | #define QM_REG_PQTX2PF_27_RT_OFFSET 34521 | |
4670 | #define QM_REG_PQTX2PF_28_RT_OFFSET 34522 | |
4671 | #define QM_REG_PQTX2PF_29_RT_OFFSET 34523 | |
4672 | #define QM_REG_PQTX2PF_30_RT_OFFSET 34524 | |
4673 | #define QM_REG_PQTX2PF_31_RT_OFFSET 34525 | |
4674 | #define QM_REG_PQTX2PF_32_RT_OFFSET 34526 | |
4675 | #define QM_REG_PQTX2PF_33_RT_OFFSET 34527 | |
4676 | #define QM_REG_PQTX2PF_34_RT_OFFSET 34528 | |
4677 | #define QM_REG_PQTX2PF_35_RT_OFFSET 34529 | |
4678 | #define QM_REG_PQTX2PF_36_RT_OFFSET 34530 | |
4679 | #define QM_REG_PQTX2PF_37_RT_OFFSET 34531 | |
4680 | #define QM_REG_PQTX2PF_38_RT_OFFSET 34532 | |
4681 | #define QM_REG_PQTX2PF_39_RT_OFFSET 34533 | |
4682 | #define QM_REG_PQTX2PF_40_RT_OFFSET 34534 | |
4683 | #define QM_REG_PQTX2PF_41_RT_OFFSET 34535 | |
4684 | #define QM_REG_PQTX2PF_42_RT_OFFSET 34536 | |
4685 | #define QM_REG_PQTX2PF_43_RT_OFFSET 34537 | |
4686 | #define QM_REG_PQTX2PF_44_RT_OFFSET 34538 | |
4687 | #define QM_REG_PQTX2PF_45_RT_OFFSET 34539 | |
4688 | #define QM_REG_PQTX2PF_46_RT_OFFSET 34540 | |
4689 | #define QM_REG_PQTX2PF_47_RT_OFFSET 34541 | |
4690 | #define QM_REG_PQTX2PF_48_RT_OFFSET 34542 | |
4691 | #define QM_REG_PQTX2PF_49_RT_OFFSET 34543 | |
4692 | #define QM_REG_PQTX2PF_50_RT_OFFSET 34544 | |
4693 | #define QM_REG_PQTX2PF_51_RT_OFFSET 34545 | |
4694 | #define QM_REG_PQTX2PF_52_RT_OFFSET 34546 | |
4695 | #define QM_REG_PQTX2PF_53_RT_OFFSET 34547 | |
4696 | #define QM_REG_PQTX2PF_54_RT_OFFSET 34548 | |
4697 | #define QM_REG_PQTX2PF_55_RT_OFFSET 34549 | |
4698 | #define QM_REG_PQTX2PF_56_RT_OFFSET 34550 | |
4699 | #define QM_REG_PQTX2PF_57_RT_OFFSET 34551 | |
4700 | #define QM_REG_PQTX2PF_58_RT_OFFSET 34552 | |
4701 | #define QM_REG_PQTX2PF_59_RT_OFFSET 34553 | |
4702 | #define QM_REG_PQTX2PF_60_RT_OFFSET 34554 | |
4703 | #define QM_REG_PQTX2PF_61_RT_OFFSET 34555 | |
4704 | #define QM_REG_PQTX2PF_62_RT_OFFSET 34556 | |
4705 | #define QM_REG_PQTX2PF_63_RT_OFFSET 34557 | |
4706 | #define QM_REG_PQOTHER2PF_0_RT_OFFSET 34558 | |
4707 | #define QM_REG_PQOTHER2PF_1_RT_OFFSET 34559 | |
4708 | #define QM_REG_PQOTHER2PF_2_RT_OFFSET 34560 | |
4709 | #define QM_REG_PQOTHER2PF_3_RT_OFFSET 34561 | |
4710 | #define QM_REG_PQOTHER2PF_4_RT_OFFSET 34562 | |
4711 | #define QM_REG_PQOTHER2PF_5_RT_OFFSET 34563 | |
4712 | #define QM_REG_PQOTHER2PF_6_RT_OFFSET 34564 | |
4713 | #define QM_REG_PQOTHER2PF_7_RT_OFFSET 34565 | |
4714 | #define QM_REG_PQOTHER2PF_8_RT_OFFSET 34566 | |
4715 | #define QM_REG_PQOTHER2PF_9_RT_OFFSET 34567 | |
4716 | #define QM_REG_PQOTHER2PF_10_RT_OFFSET 34568 | |
4717 | #define QM_REG_PQOTHER2PF_11_RT_OFFSET 34569 | |
4718 | #define QM_REG_PQOTHER2PF_12_RT_OFFSET 34570 | |
4719 | #define QM_REG_PQOTHER2PF_13_RT_OFFSET 34571 | |
4720 | #define QM_REG_PQOTHER2PF_14_RT_OFFSET 34572 | |
4721 | #define QM_REG_PQOTHER2PF_15_RT_OFFSET 34573 | |
4722 | #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 34574 | |
4723 | #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 34575 | |
4724 | #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 34576 | |
4725 | #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 34577 | |
4726 | #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 34578 | |
4727 | #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 34579 | |
4728 | #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 34580 | |
4729 | #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 34581 | |
4730 | #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 34582 | |
4731 | #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 34583 | |
4732 | #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 34584 | |
4733 | #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 34585 | |
4734 | #define QM_REG_RLGLBLINCVAL_RT_OFFSET 34586 | |
4735 | #define QM_REG_RLGLBLINCVAL_RT_SIZE 256 | |
4736 | #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 34842 | |
4737 | #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256 | |
4738 | #define QM_REG_RLGLBLCRD_RT_OFFSET 35098 | |
4739 | #define QM_REG_RLGLBLCRD_RT_SIZE 256 | |
4740 | #define QM_REG_RLGLBLENABLE_RT_OFFSET 35354 | |
4741 | #define QM_REG_RLPFPERIOD_RT_OFFSET 35355 | |
4742 | #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 35356 | |
4743 | #define QM_REG_RLPFINCVAL_RT_OFFSET 35357 | |
4744 | #define QM_REG_RLPFINCVAL_RT_SIZE 16 | |
4745 | #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 35373 | |
4746 | #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16 | |
4747 | #define QM_REG_RLPFCRD_RT_OFFSET 35389 | |
4748 | #define QM_REG_RLPFCRD_RT_SIZE 16 | |
4749 | #define QM_REG_RLPFENABLE_RT_OFFSET 35405 | |
4750 | #define QM_REG_RLPFVOQENABLE_RT_OFFSET 35406 | |
4751 | #define QM_REG_WFQPFWEIGHT_RT_OFFSET 35407 | |
4752 | #define QM_REG_WFQPFWEIGHT_RT_SIZE 16 | |
4753 | #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 35423 | |
4754 | #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16 | |
4755 | #define QM_REG_WFQPFCRD_RT_OFFSET 35439 | |
4756 | #define QM_REG_WFQPFCRD_RT_SIZE 256 | |
4757 | #define QM_REG_WFQPFENABLE_RT_OFFSET 35695 | |
4758 | #define QM_REG_WFQVPENABLE_RT_OFFSET 35696 | |
4759 | #define QM_REG_BASEADDRTXPQ_RT_OFFSET 35697 | |
4760 | #define QM_REG_BASEADDRTXPQ_RT_SIZE 512 | |
4761 | #define QM_REG_TXPQMAP_RT_OFFSET 36209 | |
4762 | #define QM_REG_TXPQMAP_RT_SIZE 512 | |
4763 | #define QM_REG_WFQVPWEIGHT_RT_OFFSET 36721 | |
4764 | #define QM_REG_WFQVPWEIGHT_RT_SIZE 512 | |
4765 | #define QM_REG_WFQVPCRD_RT_OFFSET 37233 | |
4766 | #define QM_REG_WFQVPCRD_RT_SIZE 512 | |
4767 | #define QM_REG_WFQVPMAP_RT_OFFSET 37745 | |
4768 | #define QM_REG_WFQVPMAP_RT_SIZE 512 | |
4769 | #define QM_REG_PTRTBLTX_RT_OFFSET 38257 | |
4770 | #define QM_REG_PTRTBLTX_RT_SIZE 1024 | |
4771 | #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 39281 | |
4772 | #define QM_REG_WFQPFCRD_MSB_RT_SIZE 320 | |
4773 | #define QM_REG_VOQCRDLINE_RT_OFFSET 39601 | |
4774 | #define QM_REG_VOQCRDLINE_RT_SIZE 36 | |
4775 | #define QM_REG_VOQINITCRDLINE_RT_OFFSET 39637 | |
4776 | #define QM_REG_VOQINITCRDLINE_RT_SIZE 36 | |
4777 | #define QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET 39673 | |
4778 | #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 39674 | |
4779 | #define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 39675 | |
4780 | #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 39676 | |
4781 | #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 39677 | |
4782 | #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 39678 | |
4783 | #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 39679 | |
4784 | #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 39680 | |
4785 | #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 39681 | |
4786 | #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4 | |
4787 | #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 39685 | |
4788 | #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4 | |
4789 | #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 39689 | |
4790 | #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32 | |
4791 | #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 39721 | |
4792 | #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16 | |
4793 | #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 39737 | |
4794 | #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16 | |
4795 | #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 39753 | |
4796 | #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16 | |
4797 | #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 39769 | |
4798 | #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16 | |
4799 | #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 39785 | |
4800 | #define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 39786 | |
4801 | #define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 39787 | |
4802 | #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8 | |
4803 | #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET 39795 | |
4804 | #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_SIZE 1024 | |
4805 | #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET 40819 | |
4806 | #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_SIZE 512 | |
4807 | #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET 41331 | |
4808 | #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_SIZE 512 | |
4809 | #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 41843 | |
4810 | #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 512 | |
4811 | #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET 42355 | |
4812 | #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_SIZE 512 | |
4813 | #define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET 42867 | |
4814 | #define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_SIZE 32 | |
4815 | #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 42899 | |
4816 | #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 42900 | |
4817 | #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 42901 | |
4818 | #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 42902 | |
4819 | #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 42903 | |
4820 | #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 42904 | |
4821 | #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 42905 | |
4822 | #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 42906 | |
4823 | #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 42907 | |
4824 | #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 42908 | |
4825 | #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 42909 | |
4826 | #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 42910 | |
4827 | #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 42911 | |
4828 | #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 42912 | |
4829 | #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 42913 | |
4830 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 42914 | |
4831 | #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 42915 | |
4832 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 42916 | |
4833 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 42917 | |
4834 | #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 42918 | |
4835 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 42919 | |
4836 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 42920 | |
4837 | #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 42921 | |
4838 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 42922 | |
4839 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 42923 | |
4840 | #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 42924 | |
4841 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 42925 | |
4842 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 42926 | |
4843 | #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 42927 | |
4844 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 42928 | |
4845 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 42929 | |
4846 | #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 42930 | |
4847 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 42931 | |
4848 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 42932 | |
4849 | #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 42933 | |
4850 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 42934 | |
4851 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 42935 | |
4852 | #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 42936 | |
4853 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 42937 | |
4854 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 42938 | |
4855 | #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 42939 | |
4856 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 42940 | |
4857 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 42941 | |
4858 | #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 42942 | |
4859 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 42943 | |
4860 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 42944 | |
4861 | #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 42945 | |
4862 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 42946 | |
4863 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 42947 | |
4864 | #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 42948 | |
4865 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 42949 | |
4866 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 42950 | |
4867 | #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 42951 | |
4868 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 42952 | |
4869 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 42953 | |
4870 | #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 42954 | |
4871 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 42955 | |
4872 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 42956 | |
4873 | #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 42957 | |
4874 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 42958 | |
4875 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 42959 | |
4876 | #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 42960 | |
4877 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 42961 | |
4878 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 42962 | |
4879 | #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 42963 | |
4880 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 42964 | |
4881 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 42965 | |
4882 | #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 42966 | |
4883 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 42967 | |
4884 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 42968 | |
4885 | #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 42969 | |
4886 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 42970 | |
4887 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 42971 | |
4888 | #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 42972 | |
4889 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 42973 | |
4890 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET 42974 | |
4891 | #define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET 42975 | |
4892 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET 42976 | |
4893 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET 42977 | |
4894 | #define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET 42978 | |
4895 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET 42979 | |
4896 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET 42980 | |
4897 | #define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET 42981 | |
4898 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET 42982 | |
4899 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET 42983 | |
4900 | #define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET 42984 | |
4901 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET 42985 | |
4902 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET 42986 | |
4903 | #define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET 42987 | |
4904 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET 42988 | |
4905 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET 42989 | |
4906 | #define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET 42990 | |
4907 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET 42991 | |
4908 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET 42992 | |
4909 | #define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET 42993 | |
4910 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET 42994 | |
4911 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET 42995 | |
4912 | #define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET 42996 | |
4913 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET 42997 | |
4914 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET 42998 | |
4915 | #define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET 42999 | |
4916 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET 43000 | |
4917 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET 43001 | |
4918 | #define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET 43002 | |
4919 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET 43003 | |
4920 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET 43004 | |
4921 | #define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET 43005 | |
4922 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET 43006 | |
4923 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET 43007 | |
4924 | #define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET 43008 | |
4925 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET 43009 | |
4926 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET 43010 | |
4927 | #define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET 43011 | |
4928 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET 43012 | |
4929 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET 43013 | |
4930 | #define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET 43014 | |
4931 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET 43015 | |
4932 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET 43016 | |
4933 | #define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET 43017 | |
4934 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET 43018 | |
4935 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET 43019 | |
4936 | #define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET 43020 | |
4937 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET 43021 | |
4938 | #define XCM_REG_CON_PHY_Q3_RT_OFFSET 43022 | |
4939 | ||
4940 | #define RUNTIME_ARRAY_SIZE 43023 | |
4941 | ||
4942 | /* Init Callbacks */ | |
4943 | #define DMAE_READY_CB 0 | |
fe56b9e6 | 4944 | |
fc48b7a6 YM |
4945 | /* The eth storm context for the Tstorm */ |
4946 | struct tstorm_eth_conn_st_ctx { | |
fe56b9e6 YM |
4947 | __le32 reserved[4]; |
4948 | }; | |
4949 | ||
4950 | /* The eth storm context for the Pstorm */ | |
4951 | struct pstorm_eth_conn_st_ctx { | |
4952 | __le32 reserved[8]; | |
4953 | }; | |
4954 | ||
4955 | /* The eth storm context for the Xstorm */ | |
4956 | struct xstorm_eth_conn_st_ctx { | |
4957 | __le32 reserved[60]; | |
4958 | }; | |
4959 | ||
21dd79e8 | 4960 | struct e4_xstorm_eth_conn_ag_ctx { |
351a4ded | 4961 | u8 reserved0; |
da090917 | 4962 | u8 state; |
351a4ded | 4963 | u8 flags0; |
21dd79e8 TT |
4964 | #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
4965 | #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
4966 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 | |
4967 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1 | |
4968 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 | |
4969 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2 | |
4970 | #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
4971 | #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
4972 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 | |
4973 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4 | |
4974 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 | |
4975 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5 | |
4976 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 | |
4977 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6 | |
4978 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 | |
4979 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7 | |
351a4ded | 4980 | u8 flags1; |
21dd79e8 TT |
4981 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 |
4982 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0 | |
4983 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 | |
4984 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1 | |
4985 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 | |
4986 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2 | |
4987 | #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 | |
4988 | #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3 | |
da090917 TT |
4989 | #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 |
4990 | #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 | |
4991 | #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 | |
4992 | #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 | |
21dd79e8 TT |
4993 | #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 |
4994 | #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 | |
4995 | #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 | |
4996 | #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 | |
fe56b9e6 | 4997 | u8 flags2; |
21dd79e8 TT |
4998 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 |
4999 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 | |
5000 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 | |
5001 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 | |
5002 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 | |
5003 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 | |
5004 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 | |
5005 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 | |
fe56b9e6 | 5006 | u8 flags3; |
21dd79e8 TT |
5007 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 |
5008 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 | |
5009 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 | |
5010 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 | |
5011 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 | |
5012 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 | |
5013 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 | |
5014 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 | |
351a4ded | 5015 | u8 flags4; |
21dd79e8 TT |
5016 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 |
5017 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 | |
5018 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 | |
5019 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 | |
5020 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 | |
5021 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 | |
5022 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 | |
5023 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 | |
fe56b9e6 | 5024 | u8 flags5; |
21dd79e8 TT |
5025 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 |
5026 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 | |
5027 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 | |
5028 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2 | |
5029 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 | |
5030 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4 | |
5031 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 | |
5032 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6 | |
fe56b9e6 | 5033 | u8 flags6; |
21dd79e8 TT |
5034 | #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 |
5035 | #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 | |
5036 | #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 | |
5037 | #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 | |
5038 | #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 | |
5039 | #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4 | |
5040 | #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 | |
5041 | #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 | |
fe56b9e6 | 5042 | u8 flags7; |
21dd79e8 TT |
5043 | #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 |
5044 | #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 | |
5045 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 | |
5046 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2 | |
5047 | #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 | |
5048 | #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
5049 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 | |
5050 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6 | |
5051 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 | |
5052 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7 | |
fe56b9e6 | 5053 | u8 flags8; |
21dd79e8 TT |
5054 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 |
5055 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0 | |
5056 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 | |
5057 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1 | |
5058 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 | |
5059 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2 | |
5060 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 | |
5061 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3 | |
5062 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 | |
5063 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4 | |
5064 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 | |
5065 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5 | |
5066 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 | |
5067 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6 | |
5068 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 | |
5069 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 | |
fe56b9e6 | 5070 | u8 flags9; |
21dd79e8 TT |
5071 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 |
5072 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 | |
5073 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 | |
5074 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 | |
5075 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 | |
5076 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 | |
5077 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 | |
5078 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 | |
5079 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 | |
5080 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 | |
5081 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 | |
5082 | #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 | |
5083 | #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 | |
5084 | #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 | |
5085 | #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 | |
5086 | #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 | |
fe56b9e6 | 5087 | u8 flags10; |
21dd79e8 TT |
5088 | #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 |
5089 | #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 | |
5090 | #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 | |
5091 | #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 | |
5092 | #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 | |
5093 | #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 | |
5094 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 | |
5095 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 | |
5096 | #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
5097 | #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
5098 | #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 | |
5099 | #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 | |
5100 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 | |
5101 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 | |
5102 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 | |
5103 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 | |
fe56b9e6 | 5104 | u8 flags11; |
21dd79e8 TT |
5105 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 |
5106 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 | |
5107 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 | |
5108 | #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1 | |
5109 | #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 | |
5110 | #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 | |
5111 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
5112 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
5113 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
5114 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
5115 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
5116 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5 | |
5117 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
5118 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
5119 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 | |
5120 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7 | |
fe56b9e6 | 5121 | u8 flags12; |
21dd79e8 TT |
5122 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 |
5123 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0 | |
5124 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 | |
5125 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1 | |
5126 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
5127 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
5128 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
5129 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
5130 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 | |
5131 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4 | |
5132 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
5133 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
5134 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 | |
5135 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6 | |
5136 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 | |
5137 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7 | |
fe56b9e6 | 5138 | u8 flags13; |
21dd79e8 TT |
5139 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 |
5140 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0 | |
5141 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 | |
5142 | #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1 | |
5143 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 | |
5144 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 | |
5145 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 | |
5146 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 | |
5147 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
5148 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
5149 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 | |
5150 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 | |
5151 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
5152 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
5153 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
5154 | #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
fe56b9e6 | 5155 | u8 flags14; |
21dd79e8 TT |
5156 | #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 |
5157 | #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 | |
5158 | #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 | |
5159 | #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 | |
5160 | #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 | |
5161 | #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 | |
5162 | #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 | |
5163 | #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 | |
5164 | #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 | |
5165 | #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 | |
5166 | #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 | |
5167 | #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 | |
5168 | #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 | |
5169 | #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 | |
351a4ded YM |
5170 | u8 edpm_event_id; |
5171 | __le16 physical_q0; | |
21dd79e8 | 5172 | __le16 e5_reserved1; |
351a4ded YM |
5173 | __le16 edpm_num_bds; |
5174 | __le16 tx_bd_cons; | |
5175 | __le16 tx_bd_prod; | |
50bc60cb | 5176 | __le16 updated_qm_pq_id; |
351a4ded YM |
5177 | __le16 conn_dpi; |
5178 | u8 byte3; | |
5179 | u8 byte4; | |
5180 | u8 byte5; | |
5181 | u8 byte6; | |
5182 | __le32 reg0; | |
5183 | __le32 reg1; | |
5184 | __le32 reg2; | |
5185 | __le32 reg3; | |
5186 | __le32 reg4; | |
5187 | __le32 reg5; | |
5188 | __le32 reg6; | |
5189 | __le16 word7; | |
5190 | __le16 word8; | |
5191 | __le16 word9; | |
5192 | __le16 word10; | |
5193 | __le32 reg7; | |
5194 | __le32 reg8; | |
5195 | __le32 reg9; | |
5196 | u8 byte7; | |
5197 | u8 byte8; | |
5198 | u8 byte9; | |
5199 | u8 byte10; | |
5200 | u8 byte11; | |
5201 | u8 byte12; | |
5202 | u8 byte13; | |
5203 | u8 byte14; | |
5204 | u8 byte15; | |
21dd79e8 | 5205 | u8 e5_reserved; |
351a4ded YM |
5206 | __le16 word11; |
5207 | __le32 reg10; | |
5208 | __le32 reg11; | |
5209 | __le32 reg12; | |
5210 | __le32 reg13; | |
5211 | __le32 reg14; | |
5212 | __le32 reg15; | |
5213 | __le32 reg16; | |
5214 | __le32 reg17; | |
5215 | __le32 reg18; | |
5216 | __le32 reg19; | |
5217 | __le16 word12; | |
5218 | __le16 word13; | |
5219 | __le16 word14; | |
5220 | __le16 word15; | |
fc48b7a6 YM |
5221 | }; |
5222 | ||
5223 | /* The eth storm context for the Ystorm */ | |
5224 | struct ystorm_eth_conn_st_ctx { | |
5225 | __le32 reserved[8]; | |
5226 | }; | |
5227 | ||
21dd79e8 | 5228 | struct e4_ystorm_eth_conn_ag_ctx { |
351a4ded YM |
5229 | u8 byte0; |
5230 | u8 state; | |
5231 | u8 flags0; | |
21dd79e8 TT |
5232 | #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 |
5233 | #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 | |
5234 | #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 | |
5235 | #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 | |
5236 | #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 | |
5237 | #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2 | |
5238 | #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 | |
5239 | #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4 | |
5240 | #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 | |
5241 | #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 | |
fc48b7a6 | 5242 | u8 flags1; |
21dd79e8 TT |
5243 | #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 |
5244 | #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0 | |
5245 | #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 | |
5246 | #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1 | |
5247 | #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 | |
5248 | #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 | |
5249 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
5250 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
5251 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
5252 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
5253 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
5254 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
5255 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
5256 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
5257 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
5258 | #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
351a4ded YM |
5259 | u8 tx_q0_int_coallecing_timeset; |
5260 | u8 byte3; | |
5261 | __le16 word0; | |
5262 | __le32 terminate_spqe; | |
5263 | __le32 reg1; | |
5264 | __le16 tx_bd_cons_upd; | |
5265 | __le16 word2; | |
5266 | __le16 word3; | |
5267 | __le16 word4; | |
5268 | __le32 reg2; | |
5269 | __le32 reg3; | |
fc48b7a6 YM |
5270 | }; |
5271 | ||
21dd79e8 | 5272 | struct e4_tstorm_eth_conn_ag_ctx { |
351a4ded YM |
5273 | u8 byte0; |
5274 | u8 byte1; | |
5275 | u8 flags0; | |
21dd79e8 TT |
5276 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 |
5277 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 | |
5278 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 | |
5279 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 | |
5280 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 | |
5281 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 | |
5282 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 | |
5283 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 | |
5284 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 | |
5285 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 | |
5286 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 | |
5287 | #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 | |
5288 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 | |
5289 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 | |
fc48b7a6 | 5290 | u8 flags1; |
21dd79e8 TT |
5291 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 |
5292 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 | |
5293 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 | |
5294 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 | |
5295 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 | |
5296 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 | |
5297 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 | |
5298 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 | |
fc48b7a6 | 5299 | u8 flags2; |
21dd79e8 TT |
5300 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 |
5301 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 | |
5302 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 | |
5303 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 | |
5304 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 | |
5305 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 | |
5306 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 | |
5307 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 | |
fc48b7a6 | 5308 | u8 flags3; |
21dd79e8 TT |
5309 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 |
5310 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 | |
5311 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 | |
5312 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 | |
5313 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 | |
5314 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 | |
5315 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 | |
5316 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 | |
5317 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 | |
5318 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 | |
5319 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 | |
5320 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 | |
fc48b7a6 | 5321 | u8 flags4; |
21dd79e8 TT |
5322 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 |
5323 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 | |
5324 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 | |
5325 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 | |
5326 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 | |
5327 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 | |
5328 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 | |
5329 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 | |
5330 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 | |
5331 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 | |
5332 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 | |
5333 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 | |
5334 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 | |
5335 | #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 | |
5336 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
5337 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
fc48b7a6 | 5338 | u8 flags5; |
21dd79e8 TT |
5339 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 |
5340 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
5341 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
5342 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
5343 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
5344 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
5345 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
5346 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
5347 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
5348 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
5349 | #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 | |
5350 | #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 | |
5351 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
5352 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
5353 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
5354 | #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
351a4ded YM |
5355 | __le32 reg0; |
5356 | __le32 reg1; | |
5357 | __le32 reg2; | |
5358 | __le32 reg3; | |
5359 | __le32 reg4; | |
5360 | __le32 reg5; | |
5361 | __le32 reg6; | |
5362 | __le32 reg7; | |
5363 | __le32 reg8; | |
5364 | u8 byte2; | |
5365 | u8 byte3; | |
5366 | __le16 rx_bd_cons; | |
5367 | u8 byte4; | |
5368 | u8 byte5; | |
5369 | __le16 rx_bd_prod; | |
5370 | __le16 word2; | |
5371 | __le16 word3; | |
5372 | __le32 reg9; | |
5373 | __le32 reg10; | |
fe56b9e6 YM |
5374 | }; |
5375 | ||
21dd79e8 | 5376 | struct e4_ustorm_eth_conn_ag_ctx { |
351a4ded YM |
5377 | u8 byte0; |
5378 | u8 byte1; | |
5379 | u8 flags0; | |
21dd79e8 TT |
5380 | #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 |
5381 | #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 | |
5382 | #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 | |
5383 | #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 | |
5384 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 | |
5385 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2 | |
5386 | #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 | |
5387 | #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4 | |
5388 | #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 | |
5389 | #define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 | |
fc48b7a6 | 5390 | u8 flags1; |
21dd79e8 TT |
5391 | #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 |
5392 | #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 | |
5393 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 | |
5394 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 | |
5395 | #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 | |
5396 | #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 | |
5397 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 | |
5398 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 | |
fc48b7a6 | 5399 | u8 flags2; |
21dd79e8 TT |
5400 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 |
5401 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 | |
5402 | #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 | |
5403 | #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1 | |
5404 | #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 | |
5405 | #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 | |
5406 | #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 | |
5407 | #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3 | |
5408 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 | |
5409 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4 | |
5410 | #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 | |
5411 | #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5 | |
5412 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 | |
5413 | #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6 | |
5414 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
5415 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
fc48b7a6 | 5416 | u8 flags3; |
21dd79e8 TT |
5417 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 |
5418 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
5419 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
5420 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
5421 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
5422 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
5423 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
5424 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
5425 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
5426 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
5427 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
5428 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
5429 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
5430 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
5431 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
5432 | #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
351a4ded YM |
5433 | u8 byte2; |
5434 | u8 byte3; | |
5435 | __le16 word0; | |
5436 | __le16 tx_bd_cons; | |
5437 | __le32 reg0; | |
5438 | __le32 reg1; | |
5439 | __le32 reg2; | |
5440 | __le32 tx_int_coallecing_timeset; | |
5441 | __le16 tx_drv_bd_cons; | |
5442 | __le16 rx_drv_cqe_cons; | |
fe56b9e6 YM |
5443 | }; |
5444 | ||
5445 | /* The eth storm context for the Ustorm */ | |
5446 | struct ustorm_eth_conn_st_ctx { | |
5447 | __le32 reserved[40]; | |
5448 | }; | |
5449 | ||
fc48b7a6 YM |
5450 | /* The eth storm context for the Mstorm */ |
5451 | struct mstorm_eth_conn_st_ctx { | |
5452 | __le32 reserved[8]; | |
5453 | }; | |
5454 | ||
fe56b9e6 | 5455 | /* eth connection context */ |
21dd79e8 | 5456 | struct e4_eth_conn_context { |
351a4ded YM |
5457 | struct tstorm_eth_conn_st_ctx tstorm_st_context; |
5458 | struct regpair tstorm_st_padding[2]; | |
5459 | struct pstorm_eth_conn_st_ctx pstorm_st_context; | |
5460 | struct xstorm_eth_conn_st_ctx xstorm_st_context; | |
21dd79e8 | 5461 | struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context; |
351a4ded | 5462 | struct ystorm_eth_conn_st_ctx ystorm_st_context; |
21dd79e8 TT |
5463 | struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context; |
5464 | struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context; | |
5465 | struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context; | |
351a4ded YM |
5466 | struct ustorm_eth_conn_st_ctx ustorm_st_context; |
5467 | struct mstorm_eth_conn_st_ctx mstorm_st_context; | |
fe56b9e6 YM |
5468 | }; |
5469 | ||
a2e7699e | 5470 | /* Ethernet filter types: mac/vlan/pair */ |
05fafbfb YM |
5471 | enum eth_error_code { |
5472 | ETH_OK = 0x00, | |
5473 | ETH_FILTERS_MAC_ADD_FAIL_FULL, | |
5474 | ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2, | |
5475 | ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2, | |
5476 | ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2, | |
5477 | ETH_FILTERS_MAC_DEL_FAIL_NOF, | |
5478 | ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2, | |
5479 | ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2, | |
5480 | ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC, | |
5481 | ETH_FILTERS_VLAN_ADD_FAIL_FULL, | |
5482 | ETH_FILTERS_VLAN_ADD_FAIL_DUP, | |
5483 | ETH_FILTERS_VLAN_DEL_FAIL_NOF, | |
5484 | ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1, | |
5485 | ETH_FILTERS_PAIR_ADD_FAIL_DUP, | |
5486 | ETH_FILTERS_PAIR_ADD_FAIL_FULL, | |
5487 | ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC, | |
5488 | ETH_FILTERS_PAIR_DEL_FAIL_NOF, | |
5489 | ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1, | |
5490 | ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC, | |
5491 | ETH_FILTERS_VNI_ADD_FAIL_FULL, | |
5492 | ETH_FILTERS_VNI_ADD_FAIL_DUP, | |
7b6859fb | 5493 | ETH_FILTERS_GFT_UPDATE_FAIL, |
05fafbfb YM |
5494 | MAX_ETH_ERROR_CODE |
5495 | }; | |
5496 | ||
a2e7699e | 5497 | /* Opcodes for the event ring */ |
351a4ded YM |
5498 | enum eth_event_opcode { |
5499 | ETH_EVENT_UNUSED, | |
5500 | ETH_EVENT_VPORT_START, | |
5501 | ETH_EVENT_VPORT_UPDATE, | |
5502 | ETH_EVENT_VPORT_STOP, | |
5503 | ETH_EVENT_TX_QUEUE_START, | |
5504 | ETH_EVENT_TX_QUEUE_STOP, | |
5505 | ETH_EVENT_RX_QUEUE_START, | |
5506 | ETH_EVENT_RX_QUEUE_UPDATE, | |
5507 | ETH_EVENT_RX_QUEUE_STOP, | |
5508 | ETH_EVENT_FILTERS_UPDATE, | |
da090917 TT |
5509 | ETH_EVENT_RX_ADD_OPENFLOW_FILTER, |
5510 | ETH_EVENT_RX_DELETE_OPENFLOW_FILTER, | |
5511 | ETH_EVENT_RX_CREATE_OPENFLOW_ACTION, | |
351a4ded YM |
5512 | ETH_EVENT_RX_ADD_UDP_FILTER, |
5513 | ETH_EVENT_RX_DELETE_UDP_FILTER, | |
da090917 TT |
5514 | ETH_EVENT_RX_CREATE_GFT_ACTION, |
5515 | ETH_EVENT_RX_GFT_UPDATE_FILTER, | |
5516 | ETH_EVENT_TX_QUEUE_UPDATE, | |
351a4ded YM |
5517 | MAX_ETH_EVENT_OPCODE |
5518 | }; | |
5519 | ||
5520 | /* Classify rule types in E2/E3 */ | |
cee4d264 | 5521 | enum eth_filter_action { |
351a4ded | 5522 | ETH_FILTER_ACTION_UNUSED, |
cee4d264 MC |
5523 | ETH_FILTER_ACTION_REMOVE, |
5524 | ETH_FILTER_ACTION_ADD, | |
fc48b7a6 | 5525 | ETH_FILTER_ACTION_REMOVE_ALL, |
cee4d264 MC |
5526 | MAX_ETH_FILTER_ACTION |
5527 | }; | |
5528 | ||
351a4ded | 5529 | /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */ |
cee4d264 | 5530 | struct eth_filter_cmd { |
351a4ded YM |
5531 | u8 type; |
5532 | u8 vport_id; | |
5533 | u8 action; | |
5534 | u8 reserved0; | |
5535 | __le32 vni; | |
5536 | __le16 mac_lsb; | |
5537 | __le16 mac_mid; | |
5538 | __le16 mac_msb; | |
5539 | __le16 vlan_id; | |
cee4d264 MC |
5540 | }; |
5541 | ||
351a4ded | 5542 | /* $$KEEP_ENDIANNESS$$ */ |
cee4d264 | 5543 | struct eth_filter_cmd_header { |
351a4ded YM |
5544 | u8 rx; |
5545 | u8 tx; | |
5546 | u8 cmd_cnt; | |
5547 | u8 assert_on_error; | |
5548 | u8 reserved1[4]; | |
cee4d264 MC |
5549 | }; |
5550 | ||
351a4ded | 5551 | /* Ethernet filter types: mac/vlan/pair */ |
cee4d264 | 5552 | enum eth_filter_type { |
351a4ded | 5553 | ETH_FILTER_TYPE_UNUSED, |
cee4d264 MC |
5554 | ETH_FILTER_TYPE_MAC, |
5555 | ETH_FILTER_TYPE_VLAN, | |
5556 | ETH_FILTER_TYPE_PAIR, | |
5557 | ETH_FILTER_TYPE_INNER_MAC, | |
5558 | ETH_FILTER_TYPE_INNER_VLAN, | |
5559 | ETH_FILTER_TYPE_INNER_PAIR, | |
5560 | ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR, | |
5561 | ETH_FILTER_TYPE_MAC_VNI_PAIR, | |
5562 | ETH_FILTER_TYPE_VNI, | |
5563 | MAX_ETH_FILTER_TYPE | |
5564 | }; | |
5565 | ||
a2e7699e | 5566 | /* Eth IPv4 Fragment Type */ |
05fafbfb YM |
5567 | enum eth_ipv4_frag_type { |
5568 | ETH_IPV4_NOT_FRAG, | |
5569 | ETH_IPV4_FIRST_FRAG, | |
5570 | ETH_IPV4_NON_FIRST_FRAG, | |
5571 | MAX_ETH_IPV4_FRAG_TYPE | |
5572 | }; | |
5573 | ||
a2e7699e | 5574 | /* eth IPv4 Fragment Type */ |
be086e7c MY |
5575 | enum eth_ip_type { |
5576 | ETH_IPV4, | |
5577 | ETH_IPV6, | |
5578 | MAX_ETH_IP_TYPE | |
5579 | }; | |
5580 | ||
a2e7699e | 5581 | /* Ethernet Ramrod Command IDs */ |
cee4d264 MC |
5582 | enum eth_ramrod_cmd_id { |
5583 | ETH_RAMROD_UNUSED, | |
351a4ded YM |
5584 | ETH_RAMROD_VPORT_START, |
5585 | ETH_RAMROD_VPORT_UPDATE, | |
5586 | ETH_RAMROD_VPORT_STOP, | |
5587 | ETH_RAMROD_RX_QUEUE_START, | |
5588 | ETH_RAMROD_RX_QUEUE_STOP, | |
5589 | ETH_RAMROD_TX_QUEUE_START, | |
5590 | ETH_RAMROD_TX_QUEUE_STOP, | |
5591 | ETH_RAMROD_FILTERS_UPDATE, | |
5592 | ETH_RAMROD_RX_QUEUE_UPDATE, | |
5593 | ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION, | |
5594 | ETH_RAMROD_RX_ADD_OPENFLOW_FILTER, | |
5595 | ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER, | |
5596 | ETH_RAMROD_RX_ADD_UDP_FILTER, | |
5597 | ETH_RAMROD_RX_DELETE_UDP_FILTER, | |
5598 | ETH_RAMROD_RX_CREATE_GFT_ACTION, | |
5599 | ETH_RAMROD_GFT_UPDATE_FILTER, | |
da090917 | 5600 | ETH_RAMROD_TX_QUEUE_UPDATE, |
cee4d264 MC |
5601 | MAX_ETH_RAMROD_CMD_ID |
5602 | }; | |
5603 | ||
a2e7699e | 5604 | /* Return code from eth sp ramrods */ |
351a4ded YM |
5605 | struct eth_return_code { |
5606 | u8 value; | |
5607 | #define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F | |
5608 | #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0 | |
5609 | #define ETH_RETURN_CODE_RESERVED_MASK 0x3 | |
5610 | #define ETH_RETURN_CODE_RESERVED_SHIFT 5 | |
5611 | #define ETH_RETURN_CODE_RX_TX_MASK 0x1 | |
5612 | #define ETH_RETURN_CODE_RX_TX_SHIFT 7 | |
5613 | }; | |
5614 | ||
5615 | /* What to do in case an error occurs */ | |
fc48b7a6 | 5616 | enum eth_tx_err { |
351a4ded | 5617 | ETH_TX_ERR_DROP, |
fc48b7a6 YM |
5618 | ETH_TX_ERR_ASSERT_MALICIOUS, |
5619 | MAX_ETH_TX_ERR | |
5620 | }; | |
5621 | ||
351a4ded | 5622 | /* Array of the different error type behaviors */ |
fc48b7a6 YM |
5623 | struct eth_tx_err_vals { |
5624 | __le16 values; | |
351a4ded YM |
5625 | #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1 |
5626 | #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0 | |
5627 | #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1 | |
5628 | #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1 | |
5629 | #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1 | |
5630 | #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2 | |
5631 | #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1 | |
5632 | #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3 | |
5633 | #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1 | |
5634 | #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4 | |
5635 | #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1 | |
5636 | #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5 | |
5637 | #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1 | |
5638 | #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6 | |
5639 | #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF | |
5640 | #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7 | |
5641 | }; | |
5642 | ||
5643 | /* vport rss configuration data */ | |
cee4d264 MC |
5644 | struct eth_vport_rss_config { |
5645 | __le16 capabilities; | |
351a4ded YM |
5646 | #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1 |
5647 | #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0 | |
5648 | #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1 | |
5649 | #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1 | |
5650 | #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1 | |
5651 | #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2 | |
5652 | #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1 | |
5653 | #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3 | |
5654 | #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1 | |
5655 | #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4 | |
5656 | #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1 | |
5657 | #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5 | |
5658 | #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1 | |
5659 | #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6 | |
5660 | #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF | |
5661 | #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7 | |
5662 | u8 rss_id; | |
5663 | u8 rss_mode; | |
5664 | u8 update_rss_key; | |
5665 | u8 update_rss_ind_table; | |
5666 | u8 update_rss_capabilities; | |
5667 | u8 tbl_size; | |
5668 | __le32 reserved2[2]; | |
5669 | __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM]; | |
5670 | ||
5671 | __le32 rss_key[ETH_RSS_KEY_SIZE_REGS]; | |
5672 | __le32 reserved3[2]; | |
5673 | }; | |
5674 | ||
5675 | /* eth vport RSS mode */ | |
cee4d264 MC |
5676 | enum eth_vport_rss_mode { |
5677 | ETH_VPORT_RSS_MODE_DISABLED, | |
5678 | ETH_VPORT_RSS_MODE_REGULAR, | |
5679 | MAX_ETH_VPORT_RSS_MODE | |
5680 | }; | |
5681 | ||
351a4ded | 5682 | /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */ |
cee4d264 MC |
5683 | struct eth_vport_rx_mode { |
5684 | __le16 state; | |
351a4ded YM |
5685 | #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1 |
5686 | #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0 | |
5687 | #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 | |
5688 | #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 | |
5689 | #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1 | |
5690 | #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2 | |
5691 | #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1 | |
5692 | #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3 | |
5693 | #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 | |
5694 | #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4 | |
5695 | #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 | |
5696 | #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5 | |
5697 | #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF | |
5698 | #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6 | |
cee4d264 MC |
5699 | }; |
5700 | ||
351a4ded | 5701 | /* Command for setting tpa parameters */ |
cee4d264 | 5702 | struct eth_vport_tpa_param { |
351a4ded YM |
5703 | u8 tpa_ipv4_en_flg; |
5704 | u8 tpa_ipv6_en_flg; | |
5705 | u8 tpa_ipv4_tunn_en_flg; | |
5706 | u8 tpa_ipv6_tunn_en_flg; | |
5707 | u8 tpa_pkt_split_flg; | |
5708 | u8 tpa_hdr_data_split_flg; | |
5709 | u8 tpa_gro_consistent_flg; | |
5710 | ||
5711 | u8 tpa_max_aggs_num; | |
5712 | ||
5713 | __le16 tpa_max_size; | |
5714 | __le16 tpa_min_size_to_start; | |
5715 | ||
5716 | __le16 tpa_min_size_to_cont; | |
5717 | u8 max_buff_num; | |
5718 | u8 reserved; | |
cee4d264 MC |
5719 | }; |
5720 | ||
351a4ded | 5721 | /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */ |
cee4d264 MC |
5722 | struct eth_vport_tx_mode { |
5723 | __le16 state; | |
351a4ded YM |
5724 | #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1 |
5725 | #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0 | |
5726 | #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 | |
5727 | #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 | |
5728 | #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1 | |
5729 | #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2 | |
5730 | #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 | |
5731 | #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3 | |
5732 | #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 | |
5733 | #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4 | |
5734 | #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF | |
5735 | #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5 | |
cee4d264 MC |
5736 | }; |
5737 | ||
a2e7699e | 5738 | /* GFT filter update action type */ |
d51e4af5 CM |
5739 | enum gft_filter_update_action { |
5740 | GFT_ADD_FILTER, | |
5741 | GFT_DELETE_FILTER, | |
5742 | MAX_GFT_FILTER_UPDATE_ACTION | |
5743 | }; | |
5744 | ||
a2e7699e | 5745 | /* Ramrod data for rx add openflow filter */ |
7b6859fb MY |
5746 | struct rx_add_openflow_filter_data { |
5747 | __le16 action_icid; | |
5748 | u8 priority; | |
5749 | u8 reserved0; | |
5750 | __le32 tenant_id; | |
5751 | __le16 dst_mac_hi; | |
5752 | __le16 dst_mac_mid; | |
5753 | __le16 dst_mac_lo; | |
5754 | __le16 src_mac_hi; | |
5755 | __le16 src_mac_mid; | |
5756 | __le16 src_mac_lo; | |
5757 | __le16 vlan_id; | |
5758 | __le16 l2_eth_type; | |
5759 | u8 ipv4_dscp; | |
5760 | u8 ipv4_frag_type; | |
5761 | u8 ipv4_over_ip; | |
5762 | u8 tenant_id_exists; | |
5763 | __le32 ipv4_dst_addr; | |
5764 | __le32 ipv4_src_addr; | |
5765 | __le16 l4_dst_port; | |
5766 | __le16 l4_src_port; | |
5767 | }; | |
5768 | ||
a2e7699e | 5769 | /* Ramrod data for rx create gft action */ |
7b6859fb MY |
5770 | struct rx_create_gft_action_data { |
5771 | u8 vport_id; | |
5772 | u8 reserved[7]; | |
5773 | }; | |
5774 | ||
a2e7699e | 5775 | /* Ramrod data for rx create openflow action */ |
7b6859fb MY |
5776 | struct rx_create_openflow_action_data { |
5777 | u8 vport_id; | |
5778 | u8 reserved[7]; | |
5779 | }; | |
5780 | ||
351a4ded | 5781 | /* Ramrod data for rx queue start ramrod */ |
cee4d264 | 5782 | struct rx_queue_start_ramrod_data { |
351a4ded YM |
5783 | __le16 rx_queue_id; |
5784 | __le16 num_of_pbl_pages; | |
5785 | __le16 bd_max_bytes; | |
5786 | __le16 sb_id; | |
5787 | u8 sb_index; | |
5788 | u8 vport_id; | |
5789 | u8 default_rss_queue_flg; | |
5790 | u8 complete_cqe_flg; | |
5791 | u8 complete_event_flg; | |
5792 | u8 stats_counter_id; | |
5793 | u8 pin_context; | |
5794 | u8 pxp_tph_valid_bd; | |
5795 | u8 pxp_tph_valid_pkt; | |
5796 | u8 pxp_st_hint; | |
5797 | ||
5798 | __le16 pxp_st_index; | |
5799 | u8 pmd_mode; | |
5800 | ||
5801 | u8 notify_en; | |
5802 | u8 toggle_val; | |
5803 | ||
5804 | u8 vf_rx_prod_index; | |
05fafbfb YM |
5805 | u8 vf_rx_prod_use_zone_a; |
5806 | u8 reserved[5]; | |
351a4ded YM |
5807 | __le16 reserved1; |
5808 | struct regpair cqe_pbl_addr; | |
5809 | struct regpair bd_base; | |
5810 | struct regpair reserved2; | |
cee4d264 MC |
5811 | }; |
5812 | ||
a2e7699e | 5813 | /* Ramrod data for rx queue stop ramrod */ |
cee4d264 | 5814 | struct rx_queue_stop_ramrod_data { |
351a4ded YM |
5815 | __le16 rx_queue_id; |
5816 | u8 complete_cqe_flg; | |
5817 | u8 complete_event_flg; | |
5818 | u8 vport_id; | |
5819 | u8 reserved[3]; | |
cee4d264 MC |
5820 | }; |
5821 | ||
351a4ded | 5822 | /* Ramrod data for rx queue update ramrod */ |
cee4d264 | 5823 | struct rx_queue_update_ramrod_data { |
351a4ded YM |
5824 | __le16 rx_queue_id; |
5825 | u8 complete_cqe_flg; | |
5826 | u8 complete_event_flg; | |
5827 | u8 vport_id; | |
50bc60cb MK |
5828 | u8 set_default_rss_queue; |
5829 | u8 reserved[3]; | |
351a4ded YM |
5830 | u8 reserved1; |
5831 | u8 reserved2; | |
5832 | u8 reserved3; | |
5833 | __le16 reserved4; | |
5834 | __le16 reserved5; | |
fc48b7a6 | 5835 | struct regpair reserved6; |
cee4d264 MC |
5836 | }; |
5837 | ||
351a4ded YM |
5838 | /* Ramrod data for rx Add UDP Filter */ |
5839 | struct rx_udp_filter_data { | |
5840 | __le16 action_icid; | |
5841 | __le16 vlan_id; | |
5842 | u8 ip_type; | |
5843 | u8 tenant_id_exists; | |
5844 | __le16 reserved1; | |
5845 | __le32 ip_dst_addr[4]; | |
5846 | __le32 ip_src_addr[4]; | |
5847 | __le16 udp_dst_port; | |
5848 | __le16 udp_src_port; | |
5849 | __le32 tenant_id; | |
cee4d264 MC |
5850 | }; |
5851 | ||
a2e7699e TT |
5852 | /* Add or delete GFT filter - filter is packet header of type of packet wished |
5853 | * to pass certain FW flow. | |
5854 | */ | |
d51e4af5 CM |
5855 | struct rx_update_gft_filter_data { |
5856 | struct regpair pkt_hdr_addr; | |
5857 | __le16 pkt_hdr_length; | |
da090917 TT |
5858 | __le16 action_icid; |
5859 | __le16 rx_qid; | |
5860 | __le16 flow_id; | |
5861 | __le16 vport_id; | |
5862 | u8 action_icid_valid; | |
5863 | u8 rx_qid_valid; | |
5864 | u8 flow_id_valid; | |
d51e4af5 | 5865 | u8 filter_action; |
7b6859fb | 5866 | u8 assert_on_error; |
50bc60cb | 5867 | u8 inner_vlan_removal_en; |
d51e4af5 CM |
5868 | }; |
5869 | ||
351a4ded YM |
5870 | /* Ramrod data for rx queue start ramrod */ |
5871 | struct tx_queue_start_ramrod_data { | |
5872 | __le16 sb_id; | |
5873 | u8 sb_index; | |
5874 | u8 vport_id; | |
5875 | u8 reserved0; | |
5876 | u8 stats_counter_id; | |
5877 | __le16 qm_pq_id; | |
5878 | u8 flags; | |
5879 | #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1 | |
5880 | #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0 | |
5881 | #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1 | |
5882 | #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1 | |
5883 | #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1 | |
5884 | #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2 | |
5885 | #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1 | |
5886 | #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3 | |
5887 | #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1 | |
5888 | #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4 | |
5889 | #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1 | |
5890 | #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5 | |
5891 | #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3 | |
5892 | #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6 | |
5893 | u8 pxp_st_hint; | |
5894 | u8 pxp_tph_valid_bd; | |
5895 | u8 pxp_tph_valid_pkt; | |
5896 | __le16 pxp_st_index; | |
5897 | __le16 comp_agg_size; | |
5898 | __le16 queue_zone_id; | |
05fafbfb | 5899 | __le16 reserved2; |
351a4ded YM |
5900 | __le16 pbl_size; |
5901 | __le16 tx_queue_id; | |
05fafbfb YM |
5902 | __le16 same_as_last_id; |
5903 | __le16 reserved[3]; | |
351a4ded YM |
5904 | struct regpair pbl_base_addr; |
5905 | struct regpair bd_cons_address; | |
5906 | }; | |
5907 | ||
5908 | /* Ramrod data for tx queue stop ramrod */ | |
cee4d264 MC |
5909 | struct tx_queue_stop_ramrod_data { |
5910 | __le16 reserved[4]; | |
5911 | }; | |
5912 | ||
da090917 TT |
5913 | /* Ramrod data for tx queue update ramrod */ |
5914 | struct tx_queue_update_ramrod_data { | |
5915 | __le16 update_qm_pq_id_flg; | |
5916 | __le16 qm_pq_id; | |
5917 | __le32 reserved0; | |
5918 | struct regpair reserved1[5]; | |
5919 | }; | |
5920 | ||
351a4ded | 5921 | /* Ramrod data for vport update ramrod */ |
cee4d264 | 5922 | struct vport_filter_update_ramrod_data { |
351a4ded YM |
5923 | struct eth_filter_cmd_header filter_cmd_hdr; |
5924 | struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT]; | |
cee4d264 MC |
5925 | }; |
5926 | ||
351a4ded | 5927 | /* Ramrod data for vport start ramrod */ |
cee4d264 | 5928 | struct vport_start_ramrod_data { |
351a4ded YM |
5929 | u8 vport_id; |
5930 | u8 sw_fid; | |
5931 | __le16 mtu; | |
5932 | u8 drop_ttl0_en; | |
5933 | u8 inner_vlan_removal_en; | |
5934 | struct eth_vport_rx_mode rx_mode; | |
5935 | struct eth_vport_tx_mode tx_mode; | |
5936 | struct eth_vport_tpa_param tpa_param; | |
5937 | __le16 default_vlan; | |
5938 | u8 tx_switching_en; | |
5939 | u8 anti_spoofing_en; | |
5940 | ||
5941 | u8 default_vlan_en; | |
5942 | ||
5943 | u8 handle_ptp_pkts; | |
5944 | u8 silent_vlan_removal_en; | |
5945 | u8 untagged; | |
5946 | struct eth_tx_err_vals tx_err_behav; | |
5947 | ||
5948 | u8 zero_placement_offset; | |
5949 | u8 ctl_frame_mac_check_en; | |
5950 | u8 ctl_frame_ethtype_check_en; | |
50bc60cb | 5951 | u8 reserved[1]; |
351a4ded YM |
5952 | }; |
5953 | ||
5954 | /* Ramrod data for vport stop ramrod */ | |
cee4d264 | 5955 | struct vport_stop_ramrod_data { |
351a4ded YM |
5956 | u8 vport_id; |
5957 | u8 reserved[7]; | |
cee4d264 MC |
5958 | }; |
5959 | ||
351a4ded | 5960 | /* Ramrod data for vport update ramrod */ |
cee4d264 | 5961 | struct vport_update_ramrod_data_cmn { |
351a4ded YM |
5962 | u8 vport_id; |
5963 | u8 update_rx_active_flg; | |
5964 | u8 rx_active_flg; | |
5965 | u8 update_tx_active_flg; | |
5966 | u8 tx_active_flg; | |
5967 | u8 update_rx_mode_flg; | |
5968 | u8 update_tx_mode_flg; | |
5969 | u8 update_approx_mcast_flg; | |
5970 | ||
5971 | u8 update_rss_flg; | |
5972 | u8 update_inner_vlan_removal_en_flg; | |
5973 | ||
5974 | u8 inner_vlan_removal_en; | |
5975 | u8 update_tpa_param_flg; | |
5976 | u8 update_tpa_en_flg; | |
5977 | u8 update_tx_switching_en_flg; | |
5978 | ||
5979 | u8 tx_switching_en; | |
5980 | u8 update_anti_spoofing_en_flg; | |
5981 | ||
5982 | u8 anti_spoofing_en; | |
5983 | u8 update_handle_ptp_pkts; | |
5984 | ||
5985 | u8 handle_ptp_pkts; | |
5986 | u8 update_default_vlan_en_flg; | |
5987 | ||
5988 | u8 default_vlan_en; | |
5989 | ||
5990 | u8 update_default_vlan_flg; | |
5991 | ||
5992 | __le16 default_vlan; | |
5993 | u8 update_accept_any_vlan_flg; | |
5994 | ||
5995 | u8 accept_any_vlan; | |
5996 | u8 silent_vlan_removal_en; | |
5997 | u8 update_mtu_flg; | |
5998 | ||
5999 | __le16 mtu; | |
be086e7c MY |
6000 | u8 update_ctl_frame_checks_en_flg; |
6001 | u8 ctl_frame_mac_check_en; | |
6002 | u8 ctl_frame_ethtype_check_en; | |
6003 | u8 reserved[15]; | |
cee4d264 MC |
6004 | }; |
6005 | ||
6006 | struct vport_update_ramrod_mcast { | |
6007 | __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; | |
6008 | }; | |
6009 | ||
351a4ded | 6010 | /* Ramrod data for vport update ramrod */ |
cee4d264 | 6011 | struct vport_update_ramrod_data { |
351a4ded YM |
6012 | struct vport_update_ramrod_data_cmn common; |
6013 | ||
6014 | struct eth_vport_rx_mode rx_mode; | |
6015 | struct eth_vport_tx_mode tx_mode; | |
50bc60cb | 6016 | __le32 reserved[3]; |
351a4ded YM |
6017 | struct eth_vport_tpa_param tpa_param; |
6018 | struct vport_update_ramrod_mcast approx_mcast; | |
6019 | struct eth_vport_rss_config rss_config; | |
cee4d264 MC |
6020 | }; |
6021 | ||
21dd79e8 | 6022 | struct e4_xstorm_eth_conn_ag_ctx_dq_ext_ldpart { |
be086e7c | 6023 | u8 reserved0; |
da090917 | 6024 | u8 state; |
be086e7c | 6025 | u8 flags0; |
21dd79e8 TT |
6026 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 |
6027 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 | |
6028 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 | |
6029 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 | |
6030 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 | |
6031 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 | |
6032 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 | |
6033 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 | |
6034 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 | |
6035 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 | |
6036 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 | |
6037 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 | |
6038 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 | |
6039 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 | |
6040 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 | |
6041 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 | |
be086e7c | 6042 | u8 flags1; |
21dd79e8 TT |
6043 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 |
6044 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 | |
6045 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 | |
6046 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 | |
6047 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1 | |
6048 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2 | |
6049 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 | |
6050 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 | |
da090917 TT |
6051 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK 0x1 |
6052 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_SHIFT 4 | |
6053 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK 0x1 | |
6054 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_SHIFT 5 | |
21dd79e8 TT |
6055 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1 |
6056 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6 | |
6057 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1 | |
6058 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7 | |
be086e7c | 6059 | u8 flags2; |
21dd79e8 TT |
6060 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3 |
6061 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0 | |
6062 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3 | |
6063 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2 | |
6064 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3 | |
6065 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4 | |
6066 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3 | |
6067 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6 | |
be086e7c | 6068 | u8 flags3; |
21dd79e8 TT |
6069 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3 |
6070 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0 | |
6071 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3 | |
6072 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2 | |
6073 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3 | |
6074 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4 | |
6075 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3 | |
6076 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6 | |
be086e7c | 6077 | u8 flags4; |
21dd79e8 TT |
6078 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3 |
6079 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0 | |
6080 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3 | |
6081 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2 | |
6082 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3 | |
6083 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4 | |
6084 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3 | |
6085 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6 | |
be086e7c | 6086 | u8 flags5; |
21dd79e8 TT |
6087 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3 |
6088 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0 | |
6089 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3 | |
6090 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2 | |
6091 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3 | |
6092 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4 | |
6093 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3 | |
6094 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6 | |
be086e7c | 6095 | u8 flags6; |
21dd79e8 TT |
6096 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3 |
6097 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0 | |
6098 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3 | |
6099 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2 | |
6100 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3 | |
6101 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4 | |
6102 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3 | |
6103 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6 | |
be086e7c | 6104 | u8 flags7; |
21dd79e8 TT |
6105 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3 |
6106 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0 | |
6107 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3 | |
6108 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2 | |
6109 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 | |
6110 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 | |
6111 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 | |
6112 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 | |
6113 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 | |
6114 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 | |
be086e7c | 6115 | u8 flags8; |
21dd79e8 TT |
6116 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 |
6117 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 | |
6118 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 | |
6119 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 | |
6120 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 | |
6121 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 | |
6122 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 | |
6123 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 | |
6124 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 | |
6125 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 | |
6126 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1 | |
6127 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5 | |
6128 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 | |
6129 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 | |
6130 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 | |
6131 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 | |
be086e7c | 6132 | u8 flags9; |
21dd79e8 TT |
6133 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 |
6134 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 | |
6135 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 | |
6136 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 | |
6137 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 | |
6138 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 | |
6139 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 | |
6140 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 | |
6141 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 | |
6142 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 | |
6143 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 | |
6144 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 | |
6145 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1 | |
6146 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6 | |
6147 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1 | |
6148 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7 | |
be086e7c | 6149 | u8 flags10; |
21dd79e8 TT |
6150 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1 |
6151 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0 | |
6152 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1 | |
6153 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1 | |
6154 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1 | |
6155 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2 | |
6156 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1 | |
6157 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3 | |
6158 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 | |
6159 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 | |
6160 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1 | |
6161 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5 | |
6162 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1 | |
6163 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6 | |
6164 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1 | |
6165 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7 | |
be086e7c | 6166 | u8 flags11; |
21dd79e8 TT |
6167 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1 |
6168 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0 | |
6169 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1 | |
6170 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1 | |
6171 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1 | |
6172 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2 | |
6173 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 | |
6174 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 | |
6175 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 | |
6176 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 | |
6177 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 | |
6178 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 | |
6179 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 | |
6180 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 | |
6181 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 | |
6182 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 | |
be086e7c | 6183 | u8 flags12; |
21dd79e8 TT |
6184 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 |
6185 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 | |
6186 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 | |
6187 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 | |
6188 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 | |
6189 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 | |
6190 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 | |
6191 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 | |
6192 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 | |
6193 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 | |
6194 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 | |
6195 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 | |
6196 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 | |
6197 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 | |
6198 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 | |
6199 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 | |
be086e7c | 6200 | u8 flags13; |
21dd79e8 TT |
6201 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 |
6202 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 | |
6203 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 | |
6204 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 | |
6205 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 | |
6206 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 | |
6207 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 | |
6208 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 | |
6209 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 | |
6210 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 | |
6211 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 | |
6212 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 | |
6213 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 | |
6214 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 | |
6215 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 | |
6216 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 | |
be086e7c | 6217 | u8 flags14; |
21dd79e8 TT |
6218 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1 |
6219 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0 | |
6220 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1 | |
6221 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1 | |
6222 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1 | |
6223 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2 | |
6224 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1 | |
6225 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3 | |
6226 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1 | |
6227 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4 | |
6228 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 | |
6229 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 | |
6230 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3 | |
6231 | #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6 | |
be086e7c MY |
6232 | u8 edpm_event_id; |
6233 | __le16 physical_q0; | |
21dd79e8 | 6234 | __le16 e5_reserved1; |
be086e7c MY |
6235 | __le16 edpm_num_bds; |
6236 | __le16 tx_bd_cons; | |
6237 | __le16 tx_bd_prod; | |
50bc60cb | 6238 | __le16 updated_qm_pq_id; |
be086e7c MY |
6239 | __le16 conn_dpi; |
6240 | u8 byte3; | |
6241 | u8 byte4; | |
6242 | u8 byte5; | |
6243 | u8 byte6; | |
6244 | __le32 reg0; | |
6245 | __le32 reg1; | |
6246 | __le32 reg2; | |
6247 | __le32 reg3; | |
6248 | __le32 reg4; | |
6249 | }; | |
6250 | ||
21dd79e8 | 6251 | struct e4_mstorm_eth_conn_ag_ctx { |
7b6859fb MY |
6252 | u8 byte0; |
6253 | u8 byte1; | |
6254 | u8 flags0; | |
21dd79e8 TT |
6255 | #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
6256 | #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
6257 | #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 | |
6258 | #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 | |
6259 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 | |
6260 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2 | |
6261 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 | |
6262 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4 | |
6263 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 | |
6264 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 | |
7b6859fb | 6265 | u8 flags1; |
21dd79e8 TT |
6266 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 |
6267 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0 | |
6268 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 | |
6269 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1 | |
6270 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 | |
6271 | #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 | |
6272 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
6273 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
6274 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
6275 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
6276 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
6277 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
6278 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
6279 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
6280 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
6281 | #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
7b6859fb MY |
6282 | __le16 word0; |
6283 | __le16 word1; | |
6284 | __le32 reg0; | |
6285 | __le32 reg1; | |
6286 | }; | |
6287 | ||
21dd79e8 | 6288 | struct e4_xstorm_eth_hw_conn_ag_ctx { |
be086e7c | 6289 | u8 reserved0; |
da090917 | 6290 | u8 state; |
be086e7c | 6291 | u8 flags0; |
21dd79e8 TT |
6292 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
6293 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
6294 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1 | |
6295 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1 | |
6296 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1 | |
6297 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2 | |
6298 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
6299 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
6300 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 | |
6301 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4 | |
6302 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1 | |
6303 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5 | |
6304 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 | |
6305 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6 | |
6306 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 | |
6307 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7 | |
be086e7c | 6308 | u8 flags1; |
21dd79e8 TT |
6309 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 |
6310 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0 | |
6311 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 | |
6312 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1 | |
6313 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 | |
6314 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2 | |
6315 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 | |
6316 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3 | |
da090917 TT |
6317 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 |
6318 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 | |
6319 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 | |
6320 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 | |
21dd79e8 TT |
6321 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 |
6322 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 | |
6323 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 | |
6324 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 | |
be086e7c | 6325 | u8 flags2; |
21dd79e8 TT |
6326 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3 |
6327 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0 | |
6328 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3 | |
6329 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2 | |
6330 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3 | |
6331 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4 | |
6332 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3 | |
6333 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6 | |
be086e7c | 6334 | u8 flags3; |
21dd79e8 TT |
6335 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 |
6336 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0 | |
6337 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 | |
6338 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2 | |
6339 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 | |
6340 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4 | |
6341 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 | |
6342 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6 | |
be086e7c | 6343 | u8 flags4; |
21dd79e8 TT |
6344 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 |
6345 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0 | |
6346 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 | |
6347 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2 | |
6348 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 | |
6349 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4 | |
6350 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 | |
6351 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6 | |
be086e7c | 6352 | u8 flags5; |
21dd79e8 TT |
6353 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 |
6354 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0 | |
6355 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 | |
6356 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2 | |
6357 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 | |
6358 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4 | |
6359 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 | |
6360 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6 | |
be086e7c | 6361 | u8 flags6; |
21dd79e8 TT |
6362 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 |
6363 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 | |
6364 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 | |
6365 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 | |
6366 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 | |
6367 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4 | |
6368 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 | |
6369 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 | |
be086e7c | 6370 | u8 flags7; |
21dd79e8 TT |
6371 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 |
6372 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 | |
6373 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 | |
6374 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2 | |
6375 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 | |
6376 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
6377 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 | |
6378 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6 | |
6379 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 | |
6380 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7 | |
be086e7c | 6381 | u8 flags8; |
21dd79e8 TT |
6382 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 |
6383 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0 | |
6384 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 | |
6385 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1 | |
6386 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 | |
6387 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2 | |
6388 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 | |
6389 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3 | |
6390 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 | |
6391 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4 | |
6392 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 | |
6393 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5 | |
6394 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 | |
6395 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6 | |
6396 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 | |
6397 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7 | |
be086e7c | 6398 | u8 flags9; |
21dd79e8 TT |
6399 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 |
6400 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0 | |
6401 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 | |
6402 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1 | |
6403 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 | |
6404 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2 | |
6405 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 | |
6406 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3 | |
6407 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 | |
6408 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4 | |
6409 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 | |
6410 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5 | |
6411 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 | |
6412 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 | |
6413 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 | |
6414 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 | |
be086e7c | 6415 | u8 flags10; |
21dd79e8 TT |
6416 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 |
6417 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 | |
6418 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 | |
6419 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 | |
6420 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 | |
6421 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 | |
6422 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 | |
6423 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3 | |
6424 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
6425 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
6426 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 | |
6427 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 | |
6428 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 | |
6429 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6 | |
6430 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 | |
6431 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7 | |
be086e7c | 6432 | u8 flags11; |
21dd79e8 TT |
6433 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 |
6434 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0 | |
6435 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 | |
6436 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1 | |
6437 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 | |
6438 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 | |
6439 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
6440 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
6441 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
6442 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
6443 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
6444 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5 | |
6445 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
6446 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
6447 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 | |
6448 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7 | |
be086e7c | 6449 | u8 flags12; |
21dd79e8 TT |
6450 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1 |
6451 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0 | |
6452 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1 | |
6453 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1 | |
6454 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
6455 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
6456 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
6457 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
6458 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1 | |
6459 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4 | |
6460 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
6461 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
6462 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1 | |
6463 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6 | |
6464 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1 | |
6465 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7 | |
be086e7c | 6466 | u8 flags13; |
21dd79e8 TT |
6467 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1 |
6468 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0 | |
6469 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1 | |
6470 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1 | |
6471 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 | |
6472 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 | |
6473 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 | |
6474 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 | |
6475 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
6476 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
6477 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 | |
6478 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 | |
6479 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
6480 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
6481 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
6482 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
be086e7c | 6483 | u8 flags14; |
21dd79e8 TT |
6484 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 |
6485 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 | |
6486 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 | |
6487 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 | |
6488 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 | |
6489 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 | |
6490 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 | |
6491 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 | |
6492 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 | |
6493 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 | |
6494 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 | |
6495 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 | |
6496 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 | |
6497 | #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 | |
be086e7c MY |
6498 | u8 edpm_event_id; |
6499 | __le16 physical_q0; | |
21dd79e8 | 6500 | __le16 e5_reserved1; |
be086e7c MY |
6501 | __le16 edpm_num_bds; |
6502 | __le16 tx_bd_cons; | |
6503 | __le16 tx_bd_prod; | |
50bc60cb | 6504 | __le16 updated_qm_pq_id; |
be086e7c MY |
6505 | __le16 conn_dpi; |
6506 | }; | |
6507 | ||
a2e7699e | 6508 | /* GFT CAM line struct */ |
7b6859fb MY |
6509 | struct gft_cam_line { |
6510 | __le32 camline; | |
6511 | #define GFT_CAM_LINE_VALID_MASK 0x1 | |
6512 | #define GFT_CAM_LINE_VALID_SHIFT 0 | |
6513 | #define GFT_CAM_LINE_DATA_MASK 0x3FFF | |
6514 | #define GFT_CAM_LINE_DATA_SHIFT 1 | |
6515 | #define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF | |
6516 | #define GFT_CAM_LINE_MASK_BITS_SHIFT 15 | |
6517 | #define GFT_CAM_LINE_RESERVED1_MASK 0x7 | |
6518 | #define GFT_CAM_LINE_RESERVED1_SHIFT 29 | |
7a9b6b8f YM |
6519 | }; |
6520 | ||
a2e7699e | 6521 | /* GFT CAM line struct with fields breakout */ |
7b6859fb MY |
6522 | struct gft_cam_line_mapped { |
6523 | __le32 camline; | |
6524 | #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1 | |
6525 | #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0 | |
6526 | #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1 | |
6527 | #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1 | |
6528 | #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1 | |
6529 | #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2 | |
6530 | #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF | |
6531 | #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3 | |
6532 | #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF | |
6533 | #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7 | |
6534 | #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF | |
6535 | #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11 | |
6536 | #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1 | |
6537 | #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15 | |
6538 | #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1 | |
6539 | #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16 | |
6540 | #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF | |
6541 | #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17 | |
6542 | #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF | |
6543 | #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21 | |
6544 | #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF | |
6545 | #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25 | |
6546 | #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7 | |
6547 | #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29 | |
6548 | }; | |
6549 | ||
6550 | union gft_cam_line_union { | |
6551 | struct gft_cam_line cam_line; | |
6552 | struct gft_cam_line_mapped cam_line_mapped; | |
6553 | }; | |
6554 | ||
a2e7699e | 6555 | /* Used in gft_profile_key: Indication for ip version */ |
7b6859fb MY |
6556 | enum gft_profile_ip_version { |
6557 | GFT_PROFILE_IPV4 = 0, | |
6558 | GFT_PROFILE_IPV6 = 1, | |
6559 | MAX_GFT_PROFILE_IP_VERSION | |
6560 | }; | |
6561 | ||
a2e7699e | 6562 | /* Profile key stucr fot GFT logic in Prs */ |
7b6859fb MY |
6563 | struct gft_profile_key { |
6564 | __le16 profile_key; | |
a2e7699e TT |
6565 | #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1 |
6566 | #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0 | |
6567 | #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1 | |
6568 | #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1 | |
6569 | #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF | |
6570 | #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2 | |
6571 | #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF | |
6572 | #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6 | |
6573 | #define GFT_PROFILE_KEY_PF_ID_MASK 0xF | |
6574 | #define GFT_PROFILE_KEY_PF_ID_SHIFT 10 | |
6575 | #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3 | |
6576 | #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14 | |
6577 | }; | |
6578 | ||
6579 | /* Used in gft_profile_key: Indication for tunnel type */ | |
7b6859fb MY |
6580 | enum gft_profile_tunnel_type { |
6581 | GFT_PROFILE_NO_TUNNEL = 0, | |
6582 | GFT_PROFILE_VXLAN_TUNNEL = 1, | |
6583 | GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2, | |
6584 | GFT_PROFILE_GRE_IP_TUNNEL = 3, | |
6585 | GFT_PROFILE_GENEVE_MAC_TUNNEL = 4, | |
6586 | GFT_PROFILE_GENEVE_IP_TUNNEL = 5, | |
6587 | MAX_GFT_PROFILE_TUNNEL_TYPE | |
6588 | }; | |
6589 | ||
a2e7699e | 6590 | /* Used in gft_profile_key: Indication for protocol type */ |
7b6859fb MY |
6591 | enum gft_profile_upper_protocol_type { |
6592 | GFT_PROFILE_ROCE_PROTOCOL = 0, | |
6593 | GFT_PROFILE_RROCE_PROTOCOL = 1, | |
6594 | GFT_PROFILE_FCOE_PROTOCOL = 2, | |
6595 | GFT_PROFILE_ICMP_PROTOCOL = 3, | |
6596 | GFT_PROFILE_ARP_PROTOCOL = 4, | |
6597 | GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5, | |
6598 | GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6, | |
6599 | GFT_PROFILE_TCP_PROTOCOL = 7, | |
6600 | GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8, | |
6601 | GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9, | |
6602 | GFT_PROFILE_UDP_PROTOCOL = 10, | |
6603 | GFT_PROFILE_USER_IP_1_INNER = 11, | |
6604 | GFT_PROFILE_USER_IP_2_OUTER = 12, | |
6605 | GFT_PROFILE_USER_ETH_1_INNER = 13, | |
6606 | GFT_PROFILE_USER_ETH_2_OUTER = 14, | |
6607 | GFT_PROFILE_RAW = 15, | |
6608 | MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE | |
6609 | }; | |
6610 | ||
a2e7699e | 6611 | /* GFT RAM line struct */ |
7b6859fb MY |
6612 | struct gft_ram_line { |
6613 | __le32 lo; | |
6614 | #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3 | |
6615 | #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0 | |
6616 | #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1 | |
6617 | #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2 | |
6618 | #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1 | |
6619 | #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3 | |
6620 | #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1 | |
6621 | #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4 | |
6622 | #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1 | |
6623 | #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5 | |
6624 | #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1 | |
6625 | #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6 | |
6626 | #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1 | |
6627 | #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7 | |
6628 | #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1 | |
6629 | #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8 | |
6630 | #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1 | |
6631 | #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9 | |
6632 | #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1 | |
6633 | #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10 | |
6634 | #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1 | |
6635 | #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11 | |
6636 | #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1 | |
6637 | #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12 | |
6638 | #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1 | |
6639 | #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13 | |
6640 | #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1 | |
6641 | #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14 | |
6642 | #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1 | |
6643 | #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15 | |
6644 | #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1 | |
6645 | #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16 | |
6646 | #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1 | |
6647 | #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17 | |
6648 | #define GFT_RAM_LINE_TTL_MASK 0x1 | |
6649 | #define GFT_RAM_LINE_TTL_SHIFT 18 | |
6650 | #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1 | |
6651 | #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19 | |
6652 | #define GFT_RAM_LINE_RESERVED0_MASK 0x1 | |
6653 | #define GFT_RAM_LINE_RESERVED0_SHIFT 20 | |
6654 | #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1 | |
6655 | #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21 | |
6656 | #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1 | |
6657 | #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22 | |
6658 | #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1 | |
6659 | #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23 | |
6660 | #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1 | |
6661 | #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24 | |
6662 | #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1 | |
6663 | #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25 | |
6664 | #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1 | |
6665 | #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26 | |
6666 | #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1 | |
6667 | #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27 | |
6668 | #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1 | |
6669 | #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28 | |
6670 | #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1 | |
6671 | #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29 | |
6672 | #define GFT_RAM_LINE_DST_PORT_MASK 0x1 | |
6673 | #define GFT_RAM_LINE_DST_PORT_SHIFT 30 | |
6674 | #define GFT_RAM_LINE_SRC_PORT_MASK 0x1 | |
6675 | #define GFT_RAM_LINE_SRC_PORT_SHIFT 31 | |
6676 | __le32 hi; | |
6677 | #define GFT_RAM_LINE_DSCP_MASK 0x1 | |
6678 | #define GFT_RAM_LINE_DSCP_SHIFT 0 | |
6679 | #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1 | |
6680 | #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1 | |
6681 | #define GFT_RAM_LINE_DST_IP_MASK 0x1 | |
6682 | #define GFT_RAM_LINE_DST_IP_SHIFT 2 | |
6683 | #define GFT_RAM_LINE_SRC_IP_MASK 0x1 | |
6684 | #define GFT_RAM_LINE_SRC_IP_SHIFT 3 | |
6685 | #define GFT_RAM_LINE_PRIORITY_MASK 0x1 | |
6686 | #define GFT_RAM_LINE_PRIORITY_SHIFT 4 | |
6687 | #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1 | |
6688 | #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5 | |
6689 | #define GFT_RAM_LINE_VLAN_MASK 0x1 | |
6690 | #define GFT_RAM_LINE_VLAN_SHIFT 6 | |
6691 | #define GFT_RAM_LINE_DST_MAC_MASK 0x1 | |
6692 | #define GFT_RAM_LINE_DST_MAC_SHIFT 7 | |
6693 | #define GFT_RAM_LINE_SRC_MAC_MASK 0x1 | |
6694 | #define GFT_RAM_LINE_SRC_MAC_SHIFT 8 | |
6695 | #define GFT_RAM_LINE_TENANT_ID_MASK 0x1 | |
6696 | #define GFT_RAM_LINE_TENANT_ID_SHIFT 9 | |
6697 | #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF | |
6698 | #define GFT_RAM_LINE_RESERVED1_SHIFT 10 | |
6699 | }; | |
6700 | ||
a2e7699e | 6701 | /* Used in the first 2 bits for gft_ram_line: Indication for vlan mask */ |
7b6859fb MY |
6702 | enum gft_vlan_select { |
6703 | INNER_PROVIDER_VLAN = 0, | |
6704 | INNER_VLAN = 1, | |
6705 | OUTER_PROVIDER_VLAN = 2, | |
6706 | OUTER_VLAN = 3, | |
6707 | MAX_GFT_VLAN_SELECT | |
6708 | }; | |
6709 | ||
a2e7699e TT |
6710 | /* The rdma task context of Mstorm */ |
6711 | struct ystorm_rdma_task_st_ctx { | |
6712 | struct regpair temp[4]; | |
6713 | }; | |
6714 | ||
21dd79e8 | 6715 | struct e4_ystorm_rdma_task_ag_ctx { |
a2e7699e TT |
6716 | u8 reserved; |
6717 | u8 byte1; | |
6718 | __le16 msem_ctx_upd_seq; | |
6719 | u8 flags0; | |
21dd79e8 TT |
6720 | #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF |
6721 | #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 | |
6722 | #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
6723 | #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 | |
6724 | #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 | |
6725 | #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 | |
6726 | #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 | |
6727 | #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6 | |
50bc60cb MK |
6728 | #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 |
6729 | #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7 | |
a2e7699e | 6730 | u8 flags1; |
21dd79e8 TT |
6731 | #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 |
6732 | #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 | |
6733 | #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 | |
6734 | #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 | |
6735 | #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 | |
6736 | #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 | |
6737 | #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 | |
6738 | #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 | |
6739 | #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 | |
6740 | #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 | |
a2e7699e | 6741 | u8 flags2; |
21dd79e8 TT |
6742 | #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 |
6743 | #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 | |
6744 | #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 | |
6745 | #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 | |
6746 | #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 | |
6747 | #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 | |
6748 | #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 | |
6749 | #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 | |
6750 | #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 | |
6751 | #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 | |
6752 | #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 | |
6753 | #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 | |
6754 | #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 | |
6755 | #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 | |
6756 | #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 | |
6757 | #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 | |
a2e7699e TT |
6758 | u8 key; |
6759 | __le32 mw_cnt; | |
6760 | u8 ref_cnt_seq; | |
6761 | u8 ctx_upd_seq; | |
6762 | __le16 dif_flags; | |
6763 | __le16 tx_ref_count; | |
6764 | __le16 last_used_ltid; | |
6765 | __le16 parent_mr_lo; | |
6766 | __le16 parent_mr_hi; | |
6767 | __le32 fbo_lo; | |
6768 | __le32 fbo_hi; | |
6769 | }; | |
6770 | ||
21dd79e8 | 6771 | struct e4_mstorm_rdma_task_ag_ctx { |
a2e7699e TT |
6772 | u8 reserved; |
6773 | u8 byte1; | |
6774 | __le16 icid; | |
6775 | u8 flags0; | |
21dd79e8 TT |
6776 | #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF |
6777 | #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 | |
6778 | #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
6779 | #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 | |
6780 | #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 | |
6781 | #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 | |
6782 | #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 | |
6783 | #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 | |
50bc60cb MK |
6784 | #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 |
6785 | #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7 | |
a2e7699e | 6786 | u8 flags1; |
21dd79e8 TT |
6787 | #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 |
6788 | #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 | |
6789 | #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 | |
6790 | #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 | |
6791 | #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 | |
6792 | #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4 | |
6793 | #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 | |
6794 | #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 | |
6795 | #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 | |
6796 | #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 | |
a2e7699e | 6797 | u8 flags2; |
21dd79e8 TT |
6798 | #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 |
6799 | #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0 | |
6800 | #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 | |
6801 | #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 | |
6802 | #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 | |
6803 | #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 | |
6804 | #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 | |
6805 | #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 | |
6806 | #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 | |
6807 | #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 | |
6808 | #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 | |
6809 | #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 | |
6810 | #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 | |
6811 | #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 | |
6812 | #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 | |
6813 | #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 | |
a2e7699e TT |
6814 | u8 key; |
6815 | __le32 mw_cnt; | |
6816 | u8 ref_cnt_seq; | |
6817 | u8 ctx_upd_seq; | |
6818 | __le16 dif_flags; | |
6819 | __le16 tx_ref_count; | |
6820 | __le16 last_used_ltid; | |
6821 | __le16 parent_mr_lo; | |
6822 | __le16 parent_mr_hi; | |
6823 | __le32 fbo_lo; | |
6824 | __le32 fbo_hi; | |
6825 | }; | |
6826 | ||
6827 | /* The roce task context of Mstorm */ | |
7b6859fb MY |
6828 | struct mstorm_rdma_task_st_ctx { |
6829 | struct regpair temp[4]; | |
6830 | }; | |
6831 | ||
a2e7699e TT |
6832 | /* The roce task context of Ustorm */ |
6833 | struct ustorm_rdma_task_st_ctx { | |
6834 | struct regpair temp[2]; | |
6835 | }; | |
6836 | ||
21dd79e8 | 6837 | struct e4_ustorm_rdma_task_ag_ctx { |
a2e7699e | 6838 | u8 reserved; |
50bc60cb | 6839 | u8 state; |
a2e7699e TT |
6840 | __le16 icid; |
6841 | u8 flags0; | |
21dd79e8 TT |
6842 | #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF |
6843 | #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 | |
6844 | #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
6845 | #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 | |
6846 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1 | |
6847 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5 | |
6848 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 | |
6849 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6 | |
a2e7699e | 6850 | u8 flags1; |
21dd79e8 TT |
6851 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 |
6852 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0 | |
6853 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 | |
6854 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2 | |
50bc60cb MK |
6855 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK 0x3 |
6856 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_SHIFT 4 | |
21dd79e8 TT |
6857 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 |
6858 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 | |
a2e7699e | 6859 | u8 flags2; |
21dd79e8 TT |
6860 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 |
6861 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0 | |
6862 | #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 | |
6863 | #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1 | |
6864 | #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 | |
6865 | #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2 | |
50bc60cb MK |
6866 | #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK 0x1 |
6867 | #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_SHIFT 3 | |
21dd79e8 TT |
6868 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 |
6869 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 | |
6870 | #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 | |
6871 | #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5 | |
6872 | #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 | |
6873 | #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6 | |
6874 | #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 | |
6875 | #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7 | |
a2e7699e | 6876 | u8 flags3; |
21dd79e8 TT |
6877 | #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 |
6878 | #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0 | |
6879 | #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 | |
6880 | #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1 | |
6881 | #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 | |
6882 | #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2 | |
6883 | #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 | |
6884 | #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3 | |
6885 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF | |
6886 | #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 | |
a2e7699e TT |
6887 | __le32 dif_err_intervals; |
6888 | __le32 dif_error_1st_interval; | |
50bc60cb | 6889 | __le32 sq_cons; |
a2e7699e | 6890 | __le32 dif_runt_value; |
50bc60cb | 6891 | __le32 sge_index; |
a2e7699e | 6892 | __le32 reg5; |
50bc60cb MK |
6893 | u8 byte2; |
6894 | u8 byte3; | |
6895 | __le16 word1; | |
6896 | __le16 word2; | |
6897 | __le16 word3; | |
6898 | __le32 reg6; | |
6899 | __le32 reg7; | |
a2e7699e TT |
6900 | }; |
6901 | ||
6902 | /* RDMA task context */ | |
21dd79e8 | 6903 | struct e4_rdma_task_context { |
a2e7699e | 6904 | struct ystorm_rdma_task_st_ctx ystorm_st_context; |
21dd79e8 | 6905 | struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context; |
a2e7699e | 6906 | struct tdif_task_context tdif_context; |
21dd79e8 | 6907 | struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context; |
a2e7699e TT |
6908 | struct mstorm_rdma_task_st_ctx mstorm_st_context; |
6909 | struct rdif_task_context rdif_context; | |
6910 | struct ustorm_rdma_task_st_ctx ustorm_st_context; | |
6911 | struct regpair ustorm_st_padding[2]; | |
21dd79e8 | 6912 | struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context; |
a2e7699e TT |
6913 | }; |
6914 | ||
6915 | /* rdma function init ramrod data */ | |
7b6859fb MY |
6916 | struct rdma_close_func_ramrod_data { |
6917 | u8 cnq_start_offset; | |
6918 | u8 num_cnqs; | |
6919 | u8 vf_id; | |
6920 | u8 vf_valid; | |
6921 | u8 reserved[4]; | |
6922 | }; | |
6923 | ||
a2e7699e | 6924 | /* rdma function init CNQ parameters */ |
7b6859fb MY |
6925 | struct rdma_cnq_params { |
6926 | __le16 sb_num; | |
6927 | u8 sb_index; | |
6928 | u8 num_pbl_pages; | |
6929 | __le32 reserved; | |
6930 | struct regpair pbl_base_addr; | |
6931 | __le16 queue_zone_num; | |
6932 | u8 reserved1[6]; | |
6933 | }; | |
6934 | ||
a2e7699e | 6935 | /* rdma create cq ramrod data */ |
7b6859fb MY |
6936 | struct rdma_create_cq_ramrod_data { |
6937 | struct regpair cq_handle; | |
6938 | struct regpair pbl_addr; | |
6939 | __le32 max_cqes; | |
7a9b6b8f YM |
6940 | __le16 pbl_num_pages; |
6941 | __le16 dpi; | |
6942 | u8 is_two_level_pbl; | |
6943 | u8 cnq_id; | |
6944 | u8 pbl_log_page_size; | |
6945 | u8 toggle_bit; | |
6946 | __le16 int_timeout; | |
6947 | __le16 reserved1; | |
6948 | }; | |
6949 | ||
a2e7699e | 6950 | /* rdma deregister tid ramrod data */ |
7a9b6b8f YM |
6951 | struct rdma_deregister_tid_ramrod_data { |
6952 | __le32 itid; | |
6953 | __le32 reserved; | |
6954 | }; | |
6955 | ||
a2e7699e | 6956 | /* rdma destroy cq output params */ |
7a9b6b8f YM |
6957 | struct rdma_destroy_cq_output_params { |
6958 | __le16 cnq_num; | |
6959 | __le16 reserved0; | |
6960 | __le32 reserved1; | |
6961 | }; | |
6962 | ||
a2e7699e | 6963 | /* rdma destroy cq ramrod data */ |
7a9b6b8f YM |
6964 | struct rdma_destroy_cq_ramrod_data { |
6965 | struct regpair output_params_addr; | |
6966 | }; | |
6967 | ||
a2e7699e | 6968 | /* RDMA slow path EQ cmd IDs */ |
7a9b6b8f YM |
6969 | enum rdma_event_opcode { |
6970 | RDMA_EVENT_UNUSED, | |
6971 | RDMA_EVENT_FUNC_INIT, | |
6972 | RDMA_EVENT_FUNC_CLOSE, | |
6973 | RDMA_EVENT_REGISTER_MR, | |
6974 | RDMA_EVENT_DEREGISTER_MR, | |
6975 | RDMA_EVENT_CREATE_CQ, | |
6976 | RDMA_EVENT_RESIZE_CQ, | |
6977 | RDMA_EVENT_DESTROY_CQ, | |
6978 | RDMA_EVENT_CREATE_SRQ, | |
6979 | RDMA_EVENT_MODIFY_SRQ, | |
6980 | RDMA_EVENT_DESTROY_SRQ, | |
6981 | MAX_RDMA_EVENT_OPCODE | |
6982 | }; | |
6983 | ||
a2e7699e | 6984 | /* RDMA FW return code for slow path ramrods */ |
7a9b6b8f YM |
6985 | enum rdma_fw_return_code { |
6986 | RDMA_RETURN_OK = 0, | |
6987 | RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR, | |
6988 | RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR, | |
6989 | RDMA_RETURN_RESIZE_CQ_ERR, | |
6990 | RDMA_RETURN_NIG_DRAIN_REQ, | |
6991 | MAX_RDMA_FW_RETURN_CODE | |
6992 | }; | |
6993 | ||
a2e7699e | 6994 | /* rdma function init header */ |
7a9b6b8f YM |
6995 | struct rdma_init_func_hdr { |
6996 | u8 cnq_start_offset; | |
6997 | u8 num_cnqs; | |
6998 | u8 cq_ring_mode; | |
7a9b6b8f YM |
6999 | u8 vf_id; |
7000 | u8 vf_valid; | |
da090917 | 7001 | u8 relaxed_ordering; |
50bc60cb MK |
7002 | __le16 first_reg_srq_id; |
7003 | __le32 reg_srq_base_addr; | |
7004 | __le32 reserved; | |
7a9b6b8f YM |
7005 | }; |
7006 | ||
a2e7699e | 7007 | /* rdma function init ramrod data */ |
7a9b6b8f YM |
7008 | struct rdma_init_func_ramrod_data { |
7009 | struct rdma_init_func_hdr params_header; | |
7010 | struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES]; | |
7011 | }; | |
7012 | ||
a2e7699e | 7013 | /* RDMA ramrod command IDs */ |
7a9b6b8f YM |
7014 | enum rdma_ramrod_cmd_id { |
7015 | RDMA_RAMROD_UNUSED, | |
7016 | RDMA_RAMROD_FUNC_INIT, | |
7017 | RDMA_RAMROD_FUNC_CLOSE, | |
7018 | RDMA_RAMROD_REGISTER_MR, | |
7019 | RDMA_RAMROD_DEREGISTER_MR, | |
7020 | RDMA_RAMROD_CREATE_CQ, | |
7021 | RDMA_RAMROD_RESIZE_CQ, | |
7022 | RDMA_RAMROD_DESTROY_CQ, | |
7023 | RDMA_RAMROD_CREATE_SRQ, | |
7024 | RDMA_RAMROD_MODIFY_SRQ, | |
7025 | RDMA_RAMROD_DESTROY_SRQ, | |
7026 | MAX_RDMA_RAMROD_CMD_ID | |
7027 | }; | |
7028 | ||
a2e7699e | 7029 | /* rdma register tid ramrod data */ |
7a9b6b8f | 7030 | struct rdma_register_tid_ramrod_data { |
7b6859fb MY |
7031 | __le16 flags; |
7032 | #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F | |
7033 | #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0 | |
7034 | #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1 | |
7035 | #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 5 | |
a2e7699e TT |
7036 | #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1 |
7037 | #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6 | |
7038 | #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1 | |
7039 | #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7 | |
7040 | #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1 | |
7041 | #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8 | |
7042 | #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1 | |
7b6859fb MY |
7043 | #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 9 |
7044 | #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1 | |
7045 | #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 10 | |
a2e7699e TT |
7046 | #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1 |
7047 | #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11 | |
7048 | #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1 | |
7049 | #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12 | |
7b6859fb MY |
7050 | #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1 |
7051 | #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 13 | |
a2e7699e TT |
7052 | #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3 |
7053 | #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14 | |
7a9b6b8f | 7054 | u8 flags1; |
7b6859fb | 7055 | #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F |
a2e7699e TT |
7056 | #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0 |
7057 | #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7 | |
7058 | #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5 | |
7a9b6b8f | 7059 | u8 flags2; |
a2e7699e TT |
7060 | #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1 |
7061 | #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0 | |
7b6859fb MY |
7062 | #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1 |
7063 | #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1 | |
a2e7699e TT |
7064 | #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F |
7065 | #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2 | |
7a9b6b8f YM |
7066 | u8 key; |
7067 | u8 length_hi; | |
7068 | u8 vf_id; | |
7069 | u8 vf_valid; | |
7070 | __le16 pd; | |
7b6859fb | 7071 | __le16 reserved2; |
7a9b6b8f YM |
7072 | __le32 length_lo; |
7073 | __le32 itid; | |
7b6859fb | 7074 | __le32 reserved3; |
7a9b6b8f YM |
7075 | struct regpair va; |
7076 | struct regpair pbl_base; | |
7077 | struct regpair dif_error_addr; | |
7078 | struct regpair dif_runt_addr; | |
7b6859fb | 7079 | __le32 reserved4[2]; |
7a9b6b8f YM |
7080 | }; |
7081 | ||
a2e7699e | 7082 | /* rdma resize cq output params */ |
7a9b6b8f YM |
7083 | struct rdma_resize_cq_output_params { |
7084 | __le32 old_cq_cons; | |
7085 | __le32 old_cq_prod; | |
7086 | }; | |
7087 | ||
a2e7699e | 7088 | /* rdma resize cq ramrod data */ |
7a9b6b8f YM |
7089 | struct rdma_resize_cq_ramrod_data { |
7090 | u8 flags; | |
a2e7699e TT |
7091 | #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1 |
7092 | #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0 | |
7093 | #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1 | |
7094 | #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1 | |
7095 | #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F | |
7096 | #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2 | |
7a9b6b8f YM |
7097 | u8 pbl_log_page_size; |
7098 | __le16 pbl_num_pages; | |
7099 | __le32 max_cqes; | |
7100 | struct regpair pbl_addr; | |
7101 | struct regpair output_params_addr; | |
7102 | }; | |
7103 | ||
a2e7699e | 7104 | /* The rdma storm context of Mstorm */ |
7a9b6b8f YM |
7105 | struct rdma_srq_context { |
7106 | struct regpair temp[8]; | |
7107 | }; | |
7108 | ||
a2e7699e | 7109 | /* rdma create qp requester ramrod data */ |
7a9b6b8f | 7110 | struct rdma_srq_create_ramrod_data { |
50bc60cb MK |
7111 | u8 flags; |
7112 | #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK 0x1 | |
7113 | #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT 0 | |
7114 | #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 | |
7115 | #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 1 | |
7116 | #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK 0x3F | |
7117 | #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT 2 | |
7118 | u8 reserved2; | |
7119 | __le16 xrc_domain; | |
7120 | __le32 xrc_srq_cq_cid; | |
7a9b6b8f YM |
7121 | struct regpair pbl_base_addr; |
7122 | __le16 pages_in_srq_pbl; | |
7123 | __le16 pd_id; | |
7124 | struct rdma_srq_id srq_id; | |
7125 | __le16 page_size; | |
50bc60cb MK |
7126 | __le16 reserved3; |
7127 | __le32 reserved4; | |
7a9b6b8f YM |
7128 | struct regpair producers_addr; |
7129 | }; | |
7130 | ||
a2e7699e | 7131 | /* rdma create qp requester ramrod data */ |
7a9b6b8f YM |
7132 | struct rdma_srq_destroy_ramrod_data { |
7133 | struct rdma_srq_id srq_id; | |
7134 | __le32 reserved; | |
7135 | }; | |
7136 | ||
a2e7699e | 7137 | /* rdma create qp requester ramrod data */ |
7a9b6b8f YM |
7138 | struct rdma_srq_modify_ramrod_data { |
7139 | struct rdma_srq_id srq_id; | |
7140 | __le32 wqe_limit; | |
7141 | }; | |
7142 | ||
a2e7699e | 7143 | /* RDMA Tid type enumeration (for register_tid ramrod) */ |
7a9b6b8f YM |
7144 | enum rdma_tid_type { |
7145 | RDMA_TID_REGISTERED_MR, | |
7146 | RDMA_TID_FMR, | |
7147 | RDMA_TID_MW_TYPE1, | |
7148 | RDMA_TID_MW_TYPE2A, | |
7149 | MAX_RDMA_TID_TYPE | |
7150 | }; | |
7151 | ||
50bc60cb MK |
7152 | struct rdma_xrc_srq_context { |
7153 | struct regpair temp[9]; | |
7154 | }; | |
7155 | ||
7156 | struct e4_tstorm_rdma_task_ag_ctx { | |
7157 | u8 byte0; | |
7158 | u8 byte1; | |
7159 | __le16 word0; | |
7160 | u8 flags0; | |
7161 | #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF | |
7162 | #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 | |
7163 | #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 | |
7164 | #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 | |
7165 | #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 | |
7166 | #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 | |
7167 | #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 | |
7168 | #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 | |
7169 | #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 | |
7170 | #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 | |
7171 | u8 flags1; | |
7172 | #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 | |
7173 | #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 | |
7174 | #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 | |
7175 | #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 | |
7176 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 | |
7177 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 | |
7178 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 | |
7179 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 | |
7180 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 | |
7181 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 | |
7182 | u8 flags2; | |
7183 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 | |
7184 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 | |
7185 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 | |
7186 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 | |
7187 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 | |
7188 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 | |
7189 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 | |
7190 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 | |
7191 | u8 flags3; | |
7192 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 | |
7193 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 | |
7194 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 | |
7195 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 | |
7196 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 | |
7197 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 | |
7198 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 | |
7199 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 | |
7200 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 | |
7201 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 | |
7202 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 | |
7203 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 | |
7204 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 | |
7205 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 | |
7206 | u8 flags4; | |
7207 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 | |
7208 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 | |
7209 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 | |
7210 | #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 | |
7211 | #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 | |
7212 | #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 | |
7213 | #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 | |
7214 | #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 | |
7215 | #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 | |
7216 | #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 | |
7217 | #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 | |
7218 | #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 | |
7219 | #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 | |
7220 | #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 | |
7221 | #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 | |
7222 | #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 | |
7223 | u8 byte2; | |
7224 | __le16 word1; | |
7225 | __le32 reg0; | |
7226 | u8 byte3; | |
7227 | u8 byte4; | |
7228 | __le16 word2; | |
7229 | __le16 word3; | |
7230 | __le16 word4; | |
7231 | __le32 reg1; | |
7232 | __le32 reg2; | |
7233 | }; | |
7234 | ||
7235 | struct e4_ustorm_rdma_conn_ag_ctx { | |
7236 | u8 reserved; | |
7237 | u8 byte1; | |
7238 | u8 flags0; | |
7239 | #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
7240 | #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
7241 | #define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK 0x1 | |
7242 | #define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_SHIFT 1 | |
7243 | #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 | |
7244 | #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 | |
7245 | #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 | |
7246 | #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 | |
7247 | #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 | |
7248 | #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 | |
7249 | u8 flags1; | |
7250 | #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 | |
7251 | #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 | |
7252 | #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 | |
7253 | #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 | |
7254 | #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 | |
7255 | #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 | |
7256 | #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 | |
7257 | #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 | |
7258 | u8 flags2; | |
7259 | #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 | |
7260 | #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 | |
7261 | #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 | |
7262 | #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 | |
7263 | #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 | |
7264 | #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 | |
7265 | #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 | |
7266 | #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 | |
7267 | #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 | |
7268 | #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 | |
7269 | #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 | |
7270 | #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 | |
7271 | #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 | |
7272 | #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 | |
7273 | #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 | |
7274 | #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 | |
7275 | u8 flags3; | |
7276 | #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 | |
7277 | #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 | |
7278 | #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
7279 | #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
7280 | #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
7281 | #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
7282 | #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
7283 | #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
7284 | #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
7285 | #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
7286 | #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
7287 | #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
7288 | #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
7289 | #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
7290 | #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
7291 | #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
7292 | u8 byte2; | |
7293 | u8 byte3; | |
7294 | __le16 conn_dpi; | |
7295 | __le16 word1; | |
7296 | __le32 cq_cons; | |
7297 | __le32 cq_se_prod; | |
7298 | __le32 cq_prod; | |
7299 | __le32 reg3; | |
7300 | __le16 int_timeout; | |
7301 | __le16 word3; | |
7302 | }; | |
7303 | ||
7304 | struct e4_xstorm_roce_conn_ag_ctx { | |
7a9b6b8f | 7305 | u8 reserved0; |
7b6859fb | 7306 | u8 state; |
7a9b6b8f | 7307 | u8 flags0; |
50bc60cb MK |
7308 | #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
7309 | #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
7310 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 | |
7311 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 | |
7312 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1 | |
7313 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT 2 | |
7314 | #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
7315 | #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
7316 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1 | |
7317 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT 4 | |
7318 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1 | |
7319 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT 5 | |
7320 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK 0x1 | |
7321 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_SHIFT 6 | |
7322 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK 0x1 | |
7323 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_SHIFT 7 | |
7a9b6b8f | 7324 | u8 flags1; |
50bc60cb MK |
7325 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK 0x1 |
7326 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_SHIFT 0 | |
7327 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK 0x1 | |
7328 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_SHIFT 1 | |
7329 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK 0x1 | |
7330 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_SHIFT 2 | |
7331 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK 0x1 | |
7332 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_SHIFT 3 | |
7333 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT12_MASK 0x1 | |
7334 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT12_SHIFT 4 | |
7335 | #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1 | |
7336 | #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5 | |
7337 | #define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1 | |
7338 | #define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_SHIFT 6 | |
7339 | #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 | |
7340 | #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 | |
7a9b6b8f | 7341 | u8 flags2; |
50bc60cb MK |
7342 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 |
7343 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 0 | |
7344 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3 | |
7345 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 2 | |
7346 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 | |
7347 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 4 | |
7348 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_MASK 0x3 | |
7349 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_SHIFT 6 | |
7a9b6b8f | 7350 | u8 flags3; |
50bc60cb MK |
7351 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_MASK 0x3 |
7352 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_SHIFT 0 | |
7353 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3 | |
7354 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 2 | |
7355 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3 | |
7356 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT 4 | |
7357 | #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 | |
7358 | #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 | |
7a9b6b8f | 7359 | u8 flags4; |
50bc60cb MK |
7360 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3 |
7361 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 0 | |
7362 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3 | |
7363 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 2 | |
7364 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3 | |
7365 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT 4 | |
7366 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_MASK 0x3 | |
7367 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_SHIFT 6 | |
7a9b6b8f | 7368 | u8 flags5; |
50bc60cb MK |
7369 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_MASK 0x3 |
7370 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_SHIFT 0 | |
7371 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_MASK 0x3 | |
7372 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_SHIFT 2 | |
7373 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_MASK 0x3 | |
7374 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_SHIFT 4 | |
7375 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_MASK 0x3 | |
7376 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_SHIFT 6 | |
7a9b6b8f | 7377 | u8 flags6; |
50bc60cb MK |
7378 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_MASK 0x3 |
7379 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_SHIFT 0 | |
7380 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_MASK 0x3 | |
7381 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_SHIFT 2 | |
7382 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_MASK 0x3 | |
7383 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_SHIFT 4 | |
7384 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_MASK 0x3 | |
7385 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_SHIFT 6 | |
7a9b6b8f | 7386 | u8 flags7; |
50bc60cb MK |
7387 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_MASK 0x3 |
7388 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_SHIFT 0 | |
7389 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_MASK 0x3 | |
7390 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_SHIFT 2 | |
7391 | #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 | |
7392 | #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
7393 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 | |
7394 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 6 | |
7395 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
7396 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 7 | |
7a9b6b8f | 7397 | u8 flags8; |
50bc60cb MK |
7398 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 |
7399 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 0 | |
7400 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK 0x1 | |
7401 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_SHIFT 1 | |
7402 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK 0x1 | |
7403 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_SHIFT 2 | |
7404 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1 | |
7405 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT 3 | |
7406 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1 | |
7407 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT 4 | |
7408 | #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 | |
7409 | #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 | |
7410 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1 | |
7411 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT 6 | |
7412 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1 | |
7413 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT 7 | |
7a9b6b8f | 7414 | u8 flags9; |
50bc60cb MK |
7415 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1 |
7416 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 0 | |
7417 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK 0x1 | |
7418 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_SHIFT 1 | |
7419 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK 0x1 | |
7420 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_SHIFT 2 | |
7421 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK 0x1 | |
7422 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_SHIFT 3 | |
7423 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK 0x1 | |
7424 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_SHIFT 4 | |
7425 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK 0x1 | |
7426 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_SHIFT 5 | |
7427 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK 0x1 | |
7428 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_SHIFT 6 | |
7429 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK 0x1 | |
7430 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_SHIFT 7 | |
7a9b6b8f | 7431 | u8 flags10; |
50bc60cb MK |
7432 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK 0x1 |
7433 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_SHIFT 0 | |
7434 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK 0x1 | |
7435 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_SHIFT 1 | |
7436 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK 0x1 | |
7437 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_SHIFT 2 | |
7438 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK 0x1 | |
7439 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_SHIFT 3 | |
7440 | #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
7441 | #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
7442 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK 0x1 | |
7443 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_SHIFT 5 | |
7444 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
7445 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 6 | |
7446 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
7447 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 7 | |
7a9b6b8f | 7448 | u8 flags11; |
50bc60cb MK |
7449 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 |
7450 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 0 | |
7451 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
7452 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 1 | |
7453 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
7454 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 2 | |
7455 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
7456 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
7457 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
7458 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
7459 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
7460 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 5 | |
7461 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
7462 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
7463 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK 0x1 | |
7464 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_SHIFT 7 | |
7a9b6b8f | 7465 | u8 flags12; |
50bc60cb MK |
7466 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK 0x1 |
7467 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_SHIFT 0 | |
7468 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK 0x1 | |
7469 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_SHIFT 1 | |
7470 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
7471 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
7472 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
7473 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
7474 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK 0x1 | |
7475 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_SHIFT 4 | |
7476 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
7477 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
7478 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK 0x1 | |
7479 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_SHIFT 6 | |
7480 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK 0x1 | |
7481 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_SHIFT 7 | |
7a9b6b8f | 7482 | u8 flags13; |
50bc60cb MK |
7483 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK 0x1 |
7484 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_SHIFT 0 | |
7485 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK 0x1 | |
7486 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_SHIFT 1 | |
7487 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 | |
7488 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 | |
7489 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 | |
7490 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 | |
7491 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
7492 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
7493 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 | |
7494 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 | |
7495 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
7496 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
7497 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
7498 | #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
7a9b6b8f | 7499 | u8 flags14; |
50bc60cb MK |
7500 | #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK 0x1 |
7501 | #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_SHIFT 0 | |
7502 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK 0x1 | |
7503 | #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_SHIFT 1 | |
7504 | #define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 | |
7505 | #define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 | |
7506 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK 0x1 | |
7507 | #define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_SHIFT 4 | |
7508 | #define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 | |
7509 | #define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 | |
7510 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_MASK 0x3 | |
7511 | #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_SHIFT 6 | |
7a9b6b8f | 7512 | u8 byte2; |
7b6859fb MY |
7513 | __le16 physical_q0; |
7514 | __le16 word1; | |
7515 | __le16 word2; | |
7516 | __le16 word3; | |
7517 | __le16 word4; | |
7518 | __le16 word5; | |
7519 | __le16 conn_dpi; | |
7520 | u8 byte3; | |
7521 | u8 byte4; | |
7522 | u8 byte5; | |
7523 | u8 byte6; | |
7524 | __le32 reg0; | |
7525 | __le32 reg1; | |
7526 | __le32 reg2; | |
7527 | __le32 snd_nxt_psn; | |
7528 | __le32 reg4; | |
50bc60cb MK |
7529 | __le32 reg5; |
7530 | __le32 reg6; | |
7b6859fb MY |
7531 | }; |
7532 | ||
50bc60cb | 7533 | struct e4_tstorm_roce_conn_ag_ctx { |
7b6859fb MY |
7534 | u8 reserved0; |
7535 | u8 byte1; | |
7536 | u8 flags0; | |
50bc60cb MK |
7537 | #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
7538 | #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
7539 | #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 | |
7540 | #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 | |
7541 | #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1 | |
7542 | #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT 2 | |
7543 | #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK 0x1 | |
7544 | #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_SHIFT 3 | |
7545 | #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1 | |
7546 | #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT 4 | |
7547 | #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1 | |
7548 | #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT 5 | |
7549 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 | |
7550 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 6 | |
7b6859fb | 7551 | u8 flags1; |
50bc60cb MK |
7552 | #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 |
7553 | #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 | |
7554 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 | |
7555 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 2 | |
7556 | #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 | |
7557 | #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 | |
7558 | #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 | |
7559 | #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 | |
7b6859fb | 7560 | u8 flags2; |
50bc60cb MK |
7561 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3 |
7562 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 0 | |
7563 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3 | |
7564 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT 2 | |
7565 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_MASK 0x3 | |
7566 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_SHIFT 4 | |
7567 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3 | |
7568 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 6 | |
7b6859fb | 7569 | u8 flags3; |
50bc60cb MK |
7570 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3 |
7571 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 0 | |
7572 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3 | |
7573 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT 2 | |
7574 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 | |
7575 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 4 | |
7576 | #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 | |
7577 | #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5 | |
7578 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 | |
7579 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 6 | |
7580 | #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 | |
7581 | #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 | |
7b6859fb | 7582 | u8 flags4; |
50bc60cb MK |
7583 | #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 |
7584 | #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 | |
7585 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1 | |
7586 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT 1 | |
7587 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1 | |
7588 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT 2 | |
7589 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK 0x1 | |
7590 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_SHIFT 3 | |
7591 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1 | |
7592 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT 4 | |
7593 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1 | |
7594 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT 5 | |
7595 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1 | |
7596 | #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 6 | |
7597 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
7598 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
7b6859fb | 7599 | u8 flags5; |
50bc60cb MK |
7600 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 |
7601 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
7602 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
7603 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
7604 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
7605 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
7606 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
7607 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
7608 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
7609 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
7610 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
7611 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
7612 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
7613 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
7614 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
7615 | #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
7b6859fb MY |
7616 | __le32 reg0; |
7617 | __le32 reg1; | |
7618 | __le32 reg2; | |
7619 | __le32 reg3; | |
7620 | __le32 reg4; | |
7621 | __le32 reg5; | |
7622 | __le32 reg6; | |
7623 | __le32 reg7; | |
7624 | __le32 reg8; | |
7625 | u8 byte2; | |
7626 | u8 byte3; | |
7627 | __le16 word0; | |
7628 | u8 byte4; | |
7629 | u8 byte5; | |
7630 | __le16 word1; | |
7631 | __le16 word2; | |
7632 | __le16 word3; | |
7633 | __le32 reg9; | |
7634 | __le32 reg10; | |
7635 | }; | |
7636 | ||
a2e7699e TT |
7637 | /* The roce storm context of Ystorm */ |
7638 | struct ystorm_roce_conn_st_ctx { | |
7639 | struct regpair temp[2]; | |
7a9b6b8f YM |
7640 | }; |
7641 | ||
a2e7699e | 7642 | /* The roce storm context of Mstorm */ |
7a9b6b8f YM |
7643 | struct pstorm_roce_conn_st_ctx { |
7644 | struct regpair temp[16]; | |
7645 | }; | |
7646 | ||
a2e7699e | 7647 | /* The roce storm context of Xstorm */ |
7a9b6b8f | 7648 | struct xstorm_roce_conn_st_ctx { |
be086e7c | 7649 | struct regpair temp[24]; |
7a9b6b8f YM |
7650 | }; |
7651 | ||
a2e7699e | 7652 | /* The roce storm context of Tstorm */ |
7a9b6b8f YM |
7653 | struct tstorm_roce_conn_st_ctx { |
7654 | struct regpair temp[30]; | |
7655 | }; | |
7656 | ||
a2e7699e TT |
7657 | /* The roce storm context of Mstorm */ |
7658 | struct mstorm_roce_conn_st_ctx { | |
7659 | struct regpair temp[6]; | |
7660 | }; | |
7661 | ||
7662 | /* The roce storm context of Ystorm */ | |
7a9b6b8f YM |
7663 | struct ustorm_roce_conn_st_ctx { |
7664 | struct regpair temp[12]; | |
7665 | }; | |
7666 | ||
a2e7699e | 7667 | /* roce connection context */ |
21dd79e8 | 7668 | struct e4_roce_conn_context { |
7a9b6b8f YM |
7669 | struct ystorm_roce_conn_st_ctx ystorm_st_context; |
7670 | struct regpair ystorm_st_padding[2]; | |
7671 | struct pstorm_roce_conn_st_ctx pstorm_st_context; | |
7672 | struct xstorm_roce_conn_st_ctx xstorm_st_context; | |
50bc60cb MK |
7673 | struct e4_xstorm_roce_conn_ag_ctx xstorm_ag_context; |
7674 | struct e4_tstorm_roce_conn_ag_ctx tstorm_ag_context; | |
7a9b6b8f | 7675 | struct timers_context timer_context; |
21dd79e8 | 7676 | struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context; |
7a9b6b8f | 7677 | struct tstorm_roce_conn_st_ctx tstorm_st_context; |
50bc60cb | 7678 | struct regpair tstorm_st_padding[2]; |
7a9b6b8f | 7679 | struct mstorm_roce_conn_st_ctx mstorm_st_context; |
50bc60cb | 7680 | struct regpair mstorm_st_padding[2]; |
7a9b6b8f | 7681 | struct ustorm_roce_conn_st_ctx ustorm_st_context; |
7a9b6b8f YM |
7682 | }; |
7683 | ||
a2e7699e | 7684 | /* roce create qp requester ramrod data */ |
7a9b6b8f YM |
7685 | struct roce_create_qp_req_ramrod_data { |
7686 | __le16 flags; | |
a2e7699e TT |
7687 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 |
7688 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 | |
7689 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 | |
7690 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2 | |
7691 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 | |
7692 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3 | |
7693 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 | |
7694 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4 | |
50bc60cb MK |
7695 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1 |
7696 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT 7 | |
a2e7699e TT |
7697 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF |
7698 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8 | |
7699 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF | |
7700 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12 | |
7a9b6b8f YM |
7701 | u8 max_ord; |
7702 | u8 traffic_class; | |
7703 | u8 hop_limit; | |
7704 | u8 orq_num_pages; | |
7705 | __le16 p_key; | |
7706 | __le32 flow_label; | |
7707 | __le32 dst_qp_id; | |
7708 | __le32 ack_timeout_val; | |
7709 | __le32 initial_psn; | |
7710 | __le16 mtu; | |
7711 | __le16 pd; | |
7712 | __le16 sq_num_pages; | |
be086e7c | 7713 | __le16 low_latency_phy_queue; |
7a9b6b8f YM |
7714 | struct regpair sq_pbl_addr; |
7715 | struct regpair orq_pbl_addr; | |
7716 | __le16 local_mac_addr[3]; | |
7717 | __le16 remote_mac_addr[3]; | |
7718 | __le16 vlan_id; | |
7719 | __le16 udp_src_port; | |
7720 | __le32 src_gid[4]; | |
7721 | __le32 dst_gid[4]; | |
50bc60cb | 7722 | __le32 cq_cid; |
7a9b6b8f YM |
7723 | struct regpair qp_handle_for_cqe; |
7724 | struct regpair qp_handle_for_async; | |
7725 | u8 stats_counter_id; | |
7726 | u8 reserved3[7]; | |
be086e7c | 7727 | __le16 regular_latency_phy_queue; |
7a9b6b8f YM |
7728 | __le16 dpi; |
7729 | }; | |
7730 | ||
a2e7699e | 7731 | /* roce create qp responder ramrod data */ |
7a9b6b8f | 7732 | struct roce_create_qp_resp_ramrod_data { |
50bc60cb | 7733 | __le32 flags; |
a2e7699e TT |
7734 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 |
7735 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 | |
7736 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 | |
7737 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 | |
7738 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 | |
7739 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 | |
7740 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 | |
7741 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 | |
7742 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1 | |
7743 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5 | |
7744 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1 | |
7745 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6 | |
7746 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 | |
7747 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7 | |
7748 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 | |
7749 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8 | |
7750 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F | |
7751 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11 | |
50bc60cb MK |
7752 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1 |
7753 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT 16 | |
7754 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x7FFF | |
7755 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT 17 | |
7756 | __le16 xrc_domain; | |
7a9b6b8f YM |
7757 | u8 max_ird; |
7758 | u8 traffic_class; | |
7759 | u8 hop_limit; | |
7760 | u8 irq_num_pages; | |
7761 | __le16 p_key; | |
7762 | __le32 flow_label; | |
7763 | __le32 dst_qp_id; | |
7764 | u8 stats_counter_id; | |
7765 | u8 reserved1; | |
7766 | __le16 mtu; | |
7767 | __le32 initial_psn; | |
7768 | __le16 pd; | |
7769 | __le16 rq_num_pages; | |
7770 | struct rdma_srq_id srq_id; | |
7771 | struct regpair rq_pbl_addr; | |
7772 | struct regpair irq_pbl_addr; | |
7773 | __le16 local_mac_addr[3]; | |
7774 | __le16 remote_mac_addr[3]; | |
7775 | __le16 vlan_id; | |
7776 | __le16 udp_src_port; | |
7777 | __le32 src_gid[4]; | |
7778 | __le32 dst_gid[4]; | |
7779 | struct regpair qp_handle_for_cqe; | |
7780 | struct regpair qp_handle_for_async; | |
be086e7c | 7781 | __le16 low_latency_phy_queue; |
50bc60cb | 7782 | u8 reserved2[2]; |
7a9b6b8f | 7783 | __le32 cq_cid; |
be086e7c | 7784 | __le16 regular_latency_phy_queue; |
7a9b6b8f YM |
7785 | __le16 dpi; |
7786 | }; | |
7787 | ||
da090917 TT |
7788 | /* roce DCQCN received statistics */ |
7789 | struct roce_dcqcn_received_stats { | |
7790 | struct regpair ecn_pkt_rcv; | |
7791 | struct regpair cnp_pkt_rcv; | |
7792 | }; | |
7793 | ||
7794 | /* roce DCQCN sent statistics */ | |
7795 | struct roce_dcqcn_sent_stats { | |
7796 | struct regpair cnp_pkt_sent; | |
7797 | }; | |
7798 | ||
a2e7699e | 7799 | /* RoCE destroy qp requester output params */ |
7a9b6b8f YM |
7800 | struct roce_destroy_qp_req_output_params { |
7801 | __le32 num_bound_mw; | |
be086e7c | 7802 | __le32 cq_prod; |
7a9b6b8f YM |
7803 | }; |
7804 | ||
a2e7699e | 7805 | /* RoCE destroy qp requester ramrod data */ |
7a9b6b8f YM |
7806 | struct roce_destroy_qp_req_ramrod_data { |
7807 | struct regpair output_params_addr; | |
7808 | }; | |
7809 | ||
a2e7699e | 7810 | /* RoCE destroy qp responder output params */ |
7a9b6b8f YM |
7811 | struct roce_destroy_qp_resp_output_params { |
7812 | __le32 num_invalidated_mw; | |
be086e7c | 7813 | __le32 cq_prod; |
7a9b6b8f YM |
7814 | }; |
7815 | ||
a2e7699e | 7816 | /* RoCE destroy qp responder ramrod data */ |
7a9b6b8f YM |
7817 | struct roce_destroy_qp_resp_ramrod_data { |
7818 | struct regpair output_params_addr; | |
7819 | }; | |
7820 | ||
a2e7699e | 7821 | /* roce special events statistics */ |
7b6859fb MY |
7822 | struct roce_events_stats { |
7823 | __le16 silent_drops; | |
7824 | __le16 rnr_naks_sent; | |
7825 | __le32 retransmit_count; | |
7826 | __le32 icrc_error_count; | |
7827 | __le32 reserved; | |
7828 | }; | |
7829 | ||
a2e7699e | 7830 | /* ROCE slow path EQ cmd IDs */ |
7a9b6b8f YM |
7831 | enum roce_event_opcode { |
7832 | ROCE_EVENT_CREATE_QP = 11, | |
7833 | ROCE_EVENT_MODIFY_QP, | |
7834 | ROCE_EVENT_QUERY_QP, | |
7835 | ROCE_EVENT_DESTROY_QP, | |
7b6859fb MY |
7836 | ROCE_EVENT_CREATE_UD_QP, |
7837 | ROCE_EVENT_DESTROY_UD_QP, | |
7a9b6b8f YM |
7838 | MAX_ROCE_EVENT_OPCODE |
7839 | }; | |
7840 | ||
a2e7699e | 7841 | /* roce func init ramrod data */ |
7b6859fb MY |
7842 | struct roce_init_func_params { |
7843 | u8 ll2_queue_id; | |
7844 | u8 cnp_vlan_priority; | |
7845 | u8 cnp_dscp; | |
7846 | u8 reserved; | |
7847 | __le32 cnp_send_timeout; | |
7848 | }; | |
7849 | ||
a2e7699e | 7850 | /* roce func init ramrod data */ |
05fafbfb YM |
7851 | struct roce_init_func_ramrod_data { |
7852 | struct rdma_init_func_ramrod_data rdma; | |
7b6859fb | 7853 | struct roce_init_func_params roce; |
05fafbfb YM |
7854 | }; |
7855 | ||
a2e7699e | 7856 | /* roce modify qp requester ramrod data */ |
7a9b6b8f YM |
7857 | struct roce_modify_qp_req_ramrod_data { |
7858 | __le16 flags; | |
a2e7699e TT |
7859 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 |
7860 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 | |
7861 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1 | |
7862 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1 | |
7863 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1 | |
7864 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2 | |
7865 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1 | |
7866 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3 | |
7867 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 | |
7868 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4 | |
7869 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1 | |
7870 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5 | |
7871 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1 | |
7872 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6 | |
7873 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1 | |
7874 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7 | |
7875 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1 | |
7876 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8 | |
7877 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1 | |
7878 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9 | |
7879 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 | |
7880 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10 | |
da090917 TT |
7881 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK 0x1 |
7882 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT 13 | |
7883 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3 | |
7884 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 14 | |
7a9b6b8f | 7885 | u8 fields; |
a2e7699e TT |
7886 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF |
7887 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0 | |
7888 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF | |
7889 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4 | |
7a9b6b8f YM |
7890 | u8 max_ord; |
7891 | u8 traffic_class; | |
7892 | u8 hop_limit; | |
7893 | __le16 p_key; | |
7894 | __le32 flow_label; | |
7895 | __le32 ack_timeout_val; | |
7896 | __le16 mtu; | |
7897 | __le16 reserved2; | |
da090917 TT |
7898 | __le32 reserved3[2]; |
7899 | __le16 low_latency_phy_queue; | |
7900 | __le16 regular_latency_phy_queue; | |
7a9b6b8f YM |
7901 | __le32 src_gid[4]; |
7902 | __le32 dst_gid[4]; | |
7903 | }; | |
7904 | ||
a2e7699e | 7905 | /* roce modify qp responder ramrod data */ |
7a9b6b8f YM |
7906 | struct roce_modify_qp_resp_ramrod_data { |
7907 | __le16 flags; | |
a2e7699e TT |
7908 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 |
7909 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 | |
7910 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 | |
7911 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1 | |
7912 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 | |
7913 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2 | |
7914 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 | |
7915 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3 | |
7916 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1 | |
7917 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4 | |
7918 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 | |
7919 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5 | |
7920 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1 | |
7921 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6 | |
7922 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1 | |
7923 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7 | |
7924 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1 | |
7925 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8 | |
7926 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 | |
7927 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9 | |
da090917 TT |
7928 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK 0x1 |
7929 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT 10 | |
7930 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x1F | |
7931 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 11 | |
7a9b6b8f | 7932 | u8 fields; |
a2e7699e TT |
7933 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 |
7934 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0 | |
7935 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F | |
7936 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3 | |
7a9b6b8f YM |
7937 | u8 max_ird; |
7938 | u8 traffic_class; | |
7939 | u8 hop_limit; | |
7940 | __le16 p_key; | |
7941 | __le32 flow_label; | |
7942 | __le16 mtu; | |
da090917 TT |
7943 | __le16 low_latency_phy_queue; |
7944 | __le16 regular_latency_phy_queue; | |
7945 | u8 reserved2[6]; | |
7a9b6b8f YM |
7946 | __le32 src_gid[4]; |
7947 | __le32 dst_gid[4]; | |
7948 | }; | |
7949 | ||
a2e7699e | 7950 | /* RoCE query qp requester output params */ |
7a9b6b8f YM |
7951 | struct roce_query_qp_req_output_params { |
7952 | __le32 psn; | |
7953 | __le32 flags; | |
a2e7699e TT |
7954 | #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1 |
7955 | #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0 | |
7956 | #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1 | |
7957 | #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1 | |
7958 | #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF | |
7959 | #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2 | |
7a9b6b8f YM |
7960 | }; |
7961 | ||
a2e7699e | 7962 | /* RoCE query qp requester ramrod data */ |
7a9b6b8f YM |
7963 | struct roce_query_qp_req_ramrod_data { |
7964 | struct regpair output_params_addr; | |
7965 | }; | |
7966 | ||
a2e7699e | 7967 | /* RoCE query qp responder output params */ |
7a9b6b8f YM |
7968 | struct roce_query_qp_resp_output_params { |
7969 | __le32 psn; | |
7970 | __le32 err_flag; | |
7971 | #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 | |
7972 | #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 | |
7973 | #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF | |
7974 | #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 | |
7975 | }; | |
7976 | ||
a2e7699e | 7977 | /* RoCE query qp responder ramrod data */ |
7a9b6b8f YM |
7978 | struct roce_query_qp_resp_ramrod_data { |
7979 | struct regpair output_params_addr; | |
7980 | }; | |
7981 | ||
50bc60cb MK |
7982 | /* ROCE ramrod command IDs */ |
7983 | enum roce_ramrod_cmd_id { | |
7984 | ROCE_RAMROD_CREATE_QP = 11, | |
7985 | ROCE_RAMROD_MODIFY_QP, | |
7986 | ROCE_RAMROD_QUERY_QP, | |
7987 | ROCE_RAMROD_DESTROY_QP, | |
7988 | ROCE_RAMROD_CREATE_UD_QP, | |
7989 | ROCE_RAMROD_DESTROY_UD_QP, | |
7990 | MAX_ROCE_RAMROD_CMD_ID | |
7991 | }; | |
7992 | ||
7993 | struct e4_xstorm_roce_conn_ag_ctx_dq_ext_ld_part { | |
7994 | u8 reserved0; | |
7995 | u8 state; | |
7996 | u8 flags0; | |
7997 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 | |
7998 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 | |
7999 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1 | |
8000 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1 | |
8001 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1 | |
8002 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2 | |
8003 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 | |
8004 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 | |
8005 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1 | |
8006 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4 | |
8007 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1 | |
8008 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5 | |
8009 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1 | |
8010 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6 | |
8011 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1 | |
8012 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7 | |
8013 | u8 flags1; | |
8014 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1 | |
8015 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0 | |
8016 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1 | |
8017 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1 | |
8018 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 | |
8019 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 | |
8020 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 | |
8021 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 | |
8022 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 | |
8023 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 | |
8024 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK 0x1 | |
8025 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_SHIFT 5 | |
8026 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK 0x1 | |
8027 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_SHIFT 6 | |
8028 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 | |
8029 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 | |
8030 | u8 flags2; | |
8031 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 | |
8032 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 | |
8033 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 | |
8034 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 | |
8035 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 | |
8036 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 | |
8037 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 | |
8038 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 | |
8039 | u8 flags3; | |
8040 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3 | |
8041 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0 | |
8042 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3 | |
8043 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2 | |
8044 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3 | |
8045 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4 | |
8046 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 | |
8047 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 | |
8048 | u8 flags4; | |
8049 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 | |
8050 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 | |
8051 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 | |
8052 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 | |
8053 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 | |
8054 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 | |
8055 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 | |
8056 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 | |
8057 | u8 flags5; | |
8058 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 | |
8059 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 | |
8060 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 | |
8061 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 | |
8062 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3 | |
8063 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4 | |
8064 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 | |
8065 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 | |
8066 | u8 flags6; | |
8067 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 | |
8068 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 | |
8069 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 | |
8070 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 | |
8071 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 | |
8072 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 | |
8073 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 | |
8074 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 | |
8075 | u8 flags7; | |
8076 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 | |
8077 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 | |
8078 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 | |
8079 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 | |
8080 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 | |
8081 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 | |
8082 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 | |
8083 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 | |
8084 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 | |
8085 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 | |
8086 | u8 flags8; | |
8087 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 | |
8088 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 | |
8089 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 | |
8090 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 | |
8091 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 | |
8092 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 | |
8093 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 | |
8094 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 | |
8095 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 | |
8096 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 | |
8097 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 | |
8098 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 | |
8099 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 | |
8100 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 | |
8101 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 | |
8102 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 | |
8103 | u8 flags9; | |
8104 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 | |
8105 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 | |
8106 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 | |
8107 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 | |
8108 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 | |
8109 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 | |
8110 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 | |
8111 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 | |
8112 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 | |
8113 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 | |
8114 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 | |
8115 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 | |
8116 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 | |
8117 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 | |
8118 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 | |
8119 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 | |
8120 | u8 flags10; | |
8121 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 | |
8122 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 | |
8123 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 | |
8124 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 | |
8125 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 | |
8126 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 | |
8127 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 | |
8128 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 | |
8129 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 | |
8130 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 | |
8131 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 | |
8132 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 | |
8133 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 | |
8134 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 | |
8135 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 | |
8136 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 | |
8137 | u8 flags11; | |
8138 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 | |
8139 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 | |
8140 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 | |
8141 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 | |
8142 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 | |
8143 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 | |
8144 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 | |
8145 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 | |
8146 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 | |
8147 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 | |
8148 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 | |
8149 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 | |
8150 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 | |
8151 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 | |
8152 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 | |
8153 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 | |
8154 | u8 flags12; | |
8155 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 | |
8156 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 | |
8157 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 | |
8158 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 | |
8159 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 | |
8160 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 | |
8161 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 | |
8162 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 | |
8163 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 | |
8164 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 | |
8165 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 | |
8166 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 | |
8167 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 | |
8168 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 | |
8169 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 | |
8170 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 | |
8171 | u8 flags13; | |
8172 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 | |
8173 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 | |
8174 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 | |
8175 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 | |
8176 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 | |
8177 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 | |
8178 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 | |
8179 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 | |
8180 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 | |
8181 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 | |
8182 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 | |
8183 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 | |
8184 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 | |
8185 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 | |
8186 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 | |
8187 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 | |
8188 | u8 flags14; | |
8189 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1 | |
8190 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0 | |
8191 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 | |
8192 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 | |
8193 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 | |
8194 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 | |
8195 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 | |
8196 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 | |
8197 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 | |
8198 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 | |
8199 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 | |
8200 | #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 | |
8201 | u8 byte2; | |
8202 | __le16 physical_q0; | |
8203 | __le16 word1; | |
8204 | __le16 word2; | |
8205 | __le16 word3; | |
8206 | __le16 word4; | |
8207 | __le16 word5; | |
8208 | __le16 conn_dpi; | |
8209 | u8 byte3; | |
8210 | u8 byte4; | |
8211 | u8 byte5; | |
8212 | u8 byte6; | |
8213 | __le32 reg0; | |
8214 | __le32 reg1; | |
8215 | __le32 reg2; | |
8216 | __le32 snd_nxt_psn; | |
8217 | __le32 reg4; | |
8218 | }; | |
8219 | ||
8220 | struct e4_mstorm_roce_conn_ag_ctx { | |
8221 | u8 byte0; | |
8222 | u8 byte1; | |
8223 | u8 flags0; | |
8224 | #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1 | |
8225 | #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0 | |
8226 | #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 | |
8227 | #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 | |
8228 | #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 | |
8229 | #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 2 | |
8230 | #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3 | |
8231 | #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 4 | |
8232 | #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 | |
8233 | #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 6 | |
8234 | u8 flags1; | |
8235 | #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 | |
8236 | #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0 | |
8237 | #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
8238 | #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1 | |
8239 | #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 | |
8240 | #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2 | |
8241 | #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
8242 | #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
8243 | #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
8244 | #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
8245 | #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
8246 | #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
8247 | #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
8248 | #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
8249 | #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
8250 | #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
8251 | __le16 word0; | |
8252 | __le16 word1; | |
8253 | __le32 reg0; | |
8254 | __le32 reg1; | |
7a9b6b8f YM |
8255 | }; |
8256 | ||
21dd79e8 | 8257 | struct e4_mstorm_roce_req_conn_ag_ctx { |
7a9b6b8f YM |
8258 | u8 byte0; |
8259 | u8 byte1; | |
8260 | u8 flags0; | |
21dd79e8 TT |
8261 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 |
8262 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 | |
8263 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 | |
8264 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 | |
8265 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 | |
8266 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 | |
8267 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 | |
8268 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 | |
8269 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 | |
8270 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 | |
7a9b6b8f | 8271 | u8 flags1; |
21dd79e8 TT |
8272 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 |
8273 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 | |
8274 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 | |
8275 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 | |
8276 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 | |
8277 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 | |
8278 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
8279 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
8280 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
8281 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
8282 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
8283 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
8284 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
8285 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
8286 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
8287 | #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
7a9b6b8f YM |
8288 | __le16 word0; |
8289 | __le16 word1; | |
8290 | __le32 reg0; | |
8291 | __le32 reg1; | |
8292 | }; | |
8293 | ||
21dd79e8 | 8294 | struct e4_mstorm_roce_resp_conn_ag_ctx { |
7a9b6b8f YM |
8295 | u8 byte0; |
8296 | u8 byte1; | |
8297 | u8 flags0; | |
21dd79e8 TT |
8298 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 |
8299 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 | |
8300 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 | |
8301 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 | |
8302 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 | |
8303 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 | |
8304 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 | |
8305 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 | |
8306 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 | |
8307 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 | |
7a9b6b8f | 8308 | u8 flags1; |
21dd79e8 TT |
8309 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 |
8310 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 | |
8311 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 | |
8312 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 | |
8313 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 | |
8314 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 | |
8315 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
8316 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
8317 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
8318 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
8319 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
8320 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
8321 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
8322 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
8323 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
8324 | #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
7a9b6b8f YM |
8325 | __le16 word0; |
8326 | __le16 word1; | |
8327 | __le32 reg0; | |
8328 | __le32 reg1; | |
8329 | }; | |
8330 | ||
21dd79e8 | 8331 | struct e4_tstorm_roce_req_conn_ag_ctx { |
7a9b6b8f YM |
8332 | u8 reserved0; |
8333 | u8 state; | |
8334 | u8 flags0; | |
21dd79e8 TT |
8335 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
8336 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
8337 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK 0x1 | |
8338 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT 1 | |
8339 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK 0x1 | |
8340 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT 2 | |
8341 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 | |
8342 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3 | |
8343 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 | |
8344 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 | |
8345 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 | |
8346 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 | |
8347 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 | |
8348 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6 | |
7a9b6b8f | 8349 | u8 flags1; |
50bc60cb MK |
8350 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 |
8351 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 | |
21dd79e8 TT |
8352 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 |
8353 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2 | |
8354 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 | |
8355 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 | |
8356 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 | |
8357 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 | |
7a9b6b8f | 8358 | u8 flags2; |
50bc60cb MK |
8359 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK 0x3 |
8360 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_SHIFT 0 | |
21dd79e8 TT |
8361 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 |
8362 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2 | |
8363 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 | |
8364 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4 | |
8365 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 | |
8366 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6 | |
7a9b6b8f | 8367 | u8 flags3; |
21dd79e8 TT |
8368 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 |
8369 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0 | |
8370 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 | |
8371 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2 | |
8372 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 | |
8373 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4 | |
50bc60cb MK |
8374 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 |
8375 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5 | |
21dd79e8 TT |
8376 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 |
8377 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6 | |
8378 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 | |
8379 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 | |
7a9b6b8f | 8380 | u8 flags4; |
21dd79e8 TT |
8381 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 |
8382 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 | |
50bc60cb MK |
8383 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK 0x1 |
8384 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_SHIFT 1 | |
21dd79e8 TT |
8385 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 |
8386 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2 | |
8387 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 | |
8388 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3 | |
8389 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 | |
8390 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4 | |
8391 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 | |
8392 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5 | |
8393 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 | |
8394 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6 | |
8395 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
8396 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
7a9b6b8f | 8397 | u8 flags5; |
21dd79e8 TT |
8398 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 |
8399 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
8400 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
8401 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
8402 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
8403 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
8404 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
8405 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
8406 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
8407 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
8408 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 | |
8409 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5 | |
8410 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
8411 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
8412 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
8413 | #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
7a9b6b8f YM |
8414 | __le32 reg0; |
8415 | __le32 snd_nxt_psn; | |
8416 | __le32 snd_max_psn; | |
8417 | __le32 orq_prod; | |
8418 | __le32 reg4; | |
8419 | __le32 reg5; | |
8420 | __le32 reg6; | |
8421 | __le32 reg7; | |
8422 | __le32 reg8; | |
8423 | u8 tx_cqe_error_type; | |
8424 | u8 orq_cache_idx; | |
8425 | __le16 snd_sq_cons_th; | |
8426 | u8 byte4; | |
8427 | u8 byte5; | |
8428 | __le16 snd_sq_cons; | |
da090917 | 8429 | __le16 conn_dpi; |
50bc60cb | 8430 | __le16 force_comp_cons; |
7a9b6b8f YM |
8431 | __le32 reg9; |
8432 | __le32 reg10; | |
8433 | }; | |
8434 | ||
21dd79e8 | 8435 | struct e4_tstorm_roce_resp_conn_ag_ctx { |
7a9b6b8f YM |
8436 | u8 byte0; |
8437 | u8 state; | |
8438 | u8 flags0; | |
21dd79e8 TT |
8439 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
8440 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
8441 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1 | |
8442 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1 | |
8443 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 | |
8444 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2 | |
8445 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 | |
8446 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3 | |
8447 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 | |
8448 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 | |
8449 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 | |
8450 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5 | |
8451 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 | |
8452 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6 | |
7a9b6b8f | 8453 | u8 flags1; |
50bc60cb MK |
8454 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 |
8455 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 | |
21dd79e8 TT |
8456 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 |
8457 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2 | |
8458 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 | |
8459 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4 | |
8460 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 | |
8461 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 | |
7a9b6b8f | 8462 | u8 flags2; |
50bc60cb MK |
8463 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 |
8464 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 | |
21dd79e8 TT |
8465 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 |
8466 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2 | |
8467 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 | |
8468 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4 | |
8469 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 | |
8470 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6 | |
7a9b6b8f | 8471 | u8 flags3; |
21dd79e8 TT |
8472 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 |
8473 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0 | |
8474 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 | |
8475 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2 | |
8476 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 | |
8477 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4 | |
50bc60cb MK |
8478 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 |
8479 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5 | |
21dd79e8 TT |
8480 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 |
8481 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6 | |
8482 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 | |
8483 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7 | |
7a9b6b8f | 8484 | u8 flags4; |
21dd79e8 TT |
8485 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 |
8486 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 | |
50bc60cb MK |
8487 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 |
8488 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 1 | |
21dd79e8 TT |
8489 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 |
8490 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2 | |
8491 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 | |
8492 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3 | |
8493 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 | |
8494 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4 | |
8495 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 | |
8496 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5 | |
8497 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 | |
8498 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6 | |
8499 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
8500 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
7a9b6b8f | 8501 | u8 flags5; |
21dd79e8 TT |
8502 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 |
8503 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
8504 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
8505 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
8506 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
8507 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
8508 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
8509 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
8510 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
8511 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
8512 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 | |
8513 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5 | |
8514 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
8515 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
8516 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
8517 | #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
7a9b6b8f YM |
8518 | __le32 psn_and_rxmit_id_echo; |
8519 | __le32 reg1; | |
8520 | __le32 reg2; | |
8521 | __le32 reg3; | |
8522 | __le32 reg4; | |
8523 | __le32 reg5; | |
8524 | __le32 reg6; | |
8525 | __le32 reg7; | |
8526 | __le32 reg8; | |
8527 | u8 tx_async_error_type; | |
8528 | u8 byte3; | |
8529 | __le16 rq_cons; | |
8530 | u8 byte4; | |
8531 | u8 byte5; | |
8532 | __le16 rq_prod; | |
8533 | __le16 conn_dpi; | |
8534 | __le16 irq_cons; | |
8535 | __le32 num_invlidated_mw; | |
8536 | __le32 reg10; | |
8537 | }; | |
8538 | ||
21dd79e8 | 8539 | struct e4_ustorm_roce_req_conn_ag_ctx { |
7a9b6b8f YM |
8540 | u8 byte0; |
8541 | u8 byte1; | |
8542 | u8 flags0; | |
21dd79e8 TT |
8543 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 |
8544 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 | |
8545 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 | |
8546 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 | |
8547 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 | |
8548 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 | |
8549 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 | |
8550 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 | |
8551 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 | |
8552 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 | |
7a9b6b8f | 8553 | u8 flags1; |
21dd79e8 TT |
8554 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 |
8555 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0 | |
8556 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 | |
8557 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2 | |
8558 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 | |
8559 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4 | |
8560 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 | |
8561 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6 | |
7a9b6b8f | 8562 | u8 flags2; |
21dd79e8 TT |
8563 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 |
8564 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 | |
8565 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 | |
8566 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 | |
8567 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 | |
8568 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 | |
8569 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 | |
8570 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3 | |
8571 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 | |
8572 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4 | |
8573 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 | |
8574 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5 | |
8575 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 | |
8576 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6 | |
8577 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
8578 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
7a9b6b8f | 8579 | u8 flags3; |
21dd79e8 TT |
8580 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 |
8581 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
8582 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
8583 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
8584 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
8585 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
8586 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
8587 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
8588 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
8589 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
8590 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
8591 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
8592 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
8593 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
8594 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
8595 | #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
7a9b6b8f YM |
8596 | u8 byte2; |
8597 | u8 byte3; | |
8598 | __le16 word0; | |
8599 | __le16 word1; | |
8600 | __le32 reg0; | |
8601 | __le32 reg1; | |
8602 | __le32 reg2; | |
8603 | __le32 reg3; | |
8604 | __le16 word2; | |
8605 | __le16 word3; | |
8606 | }; | |
8607 | ||
21dd79e8 | 8608 | struct e4_ustorm_roce_resp_conn_ag_ctx { |
7a9b6b8f YM |
8609 | u8 byte0; |
8610 | u8 byte1; | |
8611 | u8 flags0; | |
21dd79e8 TT |
8612 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 |
8613 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 | |
8614 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 | |
8615 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 | |
8616 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 | |
8617 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 | |
8618 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 | |
8619 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 | |
8620 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 | |
8621 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 | |
7a9b6b8f | 8622 | u8 flags1; |
21dd79e8 TT |
8623 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 |
8624 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0 | |
8625 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 | |
8626 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2 | |
8627 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 | |
8628 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4 | |
8629 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 | |
8630 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6 | |
7a9b6b8f | 8631 | u8 flags2; |
21dd79e8 TT |
8632 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 |
8633 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 | |
8634 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 | |
8635 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 | |
8636 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 | |
8637 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 | |
8638 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 | |
8639 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3 | |
8640 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 | |
8641 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4 | |
8642 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 | |
8643 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5 | |
8644 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 | |
8645 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6 | |
8646 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
8647 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
7a9b6b8f | 8648 | u8 flags3; |
21dd79e8 TT |
8649 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 |
8650 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
8651 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
8652 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
8653 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
8654 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
8655 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
8656 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
8657 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
8658 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
8659 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
8660 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
8661 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
8662 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
8663 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
8664 | #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
7a9b6b8f YM |
8665 | u8 byte2; |
8666 | u8 byte3; | |
8667 | __le16 word0; | |
8668 | __le16 word1; | |
8669 | __le32 reg0; | |
8670 | __le32 reg1; | |
8671 | __le32 reg2; | |
8672 | __le32 reg3; | |
8673 | __le16 word2; | |
8674 | __le16 word3; | |
8675 | }; | |
8676 | ||
21dd79e8 | 8677 | struct e4_xstorm_roce_req_conn_ag_ctx { |
7a9b6b8f YM |
8678 | u8 reserved0; |
8679 | u8 state; | |
8680 | u8 flags0; | |
21dd79e8 TT |
8681 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
8682 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
8683 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 | |
8684 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1 | |
8685 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 | |
8686 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2 | |
8687 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
8688 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
8689 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 | |
8690 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4 | |
8691 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 | |
8692 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5 | |
8693 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 | |
8694 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6 | |
8695 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 | |
8696 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7 | |
7a9b6b8f | 8697 | u8 flags1; |
21dd79e8 TT |
8698 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 |
8699 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0 | |
8700 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 | |
8701 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1 | |
8702 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 | |
8703 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2 | |
8704 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 | |
8705 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3 | |
8706 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1 | |
8707 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4 | |
8708 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1 | |
8709 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5 | |
8710 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 | |
8711 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6 | |
8712 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 | |
8713 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 | |
7a9b6b8f | 8714 | u8 flags2; |
21dd79e8 TT |
8715 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 |
8716 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0 | |
8717 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 | |
8718 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2 | |
8719 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 | |
8720 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4 | |
8721 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 | |
8722 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6 | |
7a9b6b8f | 8723 | u8 flags3; |
21dd79e8 TT |
8724 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 |
8725 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0 | |
8726 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 | |
8727 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 | |
8728 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 | |
8729 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4 | |
8730 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 | |
8731 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 | |
7a9b6b8f | 8732 | u8 flags4; |
50bc60cb MK |
8733 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK 0x3 |
8734 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_SHIFT 0 | |
8735 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK 0x3 | |
8736 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_SHIFT 2 | |
21dd79e8 TT |
8737 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 |
8738 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4 | |
8739 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 | |
8740 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6 | |
7a9b6b8f | 8741 | u8 flags5; |
21dd79e8 TT |
8742 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 |
8743 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0 | |
8744 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 | |
8745 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2 | |
8746 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 | |
8747 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4 | |
8748 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 | |
8749 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6 | |
7a9b6b8f | 8750 | u8 flags6; |
21dd79e8 TT |
8751 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 |
8752 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0 | |
8753 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 | |
8754 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2 | |
8755 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 | |
8756 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4 | |
8757 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 | |
8758 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6 | |
7a9b6b8f | 8759 | u8 flags7; |
21dd79e8 TT |
8760 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 |
8761 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0 | |
8762 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 | |
8763 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2 | |
8764 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 | |
8765 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
8766 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 | |
8767 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6 | |
8768 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 | |
8769 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7 | |
7a9b6b8f | 8770 | u8 flags8; |
21dd79e8 TT |
8771 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 |
8772 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0 | |
8773 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 | |
8774 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1 | |
8775 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 | |
8776 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2 | |
8777 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 | |
8778 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 | |
8779 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 | |
8780 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4 | |
8781 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 | |
8782 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 | |
50bc60cb MK |
8783 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 |
8784 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_SHIFT 6 | |
8785 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK 0x1 | |
8786 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_SHIFT 7 | |
7a9b6b8f | 8787 | u8 flags9; |
21dd79e8 TT |
8788 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 |
8789 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0 | |
8790 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 | |
8791 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1 | |
8792 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 | |
8793 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2 | |
8794 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 | |
8795 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3 | |
8796 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 | |
8797 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4 | |
8798 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 | |
8799 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5 | |
8800 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 | |
8801 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6 | |
8802 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 | |
8803 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7 | |
7a9b6b8f | 8804 | u8 flags10; |
21dd79e8 TT |
8805 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 |
8806 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0 | |
8807 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 | |
8808 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1 | |
8809 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 | |
8810 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2 | |
8811 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 | |
8812 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3 | |
8813 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
8814 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
8815 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 | |
8816 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5 | |
8817 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
8818 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6 | |
8819 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
8820 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7 | |
7a9b6b8f | 8821 | u8 flags11; |
21dd79e8 TT |
8822 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 |
8823 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0 | |
8824 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
8825 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1 | |
8826 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
8827 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2 | |
8828 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
8829 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
8830 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
8831 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
8832 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 | |
8833 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5 | |
8834 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
8835 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
8836 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 | |
8837 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7 | |
7a9b6b8f | 8838 | u8 flags12; |
21dd79e8 TT |
8839 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 |
8840 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 | |
8841 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 | |
8842 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1 | |
8843 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
8844 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
8845 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
8846 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
8847 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 | |
8848 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4 | |
8849 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
8850 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
8851 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 | |
8852 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6 | |
8853 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 | |
8854 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7 | |
7a9b6b8f | 8855 | u8 flags13; |
21dd79e8 TT |
8856 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 |
8857 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0 | |
8858 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 | |
8859 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1 | |
8860 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 | |
8861 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 | |
8862 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 | |
8863 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 | |
8864 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
8865 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
8866 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 | |
8867 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 | |
8868 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
8869 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
8870 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
8871 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
7a9b6b8f | 8872 | u8 flags14; |
21dd79e8 TT |
8873 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 |
8874 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0 | |
8875 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 | |
8876 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1 | |
8877 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 | |
8878 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 | |
8879 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 | |
8880 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4 | |
8881 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 | |
8882 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 | |
8883 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 | |
8884 | #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6 | |
7a9b6b8f YM |
8885 | u8 byte2; |
8886 | __le16 physical_q0; | |
8887 | __le16 word1; | |
8888 | __le16 sq_cmp_cons; | |
8889 | __le16 sq_cons; | |
8890 | __le16 sq_prod; | |
50bc60cb | 8891 | __le16 dif_error_first_sq_cons; |
7a9b6b8f | 8892 | __le16 conn_dpi; |
50bc60cb | 8893 | u8 dif_error_sge_index; |
7a9b6b8f YM |
8894 | u8 byte4; |
8895 | u8 byte5; | |
8896 | u8 byte6; | |
8897 | __le32 lsn; | |
8898 | __le32 ssn; | |
8899 | __le32 snd_una_psn; | |
8900 | __le32 snd_nxt_psn; | |
50bc60cb | 8901 | __le32 dif_error_offset; |
7a9b6b8f YM |
8902 | __le32 orq_cons_th; |
8903 | __le32 orq_cons; | |
8904 | }; | |
8905 | ||
21dd79e8 | 8906 | struct e4_xstorm_roce_resp_conn_ag_ctx { |
7a9b6b8f YM |
8907 | u8 reserved0; |
8908 | u8 state; | |
8909 | u8 flags0; | |
21dd79e8 TT |
8910 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
8911 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
8912 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 | |
8913 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1 | |
8914 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 | |
8915 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2 | |
8916 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
8917 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
8918 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 | |
8919 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4 | |
8920 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 | |
8921 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5 | |
8922 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 | |
8923 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6 | |
8924 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 | |
8925 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7 | |
7a9b6b8f | 8926 | u8 flags1; |
21dd79e8 TT |
8927 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 |
8928 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0 | |
8929 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 | |
8930 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1 | |
8931 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 | |
8932 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2 | |
8933 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 | |
8934 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3 | |
8935 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1 | |
8936 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4 | |
8937 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1 | |
8938 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5 | |
8939 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 | |
8940 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6 | |
8941 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 | |
8942 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 | |
7a9b6b8f | 8943 | u8 flags2; |
21dd79e8 TT |
8944 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 |
8945 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0 | |
8946 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 | |
8947 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2 | |
8948 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 | |
8949 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4 | |
8950 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 | |
8951 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6 | |
7a9b6b8f | 8952 | u8 flags3; |
21dd79e8 TT |
8953 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 |
8954 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0 | |
8955 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 | |
8956 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 | |
8957 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 | |
8958 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4 | |
8959 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 | |
8960 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 | |
7a9b6b8f | 8961 | u8 flags4; |
21dd79e8 TT |
8962 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 |
8963 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0 | |
8964 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 | |
8965 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2 | |
8966 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 | |
8967 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4 | |
8968 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 | |
8969 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6 | |
7a9b6b8f | 8970 | u8 flags5; |
21dd79e8 TT |
8971 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 |
8972 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0 | |
8973 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 | |
8974 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2 | |
8975 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 | |
8976 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4 | |
8977 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 | |
8978 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6 | |
7a9b6b8f | 8979 | u8 flags6; |
21dd79e8 TT |
8980 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 |
8981 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0 | |
8982 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 | |
8983 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2 | |
8984 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 | |
8985 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4 | |
8986 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 | |
8987 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6 | |
7a9b6b8f | 8988 | u8 flags7; |
21dd79e8 TT |
8989 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 |
8990 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0 | |
8991 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 | |
8992 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2 | |
8993 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 | |
8994 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
8995 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 | |
8996 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6 | |
8997 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 | |
8998 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7 | |
7a9b6b8f | 8999 | u8 flags8; |
21dd79e8 TT |
9000 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 |
9001 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0 | |
9002 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 | |
9003 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1 | |
9004 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 | |
9005 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2 | |
9006 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 | |
9007 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 | |
9008 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 | |
9009 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4 | |
9010 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 | |
9011 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 | |
9012 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 | |
9013 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6 | |
9014 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 | |
9015 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7 | |
7a9b6b8f | 9016 | u8 flags9; |
21dd79e8 TT |
9017 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 |
9018 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0 | |
9019 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 | |
9020 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1 | |
9021 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 | |
9022 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2 | |
9023 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 | |
9024 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3 | |
9025 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 | |
9026 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4 | |
9027 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 | |
9028 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5 | |
9029 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 | |
9030 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6 | |
9031 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 | |
9032 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7 | |
7a9b6b8f | 9033 | u8 flags10; |
21dd79e8 TT |
9034 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 |
9035 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0 | |
9036 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 | |
9037 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1 | |
9038 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 | |
9039 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2 | |
9040 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 | |
9041 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3 | |
9042 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
9043 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
9044 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 | |
9045 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5 | |
9046 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
9047 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6 | |
9048 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
9049 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7 | |
7a9b6b8f | 9050 | u8 flags11; |
21dd79e8 TT |
9051 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 |
9052 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0 | |
9053 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
9054 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1 | |
9055 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
9056 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2 | |
9057 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
9058 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
9059 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
9060 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
9061 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
9062 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5 | |
9063 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
9064 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
9065 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 | |
9066 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7 | |
7a9b6b8f | 9067 | u8 flags12; |
21dd79e8 TT |
9068 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 |
9069 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0 | |
9070 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1 | |
9071 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT 1 | |
9072 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
9073 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
9074 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
9075 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
9076 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 | |
9077 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4 | |
9078 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
9079 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
9080 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 | |
9081 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6 | |
9082 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 | |
9083 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7 | |
7a9b6b8f | 9084 | u8 flags13; |
21dd79e8 TT |
9085 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 |
9086 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0 | |
9087 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 | |
9088 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1 | |
9089 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 | |
9090 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 | |
9091 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 | |
9092 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 | |
9093 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
9094 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
9095 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 | |
9096 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 | |
9097 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
9098 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
9099 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
9100 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
7a9b6b8f | 9101 | u8 flags14; |
21dd79e8 TT |
9102 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 |
9103 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0 | |
9104 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 | |
9105 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1 | |
9106 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 | |
9107 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2 | |
9108 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 | |
9109 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3 | |
9110 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 | |
9111 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4 | |
9112 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 | |
9113 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5 | |
9114 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 | |
9115 | #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6 | |
7a9b6b8f YM |
9116 | u8 byte2; |
9117 | __le16 physical_q0; | |
da090917 TT |
9118 | __le16 irq_prod_shadow; |
9119 | __le16 word2; | |
9120 | __le16 irq_cons; | |
7a9b6b8f | 9121 | __le16 irq_prod; |
21dd79e8 | 9122 | __le16 e5_reserved1; |
da090917 | 9123 | __le16 conn_dpi; |
7a9b6b8f YM |
9124 | u8 rxmit_opcode; |
9125 | u8 byte4; | |
9126 | u8 byte5; | |
9127 | u8 byte6; | |
9128 | __le32 rxmit_psn_and_id; | |
9129 | __le32 rxmit_bytes_length; | |
9130 | __le32 psn; | |
9131 | __le32 reg3; | |
9132 | __le32 reg4; | |
9133 | __le32 reg5; | |
9134 | __le32 msn_and_syndrome; | |
9135 | }; | |
9136 | ||
50bc60cb MK |
9137 | struct e4_ystorm_roce_conn_ag_ctx { |
9138 | u8 byte0; | |
9139 | u8 byte1; | |
9140 | u8 flags0; | |
9141 | #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1 | |
9142 | #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0 | |
9143 | #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 | |
9144 | #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 | |
9145 | #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 | |
9146 | #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 2 | |
9147 | #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3 | |
9148 | #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 4 | |
9149 | #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 | |
9150 | #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 6 | |
9151 | u8 flags1; | |
9152 | #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 | |
9153 | #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0 | |
9154 | #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
9155 | #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1 | |
9156 | #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 | |
9157 | #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2 | |
9158 | #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
9159 | #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
9160 | #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
9161 | #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
9162 | #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
9163 | #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
9164 | #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
9165 | #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
9166 | #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
9167 | #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
9168 | u8 byte2; | |
9169 | u8 byte3; | |
9170 | __le16 word0; | |
9171 | __le32 reg0; | |
9172 | __le32 reg1; | |
9173 | __le16 word1; | |
9174 | __le16 word2; | |
9175 | __le16 word3; | |
9176 | __le16 word4; | |
9177 | __le32 reg2; | |
9178 | __le32 reg3; | |
9179 | }; | |
9180 | ||
21dd79e8 | 9181 | struct e4_ystorm_roce_req_conn_ag_ctx { |
7a9b6b8f YM |
9182 | u8 byte0; |
9183 | u8 byte1; | |
9184 | u8 flags0; | |
21dd79e8 TT |
9185 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 |
9186 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 | |
9187 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 | |
9188 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 | |
9189 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 | |
9190 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 | |
9191 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 | |
9192 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 | |
9193 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 | |
9194 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 | |
7a9b6b8f | 9195 | u8 flags1; |
21dd79e8 TT |
9196 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 |
9197 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 | |
9198 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 | |
9199 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 | |
9200 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 | |
9201 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 | |
9202 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
9203 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
9204 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
9205 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
9206 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
9207 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
9208 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
9209 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
9210 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
9211 | #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
7a9b6b8f YM |
9212 | u8 byte2; |
9213 | u8 byte3; | |
9214 | __le16 word0; | |
9215 | __le32 reg0; | |
9216 | __le32 reg1; | |
9217 | __le16 word1; | |
9218 | __le16 word2; | |
9219 | __le16 word3; | |
9220 | __le16 word4; | |
9221 | __le32 reg2; | |
9222 | __le32 reg3; | |
9223 | }; | |
9224 | ||
21dd79e8 | 9225 | struct e4_ystorm_roce_resp_conn_ag_ctx { |
7a9b6b8f YM |
9226 | u8 byte0; |
9227 | u8 byte1; | |
9228 | u8 flags0; | |
21dd79e8 TT |
9229 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 |
9230 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 | |
9231 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 | |
9232 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 | |
9233 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 | |
9234 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 | |
9235 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 | |
9236 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 | |
9237 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 | |
9238 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 | |
7a9b6b8f | 9239 | u8 flags1; |
21dd79e8 TT |
9240 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 |
9241 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 | |
9242 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 | |
9243 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 | |
9244 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 | |
9245 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 | |
9246 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
9247 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
9248 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
9249 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
9250 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
9251 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
9252 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
9253 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
9254 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
9255 | #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
7a9b6b8f YM |
9256 | u8 byte2; |
9257 | u8 byte3; | |
9258 | __le16 word0; | |
9259 | __le32 reg0; | |
9260 | __le32 reg1; | |
9261 | __le16 word1; | |
9262 | __le16 word2; | |
9263 | __le16 word3; | |
9264 | __le16 word4; | |
9265 | __le32 reg2; | |
9266 | __le32 reg3; | |
9267 | }; | |
9268 | ||
a2e7699e | 9269 | /* Roce doorbell data */ |
7b6859fb MY |
9270 | enum roce_flavor { |
9271 | PLAIN_ROCE, | |
9272 | RROCE_IPV4, | |
9273 | RROCE_IPV6, | |
9274 | MAX_ROCE_FLAVOR | |
9275 | }; | |
9276 | ||
a2e7699e | 9277 | /* The iwarp storm context of Ystorm */ |
7b6859fb MY |
9278 | struct ystorm_iwarp_conn_st_ctx { |
9279 | __le32 reserved[4]; | |
9280 | }; | |
9281 | ||
a2e7699e | 9282 | /* The iwarp storm context of Pstorm */ |
7b6859fb MY |
9283 | struct pstorm_iwarp_conn_st_ctx { |
9284 | __le32 reserved[36]; | |
9285 | }; | |
9286 | ||
a2e7699e | 9287 | /* The iwarp storm context of Xstorm */ |
7b6859fb | 9288 | struct xstorm_iwarp_conn_st_ctx { |
50bc60cb | 9289 | __le32 reserved[48]; |
7b6859fb MY |
9290 | }; |
9291 | ||
21dd79e8 | 9292 | struct e4_xstorm_iwarp_conn_ag_ctx { |
7b6859fb MY |
9293 | u8 reserved0; |
9294 | u8 state; | |
9295 | u8 flags0; | |
21dd79e8 TT |
9296 | #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
9297 | #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
9298 | #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 | |
9299 | #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 | |
9300 | #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1 | |
9301 | #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2 | |
9302 | #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
9303 | #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
9304 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 | |
9305 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 | |
9306 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1 | |
9307 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5 | |
9308 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1 | |
9309 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6 | |
9310 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1 | |
9311 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7 | |
7b6859fb | 9312 | u8 flags1; |
21dd79e8 TT |
9313 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1 |
9314 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0 | |
9315 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1 | |
9316 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1 | |
9317 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1 | |
9318 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2 | |
9319 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1 | |
9320 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3 | |
9321 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1 | |
9322 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4 | |
9323 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1 | |
9324 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5 | |
9325 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1 | |
9326 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6 | |
9327 | #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1 | |
9328 | #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7 | |
7b6859fb | 9329 | u8 flags2; |
21dd79e8 TT |
9330 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 |
9331 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0 | |
9332 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 | |
9333 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2 | |
9334 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 | |
9335 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4 | |
9336 | #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 | |
9337 | #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 | |
7b6859fb | 9338 | u8 flags3; |
21dd79e8 TT |
9339 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 |
9340 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0 | |
9341 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 | |
9342 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2 | |
9343 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 | |
9344 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4 | |
9345 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 | |
9346 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6 | |
7b6859fb | 9347 | u8 flags4; |
21dd79e8 TT |
9348 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 |
9349 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0 | |
9350 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 | |
9351 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2 | |
9352 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 | |
9353 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4 | |
9354 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3 | |
9355 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6 | |
7b6859fb | 9356 | u8 flags5; |
21dd79e8 TT |
9357 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3 |
9358 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0 | |
9359 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3 | |
9360 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2 | |
9361 | #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 | |
9362 | #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4 | |
9363 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3 | |
9364 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6 | |
7b6859fb | 9365 | u8 flags6; |
21dd79e8 TT |
9366 | #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3 |
9367 | #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0 | |
9368 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3 | |
9369 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2 | |
9370 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3 | |
9371 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4 | |
9372 | #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 | |
9373 | #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 | |
7b6859fb | 9374 | u8 flags7; |
21dd79e8 TT |
9375 | #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 |
9376 | #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 | |
9377 | #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 | |
9378 | #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2 | |
9379 | #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 | |
9380 | #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
9381 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 | |
9382 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6 | |
9383 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 | |
9384 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7 | |
7b6859fb | 9385 | u8 flags8; |
21dd79e8 TT |
9386 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 |
9387 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0 | |
9388 | #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 | |
9389 | #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 | |
9390 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 | |
9391 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2 | |
9392 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 | |
9393 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3 | |
9394 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 | |
9395 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4 | |
9396 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 | |
9397 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5 | |
9398 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 | |
9399 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6 | |
9400 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1 | |
9401 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7 | |
7b6859fb | 9402 | u8 flags9; |
21dd79e8 TT |
9403 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 |
9404 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0 | |
9405 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1 | |
9406 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1 | |
9407 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1 | |
9408 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2 | |
9409 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1 | |
9410 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3 | |
9411 | #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 | |
9412 | #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4 | |
9413 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1 | |
9414 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5 | |
9415 | #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1 | |
9416 | #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6 | |
9417 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1 | |
9418 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7 | |
7b6859fb | 9419 | u8 flags10; |
21dd79e8 TT |
9420 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1 |
9421 | #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0 | |
9422 | #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 | |
9423 | #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 | |
9424 | #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 | |
9425 | #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 | |
9426 | #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1 | |
9427 | #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3 | |
9428 | #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
9429 | #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
50bc60cb MK |
9430 | #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK 0x1 |
9431 | #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_SHIFT 5 | |
21dd79e8 TT |
9432 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 |
9433 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6 | |
9434 | #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1 | |
9435 | #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7 | |
7b6859fb | 9436 | u8 flags11; |
21dd79e8 TT |
9437 | #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 |
9438 | #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 | |
9439 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
9440 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1 | |
9441 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1 | |
9442 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2 | |
9443 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
9444 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
9445 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
9446 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
9447 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
9448 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5 | |
9449 | #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
9450 | #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
9451 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1 | |
9452 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7 | |
7b6859fb | 9453 | u8 flags12; |
21dd79e8 TT |
9454 | #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1 |
9455 | #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0 | |
9456 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1 | |
9457 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1 | |
9458 | #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
9459 | #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
9460 | #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
9461 | #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
9462 | #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1 | |
9463 | #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4 | |
9464 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
9465 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
9466 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1 | |
9467 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6 | |
9468 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1 | |
9469 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7 | |
7b6859fb | 9470 | u8 flags13; |
21dd79e8 TT |
9471 | #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1 |
9472 | #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0 | |
9473 | #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1 | |
9474 | #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1 | |
9475 | #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1 | |
9476 | #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2 | |
9477 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1 | |
9478 | #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3 | |
9479 | #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
9480 | #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
9481 | #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1 | |
9482 | #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5 | |
9483 | #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
9484 | #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
9485 | #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
9486 | #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
7b6859fb | 9487 | u8 flags14; |
21dd79e8 TT |
9488 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1 |
9489 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0 | |
9490 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1 | |
9491 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1 | |
9492 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1 | |
9493 | #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2 | |
9494 | #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1 | |
9495 | #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3 | |
9496 | #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 | |
9497 | #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 | |
9498 | #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 | |
9499 | #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 | |
50bc60cb MK |
9500 | #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK 0x3 |
9501 | #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_SHIFT 6 | |
7b6859fb MY |
9502 | u8 byte2; |
9503 | __le16 physical_q0; | |
9504 | __le16 physical_q1; | |
9505 | __le16 sq_comp_cons; | |
9506 | __le16 sq_tx_cons; | |
9507 | __le16 sq_prod; | |
9508 | __le16 word5; | |
9509 | __le16 conn_dpi; | |
9510 | u8 byte3; | |
9511 | u8 byte4; | |
9512 | u8 byte5; | |
9513 | u8 byte6; | |
9514 | __le32 reg0; | |
9515 | __le32 reg1; | |
9516 | __le32 reg2; | |
9517 | __le32 more_to_send_seq; | |
9518 | __le32 reg4; | |
50bc60cb | 9519 | __le32 rewinded_snd_max_or_term_opcode; |
7b6859fb MY |
9520 | __le32 rd_msn; |
9521 | __le16 irq_prod_via_msdm; | |
9522 | __le16 irq_cons; | |
9523 | __le16 hq_cons_th_or_mpa_data; | |
9524 | __le16 hq_cons; | |
9525 | __le32 atom_msn; | |
9526 | __le32 orq_cons; | |
9527 | __le32 orq_cons_th; | |
9528 | u8 byte7; | |
7b6859fb | 9529 | u8 wqe_data_pad_bytes; |
50bc60cb | 9530 | u8 max_ord; |
7b6859fb MY |
9531 | u8 former_hq_prod; |
9532 | u8 irq_prod_via_msem; | |
9533 | u8 byte12; | |
9534 | u8 max_pkt_pdu_size_lo; | |
9535 | u8 max_pkt_pdu_size_hi; | |
9536 | u8 byte15; | |
9537 | u8 e5_reserved; | |
9538 | __le16 e5_reserved4; | |
9539 | __le32 reg10; | |
9540 | __le32 reg11; | |
9541 | __le32 shared_queue_page_addr_lo; | |
9542 | __le32 shared_queue_page_addr_hi; | |
9543 | __le32 reg14; | |
9544 | __le32 reg15; | |
9545 | __le32 reg16; | |
9546 | __le32 reg17; | |
9547 | }; | |
9548 | ||
21dd79e8 | 9549 | struct e4_tstorm_iwarp_conn_ag_ctx { |
7b6859fb MY |
9550 | u8 reserved0; |
9551 | u8 state; | |
9552 | u8 flags0; | |
21dd79e8 TT |
9553 | #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
9554 | #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
9555 | #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 | |
9556 | #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 | |
9557 | #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1 | |
9558 | #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2 | |
50bc60cb MK |
9559 | #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK 0x1 |
9560 | #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_SHIFT 3 | |
21dd79e8 TT |
9561 | #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 |
9562 | #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 | |
9563 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 | |
9564 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 | |
9565 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 | |
9566 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6 | |
7b6859fb | 9567 | u8 flags1; |
21dd79e8 TT |
9568 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3 |
9569 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0 | |
9570 | #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3 | |
9571 | #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2 | |
9572 | #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 | |
9573 | #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 | |
9574 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 | |
9575 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6 | |
7b6859fb | 9576 | u8 flags2; |
21dd79e8 TT |
9577 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 |
9578 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0 | |
9579 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 | |
9580 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2 | |
9581 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 | |
9582 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4 | |
9583 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 | |
9584 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6 | |
7b6859fb | 9585 | u8 flags3; |
da090917 TT |
9586 | #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3 |
9587 | #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0 | |
21dd79e8 TT |
9588 | #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3 |
9589 | #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2 | |
9590 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 | |
9591 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4 | |
9592 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1 | |
9593 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5 | |
9594 | #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1 | |
9595 | #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6 | |
9596 | #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 | |
9597 | #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 | |
7b6859fb | 9598 | u8 flags4; |
21dd79e8 TT |
9599 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 |
9600 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0 | |
9601 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 | |
9602 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1 | |
9603 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 | |
9604 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2 | |
9605 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 | |
9606 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3 | |
9607 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 | |
9608 | #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4 | |
da090917 TT |
9609 | #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1 |
9610 | #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_SHIFT 5 | |
21dd79e8 TT |
9611 | #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1 |
9612 | #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6 | |
9613 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
9614 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
7b6859fb | 9615 | u8 flags5; |
21dd79e8 TT |
9616 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 |
9617 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
9618 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
9619 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
9620 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
9621 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
9622 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
9623 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
9624 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
9625 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
9626 | #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1 | |
9627 | #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5 | |
9628 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
9629 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
9630 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
9631 | #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
7b6859fb MY |
9632 | __le32 reg0; |
9633 | __le32 reg1; | |
9634 | __le32 unaligned_nxt_seq; | |
9635 | __le32 reg3; | |
9636 | __le32 reg4; | |
9637 | __le32 reg5; | |
9638 | __le32 reg6; | |
9639 | __le32 reg7; | |
9640 | __le32 reg8; | |
9641 | u8 orq_cache_idx; | |
9642 | u8 hq_prod; | |
9643 | __le16 sq_tx_cons_th; | |
9644 | u8 orq_prod; | |
9645 | u8 irq_cons; | |
9646 | __le16 sq_tx_cons; | |
9647 | __le16 conn_dpi; | |
9648 | __le16 rq_prod; | |
9649 | __le32 snd_seq; | |
9650 | __le32 last_hq_sequence; | |
9651 | }; | |
9652 | ||
a2e7699e | 9653 | /* The iwarp storm context of Tstorm */ |
7b6859fb MY |
9654 | struct tstorm_iwarp_conn_st_ctx { |
9655 | __le32 reserved[60]; | |
9656 | }; | |
9657 | ||
a2e7699e | 9658 | /* The iwarp storm context of Mstorm */ |
7b6859fb MY |
9659 | struct mstorm_iwarp_conn_st_ctx { |
9660 | __le32 reserved[32]; | |
9661 | }; | |
9662 | ||
a2e7699e | 9663 | /* The iwarp storm context of Ustorm */ |
7b6859fb MY |
9664 | struct ustorm_iwarp_conn_st_ctx { |
9665 | __le32 reserved[24]; | |
9666 | }; | |
9667 | ||
a2e7699e | 9668 | /* iwarp connection context */ |
21dd79e8 | 9669 | struct e4_iwarp_conn_context { |
7b6859fb MY |
9670 | struct ystorm_iwarp_conn_st_ctx ystorm_st_context; |
9671 | struct regpair ystorm_st_padding[2]; | |
9672 | struct pstorm_iwarp_conn_st_ctx pstorm_st_context; | |
9673 | struct regpair pstorm_st_padding[2]; | |
9674 | struct xstorm_iwarp_conn_st_ctx xstorm_st_context; | |
21dd79e8 TT |
9675 | struct e4_xstorm_iwarp_conn_ag_ctx xstorm_ag_context; |
9676 | struct e4_tstorm_iwarp_conn_ag_ctx tstorm_ag_context; | |
7b6859fb | 9677 | struct timers_context timer_context; |
21dd79e8 | 9678 | struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context; |
7b6859fb MY |
9679 | struct tstorm_iwarp_conn_st_ctx tstorm_st_context; |
9680 | struct regpair tstorm_st_padding[2]; | |
9681 | struct mstorm_iwarp_conn_st_ctx mstorm_st_context; | |
9682 | struct ustorm_iwarp_conn_st_ctx ustorm_st_context; | |
9683 | }; | |
9684 | ||
a2e7699e | 9685 | /* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */ |
7b6859fb MY |
9686 | struct iwarp_create_qp_ramrod_data { |
9687 | u8 flags; | |
9688 | #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 | |
a2e7699e TT |
9689 | #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0 |
9690 | #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 | |
9691 | #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1 | |
9692 | #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 | |
9693 | #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 | |
9694 | #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 | |
9695 | #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 | |
9696 | #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 | |
9697 | #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 | |
9698 | #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1 | |
9699 | #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5 | |
50bc60cb MK |
9700 | #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK 0x1 |
9701 | #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_SHIFT 6 | |
9702 | #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x1 | |
9703 | #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 7 | |
7b6859fb MY |
9704 | u8 reserved1; |
9705 | __le16 pd; | |
9706 | __le16 sq_num_pages; | |
9707 | __le16 rq_num_pages; | |
9708 | __le32 reserved3[2]; | |
9709 | struct regpair qp_handle_for_cqe; | |
9710 | struct rdma_srq_id srq_id; | |
9711 | __le32 cq_cid_for_sq; | |
9712 | __le32 cq_cid_for_rq; | |
9713 | __le16 dpi; | |
9714 | __le16 physical_q0; | |
9715 | __le16 physical_q1; | |
9716 | u8 reserved2[6]; | |
9717 | }; | |
9718 | ||
a2e7699e | 9719 | /* iWARP completion queue types */ |
7b6859fb MY |
9720 | enum iwarp_eqe_async_opcode { |
9721 | IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE, | |
9722 | IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED, | |
9723 | IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE, | |
9724 | IWARP_EVENT_TYPE_ASYNC_CID_CLEANED, | |
9725 | IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED, | |
9726 | IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE, | |
9727 | IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW, | |
9728 | MAX_IWARP_EQE_ASYNC_OPCODE | |
9729 | }; | |
9730 | ||
9731 | struct iwarp_eqe_data_mpa_async_completion { | |
9732 | __le16 ulp_data_len; | |
9733 | u8 reserved[6]; | |
9734 | }; | |
9735 | ||
9736 | struct iwarp_eqe_data_tcp_async_completion { | |
9737 | __le16 ulp_data_len; | |
9738 | u8 mpa_handshake_mode; | |
9739 | u8 reserved[5]; | |
9740 | }; | |
9741 | ||
a2e7699e | 9742 | /* iWARP completion queue types */ |
7b6859fb MY |
9743 | enum iwarp_eqe_sync_opcode { |
9744 | IWARP_EVENT_TYPE_TCP_OFFLOAD = | |
9745 | 11, | |
9746 | IWARP_EVENT_TYPE_MPA_OFFLOAD, | |
9747 | IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR, | |
9748 | IWARP_EVENT_TYPE_CREATE_QP, | |
9749 | IWARP_EVENT_TYPE_QUERY_QP, | |
9750 | IWARP_EVENT_TYPE_MODIFY_QP, | |
9751 | IWARP_EVENT_TYPE_DESTROY_QP, | |
50bc60cb | 9752 | IWARP_EVENT_TYPE_ABORT_TCP_OFFLOAD, |
7b6859fb MY |
9753 | MAX_IWARP_EQE_SYNC_OPCODE |
9754 | }; | |
9755 | ||
a2e7699e | 9756 | /* iWARP EQE completion status */ |
7b6859fb MY |
9757 | enum iwarp_fw_return_code { |
9758 | IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 5, | |
9759 | IWARP_CONN_ERROR_TCP_CONNECTION_RST, | |
9760 | IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT, | |
9761 | IWARP_CONN_ERROR_MPA_ERROR_REJECT, | |
9762 | IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER, | |
9763 | IWARP_CONN_ERROR_MPA_RST, | |
9764 | IWARP_CONN_ERROR_MPA_FIN, | |
9765 | IWARP_CONN_ERROR_MPA_RTR_MISMATCH, | |
9766 | IWARP_CONN_ERROR_MPA_INSUF_IRD, | |
9767 | IWARP_CONN_ERROR_MPA_INVALID_PACKET, | |
9768 | IWARP_CONN_ERROR_MPA_LOCAL_ERROR, | |
9769 | IWARP_CONN_ERROR_MPA_TIMEOUT, | |
9770 | IWARP_CONN_ERROR_MPA_TERMINATE, | |
9771 | IWARP_QP_IN_ERROR_GOOD_CLOSE, | |
9772 | IWARP_QP_IN_ERROR_BAD_CLOSE, | |
9773 | IWARP_EXCEPTION_DETECTED_LLP_CLOSED, | |
9774 | IWARP_EXCEPTION_DETECTED_LLP_RESET, | |
9775 | IWARP_EXCEPTION_DETECTED_IRQ_FULL, | |
9776 | IWARP_EXCEPTION_DETECTED_RQ_EMPTY, | |
50bc60cb MK |
9777 | IWARP_EXCEPTION_DETECTED_SRQ_EMPTY, |
9778 | IWARP_EXCEPTION_DETECTED_SRQ_LIMIT, | |
7b6859fb MY |
9779 | IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT, |
9780 | IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR, | |
9781 | IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW, | |
9782 | IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC, | |
9783 | IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR, | |
9784 | IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR, | |
9785 | IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED, | |
9786 | MAX_IWARP_FW_RETURN_CODE | |
9787 | }; | |
9788 | ||
a2e7699e | 9789 | /* unaligned opaque data received from LL2 */ |
7b6859fb MY |
9790 | struct iwarp_init_func_params { |
9791 | u8 ll2_ooo_q_index; | |
9792 | u8 reserved1[7]; | |
9793 | }; | |
9794 | ||
a2e7699e | 9795 | /* iwarp func init ramrod data */ |
7b6859fb MY |
9796 | struct iwarp_init_func_ramrod_data { |
9797 | struct rdma_init_func_ramrod_data rdma; | |
9798 | struct tcp_init_params tcp; | |
9799 | struct iwarp_init_func_params iwarp; | |
9800 | }; | |
9801 | ||
a2e7699e | 9802 | /* iWARP QP - possible states to transition to */ |
7b6859fb MY |
9803 | enum iwarp_modify_qp_new_state_type { |
9804 | IWARP_MODIFY_QP_STATE_CLOSING = 1, | |
a2e7699e | 9805 | IWARP_MODIFY_QP_STATE_ERROR = 2, |
7b6859fb MY |
9806 | MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE |
9807 | }; | |
9808 | ||
a2e7699e | 9809 | /* iwarp modify qp responder ramrod data */ |
7b6859fb MY |
9810 | struct iwarp_modify_qp_ramrod_data { |
9811 | __le16 transition_to_state; | |
9812 | __le16 flags; | |
a2e7699e TT |
9813 | #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 |
9814 | #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0 | |
9815 | #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 | |
9816 | #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1 | |
9817 | #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 | |
9818 | #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2 | |
9819 | #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1 | |
7b6859fb MY |
9820 | #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3 |
9821 | #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 | |
a2e7699e | 9822 | #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4 |
50bc60cb MK |
9823 | #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1 |
9824 | #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 5 | |
9825 | #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x3FF | |
9826 | #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 6 | |
9827 | __le16 physical_q0; | |
9828 | __le16 physical_q1; | |
9829 | __le32 reserved1[10]; | |
7b6859fb MY |
9830 | }; |
9831 | ||
a2e7699e | 9832 | /* MPA params for Enhanced mode */ |
7b6859fb MY |
9833 | struct mpa_rq_params { |
9834 | __le32 ird; | |
9835 | __le32 ord; | |
9836 | }; | |
9837 | ||
a2e7699e | 9838 | /* MPA host Address-Len for private data */ |
7b6859fb MY |
9839 | struct mpa_ulp_buffer { |
9840 | struct regpair addr; | |
9841 | __le16 len; | |
9842 | __le16 reserved[3]; | |
9843 | }; | |
9844 | ||
a2e7699e | 9845 | /* iWARP MPA offload params common to Basic and Enhanced modes */ |
7b6859fb MY |
9846 | struct mpa_outgoing_params { |
9847 | u8 crc_needed; | |
9848 | u8 reject; | |
9849 | u8 reserved[6]; | |
9850 | struct mpa_rq_params out_rq; | |
9851 | struct mpa_ulp_buffer outgoing_ulp_buffer; | |
9852 | }; | |
9853 | ||
a2e7699e TT |
9854 | /* iWARP MPA offload params passed by driver to FW in MPA Offload Request |
9855 | * Ramrod. | |
9856 | */ | |
7b6859fb MY |
9857 | struct iwarp_mpa_offload_ramrod_data { |
9858 | struct mpa_outgoing_params common; | |
9859 | __le32 tcp_cid; | |
9860 | u8 mode; | |
9861 | u8 tcp_connect_side; | |
9862 | u8 rtr_pref; | |
9863 | #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7 | |
a2e7699e TT |
9864 | #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0 |
9865 | #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F | |
9866 | #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3 | |
7b6859fb MY |
9867 | u8 reserved2; |
9868 | struct mpa_ulp_buffer incoming_ulp_buffer; | |
9869 | struct regpair async_eqe_output_buf; | |
9870 | struct regpair handle_for_async; | |
9871 | struct regpair shared_queue_addr; | |
da090917 | 9872 | __le16 rcv_wnd; |
7b6859fb | 9873 | u8 stats_counter_id; |
da090917 | 9874 | u8 reserved3[13]; |
7b6859fb MY |
9875 | }; |
9876 | ||
a2e7699e | 9877 | /* iWARP TCP connection offload params passed by driver to FW */ |
7b6859fb MY |
9878 | struct iwarp_offload_params { |
9879 | struct mpa_ulp_buffer incoming_ulp_buffer; | |
9880 | struct regpair async_eqe_output_buf; | |
9881 | struct regpair handle_for_async; | |
9882 | __le16 physical_q0; | |
9883 | __le16 physical_q1; | |
9884 | u8 stats_counter_id; | |
9885 | u8 mpa_mode; | |
9886 | u8 reserved[10]; | |
9887 | }; | |
9888 | ||
a2e7699e | 9889 | /* iWARP query QP output params */ |
7b6859fb MY |
9890 | struct iwarp_query_qp_output_params { |
9891 | __le32 flags; | |
9892 | #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 | |
a2e7699e | 9893 | #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 |
7b6859fb | 9894 | #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF |
a2e7699e | 9895 | #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 |
7b6859fb MY |
9896 | u8 reserved1[4]; |
9897 | }; | |
9898 | ||
a2e7699e | 9899 | /* iWARP query QP ramrod data */ |
7b6859fb MY |
9900 | struct iwarp_query_qp_ramrod_data { |
9901 | struct regpair output_params_addr; | |
9902 | }; | |
9903 | ||
a2e7699e | 9904 | /* iWARP Ramrod Command IDs */ |
7b6859fb | 9905 | enum iwarp_ramrod_cmd_id { |
a2e7699e | 9906 | IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 11, |
7b6859fb MY |
9907 | IWARP_RAMROD_CMD_ID_MPA_OFFLOAD, |
9908 | IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR, | |
9909 | IWARP_RAMROD_CMD_ID_CREATE_QP, | |
9910 | IWARP_RAMROD_CMD_ID_QUERY_QP, | |
9911 | IWARP_RAMROD_CMD_ID_MODIFY_QP, | |
9912 | IWARP_RAMROD_CMD_ID_DESTROY_QP, | |
50bc60cb | 9913 | IWARP_RAMROD_CMD_ID_ABORT_TCP_OFFLOAD, |
7b6859fb MY |
9914 | MAX_IWARP_RAMROD_CMD_ID |
9915 | }; | |
9916 | ||
a2e7699e | 9917 | /* Per PF iWARP retransmit path statistics */ |
7b6859fb MY |
9918 | struct iwarp_rxmit_stats_drv { |
9919 | struct regpair tx_go_to_slow_start_event_cnt; | |
9920 | struct regpair tx_fast_retransmit_event_cnt; | |
9921 | }; | |
9922 | ||
a2e7699e TT |
9923 | /* iWARP and TCP connection offload params passed by driver to FW in iWARP |
9924 | * offload ramrod. | |
9925 | */ | |
7b6859fb MY |
9926 | struct iwarp_tcp_offload_ramrod_data { |
9927 | struct iwarp_offload_params iwarp; | |
9928 | struct tcp_offload_params_opt2 tcp; | |
9929 | }; | |
9930 | ||
a2e7699e | 9931 | /* iWARP MPA negotiation types */ |
7b6859fb MY |
9932 | enum mpa_negotiation_mode { |
9933 | MPA_NEGOTIATION_TYPE_BASIC = 1, | |
9934 | MPA_NEGOTIATION_TYPE_ENHANCED = 2, | |
9935 | MAX_MPA_NEGOTIATION_MODE | |
9936 | }; | |
9937 | ||
a2e7699e | 9938 | /* iWARP MPA Enhanced mode RTR types */ |
7b6859fb MY |
9939 | enum mpa_rtr_type { |
9940 | MPA_RTR_TYPE_NONE = 0, | |
9941 | MPA_RTR_TYPE_ZERO_SEND = 1, | |
9942 | MPA_RTR_TYPE_ZERO_WRITE = 2, | |
9943 | MPA_RTR_TYPE_ZERO_SEND_AND_WRITE = 3, | |
9944 | MPA_RTR_TYPE_ZERO_READ = 4, | |
9945 | MPA_RTR_TYPE_ZERO_SEND_AND_READ = 5, | |
9946 | MPA_RTR_TYPE_ZERO_WRITE_AND_READ = 6, | |
9947 | MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ = 7, | |
9948 | MAX_MPA_RTR_TYPE | |
9949 | }; | |
9950 | ||
a2e7699e | 9951 | /* unaligned opaque data received from LL2 */ |
7b6859fb MY |
9952 | struct unaligned_opaque_data { |
9953 | __le16 first_mpa_offset; | |
9954 | u8 tcp_payload_offset; | |
9955 | u8 flags; | |
9956 | #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1 | |
a2e7699e TT |
9957 | #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0 |
9958 | #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1 | |
9959 | #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1 | |
9960 | #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F | |
9961 | #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2 | |
7b6859fb MY |
9962 | __le32 cid; |
9963 | }; | |
9964 | ||
21dd79e8 | 9965 | struct e4_mstorm_iwarp_conn_ag_ctx { |
7b6859fb MY |
9966 | u8 reserved; |
9967 | u8 state; | |
9968 | u8 flags0; | |
21dd79e8 TT |
9969 | #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
9970 | #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
9971 | #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 | |
9972 | #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 | |
9973 | #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 | |
9974 | #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2 | |
9975 | #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 | |
9976 | #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 | |
9977 | #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 | |
9978 | #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 | |
7b6859fb | 9979 | u8 flags1; |
21dd79e8 TT |
9980 | #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1 |
9981 | #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0 | |
9982 | #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 | |
9983 | #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 | |
9984 | #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 | |
9985 | #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 | |
9986 | #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
9987 | #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
9988 | #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
9989 | #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
9990 | #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
9991 | #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
9992 | #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1 | |
9993 | #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6 | |
9994 | #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
9995 | #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
7b6859fb MY |
9996 | __le16 rcq_cons; |
9997 | __le16 rcq_cons_th; | |
9998 | __le32 reg0; | |
9999 | __le32 reg1; | |
10000 | }; | |
10001 | ||
21dd79e8 | 10002 | struct e4_ustorm_iwarp_conn_ag_ctx { |
7b6859fb MY |
10003 | u8 reserved; |
10004 | u8 byte1; | |
10005 | u8 flags0; | |
21dd79e8 TT |
10006 | #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
10007 | #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
10008 | #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 | |
10009 | #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 | |
10010 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 | |
10011 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 | |
10012 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 | |
10013 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 | |
10014 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 | |
10015 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 | |
7b6859fb | 10016 | u8 flags1; |
21dd79e8 TT |
10017 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3 |
10018 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0 | |
10019 | #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 | |
10020 | #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 | |
10021 | #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 | |
10022 | #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 | |
10023 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 | |
10024 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6 | |
7b6859fb | 10025 | u8 flags2; |
21dd79e8 TT |
10026 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 |
10027 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 | |
10028 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 | |
10029 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 | |
10030 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 | |
10031 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 | |
10032 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1 | |
10033 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3 | |
10034 | #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 | |
10035 | #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 | |
10036 | #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 | |
10037 | #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 | |
10038 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 | |
10039 | #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6 | |
10040 | #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 | |
10041 | #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 | |
7b6859fb | 10042 | u8 flags3; |
21dd79e8 TT |
10043 | #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1 |
10044 | #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0 | |
10045 | #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
10046 | #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
10047 | #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
10048 | #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
10049 | #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
10050 | #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
10051 | #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
10052 | #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
10053 | #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
10054 | #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
10055 | #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
10056 | #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
10057 | #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
10058 | #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
7b6859fb MY |
10059 | u8 byte2; |
10060 | u8 byte3; | |
10061 | __le16 word0; | |
10062 | __le16 word1; | |
10063 | __le32 cq_cons; | |
10064 | __le32 cq_se_prod; | |
10065 | __le32 cq_prod; | |
10066 | __le32 reg3; | |
10067 | __le16 word2; | |
10068 | __le16 word3; | |
10069 | }; | |
10070 | ||
21dd79e8 | 10071 | struct e4_ystorm_iwarp_conn_ag_ctx { |
7b6859fb MY |
10072 | u8 byte0; |
10073 | u8 byte1; | |
10074 | u8 flags0; | |
21dd79e8 TT |
10075 | #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1 |
10076 | #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0 | |
10077 | #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 | |
10078 | #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 | |
10079 | #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 | |
10080 | #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 | |
10081 | #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 | |
10082 | #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 | |
10083 | #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 | |
10084 | #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 | |
7b6859fb | 10085 | u8 flags1; |
21dd79e8 TT |
10086 | #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 |
10087 | #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 | |
10088 | #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 | |
10089 | #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 | |
10090 | #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 | |
10091 | #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 | |
10092 | #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
10093 | #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
10094 | #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
10095 | #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
10096 | #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
10097 | #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
10098 | #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
10099 | #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
10100 | #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
10101 | #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
7b6859fb MY |
10102 | u8 byte2; |
10103 | u8 byte3; | |
10104 | __le16 word0; | |
10105 | __le32 reg0; | |
10106 | __le32 reg1; | |
10107 | __le16 word1; | |
10108 | __le16 word2; | |
10109 | __le16 word3; | |
10110 | __le16 word4; | |
10111 | __le32 reg2; | |
10112 | __le32 reg3; | |
10113 | }; | |
10114 | ||
a2e7699e | 10115 | /* The fcoe storm context of Ystorm */ |
1e128c81 AE |
10116 | struct ystorm_fcoe_conn_st_ctx { |
10117 | u8 func_mode; | |
10118 | u8 cos; | |
10119 | u8 conf_version; | |
10120 | u8 eth_hdr_size; | |
10121 | __le16 stat_ram_addr; | |
10122 | __le16 mtu; | |
10123 | __le16 max_fc_payload_len; | |
10124 | __le16 tx_max_fc_pay_len; | |
10125 | u8 fcp_cmd_size; | |
10126 | u8 fcp_rsp_size; | |
10127 | __le16 mss; | |
10128 | struct regpair reserved; | |
be086e7c | 10129 | __le16 min_frame_size; |
1e128c81 | 10130 | u8 protection_info_flags; |
a2e7699e TT |
10131 | #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 |
10132 | #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0 | |
10133 | #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 | |
10134 | #define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1 | |
10135 | #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F | |
10136 | #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2 | |
1e128c81 AE |
10137 | u8 dst_protection_per_mss; |
10138 | u8 src_protection_per_mss; | |
10139 | u8 ptu_log_page_size; | |
10140 | u8 flags; | |
a2e7699e TT |
10141 | #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 |
10142 | #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0 | |
10143 | #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 | |
10144 | #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1 | |
10145 | #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F | |
10146 | #define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2 | |
1e128c81 | 10147 | u8 fcp_xfer_size; |
1e128c81 AE |
10148 | }; |
10149 | ||
a2e7699e | 10150 | /* FCoE 16-bits vlan structure */ |
1e128c81 AE |
10151 | struct fcoe_vlan_fields { |
10152 | __le16 fields; | |
a2e7699e TT |
10153 | #define FCOE_VLAN_FIELDS_VID_MASK 0xFFF |
10154 | #define FCOE_VLAN_FIELDS_VID_SHIFT 0 | |
10155 | #define FCOE_VLAN_FIELDS_CLI_MASK 0x1 | |
10156 | #define FCOE_VLAN_FIELDS_CLI_SHIFT 12 | |
10157 | #define FCOE_VLAN_FIELDS_PRI_MASK 0x7 | |
10158 | #define FCOE_VLAN_FIELDS_PRI_SHIFT 13 | |
1e128c81 AE |
10159 | }; |
10160 | ||
a2e7699e | 10161 | /* FCoE 16-bits vlan union */ |
1e128c81 AE |
10162 | union fcoe_vlan_field_union { |
10163 | struct fcoe_vlan_fields fields; | |
10164 | __le16 val; | |
10165 | }; | |
10166 | ||
a2e7699e | 10167 | /* FCoE 16-bits vlan, vif union */ |
1e128c81 AE |
10168 | union fcoe_vlan_vif_field_union { |
10169 | union fcoe_vlan_field_union vlan; | |
10170 | __le16 vif; | |
10171 | }; | |
10172 | ||
a2e7699e | 10173 | /* Ethernet context section */ |
1e128c81 AE |
10174 | struct pstorm_fcoe_eth_context_section { |
10175 | u8 remote_addr_3; | |
10176 | u8 remote_addr_2; | |
10177 | u8 remote_addr_1; | |
10178 | u8 remote_addr_0; | |
10179 | u8 local_addr_1; | |
10180 | u8 local_addr_0; | |
10181 | u8 remote_addr_5; | |
10182 | u8 remote_addr_4; | |
10183 | u8 local_addr_5; | |
10184 | u8 local_addr_4; | |
10185 | u8 local_addr_3; | |
10186 | u8 local_addr_2; | |
10187 | union fcoe_vlan_vif_field_union vif_outer_vlan; | |
10188 | __le16 vif_outer_eth_type; | |
10189 | union fcoe_vlan_vif_field_union inner_vlan; | |
10190 | __le16 inner_eth_type; | |
10191 | }; | |
10192 | ||
a2e7699e | 10193 | /* The fcoe storm context of Pstorm */ |
1e128c81 AE |
10194 | struct pstorm_fcoe_conn_st_ctx { |
10195 | u8 func_mode; | |
10196 | u8 cos; | |
10197 | u8 conf_version; | |
10198 | u8 rsrv; | |
10199 | __le16 stat_ram_addr; | |
10200 | __le16 mss; | |
10201 | struct regpair abts_cleanup_addr; | |
10202 | struct pstorm_fcoe_eth_context_section eth; | |
10203 | u8 sid_2; | |
10204 | u8 sid_1; | |
10205 | u8 sid_0; | |
10206 | u8 flags; | |
a2e7699e TT |
10207 | #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1 |
10208 | #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0 | |
10209 | #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1 | |
10210 | #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1 | |
10211 | #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 | |
10212 | #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2 | |
10213 | #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 | |
10214 | #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3 | |
da090917 TT |
10215 | #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK 0x1 |
10216 | #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT 4 | |
10217 | #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x7 | |
10218 | #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 5 | |
1e128c81 AE |
10219 | u8 did_2; |
10220 | u8 did_1; | |
10221 | u8 did_0; | |
10222 | u8 src_mac_index; | |
10223 | __le16 rec_rr_tov_val; | |
10224 | u8 q_relative_offset; | |
10225 | u8 reserved1; | |
10226 | }; | |
10227 | ||
a2e7699e | 10228 | /* The fcoe storm context of Xstorm */ |
1e128c81 AE |
10229 | struct xstorm_fcoe_conn_st_ctx { |
10230 | u8 func_mode; | |
10231 | u8 src_mac_index; | |
10232 | u8 conf_version; | |
10233 | u8 cached_wqes_avail; | |
10234 | __le16 stat_ram_addr; | |
10235 | u8 flags; | |
a2e7699e TT |
10236 | #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1 |
10237 | #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0 | |
10238 | #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 | |
10239 | #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1 | |
10240 | #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1 | |
10241 | #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2 | |
10242 | #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3 | |
10243 | #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3 | |
10244 | #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7 | |
10245 | #define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5 | |
1e128c81 AE |
10246 | u8 cached_wqes_offset; |
10247 | u8 reserved2; | |
10248 | u8 eth_hdr_size; | |
10249 | u8 seq_id; | |
10250 | u8 max_conc_seqs; | |
10251 | __le16 num_pages_in_pbl; | |
10252 | __le16 reserved; | |
10253 | struct regpair sq_pbl_addr; | |
10254 | struct regpair sq_curr_page_addr; | |
10255 | struct regpair sq_next_page_addr; | |
10256 | struct regpair xferq_pbl_addr; | |
10257 | struct regpair xferq_curr_page_addr; | |
10258 | struct regpair xferq_next_page_addr; | |
10259 | struct regpair respq_pbl_addr; | |
10260 | struct regpair respq_curr_page_addr; | |
10261 | struct regpair respq_next_page_addr; | |
10262 | __le16 mtu; | |
10263 | __le16 tx_max_fc_pay_len; | |
10264 | __le16 max_fc_payload_len; | |
10265 | __le16 min_frame_size; | |
10266 | __le16 sq_pbl_next_index; | |
10267 | __le16 respq_pbl_next_index; | |
10268 | u8 fcp_cmd_byte_credit; | |
10269 | u8 fcp_rsp_byte_credit; | |
10270 | __le16 protection_info; | |
a2e7699e TT |
10271 | #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1 |
10272 | #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0 | |
10273 | #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 | |
10274 | #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1 | |
10275 | #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 | |
10276 | #define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2 | |
10277 | #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1 | |
10278 | #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3 | |
10279 | #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF | |
10280 | #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4 | |
10281 | #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF | |
10282 | #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8 | |
1e128c81 AE |
10283 | __le16 xferq_pbl_next_index; |
10284 | __le16 page_size; | |
10285 | u8 mid_seq; | |
10286 | u8 fcp_xfer_byte_credit; | |
10287 | u8 reserved1[2]; | |
10288 | struct fcoe_wqe cached_wqes[16]; | |
10289 | }; | |
10290 | ||
21dd79e8 | 10291 | struct e4_xstorm_fcoe_conn_ag_ctx { |
1e128c81 | 10292 | u8 reserved0; |
da090917 | 10293 | u8 state; |
1e128c81 | 10294 | u8 flags0; |
21dd79e8 TT |
10295 | #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
10296 | #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
10297 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1 | |
10298 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1 | |
10299 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1 | |
10300 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2 | |
10301 | #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
10302 | #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
10303 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1 | |
10304 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4 | |
10305 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1 | |
10306 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5 | |
10307 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1 | |
10308 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6 | |
10309 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1 | |
10310 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7 | |
1e128c81 | 10311 | u8 flags1; |
21dd79e8 TT |
10312 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1 |
10313 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0 | |
10314 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1 | |
10315 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1 | |
10316 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1 | |
10317 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2 | |
10318 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1 | |
10319 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3 | |
10320 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1 | |
10321 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4 | |
10322 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1 | |
10323 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5 | |
10324 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1 | |
10325 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6 | |
10326 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1 | |
10327 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7 | |
1e128c81 | 10328 | u8 flags2; |
21dd79e8 TT |
10329 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 |
10330 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0 | |
10331 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 | |
10332 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2 | |
10333 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 | |
10334 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4 | |
10335 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 | |
10336 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6 | |
1e128c81 | 10337 | u8 flags3; |
21dd79e8 TT |
10338 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 |
10339 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0 | |
10340 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 | |
10341 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2 | |
10342 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 | |
10343 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4 | |
10344 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 | |
10345 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6 | |
1e128c81 | 10346 | u8 flags4; |
21dd79e8 TT |
10347 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 |
10348 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0 | |
10349 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 | |
10350 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2 | |
10351 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 | |
10352 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4 | |
10353 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3 | |
10354 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6 | |
1e128c81 | 10355 | u8 flags5; |
21dd79e8 TT |
10356 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3 |
10357 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0 | |
10358 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3 | |
10359 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2 | |
10360 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3 | |
10361 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4 | |
10362 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3 | |
10363 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6 | |
1e128c81 | 10364 | u8 flags6; |
21dd79e8 TT |
10365 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3 |
10366 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0 | |
10367 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3 | |
10368 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2 | |
10369 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3 | |
10370 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4 | |
10371 | #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3 | |
10372 | #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6 | |
1e128c81 | 10373 | u8 flags7; |
21dd79e8 TT |
10374 | #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 |
10375 | #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 | |
10376 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3 | |
10377 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2 | |
10378 | #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 | |
10379 | #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
10380 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 | |
10381 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6 | |
10382 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
10383 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7 | |
1e128c81 | 10384 | u8 flags8; |
21dd79e8 TT |
10385 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 |
10386 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0 | |
10387 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 | |
10388 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1 | |
10389 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 | |
10390 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2 | |
10391 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 | |
10392 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3 | |
10393 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 | |
10394 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4 | |
10395 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 | |
10396 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5 | |
10397 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 | |
10398 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6 | |
10399 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 | |
10400 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7 | |
1e128c81 | 10401 | u8 flags9; |
21dd79e8 TT |
10402 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 |
10403 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0 | |
10404 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1 | |
10405 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1 | |
10406 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1 | |
10407 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2 | |
10408 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1 | |
10409 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3 | |
10410 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1 | |
10411 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4 | |
10412 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1 | |
10413 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5 | |
10414 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1 | |
10415 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6 | |
10416 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1 | |
10417 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7 | |
1e128c81 | 10418 | u8 flags10; |
21dd79e8 TT |
10419 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1 |
10420 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0 | |
10421 | #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 | |
10422 | #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1 | |
10423 | #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 | |
10424 | #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 | |
10425 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1 | |
10426 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3 | |
10427 | #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
10428 | #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
10429 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1 | |
10430 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5 | |
10431 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1 | |
10432 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6 | |
10433 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1 | |
10434 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7 | |
1e128c81 | 10435 | u8 flags11; |
21dd79e8 TT |
10436 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1 |
10437 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0 | |
10438 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1 | |
10439 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1 | |
10440 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1 | |
10441 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2 | |
10442 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
10443 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
10444 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
10445 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
10446 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
10447 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5 | |
10448 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
10449 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
10450 | #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1 | |
10451 | #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7 | |
1e128c81 | 10452 | u8 flags12; |
21dd79e8 TT |
10453 | #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1 |
10454 | #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0 | |
10455 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1 | |
10456 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1 | |
10457 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
10458 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
10459 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
10460 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
10461 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1 | |
10462 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4 | |
10463 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
10464 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
10465 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1 | |
10466 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6 | |
10467 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1 | |
10468 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7 | |
1e128c81 | 10469 | u8 flags13; |
21dd79e8 TT |
10470 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1 |
10471 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0 | |
10472 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1 | |
10473 | #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1 | |
10474 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 | |
10475 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 | |
10476 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 | |
10477 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 | |
10478 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
10479 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
10480 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 | |
10481 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 | |
10482 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
10483 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
10484 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
10485 | #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
1e128c81 | 10486 | u8 flags14; |
21dd79e8 TT |
10487 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1 |
10488 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0 | |
10489 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1 | |
10490 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1 | |
10491 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1 | |
10492 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2 | |
10493 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1 | |
10494 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3 | |
10495 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1 | |
10496 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4 | |
10497 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1 | |
10498 | #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5 | |
10499 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3 | |
10500 | #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6 | |
1e128c81 AE |
10501 | u8 byte2; |
10502 | __le16 physical_q0; | |
10503 | __le16 word1; | |
10504 | __le16 word2; | |
10505 | __le16 sq_cons; | |
10506 | __le16 sq_prod; | |
10507 | __le16 xferq_prod; | |
10508 | __le16 xferq_cons; | |
10509 | u8 byte3; | |
10510 | u8 byte4; | |
10511 | u8 byte5; | |
10512 | u8 byte6; | |
10513 | __le32 remain_io; | |
10514 | __le32 reg1; | |
10515 | __le32 reg2; | |
10516 | __le32 reg3; | |
10517 | __le32 reg4; | |
10518 | __le32 reg5; | |
10519 | __le32 reg6; | |
10520 | __le16 respq_prod; | |
10521 | __le16 respq_cons; | |
10522 | __le16 word9; | |
10523 | __le16 word10; | |
10524 | __le32 reg7; | |
10525 | __le32 reg8; | |
10526 | }; | |
10527 | ||
a2e7699e | 10528 | /* The fcoe storm context of Ustorm */ |
1e128c81 AE |
10529 | struct ustorm_fcoe_conn_st_ctx { |
10530 | struct regpair respq_pbl_addr; | |
10531 | __le16 num_pages_in_pbl; | |
10532 | u8 ptu_log_page_size; | |
10533 | u8 log_page_size; | |
10534 | __le16 respq_prod; | |
10535 | u8 reserved[2]; | |
10536 | }; | |
10537 | ||
21dd79e8 | 10538 | struct e4_tstorm_fcoe_conn_ag_ctx { |
1e128c81 | 10539 | u8 reserved0; |
da090917 | 10540 | u8 state; |
1e128c81 | 10541 | u8 flags0; |
21dd79e8 TT |
10542 | #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
10543 | #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
10544 | #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 | |
10545 | #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 | |
10546 | #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1 | |
10547 | #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2 | |
10548 | #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1 | |
10549 | #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3 | |
10550 | #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1 | |
10551 | #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4 | |
10552 | #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1 | |
10553 | #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5 | |
10554 | #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3 | |
10555 | #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6 | |
1e128c81 | 10556 | u8 flags1; |
21dd79e8 TT |
10557 | #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 |
10558 | #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0 | |
10559 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 | |
10560 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2 | |
10561 | #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 | |
10562 | #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 | |
10563 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 | |
10564 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6 | |
1e128c81 | 10565 | u8 flags2; |
21dd79e8 TT |
10566 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 |
10567 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0 | |
10568 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 | |
10569 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2 | |
10570 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 | |
10571 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4 | |
10572 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 | |
10573 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6 | |
1e128c81 | 10574 | u8 flags3; |
21dd79e8 TT |
10575 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 |
10576 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0 | |
10577 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 | |
10578 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2 | |
10579 | #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1 | |
10580 | #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4 | |
10581 | #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 | |
10582 | #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 | |
10583 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 | |
10584 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6 | |
10585 | #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 | |
10586 | #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 | |
1e128c81 | 10587 | u8 flags4; |
21dd79e8 TT |
10588 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 |
10589 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0 | |
10590 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 | |
10591 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1 | |
10592 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 | |
10593 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2 | |
10594 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 | |
10595 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3 | |
10596 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 | |
10597 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4 | |
10598 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 | |
10599 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5 | |
10600 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 | |
10601 | #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6 | |
10602 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
10603 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
1e128c81 | 10604 | u8 flags5; |
21dd79e8 TT |
10605 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 |
10606 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
10607 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
10608 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
10609 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
10610 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
10611 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
10612 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
10613 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
10614 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
10615 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
10616 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
10617 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
10618 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
10619 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
10620 | #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
1e128c81 AE |
10621 | __le32 reg0; |
10622 | __le32 reg1; | |
10623 | }; | |
10624 | ||
21dd79e8 | 10625 | struct e4_ustorm_fcoe_conn_ag_ctx { |
1e128c81 AE |
10626 | u8 byte0; |
10627 | u8 byte1; | |
10628 | u8 flags0; | |
21dd79e8 TT |
10629 | #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 |
10630 | #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 | |
10631 | #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 | |
10632 | #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 | |
10633 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 | |
10634 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 | |
10635 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 | |
10636 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 | |
10637 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 | |
10638 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 | |
1e128c81 | 10639 | u8 flags1; |
21dd79e8 TT |
10640 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 |
10641 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0 | |
10642 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 | |
10643 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2 | |
10644 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 | |
10645 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4 | |
10646 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 | |
10647 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6 | |
1e128c81 | 10648 | u8 flags2; |
21dd79e8 TT |
10649 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 |
10650 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 | |
10651 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
10652 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 | |
10653 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 | |
10654 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 | |
10655 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 | |
10656 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3 | |
10657 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 | |
10658 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4 | |
10659 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 | |
10660 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5 | |
10661 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 | |
10662 | #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6 | |
10663 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
10664 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
1e128c81 | 10665 | u8 flags3; |
21dd79e8 TT |
10666 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 |
10667 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
10668 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
10669 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
10670 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
10671 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
10672 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
10673 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
10674 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
10675 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
10676 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
10677 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
10678 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
10679 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
10680 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
10681 | #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
1e128c81 AE |
10682 | u8 byte2; |
10683 | u8 byte3; | |
10684 | __le16 word0; | |
10685 | __le16 word1; | |
10686 | __le32 reg0; | |
10687 | __le32 reg1; | |
10688 | __le32 reg2; | |
10689 | __le32 reg3; | |
10690 | __le16 word2; | |
10691 | __le16 word3; | |
10692 | }; | |
10693 | ||
a2e7699e | 10694 | /* The fcoe storm context of Tstorm */ |
1e128c81 AE |
10695 | struct tstorm_fcoe_conn_st_ctx { |
10696 | __le16 stat_ram_addr; | |
10697 | __le16 rx_max_fc_payload_len; | |
10698 | __le16 e_d_tov_val; | |
10699 | u8 flags; | |
a2e7699e TT |
10700 | #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1 |
10701 | #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0 | |
10702 | #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1 | |
10703 | #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1 | |
10704 | #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F | |
10705 | #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2 | |
1e128c81 AE |
10706 | u8 timers_cleanup_invocation_cnt; |
10707 | __le32 reserved1[2]; | |
a2e7699e TT |
10708 | __le32 dst_mac_address_bytes_0_to_3; |
10709 | __le16 dst_mac_address_bytes_4_to_5; | |
1e128c81 AE |
10710 | __le16 ramrod_echo; |
10711 | u8 flags1; | |
a2e7699e TT |
10712 | #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3 |
10713 | #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0 | |
10714 | #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F | |
10715 | #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2 | |
10716 | u8 cq_relative_offset; | |
da090917 | 10717 | u8 cmdq_relative_offset; |
1e128c81 | 10718 | u8 bdq_resource_id; |
da090917 | 10719 | u8 reserved0[4]; |
1e128c81 AE |
10720 | }; |
10721 | ||
21dd79e8 | 10722 | struct e4_mstorm_fcoe_conn_ag_ctx { |
1e128c81 AE |
10723 | u8 byte0; |
10724 | u8 byte1; | |
10725 | u8 flags0; | |
21dd79e8 TT |
10726 | #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 |
10727 | #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 | |
10728 | #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 | |
10729 | #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 | |
10730 | #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 | |
10731 | #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 | |
10732 | #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 | |
10733 | #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 | |
10734 | #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 | |
10735 | #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 | |
1e128c81 | 10736 | u8 flags1; |
21dd79e8 TT |
10737 | #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 |
10738 | #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 | |
10739 | #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
10740 | #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 | |
10741 | #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 | |
10742 | #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 | |
10743 | #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
10744 | #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
10745 | #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
10746 | #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
10747 | #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
10748 | #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
10749 | #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
10750 | #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
10751 | #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
10752 | #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
1e128c81 AE |
10753 | __le16 word0; |
10754 | __le16 word1; | |
10755 | __le32 reg0; | |
10756 | __le32 reg1; | |
10757 | }; | |
10758 | ||
a2e7699e | 10759 | /* Fast path part of the fcoe storm context of Mstorm */ |
1e128c81 AE |
10760 | struct fcoe_mstorm_fcoe_conn_st_ctx_fp { |
10761 | __le16 xfer_prod; | |
da090917 TT |
10762 | u8 num_cqs; |
10763 | u8 reserved1; | |
1e128c81 AE |
10764 | u8 protection_info; |
10765 | #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1 | |
10766 | #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0 | |
10767 | #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1 | |
10768 | #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT 1 | |
10769 | #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F | |
10770 | #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT 2 | |
10771 | u8 q_relative_offset; | |
10772 | u8 reserved2[2]; | |
10773 | }; | |
10774 | ||
a2e7699e | 10775 | /* Non fast path part of the fcoe storm context of Mstorm */ |
1e128c81 AE |
10776 | struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp { |
10777 | __le16 conn_id; | |
10778 | __le16 stat_ram_addr; | |
10779 | __le16 num_pages_in_pbl; | |
10780 | u8 ptu_log_page_size; | |
10781 | u8 log_page_size; | |
10782 | __le16 unsolicited_cq_count; | |
10783 | __le16 cmdq_count; | |
10784 | u8 bdq_resource_id; | |
10785 | u8 reserved0[3]; | |
10786 | struct regpair xferq_pbl_addr; | |
10787 | struct regpair reserved1; | |
10788 | struct regpair reserved2[3]; | |
10789 | }; | |
10790 | ||
a2e7699e | 10791 | /* The fcoe storm context of Mstorm */ |
1e128c81 AE |
10792 | struct mstorm_fcoe_conn_st_ctx { |
10793 | struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp; | |
10794 | struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp; | |
10795 | }; | |
10796 | ||
a2e7699e | 10797 | /* fcoe connection context */ |
21dd79e8 | 10798 | struct e4_fcoe_conn_context { |
1e128c81 AE |
10799 | struct ystorm_fcoe_conn_st_ctx ystorm_st_context; |
10800 | struct pstorm_fcoe_conn_st_ctx pstorm_st_context; | |
10801 | struct regpair pstorm_st_padding[2]; | |
10802 | struct xstorm_fcoe_conn_st_ctx xstorm_st_context; | |
21dd79e8 | 10803 | struct e4_xstorm_fcoe_conn_ag_ctx xstorm_ag_context; |
1e128c81 AE |
10804 | struct regpair xstorm_ag_padding[6]; |
10805 | struct ustorm_fcoe_conn_st_ctx ustorm_st_context; | |
10806 | struct regpair ustorm_st_padding[2]; | |
21dd79e8 | 10807 | struct e4_tstorm_fcoe_conn_ag_ctx tstorm_ag_context; |
1e128c81 AE |
10808 | struct regpair tstorm_ag_padding[2]; |
10809 | struct timers_context timer_context; | |
21dd79e8 | 10810 | struct e4_ustorm_fcoe_conn_ag_ctx ustorm_ag_context; |
1e128c81 | 10811 | struct tstorm_fcoe_conn_st_ctx tstorm_st_context; |
21dd79e8 | 10812 | struct e4_mstorm_fcoe_conn_ag_ctx mstorm_ag_context; |
1e128c81 AE |
10813 | struct mstorm_fcoe_conn_st_ctx mstorm_st_context; |
10814 | }; | |
10815 | ||
a2e7699e TT |
10816 | /* FCoE connection offload params passed by driver to FW in FCoE offload |
10817 | * ramrod. | |
10818 | */ | |
1e128c81 AE |
10819 | struct fcoe_conn_offload_ramrod_params { |
10820 | struct fcoe_conn_offload_ramrod_data offload_ramrod_data; | |
10821 | }; | |
10822 | ||
a2e7699e TT |
10823 | /* FCoE connection terminate params passed by driver to FW in FCoE terminate |
10824 | * conn ramrod. | |
10825 | */ | |
1e128c81 AE |
10826 | struct fcoe_conn_terminate_ramrod_params { |
10827 | struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data; | |
10828 | }; | |
10829 | ||
a2e7699e | 10830 | /* FCoE event type */ |
1e128c81 AE |
10831 | enum fcoe_event_type { |
10832 | FCOE_EVENT_INIT_FUNC, | |
10833 | FCOE_EVENT_DESTROY_FUNC, | |
10834 | FCOE_EVENT_STAT_FUNC, | |
10835 | FCOE_EVENT_OFFLOAD_CONN, | |
10836 | FCOE_EVENT_TERMINATE_CONN, | |
10837 | FCOE_EVENT_ERROR, | |
10838 | MAX_FCOE_EVENT_TYPE | |
10839 | }; | |
10840 | ||
a2e7699e | 10841 | /* FCoE init params passed by driver to FW in FCoE init ramrod */ |
1e128c81 AE |
10842 | struct fcoe_init_ramrod_params { |
10843 | struct fcoe_init_func_ramrod_data init_ramrod_data; | |
10844 | }; | |
10845 | ||
a2e7699e | 10846 | /* FCoE ramrod Command IDs */ |
1e128c81 AE |
10847 | enum fcoe_ramrod_cmd_id { |
10848 | FCOE_RAMROD_CMD_ID_INIT_FUNC, | |
10849 | FCOE_RAMROD_CMD_ID_DESTROY_FUNC, | |
10850 | FCOE_RAMROD_CMD_ID_STAT_FUNC, | |
10851 | FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, | |
10852 | FCOE_RAMROD_CMD_ID_TERMINATE_CONN, | |
10853 | MAX_FCOE_RAMROD_CMD_ID | |
10854 | }; | |
10855 | ||
a2e7699e TT |
10856 | /* FCoE statistics params buffer passed by driver to FW in FCoE statistics |
10857 | * ramrod. | |
10858 | */ | |
1e128c81 AE |
10859 | struct fcoe_stat_ramrod_params { |
10860 | struct fcoe_stat_ramrod_data stat_ramrod_data; | |
10861 | }; | |
10862 | ||
21dd79e8 | 10863 | struct e4_ystorm_fcoe_conn_ag_ctx { |
1e128c81 AE |
10864 | u8 byte0; |
10865 | u8 byte1; | |
10866 | u8 flags0; | |
21dd79e8 TT |
10867 | #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 |
10868 | #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 | |
10869 | #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 | |
10870 | #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 | |
10871 | #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 | |
10872 | #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 | |
10873 | #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 | |
10874 | #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 | |
10875 | #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 | |
10876 | #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 | |
1e128c81 | 10877 | u8 flags1; |
21dd79e8 TT |
10878 | #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 |
10879 | #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 | |
10880 | #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
10881 | #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 | |
10882 | #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 | |
10883 | #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 | |
10884 | #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
10885 | #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
10886 | #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
10887 | #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
10888 | #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
10889 | #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
10890 | #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
10891 | #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
10892 | #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
10893 | #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
1e128c81 AE |
10894 | u8 byte2; |
10895 | u8 byte3; | |
10896 | __le16 word0; | |
10897 | __le32 reg0; | |
10898 | __le32 reg1; | |
10899 | __le16 word1; | |
10900 | __le16 word2; | |
10901 | __le16 word3; | |
10902 | __le16 word4; | |
10903 | __le32 reg2; | |
10904 | __le32 reg3; | |
10905 | }; | |
10906 | ||
a2e7699e | 10907 | /* The iscsi storm connection context of Ystorm */ |
7a9b6b8f | 10908 | struct ystorm_iscsi_conn_st_ctx { |
da090917 | 10909 | __le32 reserved[8]; |
7a9b6b8f YM |
10910 | }; |
10911 | ||
a2e7699e | 10912 | /* Combined iSCSI and TCP storm connection of Pstorm */ |
7a9b6b8f YM |
10913 | struct pstorm_iscsi_tcp_conn_st_ctx { |
10914 | __le32 tcp[32]; | |
10915 | __le32 iscsi[4]; | |
10916 | }; | |
10917 | ||
a2e7699e | 10918 | /* The combined tcp and iscsi storm context of Xstorm */ |
7a9b6b8f | 10919 | struct xstorm_iscsi_tcp_conn_st_ctx { |
7a9b6b8f | 10920 | __le32 reserved_tcp[4]; |
da090917 | 10921 | __le32 reserved_iscsi[44]; |
7a9b6b8f YM |
10922 | }; |
10923 | ||
21dd79e8 | 10924 | struct e4_xstorm_iscsi_conn_ag_ctx { |
7a9b6b8f YM |
10925 | u8 cdu_validation; |
10926 | u8 state; | |
10927 | u8 flags0; | |
21dd79e8 TT |
10928 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
10929 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
10930 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 | |
10931 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 | |
10932 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1 | |
10933 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2 | |
10934 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
10935 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
10936 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 | |
10937 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4 | |
10938 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1 | |
10939 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5 | |
10940 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1 | |
10941 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6 | |
10942 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1 | |
10943 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7 | |
7a9b6b8f | 10944 | u8 flags1; |
21dd79e8 TT |
10945 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1 |
10946 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0 | |
10947 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1 | |
10948 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1 | |
10949 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1 | |
10950 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2 | |
10951 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1 | |
10952 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3 | |
10953 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1 | |
10954 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4 | |
10955 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1 | |
10956 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5 | |
10957 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1 | |
10958 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6 | |
10959 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1 | |
10960 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7 | |
7a9b6b8f | 10961 | u8 flags2; |
21dd79e8 TT |
10962 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 |
10963 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0 | |
10964 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 | |
10965 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2 | |
10966 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 | |
10967 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4 | |
10968 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 | |
10969 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 | |
7a9b6b8f | 10970 | u8 flags3; |
21dd79e8 TT |
10971 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 |
10972 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0 | |
10973 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 | |
10974 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2 | |
10975 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 | |
10976 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4 | |
10977 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 | |
10978 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6 | |
7a9b6b8f | 10979 | u8 flags4; |
21dd79e8 TT |
10980 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 |
10981 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0 | |
10982 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3 | |
10983 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2 | |
10984 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3 | |
10985 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4 | |
10986 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3 | |
10987 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6 | |
7a9b6b8f | 10988 | u8 flags5; |
21dd79e8 TT |
10989 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3 |
10990 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0 | |
10991 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3 | |
10992 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2 | |
10993 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3 | |
10994 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4 | |
10995 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3 | |
10996 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6 | |
7a9b6b8f | 10997 | u8 flags6; |
21dd79e8 TT |
10998 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3 |
10999 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0 | |
11000 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3 | |
11001 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2 | |
11002 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3 | |
11003 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4 | |
11004 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 | |
11005 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 | |
7a9b6b8f | 11006 | u8 flags7; |
21dd79e8 TT |
11007 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3 |
11008 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0 | |
11009 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3 | |
11010 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2 | |
11011 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3 | |
11012 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
11013 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 | |
11014 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6 | |
11015 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 | |
11016 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7 | |
7a9b6b8f | 11017 | u8 flags8; |
21dd79e8 TT |
11018 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 |
11019 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0 | |
11020 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 | |
11021 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 | |
11022 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 | |
11023 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2 | |
11024 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 | |
11025 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3 | |
11026 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 | |
11027 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4 | |
11028 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1 | |
11029 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5 | |
11030 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1 | |
11031 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6 | |
11032 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1 | |
11033 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7 | |
7a9b6b8f | 11034 | u8 flags9; |
21dd79e8 TT |
11035 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1 |
11036 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0 | |
11037 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1 | |
11038 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1 | |
11039 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1 | |
11040 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2 | |
11041 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1 | |
11042 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3 | |
11043 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1 | |
11044 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4 | |
11045 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1 | |
11046 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5 | |
11047 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1 | |
11048 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6 | |
11049 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1 | |
11050 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7 | |
7a9b6b8f | 11051 | u8 flags10; |
21dd79e8 TT |
11052 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1 |
11053 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0 | |
11054 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 | |
11055 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 | |
11056 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1 | |
11057 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2 | |
11058 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1 | |
11059 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3 | |
11060 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
11061 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
11062 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1 | |
11063 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5 | |
11064 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
11065 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6 | |
11066 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1 | |
11067 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7 | |
7a9b6b8f | 11068 | u8 flags11; |
21dd79e8 TT |
11069 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 |
11070 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 | |
11071 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
11072 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1 | |
11073 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1 | |
11074 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2 | |
11075 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
11076 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
11077 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
11078 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
11079 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
11080 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5 | |
11081 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
11082 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
11083 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1 | |
11084 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7 | |
7a9b6b8f | 11085 | u8 flags12; |
21dd79e8 TT |
11086 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1 |
11087 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0 | |
11088 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1 | |
11089 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1 | |
11090 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
11091 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
11092 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
11093 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
11094 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1 | |
11095 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4 | |
11096 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
11097 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
11098 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1 | |
11099 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6 | |
11100 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1 | |
11101 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7 | |
7a9b6b8f | 11102 | u8 flags13; |
21dd79e8 TT |
11103 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1 |
11104 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0 | |
11105 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1 | |
11106 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1 | |
11107 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 | |
11108 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 | |
11109 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 | |
11110 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 | |
11111 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
11112 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
11113 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 | |
11114 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 | |
11115 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
11116 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
11117 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
11118 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
7a9b6b8f | 11119 | u8 flags14; |
21dd79e8 TT |
11120 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1 |
11121 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0 | |
11122 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1 | |
11123 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1 | |
11124 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1 | |
11125 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2 | |
11126 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1 | |
11127 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3 | |
11128 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1 | |
11129 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4 | |
11130 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1 | |
11131 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5 | |
11132 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3 | |
11133 | #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6 | |
7a9b6b8f YM |
11134 | u8 byte2; |
11135 | __le16 physical_q0; | |
11136 | __le16 physical_q1; | |
11137 | __le16 dummy_dorq_var; | |
11138 | __le16 sq_cons; | |
11139 | __le16 sq_prod; | |
11140 | __le16 word5; | |
11141 | __le16 slow_io_total_data_tx_update; | |
11142 | u8 byte3; | |
11143 | u8 byte4; | |
11144 | u8 byte5; | |
11145 | u8 byte6; | |
11146 | __le32 reg0; | |
11147 | __le32 reg1; | |
11148 | __le32 reg2; | |
11149 | __le32 more_to_send_seq; | |
11150 | __le32 reg4; | |
11151 | __le32 reg5; | |
11152 | __le32 hq_scan_next_relevant_ack; | |
11153 | __le16 r2tq_prod; | |
11154 | __le16 r2tq_cons; | |
11155 | __le16 hq_prod; | |
11156 | __le16 hq_cons; | |
11157 | __le32 remain_seq; | |
11158 | __le32 bytes_to_next_pdu; | |
11159 | __le32 hq_tcp_seq; | |
11160 | u8 byte7; | |
11161 | u8 byte8; | |
11162 | u8 byte9; | |
11163 | u8 byte10; | |
11164 | u8 byte11; | |
11165 | u8 byte12; | |
11166 | u8 byte13; | |
11167 | u8 byte14; | |
11168 | u8 byte15; | |
21dd79e8 | 11169 | u8 e5_reserved; |
7a9b6b8f YM |
11170 | __le16 word11; |
11171 | __le32 reg10; | |
11172 | __le32 reg11; | |
11173 | __le32 exp_stat_sn; | |
be086e7c | 11174 | __le32 ongoing_fast_rxmit_seq; |
7a9b6b8f YM |
11175 | __le32 reg14; |
11176 | __le32 reg15; | |
11177 | __le32 reg16; | |
11178 | __le32 reg17; | |
11179 | }; | |
11180 | ||
21dd79e8 | 11181 | struct e4_tstorm_iscsi_conn_ag_ctx { |
7a9b6b8f YM |
11182 | u8 reserved0; |
11183 | u8 state; | |
11184 | u8 flags0; | |
21dd79e8 TT |
11185 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 |
11186 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
11187 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 | |
11188 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 | |
11189 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1 | |
11190 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2 | |
11191 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1 | |
11192 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3 | |
11193 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 | |
11194 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4 | |
11195 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1 | |
11196 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5 | |
11197 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 | |
11198 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6 | |
7a9b6b8f | 11199 | u8 flags1; |
21dd79e8 TT |
11200 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3 |
11201 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0 | |
11202 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3 | |
11203 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2 | |
11204 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 | |
11205 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 | |
11206 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 | |
11207 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6 | |
7a9b6b8f | 11208 | u8 flags2; |
21dd79e8 TT |
11209 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 |
11210 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0 | |
11211 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 | |
11212 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2 | |
11213 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 | |
11214 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4 | |
11215 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 | |
11216 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6 | |
7a9b6b8f | 11217 | u8 flags3; |
21dd79e8 TT |
11218 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 |
11219 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 | |
11220 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3 | |
11221 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 2 | |
11222 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 | |
11223 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4 | |
11224 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1 | |
11225 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5 | |
11226 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1 | |
11227 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6 | |
11228 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 | |
11229 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 | |
7a9b6b8f | 11230 | u8 flags4; |
21dd79e8 TT |
11231 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 |
11232 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0 | |
11233 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 | |
11234 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1 | |
11235 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 | |
11236 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2 | |
11237 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1 | |
11238 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3 | |
11239 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1 | |
11240 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4 | |
11241 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 | |
11242 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5 | |
11243 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1 | |
11244 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 6 | |
11245 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
11246 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
7a9b6b8f | 11247 | u8 flags5; |
21dd79e8 TT |
11248 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 |
11249 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
11250 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
11251 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
11252 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
11253 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
11254 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
11255 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
11256 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
11257 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
11258 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
11259 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
11260 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
11261 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
11262 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
11263 | #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
7a9b6b8f YM |
11264 | __le32 reg0; |
11265 | __le32 reg1; | |
50bc60cb | 11266 | __le32 rx_tcp_checksum_err_cnt; |
7a9b6b8f YM |
11267 | __le32 reg3; |
11268 | __le32 reg4; | |
11269 | __le32 reg5; | |
11270 | __le32 reg6; | |
11271 | __le32 reg7; | |
11272 | __le32 reg8; | |
be086e7c | 11273 | u8 cid_offload_cnt; |
7a9b6b8f YM |
11274 | u8 byte3; |
11275 | __le16 word0; | |
11276 | }; | |
11277 | ||
21dd79e8 | 11278 | struct e4_ustorm_iscsi_conn_ag_ctx { |
7a9b6b8f YM |
11279 | u8 byte0; |
11280 | u8 byte1; | |
11281 | u8 flags0; | |
21dd79e8 TT |
11282 | #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 |
11283 | #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 | |
11284 | #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 | |
11285 | #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 | |
11286 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 | |
11287 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 | |
11288 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 | |
11289 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 | |
11290 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 | |
11291 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 | |
7a9b6b8f | 11292 | u8 flags1; |
21dd79e8 TT |
11293 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3 |
11294 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0 | |
11295 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 | |
11296 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2 | |
11297 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 | |
11298 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4 | |
11299 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 | |
11300 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6 | |
7a9b6b8f | 11301 | u8 flags2; |
21dd79e8 TT |
11302 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 |
11303 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 | |
11304 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 | |
11305 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 | |
11306 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 | |
11307 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 | |
11308 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1 | |
11309 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3 | |
11310 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 | |
11311 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4 | |
11312 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 | |
11313 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5 | |
11314 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 | |
11315 | #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6 | |
11316 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
11317 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
7a9b6b8f | 11318 | u8 flags3; |
21dd79e8 TT |
11319 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 |
11320 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
11321 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
11322 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
11323 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
11324 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
11325 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
11326 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
11327 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
11328 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
11329 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
11330 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
11331 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
11332 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
11333 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
11334 | #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
7a9b6b8f YM |
11335 | u8 byte2; |
11336 | u8 byte3; | |
11337 | __le16 word0; | |
11338 | __le16 word1; | |
11339 | __le32 reg0; | |
11340 | __le32 reg1; | |
11341 | __le32 reg2; | |
11342 | __le32 reg3; | |
11343 | __le16 word2; | |
11344 | __le16 word3; | |
11345 | }; | |
11346 | ||
a2e7699e | 11347 | /* The iscsi storm connection context of Tstorm */ |
7a9b6b8f | 11348 | struct tstorm_iscsi_conn_st_ctx { |
da090917 | 11349 | __le32 reserved[44]; |
7a9b6b8f YM |
11350 | }; |
11351 | ||
21dd79e8 | 11352 | struct e4_mstorm_iscsi_conn_ag_ctx { |
7a9b6b8f YM |
11353 | u8 reserved; |
11354 | u8 state; | |
11355 | u8 flags0; | |
21dd79e8 TT |
11356 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 |
11357 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 | |
11358 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 | |
11359 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 | |
11360 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 | |
11361 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 | |
11362 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 | |
11363 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 | |
11364 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 | |
11365 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 | |
7a9b6b8f | 11366 | u8 flags1; |
21dd79e8 TT |
11367 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 |
11368 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 | |
11369 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 | |
11370 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 | |
11371 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 | |
11372 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 | |
11373 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
11374 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
11375 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
11376 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
11377 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
11378 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
11379 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
11380 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
11381 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
11382 | #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
7a9b6b8f YM |
11383 | __le16 word0; |
11384 | __le16 word1; | |
11385 | __le32 reg0; | |
11386 | __le32 reg1; | |
11387 | }; | |
11388 | ||
a2e7699e | 11389 | /* Combined iSCSI and TCP storm connection of Mstorm */ |
7a9b6b8f YM |
11390 | struct mstorm_iscsi_tcp_conn_st_ctx { |
11391 | __le32 reserved_tcp[20]; | |
da090917 | 11392 | __le32 reserved_iscsi[12]; |
7a9b6b8f YM |
11393 | }; |
11394 | ||
a2e7699e | 11395 | /* The iscsi storm context of Ustorm */ |
7a9b6b8f YM |
11396 | struct ustorm_iscsi_conn_st_ctx { |
11397 | __le32 reserved[52]; | |
11398 | }; | |
11399 | ||
a2e7699e | 11400 | /* iscsi connection context */ |
21dd79e8 | 11401 | struct e4_iscsi_conn_context { |
7a9b6b8f | 11402 | struct ystorm_iscsi_conn_st_ctx ystorm_st_context; |
7a9b6b8f YM |
11403 | struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context; |
11404 | struct regpair pstorm_st_padding[2]; | |
11405 | struct pb_context xpb2_context; | |
11406 | struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context; | |
11407 | struct regpair xstorm_st_padding[2]; | |
21dd79e8 TT |
11408 | struct e4_xstorm_iscsi_conn_ag_ctx xstorm_ag_context; |
11409 | struct e4_tstorm_iscsi_conn_ag_ctx tstorm_ag_context; | |
7a9b6b8f YM |
11410 | struct regpair tstorm_ag_padding[2]; |
11411 | struct timers_context timer_context; | |
21dd79e8 | 11412 | struct e4_ustorm_iscsi_conn_ag_ctx ustorm_ag_context; |
7a9b6b8f YM |
11413 | struct pb_context upb_context; |
11414 | struct tstorm_iscsi_conn_st_ctx tstorm_st_context; | |
11415 | struct regpair tstorm_st_padding[2]; | |
21dd79e8 | 11416 | struct e4_mstorm_iscsi_conn_ag_ctx mstorm_ag_context; |
7a9b6b8f YM |
11417 | struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context; |
11418 | struct ustorm_iscsi_conn_st_ctx ustorm_st_context; | |
11419 | }; | |
11420 | ||
a2e7699e | 11421 | /* iSCSI init params passed by driver to FW in iSCSI init ramrod */ |
7a9b6b8f YM |
11422 | struct iscsi_init_ramrod_params { |
11423 | struct iscsi_spe_func_init iscsi_init_spe; | |
11424 | struct tcp_init_params tcp_init; | |
11425 | }; | |
11426 | ||
21dd79e8 | 11427 | struct e4_ystorm_iscsi_conn_ag_ctx { |
7a9b6b8f YM |
11428 | u8 byte0; |
11429 | u8 byte1; | |
11430 | u8 flags0; | |
21dd79e8 TT |
11431 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 |
11432 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 | |
11433 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 | |
11434 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 | |
11435 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 | |
11436 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 | |
11437 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 | |
11438 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 | |
11439 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 | |
11440 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 | |
7a9b6b8f | 11441 | u8 flags1; |
21dd79e8 TT |
11442 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 |
11443 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 | |
11444 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 | |
11445 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 | |
11446 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 | |
11447 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 | |
11448 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
11449 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
11450 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
11451 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
11452 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
11453 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
11454 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
11455 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
11456 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
11457 | #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
7a9b6b8f YM |
11458 | u8 byte2; |
11459 | u8 byte3; | |
11460 | __le16 word0; | |
11461 | __le32 reg0; | |
11462 | __le32 reg1; | |
11463 | __le16 word1; | |
11464 | __le16 word2; | |
11465 | __le16 word3; | |
11466 | __le16 word4; | |
11467 | __le32 reg2; | |
11468 | __le32 reg3; | |
11469 | }; | |
c965db44 TT |
11470 | |
11471 | #define MFW_TRACE_SIGNATURE 0x25071946 | |
11472 | ||
11473 | /* The trace in the buffer */ | |
11474 | #define MFW_TRACE_EVENTID_MASK 0x00ffff | |
11475 | #define MFW_TRACE_PRM_SIZE_MASK 0x0f0000 | |
11476 | #define MFW_TRACE_PRM_SIZE_SHIFT 16 | |
11477 | #define MFW_TRACE_ENTRY_SIZE 3 | |
11478 | ||
11479 | struct mcp_trace { | |
11480 | u32 signature; /* Help to identify that the trace is valid */ | |
11481 | u32 size; /* the size of the trace buffer in bytes */ | |
11482 | u32 curr_level; /* 2 - all will be written to the buffer | |
11483 | * 1 - debug trace will not be written | |
11484 | * 0 - just errors will be written to the buffer | |
11485 | */ | |
11486 | u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means | |
11487 | * mask it. | |
11488 | */ | |
11489 | ||
11490 | /* Warning: the following pointers are assumed to be 32bits as they are | |
11491 | * used only in the MFW. | |
11492 | */ | |
11493 | u32 trace_prod; /* The next trace will be written to this offset */ | |
11494 | u32 trace_oldest; /* The oldest valid trace starts at this offset | |
11495 | * (usually very close after the current producer). | |
11496 | */ | |
11497 | }; | |
11498 | ||
351a4ded | 11499 | #define VF_MAX_STATIC 192 |
fe56b9e6 | 11500 | |
351a4ded YM |
11501 | #define MCP_GLOB_PATH_MAX 2 |
11502 | #define MCP_PORT_MAX 2 | |
11503 | #define MCP_GLOB_PORT_MAX 4 | |
11504 | #define MCP_GLOB_FUNC_MAX 16 | |
fe56b9e6 | 11505 | |
c965db44 | 11506 | typedef u32 offsize_t; /* In DWORDS !!! */ |
fe56b9e6 | 11507 | /* Offset from the beginning of the MCP scratchpad */ |
351a4ded YM |
11508 | #define OFFSIZE_OFFSET_SHIFT 0 |
11509 | #define OFFSIZE_OFFSET_MASK 0x0000ffff | |
fe56b9e6 | 11510 | /* Size of specific element (not the whole array if any) */ |
351a4ded YM |
11511 | #define OFFSIZE_SIZE_SHIFT 16 |
11512 | #define OFFSIZE_SIZE_MASK 0xffff0000 | |
fe56b9e6 | 11513 | |
351a4ded YM |
11514 | #define SECTION_OFFSET(_offsize) ((((_offsize & \ |
11515 | OFFSIZE_OFFSET_MASK) >> \ | |
11516 | OFFSIZE_OFFSET_SHIFT) << 2)) | |
fe56b9e6 | 11517 | |
351a4ded YM |
11518 | #define QED_SECTION_SIZE(_offsize) (((_offsize & \ |
11519 | OFFSIZE_SIZE_MASK) >> \ | |
11520 | OFFSIZE_SIZE_SHIFT) << 2) | |
fe56b9e6 | 11521 | |
351a4ded YM |
11522 | #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \ |
11523 | SECTION_OFFSET(_offsize) + \ | |
11524 | (QED_SECTION_SIZE(_offsize) * idx)) | |
11525 | ||
11526 | #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \ | |
11527 | (_pub_base + offsetof(struct mcp_public_data, sections[_section])) | |
fe56b9e6 | 11528 | |
fe56b9e6 | 11529 | /* PHY configuration */ |
351a4ded YM |
11530 | struct eth_phy_cfg { |
11531 | u32 speed; | |
11532 | #define ETH_SPEED_AUTONEG 0 | |
11533 | #define ETH_SPEED_SMARTLINQ 0x8 | |
11534 | ||
11535 | u32 pause; | |
11536 | #define ETH_PAUSE_NONE 0x0 | |
11537 | #define ETH_PAUSE_AUTONEG 0x1 | |
11538 | #define ETH_PAUSE_RX 0x2 | |
11539 | #define ETH_PAUSE_TX 0x4 | |
11540 | ||
11541 | u32 adv_speed; | |
11542 | u32 loopback_mode; | |
11543 | #define ETH_LOOPBACK_NONE (0) | |
11544 | #define ETH_LOOPBACK_INT_PHY (1) | |
11545 | #define ETH_LOOPBACK_EXT_PHY (2) | |
11546 | #define ETH_LOOPBACK_EXT (3) | |
11547 | #define ETH_LOOPBACK_MAC (4) | |
11548 | ||
645874e5 SRK |
11549 | u32 eee_cfg; |
11550 | #define EEE_CFG_EEE_ENABLED BIT(0) | |
11551 | #define EEE_CFG_TX_LPI BIT(1) | |
11552 | #define EEE_CFG_ADV_SPEED_1G BIT(2) | |
11553 | #define EEE_CFG_ADV_SPEED_10G BIT(3) | |
11554 | #define EEE_TX_TIMER_USEC_MASK (0xfffffff0) | |
11555 | #define EEE_TX_TIMER_USEC_OFFSET 4 | |
11556 | #define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00) | |
11557 | #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100) | |
11558 | #define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000) | |
11559 | ||
fe56b9e6 | 11560 | u32 feature_config_flags; |
351a4ded | 11561 | #define ETH_EEE_MODE_ADV_LPI (1 << 0) |
fe56b9e6 YM |
11562 | }; |
11563 | ||
11564 | struct port_mf_cfg { | |
351a4ded YM |
11565 | u32 dynamic_cfg; |
11566 | #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff | |
11567 | #define PORT_MF_CFG_OV_TAG_SHIFT 0 | |
11568 | #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK | |
11569 | ||
11570 | u32 reserved[1]; | |
11571 | }; | |
11572 | ||
11573 | struct eth_stats { | |
11574 | u64 r64; | |
11575 | u64 r127; | |
11576 | u64 r255; | |
11577 | u64 r511; | |
11578 | u64 r1023; | |
11579 | u64 r1518; | |
9c79ddaa MY |
11580 | |
11581 | union { | |
11582 | struct { | |
11583 | u64 r1522; | |
11584 | u64 r2047; | |
11585 | u64 r4095; | |
11586 | u64 r9216; | |
11587 | u64 r16383; | |
11588 | } bb0; | |
11589 | struct { | |
11590 | u64 unused1; | |
11591 | u64 r1519_to_max; | |
11592 | u64 unused2; | |
11593 | u64 unused3; | |
11594 | u64 unused4; | |
11595 | } ah0; | |
11596 | } u0; | |
11597 | ||
351a4ded YM |
11598 | u64 rfcs; |
11599 | u64 rxcf; | |
11600 | u64 rxpf; | |
11601 | u64 rxpp; | |
11602 | u64 raln; | |
11603 | u64 rfcr; | |
11604 | u64 rovr; | |
11605 | u64 rjbr; | |
11606 | u64 rund; | |
11607 | u64 rfrg; | |
11608 | u64 t64; | |
11609 | u64 t127; | |
11610 | u64 t255; | |
11611 | u64 t511; | |
11612 | u64 t1023; | |
11613 | u64 t1518; | |
9c79ddaa MY |
11614 | |
11615 | union { | |
11616 | struct { | |
11617 | u64 t2047; | |
11618 | u64 t4095; | |
11619 | u64 t9216; | |
11620 | u64 t16383; | |
11621 | } bb1; | |
11622 | struct { | |
11623 | u64 t1519_to_max; | |
11624 | u64 unused6; | |
11625 | u64 unused7; | |
11626 | u64 unused8; | |
11627 | } ah1; | |
11628 | } u1; | |
11629 | ||
351a4ded YM |
11630 | u64 txpf; |
11631 | u64 txpp; | |
9c79ddaa MY |
11632 | |
11633 | union { | |
11634 | struct { | |
11635 | u64 tlpiec; | |
11636 | u64 tncl; | |
11637 | } bb2; | |
11638 | struct { | |
11639 | u64 unused9; | |
11640 | u64 unused10; | |
11641 | } ah2; | |
11642 | } u2; | |
11643 | ||
351a4ded YM |
11644 | u64 rbyte; |
11645 | u64 rxuca; | |
11646 | u64 rxmca; | |
11647 | u64 rxbca; | |
11648 | u64 rxpok; | |
11649 | u64 tbyte; | |
11650 | u64 txuca; | |
11651 | u64 txmca; | |
11652 | u64 txbca; | |
11653 | u64 txcf; | |
fe56b9e6 YM |
11654 | }; |
11655 | ||
11656 | struct brb_stats { | |
351a4ded YM |
11657 | u64 brb_truncate[8]; |
11658 | u64 brb_discard[8]; | |
fe56b9e6 YM |
11659 | }; |
11660 | ||
11661 | struct port_stats { | |
351a4ded YM |
11662 | struct brb_stats brb; |
11663 | struct eth_stats eth; | |
fe56b9e6 YM |
11664 | }; |
11665 | ||
fe56b9e6 YM |
11666 | struct couple_mode_teaming { |
11667 | u8 port_cmt[MCP_GLOB_PORT_MAX]; | |
351a4ded | 11668 | #define PORT_CMT_IN_TEAM (1 << 0) |
fe56b9e6 | 11669 | |
351a4ded YM |
11670 | #define PORT_CMT_PORT_ROLE (1 << 1) |
11671 | #define PORT_CMT_PORT_INACTIVE (0 << 1) | |
11672 | #define PORT_CMT_PORT_ACTIVE (1 << 1) | |
fe56b9e6 | 11673 | |
351a4ded YM |
11674 | #define PORT_CMT_TEAM_MASK (1 << 2) |
11675 | #define PORT_CMT_TEAM0 (0 << 2) | |
11676 | #define PORT_CMT_TEAM1 (1 << 2) | |
fe56b9e6 YM |
11677 | }; |
11678 | ||
351a4ded YM |
11679 | #define LLDP_CHASSIS_ID_STAT_LEN 4 |
11680 | #define LLDP_PORT_ID_STAT_LEN 4 | |
11681 | #define DCBX_MAX_APP_PROTOCOL 32 | |
11682 | #define MAX_SYSTEM_LLDP_TLV_DATA 32 | |
fe56b9e6 | 11683 | |
351a4ded | 11684 | enum _lldp_agent { |
fe56b9e6 YM |
11685 | LLDP_NEAREST_BRIDGE = 0, |
11686 | LLDP_NEAREST_NON_TPMR_BRIDGE, | |
11687 | LLDP_NEAREST_CUSTOMER_BRIDGE, | |
11688 | LLDP_MAX_LLDP_AGENTS | |
11689 | }; | |
11690 | ||
11691 | struct lldp_config_params_s { | |
11692 | u32 config; | |
351a4ded YM |
11693 | #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff |
11694 | #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0 | |
11695 | #define LLDP_CONFIG_HOLD_MASK 0x00000f00 | |
11696 | #define LLDP_CONFIG_HOLD_SHIFT 8 | |
11697 | #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000 | |
11698 | #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12 | |
11699 | #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000 | |
11700 | #define LLDP_CONFIG_ENABLE_RX_SHIFT 30 | |
11701 | #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000 | |
11702 | #define LLDP_CONFIG_ENABLE_TX_SHIFT 31 | |
11703 | u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; | |
11704 | u32 local_port_id[LLDP_PORT_ID_STAT_LEN]; | |
fe56b9e6 YM |
11705 | }; |
11706 | ||
11707 | struct lldp_status_params_s { | |
351a4ded YM |
11708 | u32 prefix_seq_num; |
11709 | u32 status; | |
11710 | u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; | |
11711 | u32 peer_port_id[LLDP_PORT_ID_STAT_LEN]; | |
11712 | u32 suffix_seq_num; | |
fe56b9e6 YM |
11713 | }; |
11714 | ||
11715 | struct dcbx_ets_feature { | |
11716 | u32 flags; | |
351a4ded YM |
11717 | #define DCBX_ETS_ENABLED_MASK 0x00000001 |
11718 | #define DCBX_ETS_ENABLED_SHIFT 0 | |
11719 | #define DCBX_ETS_WILLING_MASK 0x00000002 | |
11720 | #define DCBX_ETS_WILLING_SHIFT 1 | |
11721 | #define DCBX_ETS_ERROR_MASK 0x00000004 | |
11722 | #define DCBX_ETS_ERROR_SHIFT 2 | |
11723 | #define DCBX_ETS_CBS_MASK 0x00000008 | |
11724 | #define DCBX_ETS_CBS_SHIFT 3 | |
11725 | #define DCBX_ETS_MAX_TCS_MASK 0x000000f0 | |
11726 | #define DCBX_ETS_MAX_TCS_SHIFT 4 | |
b5a9ee7c AE |
11727 | #define DCBX_OOO_TC_MASK 0x00000f00 |
11728 | #define DCBX_OOO_TC_SHIFT 8 | |
351a4ded | 11729 | u32 pri_tc_tbl[1]; |
b5a9ee7c | 11730 | #define DCBX_TCP_OOO_TC (4) |
351a4ded | 11731 | |
b5a9ee7c | 11732 | #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1) |
351a4ded YM |
11733 | #define DCBX_CEE_STRICT_PRIORITY 0xf |
11734 | u32 tc_bw_tbl[2]; | |
11735 | u32 tc_tsa_tbl[2]; | |
11736 | #define DCBX_ETS_TSA_STRICT 0 | |
11737 | #define DCBX_ETS_TSA_CBS 1 | |
11738 | #define DCBX_ETS_TSA_ETS 2 | |
fe56b9e6 YM |
11739 | }; |
11740 | ||
b5a9ee7c AE |
11741 | #define DCBX_TCP_OOO_TC (4) |
11742 | #define DCBX_TCP_OOO_K2_4PORT_TC (3) | |
11743 | ||
fe56b9e6 YM |
11744 | struct dcbx_app_priority_entry { |
11745 | u32 entry; | |
351a4ded YM |
11746 | #define DCBX_APP_PRI_MAP_MASK 0x000000ff |
11747 | #define DCBX_APP_PRI_MAP_SHIFT 0 | |
11748 | #define DCBX_APP_PRI_0 0x01 | |
11749 | #define DCBX_APP_PRI_1 0x02 | |
11750 | #define DCBX_APP_PRI_2 0x04 | |
11751 | #define DCBX_APP_PRI_3 0x08 | |
11752 | #define DCBX_APP_PRI_4 0x10 | |
11753 | #define DCBX_APP_PRI_5 0x20 | |
11754 | #define DCBX_APP_PRI_6 0x40 | |
11755 | #define DCBX_APP_PRI_7 0x80 | |
11756 | #define DCBX_APP_SF_MASK 0x00000300 | |
11757 | #define DCBX_APP_SF_SHIFT 8 | |
11758 | #define DCBX_APP_SF_ETHTYPE 0 | |
11759 | #define DCBX_APP_SF_PORT 1 | |
fb9ea8a9 SRK |
11760 | #define DCBX_APP_SF_IEEE_MASK 0x0000f000 |
11761 | #define DCBX_APP_SF_IEEE_SHIFT 12 | |
11762 | #define DCBX_APP_SF_IEEE_RESERVED 0 | |
11763 | #define DCBX_APP_SF_IEEE_ETHTYPE 1 | |
11764 | #define DCBX_APP_SF_IEEE_TCP_PORT 2 | |
11765 | #define DCBX_APP_SF_IEEE_UDP_PORT 3 | |
11766 | #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4 | |
11767 | ||
351a4ded YM |
11768 | #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000 |
11769 | #define DCBX_APP_PROTOCOL_ID_SHIFT 16 | |
11770 | }; | |
11771 | ||
fe56b9e6 YM |
11772 | struct dcbx_app_priority_feature { |
11773 | u32 flags; | |
351a4ded YM |
11774 | #define DCBX_APP_ENABLED_MASK 0x00000001 |
11775 | #define DCBX_APP_ENABLED_SHIFT 0 | |
11776 | #define DCBX_APP_WILLING_MASK 0x00000002 | |
11777 | #define DCBX_APP_WILLING_SHIFT 1 | |
11778 | #define DCBX_APP_ERROR_MASK 0x00000004 | |
11779 | #define DCBX_APP_ERROR_SHIFT 2 | |
11780 | #define DCBX_APP_MAX_TCS_MASK 0x0000f000 | |
11781 | #define DCBX_APP_MAX_TCS_SHIFT 12 | |
11782 | #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000 | |
11783 | #define DCBX_APP_NUM_ENTRIES_SHIFT 16 | |
fe56b9e6 YM |
11784 | struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; |
11785 | }; | |
11786 | ||
fe56b9e6 | 11787 | struct dcbx_features { |
fe56b9e6 | 11788 | struct dcbx_ets_feature ets; |
351a4ded YM |
11789 | u32 pfc; |
11790 | #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff | |
11791 | #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0 | |
11792 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01 | |
11793 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02 | |
11794 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04 | |
11795 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08 | |
11796 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10 | |
11797 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20 | |
11798 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40 | |
11799 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80 | |
11800 | ||
11801 | #define DCBX_PFC_FLAGS_MASK 0x0000ff00 | |
11802 | #define DCBX_PFC_FLAGS_SHIFT 8 | |
11803 | #define DCBX_PFC_CAPS_MASK 0x00000f00 | |
11804 | #define DCBX_PFC_CAPS_SHIFT 8 | |
11805 | #define DCBX_PFC_MBC_MASK 0x00004000 | |
11806 | #define DCBX_PFC_MBC_SHIFT 14 | |
11807 | #define DCBX_PFC_WILLING_MASK 0x00008000 | |
11808 | #define DCBX_PFC_WILLING_SHIFT 15 | |
11809 | #define DCBX_PFC_ENABLED_MASK 0x00010000 | |
11810 | #define DCBX_PFC_ENABLED_SHIFT 16 | |
11811 | #define DCBX_PFC_ERROR_MASK 0x00020000 | |
11812 | #define DCBX_PFC_ERROR_SHIFT 17 | |
fe56b9e6 | 11813 | |
fe56b9e6 YM |
11814 | struct dcbx_app_priority_feature app; |
11815 | }; | |
11816 | ||
11817 | struct dcbx_local_params { | |
11818 | u32 config; | |
351a4ded YM |
11819 | #define DCBX_CONFIG_VERSION_MASK 0x00000007 |
11820 | #define DCBX_CONFIG_VERSION_SHIFT 0 | |
11821 | #define DCBX_CONFIG_VERSION_DISABLED 0 | |
11822 | #define DCBX_CONFIG_VERSION_IEEE 1 | |
11823 | #define DCBX_CONFIG_VERSION_CEE 2 | |
11824 | #define DCBX_CONFIG_VERSION_STATIC 4 | |
fe56b9e6 | 11825 | |
351a4ded YM |
11826 | u32 flags; |
11827 | struct dcbx_features features; | |
fe56b9e6 YM |
11828 | }; |
11829 | ||
11830 | struct dcbx_mib { | |
351a4ded YM |
11831 | u32 prefix_seq_num; |
11832 | u32 flags; | |
11833 | struct dcbx_features features; | |
11834 | u32 suffix_seq_num; | |
fe56b9e6 YM |
11835 | }; |
11836 | ||
11837 | struct lldp_system_tlvs_buffer_s { | |
351a4ded YM |
11838 | u16 valid; |
11839 | u16 length; | |
11840 | u32 data[MAX_SYSTEM_LLDP_TLV_DATA]; | |
fe56b9e6 YM |
11841 | }; |
11842 | ||
351a4ded YM |
11843 | struct dcb_dscp_map { |
11844 | u32 flags; | |
11845 | #define DCB_DSCP_ENABLE_MASK 0x1 | |
11846 | #define DCB_DSCP_ENABLE_SHIFT 0 | |
11847 | #define DCB_DSCP_ENABLE 1 | |
11848 | u32 dscp_pri_map[8]; | |
fe56b9e6 YM |
11849 | }; |
11850 | ||
351a4ded YM |
11851 | struct public_global { |
11852 | u32 max_path; | |
11853 | u32 max_ports; | |
be086e7c MY |
11854 | #define MODE_1P 1 |
11855 | #define MODE_2P 2 | |
11856 | #define MODE_3P 3 | |
11857 | #define MODE_4P 4 | |
351a4ded YM |
11858 | u32 debug_mb_offset; |
11859 | u32 phymod_dbg_mb_offset; | |
11860 | struct couple_mode_teaming cmt; | |
11861 | s32 internal_temperature; | |
11862 | u32 mfw_ver; | |
11863 | u32 running_bundle_id; | |
11864 | s32 external_temperature; | |
11865 | u32 mdump_reason; | |
dd006921 SRK |
11866 | u32 data_ptr; |
11867 | u32 data_size; | |
351a4ded | 11868 | }; |
fe56b9e6 | 11869 | |
fe56b9e6 | 11870 | struct fw_flr_mb { |
351a4ded YM |
11871 | u32 aggint; |
11872 | u32 opgen_addr; | |
11873 | u32 accum_ack; | |
fe56b9e6 YM |
11874 | }; |
11875 | ||
11876 | struct public_path { | |
351a4ded YM |
11877 | struct fw_flr_mb flr_mb; |
11878 | u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; | |
11879 | ||
11880 | u32 process_kill; | |
11881 | #define PROCESS_KILL_COUNTER_MASK 0x0000ffff | |
11882 | #define PROCESS_KILL_COUNTER_SHIFT 0 | |
11883 | #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 | |
11884 | #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16 | |
fe56b9e6 YM |
11885 | #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit) |
11886 | }; | |
11887 | ||
fe56b9e6 | 11888 | struct public_port { |
351a4ded | 11889 | u32 validity_map; |
fe56b9e6 YM |
11890 | |
11891 | u32 link_status; | |
351a4ded YM |
11892 | #define LINK_STATUS_LINK_UP 0x00000001 |
11893 | #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e | |
11894 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1) | |
11895 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1) | |
11896 | #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1) | |
11897 | #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1) | |
11898 | #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1) | |
11899 | #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1) | |
11900 | #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1) | |
11901 | #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1) | |
11902 | ||
11903 | #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 | |
11904 | ||
11905 | #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 | |
11906 | #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 | |
11907 | ||
11908 | #define LINK_STATUS_PFC_ENABLED 0x00000100 | |
11909 | #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 | |
11910 | #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 | |
11911 | #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800 | |
11912 | #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000 | |
11913 | #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000 | |
11914 | #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000 | |
11915 | #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000 | |
11916 | #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000 | |
11917 | ||
11918 | #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 | |
11919 | #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18) | |
11920 | #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18) | |
11921 | #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18) | |
11922 | #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18) | |
11923 | ||
11924 | #define LINK_STATUS_SFP_TX_FAULT 0x00100000 | |
11925 | #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000 | |
11926 | #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000 | |
11927 | #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000 | |
11928 | #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000 | |
11929 | #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000 | |
11930 | #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000 | |
11931 | ||
11932 | u32 link_status1; | |
11933 | u32 ext_phy_fw_version; | |
11934 | u32 drv_phy_cfg_addr; | |
11935 | ||
11936 | u32 port_stx; | |
11937 | ||
11938 | u32 stat_nig_timer; | |
11939 | ||
11940 | struct port_mf_cfg port_mf_config; | |
11941 | struct port_stats stats; | |
11942 | ||
11943 | u32 media_type; | |
11944 | #define MEDIA_UNSPECIFIED 0x0 | |
11945 | #define MEDIA_SFPP_10G_FIBER 0x1 | |
11946 | #define MEDIA_XFP_FIBER 0x2 | |
11947 | #define MEDIA_DA_TWINAX 0x3 | |
11948 | #define MEDIA_BASE_T 0x4 | |
11949 | #define MEDIA_SFP_1G_FIBER 0x5 | |
11950 | #define MEDIA_MODULE_FIBER 0x6 | |
11951 | #define MEDIA_KR 0xf0 | |
11952 | #define MEDIA_NOT_PRESENT 0xff | |
fe56b9e6 YM |
11953 | |
11954 | u32 lfa_status; | |
351a4ded YM |
11955 | u32 link_change_count; |
11956 | ||
11957 | struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS]; | |
11958 | struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS]; | |
11959 | struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf; | |
fe56b9e6 YM |
11960 | |
11961 | /* DCBX related MIB */ | |
351a4ded YM |
11962 | struct dcbx_local_params local_admin_dcbx_mib; |
11963 | struct dcbx_mib remote_dcbx_mib; | |
11964 | struct dcbx_mib operational_dcbx_mib; | |
fc48b7a6 | 11965 | |
351a4ded YM |
11966 | u32 reserved[2]; |
11967 | u32 transceiver_data; | |
11968 | #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF | |
11969 | #define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000 | |
11970 | #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000 | |
11971 | #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001 | |
11972 | #define ETH_TRANSCEIVER_STATE_VALID 0x00000003 | |
11973 | #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008 | |
fe56b9e6 | 11974 | |
351a4ded YM |
11975 | u32 wol_info; |
11976 | u32 wol_pkt_len; | |
11977 | u32 wol_pkt_details; | |
11978 | struct dcb_dscp_map dcb_dscp_map; | |
645874e5 SRK |
11979 | |
11980 | u32 eee_status; | |
11981 | #define EEE_ACTIVE_BIT BIT(0) | |
11982 | #define EEE_LD_ADV_STATUS_MASK 0x000000f0 | |
11983 | #define EEE_LD_ADV_STATUS_OFFSET 4 | |
11984 | #define EEE_1G_ADV BIT(1) | |
11985 | #define EEE_10G_ADV BIT(2) | |
11986 | #define EEE_LP_ADV_STATUS_MASK 0x00000f00 | |
11987 | #define EEE_LP_ADV_STATUS_OFFSET 8 | |
11988 | #define EEE_SUPPORTED_SPEED_MASK 0x0000f000 | |
11989 | #define EEE_SUPPORTED_SPEED_OFFSET 12 | |
11990 | #define EEE_1G_SUPPORTED BIT(1) | |
11991 | #define EEE_10G_SUPPORTED BIT(2) | |
11992 | ||
11993 | u32 eee_remote; | |
11994 | #define EEE_REMOTE_TW_TX_MASK 0x0000ffff | |
11995 | #define EEE_REMOTE_TW_TX_OFFSET 0 | |
11996 | #define EEE_REMOTE_TW_RX_MASK 0xffff0000 | |
11997 | #define EEE_REMOTE_TW_RX_OFFSET 16 | |
cac6f691 | 11998 | |
5e9f2035 | 11999 | u32 reserved1; |
cac6f691 SRK |
12000 | u32 oem_cfg_port; |
12001 | #define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003 | |
12002 | #define OEM_CFG_CHANNEL_TYPE_OFFSET 0 | |
12003 | #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1 | |
12004 | #define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2 | |
12005 | #define OEM_CFG_SCHED_TYPE_MASK 0x0000000C | |
12006 | #define OEM_CFG_SCHED_TYPE_OFFSET 2 | |
12007 | #define OEM_CFG_SCHED_TYPE_ETS 0x1 | |
12008 | #define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2 | |
351a4ded | 12009 | }; |
fe56b9e6 YM |
12010 | |
12011 | struct public_func { | |
351a4ded | 12012 | u32 reserved0[2]; |
fe56b9e6 | 12013 | |
351a4ded YM |
12014 | u32 mtu_size; |
12015 | ||
12016 | u32 reserved[7]; | |
12017 | ||
12018 | u32 config; | |
12019 | #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 | |
12020 | #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002 | |
12021 | #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001 | |
12022 | ||
12023 | #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0 | |
12024 | #define FUNC_MF_CFG_PROTOCOL_SHIFT 4 | |
12025 | #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000 | |
c5ac9319 | 12026 | #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010 |
1e128c81 | 12027 | #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020 |
c5ac9319 | 12028 | #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030 |
351a4ded YM |
12029 | #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030 |
12030 | ||
12031 | #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00 | |
12032 | #define FUNC_MF_CFG_MIN_BW_SHIFT 8 | |
12033 | #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 | |
12034 | #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000 | |
12035 | #define FUNC_MF_CFG_MAX_BW_SHIFT 16 | |
12036 | #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000 | |
12037 | ||
12038 | u32 status; | |
12039 | #define FUNC_STATUS_VLINK_DOWN 0x00000001 | |
12040 | ||
12041 | u32 mac_upper; | |
12042 | #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff | |
12043 | #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 | |
12044 | #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK | |
12045 | u32 mac_lower; | |
12046 | #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff | |
12047 | ||
12048 | u32 fcoe_wwn_port_name_upper; | |
12049 | u32 fcoe_wwn_port_name_lower; | |
12050 | ||
12051 | u32 fcoe_wwn_node_name_upper; | |
12052 | u32 fcoe_wwn_node_name_lower; | |
12053 | ||
12054 | u32 ovlan_stag; | |
12055 | #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff | |
12056 | #define FUNC_MF_CFG_OV_STAG_SHIFT 0 | |
12057 | #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK | |
12058 | ||
12059 | u32 pf_allocation; | |
12060 | ||
12061 | u32 preserve_data; | |
12062 | ||
12063 | u32 driver_last_activity_ts; | |
12064 | ||
12065 | u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; | |
12066 | ||
12067 | u32 drv_id; | |
12068 | #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff | |
12069 | #define DRV_ID_PDA_COMP_VER_SHIFT 0 | |
12070 | ||
5d24bcf1 | 12071 | #define LOAD_REQ_HSI_VERSION 2 |
351a4ded YM |
12072 | #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000 |
12073 | #define DRV_ID_MCP_HSI_VER_SHIFT 16 | |
5d24bcf1 TT |
12074 | #define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << \ |
12075 | DRV_ID_MCP_HSI_VER_SHIFT) | |
351a4ded YM |
12076 | |
12077 | #define DRV_ID_DRV_TYPE_MASK 0x7f000000 | |
12078 | #define DRV_ID_DRV_TYPE_SHIFT 24 | |
12079 | #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT) | |
12080 | #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT) | |
12081 | ||
12082 | #define DRV_ID_DRV_INIT_HW_MASK 0x80000000 | |
12083 | #define DRV_ID_DRV_INIT_HW_SHIFT 31 | |
12084 | #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT) | |
cac6f691 SRK |
12085 | |
12086 | u32 oem_cfg_func; | |
12087 | #define OEM_CFG_FUNC_TC_MASK 0x0000000F | |
12088 | #define OEM_CFG_FUNC_TC_OFFSET 0 | |
12089 | #define OEM_CFG_FUNC_TC_0 0x0 | |
12090 | #define OEM_CFG_FUNC_TC_1 0x1 | |
12091 | #define OEM_CFG_FUNC_TC_2 0x2 | |
12092 | #define OEM_CFG_FUNC_TC_3 0x3 | |
12093 | #define OEM_CFG_FUNC_TC_4 0x4 | |
12094 | #define OEM_CFG_FUNC_TC_5 0x5 | |
12095 | #define OEM_CFG_FUNC_TC_6 0x6 | |
12096 | #define OEM_CFG_FUNC_TC_7 0x7 | |
12097 | ||
12098 | #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030 | |
12099 | #define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET 4 | |
12100 | #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1 | |
12101 | #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2 | |
351a4ded | 12102 | }; |
fe56b9e6 YM |
12103 | |
12104 | struct mcp_mac { | |
351a4ded YM |
12105 | u32 mac_upper; |
12106 | u32 mac_lower; | |
fe56b9e6 YM |
12107 | }; |
12108 | ||
12109 | struct mcp_val64 { | |
351a4ded YM |
12110 | u32 lo; |
12111 | u32 hi; | |
fe56b9e6 YM |
12112 | }; |
12113 | ||
12114 | struct mcp_file_att { | |
351a4ded YM |
12115 | u32 nvm_start_addr; |
12116 | u32 len; | |
12117 | }; | |
12118 | ||
12119 | struct bist_nvm_image_att { | |
12120 | u32 return_code; | |
12121 | u32 image_type; | |
12122 | u32 nvm_start_addr; | |
12123 | u32 len; | |
fe56b9e6 YM |
12124 | }; |
12125 | ||
12126 | #define MCP_DRV_VER_STR_SIZE 16 | |
12127 | #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32)) | |
12128 | #define MCP_DRV_NVM_BUF_LEN 32 | |
12129 | struct drv_version_stc { | |
351a4ded YM |
12130 | u32 version; |
12131 | u8 name[MCP_DRV_VER_STR_SIZE - 4]; | |
12132 | }; | |
12133 | ||
12134 | struct lan_stats_stc { | |
12135 | u64 ucast_rx_pkts; | |
12136 | u64 ucast_tx_pkts; | |
12137 | u32 fcs_err; | |
12138 | u32 rserved; | |
12139 | }; | |
12140 | ||
1e128c81 AE |
12141 | struct fcoe_stats_stc { |
12142 | u64 rx_pkts; | |
12143 | u64 tx_pkts; | |
12144 | u32 fcs_err; | |
12145 | u32 login_failure; | |
12146 | }; | |
12147 | ||
351a4ded YM |
12148 | struct ocbb_data_stc { |
12149 | u32 ocbb_host_addr; | |
12150 | u32 ocsd_host_addr; | |
12151 | u32 ocsd_req_update_interval; | |
12152 | }; | |
12153 | ||
12154 | #define MAX_NUM_OF_SENSORS 7 | |
12155 | struct temperature_status_stc { | |
12156 | u32 num_of_sensors; | |
12157 | u32 sensor[MAX_NUM_OF_SENSORS]; | |
12158 | }; | |
12159 | ||
12160 | /* crash dump configuration header */ | |
12161 | struct mdump_config_stc { | |
12162 | u32 version; | |
12163 | u32 config; | |
12164 | u32 epoc; | |
12165 | u32 num_of_logs; | |
12166 | u32 valid_logs; | |
fe56b9e6 YM |
12167 | }; |
12168 | ||
2edbff8d TT |
12169 | enum resource_id_enum { |
12170 | RESOURCE_NUM_SB_E = 0, | |
12171 | RESOURCE_NUM_L2_QUEUE_E = 1, | |
12172 | RESOURCE_NUM_VPORT_E = 2, | |
12173 | RESOURCE_NUM_VMQ_E = 3, | |
12174 | RESOURCE_FACTOR_NUM_RSS_PF_E = 4, | |
12175 | RESOURCE_FACTOR_RSS_PER_VF_E = 5, | |
12176 | RESOURCE_NUM_RL_E = 6, | |
12177 | RESOURCE_NUM_PQ_E = 7, | |
12178 | RESOURCE_NUM_VF_E = 8, | |
12179 | RESOURCE_VFC_FILTER_E = 9, | |
12180 | RESOURCE_ILT_E = 10, | |
12181 | RESOURCE_CQS_E = 11, | |
12182 | RESOURCE_GFT_PROFILES_E = 12, | |
12183 | RESOURCE_NUM_TC_E = 13, | |
12184 | RESOURCE_NUM_RSS_ENGINES_E = 14, | |
12185 | RESOURCE_LL2_QUEUE_E = 15, | |
12186 | RESOURCE_RDMA_STATS_QUEUE_E = 16, | |
9c8517c4 | 12187 | RESOURCE_BDQ_E = 17, |
2edbff8d TT |
12188 | RESOURCE_MAX_NUM, |
12189 | RESOURCE_NUM_INVALID = 0xFFFFFFFF | |
12190 | }; | |
12191 | ||
12192 | /* Resource ID is to be filled by the driver in the MB request | |
12193 | * Size, offset & flags to be filled by the MFW in the MB response | |
12194 | */ | |
12195 | struct resource_info { | |
12196 | enum resource_id_enum res_id; | |
12197 | u32 size; /* number of allocated resources */ | |
12198 | u32 offset; /* Offset of the 1st resource */ | |
12199 | u32 vf_size; | |
12200 | u32 vf_offset; | |
12201 | u32 flags; | |
12202 | #define RESOURCE_ELEMENT_STRICT (1 << 0) | |
12203 | }; | |
12204 | ||
5d24bcf1 TT |
12205 | #define DRV_ROLE_NONE 0 |
12206 | #define DRV_ROLE_PREBOOT 1 | |
12207 | #define DRV_ROLE_OS 2 | |
12208 | #define DRV_ROLE_KDUMP 3 | |
12209 | ||
12210 | struct load_req_stc { | |
12211 | u32 drv_ver_0; | |
12212 | u32 drv_ver_1; | |
12213 | u32 fw_ver; | |
12214 | u32 misc0; | |
12215 | #define LOAD_REQ_ROLE_MASK 0x000000FF | |
12216 | #define LOAD_REQ_ROLE_SHIFT 0 | |
12217 | #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00 | |
12218 | #define LOAD_REQ_LOCK_TO_SHIFT 8 | |
12219 | #define LOAD_REQ_LOCK_TO_DEFAULT 0 | |
12220 | #define LOAD_REQ_LOCK_TO_NONE 255 | |
12221 | #define LOAD_REQ_FORCE_MASK 0x000F0000 | |
12222 | #define LOAD_REQ_FORCE_SHIFT 16 | |
12223 | #define LOAD_REQ_FORCE_NONE 0 | |
12224 | #define LOAD_REQ_FORCE_PF 1 | |
12225 | #define LOAD_REQ_FORCE_ALL 2 | |
12226 | #define LOAD_REQ_FLAGS0_MASK 0x00F00000 | |
12227 | #define LOAD_REQ_FLAGS0_SHIFT 20 | |
12228 | #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0) | |
12229 | }; | |
12230 | ||
12231 | struct load_rsp_stc { | |
12232 | u32 drv_ver_0; | |
12233 | u32 drv_ver_1; | |
12234 | u32 fw_ver; | |
12235 | u32 misc0; | |
12236 | #define LOAD_RSP_ROLE_MASK 0x000000FF | |
12237 | #define LOAD_RSP_ROLE_SHIFT 0 | |
12238 | #define LOAD_RSP_HSI_MASK 0x0000FF00 | |
12239 | #define LOAD_RSP_HSI_SHIFT 8 | |
12240 | #define LOAD_RSP_FLAGS0_MASK 0x000F0000 | |
12241 | #define LOAD_RSP_FLAGS0_SHIFT 16 | |
12242 | #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0) | |
12243 | }; | |
12244 | ||
fe56b9e6 | 12245 | union drv_union_data { |
351a4ded YM |
12246 | u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD]; |
12247 | struct mcp_mac wol_mac; | |
12248 | ||
12249 | struct eth_phy_cfg drv_phy_cfg; | |
fe56b9e6 | 12250 | |
351a4ded | 12251 | struct mcp_val64 val64; |
fe56b9e6 | 12252 | |
351a4ded | 12253 | u8 raw_data[MCP_DRV_NVM_BUF_LEN]; |
fe56b9e6 | 12254 | |
351a4ded | 12255 | struct mcp_file_att file_att; |
fe56b9e6 | 12256 | |
351a4ded | 12257 | u32 ack_vf_disabled[VF_MAX_STATIC / 32]; |
fe56b9e6 | 12258 | |
351a4ded | 12259 | struct drv_version_stc drv_version; |
fe56b9e6 | 12260 | |
351a4ded | 12261 | struct lan_stats_stc lan_stats; |
1e128c81 | 12262 | struct fcoe_stats_stc fcoe_stats; |
351a4ded YM |
12263 | struct ocbb_data_stc ocbb_info; |
12264 | struct temperature_status_stc temp_info; | |
2edbff8d | 12265 | struct resource_info resource; |
351a4ded YM |
12266 | struct bist_nvm_image_att nvm_image_att; |
12267 | struct mdump_config_stc mdump_config; | |
fe56b9e6 YM |
12268 | }; |
12269 | ||
12270 | struct public_drv_mb { | |
12271 | u32 drv_mb_header; | |
351a4ded YM |
12272 | #define DRV_MSG_CODE_MASK 0xffff0000 |
12273 | #define DRV_MSG_CODE_LOAD_REQ 0x10000000 | |
12274 | #define DRV_MSG_CODE_LOAD_DONE 0x11000000 | |
12275 | #define DRV_MSG_CODE_INIT_HW 0x12000000 | |
5d24bcf1 | 12276 | #define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000 |
351a4ded YM |
12277 | #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000 |
12278 | #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 | |
12279 | #define DRV_MSG_CODE_INIT_PHY 0x22000000 | |
12280 | #define DRV_MSG_CODE_LINK_RESET 0x23000000 | |
12281 | #define DRV_MSG_CODE_SET_DCBX 0x25000000 | |
0fefbfba SK |
12282 | #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000 |
12283 | #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000 | |
12284 | #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000 | |
12285 | #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000 | |
12286 | #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000 | |
12287 | #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 | |
12288 | #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000 | |
9c8517c4 TT |
12289 | #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000 |
12290 | #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000 | |
0fefbfba SK |
12291 | #define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000 |
12292 | #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000 | |
351a4ded | 12293 | |
4b01e519 | 12294 | #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 |
351a4ded | 12295 | #define DRV_MSG_CODE_NIG_DRAIN 0x30000000 |
2a351fd9 | 12296 | #define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000 |
18a69e36 | 12297 | #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 |
351a4ded YM |
12298 | #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 |
12299 | #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000 | |
88072fd4 | 12300 | #define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000 |
62e4d438 SRK |
12301 | #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000 |
12302 | #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000 | |
c965db44 TT |
12303 | #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 |
12304 | #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 | |
62e4d438 | 12305 | #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000 |
351a4ded YM |
12306 | #define DRV_MSG_CODE_MCP_RESET 0x00090000 |
12307 | #define DRV_MSG_CODE_SET_VERSION 0x000f0000 | |
4102426f | 12308 | #define DRV_MSG_CODE_MCP_HALT 0x00100000 |
0fefbfba SK |
12309 | #define DRV_MSG_CODE_SET_VMAC 0x00110000 |
12310 | #define DRV_MSG_CODE_GET_VMAC 0x00120000 | |
12311 | #define DRV_MSG_CODE_VMAC_TYPE_SHIFT 4 | |
12312 | #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30 | |
12313 | #define DRV_MSG_CODE_VMAC_TYPE_MAC 1 | |
12314 | #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2 | |
12315 | #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3 | |
351a4ded | 12316 | |
6c754246 SRK |
12317 | #define DRV_MSG_CODE_GET_STATS 0x00130000 |
12318 | #define DRV_MSG_CODE_STATS_TYPE_LAN 1 | |
12319 | #define DRV_MSG_CODE_STATS_TYPE_FCOE 2 | |
12320 | #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3 | |
12321 | #define DRV_MSG_CODE_STATS_TYPE_RDMA 4 | |
12322 | ||
4102426f TT |
12323 | #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000 |
12324 | ||
351a4ded YM |
12325 | #define DRV_MSG_CODE_BIST_TEST 0x001e0000 |
12326 | #define DRV_MSG_CODE_SET_LED_MODE 0x00200000 | |
95691c9c | 12327 | #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000 |
dd006921 | 12328 | #define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000 |
95691c9c TT |
12329 | |
12330 | #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F | |
12331 | #define RESOURCE_CMD_REQ_RESC_SHIFT 0 | |
12332 | #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0 | |
12333 | #define RESOURCE_CMD_REQ_OPCODE_SHIFT 5 | |
12334 | #define RESOURCE_OPCODE_REQ 1 | |
12335 | #define RESOURCE_OPCODE_REQ_WO_AGING 2 | |
12336 | #define RESOURCE_OPCODE_REQ_W_AGING 3 | |
12337 | #define RESOURCE_OPCODE_RELEASE 4 | |
12338 | #define RESOURCE_OPCODE_FORCE_RELEASE 5 | |
12339 | #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00 | |
12340 | #define RESOURCE_CMD_REQ_AGE_SHIFT 8 | |
12341 | ||
12342 | #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF | |
12343 | #define RESOURCE_CMD_RSP_OWNER_SHIFT 0 | |
12344 | #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700 | |
12345 | #define RESOURCE_CMD_RSP_OPCODE_SHIFT 8 | |
12346 | #define RESOURCE_OPCODE_GNT 1 | |
12347 | #define RESOURCE_OPCODE_BUSY 2 | |
12348 | #define RESOURCE_OPCODE_RELEASED 3 | |
12349 | #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4 | |
12350 | #define RESOURCE_OPCODE_WRONG_OWNER 5 | |
12351 | #define RESOURCE_OPCODE_UNKNOWN_CMD 255 | |
12352 | ||
12353 | #define RESOURCE_DUMP 0 | |
12354 | ||
6927e826 | 12355 | #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000 |
14d39648 | 12356 | #define DRV_MSG_CODE_OS_WOL 0x002e0000 |
351a4ded | 12357 | |
645874e5 SRK |
12358 | #define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000 |
12359 | #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000 | |
351a4ded | 12360 | #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff |
fe56b9e6 YM |
12361 | |
12362 | u32 drv_mb_param; | |
0fefbfba SK |
12363 | #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000 |
12364 | #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001 | |
12365 | #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002 | |
12366 | #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003 | |
351a4ded YM |
12367 | #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x000000FF |
12368 | #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3 | |
c965db44 | 12369 | |
da090917 | 12370 | #define DRV_MB_PARAM_NVM_LEN_OFFSET 24 |
c965db44 | 12371 | |
351a4ded YM |
12372 | #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0 |
12373 | #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF | |
12374 | #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8 | |
12375 | #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00 | |
6ad8c632 SRK |
12376 | #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 |
12377 | #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0 | |
12378 | ||
0fefbfba SK |
12379 | #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0 |
12380 | #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F | |
12381 | #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0 | |
12382 | #define DRV_MB_PARAM_OV_CURR_CFG_OS 1 | |
12383 | #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2 | |
12384 | #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3 | |
12385 | ||
12386 | #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0 | |
12387 | #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF | |
12388 | #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000 | |
12389 | #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000 | |
12390 | #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00 | |
12391 | #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF | |
12392 | ||
12393 | #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0 | |
12394 | #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF | |
12395 | #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1 | |
12396 | #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2 | |
12397 | #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3 | |
12398 | #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4 | |
12399 | #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5 | |
12400 | ||
12401 | #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0 | |
12402 | #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF | |
12403 | ||
12404 | #define DRV_MB_PARAM_WOL_MASK (DRV_MB_PARAM_WOL_DEFAULT | \ | |
12405 | DRV_MB_PARAM_WOL_DISABLED | \ | |
12406 | DRV_MB_PARAM_WOL_ENABLED) | |
12407 | #define DRV_MB_PARAM_WOL_DEFAULT DRV_MB_PARAM_UNLOAD_WOL_MCP | |
12408 | #define DRV_MB_PARAM_WOL_DISABLED DRV_MB_PARAM_UNLOAD_WOL_DISABLED | |
12409 | #define DRV_MB_PARAM_WOL_ENABLED DRV_MB_PARAM_UNLOAD_WOL_ENABLED | |
12410 | ||
12411 | #define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \ | |
12412 | DRV_MB_PARAM_ESWITCH_MODE_VEB | \ | |
12413 | DRV_MB_PARAM_ESWITCH_MODE_VEPA) | |
12414 | #define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0 | |
12415 | #define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1 | |
12416 | #define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2 | |
351a4ded YM |
12417 | |
12418 | #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 | |
12419 | #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 | |
12420 | #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 | |
fe56b9e6 | 12421 | |
2edbff8d TT |
12422 | /* Resource Allocation params - Driver version support */ |
12423 | #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 | |
12424 | #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 | |
12425 | #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF | |
12426 | #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 | |
12427 | ||
351a4ded YM |
12428 | #define DRV_MB_PARAM_BIST_REGISTER_TEST 1 |
12429 | #define DRV_MB_PARAM_BIST_CLOCK_TEST 2 | |
7a4b21b7 MY |
12430 | #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3 |
12431 | #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4 | |
351a4ded YM |
12432 | |
12433 | #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0 | |
12434 | #define DRV_MB_PARAM_BIST_RC_PASSED 1 | |
12435 | #define DRV_MB_PARAM_BIST_RC_FAILED 2 | |
12436 | #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3 | |
12437 | ||
12438 | #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0 | |
12439 | #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF | |
7a4b21b7 MY |
12440 | #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8 |
12441 | #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00 | |
03dc76ca | 12442 | |
645874e5 SRK |
12443 | #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF |
12444 | #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0 | |
12445 | #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002 | |
12446 | ||
fe56b9e6 | 12447 | u32 fw_mb_header; |
351a4ded | 12448 | #define FW_MSG_CODE_MASK 0xffff0000 |
95691c9c | 12449 | #define FW_MSG_CODE_UNSUPPORTED 0x00000000 |
351a4ded YM |
12450 | #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000 |
12451 | #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 | |
12452 | #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 | |
12453 | #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000 | |
5d24bcf1 | 12454 | #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000 |
351a4ded | 12455 | #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000 |
5d24bcf1 TT |
12456 | #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000 |
12457 | #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000 | |
12458 | #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000 | |
351a4ded YM |
12459 | #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 |
12460 | #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000 | |
12461 | #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000 | |
12462 | #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000 | |
12463 | #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 | |
2edbff8d TT |
12464 | #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000 |
12465 | #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000 | |
12466 | #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000 | |
2a351fd9 | 12467 | #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE 0x3b000000 |
351a4ded | 12468 | #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000 |
c965db44 TT |
12469 | |
12470 | #define FW_MSG_CODE_NVM_OK 0x00010000 | |
62e4d438 SRK |
12471 | #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000 |
12472 | #define FW_MSG_CODE_PHY_OK 0x00110000 | |
351a4ded | 12473 | #define FW_MSG_CODE_OK 0x00160000 |
62e4d438 | 12474 | #define FW_MSG_CODE_ERROR 0x00170000 |
351a4ded | 12475 | |
14d39648 MY |
12476 | #define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000 |
12477 | #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000 | |
88072fd4 | 12478 | #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000 |
351a4ded YM |
12479 | #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff |
12480 | ||
12481 | u32 fw_mb_param; | |
9c8517c4 TT |
12482 | #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 |
12483 | #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 | |
12484 | #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF | |
12485 | #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 | |
351a4ded | 12486 | |
6927e826 MY |
12487 | /* get pf rdma protocol command responce */ |
12488 | #define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0 | |
12489 | #define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1 | |
12490 | #define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2 | |
12491 | #define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3 | |
12492 | ||
645874e5 SRK |
12493 | /* get MFW feature support response */ |
12494 | #define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002 | |
12495 | ||
fc561c8b TT |
12496 | #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0) |
12497 | ||
351a4ded YM |
12498 | u32 drv_pulse_mb; |
12499 | #define DRV_PULSE_SEQ_MASK 0x00007fff | |
12500 | #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 | |
12501 | #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 | |
12502 | ||
fe56b9e6 | 12503 | u32 mcp_pulse_mb; |
351a4ded YM |
12504 | #define MCP_PULSE_SEQ_MASK 0x00007fff |
12505 | #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 | |
12506 | #define MCP_EVENT_MASK 0xffff0000 | |
12507 | #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 | |
fe56b9e6 YM |
12508 | |
12509 | union drv_union_data union_data; | |
12510 | }; | |
12511 | ||
fe56b9e6 YM |
12512 | enum MFW_DRV_MSG_TYPE { |
12513 | MFW_DRV_MSG_LINK_CHANGE, | |
12514 | MFW_DRV_MSG_FLR_FW_ACK_FAILED, | |
12515 | MFW_DRV_MSG_VF_DISABLED, | |
12516 | MFW_DRV_MSG_LLDP_DATA_UPDATED, | |
12517 | MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED, | |
12518 | MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED, | |
351a4ded | 12519 | MFW_DRV_MSG_RESERVED4, |
334c03b5 | 12520 | MFW_DRV_MSG_BW_UPDATE, |
2a351fd9 | 12521 | MFW_DRV_MSG_S_TAG_UPDATE, |
6c754246 SRK |
12522 | MFW_DRV_MSG_GET_LAN_STATS, |
12523 | MFW_DRV_MSG_GET_FCOE_STATS, | |
12524 | MFW_DRV_MSG_GET_ISCSI_STATS, | |
12525 | MFW_DRV_MSG_GET_RDMA_STATS, | |
351a4ded | 12526 | MFW_DRV_MSG_BW_UPDATE10, |
334c03b5 | 12527 | MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE, |
351a4ded | 12528 | MFW_DRV_MSG_BW_UPDATE11, |
cac6f691 | 12529 | MFW_DRV_MSG_OEM_CFG_UPDATE, |
dd006921 | 12530 | MFW_DRV_MSG_GET_TLV_REQ, |
fe56b9e6 YM |
12531 | MFW_DRV_MSG_MAX |
12532 | }; | |
12533 | ||
351a4ded YM |
12534 | #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1) |
12535 | #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2) | |
12536 | #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3) | |
12537 | #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id)) | |
fe56b9e6 YM |
12538 | |
12539 | struct public_mfw_mb { | |
351a4ded YM |
12540 | u32 sup_msgs; |
12541 | u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; | |
12542 | u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; | |
fe56b9e6 YM |
12543 | }; |
12544 | ||
fe56b9e6 | 12545 | enum public_sections { |
351a4ded YM |
12546 | PUBLIC_DRV_MB, |
12547 | PUBLIC_MFW_MB, | |
fe56b9e6 YM |
12548 | PUBLIC_GLOBAL, |
12549 | PUBLIC_PATH, | |
12550 | PUBLIC_PORT, | |
12551 | PUBLIC_FUNC, | |
12552 | PUBLIC_MAX_SECTIONS | |
12553 | }; | |
12554 | ||
fe56b9e6 | 12555 | struct mcp_public_data { |
351a4ded YM |
12556 | u32 num_sections; |
12557 | u32 sections[PUBLIC_MAX_SECTIONS]; | |
12558 | struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX]; | |
12559 | struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX]; | |
12560 | struct public_global global; | |
12561 | struct public_path path[MCP_GLOB_PATH_MAX]; | |
12562 | struct public_port port[MCP_GLOB_PORT_MAX]; | |
12563 | struct public_func func[MCP_GLOB_FUNC_MAX]; | |
fe56b9e6 YM |
12564 | }; |
12565 | ||
dd006921 SRK |
12566 | /* OCBB definitions */ |
12567 | enum tlvs { | |
12568 | /* Category 1: Device Properties */ | |
12569 | DRV_TLV_CLP_STR, | |
12570 | DRV_TLV_CLP_STR_CTD, | |
12571 | /* Category 6: Device Configuration */ | |
12572 | DRV_TLV_SCSI_TO, | |
12573 | DRV_TLV_R_T_TOV, | |
12574 | DRV_TLV_R_A_TOV, | |
12575 | DRV_TLV_E_D_TOV, | |
12576 | DRV_TLV_CR_TOV, | |
12577 | DRV_TLV_BOOT_TYPE, | |
12578 | /* Category 8: Port Configuration */ | |
12579 | DRV_TLV_NPIV_ENABLED, | |
12580 | /* Category 10: Function Configuration */ | |
12581 | DRV_TLV_FEATURE_FLAGS, | |
12582 | DRV_TLV_LOCAL_ADMIN_ADDR, | |
12583 | DRV_TLV_ADDITIONAL_MAC_ADDR_1, | |
12584 | DRV_TLV_ADDITIONAL_MAC_ADDR_2, | |
12585 | DRV_TLV_LSO_MAX_OFFLOAD_SIZE, | |
12586 | DRV_TLV_LSO_MIN_SEGMENT_COUNT, | |
12587 | DRV_TLV_PROMISCUOUS_MODE, | |
12588 | DRV_TLV_TX_DESCRIPTORS_QUEUE_SIZE, | |
12589 | DRV_TLV_RX_DESCRIPTORS_QUEUE_SIZE, | |
12590 | DRV_TLV_NUM_OF_NET_QUEUE_VMQ_CFG, | |
12591 | DRV_TLV_FLEX_NIC_OUTER_VLAN_ID, | |
12592 | DRV_TLV_OS_DRIVER_STATES, | |
12593 | DRV_TLV_PXE_BOOT_PROGRESS, | |
12594 | /* Category 12: FC/FCoE Configuration */ | |
12595 | DRV_TLV_NPIV_STATE, | |
12596 | DRV_TLV_NUM_OF_NPIV_IDS, | |
12597 | DRV_TLV_SWITCH_NAME, | |
12598 | DRV_TLV_SWITCH_PORT_NUM, | |
12599 | DRV_TLV_SWITCH_PORT_ID, | |
12600 | DRV_TLV_VENDOR_NAME, | |
12601 | DRV_TLV_SWITCH_MODEL, | |
12602 | DRV_TLV_SWITCH_FW_VER, | |
12603 | DRV_TLV_QOS_PRIORITY_PER_802_1P, | |
12604 | DRV_TLV_PORT_ALIAS, | |
12605 | DRV_TLV_PORT_STATE, | |
12606 | DRV_TLV_FIP_TX_DESCRIPTORS_QUEUE_SIZE, | |
12607 | DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_SIZE, | |
12608 | DRV_TLV_LINK_FAILURE_COUNT, | |
12609 | DRV_TLV_FCOE_BOOT_PROGRESS, | |
12610 | /* Category 13: iSCSI Configuration */ | |
12611 | DRV_TLV_TARGET_LLMNR_ENABLED, | |
12612 | DRV_TLV_HEADER_DIGEST_FLAG_ENABLED, | |
12613 | DRV_TLV_DATA_DIGEST_FLAG_ENABLED, | |
12614 | DRV_TLV_AUTHENTICATION_METHOD, | |
12615 | DRV_TLV_ISCSI_BOOT_TARGET_PORTAL, | |
12616 | DRV_TLV_MAX_FRAME_SIZE, | |
12617 | DRV_TLV_PDU_TX_DESCRIPTORS_QUEUE_SIZE, | |
12618 | DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_SIZE, | |
12619 | DRV_TLV_ISCSI_BOOT_PROGRESS, | |
12620 | /* Category 20: Device Data */ | |
12621 | DRV_TLV_PCIE_BUS_RX_UTILIZATION, | |
12622 | DRV_TLV_PCIE_BUS_TX_UTILIZATION, | |
12623 | DRV_TLV_DEVICE_CPU_CORES_UTILIZATION, | |
12624 | DRV_TLV_LAST_VALID_DCC_TLV_RECEIVED, | |
12625 | DRV_TLV_NCSI_RX_BYTES_RECEIVED, | |
12626 | DRV_TLV_NCSI_TX_BYTES_SENT, | |
12627 | /* Category 22: Base Port Data */ | |
12628 | DRV_TLV_RX_DISCARDS, | |
12629 | DRV_TLV_RX_ERRORS, | |
12630 | DRV_TLV_TX_ERRORS, | |
12631 | DRV_TLV_TX_DISCARDS, | |
12632 | DRV_TLV_RX_FRAMES_RECEIVED, | |
12633 | DRV_TLV_TX_FRAMES_SENT, | |
12634 | /* Category 23: FC/FCoE Port Data */ | |
12635 | DRV_TLV_RX_BROADCAST_PACKETS, | |
12636 | DRV_TLV_TX_BROADCAST_PACKETS, | |
12637 | /* Category 28: Base Function Data */ | |
12638 | DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV4, | |
12639 | DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV6, | |
12640 | DRV_TLV_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, | |
12641 | DRV_TLV_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, | |
12642 | DRV_TLV_PF_RX_FRAMES_RECEIVED, | |
12643 | DRV_TLV_RX_BYTES_RECEIVED, | |
12644 | DRV_TLV_PF_TX_FRAMES_SENT, | |
12645 | DRV_TLV_TX_BYTES_SENT, | |
12646 | DRV_TLV_IOV_OFFLOAD, | |
12647 | DRV_TLV_PCI_ERRORS_CAP_ID, | |
12648 | DRV_TLV_UNCORRECTABLE_ERROR_STATUS, | |
12649 | DRV_TLV_UNCORRECTABLE_ERROR_MASK, | |
12650 | DRV_TLV_CORRECTABLE_ERROR_STATUS, | |
12651 | DRV_TLV_CORRECTABLE_ERROR_MASK, | |
12652 | DRV_TLV_PCI_ERRORS_AECC_REGISTER, | |
12653 | DRV_TLV_TX_QUEUES_EMPTY, | |
12654 | DRV_TLV_RX_QUEUES_EMPTY, | |
12655 | DRV_TLV_TX_QUEUES_FULL, | |
12656 | DRV_TLV_RX_QUEUES_FULL, | |
12657 | /* Category 29: FC/FCoE Function Data */ | |
12658 | DRV_TLV_FCOE_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, | |
12659 | DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, | |
12660 | DRV_TLV_FCOE_RX_FRAMES_RECEIVED, | |
12661 | DRV_TLV_FCOE_RX_BYTES_RECEIVED, | |
12662 | DRV_TLV_FCOE_TX_FRAMES_SENT, | |
12663 | DRV_TLV_FCOE_TX_BYTES_SENT, | |
12664 | DRV_TLV_CRC_ERROR_COUNT, | |
12665 | DRV_TLV_CRC_ERROR_1_RECEIVED_SOURCE_FC_ID, | |
12666 | DRV_TLV_CRC_ERROR_1_TIMESTAMP, | |
12667 | DRV_TLV_CRC_ERROR_2_RECEIVED_SOURCE_FC_ID, | |
12668 | DRV_TLV_CRC_ERROR_2_TIMESTAMP, | |
12669 | DRV_TLV_CRC_ERROR_3_RECEIVED_SOURCE_FC_ID, | |
12670 | DRV_TLV_CRC_ERROR_3_TIMESTAMP, | |
12671 | DRV_TLV_CRC_ERROR_4_RECEIVED_SOURCE_FC_ID, | |
12672 | DRV_TLV_CRC_ERROR_4_TIMESTAMP, | |
12673 | DRV_TLV_CRC_ERROR_5_RECEIVED_SOURCE_FC_ID, | |
12674 | DRV_TLV_CRC_ERROR_5_TIMESTAMP, | |
12675 | DRV_TLV_LOSS_OF_SYNC_ERROR_COUNT, | |
12676 | DRV_TLV_LOSS_OF_SIGNAL_ERRORS, | |
12677 | DRV_TLV_PRIMITIVE_SEQUENCE_PROTOCOL_ERROR_COUNT, | |
12678 | DRV_TLV_DISPARITY_ERROR_COUNT, | |
12679 | DRV_TLV_CODE_VIOLATION_ERROR_COUNT, | |
12680 | DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_1, | |
12681 | DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_2, | |
12682 | DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_3, | |
12683 | DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_4, | |
12684 | DRV_TLV_LAST_FLOGI_TIMESTAMP, | |
12685 | DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_1, | |
12686 | DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_2, | |
12687 | DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_3, | |
12688 | DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_4, | |
12689 | DRV_TLV_LAST_FLOGI_ACC_TIMESTAMP, | |
12690 | DRV_TLV_LAST_FLOGI_RJT, | |
12691 | DRV_TLV_LAST_FLOGI_RJT_TIMESTAMP, | |
12692 | DRV_TLV_FDISCS_SENT_COUNT, | |
12693 | DRV_TLV_FDISC_ACCS_RECEIVED, | |
12694 | DRV_TLV_FDISC_RJTS_RECEIVED, | |
12695 | DRV_TLV_PLOGI_SENT_COUNT, | |
12696 | DRV_TLV_PLOGI_ACCS_RECEIVED, | |
12697 | DRV_TLV_PLOGI_RJTS_RECEIVED, | |
12698 | DRV_TLV_PLOGI_1_SENT_DESTINATION_FC_ID, | |
12699 | DRV_TLV_PLOGI_1_TIMESTAMP, | |
12700 | DRV_TLV_PLOGI_2_SENT_DESTINATION_FC_ID, | |
12701 | DRV_TLV_PLOGI_2_TIMESTAMP, | |
12702 | DRV_TLV_PLOGI_3_SENT_DESTINATION_FC_ID, | |
12703 | DRV_TLV_PLOGI_3_TIMESTAMP, | |
12704 | DRV_TLV_PLOGI_4_SENT_DESTINATION_FC_ID, | |
12705 | DRV_TLV_PLOGI_4_TIMESTAMP, | |
12706 | DRV_TLV_PLOGI_5_SENT_DESTINATION_FC_ID, | |
12707 | DRV_TLV_PLOGI_5_TIMESTAMP, | |
12708 | DRV_TLV_PLOGI_1_ACC_RECEIVED_SOURCE_FC_ID, | |
12709 | DRV_TLV_PLOGI_1_ACC_TIMESTAMP, | |
12710 | DRV_TLV_PLOGI_2_ACC_RECEIVED_SOURCE_FC_ID, | |
12711 | DRV_TLV_PLOGI_2_ACC_TIMESTAMP, | |
12712 | DRV_TLV_PLOGI_3_ACC_RECEIVED_SOURCE_FC_ID, | |
12713 | DRV_TLV_PLOGI_3_ACC_TIMESTAMP, | |
12714 | DRV_TLV_PLOGI_4_ACC_RECEIVED_SOURCE_FC_ID, | |
12715 | DRV_TLV_PLOGI_4_ACC_TIMESTAMP, | |
12716 | DRV_TLV_PLOGI_5_ACC_RECEIVED_SOURCE_FC_ID, | |
12717 | DRV_TLV_PLOGI_5_ACC_TIMESTAMP, | |
12718 | DRV_TLV_LOGOS_ISSUED, | |
12719 | DRV_TLV_LOGO_ACCS_RECEIVED, | |
12720 | DRV_TLV_LOGO_RJTS_RECEIVED, | |
12721 | DRV_TLV_LOGO_1_RECEIVED_SOURCE_FC_ID, | |
12722 | DRV_TLV_LOGO_1_TIMESTAMP, | |
12723 | DRV_TLV_LOGO_2_RECEIVED_SOURCE_FC_ID, | |
12724 | DRV_TLV_LOGO_2_TIMESTAMP, | |
12725 | DRV_TLV_LOGO_3_RECEIVED_SOURCE_FC_ID, | |
12726 | DRV_TLV_LOGO_3_TIMESTAMP, | |
12727 | DRV_TLV_LOGO_4_RECEIVED_SOURCE_FC_ID, | |
12728 | DRV_TLV_LOGO_4_TIMESTAMP, | |
12729 | DRV_TLV_LOGO_5_RECEIVED_SOURCE_FC_ID, | |
12730 | DRV_TLV_LOGO_5_TIMESTAMP, | |
12731 | DRV_TLV_LOGOS_RECEIVED, | |
12732 | DRV_TLV_ACCS_ISSUED, | |
12733 | DRV_TLV_PRLIS_ISSUED, | |
12734 | DRV_TLV_ACCS_RECEIVED, | |
12735 | DRV_TLV_ABTS_SENT_COUNT, | |
12736 | DRV_TLV_ABTS_ACCS_RECEIVED, | |
12737 | DRV_TLV_ABTS_RJTS_RECEIVED, | |
12738 | DRV_TLV_ABTS_1_SENT_DESTINATION_FC_ID, | |
12739 | DRV_TLV_ABTS_1_TIMESTAMP, | |
12740 | DRV_TLV_ABTS_2_SENT_DESTINATION_FC_ID, | |
12741 | DRV_TLV_ABTS_2_TIMESTAMP, | |
12742 | DRV_TLV_ABTS_3_SENT_DESTINATION_FC_ID, | |
12743 | DRV_TLV_ABTS_3_TIMESTAMP, | |
12744 | DRV_TLV_ABTS_4_SENT_DESTINATION_FC_ID, | |
12745 | DRV_TLV_ABTS_4_TIMESTAMP, | |
12746 | DRV_TLV_ABTS_5_SENT_DESTINATION_FC_ID, | |
12747 | DRV_TLV_ABTS_5_TIMESTAMP, | |
12748 | DRV_TLV_RSCNS_RECEIVED, | |
12749 | DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_1, | |
12750 | DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_2, | |
12751 | DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_3, | |
12752 | DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_4, | |
12753 | DRV_TLV_LUN_RESETS_ISSUED, | |
12754 | DRV_TLV_ABORT_TASK_SETS_ISSUED, | |
12755 | DRV_TLV_TPRLOS_SENT, | |
12756 | DRV_TLV_NOS_SENT_COUNT, | |
12757 | DRV_TLV_NOS_RECEIVED_COUNT, | |
12758 | DRV_TLV_OLS_COUNT, | |
12759 | DRV_TLV_LR_COUNT, | |
12760 | DRV_TLV_LRR_COUNT, | |
12761 | DRV_TLV_LIP_SENT_COUNT, | |
12762 | DRV_TLV_LIP_RECEIVED_COUNT, | |
12763 | DRV_TLV_EOFA_COUNT, | |
12764 | DRV_TLV_EOFNI_COUNT, | |
12765 | DRV_TLV_SCSI_STATUS_CHECK_CONDITION_COUNT, | |
12766 | DRV_TLV_SCSI_STATUS_CONDITION_MET_COUNT, | |
12767 | DRV_TLV_SCSI_STATUS_BUSY_COUNT, | |
12768 | DRV_TLV_SCSI_STATUS_INTERMEDIATE_COUNT, | |
12769 | DRV_TLV_SCSI_STATUS_INTERMEDIATE_CONDITION_MET_COUNT, | |
12770 | DRV_TLV_SCSI_STATUS_RESERVATION_CONFLICT_COUNT, | |
12771 | DRV_TLV_SCSI_STATUS_TASK_SET_FULL_COUNT, | |
12772 | DRV_TLV_SCSI_STATUS_ACA_ACTIVE_COUNT, | |
12773 | DRV_TLV_SCSI_STATUS_TASK_ABORTED_COUNT, | |
12774 | DRV_TLV_SCSI_CHECK_CONDITION_1_RECEIVED_SK_ASC_ASCQ, | |
12775 | DRV_TLV_SCSI_CHECK_1_TIMESTAMP, | |
12776 | DRV_TLV_SCSI_CHECK_CONDITION_2_RECEIVED_SK_ASC_ASCQ, | |
12777 | DRV_TLV_SCSI_CHECK_2_TIMESTAMP, | |
12778 | DRV_TLV_SCSI_CHECK_CONDITION_3_RECEIVED_SK_ASC_ASCQ, | |
12779 | DRV_TLV_SCSI_CHECK_3_TIMESTAMP, | |
12780 | DRV_TLV_SCSI_CHECK_CONDITION_4_RECEIVED_SK_ASC_ASCQ, | |
12781 | DRV_TLV_SCSI_CHECK_4_TIMESTAMP, | |
12782 | DRV_TLV_SCSI_CHECK_CONDITION_5_RECEIVED_SK_ASC_ASCQ, | |
12783 | DRV_TLV_SCSI_CHECK_5_TIMESTAMP, | |
12784 | /* Category 30: iSCSI Function Data */ | |
12785 | DRV_TLV_PDU_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, | |
12786 | DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, | |
12787 | DRV_TLV_ISCSI_PDU_RX_FRAMES_RECEIVED, | |
12788 | DRV_TLV_ISCSI_PDU_RX_BYTES_RECEIVED, | |
12789 | DRV_TLV_ISCSI_PDU_TX_FRAMES_SENT, | |
12790 | DRV_TLV_ISCSI_PDU_TX_BYTES_SENT | |
12791 | }; | |
12792 | ||
fe56b9e6 | 12793 | struct nvm_cfg_mac_address { |
351a4ded YM |
12794 | u32 mac_addr_hi; |
12795 | #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF | |
12796 | #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0 | |
12797 | u32 mac_addr_lo; | |
fe56b9e6 YM |
12798 | }; |
12799 | ||
fe56b9e6 | 12800 | struct nvm_cfg1_glob { |
351a4ded YM |
12801 | u32 generic_cont0; |
12802 | #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0 | |
12803 | #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4 | |
12804 | #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0 | |
12805 | #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1 | |
12806 | #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2 | |
12807 | #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3 | |
12808 | #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4 | |
12809 | #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5 | |
12810 | #define NVM_CFG1_GLOB_MF_MODE_BD 0x6 | |
12811 | #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7 | |
12812 | u32 engineering_change[3]; | |
12813 | u32 manufacturing_id; | |
12814 | u32 serial_number[4]; | |
12815 | u32 pcie_cfg; | |
12816 | u32 mgmt_traffic; | |
12817 | u32 core_cfg; | |
12818 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF | |
12819 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0 | |
12820 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0 | |
12821 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1 | |
12822 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2 | |
12823 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3 | |
12824 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4 | |
12825 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5 | |
12826 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB | |
12827 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC | |
12828 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD | |
12829 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE | |
9c79ddaa MY |
12830 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF |
12831 | ||
351a4ded YM |
12832 | u32 e_lane_cfg1; |
12833 | u32 e_lane_cfg2; | |
12834 | u32 f_lane_cfg1; | |
12835 | u32 f_lane_cfg2; | |
12836 | u32 mps10_preemphasis; | |
12837 | u32 mps10_driver_current; | |
12838 | u32 mps25_preemphasis; | |
12839 | u32 mps25_driver_current; | |
12840 | u32 pci_id; | |
12841 | u32 pci_subsys_id; | |
12842 | u32 bar; | |
12843 | u32 mps10_txfir_main; | |
12844 | u32 mps10_txfir_post; | |
12845 | u32 mps25_txfir_main; | |
12846 | u32 mps25_txfir_post; | |
12847 | u32 manufacture_ver; | |
12848 | u32 manufacture_time; | |
12849 | u32 led_global_settings; | |
12850 | u32 generic_cont1; | |
12851 | u32 mbi_version; | |
ae33666a TT |
12852 | #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF |
12853 | #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0 | |
12854 | #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00 | |
12855 | #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8 | |
12856 | #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000 | |
12857 | #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16 | |
351a4ded YM |
12858 | u32 mbi_date; |
12859 | u32 misc_sig; | |
12860 | u32 device_capabilities; | |
12861 | #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1 | |
1e128c81 | 12862 | #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2 |
c5ac9319 YM |
12863 | #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4 |
12864 | #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8 | |
351a4ded YM |
12865 | u32 power_dissipated; |
12866 | u32 power_consumed; | |
12867 | u32 efi_version; | |
12868 | u32 multi_network_modes_capability; | |
12869 | u32 reserved[41]; | |
fe56b9e6 YM |
12870 | }; |
12871 | ||
12872 | struct nvm_cfg1_path { | |
351a4ded | 12873 | u32 reserved[30]; |
fe56b9e6 YM |
12874 | }; |
12875 | ||
12876 | struct nvm_cfg1_port { | |
351a4ded YM |
12877 | u32 reserved__m_relocated_to_option_123; |
12878 | u32 reserved__m_relocated_to_option_124; | |
12879 | u32 generic_cont0; | |
12880 | #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000 | |
12881 | #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16 | |
12882 | #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0 | |
12883 | #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1 | |
12884 | #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2 | |
12885 | #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3 | |
12886 | #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000 | |
12887 | #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20 | |
12888 | #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1 | |
12889 | #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2 | |
12890 | #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4 | |
12891 | u32 pcie_cfg; | |
12892 | u32 features; | |
12893 | u32 speed_cap_mask; | |
12894 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF | |
12895 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 | |
12896 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1 | |
12897 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2 | |
12898 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8 | |
12899 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10 | |
12900 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20 | |
12901 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 | |
12902 | u32 link_settings; | |
12903 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F | |
12904 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0 | |
12905 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0 | |
12906 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1 | |
12907 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2 | |
12908 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4 | |
12909 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5 | |
12910 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6 | |
12911 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7 | |
12912 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8 | |
12913 | #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070 | |
12914 | #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4 | |
12915 | #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1 | |
12916 | #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2 | |
12917 | #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4 | |
12918 | u32 phy_cfg; | |
12919 | u32 mgmt_traffic; | |
645874e5 | 12920 | |
351a4ded | 12921 | u32 ext_phy; |
645874e5 SRK |
12922 | /* EEE power saving mode */ |
12923 | #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000 | |
12924 | #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16 | |
12925 | #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0 | |
12926 | #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1 | |
12927 | #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2 | |
12928 | #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3 | |
12929 | ||
351a4ded YM |
12930 | u32 mba_cfg1; |
12931 | u32 mba_cfg2; | |
12932 | u32 vf_cfg; | |
12933 | struct nvm_cfg_mac_address lldp_mac_address; | |
12934 | u32 led_port_settings; | |
12935 | u32 transceiver_00; | |
12936 | u32 device_ids; | |
12937 | u32 board_cfg; | |
12938 | u32 mnm_10g_cap; | |
12939 | u32 mnm_10g_ctrl; | |
12940 | u32 mnm_10g_misc; | |
12941 | u32 mnm_25g_cap; | |
12942 | u32 mnm_25g_ctrl; | |
12943 | u32 mnm_25g_misc; | |
12944 | u32 mnm_40g_cap; | |
12945 | u32 mnm_40g_ctrl; | |
12946 | u32 mnm_40g_misc; | |
12947 | u32 mnm_50g_cap; | |
12948 | u32 mnm_50g_ctrl; | |
12949 | u32 mnm_50g_misc; | |
12950 | u32 mnm_100g_cap; | |
12951 | u32 mnm_100g_ctrl; | |
12952 | u32 mnm_100g_misc; | |
12953 | u32 reserved[116]; | |
fe56b9e6 YM |
12954 | }; |
12955 | ||
12956 | struct nvm_cfg1_func { | |
351a4ded YM |
12957 | struct nvm_cfg_mac_address mac_address; |
12958 | u32 rsrv1; | |
12959 | u32 rsrv2; | |
12960 | u32 device_id; | |
12961 | u32 cmn_cfg; | |
12962 | u32 pci_cfg; | |
12963 | struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; | |
12964 | struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; | |
12965 | u32 preboot_generic_cfg; | |
12966 | u32 reserved[8]; | |
fe56b9e6 YM |
12967 | }; |
12968 | ||
12969 | struct nvm_cfg1 { | |
351a4ded YM |
12970 | struct nvm_cfg1_glob glob; |
12971 | struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; | |
12972 | struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; | |
12973 | struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; | |
fe56b9e6 | 12974 | }; |
c965db44 TT |
12975 | |
12976 | enum spad_sections { | |
12977 | SPAD_SECTION_TRACE, | |
12978 | SPAD_SECTION_NVM_CFG, | |
12979 | SPAD_SECTION_PUBLIC, | |
12980 | SPAD_SECTION_PRIVATE, | |
12981 | SPAD_SECTION_MAX | |
12982 | }; | |
12983 | ||
12984 | #define MCP_TRACE_SIZE 2048 /* 2kb */ | |
12985 | ||
12986 | /* This section is located at a fixed location in the beginning of the | |
12987 | * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade. | |
12988 | * All the rest of data has a floating location which differs from version to | |
12989 | * version, and is pointed by the mcp_meta_data below. | |
12990 | * Moreover, the spad_layout section is part of the MFW firmware, and is loaded | |
12991 | * with it from nvram in order to clear this portion. | |
12992 | */ | |
12993 | struct static_init { | |
12994 | u32 num_sections; | |
12995 | offsize_t sections[SPAD_SECTION_MAX]; | |
12996 | #define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_])))) | |
12997 | ||
12998 | struct mcp_trace trace; | |
12999 | #define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace))) | |
13000 | u8 trace_buffer[MCP_TRACE_SIZE]; | |
13001 | #define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer))) | |
13002 | /* running_mfw has the same definition as in nvm_map.h. | |
13003 | * This bit indicate both the running dir, and the running bundle. | |
13004 | * It is set once when the LIM is loaded. | |
13005 | */ | |
13006 | u32 running_mfw; | |
13007 | #define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw)))) | |
13008 | u32 build_time; | |
13009 | #define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time)))) | |
13010 | u32 reset_type; | |
13011 | #define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type)))) | |
13012 | u32 mfw_secure_mode; | |
13013 | #define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode)))) | |
13014 | u16 pme_status_pf_bitmap; | |
13015 | #define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap)))) | |
13016 | u16 pme_enable_pf_bitmap; | |
13017 | #define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap)))) | |
13018 | u32 mim_nvm_addr; | |
13019 | u32 mim_start_addr; | |
13020 | u32 ah_pcie_link_params; | |
13021 | #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff) | |
13022 | #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT (0) | |
13023 | #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00) | |
13024 | #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT (8) | |
13025 | #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000) | |
13026 | #define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT (16) | |
13027 | #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000) | |
13028 | #define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT (24) | |
13029 | #define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params)))) | |
13030 | ||
13031 | u32 rsrv_persist[5]; /* Persist reserved for MFW upgrades */ | |
13032 | }; | |
13033 | ||
7b6859fb MY |
13034 | #define NVM_MAGIC_VALUE 0x669955aa |
13035 | ||
c965db44 TT |
13036 | enum nvm_image_type { |
13037 | NVM_TYPE_TIM1 = 0x01, | |
13038 | NVM_TYPE_TIM2 = 0x02, | |
13039 | NVM_TYPE_MIM1 = 0x03, | |
13040 | NVM_TYPE_MIM2 = 0x04, | |
13041 | NVM_TYPE_MBA = 0x05, | |
13042 | NVM_TYPE_MODULES_PN = 0x06, | |
13043 | NVM_TYPE_VPD = 0x07, | |
13044 | NVM_TYPE_MFW_TRACE1 = 0x08, | |
13045 | NVM_TYPE_MFW_TRACE2 = 0x09, | |
13046 | NVM_TYPE_NVM_CFG1 = 0x0a, | |
13047 | NVM_TYPE_L2B = 0x0b, | |
13048 | NVM_TYPE_DIR1 = 0x0c, | |
13049 | NVM_TYPE_EAGLE_FW1 = 0x0d, | |
13050 | NVM_TYPE_FALCON_FW1 = 0x0e, | |
13051 | NVM_TYPE_PCIE_FW1 = 0x0f, | |
13052 | NVM_TYPE_HW_SET = 0x10, | |
13053 | NVM_TYPE_LIM = 0x11, | |
13054 | NVM_TYPE_AVS_FW1 = 0x12, | |
13055 | NVM_TYPE_DIR2 = 0x13, | |
13056 | NVM_TYPE_CCM = 0x14, | |
13057 | NVM_TYPE_EAGLE_FW2 = 0x15, | |
13058 | NVM_TYPE_FALCON_FW2 = 0x16, | |
13059 | NVM_TYPE_PCIE_FW2 = 0x17, | |
13060 | NVM_TYPE_AVS_FW2 = 0x18, | |
13061 | NVM_TYPE_INIT_HW = 0x19, | |
13062 | NVM_TYPE_DEFAULT_CFG = 0x1a, | |
13063 | NVM_TYPE_MDUMP = 0x1b, | |
13064 | NVM_TYPE_META = 0x1c, | |
13065 | NVM_TYPE_ISCSI_CFG = 0x1d, | |
13066 | NVM_TYPE_FCOE_CFG = 0x1f, | |
13067 | NVM_TYPE_ETH_PHY_FW1 = 0x20, | |
13068 | NVM_TYPE_ETH_PHY_FW2 = 0x21, | |
13069 | NVM_TYPE_MAX, | |
13070 | }; | |
13071 | ||
13072 | #define DIR_ID_1 (0) | |
13073 | ||
fe56b9e6 | 13074 | #endif |