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r8169: simplify interrupt handler
[thirdparty/kernel/stable.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
f1e911d5 18#include <linux/phy.h>
1da177e4
LT		 19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
098b01ad 22#include <linux/io.h>
1da177e4
LT		 23#include <linux/ip.h>
24#include <linux/tcp.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
31#include <net/ip6_checksum.h>
1da177e4 32
1da177e4 33#define MODULENAME "r8169"
1da177e4 34
bca03d5f 35#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
36#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 37#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
38#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 39#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 40#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
41#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 42#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 43#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 44#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 45#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 46#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 47#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 48#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 49#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 50#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
51#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
52#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
53#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 54
b57b7e5a 55#define R8169_MSG_DEFAULT \
f0e837d9 56 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 57
477206a0
JD		 58#define TX_SLOTS_AVAIL(tp) \
59 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
60
61/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
62#define TX_FRAGS_READY_FOR(tp,nr_frags) \
63 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 64
1da177e4
LT		 65/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
66 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 67static const int multicast_filter_limit = 32;
1da177e4 68
aee77e4a 69#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 70#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
71
72#define R8169_REGS_SIZE 256
1d0254dd 73#define R8169_RX_BUF_SIZE (SZ_16K - 1)
1da177e4 74#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 75#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 76#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
77#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
78
79#define RTL8169_TX_TIMEOUT (6*HZ)
1da177e4
LT		 80
81/* write/read MMIO register */
1ef7286e
AS		 82#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
83#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
84#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
85#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
86#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
87#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
1da177e4
LT		 88
89enum mac_version {
85bffe6c
FR		 90 RTL_GIGA_MAC_VER_01 = 0,
91 RTL_GIGA_MAC_VER_02,
92 RTL_GIGA_MAC_VER_03,
93 RTL_GIGA_MAC_VER_04,
94 RTL_GIGA_MAC_VER_05,
95 RTL_GIGA_MAC_VER_06,
96 RTL_GIGA_MAC_VER_07,
97 RTL_GIGA_MAC_VER_08,
98 RTL_GIGA_MAC_VER_09,
99 RTL_GIGA_MAC_VER_10,
100 RTL_GIGA_MAC_VER_11,
101 RTL_GIGA_MAC_VER_12,
102 RTL_GIGA_MAC_VER_13,
103 RTL_GIGA_MAC_VER_14,
104 RTL_GIGA_MAC_VER_15,
105 RTL_GIGA_MAC_VER_16,
106 RTL_GIGA_MAC_VER_17,
107 RTL_GIGA_MAC_VER_18,
108 RTL_GIGA_MAC_VER_19,
109 RTL_GIGA_MAC_VER_20,
110 RTL_GIGA_MAC_VER_21,
111 RTL_GIGA_MAC_VER_22,
112 RTL_GIGA_MAC_VER_23,
113 RTL_GIGA_MAC_VER_24,
114 RTL_GIGA_MAC_VER_25,
115 RTL_GIGA_MAC_VER_26,
116 RTL_GIGA_MAC_VER_27,
117 RTL_GIGA_MAC_VER_28,
118 RTL_GIGA_MAC_VER_29,
119 RTL_GIGA_MAC_VER_30,
120 RTL_GIGA_MAC_VER_31,
121 RTL_GIGA_MAC_VER_32,
122 RTL_GIGA_MAC_VER_33,
70090424 123 RTL_GIGA_MAC_VER_34,
c2218925
HW		 124 RTL_GIGA_MAC_VER_35,
125 RTL_GIGA_MAC_VER_36,
7e18dca1 126 RTL_GIGA_MAC_VER_37,
b3d7b2f2 127 RTL_GIGA_MAC_VER_38,
5598bfe5 128 RTL_GIGA_MAC_VER_39,
c558386b
HW		 129 RTL_GIGA_MAC_VER_40,
130 RTL_GIGA_MAC_VER_41,
57538c4a 131 RTL_GIGA_MAC_VER_42,
58152cd4 132 RTL_GIGA_MAC_VER_43,
45dd95c4 133 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 134 RTL_GIGA_MAC_VER_45,
135 RTL_GIGA_MAC_VER_46,
136 RTL_GIGA_MAC_VER_47,
137 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 138 RTL_GIGA_MAC_VER_49,
139 RTL_GIGA_MAC_VER_50,
140 RTL_GIGA_MAC_VER_51,
85bffe6c 141 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 142};
143
2b7b4318
FR		 144enum rtl_tx_desc_version {
145 RTL_TD_0 = 0,
146 RTL_TD_1 = 1,
147};
148
d58d46b5
FR		 149#define JUMBO_1K ETH_DATA_LEN
150#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
151#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
152#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
153#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
154
6ed0e08f 155#define _R(NAME,TD,FW,SZ) { \
d58d46b5
FR		 156 .name = NAME, \
157 .txd_version = TD, \
158 .fw_name = FW, \
159 .jumbo_max = SZ, \
d58d46b5 160}
1da177e4 161
3c6bee1d 162static const struct {
1da177e4 163 const char *name;
2b7b4318 164 enum rtl_tx_desc_version txd_version;
953a12cc 165 const char *fw_name;
d58d46b5 166 u16 jumbo_max;
85bffe6c
FR		 167} rtl_chip_infos[] = {
168 /* PCI devices. */
169 [RTL_GIGA_MAC_VER_01] =
6ed0e08f 170 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 171 [RTL_GIGA_MAC_VER_02] =
6ed0e08f 172 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 173 [RTL_GIGA_MAC_VER_03] =
6ed0e08f 174 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 175 [RTL_GIGA_MAC_VER_04] =
6ed0e08f 176 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 177 [RTL_GIGA_MAC_VER_05] =
6ed0e08f 178 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 179 [RTL_GIGA_MAC_VER_06] =
6ed0e08f 180 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c
FR		 181 /* PCI-E devices. */
182 [RTL_GIGA_MAC_VER_07] =
6ed0e08f 183 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
85bffe6c 184 [RTL_GIGA_MAC_VER_08] =
6ed0e08f 185 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
85bffe6c 186 [RTL_GIGA_MAC_VER_09] =
6ed0e08f 187 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
85bffe6c 188 [RTL_GIGA_MAC_VER_10] =
6ed0e08f 189 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 190 [RTL_GIGA_MAC_VER_11] =
6ed0e08f 191 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
85bffe6c 192 [RTL_GIGA_MAC_VER_12] =
6ed0e08f 193 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
85bffe6c 194 [RTL_GIGA_MAC_VER_13] =
6ed0e08f 195 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 196 [RTL_GIGA_MAC_VER_14] =
6ed0e08f 197 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 198 [RTL_GIGA_MAC_VER_15] =
6ed0e08f 199 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 200 [RTL_GIGA_MAC_VER_16] =
6ed0e08f 201 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 202 [RTL_GIGA_MAC_VER_17] =
6ed0e08f 203 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
85bffe6c 204 [RTL_GIGA_MAC_VER_18] =
6ed0e08f 205 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 206 [RTL_GIGA_MAC_VER_19] =
6ed0e08f 207 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 208 [RTL_GIGA_MAC_VER_20] =
6ed0e08f 209 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 210 [RTL_GIGA_MAC_VER_21] =
6ed0e08f 211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 212 [RTL_GIGA_MAC_VER_22] =
6ed0e08f 213 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 214 [RTL_GIGA_MAC_VER_23] =
6ed0e08f 215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 216 [RTL_GIGA_MAC_VER_24] =
6ed0e08f 217 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 218 [RTL_GIGA_MAC_VER_25] =
6ed0e08f 219 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, JUMBO_9K),
85bffe6c 220 [RTL_GIGA_MAC_VER_26] =
6ed0e08f 221 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, JUMBO_9K),
85bffe6c 222 [RTL_GIGA_MAC_VER_27] =
6ed0e08f 223 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
85bffe6c 224 [RTL_GIGA_MAC_VER_28] =
6ed0e08f 225 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
85bffe6c 226 [RTL_GIGA_MAC_VER_29] =
6ed0e08f 227 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
85bffe6c 228 [RTL_GIGA_MAC_VER_30] =
6ed0e08f 229 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
85bffe6c 230 [RTL_GIGA_MAC_VER_31] =
6ed0e08f 231 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
85bffe6c 232 [RTL_GIGA_MAC_VER_32] =
6ed0e08f 233 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, JUMBO_9K),
85bffe6c 234 [RTL_GIGA_MAC_VER_33] =
6ed0e08f 235 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, JUMBO_9K),
70090424 236 [RTL_GIGA_MAC_VER_34] =
6ed0e08f 237 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, JUMBO_9K),
c2218925 238 [RTL_GIGA_MAC_VER_35] =
6ed0e08f 239 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, JUMBO_9K),
c2218925 240 [RTL_GIGA_MAC_VER_36] =
6ed0e08f 241 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, JUMBO_9K),
7e18dca1 242 [RTL_GIGA_MAC_VER_37] =
6ed0e08f 243 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1, JUMBO_1K),
b3d7b2f2 244 [RTL_GIGA_MAC_VER_38] =
6ed0e08f 245 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1, JUMBO_9K),
5598bfe5 246 [RTL_GIGA_MAC_VER_39] =
6ed0e08f 247 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1, JUMBO_1K),
c558386b 248 [RTL_GIGA_MAC_VER_40] =
6ed0e08f 249 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2, JUMBO_9K),
c558386b 250 [RTL_GIGA_MAC_VER_41] =
6ed0e08f 251 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K),
57538c4a 252 [RTL_GIGA_MAC_VER_42] =
6ed0e08f 253 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3, JUMBO_9K),
58152cd4 254 [RTL_GIGA_MAC_VER_43] =
6ed0e08f 255 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2, JUMBO_1K),
45dd95c4 256 [RTL_GIGA_MAC_VER_44] =
6ed0e08f 257 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2, JUMBO_9K),
6e1d0b89 258 [RTL_GIGA_MAC_VER_45] =
6ed0e08f 259 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1, JUMBO_9K),
6e1d0b89 260 [RTL_GIGA_MAC_VER_46] =
6ed0e08f 261 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2, JUMBO_9K),
6e1d0b89 262 [RTL_GIGA_MAC_VER_47] =
6ed0e08f 263 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1, JUMBO_1K),
6e1d0b89 264 [RTL_GIGA_MAC_VER_48] =
6ed0e08f 265 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2, JUMBO_1K),
935e2218 266 [RTL_GIGA_MAC_VER_49] =
6ed0e08f 267 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
935e2218 268 [RTL_GIGA_MAC_VER_50] =
6ed0e08f 269 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
935e2218 270 [RTL_GIGA_MAC_VER_51] =
6ed0e08f 271 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
953a12cc 272};
85bffe6c 273#undef _R
953a12cc 274
bcf0bf90
FR		 275enum cfg_version {
276 RTL_CFG_0 = 0x00,
277 RTL_CFG_1,
278 RTL_CFG_2
279};
280
9baa3c34 281static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 282 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 283 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
610c9087 284 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
d81bf551 285 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 286 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 287 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 288 { PCI_VENDOR_ID_DLINK, 0x4300,
289 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 290 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 291 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 292 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 293 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
294 { PCI_VENDOR_ID_LINKSYS, 0x1032,
295 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 296 { 0x0001, 0x8168,
297 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 298 {0,},
299};
300
301MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
302
27896c83 303static int use_dac = -1;
b57b7e5a
SH		 304static struct {
305 u32 msg_enable;
306} debug = { -1 };
1da177e4 307
07d3f51f
FR		 308enum rtl_registers {
309 MAC0 = 0, /* Ethernet hardware address. */
773d2021 310 MAC4 = 4,
07d3f51f
FR		 311 MAR0 = 8, /* Multicast filter. */
312 CounterAddrLow = 0x10,
313 CounterAddrHigh = 0x14,
314 TxDescStartAddrLow = 0x20,
315 TxDescStartAddrHigh = 0x24,
316 TxHDescStartAddrLow = 0x28,
317 TxHDescStartAddrHigh = 0x2c,
318 FLASH = 0x30,
319 ERSR = 0x36,
320 ChipCmd = 0x37,
321 TxPoll = 0x38,
322 IntrMask = 0x3c,
323 IntrStatus = 0x3e,
4f6b00e5 324
07d3f51f 325 TxConfig = 0x40,
4f6b00e5
HW		 326#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
327#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 328
4f6b00e5
HW		 329 RxConfig = 0x44,
330#define RX128_INT_EN (1 << 15) /* 8111c and later */
331#define RX_MULTI_EN (1 << 14) /* 8111c only */
332#define RXCFG_FIFO_SHIFT 13
333 /* No threshold before first PCI xfer */
334#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 335#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 336#define RXCFG_DMA_SHIFT 8
337 /* Unlimited maximum PCI burst. */
338#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 339
07d3f51f
FR		 340 RxMissed = 0x4c,
341 Cfg9346 = 0x50,
342 Config0 = 0x51,
343 Config1 = 0x52,
344 Config2 = 0x53,
d387b427
FR		 345#define PME_SIGNAL (1 << 5) /* 8168c and later */
346
07d3f51f
FR		 347 Config3 = 0x54,
348 Config4 = 0x55,
349 Config5 = 0x56,
350 MultiIntr = 0x5c,
351 PHYAR = 0x60,
07d3f51f
FR		 352 PHYstatus = 0x6c,
353 RxMaxSize = 0xda,
354 CPlusCmd = 0xe0,
355 IntrMitigate = 0xe2,
50970831
FR		 356
357#define RTL_COALESCE_MASK 0x0f
358#define RTL_COALESCE_SHIFT 4
359#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
360#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
361
07d3f51f
FR		 362 RxDescAddrLow = 0xe4,
363 RxDescAddrHigh = 0xe8,
f0298f81 364 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
365
366#define NoEarlyTx 0x3f /* Max value : no early transmit. */
367
368 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
369
370#define TxPacketMax (8064 >> 7)
3090bd9a 371#define EarlySize 0x27
f0298f81 372
07d3f51f
FR		 373 FuncEvent = 0xf0,
374 FuncEventMask = 0xf4,
375 FuncPresetState = 0xf8,
935e2218
CHL		 376 IBCR0 = 0xf8,
377 IBCR2 = 0xf9,
378 IBIMR0 = 0xfa,
379 IBISR0 = 0xfb,
07d3f51f 380 FuncForceEvent = 0xfc,
1da177e4
LT		 381};
382
f162a5d1
FR		 383enum rtl8168_8101_registers {
384 CSIDR = 0x64,
385 CSIAR = 0x68,
386#define CSIAR_FLAG 0x80000000
387#define CSIAR_WRITE_CMD 0x80000000
ff1d7331
HK		 388#define CSIAR_BYTE_ENABLE 0x0000f000
389#define CSIAR_ADDR_MASK 0x00000fff
065c27c1 390 PMCH = 0x6f,
f162a5d1
FR		 391 EPHYAR = 0x80,
392#define EPHYAR_FLAG 0x80000000
393#define EPHYAR_WRITE_CMD 0x80000000
394#define EPHYAR_REG_MASK 0x1f
395#define EPHYAR_REG_SHIFT 16
396#define EPHYAR_DATA_MASK 0xffff
5a5e4443 397 DLLPR = 0xd0,
4f6b00e5 398#define PFM_EN (1 << 6)
6e1d0b89 399#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 400 DBG_REG = 0xd1,
401#define FIX_NAK_1 (1 << 4)
402#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 403 TWSI = 0xd2,
404 MCU = 0xd3,
4f6b00e5 405#define NOW_IS_OOB (1 << 7)
c558386b
HW		 406#define TX_EMPTY (1 << 5)
407#define RX_EMPTY (1 << 4)
408#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 409#define EN_NDP (1 << 3)
410#define EN_OOB_RESET (1 << 2)
c558386b 411#define LINK_LIST_RDY (1 << 1)
daf9df6d 412 EFUSEAR = 0xdc,
413#define EFUSEAR_FLAG 0x80000000
414#define EFUSEAR_WRITE_CMD 0x80000000
415#define EFUSEAR_READ_CMD 0x00000000
416#define EFUSEAR_REG_MASK 0x03ff
417#define EFUSEAR_REG_SHIFT 8
418#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 419 MISC_1 = 0xf2,
420#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 421};
422
c0e45c1c 423enum rtl8168_registers {
4f6b00e5
HW		 424 LED_FREQ = 0x1a,
425 EEE_LED = 0x1b,
b646d900 426 ERIDR = 0x70,
427 ERIAR = 0x74,
428#define ERIAR_FLAG 0x80000000
429#define ERIAR_WRITE_CMD 0x80000000
430#define ERIAR_READ_CMD 0x00000000
431#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 432#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 433#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
434#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
435#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 436#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 437#define ERIAR_MASK_SHIFT 12
438#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
439#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 440#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 441#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 442#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 443 EPHY_RXER_NUM = 0x7c,
444 OCPDR = 0xb0, /* OCP GPHY access */
445#define OCPDR_WRITE_CMD 0x80000000
446#define OCPDR_READ_CMD 0x00000000
447#define OCPDR_REG_MASK 0x7f
448#define OCPDR_GPHY_REG_SHIFT 16
449#define OCPDR_DATA_MASK 0xffff
450 OCPAR = 0xb4,
451#define OCPAR_FLAG 0x80000000
452#define OCPAR_GPHY_WRITE_CMD 0x8000f060
453#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 454 GPHY_OCP = 0xb8,
01dc7fec 455 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
456 MISC = 0xf0, /* 8168e only. */
cecb5fd7 457#define TXPLA_RST (1 << 29)
5598bfe5 458#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 459#define PWM_EN (1 << 22)
c558386b 460#define RXDV_GATED_EN (1 << 19)
5598bfe5 461#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 462};
463
07d3f51f 464enum rtl_register_content {
1da177e4 465 /* InterruptStatusBits */
07d3f51f
FR		 466 SYSErr = 0x8000,
467 PCSTimeout = 0x4000,
468 SWInt = 0x0100,
469 TxDescUnavail = 0x0080,
470 RxFIFOOver = 0x0040,
471 LinkChg = 0x0020,
472 RxOverflow = 0x0010,
473 TxErr = 0x0008,
474 TxOK = 0x0004,
475 RxErr = 0x0002,
476 RxOK = 0x0001,
1da177e4
LT		 477
478 /* RxStatusDesc */
e03f33af 479 RxBOVF = (1 << 24),
9dccf611
FR		 480 RxFOVF = (1 << 23),
481 RxRWT = (1 << 22),
482 RxRES = (1 << 21),
483 RxRUNT = (1 << 20),
484 RxCRC = (1 << 19),
1da177e4
LT		 485
486 /* ChipCmdBits */
4f6b00e5 487 StopReq = 0x80,
07d3f51f
FR		 488 CmdReset = 0x10,
489 CmdRxEnb = 0x08,
490 CmdTxEnb = 0x04,
491 RxBufEmpty = 0x01,
1da177e4 492
275391a4
FR		 493 /* TXPoll register p.5 */
494 HPQ = 0x80, /* Poll cmd on the high prio queue */
495 NPQ = 0x40, /* Poll cmd on the low prio queue */
496 FSWInt = 0x01, /* Forced software interrupt */
497
1da177e4 498 /* Cfg9346Bits */
07d3f51f
FR		 499 Cfg9346_Lock = 0x00,
500 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 501
502 /* rx_mode_bits */
07d3f51f
FR		 503 AcceptErr = 0x20,
504 AcceptRunt = 0x10,
505 AcceptBroadcast = 0x08,
506 AcceptMulticast = 0x04,
507 AcceptMyPhys = 0x02,
508 AcceptAllPhys = 0x01,
1687b566 509#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 510
1da177e4
LT		 511 /* TxConfigBits */
512 TxInterFrameGapShift = 24,
513 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
514
5d06a99f 515 /* Config1 register p.24 */
f162a5d1
FR		 516 LEDS1 = (1 << 7),
517 LEDS0 = (1 << 6),
f162a5d1
FR		 518 Speed_down = (1 << 4),
519 MEMMAP = (1 << 3),
520 IOMAP = (1 << 2),
521 VPD = (1 << 1),
5d06a99f
FR		 522 PMEnable = (1 << 0), /* Power Management Enable */
523
6dccd16b 524 /* Config2 register p. 25 */
57538c4a 525 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 526 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 527 PCI_Clock_66MHz = 0x01,
528 PCI_Clock_33MHz = 0x00,
529
61a4dcc2
FR		 530 /* Config3 register p.25 */
531 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
532 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 533 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 534 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 535 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 536
d58d46b5
FR		 537 /* Config4 register */
538 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
539
5d06a99f 540 /* Config5 register p.27 */
61a4dcc2
FR		 541 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
542 MWF = (1 << 5), /* Accept Multicast wakeup frame */
543 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 544 Spi_en = (1 << 3),
61a4dcc2 545 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 546 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 547 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 548
1da177e4 549 /* CPlusCmd p.31 */
f162a5d1
FR		 550 EnableBist = (1 << 15), // 8168 8101
551 Mac_dbgo_oe = (1 << 14), // 8168 8101
552 Normal_mode = (1 << 13), // unused
553 Force_half_dup = (1 << 12), // 8168 8101
554 Force_rxflow_en = (1 << 11), // 8168 8101
555 Force_txflow_en = (1 << 10), // 8168 8101
556 Cxpl_dbg_sel = (1 << 9), // 8168 8101
557 ASF = (1 << 8), // 8168 8101
558 PktCntrDisable = (1 << 7), // 8168 8101
559 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 560 RxVlan = (1 << 6),
561 RxChkSum = (1 << 5),
562 PCIDAC = (1 << 4),
563 PCIMulRW = (1 << 3),
9a3c81fa 564#define INTT_MASK GENMASK(1, 0)
0e485150
FR		 565 INTT_0 = 0x0000, // 8168
566 INTT_1 = 0x0001, // 8168
567 INTT_2 = 0x0002, // 8168
568 INTT_3 = 0x0003, // 8168
1da177e4
LT		 569
570 /* rtl8169_PHYstatus */
07d3f51f
FR		 571 TBI_Enable = 0x80,
572 TxFlowCtrl = 0x40,
573 RxFlowCtrl = 0x20,
574 _1000bpsF = 0x10,
575 _100bps = 0x08,
576 _10bps = 0x04,
577 LinkStatus = 0x02,
578 FullDup = 0x01,
1da177e4 579
1da177e4 580 /* _TBICSRBit */
07d3f51f 581 TBILinkOK = 0x02000000,
d4a3a0fc 582
6e85d5ad
CV		 583 /* ResetCounterCommand */
584 CounterReset = 0x1,
585
d4a3a0fc 586 /* DumpCounterCommand */
07d3f51f 587 CounterDump = 0x8,
6e1d0b89
CHL		 588
589 /* magic enable v2 */
590 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 591};
592
2b7b4318
FR		 593enum rtl_desc_bit {
594 /* First doubleword. */
1da177e4
LT		 595 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
596 RingEnd = (1 << 30), /* End of descriptor ring */
597 FirstFrag = (1 << 29), /* First segment of a packet */
598 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 599};
600
601/* Generic case. */
602enum rtl_tx_desc_bit {
603 /* First doubleword. */
604 TD_LSO = (1 << 27), /* Large Send Offload */
605#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 606
2b7b4318
FR		 607 /* Second doubleword. */
608 TxVlanTag = (1 << 17), /* Add VLAN tag */
609};
610
611/* 8169, 8168b and 810x except 8102e. */
612enum rtl_tx_desc_bit_0 {
613 /* First doubleword. */
614#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
615 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
616 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
617 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
618};
619
620/* 8102e, 8168c and beyond. */
621enum rtl_tx_desc_bit_1 {
bdfa4ed6 622 /* First doubleword. */
623 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 624 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 625#define GTTCPHO_SHIFT 18
e974604b 626#define GTTCPHO_MAX 0x7fU
bdfa4ed6 627
2b7b4318 628 /* Second doubleword. */
e974604b 629#define TCPHO_SHIFT 18
630#define TCPHO_MAX 0x3ffU
2b7b4318 631#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 632 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
633 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 634 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
635 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
636};
1da177e4 637
2b7b4318 638enum rtl_rx_desc_bit {
1da177e4
LT		 639 /* Rx private */
640 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 641 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 642
643#define RxProtoUDP (PID1)
644#define RxProtoTCP (PID0)
645#define RxProtoIP (PID1 | PID0)
646#define RxProtoMask RxProtoIP
647
648 IPFail = (1 << 16), /* IP checksum failed */
649 UDPFail = (1 << 15), /* UDP/IP checksum failed */
650 TCPFail = (1 << 14), /* TCP/IP checksum failed */
651 RxVlanTag = (1 << 16), /* VLAN tag available */
652};
653
654#define RsvdMask 0x3fffc000
12d42c50 655#define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
1da177e4
LT		 656
657struct TxDesc {
6cccd6e7
REB		 658 __le32 opts1;
659 __le32 opts2;
660 __le64 addr;
1da177e4
LT		 661};
662
663struct RxDesc {
6cccd6e7
REB		 664 __le32 opts1;
665 __le32 opts2;
666 __le64 addr;
1da177e4
LT		 667};
668
669struct ring_info {
670 struct sk_buff *skb;
671 u32 len;
672 u8 __pad[sizeof(void *) - sizeof(u32)];
673};
674
355423d0
IV		 675struct rtl8169_counters {
676 __le64 tx_packets;
677 __le64 rx_packets;
678 __le64 tx_errors;
679 __le32 rx_errors;
680 __le16 rx_missed;
681 __le16 align_errors;
682 __le32 tx_one_collision;
683 __le32 tx_multi_collision;
684 __le64 rx_unicast;
685 __le64 rx_broadcast;
686 __le32 rx_multicast;
687 __le16 tx_aborted;
688 __le16 tx_underun;
689};
690
6e85d5ad
CV		 691struct rtl8169_tc_offsets {
692 bool inited;
693 __le64 tx_errors;
694 __le32 tx_multi_collision;
6e85d5ad
CV		 695 __le16 tx_aborted;
696};
697
da78dbff 698enum rtl_flag {
6c4a70c5 699 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 700 RTL_FLAG_TASK_SLOW_PENDING,
701 RTL_FLAG_TASK_RESET_PENDING,
da78dbff
FR		 702 RTL_FLAG_MAX
703};
704
8027aa24
JW		 705struct rtl8169_stats {
706 u64 packets;
707 u64 bytes;
708 struct u64_stats_sync syncp;
709};
710
1da177e4
LT		 711struct rtl8169_private {
712 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 713 struct pci_dev *pci_dev;
c4028958 714 struct net_device *dev;
bea3348e 715 struct napi_struct napi;
b57b7e5a 716 u32 msg_enable;
2b7b4318 717 u16 mac_version;
1da177e4
LT		 718 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
719 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 720 u32 dirty_tx;
8027aa24
JW		 721 struct rtl8169_stats rx_stats;
722 struct rtl8169_stats tx_stats;
1da177e4
LT		 723 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
724 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
725 dma_addr_t TxPhyAddr;
726 dma_addr_t RxPhyAddr;
6f0333b8 727 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 728 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4 729 u16 cp_cmd;
da78dbff
FR		 730
731 u16 event_slow;
50970831 732 const struct rtl_coalesce_info *coalesce_info;
c0e45c1c 733
734 struct mdio_ops {
24192210
FR		 735 void (*write)(struct rtl8169_private *, int, int);
736 int (*read)(struct rtl8169_private *, int);
c0e45c1c 737 } mdio_ops;
738
d58d46b5
FR		 739 struct jumbo_ops {
740 void (*enable)(struct rtl8169_private *);
741 void (*disable)(struct rtl8169_private *);
742 } jumbo_ops;
743
61cb532d 744 void (*hw_start)(struct rtl8169_private *tp);
5888d3fc 745 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 746
747 struct {
da78dbff
FR		 748 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
749 struct mutex mutex;
4422bcd4
FR		 750 struct work_struct work;
751 } wk;
752
f7ffa9ae 753 unsigned supports_gmii:1;
f1e911d5 754 struct mii_bus *mii_bus;
42020320
CV		 755 dma_addr_t counters_phys_addr;
756 struct rtl8169_counters *counters;
6e85d5ad 757 struct rtl8169_tc_offsets tc_offset;
e1759441 758 u32 saved_wolopts;
f1e02ed1 759
b6ffd97f
FR		 760 struct rtl_fw {
761 const struct firmware *fw;
1c361efb
FR		 762
763#define RTL_VER_SIZE 32
764
765 char version[RTL_VER_SIZE];
766
767 struct rtl_fw_phy_action {
768 __le32 *code;
769 size_t size;
770 } phy_action;
b6ffd97f 771 } *rtl_fw;
497888cf 772#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 773
774 u32 ocp_base;
1da177e4
LT		 775};
776
979b6c13 777MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 778MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 779module_param(use_dac, int, 0);
4300e8c7 780MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 781module_param_named(debug, debug.msg_enable, int, 0);
782MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4 783MODULE_LICENSE("GPL");
bca03d5f 784MODULE_FIRMWARE(FIRMWARE_8168D_1);
785MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 786MODULE_FIRMWARE(FIRMWARE_8168E_1);
787MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 788MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 789MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 790MODULE_FIRMWARE(FIRMWARE_8168F_1);
791MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 792MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 793MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 794MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 795MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 796MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 797MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 798MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 799MODULE_FIRMWARE(FIRMWARE_8168H_1);
800MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 801MODULE_FIRMWARE(FIRMWARE_8107E_1);
802MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 803
1e1205b7
HK		 804static inline struct device *tp_to_dev(struct rtl8169_private *tp)
805{
806 return &tp->pci_dev->dev;
807}
808
da78dbff
FR		 809static void rtl_lock_work(struct rtl8169_private *tp)
810{
811 mutex_lock(&tp->wk.mutex);
812}
813
814static void rtl_unlock_work(struct rtl8169_private *tp)
815{
816 mutex_unlock(&tp->wk.mutex);
817}
818
cb73200c 819static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
d58d46b5 820{
cb73200c 821 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
7d7903b2 822 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 823}
824
ffc46952
FR		 825struct rtl_cond {
826 bool (*check)(struct rtl8169_private *);
827 const char *msg;
828};
829
830static void rtl_udelay(unsigned int d)
831{
832 udelay(d);
833}
834
835static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
836 void (*delay)(unsigned int), unsigned int d, int n,
837 bool high)
838{
839 int i;
840
841 for (i = 0; i < n; i++) {
842 delay(d);
843 if (c->check(tp) == high)
844 return true;
845 }
82e316ef
FR		 846 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
847 c->msg, !high, n, d);
ffc46952
FR		 848 return false;
849}
850
851static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
852 const struct rtl_cond *c,
853 unsigned int d, int n)
854{
855 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
856}
857
858static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
859 const struct rtl_cond *c,
860 unsigned int d, int n)
861{
862 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
863}
864
865static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
866 const struct rtl_cond *c,
867 unsigned int d, int n)
868{
869 return rtl_loop_wait(tp, c, msleep, d, n, true);
870}
871
872static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
873 const struct rtl_cond *c,
874 unsigned int d, int n)
875{
876 return rtl_loop_wait(tp, c, msleep, d, n, false);
877}
878
879#define DECLARE_RTL_COND(name) \
880static bool name ## _check(struct rtl8169_private *); \
881 \
882static const struct rtl_cond name = { \
883 .check = name ## _check, \
884 .msg = #name \
885}; \
886 \
887static bool name ## _check(struct rtl8169_private *tp)
888
c558386b
HW		 889static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
890{
891 if (reg & 0xffff0001) {
892 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
893 return true;
894 }
895 return false;
896}
897
898DECLARE_RTL_COND(rtl_ocp_gphy_cond)
899{
1ef7286e 900 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
c558386b
HW		 901}
902
903static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
904{
c558386b
HW		 905 if (rtl_ocp_reg_failure(tp, reg))
906 return;
907
1ef7286e 908 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 909
910 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
911}
912
913static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
914{
c558386b
HW		 915 if (rtl_ocp_reg_failure(tp, reg))
916 return 0;
917
1ef7286e 918 RTL_W32(tp, GPHY_OCP, reg << 15);
c558386b
HW		 919
920 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1ef7286e 921 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
c558386b
HW		 922}
923
c558386b
HW		 924static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
925{
c558386b
HW		 926 if (rtl_ocp_reg_failure(tp, reg))
927 return;
928
1ef7286e 929 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 930}
931
932static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
933{
c558386b
HW		 934 if (rtl_ocp_reg_failure(tp, reg))
935 return 0;
936
1ef7286e 937 RTL_W32(tp, OCPDR, reg << 15);
c558386b 938
1ef7286e 939 return RTL_R32(tp, OCPDR);
c558386b
HW		 940}
941
942#define OCP_STD_PHY_BASE 0xa400
943
944static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
945{
946 if (reg == 0x1f) {
947 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
948 return;
949 }
950
951 if (tp->ocp_base != OCP_STD_PHY_BASE)
952 reg -= 0x10;
953
954 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
955}
956
957static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
958{
959 if (tp->ocp_base != OCP_STD_PHY_BASE)
960 reg -= 0x10;
961
962 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
963}
964
eee3786f 965static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
966{
967 if (reg == 0x1f) {
968 tp->ocp_base = value << 4;
969 return;
970 }
971
972 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
973}
974
975static int mac_mcu_read(struct rtl8169_private *tp, int reg)
976{
977 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
978}
979
ffc46952
FR		 980DECLARE_RTL_COND(rtl_phyar_cond)
981{
1ef7286e 982 return RTL_R32(tp, PHYAR) & 0x80000000;
ffc46952
FR		 983}
984
24192210 985static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 986{
1ef7286e 987 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 988
ffc46952 989 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 990 /*
81a95f04
TT		 991 * According to hardware specs a 20us delay is required after write
992 * complete indication, but before sending next command.
024a07ba 993 */
81a95f04 994 udelay(20);
1da177e4
LT		 995}
996
24192210 997static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 998{
ffc46952 999 int value;
1da177e4 1000
1ef7286e 1001 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1002
ffc46952 1003 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1ef7286e 1004 RTL_R32(tp, PHYAR) & 0xffff : ~0;
ffc46952 1005
81a95f04
TT		 1006 /*
1007 * According to hardware specs a 20us delay is required after read
1008 * complete indication, but before sending next command.
1009 */
1010 udelay(20);
1011
1da177e4
LT		 1012 return value;
1013}
1014
935e2218
CHL		 1015DECLARE_RTL_COND(rtl_ocpar_cond)
1016{
1ef7286e 1017 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
935e2218
CHL		 1018}
1019
24192210 1020static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1021{
1ef7286e
AS		 1022 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1023 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
1024 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 1025
ffc46952 1026 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1027}
1028
24192210 1029static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1030{
24192210
FR		 1031 r8168dp_1_mdio_access(tp, reg,
1032 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1033}
1034
24192210 1035static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1036{
24192210 1037 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1038
1039 mdelay(1);
1ef7286e
AS		 1040 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1041 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 1042
ffc46952 1043 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1ef7286e 1044 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1045}
1046
e6de30d6 1047#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1048
1ef7286e 1049static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
e6de30d6 1050{
1ef7286e 1051 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1052}
1053
1ef7286e 1054static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
e6de30d6 1055{
1ef7286e 1056 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1057}
1058
24192210 1059static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1060{
1ef7286e 1061 r8168dp_2_mdio_start(tp);
e6de30d6 1062
24192210 1063 r8169_mdio_write(tp, reg, value);
e6de30d6 1064
1ef7286e 1065 r8168dp_2_mdio_stop(tp);
e6de30d6 1066}
1067
24192210 1068static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1069{
1070 int value;
1071
1ef7286e 1072 r8168dp_2_mdio_start(tp);
e6de30d6 1073
24192210 1074 value = r8169_mdio_read(tp, reg);
e6de30d6 1075
1ef7286e 1076 r8168dp_2_mdio_stop(tp);
e6de30d6 1077
1078 return value;
1079}
1080
4da19633 1081static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1082{
24192210 1083 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1084}
1085
4da19633 1086static int rtl_readphy(struct rtl8169_private *tp, int location)
1087{
24192210 1088 return tp->mdio_ops.read(tp, location);
4da19633 1089}
1090
1091static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1092{
1093 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1094}
1095
76564428 1096static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1097{
1098 int val;
1099
4da19633 1100 val = rtl_readphy(tp, reg_addr);
76564428 1101 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1102}
1103
ffc46952
FR		 1104DECLARE_RTL_COND(rtl_ephyar_cond)
1105{
1ef7286e 1106 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
ffc46952
FR		 1107}
1108
fdf6fc06 1109static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1110{
1ef7286e 1111 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
dacf8154
FR		 1112 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1113
ffc46952
FR		 1114 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1115
1116 udelay(10);
dacf8154
FR		 1117}
1118
fdf6fc06 1119static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1120{
1ef7286e 1121 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
dacf8154 1122
ffc46952 1123 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1ef7286e 1124 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1125}
1126
935e2218
CHL		 1127DECLARE_RTL_COND(rtl_eriar_cond)
1128{
1ef7286e 1129 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
935e2218
CHL		 1130}
1131
fdf6fc06
FR		 1132static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1133 u32 val, int type)
133ac40a 1134{
133ac40a 1135 BUG_ON((addr & 3) || (mask == 0));
1ef7286e
AS		 1136 RTL_W32(tp, ERIDR, val);
1137 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
133ac40a 1138
ffc46952 1139 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1140}
1141
fdf6fc06 1142static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1143{
1ef7286e 1144 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
133ac40a 1145
ffc46952 1146 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1ef7286e 1147 RTL_R32(tp, ERIDR) : ~0;
133ac40a
HW		 1148}
1149
706123d0 1150static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1151 u32 m, int type)
133ac40a
HW		 1152{
1153 u32 val;
1154
fdf6fc06
FR		 1155 val = rtl_eri_read(tp, addr, type);
1156 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1157}
1158
935e2218
CHL		 1159static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1160{
1ef7286e 1161 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218 1162 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1ef7286e 1163 RTL_R32(tp, OCPDR) : ~0;
935e2218
CHL		 1164}
1165
1166static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1167{
1168 return rtl_eri_read(tp, reg, ERIAR_OOB);
1169}
1170
1171static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1172{
1173 switch (tp->mac_version) {
1174 case RTL_GIGA_MAC_VER_27:
1175 case RTL_GIGA_MAC_VER_28:
1176 case RTL_GIGA_MAC_VER_31:
1177 return r8168dp_ocp_read(tp, mask, reg);
1178 case RTL_GIGA_MAC_VER_49:
1179 case RTL_GIGA_MAC_VER_50:
1180 case RTL_GIGA_MAC_VER_51:
1181 return r8168ep_ocp_read(tp, mask, reg);
1182 default:
1183 BUG();
1184 return ~0;
1185 }
1186}
1187
1188static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1189 u32 data)
1190{
1ef7286e
AS		 1191 RTL_W32(tp, OCPDR, data);
1192 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218
CHL		 1193 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1194}
1195
1196static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1197 u32 data)
1198{
1199 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1200 data, ERIAR_OOB);
1201}
1202
1203static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1204{
1205 switch (tp->mac_version) {
1206 case RTL_GIGA_MAC_VER_27:
1207 case RTL_GIGA_MAC_VER_28:
1208 case RTL_GIGA_MAC_VER_31:
1209 r8168dp_ocp_write(tp, mask, reg, data);
1210 break;
1211 case RTL_GIGA_MAC_VER_49:
1212 case RTL_GIGA_MAC_VER_50:
1213 case RTL_GIGA_MAC_VER_51:
1214 r8168ep_ocp_write(tp, mask, reg, data);
1215 break;
1216 default:
1217 BUG();
1218 break;
1219 }
1220}
1221
2a9b4d96
CHL		 1222static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1223{
1224 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1225
1226 ocp_write(tp, 0x1, 0x30, 0x00000001);
1227}
1228
1229#define OOB_CMD_RESET 0x00
1230#define OOB_CMD_DRIVER_START 0x05
1231#define OOB_CMD_DRIVER_STOP 0x06
1232
1233static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1234{
1235 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1236}
1237
1238DECLARE_RTL_COND(rtl_ocp_read_cond)
1239{
1240 u16 reg;
1241
1242 reg = rtl8168_get_ocp_reg(tp);
1243
1244 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1245}
1246
935e2218 1247DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1248{
935e2218
CHL		 1249 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1250}
1251
1252DECLARE_RTL_COND(rtl_ocp_tx_cond)
1253{
1ef7286e 1254 return RTL_R8(tp, IBISR0) & 0x20;
935e2218 1255}
2a9b4d96 1256
003609da
CHL		 1257static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1258{
1ef7286e 1259 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
086ca23d 1260 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1ef7286e
AS		 1261 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1262 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
003609da
CHL		 1263}
1264
935e2218
CHL		 1265static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1266{
1267 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
2a9b4d96
CHL		 1268 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1269}
1270
935e2218 1271static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1272{
935e2218
CHL		 1273 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1274 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1275 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1276}
1277
1278static void rtl8168_driver_start(struct rtl8169_private *tp)
1279{
1280 switch (tp->mac_version) {
1281 case RTL_GIGA_MAC_VER_27:
1282 case RTL_GIGA_MAC_VER_28:
1283 case RTL_GIGA_MAC_VER_31:
1284 rtl8168dp_driver_start(tp);
1285 break;
1286 case RTL_GIGA_MAC_VER_49:
1287 case RTL_GIGA_MAC_VER_50:
1288 case RTL_GIGA_MAC_VER_51:
1289 rtl8168ep_driver_start(tp);
1290 break;
1291 default:
1292 BUG();
1293 break;
1294 }
1295}
2a9b4d96 1296
935e2218
CHL		 1297static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1298{
1299 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
2a9b4d96
CHL		 1300 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1301}
1302
935e2218
CHL		 1303static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1304{
003609da 1305 rtl8168ep_stop_cmac(tp);
935e2218
CHL		 1306 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1307 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1308 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1309}
1310
1311static void rtl8168_driver_stop(struct rtl8169_private *tp)
1312{
1313 switch (tp->mac_version) {
1314 case RTL_GIGA_MAC_VER_27:
1315 case RTL_GIGA_MAC_VER_28:
1316 case RTL_GIGA_MAC_VER_31:
1317 rtl8168dp_driver_stop(tp);
1318 break;
1319 case RTL_GIGA_MAC_VER_49:
1320 case RTL_GIGA_MAC_VER_50:
1321 case RTL_GIGA_MAC_VER_51:
1322 rtl8168ep_driver_stop(tp);
1323 break;
1324 default:
1325 BUG();
1326 break;
1327 }
1328}
1329
9dbe7896 1330static bool r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1331{
1332 u16 reg = rtl8168_get_ocp_reg(tp);
1333
9dbe7896 1334 return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
2a9b4d96
CHL		 1335}
1336
9dbe7896 1337static bool r8168ep_check_dash(struct rtl8169_private *tp)
935e2218 1338{
9dbe7896 1339 return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
935e2218
CHL		 1340}
1341
9dbe7896 1342static bool r8168_check_dash(struct rtl8169_private *tp)
935e2218
CHL		 1343{
1344 switch (tp->mac_version) {
1345 case RTL_GIGA_MAC_VER_27:
1346 case RTL_GIGA_MAC_VER_28:
1347 case RTL_GIGA_MAC_VER_31:
1348 return r8168dp_check_dash(tp);
1349 case RTL_GIGA_MAC_VER_49:
1350 case RTL_GIGA_MAC_VER_50:
1351 case RTL_GIGA_MAC_VER_51:
1352 return r8168ep_check_dash(tp);
1353 default:
9dbe7896 1354 return false;
935e2218
CHL		 1355 }
1356}
1357
c28aa385 1358struct exgmac_reg {
1359 u16 addr;
1360 u16 mask;
1361 u32 val;
1362};
1363
fdf6fc06 1364static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1365 const struct exgmac_reg *r, int len)
1366{
1367 while (len-- > 0) {
fdf6fc06 1368 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1369 r++;
1370 }
1371}
1372
ffc46952
FR		 1373DECLARE_RTL_COND(rtl_efusear_cond)
1374{
1ef7286e 1375 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
ffc46952
FR		 1376}
1377
fdf6fc06 1378static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1379{
1ef7286e 1380 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
daf9df6d 1381
ffc46952 1382 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1ef7286e 1383 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1384}
1385
9085cdfa
FR		 1386static u16 rtl_get_events(struct rtl8169_private *tp)
1387{
1ef7286e 1388 return RTL_R16(tp, IntrStatus);
9085cdfa
FR		 1389}
1390
1391static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1392{
1ef7286e 1393 RTL_W16(tp, IntrStatus, bits);
9085cdfa
FR		 1394 mmiowb();
1395}
1396
1397static void rtl_irq_disable(struct rtl8169_private *tp)
1398{
1ef7286e 1399 RTL_W16(tp, IntrMask, 0);
9085cdfa
FR		 1400 mmiowb();
1401}
1402
3e990ff5
FR		 1403static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1404{
1ef7286e 1405 RTL_W16(tp, IntrMask, bits);
3e990ff5
FR		 1406}
1407
da78dbff
FR		 1408#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1409#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1410#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1411
1412static void rtl_irq_enable_all(struct rtl8169_private *tp)
1413{
1414 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1415}
1416
811fd301 1417static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1418{
9085cdfa 1419 rtl_irq_disable(tp);
da78dbff 1420 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1ef7286e 1421 RTL_R8(tp, ChipCmd);
1da177e4
LT		 1422}
1423
70090424
HW		 1424static void rtl_link_chg_patch(struct rtl8169_private *tp)
1425{
70090424 1426 struct net_device *dev = tp->dev;
29a12b49 1427 struct phy_device *phydev = dev->phydev;
70090424
HW		 1428
1429 if (!netif_running(dev))
1430 return;
1431
b3d7b2f2
HW		 1432 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1433 tp->mac_version == RTL_GIGA_MAC_VER_38) {
29a12b49 1434 if (phydev->speed == SPEED_1000) {
fdf6fc06
FR		 1435 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1436 ERIAR_EXGMAC);
1437 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1438 ERIAR_EXGMAC);
29a12b49 1439 } else if (phydev->speed == SPEED_100) {
fdf6fc06
FR		 1440 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1441 ERIAR_EXGMAC);
1442 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1443 ERIAR_EXGMAC);
70090424 1444 } else {
fdf6fc06
FR		 1445 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1446 ERIAR_EXGMAC);
1447 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1448 ERIAR_EXGMAC);
70090424
HW		 1449 }
1450 /* Reset packet filter */
706123d0 1451 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1452 ERIAR_EXGMAC);
706123d0 1453 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1454 ERIAR_EXGMAC);
c2218925
HW		 1455 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1456 tp->mac_version == RTL_GIGA_MAC_VER_36) {
29a12b49 1457 if (phydev->speed == SPEED_1000) {
fdf6fc06
FR		 1458 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1459 ERIAR_EXGMAC);
1460 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1461 ERIAR_EXGMAC);
c2218925 1462 } else {
fdf6fc06
FR		 1463 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1464 ERIAR_EXGMAC);
1465 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1466 ERIAR_EXGMAC);
c2218925 1467 }
7e18dca1 1468 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
29a12b49 1469 if (phydev->speed == SPEED_10) {
fdf6fc06
FR		 1470 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1471 ERIAR_EXGMAC);
1472 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1473 ERIAR_EXGMAC);
7e18dca1 1474 } else {
fdf6fc06
FR		 1475 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1476 ERIAR_EXGMAC);
7e18dca1 1477 }
70090424
HW		 1478 }
1479}
1480
e1759441
RW		 1481#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1482
1483static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1484{
61a4dcc2 1485 u8 options;
e1759441 1486 u32 wolopts = 0;
61a4dcc2 1487
1ef7286e 1488 options = RTL_R8(tp, Config1);
61a4dcc2 1489 if (!(options & PMEnable))
e1759441 1490 return 0;
61a4dcc2 1491
1ef7286e 1492 options = RTL_R8(tp, Config3);
61a4dcc2 1493 if (options & LinkUp)
e1759441 1494 wolopts |= WAKE_PHY;
6e1d0b89 1495 switch (tp->mac_version) {
2a71883c
HK		 1496 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1497 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1498 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1499 wolopts |= WAKE_MAGIC;
1500 break;
1501 default:
1502 if (options & MagicPacket)
1503 wolopts |= WAKE_MAGIC;
1504 break;
1505 }
61a4dcc2 1506
1ef7286e 1507 options = RTL_R8(tp, Config5);
61a4dcc2 1508 if (options & UWF)
e1759441 1509 wolopts |= WAKE_UCAST;
61a4dcc2 1510 if (options & BWF)
e1759441 1511 wolopts |= WAKE_BCAST;
61a4dcc2 1512 if (options & MWF)
e1759441 1513 wolopts |= WAKE_MCAST;
61a4dcc2 1514
e1759441 1515 return wolopts;
61a4dcc2
FR		 1516}
1517
e1759441 1518static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1519{
1520 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1521
da78dbff 1522 rtl_lock_work(tp);
e1759441 1523 wol->supported = WAKE_ANY;
433f9d0d 1524 wol->wolopts = tp->saved_wolopts;
da78dbff 1525 rtl_unlock_work(tp);
e1759441
RW		 1526}
1527
1528static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1529{
6e1d0b89 1530 unsigned int i, tmp;
350f7596 1531 static const struct {
61a4dcc2
FR		 1532 u32 opt;
1533 u16 reg;
1534 u8 mask;
1535 } cfg[] = {
61a4dcc2 1536 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1537 { WAKE_UCAST, Config5, UWF },
1538 { WAKE_BCAST, Config5, BWF },
1539 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1540 { WAKE_ANY, Config5, LanWake },
1541 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1542 };
851e6022 1543 u8 options;
61a4dcc2 1544
1ef7286e 1545 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
61a4dcc2 1546
6e1d0b89 1547 switch (tp->mac_version) {
2a71883c
HK		 1548 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1549 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1550 tmp = ARRAY_SIZE(cfg) - 1;
1551 if (wolopts & WAKE_MAGIC)
706123d0 1552 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1553 0x0dc,
1554 ERIAR_MASK_0100,
1555 MagicPacket_v2,
1556 0x0000,
1557 ERIAR_EXGMAC);
1558 else
706123d0 1559 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1560 0x0dc,
1561 ERIAR_MASK_0100,
1562 0x0000,
1563 MagicPacket_v2,
1564 ERIAR_EXGMAC);
1565 break;
1566 default:
1567 tmp = ARRAY_SIZE(cfg);
1568 break;
1569 }
1570
1571 for (i = 0; i < tmp; i++) {
1ef7286e 1572 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
e1759441 1573 if (wolopts & cfg[i].opt)
61a4dcc2 1574 options |= cfg[i].mask;
1ef7286e 1575 RTL_W8(tp, cfg[i].reg, options);
61a4dcc2
FR		 1576 }
1577
851e6022
FR		 1578 switch (tp->mac_version) {
1579 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1ef7286e 1580 options = RTL_R8(tp, Config1) & ~PMEnable;
851e6022
FR		 1581 if (wolopts)
1582 options |= PMEnable;
1ef7286e 1583 RTL_W8(tp, Config1, options);
851e6022
FR		 1584 break;
1585 default:
1ef7286e 1586 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
d387b427
FR		 1587 if (wolopts)
1588 options |= PME_SIGNAL;
1ef7286e 1589 RTL_W8(tp, Config2, options);
851e6022
FR		 1590 break;
1591 }
1592
1ef7286e 1593 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
e1759441
RW		 1594}
1595
1596static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1597{
1598 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1599 struct device *d = tp_to_dev(tp);
5fa80a32 1600
2f533f6b
HK		 1601 if (wol->wolopts & ~WAKE_ANY)
1602 return -EINVAL;
1603
5fa80a32 1604 pm_runtime_get_noresume(d);
e1759441 1605
da78dbff 1606 rtl_lock_work(tp);
61a4dcc2 1607
2f533f6b 1608 tp->saved_wolopts = wol->wolopts;
433f9d0d 1609
5fa80a32 1610 if (pm_runtime_active(d))
433f9d0d 1611 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff
FR		 1612
1613 rtl_unlock_work(tp);
61a4dcc2 1614
433f9d0d 1615 device_set_wakeup_enable(d, tp->saved_wolopts);
ea80907f 1616
5fa80a32
CHL		 1617 pm_runtime_put_noidle(d);
1618
61a4dcc2
FR		 1619 return 0;
1620}
1621
31bd204f
FR		 1622static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1623{
85bffe6c 1624 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1625}
1626
1da177e4
LT		 1627static void rtl8169_get_drvinfo(struct net_device *dev,
1628 struct ethtool_drvinfo *info)
1629{
1630 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1631 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1632
68aad78c 1633 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
68aad78c 1634 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1635 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1636 if (!IS_ERR_OR_NULL(rtl_fw))
1637 strlcpy(info->fw_version, rtl_fw->version,
1638 sizeof(info->fw_version));
1da177e4
LT		 1639}
1640
1641static int rtl8169_get_regs_len(struct net_device *dev)
1642{
1643 return R8169_REGS_SIZE;
1644}
1645
c8f44aff
MM		 1646static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1647 netdev_features_t features)
1da177e4 1648{
d58d46b5
FR		 1649 struct rtl8169_private *tp = netdev_priv(dev);
1650
2b7b4318 1651 if (dev->mtu > TD_MSS_MAX)
350fb32a 1652 features &= ~NETIF_F_ALL_TSO;
1da177e4 1653
d58d46b5 1654 if (dev->mtu > JUMBO_1K &&
6ed0e08f 1655 tp->mac_version > RTL_GIGA_MAC_VER_06)
d58d46b5
FR		 1656 features &= ~NETIF_F_IP_CSUM;
1657
350fb32a 1658 return features;
1da177e4
LT		 1659}
1660
a3984578
HK		 1661static int rtl8169_set_features(struct net_device *dev,
1662 netdev_features_t features)
1da177e4
LT		 1663{
1664 struct rtl8169_private *tp = netdev_priv(dev);
929a031d 1665 u32 rx_config;
1da177e4 1666
a3984578
HK		 1667 rtl_lock_work(tp);
1668
1ef7286e 1669 rx_config = RTL_R32(tp, RxConfig);
929a031d 1670 if (features & NETIF_F_RXALL)
1671 rx_config |= (AcceptErr | AcceptRunt);
1672 else
1673 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 1674
1ef7286e 1675 RTL_W32(tp, RxConfig, rx_config);
350fb32a 1676
929a031d 1677 if (features & NETIF_F_RXCSUM)
1678 tp->cp_cmd |= RxChkSum;
1679 else
1680 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1681
929a031d 1682 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1683 tp->cp_cmd |= RxVlan;
1684 else
1685 tp->cp_cmd &= ~RxVlan;
1686
1ef7286e
AS		 1687 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1688 RTL_R16(tp, CPlusCmd);
1da177e4 1689
da78dbff 1690 rtl_unlock_work(tp);
1da177e4
LT		 1691
1692 return 0;
1693}
1694
810f4893 1695static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1696{
df8a39de
JP		 1697 return (skb_vlan_tag_present(skb)) ?
1698 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 1699}
1700
7a8fc77b 1701static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1702{
1703 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1704
7a8fc77b 1705 if (opts2 & RxVlanTag)
86a9bad3 1706 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1707}
1708
1da177e4
LT		 1709static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1710 void *p)
1711{
5b0384f4 1712 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 1713 u32 __iomem *data = tp->mmio_addr;
1714 u32 *dw = p;
1715 int i;
1da177e4 1716
da78dbff 1717 rtl_lock_work(tp);
15edae91
PW		 1718 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1719 memcpy_fromio(dw++, data++, 4);
da78dbff 1720 rtl_unlock_work(tp);
1da177e4
LT		 1721}
1722
b57b7e5a
SH		 1723static u32 rtl8169_get_msglevel(struct net_device *dev)
1724{
1725 struct rtl8169_private *tp = netdev_priv(dev);
1726
1727 return tp->msg_enable;
1728}
1729
1730static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1731{
1732 struct rtl8169_private *tp = netdev_priv(dev);
1733
1734 tp->msg_enable = value;
1735}
1736
d4a3a0fc
SH		 1737static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1738 "tx_packets",
1739 "rx_packets",
1740 "tx_errors",
1741 "rx_errors",
1742 "rx_missed",
1743 "align_errors",
1744 "tx_single_collisions",
1745 "tx_multi_collisions",
1746 "unicast",
1747 "broadcast",
1748 "multicast",
1749 "tx_aborted",
1750 "tx_underrun",
1751};
1752
b9f2c044 1753static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1754{
b9f2c044
JG		 1755 switch (sset) {
1756 case ETH_SS_STATS:
1757 return ARRAY_SIZE(rtl8169_gstrings);
1758 default:
1759 return -EOPNOTSUPP;
1760 }
d4a3a0fc
SH		 1761}
1762
42020320 1763DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 1764{
1ef7286e 1765 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 1766}
1767
e71c9ce2 1768static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
6e85d5ad 1769{
42020320
CV		 1770 dma_addr_t paddr = tp->counters_phys_addr;
1771 u32 cmd;
6e85d5ad 1772
1ef7286e
AS		 1773 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1774 RTL_R32(tp, CounterAddrHigh);
42020320 1775 cmd = (u64)paddr & DMA_BIT_MASK(32);
1ef7286e
AS		 1776 RTL_W32(tp, CounterAddrLow, cmd);
1777 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
6e85d5ad 1778
a78e9366 1779 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 1780}
1781
e71c9ce2 1782static bool rtl8169_reset_counters(struct rtl8169_private *tp)
6e85d5ad 1783{
6e85d5ad
CV		 1784 /*
1785 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1786 * tally counters.
1787 */
1788 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1789 return true;
1790
e71c9ce2 1791 return rtl8169_do_counters(tp, CounterReset);
ffc46952
FR		 1792}
1793
e71c9ce2 1794static bool rtl8169_update_counters(struct rtl8169_private *tp)
d4a3a0fc 1795{
355423d0
IV		 1796 /*
1797 * Some chips are unable to dump tally counters when the receiver
1798 * is disabled.
1799 */
1ef7286e 1800 if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
6e85d5ad 1801 return true;
d4a3a0fc 1802
e71c9ce2 1803 return rtl8169_do_counters(tp, CounterDump);
6e85d5ad
CV		 1804}
1805
e71c9ce2 1806static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
6e85d5ad 1807{
42020320 1808 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 1809 bool ret = false;
1810
1811 /*
1812 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1813 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1814 * reset by a power cycle, while the counter values collected by the
1815 * driver are reset at every driver unload/load cycle.
1816 *
1817 * To make sure the HW values returned by @get_stats64 match the SW
1818 * values, we collect the initial values at first open(*) and use them
1819 * as offsets to normalize the values returned by @get_stats64.
1820 *
1821 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1822 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1823 * set at open time by rtl_hw_start.
1824 */
1825
1826 if (tp->tc_offset.inited)
1827 return true;
1828
1829 /* If both, reset and update fail, propagate to caller. */
e71c9ce2 1830 if (rtl8169_reset_counters(tp))
6e85d5ad
CV		 1831 ret = true;
1832
e71c9ce2 1833 if (rtl8169_update_counters(tp))
6e85d5ad
CV		 1834 ret = true;
1835
42020320
CV		 1836 tp->tc_offset.tx_errors = counters->tx_errors;
1837 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1838 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 1839 tp->tc_offset.inited = true;
1840
1841 return ret;
d4a3a0fc
SH		 1842}
1843
355423d0
IV		 1844static void rtl8169_get_ethtool_stats(struct net_device *dev,
1845 struct ethtool_stats *stats, u64 *data)
1846{
1847 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1848 struct device *d = tp_to_dev(tp);
42020320 1849 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 1850
1851 ASSERT_RTNL();
1852
e0636236
CHL		 1853 pm_runtime_get_noresume(d);
1854
1855 if (pm_runtime_active(d))
e71c9ce2 1856 rtl8169_update_counters(tp);
e0636236
CHL		 1857
1858 pm_runtime_put_noidle(d);
355423d0 1859
42020320
CV		 1860 data[0] = le64_to_cpu(counters->tx_packets);
1861 data[1] = le64_to_cpu(counters->rx_packets);
1862 data[2] = le64_to_cpu(counters->tx_errors);
1863 data[3] = le32_to_cpu(counters->rx_errors);
1864 data[4] = le16_to_cpu(counters->rx_missed);
1865 data[5] = le16_to_cpu(counters->align_errors);
1866 data[6] = le32_to_cpu(counters->tx_one_collision);
1867 data[7] = le32_to_cpu(counters->tx_multi_collision);
1868 data[8] = le64_to_cpu(counters->rx_unicast);
1869 data[9] = le64_to_cpu(counters->rx_broadcast);
1870 data[10] = le32_to_cpu(counters->rx_multicast);
1871 data[11] = le16_to_cpu(counters->tx_aborted);
1872 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 1873}
1874
d4a3a0fc
SH		 1875static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1876{
1877 switch(stringset) {
1878 case ETH_SS_STATS:
1879 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1880 break;
1881 }
1882}
1883
50970831
FR		 1884/*
1885 * Interrupt coalescing
1886 *
1887 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1888 * > 8169, 8168 and 810x line of chipsets
1889 *
1890 * 8169, 8168, and 8136(810x) serial chipsets support it.
1891 *
1892 * > 2 - the Tx timer unit at gigabit speed
1893 *
1894 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1895 * (0xe0) bit 1 and bit 0.
1896 *
1897 * For 8169
1898 * bit[1:0] \ speed 1000M 100M 10M
1899 * 0 0 320ns 2.56us 40.96us
1900 * 0 1 2.56us 20.48us 327.7us
1901 * 1 0 5.12us 40.96us 655.4us
1902 * 1 1 10.24us 81.92us 1.31ms
1903 *
1904 * For the other
1905 * bit[1:0] \ speed 1000M 100M 10M
1906 * 0 0 5us 2.56us 40.96us
1907 * 0 1 40us 20.48us 327.7us
1908 * 1 0 80us 40.96us 655.4us
1909 * 1 1 160us 81.92us 1.31ms
1910 */
1911
1912/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1913struct rtl_coalesce_scale {
1914 /* Rx / Tx */
1915 u32 nsecs[2];
1916};
1917
1918/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1919struct rtl_coalesce_info {
1920 u32 speed;
1921 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1922};
1923
1924/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1925#define rxtx_x1822(r, t) { \
1926 {{(r), (t)}}, \
1927 {{(r)*8, (t)*8}}, \
1928 {{(r)*8*2, (t)*8*2}}, \
1929 {{(r)*8*2*2, (t)*8*2*2}}, \
1930}
1931static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1932 /* speed delays: rx00 tx00 */
1933 { SPEED_10, rxtx_x1822(40960, 40960) },
1934 { SPEED_100, rxtx_x1822( 2560, 2560) },
1935 { SPEED_1000, rxtx_x1822( 320, 320) },
1936 { 0 },
1937};
1938
1939static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1940 /* speed delays: rx00 tx00 */
1941 { SPEED_10, rxtx_x1822(40960, 40960) },
1942 { SPEED_100, rxtx_x1822( 2560, 2560) },
1943 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1944 { 0 },
1945};
1946#undef rxtx_x1822
1947
1948/* get rx/tx scale vector corresponding to current speed */
1949static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1950{
1951 struct rtl8169_private *tp = netdev_priv(dev);
1952 struct ethtool_link_ksettings ecmd;
1953 const struct rtl_coalesce_info *ci;
1954 int rc;
1955
45772433 1956 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
50970831
FR		 1957 if (rc < 0)
1958 return ERR_PTR(rc);
1959
1960 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1961 if (ecmd.base.speed == ci->speed) {
1962 return ci;
1963 }
1964 }
1965
1966 return ERR_PTR(-ELNRNG);
1967}
1968
1969static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1970{
1971 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1972 const struct rtl_coalesce_info *ci;
1973 const struct rtl_coalesce_scale *scale;
1974 struct {
1975 u32 *max_frames;
1976 u32 *usecs;
1977 } coal_settings [] = {
1978 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1979 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1980 }, *p = coal_settings;
1981 int i;
1982 u16 w;
1983
1984 memset(ec, 0, sizeof(*ec));
1985
1986 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1987 ci = rtl_coalesce_info(dev);
1988 if (IS_ERR(ci))
1989 return PTR_ERR(ci);
1990
0ae0974e 1991 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
50970831
FR		 1992
1993 /* read IntrMitigate and adjust according to scale */
1ef7286e 1994 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
50970831
FR		 1995 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1996 w >>= RTL_COALESCE_SHIFT;
1997 *p->usecs = w & RTL_COALESCE_MASK;
1998 }
1999
2000 for (i = 0; i < 2; i++) {
2001 p = coal_settings + i;
2002 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2003
2004 /*
2005 * ethtool_coalesce says it is illegal to set both usecs and
2006 * max_frames to 0.
2007 */
2008 if (!*p->usecs && !*p->max_frames)
2009 *p->max_frames = 1;
2010 }
2011
2012 return 0;
2013}
2014
2015/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2016static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2017 struct net_device *dev, u32 nsec, u16 *cp01)
2018{
2019 const struct rtl_coalesce_info *ci;
2020 u16 i;
2021
2022 ci = rtl_coalesce_info(dev);
2023 if (IS_ERR(ci))
2024 return ERR_CAST(ci);
2025
2026 for (i = 0; i < 4; i++) {
2027 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2028 ci->scalev[i].nsecs[1]);
2029 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2030 *cp01 = i;
2031 return &ci->scalev[i];
2032 }
2033 }
2034
2035 return ERR_PTR(-EINVAL);
2036}
2037
2038static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2039{
2040 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 2041 const struct rtl_coalesce_scale *scale;
2042 struct {
2043 u32 frames;
2044 u32 usecs;
2045 } coal_settings [] = {
2046 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2047 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2048 }, *p = coal_settings;
2049 u16 w = 0, cp01;
2050 int i;
2051
2052 scale = rtl_coalesce_choose_scale(dev,
2053 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2054 if (IS_ERR(scale))
2055 return PTR_ERR(scale);
2056
2057 for (i = 0; i < 2; i++, p++) {
2058 u32 units;
2059
2060 /*
2061 * accept max_frames=1 we returned in rtl_get_coalesce.
2062 * accept it not only when usecs=0 because of e.g. the following scenario:
2063 *
2064 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2065 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2066 * - then user does `ethtool -C eth0 rx-usecs 100`
2067 *
2068 * since ethtool sends to kernel whole ethtool_coalesce
2069 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2070 * we'll reject it below in `frames % 4 != 0`.
2071 */
2072 if (p->frames == 1) {
2073 p->frames = 0;
2074 }
2075
2076 units = p->usecs * 1000 / scale->nsecs[i];
2077 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2078 return -EINVAL;
2079
2080 w <<= RTL_COALESCE_SHIFT;
2081 w |= units;
2082 w <<= RTL_COALESCE_SHIFT;
2083 w |= p->frames >> 2;
2084 }
2085
2086 rtl_lock_work(tp);
2087
1ef7286e 2088 RTL_W16(tp, IntrMitigate, swab16(w));
50970831 2089
9a3c81fa 2090 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1ef7286e
AS		 2091 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2092 RTL_R16(tp, CPlusCmd);
50970831
FR		 2093
2094 rtl_unlock_work(tp);
2095
2096 return 0;
2097}
2098
7282d491 2099static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2100 .get_drvinfo = rtl8169_get_drvinfo,
2101 .get_regs_len = rtl8169_get_regs_len,
2102 .get_link = ethtool_op_get_link,
50970831
FR		 2103 .get_coalesce = rtl_get_coalesce,
2104 .set_coalesce = rtl_set_coalesce,
b57b7e5a
SH		 2105 .get_msglevel = rtl8169_get_msglevel,
2106 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2107 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2108 .get_wol = rtl8169_get_wol,
2109 .set_wol = rtl8169_set_wol,
d4a3a0fc 2110 .get_strings = rtl8169_get_strings,
b9f2c044 2111 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2112 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2113 .get_ts_info = ethtool_op_get_ts_info,
dd84957e 2114 .nway_reset = phy_ethtool_nway_reset,
45772433
HK		 2115 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2116 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1da177e4
LT		 2117};
2118
07d3f51f 2119static void rtl8169_get_mac_version(struct rtl8169_private *tp,
22148df0 2120 u8 default_version)
1da177e4 2121{
0e485150
FR		 2122 /*
2123 * The driver currently handles the 8168Bf and the 8168Be identically
2124 * but they can be identified more specifically through the test below
2125 * if needed:
2126 *
1ef7286e 2127 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2128 *
2129 * Same thing for the 8101Eb and the 8101Ec:
2130 *
1ef7286e 2131 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2132 */
3744100e 2133 static const struct rtl_mac_info {
1da177e4 2134 u32 mask;
e3cf0cc0 2135 u32 val;
1da177e4
LT		 2136 int mac_version;
2137 } mac_info[] = {
935e2218
CHL		 2138 /* 8168EP family. */
2139 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2140 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2141 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2142
6e1d0b89
CHL		 2143 /* 8168H family. */
2144 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2145 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2146
c558386b 2147 /* 8168G family. */
45dd95c4 2148 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2149 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2150 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2151 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2152
c2218925 2153 /* 8168F family. */
b3d7b2f2 2154 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2155 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2156 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2157
01dc7fec 2158 /* 8168E family. */
70090424 2159 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2160 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2161 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2162
5b538df9 2163 /* 8168D family. */
daf9df6d 2164 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2165 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2166
e6de30d6 2167 /* 8168DP family. */
2168 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2169 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2170 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2171
ef808d50 2172 /* 8168C family. */
ef3386f0 2173 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2174 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2175 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2176 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2177 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2178 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
ef808d50 2179 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2180
2181 /* 8168B family. */
2182 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
e3cf0cc0
FR		 2183 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2184 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2185
2186 /* 8101 family. */
5598bfe5 2187 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2188 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
5a5e4443
HW		 2189 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2190 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2191 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2192 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2193 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2194 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2195 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2196 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2197 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2198 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2199 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2200 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2201 /* FIXME: where did these entries come from ? -- FR */
2202 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2203 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2204
2205 /* 8110 family. */
2206 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2207 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2208 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2209 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2210 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2211 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2212
f21b75e9
JD		 2213 /* Catch-all */
2214 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2215 };
2216 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2217 u32 reg;
2218
1ef7286e 2219 reg = RTL_R32(tp, TxConfig);
e3cf0cc0 2220 while ((reg & p->mask) != p->val)
1da177e4
LT		 2221 p++;
2222 tp->mac_version = p->mac_version;
5d320a20
FR		 2223
2224 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
22148df0
HK		 2225 dev_notice(tp_to_dev(tp),
2226 "unknown MAC, using family default\n");
5d320a20 2227 tp->mac_version = default_version;
58152cd4 2228 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
f7ffa9ae 2229 tp->mac_version = tp->supports_gmii ?
58152cd4 2230 RTL_GIGA_MAC_VER_42 :
2231 RTL_GIGA_MAC_VER_43;
6e1d0b89 2232 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
f7ffa9ae 2233 tp->mac_version = tp->supports_gmii ?
6e1d0b89
CHL		 2234 RTL_GIGA_MAC_VER_45 :
2235 RTL_GIGA_MAC_VER_47;
2236 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
f7ffa9ae 2237 tp->mac_version = tp->supports_gmii ?
6e1d0b89
CHL		 2238 RTL_GIGA_MAC_VER_46 :
2239 RTL_GIGA_MAC_VER_48;
5d320a20 2240 }
1da177e4
LT		 2241}
2242
2243static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2244{
49d17512 2245 netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2246}
2247
867763c1
FR		 2248struct phy_reg {
2249 u16 reg;
2250 u16 val;
2251};
2252
4da19633 2253static void rtl_writephy_batch(struct rtl8169_private *tp,
2254 const struct phy_reg *regs, int len)
867763c1
FR		 2255{
2256 while (len-- > 0) {
4da19633 2257 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2258 regs++;
2259 }
2260}
2261
bca03d5f 2262#define PHY_READ 0x00000000
2263#define PHY_DATA_OR 0x10000000
2264#define PHY_DATA_AND 0x20000000
2265#define PHY_BJMPN 0x30000000
eee3786f 2266#define PHY_MDIO_CHG 0x40000000
bca03d5f 2267#define PHY_CLEAR_READCOUNT 0x70000000
2268#define PHY_WRITE 0x80000000
2269#define PHY_READCOUNT_EQ_SKIP 0x90000000
2270#define PHY_COMP_EQ_SKIPN 0xa0000000
2271#define PHY_COMP_NEQ_SKIPN 0xb0000000
2272#define PHY_WRITE_PREVIOUS 0xc0000000
2273#define PHY_SKIPN 0xd0000000
2274#define PHY_DELAY_MS 0xe0000000
bca03d5f 2275
960aee6c
HW		 2276struct fw_info {
2277 u32 magic;
2278 char version[RTL_VER_SIZE];
2279 __le32 fw_start;
2280 __le32 fw_len;
2281 u8 chksum;
2282} __packed;
2283
1c361efb
FR		 2284#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2285
2286static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2287{
b6ffd97f 2288 const struct firmware *fw = rtl_fw->fw;
960aee6c 2289 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2290 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2291 char *version = rtl_fw->version;
2292 bool rc = false;
2293
2294 if (fw->size < FW_OPCODE_SIZE)
2295 goto out;
960aee6c
HW		 2296
2297 if (!fw_info->magic) {
2298 size_t i, size, start;
2299 u8 checksum = 0;
2300
2301 if (fw->size < sizeof(*fw_info))
2302 goto out;
2303
2304 for (i = 0; i < fw->size; i++)
2305 checksum += fw->data[i];
2306 if (checksum != 0)
2307 goto out;
2308
2309 start = le32_to_cpu(fw_info->fw_start);
2310 if (start > fw->size)
2311 goto out;
2312
2313 size = le32_to_cpu(fw_info->fw_len);
2314 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2315 goto out;
2316
2317 memcpy(version, fw_info->version, RTL_VER_SIZE);
2318
2319 pa->code = (__le32 *)(fw->data + start);
2320 pa->size = size;
2321 } else {
1c361efb
FR		 2322 if (fw->size % FW_OPCODE_SIZE)
2323 goto out;
2324
2325 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2326
2327 pa->code = (__le32 *)fw->data;
2328 pa->size = fw->size / FW_OPCODE_SIZE;
2329 }
2330 version[RTL_VER_SIZE - 1] = 0;
2331
2332 rc = true;
2333out:
2334 return rc;
2335}
2336
fd112f2e
FR		 2337static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2338 struct rtl_fw_phy_action *pa)
1c361efb 2339{
fd112f2e 2340 bool rc = false;
1c361efb 2341 size_t index;
bca03d5f 2342
1c361efb
FR		 2343 for (index = 0; index < pa->size; index++) {
2344 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2345 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2346
42b82dc1 2347 switch(action & 0xf0000000) {
2348 case PHY_READ:
2349 case PHY_DATA_OR:
2350 case PHY_DATA_AND:
eee3786f 2351 case PHY_MDIO_CHG:
42b82dc1 2352 case PHY_CLEAR_READCOUNT:
2353 case PHY_WRITE:
2354 case PHY_WRITE_PREVIOUS:
2355 case PHY_DELAY_MS:
2356 break;
2357
2358 case PHY_BJMPN:
2359 if (regno > index) {
fd112f2e 2360 netif_err(tp, ifup, tp->dev,
cecb5fd7 2361 "Out of range of firmware\n");
fd112f2e 2362 goto out;
42b82dc1 2363 }
2364 break;
2365 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2366 if (index + 2 >= pa->size) {
fd112f2e 2367 netif_err(tp, ifup, tp->dev,
cecb5fd7 2368 "Out of range of firmware\n");
fd112f2e 2369 goto out;
42b82dc1 2370 }
2371 break;
2372 case PHY_COMP_EQ_SKIPN:
2373 case PHY_COMP_NEQ_SKIPN:
2374 case PHY_SKIPN:
1c361efb 2375 if (index + 1 + regno >= pa->size) {
fd112f2e 2376 netif_err(tp, ifup, tp->dev,
cecb5fd7 2377 "Out of range of firmware\n");
fd112f2e 2378 goto out;
42b82dc1 2379 }
bca03d5f 2380 break;
2381
42b82dc1 2382 default:
fd112f2e 2383 netif_err(tp, ifup, tp->dev,
42b82dc1 2384 "Invalid action 0x%08x\n", action);
fd112f2e 2385 goto out;
bca03d5f 2386 }
2387 }
fd112f2e
FR		 2388 rc = true;
2389out:
2390 return rc;
2391}
bca03d5f 2392
fd112f2e
FR		 2393static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2394{
2395 struct net_device *dev = tp->dev;
2396 int rc = -EINVAL;
2397
2398 if (!rtl_fw_format_ok(tp, rtl_fw)) {
5c2d2b14 2399 netif_err(tp, ifup, dev, "invalid firmware\n");
fd112f2e
FR		 2400 goto out;
2401 }
2402
2403 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2404 rc = 0;
2405out:
2406 return rc;
2407}
2408
2409static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2410{
2411 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2412 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2413 u32 predata, count;
2414 size_t index;
2415
2416 predata = count = 0;
eee3786f 2417 org.write = ops->write;
2418 org.read = ops->read;
42b82dc1 2419
1c361efb
FR		 2420 for (index = 0; index < pa->size; ) {
2421 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2422 u32 data = action & 0x0000ffff;
42b82dc1 2423 u32 regno = (action & 0x0fff0000) >> 16;
2424
2425 if (!action)
2426 break;
bca03d5f 2427
2428 switch(action & 0xf0000000) {
42b82dc1 2429 case PHY_READ:
2430 predata = rtl_readphy(tp, regno);
2431 count++;
2432 index++;
2433 break;
2434 case PHY_DATA_OR:
2435 predata |= data;
2436 index++;
2437 break;
2438 case PHY_DATA_AND:
2439 predata &= data;
2440 index++;
2441 break;
2442 case PHY_BJMPN:
2443 index -= regno;
2444 break;
eee3786f 2445 case PHY_MDIO_CHG:
2446 if (data == 0) {
2447 ops->write = org.write;
2448 ops->read = org.read;
2449 } else if (data == 1) {
2450 ops->write = mac_mcu_write;
2451 ops->read = mac_mcu_read;
2452 }
2453
42b82dc1 2454 index++;
2455 break;
2456 case PHY_CLEAR_READCOUNT:
2457 count = 0;
2458 index++;
2459 break;
bca03d5f 2460 case PHY_WRITE:
42b82dc1 2461 rtl_writephy(tp, regno, data);
2462 index++;
2463 break;
2464 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2465 index += (count == data) ? 2 : 1;
bca03d5f 2466 break;
42b82dc1 2467 case PHY_COMP_EQ_SKIPN:
2468 if (predata == data)
2469 index += regno;
2470 index++;
2471 break;
2472 case PHY_COMP_NEQ_SKIPN:
2473 if (predata != data)
2474 index += regno;
2475 index++;
2476 break;
2477 case PHY_WRITE_PREVIOUS:
2478 rtl_writephy(tp, regno, predata);
2479 index++;
2480 break;
2481 case PHY_SKIPN:
2482 index += regno + 1;
2483 break;
2484 case PHY_DELAY_MS:
2485 mdelay(data);
2486 index++;
2487 break;
2488
bca03d5f 2489 default:
2490 BUG();
2491 }
2492 }
eee3786f 2493
2494 ops->write = org.write;
2495 ops->read = org.read;
bca03d5f 2496}
2497
f1e02ed1 2498static void rtl_release_firmware(struct rtl8169_private *tp)
2499{
b6ffd97f
FR		 2500 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2501 release_firmware(tp->rtl_fw->fw);
2502 kfree(tp->rtl_fw);
2503 }
2504 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2505}
2506
953a12cc 2507static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2508{
b6ffd97f 2509 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2510
2511 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2512 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2513 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2514}
2515
2516static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2517{
2518 if (rtl_readphy(tp, reg) != val)
2519 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2520 else
2521 rtl_apply_firmware(tp);
f1e02ed1 2522}
2523
4da19633 2524static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2525{
350f7596 2526 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2527 { 0x1f, 0x0001 },
2528 { 0x06, 0x006e },
2529 { 0x08, 0x0708 },
2530 { 0x15, 0x4000 },
2531 { 0x18, 0x65c7 },
1da177e4 2532
0b9b571d 2533 { 0x1f, 0x0001 },
2534 { 0x03, 0x00a1 },
2535 { 0x02, 0x0008 },
2536 { 0x01, 0x0120 },
2537 { 0x00, 0x1000 },
2538 { 0x04, 0x0800 },
2539 { 0x04, 0x0000 },
1da177e4 2540
0b9b571d 2541 { 0x03, 0xff41 },
2542 { 0x02, 0xdf60 },
2543 { 0x01, 0x0140 },
2544 { 0x00, 0x0077 },
2545 { 0x04, 0x7800 },
2546 { 0x04, 0x7000 },
2547
2548 { 0x03, 0x802f },
2549 { 0x02, 0x4f02 },
2550 { 0x01, 0x0409 },
2551 { 0x00, 0xf0f9 },
2552 { 0x04, 0x9800 },
2553 { 0x04, 0x9000 },
2554
2555 { 0x03, 0xdf01 },
2556 { 0x02, 0xdf20 },
2557 { 0x01, 0xff95 },
2558 { 0x00, 0xba00 },
2559 { 0x04, 0xa800 },
2560 { 0x04, 0xa000 },
2561
2562 { 0x03, 0xff41 },
2563 { 0x02, 0xdf20 },
2564 { 0x01, 0x0140 },
2565 { 0x00, 0x00bb },
2566 { 0x04, 0xb800 },
2567 { 0x04, 0xb000 },
2568
2569 { 0x03, 0xdf41 },
2570 { 0x02, 0xdc60 },
2571 { 0x01, 0x6340 },
2572 { 0x00, 0x007d },
2573 { 0x04, 0xd800 },
2574 { 0x04, 0xd000 },
2575
2576 { 0x03, 0xdf01 },
2577 { 0x02, 0xdf20 },
2578 { 0x01, 0x100a },
2579 { 0x00, 0xa0ff },
2580 { 0x04, 0xf800 },
2581 { 0x04, 0xf000 },
2582
2583 { 0x1f, 0x0000 },
2584 { 0x0b, 0x0000 },
2585 { 0x00, 0x9200 }
2586 };
1da177e4 2587
4da19633 2588 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2589}
2590
4da19633 2591static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2592{
350f7596 2593 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2594 { 0x1f, 0x0002 },
2595 { 0x01, 0x90d0 },
2596 { 0x1f, 0x0000 }
2597 };
2598
4da19633 2599 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2600}
2601
4da19633 2602static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2603{
2604 struct pci_dev *pdev = tp->pci_dev;
2e955856 2605
ccbae55e
SS		 2606 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2607 (pdev->subsystem_device != 0xe000))
2e955856 2608 return;
2609
4da19633 2610 rtl_writephy(tp, 0x1f, 0x0001);
2611 rtl_writephy(tp, 0x10, 0xf01b);
2612 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2613}
2614
4da19633 2615static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2616{
350f7596 2617 static const struct phy_reg phy_reg_init[] = {
2e955856 2618 { 0x1f, 0x0001 },
2619 { 0x04, 0x0000 },
2620 { 0x03, 0x00a1 },
2621 { 0x02, 0x0008 },
2622 { 0x01, 0x0120 },
2623 { 0x00, 0x1000 },
2624 { 0x04, 0x0800 },
2625 { 0x04, 0x9000 },
2626 { 0x03, 0x802f },
2627 { 0x02, 0x4f02 },
2628 { 0x01, 0x0409 },
2629 { 0x00, 0xf099 },
2630 { 0x04, 0x9800 },
2631 { 0x04, 0xa000 },
2632 { 0x03, 0xdf01 },
2633 { 0x02, 0xdf20 },
2634 { 0x01, 0xff95 },
2635 { 0x00, 0xba00 },
2636 { 0x04, 0xa800 },
2637 { 0x04, 0xf000 },
2638 { 0x03, 0xdf01 },
2639 { 0x02, 0xdf20 },
2640 { 0x01, 0x101a },
2641 { 0x00, 0xa0ff },
2642 { 0x04, 0xf800 },
2643 { 0x04, 0x0000 },
2644 { 0x1f, 0x0000 },
2645
2646 { 0x1f, 0x0001 },
2647 { 0x10, 0xf41b },
2648 { 0x14, 0xfb54 },
2649 { 0x18, 0xf5c7 },
2650 { 0x1f, 0x0000 },
2651
2652 { 0x1f, 0x0001 },
2653 { 0x17, 0x0cc0 },
2654 { 0x1f, 0x0000 }
2655 };
2656
4da19633 2657 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2658
4da19633 2659 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2660}
2661
4da19633 2662static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2663{
350f7596 2664 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2665 { 0x1f, 0x0001 },
2666 { 0x04, 0x0000 },
2667 { 0x03, 0x00a1 },
2668 { 0x02, 0x0008 },
2669 { 0x01, 0x0120 },
2670 { 0x00, 0x1000 },
2671 { 0x04, 0x0800 },
2672 { 0x04, 0x9000 },
2673 { 0x03, 0x802f },
2674 { 0x02, 0x4f02 },
2675 { 0x01, 0x0409 },
2676 { 0x00, 0xf099 },
2677 { 0x04, 0x9800 },
2678 { 0x04, 0xa000 },
2679 { 0x03, 0xdf01 },
2680 { 0x02, 0xdf20 },
2681 { 0x01, 0xff95 },
2682 { 0x00, 0xba00 },
2683 { 0x04, 0xa800 },
2684 { 0x04, 0xf000 },
2685 { 0x03, 0xdf01 },
2686 { 0x02, 0xdf20 },
2687 { 0x01, 0x101a },
2688 { 0x00, 0xa0ff },
2689 { 0x04, 0xf800 },
2690 { 0x04, 0x0000 },
2691 { 0x1f, 0x0000 },
2692
2693 { 0x1f, 0x0001 },
2694 { 0x0b, 0x8480 },
2695 { 0x1f, 0x0000 },
2696
2697 { 0x1f, 0x0001 },
2698 { 0x18, 0x67c7 },
2699 { 0x04, 0x2000 },
2700 { 0x03, 0x002f },
2701 { 0x02, 0x4360 },
2702 { 0x01, 0x0109 },
2703 { 0x00, 0x3022 },
2704 { 0x04, 0x2800 },
2705 { 0x1f, 0x0000 },
2706
2707 { 0x1f, 0x0001 },
2708 { 0x17, 0x0cc0 },
2709 { 0x1f, 0x0000 }
2710 };
2711
4da19633 2712 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2713}
2714
4da19633 2715static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2716{
350f7596 2717 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2718 { 0x10, 0xf41b },
2719 { 0x1f, 0x0000 }
2720 };
2721
4da19633 2722 rtl_writephy(tp, 0x1f, 0x0001);
2723 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2724
4da19633 2725 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2726}
2727
4da19633 2728static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2729{
350f7596 2730 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2731 { 0x1f, 0x0001 },
2732 { 0x10, 0xf41b },
2733 { 0x1f, 0x0000 }
2734 };
2735
4da19633 2736 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2737}
2738
4da19633 2739static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2740{
350f7596 2741 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2742 { 0x1f, 0x0000 },
2743 { 0x1d, 0x0f00 },
2744 { 0x1f, 0x0002 },
2745 { 0x0c, 0x1ec8 },
2746 { 0x1f, 0x0000 }
2747 };
2748
4da19633 2749 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2750}
2751
4da19633 2752static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2753{
350f7596 2754 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2755 { 0x1f, 0x0001 },
2756 { 0x1d, 0x3d98 },
2757 { 0x1f, 0x0000 }
2758 };
2759
4da19633 2760 rtl_writephy(tp, 0x1f, 0x0000);
2761 rtl_patchphy(tp, 0x14, 1 << 5);
2762 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2763
4da19633 2764 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2765}
2766
4da19633 2767static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2768{
350f7596 2769 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2770 { 0x1f, 0x0001 },
2771 { 0x12, 0x2300 },
867763c1
FR		 2772 { 0x1f, 0x0002 },
2773 { 0x00, 0x88d4 },
2774 { 0x01, 0x82b1 },
2775 { 0x03, 0x7002 },
2776 { 0x08, 0x9e30 },
2777 { 0x09, 0x01f0 },
2778 { 0x0a, 0x5500 },
2779 { 0x0c, 0x00c8 },
2780 { 0x1f, 0x0003 },
2781 { 0x12, 0xc096 },
2782 { 0x16, 0x000a },
f50d4275
FR		 2783 { 0x1f, 0x0000 },
2784 { 0x1f, 0x0000 },
2785 { 0x09, 0x2000 },
2786 { 0x09, 0x0000 }
867763c1
FR		 2787 };
2788
4da19633 2789 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2790
4da19633 2791 rtl_patchphy(tp, 0x14, 1 << 5);
2792 rtl_patchphy(tp, 0x0d, 1 << 5);
2793 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2794}
2795
4da19633 2796static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2797{
350f7596 2798 static const struct phy_reg phy_reg_init[] = {
f50d4275 2799 { 0x1f, 0x0001 },
7da97ec9 2800 { 0x12, 0x2300 },
f50d4275
FR		 2801 { 0x03, 0x802f },
2802 { 0x02, 0x4f02 },
2803 { 0x01, 0x0409 },
2804 { 0x00, 0xf099 },
2805 { 0x04, 0x9800 },
2806 { 0x04, 0x9000 },
2807 { 0x1d, 0x3d98 },
7da97ec9
FR		 2808 { 0x1f, 0x0002 },
2809 { 0x0c, 0x7eb8 },
f50d4275
FR		 2810 { 0x06, 0x0761 },
2811 { 0x1f, 0x0003 },
2812 { 0x16, 0x0f0a },
7da97ec9
FR		 2813 { 0x1f, 0x0000 }
2814 };
2815
4da19633 2816 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2817
4da19633 2818 rtl_patchphy(tp, 0x16, 1 << 0);
2819 rtl_patchphy(tp, 0x14, 1 << 5);
2820 rtl_patchphy(tp, 0x0d, 1 << 5);
2821 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2822}
2823
4da19633 2824static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2825{
350f7596 2826 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2827 { 0x1f, 0x0001 },
2828 { 0x12, 0x2300 },
2829 { 0x1d, 0x3d98 },
2830 { 0x1f, 0x0002 },
2831 { 0x0c, 0x7eb8 },
2832 { 0x06, 0x5461 },
2833 { 0x1f, 0x0003 },
2834 { 0x16, 0x0f0a },
2835 { 0x1f, 0x0000 }
2836 };
2837
4da19633 2838 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2839
4da19633 2840 rtl_patchphy(tp, 0x16, 1 << 0);
2841 rtl_patchphy(tp, 0x14, 1 << 5);
2842 rtl_patchphy(tp, 0x0d, 1 << 5);
2843 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2844}
2845
4da19633 2846static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2847{
4da19633 2848 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2849}
2850
bca03d5f 2851static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2852{
350f7596 2853 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2854 /* Channel Estimation */
5b538df9 2855 { 0x1f, 0x0001 },
daf9df6d 2856 { 0x06, 0x4064 },
2857 { 0x07, 0x2863 },
2858 { 0x08, 0x059c },
2859 { 0x09, 0x26b4 },
2860 { 0x0a, 0x6a19 },
2861 { 0x0b, 0xdcc8 },
2862 { 0x10, 0xf06d },
2863 { 0x14, 0x7f68 },
2864 { 0x18, 0x7fd9 },
2865 { 0x1c, 0xf0ff },
2866 { 0x1d, 0x3d9c },
5b538df9 2867 { 0x1f, 0x0003 },
daf9df6d 2868 { 0x12, 0xf49f },
2869 { 0x13, 0x070b },
2870 { 0x1a, 0x05ad },
bca03d5f 2871 { 0x14, 0x94c0 },
2872
2873 /*
2874 * Tx Error Issue
cecb5fd7 2875 * Enhance line driver power
bca03d5f 2876 */
5b538df9 2877 { 0x1f, 0x0002 },
daf9df6d 2878 { 0x06, 0x5561 },
2879 { 0x1f, 0x0005 },
2880 { 0x05, 0x8332 },
bca03d5f 2881 { 0x06, 0x5561 },
2882
2883 /*
2884 * Can not link to 1Gbps with bad cable
2885 * Decrease SNR threshold form 21.07dB to 19.04dB
2886 */
2887 { 0x1f, 0x0001 },
2888 { 0x17, 0x0cc0 },
daf9df6d 2889
5b538df9 2890 { 0x1f, 0x0000 },
bca03d5f 2891 { 0x0d, 0xf880 }
daf9df6d 2892 };
2893
4da19633 2894 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2895
bca03d5f 2896 /*
2897 * Rx Error Issue
2898 * Fine Tune Switching regulator parameter
2899 */
4da19633 2900 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2901 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2902 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2903
fdf6fc06 2904 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2905 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2906 { 0x1f, 0x0002 },
2907 { 0x05, 0x669a },
2908 { 0x1f, 0x0005 },
2909 { 0x05, 0x8330 },
2910 { 0x06, 0x669a },
2911 { 0x1f, 0x0002 }
2912 };
2913 int val;
2914
4da19633 2915 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2916
4da19633 2917 val = rtl_readphy(tp, 0x0d);
daf9df6d 2918
2919 if ((val & 0x00ff) != 0x006c) {
350f7596 2920 static const u32 set[] = {
daf9df6d 2921 0x0065, 0x0066, 0x0067, 0x0068,
2922 0x0069, 0x006a, 0x006b, 0x006c
2923 };
2924 int i;
2925
4da19633 2926 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2927
2928 val &= 0xff00;
2929 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2930 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2931 }
2932 } else {
350f7596 2933 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2934 { 0x1f, 0x0002 },
2935 { 0x05, 0x6662 },
2936 { 0x1f, 0x0005 },
2937 { 0x05, 0x8330 },
2938 { 0x06, 0x6662 }
2939 };
2940
4da19633 2941 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2942 }
2943
bca03d5f 2944 /* RSET couple improve */
4da19633 2945 rtl_writephy(tp, 0x1f, 0x0002);
2946 rtl_patchphy(tp, 0x0d, 0x0300);
2947 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2948
bca03d5f 2949 /* Fine tune PLL performance */
4da19633 2950 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2951 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2952 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2953
4da19633 2954 rtl_writephy(tp, 0x1f, 0x0005);
2955 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2956
2957 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2958
4da19633 2959 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2960}
2961
bca03d5f 2962static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2963{
350f7596 2964 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2965 /* Channel Estimation */
daf9df6d 2966 { 0x1f, 0x0001 },
2967 { 0x06, 0x4064 },
2968 { 0x07, 0x2863 },
2969 { 0x08, 0x059c },
2970 { 0x09, 0x26b4 },
2971 { 0x0a, 0x6a19 },
2972 { 0x0b, 0xdcc8 },
2973 { 0x10, 0xf06d },
2974 { 0x14, 0x7f68 },
2975 { 0x18, 0x7fd9 },
2976 { 0x1c, 0xf0ff },
2977 { 0x1d, 0x3d9c },
2978 { 0x1f, 0x0003 },
2979 { 0x12, 0xf49f },
2980 { 0x13, 0x070b },
2981 { 0x1a, 0x05ad },
2982 { 0x14, 0x94c0 },
2983
bca03d5f 2984 /*
2985 * Tx Error Issue
cecb5fd7 2986 * Enhance line driver power
bca03d5f 2987 */
daf9df6d 2988 { 0x1f, 0x0002 },
2989 { 0x06, 0x5561 },
2990 { 0x1f, 0x0005 },
2991 { 0x05, 0x8332 },
bca03d5f 2992 { 0x06, 0x5561 },
2993
2994 /*
2995 * Can not link to 1Gbps with bad cable
2996 * Decrease SNR threshold form 21.07dB to 19.04dB
2997 */
2998 { 0x1f, 0x0001 },
2999 { 0x17, 0x0cc0 },
daf9df6d 3000
3001 { 0x1f, 0x0000 },
bca03d5f 3002 { 0x0d, 0xf880 }
5b538df9
FR		 3003 };
3004
4da19633 3005 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 3006
fdf6fc06 3007 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3008 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3009 { 0x1f, 0x0002 },
3010 { 0x05, 0x669a },
5b538df9 3011 { 0x1f, 0x0005 },
daf9df6d 3012 { 0x05, 0x8330 },
3013 { 0x06, 0x669a },
3014
3015 { 0x1f, 0x0002 }
3016 };
3017 int val;
3018
4da19633 3019 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3020
4da19633 3021 val = rtl_readphy(tp, 0x0d);
daf9df6d 3022 if ((val & 0x00ff) != 0x006c) {
b6bc7650 3023 static const u32 set[] = {
daf9df6d 3024 0x0065, 0x0066, 0x0067, 0x0068,
3025 0x0069, 0x006a, 0x006b, 0x006c
3026 };
3027 int i;
3028
4da19633 3029 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3030
3031 val &= 0xff00;
3032 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3033 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3034 }
3035 } else {
350f7596 3036 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3037 { 0x1f, 0x0002 },
3038 { 0x05, 0x2642 },
5b538df9 3039 { 0x1f, 0x0005 },
daf9df6d 3040 { 0x05, 0x8330 },
3041 { 0x06, 0x2642 }
5b538df9
FR		 3042 };
3043
4da19633 3044 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3045 }
3046
bca03d5f 3047 /* Fine tune PLL performance */
4da19633 3048 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3049 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3050 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3051
bca03d5f 3052 /* Switching regulator Slew rate */
4da19633 3053 rtl_writephy(tp, 0x1f, 0x0002);
3054 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 3055
4da19633 3056 rtl_writephy(tp, 0x1f, 0x0005);
3057 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3058
3059 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 3060
4da19633 3061 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3062}
3063
4da19633 3064static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3065{
350f7596 3066 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3067 { 0x1f, 0x0002 },
3068 { 0x10, 0x0008 },
3069 { 0x0d, 0x006c },
3070
3071 { 0x1f, 0x0000 },
3072 { 0x0d, 0xf880 },
3073
3074 { 0x1f, 0x0001 },
3075 { 0x17, 0x0cc0 },
3076
3077 { 0x1f, 0x0001 },
3078 { 0x0b, 0xa4d8 },
3079 { 0x09, 0x281c },
3080 { 0x07, 0x2883 },
3081 { 0x0a, 0x6b35 },
3082 { 0x1d, 0x3da4 },
3083 { 0x1c, 0xeffd },
3084 { 0x14, 0x7f52 },
3085 { 0x18, 0x7fc6 },
3086 { 0x08, 0x0601 },
3087 { 0x06, 0x4063 },
3088 { 0x10, 0xf074 },
3089 { 0x1f, 0x0003 },
3090 { 0x13, 0x0789 },
3091 { 0x12, 0xf4bd },
3092 { 0x1a, 0x04fd },
3093 { 0x14, 0x84b0 },
3094 { 0x1f, 0x0000 },
3095 { 0x00, 0x9200 },
3096
3097 { 0x1f, 0x0005 },
3098 { 0x01, 0x0340 },
3099 { 0x1f, 0x0001 },
3100 { 0x04, 0x4000 },
3101 { 0x03, 0x1d21 },
3102 { 0x02, 0x0c32 },
3103 { 0x01, 0x0200 },
3104 { 0x00, 0x5554 },
3105 { 0x04, 0x4800 },
3106 { 0x04, 0x4000 },
3107 { 0x04, 0xf000 },
3108 { 0x03, 0xdf01 },
3109 { 0x02, 0xdf20 },
3110 { 0x01, 0x101a },
3111 { 0x00, 0xa0ff },
3112 { 0x04, 0xf800 },
3113 { 0x04, 0xf000 },
3114 { 0x1f, 0x0000 },
3115
3116 { 0x1f, 0x0007 },
3117 { 0x1e, 0x0023 },
3118 { 0x16, 0x0000 },
3119 { 0x1f, 0x0000 }
3120 };
3121
4da19633 3122 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3123}
3124
e6de30d6 3125static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3126{
3127 static const struct phy_reg phy_reg_init[] = {
3128 { 0x1f, 0x0001 },
3129 { 0x17, 0x0cc0 },
3130
3131 { 0x1f, 0x0007 },
3132 { 0x1e, 0x002d },
3133 { 0x18, 0x0040 },
3134 { 0x1f, 0x0000 }
3135 };
3136
3137 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3138 rtl_patchphy(tp, 0x0d, 1 << 5);
3139}
3140
70090424 3141static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3142{
3143 static const struct phy_reg phy_reg_init[] = {
3144 /* Enable Delay cap */
3145 { 0x1f, 0x0005 },
3146 { 0x05, 0x8b80 },
3147 { 0x06, 0xc896 },
3148 { 0x1f, 0x0000 },
3149
3150 /* Channel estimation fine tune */
3151 { 0x1f, 0x0001 },
3152 { 0x0b, 0x6c20 },
3153 { 0x07, 0x2872 },
3154 { 0x1c, 0xefff },
3155 { 0x1f, 0x0003 },
3156 { 0x14, 0x6420 },
3157 { 0x1f, 0x0000 },
3158
3159 /* Update PFM & 10M TX idle timer */
3160 { 0x1f, 0x0007 },
3161 { 0x1e, 0x002f },
3162 { 0x15, 0x1919 },
3163 { 0x1f, 0x0000 },
3164
3165 { 0x1f, 0x0007 },
3166 { 0x1e, 0x00ac },
3167 { 0x18, 0x0006 },
3168 { 0x1f, 0x0000 }
3169 };
3170
15ecd039
FR		 3171 rtl_apply_firmware(tp);
3172
01dc7fec 3173 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3174
3175 /* DCO enable for 10M IDLE Power */
3176 rtl_writephy(tp, 0x1f, 0x0007);
3177 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3178 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3179 rtl_writephy(tp, 0x1f, 0x0000);
3180
3181 /* For impedance matching */
3182 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3183 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3184 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3185
3186 /* PHY auto speed down */
3187 rtl_writephy(tp, 0x1f, 0x0007);
3188 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3189 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3190 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3191 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3192
3193 rtl_writephy(tp, 0x1f, 0x0005);
3194 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3195 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3196 rtl_writephy(tp, 0x1f, 0x0000);
3197
3198 rtl_writephy(tp, 0x1f, 0x0005);
3199 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3200 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3201 rtl_writephy(tp, 0x1f, 0x0007);
3202 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3203 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3204 rtl_writephy(tp, 0x1f, 0x0006);
3205 rtl_writephy(tp, 0x00, 0x5a00);
3206 rtl_writephy(tp, 0x1f, 0x0000);
3207 rtl_writephy(tp, 0x0d, 0x0007);
3208 rtl_writephy(tp, 0x0e, 0x003c);
3209 rtl_writephy(tp, 0x0d, 0x4007);
3210 rtl_writephy(tp, 0x0e, 0x0000);
3211 rtl_writephy(tp, 0x0d, 0x0000);
3212}
3213
9ecb9aab 3214static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3215{
3216 const u16 w[] = {
3217 addr[0] | (addr[1] << 8),
3218 addr[2] | (addr[3] << 8),
3219 addr[4] | (addr[5] << 8)
3220 };
3221 const struct exgmac_reg e[] = {
3222 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3223 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3224 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3225 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3226 };
3227
3228 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3229}
3230
70090424
HW		 3231static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3232{
3233 static const struct phy_reg phy_reg_init[] = {
3234 /* Enable Delay cap */
3235 { 0x1f, 0x0004 },
3236 { 0x1f, 0x0007 },
3237 { 0x1e, 0x00ac },
3238 { 0x18, 0x0006 },
3239 { 0x1f, 0x0002 },
3240 { 0x1f, 0x0000 },
3241 { 0x1f, 0x0000 },
3242
3243 /* Channel estimation fine tune */
3244 { 0x1f, 0x0003 },
3245 { 0x09, 0xa20f },
3246 { 0x1f, 0x0000 },
3247 { 0x1f, 0x0000 },
3248
3249 /* Green Setting */
3250 { 0x1f, 0x0005 },
3251 { 0x05, 0x8b5b },
3252 { 0x06, 0x9222 },
3253 { 0x05, 0x8b6d },
3254 { 0x06, 0x8000 },
3255 { 0x05, 0x8b76 },
3256 { 0x06, 0x8000 },
3257 { 0x1f, 0x0000 }
3258 };
3259
3260 rtl_apply_firmware(tp);
3261
3262 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3263
3264 /* For 4-corner performance improve */
3265 rtl_writephy(tp, 0x1f, 0x0005);
3266 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3267 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3268 rtl_writephy(tp, 0x1f, 0x0000);
3269
3270 /* PHY auto speed down */
3271 rtl_writephy(tp, 0x1f, 0x0004);
3272 rtl_writephy(tp, 0x1f, 0x0007);
3273 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3274 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3275 rtl_writephy(tp, 0x1f, 0x0002);
3276 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3277 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3278
3279 /* improve 10M EEE waveform */
3280 rtl_writephy(tp, 0x1f, 0x0005);
3281 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3282 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3283 rtl_writephy(tp, 0x1f, 0x0000);
3284
3285 /* Improve 2-pair detection performance */
3286 rtl_writephy(tp, 0x1f, 0x0005);
3287 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3288 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3289 rtl_writephy(tp, 0x1f, 0x0000);
3290
3291 /* EEE setting */
1814d6a8 3292 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
70090424
HW		 3293 rtl_writephy(tp, 0x1f, 0x0005);
3294 rtl_writephy(tp, 0x05, 0x8b85);
1814d6a8 3295 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
70090424
HW		 3296 rtl_writephy(tp, 0x1f, 0x0004);
3297 rtl_writephy(tp, 0x1f, 0x0007);
3298 rtl_writephy(tp, 0x1e, 0x0020);
1814d6a8 3299 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
70090424
HW		 3300 rtl_writephy(tp, 0x1f, 0x0002);
3301 rtl_writephy(tp, 0x1f, 0x0000);
3302 rtl_writephy(tp, 0x0d, 0x0007);
3303 rtl_writephy(tp, 0x0e, 0x003c);
3304 rtl_writephy(tp, 0x0d, 0x4007);
1814d6a8 3305 rtl_writephy(tp, 0x0e, 0x0006);
70090424
HW		 3306 rtl_writephy(tp, 0x0d, 0x0000);
3307
3308 /* Green feature */
3309 rtl_writephy(tp, 0x1f, 0x0003);
1814d6a8
HK		 3310 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3311 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
70090424 3312 rtl_writephy(tp, 0x1f, 0x0000);
b399a394
HK		 3313 rtl_writephy(tp, 0x1f, 0x0005);
3314 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3315 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3316
9ecb9aab 3317 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3318 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3319}
3320
5f886e08
HW		 3321static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3322{
3323 /* For 4-corner performance improve */
3324 rtl_writephy(tp, 0x1f, 0x0005);
3325 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3326 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3327 rtl_writephy(tp, 0x1f, 0x0000);
3328
3329 /* PHY auto speed down */
3330 rtl_writephy(tp, 0x1f, 0x0007);
3331 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3332 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3333 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3334 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3335
3336 /* Improve 10M EEE waveform */
3337 rtl_writephy(tp, 0x1f, 0x0005);
3338 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3339 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3340 rtl_writephy(tp, 0x1f, 0x0000);
3341}
3342
c2218925
HW		 3343static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3344{
3345 static const struct phy_reg phy_reg_init[] = {
3346 /* Channel estimation fine tune */
3347 { 0x1f, 0x0003 },
3348 { 0x09, 0xa20f },
3349 { 0x1f, 0x0000 },
3350
3351 /* Modify green table for giga & fnet */
3352 { 0x1f, 0x0005 },
3353 { 0x05, 0x8b55 },
3354 { 0x06, 0x0000 },
3355 { 0x05, 0x8b5e },
3356 { 0x06, 0x0000 },
3357 { 0x05, 0x8b67 },
3358 { 0x06, 0x0000 },
3359 { 0x05, 0x8b70 },
3360 { 0x06, 0x0000 },
3361 { 0x1f, 0x0000 },
3362 { 0x1f, 0x0007 },
3363 { 0x1e, 0x0078 },
3364 { 0x17, 0x0000 },
3365 { 0x19, 0x00fb },
3366 { 0x1f, 0x0000 },
3367
3368 /* Modify green table for 10M */
3369 { 0x1f, 0x0005 },
3370 { 0x05, 0x8b79 },
3371 { 0x06, 0xaa00 },
3372 { 0x1f, 0x0000 },
3373
3374 /* Disable hiimpedance detection (RTCT) */
3375 { 0x1f, 0x0003 },
3376 { 0x01, 0x328a },
3377 { 0x1f, 0x0000 }
3378 };
3379
3380 rtl_apply_firmware(tp);
3381
3382 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3383
5f886e08 3384 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3385
3386 /* Improve 2-pair detection performance */
3387 rtl_writephy(tp, 0x1f, 0x0005);
3388 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3389 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3390 rtl_writephy(tp, 0x1f, 0x0000);
3391}
3392
3393static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3394{
3395 rtl_apply_firmware(tp);
3396
5f886e08 3397 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3398}
3399
b3d7b2f2
HW		 3400static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3401{
b3d7b2f2
HW		 3402 static const struct phy_reg phy_reg_init[] = {
3403 /* Channel estimation fine tune */
3404 { 0x1f, 0x0003 },
3405 { 0x09, 0xa20f },
3406 { 0x1f, 0x0000 },
3407
3408 /* Modify green table for giga & fnet */
3409 { 0x1f, 0x0005 },
3410 { 0x05, 0x8b55 },
3411 { 0x06, 0x0000 },
3412 { 0x05, 0x8b5e },
3413 { 0x06, 0x0000 },
3414 { 0x05, 0x8b67 },
3415 { 0x06, 0x0000 },
3416 { 0x05, 0x8b70 },
3417 { 0x06, 0x0000 },
3418 { 0x1f, 0x0000 },
3419 { 0x1f, 0x0007 },
3420 { 0x1e, 0x0078 },
3421 { 0x17, 0x0000 },
3422 { 0x19, 0x00aa },
3423 { 0x1f, 0x0000 },
3424
3425 /* Modify green table for 10M */
3426 { 0x1f, 0x0005 },
3427 { 0x05, 0x8b79 },
3428 { 0x06, 0xaa00 },
3429 { 0x1f, 0x0000 },
3430
3431 /* Disable hiimpedance detection (RTCT) */
3432 { 0x1f, 0x0003 },
3433 { 0x01, 0x328a },
3434 { 0x1f, 0x0000 }
3435 };
3436
3437
3438 rtl_apply_firmware(tp);
3439
3440 rtl8168f_hw_phy_config(tp);
3441
3442 /* Improve 2-pair detection performance */
3443 rtl_writephy(tp, 0x1f, 0x0005);
3444 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3445 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3446 rtl_writephy(tp, 0x1f, 0x0000);
3447
3448 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3449
3450 /* Modify green table for giga */
3451 rtl_writephy(tp, 0x1f, 0x0005);
3452 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3453 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3454 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3455 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3456 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3457 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3458 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3459 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3460 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3461 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3462 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3463 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3464 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3465 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3466 rtl_writephy(tp, 0x1f, 0x0000);
3467
3468 /* uc same-seed solution */
3469 rtl_writephy(tp, 0x1f, 0x0005);
3470 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3471 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3472 rtl_writephy(tp, 0x1f, 0x0000);
3473
3474 /* eee setting */
706123d0 3475 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3476 rtl_writephy(tp, 0x1f, 0x0005);
3477 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3478 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3479 rtl_writephy(tp, 0x1f, 0x0004);
3480 rtl_writephy(tp, 0x1f, 0x0007);
3481 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3482 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3483 rtl_writephy(tp, 0x1f, 0x0000);
3484 rtl_writephy(tp, 0x0d, 0x0007);
3485 rtl_writephy(tp, 0x0e, 0x003c);
3486 rtl_writephy(tp, 0x0d, 0x4007);
3487 rtl_writephy(tp, 0x0e, 0x0000);
3488 rtl_writephy(tp, 0x0d, 0x0000);
3489
3490 /* Green feature */
3491 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3492 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3493 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3494 rtl_writephy(tp, 0x1f, 0x0000);
3495}
3496
c558386b
HW		 3497static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3498{
c558386b
HW		 3499 rtl_apply_firmware(tp);
3500
41f44d13 3501 rtl_writephy(tp, 0x1f, 0x0a46);
3502 if (rtl_readphy(tp, 0x10) & 0x0100) {
3503 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3504 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3505 } else {
3506 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3507 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3508 }
c558386b 3509
41f44d13 3510 rtl_writephy(tp, 0x1f, 0x0a46);
3511 if (rtl_readphy(tp, 0x13) & 0x0100) {
3512 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3513 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 3514 } else {
fe7524c0 3515 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3516 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3517 }
c558386b 3518
41f44d13 3519 /* Enable PHY auto speed down */
3520 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3521 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3522
fe7524c0 3523 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3524 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 3525 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3526 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 3527 rtl_writephy(tp, 0x1f, 0x0a43);
3528 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 3529 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3530 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 3531
41f44d13 3532 /* EEE auto-fallback function */
3533 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 3534 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3535
41f44d13 3536 /* Enable UC LPF tune function */
3537 rtl_writephy(tp, 0x1f, 0x0a43);
3538 rtl_writephy(tp, 0x13, 0x8012);
76564428 3539 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 3540
3541 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 3542 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 3543
fe7524c0 3544 /* Improve SWR Efficiency */
3545 rtl_writephy(tp, 0x1f, 0x0bcd);
3546 rtl_writephy(tp, 0x14, 0x5065);
3547 rtl_writephy(tp, 0x14, 0xd065);
3548 rtl_writephy(tp, 0x1f, 0x0bc8);
3549 rtl_writephy(tp, 0x11, 0x5655);
3550 rtl_writephy(tp, 0x1f, 0x0bcd);
3551 rtl_writephy(tp, 0x14, 0x1065);
3552 rtl_writephy(tp, 0x14, 0x9065);
3553 rtl_writephy(tp, 0x14, 0x1065);
3554
1bac1072
DC		 3555 /* Check ALDPS bit, disable it if enabled */
3556 rtl_writephy(tp, 0x1f, 0x0a43);
3557 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3558 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 3559
41f44d13 3560 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3561}
3562
57538c4a 3563static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3564{
3565 rtl_apply_firmware(tp);
3566}
3567
6e1d0b89
CHL		 3568static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3569{
3570 u16 dout_tapbin;
3571 u32 data;
3572
3573 rtl_apply_firmware(tp);
3574
3575 /* CHN EST parameters adjust - giga master */
3576 rtl_writephy(tp, 0x1f, 0x0a43);
3577 rtl_writephy(tp, 0x13, 0x809b);
76564428 3578 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 3579 rtl_writephy(tp, 0x13, 0x80a2);
76564428 3580 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 3581 rtl_writephy(tp, 0x13, 0x80a4);
76564428 3582 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 3583 rtl_writephy(tp, 0x13, 0x809c);
76564428 3584 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 3585 rtl_writephy(tp, 0x1f, 0x0000);
3586
3587 /* CHN EST parameters adjust - giga slave */
3588 rtl_writephy(tp, 0x1f, 0x0a43);
3589 rtl_writephy(tp, 0x13, 0x80ad);
76564428 3590 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 3591 rtl_writephy(tp, 0x13, 0x80b4);
76564428 3592 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 3593 rtl_writephy(tp, 0x13, 0x80ac);
76564428 3594 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 3595 rtl_writephy(tp, 0x1f, 0x0000);
3596
3597 /* CHN EST parameters adjust - fnet */
3598 rtl_writephy(tp, 0x1f, 0x0a43);
3599 rtl_writephy(tp, 0x13, 0x808e);
76564428 3600 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 3601 rtl_writephy(tp, 0x13, 0x8090);
76564428 3602 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 3603 rtl_writephy(tp, 0x13, 0x8092);
76564428 3604 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 3605 rtl_writephy(tp, 0x1f, 0x0000);
3606
3607 /* enable R-tune & PGA-retune function */
3608 dout_tapbin = 0;
3609 rtl_writephy(tp, 0x1f, 0x0a46);
3610 data = rtl_readphy(tp, 0x13);
3611 data &= 3;
3612 data <<= 2;
3613 dout_tapbin |= data;
3614 data = rtl_readphy(tp, 0x12);
3615 data &= 0xc000;
3616 data >>= 14;
3617 dout_tapbin |= data;
3618 dout_tapbin = ~(dout_tapbin^0x08);
3619 dout_tapbin <<= 12;
3620 dout_tapbin &= 0xf000;
3621 rtl_writephy(tp, 0x1f, 0x0a43);
3622 rtl_writephy(tp, 0x13, 0x827a);
76564428 3623 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3624 rtl_writephy(tp, 0x13, 0x827b);
76564428 3625 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3626 rtl_writephy(tp, 0x13, 0x827c);
76564428 3627 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3628 rtl_writephy(tp, 0x13, 0x827d);
76564428 3629 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 3630
3631 rtl_writephy(tp, 0x1f, 0x0a43);
3632 rtl_writephy(tp, 0x13, 0x0811);
76564428 3633 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3634 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3635 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3636 rtl_writephy(tp, 0x1f, 0x0000);
3637
3638 /* enable GPHY 10M */
3639 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3640 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3641 rtl_writephy(tp, 0x1f, 0x0000);
3642
3643 /* SAR ADC performance */
3644 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 3645 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 3646 rtl_writephy(tp, 0x1f, 0x0000);
3647
3648 rtl_writephy(tp, 0x1f, 0x0a43);
3649 rtl_writephy(tp, 0x13, 0x803f);
76564428 3650 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3651 rtl_writephy(tp, 0x13, 0x8047);
76564428 3652 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3653 rtl_writephy(tp, 0x13, 0x804f);
76564428 3654 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3655 rtl_writephy(tp, 0x13, 0x8057);
76564428 3656 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3657 rtl_writephy(tp, 0x13, 0x805f);
76564428 3658 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3659 rtl_writephy(tp, 0x13, 0x8067);
76564428 3660 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3661 rtl_writephy(tp, 0x13, 0x806f);
76564428 3662 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 3663 rtl_writephy(tp, 0x1f, 0x0000);
3664
3665 /* disable phy pfm mode */
3666 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3667 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3668 rtl_writephy(tp, 0x1f, 0x0000);
3669
3670 /* Check ALDPS bit, disable it if enabled */
3671 rtl_writephy(tp, 0x1f, 0x0a43);
3672 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3673 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3674
3675 rtl_writephy(tp, 0x1f, 0x0000);
3676}
3677
3678static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3679{
3680 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3681 u16 rlen;
3682 u32 data;
3683
3684 rtl_apply_firmware(tp);
3685
3686 /* CHIN EST parameter update */
3687 rtl_writephy(tp, 0x1f, 0x0a43);
3688 rtl_writephy(tp, 0x13, 0x808a);
76564428 3689 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 3690 rtl_writephy(tp, 0x1f, 0x0000);
3691
3692 /* enable R-tune & PGA-retune function */
3693 rtl_writephy(tp, 0x1f, 0x0a43);
3694 rtl_writephy(tp, 0x13, 0x0811);
76564428 3695 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3696 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3697 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3698 rtl_writephy(tp, 0x1f, 0x0000);
3699
3700 /* enable GPHY 10M */
3701 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3702 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3703 rtl_writephy(tp, 0x1f, 0x0000);
3704
3705 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3706 data = r8168_mac_ocp_read(tp, 0xdd02);
3707 ioffset_p3 = ((data & 0x80)>>7);
3708 ioffset_p3 <<= 3;
3709
3710 data = r8168_mac_ocp_read(tp, 0xdd00);
3711 ioffset_p3 |= ((data & (0xe000))>>13);
3712 ioffset_p2 = ((data & (0x1e00))>>9);
3713 ioffset_p1 = ((data & (0x01e0))>>5);
3714 ioffset_p0 = ((data & 0x0010)>>4);
3715 ioffset_p0 <<= 3;
3716 ioffset_p0 |= (data & (0x07));
3717 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3718
05b9687b 3719 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
e2e2788e 3720 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
6e1d0b89
CHL		 3721 rtl_writephy(tp, 0x1f, 0x0bcf);
3722 rtl_writephy(tp, 0x16, data);
3723 rtl_writephy(tp, 0x1f, 0x0000);
3724 }
3725
3726 /* Modify rlen (TX LPF corner frequency) level */
3727 rtl_writephy(tp, 0x1f, 0x0bcd);
3728 data = rtl_readphy(tp, 0x16);
3729 data &= 0x000f;
3730 rlen = 0;
3731 if (data > 3)
3732 rlen = data - 3;
3733 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3734 rtl_writephy(tp, 0x17, data);
3735 rtl_writephy(tp, 0x1f, 0x0bcd);
3736 rtl_writephy(tp, 0x1f, 0x0000);
3737
3738 /* disable phy pfm mode */
3739 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3740 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3741 rtl_writephy(tp, 0x1f, 0x0000);
3742
3743 /* Check ALDPS bit, disable it if enabled */
3744 rtl_writephy(tp, 0x1f, 0x0a43);
3745 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3746 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3747
3748 rtl_writephy(tp, 0x1f, 0x0000);
3749}
3750
935e2218
CHL		 3751static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3752{
3753 /* Enable PHY auto speed down */
3754 rtl_writephy(tp, 0x1f, 0x0a44);
3755 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3756 rtl_writephy(tp, 0x1f, 0x0000);
3757
3758 /* patch 10M & ALDPS */
3759 rtl_writephy(tp, 0x1f, 0x0bcc);
3760 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3761 rtl_writephy(tp, 0x1f, 0x0a44);
3762 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3763 rtl_writephy(tp, 0x1f, 0x0a43);
3764 rtl_writephy(tp, 0x13, 0x8084);
3765 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3766 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3767 rtl_writephy(tp, 0x1f, 0x0000);
3768
3769 /* Enable EEE auto-fallback function */
3770 rtl_writephy(tp, 0x1f, 0x0a4b);
3771 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3772 rtl_writephy(tp, 0x1f, 0x0000);
3773
3774 /* Enable UC LPF tune function */
3775 rtl_writephy(tp, 0x1f, 0x0a43);
3776 rtl_writephy(tp, 0x13, 0x8012);
3777 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3778 rtl_writephy(tp, 0x1f, 0x0000);
3779
3780 /* set rg_sel_sdm_rate */
3781 rtl_writephy(tp, 0x1f, 0x0c42);
3782 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3783 rtl_writephy(tp, 0x1f, 0x0000);
3784
3785 /* Check ALDPS bit, disable it if enabled */
3786 rtl_writephy(tp, 0x1f, 0x0a43);
3787 if (rtl_readphy(tp, 0x10) & 0x0004)
3788 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3789
3790 rtl_writephy(tp, 0x1f, 0x0000);
3791}
3792
3793static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3794{
3795 /* patch 10M & ALDPS */
3796 rtl_writephy(tp, 0x1f, 0x0bcc);
3797 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3798 rtl_writephy(tp, 0x1f, 0x0a44);
3799 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3800 rtl_writephy(tp, 0x1f, 0x0a43);
3801 rtl_writephy(tp, 0x13, 0x8084);
3802 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3803 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3804 rtl_writephy(tp, 0x1f, 0x0000);
3805
3806 /* Enable UC LPF tune function */
3807 rtl_writephy(tp, 0x1f, 0x0a43);
3808 rtl_writephy(tp, 0x13, 0x8012);
3809 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3810 rtl_writephy(tp, 0x1f, 0x0000);
3811
3812 /* Set rg_sel_sdm_rate */
3813 rtl_writephy(tp, 0x1f, 0x0c42);
3814 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3815 rtl_writephy(tp, 0x1f, 0x0000);
3816
3817 /* Channel estimation parameters */
3818 rtl_writephy(tp, 0x1f, 0x0a43);
3819 rtl_writephy(tp, 0x13, 0x80f3);
3820 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3821 rtl_writephy(tp, 0x13, 0x80f0);
3822 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3823 rtl_writephy(tp, 0x13, 0x80ef);
3824 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3825 rtl_writephy(tp, 0x13, 0x80f6);
3826 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3827 rtl_writephy(tp, 0x13, 0x80ec);
3828 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3829 rtl_writephy(tp, 0x13, 0x80ed);
3830 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3831 rtl_writephy(tp, 0x13, 0x80f2);
3832 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3833 rtl_writephy(tp, 0x13, 0x80f4);
3834 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3835 rtl_writephy(tp, 0x1f, 0x0a43);
3836 rtl_writephy(tp, 0x13, 0x8110);
3837 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3838 rtl_writephy(tp, 0x13, 0x810f);
3839 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3840 rtl_writephy(tp, 0x13, 0x8111);
3841 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3842 rtl_writephy(tp, 0x13, 0x8113);
3843 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3844 rtl_writephy(tp, 0x13, 0x8115);
3845 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3846 rtl_writephy(tp, 0x13, 0x810e);
3847 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3848 rtl_writephy(tp, 0x13, 0x810c);
3849 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3850 rtl_writephy(tp, 0x13, 0x810b);
3851 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3852 rtl_writephy(tp, 0x1f, 0x0a43);
3853 rtl_writephy(tp, 0x13, 0x80d1);
3854 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3855 rtl_writephy(tp, 0x13, 0x80cd);
3856 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3857 rtl_writephy(tp, 0x13, 0x80d3);
3858 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3859 rtl_writephy(tp, 0x13, 0x80d5);
3860 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3861 rtl_writephy(tp, 0x13, 0x80d7);
3862 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3863
3864 /* Force PWM-mode */
3865 rtl_writephy(tp, 0x1f, 0x0bcd);
3866 rtl_writephy(tp, 0x14, 0x5065);
3867 rtl_writephy(tp, 0x14, 0xd065);
3868 rtl_writephy(tp, 0x1f, 0x0bc8);
3869 rtl_writephy(tp, 0x12, 0x00ed);
3870 rtl_writephy(tp, 0x1f, 0x0bcd);
3871 rtl_writephy(tp, 0x14, 0x1065);
3872 rtl_writephy(tp, 0x14, 0x9065);
3873 rtl_writephy(tp, 0x14, 0x1065);
3874 rtl_writephy(tp, 0x1f, 0x0000);
3875
3876 /* Check ALDPS bit, disable it if enabled */
3877 rtl_writephy(tp, 0x1f, 0x0a43);
3878 if (rtl_readphy(tp, 0x10) & 0x0004)
3879 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3880
3881 rtl_writephy(tp, 0x1f, 0x0000);
3882}
3883
4da19633 3884static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3885{
350f7596 3886 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3887 { 0x1f, 0x0003 },
3888 { 0x08, 0x441d },
3889 { 0x01, 0x9100 },
3890 { 0x1f, 0x0000 }
3891 };
3892
4da19633 3893 rtl_writephy(tp, 0x1f, 0x0000);
3894 rtl_patchphy(tp, 0x11, 1 << 12);
3895 rtl_patchphy(tp, 0x19, 1 << 13);
3896 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3897
4da19633 3898 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3899}
3900
5a5e4443
HW		 3901static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3902{
3903 static const struct phy_reg phy_reg_init[] = {
3904 { 0x1f, 0x0005 },
3905 { 0x1a, 0x0000 },
3906 { 0x1f, 0x0000 },
3907
3908 { 0x1f, 0x0004 },
3909 { 0x1c, 0x0000 },
3910 { 0x1f, 0x0000 },
3911
3912 { 0x1f, 0x0001 },
3913 { 0x15, 0x7701 },
3914 { 0x1f, 0x0000 }
3915 };
3916
3917 /* Disable ALDPS before ram code */
eef63cc1
FR		 3918 rtl_writephy(tp, 0x1f, 0x0000);
3919 rtl_writephy(tp, 0x18, 0x0310);
3920 msleep(100);
5a5e4443 3921
953a12cc 3922 rtl_apply_firmware(tp);
5a5e4443
HW		 3923
3924 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3925}
3926
7e18dca1
HW		 3927static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3928{
7e18dca1 3929 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3930 rtl_writephy(tp, 0x1f, 0x0000);
3931 rtl_writephy(tp, 0x18, 0x0310);
3932 msleep(20);
7e18dca1
HW		 3933
3934 rtl_apply_firmware(tp);
3935
3936 /* EEE setting */
fdf6fc06 3937 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3938 rtl_writephy(tp, 0x1f, 0x0004);
3939 rtl_writephy(tp, 0x10, 0x401f);
3940 rtl_writephy(tp, 0x19, 0x7030);
3941 rtl_writephy(tp, 0x1f, 0x0000);
3942}
3943
5598bfe5
HW		 3944static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3945{
5598bfe5
HW		 3946 static const struct phy_reg phy_reg_init[] = {
3947 { 0x1f, 0x0004 },
3948 { 0x10, 0xc07f },
3949 { 0x19, 0x7030 },
3950 { 0x1f, 0x0000 }
3951 };
3952
3953 /* Disable ALDPS before ram code */
eef63cc1
FR		 3954 rtl_writephy(tp, 0x1f, 0x0000);
3955 rtl_writephy(tp, 0x18, 0x0310);
3956 msleep(100);
5598bfe5
HW		 3957
3958 rtl_apply_firmware(tp);
3959
fdf6fc06 3960 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3961 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3962
fdf6fc06 3963 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3964}
3965
5615d9f1
FR		 3966static void rtl_hw_phy_config(struct net_device *dev)
3967{
3968 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3969
3970 rtl8169_print_mac_version(tp);
3971
3972 switch (tp->mac_version) {
3973 case RTL_GIGA_MAC_VER_01:
3974 break;
3975 case RTL_GIGA_MAC_VER_02:
3976 case RTL_GIGA_MAC_VER_03:
4da19633 3977 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3978 break;
3979 case RTL_GIGA_MAC_VER_04:
4da19633 3980 rtl8169sb_hw_phy_config(tp);
5615d9f1 3981 break;
2e955856 3982 case RTL_GIGA_MAC_VER_05:
4da19633 3983 rtl8169scd_hw_phy_config(tp);
2e955856 3984 break;
8c7006aa 3985 case RTL_GIGA_MAC_VER_06:
4da19633 3986 rtl8169sce_hw_phy_config(tp);
8c7006aa 3987 break;
2857ffb7
FR		 3988 case RTL_GIGA_MAC_VER_07:
3989 case RTL_GIGA_MAC_VER_08:
3990 case RTL_GIGA_MAC_VER_09:
4da19633 3991 rtl8102e_hw_phy_config(tp);
2857ffb7 3992 break;
236b8082 3993 case RTL_GIGA_MAC_VER_11:
4da19633 3994 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3995 break;
3996 case RTL_GIGA_MAC_VER_12:
4da19633 3997 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3998 break;
3999 case RTL_GIGA_MAC_VER_17:
4da19633 4000 rtl8168bef_hw_phy_config(tp);
236b8082 4001 break;
867763c1 4002 case RTL_GIGA_MAC_VER_18:
4da19633 4003 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 4004 break;
4005 case RTL_GIGA_MAC_VER_19:
4da19633 4006 rtl8168c_1_hw_phy_config(tp);
867763c1 4007 break;
7da97ec9 4008 case RTL_GIGA_MAC_VER_20:
4da19633 4009 rtl8168c_2_hw_phy_config(tp);
7da97ec9 4010 break;
197ff761 4011 case RTL_GIGA_MAC_VER_21:
4da19633 4012 rtl8168c_3_hw_phy_config(tp);
197ff761 4013 break;
6fb07058 4014 case RTL_GIGA_MAC_VER_22:
4da19633 4015 rtl8168c_4_hw_phy_config(tp);
6fb07058 4016 break;
ef3386f0 4017 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 4018 case RTL_GIGA_MAC_VER_24:
4da19633 4019 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 4020 break;
5b538df9 4021 case RTL_GIGA_MAC_VER_25:
bca03d5f 4022 rtl8168d_1_hw_phy_config(tp);
daf9df6d 4023 break;
4024 case RTL_GIGA_MAC_VER_26:
bca03d5f 4025 rtl8168d_2_hw_phy_config(tp);
daf9df6d 4026 break;
4027 case RTL_GIGA_MAC_VER_27:
4da19633 4028 rtl8168d_3_hw_phy_config(tp);
5b538df9 4029 break;
e6de30d6 4030 case RTL_GIGA_MAC_VER_28:
4031 rtl8168d_4_hw_phy_config(tp);
4032 break;
5a5e4443
HW		 4033 case RTL_GIGA_MAC_VER_29:
4034 case RTL_GIGA_MAC_VER_30:
4035 rtl8105e_hw_phy_config(tp);
4036 break;
cecb5fd7
FR		 4037 case RTL_GIGA_MAC_VER_31:
4038 /* None. */
4039 break;
01dc7fec 4040 case RTL_GIGA_MAC_VER_32:
01dc7fec 4041 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4042 rtl8168e_1_hw_phy_config(tp);
4043 break;
4044 case RTL_GIGA_MAC_VER_34:
4045 rtl8168e_2_hw_phy_config(tp);
01dc7fec 4046 break;
c2218925
HW		 4047 case RTL_GIGA_MAC_VER_35:
4048 rtl8168f_1_hw_phy_config(tp);
4049 break;
4050 case RTL_GIGA_MAC_VER_36:
4051 rtl8168f_2_hw_phy_config(tp);
4052 break;
ef3386f0 4053
7e18dca1
HW		 4054 case RTL_GIGA_MAC_VER_37:
4055 rtl8402_hw_phy_config(tp);
4056 break;
4057
b3d7b2f2
HW		 4058 case RTL_GIGA_MAC_VER_38:
4059 rtl8411_hw_phy_config(tp);
4060 break;
4061
5598bfe5
HW		 4062 case RTL_GIGA_MAC_VER_39:
4063 rtl8106e_hw_phy_config(tp);
4064 break;
4065
c558386b
HW		 4066 case RTL_GIGA_MAC_VER_40:
4067 rtl8168g_1_hw_phy_config(tp);
4068 break;
57538c4a 4069 case RTL_GIGA_MAC_VER_42:
58152cd4 4070 case RTL_GIGA_MAC_VER_43:
45dd95c4 4071 case RTL_GIGA_MAC_VER_44:
57538c4a 4072 rtl8168g_2_hw_phy_config(tp);
4073 break;
6e1d0b89
CHL		 4074 case RTL_GIGA_MAC_VER_45:
4075 case RTL_GIGA_MAC_VER_47:
4076 rtl8168h_1_hw_phy_config(tp);
4077 break;
4078 case RTL_GIGA_MAC_VER_46:
4079 case RTL_GIGA_MAC_VER_48:
4080 rtl8168h_2_hw_phy_config(tp);
4081 break;
c558386b 4082
935e2218
CHL		 4083 case RTL_GIGA_MAC_VER_49:
4084 rtl8168ep_1_hw_phy_config(tp);
4085 break;
4086 case RTL_GIGA_MAC_VER_50:
4087 case RTL_GIGA_MAC_VER_51:
4088 rtl8168ep_2_hw_phy_config(tp);
4089 break;
4090
c558386b 4091 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 4092 default:
4093 break;
4094 }
4095}
4096
da78dbff
FR		 4097static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4098{
da78dbff
FR		 4099 if (!test_and_set_bit(flag, tp->wk.flags))
4100 schedule_work(&tp->wk.work);
da78dbff
FR		 4101}
4102
2544bfc0
FR		 4103static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4104{
2544bfc0 4105 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
e397286b 4106 (RTL_R8(tp, PHYstatus) & TBI_Enable);
2544bfc0
FR		 4107}
4108
4ff96fa6
FR		 4109static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4110{
5615d9f1 4111 rtl_hw_phy_config(dev);
4ff96fa6 4112
77332894 4113 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
49d17512
HK		 4114 netif_dbg(tp, drv, dev,
4115 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 4116 RTL_W8(tp, 0x82, 0x01);
77332894 4117 }
4ff96fa6 4118
6dccd16b
FR		 4119 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4120
4121 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4122 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4123
bcf0bf90 4124 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
49d17512
HK		 4125 netif_dbg(tp, drv, dev,
4126 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 4127 RTL_W8(tp, 0x82, 0x01);
49d17512
HK		 4128 netif_dbg(tp, drv, dev,
4129 "Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4130 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4131 }
4132
5b7ad4b7
HK		 4133 /* We may have called phy_speed_down before */
4134 phy_speed_up(dev->phydev);
4135
f75222bc 4136 genphy_soft_reset(dev->phydev);
4ff96fa6
FR		 4137}
4138
773d2021
FR		 4139static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4140{
da78dbff 4141 rtl_lock_work(tp);
773d2021 4142
1ef7286e 4143 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
908ba2bf 4144
1ef7286e
AS		 4145 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4146 RTL_R32(tp, MAC4);
908ba2bf 4147
1ef7286e
AS		 4148 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4149 RTL_R32(tp, MAC0);
908ba2bf 4150
9ecb9aab 4151 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4152 rtl_rar_exgmac_set(tp, addr);
c28aa385 4153
1ef7286e 4154 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
773d2021 4155
da78dbff 4156 rtl_unlock_work(tp);
773d2021
FR		 4157}
4158
4159static int rtl_set_mac_address(struct net_device *dev, void *p)
4160{
4161 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 4162 struct device *d = tp_to_dev(tp);
1f7aa2bc 4163 int ret;
773d2021 4164
1f7aa2bc
HK		 4165 ret = eth_mac_addr(dev, p);
4166 if (ret)
4167 return ret;
773d2021 4168
f51d4a10
CHL		 4169 pm_runtime_get_noresume(d);
4170
4171 if (pm_runtime_active(d))
4172 rtl_rar_set(tp, dev->dev_addr);
4173
4174 pm_runtime_put_noidle(d);
773d2021
FR		 4175
4176 return 0;
4177}
4178
e397286b 4179static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8b4ab28d 4180{
69b3c59f
HK		 4181 if (!netif_running(dev))
4182 return -ENODEV;
e397286b 4183
69b3c59f 4184 return phy_mii_ioctl(dev->phydev, ifr, cmd);
8b4ab28d
FR		 4185}
4186
baf63293 4187static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4188{
4189 struct mdio_ops *ops = &tp->mdio_ops;
4190
4191 switch (tp->mac_version) {
4192 case RTL_GIGA_MAC_VER_27:
4193 ops->write = r8168dp_1_mdio_write;
4194 ops->read = r8168dp_1_mdio_read;
4195 break;
e6de30d6 4196 case RTL_GIGA_MAC_VER_28:
4804b3b3 4197 case RTL_GIGA_MAC_VER_31:
e6de30d6 4198 ops->write = r8168dp_2_mdio_write;
4199 ops->read = r8168dp_2_mdio_read;
4200 break;
2a71883c 4201 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
c558386b
HW		 4202 ops->write = r8168g_mdio_write;
4203 ops->read = r8168g_mdio_read;
4204 break;
c0e45c1c 4205 default:
4206 ops->write = r8169_mdio_write;
4207 ops->read = r8169_mdio_read;
4208 break;
4209 }
4210}
4211
649b3b8c 4212static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4213{
649b3b8c 4214 switch (tp->mac_version) {
b00e69de
CB		 4215 case RTL_GIGA_MAC_VER_25:
4216 case RTL_GIGA_MAC_VER_26:
649b3b8c 4217 case RTL_GIGA_MAC_VER_29:
4218 case RTL_GIGA_MAC_VER_30:
4219 case RTL_GIGA_MAC_VER_32:
4220 case RTL_GIGA_MAC_VER_33:
4221 case RTL_GIGA_MAC_VER_34:
2a71883c 4222 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4223 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
649b3b8c 4224 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4225 break;
4226 default:
4227 break;
4228 }
4229}
4230
4231static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4232{
6fcf9b1d 4233 if (!netif_running(tp->dev) || !__rtl8169_get_wol(tp))
649b3b8c 4234 return false;
4235
5b7ad4b7 4236 phy_speed_down(tp->dev->phydev, false);
649b3b8c 4237 rtl_wol_suspend_quirk(tp);
4238
4239 return true;
4240}
4241
065c27c1 4242static void r8168_pll_power_down(struct rtl8169_private *tp)
4243{
9dbe7896 4244 if (r8168_check_dash(tp))
065c27c1 4245 return;
4246
01dc7fec 4247 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4248 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4249 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4250
649b3b8c 4251 if (rtl_wol_pll_power_down(tp))
065c27c1 4252 return;
065c27c1 4253
065c27c1 4254 switch (tp->mac_version) {
2a71883c 4255 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4256 case RTL_GIGA_MAC_VER_37:
4257 case RTL_GIGA_MAC_VER_39:
4258 case RTL_GIGA_MAC_VER_43:
42fde737 4259 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4260 case RTL_GIGA_MAC_VER_45:
4261 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4262 case RTL_GIGA_MAC_VER_47:
4263 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4264 case RTL_GIGA_MAC_VER_50:
4265 case RTL_GIGA_MAC_VER_51:
1ef7286e 4266 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
065c27c1 4267 break;
beb330a4 4268 case RTL_GIGA_MAC_VER_40:
4269 case RTL_GIGA_MAC_VER_41:
935e2218 4270 case RTL_GIGA_MAC_VER_49:
706123d0 4271 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 4272 0xfc000000, ERIAR_EXGMAC);
1ef7286e 4273 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
beb330a4 4274 break;
065c27c1 4275 }
4276}
4277
4278static void r8168_pll_power_up(struct rtl8169_private *tp)
4279{
065c27c1 4280 switch (tp->mac_version) {
2a71883c 4281 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4282 case RTL_GIGA_MAC_VER_37:
4283 case RTL_GIGA_MAC_VER_39:
4284 case RTL_GIGA_MAC_VER_43:
1ef7286e 4285 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
065c27c1 4286 break;
42fde737 4287 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4288 case RTL_GIGA_MAC_VER_45:
4289 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4290 case RTL_GIGA_MAC_VER_47:
4291 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4292 case RTL_GIGA_MAC_VER_50:
4293 case RTL_GIGA_MAC_VER_51:
1ef7286e 4294 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
6e1d0b89 4295 break;
beb330a4 4296 case RTL_GIGA_MAC_VER_40:
4297 case RTL_GIGA_MAC_VER_41:
935e2218 4298 case RTL_GIGA_MAC_VER_49:
1ef7286e 4299 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
706123d0 4300 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 4301 0x00000000, ERIAR_EXGMAC);
4302 break;
065c27c1 4303 }
4304
242cd9b5
HK		 4305 phy_resume(tp->dev->phydev);
4306 /* give MAC/PHY some time to resume */
4307 msleep(20);
065c27c1 4308}
4309
065c27c1 4310static void rtl_pll_power_down(struct rtl8169_private *tp)
4311{
4f447d29
HK		 4312 switch (tp->mac_version) {
4313 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4314 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4315 break;
4316 default:
4317 r8168_pll_power_down(tp);
4318 }
065c27c1 4319}
4320
4321static void rtl_pll_power_up(struct rtl8169_private *tp)
4322{
065c27c1 4323 switch (tp->mac_version) {
4f447d29
HK		 4324 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4325 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
065c27c1 4326 break;
065c27c1 4327 default:
4f447d29 4328 r8168_pll_power_up(tp);
065c27c1 4329 }
4330}
4331
e542a226
HW		 4332static void rtl_init_rxcfg(struct rtl8169_private *tp)
4333{
e542a226 4334 switch (tp->mac_version) {
2a71883c
HK		 4335 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4336 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
1ef7286e 4337 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
e542a226 4338 break;
2a71883c 4339 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
eb2dc35d 4340 case RTL_GIGA_MAC_VER_34:
3ced8c95 4341 case RTL_GIGA_MAC_VER_35:
1ef7286e 4342 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
e542a226 4343 break;
2a71883c 4344 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4345 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 4346 break;
e542a226 4347 default:
1ef7286e 4348 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
e542a226
HW		 4349 break;
4350 }
4351}
4352
92fc43b4
HW		 4353static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4354{
9fba0812 4355 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4356}
4357
d58d46b5
FR		 4358static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4359{
eda40b8c
HK		 4360 if (tp->jumbo_ops.enable) {
4361 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4362 tp->jumbo_ops.enable(tp);
4363 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4364 }
d58d46b5
FR		 4365}
4366
4367static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4368{
eda40b8c
HK		 4369 if (tp->jumbo_ops.disable) {
4370 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4371 tp->jumbo_ops.disable(tp);
4372 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4373 }
d58d46b5
FR		 4374}
4375
4376static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4377{
1ef7286e
AS		 4378 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4379 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
cb73200c 4380 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4381}
4382
4383static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4384{
1ef7286e
AS		 4385 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4386 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
8d98aa39 4387 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4388}
4389
4390static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4391{
1ef7286e 4392 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
d58d46b5
FR		 4393}
4394
4395static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4396{
1ef7286e 4397 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
d58d46b5
FR		 4398}
4399
4400static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4401{
1ef7286e
AS		 4402 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4403 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4404 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
cb73200c 4405 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4406}
4407
4408static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4409{
1ef7286e
AS		 4410 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4411 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4412 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
8d98aa39 4413 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4414}
4415
4416static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4417{
cb73200c 4418 rtl_tx_performance_tweak(tp,
f65d539c 4419 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4420}
4421
4422static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4423{
cb73200c 4424 rtl_tx_performance_tweak(tp,
8d98aa39 4425 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4426}
4427
4428static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4429{
d58d46b5
FR		 4430 r8168b_0_hw_jumbo_enable(tp);
4431
1ef7286e 4432 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
d58d46b5
FR		 4433}
4434
4435static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4436{
d58d46b5
FR		 4437 r8168b_0_hw_jumbo_disable(tp);
4438
1ef7286e 4439 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
d58d46b5
FR		 4440}
4441
baf63293 4442static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4443{
4444 struct jumbo_ops *ops = &tp->jumbo_ops;
4445
4446 switch (tp->mac_version) {
4447 case RTL_GIGA_MAC_VER_11:
4448 ops->disable = r8168b_0_hw_jumbo_disable;
4449 ops->enable = r8168b_0_hw_jumbo_enable;
4450 break;
4451 case RTL_GIGA_MAC_VER_12:
4452 case RTL_GIGA_MAC_VER_17:
4453 ops->disable = r8168b_1_hw_jumbo_disable;
4454 ops->enable = r8168b_1_hw_jumbo_enable;
4455 break;
4456 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4457 case RTL_GIGA_MAC_VER_19:
4458 case RTL_GIGA_MAC_VER_20:
4459 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4460 case RTL_GIGA_MAC_VER_22:
4461 case RTL_GIGA_MAC_VER_23:
4462 case RTL_GIGA_MAC_VER_24:
4463 case RTL_GIGA_MAC_VER_25:
4464 case RTL_GIGA_MAC_VER_26:
4465 ops->disable = r8168c_hw_jumbo_disable;
4466 ops->enable = r8168c_hw_jumbo_enable;
4467 break;
4468 case RTL_GIGA_MAC_VER_27:
4469 case RTL_GIGA_MAC_VER_28:
4470 ops->disable = r8168dp_hw_jumbo_disable;
4471 ops->enable = r8168dp_hw_jumbo_enable;
4472 break;
4473 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4474 case RTL_GIGA_MAC_VER_32:
4475 case RTL_GIGA_MAC_VER_33:
4476 case RTL_GIGA_MAC_VER_34:
4477 ops->disable = r8168e_hw_jumbo_disable;
4478 ops->enable = r8168e_hw_jumbo_enable;
4479 break;
4480
4481 /*
4482 * No action needed for jumbo frames with 8169.
4483 * No jumbo for 810x at all.
4484 */
2a71883c 4485 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 4486 default:
4487 ops->disable = NULL;
4488 ops->enable = NULL;
4489 break;
4490 }
4491}
4492
ffc46952
FR		 4493DECLARE_RTL_COND(rtl_chipcmd_cond)
4494{
1ef7286e 4495 return RTL_R8(tp, ChipCmd) & CmdReset;
ffc46952
FR		 4496}
4497
6f43adc8
FR		 4498static void rtl_hw_reset(struct rtl8169_private *tp)
4499{
1ef7286e 4500 RTL_W8(tp, ChipCmd, CmdReset);
6f43adc8 4501
ffc46952 4502 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4503}
4504
b6ffd97f 4505static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4506{
b6ffd97f
FR		 4507 struct rtl_fw *rtl_fw;
4508 const char *name;
4509 int rc = -ENOMEM;
953a12cc 4510
b6ffd97f
FR		 4511 name = rtl_lookup_firmware_name(tp);
4512 if (!name)
4513 goto out_no_firmware;
953a12cc 4514
b6ffd97f
FR		 4515 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4516 if (!rtl_fw)
4517 goto err_warn;
31bd204f 4518
1e1205b7 4519 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
b6ffd97f
FR		 4520 if (rc < 0)
4521 goto err_free;
4522
fd112f2e
FR		 4523 rc = rtl_check_firmware(tp, rtl_fw);
4524 if (rc < 0)
4525 goto err_release_firmware;
4526
b6ffd97f
FR		 4527 tp->rtl_fw = rtl_fw;
4528out:
4529 return;
4530
fd112f2e
FR		 4531err_release_firmware:
4532 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4533err_free:
4534 kfree(rtl_fw);
4535err_warn:
4536 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4537 name, rc);
4538out_no_firmware:
4539 tp->rtl_fw = NULL;
4540 goto out;
4541}
4542
4543static void rtl_request_firmware(struct rtl8169_private *tp)
4544{
4545 if (IS_ERR(tp->rtl_fw))
4546 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4547}
4548
92fc43b4
HW		 4549static void rtl_rx_close(struct rtl8169_private *tp)
4550{
1ef7286e 4551 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4552}
4553
ffc46952
FR		 4554DECLARE_RTL_COND(rtl_npq_cond)
4555{
1ef7286e 4556 return RTL_R8(tp, TxPoll) & NPQ;
ffc46952
FR		 4557}
4558
4559DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4560{
1ef7286e 4561 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
ffc46952
FR		 4562}
4563
e6de30d6 4564static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4
LT		 4565{
4566 /* Disable interrupts */
811fd301 4567 rtl8169_irq_mask_and_ack(tp);
1da177e4 4568
92fc43b4
HW		 4569 rtl_rx_close(tp);
4570
b2d43e6e
HK		 4571 switch (tp->mac_version) {
4572 case RTL_GIGA_MAC_VER_27:
4573 case RTL_GIGA_MAC_VER_28:
4574 case RTL_GIGA_MAC_VER_31:
ffc46952 4575 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
b2d43e6e
HK		 4576 break;
4577 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4578 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4579 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
ffc46952 4580 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
b2d43e6e
HK		 4581 break;
4582 default:
1ef7286e 4583 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
92fc43b4 4584 udelay(100);
b2d43e6e 4585 break;
e6de30d6 4586 }
4587
92fc43b4 4588 rtl_hw_reset(tp);
1da177e4
LT		 4589}
4590
7f796d83 4591static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6 4592{
9cb427b6 4593 /* Set DMA burst size and Interframe Gap Time */
1ef7286e 4594 RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
9cb427b6
FR		 4595 (InterFrameGap << TxInterFrameGapShift));
4596}
4597
4fd48c4a 4598static void rtl_set_rx_max_size(struct rtl8169_private *tp)
1da177e4 4599{
4fd48c4a
HK		 4600 /* Low hurts. Let's disable the filtering. */
4601 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
07ce4064
FR		 4602}
4603
1ef7286e 4604static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
7f796d83
FR		 4605{
4606 /*
4607 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4608 * register to be written before TxDescAddrLow to work.
4609 * Switching from MMIO to I/O access fixes the issue as well.
4610 */
1ef7286e
AS		 4611 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4612 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4613 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4614 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4615}
4616
1ef7286e 4617static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
6dccd16b 4618{
3744100e 4619 static const struct rtl_cfg2_info {
6dccd16b
FR		 4620 u32 mac_version;
4621 u32 clk;
4622 u32 val;
4623 } cfg2_info [] = {
4624 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4625 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4626 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4627 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4628 };
4629 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4630 unsigned int i;
4631 u32 clk;
4632
1ef7286e 4633 clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
cadf1855 4634 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b 4635 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1ef7286e 4636 RTL_W32(tp, 0x7c, p->val);
6dccd16b
FR		 4637 break;
4638 }
4639 }
4640}
4641
e6b763ea
FR		 4642static void rtl_set_rx_mode(struct net_device *dev)
4643{
4644 struct rtl8169_private *tp = netdev_priv(dev);
e6b763ea
FR		 4645 u32 mc_filter[2]; /* Multicast hash filter */
4646 int rx_mode;
4647 u32 tmp = 0;
4648
4649 if (dev->flags & IFF_PROMISC) {
4650 /* Unconditionally log net taps. */
4651 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4652 rx_mode =
4653 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4654 AcceptAllPhys;
4655 mc_filter[1] = mc_filter[0] = 0xffffffff;
4656 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4657 (dev->flags & IFF_ALLMULTI)) {
4658 /* Too many to filter perfectly -- accept all multicasts. */
4659 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4660 mc_filter[1] = mc_filter[0] = 0xffffffff;
4661 } else {
4662 struct netdev_hw_addr *ha;
4663
4664 rx_mode = AcceptBroadcast | AcceptMyPhys;
4665 mc_filter[1] = mc_filter[0] = 0;
4666 netdev_for_each_mc_addr(ha, dev) {
4667 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4668 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4669 rx_mode |= AcceptMulticast;
4670 }
4671 }
4672
4673 if (dev->features & NETIF_F_RXALL)
4674 rx_mode |= (AcceptErr | AcceptRunt);
4675
1ef7286e 4676 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
e6b763ea
FR		 4677
4678 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4679 u32 data = mc_filter[0];
4680
4681 mc_filter[0] = swab32(mc_filter[1]);
4682 mc_filter[1] = swab32(data);
4683 }
4684
0481776b
NW		 4685 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4686 mc_filter[1] = mc_filter[0] = 0xffffffff;
4687
1ef7286e
AS		 4688 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4689 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
e6b763ea 4690
1ef7286e 4691 RTL_W32(tp, RxConfig, tmp);
e6b763ea
FR		 4692}
4693
52f8560e
HK		 4694static void rtl_hw_start(struct rtl8169_private *tp)
4695{
4696 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4697
4698 tp->hw_start(tp);
4699
4700 rtl_set_rx_max_size(tp);
4701 rtl_set_rx_tx_desc_registers(tp);
4702 rtl_set_rx_tx_config_registers(tp);
4703 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4704
4705 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4706 RTL_R8(tp, IntrMask);
4707 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4708 rtl_set_rx_mode(tp->dev);
4709 /* no early-rx interrupts */
4710 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4711 rtl_irq_enable_all(tp);
4712}
4713
61cb532d 4714static void rtl_hw_start_8169(struct rtl8169_private *tp)
07ce4064 4715{
0ae0974e 4716 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
61cb532d 4717 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
9cb427b6 4718
1ef7286e 4719 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
1da177e4 4720
0ae0974e 4721 tp->cp_cmd |= PCIMulRW;
1da177e4 4722
cecb5fd7
FR		 4723 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4724 tp->mac_version == RTL_GIGA_MAC_VER_03) {
49d17512
HK		 4725 netif_dbg(tp, drv, tp->dev,
4726 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
bcf0bf90 4727 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4728 }
4729
1ef7286e 4730 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
bcf0bf90 4731
1ef7286e 4732 rtl8169_set_magic_reg(tp, tp->mac_version);
6dccd16b 4733
1da177e4
LT		 4734 /*
4735 * Undocumented corner. Supposedly:
4736 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4737 */
1ef7286e 4738 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4 4739
1ef7286e 4740 RTL_W32(tp, RxMissed, 0);
07ce4064 4741}
1da177e4 4742
ffc46952
FR		 4743DECLARE_RTL_COND(rtl_csiar_cond)
4744{
1ef7286e 4745 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
ffc46952
FR		 4746}
4747
ff1d7331 4748static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
beb1fe18 4749{
ff1d7331 4750 u32 func = PCI_FUNC(tp->pci_dev->devfn);
beb1fe18 4751
1ef7286e
AS		 4752 RTL_W32(tp, CSIDR, value);
4753 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
ff1d7331 4754 CSIAR_BYTE_ENABLE | func << 16);
7e18dca1 4755
ffc46952 4756 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4757}
4758
ff1d7331 4759static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4760{
ff1d7331
HK		 4761 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4762
4763 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4764 CSIAR_BYTE_ENABLE);
7e18dca1 4765
ffc46952 4766 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 4767 RTL_R32(tp, CSIDR) : ~0;
7e18dca1
HW		 4768}
4769
ff1d7331 4770static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
45dd95c4 4771{
ff1d7331
HK		 4772 struct pci_dev *pdev = tp->pci_dev;
4773 u32 csi;
45dd95c4 4774
ff1d7331
HK		 4775 /* According to Realtek the value at config space address 0x070f
4776 * controls the L0s/L1 entrance latency. We try standard ECAM access
4777 * first and if it fails fall back to CSI.
4778 */
4779 if (pdev->cfg_size > 0x070f &&
4780 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4781 return;
4782
4783 netdev_notice_once(tp->dev,
4784 "No native access to PCI extended config space, falling back to CSI\n");
4785 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4786 rtl_csi_write(tp, 0x070c, csi | val << 24);
45dd95c4 4787}
4788
f37658da 4789static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
beb1fe18 4790{
ff1d7331 4791 rtl_csi_access_enable(tp, 0x27);
dacf8154
FR		 4792}
4793
4794struct ephy_info {
4795 unsigned int offset;
4796 u16 mask;
4797 u16 bits;
4798};
4799
fdf6fc06
FR		 4800static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4801 int len)
dacf8154
FR		 4802{
4803 u16 w;
4804
4805 while (len-- > 0) {
fdf6fc06
FR		 4806 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4807 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4808 e++;
4809 }
4810}
4811
73c86ee3 4812static void rtl_disable_clock_request(struct rtl8169_private *tp)
b726e493 4813{
73c86ee3 4814 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4815 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4816}
4817
73c86ee3 4818static void rtl_enable_clock_request(struct rtl8169_private *tp)
e6de30d6 4819{
73c86ee3 4820 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4821 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4822}
4823
b51ecea8 4824static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4825{
b51ecea8 4826 u8 data;
4827
1ef7286e 4828 data = RTL_R8(tp, Config3);
b51ecea8 4829
4830 if (enable)
4831 data |= Rdy_to_L23;
4832 else
4833 data &= ~Rdy_to_L23;
4834
1ef7286e 4835 RTL_W8(tp, Config3, data);
b51ecea8 4836}
4837
a99790bf
KHF		 4838static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4839{
4840 if (enable) {
4841 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4842 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4843 } else {
4844 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4845 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4846 }
4847}
4848
beb1fe18 4849static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4850{
1ef7286e 4851 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 4852
12d42c50 4853 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4854 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
b726e493 4855
faf1e785 4856 if (tp->dev->mtu <= ETH_DATA_LEN) {
8d98aa39 4857 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
faf1e785 4858 PCI_EXP_DEVCTL_NOSNOOP_EN);
4859 }
219a1e9d
FR		 4860}
4861
beb1fe18 4862static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4863{
beb1fe18 4864 rtl_hw_start_8168bb(tp);
b726e493 4865
1ef7286e 4866 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
b726e493 4867
1ef7286e 4868 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
219a1e9d
FR		 4869}
4870
beb1fe18 4871static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4872{
1ef7286e 4873 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
b726e493 4874
1ef7286e 4875 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 4876
faf1e785 4877 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4878 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
b726e493 4879
73c86ee3 4880 rtl_disable_clock_request(tp);
b726e493 4881
12d42c50 4882 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4883 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
219a1e9d
FR		 4884}
4885
beb1fe18 4886static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4887{
350f7596 4888 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4889 { 0x01, 0, 0x0001 },
4890 { 0x02, 0x0800, 0x1000 },
4891 { 0x03, 0, 0x0042 },
4892 { 0x06, 0x0080, 0x0000 },
4893 { 0x07, 0, 0x2000 }
4894 };
4895
f37658da 4896 rtl_set_def_aspm_entry_latency(tp);
b726e493 4897
fdf6fc06 4898 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4899
beb1fe18 4900 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4901}
4902
beb1fe18 4903static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4904{
f37658da 4905 rtl_set_def_aspm_entry_latency(tp);
ef3386f0 4906
1ef7286e 4907 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
ef3386f0 4908
faf1e785 4909 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4910 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
ef3386f0 4911
12d42c50 4912 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4913 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
ef3386f0
FR		 4914}
4915
beb1fe18 4916static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4917{
f37658da 4918 rtl_set_def_aspm_entry_latency(tp);
7f3e3d3a 4919
1ef7286e 4920 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
7f3e3d3a
FR		 4921
4922 /* Magic. */
1ef7286e 4923 RTL_W8(tp, DBG_REG, 0x20);
7f3e3d3a 4924
1ef7286e 4925 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
7f3e3d3a 4926
faf1e785 4927 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4928 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7f3e3d3a 4929
12d42c50 4930 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4931 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
7f3e3d3a
FR		 4932}
4933
beb1fe18 4934static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4935{
350f7596 4936 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4937 { 0x02, 0x0800, 0x1000 },
4938 { 0x03, 0, 0x0002 },
4939 { 0x06, 0x0080, 0x0000 }
4940 };
4941
f37658da 4942 rtl_set_def_aspm_entry_latency(tp);
b726e493 4943
1ef7286e 4944 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
b726e493 4945
fdf6fc06 4946 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 4947
beb1fe18 4948 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4949}
4950
beb1fe18 4951static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4952{
350f7596 4953 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4954 { 0x01, 0, 0x0001 },
4955 { 0x03, 0x0400, 0x0220 }
4956 };
4957
f37658da 4958 rtl_set_def_aspm_entry_latency(tp);
b726e493 4959
fdf6fc06 4960 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 4961
beb1fe18 4962 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4963}
4964
beb1fe18 4965static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4966{
beb1fe18 4967 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4968}
4969
beb1fe18 4970static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4971{
f37658da 4972 rtl_set_def_aspm_entry_latency(tp);
6fb07058 4973
beb1fe18 4974 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4975}
4976
beb1fe18 4977static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4978{
f37658da 4979 rtl_set_def_aspm_entry_latency(tp);
5b538df9 4980
73c86ee3 4981 rtl_disable_clock_request(tp);
5b538df9 4982
1ef7286e 4983 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5b538df9 4984
faf1e785 4985 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4986 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5b538df9 4987
12d42c50 4988 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4989 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5b538df9
FR		 4990}
4991
beb1fe18 4992static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4993{
f37658da 4994 rtl_set_def_aspm_entry_latency(tp);
4804b3b3 4995
faf1e785 4996 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4997 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4804b3b3 4998
1ef7286e 4999 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4804b3b3 5000
73c86ee3 5001 rtl_disable_clock_request(tp);
4804b3b3 5002}
5003
beb1fe18 5004static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 5005{
5006 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 5007 { 0x0b, 0x0000, 0x0048 },
5008 { 0x19, 0x0020, 0x0050 },
5009 { 0x0c, 0x0100, 0x0020 }
e6de30d6 5010 };
e6de30d6 5011
f37658da 5012 rtl_set_def_aspm_entry_latency(tp);
e6de30d6 5013
8d98aa39 5014 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
e6de30d6 5015
1ef7286e 5016 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
e6de30d6 5017
1016a4a1 5018 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
e6de30d6 5019
73c86ee3 5020 rtl_enable_clock_request(tp);
e6de30d6 5021}
5022
beb1fe18 5023static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 5024{
70090424 5025 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5026 { 0x00, 0x0200, 0x0100 },
5027 { 0x00, 0x0000, 0x0004 },
5028 { 0x06, 0x0002, 0x0001 },
5029 { 0x06, 0x0000, 0x0030 },
5030 { 0x07, 0x0000, 0x2000 },
5031 { 0x00, 0x0000, 0x0020 },
5032 { 0x03, 0x5800, 0x2000 },
5033 { 0x03, 0x0000, 0x0001 },
5034 { 0x01, 0x0800, 0x1000 },
5035 { 0x07, 0x0000, 0x4000 },
5036 { 0x1e, 0x0000, 0x2000 },
5037 { 0x19, 0xffff, 0xfe6c },
5038 { 0x0a, 0x0000, 0x0040 }
5039 };
5040
f37658da 5041 rtl_set_def_aspm_entry_latency(tp);
01dc7fec 5042
fdf6fc06 5043 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5044
faf1e785 5045 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5046 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
01dc7fec 5047
1ef7286e 5048 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
01dc7fec 5049
73c86ee3 5050 rtl_disable_clock_request(tp);
01dc7fec 5051
5052 /* Reset tx FIFO pointer */
1ef7286e
AS		 5053 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5054 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
01dc7fec 5055
1ef7286e 5056 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
01dc7fec 5057}
5058
beb1fe18 5059static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424
HW		 5060{
5061 static const struct ephy_info e_info_8168e_2[] = {
5062 { 0x09, 0x0000, 0x0080 },
5063 { 0x19, 0x0000, 0x0224 }
5064 };
5065
f37658da 5066 rtl_set_def_aspm_entry_latency(tp);
70090424 5067
fdf6fc06 5068 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5069
faf1e785 5070 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5071 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
70090424 5072
fdf6fc06
FR		 5073 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5074 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5075 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5076 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5077 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5078 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 5079 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5080 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5081
1ef7286e 5082 RTL_W8(tp, MaxTxPacketSize, EarlySize);
70090424 5083
73c86ee3 5084 rtl_disable_clock_request(tp);
4521e1a9 5085
1ef7286e
AS		 5086 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5087 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
70090424
HW		 5088
5089 /* Adjust EEE LED frequency */
1ef7286e 5090 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
70090424 5091
1ef7286e
AS		 5092 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5093 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5094 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
aa1e7d2c
HK		 5095
5096 rtl_hw_aspm_clkreq_enable(tp, true);
70090424
HW		 5097}
5098
5f886e08 5099static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5100{
f37658da 5101 rtl_set_def_aspm_entry_latency(tp);
c2218925 5102
8d98aa39 5103 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c2218925 5104
fdf6fc06
FR		 5105 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5106 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5107 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5108 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 5109 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5110 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5111 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5112 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5113 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5114 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925 5115
1ef7286e 5116 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c2218925 5117
73c86ee3 5118 rtl_disable_clock_request(tp);
4521e1a9 5119
1ef7286e
AS		 5120 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5121 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5122 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5123 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5124 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
c2218925
HW		 5125}
5126
5f886e08
HW		 5127static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5128{
5f886e08
HW		 5129 static const struct ephy_info e_info_8168f_1[] = {
5130 { 0x06, 0x00c0, 0x0020 },
5131 { 0x08, 0x0001, 0x0002 },
5132 { 0x09, 0x0000, 0x0080 },
5133 { 0x19, 0x0000, 0x0224 }
5134 };
5135
5136 rtl_hw_start_8168f(tp);
5137
fdf6fc06 5138 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5139
706123d0 5140 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5141
5142 /* Adjust EEE LED frequency */
1ef7286e 5143 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5f886e08
HW		 5144}
5145
b3d7b2f2
HW		 5146static void rtl_hw_start_8411(struct rtl8169_private *tp)
5147{
b3d7b2f2
HW		 5148 static const struct ephy_info e_info_8168f_1[] = {
5149 { 0x06, 0x00c0, 0x0020 },
5150 { 0x0f, 0xffff, 0x5200 },
5151 { 0x1e, 0x0000, 0x4000 },
5152 { 0x19, 0x0000, 0x0224 }
5153 };
5154
5155 rtl_hw_start_8168f(tp);
b51ecea8 5156 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 5157
fdf6fc06 5158 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5159
706123d0 5160 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5161}
5162
5fbea337 5163static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b 5164{
1ef7286e 5165 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
beb330a4 5166
c558386b
HW		 5167 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5168 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5169 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5170 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5171
f37658da 5172 rtl_set_def_aspm_entry_latency(tp);
c558386b 5173
8d98aa39 5174 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c558386b 5175
706123d0
CHL		 5176 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5177 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5178 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 5179
1ef7286e
AS		 5180 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5181 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c558386b
HW		 5182
5183 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5184 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5185
5186 /* Adjust EEE LED frequency */
1ef7286e 5187 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
c558386b 5188
706123d0
CHL		 5189 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5190 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 5191
5192 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 5193}
5194
5fbea337
CHL		 5195static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5196{
5fbea337
CHL		 5197 static const struct ephy_info e_info_8168g_1[] = {
5198 { 0x00, 0x0000, 0x0008 },
5199 { 0x0c, 0x37d0, 0x0820 },
5200 { 0x1e, 0x0000, 0x0001 },
5201 { 0x19, 0x8000, 0x0000 }
5202 };
5203
5204 rtl_hw_start_8168g(tp);
5205
5206 /* disable aspm and clock request before access ephy */
a99790bf 5207 rtl_hw_aspm_clkreq_enable(tp, false);
5fbea337 5208 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
a99790bf 5209 rtl_hw_aspm_clkreq_enable(tp, true);
5fbea337
CHL		 5210}
5211
57538c4a 5212static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5213{
57538c4a 5214 static const struct ephy_info e_info_8168g_2[] = {
5215 { 0x00, 0x0000, 0x0008 },
5216 { 0x0c, 0x3df0, 0x0200 },
5217 { 0x19, 0xffff, 0xfc00 },
5218 { 0x1e, 0xffff, 0x20eb }
5219 };
5220
5fbea337 5221 rtl_hw_start_8168g(tp);
57538c4a 5222
5223 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 5224 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5225 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
57538c4a 5226 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5227}
5228
45dd95c4 5229static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5230{
45dd95c4 5231 static const struct ephy_info e_info_8411_2[] = {
5232 { 0x00, 0x0000, 0x0008 },
5233 { 0x0c, 0x3df0, 0x0200 },
5234 { 0x0f, 0xffff, 0x5200 },
5235 { 0x19, 0x0020, 0x0000 },
5236 { 0x1e, 0x0000, 0x2000 }
5237 };
5238
5fbea337 5239 rtl_hw_start_8168g(tp);
45dd95c4 5240
5241 /* disable aspm and clock request before access ephy */
a99790bf 5242 rtl_hw_aspm_clkreq_enable(tp, false);
45dd95c4 5243 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
a99790bf 5244 rtl_hw_aspm_clkreq_enable(tp, true);
45dd95c4 5245}
5246
6e1d0b89
CHL		 5247static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5248{
72521ea0 5249 int rg_saw_cnt;
6e1d0b89
CHL		 5250 u32 data;
5251 static const struct ephy_info e_info_8168h_1[] = {
5252 { 0x1e, 0x0800, 0x0001 },
5253 { 0x1d, 0x0000, 0x0800 },
5254 { 0x05, 0xffff, 0x2089 },
5255 { 0x06, 0xffff, 0x5881 },
5256 { 0x04, 0xffff, 0x154a },
5257 { 0x01, 0xffff, 0x068b }
5258 };
5259
5260 /* disable aspm and clock request before access ephy */
a99790bf 5261 rtl_hw_aspm_clkreq_enable(tp, false);
6e1d0b89
CHL		 5262 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5263
1ef7286e 5264 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6e1d0b89
CHL		 5265
5266 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5267 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5268 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5269 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5270
f37658da 5271 rtl_set_def_aspm_entry_latency(tp);
6e1d0b89 5272
8d98aa39 5273 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6e1d0b89 5274
706123d0
CHL		 5275 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5276 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 5277
706123d0 5278 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 5279
706123d0 5280 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 5281
5282 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5283
1ef7286e
AS		 5284 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5285 RTL_W8(tp, MaxTxPacketSize, EarlySize);
6e1d0b89
CHL		 5286
5287 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5288 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5289
5290 /* Adjust EEE LED frequency */
1ef7286e 5291 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6e1d0b89 5292
1ef7286e
AS		 5293 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5294 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89 5295
1ef7286e 5296 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6e1d0b89 5297
706123d0 5298 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 5299
5300 rtl_pcie_state_l2l3_enable(tp, false);
5301
5302 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 5303 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 5304 rtl_writephy(tp, 0x1f, 0x0000);
5305 if (rg_saw_cnt > 0) {
5306 u16 sw_cnt_1ms_ini;
5307
5308 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5309 sw_cnt_1ms_ini &= 0x0fff;
5310 data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec0 5311 data &= ~0x0fff;
6e1d0b89
CHL		 5312 data |= sw_cnt_1ms_ini;
5313 r8168_mac_ocp_write(tp, 0xd412, data);
5314 }
5315
5316 data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec0
CHL		 5317 data &= ~0xf0;
5318 data |= 0x70;
6e1d0b89
CHL		 5319 r8168_mac_ocp_write(tp, 0xe056, data);
5320
5321 data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec0
CHL		 5322 data &= ~0x6000;
5323 data |= 0x8008;
6e1d0b89
CHL		 5324 r8168_mac_ocp_write(tp, 0xe052, data);
5325
5326 data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec0 5327 data &= ~0x01ff;
6e1d0b89
CHL		 5328 data |= 0x017f;
5329 r8168_mac_ocp_write(tp, 0xe0d6, data);
5330
5331 data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec0 5332 data &= ~0x0fff;
6e1d0b89
CHL		 5333 data |= 0x047f;
5334 r8168_mac_ocp_write(tp, 0xd420, data);
5335
5336 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5337 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5338 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5339 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
a99790bf
KHF		 5340
5341 rtl_hw_aspm_clkreq_enable(tp, true);
6e1d0b89
CHL		 5342}
5343
935e2218
CHL		 5344static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5345{
003609da
CHL		 5346 rtl8168ep_stop_cmac(tp);
5347
1ef7286e 5348 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
935e2218
CHL		 5349
5350 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5351 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5352 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5353 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5354
f37658da 5355 rtl_set_def_aspm_entry_latency(tp);
935e2218 5356
8d98aa39 5357 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
935e2218
CHL		 5358
5359 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5360 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5361
5362 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5363
5364 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5365
1ef7286e
AS		 5366 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5367 RTL_W8(tp, MaxTxPacketSize, EarlySize);
935e2218
CHL		 5368
5369 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5370 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5371
5372 /* Adjust EEE LED frequency */
1ef7286e 5373 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
935e2218
CHL		 5374
5375 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5376
1ef7286e 5377 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
935e2218
CHL		 5378
5379 rtl_pcie_state_l2l3_enable(tp, false);
5380}
5381
5382static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5383{
935e2218
CHL		 5384 static const struct ephy_info e_info_8168ep_1[] = {
5385 { 0x00, 0xffff, 0x10ab },
5386 { 0x06, 0xffff, 0xf030 },
5387 { 0x08, 0xffff, 0x2006 },
5388 { 0x0d, 0xffff, 0x1666 },
5389 { 0x0c, 0x3ff0, 0x0000 }
5390 };
5391
5392 /* disable aspm and clock request before access ephy */
a99790bf 5393 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5394 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5395
5396 rtl_hw_start_8168ep(tp);
a99790bf
KHF		 5397
5398 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5399}
5400
5401static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5402{
935e2218
CHL		 5403 static const struct ephy_info e_info_8168ep_2[] = {
5404 { 0x00, 0xffff, 0x10a3 },
5405 { 0x19, 0xffff, 0xfc00 },
5406 { 0x1e, 0xffff, 0x20ea }
5407 };
5408
5409 /* disable aspm and clock request before access ephy */
a99790bf 5410 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5411 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5412
5413 rtl_hw_start_8168ep(tp);
5414
1ef7286e
AS		 5415 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5416 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
a99790bf
KHF		 5417
5418 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5419}
5420
5421static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5422{
935e2218
CHL		 5423 u32 data;
5424 static const struct ephy_info e_info_8168ep_3[] = {
5425 { 0x00, 0xffff, 0x10a3 },
5426 { 0x19, 0xffff, 0x7c00 },
5427 { 0x1e, 0xffff, 0x20eb },
5428 { 0x0d, 0xffff, 0x1666 }
5429 };
5430
5431 /* disable aspm and clock request before access ephy */
a99790bf 5432 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5433 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5434
5435 rtl_hw_start_8168ep(tp);
5436
1ef7286e
AS		 5437 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5438 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 5439
5440 data = r8168_mac_ocp_read(tp, 0xd3e2);
5441 data &= 0xf000;
5442 data |= 0x0271;
5443 r8168_mac_ocp_write(tp, 0xd3e2, data);
5444
5445 data = r8168_mac_ocp_read(tp, 0xd3e4);
5446 data &= 0xff00;
5447 r8168_mac_ocp_write(tp, 0xd3e4, data);
5448
5449 data = r8168_mac_ocp_read(tp, 0xe860);
5450 data |= 0x0080;
5451 r8168_mac_ocp_write(tp, 0xe860, data);
a99790bf
KHF		 5452
5453 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5454}
5455
61cb532d 5456static void rtl_hw_start_8168(struct rtl8169_private *tp)
07ce4064 5457{
1ef7286e 5458 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
2dd99530 5459
0ae0974e
HK		 5460 tp->cp_cmd &= ~INTT_MASK;
5461 tp->cp_cmd |= PktCntrDisable | INTT_1;
1ef7286e 5462 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2dd99530 5463
1ef7286e 5464 RTL_W16(tp, IntrMitigate, 0x5151);
2dd99530 5465
0e485150 5466 /* Work around for RxFIFO overflow. */
811fd301 5467 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5468 tp->event_slow |= RxFIFOOver | PCSTimeout;
5469 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5470 }
5471
219a1e9d
FR		 5472 switch (tp->mac_version) {
5473 case RTL_GIGA_MAC_VER_11:
beb1fe18 5474 rtl_hw_start_8168bb(tp);
4804b3b3 5475 break;
219a1e9d
FR		 5476
5477 case RTL_GIGA_MAC_VER_12:
5478 case RTL_GIGA_MAC_VER_17:
beb1fe18 5479 rtl_hw_start_8168bef(tp);
4804b3b3 5480 break;
219a1e9d
FR		 5481
5482 case RTL_GIGA_MAC_VER_18:
beb1fe18 5483 rtl_hw_start_8168cp_1(tp);
4804b3b3 5484 break;
219a1e9d
FR		 5485
5486 case RTL_GIGA_MAC_VER_19:
beb1fe18 5487 rtl_hw_start_8168c_1(tp);
4804b3b3 5488 break;
219a1e9d
FR		 5489
5490 case RTL_GIGA_MAC_VER_20:
beb1fe18 5491 rtl_hw_start_8168c_2(tp);
4804b3b3 5492 break;
219a1e9d 5493
197ff761 5494 case RTL_GIGA_MAC_VER_21:
beb1fe18 5495 rtl_hw_start_8168c_3(tp);
4804b3b3 5496 break;
197ff761 5497
6fb07058 5498 case RTL_GIGA_MAC_VER_22:
beb1fe18 5499 rtl_hw_start_8168c_4(tp);
4804b3b3 5500 break;
6fb07058 5501
ef3386f0 5502 case RTL_GIGA_MAC_VER_23:
beb1fe18 5503 rtl_hw_start_8168cp_2(tp);
4804b3b3 5504 break;
ef3386f0 5505
7f3e3d3a 5506 case RTL_GIGA_MAC_VER_24:
beb1fe18 5507 rtl_hw_start_8168cp_3(tp);
4804b3b3 5508 break;
7f3e3d3a 5509
5b538df9 5510 case RTL_GIGA_MAC_VER_25:
daf9df6d 5511 case RTL_GIGA_MAC_VER_26:
5512 case RTL_GIGA_MAC_VER_27:
beb1fe18 5513 rtl_hw_start_8168d(tp);
4804b3b3 5514 break;
5b538df9 5515
e6de30d6 5516 case RTL_GIGA_MAC_VER_28:
beb1fe18 5517 rtl_hw_start_8168d_4(tp);
4804b3b3 5518 break;
cecb5fd7 5519
4804b3b3 5520 case RTL_GIGA_MAC_VER_31:
beb1fe18 5521 rtl_hw_start_8168dp(tp);
4804b3b3 5522 break;
5523
01dc7fec 5524 case RTL_GIGA_MAC_VER_32:
5525 case RTL_GIGA_MAC_VER_33:
beb1fe18 5526 rtl_hw_start_8168e_1(tp);
70090424
HW		 5527 break;
5528 case RTL_GIGA_MAC_VER_34:
beb1fe18 5529 rtl_hw_start_8168e_2(tp);
01dc7fec 5530 break;
e6de30d6 5531
c2218925
HW		 5532 case RTL_GIGA_MAC_VER_35:
5533 case RTL_GIGA_MAC_VER_36:
beb1fe18 5534 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5535 break;
5536
b3d7b2f2
HW		 5537 case RTL_GIGA_MAC_VER_38:
5538 rtl_hw_start_8411(tp);
5539 break;
5540
c558386b
HW		 5541 case RTL_GIGA_MAC_VER_40:
5542 case RTL_GIGA_MAC_VER_41:
5543 rtl_hw_start_8168g_1(tp);
5544 break;
57538c4a 5545 case RTL_GIGA_MAC_VER_42:
5546 rtl_hw_start_8168g_2(tp);
5547 break;
c558386b 5548
45dd95c4 5549 case RTL_GIGA_MAC_VER_44:
5550 rtl_hw_start_8411_2(tp);
5551 break;
5552
6e1d0b89
CHL		 5553 case RTL_GIGA_MAC_VER_45:
5554 case RTL_GIGA_MAC_VER_46:
5555 rtl_hw_start_8168h_1(tp);
5556 break;
5557
935e2218
CHL		 5558 case RTL_GIGA_MAC_VER_49:
5559 rtl_hw_start_8168ep_1(tp);
5560 break;
5561
5562 case RTL_GIGA_MAC_VER_50:
5563 rtl_hw_start_8168ep_2(tp);
5564 break;
5565
5566 case RTL_GIGA_MAC_VER_51:
5567 rtl_hw_start_8168ep_3(tp);
5568 break;
5569
219a1e9d 5570 default:
49d17512
HK		 5571 netif_err(tp, drv, tp->dev,
5572 "unknown chipset (mac_version = %d)\n",
5573 tp->mac_version);
4804b3b3 5574 break;
219a1e9d 5575 }
07ce4064 5576}
1da177e4 5577
beb1fe18 5578static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5579{
350f7596 5580 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5581 { 0x01, 0, 0x6e65 },
5582 { 0x02, 0, 0x091f },
5583 { 0x03, 0, 0xc2f9 },
5584 { 0x06, 0, 0xafb5 },
5585 { 0x07, 0, 0x0e00 },
5586 { 0x19, 0, 0xec80 },
5587 { 0x01, 0, 0x2e65 },
5588 { 0x01, 0, 0x6e65 }
5589 };
5590 u8 cfg1;
5591
f37658da 5592 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5593
1ef7286e 5594 RTL_W8(tp, DBG_REG, FIX_NAK_1);
2857ffb7 5595
8d98aa39 5596 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 5597
1ef7286e 5598 RTL_W8(tp, Config1,
2857ffb7 5599 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
1ef7286e 5600 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7 5601
1ef7286e 5602 cfg1 = RTL_R8(tp, Config1);
2857ffb7 5603 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
1ef7286e 5604 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
2857ffb7 5605
fdf6fc06 5606 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5607}
5608
beb1fe18 5609static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5610{
f37658da 5611 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5612
8d98aa39 5613 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 5614
1ef7286e
AS		 5615 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5616 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7
FR		 5617}
5618
beb1fe18 5619static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5620{
beb1fe18 5621 rtl_hw_start_8102e_2(tp);
2857ffb7 5622
fdf6fc06 5623 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5624}
5625
beb1fe18 5626static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443
HW		 5627{
5628 static const struct ephy_info e_info_8105e_1[] = {
5629 { 0x07, 0, 0x4000 },
5630 { 0x19, 0, 0x0200 },
5631 { 0x19, 0, 0x0020 },
5632 { 0x1e, 0, 0x2000 },
5633 { 0x03, 0, 0x0001 },
5634 { 0x19, 0, 0x0100 },
5635 { 0x19, 0, 0x0004 },
5636 { 0x0a, 0, 0x0020 }
5637 };
5638
cecb5fd7 5639 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5640 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5a5e4443 5641
cecb5fd7 5642 /* Disable Early Tally Counter */
1ef7286e 5643 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5a5e4443 5644
1ef7286e
AS		 5645 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5646 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5a5e4443 5647
fdf6fc06 5648 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 5649
5650 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 5651}
5652
beb1fe18 5653static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5654{
beb1fe18 5655 rtl_hw_start_8105e_1(tp);
fdf6fc06 5656 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5657}
5658
7e18dca1
HW		 5659static void rtl_hw_start_8402(struct rtl8169_private *tp)
5660{
7e18dca1
HW		 5661 static const struct ephy_info e_info_8402[] = {
5662 { 0x19, 0xffff, 0xff64 },
5663 { 0x1e, 0, 0x4000 }
5664 };
5665
f37658da 5666 rtl_set_def_aspm_entry_latency(tp);
7e18dca1
HW		 5667
5668 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5669 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
7e18dca1 5670
1ef7286e
AS		 5671 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5672 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7e18dca1 5673
fdf6fc06 5674 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1 5675
8d98aa39 5676 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7e18dca1 5677
fdf6fc06
FR		 5678 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5679 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 5680 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5681 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5682 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5683 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 5684 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 5685
5686 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 5687}
5688
5598bfe5
HW		 5689static void rtl_hw_start_8106(struct rtl8169_private *tp)
5690{
5598bfe5 5691 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5692 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5598bfe5 5693
1ef7286e
AS		 5694 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5695 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5696 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
b51ecea8 5697
5698 rtl_pcie_state_l2l3_enable(tp, false);
5598bfe5
HW		 5699}
5700
61cb532d 5701static void rtl_hw_start_8101(struct rtl8169_private *tp)
07ce4064 5702{
da78dbff
FR		 5703 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5704 tp->event_slow &= ~RxFIFOOver;
811fd301 5705
cecb5fd7 5706 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5707 tp->mac_version == RTL_GIGA_MAC_VER_16)
61cb532d 5708 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
8200bc72 5709 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5710
1ef7286e 5711 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
1a964649 5712
12d42c50 5713 tp->cp_cmd &= CPCMD_QUIRK_MASK;
1ef7286e 5714 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1a964649 5715
2857ffb7
FR		 5716 switch (tp->mac_version) {
5717 case RTL_GIGA_MAC_VER_07:
beb1fe18 5718 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5719 break;
5720
5721 case RTL_GIGA_MAC_VER_08:
beb1fe18 5722 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5723 break;
5724
5725 case RTL_GIGA_MAC_VER_09:
beb1fe18 5726 rtl_hw_start_8102e_2(tp);
2857ffb7 5727 break;
5a5e4443
HW		 5728
5729 case RTL_GIGA_MAC_VER_29:
beb1fe18 5730 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5731 break;
5732 case RTL_GIGA_MAC_VER_30:
beb1fe18 5733 rtl_hw_start_8105e_2(tp);
5a5e4443 5734 break;
7e18dca1
HW		 5735
5736 case RTL_GIGA_MAC_VER_37:
5737 rtl_hw_start_8402(tp);
5738 break;
5598bfe5
HW		 5739
5740 case RTL_GIGA_MAC_VER_39:
5741 rtl_hw_start_8106(tp);
5742 break;
58152cd4 5743 case RTL_GIGA_MAC_VER_43:
5744 rtl_hw_start_8168g_2(tp);
5745 break;
6e1d0b89
CHL		 5746 case RTL_GIGA_MAC_VER_47:
5747 case RTL_GIGA_MAC_VER_48:
5748 rtl_hw_start_8168h_1(tp);
5749 break;
cdf1a608
FR		 5750 }
5751
1ef7286e 5752 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4
LT		 5753}
5754
5755static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5756{
d58d46b5
FR		 5757 struct rtl8169_private *tp = netdev_priv(dev);
5758
d58d46b5
FR		 5759 if (new_mtu > ETH_DATA_LEN)
5760 rtl_hw_jumbo_enable(tp);
5761 else
5762 rtl_hw_jumbo_disable(tp);
5763
1da177e4 5764 dev->mtu = new_mtu;
350fb32a
MM		 5765 netdev_update_features(dev);
5766
323bb685 5767 return 0;
1da177e4
LT		 5768}
5769
5770static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5771{
95e0918d 5772 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5773 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5774}
5775
6f0333b8
ED		 5776static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5777 void **data_buff, struct RxDesc *desc)
1da177e4 5778{
1d0254dd
HK		 5779 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5780 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
48addcc9 5781
6f0333b8
ED		 5782 kfree(*data_buff);
5783 *data_buff = NULL;
1da177e4
LT		 5784 rtl8169_make_unusable_by_asic(desc);
5785}
5786
1d0254dd 5787static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
1da177e4
LT		 5788{
5789 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5790
a0750138
AD		 5791 /* Force memory writes to complete before releasing descriptor */
5792 dma_wmb();
5793
1d0254dd 5794 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
1da177e4
LT		 5795}
5796
6f0333b8
ED		 5797static inline void *rtl8169_align(void *data)
5798{
5799 return (void *)ALIGN((long)data, 16);
5800}
5801
0ecbe1ca
SG		 5802static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5803 struct RxDesc *desc)
1da177e4 5804{
6f0333b8 5805 void *data;
1da177e4 5806 dma_addr_t mapping;
1e1205b7 5807 struct device *d = tp_to_dev(tp);
d3b404c2 5808 int node = dev_to_node(d);
1da177e4 5809
1d0254dd 5810 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
6f0333b8
ED		 5811 if (!data)
5812 return NULL;
e9f63f30 5813
6f0333b8
ED		 5814 if (rtl8169_align(data) != data) {
5815 kfree(data);
1d0254dd 5816 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
6f0333b8
ED		 5817 if (!data)
5818 return NULL;
5819 }
3eafe507 5820
1d0254dd 5821 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
231aee63 5822 DMA_FROM_DEVICE);
d827d86b
SG		 5823 if (unlikely(dma_mapping_error(d, mapping))) {
5824 if (net_ratelimit())
5825 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5826 goto err_out;
d827d86b 5827 }
1da177e4 5828
d731af78
HK		 5829 desc->addr = cpu_to_le64(mapping);
5830 rtl8169_mark_to_asic(desc);
6f0333b8 5831 return data;
3eafe507
SG		 5832
5833err_out:
5834 kfree(data);
5835 return NULL;
1da177e4
LT		 5836}
5837
5838static void rtl8169_rx_clear(struct rtl8169_private *tp)
5839{
07d3f51f 5840 unsigned int i;
1da177e4
LT		 5841
5842 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5843 if (tp->Rx_databuff[i]) {
5844 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5845 tp->RxDescArray + i);
5846 }
5847 }
5848}
5849
0ecbe1ca 5850static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5851{
0ecbe1ca
SG		 5852 desc->opts1 |= cpu_to_le32(RingEnd);
5853}
5b0384f4 5854
0ecbe1ca
SG		 5855static int rtl8169_rx_fill(struct rtl8169_private *tp)
5856{
5857 unsigned int i;
1da177e4 5858
0ecbe1ca
SG		 5859 for (i = 0; i < NUM_RX_DESC; i++) {
5860 void *data;
4ae47c2d 5861
0ecbe1ca 5862 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5863 if (!data) {
5864 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5865 goto err_out;
6f0333b8
ED		 5866 }
5867 tp->Rx_databuff[i] = data;
1da177e4 5868 }
1da177e4 5869
0ecbe1ca
SG		 5870 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5871 return 0;
5872
5873err_out:
5874 rtl8169_rx_clear(tp);
5875 return -ENOMEM;
1da177e4
LT		 5876}
5877
b1127e64 5878static int rtl8169_init_ring(struct rtl8169_private *tp)
1da177e4 5879{
1da177e4
LT		 5880 rtl8169_init_ring_indexes(tp);
5881
b1127e64
HK		 5882 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5883 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
1da177e4 5884
0ecbe1ca 5885 return rtl8169_rx_fill(tp);
1da177e4
LT		 5886}
5887
48addcc9 5888static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5889 struct TxDesc *desc)
5890{
5891 unsigned int len = tx_skb->len;
5892
48addcc9
SG		 5893 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5894
1da177e4
LT		 5895 desc->opts1 = 0x00;
5896 desc->opts2 = 0x00;
5897 desc->addr = 0x00;
5898 tx_skb->len = 0;
5899}
5900
3eafe507
SG		 5901static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5902 unsigned int n)
1da177e4
LT		 5903{
5904 unsigned int i;
5905
3eafe507
SG		 5906 for (i = 0; i < n; i++) {
5907 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5908 struct ring_info *tx_skb = tp->tx_skb + entry;
5909 unsigned int len = tx_skb->len;
5910
5911 if (len) {
5912 struct sk_buff *skb = tx_skb->skb;
5913
1e1205b7 5914 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
1da177e4
LT		 5915 tp->TxDescArray + entry);
5916 if (skb) {
7a4b813c 5917 dev_consume_skb_any(skb);
1da177e4
LT		 5918 tx_skb->skb = NULL;
5919 }
1da177e4
LT		 5920 }
5921 }
3eafe507
SG		 5922}
5923
5924static void rtl8169_tx_clear(struct rtl8169_private *tp)
5925{
5926 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5927 tp->cur_tx = tp->dirty_tx = 0;
5928}
5929
4422bcd4 5930static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5931{
c4028958 5932 struct net_device *dev = tp->dev;
56de414c 5933 int i;
1da177e4 5934
da78dbff
FR		 5935 napi_disable(&tp->napi);
5936 netif_stop_queue(dev);
5937 synchronize_sched();
1da177e4 5938
c7c2c39b 5939 rtl8169_hw_reset(tp);
5940
56de414c 5941 for (i = 0; i < NUM_RX_DESC; i++)
1d0254dd 5942 rtl8169_mark_to_asic(tp->RxDescArray + i);
56de414c 5943
1da177e4 5944 rtl8169_tx_clear(tp);
c7c2c39b 5945 rtl8169_init_ring_indexes(tp);
1da177e4 5946
da78dbff 5947 napi_enable(&tp->napi);
61cb532d 5948 rtl_hw_start(tp);
56de414c 5949 netif_wake_queue(dev);
1da177e4
LT		 5950}
5951
5952static void rtl8169_tx_timeout(struct net_device *dev)
5953{
da78dbff
FR		 5954 struct rtl8169_private *tp = netdev_priv(dev);
5955
5956 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5957}
5958
5959static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5960 u32 *opts)
1da177e4
LT		 5961{
5962 struct skb_shared_info *info = skb_shinfo(skb);
5963 unsigned int cur_frag, entry;
6e1d0b89 5964 struct TxDesc *uninitialized_var(txd);
1e1205b7 5965 struct device *d = tp_to_dev(tp);
1da177e4
LT		 5966
5967 entry = tp->cur_tx;
5968 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5969 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5970 dma_addr_t mapping;
5971 u32 status, len;
5972 void *addr;
5973
5974 entry = (entry + 1) % NUM_TX_DESC;
5975
5976 txd = tp->TxDescArray + entry;
9e903e08 5977 len = skb_frag_size(frag);
929f6189 5978 addr = skb_frag_address(frag);
48addcc9 5979 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5980 if (unlikely(dma_mapping_error(d, mapping))) {
5981 if (net_ratelimit())
5982 netif_err(tp, drv, tp->dev,
5983 "Failed to map TX fragments DMA!\n");
3eafe507 5984 goto err_out;
d827d86b 5985 }
1da177e4 5986
cecb5fd7 5987 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5988 status = opts[0] | len |
5989 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5990
5991 txd->opts1 = cpu_to_le32(status);
2b7b4318 5992 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5993 txd->addr = cpu_to_le64(mapping);
5994
5995 tp->tx_skb[entry].len = len;
5996 }
5997
5998 if (cur_frag) {
5999 tp->tx_skb[entry].skb = skb;
6000 txd->opts1 |= cpu_to_le32(LastFrag);
6001 }
6002
6003 return cur_frag;
3eafe507
SG		 6004
6005err_out:
6006 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6007 return -EIO;
1da177e4
LT		 6008}
6009
b423e9ae 6010static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6011{
6012 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6013}
6014
e974604b 6015static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6016 struct net_device *dev);
6017/* r8169_csum_workaround()
6018 * The hw limites the value the transport offset. When the offset is out of the
6019 * range, calculate the checksum by sw.
6020 */
6021static void r8169_csum_workaround(struct rtl8169_private *tp,
6022 struct sk_buff *skb)
6023{
6024 if (skb_shinfo(skb)->gso_size) {
6025 netdev_features_t features = tp->dev->features;
6026 struct sk_buff *segs, *nskb;
6027
6028 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6029 segs = skb_gso_segment(skb, features);
6030 if (IS_ERR(segs) || !segs)
6031 goto drop;
6032
6033 do {
6034 nskb = segs;
6035 segs = segs->next;
6036 nskb->next = NULL;
6037 rtl8169_start_xmit(nskb, tp->dev);
6038 } while (segs);
6039
eb781397 6040 dev_consume_skb_any(skb);
e974604b 6041 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6042 if (skb_checksum_help(skb) < 0)
6043 goto drop;
6044
6045 rtl8169_start_xmit(skb, tp->dev);
6046 } else {
6047 struct net_device_stats *stats;
6048
6049drop:
6050 stats = &tp->dev->stats;
6051 stats->tx_dropped++;
eb781397 6052 dev_kfree_skb_any(skb);
e974604b 6053 }
6054}
6055
6056/* msdn_giant_send_check()
6057 * According to the document of microsoft, the TCP Pseudo Header excludes the
6058 * packet length for IPv6 TCP large packets.
6059 */
6060static int msdn_giant_send_check(struct sk_buff *skb)
6061{
6062 const struct ipv6hdr *ipv6h;
6063 struct tcphdr *th;
6064 int ret;
6065
6066 ret = skb_cow_head(skb, 0);
6067 if (ret)
6068 return ret;
6069
6070 ipv6h = ipv6_hdr(skb);
6071 th = tcp_hdr(skb);
6072
6073 th->check = 0;
6074 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6075
6076 return ret;
6077}
6078
5888d3fc 6079static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6080 struct sk_buff *skb, u32 *opts)
1da177e4 6081{
350fb32a
MM		 6082 u32 mss = skb_shinfo(skb)->gso_size;
6083
2b7b4318
FR		 6084 if (mss) {
6085 opts[0] |= TD_LSO;
5888d3fc 6086 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6087 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6088 const struct iphdr *ip = ip_hdr(skb);
6089
6090 if (ip->protocol == IPPROTO_TCP)
6091 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6092 else if (ip->protocol == IPPROTO_UDP)
6093 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6094 else
6095 WARN_ON_ONCE(1);
6096 }
6097
6098 return true;
6099}
6100
6101static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6102 struct sk_buff *skb, u32 *opts)
6103{
bdfa4ed6 6104 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 6105 u32 mss = skb_shinfo(skb)->gso_size;
6106
6107 if (mss) {
e974604b 6108 if (transport_offset > GTTCPHO_MAX) {
6109 netif_warn(tp, tx_err, tp->dev,
6110 "Invalid transport offset 0x%x for TSO\n",
6111 transport_offset);
6112 return false;
6113 }
6114
4ff36466 6115 switch (vlan_get_protocol(skb)) {
e974604b 6116 case htons(ETH_P_IP):
6117 opts[0] |= TD1_GTSENV4;
6118 break;
6119
6120 case htons(ETH_P_IPV6):
6121 if (msdn_giant_send_check(skb))
6122 return false;
6123
6124 opts[0] |= TD1_GTSENV6;
6125 break;
6126
6127 default:
6128 WARN_ON_ONCE(1);
6129 break;
6130 }
6131
bdfa4ed6 6132 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 6133 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 6134 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 6135 u8 ip_protocol;
1da177e4 6136
b423e9ae 6137 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6138 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
b423e9ae 6139
e974604b 6140 if (transport_offset > TCPHO_MAX) {
6141 netif_warn(tp, tx_err, tp->dev,
6142 "Invalid transport offset 0x%x\n",
6143 transport_offset);
6144 return false;
6145 }
6146
4ff36466 6147 switch (vlan_get_protocol(skb)) {
e974604b 6148 case htons(ETH_P_IP):
6149 opts[1] |= TD1_IPv4_CS;
6150 ip_protocol = ip_hdr(skb)->protocol;
6151 break;
6152
6153 case htons(ETH_P_IPV6):
6154 opts[1] |= TD1_IPv6_CS;
6155 ip_protocol = ipv6_hdr(skb)->nexthdr;
6156 break;
6157
6158 default:
6159 ip_protocol = IPPROTO_RAW;
6160 break;
6161 }
6162
6163 if (ip_protocol == IPPROTO_TCP)
6164 opts[1] |= TD1_TCP_CS;
6165 else if (ip_protocol == IPPROTO_UDP)
6166 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 6167 else
6168 WARN_ON_ONCE(1);
e974604b 6169
6170 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 6171 } else {
6172 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6173 return !eth_skb_pad(skb);
1da177e4 6174 }
5888d3fc 6175
b423e9ae 6176 return true;
1da177e4
LT		 6177}
6178
61357325
SH		 6179static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6180 struct net_device *dev)
1da177e4
LT		 6181{
6182 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 6183 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4 6184 struct TxDesc *txd = tp->TxDescArray + entry;
1e1205b7 6185 struct device *d = tp_to_dev(tp);
1da177e4
LT		 6186 dma_addr_t mapping;
6187 u32 status, len;
2b7b4318 6188 u32 opts[2];
3eafe507 6189 int frags;
5b0384f4 6190
477206a0 6191 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 6192 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 6193 goto err_stop_0;
1da177e4
LT		 6194 }
6195
6196 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 6197 goto err_stop_0;
6198
b423e9ae 6199 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6200 opts[0] = DescOwn;
6201
e974604b 6202 if (!tp->tso_csum(tp, skb, opts)) {
6203 r8169_csum_workaround(tp, skb);
6204 return NETDEV_TX_OK;
6205 }
b423e9ae 6206
3eafe507 6207 len = skb_headlen(skb);
48addcc9 6208 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 6209 if (unlikely(dma_mapping_error(d, mapping))) {
6210 if (net_ratelimit())
6211 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 6212 goto err_dma_0;
d827d86b 6213 }
3eafe507
SG		 6214
6215 tp->tx_skb[entry].len = len;
6216 txd->addr = cpu_to_le64(mapping);
1da177e4 6217
2b7b4318 6218 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 6219 if (frags < 0)
6220 goto err_dma_1;
6221 else if (frags)
2b7b4318 6222 opts[0] |= FirstFrag;
3eafe507 6223 else {
2b7b4318 6224 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 6225 tp->tx_skb[entry].skb = skb;
6226 }
6227
2b7b4318
FR		 6228 txd->opts2 = cpu_to_le32(opts[1]);
6229
5047fb5d
RC		 6230 skb_tx_timestamp(skb);
6231
a0750138
AD		 6232 /* Force memory writes to complete before releasing descriptor */
6233 dma_wmb();
1da177e4 6234
cecb5fd7 6235 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 6236 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6237 txd->opts1 = cpu_to_le32(status);
6238
a0750138 6239 /* Force all memory writes to complete before notifying device */
4c020a96 6240 wmb();
1da177e4 6241
a0750138
AD		 6242 tp->cur_tx += frags + 1;
6243
1ef7286e 6244 RTL_W8(tp, TxPoll, NPQ);
1da177e4 6245
87cda7cb 6246 mmiowb();
da78dbff 6247
87cda7cb 6248 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 6249 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6250 * not miss a ring update when it notices a stopped queue.
6251 */
6252 smp_wmb();
1da177e4 6253 netif_stop_queue(dev);
ae1f23fb
FR		 6254 /* Sync with rtl_tx:
6255 * - publish queue status and cur_tx ring index (write barrier)
6256 * - refresh dirty_tx ring index (read barrier).
6257 * May the current thread have a pessimistic view of the ring
6258 * status and forget to wake up queue, a racing rtl_tx thread
6259 * can't.
6260 */
1e874e04 6261 smp_mb();
477206a0 6262 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 6263 netif_wake_queue(dev);
6264 }
6265
61357325 6266 return NETDEV_TX_OK;
1da177e4 6267
3eafe507 6268err_dma_1:
48addcc9 6269 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 6270err_dma_0:
989c9ba1 6271 dev_kfree_skb_any(skb);
3eafe507
SG		 6272 dev->stats.tx_dropped++;
6273 return NETDEV_TX_OK;
6274
6275err_stop_0:
1da177e4 6276 netif_stop_queue(dev);
cebf8cc7 6277 dev->stats.tx_dropped++;
61357325 6278 return NETDEV_TX_BUSY;
1da177e4
LT		 6279}
6280
6281static void rtl8169_pcierr_interrupt(struct net_device *dev)
6282{
6283 struct rtl8169_private *tp = netdev_priv(dev);
6284 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 6285 u16 pci_status, pci_cmd;
6286
6287 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6288 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6289
bf82c189
JP		 6290 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6291 pci_cmd, pci_status);
1da177e4
LT		 6292
6293 /*
6294 * The recovery sequence below admits a very elaborated explanation:
6295 * - it seems to work;
d03902b8
FR		 6296 * - I did not see what else could be done;
6297 * - it makes iop3xx happy.
1da177e4
LT		 6298 *
6299 * Feel free to adjust to your needs.
6300 */
a27993f3 6301 if (pdev->broken_parity_status)
d03902b8
FR		 6302 pci_cmd &= ~PCI_COMMAND_PARITY;
6303 else
6304 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6305
6306 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 6307
6308 pci_write_config_word(pdev, PCI_STATUS,
6309 pci_status & (PCI_STATUS_DETECTED_PARITY |
6310 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6311 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6312
6313 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 6314 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
bf82c189 6315 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4 6316 tp->cp_cmd &= ~PCIDAC;
1ef7286e 6317 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1da177e4 6318 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 6319 }
6320
e6de30d6 6321 rtl8169_hw_reset(tp);
d03902b8 6322
98ddf986 6323 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6324}
6325
da78dbff 6326static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 6327{
6328 unsigned int dirty_tx, tx_left;
6329
1da177e4
LT		 6330 dirty_tx = tp->dirty_tx;
6331 smp_rmb();
6332 tx_left = tp->cur_tx - dirty_tx;
6333
6334 while (tx_left > 0) {
6335 unsigned int entry = dirty_tx % NUM_TX_DESC;
6336 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 6337 u32 status;
6338
1da177e4
LT		 6339 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6340 if (status & DescOwn)
6341 break;
6342
a0750138
AD		 6343 /* This barrier is needed to keep us from reading
6344 * any other fields out of the Tx descriptor until
6345 * we know the status of DescOwn
6346 */
6347 dma_rmb();
6348
1e1205b7 6349 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
48addcc9 6350 tp->TxDescArray + entry);
1da177e4 6351 if (status & LastFrag) {
87cda7cb
DM		 6352 u64_stats_update_begin(&tp->tx_stats.syncp);
6353 tp->tx_stats.packets++;
6354 tp->tx_stats.bytes += tx_skb->skb->len;
6355 u64_stats_update_end(&tp->tx_stats.syncp);
7a4b813c 6356 dev_consume_skb_any(tx_skb->skb);
1da177e4
LT		 6357 tx_skb->skb = NULL;
6358 }
6359 dirty_tx++;
6360 tx_left--;
6361 }
6362
6363 if (tp->dirty_tx != dirty_tx) {
6364 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6365 /* Sync with rtl8169_start_xmit:
6366 * - publish dirty_tx ring index (write barrier)
6367 * - refresh cur_tx ring index and queue status (read barrier)
6368 * May the current thread miss the stopped queue condition,
6369 * a racing xmit thread can only have a right view of the
6370 * ring status.
6371 */
1e874e04 6372 smp_mb();
1da177e4 6373 if (netif_queue_stopped(dev) &&
477206a0 6374 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6375 netif_wake_queue(dev);
6376 }
d78ae2dc
FR		 6377 /*
6378 * 8168 hack: TxPoll requests are lost when the Tx packets are
6379 * too close. Let's kick an extra TxPoll request when a burst
6380 * of start_xmit activity is detected (if it is not detected,
6381 * it is slow enough). -- FR
6382 */
1ef7286e
AS		 6383 if (tp->cur_tx != dirty_tx)
6384 RTL_W8(tp, TxPoll, NPQ);
1da177e4
LT		 6385 }
6386}
6387
126fa4b9
FR		 6388static inline int rtl8169_fragmented_frame(u32 status)
6389{
6390 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6391}
6392
adea1ac7 6393static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6394{
1da177e4
LT		 6395 u32 status = opts1 & RxProtoMask;
6396
6397 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6398 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6399 skb->ip_summed = CHECKSUM_UNNECESSARY;
6400 else
bc8acf2c 6401 skb_checksum_none_assert(skb);
1da177e4
LT		 6402}
6403
6f0333b8
ED		 6404static struct sk_buff *rtl8169_try_rx_copy(void *data,
6405 struct rtl8169_private *tp,
6406 int pkt_size,
6407 dma_addr_t addr)
1da177e4 6408{
b449655f 6409 struct sk_buff *skb;
1e1205b7 6410 struct device *d = tp_to_dev(tp);
b449655f 6411
6f0333b8 6412 data = rtl8169_align(data);
48addcc9 6413 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8 6414 prefetch(data);
e2338f86 6415 skb = napi_alloc_skb(&tp->napi, pkt_size);
6f0333b8 6416 if (skb)
8a67aa86 6417 skb_copy_to_linear_data(skb, data, pkt_size);
48addcc9
SG		 6418 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6419
6f0333b8 6420 return skb;
1da177e4
LT		 6421}
6422
da78dbff 6423static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6424{
6425 unsigned int cur_rx, rx_left;
6f0333b8 6426 unsigned int count;
1da177e4 6427
1da177e4 6428 cur_rx = tp->cur_rx;
1da177e4 6429
9fba0812 6430 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6431 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6432 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6433 u32 status;
6434
6202806e 6435 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 6436 if (status & DescOwn)
6437 break;
a0750138
AD		 6438
6439 /* This barrier is needed to keep us from reading
6440 * any other fields out of the Rx descriptor until
6441 * we know the status of DescOwn
6442 */
6443 dma_rmb();
6444
4dcb7d33 6445 if (unlikely(status & RxRES)) {
bf82c189
JP		 6446 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6447 status);
cebf8cc7 6448 dev->stats.rx_errors++;
1da177e4 6449 if (status & (RxRWT | RxRUNT))
cebf8cc7 6450 dev->stats.rx_length_errors++;
1da177e4 6451 if (status & RxCRC)
cebf8cc7 6452 dev->stats.rx_crc_errors++;
6202806e
HK		 6453 /* RxFOVF is a reserved bit on later chip versions */
6454 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6455 status & RxFOVF) {
da78dbff 6456 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6457 dev->stats.rx_fifo_errors++;
6202806e
HK		 6458 } else if (status & (RxRUNT | RxCRC) &&
6459 !(status & RxRWT) &&
6460 dev->features & NETIF_F_RXALL) {
6bbe021d 6461 goto process_pkt;
6202806e 6462 }
1da177e4 6463 } else {
6f0333b8 6464 struct sk_buff *skb;
6bbe021d
BG		 6465 dma_addr_t addr;
6466 int pkt_size;
6467
6468process_pkt:
6469 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6470 if (likely(!(dev->features & NETIF_F_RXFCS)))
6471 pkt_size = (status & 0x00003fff) - 4;
6472 else
6473 pkt_size = status & 0x00003fff;
1da177e4 6474
126fa4b9
FR		 6475 /*
6476 * The driver does not support incoming fragmented
6477 * frames. They are seen as a symptom of over-mtu
6478 * sized frames.
6479 */
6480 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6481 dev->stats.rx_dropped++;
6482 dev->stats.rx_length_errors++;
ce11ff5e 6483 goto release_descriptor;
126fa4b9
FR		 6484 }
6485
6f0333b8
ED		 6486 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6487 tp, pkt_size, addr);
6f0333b8
ED		 6488 if (!skb) {
6489 dev->stats.rx_dropped++;
ce11ff5e 6490 goto release_descriptor;
1da177e4
LT		 6491 }
6492
adea1ac7 6493 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6494 skb_put(skb, pkt_size);
6495 skb->protocol = eth_type_trans(skb, dev);
6496
7a8fc77b
FR		 6497 rtl8169_rx_vlan_tag(desc, skb);
6498
39174291 6499 if (skb->pkt_type == PACKET_MULTICAST)
6500 dev->stats.multicast++;
6501
56de414c 6502 napi_gro_receive(&tp->napi, skb);
1da177e4 6503
8027aa24
JW		 6504 u64_stats_update_begin(&tp->rx_stats.syncp);
6505 tp->rx_stats.packets++;
6506 tp->rx_stats.bytes += pkt_size;
6507 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6508 }
ce11ff5e 6509release_descriptor:
6510 desc->opts2 = 0;
1d0254dd 6511 rtl8169_mark_to_asic(desc);
1da177e4
LT		 6512 }
6513
6514 count = cur_rx - tp->cur_rx;
6515 tp->cur_rx = cur_rx;
6516
1da177e4
LT		 6517 return count;
6518}
6519
07d3f51f 6520static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6521{
ebcd5daa 6522 struct rtl8169_private *tp = dev_instance;
05bbe558 6523 u16 status = rtl_get_events(tp);
1da177e4 6524
05bbe558
HK		 6525 if (status == 0xffff || !(status & (RTL_EVENT_NAPI | tp->event_slow)))
6526 return IRQ_NONE;
1da177e4 6527
05bbe558
HK		 6528 rtl_irq_disable(tp);
6529 napi_schedule_irqoff(&tp->napi);
6530
6531 return IRQ_HANDLED;
da78dbff 6532}
1da177e4 6533
da78dbff
FR		 6534/*
6535 * Workqueue context.
6536 */
6537static void rtl_slow_event_work(struct rtl8169_private *tp)
6538{
6539 struct net_device *dev = tp->dev;
6540 u16 status;
6541
6542 status = rtl_get_events(tp) & tp->event_slow;
6543 rtl_ack_events(tp, status);
1da177e4 6544
da78dbff
FR		 6545 if (unlikely(status & RxFIFOOver)) {
6546 switch (tp->mac_version) {
6547 /* Work around for rx fifo overflow */
6548 case RTL_GIGA_MAC_VER_11:
6549 netif_stop_queue(dev);
934714d0
FR		 6550 /* XXX - Hack alert. See rtl_task(). */
6551 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6552 default:
f11a377b
DD		 6553 break;
6554 }
da78dbff 6555 }
1da177e4 6556
da78dbff
FR		 6557 if (unlikely(status & SYSErr))
6558 rtl8169_pcierr_interrupt(dev);
0e485150 6559
da78dbff 6560 if (status & LinkChg)
f1e911d5 6561 phy_mac_interrupt(dev->phydev);
1da177e4 6562
7dbb4918 6563 rtl_irq_enable_all(tp);
1da177e4
LT		 6564}
6565
4422bcd4
FR		 6566static void rtl_task(struct work_struct *work)
6567{
da78dbff
FR		 6568 static const struct {
6569 int bitnr;
6570 void (*action)(struct rtl8169_private *);
6571 } rtl_work[] = {
934714d0 6572 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6573 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6574 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
da78dbff 6575 };
4422bcd4
FR		 6576 struct rtl8169_private *tp =
6577 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6578 struct net_device *dev = tp->dev;
6579 int i;
6580
6581 rtl_lock_work(tp);
6582
6c4a70c5
FR		 6583 if (!netif_running(dev) ||
6584 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6585 goto out_unlock;
6586
6587 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6588 bool pending;
6589
da78dbff 6590 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6591 if (pending)
6592 rtl_work[i].action(tp);
6593 }
4422bcd4 6594
da78dbff
FR		 6595out_unlock:
6596 rtl_unlock_work(tp);
4422bcd4
FR		 6597}
6598
bea3348e 6599static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6600{
bea3348e
SH		 6601 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6602 struct net_device *dev = tp->dev;
da78dbff
FR		 6603 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6604 int work_done= 0;
6605 u16 status;
6606
6607 status = rtl_get_events(tp);
6608 rtl_ack_events(tp, status & ~tp->event_slow);
6609
6610 if (status & RTL_EVENT_NAPI_RX)
6611 work_done = rtl_rx(dev, tp, (u32) budget);
6612
6613 if (status & RTL_EVENT_NAPI_TX)
6614 rtl_tx(dev, tp);
1da177e4 6615
da78dbff
FR		 6616 if (status & tp->event_slow) {
6617 enable_mask &= ~tp->event_slow;
6618
6619 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6620 }
1da177e4 6621
bea3348e 6622 if (work_done < budget) {
6ad20165 6623 napi_complete_done(napi, work_done);
f11a377b 6624
da78dbff
FR		 6625 rtl_irq_enable(tp, enable_mask);
6626 mmiowb();
1da177e4
LT		 6627 }
6628
bea3348e 6629 return work_done;
1da177e4 6630}
1da177e4 6631
1ef7286e 6632static void rtl8169_rx_missed(struct net_device *dev)
523a6094
FR		 6633{
6634 struct rtl8169_private *tp = netdev_priv(dev);
6635
6636 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6637 return;
6638
1ef7286e
AS		 6639 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6640 RTL_W32(tp, RxMissed, 0);
523a6094
FR		 6641}
6642
f1e911d5
HK		 6643static void r8169_phylink_handler(struct net_device *ndev)
6644{
6645 struct rtl8169_private *tp = netdev_priv(ndev);
6646
6647 if (netif_carrier_ok(ndev)) {
6648 rtl_link_chg_patch(tp);
6649 pm_request_resume(&tp->pci_dev->dev);
6650 } else {
6651 pm_runtime_idle(&tp->pci_dev->dev);
6652 }
6653
6654 if (net_ratelimit())
6655 phy_print_status(ndev->phydev);
6656}
6657
6658static int r8169_phy_connect(struct rtl8169_private *tp)
6659{
6660 struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6661 phy_interface_t phy_mode;
6662 int ret;
6663
f7ffa9ae 6664 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
f1e911d5
HK		 6665 PHY_INTERFACE_MODE_MII;
6666
6667 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6668 phy_mode);
6669 if (ret)
6670 return ret;
6671
f7ffa9ae 6672 if (!tp->supports_gmii)
f1e911d5
HK		 6673 phy_set_max_speed(phydev, SPEED_100);
6674
6675 /* Ensure to advertise everything, incl. pause */
6676 phydev->advertising = phydev->supported;
6677
6678 phy_attached_info(phydev);
6679
6680 return 0;
6681}
6682
1da177e4
LT		 6683static void rtl8169_down(struct net_device *dev)
6684{
6685 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6686
f1e911d5
HK		 6687 phy_stop(dev->phydev);
6688
93dd79e8 6689 napi_disable(&tp->napi);
da78dbff 6690 netif_stop_queue(dev);
1da177e4 6691
92fc43b4 6692 rtl8169_hw_reset(tp);
323bb685
SG		 6693 /*
6694 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6695 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6696 * and napi is disabled (rtl8169_poll).
323bb685 6697 */
1ef7286e 6698 rtl8169_rx_missed(dev);
1da177e4 6699
1da177e4 6700 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6701 synchronize_sched();
1da177e4 6702
1da177e4
LT		 6703 rtl8169_tx_clear(tp);
6704
6705 rtl8169_rx_clear(tp);
065c27c1 6706
6707 rtl_pll_power_down(tp);
1da177e4
LT		 6708}
6709
6710static int rtl8169_close(struct net_device *dev)
6711{
6712 struct rtl8169_private *tp = netdev_priv(dev);
6713 struct pci_dev *pdev = tp->pci_dev;
6714
e1759441
RW		 6715 pm_runtime_get_sync(&pdev->dev);
6716
cecb5fd7 6717 /* Update counters before going down */
e71c9ce2 6718 rtl8169_update_counters(tp);
355423d0 6719
da78dbff 6720 rtl_lock_work(tp);
6c4a70c5 6721 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6722
1da177e4 6723 rtl8169_down(dev);
da78dbff 6724 rtl_unlock_work(tp);
1da177e4 6725
4ea72445
L		 6726 cancel_work_sync(&tp->wk.work);
6727
f1e911d5
HK		 6728 phy_disconnect(dev->phydev);
6729
ebcd5daa 6730 pci_free_irq(pdev, 0, tp);
1da177e4 6731
82553bb6
SG		 6732 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6733 tp->RxPhyAddr);
6734 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6735 tp->TxPhyAddr);
1da177e4
LT		 6736 tp->TxDescArray = NULL;
6737 tp->RxDescArray = NULL;
6738
e1759441
RW		 6739 pm_runtime_put_sync(&pdev->dev);
6740
1da177e4
LT		 6741 return 0;
6742}
6743
dc1c00ce
FR		 6744#ifdef CONFIG_NET_POLL_CONTROLLER
6745static void rtl8169_netpoll(struct net_device *dev)
6746{
6747 struct rtl8169_private *tp = netdev_priv(dev);
6748
6d8b8349 6749 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
dc1c00ce
FR		 6750}
6751#endif
6752
df43ac78
FR		 6753static int rtl_open(struct net_device *dev)
6754{
6755 struct rtl8169_private *tp = netdev_priv(dev);
df43ac78
FR		 6756 struct pci_dev *pdev = tp->pci_dev;
6757 int retval = -ENOMEM;
6758
6759 pm_runtime_get_sync(&pdev->dev);
6760
6761 /*
e75d6606 6762 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6763 * dma_alloc_coherent provides more.
6764 */
6765 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6766 &tp->TxPhyAddr, GFP_KERNEL);
6767 if (!tp->TxDescArray)
6768 goto err_pm_runtime_put;
6769
6770 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6771 &tp->RxPhyAddr, GFP_KERNEL);
6772 if (!tp->RxDescArray)
6773 goto err_free_tx_0;
6774
b1127e64 6775 retval = rtl8169_init_ring(tp);
df43ac78
FR		 6776 if (retval < 0)
6777 goto err_free_rx_1;
6778
6779 INIT_WORK(&tp->wk.work, rtl_task);
6780
6781 smp_mb();
6782
6783 rtl_request_firmware(tp);
6784
ebcd5daa 6785 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6c6aa15f 6786 dev->name);
df43ac78
FR		 6787 if (retval < 0)
6788 goto err_release_fw_2;
6789
f1e911d5
HK		 6790 retval = r8169_phy_connect(tp);
6791 if (retval)
6792 goto err_free_irq;
6793
df43ac78
FR		 6794 rtl_lock_work(tp);
6795
6796 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6797
6798 napi_enable(&tp->napi);
6799
6800 rtl8169_init_phy(dev, tp);
6801
df43ac78
FR		 6802 rtl_pll_power_up(tp);
6803
61cb532d 6804 rtl_hw_start(tp);
df43ac78 6805
e71c9ce2 6806 if (!rtl8169_init_counter_offsets(tp))
6e85d5ad
CV		 6807 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6808
f1e911d5 6809 phy_start(dev->phydev);
df43ac78
FR		 6810 netif_start_queue(dev);
6811
6812 rtl_unlock_work(tp);
6813
a92a0849 6814 pm_runtime_put_sync(&pdev->dev);
df43ac78
FR		 6815out:
6816 return retval;
6817
f1e911d5
HK		 6818err_free_irq:
6819 pci_free_irq(pdev, 0, tp);
df43ac78
FR		 6820err_release_fw_2:
6821 rtl_release_firmware(tp);
6822 rtl8169_rx_clear(tp);
6823err_free_rx_1:
6824 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6825 tp->RxPhyAddr);
6826 tp->RxDescArray = NULL;
6827err_free_tx_0:
6828 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6829 tp->TxPhyAddr);
6830 tp->TxDescArray = NULL;
6831err_pm_runtime_put:
6832 pm_runtime_put_noidle(&pdev->dev);
6833 goto out;
6834}
6835
bc1f4470 6836static void
8027aa24 6837rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6838{
6839 struct rtl8169_private *tp = netdev_priv(dev);
f09cf4b7 6840 struct pci_dev *pdev = tp->pci_dev;
42020320 6841 struct rtl8169_counters *counters = tp->counters;
8027aa24 6842 unsigned int start;
1da177e4 6843
f09cf4b7
CHL		 6844 pm_runtime_get_noresume(&pdev->dev);
6845
6846 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
1ef7286e 6847 rtl8169_rx_missed(dev);
5b0384f4 6848
8027aa24 6849 do {
57a7744e 6850 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 6851 stats->rx_packets = tp->rx_stats.packets;
6852 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 6853 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 6854
8027aa24 6855 do {
57a7744e 6856 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 6857 stats->tx_packets = tp->tx_stats.packets;
6858 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 6859 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 6860
6861 stats->rx_dropped = dev->stats.rx_dropped;
6862 stats->tx_dropped = dev->stats.tx_dropped;
6863 stats->rx_length_errors = dev->stats.rx_length_errors;
6864 stats->rx_errors = dev->stats.rx_errors;
6865 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6866 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6867 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 6868 stats->multicast = dev->stats.multicast;
8027aa24 6869
6e85d5ad
CV		 6870 /*
6871 * Fetch additonal counter values missing in stats collected by driver
6872 * from tally counters.
6873 */
f09cf4b7 6874 if (pm_runtime_active(&pdev->dev))
e71c9ce2 6875 rtl8169_update_counters(tp);
6e85d5ad
CV		 6876
6877 /*
6878 * Subtract values fetched during initalization.
6879 * See rtl8169_init_counter_offsets for a description why we do that.
6880 */
42020320 6881 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 6882 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 6883 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 6884 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 6885 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 6886 le16_to_cpu(tp->tc_offset.tx_aborted);
6887
f09cf4b7 6888 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 6889}
6890
861ab440 6891static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6892{
065c27c1 6893 struct rtl8169_private *tp = netdev_priv(dev);
6894
5d06a99f 6895 if (!netif_running(dev))
861ab440 6896 return;
5d06a99f 6897
f1e911d5 6898 phy_stop(dev->phydev);
5d06a99f
FR		 6899 netif_device_detach(dev);
6900 netif_stop_queue(dev);
da78dbff
FR		 6901
6902 rtl_lock_work(tp);
6903 napi_disable(&tp->napi);
6c4a70c5 6904 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 6905 rtl_unlock_work(tp);
6906
6907 rtl_pll_power_down(tp);
861ab440
RW		 6908}
6909
6910#ifdef CONFIG_PM
6911
6912static int rtl8169_suspend(struct device *device)
6913{
6914 struct pci_dev *pdev = to_pci_dev(device);
6915 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6916
861ab440 6917 rtl8169_net_suspend(dev);
1371fa6d 6918
5d06a99f
FR		 6919 return 0;
6920}
6921
e1759441
RW		 6922static void __rtl8169_resume(struct net_device *dev)
6923{
065c27c1 6924 struct rtl8169_private *tp = netdev_priv(dev);
6925
e1759441 6926 netif_device_attach(dev);
065c27c1 6927
6928 rtl_pll_power_up(tp);
92bad850 6929 rtl8169_init_phy(dev, tp);
065c27c1 6930
f1e911d5
HK		 6931 phy_start(tp->dev->phydev);
6932
cff4c162
AS		 6933 rtl_lock_work(tp);
6934 napi_enable(&tp->napi);
6c4a70c5 6935 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6936 rtl_unlock_work(tp);
da78dbff 6937
98ddf986 6938 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6939}
6940
861ab440 6941static int rtl8169_resume(struct device *device)
5d06a99f 6942{
861ab440 6943 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f
FR		 6944 struct net_device *dev = pci_get_drvdata(pdev);
6945
e1759441
RW		 6946 if (netif_running(dev))
6947 __rtl8169_resume(dev);
5d06a99f 6948
e1759441
RW		 6949 return 0;
6950}
6951
6952static int rtl8169_runtime_suspend(struct device *device)
6953{
6954 struct pci_dev *pdev = to_pci_dev(device);
6955 struct net_device *dev = pci_get_drvdata(pdev);
6956 struct rtl8169_private *tp = netdev_priv(dev);
6957
07df5bd8 6958 if (!tp->TxDescArray)
e1759441
RW		 6959 return 0;
6960
da78dbff 6961 rtl_lock_work(tp);
e1759441 6962 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6963 rtl_unlock_work(tp);
e1759441
RW		 6964
6965 rtl8169_net_suspend(dev);
6966
f09cf4b7 6967 /* Update counters before going runtime suspend */
1ef7286e 6968 rtl8169_rx_missed(dev);
e71c9ce2 6969 rtl8169_update_counters(tp);
f09cf4b7 6970
e1759441
RW		 6971 return 0;
6972}
6973
6974static int rtl8169_runtime_resume(struct device *device)
6975{
6976 struct pci_dev *pdev = to_pci_dev(device);
6977 struct net_device *dev = pci_get_drvdata(pdev);
6978 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 6979 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 6980
6981 if (!tp->TxDescArray)
6982 return 0;
6983
da78dbff 6984 rtl_lock_work(tp);
e1759441 6985 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff 6986 rtl_unlock_work(tp);
e1759441
RW		 6987
6988 __rtl8169_resume(dev);
5d06a99f 6989
5d06a99f
FR		 6990 return 0;
6991}
6992
e1759441
RW		 6993static int rtl8169_runtime_idle(struct device *device)
6994{
6995 struct pci_dev *pdev = to_pci_dev(device);
6996 struct net_device *dev = pci_get_drvdata(pdev);
e1759441 6997
a92a0849
HK		 6998 if (!netif_running(dev) || !netif_carrier_ok(dev))
6999 pm_schedule_suspend(device, 10000);
7000
7001 return -EBUSY;
e1759441
RW		 7002}
7003
47145210 7004static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 7005 .suspend = rtl8169_suspend,
7006 .resume = rtl8169_resume,
7007 .freeze = rtl8169_suspend,
7008 .thaw = rtl8169_resume,
7009 .poweroff = rtl8169_suspend,
7010 .restore = rtl8169_resume,
7011 .runtime_suspend = rtl8169_runtime_suspend,
7012 .runtime_resume = rtl8169_runtime_resume,
7013 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 7014};
7015
7016#define RTL8169_PM_OPS (&rtl8169_pm_ops)
7017
7018#else /* !CONFIG_PM */
7019
7020#define RTL8169_PM_OPS NULL
7021
7022#endif /* !CONFIG_PM */
7023
649b3b8c 7024static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7025{
649b3b8c 7026 /* WoL fails with 8168b when the receiver is disabled. */
7027 switch (tp->mac_version) {
7028 case RTL_GIGA_MAC_VER_11:
7029 case RTL_GIGA_MAC_VER_12:
7030 case RTL_GIGA_MAC_VER_17:
7031 pci_clear_master(tp->pci_dev);
7032
1ef7286e 7033 RTL_W8(tp, ChipCmd, CmdRxEnb);
649b3b8c 7034 /* PCI commit */
1ef7286e 7035 RTL_R8(tp, ChipCmd);
649b3b8c 7036 break;
7037 default:
7038 break;
7039 }
7040}
7041
1765f95d
FR		 7042static void rtl_shutdown(struct pci_dev *pdev)
7043{
861ab440 7044 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 7045 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 7046
7047 rtl8169_net_suspend(dev);
1765f95d 7048
cecb5fd7 7049 /* Restore original MAC address */
cc098dc7
IV		 7050 rtl_rar_set(tp, dev->perm_addr);
7051
92fc43b4 7052 rtl8169_hw_reset(tp);
4bb3f522 7053
861ab440 7054 if (system_state == SYSTEM_POWER_OFF) {
433f9d0d 7055 if (tp->saved_wolopts) {
649b3b8c 7056 rtl_wol_suspend_quirk(tp);
7057 rtl_wol_shutdown_quirk(tp);
ca52efd5 7058 }
7059
861ab440
RW		 7060 pci_wake_from_d3(pdev, true);
7061 pci_set_power_state(pdev, PCI_D3hot);
7062 }
7063}
5d06a99f 7064
baf63293 7065static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 7066{
7067 struct net_device *dev = pci_get_drvdata(pdev);
7068 struct rtl8169_private *tp = netdev_priv(dev);
7069
9dbe7896 7070 if (r8168_check_dash(tp))
e27566ed 7071 rtl8168_driver_stop(tp);
e27566ed 7072
ad1be8d3
DN		 7073 netif_napi_del(&tp->napi);
7074
e27566ed 7075 unregister_netdev(dev);
f1e911d5 7076 mdiobus_unregister(tp->mii_bus);
e27566ed
FR		 7077
7078 rtl_release_firmware(tp);
7079
7080 if (pci_dev_run_wake(pdev))
7081 pm_runtime_get_noresume(&pdev->dev);
7082
7083 /* restore original MAC address */
7084 rtl_rar_set(tp, dev->perm_addr);
e27566ed
FR		 7085}
7086
fa9c385e 7087static const struct net_device_ops rtl_netdev_ops = {
df43ac78 7088 .ndo_open = rtl_open,
fa9c385e
FR		 7089 .ndo_stop = rtl8169_close,
7090 .ndo_get_stats64 = rtl8169_get_stats64,
7091 .ndo_start_xmit = rtl8169_start_xmit,
7092 .ndo_tx_timeout = rtl8169_tx_timeout,
7093 .ndo_validate_addr = eth_validate_addr,
7094 .ndo_change_mtu = rtl8169_change_mtu,
7095 .ndo_fix_features = rtl8169_fix_features,
7096 .ndo_set_features = rtl8169_set_features,
7097 .ndo_set_mac_address = rtl_set_mac_address,
7098 .ndo_do_ioctl = rtl8169_ioctl,
7099 .ndo_set_rx_mode = rtl_set_rx_mode,
7100#ifdef CONFIG_NET_POLL_CONTROLLER
7101 .ndo_poll_controller = rtl8169_netpoll,
7102#endif
7103
7104};
7105
31fa8b18 7106static const struct rtl_cfg_info {
61cb532d 7107 void (*hw_start)(struct rtl8169_private *tp);
31fa8b18 7108 u16 event_slow;
14967f94 7109 unsigned int has_gmii:1;
50970831 7110 const struct rtl_coalesce_info *coalesce_info;
31fa8b18
FR		 7111 u8 default_ver;
7112} rtl_cfg_infos [] = {
7113 [RTL_CFG_0] = {
7114 .hw_start = rtl_hw_start_8169,
31fa8b18 7115 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
14967f94 7116 .has_gmii = 1,
50970831 7117 .coalesce_info = rtl_coalesce_info_8169,
31fa8b18
FR		 7118 .default_ver = RTL_GIGA_MAC_VER_01,
7119 },
7120 [RTL_CFG_1] = {
7121 .hw_start = rtl_hw_start_8168,
31fa8b18 7122 .event_slow = SYSErr | LinkChg | RxOverflow,
14967f94 7123 .has_gmii = 1,
50970831 7124 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 7125 .default_ver = RTL_GIGA_MAC_VER_11,
7126 },
7127 [RTL_CFG_2] = {
7128 .hw_start = rtl_hw_start_8101,
31fa8b18
FR		 7129 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7130 PCSTimeout,
50970831 7131 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 7132 .default_ver = RTL_GIGA_MAC_VER_13,
7133 }
7134};
7135
6c6aa15f 7136static int rtl_alloc_irq(struct rtl8169_private *tp)
31fa8b18 7137{
6c6aa15f 7138 unsigned int flags;
31fa8b18 7139
6c6aa15f 7140 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1ef7286e
AS		 7141 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7142 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7143 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6c6aa15f
HK		 7144 flags = PCI_IRQ_LEGACY;
7145 } else {
7146 flags = PCI_IRQ_ALL_TYPES;
31fa8b18 7147 }
6c6aa15f
HK		 7148
7149 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
31fa8b18
FR		 7150}
7151
c558386b
HW		 7152DECLARE_RTL_COND(rtl_link_list_ready_cond)
7153{
1ef7286e 7154 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
c558386b
HW		 7155}
7156
7157DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7158{
1ef7286e 7159 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
c558386b
HW		 7160}
7161
f1e911d5
HK		 7162static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7163{
7164 struct rtl8169_private *tp = mii_bus->priv;
7165
7166 if (phyaddr > 0)
7167 return -ENODEV;
7168
7169 return rtl_readphy(tp, phyreg);
7170}
7171
7172static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7173 int phyreg, u16 val)
7174{
7175 struct rtl8169_private *tp = mii_bus->priv;
7176
7177 if (phyaddr > 0)
7178 return -ENODEV;
7179
7180 rtl_writephy(tp, phyreg, val);
7181
7182 return 0;
7183}
7184
7185static int r8169_mdio_register(struct rtl8169_private *tp)
7186{
7187 struct pci_dev *pdev = tp->pci_dev;
7188 struct phy_device *phydev;
7189 struct mii_bus *new_bus;
7190 int ret;
7191
7192 new_bus = devm_mdiobus_alloc(&pdev->dev);
7193 if (!new_bus)
7194 return -ENOMEM;
7195
7196 new_bus->name = "r8169";
7197 new_bus->priv = tp;
7198 new_bus->parent = &pdev->dev;
7199 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7200 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7201 PCI_DEVID(pdev->bus->number, pdev->devfn));
7202
7203 new_bus->read = r8169_mdio_read_reg;
7204 new_bus->write = r8169_mdio_write_reg;
7205
7206 ret = mdiobus_register(new_bus);
7207 if (ret)
7208 return ret;
7209
7210 phydev = mdiobus_get_phy(new_bus, 0);
7211 if (!phydev) {
7212 mdiobus_unregister(new_bus);
7213 return -ENODEV;
7214 }
7215
242cd9b5
HK		 7216 /* PHY will be woken up in rtl_open() */
7217 phy_suspend(phydev);
7218
f1e911d5
HK		 7219 tp->mii_bus = new_bus;
7220
7221 return 0;
7222}
7223
baf63293 7224static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b 7225{
c558386b
HW		 7226 u32 data;
7227
7228 tp->ocp_base = OCP_STD_PHY_BASE;
7229
1ef7286e 7230 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
c558386b
HW		 7231
7232 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7233 return;
7234
7235 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7236 return;
7237
1ef7286e 7238 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
c558386b 7239 msleep(1);
1ef7286e 7240 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
c558386b 7241
5f8bcce9 7242 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7243 data &= ~(1 << 14);
7244 r8168_mac_ocp_write(tp, 0xe8de, data);
7245
7246 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7247 return;
7248
5f8bcce9 7249 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7250 data |= (1 << 15);
7251 r8168_mac_ocp_write(tp, 0xe8de, data);
7252
7253 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7254 return;
7255}
7256
003609da
CHL		 7257static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7258{
7259 rtl8168ep_stop_cmac(tp);
7260 rtl_hw_init_8168g(tp);
7261}
7262
baf63293 7263static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 7264{
7265 switch (tp->mac_version) {
2a71883c 7266 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
003609da
CHL		 7267 rtl_hw_init_8168g(tp);
7268 break;
2a71883c 7269 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
003609da 7270 rtl_hw_init_8168ep(tp);
c558386b 7271 break;
c558386b
HW		 7272 default:
7273 break;
7274 }
7275}
7276
929a031d 7277static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 7278{
7279 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3b6cf25d 7280 struct rtl8169_private *tp;
3b6cf25d 7281 struct net_device *dev;
c8d48d9c 7282 int chipset, region, i;
3b6cf25d
FR		 7283 int rc;
7284
4c45d24a
HK		 7285 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7286 if (!dev)
7287 return -ENOMEM;
3b6cf25d
FR		 7288
7289 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 7290 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 7291 tp = netdev_priv(dev);
7292 tp->dev = dev;
7293 tp->pci_dev = pdev;
7294 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
f7ffa9ae 7295 tp->supports_gmii = cfg->has_gmii;
3b6cf25d 7296
3b6cf25d 7297 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4c45d24a 7298 rc = pcim_enable_device(pdev);
3b6cf25d 7299 if (rc < 0) {
22148df0 7300 dev_err(&pdev->dev, "enable failure\n");
4c45d24a 7301 return rc;
3b6cf25d
FR		 7302 }
7303
4c45d24a 7304 if (pcim_set_mwi(pdev) < 0)
22148df0 7305 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
3b6cf25d 7306
c8d48d9c
HK		 7307 /* use first MMIO region */
7308 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7309 if (region < 0) {
22148df0 7310 dev_err(&pdev->dev, "no MMIO resource found\n");
4c45d24a 7311 return -ENODEV;
3b6cf25d
FR		 7312 }
7313
7314 /* check for weird/broken PCI region reporting */
7315 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
22148df0 7316 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
4c45d24a 7317 return -ENODEV;
3b6cf25d
FR		 7318 }
7319
93a00d4d 7320 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
3b6cf25d 7321 if (rc < 0) {
22148df0 7322 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
4c45d24a 7323 return rc;
3b6cf25d
FR		 7324 }
7325
93a00d4d 7326 tp->mmio_addr = pcim_iomap_table(pdev)[region];
3b6cf25d
FR		 7327
7328 if (!pci_is_pcie(pdev))
22148df0 7329 dev_info(&pdev->dev, "not PCI Express\n");
3b6cf25d
FR		 7330
7331 /* Identify chip attached to board */
22148df0 7332 rtl8169_get_mac_version(tp, cfg->default_ver);
3b6cf25d 7333
e397286b
HK		 7334 if (rtl_tbi_enabled(tp)) {
7335 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7336 return -ENODEV;
7337 }
7338
0ae0974e 7339 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
27896c83
AB		 7340
7341 if ((sizeof(dma_addr_t) > 4) &&
7342 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7343 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
f0076436
AB		 7344 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7345 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
27896c83
AB		 7346
7347 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7348 if (!pci_is_pcie(pdev))
7349 tp->cp_cmd |= PCIDAC;
7350 dev->features |= NETIF_F_HIGHDMA;
7351 } else {
7352 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7353 if (rc < 0) {
22148df0 7354 dev_err(&pdev->dev, "DMA configuration failed\n");
4c45d24a 7355 return rc;
27896c83
AB		 7356 }
7357 }
7358
3b6cf25d
FR		 7359 rtl_init_rxcfg(tp);
7360
7361 rtl_irq_disable(tp);
7362
c558386b
HW		 7363 rtl_hw_initialize(tp);
7364
3b6cf25d
FR		 7365 rtl_hw_reset(tp);
7366
7367 rtl_ack_events(tp, 0xffff);
7368
7369 pci_set_master(pdev);
7370
3b6cf25d 7371 rtl_init_mdio_ops(tp);
3b6cf25d
FR		 7372 rtl_init_jumbo_ops(tp);
7373
7374 rtl8169_print_mac_version(tp);
7375
7376 chipset = tp->mac_version;
3b6cf25d 7377
6c6aa15f
HK		 7378 rc = rtl_alloc_irq(tp);
7379 if (rc < 0) {
22148df0 7380 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6c6aa15f
HK		 7381 return rc;
7382 }
3b6cf25d 7383
18041b52 7384 tp->saved_wolopts = __rtl8169_get_wol(tp);
7edf6d31 7385
3b6cf25d 7386 mutex_init(&tp->wk.mutex);
340fea3d
KM		 7387 u64_stats_init(&tp->rx_stats.syncp);
7388 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 7389
7390 /* Get MAC address */
b2d43e6e 7391 switch (tp->mac_version) {
353af85e 7392 u8 mac_addr[ETH_ALEN] __aligned(4);
b2d43e6e
HK		 7393 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7394 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
05b9687b 7395 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
353af85e 7396 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89 7397
353af85e
HK		 7398 if (is_valid_ether_addr(mac_addr))
7399 rtl_rar_set(tp, mac_addr);
b2d43e6e
HK		 7400 break;
7401 default:
7402 break;
6e1d0b89 7403 }
3b6cf25d 7404 for (i = 0; i < ETH_ALEN; i++)
1ef7286e 7405 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
3b6cf25d 7406
7ad24ea4 7407 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 7408 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d 7409
37621493 7410 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
3b6cf25d
FR		 7411
7412 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7413 * properly for all devices */
7414 dev->features |= NETIF_F_RXCSUM |
f646968f 7415 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7416
7417 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 7418 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7419 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7420 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7421 NETIF_F_HIGHDMA;
2d0ec544 7422 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3b6cf25d 7423
929a031d 7424 tp->cp_cmd |= RxChkSum | RxVlan;
7425
7426 /*
7427 * Pretend we are using VLANs; This bypasses a nasty bug where
7428 * Interrupts stop flowing on high load on 8110SCd controllers.
7429 */
3b6cf25d 7430 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 7431 /* Disallow toggling */
f646968f 7432 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 7433
a4328ddb
HK		 7434 switch (rtl_chip_infos[chipset].txd_version) {
7435 case RTL_TD_0:
5888d3fc 7436 tp->tso_csum = rtl8169_tso_csum_v1;
a4328ddb
HK		 7437 break;
7438 case RTL_TD_1:
5888d3fc 7439 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 7440 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
a4328ddb
HK		 7441 break;
7442 default:
5888d3fc 7443 WARN_ON_ONCE(1);
a4328ddb 7444 }
5888d3fc 7445
3b6cf25d
FR		 7446 dev->hw_features |= NETIF_F_RXALL;
7447 dev->hw_features |= NETIF_F_RXFCS;
7448
c7315a95
JW		 7449 /* MTU range: 60 - hw-specific max */
7450 dev->min_mtu = ETH_ZLEN;
7451 dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
7452
3b6cf25d
FR		 7453 tp->hw_start = cfg->hw_start;
7454 tp->event_slow = cfg->event_slow;
50970831 7455 tp->coalesce_info = cfg->coalesce_info;
3b6cf25d 7456
3b6cf25d
FR		 7457 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7458
4c45d24a
HK		 7459 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7460 &tp->counters_phys_addr,
7461 GFP_KERNEL);
4cf964af
HK		 7462 if (!tp->counters)
7463 return -ENOMEM;
42020320 7464
19c9ea36
HK		 7465 pci_set_drvdata(pdev, dev);
7466
f1e911d5
HK		 7467 rc = r8169_mdio_register(tp);
7468 if (rc)
4cf964af 7469 return rc;
3b6cf25d 7470
07df5bd8
HK		 7471 /* chip gets powered up in rtl_open() */
7472 rtl_pll_power_down(tp);
7473
f1e911d5
HK		 7474 rc = register_netdev(dev);
7475 if (rc)
7476 goto err_mdio_unregister;
7477
2d6c5a61
HK		 7478 netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7479 rtl_chip_infos[chipset].name, dev->dev_addr,
90b989c5 7480 (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
29274991 7481 pci_irq_vector(pdev, 0));
3b6cf25d
FR		 7482 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7483 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7484 "tx checksumming: %s]\n",
7485 rtl_chip_infos[chipset].jumbo_max,
6ed0e08f 7486 tp->mac_version <= RTL_GIGA_MAC_VER_06 ? "ok" : "ko");
3b6cf25d
FR		 7487 }
7488
9dbe7896 7489 if (r8168_check_dash(tp))
3b6cf25d 7490 rtl8168_driver_start(tp);
3b6cf25d 7491
a92a0849
HK		 7492 if (pci_dev_run_wake(pdev))
7493 pm_runtime_put_sync(&pdev->dev);
7494
4c45d24a 7495 return 0;
f1e911d5
HK		 7496
7497err_mdio_unregister:
7498 mdiobus_unregister(tp->mii_bus);
7499 return rc;
3b6cf25d
FR		 7500}
7501
1da177e4
LT		 7502static struct pci_driver rtl8169_pci_driver = {
7503 .name = MODULENAME,
7504 .id_table = rtl8169_pci_tbl,
3b6cf25d 7505 .probe = rtl_init_one,
baf63293 7506 .remove = rtl_remove_one,
1765f95d 7507 .shutdown = rtl_shutdown,
861ab440 7508 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7509};
7510
3eeb7da9 7511module_pci_driver(rtl8169_pci_driver);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git