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r8169: replace rx_buf_sz with a constant
[thirdparty/kernel/stable.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
a6b7a407 24#include <linux/interrupt.h>
1da177e4 25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
31#include <net/ip6_checksum.h>
1da177e4
LT		 32
33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 48#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 49#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 50#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 51#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 52#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 53#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 54#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 55#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 59
1da177e4
LT		 60#ifdef RTL8169_DEBUG
61#define assert(expr) \
5b0384f4
FR		 62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 64 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 65 }
06fa7358
JP		 66#define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 68#else
69#define assert(expr) do {} while (0)
70#define dprintk(fmt, args...) do {} while (0)
71#endif /* RTL8169_DEBUG */
72
b57b7e5a 73#define R8169_MSG_DEFAULT \
f0e837d9 74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 75
477206a0
JD		 76#define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80#define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 82
1da177e4
LT		 83/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 85static const int multicast_filter_limit = 32;
1da177e4 86
aee77e4a 87#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 88#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
89
90#define R8169_REGS_SIZE 256
1d0254dd 91#define R8169_RX_BUF_SIZE (SZ_16K - 1)
1da177e4 92#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 93#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 94#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
95#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
96
97#define RTL8169_TX_TIMEOUT (6*HZ)
98#define RTL8169_PHY_TIMEOUT (10*HZ)
99
100/* write/read MMIO register */
1ef7286e
AS		 101#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
102#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
103#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
104#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
105#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
106#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
1da177e4
LT		 107
108enum mac_version {
85bffe6c
FR		 109 RTL_GIGA_MAC_VER_01 = 0,
110 RTL_GIGA_MAC_VER_02,
111 RTL_GIGA_MAC_VER_03,
112 RTL_GIGA_MAC_VER_04,
113 RTL_GIGA_MAC_VER_05,
114 RTL_GIGA_MAC_VER_06,
115 RTL_GIGA_MAC_VER_07,
116 RTL_GIGA_MAC_VER_08,
117 RTL_GIGA_MAC_VER_09,
118 RTL_GIGA_MAC_VER_10,
119 RTL_GIGA_MAC_VER_11,
120 RTL_GIGA_MAC_VER_12,
121 RTL_GIGA_MAC_VER_13,
122 RTL_GIGA_MAC_VER_14,
123 RTL_GIGA_MAC_VER_15,
124 RTL_GIGA_MAC_VER_16,
125 RTL_GIGA_MAC_VER_17,
126 RTL_GIGA_MAC_VER_18,
127 RTL_GIGA_MAC_VER_19,
128 RTL_GIGA_MAC_VER_20,
129 RTL_GIGA_MAC_VER_21,
130 RTL_GIGA_MAC_VER_22,
131 RTL_GIGA_MAC_VER_23,
132 RTL_GIGA_MAC_VER_24,
133 RTL_GIGA_MAC_VER_25,
134 RTL_GIGA_MAC_VER_26,
135 RTL_GIGA_MAC_VER_27,
136 RTL_GIGA_MAC_VER_28,
137 RTL_GIGA_MAC_VER_29,
138 RTL_GIGA_MAC_VER_30,
139 RTL_GIGA_MAC_VER_31,
140 RTL_GIGA_MAC_VER_32,
141 RTL_GIGA_MAC_VER_33,
70090424 142 RTL_GIGA_MAC_VER_34,
c2218925
HW		 143 RTL_GIGA_MAC_VER_35,
144 RTL_GIGA_MAC_VER_36,
7e18dca1 145 RTL_GIGA_MAC_VER_37,
b3d7b2f2 146 RTL_GIGA_MAC_VER_38,
5598bfe5 147 RTL_GIGA_MAC_VER_39,
c558386b
HW		 148 RTL_GIGA_MAC_VER_40,
149 RTL_GIGA_MAC_VER_41,
57538c4a 150 RTL_GIGA_MAC_VER_42,
58152cd4 151 RTL_GIGA_MAC_VER_43,
45dd95c4 152 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 153 RTL_GIGA_MAC_VER_45,
154 RTL_GIGA_MAC_VER_46,
155 RTL_GIGA_MAC_VER_47,
156 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 157 RTL_GIGA_MAC_VER_49,
158 RTL_GIGA_MAC_VER_50,
159 RTL_GIGA_MAC_VER_51,
85bffe6c 160 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 161};
162
2b7b4318
FR		 163enum rtl_tx_desc_version {
164 RTL_TD_0 = 0,
165 RTL_TD_1 = 1,
166};
167
d58d46b5
FR		 168#define JUMBO_1K ETH_DATA_LEN
169#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
170#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
171#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
172#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
173
174#define _R(NAME,TD,FW,SZ,B) { \
175 .name = NAME, \
176 .txd_version = TD, \
177 .fw_name = FW, \
178 .jumbo_max = SZ, \
179 .jumbo_tx_csum = B \
180}
1da177e4 181
3c6bee1d 182static const struct {
1da177e4 183 const char *name;
2b7b4318 184 enum rtl_tx_desc_version txd_version;
953a12cc 185 const char *fw_name;
d58d46b5
FR		 186 u16 jumbo_max;
187 bool jumbo_tx_csum;
85bffe6c
FR		 188} rtl_chip_infos[] = {
189 /* PCI devices. */
190 [RTL_GIGA_MAC_VER_01] =
d58d46b5 191 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 192 [RTL_GIGA_MAC_VER_02] =
d58d46b5 193 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_03] =
d58d46b5 195 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 196 [RTL_GIGA_MAC_VER_04] =
d58d46b5 197 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 198 [RTL_GIGA_MAC_VER_05] =
d58d46b5 199 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 200 [RTL_GIGA_MAC_VER_06] =
d58d46b5 201 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 202 /* PCI-E devices. */
203 [RTL_GIGA_MAC_VER_07] =
d58d46b5 204 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 205 [RTL_GIGA_MAC_VER_08] =
d58d46b5 206 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 207 [RTL_GIGA_MAC_VER_09] =
d58d46b5 208 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 209 [RTL_GIGA_MAC_VER_10] =
d58d46b5 210 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 211 [RTL_GIGA_MAC_VER_11] =
d58d46b5 212 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 213 [RTL_GIGA_MAC_VER_12] =
d58d46b5 214 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 215 [RTL_GIGA_MAC_VER_13] =
d58d46b5 216 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 217 [RTL_GIGA_MAC_VER_14] =
d58d46b5 218 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 219 [RTL_GIGA_MAC_VER_15] =
d58d46b5 220 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 221 [RTL_GIGA_MAC_VER_16] =
d58d46b5 222 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 223 [RTL_GIGA_MAC_VER_17] =
f75761b6 224 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 225 [RTL_GIGA_MAC_VER_18] =
d58d46b5 226 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 227 [RTL_GIGA_MAC_VER_19] =
d58d46b5 228 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 229 [RTL_GIGA_MAC_VER_20] =
d58d46b5 230 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 231 [RTL_GIGA_MAC_VER_21] =
d58d46b5 232 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 233 [RTL_GIGA_MAC_VER_22] =
d58d46b5 234 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 235 [RTL_GIGA_MAC_VER_23] =
d58d46b5 236 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 237 [RTL_GIGA_MAC_VER_24] =
d58d46b5 238 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 239 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 240 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
241 JUMBO_9K, false),
85bffe6c 242 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 243 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
244 JUMBO_9K, false),
85bffe6c 245 [RTL_GIGA_MAC_VER_27] =
d58d46b5 246 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 247 [RTL_GIGA_MAC_VER_28] =
d58d46b5 248 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 249 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 250 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
251 JUMBO_1K, true),
85bffe6c 252 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 253 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
254 JUMBO_1K, true),
85bffe6c 255 [RTL_GIGA_MAC_VER_31] =
d58d46b5 256 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 257 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 258 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
259 JUMBO_9K, false),
85bffe6c 260 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 261 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
262 JUMBO_9K, false),
70090424 263 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 264 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
265 JUMBO_9K, false),
c2218925 266 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 267 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
268 JUMBO_9K, false),
c2218925 269 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 270 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
271 JUMBO_9K, false),
7e18dca1
HW		 272 [RTL_GIGA_MAC_VER_37] =
273 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
274 JUMBO_1K, true),
b3d7b2f2
HW		 275 [RTL_GIGA_MAC_VER_38] =
276 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
277 JUMBO_9K, false),
5598bfe5
HW		 278 [RTL_GIGA_MAC_VER_39] =
279 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
280 JUMBO_1K, true),
c558386b 281 [RTL_GIGA_MAC_VER_40] =
beb330a4 282 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
c558386b
HW		 283 JUMBO_9K, false),
284 [RTL_GIGA_MAC_VER_41] =
285 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
57538c4a 286 [RTL_GIGA_MAC_VER_42] =
287 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
288 JUMBO_9K, false),
58152cd4 289 [RTL_GIGA_MAC_VER_43] =
290 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
291 JUMBO_1K, true),
45dd95c4 292 [RTL_GIGA_MAC_VER_44] =
293 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
294 JUMBO_9K, false),
6e1d0b89
CHL		 295 [RTL_GIGA_MAC_VER_45] =
296 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
297 JUMBO_9K, false),
298 [RTL_GIGA_MAC_VER_46] =
299 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
300 JUMBO_9K, false),
301 [RTL_GIGA_MAC_VER_47] =
302 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
303 JUMBO_1K, false),
304 [RTL_GIGA_MAC_VER_48] =
305 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
306 JUMBO_1K, false),
935e2218
CHL		 307 [RTL_GIGA_MAC_VER_49] =
308 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
309 JUMBO_9K, false),
310 [RTL_GIGA_MAC_VER_50] =
311 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
312 JUMBO_9K, false),
313 [RTL_GIGA_MAC_VER_51] =
314 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
315 JUMBO_9K, false),
953a12cc 316};
85bffe6c 317#undef _R
953a12cc 318
bcf0bf90
FR		 319enum cfg_version {
320 RTL_CFG_0 = 0x00,
321 RTL_CFG_1,
322 RTL_CFG_2
323};
324
9baa3c34 325static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 326 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
610c9087 328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
d81bf551 329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 332 { PCI_VENDOR_ID_DLINK, 0x4300,
333 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 334 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 336 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 337 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
338 { PCI_VENDOR_ID_LINKSYS, 0x1032,
339 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 340 { 0x0001, 0x8168,
341 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 342 {0,},
343};
344
345MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
346
27896c83 347static int use_dac = -1;
b57b7e5a
SH		 348static struct {
349 u32 msg_enable;
350} debug = { -1 };
1da177e4 351
07d3f51f
FR		 352enum rtl_registers {
353 MAC0 = 0, /* Ethernet hardware address. */
773d2021 354 MAC4 = 4,
07d3f51f
FR		 355 MAR0 = 8, /* Multicast filter. */
356 CounterAddrLow = 0x10,
357 CounterAddrHigh = 0x14,
358 TxDescStartAddrLow = 0x20,
359 TxDescStartAddrHigh = 0x24,
360 TxHDescStartAddrLow = 0x28,
361 TxHDescStartAddrHigh = 0x2c,
362 FLASH = 0x30,
363 ERSR = 0x36,
364 ChipCmd = 0x37,
365 TxPoll = 0x38,
366 IntrMask = 0x3c,
367 IntrStatus = 0x3e,
4f6b00e5 368
07d3f51f 369 TxConfig = 0x40,
4f6b00e5
HW		 370#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
371#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 372
4f6b00e5
HW		 373 RxConfig = 0x44,
374#define RX128_INT_EN (1 << 15) /* 8111c and later */
375#define RX_MULTI_EN (1 << 14) /* 8111c only */
376#define RXCFG_FIFO_SHIFT 13
377 /* No threshold before first PCI xfer */
378#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 379#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 380#define RXCFG_DMA_SHIFT 8
381 /* Unlimited maximum PCI burst. */
382#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 383
07d3f51f
FR		 384 RxMissed = 0x4c,
385 Cfg9346 = 0x50,
386 Config0 = 0x51,
387 Config1 = 0x52,
388 Config2 = 0x53,
d387b427
FR		 389#define PME_SIGNAL (1 << 5) /* 8168c and later */
390
07d3f51f
FR		 391 Config3 = 0x54,
392 Config4 = 0x55,
393 Config5 = 0x56,
394 MultiIntr = 0x5c,
395 PHYAR = 0x60,
07d3f51f
FR		 396 PHYstatus = 0x6c,
397 RxMaxSize = 0xda,
398 CPlusCmd = 0xe0,
399 IntrMitigate = 0xe2,
50970831
FR		 400
401#define RTL_COALESCE_MASK 0x0f
402#define RTL_COALESCE_SHIFT 4
403#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
404#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
405
07d3f51f
FR		 406 RxDescAddrLow = 0xe4,
407 RxDescAddrHigh = 0xe8,
f0298f81 408 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
409
410#define NoEarlyTx 0x3f /* Max value : no early transmit. */
411
412 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
413
414#define TxPacketMax (8064 >> 7)
3090bd9a 415#define EarlySize 0x27
f0298f81 416
07d3f51f
FR		 417 FuncEvent = 0xf0,
418 FuncEventMask = 0xf4,
419 FuncPresetState = 0xf8,
935e2218
CHL		 420 IBCR0 = 0xf8,
421 IBCR2 = 0xf9,
422 IBIMR0 = 0xfa,
423 IBISR0 = 0xfb,
07d3f51f 424 FuncForceEvent = 0xfc,
1da177e4
LT		 425};
426
f162a5d1
FR		 427enum rtl8110_registers {
428 TBICSR = 0x64,
429 TBI_ANAR = 0x68,
430 TBI_LPAR = 0x6a,
431};
432
433enum rtl8168_8101_registers {
434 CSIDR = 0x64,
435 CSIAR = 0x68,
436#define CSIAR_FLAG 0x80000000
437#define CSIAR_WRITE_CMD 0x80000000
438#define CSIAR_BYTE_ENABLE 0x0f
439#define CSIAR_BYTE_ENABLE_SHIFT 12
440#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 441#define CSIAR_FUNC_CARD 0x00000000
442#define CSIAR_FUNC_SDIO 0x00010000
443#define CSIAR_FUNC_NIC 0x00020000
45dd95c4 444#define CSIAR_FUNC_NIC2 0x00010000
065c27c1 445 PMCH = 0x6f,
f162a5d1
FR		 446 EPHYAR = 0x80,
447#define EPHYAR_FLAG 0x80000000
448#define EPHYAR_WRITE_CMD 0x80000000
449#define EPHYAR_REG_MASK 0x1f
450#define EPHYAR_REG_SHIFT 16
451#define EPHYAR_DATA_MASK 0xffff
5a5e4443 452 DLLPR = 0xd0,
4f6b00e5 453#define PFM_EN (1 << 6)
6e1d0b89 454#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 455 DBG_REG = 0xd1,
456#define FIX_NAK_1 (1 << 4)
457#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 458 TWSI = 0xd2,
459 MCU = 0xd3,
4f6b00e5 460#define NOW_IS_OOB (1 << 7)
c558386b
HW		 461#define TX_EMPTY (1 << 5)
462#define RX_EMPTY (1 << 4)
463#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 464#define EN_NDP (1 << 3)
465#define EN_OOB_RESET (1 << 2)
c558386b 466#define LINK_LIST_RDY (1 << 1)
daf9df6d 467 EFUSEAR = 0xdc,
468#define EFUSEAR_FLAG 0x80000000
469#define EFUSEAR_WRITE_CMD 0x80000000
470#define EFUSEAR_READ_CMD 0x00000000
471#define EFUSEAR_REG_MASK 0x03ff
472#define EFUSEAR_REG_SHIFT 8
473#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 474 MISC_1 = 0xf2,
475#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 476};
477
c0e45c1c 478enum rtl8168_registers {
4f6b00e5
HW		 479 LED_FREQ = 0x1a,
480 EEE_LED = 0x1b,
b646d900 481 ERIDR = 0x70,
482 ERIAR = 0x74,
483#define ERIAR_FLAG 0x80000000
484#define ERIAR_WRITE_CMD 0x80000000
485#define ERIAR_READ_CMD 0x00000000
486#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 487#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 488#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
489#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
490#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 491#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 492#define ERIAR_MASK_SHIFT 12
493#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
494#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 495#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 496#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 497#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 498 EPHY_RXER_NUM = 0x7c,
499 OCPDR = 0xb0, /* OCP GPHY access */
500#define OCPDR_WRITE_CMD 0x80000000
501#define OCPDR_READ_CMD 0x00000000
502#define OCPDR_REG_MASK 0x7f
503#define OCPDR_GPHY_REG_SHIFT 16
504#define OCPDR_DATA_MASK 0xffff
505 OCPAR = 0xb4,
506#define OCPAR_FLAG 0x80000000
507#define OCPAR_GPHY_WRITE_CMD 0x8000f060
508#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 509 GPHY_OCP = 0xb8,
01dc7fec 510 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
511 MISC = 0xf0, /* 8168e only. */
cecb5fd7 512#define TXPLA_RST (1 << 29)
5598bfe5 513#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 514#define PWM_EN (1 << 22)
c558386b 515#define RXDV_GATED_EN (1 << 19)
5598bfe5 516#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 517};
518
07d3f51f 519enum rtl_register_content {
1da177e4 520 /* InterruptStatusBits */
07d3f51f
FR		 521 SYSErr = 0x8000,
522 PCSTimeout = 0x4000,
523 SWInt = 0x0100,
524 TxDescUnavail = 0x0080,
525 RxFIFOOver = 0x0040,
526 LinkChg = 0x0020,
527 RxOverflow = 0x0010,
528 TxErr = 0x0008,
529 TxOK = 0x0004,
530 RxErr = 0x0002,
531 RxOK = 0x0001,
1da177e4
LT		 532
533 /* RxStatusDesc */
e03f33af 534 RxBOVF = (1 << 24),
9dccf611
FR		 535 RxFOVF = (1 << 23),
536 RxRWT = (1 << 22),
537 RxRES = (1 << 21),
538 RxRUNT = (1 << 20),
539 RxCRC = (1 << 19),
1da177e4
LT		 540
541 /* ChipCmdBits */
4f6b00e5 542 StopReq = 0x80,
07d3f51f
FR		 543 CmdReset = 0x10,
544 CmdRxEnb = 0x08,
545 CmdTxEnb = 0x04,
546 RxBufEmpty = 0x01,
1da177e4 547
275391a4
FR		 548 /* TXPoll register p.5 */
549 HPQ = 0x80, /* Poll cmd on the high prio queue */
550 NPQ = 0x40, /* Poll cmd on the low prio queue */
551 FSWInt = 0x01, /* Forced software interrupt */
552
1da177e4 553 /* Cfg9346Bits */
07d3f51f
FR		 554 Cfg9346_Lock = 0x00,
555 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 556
557 /* rx_mode_bits */
07d3f51f
FR		 558 AcceptErr = 0x20,
559 AcceptRunt = 0x10,
560 AcceptBroadcast = 0x08,
561 AcceptMulticast = 0x04,
562 AcceptMyPhys = 0x02,
563 AcceptAllPhys = 0x01,
1687b566 564#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 565
1da177e4
LT		 566 /* TxConfigBits */
567 TxInterFrameGapShift = 24,
568 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
569
5d06a99f 570 /* Config1 register p.24 */
f162a5d1
FR		 571 LEDS1 = (1 << 7),
572 LEDS0 = (1 << 6),
f162a5d1
FR		 573 Speed_down = (1 << 4),
574 MEMMAP = (1 << 3),
575 IOMAP = (1 << 2),
576 VPD = (1 << 1),
5d06a99f
FR		 577 PMEnable = (1 << 0), /* Power Management Enable */
578
6dccd16b 579 /* Config2 register p. 25 */
57538c4a 580 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 581 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 582 PCI_Clock_66MHz = 0x01,
583 PCI_Clock_33MHz = 0x00,
584
61a4dcc2
FR		 585 /* Config3 register p.25 */
586 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
587 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 588 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 589 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 590 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 591
d58d46b5
FR		 592 /* Config4 register */
593 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
594
5d06a99f 595 /* Config5 register p.27 */
61a4dcc2
FR		 596 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
597 MWF = (1 << 5), /* Accept Multicast wakeup frame */
598 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 599 Spi_en = (1 << 3),
61a4dcc2 600 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 601 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 602 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 603
1da177e4
LT		 604 /* TBICSR p.28 */
605 TBIReset = 0x80000000,
606 TBILoopback = 0x40000000,
607 TBINwEnable = 0x20000000,
608 TBINwRestart = 0x10000000,
609 TBILinkOk = 0x02000000,
610 TBINwComplete = 0x01000000,
611
612 /* CPlusCmd p.31 */
f162a5d1
FR		 613 EnableBist = (1 << 15), // 8168 8101
614 Mac_dbgo_oe = (1 << 14), // 8168 8101
615 Normal_mode = (1 << 13), // unused
616 Force_half_dup = (1 << 12), // 8168 8101
617 Force_rxflow_en = (1 << 11), // 8168 8101
618 Force_txflow_en = (1 << 10), // 8168 8101
619 Cxpl_dbg_sel = (1 << 9), // 8168 8101
620 ASF = (1 << 8), // 8168 8101
621 PktCntrDisable = (1 << 7), // 8168 8101
622 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 623 RxVlan = (1 << 6),
624 RxChkSum = (1 << 5),
625 PCIDAC = (1 << 4),
626 PCIMulRW = (1 << 3),
0e485150
FR		 627 INTT_0 = 0x0000, // 8168
628 INTT_1 = 0x0001, // 8168
629 INTT_2 = 0x0002, // 8168
630 INTT_3 = 0x0003, // 8168
1da177e4
LT		 631
632 /* rtl8169_PHYstatus */
07d3f51f
FR		 633 TBI_Enable = 0x80,
634 TxFlowCtrl = 0x40,
635 RxFlowCtrl = 0x20,
636 _1000bpsF = 0x10,
637 _100bps = 0x08,
638 _10bps = 0x04,
639 LinkStatus = 0x02,
640 FullDup = 0x01,
1da177e4 641
1da177e4 642 /* _TBICSRBit */
07d3f51f 643 TBILinkOK = 0x02000000,
d4a3a0fc 644
6e85d5ad
CV		 645 /* ResetCounterCommand */
646 CounterReset = 0x1,
647
d4a3a0fc 648 /* DumpCounterCommand */
07d3f51f 649 CounterDump = 0x8,
6e1d0b89
CHL		 650
651 /* magic enable v2 */
652 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 653};
654
2b7b4318
FR		 655enum rtl_desc_bit {
656 /* First doubleword. */
1da177e4
LT		 657 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
658 RingEnd = (1 << 30), /* End of descriptor ring */
659 FirstFrag = (1 << 29), /* First segment of a packet */
660 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 661};
662
663/* Generic case. */
664enum rtl_tx_desc_bit {
665 /* First doubleword. */
666 TD_LSO = (1 << 27), /* Large Send Offload */
667#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 668
2b7b4318
FR		 669 /* Second doubleword. */
670 TxVlanTag = (1 << 17), /* Add VLAN tag */
671};
672
673/* 8169, 8168b and 810x except 8102e. */
674enum rtl_tx_desc_bit_0 {
675 /* First doubleword. */
676#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
677 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
678 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
679 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
680};
681
682/* 8102e, 8168c and beyond. */
683enum rtl_tx_desc_bit_1 {
bdfa4ed6 684 /* First doubleword. */
685 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 686 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 687#define GTTCPHO_SHIFT 18
e974604b 688#define GTTCPHO_MAX 0x7fU
bdfa4ed6 689
2b7b4318 690 /* Second doubleword. */
e974604b 691#define TCPHO_SHIFT 18
692#define TCPHO_MAX 0x3ffU
2b7b4318 693#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 694 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
695 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 696 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
697 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
698};
1da177e4 699
2b7b4318 700enum rtl_rx_desc_bit {
1da177e4
LT		 701 /* Rx private */
702 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 703 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 704
705#define RxProtoUDP (PID1)
706#define RxProtoTCP (PID0)
707#define RxProtoIP (PID1 | PID0)
708#define RxProtoMask RxProtoIP
709
710 IPFail = (1 << 16), /* IP checksum failed */
711 UDPFail = (1 << 15), /* UDP/IP checksum failed */
712 TCPFail = (1 << 14), /* TCP/IP checksum failed */
713 RxVlanTag = (1 << 16), /* VLAN tag available */
714};
715
716#define RsvdMask 0x3fffc000
717
718struct TxDesc {
6cccd6e7
REB		 719 __le32 opts1;
720 __le32 opts2;
721 __le64 addr;
1da177e4
LT		 722};
723
724struct RxDesc {
6cccd6e7
REB		 725 __le32 opts1;
726 __le32 opts2;
727 __le64 addr;
1da177e4
LT		 728};
729
730struct ring_info {
731 struct sk_buff *skb;
732 u32 len;
733 u8 __pad[sizeof(void *) - sizeof(u32)];
734};
735
355423d0
IV		 736struct rtl8169_counters {
737 __le64 tx_packets;
738 __le64 rx_packets;
739 __le64 tx_errors;
740 __le32 rx_errors;
741 __le16 rx_missed;
742 __le16 align_errors;
743 __le32 tx_one_collision;
744 __le32 tx_multi_collision;
745 __le64 rx_unicast;
746 __le64 rx_broadcast;
747 __le32 rx_multicast;
748 __le16 tx_aborted;
749 __le16 tx_underun;
750};
751
6e85d5ad
CV		 752struct rtl8169_tc_offsets {
753 bool inited;
754 __le64 tx_errors;
755 __le32 tx_multi_collision;
6e85d5ad
CV		 756 __le16 tx_aborted;
757};
758
da78dbff 759enum rtl_flag {
6c4a70c5 760 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 761 RTL_FLAG_TASK_SLOW_PENDING,
762 RTL_FLAG_TASK_RESET_PENDING,
763 RTL_FLAG_TASK_PHY_PENDING,
764 RTL_FLAG_MAX
765};
766
8027aa24
JW		 767struct rtl8169_stats {
768 u64 packets;
769 u64 bytes;
770 struct u64_stats_sync syncp;
771};
772
1da177e4
LT		 773struct rtl8169_private {
774 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 775 struct pci_dev *pci_dev;
c4028958 776 struct net_device *dev;
bea3348e 777 struct napi_struct napi;
b57b7e5a 778 u32 msg_enable;
2b7b4318
FR		 779 u16 txd_version;
780 u16 mac_version;
1da177e4
LT		 781 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
782 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 783 u32 dirty_tx;
8027aa24
JW		 784 struct rtl8169_stats rx_stats;
785 struct rtl8169_stats tx_stats;
1da177e4
LT		 786 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
787 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
788 dma_addr_t TxPhyAddr;
789 dma_addr_t RxPhyAddr;
6f0333b8 790 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 791 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 792 struct timer_list timer;
793 u16 cp_cmd;
da78dbff
FR		 794
795 u16 event_slow;
50970831 796 const struct rtl_coalesce_info *coalesce_info;
c0e45c1c 797
798 struct mdio_ops {
24192210
FR		 799 void (*write)(struct rtl8169_private *, int, int);
800 int (*read)(struct rtl8169_private *, int);
c0e45c1c 801 } mdio_ops;
802
065c27c1 803 struct pll_power_ops {
804 void (*down)(struct rtl8169_private *);
805 void (*up)(struct rtl8169_private *);
806 } pll_power_ops;
807
d58d46b5
FR		 808 struct jumbo_ops {
809 void (*enable)(struct rtl8169_private *);
810 void (*disable)(struct rtl8169_private *);
811 } jumbo_ops;
812
beb1fe18 813 struct csi_ops {
52989f0e
FR		 814 void (*write)(struct rtl8169_private *, int, int);
815 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 816 } csi_ops;
817
54405cde 818 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
6fa1ba61
PR		 819 int (*get_link_ksettings)(struct net_device *,
820 struct ethtool_link_ksettings *);
4da19633 821 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 822 void (*hw_start)(struct net_device *);
4da19633 823 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1ef7286e 824 unsigned int (*link_ok)(struct rtl8169_private *tp);
8b4ab28d 825 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
5888d3fc 826 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 827
828 struct {
da78dbff
FR		 829 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
830 struct mutex mutex;
4422bcd4
FR		 831 struct work_struct work;
832 } wk;
833
ccdffb9a 834 struct mii_if_info mii;
42020320
CV		 835 dma_addr_t counters_phys_addr;
836 struct rtl8169_counters *counters;
6e85d5ad 837 struct rtl8169_tc_offsets tc_offset;
e1759441 838 u32 saved_wolopts;
e03f33af 839 u32 opts1_mask;
f1e02ed1 840
b6ffd97f
FR		 841 struct rtl_fw {
842 const struct firmware *fw;
1c361efb
FR		 843
844#define RTL_VER_SIZE 32
845
846 char version[RTL_VER_SIZE];
847
848 struct rtl_fw_phy_action {
849 __le32 *code;
850 size_t size;
851 } phy_action;
b6ffd97f 852 } *rtl_fw;
497888cf 853#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 854
855 u32 ocp_base;
1da177e4
LT		 856};
857
979b6c13 858MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 859MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 860module_param(use_dac, int, 0);
4300e8c7 861MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 862module_param_named(debug, debug.msg_enable, int, 0);
863MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 864MODULE_LICENSE("GPL");
865MODULE_VERSION(RTL8169_VERSION);
bca03d5f 866MODULE_FIRMWARE(FIRMWARE_8168D_1);
867MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 868MODULE_FIRMWARE(FIRMWARE_8168E_1);
869MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 870MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 871MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 872MODULE_FIRMWARE(FIRMWARE_8168F_1);
873MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 874MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 875MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 876MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 877MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 878MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 879MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 880MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 881MODULE_FIRMWARE(FIRMWARE_8168H_1);
882MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 883MODULE_FIRMWARE(FIRMWARE_8107E_1);
884MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 885
1e1205b7
HK		 886static inline struct device *tp_to_dev(struct rtl8169_private *tp)
887{
888 return &tp->pci_dev->dev;
889}
890
da78dbff
FR		 891static void rtl_lock_work(struct rtl8169_private *tp)
892{
893 mutex_lock(&tp->wk.mutex);
894}
895
896static void rtl_unlock_work(struct rtl8169_private *tp)
897{
898 mutex_unlock(&tp->wk.mutex);
899}
900
cb73200c 901static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
d58d46b5 902{
cb73200c 903 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
7d7903b2 904 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 905}
906
ffc46952
FR		 907struct rtl_cond {
908 bool (*check)(struct rtl8169_private *);
909 const char *msg;
910};
911
912static void rtl_udelay(unsigned int d)
913{
914 udelay(d);
915}
916
917static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
918 void (*delay)(unsigned int), unsigned int d, int n,
919 bool high)
920{
921 int i;
922
923 for (i = 0; i < n; i++) {
924 delay(d);
925 if (c->check(tp) == high)
926 return true;
927 }
82e316ef
FR		 928 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
929 c->msg, !high, n, d);
ffc46952
FR		 930 return false;
931}
932
933static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
934 const struct rtl_cond *c,
935 unsigned int d, int n)
936{
937 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
938}
939
940static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
941 const struct rtl_cond *c,
942 unsigned int d, int n)
943{
944 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
945}
946
947static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
948 const struct rtl_cond *c,
949 unsigned int d, int n)
950{
951 return rtl_loop_wait(tp, c, msleep, d, n, true);
952}
953
954static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
955 const struct rtl_cond *c,
956 unsigned int d, int n)
957{
958 return rtl_loop_wait(tp, c, msleep, d, n, false);
959}
960
961#define DECLARE_RTL_COND(name) \
962static bool name ## _check(struct rtl8169_private *); \
963 \
964static const struct rtl_cond name = { \
965 .check = name ## _check, \
966 .msg = #name \
967}; \
968 \
969static bool name ## _check(struct rtl8169_private *tp)
970
c558386b
HW		 971static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
972{
973 if (reg & 0xffff0001) {
974 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
975 return true;
976 }
977 return false;
978}
979
980DECLARE_RTL_COND(rtl_ocp_gphy_cond)
981{
1ef7286e 982 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
c558386b
HW		 983}
984
985static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
986{
c558386b
HW		 987 if (rtl_ocp_reg_failure(tp, reg))
988 return;
989
1ef7286e 990 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 991
992 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
993}
994
995static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
996{
c558386b
HW		 997 if (rtl_ocp_reg_failure(tp, reg))
998 return 0;
999
1ef7286e 1000 RTL_W32(tp, GPHY_OCP, reg << 15);
c558386b
HW		 1001
1002 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1ef7286e 1003 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
c558386b
HW		 1004}
1005
c558386b
HW		 1006static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1007{
c558386b
HW		 1008 if (rtl_ocp_reg_failure(tp, reg))
1009 return;
1010
1ef7286e 1011 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1012}
1013
1014static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1015{
c558386b
HW		 1016 if (rtl_ocp_reg_failure(tp, reg))
1017 return 0;
1018
1ef7286e 1019 RTL_W32(tp, OCPDR, reg << 15);
c558386b 1020
1ef7286e 1021 return RTL_R32(tp, OCPDR);
c558386b
HW		 1022}
1023
1024#define OCP_STD_PHY_BASE 0xa400
1025
1026static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1027{
1028 if (reg == 0x1f) {
1029 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1030 return;
1031 }
1032
1033 if (tp->ocp_base != OCP_STD_PHY_BASE)
1034 reg -= 0x10;
1035
1036 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1037}
1038
1039static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1040{
1041 if (tp->ocp_base != OCP_STD_PHY_BASE)
1042 reg -= 0x10;
1043
1044 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1045}
1046
eee3786f 1047static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1048{
1049 if (reg == 0x1f) {
1050 tp->ocp_base = value << 4;
1051 return;
1052 }
1053
1054 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1055}
1056
1057static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1058{
1059 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1060}
1061
ffc46952
FR		 1062DECLARE_RTL_COND(rtl_phyar_cond)
1063{
1ef7286e 1064 return RTL_R32(tp, PHYAR) & 0x80000000;
ffc46952
FR		 1065}
1066
24192210 1067static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1068{
1ef7286e 1069 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1070
ffc46952 1071 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1072 /*
81a95f04
TT		 1073 * According to hardware specs a 20us delay is required after write
1074 * complete indication, but before sending next command.
024a07ba 1075 */
81a95f04 1076 udelay(20);
1da177e4
LT		 1077}
1078
24192210 1079static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1080{
ffc46952 1081 int value;
1da177e4 1082
1ef7286e 1083 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1084
ffc46952 1085 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1ef7286e 1086 RTL_R32(tp, PHYAR) & 0xffff : ~0;
ffc46952 1087
81a95f04
TT		 1088 /*
1089 * According to hardware specs a 20us delay is required after read
1090 * complete indication, but before sending next command.
1091 */
1092 udelay(20);
1093
1da177e4
LT		 1094 return value;
1095}
1096
935e2218
CHL		 1097DECLARE_RTL_COND(rtl_ocpar_cond)
1098{
1ef7286e 1099 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
935e2218
CHL		 1100}
1101
24192210 1102static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1103{
1ef7286e
AS		 1104 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1105 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
1106 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 1107
ffc46952 1108 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1109}
1110
24192210 1111static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1112{
24192210
FR		 1113 r8168dp_1_mdio_access(tp, reg,
1114 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1115}
1116
24192210 1117static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1118{
24192210 1119 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1120
1121 mdelay(1);
1ef7286e
AS		 1122 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1123 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 1124
ffc46952 1125 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1ef7286e 1126 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1127}
1128
e6de30d6 1129#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1130
1ef7286e 1131static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
e6de30d6 1132{
1ef7286e 1133 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1134}
1135
1ef7286e 1136static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
e6de30d6 1137{
1ef7286e 1138 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1139}
1140
24192210 1141static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1142{
1ef7286e 1143 r8168dp_2_mdio_start(tp);
e6de30d6 1144
24192210 1145 r8169_mdio_write(tp, reg, value);
e6de30d6 1146
1ef7286e 1147 r8168dp_2_mdio_stop(tp);
e6de30d6 1148}
1149
24192210 1150static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1151{
1152 int value;
1153
1ef7286e 1154 r8168dp_2_mdio_start(tp);
e6de30d6 1155
24192210 1156 value = r8169_mdio_read(tp, reg);
e6de30d6 1157
1ef7286e 1158 r8168dp_2_mdio_stop(tp);
e6de30d6 1159
1160 return value;
1161}
1162
4da19633 1163static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1164{
24192210 1165 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1166}
1167
4da19633 1168static int rtl_readphy(struct rtl8169_private *tp, int location)
1169{
24192210 1170 return tp->mdio_ops.read(tp, location);
4da19633 1171}
1172
1173static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1174{
1175 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1176}
1177
76564428 1178static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1179{
1180 int val;
1181
4da19633 1182 val = rtl_readphy(tp, reg_addr);
76564428 1183 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1184}
1185
ccdffb9a
FR		 1186static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1187 int val)
1188{
1189 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1190
4da19633 1191 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1192}
1193
1194static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1195{
1196 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1197
4da19633 1198 return rtl_readphy(tp, location);
ccdffb9a
FR		 1199}
1200
ffc46952
FR		 1201DECLARE_RTL_COND(rtl_ephyar_cond)
1202{
1ef7286e 1203 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
ffc46952
FR		 1204}
1205
fdf6fc06 1206static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1207{
1ef7286e 1208 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
dacf8154
FR		 1209 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1210
ffc46952
FR		 1211 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1212
1213 udelay(10);
dacf8154
FR		 1214}
1215
fdf6fc06 1216static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1217{
1ef7286e 1218 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
dacf8154 1219
ffc46952 1220 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1ef7286e 1221 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1222}
1223
935e2218
CHL		 1224DECLARE_RTL_COND(rtl_eriar_cond)
1225{
1ef7286e 1226 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
935e2218
CHL		 1227}
1228
fdf6fc06
FR		 1229static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1230 u32 val, int type)
133ac40a 1231{
133ac40a 1232 BUG_ON((addr & 3) || (mask == 0));
1ef7286e
AS		 1233 RTL_W32(tp, ERIDR, val);
1234 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
133ac40a 1235
ffc46952 1236 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1237}
1238
fdf6fc06 1239static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1240{
1ef7286e 1241 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
133ac40a 1242
ffc46952 1243 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1ef7286e 1244 RTL_R32(tp, ERIDR) : ~0;
133ac40a
HW		 1245}
1246
706123d0 1247static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1248 u32 m, int type)
133ac40a
HW		 1249{
1250 u32 val;
1251
fdf6fc06
FR		 1252 val = rtl_eri_read(tp, addr, type);
1253 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1254}
1255
935e2218
CHL		 1256static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1257{
1ef7286e 1258 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218 1259 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1ef7286e 1260 RTL_R32(tp, OCPDR) : ~0;
935e2218
CHL		 1261}
1262
1263static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1264{
1265 return rtl_eri_read(tp, reg, ERIAR_OOB);
1266}
1267
1268static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1269{
1270 switch (tp->mac_version) {
1271 case RTL_GIGA_MAC_VER_27:
1272 case RTL_GIGA_MAC_VER_28:
1273 case RTL_GIGA_MAC_VER_31:
1274 return r8168dp_ocp_read(tp, mask, reg);
1275 case RTL_GIGA_MAC_VER_49:
1276 case RTL_GIGA_MAC_VER_50:
1277 case RTL_GIGA_MAC_VER_51:
1278 return r8168ep_ocp_read(tp, mask, reg);
1279 default:
1280 BUG();
1281 return ~0;
1282 }
1283}
1284
1285static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1286 u32 data)
1287{
1ef7286e
AS		 1288 RTL_W32(tp, OCPDR, data);
1289 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218
CHL		 1290 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1291}
1292
1293static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1294 u32 data)
1295{
1296 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1297 data, ERIAR_OOB);
1298}
1299
1300static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1301{
1302 switch (tp->mac_version) {
1303 case RTL_GIGA_MAC_VER_27:
1304 case RTL_GIGA_MAC_VER_28:
1305 case RTL_GIGA_MAC_VER_31:
1306 r8168dp_ocp_write(tp, mask, reg, data);
1307 break;
1308 case RTL_GIGA_MAC_VER_49:
1309 case RTL_GIGA_MAC_VER_50:
1310 case RTL_GIGA_MAC_VER_51:
1311 r8168ep_ocp_write(tp, mask, reg, data);
1312 break;
1313 default:
1314 BUG();
1315 break;
1316 }
1317}
1318
2a9b4d96
CHL		 1319static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1320{
1321 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1322
1323 ocp_write(tp, 0x1, 0x30, 0x00000001);
1324}
1325
1326#define OOB_CMD_RESET 0x00
1327#define OOB_CMD_DRIVER_START 0x05
1328#define OOB_CMD_DRIVER_STOP 0x06
1329
1330static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1331{
1332 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1333}
1334
1335DECLARE_RTL_COND(rtl_ocp_read_cond)
1336{
1337 u16 reg;
1338
1339 reg = rtl8168_get_ocp_reg(tp);
1340
1341 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1342}
1343
935e2218 1344DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1345{
935e2218
CHL		 1346 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1347}
1348
1349DECLARE_RTL_COND(rtl_ocp_tx_cond)
1350{
1ef7286e 1351 return RTL_R8(tp, IBISR0) & 0x20;
935e2218 1352}
2a9b4d96 1353
003609da
CHL		 1354static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1355{
1ef7286e 1356 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
086ca23d 1357 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1ef7286e
AS		 1358 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1359 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
003609da
CHL		 1360}
1361
935e2218
CHL		 1362static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1363{
1364 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
2a9b4d96
CHL		 1365 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1366}
1367
935e2218 1368static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1369{
935e2218
CHL		 1370 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1371 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1372 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1373}
1374
1375static void rtl8168_driver_start(struct rtl8169_private *tp)
1376{
1377 switch (tp->mac_version) {
1378 case RTL_GIGA_MAC_VER_27:
1379 case RTL_GIGA_MAC_VER_28:
1380 case RTL_GIGA_MAC_VER_31:
1381 rtl8168dp_driver_start(tp);
1382 break;
1383 case RTL_GIGA_MAC_VER_49:
1384 case RTL_GIGA_MAC_VER_50:
1385 case RTL_GIGA_MAC_VER_51:
1386 rtl8168ep_driver_start(tp);
1387 break;
1388 default:
1389 BUG();
1390 break;
1391 }
1392}
2a9b4d96 1393
935e2218
CHL		 1394static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1395{
1396 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
2a9b4d96
CHL		 1397 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1398}
1399
935e2218
CHL		 1400static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1401{
003609da 1402 rtl8168ep_stop_cmac(tp);
935e2218
CHL		 1403 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1404 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1405 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1406}
1407
1408static void rtl8168_driver_stop(struct rtl8169_private *tp)
1409{
1410 switch (tp->mac_version) {
1411 case RTL_GIGA_MAC_VER_27:
1412 case RTL_GIGA_MAC_VER_28:
1413 case RTL_GIGA_MAC_VER_31:
1414 rtl8168dp_driver_stop(tp);
1415 break;
1416 case RTL_GIGA_MAC_VER_49:
1417 case RTL_GIGA_MAC_VER_50:
1418 case RTL_GIGA_MAC_VER_51:
1419 rtl8168ep_driver_stop(tp);
1420 break;
1421 default:
1422 BUG();
1423 break;
1424 }
1425}
1426
9dbe7896 1427static bool r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1428{
1429 u16 reg = rtl8168_get_ocp_reg(tp);
1430
9dbe7896 1431 return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
2a9b4d96
CHL		 1432}
1433
9dbe7896 1434static bool r8168ep_check_dash(struct rtl8169_private *tp)
935e2218 1435{
9dbe7896 1436 return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
935e2218
CHL		 1437}
1438
9dbe7896 1439static bool r8168_check_dash(struct rtl8169_private *tp)
935e2218
CHL		 1440{
1441 switch (tp->mac_version) {
1442 case RTL_GIGA_MAC_VER_27:
1443 case RTL_GIGA_MAC_VER_28:
1444 case RTL_GIGA_MAC_VER_31:
1445 return r8168dp_check_dash(tp);
1446 case RTL_GIGA_MAC_VER_49:
1447 case RTL_GIGA_MAC_VER_50:
1448 case RTL_GIGA_MAC_VER_51:
1449 return r8168ep_check_dash(tp);
1450 default:
9dbe7896 1451 return false;
935e2218
CHL		 1452 }
1453}
1454
c28aa385 1455struct exgmac_reg {
1456 u16 addr;
1457 u16 mask;
1458 u32 val;
1459};
1460
fdf6fc06 1461static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1462 const struct exgmac_reg *r, int len)
1463{
1464 while (len-- > 0) {
fdf6fc06 1465 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1466 r++;
1467 }
1468}
1469
ffc46952
FR		 1470DECLARE_RTL_COND(rtl_efusear_cond)
1471{
1ef7286e 1472 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
ffc46952
FR		 1473}
1474
fdf6fc06 1475static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1476{
1ef7286e 1477 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
daf9df6d 1478
ffc46952 1479 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1ef7286e 1480 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1481}
1482
9085cdfa
FR		 1483static u16 rtl_get_events(struct rtl8169_private *tp)
1484{
1ef7286e 1485 return RTL_R16(tp, IntrStatus);
9085cdfa
FR		 1486}
1487
1488static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1489{
1ef7286e 1490 RTL_W16(tp, IntrStatus, bits);
9085cdfa
FR		 1491 mmiowb();
1492}
1493
1494static void rtl_irq_disable(struct rtl8169_private *tp)
1495{
1ef7286e 1496 RTL_W16(tp, IntrMask, 0);
9085cdfa
FR		 1497 mmiowb();
1498}
1499
3e990ff5
FR		 1500static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1501{
1ef7286e 1502 RTL_W16(tp, IntrMask, bits);
3e990ff5
FR		 1503}
1504
da78dbff
FR		 1505#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1506#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1507#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1508
1509static void rtl_irq_enable_all(struct rtl8169_private *tp)
1510{
1511 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1512}
1513
811fd301 1514static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1515{
9085cdfa 1516 rtl_irq_disable(tp);
da78dbff 1517 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1ef7286e 1518 RTL_R8(tp, ChipCmd);
1da177e4
LT		 1519}
1520
4da19633 1521static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1522{
1ef7286e 1523 return RTL_R32(tp, TBICSR) & TBIReset;
1da177e4
LT		 1524}
1525
4da19633 1526static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1527{
4da19633 1528 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1529}
1530
1ef7286e 1531static unsigned int rtl8169_tbi_link_ok(struct rtl8169_private *tp)
1da177e4 1532{
1ef7286e 1533 return RTL_R32(tp, TBICSR) & TBILinkOk;
1da177e4
LT		 1534}
1535
1ef7286e 1536static unsigned int rtl8169_xmii_link_ok(struct rtl8169_private *tp)
1da177e4 1537{
1ef7286e 1538 return RTL_R8(tp, PHYstatus) & LinkStatus;
1da177e4
LT		 1539}
1540
4da19633 1541static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1542{
1ef7286e 1543 RTL_W32(tp, TBICSR, RTL_R32(tp, TBICSR) | TBIReset);
1da177e4
LT		 1544}
1545
4da19633 1546static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1547{
1548 unsigned int val;
1549
4da19633 1550 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1551 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1552}
1553
70090424
HW		 1554static void rtl_link_chg_patch(struct rtl8169_private *tp)
1555{
70090424
HW		 1556 struct net_device *dev = tp->dev;
1557
1558 if (!netif_running(dev))
1559 return;
1560
b3d7b2f2
HW		 1561 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1562 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1ef7286e 1563 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1564 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1565 ERIAR_EXGMAC);
1566 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1567 ERIAR_EXGMAC);
1ef7286e 1568 } else if (RTL_R8(tp, PHYstatus) & _100bps) {
fdf6fc06
FR		 1569 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1570 ERIAR_EXGMAC);
1571 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1572 ERIAR_EXGMAC);
70090424 1573 } else {
fdf6fc06
FR		 1574 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1575 ERIAR_EXGMAC);
1576 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1577 ERIAR_EXGMAC);
70090424
HW		 1578 }
1579 /* Reset packet filter */
706123d0 1580 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1581 ERIAR_EXGMAC);
706123d0 1582 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1583 ERIAR_EXGMAC);
c2218925
HW		 1584 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1585 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1ef7286e 1586 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1587 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1588 ERIAR_EXGMAC);
1589 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1590 ERIAR_EXGMAC);
c2218925 1591 } else {
fdf6fc06
FR		 1592 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1593 ERIAR_EXGMAC);
1594 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1595 ERIAR_EXGMAC);
c2218925 1596 }
7e18dca1 1597 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1ef7286e 1598 if (RTL_R8(tp, PHYstatus) & _10bps) {
fdf6fc06
FR		 1599 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1600 ERIAR_EXGMAC);
1601 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1602 ERIAR_EXGMAC);
7e18dca1 1603 } else {
fdf6fc06
FR		 1604 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1605 ERIAR_EXGMAC);
7e18dca1 1606 }
70090424
HW		 1607 }
1608}
1609
ef4d5fcc 1610static void rtl8169_check_link_status(struct net_device *dev,
1ef7286e 1611 struct rtl8169_private *tp)
1da177e4 1612{
1e1205b7
HK		 1613 struct device *d = tp_to_dev(tp);
1614
1ef7286e 1615 if (tp->link_ok(tp)) {
70090424 1616 rtl_link_chg_patch(tp);
e1759441 1617 /* This is to cancel a scheduled suspend if there's one. */
1e1205b7 1618 pm_request_resume(d);
1da177e4 1619 netif_carrier_on(dev);
1519e57f
FR		 1620 if (net_ratelimit())
1621 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1622 } else {
1da177e4 1623 netif_carrier_off(dev);
bf82c189 1624 netif_info(tp, ifdown, dev, "link down\n");
1e1205b7 1625 pm_runtime_idle(d);
b57b7e5a 1626 }
1da177e4
LT		 1627}
1628
e1759441
RW		 1629#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1630
1631static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1632{
61a4dcc2 1633 u8 options;
e1759441 1634 u32 wolopts = 0;
61a4dcc2 1635
1ef7286e 1636 options = RTL_R8(tp, Config1);
61a4dcc2 1637 if (!(options & PMEnable))
e1759441 1638 return 0;
61a4dcc2 1639
1ef7286e 1640 options = RTL_R8(tp, Config3);
61a4dcc2 1641 if (options & LinkUp)
e1759441 1642 wolopts |= WAKE_PHY;
6e1d0b89 1643 switch (tp->mac_version) {
ac85bcdb
CHL		 1644 case RTL_GIGA_MAC_VER_34:
1645 case RTL_GIGA_MAC_VER_35:
1646 case RTL_GIGA_MAC_VER_36:
1647 case RTL_GIGA_MAC_VER_37:
1648 case RTL_GIGA_MAC_VER_38:
1649 case RTL_GIGA_MAC_VER_40:
1650 case RTL_GIGA_MAC_VER_41:
1651 case RTL_GIGA_MAC_VER_42:
1652 case RTL_GIGA_MAC_VER_43:
1653 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1654 case RTL_GIGA_MAC_VER_45:
1655 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1656 case RTL_GIGA_MAC_VER_47:
1657 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 1658 case RTL_GIGA_MAC_VER_49:
1659 case RTL_GIGA_MAC_VER_50:
1660 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1661 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1662 wolopts |= WAKE_MAGIC;
1663 break;
1664 default:
1665 if (options & MagicPacket)
1666 wolopts |= WAKE_MAGIC;
1667 break;
1668 }
61a4dcc2 1669
1ef7286e 1670 options = RTL_R8(tp, Config5);
61a4dcc2 1671 if (options & UWF)
e1759441 1672 wolopts |= WAKE_UCAST;
61a4dcc2 1673 if (options & BWF)
e1759441 1674 wolopts |= WAKE_BCAST;
61a4dcc2 1675 if (options & MWF)
e1759441 1676 wolopts |= WAKE_MCAST;
61a4dcc2 1677
e1759441 1678 return wolopts;
61a4dcc2
FR		 1679}
1680
e1759441 1681static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1682{
1683 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1684 struct device *d = tp_to_dev(tp);
5fa80a32
CHL		 1685
1686 pm_runtime_get_noresume(d);
e1759441 1687
da78dbff 1688 rtl_lock_work(tp);
e1759441
RW		 1689
1690 wol->supported = WAKE_ANY;
5fa80a32
CHL		 1691 if (pm_runtime_active(d))
1692 wol->wolopts = __rtl8169_get_wol(tp);
1693 else
1694 wol->wolopts = tp->saved_wolopts;
e1759441 1695
da78dbff 1696 rtl_unlock_work(tp);
5fa80a32
CHL		 1697
1698 pm_runtime_put_noidle(d);
e1759441
RW		 1699}
1700
1701static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1702{
6e1d0b89 1703 unsigned int i, tmp;
350f7596 1704 static const struct {
61a4dcc2
FR		 1705 u32 opt;
1706 u16 reg;
1707 u8 mask;
1708 } cfg[] = {
61a4dcc2 1709 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1710 { WAKE_UCAST, Config5, UWF },
1711 { WAKE_BCAST, Config5, BWF },
1712 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1713 { WAKE_ANY, Config5, LanWake },
1714 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1715 };
851e6022 1716 u8 options;
61a4dcc2 1717
1ef7286e 1718 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
61a4dcc2 1719
6e1d0b89 1720 switch (tp->mac_version) {
ac85bcdb
CHL		 1721 case RTL_GIGA_MAC_VER_34:
1722 case RTL_GIGA_MAC_VER_35:
1723 case RTL_GIGA_MAC_VER_36:
1724 case RTL_GIGA_MAC_VER_37:
1725 case RTL_GIGA_MAC_VER_38:
1726 case RTL_GIGA_MAC_VER_40:
1727 case RTL_GIGA_MAC_VER_41:
1728 case RTL_GIGA_MAC_VER_42:
1729 case RTL_GIGA_MAC_VER_43:
1730 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1731 case RTL_GIGA_MAC_VER_45:
1732 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1733 case RTL_GIGA_MAC_VER_47:
1734 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 1735 case RTL_GIGA_MAC_VER_49:
1736 case RTL_GIGA_MAC_VER_50:
1737 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1738 tmp = ARRAY_SIZE(cfg) - 1;
1739 if (wolopts & WAKE_MAGIC)
706123d0 1740 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1741 0x0dc,
1742 ERIAR_MASK_0100,
1743 MagicPacket_v2,
1744 0x0000,
1745 ERIAR_EXGMAC);
1746 else
706123d0 1747 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1748 0x0dc,
1749 ERIAR_MASK_0100,
1750 0x0000,
1751 MagicPacket_v2,
1752 ERIAR_EXGMAC);
1753 break;
1754 default:
1755 tmp = ARRAY_SIZE(cfg);
1756 break;
1757 }
1758
1759 for (i = 0; i < tmp; i++) {
1ef7286e 1760 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
e1759441 1761 if (wolopts & cfg[i].opt)
61a4dcc2 1762 options |= cfg[i].mask;
1ef7286e 1763 RTL_W8(tp, cfg[i].reg, options);
61a4dcc2
FR		 1764 }
1765
851e6022
FR		 1766 switch (tp->mac_version) {
1767 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1ef7286e 1768 options = RTL_R8(tp, Config1) & ~PMEnable;
851e6022
FR		 1769 if (wolopts)
1770 options |= PMEnable;
1ef7286e 1771 RTL_W8(tp, Config1, options);
851e6022
FR		 1772 break;
1773 default:
1ef7286e 1774 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
d387b427
FR		 1775 if (wolopts)
1776 options |= PME_SIGNAL;
1ef7286e 1777 RTL_W8(tp, Config2, options);
851e6022
FR		 1778 break;
1779 }
1780
1ef7286e 1781 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
e1759441
RW		 1782}
1783
1784static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1785{
1786 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1787 struct device *d = tp_to_dev(tp);
5fa80a32
CHL		 1788
1789 pm_runtime_get_noresume(d);
e1759441 1790
da78dbff 1791 rtl_lock_work(tp);
61a4dcc2 1792
5fa80a32
CHL		 1793 if (pm_runtime_active(d))
1794 __rtl8169_set_wol(tp, wol->wolopts);
1795 else
1796 tp->saved_wolopts = wol->wolopts;
da78dbff
FR		 1797
1798 rtl_unlock_work(tp);
61a4dcc2 1799
1e1205b7 1800 device_set_wakeup_enable(d, wol->wolopts);
ea80907f 1801
5fa80a32
CHL		 1802 pm_runtime_put_noidle(d);
1803
61a4dcc2
FR		 1804 return 0;
1805}
1806
31bd204f
FR		 1807static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1808{
85bffe6c 1809 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1810}
1811
1da177e4
LT		 1812static void rtl8169_get_drvinfo(struct net_device *dev,
1813 struct ethtool_drvinfo *info)
1814{
1815 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1816 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1817
68aad78c
RJ		 1818 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1819 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1820 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1821 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1822 if (!IS_ERR_OR_NULL(rtl_fw))
1823 strlcpy(info->fw_version, rtl_fw->version,
1824 sizeof(info->fw_version));
1da177e4
LT		 1825}
1826
1827static int rtl8169_get_regs_len(struct net_device *dev)
1828{
1829 return R8169_REGS_SIZE;
1830}
1831
1832static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1833 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1834{
1835 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1836 int ret = 0;
1837 u32 reg;
1838
1ef7286e 1839 reg = RTL_R32(tp, TBICSR);
1da177e4
LT		 1840 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1841 (duplex == DUPLEX_FULL)) {
1ef7286e 1842 RTL_W32(tp, TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1da177e4 1843 } else if (autoneg == AUTONEG_ENABLE)
1ef7286e 1844 RTL_W32(tp, TBICSR, reg | TBINwEnable | TBINwRestart);
1da177e4 1845 else {
bf82c189
JP		 1846 netif_warn(tp, link, dev,
1847 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1848 ret = -EOPNOTSUPP;
1849 }
1850
1851 return ret;
1852}
1853
1854static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1855 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1856{
1857 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1858 int giga_ctrl, bmcr;
54405cde 1859 int rc = -EINVAL;
1da177e4 1860
716b50a3 1861 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1862
1863 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1864 int auto_nego;
1865
4da19633 1866 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1867 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1868 ADVERTISE_100HALF | ADVERTISE_100FULL);
1869
1870 if (adv & ADVERTISED_10baseT_Half)
1871 auto_nego |= ADVERTISE_10HALF;
1872 if (adv & ADVERTISED_10baseT_Full)
1873 auto_nego |= ADVERTISE_10FULL;
1874 if (adv & ADVERTISED_100baseT_Half)
1875 auto_nego |= ADVERTISE_100HALF;
1876 if (adv & ADVERTISED_100baseT_Full)
1877 auto_nego |= ADVERTISE_100FULL;
1878
3577aa1b 1879 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1880
4da19633 1881 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1882 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1883
3577aa1b 1884 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1885 if (tp->mii.supports_gmii) {
54405cde
ON		 1886 if (adv & ADVERTISED_1000baseT_Half)
1887 giga_ctrl |= ADVERTISE_1000HALF;
1888 if (adv & ADVERTISED_1000baseT_Full)
1889 giga_ctrl |= ADVERTISE_1000FULL;
1890 } else if (adv & (ADVERTISED_1000baseT_Half |
1891 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1892 netif_info(tp, link, dev,
1893 "PHY does not support 1000Mbps\n");
54405cde 1894 goto out;
bcf0bf90 1895 }
1da177e4 1896
3577aa1b 1897 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1898
4da19633 1899 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1900 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1901 } else {
3577aa1b 1902 if (speed == SPEED_10)
1903 bmcr = 0;
1904 else if (speed == SPEED_100)
1905 bmcr = BMCR_SPEED100;
1906 else
54405cde 1907 goto out;
3577aa1b 1908
1909 if (duplex == DUPLEX_FULL)
1910 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1911 }
1912
4da19633 1913 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1914
cecb5fd7
FR		 1915 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1916 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1917 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1918 rtl_writephy(tp, 0x17, 0x2138);
1919 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1920 } else {
4da19633 1921 rtl_writephy(tp, 0x17, 0x2108);
1922 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1923 }
1924 }
1925
54405cde
ON		 1926 rc = 0;
1927out:
1928 return rc;
1da177e4
LT		 1929}
1930
1931static int rtl8169_set_speed(struct net_device *dev,
54405cde 1932 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1933{
1934 struct rtl8169_private *tp = netdev_priv(dev);
1935 int ret;
1936
54405cde 1937 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1938 if (ret < 0)
1939 goto out;
1da177e4 1940
4876cc1e 1941 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
c4556975
CHL		 1942 (advertising & ADVERTISED_1000baseT_Full) &&
1943 !pci_is_pcie(tp->pci_dev)) {
1da177e4 1944 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1945 }
1946out:
1da177e4
LT		 1947 return ret;
1948}
1949
c8f44aff
MM		 1950static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1951 netdev_features_t features)
1da177e4 1952{
d58d46b5
FR		 1953 struct rtl8169_private *tp = netdev_priv(dev);
1954
2b7b4318 1955 if (dev->mtu > TD_MSS_MAX)
350fb32a 1956 features &= ~NETIF_F_ALL_TSO;
1da177e4 1957
d58d46b5
FR		 1958 if (dev->mtu > JUMBO_1K &&
1959 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1960 features &= ~NETIF_F_IP_CSUM;
1961
350fb32a 1962 return features;
1da177e4
LT		 1963}
1964
da78dbff
FR		 1965static void __rtl8169_set_features(struct net_device *dev,
1966 netdev_features_t features)
1da177e4
LT		 1967{
1968 struct rtl8169_private *tp = netdev_priv(dev);
929a031d 1969 u32 rx_config;
1da177e4 1970
1ef7286e 1971 rx_config = RTL_R32(tp, RxConfig);
929a031d 1972 if (features & NETIF_F_RXALL)
1973 rx_config |= (AcceptErr | AcceptRunt);
1974 else
1975 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 1976
1ef7286e 1977 RTL_W32(tp, RxConfig, rx_config);
350fb32a 1978
929a031d 1979 if (features & NETIF_F_RXCSUM)
1980 tp->cp_cmd |= RxChkSum;
1981 else
1982 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1983
929a031d 1984 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1985 tp->cp_cmd |= RxVlan;
1986 else
1987 tp->cp_cmd &= ~RxVlan;
1988
1ef7286e 1989 tp->cp_cmd |= RTL_R16(tp, CPlusCmd) & ~(RxVlan | RxChkSum);
929a031d 1990
1ef7286e
AS		 1991 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1992 RTL_R16(tp, CPlusCmd);
da78dbff 1993}
1da177e4 1994
da78dbff
FR		 1995static int rtl8169_set_features(struct net_device *dev,
1996 netdev_features_t features)
1997{
1998 struct rtl8169_private *tp = netdev_priv(dev);
1999
929a031d 2000 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2001
da78dbff 2002 rtl_lock_work(tp);
85911d71 2003 if (features ^ dev->features)
929a031d 2004 __rtl8169_set_features(dev, features);
da78dbff 2005 rtl_unlock_work(tp);
1da177e4
LT		 2006
2007 return 0;
2008}
2009
da78dbff 2010
810f4893 2011static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 2012{
df8a39de
JP		 2013 return (skb_vlan_tag_present(skb)) ?
2014 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 2015}
2016
7a8fc77b 2017static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 2018{
2019 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 2020
7a8fc77b 2021 if (opts2 & RxVlanTag)
86a9bad3 2022 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 2023}
2024
6fa1ba61
PR		 2025static int rtl8169_get_link_ksettings_tbi(struct net_device *dev,
2026 struct ethtool_link_ksettings *cmd)
1da177e4
LT		 2027{
2028 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 2029 u32 status;
6fa1ba61 2030 u32 supported, advertising;
1da177e4 2031
6fa1ba61 2032 supported =
1da177e4 2033 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
6fa1ba61 2034 cmd->base.port = PORT_FIBRE;
1da177e4 2035
1ef7286e 2036 status = RTL_R32(tp, TBICSR);
6fa1ba61
PR		 2037 advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2038 cmd->base.autoneg = !!(status & TBINwEnable);
1da177e4 2039
6fa1ba61
PR		 2040 cmd->base.speed = SPEED_1000;
2041 cmd->base.duplex = DUPLEX_FULL; /* Always set */
2042
2043 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2044 supported);
2045 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2046 advertising);
ccdffb9a
FR		 2047
2048 return 0;
1da177e4
LT		 2049}
2050
6fa1ba61
PR		 2051static int rtl8169_get_link_ksettings_xmii(struct net_device *dev,
2052 struct ethtool_link_ksettings *cmd)
1da177e4
LT		 2053{
2054 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 2055
82c01a84 2056 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
2057
2058 return 0;
1da177e4
LT		 2059}
2060
6fa1ba61
PR		 2061static int rtl8169_get_link_ksettings(struct net_device *dev,
2062 struct ethtool_link_ksettings *cmd)
1da177e4
LT		 2063{
2064 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 2065 int rc;
1da177e4 2066
da78dbff 2067 rtl_lock_work(tp);
6fa1ba61 2068 rc = tp->get_link_ksettings(dev, cmd);
da78dbff 2069 rtl_unlock_work(tp);
1da177e4 2070
ccdffb9a 2071 return rc;
1da177e4
LT		 2072}
2073
9e77d7a5
TJ		 2074static int rtl8169_set_link_ksettings(struct net_device *dev,
2075 const struct ethtool_link_ksettings *cmd)
2076{
2077 struct rtl8169_private *tp = netdev_priv(dev);
2078 int rc;
2079 u32 advertising;
2080
2081 if (!ethtool_convert_link_mode_to_legacy_u32(&advertising,
2082 cmd->link_modes.advertising))
2083 return -EINVAL;
2084
2085 del_timer_sync(&tp->timer);
2086
2087 rtl_lock_work(tp);
2088 rc = rtl8169_set_speed(dev, cmd->base.autoneg, cmd->base.speed,
2089 cmd->base.duplex, advertising);
2090 rtl_unlock_work(tp);
2091
2092 return rc;
2093}
2094
1da177e4
LT		 2095static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2096 void *p)
2097{
5b0384f4 2098 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 2099 u32 __iomem *data = tp->mmio_addr;
2100 u32 *dw = p;
2101 int i;
1da177e4 2102
da78dbff 2103 rtl_lock_work(tp);
15edae91
PW		 2104 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2105 memcpy_fromio(dw++, data++, 4);
da78dbff 2106 rtl_unlock_work(tp);
1da177e4
LT		 2107}
2108
b57b7e5a
SH		 2109static u32 rtl8169_get_msglevel(struct net_device *dev)
2110{
2111 struct rtl8169_private *tp = netdev_priv(dev);
2112
2113 return tp->msg_enable;
2114}
2115
2116static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2117{
2118 struct rtl8169_private *tp = netdev_priv(dev);
2119
2120 tp->msg_enable = value;
2121}
2122
d4a3a0fc
SH		 2123static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2124 "tx_packets",
2125 "rx_packets",
2126 "tx_errors",
2127 "rx_errors",
2128 "rx_missed",
2129 "align_errors",
2130 "tx_single_collisions",
2131 "tx_multi_collisions",
2132 "unicast",
2133 "broadcast",
2134 "multicast",
2135 "tx_aborted",
2136 "tx_underrun",
2137};
2138
b9f2c044 2139static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 2140{
b9f2c044
JG		 2141 switch (sset) {
2142 case ETH_SS_STATS:
2143 return ARRAY_SIZE(rtl8169_gstrings);
2144 default:
2145 return -EOPNOTSUPP;
2146 }
d4a3a0fc
SH		 2147}
2148
42020320 2149DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 2150{
1ef7286e 2151 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 2152}
2153
42020320 2154static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
6e85d5ad
CV		 2155{
2156 struct rtl8169_private *tp = netdev_priv(dev);
42020320
CV		 2157 dma_addr_t paddr = tp->counters_phys_addr;
2158 u32 cmd;
6e85d5ad 2159
1ef7286e
AS		 2160 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
2161 RTL_R32(tp, CounterAddrHigh);
42020320 2162 cmd = (u64)paddr & DMA_BIT_MASK(32);
1ef7286e
AS		 2163 RTL_W32(tp, CounterAddrLow, cmd);
2164 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
6e85d5ad 2165
a78e9366 2166 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 2167}
2168
2169static bool rtl8169_reset_counters(struct net_device *dev)
2170{
2171 struct rtl8169_private *tp = netdev_priv(dev);
6e85d5ad
CV		 2172
2173 /*
2174 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2175 * tally counters.
2176 */
2177 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2178 return true;
2179
42020320 2180 return rtl8169_do_counters(dev, CounterReset);
ffc46952
FR		 2181}
2182
6e85d5ad 2183static bool rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 2184{
2185 struct rtl8169_private *tp = netdev_priv(dev);
d4a3a0fc 2186
355423d0
IV		 2187 /*
2188 * Some chips are unable to dump tally counters when the receiver
2189 * is disabled.
2190 */
1ef7286e 2191 if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
6e85d5ad 2192 return true;
d4a3a0fc 2193
42020320 2194 return rtl8169_do_counters(dev, CounterDump);
6e85d5ad
CV		 2195}
2196
2197static bool rtl8169_init_counter_offsets(struct net_device *dev)
2198{
2199 struct rtl8169_private *tp = netdev_priv(dev);
42020320 2200 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 2201 bool ret = false;
2202
2203 /*
2204 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2205 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2206 * reset by a power cycle, while the counter values collected by the
2207 * driver are reset at every driver unload/load cycle.
2208 *
2209 * To make sure the HW values returned by @get_stats64 match the SW
2210 * values, we collect the initial values at first open(*) and use them
2211 * as offsets to normalize the values returned by @get_stats64.
2212 *
2213 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2214 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2215 * set at open time by rtl_hw_start.
2216 */
2217
2218 if (tp->tc_offset.inited)
2219 return true;
2220
2221 /* If both, reset and update fail, propagate to caller. */
2222 if (rtl8169_reset_counters(dev))
2223 ret = true;
2224
2225 if (rtl8169_update_counters(dev))
2226 ret = true;
2227
42020320
CV		 2228 tp->tc_offset.tx_errors = counters->tx_errors;
2229 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2230 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 2231 tp->tc_offset.inited = true;
2232
2233 return ret;
d4a3a0fc
SH		 2234}
2235
355423d0
IV		 2236static void rtl8169_get_ethtool_stats(struct net_device *dev,
2237 struct ethtool_stats *stats, u64 *data)
2238{
2239 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 2240 struct device *d = tp_to_dev(tp);
42020320 2241 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 2242
2243 ASSERT_RTNL();
2244
e0636236
CHL		 2245 pm_runtime_get_noresume(d);
2246
2247 if (pm_runtime_active(d))
2248 rtl8169_update_counters(dev);
2249
2250 pm_runtime_put_noidle(d);
355423d0 2251
42020320
CV		 2252 data[0] = le64_to_cpu(counters->tx_packets);
2253 data[1] = le64_to_cpu(counters->rx_packets);
2254 data[2] = le64_to_cpu(counters->tx_errors);
2255 data[3] = le32_to_cpu(counters->rx_errors);
2256 data[4] = le16_to_cpu(counters->rx_missed);
2257 data[5] = le16_to_cpu(counters->align_errors);
2258 data[6] = le32_to_cpu(counters->tx_one_collision);
2259 data[7] = le32_to_cpu(counters->tx_multi_collision);
2260 data[8] = le64_to_cpu(counters->rx_unicast);
2261 data[9] = le64_to_cpu(counters->rx_broadcast);
2262 data[10] = le32_to_cpu(counters->rx_multicast);
2263 data[11] = le16_to_cpu(counters->tx_aborted);
2264 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 2265}
2266
d4a3a0fc
SH		 2267static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2268{
2269 switch(stringset) {
2270 case ETH_SS_STATS:
2271 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2272 break;
2273 }
2274}
2275
f0903ea3
FF		 2276static int rtl8169_nway_reset(struct net_device *dev)
2277{
2278 struct rtl8169_private *tp = netdev_priv(dev);
2279
2280 return mii_nway_restart(&tp->mii);
2281}
2282
50970831
FR		 2283/*
2284 * Interrupt coalescing
2285 *
2286 * > 1 - the availability of the IntrMitigate (0xe2) register through the
2287 * > 8169, 8168 and 810x line of chipsets
2288 *
2289 * 8169, 8168, and 8136(810x) serial chipsets support it.
2290 *
2291 * > 2 - the Tx timer unit at gigabit speed
2292 *
2293 * The unit of the timer depends on both the speed and the setting of CPlusCmd
2294 * (0xe0) bit 1 and bit 0.
2295 *
2296 * For 8169
2297 * bit[1:0] \ speed 1000M 100M 10M
2298 * 0 0 320ns 2.56us 40.96us
2299 * 0 1 2.56us 20.48us 327.7us
2300 * 1 0 5.12us 40.96us 655.4us
2301 * 1 1 10.24us 81.92us 1.31ms
2302 *
2303 * For the other
2304 * bit[1:0] \ speed 1000M 100M 10M
2305 * 0 0 5us 2.56us 40.96us
2306 * 0 1 40us 20.48us 327.7us
2307 * 1 0 80us 40.96us 655.4us
2308 * 1 1 160us 81.92us 1.31ms
2309 */
2310
2311/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
2312struct rtl_coalesce_scale {
2313 /* Rx / Tx */
2314 u32 nsecs[2];
2315};
2316
2317/* rx/tx scale factors for all CPlusCmd[0:1] cases */
2318struct rtl_coalesce_info {
2319 u32 speed;
2320 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
2321};
2322
2323/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
2324#define rxtx_x1822(r, t) { \
2325 {{(r), (t)}}, \
2326 {{(r)*8, (t)*8}}, \
2327 {{(r)*8*2, (t)*8*2}}, \
2328 {{(r)*8*2*2, (t)*8*2*2}}, \
2329}
2330static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
2331 /* speed delays: rx00 tx00 */
2332 { SPEED_10, rxtx_x1822(40960, 40960) },
2333 { SPEED_100, rxtx_x1822( 2560, 2560) },
2334 { SPEED_1000, rxtx_x1822( 320, 320) },
2335 { 0 },
2336};
2337
2338static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
2339 /* speed delays: rx00 tx00 */
2340 { SPEED_10, rxtx_x1822(40960, 40960) },
2341 { SPEED_100, rxtx_x1822( 2560, 2560) },
2342 { SPEED_1000, rxtx_x1822( 5000, 5000) },
2343 { 0 },
2344};
2345#undef rxtx_x1822
2346
2347/* get rx/tx scale vector corresponding to current speed */
2348static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
2349{
2350 struct rtl8169_private *tp = netdev_priv(dev);
2351 struct ethtool_link_ksettings ecmd;
2352 const struct rtl_coalesce_info *ci;
2353 int rc;
2354
2355 rc = rtl8169_get_link_ksettings(dev, &ecmd);
2356 if (rc < 0)
2357 return ERR_PTR(rc);
2358
2359 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
2360 if (ecmd.base.speed == ci->speed) {
2361 return ci;
2362 }
2363 }
2364
2365 return ERR_PTR(-ELNRNG);
2366}
2367
2368static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2369{
2370 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 2371 const struct rtl_coalesce_info *ci;
2372 const struct rtl_coalesce_scale *scale;
2373 struct {
2374 u32 *max_frames;
2375 u32 *usecs;
2376 } coal_settings [] = {
2377 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
2378 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
2379 }, *p = coal_settings;
2380 int i;
2381 u16 w;
2382
2383 memset(ec, 0, sizeof(*ec));
2384
2385 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2386 ci = rtl_coalesce_info(dev);
2387 if (IS_ERR(ci))
2388 return PTR_ERR(ci);
2389
1ef7286e 2390 scale = &ci->scalev[RTL_R16(tp, CPlusCmd) & 3];
50970831
FR		 2391
2392 /* read IntrMitigate and adjust according to scale */
1ef7286e 2393 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
50970831
FR		 2394 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2395 w >>= RTL_COALESCE_SHIFT;
2396 *p->usecs = w & RTL_COALESCE_MASK;
2397 }
2398
2399 for (i = 0; i < 2; i++) {
2400 p = coal_settings + i;
2401 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2402
2403 /*
2404 * ethtool_coalesce says it is illegal to set both usecs and
2405 * max_frames to 0.
2406 */
2407 if (!*p->usecs && !*p->max_frames)
2408 *p->max_frames = 1;
2409 }
2410
2411 return 0;
2412}
2413
2414/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2415static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2416 struct net_device *dev, u32 nsec, u16 *cp01)
2417{
2418 const struct rtl_coalesce_info *ci;
2419 u16 i;
2420
2421 ci = rtl_coalesce_info(dev);
2422 if (IS_ERR(ci))
2423 return ERR_CAST(ci);
2424
2425 for (i = 0; i < 4; i++) {
2426 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2427 ci->scalev[i].nsecs[1]);
2428 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2429 *cp01 = i;
2430 return &ci->scalev[i];
2431 }
2432 }
2433
2434 return ERR_PTR(-EINVAL);
2435}
2436
2437static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2438{
2439 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 2440 const struct rtl_coalesce_scale *scale;
2441 struct {
2442 u32 frames;
2443 u32 usecs;
2444 } coal_settings [] = {
2445 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2446 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2447 }, *p = coal_settings;
2448 u16 w = 0, cp01;
2449 int i;
2450
2451 scale = rtl_coalesce_choose_scale(dev,
2452 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2453 if (IS_ERR(scale))
2454 return PTR_ERR(scale);
2455
2456 for (i = 0; i < 2; i++, p++) {
2457 u32 units;
2458
2459 /*
2460 * accept max_frames=1 we returned in rtl_get_coalesce.
2461 * accept it not only when usecs=0 because of e.g. the following scenario:
2462 *
2463 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2464 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2465 * - then user does `ethtool -C eth0 rx-usecs 100`
2466 *
2467 * since ethtool sends to kernel whole ethtool_coalesce
2468 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2469 * we'll reject it below in `frames % 4 != 0`.
2470 */
2471 if (p->frames == 1) {
2472 p->frames = 0;
2473 }
2474
2475 units = p->usecs * 1000 / scale->nsecs[i];
2476 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2477 return -EINVAL;
2478
2479 w <<= RTL_COALESCE_SHIFT;
2480 w |= units;
2481 w <<= RTL_COALESCE_SHIFT;
2482 w |= p->frames >> 2;
2483 }
2484
2485 rtl_lock_work(tp);
2486
1ef7286e 2487 RTL_W16(tp, IntrMitigate, swab16(w));
50970831
FR		 2488
2489 tp->cp_cmd = (tp->cp_cmd & ~3) | cp01;
1ef7286e
AS		 2490 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2491 RTL_R16(tp, CPlusCmd);
50970831
FR		 2492
2493 rtl_unlock_work(tp);
2494
2495 return 0;
2496}
2497
7282d491 2498static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2499 .get_drvinfo = rtl8169_get_drvinfo,
2500 .get_regs_len = rtl8169_get_regs_len,
2501 .get_link = ethtool_op_get_link,
50970831
FR		 2502 .get_coalesce = rtl_get_coalesce,
2503 .set_coalesce = rtl_set_coalesce,
b57b7e5a
SH		 2504 .get_msglevel = rtl8169_get_msglevel,
2505 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2506 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2507 .get_wol = rtl8169_get_wol,
2508 .set_wol = rtl8169_set_wol,
d4a3a0fc 2509 .get_strings = rtl8169_get_strings,
b9f2c044 2510 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2511 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2512 .get_ts_info = ethtool_op_get_ts_info,
f0903ea3 2513 .nway_reset = rtl8169_nway_reset,
6fa1ba61 2514 .get_link_ksettings = rtl8169_get_link_ksettings,
9e77d7a5 2515 .set_link_ksettings = rtl8169_set_link_ksettings,
1da177e4
LT		 2516};
2517
07d3f51f 2518static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2519 struct net_device *dev, u8 default_version)
1da177e4 2520{
0e485150
FR		 2521 /*
2522 * The driver currently handles the 8168Bf and the 8168Be identically
2523 * but they can be identified more specifically through the test below
2524 * if needed:
2525 *
1ef7286e 2526 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2527 *
2528 * Same thing for the 8101Eb and the 8101Ec:
2529 *
1ef7286e 2530 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2531 */
3744100e 2532 static const struct rtl_mac_info {
1da177e4 2533 u32 mask;
e3cf0cc0 2534 u32 val;
1da177e4
LT		 2535 int mac_version;
2536 } mac_info[] = {
935e2218
CHL		 2537 /* 8168EP family. */
2538 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2539 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2540 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2541
6e1d0b89
CHL		 2542 /* 8168H family. */
2543 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2544 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2545
c558386b 2546 /* 8168G family. */
45dd95c4 2547 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2548 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2549 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2550 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2551
c2218925 2552 /* 8168F family. */
b3d7b2f2 2553 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2554 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2555 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2556
01dc7fec 2557 /* 8168E family. */
70090424 2558 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2559 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2560 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2561 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2562
5b538df9 2563 /* 8168D family. */
daf9df6d 2564 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2565 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2566 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2567
e6de30d6 2568 /* 8168DP family. */
2569 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2570 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2571 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2572
ef808d50 2573 /* 8168C family. */
17c99297 2574 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2575 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2576 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2577 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2578 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2579 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2580 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2581 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2582 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2583
2584 /* 8168B family. */
2585 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2586 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2587 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2588 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2589
2590 /* 8101 family. */
5598bfe5
HW		 2591 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2592 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2593 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2594 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2595 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2596 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2597 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2598 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2599 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2600 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2601 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2602 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2603 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2604 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2605 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2606 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2607 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2608 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2609 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2610 /* FIXME: where did these entries come from ? -- FR */
2611 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2612 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2613
2614 /* 8110 family. */
2615 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2616 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2617 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2618 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2619 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2620 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2621
f21b75e9
JD		 2622 /* Catch-all */
2623 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2624 };
2625 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2626 u32 reg;
2627
1ef7286e 2628 reg = RTL_R32(tp, TxConfig);
e3cf0cc0 2629 while ((reg & p->mask) != p->val)
1da177e4
LT		 2630 p++;
2631 tp->mac_version = p->mac_version;
5d320a20
FR		 2632
2633 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2634 netif_notice(tp, probe, dev,
2635 "unknown MAC, using family default\n");
2636 tp->mac_version = default_version;
58152cd4 2637 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2638 tp->mac_version = tp->mii.supports_gmii ?
2639 RTL_GIGA_MAC_VER_42 :
2640 RTL_GIGA_MAC_VER_43;
6e1d0b89
CHL		 2641 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2642 tp->mac_version = tp->mii.supports_gmii ?
2643 RTL_GIGA_MAC_VER_45 :
2644 RTL_GIGA_MAC_VER_47;
2645 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2646 tp->mac_version = tp->mii.supports_gmii ?
2647 RTL_GIGA_MAC_VER_46 :
2648 RTL_GIGA_MAC_VER_48;
5d320a20 2649 }
1da177e4
LT		 2650}
2651
2652static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2653{
bcf0bf90 2654 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2655}
2656
867763c1
FR		 2657struct phy_reg {
2658 u16 reg;
2659 u16 val;
2660};
2661
4da19633 2662static void rtl_writephy_batch(struct rtl8169_private *tp,
2663 const struct phy_reg *regs, int len)
867763c1
FR		 2664{
2665 while (len-- > 0) {
4da19633 2666 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2667 regs++;
2668 }
2669}
2670
bca03d5f 2671#define PHY_READ 0x00000000
2672#define PHY_DATA_OR 0x10000000
2673#define PHY_DATA_AND 0x20000000
2674#define PHY_BJMPN 0x30000000
eee3786f 2675#define PHY_MDIO_CHG 0x40000000
bca03d5f 2676#define PHY_CLEAR_READCOUNT 0x70000000
2677#define PHY_WRITE 0x80000000
2678#define PHY_READCOUNT_EQ_SKIP 0x90000000
2679#define PHY_COMP_EQ_SKIPN 0xa0000000
2680#define PHY_COMP_NEQ_SKIPN 0xb0000000
2681#define PHY_WRITE_PREVIOUS 0xc0000000
2682#define PHY_SKIPN 0xd0000000
2683#define PHY_DELAY_MS 0xe0000000
bca03d5f 2684
960aee6c
HW		 2685struct fw_info {
2686 u32 magic;
2687 char version[RTL_VER_SIZE];
2688 __le32 fw_start;
2689 __le32 fw_len;
2690 u8 chksum;
2691} __packed;
2692
1c361efb
FR		 2693#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2694
2695static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2696{
b6ffd97f 2697 const struct firmware *fw = rtl_fw->fw;
960aee6c 2698 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2699 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2700 char *version = rtl_fw->version;
2701 bool rc = false;
2702
2703 if (fw->size < FW_OPCODE_SIZE)
2704 goto out;
960aee6c
HW		 2705
2706 if (!fw_info->magic) {
2707 size_t i, size, start;
2708 u8 checksum = 0;
2709
2710 if (fw->size < sizeof(*fw_info))
2711 goto out;
2712
2713 for (i = 0; i < fw->size; i++)
2714 checksum += fw->data[i];
2715 if (checksum != 0)
2716 goto out;
2717
2718 start = le32_to_cpu(fw_info->fw_start);
2719 if (start > fw->size)
2720 goto out;
2721
2722 size = le32_to_cpu(fw_info->fw_len);
2723 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2724 goto out;
2725
2726 memcpy(version, fw_info->version, RTL_VER_SIZE);
2727
2728 pa->code = (__le32 *)(fw->data + start);
2729 pa->size = size;
2730 } else {
1c361efb
FR		 2731 if (fw->size % FW_OPCODE_SIZE)
2732 goto out;
2733
2734 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2735
2736 pa->code = (__le32 *)fw->data;
2737 pa->size = fw->size / FW_OPCODE_SIZE;
2738 }
2739 version[RTL_VER_SIZE - 1] = 0;
2740
2741 rc = true;
2742out:
2743 return rc;
2744}
2745
fd112f2e
FR		 2746static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2747 struct rtl_fw_phy_action *pa)
1c361efb 2748{
fd112f2e 2749 bool rc = false;
1c361efb 2750 size_t index;
bca03d5f 2751
1c361efb
FR		 2752 for (index = 0; index < pa->size; index++) {
2753 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2754 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2755
42b82dc1 2756 switch(action & 0xf0000000) {
2757 case PHY_READ:
2758 case PHY_DATA_OR:
2759 case PHY_DATA_AND:
eee3786f 2760 case PHY_MDIO_CHG:
42b82dc1 2761 case PHY_CLEAR_READCOUNT:
2762 case PHY_WRITE:
2763 case PHY_WRITE_PREVIOUS:
2764 case PHY_DELAY_MS:
2765 break;
2766
2767 case PHY_BJMPN:
2768 if (regno > index) {
fd112f2e 2769 netif_err(tp, ifup, tp->dev,
cecb5fd7 2770 "Out of range of firmware\n");
fd112f2e 2771 goto out;
42b82dc1 2772 }
2773 break;
2774 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2775 if (index + 2 >= pa->size) {
fd112f2e 2776 netif_err(tp, ifup, tp->dev,
cecb5fd7 2777 "Out of range of firmware\n");
fd112f2e 2778 goto out;
42b82dc1 2779 }
2780 break;
2781 case PHY_COMP_EQ_SKIPN:
2782 case PHY_COMP_NEQ_SKIPN:
2783 case PHY_SKIPN:
1c361efb 2784 if (index + 1 + regno >= pa->size) {
fd112f2e 2785 netif_err(tp, ifup, tp->dev,
cecb5fd7 2786 "Out of range of firmware\n");
fd112f2e 2787 goto out;
42b82dc1 2788 }
bca03d5f 2789 break;
2790
42b82dc1 2791 default:
fd112f2e 2792 netif_err(tp, ifup, tp->dev,
42b82dc1 2793 "Invalid action 0x%08x\n", action);
fd112f2e 2794 goto out;
bca03d5f 2795 }
2796 }
fd112f2e
FR		 2797 rc = true;
2798out:
2799 return rc;
2800}
bca03d5f 2801
fd112f2e
FR		 2802static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2803{
2804 struct net_device *dev = tp->dev;
2805 int rc = -EINVAL;
2806
2807 if (!rtl_fw_format_ok(tp, rtl_fw)) {
5c2d2b14 2808 netif_err(tp, ifup, dev, "invalid firmware\n");
fd112f2e
FR		 2809 goto out;
2810 }
2811
2812 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2813 rc = 0;
2814out:
2815 return rc;
2816}
2817
2818static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2819{
2820 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2821 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2822 u32 predata, count;
2823 size_t index;
2824
2825 predata = count = 0;
eee3786f 2826 org.write = ops->write;
2827 org.read = ops->read;
42b82dc1 2828
1c361efb
FR		 2829 for (index = 0; index < pa->size; ) {
2830 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2831 u32 data = action & 0x0000ffff;
42b82dc1 2832 u32 regno = (action & 0x0fff0000) >> 16;
2833
2834 if (!action)
2835 break;
bca03d5f 2836
2837 switch(action & 0xf0000000) {
42b82dc1 2838 case PHY_READ:
2839 predata = rtl_readphy(tp, regno);
2840 count++;
2841 index++;
2842 break;
2843 case PHY_DATA_OR:
2844 predata |= data;
2845 index++;
2846 break;
2847 case PHY_DATA_AND:
2848 predata &= data;
2849 index++;
2850 break;
2851 case PHY_BJMPN:
2852 index -= regno;
2853 break;
eee3786f 2854 case PHY_MDIO_CHG:
2855 if (data == 0) {
2856 ops->write = org.write;
2857 ops->read = org.read;
2858 } else if (data == 1) {
2859 ops->write = mac_mcu_write;
2860 ops->read = mac_mcu_read;
2861 }
2862
42b82dc1 2863 index++;
2864 break;
2865 case PHY_CLEAR_READCOUNT:
2866 count = 0;
2867 index++;
2868 break;
bca03d5f 2869 case PHY_WRITE:
42b82dc1 2870 rtl_writephy(tp, regno, data);
2871 index++;
2872 break;
2873 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2874 index += (count == data) ? 2 : 1;
bca03d5f 2875 break;
42b82dc1 2876 case PHY_COMP_EQ_SKIPN:
2877 if (predata == data)
2878 index += regno;
2879 index++;
2880 break;
2881 case PHY_COMP_NEQ_SKIPN:
2882 if (predata != data)
2883 index += regno;
2884 index++;
2885 break;
2886 case PHY_WRITE_PREVIOUS:
2887 rtl_writephy(tp, regno, predata);
2888 index++;
2889 break;
2890 case PHY_SKIPN:
2891 index += regno + 1;
2892 break;
2893 case PHY_DELAY_MS:
2894 mdelay(data);
2895 index++;
2896 break;
2897
bca03d5f 2898 default:
2899 BUG();
2900 }
2901 }
eee3786f 2902
2903 ops->write = org.write;
2904 ops->read = org.read;
bca03d5f 2905}
2906
f1e02ed1 2907static void rtl_release_firmware(struct rtl8169_private *tp)
2908{
b6ffd97f
FR		 2909 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2910 release_firmware(tp->rtl_fw->fw);
2911 kfree(tp->rtl_fw);
2912 }
2913 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2914}
2915
953a12cc 2916static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2917{
b6ffd97f 2918 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2919
2920 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2921 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2922 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2923}
2924
2925static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2926{
2927 if (rtl_readphy(tp, reg) != val)
2928 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2929 else
2930 rtl_apply_firmware(tp);
f1e02ed1 2931}
2932
4da19633 2933static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2934{
350f7596 2935 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2936 { 0x1f, 0x0001 },
2937 { 0x06, 0x006e },
2938 { 0x08, 0x0708 },
2939 { 0x15, 0x4000 },
2940 { 0x18, 0x65c7 },
1da177e4 2941
0b9b571d 2942 { 0x1f, 0x0001 },
2943 { 0x03, 0x00a1 },
2944 { 0x02, 0x0008 },
2945 { 0x01, 0x0120 },
2946 { 0x00, 0x1000 },
2947 { 0x04, 0x0800 },
2948 { 0x04, 0x0000 },
1da177e4 2949
0b9b571d 2950 { 0x03, 0xff41 },
2951 { 0x02, 0xdf60 },
2952 { 0x01, 0x0140 },
2953 { 0x00, 0x0077 },
2954 { 0x04, 0x7800 },
2955 { 0x04, 0x7000 },
2956
2957 { 0x03, 0x802f },
2958 { 0x02, 0x4f02 },
2959 { 0x01, 0x0409 },
2960 { 0x00, 0xf0f9 },
2961 { 0x04, 0x9800 },
2962 { 0x04, 0x9000 },
2963
2964 { 0x03, 0xdf01 },
2965 { 0x02, 0xdf20 },
2966 { 0x01, 0xff95 },
2967 { 0x00, 0xba00 },
2968 { 0x04, 0xa800 },
2969 { 0x04, 0xa000 },
2970
2971 { 0x03, 0xff41 },
2972 { 0x02, 0xdf20 },
2973 { 0x01, 0x0140 },
2974 { 0x00, 0x00bb },
2975 { 0x04, 0xb800 },
2976 { 0x04, 0xb000 },
2977
2978 { 0x03, 0xdf41 },
2979 { 0x02, 0xdc60 },
2980 { 0x01, 0x6340 },
2981 { 0x00, 0x007d },
2982 { 0x04, 0xd800 },
2983 { 0x04, 0xd000 },
2984
2985 { 0x03, 0xdf01 },
2986 { 0x02, 0xdf20 },
2987 { 0x01, 0x100a },
2988 { 0x00, 0xa0ff },
2989 { 0x04, 0xf800 },
2990 { 0x04, 0xf000 },
2991
2992 { 0x1f, 0x0000 },
2993 { 0x0b, 0x0000 },
2994 { 0x00, 0x9200 }
2995 };
1da177e4 2996
4da19633 2997 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2998}
2999
4da19633 3000static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 3001{
350f7596 3002 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 3003 { 0x1f, 0x0002 },
3004 { 0x01, 0x90d0 },
3005 { 0x1f, 0x0000 }
3006 };
3007
4da19633 3008 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 3009}
3010
4da19633 3011static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 3012{
3013 struct pci_dev *pdev = tp->pci_dev;
2e955856 3014
ccbae55e
SS		 3015 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
3016 (pdev->subsystem_device != 0xe000))
2e955856 3017 return;
3018
4da19633 3019 rtl_writephy(tp, 0x1f, 0x0001);
3020 rtl_writephy(tp, 0x10, 0xf01b);
3021 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 3022}
3023
4da19633 3024static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 3025{
350f7596 3026 static const struct phy_reg phy_reg_init[] = {
2e955856 3027 { 0x1f, 0x0001 },
3028 { 0x04, 0x0000 },
3029 { 0x03, 0x00a1 },
3030 { 0x02, 0x0008 },
3031 { 0x01, 0x0120 },
3032 { 0x00, 0x1000 },
3033 { 0x04, 0x0800 },
3034 { 0x04, 0x9000 },
3035 { 0x03, 0x802f },
3036 { 0x02, 0x4f02 },
3037 { 0x01, 0x0409 },
3038 { 0x00, 0xf099 },
3039 { 0x04, 0x9800 },
3040 { 0x04, 0xa000 },
3041 { 0x03, 0xdf01 },
3042 { 0x02, 0xdf20 },
3043 { 0x01, 0xff95 },
3044 { 0x00, 0xba00 },
3045 { 0x04, 0xa800 },
3046 { 0x04, 0xf000 },
3047 { 0x03, 0xdf01 },
3048 { 0x02, 0xdf20 },
3049 { 0x01, 0x101a },
3050 { 0x00, 0xa0ff },
3051 { 0x04, 0xf800 },
3052 { 0x04, 0x0000 },
3053 { 0x1f, 0x0000 },
3054
3055 { 0x1f, 0x0001 },
3056 { 0x10, 0xf41b },
3057 { 0x14, 0xfb54 },
3058 { 0x18, 0xf5c7 },
3059 { 0x1f, 0x0000 },
3060
3061 { 0x1f, 0x0001 },
3062 { 0x17, 0x0cc0 },
3063 { 0x1f, 0x0000 }
3064 };
3065
4da19633 3066 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 3067
4da19633 3068 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 3069}
3070
4da19633 3071static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 3072{
350f7596 3073 static const struct phy_reg phy_reg_init[] = {
8c7006aa 3074 { 0x1f, 0x0001 },
3075 { 0x04, 0x0000 },
3076 { 0x03, 0x00a1 },
3077 { 0x02, 0x0008 },
3078 { 0x01, 0x0120 },
3079 { 0x00, 0x1000 },
3080 { 0x04, 0x0800 },
3081 { 0x04, 0x9000 },
3082 { 0x03, 0x802f },
3083 { 0x02, 0x4f02 },
3084 { 0x01, 0x0409 },
3085 { 0x00, 0xf099 },
3086 { 0x04, 0x9800 },
3087 { 0x04, 0xa000 },
3088 { 0x03, 0xdf01 },
3089 { 0x02, 0xdf20 },
3090 { 0x01, 0xff95 },
3091 { 0x00, 0xba00 },
3092 { 0x04, 0xa800 },
3093 { 0x04, 0xf000 },
3094 { 0x03, 0xdf01 },
3095 { 0x02, 0xdf20 },
3096 { 0x01, 0x101a },
3097 { 0x00, 0xa0ff },
3098 { 0x04, 0xf800 },
3099 { 0x04, 0x0000 },
3100 { 0x1f, 0x0000 },
3101
3102 { 0x1f, 0x0001 },
3103 { 0x0b, 0x8480 },
3104 { 0x1f, 0x0000 },
3105
3106 { 0x1f, 0x0001 },
3107 { 0x18, 0x67c7 },
3108 { 0x04, 0x2000 },
3109 { 0x03, 0x002f },
3110 { 0x02, 0x4360 },
3111 { 0x01, 0x0109 },
3112 { 0x00, 0x3022 },
3113 { 0x04, 0x2800 },
3114 { 0x1f, 0x0000 },
3115
3116 { 0x1f, 0x0001 },
3117 { 0x17, 0x0cc0 },
3118 { 0x1f, 0x0000 }
3119 };
3120
4da19633 3121 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 3122}
3123
4da19633 3124static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 3125{
350f7596 3126 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 3127 { 0x10, 0xf41b },
3128 { 0x1f, 0x0000 }
3129 };
3130
4da19633 3131 rtl_writephy(tp, 0x1f, 0x0001);
3132 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 3133
4da19633 3134 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 3135}
3136
4da19633 3137static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 3138{
350f7596 3139 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 3140 { 0x1f, 0x0001 },
3141 { 0x10, 0xf41b },
3142 { 0x1f, 0x0000 }
3143 };
3144
4da19633 3145 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 3146}
3147
4da19633 3148static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 3149{
350f7596 3150 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 3151 { 0x1f, 0x0000 },
3152 { 0x1d, 0x0f00 },
3153 { 0x1f, 0x0002 },
3154 { 0x0c, 0x1ec8 },
3155 { 0x1f, 0x0000 }
3156 };
3157
4da19633 3158 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 3159}
3160
4da19633 3161static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 3162{
350f7596 3163 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 3164 { 0x1f, 0x0001 },
3165 { 0x1d, 0x3d98 },
3166 { 0x1f, 0x0000 }
3167 };
3168
4da19633 3169 rtl_writephy(tp, 0x1f, 0x0000);
3170 rtl_patchphy(tp, 0x14, 1 << 5);
3171 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 3172
4da19633 3173 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 3174}
3175
4da19633 3176static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 3177{
350f7596 3178 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 3179 { 0x1f, 0x0001 },
3180 { 0x12, 0x2300 },
867763c1
FR		 3181 { 0x1f, 0x0002 },
3182 { 0x00, 0x88d4 },
3183 { 0x01, 0x82b1 },
3184 { 0x03, 0x7002 },
3185 { 0x08, 0x9e30 },
3186 { 0x09, 0x01f0 },
3187 { 0x0a, 0x5500 },
3188 { 0x0c, 0x00c8 },
3189 { 0x1f, 0x0003 },
3190 { 0x12, 0xc096 },
3191 { 0x16, 0x000a },
f50d4275
FR		 3192 { 0x1f, 0x0000 },
3193 { 0x1f, 0x0000 },
3194 { 0x09, 0x2000 },
3195 { 0x09, 0x0000 }
867763c1
FR		 3196 };
3197
4da19633 3198 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3199
4da19633 3200 rtl_patchphy(tp, 0x14, 1 << 5);
3201 rtl_patchphy(tp, 0x0d, 1 << 5);
3202 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 3203}
3204
4da19633 3205static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 3206{
350f7596 3207 static const struct phy_reg phy_reg_init[] = {
f50d4275 3208 { 0x1f, 0x0001 },
7da97ec9 3209 { 0x12, 0x2300 },
f50d4275
FR		 3210 { 0x03, 0x802f },
3211 { 0x02, 0x4f02 },
3212 { 0x01, 0x0409 },
3213 { 0x00, 0xf099 },
3214 { 0x04, 0x9800 },
3215 { 0x04, 0x9000 },
3216 { 0x1d, 0x3d98 },
7da97ec9
FR		 3217 { 0x1f, 0x0002 },
3218 { 0x0c, 0x7eb8 },
f50d4275
FR		 3219 { 0x06, 0x0761 },
3220 { 0x1f, 0x0003 },
3221 { 0x16, 0x0f0a },
7da97ec9
FR		 3222 { 0x1f, 0x0000 }
3223 };
3224
4da19633 3225 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3226
4da19633 3227 rtl_patchphy(tp, 0x16, 1 << 0);
3228 rtl_patchphy(tp, 0x14, 1 << 5);
3229 rtl_patchphy(tp, 0x0d, 1 << 5);
3230 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 3231}
3232
4da19633 3233static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 3234{
350f7596 3235 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 3236 { 0x1f, 0x0001 },
3237 { 0x12, 0x2300 },
3238 { 0x1d, 0x3d98 },
3239 { 0x1f, 0x0002 },
3240 { 0x0c, 0x7eb8 },
3241 { 0x06, 0x5461 },
3242 { 0x1f, 0x0003 },
3243 { 0x16, 0x0f0a },
3244 { 0x1f, 0x0000 }
3245 };
3246
4da19633 3247 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 3248
4da19633 3249 rtl_patchphy(tp, 0x16, 1 << 0);
3250 rtl_patchphy(tp, 0x14, 1 << 5);
3251 rtl_patchphy(tp, 0x0d, 1 << 5);
3252 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 3253}
3254
4da19633 3255static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 3256{
4da19633 3257 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 3258}
3259
bca03d5f 3260static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 3261{
350f7596 3262 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3263 /* Channel Estimation */
5b538df9 3264 { 0x1f, 0x0001 },
daf9df6d 3265 { 0x06, 0x4064 },
3266 { 0x07, 0x2863 },
3267 { 0x08, 0x059c },
3268 { 0x09, 0x26b4 },
3269 { 0x0a, 0x6a19 },
3270 { 0x0b, 0xdcc8 },
3271 { 0x10, 0xf06d },
3272 { 0x14, 0x7f68 },
3273 { 0x18, 0x7fd9 },
3274 { 0x1c, 0xf0ff },
3275 { 0x1d, 0x3d9c },
5b538df9 3276 { 0x1f, 0x0003 },
daf9df6d 3277 { 0x12, 0xf49f },
3278 { 0x13, 0x070b },
3279 { 0x1a, 0x05ad },
bca03d5f 3280 { 0x14, 0x94c0 },
3281
3282 /*
3283 * Tx Error Issue
cecb5fd7 3284 * Enhance line driver power
bca03d5f 3285 */
5b538df9 3286 { 0x1f, 0x0002 },
daf9df6d 3287 { 0x06, 0x5561 },
3288 { 0x1f, 0x0005 },
3289 { 0x05, 0x8332 },
bca03d5f 3290 { 0x06, 0x5561 },
3291
3292 /*
3293 * Can not link to 1Gbps with bad cable
3294 * Decrease SNR threshold form 21.07dB to 19.04dB
3295 */
3296 { 0x1f, 0x0001 },
3297 { 0x17, 0x0cc0 },
daf9df6d 3298
5b538df9 3299 { 0x1f, 0x0000 },
bca03d5f 3300 { 0x0d, 0xf880 }
daf9df6d 3301 };
3302
4da19633 3303 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 3304
bca03d5f 3305 /*
3306 * Rx Error Issue
3307 * Fine Tune Switching regulator parameter
3308 */
4da19633 3309 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3310 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3311 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 3312
fdf6fc06 3313 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3314 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3315 { 0x1f, 0x0002 },
3316 { 0x05, 0x669a },
3317 { 0x1f, 0x0005 },
3318 { 0x05, 0x8330 },
3319 { 0x06, 0x669a },
3320 { 0x1f, 0x0002 }
3321 };
3322 int val;
3323
4da19633 3324 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3325
4da19633 3326 val = rtl_readphy(tp, 0x0d);
daf9df6d 3327
3328 if ((val & 0x00ff) != 0x006c) {
350f7596 3329 static const u32 set[] = {
daf9df6d 3330 0x0065, 0x0066, 0x0067, 0x0068,
3331 0x0069, 0x006a, 0x006b, 0x006c
3332 };
3333 int i;
3334
4da19633 3335 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3336
3337 val &= 0xff00;
3338 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3339 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3340 }
3341 } else {
350f7596 3342 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3343 { 0x1f, 0x0002 },
3344 { 0x05, 0x6662 },
3345 { 0x1f, 0x0005 },
3346 { 0x05, 0x8330 },
3347 { 0x06, 0x6662 }
3348 };
3349
4da19633 3350 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3351 }
3352
bca03d5f 3353 /* RSET couple improve */
4da19633 3354 rtl_writephy(tp, 0x1f, 0x0002);
3355 rtl_patchphy(tp, 0x0d, 0x0300);
3356 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 3357
bca03d5f 3358 /* Fine tune PLL performance */
4da19633 3359 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3360 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3361 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3362
4da19633 3363 rtl_writephy(tp, 0x1f, 0x0005);
3364 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3365
3366 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 3367
4da19633 3368 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3369}
3370
bca03d5f 3371static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3372{
350f7596 3373 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3374 /* Channel Estimation */
daf9df6d 3375 { 0x1f, 0x0001 },
3376 { 0x06, 0x4064 },
3377 { 0x07, 0x2863 },
3378 { 0x08, 0x059c },
3379 { 0x09, 0x26b4 },
3380 { 0x0a, 0x6a19 },
3381 { 0x0b, 0xdcc8 },
3382 { 0x10, 0xf06d },
3383 { 0x14, 0x7f68 },
3384 { 0x18, 0x7fd9 },
3385 { 0x1c, 0xf0ff },
3386 { 0x1d, 0x3d9c },
3387 { 0x1f, 0x0003 },
3388 { 0x12, 0xf49f },
3389 { 0x13, 0x070b },
3390 { 0x1a, 0x05ad },
3391 { 0x14, 0x94c0 },
3392
bca03d5f 3393 /*
3394 * Tx Error Issue
cecb5fd7 3395 * Enhance line driver power
bca03d5f 3396 */
daf9df6d 3397 { 0x1f, 0x0002 },
3398 { 0x06, 0x5561 },
3399 { 0x1f, 0x0005 },
3400 { 0x05, 0x8332 },
bca03d5f 3401 { 0x06, 0x5561 },
3402
3403 /*
3404 * Can not link to 1Gbps with bad cable
3405 * Decrease SNR threshold form 21.07dB to 19.04dB
3406 */
3407 { 0x1f, 0x0001 },
3408 { 0x17, 0x0cc0 },
daf9df6d 3409
3410 { 0x1f, 0x0000 },
bca03d5f 3411 { 0x0d, 0xf880 }
5b538df9
FR		 3412 };
3413
4da19633 3414 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 3415
fdf6fc06 3416 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3417 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3418 { 0x1f, 0x0002 },
3419 { 0x05, 0x669a },
5b538df9 3420 { 0x1f, 0x0005 },
daf9df6d 3421 { 0x05, 0x8330 },
3422 { 0x06, 0x669a },
3423
3424 { 0x1f, 0x0002 }
3425 };
3426 int val;
3427
4da19633 3428 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3429
4da19633 3430 val = rtl_readphy(tp, 0x0d);
daf9df6d 3431 if ((val & 0x00ff) != 0x006c) {
b6bc7650 3432 static const u32 set[] = {
daf9df6d 3433 0x0065, 0x0066, 0x0067, 0x0068,
3434 0x0069, 0x006a, 0x006b, 0x006c
3435 };
3436 int i;
3437
4da19633 3438 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3439
3440 val &= 0xff00;
3441 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3442 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3443 }
3444 } else {
350f7596 3445 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3446 { 0x1f, 0x0002 },
3447 { 0x05, 0x2642 },
5b538df9 3448 { 0x1f, 0x0005 },
daf9df6d 3449 { 0x05, 0x8330 },
3450 { 0x06, 0x2642 }
5b538df9
FR		 3451 };
3452
4da19633 3453 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3454 }
3455
bca03d5f 3456 /* Fine tune PLL performance */
4da19633 3457 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3458 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3459 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3460
bca03d5f 3461 /* Switching regulator Slew rate */
4da19633 3462 rtl_writephy(tp, 0x1f, 0x0002);
3463 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 3464
4da19633 3465 rtl_writephy(tp, 0x1f, 0x0005);
3466 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3467
3468 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 3469
4da19633 3470 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3471}
3472
4da19633 3473static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3474{
350f7596 3475 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3476 { 0x1f, 0x0002 },
3477 { 0x10, 0x0008 },
3478 { 0x0d, 0x006c },
3479
3480 { 0x1f, 0x0000 },
3481 { 0x0d, 0xf880 },
3482
3483 { 0x1f, 0x0001 },
3484 { 0x17, 0x0cc0 },
3485
3486 { 0x1f, 0x0001 },
3487 { 0x0b, 0xa4d8 },
3488 { 0x09, 0x281c },
3489 { 0x07, 0x2883 },
3490 { 0x0a, 0x6b35 },
3491 { 0x1d, 0x3da4 },
3492 { 0x1c, 0xeffd },
3493 { 0x14, 0x7f52 },
3494 { 0x18, 0x7fc6 },
3495 { 0x08, 0x0601 },
3496 { 0x06, 0x4063 },
3497 { 0x10, 0xf074 },
3498 { 0x1f, 0x0003 },
3499 { 0x13, 0x0789 },
3500 { 0x12, 0xf4bd },
3501 { 0x1a, 0x04fd },
3502 { 0x14, 0x84b0 },
3503 { 0x1f, 0x0000 },
3504 { 0x00, 0x9200 },
3505
3506 { 0x1f, 0x0005 },
3507 { 0x01, 0x0340 },
3508 { 0x1f, 0x0001 },
3509 { 0x04, 0x4000 },
3510 { 0x03, 0x1d21 },
3511 { 0x02, 0x0c32 },
3512 { 0x01, 0x0200 },
3513 { 0x00, 0x5554 },
3514 { 0x04, 0x4800 },
3515 { 0x04, 0x4000 },
3516 { 0x04, 0xf000 },
3517 { 0x03, 0xdf01 },
3518 { 0x02, 0xdf20 },
3519 { 0x01, 0x101a },
3520 { 0x00, 0xa0ff },
3521 { 0x04, 0xf800 },
3522 { 0x04, 0xf000 },
3523 { 0x1f, 0x0000 },
3524
3525 { 0x1f, 0x0007 },
3526 { 0x1e, 0x0023 },
3527 { 0x16, 0x0000 },
3528 { 0x1f, 0x0000 }
3529 };
3530
4da19633 3531 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3532}
3533
e6de30d6 3534static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3535{
3536 static const struct phy_reg phy_reg_init[] = {
3537 { 0x1f, 0x0001 },
3538 { 0x17, 0x0cc0 },
3539
3540 { 0x1f, 0x0007 },
3541 { 0x1e, 0x002d },
3542 { 0x18, 0x0040 },
3543 { 0x1f, 0x0000 }
3544 };
3545
3546 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3547 rtl_patchphy(tp, 0x0d, 1 << 5);
3548}
3549
70090424 3550static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3551{
3552 static const struct phy_reg phy_reg_init[] = {
3553 /* Enable Delay cap */
3554 { 0x1f, 0x0005 },
3555 { 0x05, 0x8b80 },
3556 { 0x06, 0xc896 },
3557 { 0x1f, 0x0000 },
3558
3559 /* Channel estimation fine tune */
3560 { 0x1f, 0x0001 },
3561 { 0x0b, 0x6c20 },
3562 { 0x07, 0x2872 },
3563 { 0x1c, 0xefff },
3564 { 0x1f, 0x0003 },
3565 { 0x14, 0x6420 },
3566 { 0x1f, 0x0000 },
3567
3568 /* Update PFM & 10M TX idle timer */
3569 { 0x1f, 0x0007 },
3570 { 0x1e, 0x002f },
3571 { 0x15, 0x1919 },
3572 { 0x1f, 0x0000 },
3573
3574 { 0x1f, 0x0007 },
3575 { 0x1e, 0x00ac },
3576 { 0x18, 0x0006 },
3577 { 0x1f, 0x0000 }
3578 };
3579
15ecd039
FR		 3580 rtl_apply_firmware(tp);
3581
01dc7fec 3582 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3583
3584 /* DCO enable for 10M IDLE Power */
3585 rtl_writephy(tp, 0x1f, 0x0007);
3586 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3587 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3588 rtl_writephy(tp, 0x1f, 0x0000);
3589
3590 /* For impedance matching */
3591 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3592 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3593 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3594
3595 /* PHY auto speed down */
3596 rtl_writephy(tp, 0x1f, 0x0007);
3597 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3598 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3599 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3600 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3601
3602 rtl_writephy(tp, 0x1f, 0x0005);
3603 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3604 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3605 rtl_writephy(tp, 0x1f, 0x0000);
3606
3607 rtl_writephy(tp, 0x1f, 0x0005);
3608 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3609 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3610 rtl_writephy(tp, 0x1f, 0x0007);
3611 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3612 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3613 rtl_writephy(tp, 0x1f, 0x0006);
3614 rtl_writephy(tp, 0x00, 0x5a00);
3615 rtl_writephy(tp, 0x1f, 0x0000);
3616 rtl_writephy(tp, 0x0d, 0x0007);
3617 rtl_writephy(tp, 0x0e, 0x003c);
3618 rtl_writephy(tp, 0x0d, 0x4007);
3619 rtl_writephy(tp, 0x0e, 0x0000);
3620 rtl_writephy(tp, 0x0d, 0x0000);
3621}
3622
9ecb9aab 3623static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3624{
3625 const u16 w[] = {
3626 addr[0] | (addr[1] << 8),
3627 addr[2] | (addr[3] << 8),
3628 addr[4] | (addr[5] << 8)
3629 };
3630 const struct exgmac_reg e[] = {
3631 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3632 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3633 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3634 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3635 };
3636
3637 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3638}
3639
70090424
HW		 3640static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3641{
3642 static const struct phy_reg phy_reg_init[] = {
3643 /* Enable Delay cap */
3644 { 0x1f, 0x0004 },
3645 { 0x1f, 0x0007 },
3646 { 0x1e, 0x00ac },
3647 { 0x18, 0x0006 },
3648 { 0x1f, 0x0002 },
3649 { 0x1f, 0x0000 },
3650 { 0x1f, 0x0000 },
3651
3652 /* Channel estimation fine tune */
3653 { 0x1f, 0x0003 },
3654 { 0x09, 0xa20f },
3655 { 0x1f, 0x0000 },
3656 { 0x1f, 0x0000 },
3657
3658 /* Green Setting */
3659 { 0x1f, 0x0005 },
3660 { 0x05, 0x8b5b },
3661 { 0x06, 0x9222 },
3662 { 0x05, 0x8b6d },
3663 { 0x06, 0x8000 },
3664 { 0x05, 0x8b76 },
3665 { 0x06, 0x8000 },
3666 { 0x1f, 0x0000 }
3667 };
3668
3669 rtl_apply_firmware(tp);
3670
3671 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3672
3673 /* For 4-corner performance improve */
3674 rtl_writephy(tp, 0x1f, 0x0005);
3675 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3676 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3677 rtl_writephy(tp, 0x1f, 0x0000);
3678
3679 /* PHY auto speed down */
3680 rtl_writephy(tp, 0x1f, 0x0004);
3681 rtl_writephy(tp, 0x1f, 0x0007);
3682 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3683 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3684 rtl_writephy(tp, 0x1f, 0x0002);
3685 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3686 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3687
3688 /* improve 10M EEE waveform */
3689 rtl_writephy(tp, 0x1f, 0x0005);
3690 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3691 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3692 rtl_writephy(tp, 0x1f, 0x0000);
3693
3694 /* Improve 2-pair detection performance */
3695 rtl_writephy(tp, 0x1f, 0x0005);
3696 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3697 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3698 rtl_writephy(tp, 0x1f, 0x0000);
3699
3700 /* EEE setting */
1814d6a8 3701 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
70090424
HW		 3702 rtl_writephy(tp, 0x1f, 0x0005);
3703 rtl_writephy(tp, 0x05, 0x8b85);
1814d6a8 3704 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
70090424
HW		 3705 rtl_writephy(tp, 0x1f, 0x0004);
3706 rtl_writephy(tp, 0x1f, 0x0007);
3707 rtl_writephy(tp, 0x1e, 0x0020);
1814d6a8 3708 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
70090424
HW		 3709 rtl_writephy(tp, 0x1f, 0x0002);
3710 rtl_writephy(tp, 0x1f, 0x0000);
3711 rtl_writephy(tp, 0x0d, 0x0007);
3712 rtl_writephy(tp, 0x0e, 0x003c);
3713 rtl_writephy(tp, 0x0d, 0x4007);
1814d6a8 3714 rtl_writephy(tp, 0x0e, 0x0006);
70090424
HW		 3715 rtl_writephy(tp, 0x0d, 0x0000);
3716
3717 /* Green feature */
3718 rtl_writephy(tp, 0x1f, 0x0003);
1814d6a8
HK		 3719 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3720 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
70090424 3721 rtl_writephy(tp, 0x1f, 0x0000);
b399a394
HK		 3722 rtl_writephy(tp, 0x1f, 0x0005);
3723 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3724 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3725
9ecb9aab 3726 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3727 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3728}
3729
5f886e08
HW		 3730static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3731{
3732 /* For 4-corner performance improve */
3733 rtl_writephy(tp, 0x1f, 0x0005);
3734 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3735 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3736 rtl_writephy(tp, 0x1f, 0x0000);
3737
3738 /* PHY auto speed down */
3739 rtl_writephy(tp, 0x1f, 0x0007);
3740 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3741 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3742 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3743 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3744
3745 /* Improve 10M EEE waveform */
3746 rtl_writephy(tp, 0x1f, 0x0005);
3747 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3748 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3749 rtl_writephy(tp, 0x1f, 0x0000);
3750}
3751
c2218925
HW		 3752static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3753{
3754 static const struct phy_reg phy_reg_init[] = {
3755 /* Channel estimation fine tune */
3756 { 0x1f, 0x0003 },
3757 { 0x09, 0xa20f },
3758 { 0x1f, 0x0000 },
3759
3760 /* Modify green table for giga & fnet */
3761 { 0x1f, 0x0005 },
3762 { 0x05, 0x8b55 },
3763 { 0x06, 0x0000 },
3764 { 0x05, 0x8b5e },
3765 { 0x06, 0x0000 },
3766 { 0x05, 0x8b67 },
3767 { 0x06, 0x0000 },
3768 { 0x05, 0x8b70 },
3769 { 0x06, 0x0000 },
3770 { 0x1f, 0x0000 },
3771 { 0x1f, 0x0007 },
3772 { 0x1e, 0x0078 },
3773 { 0x17, 0x0000 },
3774 { 0x19, 0x00fb },
3775 { 0x1f, 0x0000 },
3776
3777 /* Modify green table for 10M */
3778 { 0x1f, 0x0005 },
3779 { 0x05, 0x8b79 },
3780 { 0x06, 0xaa00 },
3781 { 0x1f, 0x0000 },
3782
3783 /* Disable hiimpedance detection (RTCT) */
3784 { 0x1f, 0x0003 },
3785 { 0x01, 0x328a },
3786 { 0x1f, 0x0000 }
3787 };
3788
3789 rtl_apply_firmware(tp);
3790
3791 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3792
5f886e08 3793 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3794
3795 /* Improve 2-pair detection performance */
3796 rtl_writephy(tp, 0x1f, 0x0005);
3797 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3798 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3799 rtl_writephy(tp, 0x1f, 0x0000);
3800}
3801
3802static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3803{
3804 rtl_apply_firmware(tp);
3805
5f886e08 3806 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3807}
3808
b3d7b2f2
HW		 3809static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3810{
b3d7b2f2
HW		 3811 static const struct phy_reg phy_reg_init[] = {
3812 /* Channel estimation fine tune */
3813 { 0x1f, 0x0003 },
3814 { 0x09, 0xa20f },
3815 { 0x1f, 0x0000 },
3816
3817 /* Modify green table for giga & fnet */
3818 { 0x1f, 0x0005 },
3819 { 0x05, 0x8b55 },
3820 { 0x06, 0x0000 },
3821 { 0x05, 0x8b5e },
3822 { 0x06, 0x0000 },
3823 { 0x05, 0x8b67 },
3824 { 0x06, 0x0000 },
3825 { 0x05, 0x8b70 },
3826 { 0x06, 0x0000 },
3827 { 0x1f, 0x0000 },
3828 { 0x1f, 0x0007 },
3829 { 0x1e, 0x0078 },
3830 { 0x17, 0x0000 },
3831 { 0x19, 0x00aa },
3832 { 0x1f, 0x0000 },
3833
3834 /* Modify green table for 10M */
3835 { 0x1f, 0x0005 },
3836 { 0x05, 0x8b79 },
3837 { 0x06, 0xaa00 },
3838 { 0x1f, 0x0000 },
3839
3840 /* Disable hiimpedance detection (RTCT) */
3841 { 0x1f, 0x0003 },
3842 { 0x01, 0x328a },
3843 { 0x1f, 0x0000 }
3844 };
3845
3846
3847 rtl_apply_firmware(tp);
3848
3849 rtl8168f_hw_phy_config(tp);
3850
3851 /* Improve 2-pair detection performance */
3852 rtl_writephy(tp, 0x1f, 0x0005);
3853 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3854 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3855 rtl_writephy(tp, 0x1f, 0x0000);
3856
3857 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3858
3859 /* Modify green table for giga */
3860 rtl_writephy(tp, 0x1f, 0x0005);
3861 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3862 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3863 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3864 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3865 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3866 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3867 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3868 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3869 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3870 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3871 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3872 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3873 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3874 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3875 rtl_writephy(tp, 0x1f, 0x0000);
3876
3877 /* uc same-seed solution */
3878 rtl_writephy(tp, 0x1f, 0x0005);
3879 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3880 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3881 rtl_writephy(tp, 0x1f, 0x0000);
3882
3883 /* eee setting */
706123d0 3884 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3885 rtl_writephy(tp, 0x1f, 0x0005);
3886 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3887 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3888 rtl_writephy(tp, 0x1f, 0x0004);
3889 rtl_writephy(tp, 0x1f, 0x0007);
3890 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3891 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3892 rtl_writephy(tp, 0x1f, 0x0000);
3893 rtl_writephy(tp, 0x0d, 0x0007);
3894 rtl_writephy(tp, 0x0e, 0x003c);
3895 rtl_writephy(tp, 0x0d, 0x4007);
3896 rtl_writephy(tp, 0x0e, 0x0000);
3897 rtl_writephy(tp, 0x0d, 0x0000);
3898
3899 /* Green feature */
3900 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3901 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3902 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3903 rtl_writephy(tp, 0x1f, 0x0000);
3904}
3905
c558386b
HW		 3906static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3907{
c558386b
HW		 3908 rtl_apply_firmware(tp);
3909
41f44d13 3910 rtl_writephy(tp, 0x1f, 0x0a46);
3911 if (rtl_readphy(tp, 0x10) & 0x0100) {
3912 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3913 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3914 } else {
3915 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3916 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3917 }
c558386b 3918
41f44d13 3919 rtl_writephy(tp, 0x1f, 0x0a46);
3920 if (rtl_readphy(tp, 0x13) & 0x0100) {
3921 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3922 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 3923 } else {
fe7524c0 3924 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3925 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3926 }
c558386b 3927
41f44d13 3928 /* Enable PHY auto speed down */
3929 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3930 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3931
fe7524c0 3932 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3933 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 3934 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3935 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 3936 rtl_writephy(tp, 0x1f, 0x0a43);
3937 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 3938 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3939 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 3940
41f44d13 3941 /* EEE auto-fallback function */
3942 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 3943 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3944
41f44d13 3945 /* Enable UC LPF tune function */
3946 rtl_writephy(tp, 0x1f, 0x0a43);
3947 rtl_writephy(tp, 0x13, 0x8012);
76564428 3948 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 3949
3950 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 3951 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 3952
fe7524c0 3953 /* Improve SWR Efficiency */
3954 rtl_writephy(tp, 0x1f, 0x0bcd);
3955 rtl_writephy(tp, 0x14, 0x5065);
3956 rtl_writephy(tp, 0x14, 0xd065);
3957 rtl_writephy(tp, 0x1f, 0x0bc8);
3958 rtl_writephy(tp, 0x11, 0x5655);
3959 rtl_writephy(tp, 0x1f, 0x0bcd);
3960 rtl_writephy(tp, 0x14, 0x1065);
3961 rtl_writephy(tp, 0x14, 0x9065);
3962 rtl_writephy(tp, 0x14, 0x1065);
3963
1bac1072
DC		 3964 /* Check ALDPS bit, disable it if enabled */
3965 rtl_writephy(tp, 0x1f, 0x0a43);
3966 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3967 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 3968
41f44d13 3969 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3970}
3971
57538c4a 3972static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3973{
3974 rtl_apply_firmware(tp);
3975}
3976
6e1d0b89
CHL		 3977static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3978{
3979 u16 dout_tapbin;
3980 u32 data;
3981
3982 rtl_apply_firmware(tp);
3983
3984 /* CHN EST parameters adjust - giga master */
3985 rtl_writephy(tp, 0x1f, 0x0a43);
3986 rtl_writephy(tp, 0x13, 0x809b);
76564428 3987 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 3988 rtl_writephy(tp, 0x13, 0x80a2);
76564428 3989 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 3990 rtl_writephy(tp, 0x13, 0x80a4);
76564428 3991 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 3992 rtl_writephy(tp, 0x13, 0x809c);
76564428 3993 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 3994 rtl_writephy(tp, 0x1f, 0x0000);
3995
3996 /* CHN EST parameters adjust - giga slave */
3997 rtl_writephy(tp, 0x1f, 0x0a43);
3998 rtl_writephy(tp, 0x13, 0x80ad);
76564428 3999 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 4000 rtl_writephy(tp, 0x13, 0x80b4);
76564428 4001 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 4002 rtl_writephy(tp, 0x13, 0x80ac);
76564428 4003 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 4004 rtl_writephy(tp, 0x1f, 0x0000);
4005
4006 /* CHN EST parameters adjust - fnet */
4007 rtl_writephy(tp, 0x1f, 0x0a43);
4008 rtl_writephy(tp, 0x13, 0x808e);
76564428 4009 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 4010 rtl_writephy(tp, 0x13, 0x8090);
76564428 4011 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 4012 rtl_writephy(tp, 0x13, 0x8092);
76564428 4013 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 4014 rtl_writephy(tp, 0x1f, 0x0000);
4015
4016 /* enable R-tune & PGA-retune function */
4017 dout_tapbin = 0;
4018 rtl_writephy(tp, 0x1f, 0x0a46);
4019 data = rtl_readphy(tp, 0x13);
4020 data &= 3;
4021 data <<= 2;
4022 dout_tapbin |= data;
4023 data = rtl_readphy(tp, 0x12);
4024 data &= 0xc000;
4025 data >>= 14;
4026 dout_tapbin |= data;
4027 dout_tapbin = ~(dout_tapbin^0x08);
4028 dout_tapbin <<= 12;
4029 dout_tapbin &= 0xf000;
4030 rtl_writephy(tp, 0x1f, 0x0a43);
4031 rtl_writephy(tp, 0x13, 0x827a);
76564428 4032 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 4033 rtl_writephy(tp, 0x13, 0x827b);
76564428 4034 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 4035 rtl_writephy(tp, 0x13, 0x827c);
76564428 4036 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 4037 rtl_writephy(tp, 0x13, 0x827d);
76564428 4038 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 4039
4040 rtl_writephy(tp, 0x1f, 0x0a43);
4041 rtl_writephy(tp, 0x13, 0x0811);
76564428 4042 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 4043 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 4044 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 4045 rtl_writephy(tp, 0x1f, 0x0000);
4046
4047 /* enable GPHY 10M */
4048 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 4049 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 4050 rtl_writephy(tp, 0x1f, 0x0000);
4051
4052 /* SAR ADC performance */
4053 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 4054 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 4055 rtl_writephy(tp, 0x1f, 0x0000);
4056
4057 rtl_writephy(tp, 0x1f, 0x0a43);
4058 rtl_writephy(tp, 0x13, 0x803f);
76564428 4059 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4060 rtl_writephy(tp, 0x13, 0x8047);
76564428 4061 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4062 rtl_writephy(tp, 0x13, 0x804f);
76564428 4063 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4064 rtl_writephy(tp, 0x13, 0x8057);
76564428 4065 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4066 rtl_writephy(tp, 0x13, 0x805f);
76564428 4067 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4068 rtl_writephy(tp, 0x13, 0x8067);
76564428 4069 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4070 rtl_writephy(tp, 0x13, 0x806f);
76564428 4071 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 4072 rtl_writephy(tp, 0x1f, 0x0000);
4073
4074 /* disable phy pfm mode */
4075 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 4076 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 4077 rtl_writephy(tp, 0x1f, 0x0000);
4078
4079 /* Check ALDPS bit, disable it if enabled */
4080 rtl_writephy(tp, 0x1f, 0x0a43);
4081 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 4082 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 4083
4084 rtl_writephy(tp, 0x1f, 0x0000);
4085}
4086
4087static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
4088{
4089 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
4090 u16 rlen;
4091 u32 data;
4092
4093 rtl_apply_firmware(tp);
4094
4095 /* CHIN EST parameter update */
4096 rtl_writephy(tp, 0x1f, 0x0a43);
4097 rtl_writephy(tp, 0x13, 0x808a);
76564428 4098 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 4099 rtl_writephy(tp, 0x1f, 0x0000);
4100
4101 /* enable R-tune & PGA-retune function */
4102 rtl_writephy(tp, 0x1f, 0x0a43);
4103 rtl_writephy(tp, 0x13, 0x0811);
76564428 4104 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 4105 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 4106 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 4107 rtl_writephy(tp, 0x1f, 0x0000);
4108
4109 /* enable GPHY 10M */
4110 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 4111 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 4112 rtl_writephy(tp, 0x1f, 0x0000);
4113
4114 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
4115 data = r8168_mac_ocp_read(tp, 0xdd02);
4116 ioffset_p3 = ((data & 0x80)>>7);
4117 ioffset_p3 <<= 3;
4118
4119 data = r8168_mac_ocp_read(tp, 0xdd00);
4120 ioffset_p3 |= ((data & (0xe000))>>13);
4121 ioffset_p2 = ((data & (0x1e00))>>9);
4122 ioffset_p1 = ((data & (0x01e0))>>5);
4123 ioffset_p0 = ((data & 0x0010)>>4);
4124 ioffset_p0 <<= 3;
4125 ioffset_p0 |= (data & (0x07));
4126 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
4127
05b9687b 4128 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
e2e2788e 4129 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
6e1d0b89
CHL		 4130 rtl_writephy(tp, 0x1f, 0x0bcf);
4131 rtl_writephy(tp, 0x16, data);
4132 rtl_writephy(tp, 0x1f, 0x0000);
4133 }
4134
4135 /* Modify rlen (TX LPF corner frequency) level */
4136 rtl_writephy(tp, 0x1f, 0x0bcd);
4137 data = rtl_readphy(tp, 0x16);
4138 data &= 0x000f;
4139 rlen = 0;
4140 if (data > 3)
4141 rlen = data - 3;
4142 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
4143 rtl_writephy(tp, 0x17, data);
4144 rtl_writephy(tp, 0x1f, 0x0bcd);
4145 rtl_writephy(tp, 0x1f, 0x0000);
4146
4147 /* disable phy pfm mode */
4148 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 4149 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 4150 rtl_writephy(tp, 0x1f, 0x0000);
4151
4152 /* Check ALDPS bit, disable it if enabled */
4153 rtl_writephy(tp, 0x1f, 0x0a43);
4154 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 4155 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 4156
4157 rtl_writephy(tp, 0x1f, 0x0000);
4158}
4159
935e2218
CHL		 4160static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4161{
4162 /* Enable PHY auto speed down */
4163 rtl_writephy(tp, 0x1f, 0x0a44);
4164 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4165 rtl_writephy(tp, 0x1f, 0x0000);
4166
4167 /* patch 10M & ALDPS */
4168 rtl_writephy(tp, 0x1f, 0x0bcc);
4169 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4170 rtl_writephy(tp, 0x1f, 0x0a44);
4171 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4172 rtl_writephy(tp, 0x1f, 0x0a43);
4173 rtl_writephy(tp, 0x13, 0x8084);
4174 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4175 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4176 rtl_writephy(tp, 0x1f, 0x0000);
4177
4178 /* Enable EEE auto-fallback function */
4179 rtl_writephy(tp, 0x1f, 0x0a4b);
4180 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4181 rtl_writephy(tp, 0x1f, 0x0000);
4182
4183 /* Enable UC LPF tune function */
4184 rtl_writephy(tp, 0x1f, 0x0a43);
4185 rtl_writephy(tp, 0x13, 0x8012);
4186 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4187 rtl_writephy(tp, 0x1f, 0x0000);
4188
4189 /* set rg_sel_sdm_rate */
4190 rtl_writephy(tp, 0x1f, 0x0c42);
4191 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4192 rtl_writephy(tp, 0x1f, 0x0000);
4193
4194 /* Check ALDPS bit, disable it if enabled */
4195 rtl_writephy(tp, 0x1f, 0x0a43);
4196 if (rtl_readphy(tp, 0x10) & 0x0004)
4197 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4198
4199 rtl_writephy(tp, 0x1f, 0x0000);
4200}
4201
4202static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4203{
4204 /* patch 10M & ALDPS */
4205 rtl_writephy(tp, 0x1f, 0x0bcc);
4206 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4207 rtl_writephy(tp, 0x1f, 0x0a44);
4208 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4209 rtl_writephy(tp, 0x1f, 0x0a43);
4210 rtl_writephy(tp, 0x13, 0x8084);
4211 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4212 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4213 rtl_writephy(tp, 0x1f, 0x0000);
4214
4215 /* Enable UC LPF tune function */
4216 rtl_writephy(tp, 0x1f, 0x0a43);
4217 rtl_writephy(tp, 0x13, 0x8012);
4218 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4219 rtl_writephy(tp, 0x1f, 0x0000);
4220
4221 /* Set rg_sel_sdm_rate */
4222 rtl_writephy(tp, 0x1f, 0x0c42);
4223 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4224 rtl_writephy(tp, 0x1f, 0x0000);
4225
4226 /* Channel estimation parameters */
4227 rtl_writephy(tp, 0x1f, 0x0a43);
4228 rtl_writephy(tp, 0x13, 0x80f3);
4229 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4230 rtl_writephy(tp, 0x13, 0x80f0);
4231 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4232 rtl_writephy(tp, 0x13, 0x80ef);
4233 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4234 rtl_writephy(tp, 0x13, 0x80f6);
4235 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4236 rtl_writephy(tp, 0x13, 0x80ec);
4237 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4238 rtl_writephy(tp, 0x13, 0x80ed);
4239 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4240 rtl_writephy(tp, 0x13, 0x80f2);
4241 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4242 rtl_writephy(tp, 0x13, 0x80f4);
4243 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4244 rtl_writephy(tp, 0x1f, 0x0a43);
4245 rtl_writephy(tp, 0x13, 0x8110);
4246 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4247 rtl_writephy(tp, 0x13, 0x810f);
4248 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4249 rtl_writephy(tp, 0x13, 0x8111);
4250 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4251 rtl_writephy(tp, 0x13, 0x8113);
4252 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4253 rtl_writephy(tp, 0x13, 0x8115);
4254 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4255 rtl_writephy(tp, 0x13, 0x810e);
4256 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4257 rtl_writephy(tp, 0x13, 0x810c);
4258 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4259 rtl_writephy(tp, 0x13, 0x810b);
4260 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4261 rtl_writephy(tp, 0x1f, 0x0a43);
4262 rtl_writephy(tp, 0x13, 0x80d1);
4263 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4264 rtl_writephy(tp, 0x13, 0x80cd);
4265 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4266 rtl_writephy(tp, 0x13, 0x80d3);
4267 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4268 rtl_writephy(tp, 0x13, 0x80d5);
4269 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4270 rtl_writephy(tp, 0x13, 0x80d7);
4271 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4272
4273 /* Force PWM-mode */
4274 rtl_writephy(tp, 0x1f, 0x0bcd);
4275 rtl_writephy(tp, 0x14, 0x5065);
4276 rtl_writephy(tp, 0x14, 0xd065);
4277 rtl_writephy(tp, 0x1f, 0x0bc8);
4278 rtl_writephy(tp, 0x12, 0x00ed);
4279 rtl_writephy(tp, 0x1f, 0x0bcd);
4280 rtl_writephy(tp, 0x14, 0x1065);
4281 rtl_writephy(tp, 0x14, 0x9065);
4282 rtl_writephy(tp, 0x14, 0x1065);
4283 rtl_writephy(tp, 0x1f, 0x0000);
4284
4285 /* Check ALDPS bit, disable it if enabled */
4286 rtl_writephy(tp, 0x1f, 0x0a43);
4287 if (rtl_readphy(tp, 0x10) & 0x0004)
4288 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4289
4290 rtl_writephy(tp, 0x1f, 0x0000);
4291}
4292
4da19633 4293static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 4294{
350f7596 4295 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 4296 { 0x1f, 0x0003 },
4297 { 0x08, 0x441d },
4298 { 0x01, 0x9100 },
4299 { 0x1f, 0x0000 }
4300 };
4301
4da19633 4302 rtl_writephy(tp, 0x1f, 0x0000);
4303 rtl_patchphy(tp, 0x11, 1 << 12);
4304 rtl_patchphy(tp, 0x19, 1 << 13);
4305 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 4306
4da19633 4307 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 4308}
4309
5a5e4443
HW		 4310static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4311{
4312 static const struct phy_reg phy_reg_init[] = {
4313 { 0x1f, 0x0005 },
4314 { 0x1a, 0x0000 },
4315 { 0x1f, 0x0000 },
4316
4317 { 0x1f, 0x0004 },
4318 { 0x1c, 0x0000 },
4319 { 0x1f, 0x0000 },
4320
4321 { 0x1f, 0x0001 },
4322 { 0x15, 0x7701 },
4323 { 0x1f, 0x0000 }
4324 };
4325
4326 /* Disable ALDPS before ram code */
eef63cc1
FR		 4327 rtl_writephy(tp, 0x1f, 0x0000);
4328 rtl_writephy(tp, 0x18, 0x0310);
4329 msleep(100);
5a5e4443 4330
953a12cc 4331 rtl_apply_firmware(tp);
5a5e4443
HW		 4332
4333 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4334}
4335
7e18dca1
HW		 4336static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4337{
7e18dca1 4338 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 4339 rtl_writephy(tp, 0x1f, 0x0000);
4340 rtl_writephy(tp, 0x18, 0x0310);
4341 msleep(20);
7e18dca1
HW		 4342
4343 rtl_apply_firmware(tp);
4344
4345 /* EEE setting */
fdf6fc06 4346 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 4347 rtl_writephy(tp, 0x1f, 0x0004);
4348 rtl_writephy(tp, 0x10, 0x401f);
4349 rtl_writephy(tp, 0x19, 0x7030);
4350 rtl_writephy(tp, 0x1f, 0x0000);
4351}
4352
5598bfe5
HW		 4353static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4354{
5598bfe5
HW		 4355 static const struct phy_reg phy_reg_init[] = {
4356 { 0x1f, 0x0004 },
4357 { 0x10, 0xc07f },
4358 { 0x19, 0x7030 },
4359 { 0x1f, 0x0000 }
4360 };
4361
4362 /* Disable ALDPS before ram code */
eef63cc1
FR		 4363 rtl_writephy(tp, 0x1f, 0x0000);
4364 rtl_writephy(tp, 0x18, 0x0310);
4365 msleep(100);
5598bfe5
HW		 4366
4367 rtl_apply_firmware(tp);
4368
fdf6fc06 4369 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4370 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4371
fdf6fc06 4372 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4373}
4374
5615d9f1
FR		 4375static void rtl_hw_phy_config(struct net_device *dev)
4376{
4377 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 4378
4379 rtl8169_print_mac_version(tp);
4380
4381 switch (tp->mac_version) {
4382 case RTL_GIGA_MAC_VER_01:
4383 break;
4384 case RTL_GIGA_MAC_VER_02:
4385 case RTL_GIGA_MAC_VER_03:
4da19633 4386 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 4387 break;
4388 case RTL_GIGA_MAC_VER_04:
4da19633 4389 rtl8169sb_hw_phy_config(tp);
5615d9f1 4390 break;
2e955856 4391 case RTL_GIGA_MAC_VER_05:
4da19633 4392 rtl8169scd_hw_phy_config(tp);
2e955856 4393 break;
8c7006aa 4394 case RTL_GIGA_MAC_VER_06:
4da19633 4395 rtl8169sce_hw_phy_config(tp);
8c7006aa 4396 break;
2857ffb7
FR		 4397 case RTL_GIGA_MAC_VER_07:
4398 case RTL_GIGA_MAC_VER_08:
4399 case RTL_GIGA_MAC_VER_09:
4da19633 4400 rtl8102e_hw_phy_config(tp);
2857ffb7 4401 break;
236b8082 4402 case RTL_GIGA_MAC_VER_11:
4da19633 4403 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 4404 break;
4405 case RTL_GIGA_MAC_VER_12:
4da19633 4406 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 4407 break;
4408 case RTL_GIGA_MAC_VER_17:
4da19633 4409 rtl8168bef_hw_phy_config(tp);
236b8082 4410 break;
867763c1 4411 case RTL_GIGA_MAC_VER_18:
4da19633 4412 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 4413 break;
4414 case RTL_GIGA_MAC_VER_19:
4da19633 4415 rtl8168c_1_hw_phy_config(tp);
867763c1 4416 break;
7da97ec9 4417 case RTL_GIGA_MAC_VER_20:
4da19633 4418 rtl8168c_2_hw_phy_config(tp);
7da97ec9 4419 break;
197ff761 4420 case RTL_GIGA_MAC_VER_21:
4da19633 4421 rtl8168c_3_hw_phy_config(tp);
197ff761 4422 break;
6fb07058 4423 case RTL_GIGA_MAC_VER_22:
4da19633 4424 rtl8168c_4_hw_phy_config(tp);
6fb07058 4425 break;
ef3386f0 4426 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 4427 case RTL_GIGA_MAC_VER_24:
4da19633 4428 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 4429 break;
5b538df9 4430 case RTL_GIGA_MAC_VER_25:
bca03d5f 4431 rtl8168d_1_hw_phy_config(tp);
daf9df6d 4432 break;
4433 case RTL_GIGA_MAC_VER_26:
bca03d5f 4434 rtl8168d_2_hw_phy_config(tp);
daf9df6d 4435 break;
4436 case RTL_GIGA_MAC_VER_27:
4da19633 4437 rtl8168d_3_hw_phy_config(tp);
5b538df9 4438 break;
e6de30d6 4439 case RTL_GIGA_MAC_VER_28:
4440 rtl8168d_4_hw_phy_config(tp);
4441 break;
5a5e4443
HW		 4442 case RTL_GIGA_MAC_VER_29:
4443 case RTL_GIGA_MAC_VER_30:
4444 rtl8105e_hw_phy_config(tp);
4445 break;
cecb5fd7
FR		 4446 case RTL_GIGA_MAC_VER_31:
4447 /* None. */
4448 break;
01dc7fec 4449 case RTL_GIGA_MAC_VER_32:
01dc7fec 4450 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4451 rtl8168e_1_hw_phy_config(tp);
4452 break;
4453 case RTL_GIGA_MAC_VER_34:
4454 rtl8168e_2_hw_phy_config(tp);
01dc7fec 4455 break;
c2218925
HW		 4456 case RTL_GIGA_MAC_VER_35:
4457 rtl8168f_1_hw_phy_config(tp);
4458 break;
4459 case RTL_GIGA_MAC_VER_36:
4460 rtl8168f_2_hw_phy_config(tp);
4461 break;
ef3386f0 4462
7e18dca1
HW		 4463 case RTL_GIGA_MAC_VER_37:
4464 rtl8402_hw_phy_config(tp);
4465 break;
4466
b3d7b2f2
HW		 4467 case RTL_GIGA_MAC_VER_38:
4468 rtl8411_hw_phy_config(tp);
4469 break;
4470
5598bfe5
HW		 4471 case RTL_GIGA_MAC_VER_39:
4472 rtl8106e_hw_phy_config(tp);
4473 break;
4474
c558386b
HW		 4475 case RTL_GIGA_MAC_VER_40:
4476 rtl8168g_1_hw_phy_config(tp);
4477 break;
57538c4a 4478 case RTL_GIGA_MAC_VER_42:
58152cd4 4479 case RTL_GIGA_MAC_VER_43:
45dd95c4 4480 case RTL_GIGA_MAC_VER_44:
57538c4a 4481 rtl8168g_2_hw_phy_config(tp);
4482 break;
6e1d0b89
CHL		 4483 case RTL_GIGA_MAC_VER_45:
4484 case RTL_GIGA_MAC_VER_47:
4485 rtl8168h_1_hw_phy_config(tp);
4486 break;
4487 case RTL_GIGA_MAC_VER_46:
4488 case RTL_GIGA_MAC_VER_48:
4489 rtl8168h_2_hw_phy_config(tp);
4490 break;
c558386b 4491
935e2218
CHL		 4492 case RTL_GIGA_MAC_VER_49:
4493 rtl8168ep_1_hw_phy_config(tp);
4494 break;
4495 case RTL_GIGA_MAC_VER_50:
4496 case RTL_GIGA_MAC_VER_51:
4497 rtl8168ep_2_hw_phy_config(tp);
4498 break;
4499
c558386b 4500 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 4501 default:
4502 break;
4503 }
4504}
4505
da78dbff 4506static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 4507{
1da177e4 4508 struct timer_list *timer = &tp->timer;
1da177e4
LT		 4509 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4510
bcf0bf90 4511 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 4512
4da19633 4513 if (tp->phy_reset_pending(tp)) {
5b0384f4 4514 /*
1da177e4
LT		 4515 * A busy loop could burn quite a few cycles on nowadays CPU.
4516 * Let's delay the execution of the timer for a few ticks.
4517 */
4518 timeout = HZ/10;
4519 goto out_mod_timer;
4520 }
4521
1ef7286e 4522 if (tp->link_ok(tp))
da78dbff 4523 return;
1da177e4 4524
9bb8eeb5 4525 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 4526
4da19633 4527 tp->phy_reset_enable(tp);
1da177e4
LT		 4528
4529out_mod_timer:
4530 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 4531}
4532
4533static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4534{
da78dbff
FR		 4535 if (!test_and_set_bit(flag, tp->wk.flags))
4536 schedule_work(&tp->wk.work);
da78dbff
FR		 4537}
4538
9de36ccf 4539static void rtl8169_phy_timer(struct timer_list *t)
da78dbff 4540{
9de36ccf 4541 struct rtl8169_private *tp = from_timer(tp, t, timer);
da78dbff 4542
98ddf986 4543 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 4544}
4545
ffc46952
FR		 4546DECLARE_RTL_COND(rtl_phy_reset_cond)
4547{
4548 return tp->phy_reset_pending(tp);
4549}
4550
bf793295
FR		 4551static void rtl8169_phy_reset(struct net_device *dev,
4552 struct rtl8169_private *tp)
4553{
4da19633 4554 tp->phy_reset_enable(tp);
ffc46952 4555 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 4556}
4557
2544bfc0
FR		 4558static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4559{
2544bfc0 4560 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
1ef7286e 4561 (RTL_R8(tp, PHYstatus) & TBI_Enable);
2544bfc0
FR		 4562}
4563
4ff96fa6
FR		 4564static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4565{
5615d9f1 4566 rtl_hw_phy_config(dev);
4ff96fa6 4567
77332894
MS		 4568 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4569 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 4570 RTL_W8(tp, 0x82, 0x01);
77332894 4571 }
4ff96fa6 4572
6dccd16b
FR		 4573 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4574
4575 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4576 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4577
bcf0bf90 4578 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6 4579 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 4580 RTL_W8(tp, 0x82, 0x01);
4ff96fa6 4581 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4582 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4583 }
4584
bf793295
FR		 4585 rtl8169_phy_reset(dev, tp);
4586
54405cde 4587 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 4588 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4589 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4590 (tp->mii.supports_gmii ?
4591 ADVERTISED_1000baseT_Half |
4592 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 4593
2544bfc0 4594 if (rtl_tbi_enabled(tp))
bf82c189 4595 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 4596}
4597
773d2021
FR		 4598static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4599{
da78dbff 4600 rtl_lock_work(tp);
773d2021 4601
1ef7286e 4602 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
908ba2bf 4603
1ef7286e
AS		 4604 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4605 RTL_R32(tp, MAC4);
908ba2bf 4606
1ef7286e
AS		 4607 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4608 RTL_R32(tp, MAC0);
908ba2bf 4609
9ecb9aab 4610 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4611 rtl_rar_exgmac_set(tp, addr);
c28aa385 4612
1ef7286e 4613 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
773d2021 4614
da78dbff 4615 rtl_unlock_work(tp);
773d2021
FR		 4616}
4617
4618static int rtl_set_mac_address(struct net_device *dev, void *p)
4619{
4620 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 4621 struct device *d = tp_to_dev(tp);
1f7aa2bc 4622 int ret;
773d2021 4623
1f7aa2bc
HK		 4624 ret = eth_mac_addr(dev, p);
4625 if (ret)
4626 return ret;
773d2021 4627
f51d4a10
CHL		 4628 pm_runtime_get_noresume(d);
4629
4630 if (pm_runtime_active(d))
4631 rtl_rar_set(tp, dev->dev_addr);
4632
4633 pm_runtime_put_noidle(d);
773d2021
FR		 4634
4635 return 0;
4636}
4637
5f787a1a
FR		 4638static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4639{
4640 struct rtl8169_private *tp = netdev_priv(dev);
4641 struct mii_ioctl_data *data = if_mii(ifr);
4642
8b4ab28d
FR		 4643 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4644}
5f787a1a 4645
cecb5fd7
FR		 4646static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4647 struct mii_ioctl_data *data, int cmd)
8b4ab28d 4648{
5f787a1a
FR		 4649 switch (cmd) {
4650 case SIOCGMIIPHY:
4651 data->phy_id = 32; /* Internal PHY */
4652 return 0;
4653
4654 case SIOCGMIIREG:
4da19633 4655 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 4656 return 0;
4657
4658 case SIOCSMIIREG:
4da19633 4659 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 4660 return 0;
4661 }
4662 return -EOPNOTSUPP;
4663}
4664
8b4ab28d
FR		 4665static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4666{
4667 return -EOPNOTSUPP;
4668}
4669
baf63293 4670static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4671{
4672 struct mdio_ops *ops = &tp->mdio_ops;
4673
4674 switch (tp->mac_version) {
4675 case RTL_GIGA_MAC_VER_27:
4676 ops->write = r8168dp_1_mdio_write;
4677 ops->read = r8168dp_1_mdio_read;
4678 break;
e6de30d6 4679 case RTL_GIGA_MAC_VER_28:
4804b3b3 4680 case RTL_GIGA_MAC_VER_31:
e6de30d6 4681 ops->write = r8168dp_2_mdio_write;
4682 ops->read = r8168dp_2_mdio_read;
4683 break;
c558386b
HW		 4684 case RTL_GIGA_MAC_VER_40:
4685 case RTL_GIGA_MAC_VER_41:
57538c4a 4686 case RTL_GIGA_MAC_VER_42:
58152cd4 4687 case RTL_GIGA_MAC_VER_43:
45dd95c4 4688 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4689 case RTL_GIGA_MAC_VER_45:
4690 case RTL_GIGA_MAC_VER_46:
4691 case RTL_GIGA_MAC_VER_47:
4692 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4693 case RTL_GIGA_MAC_VER_49:
4694 case RTL_GIGA_MAC_VER_50:
4695 case RTL_GIGA_MAC_VER_51:
c558386b
HW		 4696 ops->write = r8168g_mdio_write;
4697 ops->read = r8168g_mdio_read;
4698 break;
c0e45c1c 4699 default:
4700 ops->write = r8169_mdio_write;
4701 ops->read = r8169_mdio_read;
4702 break;
4703 }
4704}
4705
e2409d83 4706static void rtl_speed_down(struct rtl8169_private *tp)
4707{
4708 u32 adv;
4709 int lpa;
4710
4711 rtl_writephy(tp, 0x1f, 0x0000);
4712 lpa = rtl_readphy(tp, MII_LPA);
4713
4714 if (lpa & (LPA_10HALF | LPA_10FULL))
4715 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4716 else if (lpa & (LPA_100HALF | LPA_100FULL))
4717 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4718 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4719 else
4720 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4721 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4722 (tp->mii.supports_gmii ?
4723 ADVERTISED_1000baseT_Half |
4724 ADVERTISED_1000baseT_Full : 0);
4725
4726 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4727 adv);
4728}
4729
649b3b8c 4730static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4731{
649b3b8c 4732 switch (tp->mac_version) {
b00e69de
CB		 4733 case RTL_GIGA_MAC_VER_25:
4734 case RTL_GIGA_MAC_VER_26:
649b3b8c 4735 case RTL_GIGA_MAC_VER_29:
4736 case RTL_GIGA_MAC_VER_30:
4737 case RTL_GIGA_MAC_VER_32:
4738 case RTL_GIGA_MAC_VER_33:
4739 case RTL_GIGA_MAC_VER_34:
7e18dca1 4740 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4741 case RTL_GIGA_MAC_VER_38:
5598bfe5 4742 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 4743 case RTL_GIGA_MAC_VER_40:
4744 case RTL_GIGA_MAC_VER_41:
57538c4a 4745 case RTL_GIGA_MAC_VER_42:
58152cd4 4746 case RTL_GIGA_MAC_VER_43:
45dd95c4 4747 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4748 case RTL_GIGA_MAC_VER_45:
4749 case RTL_GIGA_MAC_VER_46:
4750 case RTL_GIGA_MAC_VER_47:
4751 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4752 case RTL_GIGA_MAC_VER_49:
4753 case RTL_GIGA_MAC_VER_50:
4754 case RTL_GIGA_MAC_VER_51:
1ef7286e 4755 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
649b3b8c 4756 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4757 break;
4758 default:
4759 break;
4760 }
4761}
4762
4763static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4764{
4765 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4766 return false;
4767
e2409d83 4768 rtl_speed_down(tp);
649b3b8c 4769 rtl_wol_suspend_quirk(tp);
4770
4771 return true;
4772}
4773
065c27c1 4774static void r810x_phy_power_down(struct rtl8169_private *tp)
4775{
4776 rtl_writephy(tp, 0x1f, 0x0000);
4777 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4778}
4779
4780static void r810x_phy_power_up(struct rtl8169_private *tp)
4781{
4782 rtl_writephy(tp, 0x1f, 0x0000);
4783 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4784}
4785
4786static void r810x_pll_power_down(struct rtl8169_private *tp)
4787{
649b3b8c 4788 if (rtl_wol_pll_power_down(tp))
065c27c1 4789 return;
065c27c1 4790
4791 r810x_phy_power_down(tp);
0004299a
HW		 4792
4793 switch (tp->mac_version) {
4794 case RTL_GIGA_MAC_VER_07:
4795 case RTL_GIGA_MAC_VER_08:
4796 case RTL_GIGA_MAC_VER_09:
4797 case RTL_GIGA_MAC_VER_10:
4798 case RTL_GIGA_MAC_VER_13:
4799 case RTL_GIGA_MAC_VER_16:
4800 break;
4801 default:
1ef7286e 4802 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
0004299a
HW		 4803 break;
4804 }
065c27c1 4805}
4806
4807static void r810x_pll_power_up(struct rtl8169_private *tp)
4808{
4809 r810x_phy_power_up(tp);
0004299a
HW		 4810
4811 switch (tp->mac_version) {
4812 case RTL_GIGA_MAC_VER_07:
4813 case RTL_GIGA_MAC_VER_08:
4814 case RTL_GIGA_MAC_VER_09:
4815 case RTL_GIGA_MAC_VER_10:
4816 case RTL_GIGA_MAC_VER_13:
4817 case RTL_GIGA_MAC_VER_16:
4818 break;
6e1d0b89
CHL		 4819 case RTL_GIGA_MAC_VER_47:
4820 case RTL_GIGA_MAC_VER_48:
1ef7286e 4821 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
6e1d0b89 4822 break;
0004299a 4823 default:
1ef7286e 4824 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
0004299a
HW		 4825 break;
4826 }
065c27c1 4827}
4828
4829static void r8168_phy_power_up(struct rtl8169_private *tp)
4830{
4831 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4832 switch (tp->mac_version) {
4833 case RTL_GIGA_MAC_VER_11:
4834 case RTL_GIGA_MAC_VER_12:
4835 case RTL_GIGA_MAC_VER_17:
4836 case RTL_GIGA_MAC_VER_18:
4837 case RTL_GIGA_MAC_VER_19:
4838 case RTL_GIGA_MAC_VER_20:
4839 case RTL_GIGA_MAC_VER_21:
4840 case RTL_GIGA_MAC_VER_22:
4841 case RTL_GIGA_MAC_VER_23:
4842 case RTL_GIGA_MAC_VER_24:
4843 case RTL_GIGA_MAC_VER_25:
4844 case RTL_GIGA_MAC_VER_26:
4845 case RTL_GIGA_MAC_VER_27:
4846 case RTL_GIGA_MAC_VER_28:
4847 case RTL_GIGA_MAC_VER_31:
4848 rtl_writephy(tp, 0x0e, 0x0000);
4849 break;
4850 default:
4851 break;
4852 }
065c27c1 4853 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4854}
4855
4856static void r8168_phy_power_down(struct rtl8169_private *tp)
4857{
4858 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4859 switch (tp->mac_version) {
4860 case RTL_GIGA_MAC_VER_32:
4861 case RTL_GIGA_MAC_VER_33:
beb330a4 4862 case RTL_GIGA_MAC_VER_40:
4863 case RTL_GIGA_MAC_VER_41:
01dc7fec 4864 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4865 break;
4866
4867 case RTL_GIGA_MAC_VER_11:
4868 case RTL_GIGA_MAC_VER_12:
4869 case RTL_GIGA_MAC_VER_17:
4870 case RTL_GIGA_MAC_VER_18:
4871 case RTL_GIGA_MAC_VER_19:
4872 case RTL_GIGA_MAC_VER_20:
4873 case RTL_GIGA_MAC_VER_21:
4874 case RTL_GIGA_MAC_VER_22:
4875 case RTL_GIGA_MAC_VER_23:
4876 case RTL_GIGA_MAC_VER_24:
4877 case RTL_GIGA_MAC_VER_25:
4878 case RTL_GIGA_MAC_VER_26:
4879 case RTL_GIGA_MAC_VER_27:
4880 case RTL_GIGA_MAC_VER_28:
4881 case RTL_GIGA_MAC_VER_31:
4882 rtl_writephy(tp, 0x0e, 0x0200);
4883 default:
4884 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4885 break;
4886 }
065c27c1 4887}
4888
4889static void r8168_pll_power_down(struct rtl8169_private *tp)
4890{
9dbe7896 4891 if (r8168_check_dash(tp))
065c27c1 4892 return;
4893
cecb5fd7
FR		 4894 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4895 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
1ef7286e 4896 (RTL_R16(tp, CPlusCmd) & ASF)) {
065c27c1 4897 return;
4898 }
4899
01dc7fec 4900 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4901 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4902 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4903
649b3b8c 4904 if (rtl_wol_pll_power_down(tp))
065c27c1 4905 return;
065c27c1 4906
4907 r8168_phy_power_down(tp);
4908
4909 switch (tp->mac_version) {
4910 case RTL_GIGA_MAC_VER_25:
4911 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4912 case RTL_GIGA_MAC_VER_27:
4913 case RTL_GIGA_MAC_VER_28:
4804b3b3 4914 case RTL_GIGA_MAC_VER_31:
01dc7fec 4915 case RTL_GIGA_MAC_VER_32:
4916 case RTL_GIGA_MAC_VER_33:
42fde737 4917 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4918 case RTL_GIGA_MAC_VER_45:
4919 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4920 case RTL_GIGA_MAC_VER_50:
4921 case RTL_GIGA_MAC_VER_51:
1ef7286e 4922 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
065c27c1 4923 break;
beb330a4 4924 case RTL_GIGA_MAC_VER_40:
4925 case RTL_GIGA_MAC_VER_41:
935e2218 4926 case RTL_GIGA_MAC_VER_49:
706123d0 4927 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 4928 0xfc000000, ERIAR_EXGMAC);
1ef7286e 4929 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
beb330a4 4930 break;
065c27c1 4931 }
4932}
4933
4934static void r8168_pll_power_up(struct rtl8169_private *tp)
4935{
065c27c1 4936 switch (tp->mac_version) {
4937 case RTL_GIGA_MAC_VER_25:
4938 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4939 case RTL_GIGA_MAC_VER_27:
4940 case RTL_GIGA_MAC_VER_28:
4804b3b3 4941 case RTL_GIGA_MAC_VER_31:
01dc7fec 4942 case RTL_GIGA_MAC_VER_32:
4943 case RTL_GIGA_MAC_VER_33:
1ef7286e 4944 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
065c27c1 4945 break;
42fde737 4946 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4947 case RTL_GIGA_MAC_VER_45:
4948 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4949 case RTL_GIGA_MAC_VER_50:
4950 case RTL_GIGA_MAC_VER_51:
1ef7286e 4951 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
6e1d0b89 4952 break;
beb330a4 4953 case RTL_GIGA_MAC_VER_40:
4954 case RTL_GIGA_MAC_VER_41:
935e2218 4955 case RTL_GIGA_MAC_VER_49:
1ef7286e 4956 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
706123d0 4957 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 4958 0x00000000, ERIAR_EXGMAC);
4959 break;
065c27c1 4960 }
4961
4962 r8168_phy_power_up(tp);
4963}
4964
d58d46b5
FR		 4965static void rtl_generic_op(struct rtl8169_private *tp,
4966 void (*op)(struct rtl8169_private *))
065c27c1 4967{
4968 if (op)
4969 op(tp);
4970}
4971
4972static void rtl_pll_power_down(struct rtl8169_private *tp)
4973{
d58d46b5 4974 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4975}
4976
4977static void rtl_pll_power_up(struct rtl8169_private *tp)
4978{
d58d46b5 4979 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4980}
4981
baf63293 4982static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4983{
4984 struct pll_power_ops *ops = &tp->pll_power_ops;
4985
4986 switch (tp->mac_version) {
4987 case RTL_GIGA_MAC_VER_07:
4988 case RTL_GIGA_MAC_VER_08:
4989 case RTL_GIGA_MAC_VER_09:
4990 case RTL_GIGA_MAC_VER_10:
4991 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4992 case RTL_GIGA_MAC_VER_29:
4993 case RTL_GIGA_MAC_VER_30:
7e18dca1 4994 case RTL_GIGA_MAC_VER_37:
5598bfe5 4995 case RTL_GIGA_MAC_VER_39:
58152cd4 4996 case RTL_GIGA_MAC_VER_43:
6e1d0b89
CHL		 4997 case RTL_GIGA_MAC_VER_47:
4998 case RTL_GIGA_MAC_VER_48:
065c27c1 4999 ops->down = r810x_pll_power_down;
5000 ops->up = r810x_pll_power_up;
5001 break;
5002
5003 case RTL_GIGA_MAC_VER_11:
5004 case RTL_GIGA_MAC_VER_12:
5005 case RTL_GIGA_MAC_VER_17:
5006 case RTL_GIGA_MAC_VER_18:
5007 case RTL_GIGA_MAC_VER_19:
5008 case RTL_GIGA_MAC_VER_20:
5009 case RTL_GIGA_MAC_VER_21:
5010 case RTL_GIGA_MAC_VER_22:
5011 case RTL_GIGA_MAC_VER_23:
5012 case RTL_GIGA_MAC_VER_24:
5013 case RTL_GIGA_MAC_VER_25:
5014 case RTL_GIGA_MAC_VER_26:
5015 case RTL_GIGA_MAC_VER_27:
e6de30d6 5016 case RTL_GIGA_MAC_VER_28:
4804b3b3 5017 case RTL_GIGA_MAC_VER_31:
01dc7fec 5018 case RTL_GIGA_MAC_VER_32:
5019 case RTL_GIGA_MAC_VER_33:
70090424 5020 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 5021 case RTL_GIGA_MAC_VER_35:
5022 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 5023 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 5024 case RTL_GIGA_MAC_VER_40:
5025 case RTL_GIGA_MAC_VER_41:
57538c4a 5026 case RTL_GIGA_MAC_VER_42:
45dd95c4 5027 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5028 case RTL_GIGA_MAC_VER_45:
5029 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 5030 case RTL_GIGA_MAC_VER_49:
5031 case RTL_GIGA_MAC_VER_50:
5032 case RTL_GIGA_MAC_VER_51:
065c27c1 5033 ops->down = r8168_pll_power_down;
5034 ops->up = r8168_pll_power_up;
5035 break;
5036
5037 default:
5038 ops->down = NULL;
5039 ops->up = NULL;
5040 break;
5041 }
5042}
5043
e542a226
HW		 5044static void rtl_init_rxcfg(struct rtl8169_private *tp)
5045{
e542a226
HW		 5046 switch (tp->mac_version) {
5047 case RTL_GIGA_MAC_VER_01:
5048 case RTL_GIGA_MAC_VER_02:
5049 case RTL_GIGA_MAC_VER_03:
5050 case RTL_GIGA_MAC_VER_04:
5051 case RTL_GIGA_MAC_VER_05:
5052 case RTL_GIGA_MAC_VER_06:
5053 case RTL_GIGA_MAC_VER_10:
5054 case RTL_GIGA_MAC_VER_11:
5055 case RTL_GIGA_MAC_VER_12:
5056 case RTL_GIGA_MAC_VER_13:
5057 case RTL_GIGA_MAC_VER_14:
5058 case RTL_GIGA_MAC_VER_15:
5059 case RTL_GIGA_MAC_VER_16:
5060 case RTL_GIGA_MAC_VER_17:
1ef7286e 5061 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
e542a226
HW		 5062 break;
5063 case RTL_GIGA_MAC_VER_18:
5064 case RTL_GIGA_MAC_VER_19:
5065 case RTL_GIGA_MAC_VER_20:
5066 case RTL_GIGA_MAC_VER_21:
5067 case RTL_GIGA_MAC_VER_22:
5068 case RTL_GIGA_MAC_VER_23:
5069 case RTL_GIGA_MAC_VER_24:
eb2dc35d 5070 case RTL_GIGA_MAC_VER_34:
3ced8c95 5071 case RTL_GIGA_MAC_VER_35:
1ef7286e 5072 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
e542a226 5073 break;
beb330a4 5074 case RTL_GIGA_MAC_VER_40:
5075 case RTL_GIGA_MAC_VER_41:
57538c4a 5076 case RTL_GIGA_MAC_VER_42:
58152cd4 5077 case RTL_GIGA_MAC_VER_43:
45dd95c4 5078 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5079 case RTL_GIGA_MAC_VER_45:
5080 case RTL_GIGA_MAC_VER_46:
5081 case RTL_GIGA_MAC_VER_47:
5082 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 5083 case RTL_GIGA_MAC_VER_49:
5084 case RTL_GIGA_MAC_VER_50:
5085 case RTL_GIGA_MAC_VER_51:
1ef7286e 5086 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 5087 break;
e542a226 5088 default:
1ef7286e 5089 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
e542a226
HW		 5090 break;
5091 }
5092}
5093
92fc43b4
HW		 5094static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
5095{
9fba0812 5096 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 5097}
5098
d58d46b5
FR		 5099static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
5100{
1ef7286e 5101 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
d58d46b5 5102 rtl_generic_op(tp, tp->jumbo_ops.enable);
1ef7286e 5103 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 5104}
5105
5106static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5107{
1ef7286e 5108 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
d58d46b5 5109 rtl_generic_op(tp, tp->jumbo_ops.disable);
1ef7286e 5110 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 5111}
5112
5113static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5114{
1ef7286e
AS		 5115 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
5116 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
cb73200c 5117 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 5118}
5119
5120static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5121{
1ef7286e
AS		 5122 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
5123 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
8d98aa39 5124 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 5125}
5126
5127static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5128{
1ef7286e 5129 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
d58d46b5
FR		 5130}
5131
5132static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5133{
1ef7286e 5134 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
d58d46b5
FR		 5135}
5136
5137static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5138{
1ef7286e
AS		 5139 RTL_W8(tp, MaxTxPacketSize, 0x3f);
5140 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
5141 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
cb73200c 5142 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 5143}
5144
5145static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5146{
1ef7286e
AS		 5147 RTL_W8(tp, MaxTxPacketSize, 0x0c);
5148 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
5149 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
8d98aa39 5150 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 5151}
5152
5153static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5154{
cb73200c 5155 rtl_tx_performance_tweak(tp,
f65d539c 5156 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 5157}
5158
5159static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5160{
cb73200c 5161 rtl_tx_performance_tweak(tp,
8d98aa39 5162 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 5163}
5164
5165static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5166{
d58d46b5
FR		 5167 r8168b_0_hw_jumbo_enable(tp);
5168
1ef7286e 5169 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
d58d46b5
FR		 5170}
5171
5172static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5173{
d58d46b5
FR		 5174 r8168b_0_hw_jumbo_disable(tp);
5175
1ef7286e 5176 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
d58d46b5
FR		 5177}
5178
baf63293 5179static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 5180{
5181 struct jumbo_ops *ops = &tp->jumbo_ops;
5182
5183 switch (tp->mac_version) {
5184 case RTL_GIGA_MAC_VER_11:
5185 ops->disable = r8168b_0_hw_jumbo_disable;
5186 ops->enable = r8168b_0_hw_jumbo_enable;
5187 break;
5188 case RTL_GIGA_MAC_VER_12:
5189 case RTL_GIGA_MAC_VER_17:
5190 ops->disable = r8168b_1_hw_jumbo_disable;
5191 ops->enable = r8168b_1_hw_jumbo_enable;
5192 break;
5193 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5194 case RTL_GIGA_MAC_VER_19:
5195 case RTL_GIGA_MAC_VER_20:
5196 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5197 case RTL_GIGA_MAC_VER_22:
5198 case RTL_GIGA_MAC_VER_23:
5199 case RTL_GIGA_MAC_VER_24:
5200 case RTL_GIGA_MAC_VER_25:
5201 case RTL_GIGA_MAC_VER_26:
5202 ops->disable = r8168c_hw_jumbo_disable;
5203 ops->enable = r8168c_hw_jumbo_enable;
5204 break;
5205 case RTL_GIGA_MAC_VER_27:
5206 case RTL_GIGA_MAC_VER_28:
5207 ops->disable = r8168dp_hw_jumbo_disable;
5208 ops->enable = r8168dp_hw_jumbo_enable;
5209 break;
5210 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5211 case RTL_GIGA_MAC_VER_32:
5212 case RTL_GIGA_MAC_VER_33:
5213 case RTL_GIGA_MAC_VER_34:
5214 ops->disable = r8168e_hw_jumbo_disable;
5215 ops->enable = r8168e_hw_jumbo_enable;
5216 break;
5217
5218 /*
5219 * No action needed for jumbo frames with 8169.
5220 * No jumbo for 810x at all.
5221 */
c558386b
HW		 5222 case RTL_GIGA_MAC_VER_40:
5223 case RTL_GIGA_MAC_VER_41:
57538c4a 5224 case RTL_GIGA_MAC_VER_42:
58152cd4 5225 case RTL_GIGA_MAC_VER_43:
45dd95c4 5226 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5227 case RTL_GIGA_MAC_VER_45:
5228 case RTL_GIGA_MAC_VER_46:
5229 case RTL_GIGA_MAC_VER_47:
5230 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 5231 case RTL_GIGA_MAC_VER_49:
5232 case RTL_GIGA_MAC_VER_50:
5233 case RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 5234 default:
5235 ops->disable = NULL;
5236 ops->enable = NULL;
5237 break;
5238 }
5239}
5240
ffc46952
FR		 5241DECLARE_RTL_COND(rtl_chipcmd_cond)
5242{
1ef7286e 5243 return RTL_R8(tp, ChipCmd) & CmdReset;
ffc46952
FR		 5244}
5245
6f43adc8
FR		 5246static void rtl_hw_reset(struct rtl8169_private *tp)
5247{
1ef7286e 5248 RTL_W8(tp, ChipCmd, CmdReset);
6f43adc8 5249
ffc46952 5250 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 5251}
5252
b6ffd97f 5253static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 5254{
b6ffd97f
FR		 5255 struct rtl_fw *rtl_fw;
5256 const char *name;
5257 int rc = -ENOMEM;
953a12cc 5258
b6ffd97f
FR		 5259 name = rtl_lookup_firmware_name(tp);
5260 if (!name)
5261 goto out_no_firmware;
953a12cc 5262
b6ffd97f
FR		 5263 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5264 if (!rtl_fw)
5265 goto err_warn;
31bd204f 5266
1e1205b7 5267 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
b6ffd97f
FR		 5268 if (rc < 0)
5269 goto err_free;
5270
fd112f2e
FR		 5271 rc = rtl_check_firmware(tp, rtl_fw);
5272 if (rc < 0)
5273 goto err_release_firmware;
5274
b6ffd97f
FR		 5275 tp->rtl_fw = rtl_fw;
5276out:
5277 return;
5278
fd112f2e
FR		 5279err_release_firmware:
5280 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 5281err_free:
5282 kfree(rtl_fw);
5283err_warn:
5284 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5285 name, rc);
5286out_no_firmware:
5287 tp->rtl_fw = NULL;
5288 goto out;
5289}
5290
5291static void rtl_request_firmware(struct rtl8169_private *tp)
5292{
5293 if (IS_ERR(tp->rtl_fw))
5294 rtl_request_uncached_firmware(tp);
953a12cc
FR		 5295}
5296
92fc43b4
HW		 5297static void rtl_rx_close(struct rtl8169_private *tp)
5298{
1ef7286e 5299 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 5300}
5301
ffc46952
FR		 5302DECLARE_RTL_COND(rtl_npq_cond)
5303{
1ef7286e 5304 return RTL_R8(tp, TxPoll) & NPQ;
ffc46952
FR		 5305}
5306
5307DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5308{
1ef7286e 5309 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
ffc46952
FR		 5310}
5311
e6de30d6 5312static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4
LT		 5313{
5314 /* Disable interrupts */
811fd301 5315 rtl8169_irq_mask_and_ack(tp);
1da177e4 5316
92fc43b4
HW		 5317 rtl_rx_close(tp);
5318
5d2e1957 5319 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 5320 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5321 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 5322 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925 5323 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
6e1d0b89
CHL		 5324 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5325 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5326 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5327 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5328 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5329 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5330 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5331 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5332 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5333 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5334 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5335 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
935e2218
CHL		 5336 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5337 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5338 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5339 tp->mac_version == RTL_GIGA_MAC_VER_51) {
1ef7286e 5340 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
ffc46952 5341 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4 5342 } else {
1ef7286e 5343 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
92fc43b4 5344 udelay(100);
e6de30d6 5345 }
5346
92fc43b4 5347 rtl_hw_reset(tp);
1da177e4
LT		 5348}
5349
7f796d83 5350static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6 5351{
9cb427b6 5352 /* Set DMA burst size and Interframe Gap Time */
1ef7286e 5353 RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
9cb427b6
FR		 5354 (InterFrameGap << TxInterFrameGapShift));
5355}
5356
07ce4064 5357static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 5358{
5359 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5360
07ce4064
FR		 5361 tp->hw_start(dev);
5362
da78dbff 5363 rtl_irq_enable_all(tp);
07ce4064
FR		 5364}
5365
1ef7286e 5366static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
7f796d83
FR		 5367{
5368 /*
5369 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5370 * register to be written before TxDescAddrLow to work.
5371 * Switching from MMIO to I/O access fixes the issue as well.
5372 */
1ef7286e
AS		 5373 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5374 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5375 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5376 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 5377}
5378
1ef7286e 5379static u16 rtl_rw_cpluscmd(struct rtl8169_private *tp)
7f796d83
FR		 5380{
5381 u16 cmd;
5382
1ef7286e
AS		 5383 cmd = RTL_R16(tp, CPlusCmd);
5384 RTL_W16(tp, CPlusCmd, cmd);
7f796d83
FR		 5385 return cmd;
5386}
5387
1d0254dd 5388static void rtl_set_rx_max_size(struct rtl8169_private *tp)
7f796d83
FR		 5389{
5390 /* Low hurts. Let's disable the filtering. */
1d0254dd 5391 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
7f796d83
FR		 5392}
5393
1ef7286e 5394static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
6dccd16b 5395{
3744100e 5396 static const struct rtl_cfg2_info {
6dccd16b
FR		 5397 u32 mac_version;
5398 u32 clk;
5399 u32 val;
5400 } cfg2_info [] = {
5401 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5402 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5403 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5404 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 5405 };
5406 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 5407 unsigned int i;
5408 u32 clk;
5409
1ef7286e 5410 clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
cadf1855 5411 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b 5412 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1ef7286e 5413 RTL_W32(tp, 0x7c, p->val);
6dccd16b
FR		 5414 break;
5415 }
5416 }
5417}
5418
e6b763ea
FR		 5419static void rtl_set_rx_mode(struct net_device *dev)
5420{
5421 struct rtl8169_private *tp = netdev_priv(dev);
e6b763ea
FR		 5422 u32 mc_filter[2]; /* Multicast hash filter */
5423 int rx_mode;
5424 u32 tmp = 0;
5425
5426 if (dev->flags & IFF_PROMISC) {
5427 /* Unconditionally log net taps. */
5428 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5429 rx_mode =
5430 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5431 AcceptAllPhys;
5432 mc_filter[1] = mc_filter[0] = 0xffffffff;
5433 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5434 (dev->flags & IFF_ALLMULTI)) {
5435 /* Too many to filter perfectly -- accept all multicasts. */
5436 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5437 mc_filter[1] = mc_filter[0] = 0xffffffff;
5438 } else {
5439 struct netdev_hw_addr *ha;
5440
5441 rx_mode = AcceptBroadcast | AcceptMyPhys;
5442 mc_filter[1] = mc_filter[0] = 0;
5443 netdev_for_each_mc_addr(ha, dev) {
5444 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5445 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5446 rx_mode |= AcceptMulticast;
5447 }
5448 }
5449
5450 if (dev->features & NETIF_F_RXALL)
5451 rx_mode |= (AcceptErr | AcceptRunt);
5452
1ef7286e 5453 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
e6b763ea
FR		 5454
5455 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5456 u32 data = mc_filter[0];
5457
5458 mc_filter[0] = swab32(mc_filter[1]);
5459 mc_filter[1] = swab32(data);
5460 }
5461
0481776b
NW		 5462 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5463 mc_filter[1] = mc_filter[0] = 0xffffffff;
5464
1ef7286e
AS		 5465 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
5466 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
e6b763ea 5467
1ef7286e 5468 RTL_W32(tp, RxConfig, tmp);
e6b763ea
FR		 5469}
5470
07ce4064
FR		 5471static void rtl_hw_start_8169(struct net_device *dev)
5472{
5473 struct rtl8169_private *tp = netdev_priv(dev);
07ce4064 5474 struct pci_dev *pdev = tp->pci_dev;
07ce4064 5475
9cb427b6 5476 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1ef7286e 5477 RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) | PCIMulRW);
9cb427b6
FR		 5478 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5479 }
5480
1ef7286e 5481 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 5482 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5483 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5484 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5485 tp->mac_version == RTL_GIGA_MAC_VER_04)
1ef7286e 5486 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
9cb427b6 5487
e542a226
HW		 5488 rtl_init_rxcfg(tp);
5489
1ef7286e 5490 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
1da177e4 5491
1d0254dd 5492 rtl_set_rx_max_size(tp);
1da177e4 5493
cecb5fd7
FR		 5494 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5495 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5496 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5497 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 5498 rtl_set_rx_tx_config_registers(tp);
1da177e4 5499
1ef7286e 5500 tp->cp_cmd |= rtl_rw_cpluscmd(tp) | PCIMulRW;
1da177e4 5501
cecb5fd7
FR		 5502 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5503 tp->mac_version == RTL_GIGA_MAC_VER_03) {
05b9687b 5504 dprintk("Set MAC Reg C+CR Offset 0xe0. "
1da177e4 5505 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 5506 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 5507 }
5508
1ef7286e 5509 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
bcf0bf90 5510
1ef7286e 5511 rtl8169_set_magic_reg(tp, tp->mac_version);
6dccd16b 5512
1da177e4
LT		 5513 /*
5514 * Undocumented corner. Supposedly:
5515 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5516 */
1ef7286e 5517 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4 5518
1ef7286e 5519 rtl_set_rx_tx_desc_registers(tp);
9cb427b6 5520
cecb5fd7
FR		 5521 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5522 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5523 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5524 tp->mac_version != RTL_GIGA_MAC_VER_04) {
1ef7286e 5525 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
c946b304
FR		 5526 rtl_set_rx_tx_config_registers(tp);
5527 }
5528
1ef7286e 5529 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 5530
5531 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1ef7286e 5532 RTL_R8(tp, IntrMask);
1da177e4 5533
1ef7286e 5534 RTL_W32(tp, RxMissed, 0);
1da177e4 5535
07ce4064 5536 rtl_set_rx_mode(dev);
1da177e4
LT		 5537
5538 /* no early-rx interrupts */
1ef7286e 5539 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
07ce4064 5540}
1da177e4 5541
beb1fe18
HW		 5542static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5543{
5544 if (tp->csi_ops.write)
52989f0e 5545 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 5546}
5547
5548static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5549{
52989f0e 5550 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 5551}
5552
5553static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 5554{
5555 u32 csi;
5556
beb1fe18
HW		 5557 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5558 rtl_csi_write(tp, 0x070c, csi | bits);
5559}
5560
5561static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5562{
5563 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 5564}
5565
beb1fe18 5566static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 5567{
beb1fe18 5568 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 5569}
5570
ffc46952
FR		 5571DECLARE_RTL_COND(rtl_csiar_cond)
5572{
1ef7286e 5573 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
ffc46952
FR		 5574}
5575
52989f0e 5576static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 5577{
1ef7286e
AS		 5578 RTL_W32(tp, CSIDR, value);
5579 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
beb1fe18
HW		 5580 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5581
ffc46952 5582 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 5583}
5584
52989f0e 5585static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 5586{
1ef7286e 5587 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) |
beb1fe18
HW		 5588 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5589
ffc46952 5590 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 5591 RTL_R32(tp, CSIDR) : ~0;
beb1fe18
HW		 5592}
5593
52989f0e 5594static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 5595{
1ef7286e
AS		 5596 RTL_W32(tp, CSIDR, value);
5597 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
7e18dca1
HW		 5598 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5599 CSIAR_FUNC_NIC);
5600
ffc46952 5601 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 5602}
5603
52989f0e 5604static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 5605{
1ef7286e 5606 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
7e18dca1
HW		 5607 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5608
ffc46952 5609 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 5610 RTL_R32(tp, CSIDR) : ~0;
7e18dca1
HW		 5611}
5612
45dd95c4 5613static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5614{
1ef7286e
AS		 5615 RTL_W32(tp, CSIDR, value);
5616 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
45dd95c4 5617 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5618 CSIAR_FUNC_NIC2);
5619
5620 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5621}
5622
5623static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5624{
1ef7286e 5625 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
45dd95c4 5626 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5627
5628 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 5629 RTL_R32(tp, CSIDR) : ~0;
45dd95c4 5630}
5631
baf63293 5632static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 5633{
5634 struct csi_ops *ops = &tp->csi_ops;
5635
5636 switch (tp->mac_version) {
5637 case RTL_GIGA_MAC_VER_01:
5638 case RTL_GIGA_MAC_VER_02:
5639 case RTL_GIGA_MAC_VER_03:
5640 case RTL_GIGA_MAC_VER_04:
5641 case RTL_GIGA_MAC_VER_05:
5642 case RTL_GIGA_MAC_VER_06:
5643 case RTL_GIGA_MAC_VER_10:
5644 case RTL_GIGA_MAC_VER_11:
5645 case RTL_GIGA_MAC_VER_12:
5646 case RTL_GIGA_MAC_VER_13:
5647 case RTL_GIGA_MAC_VER_14:
5648 case RTL_GIGA_MAC_VER_15:
5649 case RTL_GIGA_MAC_VER_16:
5650 case RTL_GIGA_MAC_VER_17:
5651 ops->write = NULL;
5652 ops->read = NULL;
5653 break;
5654
7e18dca1 5655 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 5656 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 5657 ops->write = r8402_csi_write;
5658 ops->read = r8402_csi_read;
5659 break;
5660
45dd95c4 5661 case RTL_GIGA_MAC_VER_44:
5662 ops->write = r8411_csi_write;
5663 ops->read = r8411_csi_read;
5664 break;
5665
beb1fe18
HW		 5666 default:
5667 ops->write = r8169_csi_write;
5668 ops->read = r8169_csi_read;
5669 break;
5670 }
dacf8154
FR		 5671}
5672
5673struct ephy_info {
5674 unsigned int offset;
5675 u16 mask;
5676 u16 bits;
5677};
5678
fdf6fc06
FR		 5679static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5680 int len)
dacf8154
FR		 5681{
5682 u16 w;
5683
5684 while (len-- > 0) {
fdf6fc06
FR		 5685 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5686 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 5687 e++;
5688 }
5689}
5690
73c86ee3 5691static void rtl_disable_clock_request(struct rtl8169_private *tp)
b726e493 5692{
73c86ee3 5693 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 5694 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 5695}
5696
73c86ee3 5697static void rtl_enable_clock_request(struct rtl8169_private *tp)
e6de30d6 5698{
73c86ee3 5699 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 5700 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 5701}
5702
b51ecea8 5703static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5704{
b51ecea8 5705 u8 data;
5706
1ef7286e 5707 data = RTL_R8(tp, Config3);
b51ecea8 5708
5709 if (enable)
5710 data |= Rdy_to_L23;
5711 else
5712 data &= ~Rdy_to_L23;
5713
1ef7286e 5714 RTL_W8(tp, Config3, data);
b51ecea8 5715}
5716
b726e493
FR		 5717#define R8168_CPCMD_QUIRK_MASK (\
5718 EnableBist | \
5719 Mac_dbgo_oe | \
5720 Force_half_dup | \
5721 Force_rxflow_en | \
5722 Force_txflow_en | \
5723 Cxpl_dbg_sel | \
5724 ASF | \
5725 PktCntrDisable | \
5726 Mac_dbgo_sel)
5727
beb1fe18 5728static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 5729{
1ef7286e 5730 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 5731
1ef7286e 5732 RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
b726e493 5733
faf1e785 5734 if (tp->dev->mtu <= ETH_DATA_LEN) {
8d98aa39 5735 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
faf1e785 5736 PCI_EXP_DEVCTL_NOSNOOP_EN);
5737 }
219a1e9d
FR		 5738}
5739
beb1fe18 5740static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 5741{
beb1fe18 5742 rtl_hw_start_8168bb(tp);
b726e493 5743
1ef7286e 5744 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
b726e493 5745
1ef7286e 5746 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
219a1e9d
FR		 5747}
5748
beb1fe18 5749static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 5750{
1ef7286e 5751 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
b726e493 5752
1ef7286e 5753 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 5754
faf1e785 5755 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5756 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
b726e493 5757
73c86ee3 5758 rtl_disable_clock_request(tp);
b726e493 5759
1ef7286e 5760 RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 5761}
5762
beb1fe18 5763static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 5764{
350f7596 5765 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 5766 { 0x01, 0, 0x0001 },
5767 { 0x02, 0x0800, 0x1000 },
5768 { 0x03, 0, 0x0042 },
5769 { 0x06, 0x0080, 0x0000 },
5770 { 0x07, 0, 0x2000 }
5771 };
5772
beb1fe18 5773 rtl_csi_access_enable_2(tp);
b726e493 5774
fdf6fc06 5775 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 5776
beb1fe18 5777 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5778}
5779
beb1fe18 5780static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 5781{
beb1fe18 5782 rtl_csi_access_enable_2(tp);
ef3386f0 5783
1ef7286e 5784 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
ef3386f0 5785
faf1e785 5786 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5787 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
ef3386f0 5788
1ef7286e 5789 RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
ef3386f0
FR		 5790}
5791
beb1fe18 5792static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 5793{
beb1fe18 5794 rtl_csi_access_enable_2(tp);
7f3e3d3a 5795
1ef7286e 5796 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
7f3e3d3a
FR		 5797
5798 /* Magic. */
1ef7286e 5799 RTL_W8(tp, DBG_REG, 0x20);
7f3e3d3a 5800
1ef7286e 5801 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
7f3e3d3a 5802
faf1e785 5803 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5804 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7f3e3d3a 5805
1ef7286e 5806 RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
7f3e3d3a
FR		 5807}
5808
beb1fe18 5809static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 5810{
350f7596 5811 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 5812 { 0x02, 0x0800, 0x1000 },
5813 { 0x03, 0, 0x0002 },
5814 { 0x06, 0x0080, 0x0000 }
5815 };
5816
beb1fe18 5817 rtl_csi_access_enable_2(tp);
b726e493 5818
1ef7286e 5819 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
b726e493 5820
fdf6fc06 5821 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 5822
beb1fe18 5823 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5824}
5825
beb1fe18 5826static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 5827{
350f7596 5828 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 5829 { 0x01, 0, 0x0001 },
5830 { 0x03, 0x0400, 0x0220 }
5831 };
5832
beb1fe18 5833 rtl_csi_access_enable_2(tp);
b726e493 5834
fdf6fc06 5835 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 5836
beb1fe18 5837 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5838}
5839
beb1fe18 5840static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 5841{
beb1fe18 5842 rtl_hw_start_8168c_2(tp);
197ff761
FR		 5843}
5844
beb1fe18 5845static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 5846{
beb1fe18 5847 rtl_csi_access_enable_2(tp);
6fb07058 5848
beb1fe18 5849 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 5850}
5851
beb1fe18 5852static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 5853{
beb1fe18 5854 rtl_csi_access_enable_2(tp);
5b538df9 5855
73c86ee3 5856 rtl_disable_clock_request(tp);
5b538df9 5857
1ef7286e 5858 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5b538df9 5859
faf1e785 5860 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5861 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5b538df9 5862
1ef7286e 5863 RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5b538df9
FR		 5864}
5865
beb1fe18 5866static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 5867{
beb1fe18 5868 rtl_csi_access_enable_1(tp);
4804b3b3 5869
faf1e785 5870 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5871 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4804b3b3 5872
1ef7286e 5873 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4804b3b3 5874
73c86ee3 5875 rtl_disable_clock_request(tp);
4804b3b3 5876}
5877
beb1fe18 5878static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 5879{
5880 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 5881 { 0x0b, 0x0000, 0x0048 },
5882 { 0x19, 0x0020, 0x0050 },
5883 { 0x0c, 0x0100, 0x0020 }
e6de30d6 5884 };
e6de30d6 5885
beb1fe18 5886 rtl_csi_access_enable_1(tp);
e6de30d6 5887
8d98aa39 5888 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
e6de30d6 5889
1ef7286e 5890 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
e6de30d6 5891
1016a4a1 5892 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
e6de30d6 5893
73c86ee3 5894 rtl_enable_clock_request(tp);
e6de30d6 5895}
5896
beb1fe18 5897static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 5898{
70090424 5899 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5900 { 0x00, 0x0200, 0x0100 },
5901 { 0x00, 0x0000, 0x0004 },
5902 { 0x06, 0x0002, 0x0001 },
5903 { 0x06, 0x0000, 0x0030 },
5904 { 0x07, 0x0000, 0x2000 },
5905 { 0x00, 0x0000, 0x0020 },
5906 { 0x03, 0x5800, 0x2000 },
5907 { 0x03, 0x0000, 0x0001 },
5908 { 0x01, 0x0800, 0x1000 },
5909 { 0x07, 0x0000, 0x4000 },
5910 { 0x1e, 0x0000, 0x2000 },
5911 { 0x19, 0xffff, 0xfe6c },
5912 { 0x0a, 0x0000, 0x0040 }
5913 };
5914
beb1fe18 5915 rtl_csi_access_enable_2(tp);
01dc7fec 5916
fdf6fc06 5917 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5918
faf1e785 5919 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5920 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
01dc7fec 5921
1ef7286e 5922 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
01dc7fec 5923
73c86ee3 5924 rtl_disable_clock_request(tp);
01dc7fec 5925
5926 /* Reset tx FIFO pointer */
1ef7286e
AS		 5927 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5928 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
01dc7fec 5929
1ef7286e 5930 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
01dc7fec 5931}
5932
beb1fe18 5933static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424
HW		 5934{
5935 static const struct ephy_info e_info_8168e_2[] = {
5936 { 0x09, 0x0000, 0x0080 },
5937 { 0x19, 0x0000, 0x0224 }
5938 };
5939
beb1fe18 5940 rtl_csi_access_enable_1(tp);
70090424 5941
fdf6fc06 5942 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5943
faf1e785 5944 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5945 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
70090424 5946
fdf6fc06
FR		 5947 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5948 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5949 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5950 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5951 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5952 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 5953 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5954 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5955
1ef7286e 5956 RTL_W8(tp, MaxTxPacketSize, EarlySize);
70090424 5957
73c86ee3 5958 rtl_disable_clock_request(tp);
4521e1a9 5959
1ef7286e
AS		 5960 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5961 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
70090424
HW		 5962
5963 /* Adjust EEE LED frequency */
1ef7286e 5964 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
70090424 5965
1ef7286e
AS		 5966 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5967 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5968 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
70090424
HW		 5969}
5970
5f886e08 5971static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5972{
5f886e08 5973 rtl_csi_access_enable_2(tp);
c2218925 5974
8d98aa39 5975 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c2218925 5976
fdf6fc06
FR		 5977 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5978 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5979 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5980 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 5981 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5982 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5983 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5984 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5985 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5986 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925 5987
1ef7286e 5988 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c2218925 5989
73c86ee3 5990 rtl_disable_clock_request(tp);
4521e1a9 5991
1ef7286e
AS		 5992 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5993 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5994 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5995 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5996 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
c2218925
HW		 5997}
5998
5f886e08
HW		 5999static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
6000{
5f886e08
HW		 6001 static const struct ephy_info e_info_8168f_1[] = {
6002 { 0x06, 0x00c0, 0x0020 },
6003 { 0x08, 0x0001, 0x0002 },
6004 { 0x09, 0x0000, 0x0080 },
6005 { 0x19, 0x0000, 0x0224 }
6006 };
6007
6008 rtl_hw_start_8168f(tp);
6009
fdf6fc06 6010 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 6011
706123d0 6012 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 6013
6014 /* Adjust EEE LED frequency */
1ef7286e 6015 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5f886e08
HW		 6016}
6017
b3d7b2f2
HW		 6018static void rtl_hw_start_8411(struct rtl8169_private *tp)
6019{
b3d7b2f2
HW		 6020 static const struct ephy_info e_info_8168f_1[] = {
6021 { 0x06, 0x00c0, 0x0020 },
6022 { 0x0f, 0xffff, 0x5200 },
6023 { 0x1e, 0x0000, 0x4000 },
6024 { 0x19, 0x0000, 0x0224 }
6025 };
6026
6027 rtl_hw_start_8168f(tp);
b51ecea8 6028 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 6029
fdf6fc06 6030 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 6031
706123d0 6032 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 6033}
6034
5fbea337 6035static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b 6036{
1ef7286e 6037 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
beb330a4 6038
c558386b
HW		 6039 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6040 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6041 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6042 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6043
6044 rtl_csi_access_enable_1(tp);
6045
8d98aa39 6046 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c558386b 6047
706123d0
CHL		 6048 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6049 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 6050 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 6051
1ef7286e
AS		 6052 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
6053 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c558386b
HW		 6054
6055 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6056 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6057
6058 /* Adjust EEE LED frequency */
1ef7286e 6059 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
c558386b 6060
706123d0
CHL		 6061 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6062 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 6063
6064 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 6065}
6066
5fbea337
CHL		 6067static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6068{
5fbea337
CHL		 6069 static const struct ephy_info e_info_8168g_1[] = {
6070 { 0x00, 0x0000, 0x0008 },
6071 { 0x0c, 0x37d0, 0x0820 },
6072 { 0x1e, 0x0000, 0x0001 },
6073 { 0x19, 0x8000, 0x0000 }
6074 };
6075
6076 rtl_hw_start_8168g(tp);
6077
6078 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 6079 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6080 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5fbea337
CHL		 6081 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6082}
6083
57538c4a 6084static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6085{
57538c4a 6086 static const struct ephy_info e_info_8168g_2[] = {
6087 { 0x00, 0x0000, 0x0008 },
6088 { 0x0c, 0x3df0, 0x0200 },
6089 { 0x19, 0xffff, 0xfc00 },
6090 { 0x1e, 0xffff, 0x20eb }
6091 };
6092
5fbea337 6093 rtl_hw_start_8168g(tp);
57538c4a 6094
6095 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 6096 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6097 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
57538c4a 6098 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6099}
6100
45dd95c4 6101static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6102{
45dd95c4 6103 static const struct ephy_info e_info_8411_2[] = {
6104 { 0x00, 0x0000, 0x0008 },
6105 { 0x0c, 0x3df0, 0x0200 },
6106 { 0x0f, 0xffff, 0x5200 },
6107 { 0x19, 0x0020, 0x0000 },
6108 { 0x1e, 0x0000, 0x2000 }
6109 };
6110
5fbea337 6111 rtl_hw_start_8168g(tp);
45dd95c4 6112
6113 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 6114 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6115 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
45dd95c4 6116 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6117}
6118
6e1d0b89
CHL		 6119static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6120{
72521ea0 6121 int rg_saw_cnt;
6e1d0b89
CHL		 6122 u32 data;
6123 static const struct ephy_info e_info_8168h_1[] = {
6124 { 0x1e, 0x0800, 0x0001 },
6125 { 0x1d, 0x0000, 0x0800 },
6126 { 0x05, 0xffff, 0x2089 },
6127 { 0x06, 0xffff, 0x5881 },
6128 { 0x04, 0xffff, 0x154a },
6129 { 0x01, 0xffff, 0x068b }
6130 };
6131
6132 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 6133 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6134 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6e1d0b89
CHL		 6135 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6136
1ef7286e 6137 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6e1d0b89
CHL		 6138
6139 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6140 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6141 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6142 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6143
6144 rtl_csi_access_enable_1(tp);
6145
8d98aa39 6146 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6e1d0b89 6147
706123d0
CHL		 6148 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6149 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 6150
706123d0 6151 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 6152
706123d0 6153 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 6154
6155 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6156
1ef7286e
AS		 6157 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
6158 RTL_W8(tp, MaxTxPacketSize, EarlySize);
6e1d0b89
CHL		 6159
6160 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6161 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6162
6163 /* Adjust EEE LED frequency */
1ef7286e 6164 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6e1d0b89 6165
1ef7286e
AS		 6166 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
6167 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89 6168
1ef7286e 6169 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6e1d0b89 6170
706123d0 6171 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 6172
6173 rtl_pcie_state_l2l3_enable(tp, false);
6174
6175 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 6176 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 6177 rtl_writephy(tp, 0x1f, 0x0000);
6178 if (rg_saw_cnt > 0) {
6179 u16 sw_cnt_1ms_ini;
6180
6181 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6182 sw_cnt_1ms_ini &= 0x0fff;
6183 data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec0 6184 data &= ~0x0fff;
6e1d0b89
CHL		 6185 data |= sw_cnt_1ms_ini;
6186 r8168_mac_ocp_write(tp, 0xd412, data);
6187 }
6188
6189 data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec0
CHL		 6190 data &= ~0xf0;
6191 data |= 0x70;
6e1d0b89
CHL		 6192 r8168_mac_ocp_write(tp, 0xe056, data);
6193
6194 data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec0
CHL		 6195 data &= ~0x6000;
6196 data |= 0x8008;
6e1d0b89
CHL		 6197 r8168_mac_ocp_write(tp, 0xe052, data);
6198
6199 data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec0 6200 data &= ~0x01ff;
6e1d0b89
CHL		 6201 data |= 0x017f;
6202 r8168_mac_ocp_write(tp, 0xe0d6, data);
6203
6204 data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec0 6205 data &= ~0x0fff;
6e1d0b89
CHL		 6206 data |= 0x047f;
6207 r8168_mac_ocp_write(tp, 0xd420, data);
6208
6209 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6210 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6211 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6212 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6213}
6214
935e2218
CHL		 6215static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6216{
003609da
CHL		 6217 rtl8168ep_stop_cmac(tp);
6218
1ef7286e 6219 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
935e2218
CHL		 6220
6221 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6222 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6223 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6224 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6225
6226 rtl_csi_access_enable_1(tp);
6227
8d98aa39 6228 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
935e2218
CHL		 6229
6230 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6231 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6232
6233 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6234
6235 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6236
1ef7286e
AS		 6237 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
6238 RTL_W8(tp, MaxTxPacketSize, EarlySize);
935e2218
CHL		 6239
6240 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6241 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6242
6243 /* Adjust EEE LED frequency */
1ef7286e 6244 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
935e2218
CHL		 6245
6246 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6247
1ef7286e 6248 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
935e2218
CHL		 6249
6250 rtl_pcie_state_l2l3_enable(tp, false);
6251}
6252
6253static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6254{
935e2218
CHL		 6255 static const struct ephy_info e_info_8168ep_1[] = {
6256 { 0x00, 0xffff, 0x10ab },
6257 { 0x06, 0xffff, 0xf030 },
6258 { 0x08, 0xffff, 0x2006 },
6259 { 0x0d, 0xffff, 0x1666 },
6260 { 0x0c, 0x3ff0, 0x0000 }
6261 };
6262
6263 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 6264 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6265 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
935e2218
CHL		 6266 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6267
6268 rtl_hw_start_8168ep(tp);
6269}
6270
6271static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6272{
935e2218
CHL		 6273 static const struct ephy_info e_info_8168ep_2[] = {
6274 { 0x00, 0xffff, 0x10a3 },
6275 { 0x19, 0xffff, 0xfc00 },
6276 { 0x1e, 0xffff, 0x20ea }
6277 };
6278
6279 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 6280 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6281 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
935e2218
CHL		 6282 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6283
6284 rtl_hw_start_8168ep(tp);
6285
1ef7286e
AS		 6286 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
6287 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 6288}
6289
6290static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6291{
935e2218
CHL		 6292 u32 data;
6293 static const struct ephy_info e_info_8168ep_3[] = {
6294 { 0x00, 0xffff, 0x10a3 },
6295 { 0x19, 0xffff, 0x7c00 },
6296 { 0x1e, 0xffff, 0x20eb },
6297 { 0x0d, 0xffff, 0x1666 }
6298 };
6299
6300 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 6301 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6302 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
935e2218
CHL		 6303 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6304
6305 rtl_hw_start_8168ep(tp);
6306
1ef7286e
AS		 6307 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
6308 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 6309
6310 data = r8168_mac_ocp_read(tp, 0xd3e2);
6311 data &= 0xf000;
6312 data |= 0x0271;
6313 r8168_mac_ocp_write(tp, 0xd3e2, data);
6314
6315 data = r8168_mac_ocp_read(tp, 0xd3e4);
6316 data &= 0xff00;
6317 r8168_mac_ocp_write(tp, 0xd3e4, data);
6318
6319 data = r8168_mac_ocp_read(tp, 0xe860);
6320 data |= 0x0080;
6321 r8168_mac_ocp_write(tp, 0xe860, data);
6322}
6323
07ce4064
FR		 6324static void rtl_hw_start_8168(struct net_device *dev)
6325{
2dd99530 6326 struct rtl8169_private *tp = netdev_priv(dev);
2dd99530 6327
1ef7286e 6328 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
2dd99530 6329
1ef7286e 6330 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
2dd99530 6331
1d0254dd 6332 rtl_set_rx_max_size(tp);
2dd99530 6333
1ef7286e 6334 tp->cp_cmd |= RTL_R16(tp, CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530 6335
1ef7286e 6336 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2dd99530 6337
1ef7286e 6338 RTL_W16(tp, IntrMitigate, 0x5151);
2dd99530 6339
0e485150 6340 /* Work around for RxFIFO overflow. */
811fd301 6341 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 6342 tp->event_slow |= RxFIFOOver | PCSTimeout;
6343 tp->event_slow &= ~RxOverflow;
0e485150
FR		 6344 }
6345
1ef7286e 6346 rtl_set_rx_tx_desc_registers(tp);
2dd99530 6347
1a964649 6348 rtl_set_rx_tx_config_registers(tp);
2dd99530 6349
1ef7286e 6350 RTL_R8(tp, IntrMask);
2dd99530 6351
219a1e9d
FR		 6352 switch (tp->mac_version) {
6353 case RTL_GIGA_MAC_VER_11:
beb1fe18 6354 rtl_hw_start_8168bb(tp);
4804b3b3 6355 break;
219a1e9d
FR		 6356
6357 case RTL_GIGA_MAC_VER_12:
6358 case RTL_GIGA_MAC_VER_17:
beb1fe18 6359 rtl_hw_start_8168bef(tp);
4804b3b3 6360 break;
219a1e9d
FR		 6361
6362 case RTL_GIGA_MAC_VER_18:
beb1fe18 6363 rtl_hw_start_8168cp_1(tp);
4804b3b3 6364 break;
219a1e9d
FR		 6365
6366 case RTL_GIGA_MAC_VER_19:
beb1fe18 6367 rtl_hw_start_8168c_1(tp);
4804b3b3 6368 break;
219a1e9d
FR		 6369
6370 case RTL_GIGA_MAC_VER_20:
beb1fe18 6371 rtl_hw_start_8168c_2(tp);
4804b3b3 6372 break;
219a1e9d 6373
197ff761 6374 case RTL_GIGA_MAC_VER_21:
beb1fe18 6375 rtl_hw_start_8168c_3(tp);
4804b3b3 6376 break;
197ff761 6377
6fb07058 6378 case RTL_GIGA_MAC_VER_22:
beb1fe18 6379 rtl_hw_start_8168c_4(tp);
4804b3b3 6380 break;
6fb07058 6381
ef3386f0 6382 case RTL_GIGA_MAC_VER_23:
beb1fe18 6383 rtl_hw_start_8168cp_2(tp);
4804b3b3 6384 break;
ef3386f0 6385
7f3e3d3a 6386 case RTL_GIGA_MAC_VER_24:
beb1fe18 6387 rtl_hw_start_8168cp_3(tp);
4804b3b3 6388 break;
7f3e3d3a 6389
5b538df9 6390 case RTL_GIGA_MAC_VER_25:
daf9df6d 6391 case RTL_GIGA_MAC_VER_26:
6392 case RTL_GIGA_MAC_VER_27:
beb1fe18 6393 rtl_hw_start_8168d(tp);
4804b3b3 6394 break;
5b538df9 6395
e6de30d6 6396 case RTL_GIGA_MAC_VER_28:
beb1fe18 6397 rtl_hw_start_8168d_4(tp);
4804b3b3 6398 break;
cecb5fd7 6399
4804b3b3 6400 case RTL_GIGA_MAC_VER_31:
beb1fe18 6401 rtl_hw_start_8168dp(tp);
4804b3b3 6402 break;
6403
01dc7fec 6404 case RTL_GIGA_MAC_VER_32:
6405 case RTL_GIGA_MAC_VER_33:
beb1fe18 6406 rtl_hw_start_8168e_1(tp);
70090424
HW		 6407 break;
6408 case RTL_GIGA_MAC_VER_34:
beb1fe18 6409 rtl_hw_start_8168e_2(tp);
01dc7fec 6410 break;
e6de30d6 6411
c2218925
HW		 6412 case RTL_GIGA_MAC_VER_35:
6413 case RTL_GIGA_MAC_VER_36:
beb1fe18 6414 rtl_hw_start_8168f_1(tp);
c2218925
HW		 6415 break;
6416
b3d7b2f2
HW		 6417 case RTL_GIGA_MAC_VER_38:
6418 rtl_hw_start_8411(tp);
6419 break;
6420
c558386b
HW		 6421 case RTL_GIGA_MAC_VER_40:
6422 case RTL_GIGA_MAC_VER_41:
6423 rtl_hw_start_8168g_1(tp);
6424 break;
57538c4a 6425 case RTL_GIGA_MAC_VER_42:
6426 rtl_hw_start_8168g_2(tp);
6427 break;
c558386b 6428
45dd95c4 6429 case RTL_GIGA_MAC_VER_44:
6430 rtl_hw_start_8411_2(tp);
6431 break;
6432
6e1d0b89
CHL		 6433 case RTL_GIGA_MAC_VER_45:
6434 case RTL_GIGA_MAC_VER_46:
6435 rtl_hw_start_8168h_1(tp);
6436 break;
6437
935e2218
CHL		 6438 case RTL_GIGA_MAC_VER_49:
6439 rtl_hw_start_8168ep_1(tp);
6440 break;
6441
6442 case RTL_GIGA_MAC_VER_50:
6443 rtl_hw_start_8168ep_2(tp);
6444 break;
6445
6446 case RTL_GIGA_MAC_VER_51:
6447 rtl_hw_start_8168ep_3(tp);
6448 break;
6449
219a1e9d
FR		 6450 default:
6451 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6452 dev->name, tp->mac_version);
4804b3b3 6453 break;
219a1e9d 6454 }
2dd99530 6455
1ef7286e 6456 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1a964649 6457
1ef7286e 6458 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
0e485150 6459
1a964649 6460 rtl_set_rx_mode(dev);
b8363901 6461
1ef7286e 6462 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
07ce4064 6463}
1da177e4 6464
2857ffb7
FR		 6465#define R810X_CPCMD_QUIRK_MASK (\
6466 EnableBist | \
6467 Mac_dbgo_oe | \
6468 Force_half_dup | \
5edcc537 6469 Force_rxflow_en | \
2857ffb7
FR		 6470 Force_txflow_en | \
6471 Cxpl_dbg_sel | \
6472 ASF | \
6473 PktCntrDisable | \
d24e9aaf 6474 Mac_dbgo_sel)
2857ffb7 6475
beb1fe18 6476static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 6477{
350f7596 6478 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 6479 { 0x01, 0, 0x6e65 },
6480 { 0x02, 0, 0x091f },
6481 { 0x03, 0, 0xc2f9 },
6482 { 0x06, 0, 0xafb5 },
6483 { 0x07, 0, 0x0e00 },
6484 { 0x19, 0, 0xec80 },
6485 { 0x01, 0, 0x2e65 },
6486 { 0x01, 0, 0x6e65 }
6487 };
6488 u8 cfg1;
6489
beb1fe18 6490 rtl_csi_access_enable_2(tp);
2857ffb7 6491
1ef7286e 6492 RTL_W8(tp, DBG_REG, FIX_NAK_1);
2857ffb7 6493
8d98aa39 6494 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 6495
1ef7286e 6496 RTL_W8(tp, Config1,
2857ffb7 6497 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
1ef7286e 6498 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7 6499
1ef7286e 6500 cfg1 = RTL_R8(tp, Config1);
2857ffb7 6501 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
1ef7286e 6502 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
2857ffb7 6503
fdf6fc06 6504 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 6505}
6506
beb1fe18 6507static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 6508{
beb1fe18 6509 rtl_csi_access_enable_2(tp);
2857ffb7 6510
8d98aa39 6511 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 6512
1ef7286e
AS		 6513 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
6514 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7
FR		 6515}
6516
beb1fe18 6517static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 6518{
beb1fe18 6519 rtl_hw_start_8102e_2(tp);
2857ffb7 6520
fdf6fc06 6521 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 6522}
6523
beb1fe18 6524static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443
HW		 6525{
6526 static const struct ephy_info e_info_8105e_1[] = {
6527 { 0x07, 0, 0x4000 },
6528 { 0x19, 0, 0x0200 },
6529 { 0x19, 0, 0x0020 },
6530 { 0x1e, 0, 0x2000 },
6531 { 0x03, 0, 0x0001 },
6532 { 0x19, 0, 0x0100 },
6533 { 0x19, 0, 0x0004 },
6534 { 0x0a, 0, 0x0020 }
6535 };
6536
cecb5fd7 6537 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 6538 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5a5e4443 6539
cecb5fd7 6540 /* Disable Early Tally Counter */
1ef7286e 6541 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5a5e4443 6542
1ef7286e
AS		 6543 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
6544 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5a5e4443 6545
fdf6fc06 6546 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 6547
6548 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 6549}
6550
beb1fe18 6551static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 6552{
beb1fe18 6553 rtl_hw_start_8105e_1(tp);
fdf6fc06 6554 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 6555}
6556
7e18dca1
HW		 6557static void rtl_hw_start_8402(struct rtl8169_private *tp)
6558{
7e18dca1
HW		 6559 static const struct ephy_info e_info_8402[] = {
6560 { 0x19, 0xffff, 0xff64 },
6561 { 0x1e, 0, 0x4000 }
6562 };
6563
6564 rtl_csi_access_enable_2(tp);
6565
6566 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 6567 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
7e18dca1 6568
1ef7286e
AS		 6569 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6570 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7e18dca1 6571
fdf6fc06 6572 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1 6573
8d98aa39 6574 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7e18dca1 6575
fdf6fc06
FR		 6576 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6577 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 6578 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6579 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 6580 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6581 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 6582 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 6583
6584 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 6585}
6586
5598bfe5
HW		 6587static void rtl_hw_start_8106(struct rtl8169_private *tp)
6588{
5598bfe5 6589 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 6590 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5598bfe5 6591
1ef7286e
AS		 6592 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6593 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
6594 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
b51ecea8 6595
6596 rtl_pcie_state_l2l3_enable(tp, false);
5598bfe5
HW		 6597}
6598
07ce4064
FR		 6599static void rtl_hw_start_8101(struct net_device *dev)
6600{
cdf1a608 6601 struct rtl8169_private *tp = netdev_priv(dev);
cdf1a608
FR		 6602 struct pci_dev *pdev = tp->pci_dev;
6603
da78dbff
FR		 6604 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6605 tp->event_slow &= ~RxFIFOOver;
811fd301 6606
cecb5fd7 6607 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 6608 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 6609 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6610 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 6611
1ef7286e 6612 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
d24e9aaf 6613
1ef7286e 6614 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
1a964649 6615
1d0254dd 6616 rtl_set_rx_max_size(tp);
1a964649 6617
6618 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
1ef7286e 6619 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1a964649 6620
1ef7286e 6621 rtl_set_rx_tx_desc_registers(tp);
1a964649 6622
6623 rtl_set_rx_tx_config_registers(tp);
6624
2857ffb7
FR		 6625 switch (tp->mac_version) {
6626 case RTL_GIGA_MAC_VER_07:
beb1fe18 6627 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 6628 break;
6629
6630 case RTL_GIGA_MAC_VER_08:
beb1fe18 6631 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 6632 break;
6633
6634 case RTL_GIGA_MAC_VER_09:
beb1fe18 6635 rtl_hw_start_8102e_2(tp);
2857ffb7 6636 break;
5a5e4443
HW		 6637
6638 case RTL_GIGA_MAC_VER_29:
beb1fe18 6639 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 6640 break;
6641 case RTL_GIGA_MAC_VER_30:
beb1fe18 6642 rtl_hw_start_8105e_2(tp);
5a5e4443 6643 break;
7e18dca1
HW		 6644
6645 case RTL_GIGA_MAC_VER_37:
6646 rtl_hw_start_8402(tp);
6647 break;
5598bfe5
HW		 6648
6649 case RTL_GIGA_MAC_VER_39:
6650 rtl_hw_start_8106(tp);
6651 break;
58152cd4 6652 case RTL_GIGA_MAC_VER_43:
6653 rtl_hw_start_8168g_2(tp);
6654 break;
6e1d0b89
CHL		 6655 case RTL_GIGA_MAC_VER_47:
6656 case RTL_GIGA_MAC_VER_48:
6657 rtl_hw_start_8168h_1(tp);
6658 break;
cdf1a608
FR		 6659 }
6660
1ef7286e 6661 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
cdf1a608 6662
1ef7286e 6663 RTL_W16(tp, IntrMitigate, 0x0000);
cdf1a608 6664
1ef7286e 6665 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
cdf1a608 6666
cdf1a608
FR		 6667 rtl_set_rx_mode(dev);
6668
1ef7286e 6669 RTL_R8(tp, IntrMask);
1a964649 6670
1ef7286e 6671 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
1da177e4
LT		 6672}
6673
6674static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6675{
d58d46b5
FR		 6676 struct rtl8169_private *tp = netdev_priv(dev);
6677
d58d46b5
FR		 6678 if (new_mtu > ETH_DATA_LEN)
6679 rtl_hw_jumbo_enable(tp);
6680 else
6681 rtl_hw_jumbo_disable(tp);
6682
1da177e4 6683 dev->mtu = new_mtu;
350fb32a
MM		 6684 netdev_update_features(dev);
6685
323bb685 6686 return 0;
1da177e4
LT		 6687}
6688
6689static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6690{
95e0918d 6691 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 6692 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6693}
6694
6f0333b8
ED		 6695static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6696 void **data_buff, struct RxDesc *desc)
1da177e4 6697{
1d0254dd
HK		 6698 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
6699 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
48addcc9 6700
6f0333b8
ED		 6701 kfree(*data_buff);
6702 *data_buff = NULL;
1da177e4
LT		 6703 rtl8169_make_unusable_by_asic(desc);
6704}
6705
1d0254dd 6706static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
1da177e4
LT		 6707{
6708 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6709
a0750138
AD		 6710 /* Force memory writes to complete before releasing descriptor */
6711 dma_wmb();
6712
1d0254dd 6713 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
1da177e4
LT		 6714}
6715
1d0254dd 6716static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping)
1da177e4
LT		 6717{
6718 desc->addr = cpu_to_le64(mapping);
1d0254dd 6719 rtl8169_mark_to_asic(desc);
1da177e4
LT		 6720}
6721
6f0333b8
ED		 6722static inline void *rtl8169_align(void *data)
6723{
6724 return (void *)ALIGN((long)data, 16);
6725}
6726
0ecbe1ca
SG		 6727static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6728 struct RxDesc *desc)
1da177e4 6729{
6f0333b8 6730 void *data;
1da177e4 6731 dma_addr_t mapping;
1e1205b7 6732 struct device *d = tp_to_dev(tp);
d3b404c2 6733 int node = dev_to_node(d);
1da177e4 6734
1d0254dd 6735 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
6f0333b8
ED		 6736 if (!data)
6737 return NULL;
e9f63f30 6738
6f0333b8
ED		 6739 if (rtl8169_align(data) != data) {
6740 kfree(data);
1d0254dd 6741 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
6f0333b8
ED		 6742 if (!data)
6743 return NULL;
6744 }
3eafe507 6745
1d0254dd 6746 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
231aee63 6747 DMA_FROM_DEVICE);
d827d86b
SG		 6748 if (unlikely(dma_mapping_error(d, mapping))) {
6749 if (net_ratelimit())
6750 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 6751 goto err_out;
d827d86b 6752 }
1da177e4 6753
1d0254dd 6754 rtl8169_map_to_asic(desc, mapping);
6f0333b8 6755 return data;
3eafe507
SG		 6756
6757err_out:
6758 kfree(data);
6759 return NULL;
1da177e4
LT		 6760}
6761
6762static void rtl8169_rx_clear(struct rtl8169_private *tp)
6763{
07d3f51f 6764 unsigned int i;
1da177e4
LT		 6765
6766 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 6767 if (tp->Rx_databuff[i]) {
6768 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 6769 tp->RxDescArray + i);
6770 }
6771 }
6772}
6773
0ecbe1ca 6774static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 6775{
0ecbe1ca
SG		 6776 desc->opts1 |= cpu_to_le32(RingEnd);
6777}
5b0384f4 6778
0ecbe1ca
SG		 6779static int rtl8169_rx_fill(struct rtl8169_private *tp)
6780{
6781 unsigned int i;
1da177e4 6782
0ecbe1ca
SG		 6783 for (i = 0; i < NUM_RX_DESC; i++) {
6784 void *data;
4ae47c2d 6785
0ecbe1ca 6786 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 6787 if (!data) {
6788 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 6789 goto err_out;
6f0333b8
ED		 6790 }
6791 tp->Rx_databuff[i] = data;
1da177e4 6792 }
1da177e4 6793
0ecbe1ca
SG		 6794 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6795 return 0;
6796
6797err_out:
6798 rtl8169_rx_clear(tp);
6799 return -ENOMEM;
1da177e4
LT		 6800}
6801
b1127e64 6802static int rtl8169_init_ring(struct rtl8169_private *tp)
1da177e4 6803{
1da177e4
LT		 6804 rtl8169_init_ring_indexes(tp);
6805
b1127e64
HK		 6806 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
6807 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
1da177e4 6808
0ecbe1ca 6809 return rtl8169_rx_fill(tp);
1da177e4
LT		 6810}
6811
48addcc9 6812static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 6813 struct TxDesc *desc)
6814{
6815 unsigned int len = tx_skb->len;
6816
48addcc9
SG		 6817 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6818
1da177e4
LT		 6819 desc->opts1 = 0x00;
6820 desc->opts2 = 0x00;
6821 desc->addr = 0x00;
6822 tx_skb->len = 0;
6823}
6824
3eafe507
SG		 6825static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6826 unsigned int n)
1da177e4
LT		 6827{
6828 unsigned int i;
6829
3eafe507
SG		 6830 for (i = 0; i < n; i++) {
6831 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 6832 struct ring_info *tx_skb = tp->tx_skb + entry;
6833 unsigned int len = tx_skb->len;
6834
6835 if (len) {
6836 struct sk_buff *skb = tx_skb->skb;
6837
1e1205b7 6838 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
1da177e4
LT		 6839 tp->TxDescArray + entry);
6840 if (skb) {
7a4b813c 6841 dev_consume_skb_any(skb);
1da177e4
LT		 6842 tx_skb->skb = NULL;
6843 }
1da177e4
LT		 6844 }
6845 }
3eafe507
SG		 6846}
6847
6848static void rtl8169_tx_clear(struct rtl8169_private *tp)
6849{
6850 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 6851 tp->cur_tx = tp->dirty_tx = 0;
6852}
6853
4422bcd4 6854static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 6855{
c4028958 6856 struct net_device *dev = tp->dev;
56de414c 6857 int i;
1da177e4 6858
da78dbff
FR		 6859 napi_disable(&tp->napi);
6860 netif_stop_queue(dev);
6861 synchronize_sched();
1da177e4 6862
c7c2c39b 6863 rtl8169_hw_reset(tp);
6864
56de414c 6865 for (i = 0; i < NUM_RX_DESC; i++)
1d0254dd 6866 rtl8169_mark_to_asic(tp->RxDescArray + i);
56de414c 6867
1da177e4 6868 rtl8169_tx_clear(tp);
c7c2c39b 6869 rtl8169_init_ring_indexes(tp);
1da177e4 6870
da78dbff 6871 napi_enable(&tp->napi);
56de414c
FR		 6872 rtl_hw_start(dev);
6873 netif_wake_queue(dev);
1ef7286e 6874 rtl8169_check_link_status(dev, tp);
1da177e4
LT		 6875}
6876
6877static void rtl8169_tx_timeout(struct net_device *dev)
6878{
da78dbff
FR		 6879 struct rtl8169_private *tp = netdev_priv(dev);
6880
6881 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6882}
6883
6884static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 6885 u32 *opts)
1da177e4
LT		 6886{
6887 struct skb_shared_info *info = skb_shinfo(skb);
6888 unsigned int cur_frag, entry;
6e1d0b89 6889 struct TxDesc *uninitialized_var(txd);
1e1205b7 6890 struct device *d = tp_to_dev(tp);
1da177e4
LT		 6891
6892 entry = tp->cur_tx;
6893 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 6894 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 6895 dma_addr_t mapping;
6896 u32 status, len;
6897 void *addr;
6898
6899 entry = (entry + 1) % NUM_TX_DESC;
6900
6901 txd = tp->TxDescArray + entry;
9e903e08 6902 len = skb_frag_size(frag);
929f6189 6903 addr = skb_frag_address(frag);
48addcc9 6904 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 6905 if (unlikely(dma_mapping_error(d, mapping))) {
6906 if (net_ratelimit())
6907 netif_err(tp, drv, tp->dev,
6908 "Failed to map TX fragments DMA!\n");
3eafe507 6909 goto err_out;
d827d86b 6910 }
1da177e4 6911
cecb5fd7 6912 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 6913 status = opts[0] | len |
6914 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6915
6916 txd->opts1 = cpu_to_le32(status);
2b7b4318 6917 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 6918 txd->addr = cpu_to_le64(mapping);
6919
6920 tp->tx_skb[entry].len = len;
6921 }
6922
6923 if (cur_frag) {
6924 tp->tx_skb[entry].skb = skb;
6925 txd->opts1 |= cpu_to_le32(LastFrag);
6926 }
6927
6928 return cur_frag;
3eafe507
SG		 6929
6930err_out:
6931 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6932 return -EIO;
1da177e4
LT		 6933}
6934
b423e9ae 6935static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6936{
6937 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6938}
6939
e974604b 6940static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6941 struct net_device *dev);
6942/* r8169_csum_workaround()
6943 * The hw limites the value the transport offset. When the offset is out of the
6944 * range, calculate the checksum by sw.
6945 */
6946static void r8169_csum_workaround(struct rtl8169_private *tp,
6947 struct sk_buff *skb)
6948{
6949 if (skb_shinfo(skb)->gso_size) {
6950 netdev_features_t features = tp->dev->features;
6951 struct sk_buff *segs, *nskb;
6952
6953 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6954 segs = skb_gso_segment(skb, features);
6955 if (IS_ERR(segs) || !segs)
6956 goto drop;
6957
6958 do {
6959 nskb = segs;
6960 segs = segs->next;
6961 nskb->next = NULL;
6962 rtl8169_start_xmit(nskb, tp->dev);
6963 } while (segs);
6964
eb781397 6965 dev_consume_skb_any(skb);
e974604b 6966 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6967 if (skb_checksum_help(skb) < 0)
6968 goto drop;
6969
6970 rtl8169_start_xmit(skb, tp->dev);
6971 } else {
6972 struct net_device_stats *stats;
6973
6974drop:
6975 stats = &tp->dev->stats;
6976 stats->tx_dropped++;
eb781397 6977 dev_kfree_skb_any(skb);
e974604b 6978 }
6979}
6980
6981/* msdn_giant_send_check()
6982 * According to the document of microsoft, the TCP Pseudo Header excludes the
6983 * packet length for IPv6 TCP large packets.
6984 */
6985static int msdn_giant_send_check(struct sk_buff *skb)
6986{
6987 const struct ipv6hdr *ipv6h;
6988 struct tcphdr *th;
6989 int ret;
6990
6991 ret = skb_cow_head(skb, 0);
6992 if (ret)
6993 return ret;
6994
6995 ipv6h = ipv6_hdr(skb);
6996 th = tcp_hdr(skb);
6997
6998 th->check = 0;
6999 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7000
7001 return ret;
7002}
7003
7004static inline __be16 get_protocol(struct sk_buff *skb)
7005{
7006 __be16 protocol;
7007
7008 if (skb->protocol == htons(ETH_P_8021Q))
7009 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7010 else
7011 protocol = skb->protocol;
7012
7013 return protocol;
7014}
7015
5888d3fc 7016static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7017 struct sk_buff *skb, u32 *opts)
1da177e4 7018{
350fb32a
MM		 7019 u32 mss = skb_shinfo(skb)->gso_size;
7020
2b7b4318
FR		 7021 if (mss) {
7022 opts[0] |= TD_LSO;
5888d3fc 7023 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7024 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7025 const struct iphdr *ip = ip_hdr(skb);
7026
7027 if (ip->protocol == IPPROTO_TCP)
7028 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7029 else if (ip->protocol == IPPROTO_UDP)
7030 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7031 else
7032 WARN_ON_ONCE(1);
7033 }
7034
7035 return true;
7036}
7037
7038static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7039 struct sk_buff *skb, u32 *opts)
7040{
bdfa4ed6 7041 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 7042 u32 mss = skb_shinfo(skb)->gso_size;
7043
7044 if (mss) {
e974604b 7045 if (transport_offset > GTTCPHO_MAX) {
7046 netif_warn(tp, tx_err, tp->dev,
7047 "Invalid transport offset 0x%x for TSO\n",
7048 transport_offset);
7049 return false;
7050 }
7051
7052 switch (get_protocol(skb)) {
7053 case htons(ETH_P_IP):
7054 opts[0] |= TD1_GTSENV4;
7055 break;
7056
7057 case htons(ETH_P_IPV6):
7058 if (msdn_giant_send_check(skb))
7059 return false;
7060
7061 opts[0] |= TD1_GTSENV6;
7062 break;
7063
7064 default:
7065 WARN_ON_ONCE(1);
7066 break;
7067 }
7068
bdfa4ed6 7069 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 7070 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 7071 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 7072 u8 ip_protocol;
1da177e4 7073
b423e9ae 7074 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 7075 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
b423e9ae 7076
e974604b 7077 if (transport_offset > TCPHO_MAX) {
7078 netif_warn(tp, tx_err, tp->dev,
7079 "Invalid transport offset 0x%x\n",
7080 transport_offset);
7081 return false;
7082 }
7083
7084 switch (get_protocol(skb)) {
7085 case htons(ETH_P_IP):
7086 opts[1] |= TD1_IPv4_CS;
7087 ip_protocol = ip_hdr(skb)->protocol;
7088 break;
7089
7090 case htons(ETH_P_IPV6):
7091 opts[1] |= TD1_IPv6_CS;
7092 ip_protocol = ipv6_hdr(skb)->nexthdr;
7093 break;
7094
7095 default:
7096 ip_protocol = IPPROTO_RAW;
7097 break;
7098 }
7099
7100 if (ip_protocol == IPPROTO_TCP)
7101 opts[1] |= TD1_TCP_CS;
7102 else if (ip_protocol == IPPROTO_UDP)
7103 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 7104 else
7105 WARN_ON_ONCE(1);
e974604b 7106
7107 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 7108 } else {
7109 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 7110 return !eth_skb_pad(skb);
1da177e4 7111 }
5888d3fc 7112
b423e9ae 7113 return true;
1da177e4
LT		 7114}
7115
61357325
SH		 7116static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7117 struct net_device *dev)
1da177e4
LT		 7118{
7119 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 7120 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4 7121 struct TxDesc *txd = tp->TxDescArray + entry;
1e1205b7 7122 struct device *d = tp_to_dev(tp);
1da177e4
LT		 7123 dma_addr_t mapping;
7124 u32 status, len;
2b7b4318 7125 u32 opts[2];
3eafe507 7126 int frags;
5b0384f4 7127
477206a0 7128 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 7129 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 7130 goto err_stop_0;
1da177e4
LT		 7131 }
7132
7133 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 7134 goto err_stop_0;
7135
b423e9ae 7136 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7137 opts[0] = DescOwn;
7138
e974604b 7139 if (!tp->tso_csum(tp, skb, opts)) {
7140 r8169_csum_workaround(tp, skb);
7141 return NETDEV_TX_OK;
7142 }
b423e9ae 7143
3eafe507 7144 len = skb_headlen(skb);
48addcc9 7145 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 7146 if (unlikely(dma_mapping_error(d, mapping))) {
7147 if (net_ratelimit())
7148 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 7149 goto err_dma_0;
d827d86b 7150 }
3eafe507
SG		 7151
7152 tp->tx_skb[entry].len = len;
7153 txd->addr = cpu_to_le64(mapping);
1da177e4 7154
2b7b4318 7155 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 7156 if (frags < 0)
7157 goto err_dma_1;
7158 else if (frags)
2b7b4318 7159 opts[0] |= FirstFrag;
3eafe507 7160 else {
2b7b4318 7161 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 7162 tp->tx_skb[entry].skb = skb;
7163 }
7164
2b7b4318
FR		 7165 txd->opts2 = cpu_to_le32(opts[1]);
7166
5047fb5d
RC		 7167 skb_tx_timestamp(skb);
7168
a0750138
AD		 7169 /* Force memory writes to complete before releasing descriptor */
7170 dma_wmb();
1da177e4 7171
cecb5fd7 7172 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 7173 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 7174 txd->opts1 = cpu_to_le32(status);
7175
a0750138 7176 /* Force all memory writes to complete before notifying device */
4c020a96 7177 wmb();
1da177e4 7178
a0750138
AD		 7179 tp->cur_tx += frags + 1;
7180
1ef7286e 7181 RTL_W8(tp, TxPoll, NPQ);
1da177e4 7182
87cda7cb 7183 mmiowb();
da78dbff 7184
87cda7cb 7185 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 7186 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7187 * not miss a ring update when it notices a stopped queue.
7188 */
7189 smp_wmb();
1da177e4 7190 netif_stop_queue(dev);
ae1f23fb
FR		 7191 /* Sync with rtl_tx:
7192 * - publish queue status and cur_tx ring index (write barrier)
7193 * - refresh dirty_tx ring index (read barrier).
7194 * May the current thread have a pessimistic view of the ring
7195 * status and forget to wake up queue, a racing rtl_tx thread
7196 * can't.
7197 */
1e874e04 7198 smp_mb();
477206a0 7199 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 7200 netif_wake_queue(dev);
7201 }
7202
61357325 7203 return NETDEV_TX_OK;
1da177e4 7204
3eafe507 7205err_dma_1:
48addcc9 7206 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 7207err_dma_0:
989c9ba1 7208 dev_kfree_skb_any(skb);
3eafe507
SG		 7209 dev->stats.tx_dropped++;
7210 return NETDEV_TX_OK;
7211
7212err_stop_0:
1da177e4 7213 netif_stop_queue(dev);
cebf8cc7 7214 dev->stats.tx_dropped++;
61357325 7215 return NETDEV_TX_BUSY;
1da177e4
LT		 7216}
7217
7218static void rtl8169_pcierr_interrupt(struct net_device *dev)
7219{
7220 struct rtl8169_private *tp = netdev_priv(dev);
7221 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 7222 u16 pci_status, pci_cmd;
7223
7224 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7225 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7226
bf82c189
JP		 7227 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7228 pci_cmd, pci_status);
1da177e4
LT		 7229
7230 /*
7231 * The recovery sequence below admits a very elaborated explanation:
7232 * - it seems to work;
d03902b8
FR		 7233 * - I did not see what else could be done;
7234 * - it makes iop3xx happy.
1da177e4
LT		 7235 *
7236 * Feel free to adjust to your needs.
7237 */
a27993f3 7238 if (pdev->broken_parity_status)
d03902b8
FR		 7239 pci_cmd &= ~PCI_COMMAND_PARITY;
7240 else
7241 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7242
7243 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 7244
7245 pci_write_config_word(pdev, PCI_STATUS,
7246 pci_status & (PCI_STATUS_DETECTED_PARITY |
7247 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7248 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7249
7250 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 7251 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
bf82c189 7252 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4 7253 tp->cp_cmd &= ~PCIDAC;
1ef7286e 7254 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1da177e4 7255 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 7256 }
7257
e6de30d6 7258 rtl8169_hw_reset(tp);
d03902b8 7259
98ddf986 7260 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 7261}
7262
da78dbff 7263static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 7264{
7265 unsigned int dirty_tx, tx_left;
7266
1da177e4
LT		 7267 dirty_tx = tp->dirty_tx;
7268 smp_rmb();
7269 tx_left = tp->cur_tx - dirty_tx;
7270
7271 while (tx_left > 0) {
7272 unsigned int entry = dirty_tx % NUM_TX_DESC;
7273 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 7274 u32 status;
7275
1da177e4
LT		 7276 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7277 if (status & DescOwn)
7278 break;
7279
a0750138
AD		 7280 /* This barrier is needed to keep us from reading
7281 * any other fields out of the Tx descriptor until
7282 * we know the status of DescOwn
7283 */
7284 dma_rmb();
7285
1e1205b7 7286 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
48addcc9 7287 tp->TxDescArray + entry);
1da177e4 7288 if (status & LastFrag) {
87cda7cb
DM		 7289 u64_stats_update_begin(&tp->tx_stats.syncp);
7290 tp->tx_stats.packets++;
7291 tp->tx_stats.bytes += tx_skb->skb->len;
7292 u64_stats_update_end(&tp->tx_stats.syncp);
7a4b813c 7293 dev_consume_skb_any(tx_skb->skb);
1da177e4
LT		 7294 tx_skb->skb = NULL;
7295 }
7296 dirty_tx++;
7297 tx_left--;
7298 }
7299
7300 if (tp->dirty_tx != dirty_tx) {
7301 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 7302 /* Sync with rtl8169_start_xmit:
7303 * - publish dirty_tx ring index (write barrier)
7304 * - refresh cur_tx ring index and queue status (read barrier)
7305 * May the current thread miss the stopped queue condition,
7306 * a racing xmit thread can only have a right view of the
7307 * ring status.
7308 */
1e874e04 7309 smp_mb();
1da177e4 7310 if (netif_queue_stopped(dev) &&
477206a0 7311 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 7312 netif_wake_queue(dev);
7313 }
d78ae2dc
FR		 7314 /*
7315 * 8168 hack: TxPoll requests are lost when the Tx packets are
7316 * too close. Let's kick an extra TxPoll request when a burst
7317 * of start_xmit activity is detected (if it is not detected,
7318 * it is slow enough). -- FR
7319 */
1ef7286e
AS		 7320 if (tp->cur_tx != dirty_tx)
7321 RTL_W8(tp, TxPoll, NPQ);
1da177e4
LT		 7322 }
7323}
7324
126fa4b9
FR		 7325static inline int rtl8169_fragmented_frame(u32 status)
7326{
7327 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7328}
7329
adea1ac7 7330static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 7331{
1da177e4
LT		 7332 u32 status = opts1 & RxProtoMask;
7333
7334 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 7335 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 7336 skb->ip_summed = CHECKSUM_UNNECESSARY;
7337 else
bc8acf2c 7338 skb_checksum_none_assert(skb);
1da177e4
LT		 7339}
7340
6f0333b8
ED		 7341static struct sk_buff *rtl8169_try_rx_copy(void *data,
7342 struct rtl8169_private *tp,
7343 int pkt_size,
7344 dma_addr_t addr)
1da177e4 7345{
b449655f 7346 struct sk_buff *skb;
1e1205b7 7347 struct device *d = tp_to_dev(tp);
b449655f 7348
6f0333b8 7349 data = rtl8169_align(data);
48addcc9 7350 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8 7351 prefetch(data);
e2338f86 7352 skb = napi_alloc_skb(&tp->napi, pkt_size);
6f0333b8 7353 if (skb)
8a67aa86 7354 skb_copy_to_linear_data(skb, data, pkt_size);
48addcc9
SG		 7355 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7356
6f0333b8 7357 return skb;
1da177e4
LT		 7358}
7359
da78dbff 7360static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 7361{
7362 unsigned int cur_rx, rx_left;
6f0333b8 7363 unsigned int count;
1da177e4 7364
1da177e4 7365 cur_rx = tp->cur_rx;
1da177e4 7366
9fba0812 7367 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 7368 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 7369 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 7370 u32 status;
7371
e03f33af 7372 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 7373 if (status & DescOwn)
7374 break;
a0750138
AD		 7375
7376 /* This barrier is needed to keep us from reading
7377 * any other fields out of the Rx descriptor until
7378 * we know the status of DescOwn
7379 */
7380 dma_rmb();
7381
4dcb7d33 7382 if (unlikely(status & RxRES)) {
bf82c189
JP		 7383 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7384 status);
cebf8cc7 7385 dev->stats.rx_errors++;
1da177e4 7386 if (status & (RxRWT | RxRUNT))
cebf8cc7 7387 dev->stats.rx_length_errors++;
1da177e4 7388 if (status & RxCRC)
cebf8cc7 7389 dev->stats.rx_crc_errors++;
9dccf611 7390 if (status & RxFOVF) {
da78dbff 7391 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 7392 dev->stats.rx_fifo_errors++;
9dccf611 7393 }
6bbe021d
BG		 7394 if ((status & (RxRUNT | RxCRC)) &&
7395 !(status & (RxRWT | RxFOVF)) &&
7396 (dev->features & NETIF_F_RXALL))
7397 goto process_pkt;
1da177e4 7398 } else {
6f0333b8 7399 struct sk_buff *skb;
6bbe021d
BG		 7400 dma_addr_t addr;
7401 int pkt_size;
7402
7403process_pkt:
7404 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 7405 if (likely(!(dev->features & NETIF_F_RXFCS)))
7406 pkt_size = (status & 0x00003fff) - 4;
7407 else
7408 pkt_size = status & 0x00003fff;
1da177e4 7409
126fa4b9
FR		 7410 /*
7411 * The driver does not support incoming fragmented
7412 * frames. They are seen as a symptom of over-mtu
7413 * sized frames.
7414 */
7415 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 7416 dev->stats.rx_dropped++;
7417 dev->stats.rx_length_errors++;
ce11ff5e 7418 goto release_descriptor;
126fa4b9
FR		 7419 }
7420
6f0333b8
ED		 7421 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7422 tp, pkt_size, addr);
6f0333b8
ED		 7423 if (!skb) {
7424 dev->stats.rx_dropped++;
ce11ff5e 7425 goto release_descriptor;
1da177e4
LT		 7426 }
7427
adea1ac7 7428 rtl8169_rx_csum(skb, status);
1da177e4
LT		 7429 skb_put(skb, pkt_size);
7430 skb->protocol = eth_type_trans(skb, dev);
7431
7a8fc77b
FR		 7432 rtl8169_rx_vlan_tag(desc, skb);
7433
39174291 7434 if (skb->pkt_type == PACKET_MULTICAST)
7435 dev->stats.multicast++;
7436
56de414c 7437 napi_gro_receive(&tp->napi, skb);
1da177e4 7438
8027aa24
JW		 7439 u64_stats_update_begin(&tp->rx_stats.syncp);
7440 tp->rx_stats.packets++;
7441 tp->rx_stats.bytes += pkt_size;
7442 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 7443 }
ce11ff5e 7444release_descriptor:
7445 desc->opts2 = 0;
1d0254dd 7446 rtl8169_mark_to_asic(desc);
1da177e4
LT		 7447 }
7448
7449 count = cur_rx - tp->cur_rx;
7450 tp->cur_rx = cur_rx;
7451
1da177e4
LT		 7452 return count;
7453}
7454
07d3f51f 7455static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 7456{
07d3f51f 7457 struct net_device *dev = dev_instance;
1da177e4 7458 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 7459 int handled = 0;
9085cdfa 7460 u16 status;
1da177e4 7461
9085cdfa 7462 status = rtl_get_events(tp);
da78dbff
FR		 7463 if (status && status != 0xffff) {
7464 status &= RTL_EVENT_NAPI | tp->event_slow;
7465 if (status) {
7466 handled = 1;
1da177e4 7467
da78dbff 7468 rtl_irq_disable(tp);
9a899a35 7469 napi_schedule_irqoff(&tp->napi);
f11a377b 7470 }
da78dbff
FR		 7471 }
7472 return IRQ_RETVAL(handled);
7473}
1da177e4 7474
da78dbff
FR		 7475/*
7476 * Workqueue context.
7477 */
7478static void rtl_slow_event_work(struct rtl8169_private *tp)
7479{
7480 struct net_device *dev = tp->dev;
7481 u16 status;
7482
7483 status = rtl_get_events(tp) & tp->event_slow;
7484 rtl_ack_events(tp, status);
1da177e4 7485
da78dbff
FR		 7486 if (unlikely(status & RxFIFOOver)) {
7487 switch (tp->mac_version) {
7488 /* Work around for rx fifo overflow */
7489 case RTL_GIGA_MAC_VER_11:
7490 netif_stop_queue(dev);
934714d0
FR		 7491 /* XXX - Hack alert. See rtl_task(). */
7492 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 7493 default:
f11a377b
DD		 7494 break;
7495 }
da78dbff 7496 }
1da177e4 7497
da78dbff
FR		 7498 if (unlikely(status & SYSErr))
7499 rtl8169_pcierr_interrupt(dev);
0e485150 7500
da78dbff 7501 if (status & LinkChg)
1ef7286e 7502 rtl8169_check_link_status(dev, tp);
1da177e4 7503
7dbb4918 7504 rtl_irq_enable_all(tp);
1da177e4
LT		 7505}
7506
4422bcd4
FR		 7507static void rtl_task(struct work_struct *work)
7508{
da78dbff
FR		 7509 static const struct {
7510 int bitnr;
7511 void (*action)(struct rtl8169_private *);
7512 } rtl_work[] = {
934714d0 7513 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 7514 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7515 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7516 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7517 };
4422bcd4
FR		 7518 struct rtl8169_private *tp =
7519 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 7520 struct net_device *dev = tp->dev;
7521 int i;
7522
7523 rtl_lock_work(tp);
7524
6c4a70c5
FR		 7525 if (!netif_running(dev) ||
7526 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 7527 goto out_unlock;
7528
7529 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7530 bool pending;
7531
da78dbff 7532 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 7533 if (pending)
7534 rtl_work[i].action(tp);
7535 }
4422bcd4 7536
da78dbff
FR		 7537out_unlock:
7538 rtl_unlock_work(tp);
4422bcd4
FR		 7539}
7540
bea3348e 7541static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 7542{
bea3348e
SH		 7543 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7544 struct net_device *dev = tp->dev;
da78dbff
FR		 7545 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7546 int work_done= 0;
7547 u16 status;
7548
7549 status = rtl_get_events(tp);
7550 rtl_ack_events(tp, status & ~tp->event_slow);
7551
7552 if (status & RTL_EVENT_NAPI_RX)
7553 work_done = rtl_rx(dev, tp, (u32) budget);
7554
7555 if (status & RTL_EVENT_NAPI_TX)
7556 rtl_tx(dev, tp);
1da177e4 7557
da78dbff
FR		 7558 if (status & tp->event_slow) {
7559 enable_mask &= ~tp->event_slow;
7560
7561 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7562 }
1da177e4 7563
bea3348e 7564 if (work_done < budget) {
6ad20165 7565 napi_complete_done(napi, work_done);
f11a377b 7566
da78dbff
FR		 7567 rtl_irq_enable(tp, enable_mask);
7568 mmiowb();
1da177e4
LT		 7569 }
7570
bea3348e 7571 return work_done;
1da177e4 7572}
1da177e4 7573
1ef7286e 7574static void rtl8169_rx_missed(struct net_device *dev)
523a6094
FR		 7575{
7576 struct rtl8169_private *tp = netdev_priv(dev);
7577
7578 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7579 return;
7580
1ef7286e
AS		 7581 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
7582 RTL_W32(tp, RxMissed, 0);
523a6094
FR		 7583}
7584
1da177e4
LT		 7585static void rtl8169_down(struct net_device *dev)
7586{
7587 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 7588
4876cc1e 7589 del_timer_sync(&tp->timer);
1da177e4 7590
93dd79e8 7591 napi_disable(&tp->napi);
da78dbff 7592 netif_stop_queue(dev);
1da177e4 7593
92fc43b4 7594 rtl8169_hw_reset(tp);
323bb685
SG		 7595 /*
7596 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 7597 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7598 * and napi is disabled (rtl8169_poll).
323bb685 7599 */
1ef7286e 7600 rtl8169_rx_missed(dev);
1da177e4 7601
1da177e4 7602 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 7603 synchronize_sched();
1da177e4 7604
1da177e4
LT		 7605 rtl8169_tx_clear(tp);
7606
7607 rtl8169_rx_clear(tp);
065c27c1 7608
7609 rtl_pll_power_down(tp);
1da177e4
LT		 7610}
7611
7612static int rtl8169_close(struct net_device *dev)
7613{
7614 struct rtl8169_private *tp = netdev_priv(dev);
7615 struct pci_dev *pdev = tp->pci_dev;
7616
e1759441
RW		 7617 pm_runtime_get_sync(&pdev->dev);
7618
cecb5fd7 7619 /* Update counters before going down */
355423d0
IV		 7620 rtl8169_update_counters(dev);
7621
da78dbff 7622 rtl_lock_work(tp);
6c4a70c5 7623 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 7624
1da177e4 7625 rtl8169_down(dev);
da78dbff 7626 rtl_unlock_work(tp);
1da177e4 7627
4ea72445
L		 7628 cancel_work_sync(&tp->wk.work);
7629
6c6aa15f 7630 pci_free_irq(pdev, 0, dev);
1da177e4 7631
82553bb6
SG		 7632 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7633 tp->RxPhyAddr);
7634 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7635 tp->TxPhyAddr);
1da177e4
LT		 7636 tp->TxDescArray = NULL;
7637 tp->RxDescArray = NULL;
7638
e1759441
RW		 7639 pm_runtime_put_sync(&pdev->dev);
7640
1da177e4
LT		 7641 return 0;
7642}
7643
dc1c00ce
FR		 7644#ifdef CONFIG_NET_POLL_CONTROLLER
7645static void rtl8169_netpoll(struct net_device *dev)
7646{
7647 struct rtl8169_private *tp = netdev_priv(dev);
7648
29274991 7649 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), dev);
dc1c00ce
FR		 7650}
7651#endif
7652
df43ac78
FR		 7653static int rtl_open(struct net_device *dev)
7654{
7655 struct rtl8169_private *tp = netdev_priv(dev);
df43ac78
FR		 7656 struct pci_dev *pdev = tp->pci_dev;
7657 int retval = -ENOMEM;
7658
7659 pm_runtime_get_sync(&pdev->dev);
7660
7661 /*
e75d6606 7662 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 7663 * dma_alloc_coherent provides more.
7664 */
7665 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7666 &tp->TxPhyAddr, GFP_KERNEL);
7667 if (!tp->TxDescArray)
7668 goto err_pm_runtime_put;
7669
7670 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7671 &tp->RxPhyAddr, GFP_KERNEL);
7672 if (!tp->RxDescArray)
7673 goto err_free_tx_0;
7674
b1127e64 7675 retval = rtl8169_init_ring(tp);
df43ac78
FR		 7676 if (retval < 0)
7677 goto err_free_rx_1;
7678
7679 INIT_WORK(&tp->wk.work, rtl_task);
7680
7681 smp_mb();
7682
7683 rtl_request_firmware(tp);
7684
6c6aa15f
HK		 7685 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, dev,
7686 dev->name);
df43ac78
FR		 7687 if (retval < 0)
7688 goto err_release_fw_2;
7689
7690 rtl_lock_work(tp);
7691
7692 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7693
7694 napi_enable(&tp->napi);
7695
7696 rtl8169_init_phy(dev, tp);
7697
7698 __rtl8169_set_features(dev, dev->features);
7699
7700 rtl_pll_power_up(tp);
7701
7702 rtl_hw_start(dev);
7703
6e85d5ad
CV		 7704 if (!rtl8169_init_counter_offsets(dev))
7705 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7706
df43ac78
FR		 7707 netif_start_queue(dev);
7708
7709 rtl_unlock_work(tp);
7710
7711 tp->saved_wolopts = 0;
a92a0849 7712 pm_runtime_put_sync(&pdev->dev);
df43ac78 7713
1ef7286e 7714 rtl8169_check_link_status(dev, tp);
df43ac78
FR		 7715out:
7716 return retval;
7717
7718err_release_fw_2:
7719 rtl_release_firmware(tp);
7720 rtl8169_rx_clear(tp);
7721err_free_rx_1:
7722 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7723 tp->RxPhyAddr);
7724 tp->RxDescArray = NULL;
7725err_free_tx_0:
7726 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7727 tp->TxPhyAddr);
7728 tp->TxDescArray = NULL;
7729err_pm_runtime_put:
7730 pm_runtime_put_noidle(&pdev->dev);
7731 goto out;
7732}
7733
bc1f4470 7734static void
8027aa24 7735rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 7736{
7737 struct rtl8169_private *tp = netdev_priv(dev);
f09cf4b7 7738 struct pci_dev *pdev = tp->pci_dev;
42020320 7739 struct rtl8169_counters *counters = tp->counters;
8027aa24 7740 unsigned int start;
1da177e4 7741
f09cf4b7
CHL		 7742 pm_runtime_get_noresume(&pdev->dev);
7743
7744 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
1ef7286e 7745 rtl8169_rx_missed(dev);
5b0384f4 7746
8027aa24 7747 do {
57a7744e 7748 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 7749 stats->rx_packets = tp->rx_stats.packets;
7750 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 7751 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 7752
8027aa24 7753 do {
57a7744e 7754 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 7755 stats->tx_packets = tp->tx_stats.packets;
7756 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 7757 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 7758
7759 stats->rx_dropped = dev->stats.rx_dropped;
7760 stats->tx_dropped = dev->stats.tx_dropped;
7761 stats->rx_length_errors = dev->stats.rx_length_errors;
7762 stats->rx_errors = dev->stats.rx_errors;
7763 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7764 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7765 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 7766 stats->multicast = dev->stats.multicast;
8027aa24 7767
6e85d5ad
CV		 7768 /*
7769 * Fetch additonal counter values missing in stats collected by driver
7770 * from tally counters.
7771 */
f09cf4b7
CHL		 7772 if (pm_runtime_active(&pdev->dev))
7773 rtl8169_update_counters(dev);
6e85d5ad
CV		 7774
7775 /*
7776 * Subtract values fetched during initalization.
7777 * See rtl8169_init_counter_offsets for a description why we do that.
7778 */
42020320 7779 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 7780 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 7781 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 7782 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 7783 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 7784 le16_to_cpu(tp->tc_offset.tx_aborted);
7785
f09cf4b7 7786 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 7787}
7788
861ab440 7789static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 7790{
065c27c1 7791 struct rtl8169_private *tp = netdev_priv(dev);
7792
5d06a99f 7793 if (!netif_running(dev))
861ab440 7794 return;
5d06a99f
FR		 7795
7796 netif_device_detach(dev);
7797 netif_stop_queue(dev);
da78dbff
FR		 7798
7799 rtl_lock_work(tp);
7800 napi_disable(&tp->napi);
6c4a70c5 7801 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 7802 rtl_unlock_work(tp);
7803
7804 rtl_pll_power_down(tp);
861ab440
RW		 7805}
7806
7807#ifdef CONFIG_PM
7808
7809static int rtl8169_suspend(struct device *device)
7810{
7811 struct pci_dev *pdev = to_pci_dev(device);
7812 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 7813
861ab440 7814 rtl8169_net_suspend(dev);
1371fa6d 7815
5d06a99f
FR		 7816 return 0;
7817}
7818
e1759441
RW		 7819static void __rtl8169_resume(struct net_device *dev)
7820{
065c27c1 7821 struct rtl8169_private *tp = netdev_priv(dev);
7822
e1759441 7823 netif_device_attach(dev);
065c27c1 7824
7825 rtl_pll_power_up(tp);
7826
cff4c162
AS		 7827 rtl_lock_work(tp);
7828 napi_enable(&tp->napi);
6c4a70c5 7829 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 7830 rtl_unlock_work(tp);
da78dbff 7831
98ddf986 7832 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 7833}
7834
861ab440 7835static int rtl8169_resume(struct device *device)
5d06a99f 7836{
861ab440 7837 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 7838 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 7839 struct rtl8169_private *tp = netdev_priv(dev);
7840
7841 rtl8169_init_phy(dev, tp);
5d06a99f 7842
e1759441
RW		 7843 if (netif_running(dev))
7844 __rtl8169_resume(dev);
5d06a99f 7845
e1759441
RW		 7846 return 0;
7847}
7848
7849static int rtl8169_runtime_suspend(struct device *device)
7850{
7851 struct pci_dev *pdev = to_pci_dev(device);
7852 struct net_device *dev = pci_get_drvdata(pdev);
7853 struct rtl8169_private *tp = netdev_priv(dev);
7854
a92a0849
HK		 7855 if (!tp->TxDescArray) {
7856 rtl_pll_power_down(tp);
e1759441 7857 return 0;
a92a0849 7858 }
e1759441 7859
da78dbff 7860 rtl_lock_work(tp);
e1759441
RW		 7861 tp->saved_wolopts = __rtl8169_get_wol(tp);
7862 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 7863 rtl_unlock_work(tp);
e1759441
RW		 7864
7865 rtl8169_net_suspend(dev);
7866
f09cf4b7 7867 /* Update counters before going runtime suspend */
1ef7286e 7868 rtl8169_rx_missed(dev);
f09cf4b7
CHL		 7869 rtl8169_update_counters(dev);
7870
e1759441
RW		 7871 return 0;
7872}
7873
7874static int rtl8169_runtime_resume(struct device *device)
7875{
7876 struct pci_dev *pdev = to_pci_dev(device);
7877 struct net_device *dev = pci_get_drvdata(pdev);
7878 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 7879 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 7880
7881 if (!tp->TxDescArray)
7882 return 0;
7883
da78dbff 7884 rtl_lock_work(tp);
e1759441
RW		 7885 __rtl8169_set_wol(tp, tp->saved_wolopts);
7886 tp->saved_wolopts = 0;
da78dbff 7887 rtl_unlock_work(tp);
e1759441 7888
fccec10b
SG		 7889 rtl8169_init_phy(dev, tp);
7890
e1759441 7891 __rtl8169_resume(dev);
5d06a99f 7892
5d06a99f
FR		 7893 return 0;
7894}
7895
e1759441
RW		 7896static int rtl8169_runtime_idle(struct device *device)
7897{
7898 struct pci_dev *pdev = to_pci_dev(device);
7899 struct net_device *dev = pci_get_drvdata(pdev);
e1759441 7900
a92a0849
HK		 7901 if (!netif_running(dev) || !netif_carrier_ok(dev))
7902 pm_schedule_suspend(device, 10000);
7903
7904 return -EBUSY;
e1759441
RW		 7905}
7906
47145210 7907static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 7908 .suspend = rtl8169_suspend,
7909 .resume = rtl8169_resume,
7910 .freeze = rtl8169_suspend,
7911 .thaw = rtl8169_resume,
7912 .poweroff = rtl8169_suspend,
7913 .restore = rtl8169_resume,
7914 .runtime_suspend = rtl8169_runtime_suspend,
7915 .runtime_resume = rtl8169_runtime_resume,
7916 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 7917};
7918
7919#define RTL8169_PM_OPS (&rtl8169_pm_ops)
7920
7921#else /* !CONFIG_PM */
7922
7923#define RTL8169_PM_OPS NULL
7924
7925#endif /* !CONFIG_PM */
7926
649b3b8c 7927static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7928{
649b3b8c 7929 /* WoL fails with 8168b when the receiver is disabled. */
7930 switch (tp->mac_version) {
7931 case RTL_GIGA_MAC_VER_11:
7932 case RTL_GIGA_MAC_VER_12:
7933 case RTL_GIGA_MAC_VER_17:
7934 pci_clear_master(tp->pci_dev);
7935
1ef7286e 7936 RTL_W8(tp, ChipCmd, CmdRxEnb);
649b3b8c 7937 /* PCI commit */
1ef7286e 7938 RTL_R8(tp, ChipCmd);
649b3b8c 7939 break;
7940 default:
7941 break;
7942 }
7943}
7944
1765f95d
FR		 7945static void rtl_shutdown(struct pci_dev *pdev)
7946{
861ab440 7947 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 7948 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 7949
7950 rtl8169_net_suspend(dev);
1765f95d 7951
cecb5fd7 7952 /* Restore original MAC address */
cc098dc7
IV		 7953 rtl_rar_set(tp, dev->perm_addr);
7954
92fc43b4 7955 rtl8169_hw_reset(tp);
4bb3f522 7956
861ab440 7957 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 7958 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7959 rtl_wol_suspend_quirk(tp);
7960 rtl_wol_shutdown_quirk(tp);
ca52efd5 7961 }
7962
861ab440
RW		 7963 pci_wake_from_d3(pdev, true);
7964 pci_set_power_state(pdev, PCI_D3hot);
7965 }
7966}
5d06a99f 7967
baf63293 7968static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 7969{
7970 struct net_device *dev = pci_get_drvdata(pdev);
7971 struct rtl8169_private *tp = netdev_priv(dev);
7972
9dbe7896 7973 if (r8168_check_dash(tp))
e27566ed 7974 rtl8168_driver_stop(tp);
e27566ed 7975
ad1be8d3
DN		 7976 netif_napi_del(&tp->napi);
7977
e27566ed
FR		 7978 unregister_netdev(dev);
7979
7980 rtl_release_firmware(tp);
7981
7982 if (pci_dev_run_wake(pdev))
7983 pm_runtime_get_noresume(&pdev->dev);
7984
7985 /* restore original MAC address */
7986 rtl_rar_set(tp, dev->perm_addr);
e27566ed
FR		 7987}
7988
fa9c385e 7989static const struct net_device_ops rtl_netdev_ops = {
df43ac78 7990 .ndo_open = rtl_open,
fa9c385e
FR		 7991 .ndo_stop = rtl8169_close,
7992 .ndo_get_stats64 = rtl8169_get_stats64,
7993 .ndo_start_xmit = rtl8169_start_xmit,
7994 .ndo_tx_timeout = rtl8169_tx_timeout,
7995 .ndo_validate_addr = eth_validate_addr,
7996 .ndo_change_mtu = rtl8169_change_mtu,
7997 .ndo_fix_features = rtl8169_fix_features,
7998 .ndo_set_features = rtl8169_set_features,
7999 .ndo_set_mac_address = rtl_set_mac_address,
8000 .ndo_do_ioctl = rtl8169_ioctl,
8001 .ndo_set_rx_mode = rtl_set_rx_mode,
8002#ifdef CONFIG_NET_POLL_CONTROLLER
8003 .ndo_poll_controller = rtl8169_netpoll,
8004#endif
8005
8006};
8007
31fa8b18
FR		 8008static const struct rtl_cfg_info {
8009 void (*hw_start)(struct net_device *);
8010 unsigned int region;
31fa8b18 8011 u16 event_slow;
14967f94 8012 unsigned int has_gmii:1;
50970831 8013 const struct rtl_coalesce_info *coalesce_info;
31fa8b18
FR		 8014 u8 default_ver;
8015} rtl_cfg_infos [] = {
8016 [RTL_CFG_0] = {
8017 .hw_start = rtl_hw_start_8169,
8018 .region = 1,
31fa8b18 8019 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
14967f94 8020 .has_gmii = 1,
50970831 8021 .coalesce_info = rtl_coalesce_info_8169,
31fa8b18
FR		 8022 .default_ver = RTL_GIGA_MAC_VER_01,
8023 },
8024 [RTL_CFG_1] = {
8025 .hw_start = rtl_hw_start_8168,
8026 .region = 2,
31fa8b18 8027 .event_slow = SYSErr | LinkChg | RxOverflow,
14967f94 8028 .has_gmii = 1,
50970831 8029 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 8030 .default_ver = RTL_GIGA_MAC_VER_11,
8031 },
8032 [RTL_CFG_2] = {
8033 .hw_start = rtl_hw_start_8101,
8034 .region = 2,
31fa8b18
FR		 8035 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8036 PCSTimeout,
50970831 8037 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 8038 .default_ver = RTL_GIGA_MAC_VER_13,
8039 }
8040};
8041
6c6aa15f 8042static int rtl_alloc_irq(struct rtl8169_private *tp)
31fa8b18 8043{
6c6aa15f 8044 unsigned int flags;
31fa8b18 8045
6c6aa15f 8046 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1ef7286e
AS		 8047 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
8048 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
8049 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6c6aa15f
HK		 8050 flags = PCI_IRQ_LEGACY;
8051 } else {
8052 flags = PCI_IRQ_ALL_TYPES;
31fa8b18 8053 }
6c6aa15f
HK		 8054
8055 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
31fa8b18
FR		 8056}
8057
c558386b
HW		 8058DECLARE_RTL_COND(rtl_link_list_ready_cond)
8059{
1ef7286e 8060 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
c558386b
HW		 8061}
8062
8063DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8064{
1ef7286e 8065 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
c558386b
HW		 8066}
8067
baf63293 8068static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b 8069{
c558386b
HW		 8070 u32 data;
8071
8072 tp->ocp_base = OCP_STD_PHY_BASE;
8073
1ef7286e 8074 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
c558386b
HW		 8075
8076 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8077 return;
8078
8079 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8080 return;
8081
1ef7286e 8082 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
c558386b 8083 msleep(1);
1ef7286e 8084 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
c558386b 8085
5f8bcce9 8086 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 8087 data &= ~(1 << 14);
8088 r8168_mac_ocp_write(tp, 0xe8de, data);
8089
8090 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8091 return;
8092
5f8bcce9 8093 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 8094 data |= (1 << 15);
8095 r8168_mac_ocp_write(tp, 0xe8de, data);
8096
8097 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8098 return;
8099}
8100
003609da
CHL		 8101static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8102{
8103 rtl8168ep_stop_cmac(tp);
8104 rtl_hw_init_8168g(tp);
8105}
8106
baf63293 8107static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 8108{
8109 switch (tp->mac_version) {
8110 case RTL_GIGA_MAC_VER_40:
8111 case RTL_GIGA_MAC_VER_41:
57538c4a 8112 case RTL_GIGA_MAC_VER_42:
58152cd4 8113 case RTL_GIGA_MAC_VER_43:
45dd95c4 8114 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 8115 case RTL_GIGA_MAC_VER_45:
8116 case RTL_GIGA_MAC_VER_46:
8117 case RTL_GIGA_MAC_VER_47:
8118 case RTL_GIGA_MAC_VER_48:
003609da
CHL		 8119 rtl_hw_init_8168g(tp);
8120 break;
935e2218
CHL		 8121 case RTL_GIGA_MAC_VER_49:
8122 case RTL_GIGA_MAC_VER_50:
8123 case RTL_GIGA_MAC_VER_51:
003609da 8124 rtl_hw_init_8168ep(tp);
c558386b 8125 break;
c558386b
HW		 8126 default:
8127 break;
8128 }
8129}
8130
929a031d 8131static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 8132{
8133 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8134 const unsigned int region = cfg->region;
8135 struct rtl8169_private *tp;
8136 struct mii_if_info *mii;
8137 struct net_device *dev;
3b6cf25d
FR		 8138 int chipset, i;
8139 int rc;
8140
8141 if (netif_msg_drv(&debug)) {
8142 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8143 MODULENAME, RTL8169_VERSION);
8144 }
8145
4c45d24a
HK		 8146 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
8147 if (!dev)
8148 return -ENOMEM;
3b6cf25d
FR		 8149
8150 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 8151 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 8152 tp = netdev_priv(dev);
8153 tp->dev = dev;
8154 tp->pci_dev = pdev;
8155 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8156
8157 mii = &tp->mii;
8158 mii->dev = dev;
8159 mii->mdio_read = rtl_mdio_read;
8160 mii->mdio_write = rtl_mdio_write;
8161 mii->phy_id_mask = 0x1f;
8162 mii->reg_num_mask = 0x1f;
14967f94 8163 mii->supports_gmii = cfg->has_gmii;
3b6cf25d
FR		 8164
8165 /* disable ASPM completely as that cause random device stop working
8166 * problems as well as full system hangs for some PCIe devices users */
8167 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8168 PCIE_LINK_STATE_CLKPM);
8169
8170 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4c45d24a 8171 rc = pcim_enable_device(pdev);
3b6cf25d
FR		 8172 if (rc < 0) {
8173 netif_err(tp, probe, dev, "enable failure\n");
4c45d24a 8174 return rc;
3b6cf25d
FR		 8175 }
8176
4c45d24a 8177 if (pcim_set_mwi(pdev) < 0)
3b6cf25d
FR		 8178 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8179
8180 /* make sure PCI base addr 1 is MMIO */
8181 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8182 netif_err(tp, probe, dev,
8183 "region #%d not an MMIO resource, aborting\n",
8184 region);
4c45d24a 8185 return -ENODEV;
3b6cf25d
FR		 8186 }
8187
8188 /* check for weird/broken PCI region reporting */
8189 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8190 netif_err(tp, probe, dev,
8191 "Invalid PCI region size(s), aborting\n");
4c45d24a 8192 return -ENODEV;
3b6cf25d
FR		 8193 }
8194
93a00d4d 8195 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
3b6cf25d 8196 if (rc < 0) {
93a00d4d 8197 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
4c45d24a 8198 return rc;
3b6cf25d
FR		 8199 }
8200
93a00d4d 8201 tp->mmio_addr = pcim_iomap_table(pdev)[region];
3b6cf25d
FR		 8202
8203 if (!pci_is_pcie(pdev))
8204 netif_info(tp, probe, dev, "not PCI Express\n");
8205
8206 /* Identify chip attached to board */
8207 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8208
27896c83
AB		 8209 tp->cp_cmd = 0;
8210
8211 if ((sizeof(dma_addr_t) > 4) &&
8212 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8213 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
f0076436
AB		 8214 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8215 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
27896c83
AB		 8216
8217 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8218 if (!pci_is_pcie(pdev))
8219 tp->cp_cmd |= PCIDAC;
8220 dev->features |= NETIF_F_HIGHDMA;
8221 } else {
8222 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8223 if (rc < 0) {
8224 netif_err(tp, probe, dev, "DMA configuration failed\n");
4c45d24a 8225 return rc;
27896c83
AB		 8226 }
8227 }
8228
3b6cf25d
FR		 8229 rtl_init_rxcfg(tp);
8230
8231 rtl_irq_disable(tp);
8232
c558386b
HW		 8233 rtl_hw_initialize(tp);
8234
3b6cf25d
FR		 8235 rtl_hw_reset(tp);
8236
8237 rtl_ack_events(tp, 0xffff);
8238
8239 pci_set_master(pdev);
8240
3b6cf25d
FR		 8241 rtl_init_mdio_ops(tp);
8242 rtl_init_pll_power_ops(tp);
8243 rtl_init_jumbo_ops(tp);
beb1fe18 8244 rtl_init_csi_ops(tp);
3b6cf25d
FR		 8245
8246 rtl8169_print_mac_version(tp);
8247
8248 chipset = tp->mac_version;
8249 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8250
6c6aa15f
HK		 8251 rc = rtl_alloc_irq(tp);
8252 if (rc < 0) {
8253 netif_err(tp, probe, dev, "Can't allocate interrupt\n");
8254 return rc;
8255 }
3b6cf25d 8256
7edf6d31
HK		 8257 /* override BIOS settings, use userspace tools to enable WOL */
8258 __rtl8169_set_wol(tp, 0);
8259
3b6cf25d
FR		 8260 if (rtl_tbi_enabled(tp)) {
8261 tp->set_speed = rtl8169_set_speed_tbi;
6fa1ba61 8262 tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi;
3b6cf25d
FR		 8263 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8264 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8265 tp->link_ok = rtl8169_tbi_link_ok;
8266 tp->do_ioctl = rtl_tbi_ioctl;
8267 } else {
8268 tp->set_speed = rtl8169_set_speed_xmii;
6fa1ba61 8269 tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii;
3b6cf25d
FR		 8270 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8271 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8272 tp->link_ok = rtl8169_xmii_link_ok;
8273 tp->do_ioctl = rtl_xmii_ioctl;
8274 }
8275
8276 mutex_init(&tp->wk.mutex);
340fea3d
KM		 8277 u64_stats_init(&tp->rx_stats.syncp);
8278 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 8279
8280 /* Get MAC address */
89cceb27
CHL		 8281 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8282 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8283 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8284 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8285 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8286 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8287 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8288 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8289 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8290 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
6e1d0b89
CHL		 8291 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8292 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
935e2218
CHL		 8293 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8294 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8295 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8296 tp->mac_version == RTL_GIGA_MAC_VER_51) {
6e1d0b89
CHL		 8297 u16 mac_addr[3];
8298
05b9687b
CHL		 8299 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8300 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89
CHL		 8301
8302 if (is_valid_ether_addr((u8 *)mac_addr))
8303 rtl_rar_set(tp, (u8 *)mac_addr);
8304 }
3b6cf25d 8305 for (i = 0; i < ETH_ALEN; i++)
1ef7286e 8306 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
3b6cf25d 8307
7ad24ea4 8308 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 8309 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d 8310
37621493 8311 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
3b6cf25d
FR		 8312
8313 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8314 * properly for all devices */
8315 dev->features |= NETIF_F_RXCSUM |
f646968f 8316 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 8317
8318 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 8319 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8320 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 8321 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8322 NETIF_F_HIGHDMA;
8323
929a031d 8324 tp->cp_cmd |= RxChkSum | RxVlan;
8325
8326 /*
8327 * Pretend we are using VLANs; This bypasses a nasty bug where
8328 * Interrupts stop flowing on high load on 8110SCd controllers.
8329 */
3b6cf25d 8330 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 8331 /* Disallow toggling */
f646968f 8332 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 8333
5888d3fc 8334 if (tp->txd_version == RTL_TD_0)
8335 tp->tso_csum = rtl8169_tso_csum_v1;
e974604b 8336 else if (tp->txd_version == RTL_TD_1) {
5888d3fc 8337 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 8338 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8339 } else
5888d3fc 8340 WARN_ON_ONCE(1);
8341
3b6cf25d
FR		 8342 dev->hw_features |= NETIF_F_RXALL;
8343 dev->hw_features |= NETIF_F_RXFCS;
8344
c7315a95
JW		 8345 /* MTU range: 60 - hw-specific max */
8346 dev->min_mtu = ETH_ZLEN;
8347 dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
8348
3b6cf25d
FR		 8349 tp->hw_start = cfg->hw_start;
8350 tp->event_slow = cfg->event_slow;
50970831 8351 tp->coalesce_info = cfg->coalesce_info;
3b6cf25d
FR		 8352
8353 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8354 ~(RxBOVF | RxFOVF) : ~0;
8355
9de36ccf 8356 timer_setup(&tp->timer, rtl8169_phy_timer, 0);
3b6cf25d
FR		 8357
8358 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8359
4c45d24a
HK		 8360 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8361 &tp->counters_phys_addr,
8362 GFP_KERNEL);
4cf964af
HK		 8363 if (!tp->counters)
8364 return -ENOMEM;
42020320 8365
19c9ea36
HK		 8366 pci_set_drvdata(pdev, dev);
8367
3b6cf25d
FR		 8368 rc = register_netdev(dev);
8369 if (rc < 0)
4cf964af 8370 return rc;
3b6cf25d 8371
92a7c4e7 8372 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
93a00d4d 8373 rtl_chip_infos[chipset].name, tp->mmio_addr, dev->dev_addr,
1ef7286e 8374 (u32)(RTL_R32(tp, TxConfig) & 0x9cf0f8ff),
29274991 8375 pci_irq_vector(pdev, 0));
3b6cf25d
FR		 8376 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8377 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8378 "tx checksumming: %s]\n",
8379 rtl_chip_infos[chipset].jumbo_max,
8380 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8381 }
8382
9dbe7896 8383 if (r8168_check_dash(tp))
3b6cf25d 8384 rtl8168_driver_start(tp);
3b6cf25d 8385
3b6cf25d
FR		 8386 netif_carrier_off(dev);
8387
a92a0849
HK		 8388 if (pci_dev_run_wake(pdev))
8389 pm_runtime_put_sync(&pdev->dev);
8390
4c45d24a 8391 return 0;
3b6cf25d
FR		 8392}
8393
1da177e4
LT		 8394static struct pci_driver rtl8169_pci_driver = {
8395 .name = MODULENAME,
8396 .id_table = rtl8169_pci_tbl,
3b6cf25d 8397 .probe = rtl_init_one,
baf63293 8398 .remove = rtl_remove_one,
1765f95d 8399 .shutdown = rtl_shutdown,
861ab440 8400 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 8401};
8402
3eeb7da9 8403module_pci_driver(rtl8169_pci_driver);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git