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r8169: remove rtl8169_reinit_task.
[thirdparty/kernel/stable.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4 31
99f252b0 32#include <asm/system.h>
1da177e4
LT		 33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 48
1da177e4
LT		 49#ifdef RTL8169_DEBUG
50#define assert(expr) \
5b0384f4
FR		 51 if (!(expr)) { \
52 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 53 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 54 }
06fa7358
JP		 55#define dprintk(fmt, args...) \
56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 57#else
58#define assert(expr) do {} while (0)
59#define dprintk(fmt, args...) do {} while (0)
60#endif /* RTL8169_DEBUG */
61
b57b7e5a 62#define R8169_MSG_DEFAULT \
f0e837d9 63 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 64
1da177e4
LT		 65#define TX_BUFFS_AVAIL(tp) \
66 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
67
1da177e4
LT		 68/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 70static const int multicast_filter_limit = 32;
1da177e4 71
9c14ceaf 72#define MAX_READ_REQUEST_SHIFT 12
1da177e4 73#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 74#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76
77#define R8169_REGS_SIZE 256
78#define R8169_NAPI_WEIGHT 64
79#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81#define RX_BUF_SIZE 1536 /* Rx Buffer size */
82#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
84
85#define RTL8169_TX_TIMEOUT (6*HZ)
86#define RTL8169_PHY_TIMEOUT (10*HZ)
87
ea8dbdd1 88#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 90#define RTL_EEPROM_SIG_ADDR 0x0000
91
1da177e4
LT		 92/* write/read MMIO register */
93#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96#define RTL_R8(reg) readb (ioaddr + (reg))
97#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 98#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 99
100enum mac_version {
85bffe6c
FR		 101 RTL_GIGA_MAC_VER_01 = 0,
102 RTL_GIGA_MAC_VER_02,
103 RTL_GIGA_MAC_VER_03,
104 RTL_GIGA_MAC_VER_04,
105 RTL_GIGA_MAC_VER_05,
106 RTL_GIGA_MAC_VER_06,
107 RTL_GIGA_MAC_VER_07,
108 RTL_GIGA_MAC_VER_08,
109 RTL_GIGA_MAC_VER_09,
110 RTL_GIGA_MAC_VER_10,
111 RTL_GIGA_MAC_VER_11,
112 RTL_GIGA_MAC_VER_12,
113 RTL_GIGA_MAC_VER_13,
114 RTL_GIGA_MAC_VER_14,
115 RTL_GIGA_MAC_VER_15,
116 RTL_GIGA_MAC_VER_16,
117 RTL_GIGA_MAC_VER_17,
118 RTL_GIGA_MAC_VER_18,
119 RTL_GIGA_MAC_VER_19,
120 RTL_GIGA_MAC_VER_20,
121 RTL_GIGA_MAC_VER_21,
122 RTL_GIGA_MAC_VER_22,
123 RTL_GIGA_MAC_VER_23,
124 RTL_GIGA_MAC_VER_24,
125 RTL_GIGA_MAC_VER_25,
126 RTL_GIGA_MAC_VER_26,
127 RTL_GIGA_MAC_VER_27,
128 RTL_GIGA_MAC_VER_28,
129 RTL_GIGA_MAC_VER_29,
130 RTL_GIGA_MAC_VER_30,
131 RTL_GIGA_MAC_VER_31,
132 RTL_GIGA_MAC_VER_32,
133 RTL_GIGA_MAC_VER_33,
70090424 134 RTL_GIGA_MAC_VER_34,
c2218925
HW		 135 RTL_GIGA_MAC_VER_35,
136 RTL_GIGA_MAC_VER_36,
85bffe6c 137 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 138};
139
2b7b4318
FR		 140enum rtl_tx_desc_version {
141 RTL_TD_0 = 0,
142 RTL_TD_1 = 1,
143};
144
d58d46b5
FR		 145#define JUMBO_1K ETH_DATA_LEN
146#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
147#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
148#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
149#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
150
151#define _R(NAME,TD,FW,SZ,B) { \
152 .name = NAME, \
153 .txd_version = TD, \
154 .fw_name = FW, \
155 .jumbo_max = SZ, \
156 .jumbo_tx_csum = B \
157}
1da177e4 158
3c6bee1d 159static const struct {
1da177e4 160 const char *name;
2b7b4318 161 enum rtl_tx_desc_version txd_version;
953a12cc 162 const char *fw_name;
d58d46b5
FR		 163 u16 jumbo_max;
164 bool jumbo_tx_csum;
85bffe6c
FR		 165} rtl_chip_infos[] = {
166 /* PCI devices. */
167 [RTL_GIGA_MAC_VER_01] =
d58d46b5 168 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 169 [RTL_GIGA_MAC_VER_02] =
d58d46b5 170 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 171 [RTL_GIGA_MAC_VER_03] =
d58d46b5 172 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 173 [RTL_GIGA_MAC_VER_04] =
d58d46b5 174 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 175 [RTL_GIGA_MAC_VER_05] =
d58d46b5 176 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 177 [RTL_GIGA_MAC_VER_06] =
d58d46b5 178 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 179 /* PCI-E devices. */
180 [RTL_GIGA_MAC_VER_07] =
d58d46b5 181 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 182 [RTL_GIGA_MAC_VER_08] =
d58d46b5 183 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 184 [RTL_GIGA_MAC_VER_09] =
d58d46b5 185 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 186 [RTL_GIGA_MAC_VER_10] =
d58d46b5 187 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 188 [RTL_GIGA_MAC_VER_11] =
d58d46b5 189 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 190 [RTL_GIGA_MAC_VER_12] =
d58d46b5 191 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 192 [RTL_GIGA_MAC_VER_13] =
d58d46b5 193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_14] =
d58d46b5 195 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 196 [RTL_GIGA_MAC_VER_15] =
d58d46b5 197 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 198 [RTL_GIGA_MAC_VER_16] =
d58d46b5 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 200 [RTL_GIGA_MAC_VER_17] =
d58d46b5 201 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 202 [RTL_GIGA_MAC_VER_18] =
d58d46b5 203 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 204 [RTL_GIGA_MAC_VER_19] =
d58d46b5 205 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 206 [RTL_GIGA_MAC_VER_20] =
d58d46b5 207 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 208 [RTL_GIGA_MAC_VER_21] =
d58d46b5 209 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 210 [RTL_GIGA_MAC_VER_22] =
d58d46b5 211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 212 [RTL_GIGA_MAC_VER_23] =
d58d46b5 213 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_24] =
d58d46b5 215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 217 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
218 JUMBO_9K, false),
85bffe6c 219 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 220 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
221 JUMBO_9K, false),
85bffe6c 222 [RTL_GIGA_MAC_VER_27] =
d58d46b5 223 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 224 [RTL_GIGA_MAC_VER_28] =
d58d46b5 225 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 226 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 227 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
228 JUMBO_1K, true),
85bffe6c 229 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 230 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
231 JUMBO_1K, true),
85bffe6c 232 [RTL_GIGA_MAC_VER_31] =
d58d46b5 233 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 235 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
236 JUMBO_9K, false),
85bffe6c 237 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 238 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
239 JUMBO_9K, false),
70090424 240 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 241 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
242 JUMBO_9K, false),
c2218925 243 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 244 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
245 JUMBO_9K, false),
c2218925 246 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 247 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
248 JUMBO_9K, false),
953a12cc 249};
85bffe6c 250#undef _R
953a12cc 251
bcf0bf90
FR		 252enum cfg_version {
253 RTL_CFG_0 = 0x00,
254 RTL_CFG_1,
255 RTL_CFG_2
256};
257
07ce4064
FR		 258static void rtl_hw_start_8169(struct net_device *);
259static void rtl_hw_start_8168(struct net_device *);
260static void rtl_hw_start_8101(struct net_device *);
261
a3aa1884 262static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 263 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 264 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
268 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 269 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 270 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 271 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
272 { PCI_VENDOR_ID_LINKSYS, 0x1032,
273 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 274 { 0x0001, 0x8168,
275 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 276 {0,},
277};
278
279MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
280
6f0333b8 281static int rx_buf_sz = 16383;
4300e8c7 282static int use_dac;
b57b7e5a
SH		 283static struct {
284 u32 msg_enable;
285} debug = { -1 };
1da177e4 286
07d3f51f
FR		 287enum rtl_registers {
288 MAC0 = 0, /* Ethernet hardware address. */
773d2021 289 MAC4 = 4,
07d3f51f
FR		 290 MAR0 = 8, /* Multicast filter. */
291 CounterAddrLow = 0x10,
292 CounterAddrHigh = 0x14,
293 TxDescStartAddrLow = 0x20,
294 TxDescStartAddrHigh = 0x24,
295 TxHDescStartAddrLow = 0x28,
296 TxHDescStartAddrHigh = 0x2c,
297 FLASH = 0x30,
298 ERSR = 0x36,
299 ChipCmd = 0x37,
300 TxPoll = 0x38,
301 IntrMask = 0x3c,
302 IntrStatus = 0x3e,
4f6b00e5 303
07d3f51f 304 TxConfig = 0x40,
4f6b00e5
HW		 305#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
306#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 307
4f6b00e5
HW		 308 RxConfig = 0x44,
309#define RX128_INT_EN (1 << 15) /* 8111c and later */
310#define RX_MULTI_EN (1 << 14) /* 8111c only */
311#define RXCFG_FIFO_SHIFT 13
312 /* No threshold before first PCI xfer */
313#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
314#define RXCFG_DMA_SHIFT 8
315 /* Unlimited maximum PCI burst. */
316#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 317
07d3f51f
FR		 318 RxMissed = 0x4c,
319 Cfg9346 = 0x50,
320 Config0 = 0x51,
321 Config1 = 0x52,
322 Config2 = 0x53,
323 Config3 = 0x54,
324 Config4 = 0x55,
325 Config5 = 0x56,
326 MultiIntr = 0x5c,
327 PHYAR = 0x60,
07d3f51f
FR		 328 PHYstatus = 0x6c,
329 RxMaxSize = 0xda,
330 CPlusCmd = 0xe0,
331 IntrMitigate = 0xe2,
332 RxDescAddrLow = 0xe4,
333 RxDescAddrHigh = 0xe8,
f0298f81 334 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
335
336#define NoEarlyTx 0x3f /* Max value : no early transmit. */
337
338 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
339
340#define TxPacketMax (8064 >> 7)
3090bd9a 341#define EarlySize 0x27
f0298f81 342
07d3f51f
FR		 343 FuncEvent = 0xf0,
344 FuncEventMask = 0xf4,
345 FuncPresetState = 0xf8,
346 FuncForceEvent = 0xfc,
1da177e4
LT		 347};
348
f162a5d1
FR		 349enum rtl8110_registers {
350 TBICSR = 0x64,
351 TBI_ANAR = 0x68,
352 TBI_LPAR = 0x6a,
353};
354
355enum rtl8168_8101_registers {
356 CSIDR = 0x64,
357 CSIAR = 0x68,
358#define CSIAR_FLAG 0x80000000
359#define CSIAR_WRITE_CMD 0x80000000
360#define CSIAR_BYTE_ENABLE 0x0f
361#define CSIAR_BYTE_ENABLE_SHIFT 12
362#define CSIAR_ADDR_MASK 0x0fff
065c27c1 363 PMCH = 0x6f,
f162a5d1
FR		 364 EPHYAR = 0x80,
365#define EPHYAR_FLAG 0x80000000
366#define EPHYAR_WRITE_CMD 0x80000000
367#define EPHYAR_REG_MASK 0x1f
368#define EPHYAR_REG_SHIFT 16
369#define EPHYAR_DATA_MASK 0xffff
5a5e4443 370 DLLPR = 0xd0,
4f6b00e5 371#define PFM_EN (1 << 6)
f162a5d1
FR		 372 DBG_REG = 0xd1,
373#define FIX_NAK_1 (1 << 4)
374#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 375 TWSI = 0xd2,
376 MCU = 0xd3,
4f6b00e5 377#define NOW_IS_OOB (1 << 7)
5a5e4443
HW		 378#define EN_NDP (1 << 3)
379#define EN_OOB_RESET (1 << 2)
daf9df6d 380 EFUSEAR = 0xdc,
381#define EFUSEAR_FLAG 0x80000000
382#define EFUSEAR_WRITE_CMD 0x80000000
383#define EFUSEAR_READ_CMD 0x00000000
384#define EFUSEAR_REG_MASK 0x03ff
385#define EFUSEAR_REG_SHIFT 8
386#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 387};
388
c0e45c1c 389enum rtl8168_registers {
4f6b00e5
HW		 390 LED_FREQ = 0x1a,
391 EEE_LED = 0x1b,
b646d900 392 ERIDR = 0x70,
393 ERIAR = 0x74,
394#define ERIAR_FLAG 0x80000000
395#define ERIAR_WRITE_CMD 0x80000000
396#define ERIAR_READ_CMD 0x00000000
397#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 398#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 399#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
400#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
401#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
402#define ERIAR_MASK_SHIFT 12
403#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
404#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
405#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 406 EPHY_RXER_NUM = 0x7c,
407 OCPDR = 0xb0, /* OCP GPHY access */
408#define OCPDR_WRITE_CMD 0x80000000
409#define OCPDR_READ_CMD 0x00000000
410#define OCPDR_REG_MASK 0x7f
411#define OCPDR_GPHY_REG_SHIFT 16
412#define OCPDR_DATA_MASK 0xffff
413 OCPAR = 0xb4,
414#define OCPAR_FLAG 0x80000000
415#define OCPAR_GPHY_WRITE_CMD 0x8000f060
416#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 417 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
418 MISC = 0xf0, /* 8168e only. */
cecb5fd7 419#define TXPLA_RST (1 << 29)
4f6b00e5 420#define PWM_EN (1 << 22)
c0e45c1c 421};
422
07d3f51f 423enum rtl_register_content {
1da177e4 424 /* InterruptStatusBits */
07d3f51f
FR		 425 SYSErr = 0x8000,
426 PCSTimeout = 0x4000,
427 SWInt = 0x0100,
428 TxDescUnavail = 0x0080,
429 RxFIFOOver = 0x0040,
430 LinkChg = 0x0020,
431 RxOverflow = 0x0010,
432 TxErr = 0x0008,
433 TxOK = 0x0004,
434 RxErr = 0x0002,
435 RxOK = 0x0001,
1da177e4
LT		 436
437 /* RxStatusDesc */
e03f33af 438 RxBOVF = (1 << 24),
9dccf611
FR		 439 RxFOVF = (1 << 23),
440 RxRWT = (1 << 22),
441 RxRES = (1 << 21),
442 RxRUNT = (1 << 20),
443 RxCRC = (1 << 19),
1da177e4
LT		 444
445 /* ChipCmdBits */
4f6b00e5 446 StopReq = 0x80,
07d3f51f
FR		 447 CmdReset = 0x10,
448 CmdRxEnb = 0x08,
449 CmdTxEnb = 0x04,
450 RxBufEmpty = 0x01,
1da177e4 451
275391a4
FR		 452 /* TXPoll register p.5 */
453 HPQ = 0x80, /* Poll cmd on the high prio queue */
454 NPQ = 0x40, /* Poll cmd on the low prio queue */
455 FSWInt = 0x01, /* Forced software interrupt */
456
1da177e4 457 /* Cfg9346Bits */
07d3f51f
FR		 458 Cfg9346_Lock = 0x00,
459 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 460
461 /* rx_mode_bits */
07d3f51f
FR		 462 AcceptErr = 0x20,
463 AcceptRunt = 0x10,
464 AcceptBroadcast = 0x08,
465 AcceptMulticast = 0x04,
466 AcceptMyPhys = 0x02,
467 AcceptAllPhys = 0x01,
1687b566 468#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 469
1da177e4
LT		 470 /* TxConfigBits */
471 TxInterFrameGapShift = 24,
472 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
473
5d06a99f 474 /* Config1 register p.24 */
f162a5d1
FR		 475 LEDS1 = (1 << 7),
476 LEDS0 = (1 << 6),
f162a5d1
FR		 477 Speed_down = (1 << 4),
478 MEMMAP = (1 << 3),
479 IOMAP = (1 << 2),
480 VPD = (1 << 1),
5d06a99f
FR		 481 PMEnable = (1 << 0), /* Power Management Enable */
482
6dccd16b 483 /* Config2 register p. 25 */
2ca6cf06 484 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 485 PCI_Clock_66MHz = 0x01,
486 PCI_Clock_33MHz = 0x00,
487
61a4dcc2
FR		 488 /* Config3 register p.25 */
489 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
490 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 491 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 492 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 493
d58d46b5
FR		 494 /* Config4 register */
495 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
496
5d06a99f 497 /* Config5 register p.27 */
61a4dcc2
FR		 498 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
499 MWF = (1 << 5), /* Accept Multicast wakeup frame */
500 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 501 Spi_en = (1 << 3),
61a4dcc2 502 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 503 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
504
1da177e4
LT		 505 /* TBICSR p.28 */
506 TBIReset = 0x80000000,
507 TBILoopback = 0x40000000,
508 TBINwEnable = 0x20000000,
509 TBINwRestart = 0x10000000,
510 TBILinkOk = 0x02000000,
511 TBINwComplete = 0x01000000,
512
513 /* CPlusCmd p.31 */
f162a5d1
FR		 514 EnableBist = (1 << 15), // 8168 8101
515 Mac_dbgo_oe = (1 << 14), // 8168 8101
516 Normal_mode = (1 << 13), // unused
517 Force_half_dup = (1 << 12), // 8168 8101
518 Force_rxflow_en = (1 << 11), // 8168 8101
519 Force_txflow_en = (1 << 10), // 8168 8101
520 Cxpl_dbg_sel = (1 << 9), // 8168 8101
521 ASF = (1 << 8), // 8168 8101
522 PktCntrDisable = (1 << 7), // 8168 8101
523 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 524 RxVlan = (1 << 6),
525 RxChkSum = (1 << 5),
526 PCIDAC = (1 << 4),
527 PCIMulRW = (1 << 3),
0e485150
FR		 528 INTT_0 = 0x0000, // 8168
529 INTT_1 = 0x0001, // 8168
530 INTT_2 = 0x0002, // 8168
531 INTT_3 = 0x0003, // 8168
1da177e4
LT		 532
533 /* rtl8169_PHYstatus */
07d3f51f
FR		 534 TBI_Enable = 0x80,
535 TxFlowCtrl = 0x40,
536 RxFlowCtrl = 0x20,
537 _1000bpsF = 0x10,
538 _100bps = 0x08,
539 _10bps = 0x04,
540 LinkStatus = 0x02,
541 FullDup = 0x01,
1da177e4 542
1da177e4 543 /* _TBICSRBit */
07d3f51f 544 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 545
546 /* DumpCounterCommand */
07d3f51f 547 CounterDump = 0x8,
1da177e4
LT		 548};
549
2b7b4318
FR		 550enum rtl_desc_bit {
551 /* First doubleword. */
1da177e4
LT		 552 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
553 RingEnd = (1 << 30), /* End of descriptor ring */
554 FirstFrag = (1 << 29), /* First segment of a packet */
555 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 556};
557
558/* Generic case. */
559enum rtl_tx_desc_bit {
560 /* First doubleword. */
561 TD_LSO = (1 << 27), /* Large Send Offload */
562#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 563
2b7b4318
FR		 564 /* Second doubleword. */
565 TxVlanTag = (1 << 17), /* Add VLAN tag */
566};
567
568/* 8169, 8168b and 810x except 8102e. */
569enum rtl_tx_desc_bit_0 {
570 /* First doubleword. */
571#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
572 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
573 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
574 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
575};
576
577/* 8102e, 8168c and beyond. */
578enum rtl_tx_desc_bit_1 {
579 /* Second doubleword. */
580#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
581 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
582 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
583 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
584};
1da177e4 585
2b7b4318
FR		 586static const struct rtl_tx_desc_info {
587 struct {
588 u32 udp;
589 u32 tcp;
590 } checksum;
591 u16 mss_shift;
592 u16 opts_offset;
593} tx_desc_info [] = {
594 [RTL_TD_0] = {
595 .checksum = {
596 .udp = TD0_IP_CS | TD0_UDP_CS,
597 .tcp = TD0_IP_CS | TD0_TCP_CS
598 },
599 .mss_shift = TD0_MSS_SHIFT,
600 .opts_offset = 0
601 },
602 [RTL_TD_1] = {
603 .checksum = {
604 .udp = TD1_IP_CS | TD1_UDP_CS,
605 .tcp = TD1_IP_CS | TD1_TCP_CS
606 },
607 .mss_shift = TD1_MSS_SHIFT,
608 .opts_offset = 1
609 }
610};
611
612enum rtl_rx_desc_bit {
1da177e4
LT		 613 /* Rx private */
614 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
615 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
616
617#define RxProtoUDP (PID1)
618#define RxProtoTCP (PID0)
619#define RxProtoIP (PID1 | PID0)
620#define RxProtoMask RxProtoIP
621
622 IPFail = (1 << 16), /* IP checksum failed */
623 UDPFail = (1 << 15), /* UDP/IP checksum failed */
624 TCPFail = (1 << 14), /* TCP/IP checksum failed */
625 RxVlanTag = (1 << 16), /* VLAN tag available */
626};
627
628#define RsvdMask 0x3fffc000
629
630struct TxDesc {
6cccd6e7
REB		 631 __le32 opts1;
632 __le32 opts2;
633 __le64 addr;
1da177e4
LT		 634};
635
636struct RxDesc {
6cccd6e7
REB		 637 __le32 opts1;
638 __le32 opts2;
639 __le64 addr;
1da177e4
LT		 640};
641
642struct ring_info {
643 struct sk_buff *skb;
644 u32 len;
645 u8 __pad[sizeof(void *) - sizeof(u32)];
646};
647
f23e7fda 648enum features {
ccdffb9a
FR		 649 RTL_FEATURE_WOL = (1 << 0),
650 RTL_FEATURE_MSI = (1 << 1),
651 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 652};
653
355423d0
IV		 654struct rtl8169_counters {
655 __le64 tx_packets;
656 __le64 rx_packets;
657 __le64 tx_errors;
658 __le32 rx_errors;
659 __le16 rx_missed;
660 __le16 align_errors;
661 __le32 tx_one_collision;
662 __le32 tx_multi_collision;
663 __le64 rx_unicast;
664 __le64 rx_broadcast;
665 __le32 rx_multicast;
666 __le16 tx_aborted;
667 __le16 tx_underun;
668};
669
1da177e4
LT		 670struct rtl8169_private {
671 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 672 struct pci_dev *pci_dev;
c4028958 673 struct net_device *dev;
bea3348e 674 struct napi_struct napi;
cecb5fd7 675 spinlock_t lock;
b57b7e5a 676 u32 msg_enable;
2b7b4318
FR		 677 u16 txd_version;
678 u16 mac_version;
1da177e4
LT		 679 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
680 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
681 u32 dirty_rx;
682 u32 dirty_tx;
683 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
684 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
685 dma_addr_t TxPhyAddr;
686 dma_addr_t RxPhyAddr;
6f0333b8 687 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 688 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 689 struct timer_list timer;
690 u16 cp_cmd;
0e485150
FR		 691 u16 intr_event;
692 u16 napi_event;
1da177e4 693 u16 intr_mask;
c0e45c1c 694
695 struct mdio_ops {
696 void (*write)(void __iomem *, int, int);
697 int (*read)(void __iomem *, int);
698 } mdio_ops;
699
065c27c1 700 struct pll_power_ops {
701 void (*down)(struct rtl8169_private *);
702 void (*up)(struct rtl8169_private *);
703 } pll_power_ops;
704
d58d46b5
FR		 705 struct jumbo_ops {
706 void (*enable)(struct rtl8169_private *);
707 void (*disable)(struct rtl8169_private *);
708 } jumbo_ops;
709
54405cde 710 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 711 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 712 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 713 void (*hw_start)(struct net_device *);
4da19633 714 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 715 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 716 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
c4028958 717 struct delayed_work task;
f23e7fda 718 unsigned features;
ccdffb9a
FR		 719
720 struct mii_if_info mii;
355423d0 721 struct rtl8169_counters counters;
e1759441 722 u32 saved_wolopts;
e03f33af 723 u32 opts1_mask;
f1e02ed1 724
b6ffd97f
FR		 725 struct rtl_fw {
726 const struct firmware *fw;
1c361efb
FR		 727
728#define RTL_VER_SIZE 32
729
730 char version[RTL_VER_SIZE];
731
732 struct rtl_fw_phy_action {
733 __le32 *code;
734 size_t size;
735 } phy_action;
b6ffd97f 736 } *rtl_fw;
497888cf 737#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
1da177e4
LT		 738};
739
979b6c13 740MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 741MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 742module_param(use_dac, int, 0);
4300e8c7 743MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 744module_param_named(debug, debug.msg_enable, int, 0);
745MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 746MODULE_LICENSE("GPL");
747MODULE_VERSION(RTL8169_VERSION);
bca03d5f 748MODULE_FIRMWARE(FIRMWARE_8168D_1);
749MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 750MODULE_FIRMWARE(FIRMWARE_8168E_1);
751MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 752MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 753MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 754MODULE_FIRMWARE(FIRMWARE_8168F_1);
755MODULE_FIRMWARE(FIRMWARE_8168F_2);
1da177e4
LT		 756
757static int rtl8169_open(struct net_device *dev);
61357325
SH		 758static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
759 struct net_device *dev);
7d12e780 760static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 761static int rtl8169_init_ring(struct net_device *dev);
07ce4064 762static void rtl_hw_start(struct net_device *dev);
1da177e4 763static int rtl8169_close(struct net_device *dev);
07ce4064 764static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 765static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 766static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 767static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 768 void __iomem *, u32 budget);
4dcb7d33 769static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 770static void rtl8169_down(struct net_device *dev);
99f252b0 771static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 772static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 773
d58d46b5
FR		 774static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
775{
776 int cap = pci_pcie_cap(pdev);
777
778 if (cap) {
779 u16 ctl;
780
781 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
782 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
783 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
784 }
785}
786
b646d900 787static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
788{
789 void __iomem *ioaddr = tp->mmio_addr;
790 int i;
791
792 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
793 for (i = 0; i < 20; i++) {
794 udelay(100);
795 if (RTL_R32(OCPAR) & OCPAR_FLAG)
796 break;
797 }
798 return RTL_R32(OCPDR);
799}
800
801static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
802{
803 void __iomem *ioaddr = tp->mmio_addr;
804 int i;
805
806 RTL_W32(OCPDR, data);
807 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
808 for (i = 0; i < 20; i++) {
809 udelay(100);
810 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
811 break;
812 }
813}
814
fac5b3ca 815static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 816{
fac5b3ca 817 void __iomem *ioaddr = tp->mmio_addr;
b646d900 818 int i;
819
820 RTL_W8(ERIDR, cmd);
821 RTL_W32(ERIAR, 0x800010e8);
822 msleep(2);
823 for (i = 0; i < 5; i++) {
824 udelay(100);
1e4e82ba 825 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
b646d900 826 break;
827 }
828
fac5b3ca 829 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 830}
831
832#define OOB_CMD_RESET 0x00
833#define OOB_CMD_DRIVER_START 0x05
834#define OOB_CMD_DRIVER_STOP 0x06
835
cecb5fd7
FR		 836static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
837{
838 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
839}
840
b646d900 841static void rtl8168_driver_start(struct rtl8169_private *tp)
842{
cecb5fd7 843 u16 reg;
b646d900 844 int i;
845
846 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
847
cecb5fd7 848 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 849
b646d900 850 for (i = 0; i < 10; i++) {
851 msleep(10);
4804b3b3 852 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 853 break;
854 }
855}
856
857static void rtl8168_driver_stop(struct rtl8169_private *tp)
858{
cecb5fd7 859 u16 reg;
b646d900 860 int i;
861
862 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
863
cecb5fd7 864 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 865
b646d900 866 for (i = 0; i < 10; i++) {
867 msleep(10);
4804b3b3 868 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 869 break;
870 }
871}
872
4804b3b3 873static int r8168dp_check_dash(struct rtl8169_private *tp)
874{
cecb5fd7 875 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 876
cecb5fd7 877 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 878}
b646d900 879
4da19633 880static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 881{
882 int i;
883
a6baf3af 884 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 885
2371408c 886 for (i = 20; i > 0; i--) {
07d3f51f
FR		 887 /*
888 * Check if the RTL8169 has completed writing to the specified
889 * MII register.
890 */
5b0384f4 891 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 892 break;
2371408c 893 udelay(25);
1da177e4 894 }
024a07ba 895 /*
81a95f04
TT		 896 * According to hardware specs a 20us delay is required after write
897 * complete indication, but before sending next command.
024a07ba 898 */
81a95f04 899 udelay(20);
1da177e4
LT		 900}
901
4da19633 902static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 903{
904 int i, value = -1;
905
a6baf3af 906 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 907
2371408c 908 for (i = 20; i > 0; i--) {
07d3f51f
FR		 909 /*
910 * Check if the RTL8169 has completed retrieving data from
911 * the specified MII register.
912 */
1da177e4 913 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 914 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 915 break;
916 }
2371408c 917 udelay(25);
1da177e4 918 }
81a95f04
TT		 919 /*
920 * According to hardware specs a 20us delay is required after read
921 * complete indication, but before sending next command.
922 */
923 udelay(20);
924
1da177e4
LT		 925 return value;
926}
927
c0e45c1c 928static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
929{
930 int i;
931
932 RTL_W32(OCPDR, data |
933 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
934 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
935 RTL_W32(EPHY_RXER_NUM, 0);
936
937 for (i = 0; i < 100; i++) {
938 mdelay(1);
939 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
940 break;
941 }
942}
943
944static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
945{
946 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
947 (value & OCPDR_DATA_MASK));
948}
949
950static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
951{
952 int i;
953
954 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
955
956 mdelay(1);
957 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
958 RTL_W32(EPHY_RXER_NUM, 0);
959
960 for (i = 0; i < 100; i++) {
961 mdelay(1);
962 if (RTL_R32(OCPAR) & OCPAR_FLAG)
963 break;
964 }
965
966 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
967}
968
e6de30d6 969#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
970
971static void r8168dp_2_mdio_start(void __iomem *ioaddr)
972{
973 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
974}
975
976static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
977{
978 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
979}
980
981static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
982{
983 r8168dp_2_mdio_start(ioaddr);
984
985 r8169_mdio_write(ioaddr, reg_addr, value);
986
987 r8168dp_2_mdio_stop(ioaddr);
988}
989
990static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
991{
992 int value;
993
994 r8168dp_2_mdio_start(ioaddr);
995
996 value = r8169_mdio_read(ioaddr, reg_addr);
997
998 r8168dp_2_mdio_stop(ioaddr);
999
1000 return value;
1001}
1002
4da19633 1003static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1004{
c0e45c1c 1005 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 1006}
1007
4da19633 1008static int rtl_readphy(struct rtl8169_private *tp, int location)
1009{
c0e45c1c 1010 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 1011}
1012
1013static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1014{
1015 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1016}
1017
1018static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1019{
1020 int val;
1021
4da19633 1022 val = rtl_readphy(tp, reg_addr);
1023 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1024}
1025
ccdffb9a
FR		 1026static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1027 int val)
1028{
1029 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1030
4da19633 1031 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1032}
1033
1034static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1035{
1036 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1037
4da19633 1038 return rtl_readphy(tp, location);
ccdffb9a
FR		 1039}
1040
dacf8154
FR		 1041static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1042{
1043 unsigned int i;
1044
1045 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1046 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1047
1048 for (i = 0; i < 100; i++) {
1049 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1050 break;
1051 udelay(10);
1052 }
1053}
1054
1055static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1056{
1057 u16 value = 0xffff;
1058 unsigned int i;
1059
1060 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1061
1062 for (i = 0; i < 100; i++) {
1063 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1064 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1065 break;
1066 }
1067 udelay(10);
1068 }
1069
1070 return value;
1071}
1072
1073static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1074{
1075 unsigned int i;
1076
1077 RTL_W32(CSIDR, value);
1078 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1079 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1080
1081 for (i = 0; i < 100; i++) {
1082 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1083 break;
1084 udelay(10);
1085 }
1086}
1087
1088static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1089{
1090 u32 value = ~0x00;
1091 unsigned int i;
1092
1093 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1094 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1095
1096 for (i = 0; i < 100; i++) {
1097 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1098 value = RTL_R32(CSIDR);
1099 break;
1100 }
1101 udelay(10);
1102 }
1103
1104 return value;
1105}
1106
133ac40a
HW		 1107static
1108void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1109{
1110 unsigned int i;
1111
1112 BUG_ON((addr & 3) || (mask == 0));
1113 RTL_W32(ERIDR, val);
1114 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1115
1116 for (i = 0; i < 100; i++) {
1117 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1118 break;
1119 udelay(100);
1120 }
1121}
1122
1123static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1124{
1125 u32 value = ~0x00;
1126 unsigned int i;
1127
1128 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1129
1130 for (i = 0; i < 100; i++) {
1131 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1132 value = RTL_R32(ERIDR);
1133 break;
1134 }
1135 udelay(100);
1136 }
1137
1138 return value;
1139}
1140
1141static void
1142rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1143{
1144 u32 val;
1145
1146 val = rtl_eri_read(ioaddr, addr, type);
1147 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1148}
1149
c28aa385 1150struct exgmac_reg {
1151 u16 addr;
1152 u16 mask;
1153 u32 val;
1154};
1155
1156static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1157 const struct exgmac_reg *r, int len)
1158{
1159 while (len-- > 0) {
1160 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1161 r++;
1162 }
1163}
1164
daf9df6d 1165static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1166{
1167 u8 value = 0xff;
1168 unsigned int i;
1169
1170 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1171
1172 for (i = 0; i < 300; i++) {
1173 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1174 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1175 break;
1176 }
1177 udelay(100);
1178 }
1179
1180 return value;
1181}
1182
811fd301 1183static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1184{
811fd301 1185 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1186
811fd301 1187 RTL_W16(IntrMask, 0x0000);
1188 RTL_W16(IntrStatus, tp->intr_event);
1189 RTL_R8(ChipCmd);
1da177e4
LT		 1190}
1191
4da19633 1192static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1193{
4da19633 1194 void __iomem *ioaddr = tp->mmio_addr;
1195
1da177e4
LT		 1196 return RTL_R32(TBICSR) & TBIReset;
1197}
1198
4da19633 1199static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1200{
4da19633 1201 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1202}
1203
1204static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1205{
1206 return RTL_R32(TBICSR) & TBILinkOk;
1207}
1208
1209static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1210{
1211 return RTL_R8(PHYstatus) & LinkStatus;
1212}
1213
4da19633 1214static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1215{
4da19633 1216 void __iomem *ioaddr = tp->mmio_addr;
1217
1da177e4
LT		 1218 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1219}
1220
4da19633 1221static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1222{
1223 unsigned int val;
1224
4da19633 1225 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1226 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1227}
1228
70090424
HW		 1229static void rtl_link_chg_patch(struct rtl8169_private *tp)
1230{
1231 void __iomem *ioaddr = tp->mmio_addr;
1232 struct net_device *dev = tp->dev;
1233
1234 if (!netif_running(dev))
1235 return;
1236
1237 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1238 if (RTL_R8(PHYstatus) & _1000bpsF) {
1239 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1240 0x00000011, ERIAR_EXGMAC);
1241 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1242 0x00000005, ERIAR_EXGMAC);
1243 } else if (RTL_R8(PHYstatus) & _100bps) {
1244 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1245 0x0000001f, ERIAR_EXGMAC);
1246 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1247 0x00000005, ERIAR_EXGMAC);
1248 } else {
1249 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1250 0x0000001f, ERIAR_EXGMAC);
1251 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1252 0x0000003f, ERIAR_EXGMAC);
1253 }
1254 /* Reset packet filter */
1255 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1256 ERIAR_EXGMAC);
1257 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1258 ERIAR_EXGMAC);
c2218925
HW		 1259 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1260 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1261 if (RTL_R8(PHYstatus) & _1000bpsF) {
1262 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1263 0x00000011, ERIAR_EXGMAC);
1264 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1265 0x00000005, ERIAR_EXGMAC);
1266 } else {
1267 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1268 0x0000001f, ERIAR_EXGMAC);
1269 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1270 0x0000003f, ERIAR_EXGMAC);
1271 }
70090424
HW		 1272 }
1273}
1274
e4fbce74 1275static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1276 struct rtl8169_private *tp,
1277 void __iomem *ioaddr, bool pm)
1da177e4
LT		 1278{
1279 unsigned long flags;
1280
1281 spin_lock_irqsave(&tp->lock, flags);
1282 if (tp->link_ok(ioaddr)) {
70090424 1283 rtl_link_chg_patch(tp);
e1759441 1284 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1285 if (pm)
1286 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1287 netif_carrier_on(dev);
1519e57f
FR		 1288 if (net_ratelimit())
1289 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1290 } else {
1da177e4 1291 netif_carrier_off(dev);
bf82c189 1292 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1293 if (pm)
10953db8 1294 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1295 }
1da177e4
LT		 1296 spin_unlock_irqrestore(&tp->lock, flags);
1297}
1298
e4fbce74
RW		 1299static void rtl8169_check_link_status(struct net_device *dev,
1300 struct rtl8169_private *tp,
1301 void __iomem *ioaddr)
1302{
1303 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1304}
1305
e1759441
RW		 1306#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1307
1308static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1309{
61a4dcc2
FR		 1310 void __iomem *ioaddr = tp->mmio_addr;
1311 u8 options;
e1759441 1312 u32 wolopts = 0;
61a4dcc2
FR		 1313
1314 options = RTL_R8(Config1);
1315 if (!(options & PMEnable))
e1759441 1316 return 0;
61a4dcc2
FR		 1317
1318 options = RTL_R8(Config3);
1319 if (options & LinkUp)
e1759441 1320 wolopts |= WAKE_PHY;
61a4dcc2 1321 if (options & MagicPacket)
e1759441 1322 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1323
1324 options = RTL_R8(Config5);
1325 if (options & UWF)
e1759441 1326 wolopts |= WAKE_UCAST;
61a4dcc2 1327 if (options & BWF)
e1759441 1328 wolopts |= WAKE_BCAST;
61a4dcc2 1329 if (options & MWF)
e1759441 1330 wolopts |= WAKE_MCAST;
61a4dcc2 1331
e1759441 1332 return wolopts;
61a4dcc2
FR		 1333}
1334
e1759441 1335static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1336{
1337 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1338
1339 spin_lock_irq(&tp->lock);
1340
1341 wol->supported = WAKE_ANY;
1342 wol->wolopts = __rtl8169_get_wol(tp);
1343
1344 spin_unlock_irq(&tp->lock);
1345}
1346
1347static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1348{
61a4dcc2 1349 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1350 unsigned int i;
350f7596 1351 static const struct {
61a4dcc2
FR		 1352 u32 opt;
1353 u16 reg;
1354 u8 mask;
1355 } cfg[] = {
1356 { WAKE_ANY, Config1, PMEnable },
1357 { WAKE_PHY, Config3, LinkUp },
1358 { WAKE_MAGIC, Config3, MagicPacket },
1359 { WAKE_UCAST, Config5, UWF },
1360 { WAKE_BCAST, Config5, BWF },
1361 { WAKE_MCAST, Config5, MWF },
1362 { WAKE_ANY, Config5, LanWake }
1363 };
1364
61a4dcc2
FR		 1365 RTL_W8(Cfg9346, Cfg9346_Unlock);
1366
1367 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1368 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1369 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1370 options |= cfg[i].mask;
1371 RTL_W8(cfg[i].reg, options);
1372 }
1373
1374 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1375}
1376
1377static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1378{
1379 struct rtl8169_private *tp = netdev_priv(dev);
1380
1381 spin_lock_irq(&tp->lock);
61a4dcc2 1382
f23e7fda
FR		 1383 if (wol->wolopts)
1384 tp->features |= RTL_FEATURE_WOL;
1385 else
1386 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1387 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1388 spin_unlock_irq(&tp->lock);
1389
ea80907f 1390 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1391
61a4dcc2
FR		 1392 return 0;
1393}
1394
31bd204f
FR		 1395static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1396{
85bffe6c 1397 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1398}
1399
1da177e4
LT		 1400static void rtl8169_get_drvinfo(struct net_device *dev,
1401 struct ethtool_drvinfo *info)
1402{
1403 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1404 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1405
68aad78c
RJ		 1406 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1407 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1408 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1409 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1410 if (!IS_ERR_OR_NULL(rtl_fw))
1411 strlcpy(info->fw_version, rtl_fw->version,
1412 sizeof(info->fw_version));
1da177e4
LT		 1413}
1414
1415static int rtl8169_get_regs_len(struct net_device *dev)
1416{
1417 return R8169_REGS_SIZE;
1418}
1419
1420static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1421 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1422{
1423 struct rtl8169_private *tp = netdev_priv(dev);
1424 void __iomem *ioaddr = tp->mmio_addr;
1425 int ret = 0;
1426 u32 reg;
1427
1428 reg = RTL_R32(TBICSR);
1429 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1430 (duplex == DUPLEX_FULL)) {
1431 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1432 } else if (autoneg == AUTONEG_ENABLE)
1433 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1434 else {
bf82c189
JP		 1435 netif_warn(tp, link, dev,
1436 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1437 ret = -EOPNOTSUPP;
1438 }
1439
1440 return ret;
1441}
1442
1443static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1444 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1445{
1446 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1447 int giga_ctrl, bmcr;
54405cde 1448 int rc = -EINVAL;
1da177e4 1449
716b50a3 1450 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1451
1452 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1453 int auto_nego;
1454
4da19633 1455 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1456 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1457 ADVERTISE_100HALF | ADVERTISE_100FULL);
1458
1459 if (adv & ADVERTISED_10baseT_Half)
1460 auto_nego |= ADVERTISE_10HALF;
1461 if (adv & ADVERTISED_10baseT_Full)
1462 auto_nego |= ADVERTISE_10FULL;
1463 if (adv & ADVERTISED_100baseT_Half)
1464 auto_nego |= ADVERTISE_100HALF;
1465 if (adv & ADVERTISED_100baseT_Full)
1466 auto_nego |= ADVERTISE_100FULL;
1467
3577aa1b 1468 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1469
4da19633 1470 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1471 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1472
3577aa1b 1473 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1474 if (tp->mii.supports_gmii) {
54405cde
ON		 1475 if (adv & ADVERTISED_1000baseT_Half)
1476 giga_ctrl |= ADVERTISE_1000HALF;
1477 if (adv & ADVERTISED_1000baseT_Full)
1478 giga_ctrl |= ADVERTISE_1000FULL;
1479 } else if (adv & (ADVERTISED_1000baseT_Half |
1480 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1481 netif_info(tp, link, dev,
1482 "PHY does not support 1000Mbps\n");
54405cde 1483 goto out;
bcf0bf90 1484 }
1da177e4 1485
3577aa1b 1486 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1487
4da19633 1488 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1489 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1490 } else {
1491 giga_ctrl = 0;
1492
1493 if (speed == SPEED_10)
1494 bmcr = 0;
1495 else if (speed == SPEED_100)
1496 bmcr = BMCR_SPEED100;
1497 else
54405cde 1498 goto out;
3577aa1b 1499
1500 if (duplex == DUPLEX_FULL)
1501 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1502 }
1503
4da19633 1504 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1505
cecb5fd7
FR		 1506 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1507 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1508 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1509 rtl_writephy(tp, 0x17, 0x2138);
1510 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1511 } else {
4da19633 1512 rtl_writephy(tp, 0x17, 0x2108);
1513 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1514 }
1515 }
1516
54405cde
ON		 1517 rc = 0;
1518out:
1519 return rc;
1da177e4
LT		 1520}
1521
1522static int rtl8169_set_speed(struct net_device *dev,
54405cde 1523 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1524{
1525 struct rtl8169_private *tp = netdev_priv(dev);
1526 int ret;
1527
54405cde 1528 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1529 if (ret < 0)
1530 goto out;
1da177e4 1531
4876cc1e
FR		 1532 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1533 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1534 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1535 }
1536out:
1da177e4
LT		 1537 return ret;
1538}
1539
1540static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1541{
1542 struct rtl8169_private *tp = netdev_priv(dev);
1543 unsigned long flags;
1544 int ret;
1545
4876cc1e
FR		 1546 del_timer_sync(&tp->timer);
1547
1da177e4 1548 spin_lock_irqsave(&tp->lock, flags);
cecb5fd7 1549 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1550 cmd->duplex, cmd->advertising);
1da177e4 1551 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1552
1da177e4
LT		 1553 return ret;
1554}
1555
c8f44aff
MM		 1556static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1557 netdev_features_t features)
1da177e4 1558{
d58d46b5
FR		 1559 struct rtl8169_private *tp = netdev_priv(dev);
1560
2b7b4318 1561 if (dev->mtu > TD_MSS_MAX)
350fb32a 1562 features &= ~NETIF_F_ALL_TSO;
1da177e4 1563
d58d46b5
FR		 1564 if (dev->mtu > JUMBO_1K &&
1565 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1566 features &= ~NETIF_F_IP_CSUM;
1567
350fb32a 1568 return features;
1da177e4
LT		 1569}
1570
c8f44aff
MM		 1571static int rtl8169_set_features(struct net_device *dev,
1572 netdev_features_t features)
1da177e4
LT		 1573{
1574 struct rtl8169_private *tp = netdev_priv(dev);
1575 void __iomem *ioaddr = tp->mmio_addr;
1576 unsigned long flags;
1577
1578 spin_lock_irqsave(&tp->lock, flags);
1579
350fb32a 1580 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1581 tp->cp_cmd |= RxChkSum;
1582 else
1583 tp->cp_cmd &= ~RxChkSum;
1584
350fb32a
MM		 1585 if (dev->features & NETIF_F_HW_VLAN_RX)
1586 tp->cp_cmd |= RxVlan;
1587 else
1588 tp->cp_cmd &= ~RxVlan;
1589
1da177e4
LT		 1590 RTL_W16(CPlusCmd, tp->cp_cmd);
1591 RTL_R16(CPlusCmd);
1592
1593 spin_unlock_irqrestore(&tp->lock, flags);
1594
1595 return 0;
1596}
1597
1da177e4
LT		 1598static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1599 struct sk_buff *skb)
1600{
eab6d18d 1601 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1602 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1603}
1604
7a8fc77b 1605static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1606{
1607 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1608
7a8fc77b
FR		 1609 if (opts2 & RxVlanTag)
1610 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1611
1da177e4 1612 desc->opts2 = 0;
1da177e4
LT		 1613}
1614
ccdffb9a 1615static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1616{
1617 struct rtl8169_private *tp = netdev_priv(dev);
1618 void __iomem *ioaddr = tp->mmio_addr;
1619 u32 status;
1620
1621 cmd->supported =
1622 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1623 cmd->port = PORT_FIBRE;
1624 cmd->transceiver = XCVR_INTERNAL;
1625
1626 status = RTL_R32(TBICSR);
1627 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1628 cmd->autoneg = !!(status & TBINwEnable);
1629
70739497 1630 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1631 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1632
1633 return 0;
1da177e4
LT		 1634}
1635
ccdffb9a 1636static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1637{
1638 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1639
1640 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1641}
1642
1643static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1644{
1645 struct rtl8169_private *tp = netdev_priv(dev);
1646 unsigned long flags;
ccdffb9a 1647 int rc;
1da177e4
LT		 1648
1649 spin_lock_irqsave(&tp->lock, flags);
1650
ccdffb9a 1651 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1652
1653 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1654 return rc;
1da177e4
LT		 1655}
1656
1657static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1658 void *p)
1659{
5b0384f4
FR		 1660 struct rtl8169_private *tp = netdev_priv(dev);
1661 unsigned long flags;
1da177e4 1662
5b0384f4
FR		 1663 if (regs->len > R8169_REGS_SIZE)
1664 regs->len = R8169_REGS_SIZE;
1da177e4 1665
5b0384f4
FR		 1666 spin_lock_irqsave(&tp->lock, flags);
1667 memcpy_fromio(p, tp->mmio_addr, regs->len);
1668 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1669}
1670
b57b7e5a
SH		 1671static u32 rtl8169_get_msglevel(struct net_device *dev)
1672{
1673 struct rtl8169_private *tp = netdev_priv(dev);
1674
1675 return tp->msg_enable;
1676}
1677
1678static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1679{
1680 struct rtl8169_private *tp = netdev_priv(dev);
1681
1682 tp->msg_enable = value;
1683}
1684
d4a3a0fc
SH		 1685static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1686 "tx_packets",
1687 "rx_packets",
1688 "tx_errors",
1689 "rx_errors",
1690 "rx_missed",
1691 "align_errors",
1692 "tx_single_collisions",
1693 "tx_multi_collisions",
1694 "unicast",
1695 "broadcast",
1696 "multicast",
1697 "tx_aborted",
1698 "tx_underrun",
1699};
1700
b9f2c044 1701static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1702{
b9f2c044
JG		 1703 switch (sset) {
1704 case ETH_SS_STATS:
1705 return ARRAY_SIZE(rtl8169_gstrings);
1706 default:
1707 return -EOPNOTSUPP;
1708 }
d4a3a0fc
SH		 1709}
1710
355423d0 1711static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1712{
1713 struct rtl8169_private *tp = netdev_priv(dev);
1714 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1715 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1716 struct rtl8169_counters *counters;
1717 dma_addr_t paddr;
1718 u32 cmd;
355423d0 1719 int wait = 1000;
d4a3a0fc 1720
355423d0
IV		 1721 /*
1722 * Some chips are unable to dump tally counters when the receiver
1723 * is disabled.
1724 */
1725 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1726 return;
d4a3a0fc 1727
48addcc9 1728 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1729 if (!counters)
1730 return;
1731
1732 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1733 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1734 RTL_W32(CounterAddrLow, cmd);
1735 RTL_W32(CounterAddrLow, cmd | CounterDump);
1736
355423d0
IV		 1737 while (wait--) {
1738 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1739 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1740 break;
355423d0
IV		 1741 }
1742 udelay(10);
d4a3a0fc
SH		 1743 }
1744
1745 RTL_W32(CounterAddrLow, 0);
1746 RTL_W32(CounterAddrHigh, 0);
1747
48addcc9 1748 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1749}
1750
355423d0
IV		 1751static void rtl8169_get_ethtool_stats(struct net_device *dev,
1752 struct ethtool_stats *stats, u64 *data)
1753{
1754 struct rtl8169_private *tp = netdev_priv(dev);
1755
1756 ASSERT_RTNL();
1757
1758 rtl8169_update_counters(dev);
1759
1760 data[0] = le64_to_cpu(tp->counters.tx_packets);
1761 data[1] = le64_to_cpu(tp->counters.rx_packets);
1762 data[2] = le64_to_cpu(tp->counters.tx_errors);
1763 data[3] = le32_to_cpu(tp->counters.rx_errors);
1764 data[4] = le16_to_cpu(tp->counters.rx_missed);
1765 data[5] = le16_to_cpu(tp->counters.align_errors);
1766 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1767 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1768 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1769 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1770 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1771 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1772 data[12] = le16_to_cpu(tp->counters.tx_underun);
1773}
1774
d4a3a0fc
SH		 1775static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1776{
1777 switch(stringset) {
1778 case ETH_SS_STATS:
1779 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1780 break;
1781 }
1782}
1783
7282d491 1784static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1785 .get_drvinfo = rtl8169_get_drvinfo,
1786 .get_regs_len = rtl8169_get_regs_len,
1787 .get_link = ethtool_op_get_link,
1788 .get_settings = rtl8169_get_settings,
1789 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1790 .get_msglevel = rtl8169_get_msglevel,
1791 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1792 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1793 .get_wol = rtl8169_get_wol,
1794 .set_wol = rtl8169_set_wol,
d4a3a0fc 1795 .get_strings = rtl8169_get_strings,
b9f2c044 1796 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1797 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1798};
1799
07d3f51f 1800static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1801 struct net_device *dev, u8 default_version)
1da177e4 1802{
5d320a20 1803 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1804 /*
1805 * The driver currently handles the 8168Bf and the 8168Be identically
1806 * but they can be identified more specifically through the test below
1807 * if needed:
1808 *
1809 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1810 *
1811 * Same thing for the 8101Eb and the 8101Ec:
1812 *
1813 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1814 */
3744100e 1815 static const struct rtl_mac_info {
1da177e4 1816 u32 mask;
e3cf0cc0 1817 u32 val;
1da177e4
LT		 1818 int mac_version;
1819 } mac_info[] = {
c2218925
HW		 1820 /* 8168F family. */
1821 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1822 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1823
01dc7fec 1824 /* 8168E family. */
70090424 1825 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 1826 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1827 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1828 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1829
5b538df9 1830 /* 8168D family. */
daf9df6d 1831 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1832 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1833 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1834
e6de30d6 1835 /* 8168DP family. */
1836 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1837 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1838 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1839
ef808d50 1840 /* 8168C family. */
17c99297 1841 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1842 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1843 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1844 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1845 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1846 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1847 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1848 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1849 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1850
1851 /* 8168B family. */
1852 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1853 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1854 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1855 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1856
1857 /* 8101 family. */
36a0e6c2 1858 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1859 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1860 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1861 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1862 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1863 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1864 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1865 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1866 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1867 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1868 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1869 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1870 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1871 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1872 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1873 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1874 /* FIXME: where did these entries come from ? -- FR */
1875 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1876 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1877
1878 /* 8110 family. */
1879 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1880 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1881 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1882 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1883 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1884 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1885
f21b75e9
JD		 1886 /* Catch-all */
1887 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 1888 };
1889 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 1890 u32 reg;
1891
e3cf0cc0
FR		 1892 reg = RTL_R32(TxConfig);
1893 while ((reg & p->mask) != p->val)
1da177e4
LT		 1894 p++;
1895 tp->mac_version = p->mac_version;
5d320a20
FR		 1896
1897 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1898 netif_notice(tp, probe, dev,
1899 "unknown MAC, using family default\n");
1900 tp->mac_version = default_version;
1901 }
1da177e4
LT		 1902}
1903
1904static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1905{
bcf0bf90 1906 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1907}
1908
867763c1
FR		 1909struct phy_reg {
1910 u16 reg;
1911 u16 val;
1912};
1913
4da19633 1914static void rtl_writephy_batch(struct rtl8169_private *tp,
1915 const struct phy_reg *regs, int len)
867763c1
FR		 1916{
1917 while (len-- > 0) {
4da19633 1918 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1919 regs++;
1920 }
1921}
1922
bca03d5f 1923#define PHY_READ 0x00000000
1924#define PHY_DATA_OR 0x10000000
1925#define PHY_DATA_AND 0x20000000
1926#define PHY_BJMPN 0x30000000
1927#define PHY_READ_EFUSE 0x40000000
1928#define PHY_READ_MAC_BYTE 0x50000000
1929#define PHY_WRITE_MAC_BYTE 0x60000000
1930#define PHY_CLEAR_READCOUNT 0x70000000
1931#define PHY_WRITE 0x80000000
1932#define PHY_READCOUNT_EQ_SKIP 0x90000000
1933#define PHY_COMP_EQ_SKIPN 0xa0000000
1934#define PHY_COMP_NEQ_SKIPN 0xb0000000
1935#define PHY_WRITE_PREVIOUS 0xc0000000
1936#define PHY_SKIPN 0xd0000000
1937#define PHY_DELAY_MS 0xe0000000
1938#define PHY_WRITE_ERI_WORD 0xf0000000
1939
960aee6c
HW		 1940struct fw_info {
1941 u32 magic;
1942 char version[RTL_VER_SIZE];
1943 __le32 fw_start;
1944 __le32 fw_len;
1945 u8 chksum;
1946} __packed;
1947
1c361efb
FR		 1948#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1949
1950static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 1951{
b6ffd97f 1952 const struct firmware *fw = rtl_fw->fw;
960aee6c 1953 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 1954 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1955 char *version = rtl_fw->version;
1956 bool rc = false;
1957
1958 if (fw->size < FW_OPCODE_SIZE)
1959 goto out;
960aee6c
HW		 1960
1961 if (!fw_info->magic) {
1962 size_t i, size, start;
1963 u8 checksum = 0;
1964
1965 if (fw->size < sizeof(*fw_info))
1966 goto out;
1967
1968 for (i = 0; i < fw->size; i++)
1969 checksum += fw->data[i];
1970 if (checksum != 0)
1971 goto out;
1972
1973 start = le32_to_cpu(fw_info->fw_start);
1974 if (start > fw->size)
1975 goto out;
1976
1977 size = le32_to_cpu(fw_info->fw_len);
1978 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1979 goto out;
1980
1981 memcpy(version, fw_info->version, RTL_VER_SIZE);
1982
1983 pa->code = (__le32 *)(fw->data + start);
1984 pa->size = size;
1985 } else {
1c361efb
FR		 1986 if (fw->size % FW_OPCODE_SIZE)
1987 goto out;
1988
1989 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1990
1991 pa->code = (__le32 *)fw->data;
1992 pa->size = fw->size / FW_OPCODE_SIZE;
1993 }
1994 version[RTL_VER_SIZE - 1] = 0;
1995
1996 rc = true;
1997out:
1998 return rc;
1999}
2000
fd112f2e
FR		 2001static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2002 struct rtl_fw_phy_action *pa)
1c361efb 2003{
fd112f2e 2004 bool rc = false;
1c361efb 2005 size_t index;
bca03d5f 2006
1c361efb
FR		 2007 for (index = 0; index < pa->size; index++) {
2008 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2009 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2010
42b82dc1 2011 switch(action & 0xf0000000) {
2012 case PHY_READ:
2013 case PHY_DATA_OR:
2014 case PHY_DATA_AND:
2015 case PHY_READ_EFUSE:
2016 case PHY_CLEAR_READCOUNT:
2017 case PHY_WRITE:
2018 case PHY_WRITE_PREVIOUS:
2019 case PHY_DELAY_MS:
2020 break;
2021
2022 case PHY_BJMPN:
2023 if (regno > index) {
fd112f2e 2024 netif_err(tp, ifup, tp->dev,
cecb5fd7 2025 "Out of range of firmware\n");
fd112f2e 2026 goto out;
42b82dc1 2027 }
2028 break;
2029 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2030 if (index + 2 >= pa->size) {
fd112f2e 2031 netif_err(tp, ifup, tp->dev,
cecb5fd7 2032 "Out of range of firmware\n");
fd112f2e 2033 goto out;
42b82dc1 2034 }
2035 break;
2036 case PHY_COMP_EQ_SKIPN:
2037 case PHY_COMP_NEQ_SKIPN:
2038 case PHY_SKIPN:
1c361efb 2039 if (index + 1 + regno >= pa->size) {
fd112f2e 2040 netif_err(tp, ifup, tp->dev,
cecb5fd7 2041 "Out of range of firmware\n");
fd112f2e 2042 goto out;
42b82dc1 2043 }
bca03d5f 2044 break;
2045
42b82dc1 2046 case PHY_READ_MAC_BYTE:
2047 case PHY_WRITE_MAC_BYTE:
2048 case PHY_WRITE_ERI_WORD:
2049 default:
fd112f2e 2050 netif_err(tp, ifup, tp->dev,
42b82dc1 2051 "Invalid action 0x%08x\n", action);
fd112f2e 2052 goto out;
bca03d5f 2053 }
2054 }
fd112f2e
FR		 2055 rc = true;
2056out:
2057 return rc;
2058}
bca03d5f 2059
fd112f2e
FR		 2060static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2061{
2062 struct net_device *dev = tp->dev;
2063 int rc = -EINVAL;
2064
2065 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2066 netif_err(tp, ifup, dev, "invalid firwmare\n");
2067 goto out;
2068 }
2069
2070 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2071 rc = 0;
2072out:
2073 return rc;
2074}
2075
2076static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2077{
2078 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2079 u32 predata, count;
2080 size_t index;
2081
2082 predata = count = 0;
42b82dc1 2083
1c361efb
FR		 2084 for (index = 0; index < pa->size; ) {
2085 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2086 u32 data = action & 0x0000ffff;
42b82dc1 2087 u32 regno = (action & 0x0fff0000) >> 16;
2088
2089 if (!action)
2090 break;
bca03d5f 2091
2092 switch(action & 0xf0000000) {
42b82dc1 2093 case PHY_READ:
2094 predata = rtl_readphy(tp, regno);
2095 count++;
2096 index++;
2097 break;
2098 case PHY_DATA_OR:
2099 predata |= data;
2100 index++;
2101 break;
2102 case PHY_DATA_AND:
2103 predata &= data;
2104 index++;
2105 break;
2106 case PHY_BJMPN:
2107 index -= regno;
2108 break;
2109 case PHY_READ_EFUSE:
2110 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2111 index++;
2112 break;
2113 case PHY_CLEAR_READCOUNT:
2114 count = 0;
2115 index++;
2116 break;
bca03d5f 2117 case PHY_WRITE:
42b82dc1 2118 rtl_writephy(tp, regno, data);
2119 index++;
2120 break;
2121 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2122 index += (count == data) ? 2 : 1;
bca03d5f 2123 break;
42b82dc1 2124 case PHY_COMP_EQ_SKIPN:
2125 if (predata == data)
2126 index += regno;
2127 index++;
2128 break;
2129 case PHY_COMP_NEQ_SKIPN:
2130 if (predata != data)
2131 index += regno;
2132 index++;
2133 break;
2134 case PHY_WRITE_PREVIOUS:
2135 rtl_writephy(tp, regno, predata);
2136 index++;
2137 break;
2138 case PHY_SKIPN:
2139 index += regno + 1;
2140 break;
2141 case PHY_DELAY_MS:
2142 mdelay(data);
2143 index++;
2144 break;
2145
2146 case PHY_READ_MAC_BYTE:
2147 case PHY_WRITE_MAC_BYTE:
2148 case PHY_WRITE_ERI_WORD:
bca03d5f 2149 default:
2150 BUG();
2151 }
2152 }
2153}
2154
f1e02ed1 2155static void rtl_release_firmware(struct rtl8169_private *tp)
2156{
b6ffd97f
FR		 2157 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2158 release_firmware(tp->rtl_fw->fw);
2159 kfree(tp->rtl_fw);
2160 }
2161 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2162}
2163
953a12cc 2164static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2165{
b6ffd97f 2166 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2167
2168 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
b6ffd97f
FR		 2169 if (!IS_ERR_OR_NULL(rtl_fw))
2170 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2171}
2172
2173static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2174{
2175 if (rtl_readphy(tp, reg) != val)
2176 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2177 else
2178 rtl_apply_firmware(tp);
f1e02ed1 2179}
2180
4da19633 2181static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2182{
350f7596 2183 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2184 { 0x1f, 0x0001 },
2185 { 0x06, 0x006e },
2186 { 0x08, 0x0708 },
2187 { 0x15, 0x4000 },
2188 { 0x18, 0x65c7 },
1da177e4 2189
0b9b571d 2190 { 0x1f, 0x0001 },
2191 { 0x03, 0x00a1 },
2192 { 0x02, 0x0008 },
2193 { 0x01, 0x0120 },
2194 { 0x00, 0x1000 },
2195 { 0x04, 0x0800 },
2196 { 0x04, 0x0000 },
1da177e4 2197
0b9b571d 2198 { 0x03, 0xff41 },
2199 { 0x02, 0xdf60 },
2200 { 0x01, 0x0140 },
2201 { 0x00, 0x0077 },
2202 { 0x04, 0x7800 },
2203 { 0x04, 0x7000 },
2204
2205 { 0x03, 0x802f },
2206 { 0x02, 0x4f02 },
2207 { 0x01, 0x0409 },
2208 { 0x00, 0xf0f9 },
2209 { 0x04, 0x9800 },
2210 { 0x04, 0x9000 },
2211
2212 { 0x03, 0xdf01 },
2213 { 0x02, 0xdf20 },
2214 { 0x01, 0xff95 },
2215 { 0x00, 0xba00 },
2216 { 0x04, 0xa800 },
2217 { 0x04, 0xa000 },
2218
2219 { 0x03, 0xff41 },
2220 { 0x02, 0xdf20 },
2221 { 0x01, 0x0140 },
2222 { 0x00, 0x00bb },
2223 { 0x04, 0xb800 },
2224 { 0x04, 0xb000 },
2225
2226 { 0x03, 0xdf41 },
2227 { 0x02, 0xdc60 },
2228 { 0x01, 0x6340 },
2229 { 0x00, 0x007d },
2230 { 0x04, 0xd800 },
2231 { 0x04, 0xd000 },
2232
2233 { 0x03, 0xdf01 },
2234 { 0x02, 0xdf20 },
2235 { 0x01, 0x100a },
2236 { 0x00, 0xa0ff },
2237 { 0x04, 0xf800 },
2238 { 0x04, 0xf000 },
2239
2240 { 0x1f, 0x0000 },
2241 { 0x0b, 0x0000 },
2242 { 0x00, 0x9200 }
2243 };
1da177e4 2244
4da19633 2245 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2246}
2247
4da19633 2248static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2249{
350f7596 2250 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2251 { 0x1f, 0x0002 },
2252 { 0x01, 0x90d0 },
2253 { 0x1f, 0x0000 }
2254 };
2255
4da19633 2256 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2257}
2258
4da19633 2259static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2260{
2261 struct pci_dev *pdev = tp->pci_dev;
2e955856 2262
ccbae55e
SS		 2263 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2264 (pdev->subsystem_device != 0xe000))
2e955856 2265 return;
2266
4da19633 2267 rtl_writephy(tp, 0x1f, 0x0001);
2268 rtl_writephy(tp, 0x10, 0xf01b);
2269 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2270}
2271
4da19633 2272static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2273{
350f7596 2274 static const struct phy_reg phy_reg_init[] = {
2e955856 2275 { 0x1f, 0x0001 },
2276 { 0x04, 0x0000 },
2277 { 0x03, 0x00a1 },
2278 { 0x02, 0x0008 },
2279 { 0x01, 0x0120 },
2280 { 0x00, 0x1000 },
2281 { 0x04, 0x0800 },
2282 { 0x04, 0x9000 },
2283 { 0x03, 0x802f },
2284 { 0x02, 0x4f02 },
2285 { 0x01, 0x0409 },
2286 { 0x00, 0xf099 },
2287 { 0x04, 0x9800 },
2288 { 0x04, 0xa000 },
2289 { 0x03, 0xdf01 },
2290 { 0x02, 0xdf20 },
2291 { 0x01, 0xff95 },
2292 { 0x00, 0xba00 },
2293 { 0x04, 0xa800 },
2294 { 0x04, 0xf000 },
2295 { 0x03, 0xdf01 },
2296 { 0x02, 0xdf20 },
2297 { 0x01, 0x101a },
2298 { 0x00, 0xa0ff },
2299 { 0x04, 0xf800 },
2300 { 0x04, 0x0000 },
2301 { 0x1f, 0x0000 },
2302
2303 { 0x1f, 0x0001 },
2304 { 0x10, 0xf41b },
2305 { 0x14, 0xfb54 },
2306 { 0x18, 0xf5c7 },
2307 { 0x1f, 0x0000 },
2308
2309 { 0x1f, 0x0001 },
2310 { 0x17, 0x0cc0 },
2311 { 0x1f, 0x0000 }
2312 };
2313
4da19633 2314 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2315
4da19633 2316 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2317}
2318
4da19633 2319static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2320{
350f7596 2321 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2322 { 0x1f, 0x0001 },
2323 { 0x04, 0x0000 },
2324 { 0x03, 0x00a1 },
2325 { 0x02, 0x0008 },
2326 { 0x01, 0x0120 },
2327 { 0x00, 0x1000 },
2328 { 0x04, 0x0800 },
2329 { 0x04, 0x9000 },
2330 { 0x03, 0x802f },
2331 { 0x02, 0x4f02 },
2332 { 0x01, 0x0409 },
2333 { 0x00, 0xf099 },
2334 { 0x04, 0x9800 },
2335 { 0x04, 0xa000 },
2336 { 0x03, 0xdf01 },
2337 { 0x02, 0xdf20 },
2338 { 0x01, 0xff95 },
2339 { 0x00, 0xba00 },
2340 { 0x04, 0xa800 },
2341 { 0x04, 0xf000 },
2342 { 0x03, 0xdf01 },
2343 { 0x02, 0xdf20 },
2344 { 0x01, 0x101a },
2345 { 0x00, 0xa0ff },
2346 { 0x04, 0xf800 },
2347 { 0x04, 0x0000 },
2348 { 0x1f, 0x0000 },
2349
2350 { 0x1f, 0x0001 },
2351 { 0x0b, 0x8480 },
2352 { 0x1f, 0x0000 },
2353
2354 { 0x1f, 0x0001 },
2355 { 0x18, 0x67c7 },
2356 { 0x04, 0x2000 },
2357 { 0x03, 0x002f },
2358 { 0x02, 0x4360 },
2359 { 0x01, 0x0109 },
2360 { 0x00, 0x3022 },
2361 { 0x04, 0x2800 },
2362 { 0x1f, 0x0000 },
2363
2364 { 0x1f, 0x0001 },
2365 { 0x17, 0x0cc0 },
2366 { 0x1f, 0x0000 }
2367 };
2368
4da19633 2369 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2370}
2371
4da19633 2372static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2373{
350f7596 2374 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2375 { 0x10, 0xf41b },
2376 { 0x1f, 0x0000 }
2377 };
2378
4da19633 2379 rtl_writephy(tp, 0x1f, 0x0001);
2380 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2381
4da19633 2382 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2383}
2384
4da19633 2385static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2386{
350f7596 2387 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2388 { 0x1f, 0x0001 },
2389 { 0x10, 0xf41b },
2390 { 0x1f, 0x0000 }
2391 };
2392
4da19633 2393 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2394}
2395
4da19633 2396static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2397{
350f7596 2398 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2399 { 0x1f, 0x0000 },
2400 { 0x1d, 0x0f00 },
2401 { 0x1f, 0x0002 },
2402 { 0x0c, 0x1ec8 },
2403 { 0x1f, 0x0000 }
2404 };
2405
4da19633 2406 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2407}
2408
4da19633 2409static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2410{
350f7596 2411 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2412 { 0x1f, 0x0001 },
2413 { 0x1d, 0x3d98 },
2414 { 0x1f, 0x0000 }
2415 };
2416
4da19633 2417 rtl_writephy(tp, 0x1f, 0x0000);
2418 rtl_patchphy(tp, 0x14, 1 << 5);
2419 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2420
4da19633 2421 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2422}
2423
4da19633 2424static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2425{
350f7596 2426 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2427 { 0x1f, 0x0001 },
2428 { 0x12, 0x2300 },
867763c1
FR		 2429 { 0x1f, 0x0002 },
2430 { 0x00, 0x88d4 },
2431 { 0x01, 0x82b1 },
2432 { 0x03, 0x7002 },
2433 { 0x08, 0x9e30 },
2434 { 0x09, 0x01f0 },
2435 { 0x0a, 0x5500 },
2436 { 0x0c, 0x00c8 },
2437 { 0x1f, 0x0003 },
2438 { 0x12, 0xc096 },
2439 { 0x16, 0x000a },
f50d4275
FR		 2440 { 0x1f, 0x0000 },
2441 { 0x1f, 0x0000 },
2442 { 0x09, 0x2000 },
2443 { 0x09, 0x0000 }
867763c1
FR		 2444 };
2445
4da19633 2446 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2447
4da19633 2448 rtl_patchphy(tp, 0x14, 1 << 5);
2449 rtl_patchphy(tp, 0x0d, 1 << 5);
2450 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2451}
2452
4da19633 2453static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2454{
350f7596 2455 static const struct phy_reg phy_reg_init[] = {
f50d4275 2456 { 0x1f, 0x0001 },
7da97ec9 2457 { 0x12, 0x2300 },
f50d4275
FR		 2458 { 0x03, 0x802f },
2459 { 0x02, 0x4f02 },
2460 { 0x01, 0x0409 },
2461 { 0x00, 0xf099 },
2462 { 0x04, 0x9800 },
2463 { 0x04, 0x9000 },
2464 { 0x1d, 0x3d98 },
7da97ec9
FR		 2465 { 0x1f, 0x0002 },
2466 { 0x0c, 0x7eb8 },
f50d4275
FR		 2467 { 0x06, 0x0761 },
2468 { 0x1f, 0x0003 },
2469 { 0x16, 0x0f0a },
7da97ec9
FR		 2470 { 0x1f, 0x0000 }
2471 };
2472
4da19633 2473 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2474
4da19633 2475 rtl_patchphy(tp, 0x16, 1 << 0);
2476 rtl_patchphy(tp, 0x14, 1 << 5);
2477 rtl_patchphy(tp, 0x0d, 1 << 5);
2478 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2479}
2480
4da19633 2481static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2482{
350f7596 2483 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2484 { 0x1f, 0x0001 },
2485 { 0x12, 0x2300 },
2486 { 0x1d, 0x3d98 },
2487 { 0x1f, 0x0002 },
2488 { 0x0c, 0x7eb8 },
2489 { 0x06, 0x5461 },
2490 { 0x1f, 0x0003 },
2491 { 0x16, 0x0f0a },
2492 { 0x1f, 0x0000 }
2493 };
2494
4da19633 2495 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2496
4da19633 2497 rtl_patchphy(tp, 0x16, 1 << 0);
2498 rtl_patchphy(tp, 0x14, 1 << 5);
2499 rtl_patchphy(tp, 0x0d, 1 << 5);
2500 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2501}
2502
4da19633 2503static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2504{
4da19633 2505 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2506}
2507
bca03d5f 2508static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2509{
350f7596 2510 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2511 /* Channel Estimation */
5b538df9 2512 { 0x1f, 0x0001 },
daf9df6d 2513 { 0x06, 0x4064 },
2514 { 0x07, 0x2863 },
2515 { 0x08, 0x059c },
2516 { 0x09, 0x26b4 },
2517 { 0x0a, 0x6a19 },
2518 { 0x0b, 0xdcc8 },
2519 { 0x10, 0xf06d },
2520 { 0x14, 0x7f68 },
2521 { 0x18, 0x7fd9 },
2522 { 0x1c, 0xf0ff },
2523 { 0x1d, 0x3d9c },
5b538df9 2524 { 0x1f, 0x0003 },
daf9df6d 2525 { 0x12, 0xf49f },
2526 { 0x13, 0x070b },
2527 { 0x1a, 0x05ad },
bca03d5f 2528 { 0x14, 0x94c0 },
2529
2530 /*
2531 * Tx Error Issue
cecb5fd7 2532 * Enhance line driver power
bca03d5f 2533 */
5b538df9 2534 { 0x1f, 0x0002 },
daf9df6d 2535 { 0x06, 0x5561 },
2536 { 0x1f, 0x0005 },
2537 { 0x05, 0x8332 },
bca03d5f 2538 { 0x06, 0x5561 },
2539
2540 /*
2541 * Can not link to 1Gbps with bad cable
2542 * Decrease SNR threshold form 21.07dB to 19.04dB
2543 */
2544 { 0x1f, 0x0001 },
2545 { 0x17, 0x0cc0 },
daf9df6d 2546
5b538df9 2547 { 0x1f, 0x0000 },
bca03d5f 2548 { 0x0d, 0xf880 }
daf9df6d 2549 };
bca03d5f 2550 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2551
4da19633 2552 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2553
bca03d5f 2554 /*
2555 * Rx Error Issue
2556 * Fine Tune Switching regulator parameter
2557 */
4da19633 2558 rtl_writephy(tp, 0x1f, 0x0002);
2559 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2560 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2561
daf9df6d 2562 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2563 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2564 { 0x1f, 0x0002 },
2565 { 0x05, 0x669a },
2566 { 0x1f, 0x0005 },
2567 { 0x05, 0x8330 },
2568 { 0x06, 0x669a },
2569 { 0x1f, 0x0002 }
2570 };
2571 int val;
2572
4da19633 2573 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2574
4da19633 2575 val = rtl_readphy(tp, 0x0d);
daf9df6d 2576
2577 if ((val & 0x00ff) != 0x006c) {
350f7596 2578 static const u32 set[] = {
daf9df6d 2579 0x0065, 0x0066, 0x0067, 0x0068,
2580 0x0069, 0x006a, 0x006b, 0x006c
2581 };
2582 int i;
2583
4da19633 2584 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2585
2586 val &= 0xff00;
2587 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2588 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2589 }
2590 } else {
350f7596 2591 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2592 { 0x1f, 0x0002 },
2593 { 0x05, 0x6662 },
2594 { 0x1f, 0x0005 },
2595 { 0x05, 0x8330 },
2596 { 0x06, 0x6662 }
2597 };
2598
4da19633 2599 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2600 }
2601
bca03d5f 2602 /* RSET couple improve */
4da19633 2603 rtl_writephy(tp, 0x1f, 0x0002);
2604 rtl_patchphy(tp, 0x0d, 0x0300);
2605 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2606
bca03d5f 2607 /* Fine tune PLL performance */
4da19633 2608 rtl_writephy(tp, 0x1f, 0x0002);
2609 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2610 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2611
4da19633 2612 rtl_writephy(tp, 0x1f, 0x0005);
2613 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2614
2615 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2616
4da19633 2617 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2618}
2619
bca03d5f 2620static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2621{
350f7596 2622 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2623 /* Channel Estimation */
daf9df6d 2624 { 0x1f, 0x0001 },
2625 { 0x06, 0x4064 },
2626 { 0x07, 0x2863 },
2627 { 0x08, 0x059c },
2628 { 0x09, 0x26b4 },
2629 { 0x0a, 0x6a19 },
2630 { 0x0b, 0xdcc8 },
2631 { 0x10, 0xf06d },
2632 { 0x14, 0x7f68 },
2633 { 0x18, 0x7fd9 },
2634 { 0x1c, 0xf0ff },
2635 { 0x1d, 0x3d9c },
2636 { 0x1f, 0x0003 },
2637 { 0x12, 0xf49f },
2638 { 0x13, 0x070b },
2639 { 0x1a, 0x05ad },
2640 { 0x14, 0x94c0 },
2641
bca03d5f 2642 /*
2643 * Tx Error Issue
cecb5fd7 2644 * Enhance line driver power
bca03d5f 2645 */
daf9df6d 2646 { 0x1f, 0x0002 },
2647 { 0x06, 0x5561 },
2648 { 0x1f, 0x0005 },
2649 { 0x05, 0x8332 },
bca03d5f 2650 { 0x06, 0x5561 },
2651
2652 /*
2653 * Can not link to 1Gbps with bad cable
2654 * Decrease SNR threshold form 21.07dB to 19.04dB
2655 */
2656 { 0x1f, 0x0001 },
2657 { 0x17, 0x0cc0 },
daf9df6d 2658
2659 { 0x1f, 0x0000 },
bca03d5f 2660 { 0x0d, 0xf880 }
5b538df9 2661 };
bca03d5f 2662 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2663
4da19633 2664 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2665
daf9df6d 2666 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2667 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2668 { 0x1f, 0x0002 },
2669 { 0x05, 0x669a },
5b538df9 2670 { 0x1f, 0x0005 },
daf9df6d 2671 { 0x05, 0x8330 },
2672 { 0x06, 0x669a },
2673
2674 { 0x1f, 0x0002 }
2675 };
2676 int val;
2677
4da19633 2678 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2679
4da19633 2680 val = rtl_readphy(tp, 0x0d);
daf9df6d 2681 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2682 static const u32 set[] = {
daf9df6d 2683 0x0065, 0x0066, 0x0067, 0x0068,
2684 0x0069, 0x006a, 0x006b, 0x006c
2685 };
2686 int i;
2687
4da19633 2688 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2689
2690 val &= 0xff00;
2691 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2692 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2693 }
2694 } else {
350f7596 2695 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2696 { 0x1f, 0x0002 },
2697 { 0x05, 0x2642 },
5b538df9 2698 { 0x1f, 0x0005 },
daf9df6d 2699 { 0x05, 0x8330 },
2700 { 0x06, 0x2642 }
5b538df9
FR		 2701 };
2702
4da19633 2703 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2704 }
2705
bca03d5f 2706 /* Fine tune PLL performance */
4da19633 2707 rtl_writephy(tp, 0x1f, 0x0002);
2708 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2709 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2710
bca03d5f 2711 /* Switching regulator Slew rate */
4da19633 2712 rtl_writephy(tp, 0x1f, 0x0002);
2713 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2714
4da19633 2715 rtl_writephy(tp, 0x1f, 0x0005);
2716 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2717
2718 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2719
4da19633 2720 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2721}
2722
4da19633 2723static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2724{
350f7596 2725 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2726 { 0x1f, 0x0002 },
2727 { 0x10, 0x0008 },
2728 { 0x0d, 0x006c },
2729
2730 { 0x1f, 0x0000 },
2731 { 0x0d, 0xf880 },
2732
2733 { 0x1f, 0x0001 },
2734 { 0x17, 0x0cc0 },
2735
2736 { 0x1f, 0x0001 },
2737 { 0x0b, 0xa4d8 },
2738 { 0x09, 0x281c },
2739 { 0x07, 0x2883 },
2740 { 0x0a, 0x6b35 },
2741 { 0x1d, 0x3da4 },
2742 { 0x1c, 0xeffd },
2743 { 0x14, 0x7f52 },
2744 { 0x18, 0x7fc6 },
2745 { 0x08, 0x0601 },
2746 { 0x06, 0x4063 },
2747 { 0x10, 0xf074 },
2748 { 0x1f, 0x0003 },
2749 { 0x13, 0x0789 },
2750 { 0x12, 0xf4bd },
2751 { 0x1a, 0x04fd },
2752 { 0x14, 0x84b0 },
2753 { 0x1f, 0x0000 },
2754 { 0x00, 0x9200 },
2755
2756 { 0x1f, 0x0005 },
2757 { 0x01, 0x0340 },
2758 { 0x1f, 0x0001 },
2759 { 0x04, 0x4000 },
2760 { 0x03, 0x1d21 },
2761 { 0x02, 0x0c32 },
2762 { 0x01, 0x0200 },
2763 { 0x00, 0x5554 },
2764 { 0x04, 0x4800 },
2765 { 0x04, 0x4000 },
2766 { 0x04, 0xf000 },
2767 { 0x03, 0xdf01 },
2768 { 0x02, 0xdf20 },
2769 { 0x01, 0x101a },
2770 { 0x00, 0xa0ff },
2771 { 0x04, 0xf800 },
2772 { 0x04, 0xf000 },
2773 { 0x1f, 0x0000 },
2774
2775 { 0x1f, 0x0007 },
2776 { 0x1e, 0x0023 },
2777 { 0x16, 0x0000 },
2778 { 0x1f, 0x0000 }
2779 };
2780
4da19633 2781 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2782}
2783
e6de30d6 2784static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2785{
2786 static const struct phy_reg phy_reg_init[] = {
2787 { 0x1f, 0x0001 },
2788 { 0x17, 0x0cc0 },
2789
2790 { 0x1f, 0x0007 },
2791 { 0x1e, 0x002d },
2792 { 0x18, 0x0040 },
2793 { 0x1f, 0x0000 }
2794 };
2795
2796 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2797 rtl_patchphy(tp, 0x0d, 1 << 5);
2798}
2799
70090424 2800static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 2801{
2802 static const struct phy_reg phy_reg_init[] = {
2803 /* Enable Delay cap */
2804 { 0x1f, 0x0005 },
2805 { 0x05, 0x8b80 },
2806 { 0x06, 0xc896 },
2807 { 0x1f, 0x0000 },
2808
2809 /* Channel estimation fine tune */
2810 { 0x1f, 0x0001 },
2811 { 0x0b, 0x6c20 },
2812 { 0x07, 0x2872 },
2813 { 0x1c, 0xefff },
2814 { 0x1f, 0x0003 },
2815 { 0x14, 0x6420 },
2816 { 0x1f, 0x0000 },
2817
2818 /* Update PFM & 10M TX idle timer */
2819 { 0x1f, 0x0007 },
2820 { 0x1e, 0x002f },
2821 { 0x15, 0x1919 },
2822 { 0x1f, 0x0000 },
2823
2824 { 0x1f, 0x0007 },
2825 { 0x1e, 0x00ac },
2826 { 0x18, 0x0006 },
2827 { 0x1f, 0x0000 }
2828 };
2829
15ecd039
FR		 2830 rtl_apply_firmware(tp);
2831
01dc7fec 2832 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2833
2834 /* DCO enable for 10M IDLE Power */
2835 rtl_writephy(tp, 0x1f, 0x0007);
2836 rtl_writephy(tp, 0x1e, 0x0023);
2837 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2838 rtl_writephy(tp, 0x1f, 0x0000);
2839
2840 /* For impedance matching */
2841 rtl_writephy(tp, 0x1f, 0x0002);
2842 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2843 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2844
2845 /* PHY auto speed down */
2846 rtl_writephy(tp, 0x1f, 0x0007);
2847 rtl_writephy(tp, 0x1e, 0x002d);
2848 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2849 rtl_writephy(tp, 0x1f, 0x0000);
2850 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2851
2852 rtl_writephy(tp, 0x1f, 0x0005);
2853 rtl_writephy(tp, 0x05, 0x8b86);
2854 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2855 rtl_writephy(tp, 0x1f, 0x0000);
2856
2857 rtl_writephy(tp, 0x1f, 0x0005);
2858 rtl_writephy(tp, 0x05, 0x8b85);
2859 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2860 rtl_writephy(tp, 0x1f, 0x0007);
2861 rtl_writephy(tp, 0x1e, 0x0020);
2862 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2863 rtl_writephy(tp, 0x1f, 0x0006);
2864 rtl_writephy(tp, 0x00, 0x5a00);
2865 rtl_writephy(tp, 0x1f, 0x0000);
2866 rtl_writephy(tp, 0x0d, 0x0007);
2867 rtl_writephy(tp, 0x0e, 0x003c);
2868 rtl_writephy(tp, 0x0d, 0x4007);
2869 rtl_writephy(tp, 0x0e, 0x0000);
2870 rtl_writephy(tp, 0x0d, 0x0000);
2871}
2872
70090424
HW		 2873static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2874{
2875 static const struct phy_reg phy_reg_init[] = {
2876 /* Enable Delay cap */
2877 { 0x1f, 0x0004 },
2878 { 0x1f, 0x0007 },
2879 { 0x1e, 0x00ac },
2880 { 0x18, 0x0006 },
2881 { 0x1f, 0x0002 },
2882 { 0x1f, 0x0000 },
2883 { 0x1f, 0x0000 },
2884
2885 /* Channel estimation fine tune */
2886 { 0x1f, 0x0003 },
2887 { 0x09, 0xa20f },
2888 { 0x1f, 0x0000 },
2889 { 0x1f, 0x0000 },
2890
2891 /* Green Setting */
2892 { 0x1f, 0x0005 },
2893 { 0x05, 0x8b5b },
2894 { 0x06, 0x9222 },
2895 { 0x05, 0x8b6d },
2896 { 0x06, 0x8000 },
2897 { 0x05, 0x8b76 },
2898 { 0x06, 0x8000 },
2899 { 0x1f, 0x0000 }
2900 };
2901
2902 rtl_apply_firmware(tp);
2903
2904 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2905
2906 /* For 4-corner performance improve */
2907 rtl_writephy(tp, 0x1f, 0x0005);
2908 rtl_writephy(tp, 0x05, 0x8b80);
2909 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2910 rtl_writephy(tp, 0x1f, 0x0000);
2911
2912 /* PHY auto speed down */
2913 rtl_writephy(tp, 0x1f, 0x0004);
2914 rtl_writephy(tp, 0x1f, 0x0007);
2915 rtl_writephy(tp, 0x1e, 0x002d);
2916 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2917 rtl_writephy(tp, 0x1f, 0x0002);
2918 rtl_writephy(tp, 0x1f, 0x0000);
2919 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2920
2921 /* improve 10M EEE waveform */
2922 rtl_writephy(tp, 0x1f, 0x0005);
2923 rtl_writephy(tp, 0x05, 0x8b86);
2924 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2925 rtl_writephy(tp, 0x1f, 0x0000);
2926
2927 /* Improve 2-pair detection performance */
2928 rtl_writephy(tp, 0x1f, 0x0005);
2929 rtl_writephy(tp, 0x05, 0x8b85);
2930 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2931 rtl_writephy(tp, 0x1f, 0x0000);
2932
2933 /* EEE setting */
2934 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2935 ERIAR_EXGMAC);
2936 rtl_writephy(tp, 0x1f, 0x0005);
2937 rtl_writephy(tp, 0x05, 0x8b85);
2938 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2939 rtl_writephy(tp, 0x1f, 0x0004);
2940 rtl_writephy(tp, 0x1f, 0x0007);
2941 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 2942 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 2943 rtl_writephy(tp, 0x1f, 0x0002);
2944 rtl_writephy(tp, 0x1f, 0x0000);
2945 rtl_writephy(tp, 0x0d, 0x0007);
2946 rtl_writephy(tp, 0x0e, 0x003c);
2947 rtl_writephy(tp, 0x0d, 0x4007);
2948 rtl_writephy(tp, 0x0e, 0x0000);
2949 rtl_writephy(tp, 0x0d, 0x0000);
2950
2951 /* Green feature */
2952 rtl_writephy(tp, 0x1f, 0x0003);
2953 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2954 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2955 rtl_writephy(tp, 0x1f, 0x0000);
2956}
2957
c2218925
HW		 2958static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
2959{
2960 static const struct phy_reg phy_reg_init[] = {
2961 /* Channel estimation fine tune */
2962 { 0x1f, 0x0003 },
2963 { 0x09, 0xa20f },
2964 { 0x1f, 0x0000 },
2965
2966 /* Modify green table for giga & fnet */
2967 { 0x1f, 0x0005 },
2968 { 0x05, 0x8b55 },
2969 { 0x06, 0x0000 },
2970 { 0x05, 0x8b5e },
2971 { 0x06, 0x0000 },
2972 { 0x05, 0x8b67 },
2973 { 0x06, 0x0000 },
2974 { 0x05, 0x8b70 },
2975 { 0x06, 0x0000 },
2976 { 0x1f, 0x0000 },
2977 { 0x1f, 0x0007 },
2978 { 0x1e, 0x0078 },
2979 { 0x17, 0x0000 },
2980 { 0x19, 0x00fb },
2981 { 0x1f, 0x0000 },
2982
2983 /* Modify green table for 10M */
2984 { 0x1f, 0x0005 },
2985 { 0x05, 0x8b79 },
2986 { 0x06, 0xaa00 },
2987 { 0x1f, 0x0000 },
2988
2989 /* Disable hiimpedance detection (RTCT) */
2990 { 0x1f, 0x0003 },
2991 { 0x01, 0x328a },
2992 { 0x1f, 0x0000 }
2993 };
2994
2995 rtl_apply_firmware(tp);
2996
2997 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2998
2999 /* For 4-corner performance improve */
3000 rtl_writephy(tp, 0x1f, 0x0005);
3001 rtl_writephy(tp, 0x05, 0x8b80);
3002 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3003 rtl_writephy(tp, 0x1f, 0x0000);
3004
3005 /* PHY auto speed down */
3006 rtl_writephy(tp, 0x1f, 0x0007);
3007 rtl_writephy(tp, 0x1e, 0x002d);
3008 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3009 rtl_writephy(tp, 0x1f, 0x0000);
3010 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3011
3012 /* Improve 10M EEE waveform */
3013 rtl_writephy(tp, 0x1f, 0x0005);
3014 rtl_writephy(tp, 0x05, 0x8b86);
3015 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3016 rtl_writephy(tp, 0x1f, 0x0000);
3017
3018 /* Improve 2-pair detection performance */
3019 rtl_writephy(tp, 0x1f, 0x0005);
3020 rtl_writephy(tp, 0x05, 0x8b85);
3021 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3022 rtl_writephy(tp, 0x1f, 0x0000);
3023}
3024
3025static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3026{
3027 rtl_apply_firmware(tp);
3028
3029 /* For 4-corner performance improve */
3030 rtl_writephy(tp, 0x1f, 0x0005);
3031 rtl_writephy(tp, 0x05, 0x8b80);
3032 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3033 rtl_writephy(tp, 0x1f, 0x0000);
3034
3035 /* PHY auto speed down */
3036 rtl_writephy(tp, 0x1f, 0x0007);
3037 rtl_writephy(tp, 0x1e, 0x002d);
3038 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3039 rtl_writephy(tp, 0x1f, 0x0000);
3040 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3041
3042 /* Improve 10M EEE waveform */
3043 rtl_writephy(tp, 0x1f, 0x0005);
3044 rtl_writephy(tp, 0x05, 0x8b86);
3045 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3046 rtl_writephy(tp, 0x1f, 0x0000);
3047}
3048
4da19633 3049static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3050{
350f7596 3051 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3052 { 0x1f, 0x0003 },
3053 { 0x08, 0x441d },
3054 { 0x01, 0x9100 },
3055 { 0x1f, 0x0000 }
3056 };
3057
4da19633 3058 rtl_writephy(tp, 0x1f, 0x0000);
3059 rtl_patchphy(tp, 0x11, 1 << 12);
3060 rtl_patchphy(tp, 0x19, 1 << 13);
3061 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3062
4da19633 3063 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3064}
3065
5a5e4443
HW		 3066static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3067{
3068 static const struct phy_reg phy_reg_init[] = {
3069 { 0x1f, 0x0005 },
3070 { 0x1a, 0x0000 },
3071 { 0x1f, 0x0000 },
3072
3073 { 0x1f, 0x0004 },
3074 { 0x1c, 0x0000 },
3075 { 0x1f, 0x0000 },
3076
3077 { 0x1f, 0x0001 },
3078 { 0x15, 0x7701 },
3079 { 0x1f, 0x0000 }
3080 };
3081
3082 /* Disable ALDPS before ram code */
3083 rtl_writephy(tp, 0x1f, 0x0000);
3084 rtl_writephy(tp, 0x18, 0x0310);
3085 msleep(100);
3086
953a12cc 3087 rtl_apply_firmware(tp);
5a5e4443
HW		 3088
3089 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3090}
3091
5615d9f1
FR		 3092static void rtl_hw_phy_config(struct net_device *dev)
3093{
3094 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3095
3096 rtl8169_print_mac_version(tp);
3097
3098 switch (tp->mac_version) {
3099 case RTL_GIGA_MAC_VER_01:
3100 break;
3101 case RTL_GIGA_MAC_VER_02:
3102 case RTL_GIGA_MAC_VER_03:
4da19633 3103 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3104 break;
3105 case RTL_GIGA_MAC_VER_04:
4da19633 3106 rtl8169sb_hw_phy_config(tp);
5615d9f1 3107 break;
2e955856 3108 case RTL_GIGA_MAC_VER_05:
4da19633 3109 rtl8169scd_hw_phy_config(tp);
2e955856 3110 break;
8c7006aa 3111 case RTL_GIGA_MAC_VER_06:
4da19633 3112 rtl8169sce_hw_phy_config(tp);
8c7006aa 3113 break;
2857ffb7
FR		 3114 case RTL_GIGA_MAC_VER_07:
3115 case RTL_GIGA_MAC_VER_08:
3116 case RTL_GIGA_MAC_VER_09:
4da19633 3117 rtl8102e_hw_phy_config(tp);
2857ffb7 3118 break;
236b8082 3119 case RTL_GIGA_MAC_VER_11:
4da19633 3120 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3121 break;
3122 case RTL_GIGA_MAC_VER_12:
4da19633 3123 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3124 break;
3125 case RTL_GIGA_MAC_VER_17:
4da19633 3126 rtl8168bef_hw_phy_config(tp);
236b8082 3127 break;
867763c1 3128 case RTL_GIGA_MAC_VER_18:
4da19633 3129 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3130 break;
3131 case RTL_GIGA_MAC_VER_19:
4da19633 3132 rtl8168c_1_hw_phy_config(tp);
867763c1 3133 break;
7da97ec9 3134 case RTL_GIGA_MAC_VER_20:
4da19633 3135 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3136 break;
197ff761 3137 case RTL_GIGA_MAC_VER_21:
4da19633 3138 rtl8168c_3_hw_phy_config(tp);
197ff761 3139 break;
6fb07058 3140 case RTL_GIGA_MAC_VER_22:
4da19633 3141 rtl8168c_4_hw_phy_config(tp);
6fb07058 3142 break;
ef3386f0 3143 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3144 case RTL_GIGA_MAC_VER_24:
4da19633 3145 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3146 break;
5b538df9 3147 case RTL_GIGA_MAC_VER_25:
bca03d5f 3148 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3149 break;
3150 case RTL_GIGA_MAC_VER_26:
bca03d5f 3151 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3152 break;
3153 case RTL_GIGA_MAC_VER_27:
4da19633 3154 rtl8168d_3_hw_phy_config(tp);
5b538df9 3155 break;
e6de30d6 3156 case RTL_GIGA_MAC_VER_28:
3157 rtl8168d_4_hw_phy_config(tp);
3158 break;
5a5e4443
HW		 3159 case RTL_GIGA_MAC_VER_29:
3160 case RTL_GIGA_MAC_VER_30:
3161 rtl8105e_hw_phy_config(tp);
3162 break;
cecb5fd7
FR		 3163 case RTL_GIGA_MAC_VER_31:
3164 /* None. */
3165 break;
01dc7fec 3166 case RTL_GIGA_MAC_VER_32:
01dc7fec 3167 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3168 rtl8168e_1_hw_phy_config(tp);
3169 break;
3170 case RTL_GIGA_MAC_VER_34:
3171 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3172 break;
c2218925
HW		 3173 case RTL_GIGA_MAC_VER_35:
3174 rtl8168f_1_hw_phy_config(tp);
3175 break;
3176 case RTL_GIGA_MAC_VER_36:
3177 rtl8168f_2_hw_phy_config(tp);
3178 break;
ef3386f0 3179
5615d9f1
FR		 3180 default:
3181 break;
3182 }
3183}
3184
1da177e4
LT		 3185static void rtl8169_phy_timer(unsigned long __opaque)
3186{
3187 struct net_device *dev = (struct net_device *)__opaque;
3188 struct rtl8169_private *tp = netdev_priv(dev);
3189 struct timer_list *timer = &tp->timer;
3190 void __iomem *ioaddr = tp->mmio_addr;
3191 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3192
bcf0bf90 3193 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3194
1da177e4
LT		 3195 spin_lock_irq(&tp->lock);
3196
4da19633 3197 if (tp->phy_reset_pending(tp)) {
5b0384f4 3198 /*
1da177e4
LT		 3199 * A busy loop could burn quite a few cycles on nowadays CPU.
3200 * Let's delay the execution of the timer for a few ticks.
3201 */
3202 timeout = HZ/10;
3203 goto out_mod_timer;
3204 }
3205
3206 if (tp->link_ok(ioaddr))
3207 goto out_unlock;
3208
bf82c189 3209 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 3210
4da19633 3211 tp->phy_reset_enable(tp);
1da177e4
LT		 3212
3213out_mod_timer:
3214 mod_timer(timer, jiffies + timeout);
3215out_unlock:
3216 spin_unlock_irq(&tp->lock);
3217}
3218
1da177e4
LT		 3219#ifdef CONFIG_NET_POLL_CONTROLLER
3220/*
3221 * Polling 'interrupt' - used by things like netconsole to send skbs
3222 * without having to re-enable interrupts. It's not called while
3223 * the interrupt routine is executing.
3224 */
3225static void rtl8169_netpoll(struct net_device *dev)
3226{
3227 struct rtl8169_private *tp = netdev_priv(dev);
3228 struct pci_dev *pdev = tp->pci_dev;
3229
3230 disable_irq(pdev->irq);
7d12e780 3231 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 3232 enable_irq(pdev->irq);
3233}
3234#endif
3235
3236static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3237 void __iomem *ioaddr)
3238{
3239 iounmap(ioaddr);
3240 pci_release_regions(pdev);
87aeec76 3241 pci_clear_mwi(pdev);
1da177e4
LT		 3242 pci_disable_device(pdev);
3243 free_netdev(dev);
3244}
3245
bf793295
FR		 3246static void rtl8169_phy_reset(struct net_device *dev,
3247 struct rtl8169_private *tp)
3248{
07d3f51f 3249 unsigned int i;
bf793295 3250
4da19633 3251 tp->phy_reset_enable(tp);
bf793295 3252 for (i = 0; i < 100; i++) {
4da19633 3253 if (!tp->phy_reset_pending(tp))
bf793295
FR		 3254 return;
3255 msleep(1);
3256 }
bf82c189 3257 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 3258}
3259
2544bfc0
FR		 3260static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3261{
3262 void __iomem *ioaddr = tp->mmio_addr;
3263
3264 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3265 (RTL_R8(PHYstatus) & TBI_Enable);
3266}
3267
4ff96fa6
FR		 3268static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3269{
3270 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3271
5615d9f1 3272 rtl_hw_phy_config(dev);
4ff96fa6 3273
77332894
MS		 3274 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3275 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3276 RTL_W8(0x82, 0x01);
3277 }
4ff96fa6 3278
6dccd16b
FR		 3279 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3280
3281 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3282 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3283
bcf0bf90 3284 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3285 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3286 RTL_W8(0x82, 0x01);
3287 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3288 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3289 }
3290
bf793295
FR		 3291 rtl8169_phy_reset(dev, tp);
3292
54405cde 3293 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3294 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3295 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3296 (tp->mii.supports_gmii ?
3297 ADVERTISED_1000baseT_Half |
3298 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3299
2544bfc0 3300 if (rtl_tbi_enabled(tp))
bf82c189 3301 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3302}
3303
773d2021
FR		 3304static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3305{
3306 void __iomem *ioaddr = tp->mmio_addr;
3307 u32 high;
3308 u32 low;
3309
3310 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3311 high = addr[4] | (addr[5] << 8);
3312
3313 spin_lock_irq(&tp->lock);
3314
3315 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3316
773d2021 3317 RTL_W32(MAC4, high);
908ba2bf 3318 RTL_R32(MAC4);
3319
78f1cd02 3320 RTL_W32(MAC0, low);
908ba2bf 3321 RTL_R32(MAC0);
3322
c28aa385 3323 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3324 const struct exgmac_reg e[] = {
3325 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3326 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3327 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3328 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3329 low >> 16 },
3330 };
3331
3332 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3333 }
3334
773d2021
FR		 3335 RTL_W8(Cfg9346, Cfg9346_Lock);
3336
3337 spin_unlock_irq(&tp->lock);
3338}
3339
3340static int rtl_set_mac_address(struct net_device *dev, void *p)
3341{
3342 struct rtl8169_private *tp = netdev_priv(dev);
3343 struct sockaddr *addr = p;
3344
3345 if (!is_valid_ether_addr(addr->sa_data))
3346 return -EADDRNOTAVAIL;
3347
3348 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3349
3350 rtl_rar_set(tp, dev->dev_addr);
3351
3352 return 0;
3353}
3354
5f787a1a
FR		 3355static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3356{
3357 struct rtl8169_private *tp = netdev_priv(dev);
3358 struct mii_ioctl_data *data = if_mii(ifr);
3359
8b4ab28d
FR		 3360 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3361}
5f787a1a 3362
cecb5fd7
FR		 3363static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3364 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3365{
5f787a1a
FR		 3366 switch (cmd) {
3367 case SIOCGMIIPHY:
3368 data->phy_id = 32; /* Internal PHY */
3369 return 0;
3370
3371 case SIOCGMIIREG:
4da19633 3372 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3373 return 0;
3374
3375 case SIOCSMIIREG:
4da19633 3376 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3377 return 0;
3378 }
3379 return -EOPNOTSUPP;
3380}
3381
8b4ab28d
FR		 3382static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3383{
3384 return -EOPNOTSUPP;
3385}
3386
0e485150
FR		 3387static const struct rtl_cfg_info {
3388 void (*hw_start)(struct net_device *);
3389 unsigned int region;
3390 unsigned int align;
3391 u16 intr_event;
3392 u16 napi_event;
ccdffb9a 3393 unsigned features;
f21b75e9 3394 u8 default_ver;
0e485150
FR		 3395} rtl_cfg_infos [] = {
3396 [RTL_CFG_0] = {
3397 .hw_start = rtl_hw_start_8169,
3398 .region = 1,
e9f63f30 3399 .align = 0,
0e485150
FR		 3400 .intr_event = SYSErr | LinkChg | RxOverflow |
3401 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 3402 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3403 .features = RTL_FEATURE_GMII,
3404 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 3405 },
3406 [RTL_CFG_1] = {
3407 .hw_start = rtl_hw_start_8168,
3408 .region = 2,
3409 .align = 8,
53f57357 3410 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 3411 TxErr | TxOK | RxOK | RxErr,
fbac58fc 3412 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3413 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3414 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 3415 },
3416 [RTL_CFG_2] = {
3417 .hw_start = rtl_hw_start_8101,
3418 .region = 2,
3419 .align = 8,
3420 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3421 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 3422 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3423 .features = RTL_FEATURE_MSI,
3424 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 3425 }
3426};
3427
fbac58fc 3428/* Cfg9346_Unlock assumed. */
2ca6cf06 3429static unsigned rtl_try_msi(struct rtl8169_private *tp,
fbac58fc
FR		 3430 const struct rtl_cfg_info *cfg)
3431{
2ca6cf06 3432 void __iomem *ioaddr = tp->mmio_addr;
fbac58fc
FR		 3433 unsigned msi = 0;
3434 u8 cfg2;
3435
3436 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 3437 if (cfg->features & RTL_FEATURE_MSI) {
2ca6cf06 3438 if (pci_enable_msi(tp->pci_dev)) {
3439 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
fbac58fc
FR		 3440 } else {
3441 cfg2 |= MSIEnable;
3442 msi = RTL_FEATURE_MSI;
3443 }
3444 }
2ca6cf06 3445 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3446 RTL_W8(Config2, cfg2);
fbac58fc
FR		 3447 return msi;
3448}
3449
3450static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3451{
3452 if (tp->features & RTL_FEATURE_MSI) {
3453 pci_disable_msi(pdev);
3454 tp->features &= ~RTL_FEATURE_MSI;
3455 }
3456}
3457
8b4ab28d
FR		 3458static const struct net_device_ops rtl8169_netdev_ops = {
3459 .ndo_open = rtl8169_open,
3460 .ndo_stop = rtl8169_close,
3461 .ndo_get_stats = rtl8169_get_stats,
00829823 3462 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 3463 .ndo_tx_timeout = rtl8169_tx_timeout,
3464 .ndo_validate_addr = eth_validate_addr,
3465 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 3466 .ndo_fix_features = rtl8169_fix_features,
3467 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 3468 .ndo_set_mac_address = rtl_set_mac_address,
3469 .ndo_do_ioctl = rtl8169_ioctl,
afc4b13d 3470 .ndo_set_rx_mode = rtl_set_rx_mode,
8b4ab28d
FR		 3471#ifdef CONFIG_NET_POLL_CONTROLLER
3472 .ndo_poll_controller = rtl8169_netpoll,
3473#endif
3474
3475};
3476
c0e45c1c 3477static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3478{
3479 struct mdio_ops *ops = &tp->mdio_ops;
3480
3481 switch (tp->mac_version) {
3482 case RTL_GIGA_MAC_VER_27:
3483 ops->write = r8168dp_1_mdio_write;
3484 ops->read = r8168dp_1_mdio_read;
3485 break;
e6de30d6 3486 case RTL_GIGA_MAC_VER_28:
4804b3b3 3487 case RTL_GIGA_MAC_VER_31:
e6de30d6 3488 ops->write = r8168dp_2_mdio_write;
3489 ops->read = r8168dp_2_mdio_read;
3490 break;
c0e45c1c 3491 default:
3492 ops->write = r8169_mdio_write;
3493 ops->read = r8169_mdio_read;
3494 break;
3495 }
3496}
3497
649b3b8c 3498static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3499{
3500 void __iomem *ioaddr = tp->mmio_addr;
3501
3502 switch (tp->mac_version) {
3503 case RTL_GIGA_MAC_VER_29:
3504 case RTL_GIGA_MAC_VER_30:
3505 case RTL_GIGA_MAC_VER_32:
3506 case RTL_GIGA_MAC_VER_33:
3507 case RTL_GIGA_MAC_VER_34:
3508 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3509 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3510 break;
3511 default:
3512 break;
3513 }
3514}
3515
3516static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3517{
3518 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3519 return false;
3520
3521 rtl_writephy(tp, 0x1f, 0x0000);
3522 rtl_writephy(tp, MII_BMCR, 0x0000);
3523
3524 rtl_wol_suspend_quirk(tp);
3525
3526 return true;
3527}
3528
065c27c1 3529static void r810x_phy_power_down(struct rtl8169_private *tp)
3530{
3531 rtl_writephy(tp, 0x1f, 0x0000);
3532 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3533}
3534
3535static void r810x_phy_power_up(struct rtl8169_private *tp)
3536{
3537 rtl_writephy(tp, 0x1f, 0x0000);
3538 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3539}
3540
3541static void r810x_pll_power_down(struct rtl8169_private *tp)
3542{
649b3b8c 3543 if (rtl_wol_pll_power_down(tp))
065c27c1 3544 return;
065c27c1 3545
3546 r810x_phy_power_down(tp);
3547}
3548
3549static void r810x_pll_power_up(struct rtl8169_private *tp)
3550{
3551 r810x_phy_power_up(tp);
3552}
3553
3554static void r8168_phy_power_up(struct rtl8169_private *tp)
3555{
3556 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3557 switch (tp->mac_version) {
3558 case RTL_GIGA_MAC_VER_11:
3559 case RTL_GIGA_MAC_VER_12:
3560 case RTL_GIGA_MAC_VER_17:
3561 case RTL_GIGA_MAC_VER_18:
3562 case RTL_GIGA_MAC_VER_19:
3563 case RTL_GIGA_MAC_VER_20:
3564 case RTL_GIGA_MAC_VER_21:
3565 case RTL_GIGA_MAC_VER_22:
3566 case RTL_GIGA_MAC_VER_23:
3567 case RTL_GIGA_MAC_VER_24:
3568 case RTL_GIGA_MAC_VER_25:
3569 case RTL_GIGA_MAC_VER_26:
3570 case RTL_GIGA_MAC_VER_27:
3571 case RTL_GIGA_MAC_VER_28:
3572 case RTL_GIGA_MAC_VER_31:
3573 rtl_writephy(tp, 0x0e, 0x0000);
3574 break;
3575 default:
3576 break;
3577 }
065c27c1 3578 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3579}
3580
3581static void r8168_phy_power_down(struct rtl8169_private *tp)
3582{
3583 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3584 switch (tp->mac_version) {
3585 case RTL_GIGA_MAC_VER_32:
3586 case RTL_GIGA_MAC_VER_33:
3587 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3588 break;
3589
3590 case RTL_GIGA_MAC_VER_11:
3591 case RTL_GIGA_MAC_VER_12:
3592 case RTL_GIGA_MAC_VER_17:
3593 case RTL_GIGA_MAC_VER_18:
3594 case RTL_GIGA_MAC_VER_19:
3595 case RTL_GIGA_MAC_VER_20:
3596 case RTL_GIGA_MAC_VER_21:
3597 case RTL_GIGA_MAC_VER_22:
3598 case RTL_GIGA_MAC_VER_23:
3599 case RTL_GIGA_MAC_VER_24:
3600 case RTL_GIGA_MAC_VER_25:
3601 case RTL_GIGA_MAC_VER_26:
3602 case RTL_GIGA_MAC_VER_27:
3603 case RTL_GIGA_MAC_VER_28:
3604 case RTL_GIGA_MAC_VER_31:
3605 rtl_writephy(tp, 0x0e, 0x0200);
3606 default:
3607 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3608 break;
3609 }
065c27c1 3610}
3611
3612static void r8168_pll_power_down(struct rtl8169_private *tp)
3613{
3614 void __iomem *ioaddr = tp->mmio_addr;
3615
cecb5fd7
FR		 3616 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3617 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3618 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3619 r8168dp_check_dash(tp)) {
065c27c1 3620 return;
5d2e1957 3621 }
065c27c1 3622
cecb5fd7
FR		 3623 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3624 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3625 (RTL_R16(CPlusCmd) & ASF)) {
3626 return;
3627 }
3628
01dc7fec 3629 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3630 tp->mac_version == RTL_GIGA_MAC_VER_33)
3631 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3632
649b3b8c 3633 if (rtl_wol_pll_power_down(tp))
065c27c1 3634 return;
065c27c1 3635
3636 r8168_phy_power_down(tp);
3637
3638 switch (tp->mac_version) {
3639 case RTL_GIGA_MAC_VER_25:
3640 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3641 case RTL_GIGA_MAC_VER_27:
3642 case RTL_GIGA_MAC_VER_28:
4804b3b3 3643 case RTL_GIGA_MAC_VER_31:
01dc7fec 3644 case RTL_GIGA_MAC_VER_32:
3645 case RTL_GIGA_MAC_VER_33:
065c27c1 3646 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3647 break;
3648 }
3649}
3650
3651static void r8168_pll_power_up(struct rtl8169_private *tp)
3652{
3653 void __iomem *ioaddr = tp->mmio_addr;
3654
cecb5fd7
FR		 3655 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3656 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3657 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3658 r8168dp_check_dash(tp)) {
065c27c1 3659 return;
5d2e1957 3660 }
065c27c1 3661
3662 switch (tp->mac_version) {
3663 case RTL_GIGA_MAC_VER_25:
3664 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3665 case RTL_GIGA_MAC_VER_27:
3666 case RTL_GIGA_MAC_VER_28:
4804b3b3 3667 case RTL_GIGA_MAC_VER_31:
01dc7fec 3668 case RTL_GIGA_MAC_VER_32:
3669 case RTL_GIGA_MAC_VER_33:
065c27c1 3670 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3671 break;
3672 }
3673
3674 r8168_phy_power_up(tp);
3675}
3676
d58d46b5
FR		 3677static void rtl_generic_op(struct rtl8169_private *tp,
3678 void (*op)(struct rtl8169_private *))
065c27c1 3679{
3680 if (op)
3681 op(tp);
3682}
3683
3684static void rtl_pll_power_down(struct rtl8169_private *tp)
3685{
d58d46b5 3686 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 3687}
3688
3689static void rtl_pll_power_up(struct rtl8169_private *tp)
3690{
d58d46b5 3691 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 3692}
3693
3694static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3695{
3696 struct pll_power_ops *ops = &tp->pll_power_ops;
3697
3698 switch (tp->mac_version) {
3699 case RTL_GIGA_MAC_VER_07:
3700 case RTL_GIGA_MAC_VER_08:
3701 case RTL_GIGA_MAC_VER_09:
3702 case RTL_GIGA_MAC_VER_10:
3703 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3704 case RTL_GIGA_MAC_VER_29:
3705 case RTL_GIGA_MAC_VER_30:
065c27c1 3706 ops->down = r810x_pll_power_down;
3707 ops->up = r810x_pll_power_up;
3708 break;
3709
3710 case RTL_GIGA_MAC_VER_11:
3711 case RTL_GIGA_MAC_VER_12:
3712 case RTL_GIGA_MAC_VER_17:
3713 case RTL_GIGA_MAC_VER_18:
3714 case RTL_GIGA_MAC_VER_19:
3715 case RTL_GIGA_MAC_VER_20:
3716 case RTL_GIGA_MAC_VER_21:
3717 case RTL_GIGA_MAC_VER_22:
3718 case RTL_GIGA_MAC_VER_23:
3719 case RTL_GIGA_MAC_VER_24:
3720 case RTL_GIGA_MAC_VER_25:
3721 case RTL_GIGA_MAC_VER_26:
3722 case RTL_GIGA_MAC_VER_27:
e6de30d6 3723 case RTL_GIGA_MAC_VER_28:
4804b3b3 3724 case RTL_GIGA_MAC_VER_31:
01dc7fec 3725 case RTL_GIGA_MAC_VER_32:
3726 case RTL_GIGA_MAC_VER_33:
70090424 3727 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 3728 case RTL_GIGA_MAC_VER_35:
3729 case RTL_GIGA_MAC_VER_36:
065c27c1 3730 ops->down = r8168_pll_power_down;
3731 ops->up = r8168_pll_power_up;
3732 break;
3733
3734 default:
3735 ops->down = NULL;
3736 ops->up = NULL;
3737 break;
3738 }
3739}
3740
e542a226
HW		 3741static void rtl_init_rxcfg(struct rtl8169_private *tp)
3742{
3743 void __iomem *ioaddr = tp->mmio_addr;
3744
3745 switch (tp->mac_version) {
3746 case RTL_GIGA_MAC_VER_01:
3747 case RTL_GIGA_MAC_VER_02:
3748 case RTL_GIGA_MAC_VER_03:
3749 case RTL_GIGA_MAC_VER_04:
3750 case RTL_GIGA_MAC_VER_05:
3751 case RTL_GIGA_MAC_VER_06:
3752 case RTL_GIGA_MAC_VER_10:
3753 case RTL_GIGA_MAC_VER_11:
3754 case RTL_GIGA_MAC_VER_12:
3755 case RTL_GIGA_MAC_VER_13:
3756 case RTL_GIGA_MAC_VER_14:
3757 case RTL_GIGA_MAC_VER_15:
3758 case RTL_GIGA_MAC_VER_16:
3759 case RTL_GIGA_MAC_VER_17:
3760 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3761 break;
3762 case RTL_GIGA_MAC_VER_18:
3763 case RTL_GIGA_MAC_VER_19:
3764 case RTL_GIGA_MAC_VER_20:
3765 case RTL_GIGA_MAC_VER_21:
3766 case RTL_GIGA_MAC_VER_22:
3767 case RTL_GIGA_MAC_VER_23:
3768 case RTL_GIGA_MAC_VER_24:
3769 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3770 break;
3771 default:
3772 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3773 break;
3774 }
3775}
3776
92fc43b4
HW		 3777static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3778{
3779 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3780}
3781
d58d46b5
FR		 3782static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3783{
3784 rtl_generic_op(tp, tp->jumbo_ops.enable);
3785}
3786
3787static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3788{
3789 rtl_generic_op(tp, tp->jumbo_ops.disable);
3790}
3791
3792static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3793{
3794 void __iomem *ioaddr = tp->mmio_addr;
3795
3796 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3797 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3798 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3799}
3800
3801static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3802{
3803 void __iomem *ioaddr = tp->mmio_addr;
3804
3805 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3806 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3807 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3808}
3809
3810static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3811{
3812 void __iomem *ioaddr = tp->mmio_addr;
3813
3814 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3815}
3816
3817static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3818{
3819 void __iomem *ioaddr = tp->mmio_addr;
3820
3821 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3822}
3823
3824static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3825{
3826 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 3827
3828 RTL_W8(MaxTxPacketSize, 0x3f);
3829 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3830 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 3831 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 3832}
3833
3834static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3835{
3836 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 3837
3838 RTL_W8(MaxTxPacketSize, 0x0c);
3839 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3840 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 3841 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 3842}
3843
3844static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3845{
3846 rtl_tx_performance_tweak(tp->pci_dev,
3847 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3848}
3849
3850static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3851{
3852 rtl_tx_performance_tweak(tp->pci_dev,
3853 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3854}
3855
3856static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3857{
3858 void __iomem *ioaddr = tp->mmio_addr;
3859
3860 r8168b_0_hw_jumbo_enable(tp);
3861
3862 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3863}
3864
3865static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3866{
3867 void __iomem *ioaddr = tp->mmio_addr;
3868
3869 r8168b_0_hw_jumbo_disable(tp);
3870
3871 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3872}
3873
3874static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3875{
3876 struct jumbo_ops *ops = &tp->jumbo_ops;
3877
3878 switch (tp->mac_version) {
3879 case RTL_GIGA_MAC_VER_11:
3880 ops->disable = r8168b_0_hw_jumbo_disable;
3881 ops->enable = r8168b_0_hw_jumbo_enable;
3882 break;
3883 case RTL_GIGA_MAC_VER_12:
3884 case RTL_GIGA_MAC_VER_17:
3885 ops->disable = r8168b_1_hw_jumbo_disable;
3886 ops->enable = r8168b_1_hw_jumbo_enable;
3887 break;
3888 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3889 case RTL_GIGA_MAC_VER_19:
3890 case RTL_GIGA_MAC_VER_20:
3891 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3892 case RTL_GIGA_MAC_VER_22:
3893 case RTL_GIGA_MAC_VER_23:
3894 case RTL_GIGA_MAC_VER_24:
3895 case RTL_GIGA_MAC_VER_25:
3896 case RTL_GIGA_MAC_VER_26:
3897 ops->disable = r8168c_hw_jumbo_disable;
3898 ops->enable = r8168c_hw_jumbo_enable;
3899 break;
3900 case RTL_GIGA_MAC_VER_27:
3901 case RTL_GIGA_MAC_VER_28:
3902 ops->disable = r8168dp_hw_jumbo_disable;
3903 ops->enable = r8168dp_hw_jumbo_enable;
3904 break;
3905 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3906 case RTL_GIGA_MAC_VER_32:
3907 case RTL_GIGA_MAC_VER_33:
3908 case RTL_GIGA_MAC_VER_34:
3909 ops->disable = r8168e_hw_jumbo_disable;
3910 ops->enable = r8168e_hw_jumbo_enable;
3911 break;
3912
3913 /*
3914 * No action needed for jumbo frames with 8169.
3915 * No jumbo for 810x at all.
3916 */
3917 default:
3918 ops->disable = NULL;
3919 ops->enable = NULL;
3920 break;
3921 }
3922}
3923
6f43adc8
FR		 3924static void rtl_hw_reset(struct rtl8169_private *tp)
3925{
3926 void __iomem *ioaddr = tp->mmio_addr;
3927 int i;
3928
3929 /* Soft reset the chip. */
3930 RTL_W8(ChipCmd, CmdReset);
3931
3932 /* Check that the chip has finished the reset. */
3933 for (i = 0; i < 100; i++) {
3934 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3935 break;
92fc43b4 3936 udelay(100);
6f43adc8
FR		 3937 }
3938}
3939
1da177e4 3940static int __devinit
4ff96fa6 3941rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3942{
0e485150
FR		 3943 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3944 const unsigned int region = cfg->region;
1da177e4 3945 struct rtl8169_private *tp;
ccdffb9a 3946 struct mii_if_info *mii;
4ff96fa6
FR		 3947 struct net_device *dev;
3948 void __iomem *ioaddr;
2b7b4318 3949 int chipset, i;
07d3f51f 3950 int rc;
1da177e4 3951
4ff96fa6
FR		 3952 if (netif_msg_drv(&debug)) {
3953 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3954 MODULENAME, RTL8169_VERSION);
3955 }
1da177e4 3956
1da177e4 3957 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3958 if (!dev) {
b57b7e5a 3959 if (netif_msg_drv(&debug))
9b91cf9d 3960 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3961 rc = -ENOMEM;
3962 goto out;
1da177e4
LT		 3963 }
3964
1da177e4 3965 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3966 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3967 tp = netdev_priv(dev);
c4028958 3968 tp->dev = dev;
21e197f2 3969 tp->pci_dev = pdev;
b57b7e5a 3970 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3971
ccdffb9a
FR		 3972 mii = &tp->mii;
3973 mii->dev = dev;
3974 mii->mdio_read = rtl_mdio_read;
3975 mii->mdio_write = rtl_mdio_write;
3976 mii->phy_id_mask = 0x1f;
3977 mii->reg_num_mask = 0x1f;
3978 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3979
ba04c7c9
SG		 3980 /* disable ASPM completely as that cause random device stop working
3981 * problems as well as full system hangs for some PCIe devices users */
3982 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3983 PCIE_LINK_STATE_CLKPM);
3984
1da177e4
LT		 3985 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3986 rc = pci_enable_device(pdev);
b57b7e5a 3987 if (rc < 0) {
bf82c189 3988 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3989 goto err_out_free_dev_1;
1da177e4
LT		 3990 }
3991
87aeec76 3992 if (pci_set_mwi(pdev) < 0)
3993 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3994
1da177e4 3995 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3996 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3997 netif_err(tp, probe, dev,
3998 "region #%d not an MMIO resource, aborting\n",
3999 region);
1da177e4 4000 rc = -ENODEV;
87aeec76 4001 goto err_out_mwi_2;
1da177e4 4002 }
4ff96fa6 4003
1da177e4 4004 /* check for weird/broken PCI region reporting */
bcf0bf90 4005 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 4006 netif_err(tp, probe, dev,
4007 "Invalid PCI region size(s), aborting\n");
1da177e4 4008 rc = -ENODEV;
87aeec76 4009 goto err_out_mwi_2;
1da177e4
LT		 4010 }
4011
4012 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 4013 if (rc < 0) {
bf82c189 4014 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 4015 goto err_out_mwi_2;
1da177e4
LT		 4016 }
4017
d24e9aaf 4018 tp->cp_cmd = RxChkSum;
1da177e4
LT		 4019
4020 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 4021 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 4022 tp->cp_cmd |= PCIDAC;
4023 dev->features |= NETIF_F_HIGHDMA;
4024 } else {
284901a9 4025 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 4026 if (rc < 0) {
bf82c189 4027 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 4028 goto err_out_free_res_3;
1da177e4
LT		 4029 }
4030 }
4031
1da177e4 4032 /* ioremap MMIO region */
bcf0bf90 4033 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 4034 if (!ioaddr) {
bf82c189 4035 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 4036 rc = -EIO;
87aeec76 4037 goto err_out_free_res_3;
1da177e4 4038 }
6f43adc8 4039 tp->mmio_addr = ioaddr;
1da177e4 4040
e44daade
JM		 4041 if (!pci_is_pcie(pdev))
4042 netif_info(tp, probe, dev, "not PCI Express\n");
4300e8c7 4043
e542a226
HW		 4044 /* Identify chip attached to board */
4045 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
4046
4047 rtl_init_rxcfg(tp);
4048
d78ad8cb 4049 RTL_W16(IntrMask, 0x0000);
1da177e4 4050
6f43adc8 4051 rtl_hw_reset(tp);
1da177e4 4052
d78ad8cb
KW		 4053 RTL_W16(IntrStatus, 0xffff);
4054
ca52efd5 4055 pci_set_master(pdev);
4056
7a8fc77b
FR		 4057 /*
4058 * Pretend we are using VLANs; This bypasses a nasty bug where
4059 * Interrupts stop flowing on high load on 8110SCd controllers.
4060 */
4061 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4062 tp->cp_cmd |= RxVlan;
4063
c0e45c1c 4064 rtl_init_mdio_ops(tp);
065c27c1 4065 rtl_init_pll_power_ops(tp);
d58d46b5 4066 rtl_init_jumbo_ops(tp);
c0e45c1c 4067
1da177e4 4068 rtl8169_print_mac_version(tp);
1da177e4 4069
85bffe6c
FR		 4070 chipset = tp->mac_version;
4071 tp->txd_version = rtl_chip_infos[chipset].txd_version;
1da177e4 4072
5d06a99f
FR		 4073 RTL_W8(Cfg9346, Cfg9346_Unlock);
4074 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
4075 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 4076 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
4077 tp->features |= RTL_FEATURE_WOL;
4078 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
4079 tp->features |= RTL_FEATURE_WOL;
2ca6cf06 4080 tp->features |= rtl_try_msi(tp, cfg);
5d06a99f
FR		 4081 RTL_W8(Cfg9346, Cfg9346_Lock);
4082
2544bfc0 4083 if (rtl_tbi_enabled(tp)) {
1da177e4
LT		 4084 tp->set_speed = rtl8169_set_speed_tbi;
4085 tp->get_settings = rtl8169_gset_tbi;
4086 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
4087 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
4088 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 4089 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4
LT		 4090 } else {
4091 tp->set_speed = rtl8169_set_speed_xmii;
4092 tp->get_settings = rtl8169_gset_xmii;
4093 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
4094 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
4095 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 4096 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 4097 }
4098
df58ef51
FR		 4099 spin_lock_init(&tp->lock);
4100
7bf6bf48 4101 /* Get MAC address */
6a3c910c 4102 for (i = 0; i < ETH_ALEN; i++)
1da177e4 4103 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 4104 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 4105
1da177e4 4106 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 4107 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
4108 dev->irq = pdev->irq;
4109 dev->base_addr = (unsigned long) ioaddr;
1da177e4 4110
bea3348e 4111 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 4112
350fb32a
MM		 4113 /* don't enable SG, IP_CSUM and TSO by default - it might not work
4114 * properly for all devices */
4115 dev->features |= NETIF_F_RXCSUM |
4116 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4117
4118 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4119 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4120 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4121 NETIF_F_HIGHDMA;
4122
4123 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4124 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
4125 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4
LT		 4126
4127 tp->intr_mask = 0xffff;
0e485150
FR		 4128 tp->hw_start = cfg->hw_start;
4129 tp->intr_event = cfg->intr_event;
4130 tp->napi_event = cfg->napi_event;
1da177e4 4131
e03f33af
FR		 4132 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
4133 ~(RxBOVF | RxFOVF) : ~0;
4134
2efa53f3
FR		 4135 init_timer(&tp->timer);
4136 tp->timer.data = (unsigned long) dev;
4137 tp->timer.function = rtl8169_phy_timer;
4138
b6ffd97f 4139 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
953a12cc 4140
1da177e4 4141 rc = register_netdev(dev);
4ff96fa6 4142 if (rc < 0)
87aeec76 4143 goto err_out_msi_4;
1da177e4
LT		 4144
4145 pci_set_drvdata(pdev, dev);
4146
bf82c189 4147 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
85bffe6c 4148 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 4149 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
d58d46b5
FR		 4150 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
4151 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
4152 "tx checksumming: %s]\n",
4153 rtl_chip_infos[chipset].jumbo_max,
4154 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
4155 }
1da177e4 4156
cecb5fd7
FR		 4157 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4158 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4159 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 4160 rtl8168_driver_start(tp);
e6de30d6 4161 }
b646d900 4162
8b76ab39 4163 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 4164
f3ec4f87
AS		 4165 if (pci_dev_run_wake(pdev))
4166 pm_runtime_put_noidle(&pdev->dev);
e1759441 4167
0d672e9f
IV		 4168 netif_carrier_off(dev);
4169
4ff96fa6
FR		 4170out:
4171 return rc;
1da177e4 4172
87aeec76 4173err_out_msi_4:
fbac58fc 4174 rtl_disable_msi(pdev, tp);
4ff96fa6 4175 iounmap(ioaddr);
87aeec76 4176err_out_free_res_3:
4ff96fa6 4177 pci_release_regions(pdev);
87aeec76 4178err_out_mwi_2:
4ff96fa6 4179 pci_clear_mwi(pdev);
4ff96fa6
FR		 4180 pci_disable_device(pdev);
4181err_out_free_dev_1:
4182 free_netdev(dev);
4183 goto out;
1da177e4
LT		 4184}
4185
07d3f51f 4186static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 4187{
4188 struct net_device *dev = pci_get_drvdata(pdev);
4189 struct rtl8169_private *tp = netdev_priv(dev);
4190
cecb5fd7
FR		 4191 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4192 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4193 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 4194 rtl8168_driver_stop(tp);
e6de30d6 4195 }
b646d900 4196
23f333a2 4197 cancel_delayed_work_sync(&tp->task);
eb2a021c 4198
1da177e4 4199 unregister_netdev(dev);
cc098dc7 4200
953a12cc
FR		 4201 rtl_release_firmware(tp);
4202
f3ec4f87
AS		 4203 if (pci_dev_run_wake(pdev))
4204 pm_runtime_get_noresume(&pdev->dev);
e1759441 4205
cc098dc7
IV		 4206 /* restore original MAC address */
4207 rtl_rar_set(tp, dev->perm_addr);
4208
fbac58fc 4209 rtl_disable_msi(pdev, tp);
1da177e4
LT		 4210 rtl8169_release_board(pdev, dev, tp->mmio_addr);
4211 pci_set_drvdata(pdev, NULL);
4212}
4213
b6ffd97f 4214static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4215{
b6ffd97f
FR		 4216 struct rtl_fw *rtl_fw;
4217 const char *name;
4218 int rc = -ENOMEM;
953a12cc 4219
b6ffd97f
FR		 4220 name = rtl_lookup_firmware_name(tp);
4221 if (!name)
4222 goto out_no_firmware;
953a12cc 4223
b6ffd97f
FR		 4224 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4225 if (!rtl_fw)
4226 goto err_warn;
31bd204f 4227
b6ffd97f
FR		 4228 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4229 if (rc < 0)
4230 goto err_free;
4231
fd112f2e
FR		 4232 rc = rtl_check_firmware(tp, rtl_fw);
4233 if (rc < 0)
4234 goto err_release_firmware;
4235
b6ffd97f
FR		 4236 tp->rtl_fw = rtl_fw;
4237out:
4238 return;
4239
fd112f2e
FR		 4240err_release_firmware:
4241 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4242err_free:
4243 kfree(rtl_fw);
4244err_warn:
4245 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4246 name, rc);
4247out_no_firmware:
4248 tp->rtl_fw = NULL;
4249 goto out;
4250}
4251
4252static void rtl_request_firmware(struct rtl8169_private *tp)
4253{
4254 if (IS_ERR(tp->rtl_fw))
4255 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4256}
4257
1da177e4
LT		 4258static int rtl8169_open(struct net_device *dev)
4259{
4260 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 4261 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4262 struct pci_dev *pdev = tp->pci_dev;
99f252b0 4263 int retval = -ENOMEM;
1da177e4 4264
e1759441 4265 pm_runtime_get_sync(&pdev->dev);
1da177e4 4266
1da177e4
LT		 4267 /*
4268 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 4269 * dma_alloc_coherent provides more.
1da177e4 4270 */
82553bb6
SG		 4271 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4272 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 4273 if (!tp->TxDescArray)
e1759441 4274 goto err_pm_runtime_put;
1da177e4 4275
82553bb6
SG		 4276 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4277 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 4278 if (!tp->RxDescArray)
99f252b0 4279 goto err_free_tx_0;
1da177e4
LT		 4280
4281 retval = rtl8169_init_ring(dev);
4282 if (retval < 0)
99f252b0 4283 goto err_free_rx_1;
1da177e4 4284
c4028958 4285 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 4286
99f252b0
FR		 4287 smp_mb();
4288
953a12cc
FR		 4289 rtl_request_firmware(tp);
4290
fbac58fc
FR		 4291 retval = request_irq(dev->irq, rtl8169_interrupt,
4292 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 4293 dev->name, dev);
4294 if (retval < 0)
953a12cc 4295 goto err_release_fw_2;
99f252b0 4296
bea3348e 4297 napi_enable(&tp->napi);
bea3348e 4298
eee3a96c 4299 rtl8169_init_phy(dev, tp);
4300
350fb32a 4301 rtl8169_set_features(dev, dev->features);
eee3a96c 4302
065c27c1 4303 rtl_pll_power_up(tp);
4304
07ce4064 4305 rtl_hw_start(dev);
1da177e4 4306
e1759441
RW		 4307 tp->saved_wolopts = 0;
4308 pm_runtime_put_noidle(&pdev->dev);
4309
eee3a96c 4310 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 4311out:
4312 return retval;
4313
953a12cc
FR		 4314err_release_fw_2:
4315 rtl_release_firmware(tp);
99f252b0
FR		 4316 rtl8169_rx_clear(tp);
4317err_free_rx_1:
82553bb6
SG		 4318 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4319 tp->RxPhyAddr);
e1759441 4320 tp->RxDescArray = NULL;
99f252b0 4321err_free_tx_0:
82553bb6
SG		 4322 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4323 tp->TxPhyAddr);
e1759441
RW		 4324 tp->TxDescArray = NULL;
4325err_pm_runtime_put:
4326 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 4327 goto out;
4328}
4329
92fc43b4
HW		 4330static void rtl_rx_close(struct rtl8169_private *tp)
4331{
4332 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4333
1687b566 4334 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4335}
4336
e6de30d6 4337static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4338{
e6de30d6 4339 void __iomem *ioaddr = tp->mmio_addr;
4340
1da177e4 4341 /* Disable interrupts */
811fd301 4342 rtl8169_irq_mask_and_ack(tp);
1da177e4 4343
92fc43b4
HW		 4344 rtl_rx_close(tp);
4345
5d2e1957 4346 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4347 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4348 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 4349 while (RTL_R8(TxPoll) & NPQ)
4350 udelay(20);
c2218925
HW		 4351 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4352 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4353 tp->mac_version == RTL_GIGA_MAC_VER_36) {
c2b0c1e7 4354 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
70090424
HW		 4355 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4356 udelay(100);
92fc43b4
HW		 4357 } else {
4358 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4359 udelay(100);
e6de30d6 4360 }
4361
92fc43b4 4362 rtl_hw_reset(tp);
1da177e4
LT		 4363}
4364
7f796d83 4365static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4366{
4367 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4368
4369 /* Set DMA burst size and Interframe Gap Time */
4370 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4371 (InterFrameGap << TxInterFrameGapShift));
4372}
4373
07ce4064 4374static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4375{
4376 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4377
07ce4064
FR		 4378 tp->hw_start(dev);
4379
07ce4064
FR		 4380 netif_start_queue(dev);
4381}
4382
7f796d83
FR		 4383static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4384 void __iomem *ioaddr)
4385{
4386 /*
4387 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4388 * register to be written before TxDescAddrLow to work.
4389 * Switching from MMIO to I/O access fixes the issue as well.
4390 */
4391 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4392 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4393 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4394 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4395}
4396
4397static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4398{
4399 u16 cmd;
4400
4401 cmd = RTL_R16(CPlusCmd);
4402 RTL_W16(CPlusCmd, cmd);
4403 return cmd;
4404}
4405
fdd7b4c3 4406static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4407{
4408 /* Low hurts. Let's disable the filtering. */
207d6e87 4409 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4410}
4411
6dccd16b
FR		 4412static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4413{
3744100e 4414 static const struct rtl_cfg2_info {
6dccd16b
FR		 4415 u32 mac_version;
4416 u32 clk;
4417 u32 val;
4418 } cfg2_info [] = {
4419 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4420 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4421 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4422 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4423 };
4424 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4425 unsigned int i;
4426 u32 clk;
4427
4428 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4429 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4430 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4431 RTL_W32(0x7c, p->val);
4432 break;
4433 }
4434 }
4435}
4436
07ce4064
FR		 4437static void rtl_hw_start_8169(struct net_device *dev)
4438{
4439 struct rtl8169_private *tp = netdev_priv(dev);
4440 void __iomem *ioaddr = tp->mmio_addr;
4441 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4442
9cb427b6
FR		 4443 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4444 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4445 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4446 }
4447
1da177e4 4448 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4449 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4450 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4451 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4452 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4453 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4454
e542a226
HW		 4455 rtl_init_rxcfg(tp);
4456
f0298f81 4457 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4458
6f0333b8 4459 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4460
cecb5fd7
FR		 4461 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4462 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4463 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4464 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4465 rtl_set_rx_tx_config_registers(tp);
1da177e4 4466
7f796d83 4467 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4468
cecb5fd7
FR		 4469 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4470 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4471 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4472 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4473 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4474 }
4475
bcf0bf90
FR		 4476 RTL_W16(CPlusCmd, tp->cp_cmd);
4477
6dccd16b
FR		 4478 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4479
1da177e4
LT		 4480 /*
4481 * Undocumented corner. Supposedly:
4482 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4483 */
4484 RTL_W16(IntrMitigate, 0x0000);
4485
7f796d83 4486 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4487
cecb5fd7
FR		 4488 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4489 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4490 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4491 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4492 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4493 rtl_set_rx_tx_config_registers(tp);
4494 }
4495
1da177e4 4496 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4497
4498 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4499 RTL_R8(IntrMask);
1da177e4
LT		 4500
4501 RTL_W32(RxMissed, 0);
4502
07ce4064 4503 rtl_set_rx_mode(dev);
1da177e4
LT		 4504
4505 /* no early-rx interrupts */
4506 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 4507
4508 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 4509 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4510}
1da177e4 4511
650e8d5d 4512static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 4513{
4514 u32 csi;
4515
4516 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 4517 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4518}
4519
e6de30d6 4520static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4521{
4522 rtl_csi_access_enable(ioaddr, 0x17000000);
4523}
4524
650e8d5d 4525static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4526{
4527 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 4528}
4529
4530struct ephy_info {
4531 unsigned int offset;
4532 u16 mask;
4533 u16 bits;
4534};
4535
350f7596 4536static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 4537{
4538 u16 w;
4539
4540 while (len-- > 0) {
4541 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4542 rtl_ephy_write(ioaddr, e->offset, w);
4543 e++;
4544 }
4545}
4546
b726e493
FR		 4547static void rtl_disable_clock_request(struct pci_dev *pdev)
4548{
e44daade 4549 int cap = pci_pcie_cap(pdev);
b726e493
FR		 4550
4551 if (cap) {
4552 u16 ctl;
4553
4554 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4555 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4556 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4557 }
4558}
4559
e6de30d6 4560static void rtl_enable_clock_request(struct pci_dev *pdev)
4561{
e44daade 4562 int cap = pci_pcie_cap(pdev);
e6de30d6 4563
4564 if (cap) {
4565 u16 ctl;
4566
4567 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4568 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4569 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4570 }
4571}
4572
b726e493
FR		 4573#define R8168_CPCMD_QUIRK_MASK (\
4574 EnableBist | \
4575 Mac_dbgo_oe | \
4576 Force_half_dup | \
4577 Force_rxflow_en | \
4578 Force_txflow_en | \
4579 Cxpl_dbg_sel | \
4580 ASF | \
4581 PktCntrDisable | \
4582 Mac_dbgo_sel)
4583
219a1e9d
FR		 4584static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4585{
b726e493
FR		 4586 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4587
4588 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4589
2e68ae44
FR		 4590 rtl_tx_performance_tweak(pdev,
4591 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4592}
4593
4594static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4595{
4596 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 4597
f0298f81 4598 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4599
4600 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4601}
4602
4603static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4604{
b726e493
FR		 4605 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4606
4607 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4608
219a1e9d 4609 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4610
4611 rtl_disable_clock_request(pdev);
4612
4613 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4614}
4615
ef3386f0 4616static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 4617{
350f7596 4618 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4619 { 0x01, 0, 0x0001 },
4620 { 0x02, 0x0800, 0x1000 },
4621 { 0x03, 0, 0x0042 },
4622 { 0x06, 0x0080, 0x0000 },
4623 { 0x07, 0, 0x2000 }
4624 };
4625
650e8d5d 4626 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4627
4628 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4629
219a1e9d
FR		 4630 __rtl_hw_start_8168cp(ioaddr, pdev);
4631}
4632
ef3386f0
FR		 4633static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4634{
650e8d5d 4635 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 4636
4637 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4638
4639 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4640
4641 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4642}
4643
7f3e3d3a
FR		 4644static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4645{
650e8d5d 4646 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 4647
4648 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4649
4650 /* Magic. */
4651 RTL_W8(DBG_REG, 0x20);
4652
f0298f81 4653 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4654
4655 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4656
4657 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4658}
4659
219a1e9d
FR		 4660static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4661{
350f7596 4662 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4663 { 0x02, 0x0800, 0x1000 },
4664 { 0x03, 0, 0x0002 },
4665 { 0x06, 0x0080, 0x0000 }
4666 };
4667
650e8d5d 4668 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4669
4670 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4671
4672 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4673
219a1e9d
FR		 4674 __rtl_hw_start_8168cp(ioaddr, pdev);
4675}
4676
4677static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4678{
350f7596 4679 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4680 { 0x01, 0, 0x0001 },
4681 { 0x03, 0x0400, 0x0220 }
4682 };
4683
650e8d5d 4684 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4685
4686 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4687
219a1e9d
FR		 4688 __rtl_hw_start_8168cp(ioaddr, pdev);
4689}
4690
197ff761
FR		 4691static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4692{
4693 rtl_hw_start_8168c_2(ioaddr, pdev);
4694}
4695
6fb07058
FR		 4696static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4697{
650e8d5d 4698 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 4699
4700 __rtl_hw_start_8168cp(ioaddr, pdev);
4701}
4702
5b538df9
FR		 4703static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4704{
650e8d5d 4705 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 4706
4707 rtl_disable_clock_request(pdev);
4708
f0298f81 4709 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4710
4711 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4712
4713 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4714}
4715
4804b3b3 4716static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4717{
4718 rtl_csi_access_enable_1(ioaddr);
4719
4720 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4721
4722 RTL_W8(MaxTxPacketSize, TxPacketMax);
4723
4724 rtl_disable_clock_request(pdev);
4725}
4726
e6de30d6 4727static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4728{
4729 static const struct ephy_info e_info_8168d_4[] = {
4730 { 0x0b, ~0, 0x48 },
4731 { 0x19, 0x20, 0x50 },
4732 { 0x0c, ~0, 0x20 }
4733 };
4734 int i;
4735
4736 rtl_csi_access_enable_1(ioaddr);
4737
4738 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4739
4740 RTL_W8(MaxTxPacketSize, TxPacketMax);
4741
4742 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4743 const struct ephy_info *e = e_info_8168d_4 + i;
4744 u16 w;
4745
4746 w = rtl_ephy_read(ioaddr, e->offset);
4747 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4748 }
4749
4750 rtl_enable_clock_request(pdev);
4751}
4752
70090424 4753static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
01dc7fec 4754{
70090424 4755 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4756 { 0x00, 0x0200, 0x0100 },
4757 { 0x00, 0x0000, 0x0004 },
4758 { 0x06, 0x0002, 0x0001 },
4759 { 0x06, 0x0000, 0x0030 },
4760 { 0x07, 0x0000, 0x2000 },
4761 { 0x00, 0x0000, 0x0020 },
4762 { 0x03, 0x5800, 0x2000 },
4763 { 0x03, 0x0000, 0x0001 },
4764 { 0x01, 0x0800, 0x1000 },
4765 { 0x07, 0x0000, 0x4000 },
4766 { 0x1e, 0x0000, 0x2000 },
4767 { 0x19, 0xffff, 0xfe6c },
4768 { 0x0a, 0x0000, 0x0040 }
4769 };
4770
4771 rtl_csi_access_enable_2(ioaddr);
4772
70090424 4773 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4774
4775 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4776
4777 RTL_W8(MaxTxPacketSize, TxPacketMax);
4778
4779 rtl_disable_clock_request(pdev);
4780
4781 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4782 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4783 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4784
cecb5fd7 4785 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4786}
4787
70090424
HW		 4788static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4789{
4790 static const struct ephy_info e_info_8168e_2[] = {
4791 { 0x09, 0x0000, 0x0080 },
4792 { 0x19, 0x0000, 0x0224 }
4793 };
4794
4795 rtl_csi_access_enable_1(ioaddr);
4796
4797 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4798
4799 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4800
4801 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4802 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4803 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4804 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4805 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4806 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4807 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4808 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4809 ERIAR_EXGMAC);
4810
3090bd9a 4811 RTL_W8(MaxTxPacketSize, EarlySize);
70090424
HW		 4812
4813 rtl_disable_clock_request(pdev);
4814
4815 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4816 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4817
4818 /* Adjust EEE LED frequency */
4819 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4820
4821 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4822 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4823 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4824}
4825
c2218925
HW		 4826static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4827{
4828 static const struct ephy_info e_info_8168f_1[] = {
4829 { 0x06, 0x00c0, 0x0020 },
4830 { 0x08, 0x0001, 0x0002 },
4831 { 0x09, 0x0000, 0x0080 },
4832 { 0x19, 0x0000, 0x0224 }
4833 };
4834
4835 rtl_csi_access_enable_1(ioaddr);
4836
4837 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4838
4839 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4840
4841 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4842 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4843 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4844 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4845 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4846 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4847 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4848 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4849 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4850 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4851 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4852 ERIAR_EXGMAC);
4853
4854 RTL_W8(MaxTxPacketSize, EarlySize);
4855
4856 rtl_disable_clock_request(pdev);
4857
4858 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4859 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4860
4861 /* Adjust EEE LED frequency */
4862 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4863
4864 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4865 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4866 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4867}
4868
07ce4064
FR		 4869static void rtl_hw_start_8168(struct net_device *dev)
4870{
2dd99530
FR		 4871 struct rtl8169_private *tp = netdev_priv(dev);
4872 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4873 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4874
4875 RTL_W8(Cfg9346, Cfg9346_Unlock);
4876
f0298f81 4877 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4878
6f0333b8 4879 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4880
0e485150 4881 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4882
4883 RTL_W16(CPlusCmd, tp->cp_cmd);
4884
0e485150 4885 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4886
0e485150 4887 /* Work around for RxFIFO overflow. */
811fd301 4888 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
0e485150
FR		 4889 tp->intr_event |= RxFIFOOver | PCSTimeout;
4890 tp->intr_event &= ~RxOverflow;
4891 }
4892
4893 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4894
b8363901
FR		 4895 rtl_set_rx_mode(dev);
4896
4897 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4898 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4899
4900 RTL_R8(IntrMask);
4901
219a1e9d
FR		 4902 switch (tp->mac_version) {
4903 case RTL_GIGA_MAC_VER_11:
4904 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4905 break;
219a1e9d
FR		 4906
4907 case RTL_GIGA_MAC_VER_12:
4908 case RTL_GIGA_MAC_VER_17:
4909 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4910 break;
219a1e9d
FR		 4911
4912 case RTL_GIGA_MAC_VER_18:
ef3386f0 4913 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4914 break;
219a1e9d
FR		 4915
4916 case RTL_GIGA_MAC_VER_19:
4917 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4918 break;
219a1e9d
FR		 4919
4920 case RTL_GIGA_MAC_VER_20:
4921 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4922 break;
219a1e9d 4923
197ff761
FR		 4924 case RTL_GIGA_MAC_VER_21:
4925 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4926 break;
197ff761 4927
6fb07058
FR		 4928 case RTL_GIGA_MAC_VER_22:
4929 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4930 break;
6fb07058 4931
ef3386f0
FR		 4932 case RTL_GIGA_MAC_VER_23:
4933 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4934 break;
ef3386f0 4935
7f3e3d3a
FR		 4936 case RTL_GIGA_MAC_VER_24:
4937 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4938 break;
7f3e3d3a 4939
5b538df9 4940 case RTL_GIGA_MAC_VER_25:
daf9df6d 4941 case RTL_GIGA_MAC_VER_26:
4942 case RTL_GIGA_MAC_VER_27:
5b538df9 4943 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4944 break;
5b538df9 4945
e6de30d6 4946 case RTL_GIGA_MAC_VER_28:
4947 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 4948 break;
cecb5fd7 4949
4804b3b3 4950 case RTL_GIGA_MAC_VER_31:
4951 rtl_hw_start_8168dp(ioaddr, pdev);
4952 break;
4953
01dc7fec 4954 case RTL_GIGA_MAC_VER_32:
4955 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4956 rtl_hw_start_8168e_1(ioaddr, pdev);
4957 break;
4958 case RTL_GIGA_MAC_VER_34:
4959 rtl_hw_start_8168e_2(ioaddr, pdev);
01dc7fec 4960 break;
e6de30d6 4961
c2218925
HW		 4962 case RTL_GIGA_MAC_VER_35:
4963 case RTL_GIGA_MAC_VER_36:
4964 rtl_hw_start_8168f_1(ioaddr, pdev);
4965 break;
4966
219a1e9d
FR		 4967 default:
4968 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4969 dev->name, tp->mac_version);
4804b3b3 4970 break;
219a1e9d 4971 }
2dd99530 4972
0e485150
FR		 4973 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4974
b8363901
FR		 4975 RTL_W8(Cfg9346, Cfg9346_Lock);
4976
2dd99530 4977 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 4978
0e485150 4979 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4980}
1da177e4 4981
2857ffb7
FR		 4982#define R810X_CPCMD_QUIRK_MASK (\
4983 EnableBist | \
4984 Mac_dbgo_oe | \
4985 Force_half_dup | \
5edcc537 4986 Force_rxflow_en | \
2857ffb7
FR		 4987 Force_txflow_en | \
4988 Cxpl_dbg_sel | \
4989 ASF | \
4990 PktCntrDisable | \
d24e9aaf 4991 Mac_dbgo_sel)
2857ffb7
FR		 4992
4993static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4994{
350f7596 4995 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 4996 { 0x01, 0, 0x6e65 },
4997 { 0x02, 0, 0x091f },
4998 { 0x03, 0, 0xc2f9 },
4999 { 0x06, 0, 0xafb5 },
5000 { 0x07, 0, 0x0e00 },
5001 { 0x19, 0, 0xec80 },
5002 { 0x01, 0, 0x2e65 },
5003 { 0x01, 0, 0x6e65 }
5004 };
5005 u8 cfg1;
5006
650e8d5d 5007 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 5008
5009 RTL_W8(DBG_REG, FIX_NAK_1);
5010
5011 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5012
5013 RTL_W8(Config1,
5014 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5015 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5016
5017 cfg1 = RTL_R8(Config1);
5018 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5019 RTL_W8(Config1, cfg1 & ~LEDS0);
5020
2857ffb7
FR		 5021 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5022}
5023
5024static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5025{
650e8d5d 5026 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 5027
5028 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5029
5030 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5031 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5032}
5033
5034static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
5035{
5036 rtl_hw_start_8102e_2(ioaddr, pdev);
5037
5038 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
5039}
5040
5a5e4443
HW		 5041static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5042{
5043 static const struct ephy_info e_info_8105e_1[] = {
5044 { 0x07, 0, 0x4000 },
5045 { 0x19, 0, 0x0200 },
5046 { 0x19, 0, 0x0020 },
5047 { 0x1e, 0, 0x2000 },
5048 { 0x03, 0, 0x0001 },
5049 { 0x19, 0, 0x0100 },
5050 { 0x19, 0, 0x0004 },
5051 { 0x0a, 0, 0x0020 }
5052 };
5053
cecb5fd7 5054 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5055 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5056
cecb5fd7 5057 /* Disable Early Tally Counter */
5a5e4443
HW		 5058 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5059
5060 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5061 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443
HW		 5062
5063 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5064}
5065
5066static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5067{
5068 rtl_hw_start_8105e_1(ioaddr, pdev);
5069 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
5070}
5071
07ce4064
FR		 5072static void rtl_hw_start_8101(struct net_device *dev)
5073{
cdf1a608
FR		 5074 struct rtl8169_private *tp = netdev_priv(dev);
5075 void __iomem *ioaddr = tp->mmio_addr;
5076 struct pci_dev *pdev = tp->pci_dev;
5077
811fd301 5078 if (tp->mac_version >= RTL_GIGA_MAC_VER_30) {
5079 tp->intr_event &= ~RxFIFOOver;
5080 tp->napi_event &= ~RxFIFOOver;
5081 }
5082
cecb5fd7
FR		 5083 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5084 tp->mac_version == RTL_GIGA_MAC_VER_16) {
e44daade 5085 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 5086
5087 if (cap) {
5088 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5089 PCI_EXP_DEVCTL_NOSNOOP_EN);
5090 }
cdf1a608
FR		 5091 }
5092
d24e9aaf
HW		 5093 RTL_W8(Cfg9346, Cfg9346_Unlock);
5094
2857ffb7
FR		 5095 switch (tp->mac_version) {
5096 case RTL_GIGA_MAC_VER_07:
5097 rtl_hw_start_8102e_1(ioaddr, pdev);
5098 break;
5099
5100 case RTL_GIGA_MAC_VER_08:
5101 rtl_hw_start_8102e_3(ioaddr, pdev);
5102 break;
5103
5104 case RTL_GIGA_MAC_VER_09:
5105 rtl_hw_start_8102e_2(ioaddr, pdev);
5106 break;
5a5e4443
HW		 5107
5108 case RTL_GIGA_MAC_VER_29:
5109 rtl_hw_start_8105e_1(ioaddr, pdev);
5110 break;
5111 case RTL_GIGA_MAC_VER_30:
5112 rtl_hw_start_8105e_2(ioaddr, pdev);
5113 break;
cdf1a608
FR		 5114 }
5115
d24e9aaf 5116 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5117
f0298f81 5118 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 5119
6f0333b8 5120 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 5121
d24e9aaf 5122 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 5123 RTL_W16(CPlusCmd, tp->cp_cmd);
5124
5125 RTL_W16(IntrMitigate, 0x0000);
5126
5127 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5128
5129 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5130 rtl_set_rx_tx_config_registers(tp);
5131
cdf1a608
FR		 5132 RTL_R8(IntrMask);
5133
cdf1a608
FR		 5134 rtl_set_rx_mode(dev);
5135
5136 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 5137
0e485150 5138 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 5139}
5140
5141static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5142{
d58d46b5
FR		 5143 struct rtl8169_private *tp = netdev_priv(dev);
5144
5145 if (new_mtu < ETH_ZLEN ||
5146 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5147 return -EINVAL;
5148
d58d46b5
FR		 5149 if (new_mtu > ETH_DATA_LEN)
5150 rtl_hw_jumbo_enable(tp);
5151 else
5152 rtl_hw_jumbo_disable(tp);
5153
1da177e4 5154 dev->mtu = new_mtu;
350fb32a
MM		 5155 netdev_update_features(dev);
5156
323bb685 5157 return 0;
1da177e4
LT		 5158}
5159
5160static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5161{
95e0918d 5162 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5163 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5164}
5165
6f0333b8
ED		 5166static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5167 void **data_buff, struct RxDesc *desc)
1da177e4 5168{
48addcc9 5169 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5170 DMA_FROM_DEVICE);
48addcc9 5171
6f0333b8
ED		 5172 kfree(*data_buff);
5173 *data_buff = NULL;
1da177e4
LT		 5174 rtl8169_make_unusable_by_asic(desc);
5175}
5176
5177static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5178{
5179 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5180
5181 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5182}
5183
5184static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5185 u32 rx_buf_sz)
5186{
5187 desc->addr = cpu_to_le64(mapping);
5188 wmb();
5189 rtl8169_mark_to_asic(desc, rx_buf_sz);
5190}
5191
6f0333b8
ED		 5192static inline void *rtl8169_align(void *data)
5193{
5194 return (void *)ALIGN((long)data, 16);
5195}
5196
0ecbe1ca
SG		 5197static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5198 struct RxDesc *desc)
1da177e4 5199{
6f0333b8 5200 void *data;
1da177e4 5201 dma_addr_t mapping;
48addcc9 5202 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5203 struct net_device *dev = tp->dev;
6f0333b8 5204 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5205
6f0333b8
ED		 5206 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5207 if (!data)
5208 return NULL;
e9f63f30 5209
6f0333b8
ED		 5210 if (rtl8169_align(data) != data) {
5211 kfree(data);
5212 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5213 if (!data)
5214 return NULL;
5215 }
3eafe507 5216
48addcc9 5217 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5218 DMA_FROM_DEVICE);
d827d86b
SG		 5219 if (unlikely(dma_mapping_error(d, mapping))) {
5220 if (net_ratelimit())
5221 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5222 goto err_out;
d827d86b 5223 }
1da177e4
LT		 5224
5225 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5226 return data;
3eafe507
SG		 5227
5228err_out:
5229 kfree(data);
5230 return NULL;
1da177e4
LT		 5231}
5232
5233static void rtl8169_rx_clear(struct rtl8169_private *tp)
5234{
07d3f51f 5235 unsigned int i;
1da177e4
LT		 5236
5237 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5238 if (tp->Rx_databuff[i]) {
5239 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5240 tp->RxDescArray + i);
5241 }
5242 }
5243}
5244
0ecbe1ca 5245static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5246{
0ecbe1ca
SG		 5247 desc->opts1 |= cpu_to_le32(RingEnd);
5248}
5b0384f4 5249
0ecbe1ca
SG		 5250static int rtl8169_rx_fill(struct rtl8169_private *tp)
5251{
5252 unsigned int i;
1da177e4 5253
0ecbe1ca
SG		 5254 for (i = 0; i < NUM_RX_DESC; i++) {
5255 void *data;
4ae47c2d 5256
6f0333b8 5257 if (tp->Rx_databuff[i])
1da177e4 5258 continue;
bcf0bf90 5259
0ecbe1ca 5260 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5261 if (!data) {
5262 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5263 goto err_out;
6f0333b8
ED		 5264 }
5265 tp->Rx_databuff[i] = data;
1da177e4 5266 }
1da177e4 5267
0ecbe1ca
SG		 5268 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5269 return 0;
5270
5271err_out:
5272 rtl8169_rx_clear(tp);
5273 return -ENOMEM;
1da177e4
LT		 5274}
5275
1da177e4
LT		 5276static int rtl8169_init_ring(struct net_device *dev)
5277{
5278 struct rtl8169_private *tp = netdev_priv(dev);
5279
5280 rtl8169_init_ring_indexes(tp);
5281
5282 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5283 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5284
0ecbe1ca 5285 return rtl8169_rx_fill(tp);
1da177e4
LT		 5286}
5287
48addcc9 5288static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5289 struct TxDesc *desc)
5290{
5291 unsigned int len = tx_skb->len;
5292
48addcc9
SG		 5293 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5294
1da177e4
LT		 5295 desc->opts1 = 0x00;
5296 desc->opts2 = 0x00;
5297 desc->addr = 0x00;
5298 tx_skb->len = 0;
5299}
5300
3eafe507
SG		 5301static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5302 unsigned int n)
1da177e4
LT		 5303{
5304 unsigned int i;
5305
3eafe507
SG		 5306 for (i = 0; i < n; i++) {
5307 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5308 struct ring_info *tx_skb = tp->tx_skb + entry;
5309 unsigned int len = tx_skb->len;
5310
5311 if (len) {
5312 struct sk_buff *skb = tx_skb->skb;
5313
48addcc9 5314 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5315 tp->TxDescArray + entry);
5316 if (skb) {
cac4b22f 5317 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5318 dev_kfree_skb(skb);
5319 tx_skb->skb = NULL;
5320 }
1da177e4
LT		 5321 }
5322 }
3eafe507
SG		 5323}
5324
5325static void rtl8169_tx_clear(struct rtl8169_private *tp)
5326{
5327 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5328 tp->cur_tx = tp->dirty_tx = 0;
5329}
5330
c4028958 5331static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 5332{
5333 struct rtl8169_private *tp = netdev_priv(dev);
5334
c4028958 5335 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 5336 schedule_delayed_work(&tp->task, 4);
5337}
5338
5339static void rtl8169_wait_for_quiescence(struct net_device *dev)
5340{
5341 struct rtl8169_private *tp = netdev_priv(dev);
5342 void __iomem *ioaddr = tp->mmio_addr;
5343
5344 synchronize_irq(dev->irq);
5345
5346 /* Wait for any pending NAPI task to complete */
bea3348e 5347 napi_disable(&tp->napi);
1da177e4 5348
811fd301 5349 rtl8169_irq_mask_and_ack(tp);
1da177e4 5350
d1d08d12
DM		 5351 tp->intr_mask = 0xffff;
5352 RTL_W16(IntrMask, tp->intr_event);
bea3348e 5353 napi_enable(&tp->napi);
1da177e4
LT		 5354}
5355
c4028958 5356static void rtl8169_reset_task(struct work_struct *work)
1da177e4 5357{
c4028958
DH		 5358 struct rtl8169_private *tp =
5359 container_of(work, struct rtl8169_private, task.work);
5360 struct net_device *dev = tp->dev;
56de414c 5361 int i;
1da177e4 5362
eb2a021c
FR		 5363 rtnl_lock();
5364
1da177e4 5365 if (!netif_running(dev))
eb2a021c 5366 goto out_unlock;
1da177e4 5367
c7c2c39b 5368 rtl8169_hw_reset(tp);
5369
1da177e4
LT		 5370 rtl8169_wait_for_quiescence(dev);
5371
56de414c
FR		 5372 for (i = 0; i < NUM_RX_DESC; i++)
5373 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5374
1da177e4 5375 rtl8169_tx_clear(tp);
c7c2c39b 5376 rtl8169_init_ring_indexes(tp);
1da177e4 5377
56de414c
FR		 5378 rtl_hw_start(dev);
5379 netif_wake_queue(dev);
5380 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
eb2a021c
FR		 5381
5382out_unlock:
5383 rtnl_unlock();
1da177e4
LT		 5384}
5385
5386static void rtl8169_tx_timeout(struct net_device *dev)
5387{
1da177e4
LT		 5388 rtl8169_schedule_work(dev, rtl8169_reset_task);
5389}
5390
5391static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5392 u32 *opts)
1da177e4
LT		 5393{
5394 struct skb_shared_info *info = skb_shinfo(skb);
5395 unsigned int cur_frag, entry;
a6343afb 5396 struct TxDesc * uninitialized_var(txd);
48addcc9 5397 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5398
5399 entry = tp->cur_tx;
5400 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5401 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5402 dma_addr_t mapping;
5403 u32 status, len;
5404 void *addr;
5405
5406 entry = (entry + 1) % NUM_TX_DESC;
5407
5408 txd = tp->TxDescArray + entry;
9e903e08 5409 len = skb_frag_size(frag);
929f6189 5410 addr = skb_frag_address(frag);
48addcc9 5411 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5412 if (unlikely(dma_mapping_error(d, mapping))) {
5413 if (net_ratelimit())
5414 netif_err(tp, drv, tp->dev,
5415 "Failed to map TX fragments DMA!\n");
3eafe507 5416 goto err_out;
d827d86b 5417 }
1da177e4 5418
cecb5fd7 5419 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5420 status = opts[0] | len |
5421 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5422
5423 txd->opts1 = cpu_to_le32(status);
2b7b4318 5424 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5425 txd->addr = cpu_to_le64(mapping);
5426
5427 tp->tx_skb[entry].len = len;
5428 }
5429
5430 if (cur_frag) {
5431 tp->tx_skb[entry].skb = skb;
5432 txd->opts1 |= cpu_to_le32(LastFrag);
5433 }
5434
5435 return cur_frag;
3eafe507
SG		 5436
5437err_out:
5438 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5439 return -EIO;
1da177e4
LT		 5440}
5441
2b7b4318
FR		 5442static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5443 struct sk_buff *skb, u32 *opts)
1da177e4 5444{
2b7b4318 5445 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5446 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5447 int offset = info->opts_offset;
350fb32a 5448
2b7b4318
FR		 5449 if (mss) {
5450 opts[0] |= TD_LSO;
5451 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5452 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5453 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5454
5455 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5456 opts[offset] |= info->checksum.tcp;
1da177e4 5457 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5458 opts[offset] |= info->checksum.udp;
5459 else
5460 WARN_ON_ONCE(1);
1da177e4 5461 }
1da177e4
LT		 5462}
5463
61357325
SH		 5464static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5465 struct net_device *dev)
1da177e4
LT		 5466{
5467 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5468 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5469 struct TxDesc *txd = tp->TxDescArray + entry;
5470 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5471 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5472 dma_addr_t mapping;
5473 u32 status, len;
2b7b4318 5474 u32 opts[2];
3eafe507 5475 int frags;
5b0384f4 5476
1da177e4 5477 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 5478 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5479 goto err_stop_0;
1da177e4
LT		 5480 }
5481
5482 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5483 goto err_stop_0;
5484
5485 len = skb_headlen(skb);
48addcc9 5486 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5487 if (unlikely(dma_mapping_error(d, mapping))) {
5488 if (net_ratelimit())
5489 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5490 goto err_dma_0;
d827d86b 5491 }
3eafe507
SG		 5492
5493 tp->tx_skb[entry].len = len;
5494 txd->addr = cpu_to_le64(mapping);
1da177e4 5495
2b7b4318
FR		 5496 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5497 opts[0] = DescOwn;
1da177e4 5498
2b7b4318
FR		 5499 rtl8169_tso_csum(tp, skb, opts);
5500
5501 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5502 if (frags < 0)
5503 goto err_dma_1;
5504 else if (frags)
2b7b4318 5505 opts[0] |= FirstFrag;
3eafe507 5506 else {
2b7b4318 5507 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5508 tp->tx_skb[entry].skb = skb;
5509 }
5510
2b7b4318
FR		 5511 txd->opts2 = cpu_to_le32(opts[1]);
5512
1da177e4
LT		 5513 wmb();
5514
cecb5fd7 5515 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5516 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5517 txd->opts1 = cpu_to_le32(status);
5518
1da177e4
LT		 5519 tp->cur_tx += frags + 1;
5520
4c020a96 5521 wmb();
1da177e4 5522
cecb5fd7 5523 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 5524
5525 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5526 netif_stop_queue(dev);
5527 smp_rmb();
5528 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5529 netif_wake_queue(dev);
5530 }
5531
61357325 5532 return NETDEV_TX_OK;
1da177e4 5533
3eafe507 5534err_dma_1:
48addcc9 5535 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5536err_dma_0:
5537 dev_kfree_skb(skb);
5538 dev->stats.tx_dropped++;
5539 return NETDEV_TX_OK;
5540
5541err_stop_0:
1da177e4 5542 netif_stop_queue(dev);
cebf8cc7 5543 dev->stats.tx_dropped++;
61357325 5544 return NETDEV_TX_BUSY;
1da177e4
LT		 5545}
5546
5547static void rtl8169_pcierr_interrupt(struct net_device *dev)
5548{
5549 struct rtl8169_private *tp = netdev_priv(dev);
5550 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5551 u16 pci_status, pci_cmd;
5552
5553 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5554 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5555
bf82c189
JP		 5556 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5557 pci_cmd, pci_status);
1da177e4
LT		 5558
5559 /*
5560 * The recovery sequence below admits a very elaborated explanation:
5561 * - it seems to work;
d03902b8
FR		 5562 * - I did not see what else could be done;
5563 * - it makes iop3xx happy.
1da177e4
LT		 5564 *
5565 * Feel free to adjust to your needs.
5566 */
a27993f3 5567 if (pdev->broken_parity_status)
d03902b8
FR		 5568 pci_cmd &= ~PCI_COMMAND_PARITY;
5569 else
5570 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5571
5572 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5573
5574 pci_write_config_word(pdev, PCI_STATUS,
5575 pci_status & (PCI_STATUS_DETECTED_PARITY |
5576 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5577 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5578
5579 /* The infamous DAC f*ckup only happens at boot time */
5580 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5581 void __iomem *ioaddr = tp->mmio_addr;
5582
bf82c189 5583 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5584 tp->cp_cmd &= ~PCIDAC;
5585 RTL_W16(CPlusCmd, tp->cp_cmd);
5586 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5587 }
5588
e6de30d6 5589 rtl8169_hw_reset(tp);
d03902b8 5590
209e5ac8 5591 rtl8169_schedule_work(dev, rtl8169_reset_task);
1da177e4
LT		 5592}
5593
07d3f51f
FR		 5594static void rtl8169_tx_interrupt(struct net_device *dev,
5595 struct rtl8169_private *tp,
5596 void __iomem *ioaddr)
1da177e4
LT		 5597{
5598 unsigned int dirty_tx, tx_left;
5599
1da177e4
LT		 5600 dirty_tx = tp->dirty_tx;
5601 smp_rmb();
5602 tx_left = tp->cur_tx - dirty_tx;
5603
5604 while (tx_left > 0) {
5605 unsigned int entry = dirty_tx % NUM_TX_DESC;
5606 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5607 u32 status;
5608
5609 rmb();
5610 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5611 if (status & DescOwn)
5612 break;
5613
48addcc9
SG		 5614 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5615 tp->TxDescArray + entry);
1da177e4 5616 if (status & LastFrag) {
cac4b22f
SG		 5617 dev->stats.tx_packets++;
5618 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 5619 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5620 tx_skb->skb = NULL;
5621 }
5622 dirty_tx++;
5623 tx_left--;
5624 }
5625
5626 if (tp->dirty_tx != dirty_tx) {
5627 tp->dirty_tx = dirty_tx;
5628 smp_wmb();
5629 if (netif_queue_stopped(dev) &&
5630 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5631 netif_wake_queue(dev);
5632 }
d78ae2dc
FR		 5633 /*
5634 * 8168 hack: TxPoll requests are lost when the Tx packets are
5635 * too close. Let's kick an extra TxPoll request when a burst
5636 * of start_xmit activity is detected (if it is not detected,
5637 * it is slow enough). -- FR
5638 */
5639 smp_rmb();
5640 if (tp->cur_tx != dirty_tx)
5641 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 5642 }
5643}
5644
126fa4b9
FR		 5645static inline int rtl8169_fragmented_frame(u32 status)
5646{
5647 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5648}
5649
adea1ac7 5650static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5651{
1da177e4
LT		 5652 u32 status = opts1 & RxProtoMask;
5653
5654 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5655 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5656 skb->ip_summed = CHECKSUM_UNNECESSARY;
5657 else
bc8acf2c 5658 skb_checksum_none_assert(skb);
1da177e4
LT		 5659}
5660
6f0333b8
ED		 5661static struct sk_buff *rtl8169_try_rx_copy(void *data,
5662 struct rtl8169_private *tp,
5663 int pkt_size,
5664 dma_addr_t addr)
1da177e4 5665{
b449655f 5666 struct sk_buff *skb;
48addcc9 5667 struct device *d = &tp->pci_dev->dev;
b449655f 5668
6f0333b8 5669 data = rtl8169_align(data);
48addcc9 5670 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 5671 prefetch(data);
5672 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5673 if (skb)
5674 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 5675 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5676
6f0333b8 5677 return skb;
1da177e4
LT		 5678}
5679
07d3f51f
FR		 5680static int rtl8169_rx_interrupt(struct net_device *dev,
5681 struct rtl8169_private *tp,
bea3348e 5682 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 5683{
5684 unsigned int cur_rx, rx_left;
6f0333b8 5685 unsigned int count;
1da177e4 5686
1da177e4
LT		 5687 cur_rx = tp->cur_rx;
5688 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 5689 rx_left = min(rx_left, budget);
1da177e4 5690
4dcb7d33 5691 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 5692 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 5693 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 5694 u32 status;
5695
5696 rmb();
e03f33af 5697 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 5698
5699 if (status & DescOwn)
5700 break;
4dcb7d33 5701 if (unlikely(status & RxRES)) {
bf82c189
JP		 5702 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5703 status);
cebf8cc7 5704 dev->stats.rx_errors++;
1da177e4 5705 if (status & (RxRWT | RxRUNT))
cebf8cc7 5706 dev->stats.rx_length_errors++;
1da177e4 5707 if (status & RxCRC)
cebf8cc7 5708 dev->stats.rx_crc_errors++;
9dccf611
FR		 5709 if (status & RxFOVF) {
5710 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 5711 dev->stats.rx_fifo_errors++;
9dccf611 5712 }
6f0333b8 5713 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 5714 } else {
6f0333b8 5715 struct sk_buff *skb;
b449655f 5716 dma_addr_t addr = le64_to_cpu(desc->addr);
deb9d93c 5717 int pkt_size = (status & 0x00003fff) - 4;
1da177e4 5718
126fa4b9
FR		 5719 /*
5720 * The driver does not support incoming fragmented
5721 * frames. They are seen as a symptom of over-mtu
5722 * sized frames.
5723 */
5724 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 5725 dev->stats.rx_dropped++;
5726 dev->stats.rx_length_errors++;
6f0333b8 5727 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 5728 continue;
126fa4b9
FR		 5729 }
5730
6f0333b8
ED		 5731 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5732 tp, pkt_size, addr);
5733 rtl8169_mark_to_asic(desc, rx_buf_sz);
5734 if (!skb) {
5735 dev->stats.rx_dropped++;
5736 continue;
1da177e4
LT		 5737 }
5738
adea1ac7 5739 rtl8169_rx_csum(skb, status);
1da177e4
LT		 5740 skb_put(skb, pkt_size);
5741 skb->protocol = eth_type_trans(skb, dev);
5742
7a8fc77b
FR		 5743 rtl8169_rx_vlan_tag(desc, skb);
5744
56de414c 5745 napi_gro_receive(&tp->napi, skb);
1da177e4 5746
cebf8cc7
FR		 5747 dev->stats.rx_bytes += pkt_size;
5748 dev->stats.rx_packets++;
1da177e4 5749 }
6dccd16b
FR		 5750
5751 /* Work around for AMD plateform. */
95e0918d 5752 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 5753 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5754 desc->opts2 = 0;
5755 cur_rx++;
5756 }
1da177e4
LT		 5757 }
5758
5759 count = cur_rx - tp->cur_rx;
5760 tp->cur_rx = cur_rx;
5761
6f0333b8 5762 tp->dirty_rx += count;
1da177e4
LT		 5763
5764 return count;
5765}
5766
07d3f51f 5767static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5768{
07d3f51f 5769 struct net_device *dev = dev_instance;
1da177e4 5770 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5771 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5772 int handled = 0;
865c652d 5773 int status;
1da177e4 5774
f11a377b
DD		 5775 /* loop handling interrupts until we have no new ones or
5776 * we hit a invalid/hotplug case.
5777 */
865c652d 5778 status = RTL_R16(IntrStatus);
f11a377b 5779 while (status && status != 0xffff) {
811fd301 5780 status &= tp->intr_event;
5781 if (!status)
5782 break;
5783
f11a377b 5784 handled = 1;
1da177e4 5785
f11a377b
DD		 5786 /* Handle all of the error cases first. These will reset
5787 * the chip, so just exit the loop.
5788 */
5789 if (unlikely(!netif_running(dev))) {
92fc43b4 5790 rtl8169_hw_reset(tp);
f11a377b
DD		 5791 break;
5792 }
1da177e4 5793
1519e57f
FR		 5794 if (unlikely(status & RxFIFOOver)) {
5795 switch (tp->mac_version) {
5796 /* Work around for rx fifo overflow */
5797 case RTL_GIGA_MAC_VER_11:
1519e57f
FR		 5798 netif_stop_queue(dev);
5799 rtl8169_tx_timeout(dev);
5800 goto done;
1519e57f
FR		 5801 default:
5802 break;
5803 }
f11a377b 5804 }
1da177e4 5805
f11a377b
DD		 5806 if (unlikely(status & SYSErr)) {
5807 rtl8169_pcierr_interrupt(dev);
5808 break;
5809 }
1da177e4 5810
f11a377b 5811 if (status & LinkChg)
e4fbce74 5812 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 5813
f11a377b
DD		 5814 /* We need to see the lastest version of tp->intr_mask to
5815 * avoid ignoring an MSI interrupt and having to wait for
5816 * another event which may never come.
5817 */
5818 smp_rmb();
5819 if (status & tp->intr_mask & tp->napi_event) {
5820 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5821 tp->intr_mask = ~tp->napi_event;
5822
5823 if (likely(napi_schedule_prep(&tp->napi)))
5824 __napi_schedule(&tp->napi);
bf82c189
JP		 5825 else
5826 netif_info(tp, intr, dev,
5827 "interrupt %04x in poll\n", status);
f11a377b 5828 }
1da177e4 5829
f11a377b
DD		 5830 /* We only get a new MSI interrupt when all active irq
5831 * sources on the chip have been acknowledged. So, ack
5832 * everything we've seen and check if new sources have become
5833 * active to avoid blocking all interrupts from the chip.
5834 */
5835 RTL_W16(IntrStatus,
5836 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5837 status = RTL_R16(IntrStatus);
865c652d 5838 }
1519e57f 5839done:
1da177e4
LT		 5840 return IRQ_RETVAL(handled);
5841}
5842
bea3348e 5843static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5844{
bea3348e
SH		 5845 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5846 struct net_device *dev = tp->dev;
1da177e4 5847 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 5848 int work_done;
1da177e4 5849
bea3348e 5850 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 5851 rtl8169_tx_interrupt(dev, tp, ioaddr);
5852
bea3348e 5853 if (work_done < budget) {
288379f0 5854 napi_complete(napi);
f11a377b
DD		 5855
5856 /* We need for force the visibility of tp->intr_mask
5857 * for other CPUs, as we can loose an MSI interrupt
5858 * and potentially wait for a retransmit timeout if we don't.
5859 * The posted write to IntrMask is safe, as it will
5860 * eventually make it to the chip and we won't loose anything
5861 * until it does.
1da177e4 5862 */
f11a377b 5863 tp->intr_mask = 0xffff;
4c020a96 5864 wmb();
0e485150 5865 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 5866 }
5867
bea3348e 5868 return work_done;
1da177e4 5869}
1da177e4 5870
523a6094
FR		 5871static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5872{
5873 struct rtl8169_private *tp = netdev_priv(dev);
5874
5875 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5876 return;
5877
5878 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5879 RTL_W32(RxMissed, 0);
5880}
5881
1da177e4
LT		 5882static void rtl8169_down(struct net_device *dev)
5883{
5884 struct rtl8169_private *tp = netdev_priv(dev);
5885 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5886
4876cc1e 5887 del_timer_sync(&tp->timer);
1da177e4
LT		 5888
5889 netif_stop_queue(dev);
5890
93dd79e8 5891 napi_disable(&tp->napi);
93dd79e8 5892
1da177e4
LT		 5893 spin_lock_irq(&tp->lock);
5894
92fc43b4 5895 rtl8169_hw_reset(tp);
323bb685
SG		 5896 /*
5897 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 5898 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5899 * and napi is disabled (rtl8169_poll).
323bb685 5900 */
523a6094 5901 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5902
5903 spin_unlock_irq(&tp->lock);
5904
5905 synchronize_irq(dev->irq);
5906
1da177e4 5907 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 5908 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 5909
1da177e4
LT		 5910 rtl8169_tx_clear(tp);
5911
5912 rtl8169_rx_clear(tp);
065c27c1 5913
5914 rtl_pll_power_down(tp);
1da177e4
LT		 5915}
5916
5917static int rtl8169_close(struct net_device *dev)
5918{
5919 struct rtl8169_private *tp = netdev_priv(dev);
5920 struct pci_dev *pdev = tp->pci_dev;
5921
e1759441
RW		 5922 pm_runtime_get_sync(&pdev->dev);
5923
cecb5fd7 5924 /* Update counters before going down */
355423d0
IV		 5925 rtl8169_update_counters(dev);
5926
1da177e4
LT		 5927 rtl8169_down(dev);
5928
5929 free_irq(dev->irq, dev);
5930
82553bb6
SG		 5931 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5932 tp->RxPhyAddr);
5933 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5934 tp->TxPhyAddr);
1da177e4
LT		 5935 tp->TxDescArray = NULL;
5936 tp->RxDescArray = NULL;
5937
e1759441
RW		 5938 pm_runtime_put_sync(&pdev->dev);
5939
1da177e4
LT		 5940 return 0;
5941}
5942
07ce4064 5943static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5944{
5945 struct rtl8169_private *tp = netdev_priv(dev);
5946 void __iomem *ioaddr = tp->mmio_addr;
5947 unsigned long flags;
5948 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 5949 int rx_mode;
1da177e4
LT		 5950 u32 tmp = 0;
5951
5952 if (dev->flags & IFF_PROMISC) {
5953 /* Unconditionally log net taps. */
bf82c189 5954 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 5955 rx_mode =
5956 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5957 AcceptAllPhys;
5958 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 5959 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 5960 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 5961 /* Too many to filter perfectly -- accept all multicasts. */
5962 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5963 mc_filter[1] = mc_filter[0] = 0xffffffff;
5964 } else {
22bedad3 5965 struct netdev_hw_addr *ha;
07d3f51f 5966
1da177e4
LT		 5967 rx_mode = AcceptBroadcast | AcceptMyPhys;
5968 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 5969 netdev_for_each_mc_addr(ha, dev) {
5970 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 5971 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5972 rx_mode |= AcceptMulticast;
5973 }
5974 }
5975
5976 spin_lock_irqsave(&tp->lock, flags);
5977
1687b566 5978 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
1da177e4 5979
f887cce8 5980 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 5981 u32 data = mc_filter[0];
5982
5983 mc_filter[0] = swab32(mc_filter[1]);
5984 mc_filter[1] = swab32(data);
bcf0bf90
FR		 5985 }
5986
1da177e4 5987 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 5988 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 5989
57a9f236
FR		 5990 RTL_W32(RxConfig, tmp);
5991
1da177e4
LT		 5992 spin_unlock_irqrestore(&tp->lock, flags);
5993}
5994
5995/**
5996 * rtl8169_get_stats - Get rtl8169 read/write statistics
5997 * @dev: The Ethernet Device to get statistics for
5998 *
5999 * Get TX/RX statistics for rtl8169
6000 */
6001static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
6002{
6003 struct rtl8169_private *tp = netdev_priv(dev);
6004 void __iomem *ioaddr = tp->mmio_addr;
6005 unsigned long flags;
6006
6007 if (netif_running(dev)) {
6008 spin_lock_irqsave(&tp->lock, flags);
523a6094 6009 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 6010 spin_unlock_irqrestore(&tp->lock, flags);
6011 }
5b0384f4 6012
cebf8cc7 6013 return &dev->stats;
1da177e4
LT		 6014}
6015
861ab440 6016static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6017{
065c27c1 6018 struct rtl8169_private *tp = netdev_priv(dev);
6019
5d06a99f 6020 if (!netif_running(dev))
861ab440 6021 return;
5d06a99f 6022
065c27c1 6023 rtl_pll_power_down(tp);
6024
5d06a99f
FR		 6025 netif_device_detach(dev);
6026 netif_stop_queue(dev);
861ab440
RW		 6027}
6028
6029#ifdef CONFIG_PM
6030
6031static int rtl8169_suspend(struct device *device)
6032{
6033 struct pci_dev *pdev = to_pci_dev(device);
6034 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6035
861ab440 6036 rtl8169_net_suspend(dev);
1371fa6d 6037
5d06a99f
FR		 6038 return 0;
6039}
6040
e1759441
RW		 6041static void __rtl8169_resume(struct net_device *dev)
6042{
065c27c1 6043 struct rtl8169_private *tp = netdev_priv(dev);
6044
e1759441 6045 netif_device_attach(dev);
065c27c1 6046
6047 rtl_pll_power_up(tp);
6048
e1759441
RW		 6049 rtl8169_schedule_work(dev, rtl8169_reset_task);
6050}
6051
861ab440 6052static int rtl8169_resume(struct device *device)
5d06a99f 6053{
861ab440 6054 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6055 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6056 struct rtl8169_private *tp = netdev_priv(dev);
6057
6058 rtl8169_init_phy(dev, tp);
5d06a99f 6059
e1759441
RW		 6060 if (netif_running(dev))
6061 __rtl8169_resume(dev);
5d06a99f 6062
e1759441
RW		 6063 return 0;
6064}
6065
6066static int rtl8169_runtime_suspend(struct device *device)
6067{
6068 struct pci_dev *pdev = to_pci_dev(device);
6069 struct net_device *dev = pci_get_drvdata(pdev);
6070 struct rtl8169_private *tp = netdev_priv(dev);
6071
6072 if (!tp->TxDescArray)
6073 return 0;
6074
6075 spin_lock_irq(&tp->lock);
6076 tp->saved_wolopts = __rtl8169_get_wol(tp);
6077 __rtl8169_set_wol(tp, WAKE_ANY);
6078 spin_unlock_irq(&tp->lock);
6079
6080 rtl8169_net_suspend(dev);
6081
6082 return 0;
6083}
6084
6085static int rtl8169_runtime_resume(struct device *device)
6086{
6087 struct pci_dev *pdev = to_pci_dev(device);
6088 struct net_device *dev = pci_get_drvdata(pdev);
6089 struct rtl8169_private *tp = netdev_priv(dev);
6090
6091 if (!tp->TxDescArray)
6092 return 0;
6093
6094 spin_lock_irq(&tp->lock);
6095 __rtl8169_set_wol(tp, tp->saved_wolopts);
6096 tp->saved_wolopts = 0;
6097 spin_unlock_irq(&tp->lock);
6098
fccec10b
SG		 6099 rtl8169_init_phy(dev, tp);
6100
e1759441 6101 __rtl8169_resume(dev);
5d06a99f 6102
5d06a99f
FR		 6103 return 0;
6104}
6105
e1759441
RW		 6106static int rtl8169_runtime_idle(struct device *device)
6107{
6108 struct pci_dev *pdev = to_pci_dev(device);
6109 struct net_device *dev = pci_get_drvdata(pdev);
6110 struct rtl8169_private *tp = netdev_priv(dev);
6111
e4fbce74 6112 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6113}
6114
47145210 6115static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6116 .suspend = rtl8169_suspend,
6117 .resume = rtl8169_resume,
6118 .freeze = rtl8169_suspend,
6119 .thaw = rtl8169_resume,
6120 .poweroff = rtl8169_suspend,
6121 .restore = rtl8169_resume,
6122 .runtime_suspend = rtl8169_runtime_suspend,
6123 .runtime_resume = rtl8169_runtime_resume,
6124 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6125};
6126
6127#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6128
6129#else /* !CONFIG_PM */
6130
6131#define RTL8169_PM_OPS NULL
6132
6133#endif /* !CONFIG_PM */
6134
649b3b8c 6135static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6136{
6137 void __iomem *ioaddr = tp->mmio_addr;
6138
6139 /* WoL fails with 8168b when the receiver is disabled. */
6140 switch (tp->mac_version) {
6141 case RTL_GIGA_MAC_VER_11:
6142 case RTL_GIGA_MAC_VER_12:
6143 case RTL_GIGA_MAC_VER_17:
6144 pci_clear_master(tp->pci_dev);
6145
6146 RTL_W8(ChipCmd, CmdRxEnb);
6147 /* PCI commit */
6148 RTL_R8(ChipCmd);
6149 break;
6150 default:
6151 break;
6152 }
6153}
6154
1765f95d
FR		 6155static void rtl_shutdown(struct pci_dev *pdev)
6156{
861ab440 6157 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6158 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 6159
6160 rtl8169_net_suspend(dev);
1765f95d 6161
cecb5fd7 6162 /* Restore original MAC address */
cc098dc7
IV		 6163 rtl_rar_set(tp, dev->perm_addr);
6164
4bb3f522 6165 spin_lock_irq(&tp->lock);
6166
92fc43b4 6167 rtl8169_hw_reset(tp);
4bb3f522 6168
6169 spin_unlock_irq(&tp->lock);
6170
861ab440 6171 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6172 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6173 rtl_wol_suspend_quirk(tp);
6174 rtl_wol_shutdown_quirk(tp);
ca52efd5 6175 }
6176
861ab440
RW		 6177 pci_wake_from_d3(pdev, true);
6178 pci_set_power_state(pdev, PCI_D3hot);
6179 }
6180}
5d06a99f 6181
1da177e4
LT		 6182static struct pci_driver rtl8169_pci_driver = {
6183 .name = MODULENAME,
6184 .id_table = rtl8169_pci_tbl,
6185 .probe = rtl8169_init_one,
6186 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 6187 .shutdown = rtl_shutdown,
861ab440 6188 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 6189};
6190
07d3f51f 6191static int __init rtl8169_init_module(void)
1da177e4 6192{
29917620 6193 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 6194}
6195
07d3f51f 6196static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 6197{
6198 pci_unregister_driver(&rtl8169_pci_driver);
6199}
6200
6201module_init(rtl8169_init_module);
6202module_exit(rtl8169_cleanup_module);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git