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r8169: use phy_resume/phy_suspend
[thirdparty/kernel/stable.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
f1e911d5 19#include <linux/phy.h>
1da177e4
LT		 20#include <linux/if_vlan.h>
21#include <linux/crc32.h>
22#include <linux/in.h>
23#include <linux/ip.h>
24#include <linux/tcp.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
31#include <net/ip6_checksum.h>
1da177e4
LT		 32
33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4 37#define MODULENAME "r8169"
1da177e4 38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 43#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 44#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 46#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 47#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 48#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 49#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 50#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 51#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 52#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 53#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 54#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
55#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
56#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
57#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 58
b57b7e5a 59#define R8169_MSG_DEFAULT \
f0e837d9 60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 61
477206a0
JD		 62#define TX_SLOTS_AVAIL(tp) \
63 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
64
65/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
66#define TX_FRAGS_READY_FOR(tp,nr_frags) \
67 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 68
1da177e4
LT		 69/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
70 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 71static const int multicast_filter_limit = 32;
1da177e4 72
aee77e4a 73#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 74#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
75
76#define R8169_REGS_SIZE 256
1d0254dd 77#define R8169_RX_BUF_SIZE (SZ_16K - 1)
1da177e4 78#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 79#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 80#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
81#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
82
83#define RTL8169_TX_TIMEOUT (6*HZ)
1da177e4
LT		 84
85/* write/read MMIO register */
1ef7286e
AS		 86#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
87#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
88#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
89#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
90#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
91#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
1da177e4
LT		 92
93enum mac_version {
85bffe6c
FR		 94 RTL_GIGA_MAC_VER_01 = 0,
95 RTL_GIGA_MAC_VER_02,
96 RTL_GIGA_MAC_VER_03,
97 RTL_GIGA_MAC_VER_04,
98 RTL_GIGA_MAC_VER_05,
99 RTL_GIGA_MAC_VER_06,
100 RTL_GIGA_MAC_VER_07,
101 RTL_GIGA_MAC_VER_08,
102 RTL_GIGA_MAC_VER_09,
103 RTL_GIGA_MAC_VER_10,
104 RTL_GIGA_MAC_VER_11,
105 RTL_GIGA_MAC_VER_12,
106 RTL_GIGA_MAC_VER_13,
107 RTL_GIGA_MAC_VER_14,
108 RTL_GIGA_MAC_VER_15,
109 RTL_GIGA_MAC_VER_16,
110 RTL_GIGA_MAC_VER_17,
111 RTL_GIGA_MAC_VER_18,
112 RTL_GIGA_MAC_VER_19,
113 RTL_GIGA_MAC_VER_20,
114 RTL_GIGA_MAC_VER_21,
115 RTL_GIGA_MAC_VER_22,
116 RTL_GIGA_MAC_VER_23,
117 RTL_GIGA_MAC_VER_24,
118 RTL_GIGA_MAC_VER_25,
119 RTL_GIGA_MAC_VER_26,
120 RTL_GIGA_MAC_VER_27,
121 RTL_GIGA_MAC_VER_28,
122 RTL_GIGA_MAC_VER_29,
123 RTL_GIGA_MAC_VER_30,
124 RTL_GIGA_MAC_VER_31,
125 RTL_GIGA_MAC_VER_32,
126 RTL_GIGA_MAC_VER_33,
70090424 127 RTL_GIGA_MAC_VER_34,
c2218925
HW		 128 RTL_GIGA_MAC_VER_35,
129 RTL_GIGA_MAC_VER_36,
7e18dca1 130 RTL_GIGA_MAC_VER_37,
b3d7b2f2 131 RTL_GIGA_MAC_VER_38,
5598bfe5 132 RTL_GIGA_MAC_VER_39,
c558386b
HW		 133 RTL_GIGA_MAC_VER_40,
134 RTL_GIGA_MAC_VER_41,
57538c4a 135 RTL_GIGA_MAC_VER_42,
58152cd4 136 RTL_GIGA_MAC_VER_43,
45dd95c4 137 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 138 RTL_GIGA_MAC_VER_45,
139 RTL_GIGA_MAC_VER_46,
140 RTL_GIGA_MAC_VER_47,
141 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 142 RTL_GIGA_MAC_VER_49,
143 RTL_GIGA_MAC_VER_50,
144 RTL_GIGA_MAC_VER_51,
85bffe6c 145 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 146};
147
2b7b4318
FR		 148enum rtl_tx_desc_version {
149 RTL_TD_0 = 0,
150 RTL_TD_1 = 1,
151};
152
d58d46b5
FR		 153#define JUMBO_1K ETH_DATA_LEN
154#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
155#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
156#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
157#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
158
6ed0e08f 159#define _R(NAME,TD,FW,SZ) { \
d58d46b5
FR		 160 .name = NAME, \
161 .txd_version = TD, \
162 .fw_name = FW, \
163 .jumbo_max = SZ, \
d58d46b5 164}
1da177e4 165
3c6bee1d 166static const struct {
1da177e4 167 const char *name;
2b7b4318 168 enum rtl_tx_desc_version txd_version;
953a12cc 169 const char *fw_name;
d58d46b5 170 u16 jumbo_max;
85bffe6c
FR		 171} rtl_chip_infos[] = {
172 /* PCI devices. */
173 [RTL_GIGA_MAC_VER_01] =
6ed0e08f 174 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 175 [RTL_GIGA_MAC_VER_02] =
6ed0e08f 176 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 177 [RTL_GIGA_MAC_VER_03] =
6ed0e08f 178 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 179 [RTL_GIGA_MAC_VER_04] =
6ed0e08f 180 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 181 [RTL_GIGA_MAC_VER_05] =
6ed0e08f 182 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 183 [RTL_GIGA_MAC_VER_06] =
6ed0e08f 184 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c
FR		 185 /* PCI-E devices. */
186 [RTL_GIGA_MAC_VER_07] =
6ed0e08f 187 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
85bffe6c 188 [RTL_GIGA_MAC_VER_08] =
6ed0e08f 189 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
85bffe6c 190 [RTL_GIGA_MAC_VER_09] =
6ed0e08f 191 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
85bffe6c 192 [RTL_GIGA_MAC_VER_10] =
6ed0e08f 193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 194 [RTL_GIGA_MAC_VER_11] =
6ed0e08f 195 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
85bffe6c 196 [RTL_GIGA_MAC_VER_12] =
6ed0e08f 197 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
85bffe6c 198 [RTL_GIGA_MAC_VER_13] =
6ed0e08f 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 200 [RTL_GIGA_MAC_VER_14] =
6ed0e08f 201 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 202 [RTL_GIGA_MAC_VER_15] =
6ed0e08f 203 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 204 [RTL_GIGA_MAC_VER_16] =
6ed0e08f 205 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 206 [RTL_GIGA_MAC_VER_17] =
6ed0e08f 207 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
85bffe6c 208 [RTL_GIGA_MAC_VER_18] =
6ed0e08f 209 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 210 [RTL_GIGA_MAC_VER_19] =
6ed0e08f 211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 212 [RTL_GIGA_MAC_VER_20] =
6ed0e08f 213 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 214 [RTL_GIGA_MAC_VER_21] =
6ed0e08f 215 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 216 [RTL_GIGA_MAC_VER_22] =
6ed0e08f 217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 218 [RTL_GIGA_MAC_VER_23] =
6ed0e08f 219 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 220 [RTL_GIGA_MAC_VER_24] =
6ed0e08f 221 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 222 [RTL_GIGA_MAC_VER_25] =
6ed0e08f 223 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, JUMBO_9K),
85bffe6c 224 [RTL_GIGA_MAC_VER_26] =
6ed0e08f 225 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, JUMBO_9K),
85bffe6c 226 [RTL_GIGA_MAC_VER_27] =
6ed0e08f 227 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
85bffe6c 228 [RTL_GIGA_MAC_VER_28] =
6ed0e08f 229 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
85bffe6c 230 [RTL_GIGA_MAC_VER_29] =
6ed0e08f 231 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
85bffe6c 232 [RTL_GIGA_MAC_VER_30] =
6ed0e08f 233 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
85bffe6c 234 [RTL_GIGA_MAC_VER_31] =
6ed0e08f 235 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
85bffe6c 236 [RTL_GIGA_MAC_VER_32] =
6ed0e08f 237 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, JUMBO_9K),
85bffe6c 238 [RTL_GIGA_MAC_VER_33] =
6ed0e08f 239 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, JUMBO_9K),
70090424 240 [RTL_GIGA_MAC_VER_34] =
6ed0e08f 241 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, JUMBO_9K),
c2218925 242 [RTL_GIGA_MAC_VER_35] =
6ed0e08f 243 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, JUMBO_9K),
c2218925 244 [RTL_GIGA_MAC_VER_36] =
6ed0e08f 245 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, JUMBO_9K),
7e18dca1 246 [RTL_GIGA_MAC_VER_37] =
6ed0e08f 247 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1, JUMBO_1K),
b3d7b2f2 248 [RTL_GIGA_MAC_VER_38] =
6ed0e08f 249 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1, JUMBO_9K),
5598bfe5 250 [RTL_GIGA_MAC_VER_39] =
6ed0e08f 251 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1, JUMBO_1K),
c558386b 252 [RTL_GIGA_MAC_VER_40] =
6ed0e08f 253 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2, JUMBO_9K),
c558386b 254 [RTL_GIGA_MAC_VER_41] =
6ed0e08f 255 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K),
57538c4a 256 [RTL_GIGA_MAC_VER_42] =
6ed0e08f 257 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3, JUMBO_9K),
58152cd4 258 [RTL_GIGA_MAC_VER_43] =
6ed0e08f 259 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2, JUMBO_1K),
45dd95c4 260 [RTL_GIGA_MAC_VER_44] =
6ed0e08f 261 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2, JUMBO_9K),
6e1d0b89 262 [RTL_GIGA_MAC_VER_45] =
6ed0e08f 263 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1, JUMBO_9K),
6e1d0b89 264 [RTL_GIGA_MAC_VER_46] =
6ed0e08f 265 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2, JUMBO_9K),
6e1d0b89 266 [RTL_GIGA_MAC_VER_47] =
6ed0e08f 267 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1, JUMBO_1K),
6e1d0b89 268 [RTL_GIGA_MAC_VER_48] =
6ed0e08f 269 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2, JUMBO_1K),
935e2218 270 [RTL_GIGA_MAC_VER_49] =
6ed0e08f 271 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
935e2218 272 [RTL_GIGA_MAC_VER_50] =
6ed0e08f 273 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
935e2218 274 [RTL_GIGA_MAC_VER_51] =
6ed0e08f 275 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
953a12cc 276};
85bffe6c 277#undef _R
953a12cc 278
bcf0bf90
FR		 279enum cfg_version {
280 RTL_CFG_0 = 0x00,
281 RTL_CFG_1,
282 RTL_CFG_2
283};
284
9baa3c34 285static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 286 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 287 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
610c9087 288 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
d81bf551 289 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 290 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 291 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 292 { PCI_VENDOR_ID_DLINK, 0x4300,
293 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 294 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 295 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 296 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 297 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
298 { PCI_VENDOR_ID_LINKSYS, 0x1032,
299 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 300 { 0x0001, 0x8168,
301 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 302 {0,},
303};
304
305MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
306
27896c83 307static int use_dac = -1;
b57b7e5a
SH		 308static struct {
309 u32 msg_enable;
310} debug = { -1 };
1da177e4 311
07d3f51f
FR		 312enum rtl_registers {
313 MAC0 = 0, /* Ethernet hardware address. */
773d2021 314 MAC4 = 4,
07d3f51f
FR		 315 MAR0 = 8, /* Multicast filter. */
316 CounterAddrLow = 0x10,
317 CounterAddrHigh = 0x14,
318 TxDescStartAddrLow = 0x20,
319 TxDescStartAddrHigh = 0x24,
320 TxHDescStartAddrLow = 0x28,
321 TxHDescStartAddrHigh = 0x2c,
322 FLASH = 0x30,
323 ERSR = 0x36,
324 ChipCmd = 0x37,
325 TxPoll = 0x38,
326 IntrMask = 0x3c,
327 IntrStatus = 0x3e,
4f6b00e5 328
07d3f51f 329 TxConfig = 0x40,
4f6b00e5
HW		 330#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
331#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 332
4f6b00e5
HW		 333 RxConfig = 0x44,
334#define RX128_INT_EN (1 << 15) /* 8111c and later */
335#define RX_MULTI_EN (1 << 14) /* 8111c only */
336#define RXCFG_FIFO_SHIFT 13
337 /* No threshold before first PCI xfer */
338#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 339#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 340#define RXCFG_DMA_SHIFT 8
341 /* Unlimited maximum PCI burst. */
342#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 343
07d3f51f
FR		 344 RxMissed = 0x4c,
345 Cfg9346 = 0x50,
346 Config0 = 0x51,
347 Config1 = 0x52,
348 Config2 = 0x53,
d387b427
FR		 349#define PME_SIGNAL (1 << 5) /* 8168c and later */
350
07d3f51f
FR		 351 Config3 = 0x54,
352 Config4 = 0x55,
353 Config5 = 0x56,
354 MultiIntr = 0x5c,
355 PHYAR = 0x60,
07d3f51f
FR		 356 PHYstatus = 0x6c,
357 RxMaxSize = 0xda,
358 CPlusCmd = 0xe0,
359 IntrMitigate = 0xe2,
50970831
FR		 360
361#define RTL_COALESCE_MASK 0x0f
362#define RTL_COALESCE_SHIFT 4
363#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
364#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
365
07d3f51f
FR		 366 RxDescAddrLow = 0xe4,
367 RxDescAddrHigh = 0xe8,
f0298f81 368 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
369
370#define NoEarlyTx 0x3f /* Max value : no early transmit. */
371
372 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
373
374#define TxPacketMax (8064 >> 7)
3090bd9a 375#define EarlySize 0x27
f0298f81 376
07d3f51f
FR		 377 FuncEvent = 0xf0,
378 FuncEventMask = 0xf4,
379 FuncPresetState = 0xf8,
935e2218
CHL		 380 IBCR0 = 0xf8,
381 IBCR2 = 0xf9,
382 IBIMR0 = 0xfa,
383 IBISR0 = 0xfb,
07d3f51f 384 FuncForceEvent = 0xfc,
1da177e4
LT		 385};
386
f162a5d1
FR		 387enum rtl8168_8101_registers {
388 CSIDR = 0x64,
389 CSIAR = 0x68,
390#define CSIAR_FLAG 0x80000000
391#define CSIAR_WRITE_CMD 0x80000000
ff1d7331
HK		 392#define CSIAR_BYTE_ENABLE 0x0000f000
393#define CSIAR_ADDR_MASK 0x00000fff
065c27c1 394 PMCH = 0x6f,
f162a5d1
FR		 395 EPHYAR = 0x80,
396#define EPHYAR_FLAG 0x80000000
397#define EPHYAR_WRITE_CMD 0x80000000
398#define EPHYAR_REG_MASK 0x1f
399#define EPHYAR_REG_SHIFT 16
400#define EPHYAR_DATA_MASK 0xffff
5a5e4443 401 DLLPR = 0xd0,
4f6b00e5 402#define PFM_EN (1 << 6)
6e1d0b89 403#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 404 DBG_REG = 0xd1,
405#define FIX_NAK_1 (1 << 4)
406#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 407 TWSI = 0xd2,
408 MCU = 0xd3,
4f6b00e5 409#define NOW_IS_OOB (1 << 7)
c558386b
HW		 410#define TX_EMPTY (1 << 5)
411#define RX_EMPTY (1 << 4)
412#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 413#define EN_NDP (1 << 3)
414#define EN_OOB_RESET (1 << 2)
c558386b 415#define LINK_LIST_RDY (1 << 1)
daf9df6d 416 EFUSEAR = 0xdc,
417#define EFUSEAR_FLAG 0x80000000
418#define EFUSEAR_WRITE_CMD 0x80000000
419#define EFUSEAR_READ_CMD 0x00000000
420#define EFUSEAR_REG_MASK 0x03ff
421#define EFUSEAR_REG_SHIFT 8
422#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 423 MISC_1 = 0xf2,
424#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 425};
426
c0e45c1c 427enum rtl8168_registers {
4f6b00e5
HW		 428 LED_FREQ = 0x1a,
429 EEE_LED = 0x1b,
b646d900 430 ERIDR = 0x70,
431 ERIAR = 0x74,
432#define ERIAR_FLAG 0x80000000
433#define ERIAR_WRITE_CMD 0x80000000
434#define ERIAR_READ_CMD 0x00000000
435#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 436#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 437#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
438#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
439#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 440#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 441#define ERIAR_MASK_SHIFT 12
442#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
443#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 444#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 445#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 446#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 447 EPHY_RXER_NUM = 0x7c,
448 OCPDR = 0xb0, /* OCP GPHY access */
449#define OCPDR_WRITE_CMD 0x80000000
450#define OCPDR_READ_CMD 0x00000000
451#define OCPDR_REG_MASK 0x7f
452#define OCPDR_GPHY_REG_SHIFT 16
453#define OCPDR_DATA_MASK 0xffff
454 OCPAR = 0xb4,
455#define OCPAR_FLAG 0x80000000
456#define OCPAR_GPHY_WRITE_CMD 0x8000f060
457#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 458 GPHY_OCP = 0xb8,
01dc7fec 459 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
460 MISC = 0xf0, /* 8168e only. */
cecb5fd7 461#define TXPLA_RST (1 << 29)
5598bfe5 462#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 463#define PWM_EN (1 << 22)
c558386b 464#define RXDV_GATED_EN (1 << 19)
5598bfe5 465#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 466};
467
07d3f51f 468enum rtl_register_content {
1da177e4 469 /* InterruptStatusBits */
07d3f51f
FR		 470 SYSErr = 0x8000,
471 PCSTimeout = 0x4000,
472 SWInt = 0x0100,
473 TxDescUnavail = 0x0080,
474 RxFIFOOver = 0x0040,
475 LinkChg = 0x0020,
476 RxOverflow = 0x0010,
477 TxErr = 0x0008,
478 TxOK = 0x0004,
479 RxErr = 0x0002,
480 RxOK = 0x0001,
1da177e4
LT		 481
482 /* RxStatusDesc */
e03f33af 483 RxBOVF = (1 << 24),
9dccf611
FR		 484 RxFOVF = (1 << 23),
485 RxRWT = (1 << 22),
486 RxRES = (1 << 21),
487 RxRUNT = (1 << 20),
488 RxCRC = (1 << 19),
1da177e4
LT		 489
490 /* ChipCmdBits */
4f6b00e5 491 StopReq = 0x80,
07d3f51f
FR		 492 CmdReset = 0x10,
493 CmdRxEnb = 0x08,
494 CmdTxEnb = 0x04,
495 RxBufEmpty = 0x01,
1da177e4 496
275391a4
FR		 497 /* TXPoll register p.5 */
498 HPQ = 0x80, /* Poll cmd on the high prio queue */
499 NPQ = 0x40, /* Poll cmd on the low prio queue */
500 FSWInt = 0x01, /* Forced software interrupt */
501
1da177e4 502 /* Cfg9346Bits */
07d3f51f
FR		 503 Cfg9346_Lock = 0x00,
504 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 505
506 /* rx_mode_bits */
07d3f51f
FR		 507 AcceptErr = 0x20,
508 AcceptRunt = 0x10,
509 AcceptBroadcast = 0x08,
510 AcceptMulticast = 0x04,
511 AcceptMyPhys = 0x02,
512 AcceptAllPhys = 0x01,
1687b566 513#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 514
1da177e4
LT		 515 /* TxConfigBits */
516 TxInterFrameGapShift = 24,
517 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
518
5d06a99f 519 /* Config1 register p.24 */
f162a5d1
FR		 520 LEDS1 = (1 << 7),
521 LEDS0 = (1 << 6),
f162a5d1
FR		 522 Speed_down = (1 << 4),
523 MEMMAP = (1 << 3),
524 IOMAP = (1 << 2),
525 VPD = (1 << 1),
5d06a99f
FR		 526 PMEnable = (1 << 0), /* Power Management Enable */
527
6dccd16b 528 /* Config2 register p. 25 */
57538c4a 529 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 530 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 531 PCI_Clock_66MHz = 0x01,
532 PCI_Clock_33MHz = 0x00,
533
61a4dcc2
FR		 534 /* Config3 register p.25 */
535 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
536 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 537 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 538 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 539 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 540
d58d46b5
FR		 541 /* Config4 register */
542 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
543
5d06a99f 544 /* Config5 register p.27 */
61a4dcc2
FR		 545 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
546 MWF = (1 << 5), /* Accept Multicast wakeup frame */
547 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 548 Spi_en = (1 << 3),
61a4dcc2 549 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 550 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 551 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 552
1da177e4 553 /* CPlusCmd p.31 */
f162a5d1
FR		 554 EnableBist = (1 << 15), // 8168 8101
555 Mac_dbgo_oe = (1 << 14), // 8168 8101
556 Normal_mode = (1 << 13), // unused
557 Force_half_dup = (1 << 12), // 8168 8101
558 Force_rxflow_en = (1 << 11), // 8168 8101
559 Force_txflow_en = (1 << 10), // 8168 8101
560 Cxpl_dbg_sel = (1 << 9), // 8168 8101
561 ASF = (1 << 8), // 8168 8101
562 PktCntrDisable = (1 << 7), // 8168 8101
563 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 564 RxVlan = (1 << 6),
565 RxChkSum = (1 << 5),
566 PCIDAC = (1 << 4),
567 PCIMulRW = (1 << 3),
9a3c81fa 568#define INTT_MASK GENMASK(1, 0)
0e485150
FR		 569 INTT_0 = 0x0000, // 8168
570 INTT_1 = 0x0001, // 8168
571 INTT_2 = 0x0002, // 8168
572 INTT_3 = 0x0003, // 8168
1da177e4
LT		 573
574 /* rtl8169_PHYstatus */
07d3f51f
FR		 575 TBI_Enable = 0x80,
576 TxFlowCtrl = 0x40,
577 RxFlowCtrl = 0x20,
578 _1000bpsF = 0x10,
579 _100bps = 0x08,
580 _10bps = 0x04,
581 LinkStatus = 0x02,
582 FullDup = 0x01,
1da177e4 583
1da177e4 584 /* _TBICSRBit */
07d3f51f 585 TBILinkOK = 0x02000000,
d4a3a0fc 586
6e85d5ad
CV		 587 /* ResetCounterCommand */
588 CounterReset = 0x1,
589
d4a3a0fc 590 /* DumpCounterCommand */
07d3f51f 591 CounterDump = 0x8,
6e1d0b89
CHL		 592
593 /* magic enable v2 */
594 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 595};
596
2b7b4318
FR		 597enum rtl_desc_bit {
598 /* First doubleword. */
1da177e4
LT		 599 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
600 RingEnd = (1 << 30), /* End of descriptor ring */
601 FirstFrag = (1 << 29), /* First segment of a packet */
602 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 603};
604
605/* Generic case. */
606enum rtl_tx_desc_bit {
607 /* First doubleword. */
608 TD_LSO = (1 << 27), /* Large Send Offload */
609#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 610
2b7b4318
FR		 611 /* Second doubleword. */
612 TxVlanTag = (1 << 17), /* Add VLAN tag */
613};
614
615/* 8169, 8168b and 810x except 8102e. */
616enum rtl_tx_desc_bit_0 {
617 /* First doubleword. */
618#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
619 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
620 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
621 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
622};
623
624/* 8102e, 8168c and beyond. */
625enum rtl_tx_desc_bit_1 {
bdfa4ed6 626 /* First doubleword. */
627 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 628 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 629#define GTTCPHO_SHIFT 18
e974604b 630#define GTTCPHO_MAX 0x7fU
bdfa4ed6 631
2b7b4318 632 /* Second doubleword. */
e974604b 633#define TCPHO_SHIFT 18
634#define TCPHO_MAX 0x3ffU
2b7b4318 635#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 636 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
637 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 638 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
639 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
640};
1da177e4 641
2b7b4318 642enum rtl_rx_desc_bit {
1da177e4
LT		 643 /* Rx private */
644 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 645 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 646
647#define RxProtoUDP (PID1)
648#define RxProtoTCP (PID0)
649#define RxProtoIP (PID1 | PID0)
650#define RxProtoMask RxProtoIP
651
652 IPFail = (1 << 16), /* IP checksum failed */
653 UDPFail = (1 << 15), /* UDP/IP checksum failed */
654 TCPFail = (1 << 14), /* TCP/IP checksum failed */
655 RxVlanTag = (1 << 16), /* VLAN tag available */
656};
657
658#define RsvdMask 0x3fffc000
12d42c50 659#define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
1da177e4
LT		 660
661struct TxDesc {
6cccd6e7
REB		 662 __le32 opts1;
663 __le32 opts2;
664 __le64 addr;
1da177e4
LT		 665};
666
667struct RxDesc {
6cccd6e7
REB		 668 __le32 opts1;
669 __le32 opts2;
670 __le64 addr;
1da177e4
LT		 671};
672
673struct ring_info {
674 struct sk_buff *skb;
675 u32 len;
676 u8 __pad[sizeof(void *) - sizeof(u32)];
677};
678
355423d0
IV		 679struct rtl8169_counters {
680 __le64 tx_packets;
681 __le64 rx_packets;
682 __le64 tx_errors;
683 __le32 rx_errors;
684 __le16 rx_missed;
685 __le16 align_errors;
686 __le32 tx_one_collision;
687 __le32 tx_multi_collision;
688 __le64 rx_unicast;
689 __le64 rx_broadcast;
690 __le32 rx_multicast;
691 __le16 tx_aborted;
692 __le16 tx_underun;
693};
694
6e85d5ad
CV		 695struct rtl8169_tc_offsets {
696 bool inited;
697 __le64 tx_errors;
698 __le32 tx_multi_collision;
6e85d5ad
CV		 699 __le16 tx_aborted;
700};
701
da78dbff 702enum rtl_flag {
6c4a70c5 703 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 704 RTL_FLAG_TASK_SLOW_PENDING,
705 RTL_FLAG_TASK_RESET_PENDING,
da78dbff
FR		 706 RTL_FLAG_MAX
707};
708
8027aa24
JW		 709struct rtl8169_stats {
710 u64 packets;
711 u64 bytes;
712 struct u64_stats_sync syncp;
713};
714
1da177e4
LT		 715struct rtl8169_private {
716 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 717 struct pci_dev *pci_dev;
c4028958 718 struct net_device *dev;
bea3348e 719 struct napi_struct napi;
b57b7e5a 720 u32 msg_enable;
2b7b4318 721 u16 mac_version;
1da177e4
LT		 722 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
723 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 724 u32 dirty_tx;
8027aa24
JW		 725 struct rtl8169_stats rx_stats;
726 struct rtl8169_stats tx_stats;
1da177e4
LT		 727 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
728 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
729 dma_addr_t TxPhyAddr;
730 dma_addr_t RxPhyAddr;
6f0333b8 731 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 732 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4 733 u16 cp_cmd;
da78dbff
FR		 734
735 u16 event_slow;
50970831 736 const struct rtl_coalesce_info *coalesce_info;
c0e45c1c 737
738 struct mdio_ops {
24192210
FR		 739 void (*write)(struct rtl8169_private *, int, int);
740 int (*read)(struct rtl8169_private *, int);
c0e45c1c 741 } mdio_ops;
742
d58d46b5
FR		 743 struct jumbo_ops {
744 void (*enable)(struct rtl8169_private *);
745 void (*disable)(struct rtl8169_private *);
746 } jumbo_ops;
747
61cb532d 748 void (*hw_start)(struct rtl8169_private *tp);
5888d3fc 749 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 750
751 struct {
da78dbff
FR		 752 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
753 struct mutex mutex;
4422bcd4
FR		 754 struct work_struct work;
755 } wk;
756
ccdffb9a 757 struct mii_if_info mii;
f1e911d5 758 struct mii_bus *mii_bus;
42020320
CV		 759 dma_addr_t counters_phys_addr;
760 struct rtl8169_counters *counters;
6e85d5ad 761 struct rtl8169_tc_offsets tc_offset;
e1759441 762 u32 saved_wolopts;
f1e02ed1 763
b6ffd97f
FR		 764 struct rtl_fw {
765 const struct firmware *fw;
1c361efb
FR		 766
767#define RTL_VER_SIZE 32
768
769 char version[RTL_VER_SIZE];
770
771 struct rtl_fw_phy_action {
772 __le32 *code;
773 size_t size;
774 } phy_action;
b6ffd97f 775 } *rtl_fw;
497888cf 776#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 777
778 u32 ocp_base;
1da177e4
LT		 779};
780
979b6c13 781MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 782MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 783module_param(use_dac, int, 0);
4300e8c7 784MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 785module_param_named(debug, debug.msg_enable, int, 0);
786MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 787MODULE_LICENSE("GPL");
788MODULE_VERSION(RTL8169_VERSION);
bca03d5f 789MODULE_FIRMWARE(FIRMWARE_8168D_1);
790MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 791MODULE_FIRMWARE(FIRMWARE_8168E_1);
792MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 793MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 794MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 795MODULE_FIRMWARE(FIRMWARE_8168F_1);
796MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 797MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 798MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 799MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 800MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 801MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 802MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 803MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 804MODULE_FIRMWARE(FIRMWARE_8168H_1);
805MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 806MODULE_FIRMWARE(FIRMWARE_8107E_1);
807MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 808
1e1205b7
HK		 809static inline struct device *tp_to_dev(struct rtl8169_private *tp)
810{
811 return &tp->pci_dev->dev;
812}
813
da78dbff
FR		 814static void rtl_lock_work(struct rtl8169_private *tp)
815{
816 mutex_lock(&tp->wk.mutex);
817}
818
819static void rtl_unlock_work(struct rtl8169_private *tp)
820{
821 mutex_unlock(&tp->wk.mutex);
822}
823
cb73200c 824static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
d58d46b5 825{
cb73200c 826 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
7d7903b2 827 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 828}
829
ffc46952
FR		 830struct rtl_cond {
831 bool (*check)(struct rtl8169_private *);
832 const char *msg;
833};
834
835static void rtl_udelay(unsigned int d)
836{
837 udelay(d);
838}
839
840static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
841 void (*delay)(unsigned int), unsigned int d, int n,
842 bool high)
843{
844 int i;
845
846 for (i = 0; i < n; i++) {
847 delay(d);
848 if (c->check(tp) == high)
849 return true;
850 }
82e316ef
FR		 851 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
852 c->msg, !high, n, d);
ffc46952
FR		 853 return false;
854}
855
856static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
857 const struct rtl_cond *c,
858 unsigned int d, int n)
859{
860 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
861}
862
863static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
864 const struct rtl_cond *c,
865 unsigned int d, int n)
866{
867 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
868}
869
870static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
871 const struct rtl_cond *c,
872 unsigned int d, int n)
873{
874 return rtl_loop_wait(tp, c, msleep, d, n, true);
875}
876
877static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
878 const struct rtl_cond *c,
879 unsigned int d, int n)
880{
881 return rtl_loop_wait(tp, c, msleep, d, n, false);
882}
883
884#define DECLARE_RTL_COND(name) \
885static bool name ## _check(struct rtl8169_private *); \
886 \
887static const struct rtl_cond name = { \
888 .check = name ## _check, \
889 .msg = #name \
890}; \
891 \
892static bool name ## _check(struct rtl8169_private *tp)
893
c558386b
HW		 894static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
895{
896 if (reg & 0xffff0001) {
897 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
898 return true;
899 }
900 return false;
901}
902
903DECLARE_RTL_COND(rtl_ocp_gphy_cond)
904{
1ef7286e 905 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
c558386b
HW		 906}
907
908static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
909{
c558386b
HW		 910 if (rtl_ocp_reg_failure(tp, reg))
911 return;
912
1ef7286e 913 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 914
915 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
916}
917
918static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
919{
c558386b
HW		 920 if (rtl_ocp_reg_failure(tp, reg))
921 return 0;
922
1ef7286e 923 RTL_W32(tp, GPHY_OCP, reg << 15);
c558386b
HW		 924
925 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1ef7286e 926 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
c558386b
HW		 927}
928
c558386b
HW		 929static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
930{
c558386b
HW		 931 if (rtl_ocp_reg_failure(tp, reg))
932 return;
933
1ef7286e 934 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 935}
936
937static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
938{
c558386b
HW		 939 if (rtl_ocp_reg_failure(tp, reg))
940 return 0;
941
1ef7286e 942 RTL_W32(tp, OCPDR, reg << 15);
c558386b 943
1ef7286e 944 return RTL_R32(tp, OCPDR);
c558386b
HW		 945}
946
947#define OCP_STD_PHY_BASE 0xa400
948
949static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
950{
951 if (reg == 0x1f) {
952 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
953 return;
954 }
955
956 if (tp->ocp_base != OCP_STD_PHY_BASE)
957 reg -= 0x10;
958
959 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
960}
961
962static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
963{
964 if (tp->ocp_base != OCP_STD_PHY_BASE)
965 reg -= 0x10;
966
967 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
968}
969
eee3786f 970static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
971{
972 if (reg == 0x1f) {
973 tp->ocp_base = value << 4;
974 return;
975 }
976
977 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
978}
979
980static int mac_mcu_read(struct rtl8169_private *tp, int reg)
981{
982 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
983}
984
ffc46952
FR		 985DECLARE_RTL_COND(rtl_phyar_cond)
986{
1ef7286e 987 return RTL_R32(tp, PHYAR) & 0x80000000;
ffc46952
FR		 988}
989
24192210 990static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 991{
1ef7286e 992 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 993
ffc46952 994 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 995 /*
81a95f04
TT		 996 * According to hardware specs a 20us delay is required after write
997 * complete indication, but before sending next command.
024a07ba 998 */
81a95f04 999 udelay(20);
1da177e4
LT		 1000}
1001
24192210 1002static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1003{
ffc46952 1004 int value;
1da177e4 1005
1ef7286e 1006 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1007
ffc46952 1008 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1ef7286e 1009 RTL_R32(tp, PHYAR) & 0xffff : ~0;
ffc46952 1010
81a95f04
TT		 1011 /*
1012 * According to hardware specs a 20us delay is required after read
1013 * complete indication, but before sending next command.
1014 */
1015 udelay(20);
1016
1da177e4
LT		 1017 return value;
1018}
1019
935e2218
CHL		 1020DECLARE_RTL_COND(rtl_ocpar_cond)
1021{
1ef7286e 1022 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
935e2218
CHL		 1023}
1024
24192210 1025static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1026{
1ef7286e
AS		 1027 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1028 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
1029 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 1030
ffc46952 1031 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1032}
1033
24192210 1034static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1035{
24192210
FR		 1036 r8168dp_1_mdio_access(tp, reg,
1037 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1038}
1039
24192210 1040static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1041{
24192210 1042 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1043
1044 mdelay(1);
1ef7286e
AS		 1045 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1046 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 1047
ffc46952 1048 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1ef7286e 1049 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1050}
1051
e6de30d6 1052#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1053
1ef7286e 1054static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
e6de30d6 1055{
1ef7286e 1056 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1057}
1058
1ef7286e 1059static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
e6de30d6 1060{
1ef7286e 1061 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1062}
1063
24192210 1064static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1065{
1ef7286e 1066 r8168dp_2_mdio_start(tp);
e6de30d6 1067
24192210 1068 r8169_mdio_write(tp, reg, value);
e6de30d6 1069
1ef7286e 1070 r8168dp_2_mdio_stop(tp);
e6de30d6 1071}
1072
24192210 1073static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1074{
1075 int value;
1076
1ef7286e 1077 r8168dp_2_mdio_start(tp);
e6de30d6 1078
24192210 1079 value = r8169_mdio_read(tp, reg);
e6de30d6 1080
1ef7286e 1081 r8168dp_2_mdio_stop(tp);
e6de30d6 1082
1083 return value;
1084}
1085
4da19633 1086static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1087{
24192210 1088 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1089}
1090
4da19633 1091static int rtl_readphy(struct rtl8169_private *tp, int location)
1092{
24192210 1093 return tp->mdio_ops.read(tp, location);
4da19633 1094}
1095
1096static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1097{
1098 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1099}
1100
76564428 1101static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1102{
1103 int val;
1104
4da19633 1105 val = rtl_readphy(tp, reg_addr);
76564428 1106 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1107}
1108
ccdffb9a
FR		 1109static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1110 int val)
1111{
1112 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1113
4da19633 1114 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1115}
1116
1117static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1118{
1119 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1120
4da19633 1121 return rtl_readphy(tp, location);
ccdffb9a
FR		 1122}
1123
ffc46952
FR		 1124DECLARE_RTL_COND(rtl_ephyar_cond)
1125{
1ef7286e 1126 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
ffc46952
FR		 1127}
1128
fdf6fc06 1129static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1130{
1ef7286e 1131 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
dacf8154
FR		 1132 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1133
ffc46952
FR		 1134 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1135
1136 udelay(10);
dacf8154
FR		 1137}
1138
fdf6fc06 1139static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1140{
1ef7286e 1141 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
dacf8154 1142
ffc46952 1143 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1ef7286e 1144 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1145}
1146
935e2218
CHL		 1147DECLARE_RTL_COND(rtl_eriar_cond)
1148{
1ef7286e 1149 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
935e2218
CHL		 1150}
1151
fdf6fc06
FR		 1152static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1153 u32 val, int type)
133ac40a 1154{
133ac40a 1155 BUG_ON((addr & 3) || (mask == 0));
1ef7286e
AS		 1156 RTL_W32(tp, ERIDR, val);
1157 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
133ac40a 1158
ffc46952 1159 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1160}
1161
fdf6fc06 1162static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1163{
1ef7286e 1164 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
133ac40a 1165
ffc46952 1166 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1ef7286e 1167 RTL_R32(tp, ERIDR) : ~0;
133ac40a
HW		 1168}
1169
706123d0 1170static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1171 u32 m, int type)
133ac40a
HW		 1172{
1173 u32 val;
1174
fdf6fc06
FR		 1175 val = rtl_eri_read(tp, addr, type);
1176 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1177}
1178
935e2218
CHL		 1179static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1180{
1ef7286e 1181 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218 1182 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1ef7286e 1183 RTL_R32(tp, OCPDR) : ~0;
935e2218
CHL		 1184}
1185
1186static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1187{
1188 return rtl_eri_read(tp, reg, ERIAR_OOB);
1189}
1190
1191static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1192{
1193 switch (tp->mac_version) {
1194 case RTL_GIGA_MAC_VER_27:
1195 case RTL_GIGA_MAC_VER_28:
1196 case RTL_GIGA_MAC_VER_31:
1197 return r8168dp_ocp_read(tp, mask, reg);
1198 case RTL_GIGA_MAC_VER_49:
1199 case RTL_GIGA_MAC_VER_50:
1200 case RTL_GIGA_MAC_VER_51:
1201 return r8168ep_ocp_read(tp, mask, reg);
1202 default:
1203 BUG();
1204 return ~0;
1205 }
1206}
1207
1208static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1209 u32 data)
1210{
1ef7286e
AS		 1211 RTL_W32(tp, OCPDR, data);
1212 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218
CHL		 1213 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1214}
1215
1216static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1217 u32 data)
1218{
1219 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1220 data, ERIAR_OOB);
1221}
1222
1223static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1224{
1225 switch (tp->mac_version) {
1226 case RTL_GIGA_MAC_VER_27:
1227 case RTL_GIGA_MAC_VER_28:
1228 case RTL_GIGA_MAC_VER_31:
1229 r8168dp_ocp_write(tp, mask, reg, data);
1230 break;
1231 case RTL_GIGA_MAC_VER_49:
1232 case RTL_GIGA_MAC_VER_50:
1233 case RTL_GIGA_MAC_VER_51:
1234 r8168ep_ocp_write(tp, mask, reg, data);
1235 break;
1236 default:
1237 BUG();
1238 break;
1239 }
1240}
1241
2a9b4d96
CHL		 1242static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1243{
1244 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1245
1246 ocp_write(tp, 0x1, 0x30, 0x00000001);
1247}
1248
1249#define OOB_CMD_RESET 0x00
1250#define OOB_CMD_DRIVER_START 0x05
1251#define OOB_CMD_DRIVER_STOP 0x06
1252
1253static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1254{
1255 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1256}
1257
1258DECLARE_RTL_COND(rtl_ocp_read_cond)
1259{
1260 u16 reg;
1261
1262 reg = rtl8168_get_ocp_reg(tp);
1263
1264 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1265}
1266
935e2218 1267DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1268{
935e2218
CHL		 1269 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1270}
1271
1272DECLARE_RTL_COND(rtl_ocp_tx_cond)
1273{
1ef7286e 1274 return RTL_R8(tp, IBISR0) & 0x20;
935e2218 1275}
2a9b4d96 1276
003609da
CHL		 1277static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1278{
1ef7286e 1279 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
086ca23d 1280 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1ef7286e
AS		 1281 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1282 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
003609da
CHL		 1283}
1284
935e2218
CHL		 1285static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1286{
1287 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
2a9b4d96
CHL		 1288 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1289}
1290
935e2218 1291static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1292{
935e2218
CHL		 1293 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1294 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1295 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1296}
1297
1298static void rtl8168_driver_start(struct rtl8169_private *tp)
1299{
1300 switch (tp->mac_version) {
1301 case RTL_GIGA_MAC_VER_27:
1302 case RTL_GIGA_MAC_VER_28:
1303 case RTL_GIGA_MAC_VER_31:
1304 rtl8168dp_driver_start(tp);
1305 break;
1306 case RTL_GIGA_MAC_VER_49:
1307 case RTL_GIGA_MAC_VER_50:
1308 case RTL_GIGA_MAC_VER_51:
1309 rtl8168ep_driver_start(tp);
1310 break;
1311 default:
1312 BUG();
1313 break;
1314 }
1315}
2a9b4d96 1316
935e2218
CHL		 1317static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1318{
1319 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
2a9b4d96
CHL		 1320 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1321}
1322
935e2218
CHL		 1323static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1324{
003609da 1325 rtl8168ep_stop_cmac(tp);
935e2218
CHL		 1326 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1327 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1328 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1329}
1330
1331static void rtl8168_driver_stop(struct rtl8169_private *tp)
1332{
1333 switch (tp->mac_version) {
1334 case RTL_GIGA_MAC_VER_27:
1335 case RTL_GIGA_MAC_VER_28:
1336 case RTL_GIGA_MAC_VER_31:
1337 rtl8168dp_driver_stop(tp);
1338 break;
1339 case RTL_GIGA_MAC_VER_49:
1340 case RTL_GIGA_MAC_VER_50:
1341 case RTL_GIGA_MAC_VER_51:
1342 rtl8168ep_driver_stop(tp);
1343 break;
1344 default:
1345 BUG();
1346 break;
1347 }
1348}
1349
9dbe7896 1350static bool r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1351{
1352 u16 reg = rtl8168_get_ocp_reg(tp);
1353
9dbe7896 1354 return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
2a9b4d96
CHL		 1355}
1356
9dbe7896 1357static bool r8168ep_check_dash(struct rtl8169_private *tp)
935e2218 1358{
9dbe7896 1359 return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
935e2218
CHL		 1360}
1361
9dbe7896 1362static bool r8168_check_dash(struct rtl8169_private *tp)
935e2218
CHL		 1363{
1364 switch (tp->mac_version) {
1365 case RTL_GIGA_MAC_VER_27:
1366 case RTL_GIGA_MAC_VER_28:
1367 case RTL_GIGA_MAC_VER_31:
1368 return r8168dp_check_dash(tp);
1369 case RTL_GIGA_MAC_VER_49:
1370 case RTL_GIGA_MAC_VER_50:
1371 case RTL_GIGA_MAC_VER_51:
1372 return r8168ep_check_dash(tp);
1373 default:
9dbe7896 1374 return false;
935e2218
CHL		 1375 }
1376}
1377
c28aa385 1378struct exgmac_reg {
1379 u16 addr;
1380 u16 mask;
1381 u32 val;
1382};
1383
fdf6fc06 1384static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1385 const struct exgmac_reg *r, int len)
1386{
1387 while (len-- > 0) {
fdf6fc06 1388 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1389 r++;
1390 }
1391}
1392
ffc46952
FR		 1393DECLARE_RTL_COND(rtl_efusear_cond)
1394{
1ef7286e 1395 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
ffc46952
FR		 1396}
1397
fdf6fc06 1398static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1399{
1ef7286e 1400 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
daf9df6d 1401
ffc46952 1402 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1ef7286e 1403 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1404}
1405
9085cdfa
FR		 1406static u16 rtl_get_events(struct rtl8169_private *tp)
1407{
1ef7286e 1408 return RTL_R16(tp, IntrStatus);
9085cdfa
FR		 1409}
1410
1411static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1412{
1ef7286e 1413 RTL_W16(tp, IntrStatus, bits);
9085cdfa
FR		 1414 mmiowb();
1415}
1416
1417static void rtl_irq_disable(struct rtl8169_private *tp)
1418{
1ef7286e 1419 RTL_W16(tp, IntrMask, 0);
9085cdfa
FR		 1420 mmiowb();
1421}
1422
3e990ff5
FR		 1423static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1424{
1ef7286e 1425 RTL_W16(tp, IntrMask, bits);
3e990ff5
FR		 1426}
1427
da78dbff
FR		 1428#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1429#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1430#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1431
1432static void rtl_irq_enable_all(struct rtl8169_private *tp)
1433{
1434 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1435}
1436
811fd301 1437static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1438{
9085cdfa 1439 rtl_irq_disable(tp);
da78dbff 1440 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1ef7286e 1441 RTL_R8(tp, ChipCmd);
1da177e4
LT		 1442}
1443
4da19633 1444static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1445{
4da19633 1446 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1447}
1448
4da19633 1449static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1450{
1451 unsigned int val;
1452
4da19633 1453 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1454 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1455}
1456
70090424
HW		 1457static void rtl_link_chg_patch(struct rtl8169_private *tp)
1458{
70090424
HW		 1459 struct net_device *dev = tp->dev;
1460
1461 if (!netif_running(dev))
1462 return;
1463
b3d7b2f2
HW		 1464 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1465 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1ef7286e 1466 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1467 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1468 ERIAR_EXGMAC);
1469 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1470 ERIAR_EXGMAC);
1ef7286e 1471 } else if (RTL_R8(tp, PHYstatus) & _100bps) {
fdf6fc06
FR		 1472 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1473 ERIAR_EXGMAC);
1474 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1475 ERIAR_EXGMAC);
70090424 1476 } else {
fdf6fc06
FR		 1477 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1478 ERIAR_EXGMAC);
1479 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1480 ERIAR_EXGMAC);
70090424
HW		 1481 }
1482 /* Reset packet filter */
706123d0 1483 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1484 ERIAR_EXGMAC);
706123d0 1485 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1486 ERIAR_EXGMAC);
c2218925
HW		 1487 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1488 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1ef7286e 1489 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1490 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1491 ERIAR_EXGMAC);
1492 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1493 ERIAR_EXGMAC);
c2218925 1494 } else {
fdf6fc06
FR		 1495 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1496 ERIAR_EXGMAC);
1497 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1498 ERIAR_EXGMAC);
c2218925 1499 }
7e18dca1 1500 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1ef7286e 1501 if (RTL_R8(tp, PHYstatus) & _10bps) {
fdf6fc06
FR		 1502 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1503 ERIAR_EXGMAC);
1504 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1505 ERIAR_EXGMAC);
7e18dca1 1506 } else {
fdf6fc06
FR		 1507 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1508 ERIAR_EXGMAC);
7e18dca1 1509 }
70090424
HW		 1510 }
1511}
1512
e1759441
RW		 1513#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1514
1515static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1516{
61a4dcc2 1517 u8 options;
e1759441 1518 u32 wolopts = 0;
61a4dcc2 1519
1ef7286e 1520 options = RTL_R8(tp, Config1);
61a4dcc2 1521 if (!(options & PMEnable))
e1759441 1522 return 0;
61a4dcc2 1523
1ef7286e 1524 options = RTL_R8(tp, Config3);
61a4dcc2 1525 if (options & LinkUp)
e1759441 1526 wolopts |= WAKE_PHY;
6e1d0b89 1527 switch (tp->mac_version) {
2a71883c
HK		 1528 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1529 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1530 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1531 wolopts |= WAKE_MAGIC;
1532 break;
1533 default:
1534 if (options & MagicPacket)
1535 wolopts |= WAKE_MAGIC;
1536 break;
1537 }
61a4dcc2 1538
1ef7286e 1539 options = RTL_R8(tp, Config5);
61a4dcc2 1540 if (options & UWF)
e1759441 1541 wolopts |= WAKE_UCAST;
61a4dcc2 1542 if (options & BWF)
e1759441 1543 wolopts |= WAKE_BCAST;
61a4dcc2 1544 if (options & MWF)
e1759441 1545 wolopts |= WAKE_MCAST;
61a4dcc2 1546
e1759441 1547 return wolopts;
61a4dcc2
FR		 1548}
1549
e1759441 1550static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1551{
1552 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1553
da78dbff 1554 rtl_lock_work(tp);
e1759441 1555 wol->supported = WAKE_ANY;
433f9d0d 1556 wol->wolopts = tp->saved_wolopts;
da78dbff 1557 rtl_unlock_work(tp);
e1759441
RW		 1558}
1559
1560static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1561{
6e1d0b89 1562 unsigned int i, tmp;
350f7596 1563 static const struct {
61a4dcc2
FR		 1564 u32 opt;
1565 u16 reg;
1566 u8 mask;
1567 } cfg[] = {
61a4dcc2 1568 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1569 { WAKE_UCAST, Config5, UWF },
1570 { WAKE_BCAST, Config5, BWF },
1571 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1572 { WAKE_ANY, Config5, LanWake },
1573 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1574 };
851e6022 1575 u8 options;
61a4dcc2 1576
1ef7286e 1577 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
61a4dcc2 1578
6e1d0b89 1579 switch (tp->mac_version) {
2a71883c
HK		 1580 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1581 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1582 tmp = ARRAY_SIZE(cfg) - 1;
1583 if (wolopts & WAKE_MAGIC)
706123d0 1584 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1585 0x0dc,
1586 ERIAR_MASK_0100,
1587 MagicPacket_v2,
1588 0x0000,
1589 ERIAR_EXGMAC);
1590 else
706123d0 1591 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1592 0x0dc,
1593 ERIAR_MASK_0100,
1594 0x0000,
1595 MagicPacket_v2,
1596 ERIAR_EXGMAC);
1597 break;
1598 default:
1599 tmp = ARRAY_SIZE(cfg);
1600 break;
1601 }
1602
1603 for (i = 0; i < tmp; i++) {
1ef7286e 1604 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
e1759441 1605 if (wolopts & cfg[i].opt)
61a4dcc2 1606 options |= cfg[i].mask;
1ef7286e 1607 RTL_W8(tp, cfg[i].reg, options);
61a4dcc2
FR		 1608 }
1609
851e6022
FR		 1610 switch (tp->mac_version) {
1611 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1ef7286e 1612 options = RTL_R8(tp, Config1) & ~PMEnable;
851e6022
FR		 1613 if (wolopts)
1614 options |= PMEnable;
1ef7286e 1615 RTL_W8(tp, Config1, options);
851e6022
FR		 1616 break;
1617 default:
1ef7286e 1618 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
d387b427
FR		 1619 if (wolopts)
1620 options |= PME_SIGNAL;
1ef7286e 1621 RTL_W8(tp, Config2, options);
851e6022
FR		 1622 break;
1623 }
1624
1ef7286e 1625 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
e1759441
RW		 1626}
1627
1628static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1629{
1630 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1631 struct device *d = tp_to_dev(tp);
5fa80a32 1632
2f533f6b
HK		 1633 if (wol->wolopts & ~WAKE_ANY)
1634 return -EINVAL;
1635
5fa80a32 1636 pm_runtime_get_noresume(d);
e1759441 1637
da78dbff 1638 rtl_lock_work(tp);
61a4dcc2 1639
2f533f6b 1640 tp->saved_wolopts = wol->wolopts;
433f9d0d 1641
5fa80a32 1642 if (pm_runtime_active(d))
433f9d0d 1643 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff
FR		 1644
1645 rtl_unlock_work(tp);
61a4dcc2 1646
433f9d0d 1647 device_set_wakeup_enable(d, tp->saved_wolopts);
ea80907f 1648
5fa80a32
CHL		 1649 pm_runtime_put_noidle(d);
1650
61a4dcc2
FR		 1651 return 0;
1652}
1653
31bd204f
FR		 1654static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1655{
85bffe6c 1656 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1657}
1658
1da177e4
LT		 1659static void rtl8169_get_drvinfo(struct net_device *dev,
1660 struct ethtool_drvinfo *info)
1661{
1662 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1663 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1664
68aad78c
RJ		 1665 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1666 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1667 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1668 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1669 if (!IS_ERR_OR_NULL(rtl_fw))
1670 strlcpy(info->fw_version, rtl_fw->version,
1671 sizeof(info->fw_version));
1da177e4
LT		 1672}
1673
1674static int rtl8169_get_regs_len(struct net_device *dev)
1675{
1676 return R8169_REGS_SIZE;
1677}
1678
1da177e4 1679static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1680 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1681{
1682 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1683 int giga_ctrl, bmcr;
54405cde 1684 int rc = -EINVAL;
1da177e4 1685
716b50a3 1686 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1687
1688 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1689 int auto_nego;
1690
4da19633 1691 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1692 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1693 ADVERTISE_100HALF | ADVERTISE_100FULL);
1694
1695 if (adv & ADVERTISED_10baseT_Half)
1696 auto_nego |= ADVERTISE_10HALF;
1697 if (adv & ADVERTISED_10baseT_Full)
1698 auto_nego |= ADVERTISE_10FULL;
1699 if (adv & ADVERTISED_100baseT_Half)
1700 auto_nego |= ADVERTISE_100HALF;
1701 if (adv & ADVERTISED_100baseT_Full)
1702 auto_nego |= ADVERTISE_100FULL;
1703
3577aa1b 1704 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1705
4da19633 1706 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1707 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1708
3577aa1b 1709 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1710 if (tp->mii.supports_gmii) {
54405cde
ON		 1711 if (adv & ADVERTISED_1000baseT_Half)
1712 giga_ctrl |= ADVERTISE_1000HALF;
1713 if (adv & ADVERTISED_1000baseT_Full)
1714 giga_ctrl |= ADVERTISE_1000FULL;
1715 } else if (adv & (ADVERTISED_1000baseT_Half |
1716 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1717 netif_info(tp, link, dev,
1718 "PHY does not support 1000Mbps\n");
54405cde 1719 goto out;
bcf0bf90 1720 }
1da177e4 1721
3577aa1b 1722 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1723
4da19633 1724 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1725 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1726 } else {
3577aa1b 1727 if (speed == SPEED_10)
1728 bmcr = 0;
1729 else if (speed == SPEED_100)
1730 bmcr = BMCR_SPEED100;
1731 else
54405cde 1732 goto out;
3577aa1b 1733
1734 if (duplex == DUPLEX_FULL)
1735 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1736 }
1737
4da19633 1738 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1739
cecb5fd7
FR		 1740 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1741 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1742 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1743 rtl_writephy(tp, 0x17, 0x2138);
1744 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1745 } else {
4da19633 1746 rtl_writephy(tp, 0x17, 0x2108);
1747 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1748 }
1749 }
1750
54405cde
ON		 1751 rc = 0;
1752out:
1753 return rc;
1da177e4
LT		 1754}
1755
1756static int rtl8169_set_speed(struct net_device *dev,
54405cde 1757 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4 1758{
335c997d 1759 return rtl8169_set_speed_xmii(dev, autoneg, speed, duplex, advertising);
1da177e4
LT		 1760}
1761
c8f44aff
MM		 1762static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1763 netdev_features_t features)
1da177e4 1764{
d58d46b5
FR		 1765 struct rtl8169_private *tp = netdev_priv(dev);
1766
2b7b4318 1767 if (dev->mtu > TD_MSS_MAX)
350fb32a 1768 features &= ~NETIF_F_ALL_TSO;
1da177e4 1769
d58d46b5 1770 if (dev->mtu > JUMBO_1K &&
6ed0e08f 1771 tp->mac_version > RTL_GIGA_MAC_VER_06)
d58d46b5
FR		 1772 features &= ~NETIF_F_IP_CSUM;
1773
350fb32a 1774 return features;
1da177e4
LT		 1775}
1776
a3984578
HK		 1777static int rtl8169_set_features(struct net_device *dev,
1778 netdev_features_t features)
1da177e4
LT		 1779{
1780 struct rtl8169_private *tp = netdev_priv(dev);
929a031d 1781 u32 rx_config;
1da177e4 1782
a3984578
HK		 1783 rtl_lock_work(tp);
1784
1ef7286e 1785 rx_config = RTL_R32(tp, RxConfig);
929a031d 1786 if (features & NETIF_F_RXALL)
1787 rx_config |= (AcceptErr | AcceptRunt);
1788 else
1789 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 1790
1ef7286e 1791 RTL_W32(tp, RxConfig, rx_config);
350fb32a 1792
929a031d 1793 if (features & NETIF_F_RXCSUM)
1794 tp->cp_cmd |= RxChkSum;
1795 else
1796 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1797
929a031d 1798 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1799 tp->cp_cmd |= RxVlan;
1800 else
1801 tp->cp_cmd &= ~RxVlan;
1802
1ef7286e
AS		 1803 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1804 RTL_R16(tp, CPlusCmd);
1da177e4 1805
da78dbff 1806 rtl_unlock_work(tp);
1da177e4
LT		 1807
1808 return 0;
1809}
1810
810f4893 1811static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1812{
df8a39de
JP		 1813 return (skb_vlan_tag_present(skb)) ?
1814 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 1815}
1816
7a8fc77b 1817static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1818{
1819 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1820
7a8fc77b 1821 if (opts2 & RxVlanTag)
86a9bad3 1822 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1823}
1824
6fa1ba61
PR		 1825static int rtl8169_get_link_ksettings(struct net_device *dev,
1826 struct ethtool_link_ksettings *cmd)
1da177e4
LT		 1827{
1828 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1829
e397286b 1830 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
1da177e4 1831
e397286b 1832 return 0;
1da177e4
LT		 1833}
1834
9e77d7a5
TJ		 1835static int rtl8169_set_link_ksettings(struct net_device *dev,
1836 const struct ethtool_link_ksettings *cmd)
1837{
1838 struct rtl8169_private *tp = netdev_priv(dev);
1839 int rc;
1840 u32 advertising;
1841
1842 if (!ethtool_convert_link_mode_to_legacy_u32(&advertising,
1843 cmd->link_modes.advertising))
1844 return -EINVAL;
1845
9e77d7a5
TJ		 1846 rtl_lock_work(tp);
1847 rc = rtl8169_set_speed(dev, cmd->base.autoneg, cmd->base.speed,
1848 cmd->base.duplex, advertising);
1849 rtl_unlock_work(tp);
1850
1851 return rc;
1852}
1853
1da177e4
LT		 1854static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1855 void *p)
1856{
5b0384f4 1857 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 1858 u32 __iomem *data = tp->mmio_addr;
1859 u32 *dw = p;
1860 int i;
1da177e4 1861
da78dbff 1862 rtl_lock_work(tp);
15edae91
PW		 1863 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1864 memcpy_fromio(dw++, data++, 4);
da78dbff 1865 rtl_unlock_work(tp);
1da177e4
LT		 1866}
1867
b57b7e5a
SH		 1868static u32 rtl8169_get_msglevel(struct net_device *dev)
1869{
1870 struct rtl8169_private *tp = netdev_priv(dev);
1871
1872 return tp->msg_enable;
1873}
1874
1875static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1876{
1877 struct rtl8169_private *tp = netdev_priv(dev);
1878
1879 tp->msg_enable = value;
1880}
1881
d4a3a0fc
SH		 1882static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1883 "tx_packets",
1884 "rx_packets",
1885 "tx_errors",
1886 "rx_errors",
1887 "rx_missed",
1888 "align_errors",
1889 "tx_single_collisions",
1890 "tx_multi_collisions",
1891 "unicast",
1892 "broadcast",
1893 "multicast",
1894 "tx_aborted",
1895 "tx_underrun",
1896};
1897
b9f2c044 1898static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1899{
b9f2c044
JG		 1900 switch (sset) {
1901 case ETH_SS_STATS:
1902 return ARRAY_SIZE(rtl8169_gstrings);
1903 default:
1904 return -EOPNOTSUPP;
1905 }
d4a3a0fc
SH		 1906}
1907
42020320 1908DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 1909{
1ef7286e 1910 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 1911}
1912
e71c9ce2 1913static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
6e85d5ad 1914{
42020320
CV		 1915 dma_addr_t paddr = tp->counters_phys_addr;
1916 u32 cmd;
6e85d5ad 1917
1ef7286e
AS		 1918 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1919 RTL_R32(tp, CounterAddrHigh);
42020320 1920 cmd = (u64)paddr & DMA_BIT_MASK(32);
1ef7286e
AS		 1921 RTL_W32(tp, CounterAddrLow, cmd);
1922 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
6e85d5ad 1923
a78e9366 1924 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 1925}
1926
e71c9ce2 1927static bool rtl8169_reset_counters(struct rtl8169_private *tp)
6e85d5ad 1928{
6e85d5ad
CV		 1929 /*
1930 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1931 * tally counters.
1932 */
1933 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1934 return true;
1935
e71c9ce2 1936 return rtl8169_do_counters(tp, CounterReset);
ffc46952
FR		 1937}
1938
e71c9ce2 1939static bool rtl8169_update_counters(struct rtl8169_private *tp)
d4a3a0fc 1940{
355423d0
IV		 1941 /*
1942 * Some chips are unable to dump tally counters when the receiver
1943 * is disabled.
1944 */
1ef7286e 1945 if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
6e85d5ad 1946 return true;
d4a3a0fc 1947
e71c9ce2 1948 return rtl8169_do_counters(tp, CounterDump);
6e85d5ad
CV		 1949}
1950
e71c9ce2 1951static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
6e85d5ad 1952{
42020320 1953 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 1954 bool ret = false;
1955
1956 /*
1957 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1958 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1959 * reset by a power cycle, while the counter values collected by the
1960 * driver are reset at every driver unload/load cycle.
1961 *
1962 * To make sure the HW values returned by @get_stats64 match the SW
1963 * values, we collect the initial values at first open(*) and use them
1964 * as offsets to normalize the values returned by @get_stats64.
1965 *
1966 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1967 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1968 * set at open time by rtl_hw_start.
1969 */
1970
1971 if (tp->tc_offset.inited)
1972 return true;
1973
1974 /* If both, reset and update fail, propagate to caller. */
e71c9ce2 1975 if (rtl8169_reset_counters(tp))
6e85d5ad
CV		 1976 ret = true;
1977
e71c9ce2 1978 if (rtl8169_update_counters(tp))
6e85d5ad
CV		 1979 ret = true;
1980
42020320
CV		 1981 tp->tc_offset.tx_errors = counters->tx_errors;
1982 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1983 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 1984 tp->tc_offset.inited = true;
1985
1986 return ret;
d4a3a0fc
SH		 1987}
1988
355423d0
IV		 1989static void rtl8169_get_ethtool_stats(struct net_device *dev,
1990 struct ethtool_stats *stats, u64 *data)
1991{
1992 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1993 struct device *d = tp_to_dev(tp);
42020320 1994 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 1995
1996 ASSERT_RTNL();
1997
e0636236
CHL		 1998 pm_runtime_get_noresume(d);
1999
2000 if (pm_runtime_active(d))
e71c9ce2 2001 rtl8169_update_counters(tp);
e0636236
CHL		 2002
2003 pm_runtime_put_noidle(d);
355423d0 2004
42020320
CV		 2005 data[0] = le64_to_cpu(counters->tx_packets);
2006 data[1] = le64_to_cpu(counters->rx_packets);
2007 data[2] = le64_to_cpu(counters->tx_errors);
2008 data[3] = le32_to_cpu(counters->rx_errors);
2009 data[4] = le16_to_cpu(counters->rx_missed);
2010 data[5] = le16_to_cpu(counters->align_errors);
2011 data[6] = le32_to_cpu(counters->tx_one_collision);
2012 data[7] = le32_to_cpu(counters->tx_multi_collision);
2013 data[8] = le64_to_cpu(counters->rx_unicast);
2014 data[9] = le64_to_cpu(counters->rx_broadcast);
2015 data[10] = le32_to_cpu(counters->rx_multicast);
2016 data[11] = le16_to_cpu(counters->tx_aborted);
2017 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 2018}
2019
d4a3a0fc
SH		 2020static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2021{
2022 switch(stringset) {
2023 case ETH_SS_STATS:
2024 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2025 break;
2026 }
2027}
2028
f0903ea3
FF		 2029static int rtl8169_nway_reset(struct net_device *dev)
2030{
2031 struct rtl8169_private *tp = netdev_priv(dev);
2032
2033 return mii_nway_restart(&tp->mii);
2034}
2035
50970831
FR		 2036/*
2037 * Interrupt coalescing
2038 *
2039 * > 1 - the availability of the IntrMitigate (0xe2) register through the
2040 * > 8169, 8168 and 810x line of chipsets
2041 *
2042 * 8169, 8168, and 8136(810x) serial chipsets support it.
2043 *
2044 * > 2 - the Tx timer unit at gigabit speed
2045 *
2046 * The unit of the timer depends on both the speed and the setting of CPlusCmd
2047 * (0xe0) bit 1 and bit 0.
2048 *
2049 * For 8169
2050 * bit[1:0] \ speed 1000M 100M 10M
2051 * 0 0 320ns 2.56us 40.96us
2052 * 0 1 2.56us 20.48us 327.7us
2053 * 1 0 5.12us 40.96us 655.4us
2054 * 1 1 10.24us 81.92us 1.31ms
2055 *
2056 * For the other
2057 * bit[1:0] \ speed 1000M 100M 10M
2058 * 0 0 5us 2.56us 40.96us
2059 * 0 1 40us 20.48us 327.7us
2060 * 1 0 80us 40.96us 655.4us
2061 * 1 1 160us 81.92us 1.31ms
2062 */
2063
2064/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
2065struct rtl_coalesce_scale {
2066 /* Rx / Tx */
2067 u32 nsecs[2];
2068};
2069
2070/* rx/tx scale factors for all CPlusCmd[0:1] cases */
2071struct rtl_coalesce_info {
2072 u32 speed;
2073 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
2074};
2075
2076/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
2077#define rxtx_x1822(r, t) { \
2078 {{(r), (t)}}, \
2079 {{(r)*8, (t)*8}}, \
2080 {{(r)*8*2, (t)*8*2}}, \
2081 {{(r)*8*2*2, (t)*8*2*2}}, \
2082}
2083static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
2084 /* speed delays: rx00 tx00 */
2085 { SPEED_10, rxtx_x1822(40960, 40960) },
2086 { SPEED_100, rxtx_x1822( 2560, 2560) },
2087 { SPEED_1000, rxtx_x1822( 320, 320) },
2088 { 0 },
2089};
2090
2091static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
2092 /* speed delays: rx00 tx00 */
2093 { SPEED_10, rxtx_x1822(40960, 40960) },
2094 { SPEED_100, rxtx_x1822( 2560, 2560) },
2095 { SPEED_1000, rxtx_x1822( 5000, 5000) },
2096 { 0 },
2097};
2098#undef rxtx_x1822
2099
2100/* get rx/tx scale vector corresponding to current speed */
2101static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
2102{
2103 struct rtl8169_private *tp = netdev_priv(dev);
2104 struct ethtool_link_ksettings ecmd;
2105 const struct rtl_coalesce_info *ci;
2106 int rc;
2107
2108 rc = rtl8169_get_link_ksettings(dev, &ecmd);
2109 if (rc < 0)
2110 return ERR_PTR(rc);
2111
2112 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
2113 if (ecmd.base.speed == ci->speed) {
2114 return ci;
2115 }
2116 }
2117
2118 return ERR_PTR(-ELNRNG);
2119}
2120
2121static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2122{
2123 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 2124 const struct rtl_coalesce_info *ci;
2125 const struct rtl_coalesce_scale *scale;
2126 struct {
2127 u32 *max_frames;
2128 u32 *usecs;
2129 } coal_settings [] = {
2130 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
2131 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
2132 }, *p = coal_settings;
2133 int i;
2134 u16 w;
2135
2136 memset(ec, 0, sizeof(*ec));
2137
2138 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2139 ci = rtl_coalesce_info(dev);
2140 if (IS_ERR(ci))
2141 return PTR_ERR(ci);
2142
0ae0974e 2143 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
50970831
FR		 2144
2145 /* read IntrMitigate and adjust according to scale */
1ef7286e 2146 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
50970831
FR		 2147 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2148 w >>= RTL_COALESCE_SHIFT;
2149 *p->usecs = w & RTL_COALESCE_MASK;
2150 }
2151
2152 for (i = 0; i < 2; i++) {
2153 p = coal_settings + i;
2154 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2155
2156 /*
2157 * ethtool_coalesce says it is illegal to set both usecs and
2158 * max_frames to 0.
2159 */
2160 if (!*p->usecs && !*p->max_frames)
2161 *p->max_frames = 1;
2162 }
2163
2164 return 0;
2165}
2166
2167/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2168static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2169 struct net_device *dev, u32 nsec, u16 *cp01)
2170{
2171 const struct rtl_coalesce_info *ci;
2172 u16 i;
2173
2174 ci = rtl_coalesce_info(dev);
2175 if (IS_ERR(ci))
2176 return ERR_CAST(ci);
2177
2178 for (i = 0; i < 4; i++) {
2179 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2180 ci->scalev[i].nsecs[1]);
2181 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2182 *cp01 = i;
2183 return &ci->scalev[i];
2184 }
2185 }
2186
2187 return ERR_PTR(-EINVAL);
2188}
2189
2190static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2191{
2192 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 2193 const struct rtl_coalesce_scale *scale;
2194 struct {
2195 u32 frames;
2196 u32 usecs;
2197 } coal_settings [] = {
2198 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2199 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2200 }, *p = coal_settings;
2201 u16 w = 0, cp01;
2202 int i;
2203
2204 scale = rtl_coalesce_choose_scale(dev,
2205 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2206 if (IS_ERR(scale))
2207 return PTR_ERR(scale);
2208
2209 for (i = 0; i < 2; i++, p++) {
2210 u32 units;
2211
2212 /*
2213 * accept max_frames=1 we returned in rtl_get_coalesce.
2214 * accept it not only when usecs=0 because of e.g. the following scenario:
2215 *
2216 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2217 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2218 * - then user does `ethtool -C eth0 rx-usecs 100`
2219 *
2220 * since ethtool sends to kernel whole ethtool_coalesce
2221 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2222 * we'll reject it below in `frames % 4 != 0`.
2223 */
2224 if (p->frames == 1) {
2225 p->frames = 0;
2226 }
2227
2228 units = p->usecs * 1000 / scale->nsecs[i];
2229 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2230 return -EINVAL;
2231
2232 w <<= RTL_COALESCE_SHIFT;
2233 w |= units;
2234 w <<= RTL_COALESCE_SHIFT;
2235 w |= p->frames >> 2;
2236 }
2237
2238 rtl_lock_work(tp);
2239
1ef7286e 2240 RTL_W16(tp, IntrMitigate, swab16(w));
50970831 2241
9a3c81fa 2242 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1ef7286e
AS		 2243 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2244 RTL_R16(tp, CPlusCmd);
50970831
FR		 2245
2246 rtl_unlock_work(tp);
2247
2248 return 0;
2249}
2250
7282d491 2251static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2252 .get_drvinfo = rtl8169_get_drvinfo,
2253 .get_regs_len = rtl8169_get_regs_len,
2254 .get_link = ethtool_op_get_link,
50970831
FR		 2255 .get_coalesce = rtl_get_coalesce,
2256 .set_coalesce = rtl_set_coalesce,
b57b7e5a
SH		 2257 .get_msglevel = rtl8169_get_msglevel,
2258 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2259 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2260 .get_wol = rtl8169_get_wol,
2261 .set_wol = rtl8169_set_wol,
d4a3a0fc 2262 .get_strings = rtl8169_get_strings,
b9f2c044 2263 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2264 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2265 .get_ts_info = ethtool_op_get_ts_info,
f0903ea3 2266 .nway_reset = rtl8169_nway_reset,
6fa1ba61 2267 .get_link_ksettings = rtl8169_get_link_ksettings,
9e77d7a5 2268 .set_link_ksettings = rtl8169_set_link_ksettings,
1da177e4
LT		 2269};
2270
07d3f51f 2271static void rtl8169_get_mac_version(struct rtl8169_private *tp,
22148df0 2272 u8 default_version)
1da177e4 2273{
0e485150
FR		 2274 /*
2275 * The driver currently handles the 8168Bf and the 8168Be identically
2276 * but they can be identified more specifically through the test below
2277 * if needed:
2278 *
1ef7286e 2279 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2280 *
2281 * Same thing for the 8101Eb and the 8101Ec:
2282 *
1ef7286e 2283 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2284 */
3744100e 2285 static const struct rtl_mac_info {
1da177e4 2286 u32 mask;
e3cf0cc0 2287 u32 val;
1da177e4
LT		 2288 int mac_version;
2289 } mac_info[] = {
935e2218
CHL		 2290 /* 8168EP family. */
2291 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2292 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2293 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2294
6e1d0b89
CHL		 2295 /* 8168H family. */
2296 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2297 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2298
c558386b 2299 /* 8168G family. */
45dd95c4 2300 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2301 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2302 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2303 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2304
c2218925 2305 /* 8168F family. */
b3d7b2f2 2306 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2307 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2308 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2309
01dc7fec 2310 /* 8168E family. */
70090424 2311 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2312 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2313 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2314
5b538df9 2315 /* 8168D family. */
daf9df6d 2316 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2317 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2318
e6de30d6 2319 /* 8168DP family. */
2320 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2321 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2322 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2323
ef808d50 2324 /* 8168C family. */
ef3386f0 2325 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2326 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2327 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2328 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2329 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2330 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
ef808d50 2331 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2332
2333 /* 8168B family. */
2334 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
e3cf0cc0
FR		 2335 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2336 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2337
2338 /* 8101 family. */
5598bfe5 2339 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2340 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
5a5e4443
HW		 2341 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2342 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2343 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2344 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2345 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2346 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2347 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2348 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2349 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2350 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2351 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2352 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2353 /* FIXME: where did these entries come from ? -- FR */
2354 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2355 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2356
2357 /* 8110 family. */
2358 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2359 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2360 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2361 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2362 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2363 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2364
f21b75e9
JD		 2365 /* Catch-all */
2366 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2367 };
2368 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2369 u32 reg;
2370
1ef7286e 2371 reg = RTL_R32(tp, TxConfig);
e3cf0cc0 2372 while ((reg & p->mask) != p->val)
1da177e4
LT		 2373 p++;
2374 tp->mac_version = p->mac_version;
5d320a20
FR		 2375
2376 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
22148df0
HK		 2377 dev_notice(tp_to_dev(tp),
2378 "unknown MAC, using family default\n");
5d320a20 2379 tp->mac_version = default_version;
58152cd4 2380 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2381 tp->mac_version = tp->mii.supports_gmii ?
2382 RTL_GIGA_MAC_VER_42 :
2383 RTL_GIGA_MAC_VER_43;
6e1d0b89
CHL		 2384 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2385 tp->mac_version = tp->mii.supports_gmii ?
2386 RTL_GIGA_MAC_VER_45 :
2387 RTL_GIGA_MAC_VER_47;
2388 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2389 tp->mac_version = tp->mii.supports_gmii ?
2390 RTL_GIGA_MAC_VER_46 :
2391 RTL_GIGA_MAC_VER_48;
5d320a20 2392 }
1da177e4
LT		 2393}
2394
2395static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2396{
49d17512 2397 netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2398}
2399
867763c1
FR		 2400struct phy_reg {
2401 u16 reg;
2402 u16 val;
2403};
2404
4da19633 2405static void rtl_writephy_batch(struct rtl8169_private *tp,
2406 const struct phy_reg *regs, int len)
867763c1
FR		 2407{
2408 while (len-- > 0) {
4da19633 2409 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2410 regs++;
2411 }
2412}
2413
bca03d5f 2414#define PHY_READ 0x00000000
2415#define PHY_DATA_OR 0x10000000
2416#define PHY_DATA_AND 0x20000000
2417#define PHY_BJMPN 0x30000000
eee3786f 2418#define PHY_MDIO_CHG 0x40000000
bca03d5f 2419#define PHY_CLEAR_READCOUNT 0x70000000
2420#define PHY_WRITE 0x80000000
2421#define PHY_READCOUNT_EQ_SKIP 0x90000000
2422#define PHY_COMP_EQ_SKIPN 0xa0000000
2423#define PHY_COMP_NEQ_SKIPN 0xb0000000
2424#define PHY_WRITE_PREVIOUS 0xc0000000
2425#define PHY_SKIPN 0xd0000000
2426#define PHY_DELAY_MS 0xe0000000
bca03d5f 2427
960aee6c
HW		 2428struct fw_info {
2429 u32 magic;
2430 char version[RTL_VER_SIZE];
2431 __le32 fw_start;
2432 __le32 fw_len;
2433 u8 chksum;
2434} __packed;
2435
1c361efb
FR		 2436#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2437
2438static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2439{
b6ffd97f 2440 const struct firmware *fw = rtl_fw->fw;
960aee6c 2441 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2442 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2443 char *version = rtl_fw->version;
2444 bool rc = false;
2445
2446 if (fw->size < FW_OPCODE_SIZE)
2447 goto out;
960aee6c
HW		 2448
2449 if (!fw_info->magic) {
2450 size_t i, size, start;
2451 u8 checksum = 0;
2452
2453 if (fw->size < sizeof(*fw_info))
2454 goto out;
2455
2456 for (i = 0; i < fw->size; i++)
2457 checksum += fw->data[i];
2458 if (checksum != 0)
2459 goto out;
2460
2461 start = le32_to_cpu(fw_info->fw_start);
2462 if (start > fw->size)
2463 goto out;
2464
2465 size = le32_to_cpu(fw_info->fw_len);
2466 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2467 goto out;
2468
2469 memcpy(version, fw_info->version, RTL_VER_SIZE);
2470
2471 pa->code = (__le32 *)(fw->data + start);
2472 pa->size = size;
2473 } else {
1c361efb
FR		 2474 if (fw->size % FW_OPCODE_SIZE)
2475 goto out;
2476
2477 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2478
2479 pa->code = (__le32 *)fw->data;
2480 pa->size = fw->size / FW_OPCODE_SIZE;
2481 }
2482 version[RTL_VER_SIZE - 1] = 0;
2483
2484 rc = true;
2485out:
2486 return rc;
2487}
2488
fd112f2e
FR		 2489static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2490 struct rtl_fw_phy_action *pa)
1c361efb 2491{
fd112f2e 2492 bool rc = false;
1c361efb 2493 size_t index;
bca03d5f 2494
1c361efb
FR		 2495 for (index = 0; index < pa->size; index++) {
2496 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2497 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2498
42b82dc1 2499 switch(action & 0xf0000000) {
2500 case PHY_READ:
2501 case PHY_DATA_OR:
2502 case PHY_DATA_AND:
eee3786f 2503 case PHY_MDIO_CHG:
42b82dc1 2504 case PHY_CLEAR_READCOUNT:
2505 case PHY_WRITE:
2506 case PHY_WRITE_PREVIOUS:
2507 case PHY_DELAY_MS:
2508 break;
2509
2510 case PHY_BJMPN:
2511 if (regno > index) {
fd112f2e 2512 netif_err(tp, ifup, tp->dev,
cecb5fd7 2513 "Out of range of firmware\n");
fd112f2e 2514 goto out;
42b82dc1 2515 }
2516 break;
2517 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2518 if (index + 2 >= pa->size) {
fd112f2e 2519 netif_err(tp, ifup, tp->dev,
cecb5fd7 2520 "Out of range of firmware\n");
fd112f2e 2521 goto out;
42b82dc1 2522 }
2523 break;
2524 case PHY_COMP_EQ_SKIPN:
2525 case PHY_COMP_NEQ_SKIPN:
2526 case PHY_SKIPN:
1c361efb 2527 if (index + 1 + regno >= pa->size) {
fd112f2e 2528 netif_err(tp, ifup, tp->dev,
cecb5fd7 2529 "Out of range of firmware\n");
fd112f2e 2530 goto out;
42b82dc1 2531 }
bca03d5f 2532 break;
2533
42b82dc1 2534 default:
fd112f2e 2535 netif_err(tp, ifup, tp->dev,
42b82dc1 2536 "Invalid action 0x%08x\n", action);
fd112f2e 2537 goto out;
bca03d5f 2538 }
2539 }
fd112f2e
FR		 2540 rc = true;
2541out:
2542 return rc;
2543}
bca03d5f 2544
fd112f2e
FR		 2545static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2546{
2547 struct net_device *dev = tp->dev;
2548 int rc = -EINVAL;
2549
2550 if (!rtl_fw_format_ok(tp, rtl_fw)) {
5c2d2b14 2551 netif_err(tp, ifup, dev, "invalid firmware\n");
fd112f2e
FR		 2552 goto out;
2553 }
2554
2555 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2556 rc = 0;
2557out:
2558 return rc;
2559}
2560
2561static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2562{
2563 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2564 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2565 u32 predata, count;
2566 size_t index;
2567
2568 predata = count = 0;
eee3786f 2569 org.write = ops->write;
2570 org.read = ops->read;
42b82dc1 2571
1c361efb
FR		 2572 for (index = 0; index < pa->size; ) {
2573 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2574 u32 data = action & 0x0000ffff;
42b82dc1 2575 u32 regno = (action & 0x0fff0000) >> 16;
2576
2577 if (!action)
2578 break;
bca03d5f 2579
2580 switch(action & 0xf0000000) {
42b82dc1 2581 case PHY_READ:
2582 predata = rtl_readphy(tp, regno);
2583 count++;
2584 index++;
2585 break;
2586 case PHY_DATA_OR:
2587 predata |= data;
2588 index++;
2589 break;
2590 case PHY_DATA_AND:
2591 predata &= data;
2592 index++;
2593 break;
2594 case PHY_BJMPN:
2595 index -= regno;
2596 break;
eee3786f 2597 case PHY_MDIO_CHG:
2598 if (data == 0) {
2599 ops->write = org.write;
2600 ops->read = org.read;
2601 } else if (data == 1) {
2602 ops->write = mac_mcu_write;
2603 ops->read = mac_mcu_read;
2604 }
2605
42b82dc1 2606 index++;
2607 break;
2608 case PHY_CLEAR_READCOUNT:
2609 count = 0;
2610 index++;
2611 break;
bca03d5f 2612 case PHY_WRITE:
42b82dc1 2613 rtl_writephy(tp, regno, data);
2614 index++;
2615 break;
2616 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2617 index += (count == data) ? 2 : 1;
bca03d5f 2618 break;
42b82dc1 2619 case PHY_COMP_EQ_SKIPN:
2620 if (predata == data)
2621 index += regno;
2622 index++;
2623 break;
2624 case PHY_COMP_NEQ_SKIPN:
2625 if (predata != data)
2626 index += regno;
2627 index++;
2628 break;
2629 case PHY_WRITE_PREVIOUS:
2630 rtl_writephy(tp, regno, predata);
2631 index++;
2632 break;
2633 case PHY_SKIPN:
2634 index += regno + 1;
2635 break;
2636 case PHY_DELAY_MS:
2637 mdelay(data);
2638 index++;
2639 break;
2640
bca03d5f 2641 default:
2642 BUG();
2643 }
2644 }
eee3786f 2645
2646 ops->write = org.write;
2647 ops->read = org.read;
bca03d5f 2648}
2649
f1e02ed1 2650static void rtl_release_firmware(struct rtl8169_private *tp)
2651{
b6ffd97f
FR		 2652 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2653 release_firmware(tp->rtl_fw->fw);
2654 kfree(tp->rtl_fw);
2655 }
2656 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2657}
2658
953a12cc 2659static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2660{
b6ffd97f 2661 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2662
2663 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2664 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2665 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2666}
2667
2668static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2669{
2670 if (rtl_readphy(tp, reg) != val)
2671 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2672 else
2673 rtl_apply_firmware(tp);
f1e02ed1 2674}
2675
4da19633 2676static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2677{
350f7596 2678 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2679 { 0x1f, 0x0001 },
2680 { 0x06, 0x006e },
2681 { 0x08, 0x0708 },
2682 { 0x15, 0x4000 },
2683 { 0x18, 0x65c7 },
1da177e4 2684
0b9b571d 2685 { 0x1f, 0x0001 },
2686 { 0x03, 0x00a1 },
2687 { 0x02, 0x0008 },
2688 { 0x01, 0x0120 },
2689 { 0x00, 0x1000 },
2690 { 0x04, 0x0800 },
2691 { 0x04, 0x0000 },
1da177e4 2692
0b9b571d 2693 { 0x03, 0xff41 },
2694 { 0x02, 0xdf60 },
2695 { 0x01, 0x0140 },
2696 { 0x00, 0x0077 },
2697 { 0x04, 0x7800 },
2698 { 0x04, 0x7000 },
2699
2700 { 0x03, 0x802f },
2701 { 0x02, 0x4f02 },
2702 { 0x01, 0x0409 },
2703 { 0x00, 0xf0f9 },
2704 { 0x04, 0x9800 },
2705 { 0x04, 0x9000 },
2706
2707 { 0x03, 0xdf01 },
2708 { 0x02, 0xdf20 },
2709 { 0x01, 0xff95 },
2710 { 0x00, 0xba00 },
2711 { 0x04, 0xa800 },
2712 { 0x04, 0xa000 },
2713
2714 { 0x03, 0xff41 },
2715 { 0x02, 0xdf20 },
2716 { 0x01, 0x0140 },
2717 { 0x00, 0x00bb },
2718 { 0x04, 0xb800 },
2719 { 0x04, 0xb000 },
2720
2721 { 0x03, 0xdf41 },
2722 { 0x02, 0xdc60 },
2723 { 0x01, 0x6340 },
2724 { 0x00, 0x007d },
2725 { 0x04, 0xd800 },
2726 { 0x04, 0xd000 },
2727
2728 { 0x03, 0xdf01 },
2729 { 0x02, 0xdf20 },
2730 { 0x01, 0x100a },
2731 { 0x00, 0xa0ff },
2732 { 0x04, 0xf800 },
2733 { 0x04, 0xf000 },
2734
2735 { 0x1f, 0x0000 },
2736 { 0x0b, 0x0000 },
2737 { 0x00, 0x9200 }
2738 };
1da177e4 2739
4da19633 2740 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2741}
2742
4da19633 2743static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2744{
350f7596 2745 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2746 { 0x1f, 0x0002 },
2747 { 0x01, 0x90d0 },
2748 { 0x1f, 0x0000 }
2749 };
2750
4da19633 2751 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2752}
2753
4da19633 2754static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2755{
2756 struct pci_dev *pdev = tp->pci_dev;
2e955856 2757
ccbae55e
SS		 2758 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2759 (pdev->subsystem_device != 0xe000))
2e955856 2760 return;
2761
4da19633 2762 rtl_writephy(tp, 0x1f, 0x0001);
2763 rtl_writephy(tp, 0x10, 0xf01b);
2764 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2765}
2766
4da19633 2767static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2768{
350f7596 2769 static const struct phy_reg phy_reg_init[] = {
2e955856 2770 { 0x1f, 0x0001 },
2771 { 0x04, 0x0000 },
2772 { 0x03, 0x00a1 },
2773 { 0x02, 0x0008 },
2774 { 0x01, 0x0120 },
2775 { 0x00, 0x1000 },
2776 { 0x04, 0x0800 },
2777 { 0x04, 0x9000 },
2778 { 0x03, 0x802f },
2779 { 0x02, 0x4f02 },
2780 { 0x01, 0x0409 },
2781 { 0x00, 0xf099 },
2782 { 0x04, 0x9800 },
2783 { 0x04, 0xa000 },
2784 { 0x03, 0xdf01 },
2785 { 0x02, 0xdf20 },
2786 { 0x01, 0xff95 },
2787 { 0x00, 0xba00 },
2788 { 0x04, 0xa800 },
2789 { 0x04, 0xf000 },
2790 { 0x03, 0xdf01 },
2791 { 0x02, 0xdf20 },
2792 { 0x01, 0x101a },
2793 { 0x00, 0xa0ff },
2794 { 0x04, 0xf800 },
2795 { 0x04, 0x0000 },
2796 { 0x1f, 0x0000 },
2797
2798 { 0x1f, 0x0001 },
2799 { 0x10, 0xf41b },
2800 { 0x14, 0xfb54 },
2801 { 0x18, 0xf5c7 },
2802 { 0x1f, 0x0000 },
2803
2804 { 0x1f, 0x0001 },
2805 { 0x17, 0x0cc0 },
2806 { 0x1f, 0x0000 }
2807 };
2808
4da19633 2809 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2810
4da19633 2811 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2812}
2813
4da19633 2814static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2815{
350f7596 2816 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2817 { 0x1f, 0x0001 },
2818 { 0x04, 0x0000 },
2819 { 0x03, 0x00a1 },
2820 { 0x02, 0x0008 },
2821 { 0x01, 0x0120 },
2822 { 0x00, 0x1000 },
2823 { 0x04, 0x0800 },
2824 { 0x04, 0x9000 },
2825 { 0x03, 0x802f },
2826 { 0x02, 0x4f02 },
2827 { 0x01, 0x0409 },
2828 { 0x00, 0xf099 },
2829 { 0x04, 0x9800 },
2830 { 0x04, 0xa000 },
2831 { 0x03, 0xdf01 },
2832 { 0x02, 0xdf20 },
2833 { 0x01, 0xff95 },
2834 { 0x00, 0xba00 },
2835 { 0x04, 0xa800 },
2836 { 0x04, 0xf000 },
2837 { 0x03, 0xdf01 },
2838 { 0x02, 0xdf20 },
2839 { 0x01, 0x101a },
2840 { 0x00, 0xa0ff },
2841 { 0x04, 0xf800 },
2842 { 0x04, 0x0000 },
2843 { 0x1f, 0x0000 },
2844
2845 { 0x1f, 0x0001 },
2846 { 0x0b, 0x8480 },
2847 { 0x1f, 0x0000 },
2848
2849 { 0x1f, 0x0001 },
2850 { 0x18, 0x67c7 },
2851 { 0x04, 0x2000 },
2852 { 0x03, 0x002f },
2853 { 0x02, 0x4360 },
2854 { 0x01, 0x0109 },
2855 { 0x00, 0x3022 },
2856 { 0x04, 0x2800 },
2857 { 0x1f, 0x0000 },
2858
2859 { 0x1f, 0x0001 },
2860 { 0x17, 0x0cc0 },
2861 { 0x1f, 0x0000 }
2862 };
2863
4da19633 2864 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2865}
2866
4da19633 2867static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2868{
350f7596 2869 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2870 { 0x10, 0xf41b },
2871 { 0x1f, 0x0000 }
2872 };
2873
4da19633 2874 rtl_writephy(tp, 0x1f, 0x0001);
2875 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2876
4da19633 2877 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2878}
2879
4da19633 2880static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2881{
350f7596 2882 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2883 { 0x1f, 0x0001 },
2884 { 0x10, 0xf41b },
2885 { 0x1f, 0x0000 }
2886 };
2887
4da19633 2888 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2889}
2890
4da19633 2891static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2892{
350f7596 2893 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2894 { 0x1f, 0x0000 },
2895 { 0x1d, 0x0f00 },
2896 { 0x1f, 0x0002 },
2897 { 0x0c, 0x1ec8 },
2898 { 0x1f, 0x0000 }
2899 };
2900
4da19633 2901 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2902}
2903
4da19633 2904static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2905{
350f7596 2906 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2907 { 0x1f, 0x0001 },
2908 { 0x1d, 0x3d98 },
2909 { 0x1f, 0x0000 }
2910 };
2911
4da19633 2912 rtl_writephy(tp, 0x1f, 0x0000);
2913 rtl_patchphy(tp, 0x14, 1 << 5);
2914 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2915
4da19633 2916 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2917}
2918
4da19633 2919static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2920{
350f7596 2921 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2922 { 0x1f, 0x0001 },
2923 { 0x12, 0x2300 },
867763c1
FR		 2924 { 0x1f, 0x0002 },
2925 { 0x00, 0x88d4 },
2926 { 0x01, 0x82b1 },
2927 { 0x03, 0x7002 },
2928 { 0x08, 0x9e30 },
2929 { 0x09, 0x01f0 },
2930 { 0x0a, 0x5500 },
2931 { 0x0c, 0x00c8 },
2932 { 0x1f, 0x0003 },
2933 { 0x12, 0xc096 },
2934 { 0x16, 0x000a },
f50d4275
FR		 2935 { 0x1f, 0x0000 },
2936 { 0x1f, 0x0000 },
2937 { 0x09, 0x2000 },
2938 { 0x09, 0x0000 }
867763c1
FR		 2939 };
2940
4da19633 2941 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2942
4da19633 2943 rtl_patchphy(tp, 0x14, 1 << 5);
2944 rtl_patchphy(tp, 0x0d, 1 << 5);
2945 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2946}
2947
4da19633 2948static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2949{
350f7596 2950 static const struct phy_reg phy_reg_init[] = {
f50d4275 2951 { 0x1f, 0x0001 },
7da97ec9 2952 { 0x12, 0x2300 },
f50d4275
FR		 2953 { 0x03, 0x802f },
2954 { 0x02, 0x4f02 },
2955 { 0x01, 0x0409 },
2956 { 0x00, 0xf099 },
2957 { 0x04, 0x9800 },
2958 { 0x04, 0x9000 },
2959 { 0x1d, 0x3d98 },
7da97ec9
FR		 2960 { 0x1f, 0x0002 },
2961 { 0x0c, 0x7eb8 },
f50d4275
FR		 2962 { 0x06, 0x0761 },
2963 { 0x1f, 0x0003 },
2964 { 0x16, 0x0f0a },
7da97ec9
FR		 2965 { 0x1f, 0x0000 }
2966 };
2967
4da19633 2968 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2969
4da19633 2970 rtl_patchphy(tp, 0x16, 1 << 0);
2971 rtl_patchphy(tp, 0x14, 1 << 5);
2972 rtl_patchphy(tp, 0x0d, 1 << 5);
2973 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2974}
2975
4da19633 2976static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2977{
350f7596 2978 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2979 { 0x1f, 0x0001 },
2980 { 0x12, 0x2300 },
2981 { 0x1d, 0x3d98 },
2982 { 0x1f, 0x0002 },
2983 { 0x0c, 0x7eb8 },
2984 { 0x06, 0x5461 },
2985 { 0x1f, 0x0003 },
2986 { 0x16, 0x0f0a },
2987 { 0x1f, 0x0000 }
2988 };
2989
4da19633 2990 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2991
4da19633 2992 rtl_patchphy(tp, 0x16, 1 << 0);
2993 rtl_patchphy(tp, 0x14, 1 << 5);
2994 rtl_patchphy(tp, 0x0d, 1 << 5);
2995 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2996}
2997
4da19633 2998static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2999{
4da19633 3000 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 3001}
3002
bca03d5f 3003static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 3004{
350f7596 3005 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3006 /* Channel Estimation */
5b538df9 3007 { 0x1f, 0x0001 },
daf9df6d 3008 { 0x06, 0x4064 },
3009 { 0x07, 0x2863 },
3010 { 0x08, 0x059c },
3011 { 0x09, 0x26b4 },
3012 { 0x0a, 0x6a19 },
3013 { 0x0b, 0xdcc8 },
3014 { 0x10, 0xf06d },
3015 { 0x14, 0x7f68 },
3016 { 0x18, 0x7fd9 },
3017 { 0x1c, 0xf0ff },
3018 { 0x1d, 0x3d9c },
5b538df9 3019 { 0x1f, 0x0003 },
daf9df6d 3020 { 0x12, 0xf49f },
3021 { 0x13, 0x070b },
3022 { 0x1a, 0x05ad },
bca03d5f 3023 { 0x14, 0x94c0 },
3024
3025 /*
3026 * Tx Error Issue
cecb5fd7 3027 * Enhance line driver power
bca03d5f 3028 */
5b538df9 3029 { 0x1f, 0x0002 },
daf9df6d 3030 { 0x06, 0x5561 },
3031 { 0x1f, 0x0005 },
3032 { 0x05, 0x8332 },
bca03d5f 3033 { 0x06, 0x5561 },
3034
3035 /*
3036 * Can not link to 1Gbps with bad cable
3037 * Decrease SNR threshold form 21.07dB to 19.04dB
3038 */
3039 { 0x1f, 0x0001 },
3040 { 0x17, 0x0cc0 },
daf9df6d 3041
5b538df9 3042 { 0x1f, 0x0000 },
bca03d5f 3043 { 0x0d, 0xf880 }
daf9df6d 3044 };
3045
4da19633 3046 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 3047
bca03d5f 3048 /*
3049 * Rx Error Issue
3050 * Fine Tune Switching regulator parameter
3051 */
4da19633 3052 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3053 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3054 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 3055
fdf6fc06 3056 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3057 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3058 { 0x1f, 0x0002 },
3059 { 0x05, 0x669a },
3060 { 0x1f, 0x0005 },
3061 { 0x05, 0x8330 },
3062 { 0x06, 0x669a },
3063 { 0x1f, 0x0002 }
3064 };
3065 int val;
3066
4da19633 3067 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3068
4da19633 3069 val = rtl_readphy(tp, 0x0d);
daf9df6d 3070
3071 if ((val & 0x00ff) != 0x006c) {
350f7596 3072 static const u32 set[] = {
daf9df6d 3073 0x0065, 0x0066, 0x0067, 0x0068,
3074 0x0069, 0x006a, 0x006b, 0x006c
3075 };
3076 int i;
3077
4da19633 3078 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3079
3080 val &= 0xff00;
3081 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3082 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3083 }
3084 } else {
350f7596 3085 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3086 { 0x1f, 0x0002 },
3087 { 0x05, 0x6662 },
3088 { 0x1f, 0x0005 },
3089 { 0x05, 0x8330 },
3090 { 0x06, 0x6662 }
3091 };
3092
4da19633 3093 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3094 }
3095
bca03d5f 3096 /* RSET couple improve */
4da19633 3097 rtl_writephy(tp, 0x1f, 0x0002);
3098 rtl_patchphy(tp, 0x0d, 0x0300);
3099 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 3100
bca03d5f 3101 /* Fine tune PLL performance */
4da19633 3102 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3103 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3104 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3105
4da19633 3106 rtl_writephy(tp, 0x1f, 0x0005);
3107 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3108
3109 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 3110
4da19633 3111 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3112}
3113
bca03d5f 3114static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3115{
350f7596 3116 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3117 /* Channel Estimation */
daf9df6d 3118 { 0x1f, 0x0001 },
3119 { 0x06, 0x4064 },
3120 { 0x07, 0x2863 },
3121 { 0x08, 0x059c },
3122 { 0x09, 0x26b4 },
3123 { 0x0a, 0x6a19 },
3124 { 0x0b, 0xdcc8 },
3125 { 0x10, 0xf06d },
3126 { 0x14, 0x7f68 },
3127 { 0x18, 0x7fd9 },
3128 { 0x1c, 0xf0ff },
3129 { 0x1d, 0x3d9c },
3130 { 0x1f, 0x0003 },
3131 { 0x12, 0xf49f },
3132 { 0x13, 0x070b },
3133 { 0x1a, 0x05ad },
3134 { 0x14, 0x94c0 },
3135
bca03d5f 3136 /*
3137 * Tx Error Issue
cecb5fd7 3138 * Enhance line driver power
bca03d5f 3139 */
daf9df6d 3140 { 0x1f, 0x0002 },
3141 { 0x06, 0x5561 },
3142 { 0x1f, 0x0005 },
3143 { 0x05, 0x8332 },
bca03d5f 3144 { 0x06, 0x5561 },
3145
3146 /*
3147 * Can not link to 1Gbps with bad cable
3148 * Decrease SNR threshold form 21.07dB to 19.04dB
3149 */
3150 { 0x1f, 0x0001 },
3151 { 0x17, 0x0cc0 },
daf9df6d 3152
3153 { 0x1f, 0x0000 },
bca03d5f 3154 { 0x0d, 0xf880 }
5b538df9
FR		 3155 };
3156
4da19633 3157 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 3158
fdf6fc06 3159 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3160 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3161 { 0x1f, 0x0002 },
3162 { 0x05, 0x669a },
5b538df9 3163 { 0x1f, 0x0005 },
daf9df6d 3164 { 0x05, 0x8330 },
3165 { 0x06, 0x669a },
3166
3167 { 0x1f, 0x0002 }
3168 };
3169 int val;
3170
4da19633 3171 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3172
4da19633 3173 val = rtl_readphy(tp, 0x0d);
daf9df6d 3174 if ((val & 0x00ff) != 0x006c) {
b6bc7650 3175 static const u32 set[] = {
daf9df6d 3176 0x0065, 0x0066, 0x0067, 0x0068,
3177 0x0069, 0x006a, 0x006b, 0x006c
3178 };
3179 int i;
3180
4da19633 3181 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3182
3183 val &= 0xff00;
3184 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3185 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3186 }
3187 } else {
350f7596 3188 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3189 { 0x1f, 0x0002 },
3190 { 0x05, 0x2642 },
5b538df9 3191 { 0x1f, 0x0005 },
daf9df6d 3192 { 0x05, 0x8330 },
3193 { 0x06, 0x2642 }
5b538df9
FR		 3194 };
3195
4da19633 3196 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3197 }
3198
bca03d5f 3199 /* Fine tune PLL performance */
4da19633 3200 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3201 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3202 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3203
bca03d5f 3204 /* Switching regulator Slew rate */
4da19633 3205 rtl_writephy(tp, 0x1f, 0x0002);
3206 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 3207
4da19633 3208 rtl_writephy(tp, 0x1f, 0x0005);
3209 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3210
3211 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 3212
4da19633 3213 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3214}
3215
4da19633 3216static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3217{
350f7596 3218 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3219 { 0x1f, 0x0002 },
3220 { 0x10, 0x0008 },
3221 { 0x0d, 0x006c },
3222
3223 { 0x1f, 0x0000 },
3224 { 0x0d, 0xf880 },
3225
3226 { 0x1f, 0x0001 },
3227 { 0x17, 0x0cc0 },
3228
3229 { 0x1f, 0x0001 },
3230 { 0x0b, 0xa4d8 },
3231 { 0x09, 0x281c },
3232 { 0x07, 0x2883 },
3233 { 0x0a, 0x6b35 },
3234 { 0x1d, 0x3da4 },
3235 { 0x1c, 0xeffd },
3236 { 0x14, 0x7f52 },
3237 { 0x18, 0x7fc6 },
3238 { 0x08, 0x0601 },
3239 { 0x06, 0x4063 },
3240 { 0x10, 0xf074 },
3241 { 0x1f, 0x0003 },
3242 { 0x13, 0x0789 },
3243 { 0x12, 0xf4bd },
3244 { 0x1a, 0x04fd },
3245 { 0x14, 0x84b0 },
3246 { 0x1f, 0x0000 },
3247 { 0x00, 0x9200 },
3248
3249 { 0x1f, 0x0005 },
3250 { 0x01, 0x0340 },
3251 { 0x1f, 0x0001 },
3252 { 0x04, 0x4000 },
3253 { 0x03, 0x1d21 },
3254 { 0x02, 0x0c32 },
3255 { 0x01, 0x0200 },
3256 { 0x00, 0x5554 },
3257 { 0x04, 0x4800 },
3258 { 0x04, 0x4000 },
3259 { 0x04, 0xf000 },
3260 { 0x03, 0xdf01 },
3261 { 0x02, 0xdf20 },
3262 { 0x01, 0x101a },
3263 { 0x00, 0xa0ff },
3264 { 0x04, 0xf800 },
3265 { 0x04, 0xf000 },
3266 { 0x1f, 0x0000 },
3267
3268 { 0x1f, 0x0007 },
3269 { 0x1e, 0x0023 },
3270 { 0x16, 0x0000 },
3271 { 0x1f, 0x0000 }
3272 };
3273
4da19633 3274 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3275}
3276
e6de30d6 3277static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3278{
3279 static const struct phy_reg phy_reg_init[] = {
3280 { 0x1f, 0x0001 },
3281 { 0x17, 0x0cc0 },
3282
3283 { 0x1f, 0x0007 },
3284 { 0x1e, 0x002d },
3285 { 0x18, 0x0040 },
3286 { 0x1f, 0x0000 }
3287 };
3288
3289 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3290 rtl_patchphy(tp, 0x0d, 1 << 5);
3291}
3292
70090424 3293static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3294{
3295 static const struct phy_reg phy_reg_init[] = {
3296 /* Enable Delay cap */
3297 { 0x1f, 0x0005 },
3298 { 0x05, 0x8b80 },
3299 { 0x06, 0xc896 },
3300 { 0x1f, 0x0000 },
3301
3302 /* Channel estimation fine tune */
3303 { 0x1f, 0x0001 },
3304 { 0x0b, 0x6c20 },
3305 { 0x07, 0x2872 },
3306 { 0x1c, 0xefff },
3307 { 0x1f, 0x0003 },
3308 { 0x14, 0x6420 },
3309 { 0x1f, 0x0000 },
3310
3311 /* Update PFM & 10M TX idle timer */
3312 { 0x1f, 0x0007 },
3313 { 0x1e, 0x002f },
3314 { 0x15, 0x1919 },
3315 { 0x1f, 0x0000 },
3316
3317 { 0x1f, 0x0007 },
3318 { 0x1e, 0x00ac },
3319 { 0x18, 0x0006 },
3320 { 0x1f, 0x0000 }
3321 };
3322
15ecd039
FR		 3323 rtl_apply_firmware(tp);
3324
01dc7fec 3325 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3326
3327 /* DCO enable for 10M IDLE Power */
3328 rtl_writephy(tp, 0x1f, 0x0007);
3329 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3330 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3331 rtl_writephy(tp, 0x1f, 0x0000);
3332
3333 /* For impedance matching */
3334 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3335 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3336 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3337
3338 /* PHY auto speed down */
3339 rtl_writephy(tp, 0x1f, 0x0007);
3340 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3341 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3342 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3343 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3344
3345 rtl_writephy(tp, 0x1f, 0x0005);
3346 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3347 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3348 rtl_writephy(tp, 0x1f, 0x0000);
3349
3350 rtl_writephy(tp, 0x1f, 0x0005);
3351 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3352 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3353 rtl_writephy(tp, 0x1f, 0x0007);
3354 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3355 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3356 rtl_writephy(tp, 0x1f, 0x0006);
3357 rtl_writephy(tp, 0x00, 0x5a00);
3358 rtl_writephy(tp, 0x1f, 0x0000);
3359 rtl_writephy(tp, 0x0d, 0x0007);
3360 rtl_writephy(tp, 0x0e, 0x003c);
3361 rtl_writephy(tp, 0x0d, 0x4007);
3362 rtl_writephy(tp, 0x0e, 0x0000);
3363 rtl_writephy(tp, 0x0d, 0x0000);
3364}
3365
9ecb9aab 3366static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3367{
3368 const u16 w[] = {
3369 addr[0] | (addr[1] << 8),
3370 addr[2] | (addr[3] << 8),
3371 addr[4] | (addr[5] << 8)
3372 };
3373 const struct exgmac_reg e[] = {
3374 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3375 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3376 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3377 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3378 };
3379
3380 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3381}
3382
70090424
HW		 3383static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3384{
3385 static const struct phy_reg phy_reg_init[] = {
3386 /* Enable Delay cap */
3387 { 0x1f, 0x0004 },
3388 { 0x1f, 0x0007 },
3389 { 0x1e, 0x00ac },
3390 { 0x18, 0x0006 },
3391 { 0x1f, 0x0002 },
3392 { 0x1f, 0x0000 },
3393 { 0x1f, 0x0000 },
3394
3395 /* Channel estimation fine tune */
3396 { 0x1f, 0x0003 },
3397 { 0x09, 0xa20f },
3398 { 0x1f, 0x0000 },
3399 { 0x1f, 0x0000 },
3400
3401 /* Green Setting */
3402 { 0x1f, 0x0005 },
3403 { 0x05, 0x8b5b },
3404 { 0x06, 0x9222 },
3405 { 0x05, 0x8b6d },
3406 { 0x06, 0x8000 },
3407 { 0x05, 0x8b76 },
3408 { 0x06, 0x8000 },
3409 { 0x1f, 0x0000 }
3410 };
3411
3412 rtl_apply_firmware(tp);
3413
3414 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3415
3416 /* For 4-corner performance improve */
3417 rtl_writephy(tp, 0x1f, 0x0005);
3418 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3419 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3420 rtl_writephy(tp, 0x1f, 0x0000);
3421
3422 /* PHY auto speed down */
3423 rtl_writephy(tp, 0x1f, 0x0004);
3424 rtl_writephy(tp, 0x1f, 0x0007);
3425 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3426 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3427 rtl_writephy(tp, 0x1f, 0x0002);
3428 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3429 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3430
3431 /* improve 10M EEE waveform */
3432 rtl_writephy(tp, 0x1f, 0x0005);
3433 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3434 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3435 rtl_writephy(tp, 0x1f, 0x0000);
3436
3437 /* Improve 2-pair detection performance */
3438 rtl_writephy(tp, 0x1f, 0x0005);
3439 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3440 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3441 rtl_writephy(tp, 0x1f, 0x0000);
3442
3443 /* EEE setting */
1814d6a8 3444 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
70090424
HW		 3445 rtl_writephy(tp, 0x1f, 0x0005);
3446 rtl_writephy(tp, 0x05, 0x8b85);
1814d6a8 3447 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
70090424
HW		 3448 rtl_writephy(tp, 0x1f, 0x0004);
3449 rtl_writephy(tp, 0x1f, 0x0007);
3450 rtl_writephy(tp, 0x1e, 0x0020);
1814d6a8 3451 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
70090424
HW		 3452 rtl_writephy(tp, 0x1f, 0x0002);
3453 rtl_writephy(tp, 0x1f, 0x0000);
3454 rtl_writephy(tp, 0x0d, 0x0007);
3455 rtl_writephy(tp, 0x0e, 0x003c);
3456 rtl_writephy(tp, 0x0d, 0x4007);
1814d6a8 3457 rtl_writephy(tp, 0x0e, 0x0006);
70090424
HW		 3458 rtl_writephy(tp, 0x0d, 0x0000);
3459
3460 /* Green feature */
3461 rtl_writephy(tp, 0x1f, 0x0003);
1814d6a8
HK		 3462 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3463 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
70090424 3464 rtl_writephy(tp, 0x1f, 0x0000);
b399a394
HK		 3465 rtl_writephy(tp, 0x1f, 0x0005);
3466 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3467 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3468
9ecb9aab 3469 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3470 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3471}
3472
5f886e08
HW		 3473static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3474{
3475 /* For 4-corner performance improve */
3476 rtl_writephy(tp, 0x1f, 0x0005);
3477 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3478 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3479 rtl_writephy(tp, 0x1f, 0x0000);
3480
3481 /* PHY auto speed down */
3482 rtl_writephy(tp, 0x1f, 0x0007);
3483 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3484 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3485 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3486 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3487
3488 /* Improve 10M EEE waveform */
3489 rtl_writephy(tp, 0x1f, 0x0005);
3490 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3491 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3492 rtl_writephy(tp, 0x1f, 0x0000);
3493}
3494
c2218925
HW		 3495static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3496{
3497 static const struct phy_reg phy_reg_init[] = {
3498 /* Channel estimation fine tune */
3499 { 0x1f, 0x0003 },
3500 { 0x09, 0xa20f },
3501 { 0x1f, 0x0000 },
3502
3503 /* Modify green table for giga & fnet */
3504 { 0x1f, 0x0005 },
3505 { 0x05, 0x8b55 },
3506 { 0x06, 0x0000 },
3507 { 0x05, 0x8b5e },
3508 { 0x06, 0x0000 },
3509 { 0x05, 0x8b67 },
3510 { 0x06, 0x0000 },
3511 { 0x05, 0x8b70 },
3512 { 0x06, 0x0000 },
3513 { 0x1f, 0x0000 },
3514 { 0x1f, 0x0007 },
3515 { 0x1e, 0x0078 },
3516 { 0x17, 0x0000 },
3517 { 0x19, 0x00fb },
3518 { 0x1f, 0x0000 },
3519
3520 /* Modify green table for 10M */
3521 { 0x1f, 0x0005 },
3522 { 0x05, 0x8b79 },
3523 { 0x06, 0xaa00 },
3524 { 0x1f, 0x0000 },
3525
3526 /* Disable hiimpedance detection (RTCT) */
3527 { 0x1f, 0x0003 },
3528 { 0x01, 0x328a },
3529 { 0x1f, 0x0000 }
3530 };
3531
3532 rtl_apply_firmware(tp);
3533
3534 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3535
5f886e08 3536 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3537
3538 /* Improve 2-pair detection performance */
3539 rtl_writephy(tp, 0x1f, 0x0005);
3540 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3541 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3542 rtl_writephy(tp, 0x1f, 0x0000);
3543}
3544
3545static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3546{
3547 rtl_apply_firmware(tp);
3548
5f886e08 3549 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3550}
3551
b3d7b2f2
HW		 3552static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3553{
b3d7b2f2
HW		 3554 static const struct phy_reg phy_reg_init[] = {
3555 /* Channel estimation fine tune */
3556 { 0x1f, 0x0003 },
3557 { 0x09, 0xa20f },
3558 { 0x1f, 0x0000 },
3559
3560 /* Modify green table for giga & fnet */
3561 { 0x1f, 0x0005 },
3562 { 0x05, 0x8b55 },
3563 { 0x06, 0x0000 },
3564 { 0x05, 0x8b5e },
3565 { 0x06, 0x0000 },
3566 { 0x05, 0x8b67 },
3567 { 0x06, 0x0000 },
3568 { 0x05, 0x8b70 },
3569 { 0x06, 0x0000 },
3570 { 0x1f, 0x0000 },
3571 { 0x1f, 0x0007 },
3572 { 0x1e, 0x0078 },
3573 { 0x17, 0x0000 },
3574 { 0x19, 0x00aa },
3575 { 0x1f, 0x0000 },
3576
3577 /* Modify green table for 10M */
3578 { 0x1f, 0x0005 },
3579 { 0x05, 0x8b79 },
3580 { 0x06, 0xaa00 },
3581 { 0x1f, 0x0000 },
3582
3583 /* Disable hiimpedance detection (RTCT) */
3584 { 0x1f, 0x0003 },
3585 { 0x01, 0x328a },
3586 { 0x1f, 0x0000 }
3587 };
3588
3589
3590 rtl_apply_firmware(tp);
3591
3592 rtl8168f_hw_phy_config(tp);
3593
3594 /* Improve 2-pair detection performance */
3595 rtl_writephy(tp, 0x1f, 0x0005);
3596 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3597 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3598 rtl_writephy(tp, 0x1f, 0x0000);
3599
3600 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3601
3602 /* Modify green table for giga */
3603 rtl_writephy(tp, 0x1f, 0x0005);
3604 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3605 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3606 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3607 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3608 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3609 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3610 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3611 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3612 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3613 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3614 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3615 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3616 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3617 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3618 rtl_writephy(tp, 0x1f, 0x0000);
3619
3620 /* uc same-seed solution */
3621 rtl_writephy(tp, 0x1f, 0x0005);
3622 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3623 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3624 rtl_writephy(tp, 0x1f, 0x0000);
3625
3626 /* eee setting */
706123d0 3627 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3628 rtl_writephy(tp, 0x1f, 0x0005);
3629 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3630 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3631 rtl_writephy(tp, 0x1f, 0x0004);
3632 rtl_writephy(tp, 0x1f, 0x0007);
3633 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3634 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3635 rtl_writephy(tp, 0x1f, 0x0000);
3636 rtl_writephy(tp, 0x0d, 0x0007);
3637 rtl_writephy(tp, 0x0e, 0x003c);
3638 rtl_writephy(tp, 0x0d, 0x4007);
3639 rtl_writephy(tp, 0x0e, 0x0000);
3640 rtl_writephy(tp, 0x0d, 0x0000);
3641
3642 /* Green feature */
3643 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3644 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3645 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3646 rtl_writephy(tp, 0x1f, 0x0000);
3647}
3648
c558386b
HW		 3649static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3650{
c558386b
HW		 3651 rtl_apply_firmware(tp);
3652
41f44d13 3653 rtl_writephy(tp, 0x1f, 0x0a46);
3654 if (rtl_readphy(tp, 0x10) & 0x0100) {
3655 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3656 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3657 } else {
3658 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3659 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3660 }
c558386b 3661
41f44d13 3662 rtl_writephy(tp, 0x1f, 0x0a46);
3663 if (rtl_readphy(tp, 0x13) & 0x0100) {
3664 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3665 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 3666 } else {
fe7524c0 3667 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3668 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3669 }
c558386b 3670
41f44d13 3671 /* Enable PHY auto speed down */
3672 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3673 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3674
fe7524c0 3675 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3676 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 3677 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3678 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 3679 rtl_writephy(tp, 0x1f, 0x0a43);
3680 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 3681 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3682 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 3683
41f44d13 3684 /* EEE auto-fallback function */
3685 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 3686 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3687
41f44d13 3688 /* Enable UC LPF tune function */
3689 rtl_writephy(tp, 0x1f, 0x0a43);
3690 rtl_writephy(tp, 0x13, 0x8012);
76564428 3691 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 3692
3693 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 3694 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 3695
fe7524c0 3696 /* Improve SWR Efficiency */
3697 rtl_writephy(tp, 0x1f, 0x0bcd);
3698 rtl_writephy(tp, 0x14, 0x5065);
3699 rtl_writephy(tp, 0x14, 0xd065);
3700 rtl_writephy(tp, 0x1f, 0x0bc8);
3701 rtl_writephy(tp, 0x11, 0x5655);
3702 rtl_writephy(tp, 0x1f, 0x0bcd);
3703 rtl_writephy(tp, 0x14, 0x1065);
3704 rtl_writephy(tp, 0x14, 0x9065);
3705 rtl_writephy(tp, 0x14, 0x1065);
3706
1bac1072
DC		 3707 /* Check ALDPS bit, disable it if enabled */
3708 rtl_writephy(tp, 0x1f, 0x0a43);
3709 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3710 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 3711
41f44d13 3712 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3713}
3714
57538c4a 3715static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3716{
3717 rtl_apply_firmware(tp);
3718}
3719
6e1d0b89
CHL		 3720static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3721{
3722 u16 dout_tapbin;
3723 u32 data;
3724
3725 rtl_apply_firmware(tp);
3726
3727 /* CHN EST parameters adjust - giga master */
3728 rtl_writephy(tp, 0x1f, 0x0a43);
3729 rtl_writephy(tp, 0x13, 0x809b);
76564428 3730 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 3731 rtl_writephy(tp, 0x13, 0x80a2);
76564428 3732 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 3733 rtl_writephy(tp, 0x13, 0x80a4);
76564428 3734 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 3735 rtl_writephy(tp, 0x13, 0x809c);
76564428 3736 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 3737 rtl_writephy(tp, 0x1f, 0x0000);
3738
3739 /* CHN EST parameters adjust - giga slave */
3740 rtl_writephy(tp, 0x1f, 0x0a43);
3741 rtl_writephy(tp, 0x13, 0x80ad);
76564428 3742 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 3743 rtl_writephy(tp, 0x13, 0x80b4);
76564428 3744 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 3745 rtl_writephy(tp, 0x13, 0x80ac);
76564428 3746 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 3747 rtl_writephy(tp, 0x1f, 0x0000);
3748
3749 /* CHN EST parameters adjust - fnet */
3750 rtl_writephy(tp, 0x1f, 0x0a43);
3751 rtl_writephy(tp, 0x13, 0x808e);
76564428 3752 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 3753 rtl_writephy(tp, 0x13, 0x8090);
76564428 3754 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 3755 rtl_writephy(tp, 0x13, 0x8092);
76564428 3756 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 3757 rtl_writephy(tp, 0x1f, 0x0000);
3758
3759 /* enable R-tune & PGA-retune function */
3760 dout_tapbin = 0;
3761 rtl_writephy(tp, 0x1f, 0x0a46);
3762 data = rtl_readphy(tp, 0x13);
3763 data &= 3;
3764 data <<= 2;
3765 dout_tapbin |= data;
3766 data = rtl_readphy(tp, 0x12);
3767 data &= 0xc000;
3768 data >>= 14;
3769 dout_tapbin |= data;
3770 dout_tapbin = ~(dout_tapbin^0x08);
3771 dout_tapbin <<= 12;
3772 dout_tapbin &= 0xf000;
3773 rtl_writephy(tp, 0x1f, 0x0a43);
3774 rtl_writephy(tp, 0x13, 0x827a);
76564428 3775 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3776 rtl_writephy(tp, 0x13, 0x827b);
76564428 3777 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3778 rtl_writephy(tp, 0x13, 0x827c);
76564428 3779 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3780 rtl_writephy(tp, 0x13, 0x827d);
76564428 3781 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 3782
3783 rtl_writephy(tp, 0x1f, 0x0a43);
3784 rtl_writephy(tp, 0x13, 0x0811);
76564428 3785 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3786 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3787 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3788 rtl_writephy(tp, 0x1f, 0x0000);
3789
3790 /* enable GPHY 10M */
3791 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3792 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3793 rtl_writephy(tp, 0x1f, 0x0000);
3794
3795 /* SAR ADC performance */
3796 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 3797 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 3798 rtl_writephy(tp, 0x1f, 0x0000);
3799
3800 rtl_writephy(tp, 0x1f, 0x0a43);
3801 rtl_writephy(tp, 0x13, 0x803f);
76564428 3802 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3803 rtl_writephy(tp, 0x13, 0x8047);
76564428 3804 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3805 rtl_writephy(tp, 0x13, 0x804f);
76564428 3806 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3807 rtl_writephy(tp, 0x13, 0x8057);
76564428 3808 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3809 rtl_writephy(tp, 0x13, 0x805f);
76564428 3810 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3811 rtl_writephy(tp, 0x13, 0x8067);
76564428 3812 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3813 rtl_writephy(tp, 0x13, 0x806f);
76564428 3814 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 3815 rtl_writephy(tp, 0x1f, 0x0000);
3816
3817 /* disable phy pfm mode */
3818 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3819 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3820 rtl_writephy(tp, 0x1f, 0x0000);
3821
3822 /* Check ALDPS bit, disable it if enabled */
3823 rtl_writephy(tp, 0x1f, 0x0a43);
3824 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3825 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3826
3827 rtl_writephy(tp, 0x1f, 0x0000);
3828}
3829
3830static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3831{
3832 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3833 u16 rlen;
3834 u32 data;
3835
3836 rtl_apply_firmware(tp);
3837
3838 /* CHIN EST parameter update */
3839 rtl_writephy(tp, 0x1f, 0x0a43);
3840 rtl_writephy(tp, 0x13, 0x808a);
76564428 3841 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 3842 rtl_writephy(tp, 0x1f, 0x0000);
3843
3844 /* enable R-tune & PGA-retune function */
3845 rtl_writephy(tp, 0x1f, 0x0a43);
3846 rtl_writephy(tp, 0x13, 0x0811);
76564428 3847 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3848 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3849 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3850 rtl_writephy(tp, 0x1f, 0x0000);
3851
3852 /* enable GPHY 10M */
3853 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3854 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3855 rtl_writephy(tp, 0x1f, 0x0000);
3856
3857 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3858 data = r8168_mac_ocp_read(tp, 0xdd02);
3859 ioffset_p3 = ((data & 0x80)>>7);
3860 ioffset_p3 <<= 3;
3861
3862 data = r8168_mac_ocp_read(tp, 0xdd00);
3863 ioffset_p3 |= ((data & (0xe000))>>13);
3864 ioffset_p2 = ((data & (0x1e00))>>9);
3865 ioffset_p1 = ((data & (0x01e0))>>5);
3866 ioffset_p0 = ((data & 0x0010)>>4);
3867 ioffset_p0 <<= 3;
3868 ioffset_p0 |= (data & (0x07));
3869 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3870
05b9687b 3871 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
e2e2788e 3872 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
6e1d0b89
CHL		 3873 rtl_writephy(tp, 0x1f, 0x0bcf);
3874 rtl_writephy(tp, 0x16, data);
3875 rtl_writephy(tp, 0x1f, 0x0000);
3876 }
3877
3878 /* Modify rlen (TX LPF corner frequency) level */
3879 rtl_writephy(tp, 0x1f, 0x0bcd);
3880 data = rtl_readphy(tp, 0x16);
3881 data &= 0x000f;
3882 rlen = 0;
3883 if (data > 3)
3884 rlen = data - 3;
3885 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3886 rtl_writephy(tp, 0x17, data);
3887 rtl_writephy(tp, 0x1f, 0x0bcd);
3888 rtl_writephy(tp, 0x1f, 0x0000);
3889
3890 /* disable phy pfm mode */
3891 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3892 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3893 rtl_writephy(tp, 0x1f, 0x0000);
3894
3895 /* Check ALDPS bit, disable it if enabled */
3896 rtl_writephy(tp, 0x1f, 0x0a43);
3897 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3898 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3899
3900 rtl_writephy(tp, 0x1f, 0x0000);
3901}
3902
935e2218
CHL		 3903static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3904{
3905 /* Enable PHY auto speed down */
3906 rtl_writephy(tp, 0x1f, 0x0a44);
3907 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3908 rtl_writephy(tp, 0x1f, 0x0000);
3909
3910 /* patch 10M & ALDPS */
3911 rtl_writephy(tp, 0x1f, 0x0bcc);
3912 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3913 rtl_writephy(tp, 0x1f, 0x0a44);
3914 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3915 rtl_writephy(tp, 0x1f, 0x0a43);
3916 rtl_writephy(tp, 0x13, 0x8084);
3917 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3918 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3919 rtl_writephy(tp, 0x1f, 0x0000);
3920
3921 /* Enable EEE auto-fallback function */
3922 rtl_writephy(tp, 0x1f, 0x0a4b);
3923 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3924 rtl_writephy(tp, 0x1f, 0x0000);
3925
3926 /* Enable UC LPF tune function */
3927 rtl_writephy(tp, 0x1f, 0x0a43);
3928 rtl_writephy(tp, 0x13, 0x8012);
3929 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3930 rtl_writephy(tp, 0x1f, 0x0000);
3931
3932 /* set rg_sel_sdm_rate */
3933 rtl_writephy(tp, 0x1f, 0x0c42);
3934 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3935 rtl_writephy(tp, 0x1f, 0x0000);
3936
3937 /* Check ALDPS bit, disable it if enabled */
3938 rtl_writephy(tp, 0x1f, 0x0a43);
3939 if (rtl_readphy(tp, 0x10) & 0x0004)
3940 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3941
3942 rtl_writephy(tp, 0x1f, 0x0000);
3943}
3944
3945static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3946{
3947 /* patch 10M & ALDPS */
3948 rtl_writephy(tp, 0x1f, 0x0bcc);
3949 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3950 rtl_writephy(tp, 0x1f, 0x0a44);
3951 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3952 rtl_writephy(tp, 0x1f, 0x0a43);
3953 rtl_writephy(tp, 0x13, 0x8084);
3954 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3955 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3956 rtl_writephy(tp, 0x1f, 0x0000);
3957
3958 /* Enable UC LPF tune function */
3959 rtl_writephy(tp, 0x1f, 0x0a43);
3960 rtl_writephy(tp, 0x13, 0x8012);
3961 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3962 rtl_writephy(tp, 0x1f, 0x0000);
3963
3964 /* Set rg_sel_sdm_rate */
3965 rtl_writephy(tp, 0x1f, 0x0c42);
3966 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3967 rtl_writephy(tp, 0x1f, 0x0000);
3968
3969 /* Channel estimation parameters */
3970 rtl_writephy(tp, 0x1f, 0x0a43);
3971 rtl_writephy(tp, 0x13, 0x80f3);
3972 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3973 rtl_writephy(tp, 0x13, 0x80f0);
3974 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3975 rtl_writephy(tp, 0x13, 0x80ef);
3976 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3977 rtl_writephy(tp, 0x13, 0x80f6);
3978 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3979 rtl_writephy(tp, 0x13, 0x80ec);
3980 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3981 rtl_writephy(tp, 0x13, 0x80ed);
3982 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3983 rtl_writephy(tp, 0x13, 0x80f2);
3984 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3985 rtl_writephy(tp, 0x13, 0x80f4);
3986 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3987 rtl_writephy(tp, 0x1f, 0x0a43);
3988 rtl_writephy(tp, 0x13, 0x8110);
3989 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3990 rtl_writephy(tp, 0x13, 0x810f);
3991 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3992 rtl_writephy(tp, 0x13, 0x8111);
3993 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3994 rtl_writephy(tp, 0x13, 0x8113);
3995 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3996 rtl_writephy(tp, 0x13, 0x8115);
3997 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3998 rtl_writephy(tp, 0x13, 0x810e);
3999 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4000 rtl_writephy(tp, 0x13, 0x810c);
4001 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4002 rtl_writephy(tp, 0x13, 0x810b);
4003 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4004 rtl_writephy(tp, 0x1f, 0x0a43);
4005 rtl_writephy(tp, 0x13, 0x80d1);
4006 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4007 rtl_writephy(tp, 0x13, 0x80cd);
4008 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4009 rtl_writephy(tp, 0x13, 0x80d3);
4010 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4011 rtl_writephy(tp, 0x13, 0x80d5);
4012 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4013 rtl_writephy(tp, 0x13, 0x80d7);
4014 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4015
4016 /* Force PWM-mode */
4017 rtl_writephy(tp, 0x1f, 0x0bcd);
4018 rtl_writephy(tp, 0x14, 0x5065);
4019 rtl_writephy(tp, 0x14, 0xd065);
4020 rtl_writephy(tp, 0x1f, 0x0bc8);
4021 rtl_writephy(tp, 0x12, 0x00ed);
4022 rtl_writephy(tp, 0x1f, 0x0bcd);
4023 rtl_writephy(tp, 0x14, 0x1065);
4024 rtl_writephy(tp, 0x14, 0x9065);
4025 rtl_writephy(tp, 0x14, 0x1065);
4026 rtl_writephy(tp, 0x1f, 0x0000);
4027
4028 /* Check ALDPS bit, disable it if enabled */
4029 rtl_writephy(tp, 0x1f, 0x0a43);
4030 if (rtl_readphy(tp, 0x10) & 0x0004)
4031 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4032
4033 rtl_writephy(tp, 0x1f, 0x0000);
4034}
4035
4da19633 4036static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 4037{
350f7596 4038 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 4039 { 0x1f, 0x0003 },
4040 { 0x08, 0x441d },
4041 { 0x01, 0x9100 },
4042 { 0x1f, 0x0000 }
4043 };
4044
4da19633 4045 rtl_writephy(tp, 0x1f, 0x0000);
4046 rtl_patchphy(tp, 0x11, 1 << 12);
4047 rtl_patchphy(tp, 0x19, 1 << 13);
4048 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 4049
4da19633 4050 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 4051}
4052
5a5e4443
HW		 4053static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4054{
4055 static const struct phy_reg phy_reg_init[] = {
4056 { 0x1f, 0x0005 },
4057 { 0x1a, 0x0000 },
4058 { 0x1f, 0x0000 },
4059
4060 { 0x1f, 0x0004 },
4061 { 0x1c, 0x0000 },
4062 { 0x1f, 0x0000 },
4063
4064 { 0x1f, 0x0001 },
4065 { 0x15, 0x7701 },
4066 { 0x1f, 0x0000 }
4067 };
4068
4069 /* Disable ALDPS before ram code */
eef63cc1
FR		 4070 rtl_writephy(tp, 0x1f, 0x0000);
4071 rtl_writephy(tp, 0x18, 0x0310);
4072 msleep(100);
5a5e4443 4073
953a12cc 4074 rtl_apply_firmware(tp);
5a5e4443
HW		 4075
4076 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4077}
4078
7e18dca1
HW		 4079static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4080{
7e18dca1 4081 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 4082 rtl_writephy(tp, 0x1f, 0x0000);
4083 rtl_writephy(tp, 0x18, 0x0310);
4084 msleep(20);
7e18dca1
HW		 4085
4086 rtl_apply_firmware(tp);
4087
4088 /* EEE setting */
fdf6fc06 4089 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 4090 rtl_writephy(tp, 0x1f, 0x0004);
4091 rtl_writephy(tp, 0x10, 0x401f);
4092 rtl_writephy(tp, 0x19, 0x7030);
4093 rtl_writephy(tp, 0x1f, 0x0000);
4094}
4095
5598bfe5
HW		 4096static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4097{
5598bfe5
HW		 4098 static const struct phy_reg phy_reg_init[] = {
4099 { 0x1f, 0x0004 },
4100 { 0x10, 0xc07f },
4101 { 0x19, 0x7030 },
4102 { 0x1f, 0x0000 }
4103 };
4104
4105 /* Disable ALDPS before ram code */
eef63cc1
FR		 4106 rtl_writephy(tp, 0x1f, 0x0000);
4107 rtl_writephy(tp, 0x18, 0x0310);
4108 msleep(100);
5598bfe5
HW		 4109
4110 rtl_apply_firmware(tp);
4111
fdf6fc06 4112 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4113 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4114
fdf6fc06 4115 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4116}
4117
5615d9f1
FR		 4118static void rtl_hw_phy_config(struct net_device *dev)
4119{
4120 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 4121
4122 rtl8169_print_mac_version(tp);
4123
4124 switch (tp->mac_version) {
4125 case RTL_GIGA_MAC_VER_01:
4126 break;
4127 case RTL_GIGA_MAC_VER_02:
4128 case RTL_GIGA_MAC_VER_03:
4da19633 4129 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 4130 break;
4131 case RTL_GIGA_MAC_VER_04:
4da19633 4132 rtl8169sb_hw_phy_config(tp);
5615d9f1 4133 break;
2e955856 4134 case RTL_GIGA_MAC_VER_05:
4da19633 4135 rtl8169scd_hw_phy_config(tp);
2e955856 4136 break;
8c7006aa 4137 case RTL_GIGA_MAC_VER_06:
4da19633 4138 rtl8169sce_hw_phy_config(tp);
8c7006aa 4139 break;
2857ffb7
FR		 4140 case RTL_GIGA_MAC_VER_07:
4141 case RTL_GIGA_MAC_VER_08:
4142 case RTL_GIGA_MAC_VER_09:
4da19633 4143 rtl8102e_hw_phy_config(tp);
2857ffb7 4144 break;
236b8082 4145 case RTL_GIGA_MAC_VER_11:
4da19633 4146 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 4147 break;
4148 case RTL_GIGA_MAC_VER_12:
4da19633 4149 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 4150 break;
4151 case RTL_GIGA_MAC_VER_17:
4da19633 4152 rtl8168bef_hw_phy_config(tp);
236b8082 4153 break;
867763c1 4154 case RTL_GIGA_MAC_VER_18:
4da19633 4155 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 4156 break;
4157 case RTL_GIGA_MAC_VER_19:
4da19633 4158 rtl8168c_1_hw_phy_config(tp);
867763c1 4159 break;
7da97ec9 4160 case RTL_GIGA_MAC_VER_20:
4da19633 4161 rtl8168c_2_hw_phy_config(tp);
7da97ec9 4162 break;
197ff761 4163 case RTL_GIGA_MAC_VER_21:
4da19633 4164 rtl8168c_3_hw_phy_config(tp);
197ff761 4165 break;
6fb07058 4166 case RTL_GIGA_MAC_VER_22:
4da19633 4167 rtl8168c_4_hw_phy_config(tp);
6fb07058 4168 break;
ef3386f0 4169 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 4170 case RTL_GIGA_MAC_VER_24:
4da19633 4171 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 4172 break;
5b538df9 4173 case RTL_GIGA_MAC_VER_25:
bca03d5f 4174 rtl8168d_1_hw_phy_config(tp);
daf9df6d 4175 break;
4176 case RTL_GIGA_MAC_VER_26:
bca03d5f 4177 rtl8168d_2_hw_phy_config(tp);
daf9df6d 4178 break;
4179 case RTL_GIGA_MAC_VER_27:
4da19633 4180 rtl8168d_3_hw_phy_config(tp);
5b538df9 4181 break;
e6de30d6 4182 case RTL_GIGA_MAC_VER_28:
4183 rtl8168d_4_hw_phy_config(tp);
4184 break;
5a5e4443
HW		 4185 case RTL_GIGA_MAC_VER_29:
4186 case RTL_GIGA_MAC_VER_30:
4187 rtl8105e_hw_phy_config(tp);
4188 break;
cecb5fd7
FR		 4189 case RTL_GIGA_MAC_VER_31:
4190 /* None. */
4191 break;
01dc7fec 4192 case RTL_GIGA_MAC_VER_32:
01dc7fec 4193 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4194 rtl8168e_1_hw_phy_config(tp);
4195 break;
4196 case RTL_GIGA_MAC_VER_34:
4197 rtl8168e_2_hw_phy_config(tp);
01dc7fec 4198 break;
c2218925
HW		 4199 case RTL_GIGA_MAC_VER_35:
4200 rtl8168f_1_hw_phy_config(tp);
4201 break;
4202 case RTL_GIGA_MAC_VER_36:
4203 rtl8168f_2_hw_phy_config(tp);
4204 break;
ef3386f0 4205
7e18dca1
HW		 4206 case RTL_GIGA_MAC_VER_37:
4207 rtl8402_hw_phy_config(tp);
4208 break;
4209
b3d7b2f2
HW		 4210 case RTL_GIGA_MAC_VER_38:
4211 rtl8411_hw_phy_config(tp);
4212 break;
4213
5598bfe5
HW		 4214 case RTL_GIGA_MAC_VER_39:
4215 rtl8106e_hw_phy_config(tp);
4216 break;
4217
c558386b
HW		 4218 case RTL_GIGA_MAC_VER_40:
4219 rtl8168g_1_hw_phy_config(tp);
4220 break;
57538c4a 4221 case RTL_GIGA_MAC_VER_42:
58152cd4 4222 case RTL_GIGA_MAC_VER_43:
45dd95c4 4223 case RTL_GIGA_MAC_VER_44:
57538c4a 4224 rtl8168g_2_hw_phy_config(tp);
4225 break;
6e1d0b89
CHL		 4226 case RTL_GIGA_MAC_VER_45:
4227 case RTL_GIGA_MAC_VER_47:
4228 rtl8168h_1_hw_phy_config(tp);
4229 break;
4230 case RTL_GIGA_MAC_VER_46:
4231 case RTL_GIGA_MAC_VER_48:
4232 rtl8168h_2_hw_phy_config(tp);
4233 break;
c558386b 4234
935e2218
CHL		 4235 case RTL_GIGA_MAC_VER_49:
4236 rtl8168ep_1_hw_phy_config(tp);
4237 break;
4238 case RTL_GIGA_MAC_VER_50:
4239 case RTL_GIGA_MAC_VER_51:
4240 rtl8168ep_2_hw_phy_config(tp);
4241 break;
4242
c558386b 4243 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 4244 default:
4245 break;
4246 }
4247}
4248
da78dbff
FR		 4249static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4250{
da78dbff
FR		 4251 if (!test_and_set_bit(flag, tp->wk.flags))
4252 schedule_work(&tp->wk.work);
da78dbff
FR		 4253}
4254
ffc46952
FR		 4255DECLARE_RTL_COND(rtl_phy_reset_cond)
4256{
e397286b 4257 return rtl8169_xmii_reset_pending(tp);
ffc46952
FR		 4258}
4259
bf793295
FR		 4260static void rtl8169_phy_reset(struct net_device *dev,
4261 struct rtl8169_private *tp)
4262{
e397286b 4263 rtl8169_xmii_reset_enable(tp);
ffc46952 4264 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 4265}
4266
2544bfc0
FR		 4267static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4268{
2544bfc0 4269 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
e397286b 4270 (RTL_R8(tp, PHYstatus) & TBI_Enable);
2544bfc0
FR		 4271}
4272
4ff96fa6
FR		 4273static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4274{
5615d9f1 4275 rtl_hw_phy_config(dev);
4ff96fa6 4276
77332894 4277 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
49d17512
HK		 4278 netif_dbg(tp, drv, dev,
4279 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 4280 RTL_W8(tp, 0x82, 0x01);
77332894 4281 }
4ff96fa6 4282
6dccd16b
FR		 4283 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4284
4285 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4286 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4287
bcf0bf90 4288 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
49d17512
HK		 4289 netif_dbg(tp, drv, dev,
4290 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 4291 RTL_W8(tp, 0x82, 0x01);
49d17512
HK		 4292 netif_dbg(tp, drv, dev,
4293 "Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4294 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4295 }
4296
bf793295
FR		 4297 rtl8169_phy_reset(dev, tp);
4298
54405cde 4299 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 4300 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4301 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4302 (tp->mii.supports_gmii ?
4303 ADVERTISED_1000baseT_Half |
4304 ADVERTISED_1000baseT_Full : 0));
4ff96fa6
FR		 4305}
4306
773d2021
FR		 4307static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4308{
da78dbff 4309 rtl_lock_work(tp);
773d2021 4310
1ef7286e 4311 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
908ba2bf 4312
1ef7286e
AS		 4313 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4314 RTL_R32(tp, MAC4);
908ba2bf 4315
1ef7286e
AS		 4316 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4317 RTL_R32(tp, MAC0);
908ba2bf 4318
9ecb9aab 4319 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4320 rtl_rar_exgmac_set(tp, addr);
c28aa385 4321
1ef7286e 4322 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
773d2021 4323
da78dbff 4324 rtl_unlock_work(tp);
773d2021
FR		 4325}
4326
4327static int rtl_set_mac_address(struct net_device *dev, void *p)
4328{
4329 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 4330 struct device *d = tp_to_dev(tp);
1f7aa2bc 4331 int ret;
773d2021 4332
1f7aa2bc
HK		 4333 ret = eth_mac_addr(dev, p);
4334 if (ret)
4335 return ret;
773d2021 4336
f51d4a10
CHL		 4337 pm_runtime_get_noresume(d);
4338
4339 if (pm_runtime_active(d))
4340 rtl_rar_set(tp, dev->dev_addr);
4341
4342 pm_runtime_put_noidle(d);
773d2021
FR		 4343
4344 return 0;
4345}
4346
cecb5fd7
FR		 4347static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4348 struct mii_ioctl_data *data, int cmd)
8b4ab28d 4349{
5f787a1a
FR		 4350 switch (cmd) {
4351 case SIOCGMIIPHY:
4352 data->phy_id = 32; /* Internal PHY */
4353 return 0;
4354
4355 case SIOCGMIIREG:
4da19633 4356 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 4357 return 0;
4358
4359 case SIOCSMIIREG:
4da19633 4360 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 4361 return 0;
4362 }
4363 return -EOPNOTSUPP;
4364}
4365
e397286b 4366static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8b4ab28d 4367{
e397286b
HK		 4368 struct rtl8169_private *tp = netdev_priv(dev);
4369 struct mii_ioctl_data *data = if_mii(ifr);
4370
4371 return netif_running(dev) ? rtl_xmii_ioctl(tp, data, cmd) : -ENODEV;
8b4ab28d
FR		 4372}
4373
baf63293 4374static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4375{
4376 struct mdio_ops *ops = &tp->mdio_ops;
4377
4378 switch (tp->mac_version) {
4379 case RTL_GIGA_MAC_VER_27:
4380 ops->write = r8168dp_1_mdio_write;
4381 ops->read = r8168dp_1_mdio_read;
4382 break;
e6de30d6 4383 case RTL_GIGA_MAC_VER_28:
4804b3b3 4384 case RTL_GIGA_MAC_VER_31:
e6de30d6 4385 ops->write = r8168dp_2_mdio_write;
4386 ops->read = r8168dp_2_mdio_read;
4387 break;
2a71883c 4388 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
c558386b
HW		 4389 ops->write = r8168g_mdio_write;
4390 ops->read = r8168g_mdio_read;
4391 break;
c0e45c1c 4392 default:
4393 ops->write = r8169_mdio_write;
4394 ops->read = r8169_mdio_read;
4395 break;
4396 }
4397}
4398
e2409d83 4399static void rtl_speed_down(struct rtl8169_private *tp)
4400{
4401 u32 adv;
4402 int lpa;
4403
4404 rtl_writephy(tp, 0x1f, 0x0000);
4405 lpa = rtl_readphy(tp, MII_LPA);
4406
4407 if (lpa & (LPA_10HALF | LPA_10FULL))
4408 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4409 else if (lpa & (LPA_100HALF | LPA_100FULL))
4410 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4411 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4412 else
4413 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4414 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4415 (tp->mii.supports_gmii ?
4416 ADVERTISED_1000baseT_Half |
4417 ADVERTISED_1000baseT_Full : 0);
4418
4419 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4420 adv);
4421}
4422
649b3b8c 4423static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4424{
649b3b8c 4425 switch (tp->mac_version) {
b00e69de
CB		 4426 case RTL_GIGA_MAC_VER_25:
4427 case RTL_GIGA_MAC_VER_26:
649b3b8c 4428 case RTL_GIGA_MAC_VER_29:
4429 case RTL_GIGA_MAC_VER_30:
4430 case RTL_GIGA_MAC_VER_32:
4431 case RTL_GIGA_MAC_VER_33:
4432 case RTL_GIGA_MAC_VER_34:
2a71883c 4433 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4434 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
649b3b8c 4435 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4436 break;
4437 default:
4438 break;
4439 }
4440}
4441
4442static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4443{
6fcf9b1d 4444 if (!netif_running(tp->dev) || !__rtl8169_get_wol(tp))
649b3b8c 4445 return false;
4446
e2409d83 4447 rtl_speed_down(tp);
649b3b8c 4448 rtl_wol_suspend_quirk(tp);
4449
4450 return true;
4451}
4452
065c27c1 4453static void r8168_pll_power_down(struct rtl8169_private *tp)
4454{
9dbe7896 4455 if (r8168_check_dash(tp))
065c27c1 4456 return;
4457
01dc7fec 4458 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4459 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4460 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4461
649b3b8c 4462 if (rtl_wol_pll_power_down(tp))
065c27c1 4463 return;
065c27c1 4464
065c27c1 4465 switch (tp->mac_version) {
2a71883c 4466 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4467 case RTL_GIGA_MAC_VER_37:
4468 case RTL_GIGA_MAC_VER_39:
4469 case RTL_GIGA_MAC_VER_43:
42fde737 4470 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4471 case RTL_GIGA_MAC_VER_45:
4472 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4473 case RTL_GIGA_MAC_VER_47:
4474 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4475 case RTL_GIGA_MAC_VER_50:
4476 case RTL_GIGA_MAC_VER_51:
1ef7286e 4477 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
065c27c1 4478 break;
beb330a4 4479 case RTL_GIGA_MAC_VER_40:
4480 case RTL_GIGA_MAC_VER_41:
935e2218 4481 case RTL_GIGA_MAC_VER_49:
706123d0 4482 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 4483 0xfc000000, ERIAR_EXGMAC);
1ef7286e 4484 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
beb330a4 4485 break;
065c27c1 4486 }
4487}
4488
4489static void r8168_pll_power_up(struct rtl8169_private *tp)
4490{
065c27c1 4491 switch (tp->mac_version) {
2a71883c 4492 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4493 case RTL_GIGA_MAC_VER_37:
4494 case RTL_GIGA_MAC_VER_39:
4495 case RTL_GIGA_MAC_VER_43:
1ef7286e 4496 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
065c27c1 4497 break;
42fde737 4498 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4499 case RTL_GIGA_MAC_VER_45:
4500 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4501 case RTL_GIGA_MAC_VER_47:
4502 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4503 case RTL_GIGA_MAC_VER_50:
4504 case RTL_GIGA_MAC_VER_51:
1ef7286e 4505 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
6e1d0b89 4506 break;
beb330a4 4507 case RTL_GIGA_MAC_VER_40:
4508 case RTL_GIGA_MAC_VER_41:
935e2218 4509 case RTL_GIGA_MAC_VER_49:
1ef7286e 4510 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
706123d0 4511 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 4512 0x00000000, ERIAR_EXGMAC);
4513 break;
065c27c1 4514 }
4515
242cd9b5
HK		 4516 phy_resume(tp->dev->phydev);
4517 /* give MAC/PHY some time to resume */
4518 msleep(20);
065c27c1 4519}
4520
065c27c1 4521static void rtl_pll_power_down(struct rtl8169_private *tp)
4522{
4f447d29
HK		 4523 switch (tp->mac_version) {
4524 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4525 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4526 break;
4527 default:
4528 r8168_pll_power_down(tp);
4529 }
065c27c1 4530}
4531
4532static void rtl_pll_power_up(struct rtl8169_private *tp)
4533{
065c27c1 4534 switch (tp->mac_version) {
4f447d29
HK		 4535 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4536 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
065c27c1 4537 break;
065c27c1 4538 default:
4f447d29 4539 r8168_pll_power_up(tp);
065c27c1 4540 }
4541}
4542
e542a226
HW		 4543static void rtl_init_rxcfg(struct rtl8169_private *tp)
4544{
e542a226 4545 switch (tp->mac_version) {
2a71883c
HK		 4546 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4547 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
1ef7286e 4548 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
e542a226 4549 break;
2a71883c 4550 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
eb2dc35d 4551 case RTL_GIGA_MAC_VER_34:
3ced8c95 4552 case RTL_GIGA_MAC_VER_35:
1ef7286e 4553 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
e542a226 4554 break;
2a71883c 4555 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4556 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 4557 break;
e542a226 4558 default:
1ef7286e 4559 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
e542a226
HW		 4560 break;
4561 }
4562}
4563
92fc43b4
HW		 4564static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4565{
9fba0812 4566 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4567}
4568
d58d46b5
FR		 4569static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4570{
eda40b8c
HK		 4571 if (tp->jumbo_ops.enable) {
4572 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4573 tp->jumbo_ops.enable(tp);
4574 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4575 }
d58d46b5
FR		 4576}
4577
4578static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4579{
eda40b8c
HK		 4580 if (tp->jumbo_ops.disable) {
4581 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4582 tp->jumbo_ops.disable(tp);
4583 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4584 }
d58d46b5
FR		 4585}
4586
4587static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4588{
1ef7286e
AS		 4589 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4590 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
cb73200c 4591 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4592}
4593
4594static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4595{
1ef7286e
AS		 4596 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4597 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
8d98aa39 4598 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4599}
4600
4601static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4602{
1ef7286e 4603 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
d58d46b5
FR		 4604}
4605
4606static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4607{
1ef7286e 4608 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
d58d46b5
FR		 4609}
4610
4611static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4612{
1ef7286e
AS		 4613 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4614 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4615 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
cb73200c 4616 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4617}
4618
4619static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4620{
1ef7286e
AS		 4621 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4622 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4623 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
8d98aa39 4624 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4625}
4626
4627static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4628{
cb73200c 4629 rtl_tx_performance_tweak(tp,
f65d539c 4630 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4631}
4632
4633static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4634{
cb73200c 4635 rtl_tx_performance_tweak(tp,
8d98aa39 4636 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4637}
4638
4639static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4640{
d58d46b5
FR		 4641 r8168b_0_hw_jumbo_enable(tp);
4642
1ef7286e 4643 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
d58d46b5
FR		 4644}
4645
4646static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4647{
d58d46b5
FR		 4648 r8168b_0_hw_jumbo_disable(tp);
4649
1ef7286e 4650 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
d58d46b5
FR		 4651}
4652
baf63293 4653static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4654{
4655 struct jumbo_ops *ops = &tp->jumbo_ops;
4656
4657 switch (tp->mac_version) {
4658 case RTL_GIGA_MAC_VER_11:
4659 ops->disable = r8168b_0_hw_jumbo_disable;
4660 ops->enable = r8168b_0_hw_jumbo_enable;
4661 break;
4662 case RTL_GIGA_MAC_VER_12:
4663 case RTL_GIGA_MAC_VER_17:
4664 ops->disable = r8168b_1_hw_jumbo_disable;
4665 ops->enable = r8168b_1_hw_jumbo_enable;
4666 break;
4667 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4668 case RTL_GIGA_MAC_VER_19:
4669 case RTL_GIGA_MAC_VER_20:
4670 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4671 case RTL_GIGA_MAC_VER_22:
4672 case RTL_GIGA_MAC_VER_23:
4673 case RTL_GIGA_MAC_VER_24:
4674 case RTL_GIGA_MAC_VER_25:
4675 case RTL_GIGA_MAC_VER_26:
4676 ops->disable = r8168c_hw_jumbo_disable;
4677 ops->enable = r8168c_hw_jumbo_enable;
4678 break;
4679 case RTL_GIGA_MAC_VER_27:
4680 case RTL_GIGA_MAC_VER_28:
4681 ops->disable = r8168dp_hw_jumbo_disable;
4682 ops->enable = r8168dp_hw_jumbo_enable;
4683 break;
4684 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4685 case RTL_GIGA_MAC_VER_32:
4686 case RTL_GIGA_MAC_VER_33:
4687 case RTL_GIGA_MAC_VER_34:
4688 ops->disable = r8168e_hw_jumbo_disable;
4689 ops->enable = r8168e_hw_jumbo_enable;
4690 break;
4691
4692 /*
4693 * No action needed for jumbo frames with 8169.
4694 * No jumbo for 810x at all.
4695 */
2a71883c 4696 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 4697 default:
4698 ops->disable = NULL;
4699 ops->enable = NULL;
4700 break;
4701 }
4702}
4703
ffc46952
FR		 4704DECLARE_RTL_COND(rtl_chipcmd_cond)
4705{
1ef7286e 4706 return RTL_R8(tp, ChipCmd) & CmdReset;
ffc46952
FR		 4707}
4708
6f43adc8
FR		 4709static void rtl_hw_reset(struct rtl8169_private *tp)
4710{
1ef7286e 4711 RTL_W8(tp, ChipCmd, CmdReset);
6f43adc8 4712
ffc46952 4713 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4714}
4715
b6ffd97f 4716static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4717{
b6ffd97f
FR		 4718 struct rtl_fw *rtl_fw;
4719 const char *name;
4720 int rc = -ENOMEM;
953a12cc 4721
b6ffd97f
FR		 4722 name = rtl_lookup_firmware_name(tp);
4723 if (!name)
4724 goto out_no_firmware;
953a12cc 4725
b6ffd97f
FR		 4726 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4727 if (!rtl_fw)
4728 goto err_warn;
31bd204f 4729
1e1205b7 4730 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
b6ffd97f
FR		 4731 if (rc < 0)
4732 goto err_free;
4733
fd112f2e
FR		 4734 rc = rtl_check_firmware(tp, rtl_fw);
4735 if (rc < 0)
4736 goto err_release_firmware;
4737
b6ffd97f
FR		 4738 tp->rtl_fw = rtl_fw;
4739out:
4740 return;
4741
fd112f2e
FR		 4742err_release_firmware:
4743 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4744err_free:
4745 kfree(rtl_fw);
4746err_warn:
4747 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4748 name, rc);
4749out_no_firmware:
4750 tp->rtl_fw = NULL;
4751 goto out;
4752}
4753
4754static void rtl_request_firmware(struct rtl8169_private *tp)
4755{
4756 if (IS_ERR(tp->rtl_fw))
4757 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4758}
4759
92fc43b4
HW		 4760static void rtl_rx_close(struct rtl8169_private *tp)
4761{
1ef7286e 4762 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4763}
4764
ffc46952
FR		 4765DECLARE_RTL_COND(rtl_npq_cond)
4766{
1ef7286e 4767 return RTL_R8(tp, TxPoll) & NPQ;
ffc46952
FR		 4768}
4769
4770DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4771{
1ef7286e 4772 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
ffc46952
FR		 4773}
4774
e6de30d6 4775static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4
LT		 4776{
4777 /* Disable interrupts */
811fd301 4778 rtl8169_irq_mask_and_ack(tp);
1da177e4 4779
92fc43b4
HW		 4780 rtl_rx_close(tp);
4781
b2d43e6e
HK		 4782 switch (tp->mac_version) {
4783 case RTL_GIGA_MAC_VER_27:
4784 case RTL_GIGA_MAC_VER_28:
4785 case RTL_GIGA_MAC_VER_31:
ffc46952 4786 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
b2d43e6e
HK		 4787 break;
4788 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4789 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4790 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
ffc46952 4791 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
b2d43e6e
HK		 4792 break;
4793 default:
1ef7286e 4794 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
92fc43b4 4795 udelay(100);
b2d43e6e 4796 break;
e6de30d6 4797 }
4798
92fc43b4 4799 rtl_hw_reset(tp);
1da177e4
LT		 4800}
4801
7f796d83 4802static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6 4803{
9cb427b6 4804 /* Set DMA burst size and Interframe Gap Time */
1ef7286e 4805 RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
9cb427b6
FR		 4806 (InterFrameGap << TxInterFrameGapShift));
4807}
4808
4fd48c4a 4809static void rtl_set_rx_max_size(struct rtl8169_private *tp)
1da177e4 4810{
4fd48c4a
HK		 4811 /* Low hurts. Let's disable the filtering. */
4812 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
07ce4064
FR		 4813}
4814
1ef7286e 4815static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
7f796d83
FR		 4816{
4817 /*
4818 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4819 * register to be written before TxDescAddrLow to work.
4820 * Switching from MMIO to I/O access fixes the issue as well.
4821 */
1ef7286e
AS		 4822 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4823 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4824 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4825 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4826}
4827
1ef7286e 4828static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
6dccd16b 4829{
3744100e 4830 static const struct rtl_cfg2_info {
6dccd16b
FR		 4831 u32 mac_version;
4832 u32 clk;
4833 u32 val;
4834 } cfg2_info [] = {
4835 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4836 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4837 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4838 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4839 };
4840 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4841 unsigned int i;
4842 u32 clk;
4843
1ef7286e 4844 clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
cadf1855 4845 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b 4846 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1ef7286e 4847 RTL_W32(tp, 0x7c, p->val);
6dccd16b
FR		 4848 break;
4849 }
4850 }
4851}
4852
e6b763ea
FR		 4853static void rtl_set_rx_mode(struct net_device *dev)
4854{
4855 struct rtl8169_private *tp = netdev_priv(dev);
e6b763ea
FR		 4856 u32 mc_filter[2]; /* Multicast hash filter */
4857 int rx_mode;
4858 u32 tmp = 0;
4859
4860 if (dev->flags & IFF_PROMISC) {
4861 /* Unconditionally log net taps. */
4862 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4863 rx_mode =
4864 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4865 AcceptAllPhys;
4866 mc_filter[1] = mc_filter[0] = 0xffffffff;
4867 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4868 (dev->flags & IFF_ALLMULTI)) {
4869 /* Too many to filter perfectly -- accept all multicasts. */
4870 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4871 mc_filter[1] = mc_filter[0] = 0xffffffff;
4872 } else {
4873 struct netdev_hw_addr *ha;
4874
4875 rx_mode = AcceptBroadcast | AcceptMyPhys;
4876 mc_filter[1] = mc_filter[0] = 0;
4877 netdev_for_each_mc_addr(ha, dev) {
4878 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4879 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4880 rx_mode |= AcceptMulticast;
4881 }
4882 }
4883
4884 if (dev->features & NETIF_F_RXALL)
4885 rx_mode |= (AcceptErr | AcceptRunt);
4886
1ef7286e 4887 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
e6b763ea
FR		 4888
4889 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4890 u32 data = mc_filter[0];
4891
4892 mc_filter[0] = swab32(mc_filter[1]);
4893 mc_filter[1] = swab32(data);
4894 }
4895
0481776b
NW		 4896 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4897 mc_filter[1] = mc_filter[0] = 0xffffffff;
4898
1ef7286e
AS		 4899 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4900 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
e6b763ea 4901
1ef7286e 4902 RTL_W32(tp, RxConfig, tmp);
e6b763ea
FR		 4903}
4904
52f8560e
HK		 4905static void rtl_hw_start(struct rtl8169_private *tp)
4906{
4907 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4908
4909 tp->hw_start(tp);
4910
4911 rtl_set_rx_max_size(tp);
4912 rtl_set_rx_tx_desc_registers(tp);
4913 rtl_set_rx_tx_config_registers(tp);
4914 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4915
4916 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4917 RTL_R8(tp, IntrMask);
4918 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4919 rtl_set_rx_mode(tp->dev);
4920 /* no early-rx interrupts */
4921 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4922 rtl_irq_enable_all(tp);
4923}
4924
61cb532d 4925static void rtl_hw_start_8169(struct rtl8169_private *tp)
07ce4064 4926{
0ae0974e 4927 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
61cb532d 4928 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
9cb427b6 4929
1ef7286e 4930 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
1da177e4 4931
0ae0974e 4932 tp->cp_cmd |= PCIMulRW;
1da177e4 4933
cecb5fd7
FR		 4934 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4935 tp->mac_version == RTL_GIGA_MAC_VER_03) {
49d17512
HK		 4936 netif_dbg(tp, drv, tp->dev,
4937 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
bcf0bf90 4938 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4939 }
4940
1ef7286e 4941 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
bcf0bf90 4942
1ef7286e 4943 rtl8169_set_magic_reg(tp, tp->mac_version);
6dccd16b 4944
1da177e4
LT		 4945 /*
4946 * Undocumented corner. Supposedly:
4947 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4948 */
1ef7286e 4949 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4 4950
1ef7286e 4951 RTL_W32(tp, RxMissed, 0);
07ce4064 4952}
1da177e4 4953
ffc46952
FR		 4954DECLARE_RTL_COND(rtl_csiar_cond)
4955{
1ef7286e 4956 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
ffc46952
FR		 4957}
4958
ff1d7331 4959static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
beb1fe18 4960{
ff1d7331 4961 u32 func = PCI_FUNC(tp->pci_dev->devfn);
beb1fe18 4962
1ef7286e
AS		 4963 RTL_W32(tp, CSIDR, value);
4964 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
ff1d7331 4965 CSIAR_BYTE_ENABLE | func << 16);
7e18dca1 4966
ffc46952 4967 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4968}
4969
ff1d7331 4970static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4971{
ff1d7331
HK		 4972 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4973
4974 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4975 CSIAR_BYTE_ENABLE);
7e18dca1 4976
ffc46952 4977 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 4978 RTL_R32(tp, CSIDR) : ~0;
7e18dca1
HW		 4979}
4980
ff1d7331 4981static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
45dd95c4 4982{
ff1d7331
HK		 4983 struct pci_dev *pdev = tp->pci_dev;
4984 u32 csi;
45dd95c4 4985
ff1d7331
HK		 4986 /* According to Realtek the value at config space address 0x070f
4987 * controls the L0s/L1 entrance latency. We try standard ECAM access
4988 * first and if it fails fall back to CSI.
4989 */
4990 if (pdev->cfg_size > 0x070f &&
4991 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4992 return;
4993
4994 netdev_notice_once(tp->dev,
4995 "No native access to PCI extended config space, falling back to CSI\n");
4996 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4997 rtl_csi_write(tp, 0x070c, csi | val << 24);
45dd95c4 4998}
4999
f37658da 5000static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
beb1fe18 5001{
ff1d7331 5002 rtl_csi_access_enable(tp, 0x27);
dacf8154
FR		 5003}
5004
5005struct ephy_info {
5006 unsigned int offset;
5007 u16 mask;
5008 u16 bits;
5009};
5010
fdf6fc06
FR		 5011static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5012 int len)
dacf8154
FR		 5013{
5014 u16 w;
5015
5016 while (len-- > 0) {
fdf6fc06
FR		 5017 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5018 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 5019 e++;
5020 }
5021}
5022
73c86ee3 5023static void rtl_disable_clock_request(struct rtl8169_private *tp)
b726e493 5024{
73c86ee3 5025 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 5026 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 5027}
5028
73c86ee3 5029static void rtl_enable_clock_request(struct rtl8169_private *tp)
e6de30d6 5030{
73c86ee3 5031 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 5032 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 5033}
5034
b51ecea8 5035static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5036{
b51ecea8 5037 u8 data;
5038
1ef7286e 5039 data = RTL_R8(tp, Config3);
b51ecea8 5040
5041 if (enable)
5042 data |= Rdy_to_L23;
5043 else
5044 data &= ~Rdy_to_L23;
5045
1ef7286e 5046 RTL_W8(tp, Config3, data);
b51ecea8 5047}
5048
a99790bf
KHF		 5049static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
5050{
5051 if (enable) {
5052 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
5053 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
5054 } else {
5055 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5056 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5057 }
5058}
5059
beb1fe18 5060static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 5061{
1ef7286e 5062 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 5063
12d42c50 5064 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 5065 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
b726e493 5066
faf1e785 5067 if (tp->dev->mtu <= ETH_DATA_LEN) {
8d98aa39 5068 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
faf1e785 5069 PCI_EXP_DEVCTL_NOSNOOP_EN);
5070 }
219a1e9d
FR		 5071}
5072
beb1fe18 5073static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 5074{
beb1fe18 5075 rtl_hw_start_8168bb(tp);
b726e493 5076
1ef7286e 5077 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
b726e493 5078
1ef7286e 5079 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
219a1e9d
FR		 5080}
5081
beb1fe18 5082static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 5083{
1ef7286e 5084 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
b726e493 5085
1ef7286e 5086 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 5087
faf1e785 5088 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5089 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
b726e493 5090
73c86ee3 5091 rtl_disable_clock_request(tp);
b726e493 5092
12d42c50 5093 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 5094 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
219a1e9d
FR		 5095}
5096
beb1fe18 5097static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 5098{
350f7596 5099 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 5100 { 0x01, 0, 0x0001 },
5101 { 0x02, 0x0800, 0x1000 },
5102 { 0x03, 0, 0x0042 },
5103 { 0x06, 0x0080, 0x0000 },
5104 { 0x07, 0, 0x2000 }
5105 };
5106
f37658da 5107 rtl_set_def_aspm_entry_latency(tp);
b726e493 5108
fdf6fc06 5109 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 5110
beb1fe18 5111 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5112}
5113
beb1fe18 5114static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 5115{
f37658da 5116 rtl_set_def_aspm_entry_latency(tp);
ef3386f0 5117
1ef7286e 5118 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
ef3386f0 5119
faf1e785 5120 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5121 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
ef3386f0 5122
12d42c50 5123 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 5124 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
ef3386f0
FR		 5125}
5126
beb1fe18 5127static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 5128{
f37658da 5129 rtl_set_def_aspm_entry_latency(tp);
7f3e3d3a 5130
1ef7286e 5131 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
7f3e3d3a
FR		 5132
5133 /* Magic. */
1ef7286e 5134 RTL_W8(tp, DBG_REG, 0x20);
7f3e3d3a 5135
1ef7286e 5136 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
7f3e3d3a 5137
faf1e785 5138 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5139 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7f3e3d3a 5140
12d42c50 5141 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 5142 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
7f3e3d3a
FR		 5143}
5144
beb1fe18 5145static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 5146{
350f7596 5147 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 5148 { 0x02, 0x0800, 0x1000 },
5149 { 0x03, 0, 0x0002 },
5150 { 0x06, 0x0080, 0x0000 }
5151 };
5152
f37658da 5153 rtl_set_def_aspm_entry_latency(tp);
b726e493 5154
1ef7286e 5155 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
b726e493 5156
fdf6fc06 5157 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 5158
beb1fe18 5159 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5160}
5161
beb1fe18 5162static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 5163{
350f7596 5164 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 5165 { 0x01, 0, 0x0001 },
5166 { 0x03, 0x0400, 0x0220 }
5167 };
5168
f37658da 5169 rtl_set_def_aspm_entry_latency(tp);
b726e493 5170
fdf6fc06 5171 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 5172
beb1fe18 5173 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5174}
5175
beb1fe18 5176static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 5177{
beb1fe18 5178 rtl_hw_start_8168c_2(tp);
197ff761
FR		 5179}
5180
beb1fe18 5181static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 5182{
f37658da 5183 rtl_set_def_aspm_entry_latency(tp);
6fb07058 5184
beb1fe18 5185 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 5186}
5187
beb1fe18 5188static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 5189{
f37658da 5190 rtl_set_def_aspm_entry_latency(tp);
5b538df9 5191
73c86ee3 5192 rtl_disable_clock_request(tp);
5b538df9 5193
1ef7286e 5194 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5b538df9 5195
faf1e785 5196 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5197 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5b538df9 5198
12d42c50 5199 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 5200 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5b538df9
FR		 5201}
5202
beb1fe18 5203static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 5204{
f37658da 5205 rtl_set_def_aspm_entry_latency(tp);
4804b3b3 5206
faf1e785 5207 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5208 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4804b3b3 5209
1ef7286e 5210 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4804b3b3 5211
73c86ee3 5212 rtl_disable_clock_request(tp);
4804b3b3 5213}
5214
beb1fe18 5215static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 5216{
5217 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 5218 { 0x0b, 0x0000, 0x0048 },
5219 { 0x19, 0x0020, 0x0050 },
5220 { 0x0c, 0x0100, 0x0020 }
e6de30d6 5221 };
e6de30d6 5222
f37658da 5223 rtl_set_def_aspm_entry_latency(tp);
e6de30d6 5224
8d98aa39 5225 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
e6de30d6 5226
1ef7286e 5227 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
e6de30d6 5228
1016a4a1 5229 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
e6de30d6 5230
73c86ee3 5231 rtl_enable_clock_request(tp);
e6de30d6 5232}
5233
beb1fe18 5234static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 5235{
70090424 5236 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5237 { 0x00, 0x0200, 0x0100 },
5238 { 0x00, 0x0000, 0x0004 },
5239 { 0x06, 0x0002, 0x0001 },
5240 { 0x06, 0x0000, 0x0030 },
5241 { 0x07, 0x0000, 0x2000 },
5242 { 0x00, 0x0000, 0x0020 },
5243 { 0x03, 0x5800, 0x2000 },
5244 { 0x03, 0x0000, 0x0001 },
5245 { 0x01, 0x0800, 0x1000 },
5246 { 0x07, 0x0000, 0x4000 },
5247 { 0x1e, 0x0000, 0x2000 },
5248 { 0x19, 0xffff, 0xfe6c },
5249 { 0x0a, 0x0000, 0x0040 }
5250 };
5251
f37658da 5252 rtl_set_def_aspm_entry_latency(tp);
01dc7fec 5253
fdf6fc06 5254 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5255
faf1e785 5256 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5257 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
01dc7fec 5258
1ef7286e 5259 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
01dc7fec 5260
73c86ee3 5261 rtl_disable_clock_request(tp);
01dc7fec 5262
5263 /* Reset tx FIFO pointer */
1ef7286e
AS		 5264 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5265 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
01dc7fec 5266
1ef7286e 5267 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
01dc7fec 5268}
5269
beb1fe18 5270static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424
HW		 5271{
5272 static const struct ephy_info e_info_8168e_2[] = {
5273 { 0x09, 0x0000, 0x0080 },
5274 { 0x19, 0x0000, 0x0224 }
5275 };
5276
f37658da 5277 rtl_set_def_aspm_entry_latency(tp);
70090424 5278
fdf6fc06 5279 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5280
faf1e785 5281 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5282 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
70090424 5283
fdf6fc06
FR		 5284 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5285 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5286 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5287 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5288 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5289 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 5290 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5291 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5292
1ef7286e 5293 RTL_W8(tp, MaxTxPacketSize, EarlySize);
70090424 5294
73c86ee3 5295 rtl_disable_clock_request(tp);
4521e1a9 5296
1ef7286e
AS		 5297 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5298 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
70090424
HW		 5299
5300 /* Adjust EEE LED frequency */
1ef7286e 5301 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
70090424 5302
1ef7286e
AS		 5303 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5304 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5305 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
aa1e7d2c
HK		 5306
5307 rtl_hw_aspm_clkreq_enable(tp, true);
70090424
HW		 5308}
5309
5f886e08 5310static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5311{
f37658da 5312 rtl_set_def_aspm_entry_latency(tp);
c2218925 5313
8d98aa39 5314 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c2218925 5315
fdf6fc06
FR		 5316 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5317 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5318 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5319 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 5320 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5321 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5322 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5323 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5324 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5325 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925 5326
1ef7286e 5327 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c2218925 5328
73c86ee3 5329 rtl_disable_clock_request(tp);
4521e1a9 5330
1ef7286e
AS		 5331 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5332 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5333 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5334 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5335 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
c2218925
HW		 5336}
5337
5f886e08
HW		 5338static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5339{
5f886e08
HW		 5340 static const struct ephy_info e_info_8168f_1[] = {
5341 { 0x06, 0x00c0, 0x0020 },
5342 { 0x08, 0x0001, 0x0002 },
5343 { 0x09, 0x0000, 0x0080 },
5344 { 0x19, 0x0000, 0x0224 }
5345 };
5346
5347 rtl_hw_start_8168f(tp);
5348
fdf6fc06 5349 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5350
706123d0 5351 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5352
5353 /* Adjust EEE LED frequency */
1ef7286e 5354 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5f886e08
HW		 5355}
5356
b3d7b2f2
HW		 5357static void rtl_hw_start_8411(struct rtl8169_private *tp)
5358{
b3d7b2f2
HW		 5359 static const struct ephy_info e_info_8168f_1[] = {
5360 { 0x06, 0x00c0, 0x0020 },
5361 { 0x0f, 0xffff, 0x5200 },
5362 { 0x1e, 0x0000, 0x4000 },
5363 { 0x19, 0x0000, 0x0224 }
5364 };
5365
5366 rtl_hw_start_8168f(tp);
b51ecea8 5367 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 5368
fdf6fc06 5369 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5370
706123d0 5371 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5372}
5373
5fbea337 5374static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b 5375{
1ef7286e 5376 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
beb330a4 5377
c558386b
HW		 5378 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5379 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5380 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5381 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5382
f37658da 5383 rtl_set_def_aspm_entry_latency(tp);
c558386b 5384
8d98aa39 5385 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c558386b 5386
706123d0
CHL		 5387 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5388 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5389 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 5390
1ef7286e
AS		 5391 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5392 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c558386b
HW		 5393
5394 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5395 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5396
5397 /* Adjust EEE LED frequency */
1ef7286e 5398 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
c558386b 5399
706123d0
CHL		 5400 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5401 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 5402
5403 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 5404}
5405
5fbea337
CHL		 5406static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5407{
5fbea337
CHL		 5408 static const struct ephy_info e_info_8168g_1[] = {
5409 { 0x00, 0x0000, 0x0008 },
5410 { 0x0c, 0x37d0, 0x0820 },
5411 { 0x1e, 0x0000, 0x0001 },
5412 { 0x19, 0x8000, 0x0000 }
5413 };
5414
5415 rtl_hw_start_8168g(tp);
5416
5417 /* disable aspm and clock request before access ephy */
a99790bf 5418 rtl_hw_aspm_clkreq_enable(tp, false);
5fbea337 5419 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
a99790bf 5420 rtl_hw_aspm_clkreq_enable(tp, true);
5fbea337
CHL		 5421}
5422
57538c4a 5423static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5424{
57538c4a 5425 static const struct ephy_info e_info_8168g_2[] = {
5426 { 0x00, 0x0000, 0x0008 },
5427 { 0x0c, 0x3df0, 0x0200 },
5428 { 0x19, 0xffff, 0xfc00 },
5429 { 0x1e, 0xffff, 0x20eb }
5430 };
5431
5fbea337 5432 rtl_hw_start_8168g(tp);
57538c4a 5433
5434 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 5435 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5436 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
57538c4a 5437 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5438}
5439
45dd95c4 5440static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5441{
45dd95c4 5442 static const struct ephy_info e_info_8411_2[] = {
5443 { 0x00, 0x0000, 0x0008 },
5444 { 0x0c, 0x3df0, 0x0200 },
5445 { 0x0f, 0xffff, 0x5200 },
5446 { 0x19, 0x0020, 0x0000 },
5447 { 0x1e, 0x0000, 0x2000 }
5448 };
5449
5fbea337 5450 rtl_hw_start_8168g(tp);
45dd95c4 5451
5452 /* disable aspm and clock request before access ephy */
a99790bf 5453 rtl_hw_aspm_clkreq_enable(tp, false);
45dd95c4 5454 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
a99790bf 5455 rtl_hw_aspm_clkreq_enable(tp, true);
45dd95c4 5456}
5457
6e1d0b89
CHL		 5458static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5459{
72521ea0 5460 int rg_saw_cnt;
6e1d0b89
CHL		 5461 u32 data;
5462 static const struct ephy_info e_info_8168h_1[] = {
5463 { 0x1e, 0x0800, 0x0001 },
5464 { 0x1d, 0x0000, 0x0800 },
5465 { 0x05, 0xffff, 0x2089 },
5466 { 0x06, 0xffff, 0x5881 },
5467 { 0x04, 0xffff, 0x154a },
5468 { 0x01, 0xffff, 0x068b }
5469 };
5470
5471 /* disable aspm and clock request before access ephy */
a99790bf 5472 rtl_hw_aspm_clkreq_enable(tp, false);
6e1d0b89
CHL		 5473 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5474
1ef7286e 5475 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6e1d0b89
CHL		 5476
5477 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5478 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5479 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5480 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5481
f37658da 5482 rtl_set_def_aspm_entry_latency(tp);
6e1d0b89 5483
8d98aa39 5484 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6e1d0b89 5485
706123d0
CHL		 5486 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5487 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 5488
706123d0 5489 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 5490
706123d0 5491 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 5492
5493 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5494
1ef7286e
AS		 5495 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5496 RTL_W8(tp, MaxTxPacketSize, EarlySize);
6e1d0b89
CHL		 5497
5498 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5499 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5500
5501 /* Adjust EEE LED frequency */
1ef7286e 5502 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6e1d0b89 5503
1ef7286e
AS		 5504 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5505 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89 5506
1ef7286e 5507 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6e1d0b89 5508
706123d0 5509 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 5510
5511 rtl_pcie_state_l2l3_enable(tp, false);
5512
5513 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 5514 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 5515 rtl_writephy(tp, 0x1f, 0x0000);
5516 if (rg_saw_cnt > 0) {
5517 u16 sw_cnt_1ms_ini;
5518
5519 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5520 sw_cnt_1ms_ini &= 0x0fff;
5521 data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec0 5522 data &= ~0x0fff;
6e1d0b89
CHL		 5523 data |= sw_cnt_1ms_ini;
5524 r8168_mac_ocp_write(tp, 0xd412, data);
5525 }
5526
5527 data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec0
CHL		 5528 data &= ~0xf0;
5529 data |= 0x70;
6e1d0b89
CHL		 5530 r8168_mac_ocp_write(tp, 0xe056, data);
5531
5532 data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec0
CHL		 5533 data &= ~0x6000;
5534 data |= 0x8008;
6e1d0b89
CHL		 5535 r8168_mac_ocp_write(tp, 0xe052, data);
5536
5537 data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec0 5538 data &= ~0x01ff;
6e1d0b89
CHL		 5539 data |= 0x017f;
5540 r8168_mac_ocp_write(tp, 0xe0d6, data);
5541
5542 data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec0 5543 data &= ~0x0fff;
6e1d0b89
CHL		 5544 data |= 0x047f;
5545 r8168_mac_ocp_write(tp, 0xd420, data);
5546
5547 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5548 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5549 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5550 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
a99790bf
KHF		 5551
5552 rtl_hw_aspm_clkreq_enable(tp, true);
6e1d0b89
CHL		 5553}
5554
935e2218
CHL		 5555static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5556{
003609da
CHL		 5557 rtl8168ep_stop_cmac(tp);
5558
1ef7286e 5559 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
935e2218
CHL		 5560
5561 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5562 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5563 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5564 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5565
f37658da 5566 rtl_set_def_aspm_entry_latency(tp);
935e2218 5567
8d98aa39 5568 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
935e2218
CHL		 5569
5570 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5571 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5572
5573 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5574
5575 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5576
1ef7286e
AS		 5577 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5578 RTL_W8(tp, MaxTxPacketSize, EarlySize);
935e2218
CHL		 5579
5580 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5581 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5582
5583 /* Adjust EEE LED frequency */
1ef7286e 5584 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
935e2218
CHL		 5585
5586 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5587
1ef7286e 5588 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
935e2218
CHL		 5589
5590 rtl_pcie_state_l2l3_enable(tp, false);
5591}
5592
5593static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5594{
935e2218
CHL		 5595 static const struct ephy_info e_info_8168ep_1[] = {
5596 { 0x00, 0xffff, 0x10ab },
5597 { 0x06, 0xffff, 0xf030 },
5598 { 0x08, 0xffff, 0x2006 },
5599 { 0x0d, 0xffff, 0x1666 },
5600 { 0x0c, 0x3ff0, 0x0000 }
5601 };
5602
5603 /* disable aspm and clock request before access ephy */
a99790bf 5604 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5605 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5606
5607 rtl_hw_start_8168ep(tp);
a99790bf
KHF		 5608
5609 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5610}
5611
5612static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5613{
935e2218
CHL		 5614 static const struct ephy_info e_info_8168ep_2[] = {
5615 { 0x00, 0xffff, 0x10a3 },
5616 { 0x19, 0xffff, 0xfc00 },
5617 { 0x1e, 0xffff, 0x20ea }
5618 };
5619
5620 /* disable aspm and clock request before access ephy */
a99790bf 5621 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5622 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5623
5624 rtl_hw_start_8168ep(tp);
5625
1ef7286e
AS		 5626 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5627 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
a99790bf
KHF		 5628
5629 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5630}
5631
5632static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5633{
935e2218
CHL		 5634 u32 data;
5635 static const struct ephy_info e_info_8168ep_3[] = {
5636 { 0x00, 0xffff, 0x10a3 },
5637 { 0x19, 0xffff, 0x7c00 },
5638 { 0x1e, 0xffff, 0x20eb },
5639 { 0x0d, 0xffff, 0x1666 }
5640 };
5641
5642 /* disable aspm and clock request before access ephy */
a99790bf 5643 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5644 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5645
5646 rtl_hw_start_8168ep(tp);
5647
1ef7286e
AS		 5648 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5649 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 5650
5651 data = r8168_mac_ocp_read(tp, 0xd3e2);
5652 data &= 0xf000;
5653 data |= 0x0271;
5654 r8168_mac_ocp_write(tp, 0xd3e2, data);
5655
5656 data = r8168_mac_ocp_read(tp, 0xd3e4);
5657 data &= 0xff00;
5658 r8168_mac_ocp_write(tp, 0xd3e4, data);
5659
5660 data = r8168_mac_ocp_read(tp, 0xe860);
5661 data |= 0x0080;
5662 r8168_mac_ocp_write(tp, 0xe860, data);
a99790bf
KHF		 5663
5664 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5665}
5666
61cb532d 5667static void rtl_hw_start_8168(struct rtl8169_private *tp)
07ce4064 5668{
1ef7286e 5669 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
2dd99530 5670
0ae0974e
HK		 5671 tp->cp_cmd &= ~INTT_MASK;
5672 tp->cp_cmd |= PktCntrDisable | INTT_1;
1ef7286e 5673 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2dd99530 5674
1ef7286e 5675 RTL_W16(tp, IntrMitigate, 0x5151);
2dd99530 5676
0e485150 5677 /* Work around for RxFIFO overflow. */
811fd301 5678 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5679 tp->event_slow |= RxFIFOOver | PCSTimeout;
5680 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5681 }
5682
219a1e9d
FR		 5683 switch (tp->mac_version) {
5684 case RTL_GIGA_MAC_VER_11:
beb1fe18 5685 rtl_hw_start_8168bb(tp);
4804b3b3 5686 break;
219a1e9d
FR		 5687
5688 case RTL_GIGA_MAC_VER_12:
5689 case RTL_GIGA_MAC_VER_17:
beb1fe18 5690 rtl_hw_start_8168bef(tp);
4804b3b3 5691 break;
219a1e9d
FR		 5692
5693 case RTL_GIGA_MAC_VER_18:
beb1fe18 5694 rtl_hw_start_8168cp_1(tp);
4804b3b3 5695 break;
219a1e9d
FR		 5696
5697 case RTL_GIGA_MAC_VER_19:
beb1fe18 5698 rtl_hw_start_8168c_1(tp);
4804b3b3 5699 break;
219a1e9d
FR		 5700
5701 case RTL_GIGA_MAC_VER_20:
beb1fe18 5702 rtl_hw_start_8168c_2(tp);
4804b3b3 5703 break;
219a1e9d 5704
197ff761 5705 case RTL_GIGA_MAC_VER_21:
beb1fe18 5706 rtl_hw_start_8168c_3(tp);
4804b3b3 5707 break;
197ff761 5708
6fb07058 5709 case RTL_GIGA_MAC_VER_22:
beb1fe18 5710 rtl_hw_start_8168c_4(tp);
4804b3b3 5711 break;
6fb07058 5712
ef3386f0 5713 case RTL_GIGA_MAC_VER_23:
beb1fe18 5714 rtl_hw_start_8168cp_2(tp);
4804b3b3 5715 break;
ef3386f0 5716
7f3e3d3a 5717 case RTL_GIGA_MAC_VER_24:
beb1fe18 5718 rtl_hw_start_8168cp_3(tp);
4804b3b3 5719 break;
7f3e3d3a 5720
5b538df9 5721 case RTL_GIGA_MAC_VER_25:
daf9df6d 5722 case RTL_GIGA_MAC_VER_26:
5723 case RTL_GIGA_MAC_VER_27:
beb1fe18 5724 rtl_hw_start_8168d(tp);
4804b3b3 5725 break;
5b538df9 5726
e6de30d6 5727 case RTL_GIGA_MAC_VER_28:
beb1fe18 5728 rtl_hw_start_8168d_4(tp);
4804b3b3 5729 break;
cecb5fd7 5730
4804b3b3 5731 case RTL_GIGA_MAC_VER_31:
beb1fe18 5732 rtl_hw_start_8168dp(tp);
4804b3b3 5733 break;
5734
01dc7fec 5735 case RTL_GIGA_MAC_VER_32:
5736 case RTL_GIGA_MAC_VER_33:
beb1fe18 5737 rtl_hw_start_8168e_1(tp);
70090424
HW		 5738 break;
5739 case RTL_GIGA_MAC_VER_34:
beb1fe18 5740 rtl_hw_start_8168e_2(tp);
01dc7fec 5741 break;
e6de30d6 5742
c2218925
HW		 5743 case RTL_GIGA_MAC_VER_35:
5744 case RTL_GIGA_MAC_VER_36:
beb1fe18 5745 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5746 break;
5747
b3d7b2f2
HW		 5748 case RTL_GIGA_MAC_VER_38:
5749 rtl_hw_start_8411(tp);
5750 break;
5751
c558386b
HW		 5752 case RTL_GIGA_MAC_VER_40:
5753 case RTL_GIGA_MAC_VER_41:
5754 rtl_hw_start_8168g_1(tp);
5755 break;
57538c4a 5756 case RTL_GIGA_MAC_VER_42:
5757 rtl_hw_start_8168g_2(tp);
5758 break;
c558386b 5759
45dd95c4 5760 case RTL_GIGA_MAC_VER_44:
5761 rtl_hw_start_8411_2(tp);
5762 break;
5763
6e1d0b89
CHL		 5764 case RTL_GIGA_MAC_VER_45:
5765 case RTL_GIGA_MAC_VER_46:
5766 rtl_hw_start_8168h_1(tp);
5767 break;
5768
935e2218
CHL		 5769 case RTL_GIGA_MAC_VER_49:
5770 rtl_hw_start_8168ep_1(tp);
5771 break;
5772
5773 case RTL_GIGA_MAC_VER_50:
5774 rtl_hw_start_8168ep_2(tp);
5775 break;
5776
5777 case RTL_GIGA_MAC_VER_51:
5778 rtl_hw_start_8168ep_3(tp);
5779 break;
5780
219a1e9d 5781 default:
49d17512
HK		 5782 netif_err(tp, drv, tp->dev,
5783 "unknown chipset (mac_version = %d)\n",
5784 tp->mac_version);
4804b3b3 5785 break;
219a1e9d 5786 }
07ce4064 5787}
1da177e4 5788
beb1fe18 5789static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5790{
350f7596 5791 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5792 { 0x01, 0, 0x6e65 },
5793 { 0x02, 0, 0x091f },
5794 { 0x03, 0, 0xc2f9 },
5795 { 0x06, 0, 0xafb5 },
5796 { 0x07, 0, 0x0e00 },
5797 { 0x19, 0, 0xec80 },
5798 { 0x01, 0, 0x2e65 },
5799 { 0x01, 0, 0x6e65 }
5800 };
5801 u8 cfg1;
5802
f37658da 5803 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5804
1ef7286e 5805 RTL_W8(tp, DBG_REG, FIX_NAK_1);
2857ffb7 5806
8d98aa39 5807 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 5808
1ef7286e 5809 RTL_W8(tp, Config1,
2857ffb7 5810 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
1ef7286e 5811 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7 5812
1ef7286e 5813 cfg1 = RTL_R8(tp, Config1);
2857ffb7 5814 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
1ef7286e 5815 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
2857ffb7 5816
fdf6fc06 5817 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5818}
5819
beb1fe18 5820static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5821{
f37658da 5822 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5823
8d98aa39 5824 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 5825
1ef7286e
AS		 5826 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5827 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7
FR		 5828}
5829
beb1fe18 5830static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5831{
beb1fe18 5832 rtl_hw_start_8102e_2(tp);
2857ffb7 5833
fdf6fc06 5834 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5835}
5836
beb1fe18 5837static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443
HW		 5838{
5839 static const struct ephy_info e_info_8105e_1[] = {
5840 { 0x07, 0, 0x4000 },
5841 { 0x19, 0, 0x0200 },
5842 { 0x19, 0, 0x0020 },
5843 { 0x1e, 0, 0x2000 },
5844 { 0x03, 0, 0x0001 },
5845 { 0x19, 0, 0x0100 },
5846 { 0x19, 0, 0x0004 },
5847 { 0x0a, 0, 0x0020 }
5848 };
5849
cecb5fd7 5850 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5851 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5a5e4443 5852
cecb5fd7 5853 /* Disable Early Tally Counter */
1ef7286e 5854 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5a5e4443 5855
1ef7286e
AS		 5856 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5857 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5a5e4443 5858
fdf6fc06 5859 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 5860
5861 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 5862}
5863
beb1fe18 5864static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5865{
beb1fe18 5866 rtl_hw_start_8105e_1(tp);
fdf6fc06 5867 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5868}
5869
7e18dca1
HW		 5870static void rtl_hw_start_8402(struct rtl8169_private *tp)
5871{
7e18dca1
HW		 5872 static const struct ephy_info e_info_8402[] = {
5873 { 0x19, 0xffff, 0xff64 },
5874 { 0x1e, 0, 0x4000 }
5875 };
5876
f37658da 5877 rtl_set_def_aspm_entry_latency(tp);
7e18dca1
HW		 5878
5879 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5880 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
7e18dca1 5881
1ef7286e
AS		 5882 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5883 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7e18dca1 5884
fdf6fc06 5885 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1 5886
8d98aa39 5887 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7e18dca1 5888
fdf6fc06
FR		 5889 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5890 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 5891 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5892 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5893 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5894 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 5895 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 5896
5897 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 5898}
5899
5598bfe5
HW		 5900static void rtl_hw_start_8106(struct rtl8169_private *tp)
5901{
5598bfe5 5902 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5903 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5598bfe5 5904
1ef7286e
AS		 5905 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5906 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5907 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
b51ecea8 5908
5909 rtl_pcie_state_l2l3_enable(tp, false);
5598bfe5
HW		 5910}
5911
61cb532d 5912static void rtl_hw_start_8101(struct rtl8169_private *tp)
07ce4064 5913{
da78dbff
FR		 5914 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5915 tp->event_slow &= ~RxFIFOOver;
811fd301 5916
cecb5fd7 5917 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5918 tp->mac_version == RTL_GIGA_MAC_VER_16)
61cb532d 5919 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
8200bc72 5920 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5921
1ef7286e 5922 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
1a964649 5923
12d42c50 5924 tp->cp_cmd &= CPCMD_QUIRK_MASK;
1ef7286e 5925 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1a964649 5926
2857ffb7
FR		 5927 switch (tp->mac_version) {
5928 case RTL_GIGA_MAC_VER_07:
beb1fe18 5929 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5930 break;
5931
5932 case RTL_GIGA_MAC_VER_08:
beb1fe18 5933 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5934 break;
5935
5936 case RTL_GIGA_MAC_VER_09:
beb1fe18 5937 rtl_hw_start_8102e_2(tp);
2857ffb7 5938 break;
5a5e4443
HW		 5939
5940 case RTL_GIGA_MAC_VER_29:
beb1fe18 5941 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5942 break;
5943 case RTL_GIGA_MAC_VER_30:
beb1fe18 5944 rtl_hw_start_8105e_2(tp);
5a5e4443 5945 break;
7e18dca1
HW		 5946
5947 case RTL_GIGA_MAC_VER_37:
5948 rtl_hw_start_8402(tp);
5949 break;
5598bfe5
HW		 5950
5951 case RTL_GIGA_MAC_VER_39:
5952 rtl_hw_start_8106(tp);
5953 break;
58152cd4 5954 case RTL_GIGA_MAC_VER_43:
5955 rtl_hw_start_8168g_2(tp);
5956 break;
6e1d0b89
CHL		 5957 case RTL_GIGA_MAC_VER_47:
5958 case RTL_GIGA_MAC_VER_48:
5959 rtl_hw_start_8168h_1(tp);
5960 break;
cdf1a608
FR		 5961 }
5962
1ef7286e 5963 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4
LT		 5964}
5965
5966static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5967{
d58d46b5
FR		 5968 struct rtl8169_private *tp = netdev_priv(dev);
5969
d58d46b5
FR		 5970 if (new_mtu > ETH_DATA_LEN)
5971 rtl_hw_jumbo_enable(tp);
5972 else
5973 rtl_hw_jumbo_disable(tp);
5974
1da177e4 5975 dev->mtu = new_mtu;
350fb32a
MM		 5976 netdev_update_features(dev);
5977
323bb685 5978 return 0;
1da177e4
LT		 5979}
5980
5981static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5982{
95e0918d 5983 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5984 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5985}
5986
6f0333b8
ED		 5987static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5988 void **data_buff, struct RxDesc *desc)
1da177e4 5989{
1d0254dd
HK		 5990 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5991 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
48addcc9 5992
6f0333b8
ED		 5993 kfree(*data_buff);
5994 *data_buff = NULL;
1da177e4
LT		 5995 rtl8169_make_unusable_by_asic(desc);
5996}
5997
1d0254dd 5998static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
1da177e4
LT		 5999{
6000 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6001
a0750138
AD		 6002 /* Force memory writes to complete before releasing descriptor */
6003 dma_wmb();
6004
1d0254dd 6005 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
1da177e4
LT		 6006}
6007
6f0333b8
ED		 6008static inline void *rtl8169_align(void *data)
6009{
6010 return (void *)ALIGN((long)data, 16);
6011}
6012
0ecbe1ca
SG		 6013static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6014 struct RxDesc *desc)
1da177e4 6015{
6f0333b8 6016 void *data;
1da177e4 6017 dma_addr_t mapping;
1e1205b7 6018 struct device *d = tp_to_dev(tp);
d3b404c2 6019 int node = dev_to_node(d);
1da177e4 6020
1d0254dd 6021 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
6f0333b8
ED		 6022 if (!data)
6023 return NULL;
e9f63f30 6024
6f0333b8
ED		 6025 if (rtl8169_align(data) != data) {
6026 kfree(data);
1d0254dd 6027 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
6f0333b8
ED		 6028 if (!data)
6029 return NULL;
6030 }
3eafe507 6031
1d0254dd 6032 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
231aee63 6033 DMA_FROM_DEVICE);
d827d86b
SG		 6034 if (unlikely(dma_mapping_error(d, mapping))) {
6035 if (net_ratelimit())
6036 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 6037 goto err_out;
d827d86b 6038 }
1da177e4 6039
d731af78
HK		 6040 desc->addr = cpu_to_le64(mapping);
6041 rtl8169_mark_to_asic(desc);
6f0333b8 6042 return data;
3eafe507
SG		 6043
6044err_out:
6045 kfree(data);
6046 return NULL;
1da177e4
LT		 6047}
6048
6049static void rtl8169_rx_clear(struct rtl8169_private *tp)
6050{
07d3f51f 6051 unsigned int i;
1da177e4
LT		 6052
6053 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 6054 if (tp->Rx_databuff[i]) {
6055 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 6056 tp->RxDescArray + i);
6057 }
6058 }
6059}
6060
0ecbe1ca 6061static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 6062{
0ecbe1ca
SG		 6063 desc->opts1 |= cpu_to_le32(RingEnd);
6064}
5b0384f4 6065
0ecbe1ca
SG		 6066static int rtl8169_rx_fill(struct rtl8169_private *tp)
6067{
6068 unsigned int i;
1da177e4 6069
0ecbe1ca
SG		 6070 for (i = 0; i < NUM_RX_DESC; i++) {
6071 void *data;
4ae47c2d 6072
0ecbe1ca 6073 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 6074 if (!data) {
6075 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 6076 goto err_out;
6f0333b8
ED		 6077 }
6078 tp->Rx_databuff[i] = data;
1da177e4 6079 }
1da177e4 6080
0ecbe1ca
SG		 6081 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6082 return 0;
6083
6084err_out:
6085 rtl8169_rx_clear(tp);
6086 return -ENOMEM;
1da177e4
LT		 6087}
6088
b1127e64 6089static int rtl8169_init_ring(struct rtl8169_private *tp)
1da177e4 6090{
1da177e4
LT		 6091 rtl8169_init_ring_indexes(tp);
6092
b1127e64
HK		 6093 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
6094 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
1da177e4 6095
0ecbe1ca 6096 return rtl8169_rx_fill(tp);
1da177e4
LT		 6097}
6098
48addcc9 6099static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 6100 struct TxDesc *desc)
6101{
6102 unsigned int len = tx_skb->len;
6103
48addcc9
SG		 6104 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6105
1da177e4
LT		 6106 desc->opts1 = 0x00;
6107 desc->opts2 = 0x00;
6108 desc->addr = 0x00;
6109 tx_skb->len = 0;
6110}
6111
3eafe507
SG		 6112static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6113 unsigned int n)
1da177e4
LT		 6114{
6115 unsigned int i;
6116
3eafe507
SG		 6117 for (i = 0; i < n; i++) {
6118 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 6119 struct ring_info *tx_skb = tp->tx_skb + entry;
6120 unsigned int len = tx_skb->len;
6121
6122 if (len) {
6123 struct sk_buff *skb = tx_skb->skb;
6124
1e1205b7 6125 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
1da177e4
LT		 6126 tp->TxDescArray + entry);
6127 if (skb) {
7a4b813c 6128 dev_consume_skb_any(skb);
1da177e4
LT		 6129 tx_skb->skb = NULL;
6130 }
1da177e4
LT		 6131 }
6132 }
3eafe507
SG		 6133}
6134
6135static void rtl8169_tx_clear(struct rtl8169_private *tp)
6136{
6137 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 6138 tp->cur_tx = tp->dirty_tx = 0;
6139}
6140
4422bcd4 6141static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 6142{
c4028958 6143 struct net_device *dev = tp->dev;
56de414c 6144 int i;
1da177e4 6145
da78dbff
FR		 6146 napi_disable(&tp->napi);
6147 netif_stop_queue(dev);
6148 synchronize_sched();
1da177e4 6149
c7c2c39b 6150 rtl8169_hw_reset(tp);
6151
56de414c 6152 for (i = 0; i < NUM_RX_DESC; i++)
1d0254dd 6153 rtl8169_mark_to_asic(tp->RxDescArray + i);
56de414c 6154
1da177e4 6155 rtl8169_tx_clear(tp);
c7c2c39b 6156 rtl8169_init_ring_indexes(tp);
1da177e4 6157
da78dbff 6158 napi_enable(&tp->napi);
61cb532d 6159 rtl_hw_start(tp);
56de414c 6160 netif_wake_queue(dev);
1da177e4
LT		 6161}
6162
6163static void rtl8169_tx_timeout(struct net_device *dev)
6164{
da78dbff
FR		 6165 struct rtl8169_private *tp = netdev_priv(dev);
6166
6167 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6168}
6169
6170static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 6171 u32 *opts)
1da177e4
LT		 6172{
6173 struct skb_shared_info *info = skb_shinfo(skb);
6174 unsigned int cur_frag, entry;
6e1d0b89 6175 struct TxDesc *uninitialized_var(txd);
1e1205b7 6176 struct device *d = tp_to_dev(tp);
1da177e4
LT		 6177
6178 entry = tp->cur_tx;
6179 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 6180 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 6181 dma_addr_t mapping;
6182 u32 status, len;
6183 void *addr;
6184
6185 entry = (entry + 1) % NUM_TX_DESC;
6186
6187 txd = tp->TxDescArray + entry;
9e903e08 6188 len = skb_frag_size(frag);
929f6189 6189 addr = skb_frag_address(frag);
48addcc9 6190 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 6191 if (unlikely(dma_mapping_error(d, mapping))) {
6192 if (net_ratelimit())
6193 netif_err(tp, drv, tp->dev,
6194 "Failed to map TX fragments DMA!\n");
3eafe507 6195 goto err_out;
d827d86b 6196 }
1da177e4 6197
cecb5fd7 6198 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 6199 status = opts[0] | len |
6200 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6201
6202 txd->opts1 = cpu_to_le32(status);
2b7b4318 6203 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 6204 txd->addr = cpu_to_le64(mapping);
6205
6206 tp->tx_skb[entry].len = len;
6207 }
6208
6209 if (cur_frag) {
6210 tp->tx_skb[entry].skb = skb;
6211 txd->opts1 |= cpu_to_le32(LastFrag);
6212 }
6213
6214 return cur_frag;
3eafe507
SG		 6215
6216err_out:
6217 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6218 return -EIO;
1da177e4
LT		 6219}
6220
b423e9ae 6221static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6222{
6223 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6224}
6225
e974604b 6226static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6227 struct net_device *dev);
6228/* r8169_csum_workaround()
6229 * The hw limites the value the transport offset. When the offset is out of the
6230 * range, calculate the checksum by sw.
6231 */
6232static void r8169_csum_workaround(struct rtl8169_private *tp,
6233 struct sk_buff *skb)
6234{
6235 if (skb_shinfo(skb)->gso_size) {
6236 netdev_features_t features = tp->dev->features;
6237 struct sk_buff *segs, *nskb;
6238
6239 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6240 segs = skb_gso_segment(skb, features);
6241 if (IS_ERR(segs) || !segs)
6242 goto drop;
6243
6244 do {
6245 nskb = segs;
6246 segs = segs->next;
6247 nskb->next = NULL;
6248 rtl8169_start_xmit(nskb, tp->dev);
6249 } while (segs);
6250
eb781397 6251 dev_consume_skb_any(skb);
e974604b 6252 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6253 if (skb_checksum_help(skb) < 0)
6254 goto drop;
6255
6256 rtl8169_start_xmit(skb, tp->dev);
6257 } else {
6258 struct net_device_stats *stats;
6259
6260drop:
6261 stats = &tp->dev->stats;
6262 stats->tx_dropped++;
eb781397 6263 dev_kfree_skb_any(skb);
e974604b 6264 }
6265}
6266
6267/* msdn_giant_send_check()
6268 * According to the document of microsoft, the TCP Pseudo Header excludes the
6269 * packet length for IPv6 TCP large packets.
6270 */
6271static int msdn_giant_send_check(struct sk_buff *skb)
6272{
6273 const struct ipv6hdr *ipv6h;
6274 struct tcphdr *th;
6275 int ret;
6276
6277 ret = skb_cow_head(skb, 0);
6278 if (ret)
6279 return ret;
6280
6281 ipv6h = ipv6_hdr(skb);
6282 th = tcp_hdr(skb);
6283
6284 th->check = 0;
6285 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6286
6287 return ret;
6288}
6289
5888d3fc 6290static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6291 struct sk_buff *skb, u32 *opts)
1da177e4 6292{
350fb32a
MM		 6293 u32 mss = skb_shinfo(skb)->gso_size;
6294
2b7b4318
FR		 6295 if (mss) {
6296 opts[0] |= TD_LSO;
5888d3fc 6297 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6298 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6299 const struct iphdr *ip = ip_hdr(skb);
6300
6301 if (ip->protocol == IPPROTO_TCP)
6302 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6303 else if (ip->protocol == IPPROTO_UDP)
6304 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6305 else
6306 WARN_ON_ONCE(1);
6307 }
6308
6309 return true;
6310}
6311
6312static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6313 struct sk_buff *skb, u32 *opts)
6314{
bdfa4ed6 6315 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 6316 u32 mss = skb_shinfo(skb)->gso_size;
6317
6318 if (mss) {
e974604b 6319 if (transport_offset > GTTCPHO_MAX) {
6320 netif_warn(tp, tx_err, tp->dev,
6321 "Invalid transport offset 0x%x for TSO\n",
6322 transport_offset);
6323 return false;
6324 }
6325
4ff36466 6326 switch (vlan_get_protocol(skb)) {
e974604b 6327 case htons(ETH_P_IP):
6328 opts[0] |= TD1_GTSENV4;
6329 break;
6330
6331 case htons(ETH_P_IPV6):
6332 if (msdn_giant_send_check(skb))
6333 return false;
6334
6335 opts[0] |= TD1_GTSENV6;
6336 break;
6337
6338 default:
6339 WARN_ON_ONCE(1);
6340 break;
6341 }
6342
bdfa4ed6 6343 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 6344 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 6345 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 6346 u8 ip_protocol;
1da177e4 6347
b423e9ae 6348 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6349 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
b423e9ae 6350
e974604b 6351 if (transport_offset > TCPHO_MAX) {
6352 netif_warn(tp, tx_err, tp->dev,
6353 "Invalid transport offset 0x%x\n",
6354 transport_offset);
6355 return false;
6356 }
6357
4ff36466 6358 switch (vlan_get_protocol(skb)) {
e974604b 6359 case htons(ETH_P_IP):
6360 opts[1] |= TD1_IPv4_CS;
6361 ip_protocol = ip_hdr(skb)->protocol;
6362 break;
6363
6364 case htons(ETH_P_IPV6):
6365 opts[1] |= TD1_IPv6_CS;
6366 ip_protocol = ipv6_hdr(skb)->nexthdr;
6367 break;
6368
6369 default:
6370 ip_protocol = IPPROTO_RAW;
6371 break;
6372 }
6373
6374 if (ip_protocol == IPPROTO_TCP)
6375 opts[1] |= TD1_TCP_CS;
6376 else if (ip_protocol == IPPROTO_UDP)
6377 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 6378 else
6379 WARN_ON_ONCE(1);
e974604b 6380
6381 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 6382 } else {
6383 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6384 return !eth_skb_pad(skb);
1da177e4 6385 }
5888d3fc 6386
b423e9ae 6387 return true;
1da177e4
LT		 6388}
6389
61357325
SH		 6390static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6391 struct net_device *dev)
1da177e4
LT		 6392{
6393 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 6394 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4 6395 struct TxDesc *txd = tp->TxDescArray + entry;
1e1205b7 6396 struct device *d = tp_to_dev(tp);
1da177e4
LT		 6397 dma_addr_t mapping;
6398 u32 status, len;
2b7b4318 6399 u32 opts[2];
3eafe507 6400 int frags;
5b0384f4 6401
477206a0 6402 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 6403 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 6404 goto err_stop_0;
1da177e4
LT		 6405 }
6406
6407 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 6408 goto err_stop_0;
6409
b423e9ae 6410 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6411 opts[0] = DescOwn;
6412
e974604b 6413 if (!tp->tso_csum(tp, skb, opts)) {
6414 r8169_csum_workaround(tp, skb);
6415 return NETDEV_TX_OK;
6416 }
b423e9ae 6417
3eafe507 6418 len = skb_headlen(skb);
48addcc9 6419 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 6420 if (unlikely(dma_mapping_error(d, mapping))) {
6421 if (net_ratelimit())
6422 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 6423 goto err_dma_0;
d827d86b 6424 }
3eafe507
SG		 6425
6426 tp->tx_skb[entry].len = len;
6427 txd->addr = cpu_to_le64(mapping);
1da177e4 6428
2b7b4318 6429 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 6430 if (frags < 0)
6431 goto err_dma_1;
6432 else if (frags)
2b7b4318 6433 opts[0] |= FirstFrag;
3eafe507 6434 else {
2b7b4318 6435 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 6436 tp->tx_skb[entry].skb = skb;
6437 }
6438
2b7b4318
FR		 6439 txd->opts2 = cpu_to_le32(opts[1]);
6440
5047fb5d
RC		 6441 skb_tx_timestamp(skb);
6442
a0750138
AD		 6443 /* Force memory writes to complete before releasing descriptor */
6444 dma_wmb();
1da177e4 6445
cecb5fd7 6446 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 6447 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6448 txd->opts1 = cpu_to_le32(status);
6449
a0750138 6450 /* Force all memory writes to complete before notifying device */
4c020a96 6451 wmb();
1da177e4 6452
a0750138
AD		 6453 tp->cur_tx += frags + 1;
6454
1ef7286e 6455 RTL_W8(tp, TxPoll, NPQ);
1da177e4 6456
87cda7cb 6457 mmiowb();
da78dbff 6458
87cda7cb 6459 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 6460 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6461 * not miss a ring update when it notices a stopped queue.
6462 */
6463 smp_wmb();
1da177e4 6464 netif_stop_queue(dev);
ae1f23fb
FR		 6465 /* Sync with rtl_tx:
6466 * - publish queue status and cur_tx ring index (write barrier)
6467 * - refresh dirty_tx ring index (read barrier).
6468 * May the current thread have a pessimistic view of the ring
6469 * status and forget to wake up queue, a racing rtl_tx thread
6470 * can't.
6471 */
1e874e04 6472 smp_mb();
477206a0 6473 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 6474 netif_wake_queue(dev);
6475 }
6476
61357325 6477 return NETDEV_TX_OK;
1da177e4 6478
3eafe507 6479err_dma_1:
48addcc9 6480 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 6481err_dma_0:
989c9ba1 6482 dev_kfree_skb_any(skb);
3eafe507
SG		 6483 dev->stats.tx_dropped++;
6484 return NETDEV_TX_OK;
6485
6486err_stop_0:
1da177e4 6487 netif_stop_queue(dev);
cebf8cc7 6488 dev->stats.tx_dropped++;
61357325 6489 return NETDEV_TX_BUSY;
1da177e4
LT		 6490}
6491
6492static void rtl8169_pcierr_interrupt(struct net_device *dev)
6493{
6494 struct rtl8169_private *tp = netdev_priv(dev);
6495 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 6496 u16 pci_status, pci_cmd;
6497
6498 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6499 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6500
bf82c189
JP		 6501 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6502 pci_cmd, pci_status);
1da177e4
LT		 6503
6504 /*
6505 * The recovery sequence below admits a very elaborated explanation:
6506 * - it seems to work;
d03902b8
FR		 6507 * - I did not see what else could be done;
6508 * - it makes iop3xx happy.
1da177e4
LT		 6509 *
6510 * Feel free to adjust to your needs.
6511 */
a27993f3 6512 if (pdev->broken_parity_status)
d03902b8
FR		 6513 pci_cmd &= ~PCI_COMMAND_PARITY;
6514 else
6515 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6516
6517 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 6518
6519 pci_write_config_word(pdev, PCI_STATUS,
6520 pci_status & (PCI_STATUS_DETECTED_PARITY |
6521 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6522 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6523
6524 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 6525 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
bf82c189 6526 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4 6527 tp->cp_cmd &= ~PCIDAC;
1ef7286e 6528 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1da177e4 6529 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 6530 }
6531
e6de30d6 6532 rtl8169_hw_reset(tp);
d03902b8 6533
98ddf986 6534 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6535}
6536
da78dbff 6537static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 6538{
6539 unsigned int dirty_tx, tx_left;
6540
1da177e4
LT		 6541 dirty_tx = tp->dirty_tx;
6542 smp_rmb();
6543 tx_left = tp->cur_tx - dirty_tx;
6544
6545 while (tx_left > 0) {
6546 unsigned int entry = dirty_tx % NUM_TX_DESC;
6547 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 6548 u32 status;
6549
1da177e4
LT		 6550 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6551 if (status & DescOwn)
6552 break;
6553
a0750138
AD		 6554 /* This barrier is needed to keep us from reading
6555 * any other fields out of the Tx descriptor until
6556 * we know the status of DescOwn
6557 */
6558 dma_rmb();
6559
1e1205b7 6560 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
48addcc9 6561 tp->TxDescArray + entry);
1da177e4 6562 if (status & LastFrag) {
87cda7cb
DM		 6563 u64_stats_update_begin(&tp->tx_stats.syncp);
6564 tp->tx_stats.packets++;
6565 tp->tx_stats.bytes += tx_skb->skb->len;
6566 u64_stats_update_end(&tp->tx_stats.syncp);
7a4b813c 6567 dev_consume_skb_any(tx_skb->skb);
1da177e4
LT		 6568 tx_skb->skb = NULL;
6569 }
6570 dirty_tx++;
6571 tx_left--;
6572 }
6573
6574 if (tp->dirty_tx != dirty_tx) {
6575 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6576 /* Sync with rtl8169_start_xmit:
6577 * - publish dirty_tx ring index (write barrier)
6578 * - refresh cur_tx ring index and queue status (read barrier)
6579 * May the current thread miss the stopped queue condition,
6580 * a racing xmit thread can only have a right view of the
6581 * ring status.
6582 */
1e874e04 6583 smp_mb();
1da177e4 6584 if (netif_queue_stopped(dev) &&
477206a0 6585 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6586 netif_wake_queue(dev);
6587 }
d78ae2dc
FR		 6588 /*
6589 * 8168 hack: TxPoll requests are lost when the Tx packets are
6590 * too close. Let's kick an extra TxPoll request when a burst
6591 * of start_xmit activity is detected (if it is not detected,
6592 * it is slow enough). -- FR
6593 */
1ef7286e
AS		 6594 if (tp->cur_tx != dirty_tx)
6595 RTL_W8(tp, TxPoll, NPQ);
1da177e4
LT		 6596 }
6597}
6598
126fa4b9
FR		 6599static inline int rtl8169_fragmented_frame(u32 status)
6600{
6601 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6602}
6603
adea1ac7 6604static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6605{
1da177e4
LT		 6606 u32 status = opts1 & RxProtoMask;
6607
6608 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6609 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6610 skb->ip_summed = CHECKSUM_UNNECESSARY;
6611 else
bc8acf2c 6612 skb_checksum_none_assert(skb);
1da177e4
LT		 6613}
6614
6f0333b8
ED		 6615static struct sk_buff *rtl8169_try_rx_copy(void *data,
6616 struct rtl8169_private *tp,
6617 int pkt_size,
6618 dma_addr_t addr)
1da177e4 6619{
b449655f 6620 struct sk_buff *skb;
1e1205b7 6621 struct device *d = tp_to_dev(tp);
b449655f 6622
6f0333b8 6623 data = rtl8169_align(data);
48addcc9 6624 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8 6625 prefetch(data);
e2338f86 6626 skb = napi_alloc_skb(&tp->napi, pkt_size);
6f0333b8 6627 if (skb)
8a67aa86 6628 skb_copy_to_linear_data(skb, data, pkt_size);
48addcc9
SG		 6629 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6630
6f0333b8 6631 return skb;
1da177e4
LT		 6632}
6633
da78dbff 6634static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6635{
6636 unsigned int cur_rx, rx_left;
6f0333b8 6637 unsigned int count;
1da177e4 6638
1da177e4 6639 cur_rx = tp->cur_rx;
1da177e4 6640
9fba0812 6641 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6642 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6643 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6644 u32 status;
6645
6202806e 6646 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 6647 if (status & DescOwn)
6648 break;
a0750138
AD		 6649
6650 /* This barrier is needed to keep us from reading
6651 * any other fields out of the Rx descriptor until
6652 * we know the status of DescOwn
6653 */
6654 dma_rmb();
6655
4dcb7d33 6656 if (unlikely(status & RxRES)) {
bf82c189
JP		 6657 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6658 status);
cebf8cc7 6659 dev->stats.rx_errors++;
1da177e4 6660 if (status & (RxRWT | RxRUNT))
cebf8cc7 6661 dev->stats.rx_length_errors++;
1da177e4 6662 if (status & RxCRC)
cebf8cc7 6663 dev->stats.rx_crc_errors++;
6202806e
HK		 6664 /* RxFOVF is a reserved bit on later chip versions */
6665 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6666 status & RxFOVF) {
da78dbff 6667 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6668 dev->stats.rx_fifo_errors++;
6202806e
HK		 6669 } else if (status & (RxRUNT | RxCRC) &&
6670 !(status & RxRWT) &&
6671 dev->features & NETIF_F_RXALL) {
6bbe021d 6672 goto process_pkt;
6202806e 6673 }
1da177e4 6674 } else {
6f0333b8 6675 struct sk_buff *skb;
6bbe021d
BG		 6676 dma_addr_t addr;
6677 int pkt_size;
6678
6679process_pkt:
6680 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6681 if (likely(!(dev->features & NETIF_F_RXFCS)))
6682 pkt_size = (status & 0x00003fff) - 4;
6683 else
6684 pkt_size = status & 0x00003fff;
1da177e4 6685
126fa4b9
FR		 6686 /*
6687 * The driver does not support incoming fragmented
6688 * frames. They are seen as a symptom of over-mtu
6689 * sized frames.
6690 */
6691 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6692 dev->stats.rx_dropped++;
6693 dev->stats.rx_length_errors++;
ce11ff5e 6694 goto release_descriptor;
126fa4b9
FR		 6695 }
6696
6f0333b8
ED		 6697 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6698 tp, pkt_size, addr);
6f0333b8
ED		 6699 if (!skb) {
6700 dev->stats.rx_dropped++;
ce11ff5e 6701 goto release_descriptor;
1da177e4
LT		 6702 }
6703
adea1ac7 6704 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6705 skb_put(skb, pkt_size);
6706 skb->protocol = eth_type_trans(skb, dev);
6707
7a8fc77b
FR		 6708 rtl8169_rx_vlan_tag(desc, skb);
6709
39174291 6710 if (skb->pkt_type == PACKET_MULTICAST)
6711 dev->stats.multicast++;
6712
56de414c 6713 napi_gro_receive(&tp->napi, skb);
1da177e4 6714
8027aa24
JW		 6715 u64_stats_update_begin(&tp->rx_stats.syncp);
6716 tp->rx_stats.packets++;
6717 tp->rx_stats.bytes += pkt_size;
6718 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6719 }
ce11ff5e 6720release_descriptor:
6721 desc->opts2 = 0;
1d0254dd 6722 rtl8169_mark_to_asic(desc);
1da177e4
LT		 6723 }
6724
6725 count = cur_rx - tp->cur_rx;
6726 tp->cur_rx = cur_rx;
6727
1da177e4
LT		 6728 return count;
6729}
6730
07d3f51f 6731static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6732{
ebcd5daa 6733 struct rtl8169_private *tp = dev_instance;
1da177e4 6734 int handled = 0;
9085cdfa 6735 u16 status;
1da177e4 6736
9085cdfa 6737 status = rtl_get_events(tp);
da78dbff
FR		 6738 if (status && status != 0xffff) {
6739 status &= RTL_EVENT_NAPI | tp->event_slow;
6740 if (status) {
6741 handled = 1;
1da177e4 6742
da78dbff 6743 rtl_irq_disable(tp);
9a899a35 6744 napi_schedule_irqoff(&tp->napi);
f11a377b 6745 }
da78dbff
FR		 6746 }
6747 return IRQ_RETVAL(handled);
6748}
1da177e4 6749
da78dbff
FR		 6750/*
6751 * Workqueue context.
6752 */
6753static void rtl_slow_event_work(struct rtl8169_private *tp)
6754{
6755 struct net_device *dev = tp->dev;
6756 u16 status;
6757
6758 status = rtl_get_events(tp) & tp->event_slow;
6759 rtl_ack_events(tp, status);
1da177e4 6760
da78dbff
FR		 6761 if (unlikely(status & RxFIFOOver)) {
6762 switch (tp->mac_version) {
6763 /* Work around for rx fifo overflow */
6764 case RTL_GIGA_MAC_VER_11:
6765 netif_stop_queue(dev);
934714d0
FR		 6766 /* XXX - Hack alert. See rtl_task(). */
6767 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6768 default:
f11a377b
DD		 6769 break;
6770 }
da78dbff 6771 }
1da177e4 6772
da78dbff
FR		 6773 if (unlikely(status & SYSErr))
6774 rtl8169_pcierr_interrupt(dev);
0e485150 6775
da78dbff 6776 if (status & LinkChg)
f1e911d5 6777 phy_mac_interrupt(dev->phydev);
1da177e4 6778
7dbb4918 6779 rtl_irq_enable_all(tp);
1da177e4
LT		 6780}
6781
4422bcd4
FR		 6782static void rtl_task(struct work_struct *work)
6783{
da78dbff
FR		 6784 static const struct {
6785 int bitnr;
6786 void (*action)(struct rtl8169_private *);
6787 } rtl_work[] = {
934714d0 6788 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6789 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6790 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
da78dbff 6791 };
4422bcd4
FR		 6792 struct rtl8169_private *tp =
6793 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6794 struct net_device *dev = tp->dev;
6795 int i;
6796
6797 rtl_lock_work(tp);
6798
6c4a70c5
FR		 6799 if (!netif_running(dev) ||
6800 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6801 goto out_unlock;
6802
6803 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6804 bool pending;
6805
da78dbff 6806 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6807 if (pending)
6808 rtl_work[i].action(tp);
6809 }
4422bcd4 6810
da78dbff
FR		 6811out_unlock:
6812 rtl_unlock_work(tp);
4422bcd4
FR		 6813}
6814
bea3348e 6815static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6816{
bea3348e
SH		 6817 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6818 struct net_device *dev = tp->dev;
da78dbff
FR		 6819 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6820 int work_done= 0;
6821 u16 status;
6822
6823 status = rtl_get_events(tp);
6824 rtl_ack_events(tp, status & ~tp->event_slow);
6825
6826 if (status & RTL_EVENT_NAPI_RX)
6827 work_done = rtl_rx(dev, tp, (u32) budget);
6828
6829 if (status & RTL_EVENT_NAPI_TX)
6830 rtl_tx(dev, tp);
1da177e4 6831
da78dbff
FR		 6832 if (status & tp->event_slow) {
6833 enable_mask &= ~tp->event_slow;
6834
6835 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6836 }
1da177e4 6837
bea3348e 6838 if (work_done < budget) {
6ad20165 6839 napi_complete_done(napi, work_done);
f11a377b 6840
da78dbff
FR		 6841 rtl_irq_enable(tp, enable_mask);
6842 mmiowb();
1da177e4
LT		 6843 }
6844
bea3348e 6845 return work_done;
1da177e4 6846}
1da177e4 6847
1ef7286e 6848static void rtl8169_rx_missed(struct net_device *dev)
523a6094
FR		 6849{
6850 struct rtl8169_private *tp = netdev_priv(dev);
6851
6852 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6853 return;
6854
1ef7286e
AS		 6855 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6856 RTL_W32(tp, RxMissed, 0);
523a6094
FR		 6857}
6858
f1e911d5
HK		 6859static void r8169_phylink_handler(struct net_device *ndev)
6860{
6861 struct rtl8169_private *tp = netdev_priv(ndev);
6862
6863 if (netif_carrier_ok(ndev)) {
6864 rtl_link_chg_patch(tp);
6865 pm_request_resume(&tp->pci_dev->dev);
6866 } else {
6867 pm_runtime_idle(&tp->pci_dev->dev);
6868 }
6869
6870 if (net_ratelimit())
6871 phy_print_status(ndev->phydev);
6872}
6873
6874static int r8169_phy_connect(struct rtl8169_private *tp)
6875{
6876 struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6877 phy_interface_t phy_mode;
6878 int ret;
6879
6880 phy_mode = tp->mii.supports_gmii ? PHY_INTERFACE_MODE_GMII :
6881 PHY_INTERFACE_MODE_MII;
6882
6883 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6884 phy_mode);
6885 if (ret)
6886 return ret;
6887
6888 if (!tp->mii.supports_gmii)
6889 phy_set_max_speed(phydev, SPEED_100);
6890
6891 /* Ensure to advertise everything, incl. pause */
6892 phydev->advertising = phydev->supported;
6893
6894 phy_attached_info(phydev);
6895
6896 return 0;
6897}
6898
1da177e4
LT		 6899static void rtl8169_down(struct net_device *dev)
6900{
6901 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6902
f1e911d5
HK		 6903 phy_stop(dev->phydev);
6904
93dd79e8 6905 napi_disable(&tp->napi);
da78dbff 6906 netif_stop_queue(dev);
1da177e4 6907
92fc43b4 6908 rtl8169_hw_reset(tp);
323bb685
SG		 6909 /*
6910 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6911 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6912 * and napi is disabled (rtl8169_poll).
323bb685 6913 */
1ef7286e 6914 rtl8169_rx_missed(dev);
1da177e4 6915
1da177e4 6916 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6917 synchronize_sched();
1da177e4 6918
1da177e4
LT		 6919 rtl8169_tx_clear(tp);
6920
6921 rtl8169_rx_clear(tp);
065c27c1 6922
6923 rtl_pll_power_down(tp);
1da177e4
LT		 6924}
6925
6926static int rtl8169_close(struct net_device *dev)
6927{
6928 struct rtl8169_private *tp = netdev_priv(dev);
6929 struct pci_dev *pdev = tp->pci_dev;
6930
e1759441
RW		 6931 pm_runtime_get_sync(&pdev->dev);
6932
cecb5fd7 6933 /* Update counters before going down */
e71c9ce2 6934 rtl8169_update_counters(tp);
355423d0 6935
da78dbff 6936 rtl_lock_work(tp);
6c4a70c5 6937 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6938
1da177e4 6939 rtl8169_down(dev);
da78dbff 6940 rtl_unlock_work(tp);
1da177e4 6941
4ea72445
L		 6942 cancel_work_sync(&tp->wk.work);
6943
f1e911d5
HK		 6944 phy_disconnect(dev->phydev);
6945
ebcd5daa 6946 pci_free_irq(pdev, 0, tp);
1da177e4 6947
82553bb6
SG		 6948 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6949 tp->RxPhyAddr);
6950 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6951 tp->TxPhyAddr);
1da177e4
LT		 6952 tp->TxDescArray = NULL;
6953 tp->RxDescArray = NULL;
6954
e1759441
RW		 6955 pm_runtime_put_sync(&pdev->dev);
6956
1da177e4
LT		 6957 return 0;
6958}
6959
dc1c00ce
FR		 6960#ifdef CONFIG_NET_POLL_CONTROLLER
6961static void rtl8169_netpoll(struct net_device *dev)
6962{
6963 struct rtl8169_private *tp = netdev_priv(dev);
6964
6d8b8349 6965 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
dc1c00ce
FR		 6966}
6967#endif
6968
df43ac78
FR		 6969static int rtl_open(struct net_device *dev)
6970{
6971 struct rtl8169_private *tp = netdev_priv(dev);
df43ac78
FR		 6972 struct pci_dev *pdev = tp->pci_dev;
6973 int retval = -ENOMEM;
6974
6975 pm_runtime_get_sync(&pdev->dev);
6976
6977 /*
e75d6606 6978 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6979 * dma_alloc_coherent provides more.
6980 */
6981 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6982 &tp->TxPhyAddr, GFP_KERNEL);
6983 if (!tp->TxDescArray)
6984 goto err_pm_runtime_put;
6985
6986 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6987 &tp->RxPhyAddr, GFP_KERNEL);
6988 if (!tp->RxDescArray)
6989 goto err_free_tx_0;
6990
b1127e64 6991 retval = rtl8169_init_ring(tp);
df43ac78
FR		 6992 if (retval < 0)
6993 goto err_free_rx_1;
6994
6995 INIT_WORK(&tp->wk.work, rtl_task);
6996
6997 smp_mb();
6998
6999 rtl_request_firmware(tp);
7000
ebcd5daa 7001 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6c6aa15f 7002 dev->name);
df43ac78
FR		 7003 if (retval < 0)
7004 goto err_release_fw_2;
7005
f1e911d5
HK		 7006 retval = r8169_phy_connect(tp);
7007 if (retval)
7008 goto err_free_irq;
7009
df43ac78
FR		 7010 rtl_lock_work(tp);
7011
7012 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7013
7014 napi_enable(&tp->napi);
7015
7016 rtl8169_init_phy(dev, tp);
7017
df43ac78
FR		 7018 rtl_pll_power_up(tp);
7019
61cb532d 7020 rtl_hw_start(tp);
df43ac78 7021
e71c9ce2 7022 if (!rtl8169_init_counter_offsets(tp))
6e85d5ad
CV		 7023 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7024
f1e911d5 7025 phy_start(dev->phydev);
df43ac78
FR		 7026 netif_start_queue(dev);
7027
7028 rtl_unlock_work(tp);
7029
a92a0849 7030 pm_runtime_put_sync(&pdev->dev);
df43ac78
FR		 7031out:
7032 return retval;
7033
f1e911d5
HK		 7034err_free_irq:
7035 pci_free_irq(pdev, 0, tp);
df43ac78
FR		 7036err_release_fw_2:
7037 rtl_release_firmware(tp);
7038 rtl8169_rx_clear(tp);
7039err_free_rx_1:
7040 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7041 tp->RxPhyAddr);
7042 tp->RxDescArray = NULL;
7043err_free_tx_0:
7044 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7045 tp->TxPhyAddr);
7046 tp->TxDescArray = NULL;
7047err_pm_runtime_put:
7048 pm_runtime_put_noidle(&pdev->dev);
7049 goto out;
7050}
7051
bc1f4470 7052static void
8027aa24 7053rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 7054{
7055 struct rtl8169_private *tp = netdev_priv(dev);
f09cf4b7 7056 struct pci_dev *pdev = tp->pci_dev;
42020320 7057 struct rtl8169_counters *counters = tp->counters;
8027aa24 7058 unsigned int start;
1da177e4 7059
f09cf4b7
CHL		 7060 pm_runtime_get_noresume(&pdev->dev);
7061
7062 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
1ef7286e 7063 rtl8169_rx_missed(dev);
5b0384f4 7064
8027aa24 7065 do {
57a7744e 7066 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 7067 stats->rx_packets = tp->rx_stats.packets;
7068 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 7069 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 7070
8027aa24 7071 do {
57a7744e 7072 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 7073 stats->tx_packets = tp->tx_stats.packets;
7074 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 7075 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 7076
7077 stats->rx_dropped = dev->stats.rx_dropped;
7078 stats->tx_dropped = dev->stats.tx_dropped;
7079 stats->rx_length_errors = dev->stats.rx_length_errors;
7080 stats->rx_errors = dev->stats.rx_errors;
7081 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7082 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7083 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 7084 stats->multicast = dev->stats.multicast;
8027aa24 7085
6e85d5ad
CV		 7086 /*
7087 * Fetch additonal counter values missing in stats collected by driver
7088 * from tally counters.
7089 */
f09cf4b7 7090 if (pm_runtime_active(&pdev->dev))
e71c9ce2 7091 rtl8169_update_counters(tp);
6e85d5ad
CV		 7092
7093 /*
7094 * Subtract values fetched during initalization.
7095 * See rtl8169_init_counter_offsets for a description why we do that.
7096 */
42020320 7097 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 7098 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 7099 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 7100 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 7101 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 7102 le16_to_cpu(tp->tc_offset.tx_aborted);
7103
f09cf4b7 7104 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 7105}
7106
861ab440 7107static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 7108{
065c27c1 7109 struct rtl8169_private *tp = netdev_priv(dev);
7110
5d06a99f 7111 if (!netif_running(dev))
861ab440 7112 return;
5d06a99f 7113
f1e911d5 7114 phy_stop(dev->phydev);
5d06a99f
FR		 7115 netif_device_detach(dev);
7116 netif_stop_queue(dev);
da78dbff
FR		 7117
7118 rtl_lock_work(tp);
7119 napi_disable(&tp->napi);
6c4a70c5 7120 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 7121 rtl_unlock_work(tp);
7122
7123 rtl_pll_power_down(tp);
861ab440
RW		 7124}
7125
7126#ifdef CONFIG_PM
7127
7128static int rtl8169_suspend(struct device *device)
7129{
7130 struct pci_dev *pdev = to_pci_dev(device);
7131 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 7132
861ab440 7133 rtl8169_net_suspend(dev);
1371fa6d 7134
5d06a99f
FR		 7135 return 0;
7136}
7137
e1759441
RW		 7138static void __rtl8169_resume(struct net_device *dev)
7139{
065c27c1 7140 struct rtl8169_private *tp = netdev_priv(dev);
7141
e1759441 7142 netif_device_attach(dev);
065c27c1 7143
7144 rtl_pll_power_up(tp);
92bad850 7145 rtl8169_init_phy(dev, tp);
065c27c1 7146
f1e911d5
HK		 7147 phy_start(tp->dev->phydev);
7148
cff4c162
AS		 7149 rtl_lock_work(tp);
7150 napi_enable(&tp->napi);
6c4a70c5 7151 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 7152 rtl_unlock_work(tp);
da78dbff 7153
98ddf986 7154 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 7155}
7156
861ab440 7157static int rtl8169_resume(struct device *device)
5d06a99f 7158{
861ab440 7159 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f
FR		 7160 struct net_device *dev = pci_get_drvdata(pdev);
7161
e1759441
RW		 7162 if (netif_running(dev))
7163 __rtl8169_resume(dev);
5d06a99f 7164
e1759441
RW		 7165 return 0;
7166}
7167
7168static int rtl8169_runtime_suspend(struct device *device)
7169{
7170 struct pci_dev *pdev = to_pci_dev(device);
7171 struct net_device *dev = pci_get_drvdata(pdev);
7172 struct rtl8169_private *tp = netdev_priv(dev);
7173
a92a0849
HK		 7174 if (!tp->TxDescArray) {
7175 rtl_pll_power_down(tp);
e1759441 7176 return 0;
a92a0849 7177 }
e1759441 7178
da78dbff 7179 rtl_lock_work(tp);
e1759441 7180 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 7181 rtl_unlock_work(tp);
e1759441
RW		 7182
7183 rtl8169_net_suspend(dev);
7184
f09cf4b7 7185 /* Update counters before going runtime suspend */
1ef7286e 7186 rtl8169_rx_missed(dev);
e71c9ce2 7187 rtl8169_update_counters(tp);
f09cf4b7 7188
e1759441
RW		 7189 return 0;
7190}
7191
7192static int rtl8169_runtime_resume(struct device *device)
7193{
7194 struct pci_dev *pdev = to_pci_dev(device);
7195 struct net_device *dev = pci_get_drvdata(pdev);
7196 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 7197 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 7198
7199 if (!tp->TxDescArray)
7200 return 0;
7201
da78dbff 7202 rtl_lock_work(tp);
e1759441 7203 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff 7204 rtl_unlock_work(tp);
e1759441
RW		 7205
7206 __rtl8169_resume(dev);
5d06a99f 7207
5d06a99f
FR		 7208 return 0;
7209}
7210
e1759441
RW		 7211static int rtl8169_runtime_idle(struct device *device)
7212{
7213 struct pci_dev *pdev = to_pci_dev(device);
7214 struct net_device *dev = pci_get_drvdata(pdev);
e1759441 7215
a92a0849
HK		 7216 if (!netif_running(dev) || !netif_carrier_ok(dev))
7217 pm_schedule_suspend(device, 10000);
7218
7219 return -EBUSY;
e1759441
RW		 7220}
7221
47145210 7222static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 7223 .suspend = rtl8169_suspend,
7224 .resume = rtl8169_resume,
7225 .freeze = rtl8169_suspend,
7226 .thaw = rtl8169_resume,
7227 .poweroff = rtl8169_suspend,
7228 .restore = rtl8169_resume,
7229 .runtime_suspend = rtl8169_runtime_suspend,
7230 .runtime_resume = rtl8169_runtime_resume,
7231 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 7232};
7233
7234#define RTL8169_PM_OPS (&rtl8169_pm_ops)
7235
7236#else /* !CONFIG_PM */
7237
7238#define RTL8169_PM_OPS NULL
7239
7240#endif /* !CONFIG_PM */
7241
649b3b8c 7242static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7243{
649b3b8c 7244 /* WoL fails with 8168b when the receiver is disabled. */
7245 switch (tp->mac_version) {
7246 case RTL_GIGA_MAC_VER_11:
7247 case RTL_GIGA_MAC_VER_12:
7248 case RTL_GIGA_MAC_VER_17:
7249 pci_clear_master(tp->pci_dev);
7250
1ef7286e 7251 RTL_W8(tp, ChipCmd, CmdRxEnb);
649b3b8c 7252 /* PCI commit */
1ef7286e 7253 RTL_R8(tp, ChipCmd);
649b3b8c 7254 break;
7255 default:
7256 break;
7257 }
7258}
7259
1765f95d
FR		 7260static void rtl_shutdown(struct pci_dev *pdev)
7261{
861ab440 7262 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 7263 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 7264
7265 rtl8169_net_suspend(dev);
1765f95d 7266
cecb5fd7 7267 /* Restore original MAC address */
cc098dc7
IV		 7268 rtl_rar_set(tp, dev->perm_addr);
7269
92fc43b4 7270 rtl8169_hw_reset(tp);
4bb3f522 7271
861ab440 7272 if (system_state == SYSTEM_POWER_OFF) {
433f9d0d 7273 if (tp->saved_wolopts) {
649b3b8c 7274 rtl_wol_suspend_quirk(tp);
7275 rtl_wol_shutdown_quirk(tp);
ca52efd5 7276 }
7277
861ab440
RW		 7278 pci_wake_from_d3(pdev, true);
7279 pci_set_power_state(pdev, PCI_D3hot);
7280 }
7281}
5d06a99f 7282
baf63293 7283static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 7284{
7285 struct net_device *dev = pci_get_drvdata(pdev);
7286 struct rtl8169_private *tp = netdev_priv(dev);
7287
9dbe7896 7288 if (r8168_check_dash(tp))
e27566ed 7289 rtl8168_driver_stop(tp);
e27566ed 7290
ad1be8d3
DN		 7291 netif_napi_del(&tp->napi);
7292
e27566ed 7293 unregister_netdev(dev);
f1e911d5 7294 mdiobus_unregister(tp->mii_bus);
e27566ed
FR		 7295
7296 rtl_release_firmware(tp);
7297
7298 if (pci_dev_run_wake(pdev))
7299 pm_runtime_get_noresume(&pdev->dev);
7300
7301 /* restore original MAC address */
7302 rtl_rar_set(tp, dev->perm_addr);
e27566ed
FR		 7303}
7304
fa9c385e 7305static const struct net_device_ops rtl_netdev_ops = {
df43ac78 7306 .ndo_open = rtl_open,
fa9c385e
FR		 7307 .ndo_stop = rtl8169_close,
7308 .ndo_get_stats64 = rtl8169_get_stats64,
7309 .ndo_start_xmit = rtl8169_start_xmit,
7310 .ndo_tx_timeout = rtl8169_tx_timeout,
7311 .ndo_validate_addr = eth_validate_addr,
7312 .ndo_change_mtu = rtl8169_change_mtu,
7313 .ndo_fix_features = rtl8169_fix_features,
7314 .ndo_set_features = rtl8169_set_features,
7315 .ndo_set_mac_address = rtl_set_mac_address,
7316 .ndo_do_ioctl = rtl8169_ioctl,
7317 .ndo_set_rx_mode = rtl_set_rx_mode,
7318#ifdef CONFIG_NET_POLL_CONTROLLER
7319 .ndo_poll_controller = rtl8169_netpoll,
7320#endif
7321
7322};
7323
31fa8b18 7324static const struct rtl_cfg_info {
61cb532d 7325 void (*hw_start)(struct rtl8169_private *tp);
31fa8b18 7326 u16 event_slow;
14967f94 7327 unsigned int has_gmii:1;
50970831 7328 const struct rtl_coalesce_info *coalesce_info;
31fa8b18
FR		 7329 u8 default_ver;
7330} rtl_cfg_infos [] = {
7331 [RTL_CFG_0] = {
7332 .hw_start = rtl_hw_start_8169,
31fa8b18 7333 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
14967f94 7334 .has_gmii = 1,
50970831 7335 .coalesce_info = rtl_coalesce_info_8169,
31fa8b18
FR		 7336 .default_ver = RTL_GIGA_MAC_VER_01,
7337 },
7338 [RTL_CFG_1] = {
7339 .hw_start = rtl_hw_start_8168,
31fa8b18 7340 .event_slow = SYSErr | LinkChg | RxOverflow,
14967f94 7341 .has_gmii = 1,
50970831 7342 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 7343 .default_ver = RTL_GIGA_MAC_VER_11,
7344 },
7345 [RTL_CFG_2] = {
7346 .hw_start = rtl_hw_start_8101,
31fa8b18
FR		 7347 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7348 PCSTimeout,
50970831 7349 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 7350 .default_ver = RTL_GIGA_MAC_VER_13,
7351 }
7352};
7353
6c6aa15f 7354static int rtl_alloc_irq(struct rtl8169_private *tp)
31fa8b18 7355{
6c6aa15f 7356 unsigned int flags;
31fa8b18 7357
6c6aa15f 7358 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1ef7286e
AS		 7359 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7360 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7361 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6c6aa15f
HK		 7362 flags = PCI_IRQ_LEGACY;
7363 } else {
7364 flags = PCI_IRQ_ALL_TYPES;
31fa8b18 7365 }
6c6aa15f
HK		 7366
7367 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
31fa8b18
FR		 7368}
7369
c558386b
HW		 7370DECLARE_RTL_COND(rtl_link_list_ready_cond)
7371{
1ef7286e 7372 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
c558386b
HW		 7373}
7374
7375DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7376{
1ef7286e 7377 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
c558386b
HW		 7378}
7379
f1e911d5
HK		 7380static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7381{
7382 struct rtl8169_private *tp = mii_bus->priv;
7383
7384 if (phyaddr > 0)
7385 return -ENODEV;
7386
7387 return rtl_readphy(tp, phyreg);
7388}
7389
7390static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7391 int phyreg, u16 val)
7392{
7393 struct rtl8169_private *tp = mii_bus->priv;
7394
7395 if (phyaddr > 0)
7396 return -ENODEV;
7397
7398 rtl_writephy(tp, phyreg, val);
7399
7400 return 0;
7401}
7402
7403static int r8169_mdio_register(struct rtl8169_private *tp)
7404{
7405 struct pci_dev *pdev = tp->pci_dev;
7406 struct phy_device *phydev;
7407 struct mii_bus *new_bus;
7408 int ret;
7409
7410 new_bus = devm_mdiobus_alloc(&pdev->dev);
7411 if (!new_bus)
7412 return -ENOMEM;
7413
7414 new_bus->name = "r8169";
7415 new_bus->priv = tp;
7416 new_bus->parent = &pdev->dev;
7417 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7418 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7419 PCI_DEVID(pdev->bus->number, pdev->devfn));
7420
7421 new_bus->read = r8169_mdio_read_reg;
7422 new_bus->write = r8169_mdio_write_reg;
7423
7424 ret = mdiobus_register(new_bus);
7425 if (ret)
7426 return ret;
7427
7428 phydev = mdiobus_get_phy(new_bus, 0);
7429 if (!phydev) {
7430 mdiobus_unregister(new_bus);
7431 return -ENODEV;
7432 }
7433
242cd9b5
HK		 7434 /* PHY will be woken up in rtl_open() */
7435 phy_suspend(phydev);
7436
f1e911d5
HK		 7437 tp->mii_bus = new_bus;
7438
7439 return 0;
7440}
7441
baf63293 7442static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b 7443{
c558386b
HW		 7444 u32 data;
7445
7446 tp->ocp_base = OCP_STD_PHY_BASE;
7447
1ef7286e 7448 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
c558386b
HW		 7449
7450 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7451 return;
7452
7453 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7454 return;
7455
1ef7286e 7456 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
c558386b 7457 msleep(1);
1ef7286e 7458 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
c558386b 7459
5f8bcce9 7460 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7461 data &= ~(1 << 14);
7462 r8168_mac_ocp_write(tp, 0xe8de, data);
7463
7464 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7465 return;
7466
5f8bcce9 7467 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7468 data |= (1 << 15);
7469 r8168_mac_ocp_write(tp, 0xe8de, data);
7470
7471 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7472 return;
7473}
7474
003609da
CHL		 7475static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7476{
7477 rtl8168ep_stop_cmac(tp);
7478 rtl_hw_init_8168g(tp);
7479}
7480
baf63293 7481static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 7482{
7483 switch (tp->mac_version) {
2a71883c 7484 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
003609da
CHL		 7485 rtl_hw_init_8168g(tp);
7486 break;
2a71883c 7487 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
003609da 7488 rtl_hw_init_8168ep(tp);
c558386b 7489 break;
c558386b
HW		 7490 default:
7491 break;
7492 }
7493}
7494
929a031d 7495static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 7496{
7497 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3b6cf25d
FR		 7498 struct rtl8169_private *tp;
7499 struct mii_if_info *mii;
7500 struct net_device *dev;
c8d48d9c 7501 int chipset, region, i;
3b6cf25d
FR		 7502 int rc;
7503
7504 if (netif_msg_drv(&debug)) {
7505 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
7506 MODULENAME, RTL8169_VERSION);
7507 }
7508
4c45d24a
HK		 7509 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7510 if (!dev)
7511 return -ENOMEM;
3b6cf25d
FR		 7512
7513 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 7514 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 7515 tp = netdev_priv(dev);
7516 tp->dev = dev;
7517 tp->pci_dev = pdev;
7518 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7519
7520 mii = &tp->mii;
7521 mii->dev = dev;
7522 mii->mdio_read = rtl_mdio_read;
7523 mii->mdio_write = rtl_mdio_write;
7524 mii->phy_id_mask = 0x1f;
7525 mii->reg_num_mask = 0x1f;
14967f94 7526 mii->supports_gmii = cfg->has_gmii;
3b6cf25d 7527
3b6cf25d 7528 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4c45d24a 7529 rc = pcim_enable_device(pdev);
3b6cf25d 7530 if (rc < 0) {
22148df0 7531 dev_err(&pdev->dev, "enable failure\n");
4c45d24a 7532 return rc;
3b6cf25d
FR		 7533 }
7534
4c45d24a 7535 if (pcim_set_mwi(pdev) < 0)
22148df0 7536 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
3b6cf25d 7537
c8d48d9c
HK		 7538 /* use first MMIO region */
7539 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7540 if (region < 0) {
22148df0 7541 dev_err(&pdev->dev, "no MMIO resource found\n");
4c45d24a 7542 return -ENODEV;
3b6cf25d
FR		 7543 }
7544
7545 /* check for weird/broken PCI region reporting */
7546 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
22148df0 7547 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
4c45d24a 7548 return -ENODEV;
3b6cf25d
FR		 7549 }
7550
93a00d4d 7551 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
3b6cf25d 7552 if (rc < 0) {
22148df0 7553 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
4c45d24a 7554 return rc;
3b6cf25d
FR		 7555 }
7556
93a00d4d 7557 tp->mmio_addr = pcim_iomap_table(pdev)[region];
3b6cf25d
FR		 7558
7559 if (!pci_is_pcie(pdev))
22148df0 7560 dev_info(&pdev->dev, "not PCI Express\n");
3b6cf25d
FR		 7561
7562 /* Identify chip attached to board */
22148df0 7563 rtl8169_get_mac_version(tp, cfg->default_ver);
3b6cf25d 7564
e397286b
HK		 7565 if (rtl_tbi_enabled(tp)) {
7566 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7567 return -ENODEV;
7568 }
7569
0ae0974e 7570 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
27896c83
AB		 7571
7572 if ((sizeof(dma_addr_t) > 4) &&
7573 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7574 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
f0076436
AB		 7575 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7576 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
27896c83
AB		 7577
7578 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7579 if (!pci_is_pcie(pdev))
7580 tp->cp_cmd |= PCIDAC;
7581 dev->features |= NETIF_F_HIGHDMA;
7582 } else {
7583 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7584 if (rc < 0) {
22148df0 7585 dev_err(&pdev->dev, "DMA configuration failed\n");
4c45d24a 7586 return rc;
27896c83
AB		 7587 }
7588 }
7589
3b6cf25d
FR		 7590 rtl_init_rxcfg(tp);
7591
7592 rtl_irq_disable(tp);
7593
c558386b
HW		 7594 rtl_hw_initialize(tp);
7595
3b6cf25d
FR		 7596 rtl_hw_reset(tp);
7597
7598 rtl_ack_events(tp, 0xffff);
7599
7600 pci_set_master(pdev);
7601
3b6cf25d 7602 rtl_init_mdio_ops(tp);
3b6cf25d
FR		 7603 rtl_init_jumbo_ops(tp);
7604
7605 rtl8169_print_mac_version(tp);
7606
7607 chipset = tp->mac_version;
3b6cf25d 7608
6c6aa15f
HK		 7609 rc = rtl_alloc_irq(tp);
7610 if (rc < 0) {
22148df0 7611 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6c6aa15f
HK		 7612 return rc;
7613 }
3b6cf25d 7614
7edf6d31
HK		 7615 /* override BIOS settings, use userspace tools to enable WOL */
7616 __rtl8169_set_wol(tp, 0);
7617
3b6cf25d 7618 mutex_init(&tp->wk.mutex);
340fea3d
KM		 7619 u64_stats_init(&tp->rx_stats.syncp);
7620 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 7621
7622 /* Get MAC address */
b2d43e6e 7623 switch (tp->mac_version) {
353af85e 7624 u8 mac_addr[ETH_ALEN] __aligned(4);
b2d43e6e
HK		 7625 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7626 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
05b9687b 7627 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
353af85e 7628 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89 7629
353af85e
HK		 7630 if (is_valid_ether_addr(mac_addr))
7631 rtl_rar_set(tp, mac_addr);
b2d43e6e
HK		 7632 break;
7633 default:
7634 break;
6e1d0b89 7635 }
3b6cf25d 7636 for (i = 0; i < ETH_ALEN; i++)
1ef7286e 7637 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
3b6cf25d 7638
7ad24ea4 7639 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 7640 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d 7641
37621493 7642 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
3b6cf25d
FR		 7643
7644 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7645 * properly for all devices */
7646 dev->features |= NETIF_F_RXCSUM |
f646968f 7647 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7648
7649 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 7650 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7651 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7652 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7653 NETIF_F_HIGHDMA;
7654
929a031d 7655 tp->cp_cmd |= RxChkSum | RxVlan;
7656
7657 /*
7658 * Pretend we are using VLANs; This bypasses a nasty bug where
7659 * Interrupts stop flowing on high load on 8110SCd controllers.
7660 */
3b6cf25d 7661 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 7662 /* Disallow toggling */
f646968f 7663 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 7664
a4328ddb
HK		 7665 switch (rtl_chip_infos[chipset].txd_version) {
7666 case RTL_TD_0:
5888d3fc 7667 tp->tso_csum = rtl8169_tso_csum_v1;
a4328ddb
HK		 7668 break;
7669 case RTL_TD_1:
5888d3fc 7670 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 7671 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
a4328ddb
HK		 7672 break;
7673 default:
5888d3fc 7674 WARN_ON_ONCE(1);
a4328ddb 7675 }
5888d3fc 7676
3b6cf25d
FR		 7677 dev->hw_features |= NETIF_F_RXALL;
7678 dev->hw_features |= NETIF_F_RXFCS;
7679
c7315a95
JW		 7680 /* MTU range: 60 - hw-specific max */
7681 dev->min_mtu = ETH_ZLEN;
7682 dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
7683
3b6cf25d
FR		 7684 tp->hw_start = cfg->hw_start;
7685 tp->event_slow = cfg->event_slow;
50970831 7686 tp->coalesce_info = cfg->coalesce_info;
3b6cf25d 7687
3b6cf25d
FR		 7688 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7689
4c45d24a
HK		 7690 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7691 &tp->counters_phys_addr,
7692 GFP_KERNEL);
4cf964af
HK		 7693 if (!tp->counters)
7694 return -ENOMEM;
42020320 7695
19c9ea36
HK		 7696 pci_set_drvdata(pdev, dev);
7697
f1e911d5
HK		 7698 rc = r8169_mdio_register(tp);
7699 if (rc)
4cf964af 7700 return rc;
3b6cf25d 7701
f1e911d5
HK		 7702 rc = register_netdev(dev);
7703 if (rc)
7704 goto err_mdio_unregister;
7705
2d6c5a61
HK		 7706 netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7707 rtl_chip_infos[chipset].name, dev->dev_addr,
90b989c5 7708 (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
29274991 7709 pci_irq_vector(pdev, 0));
3b6cf25d
FR		 7710 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7711 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7712 "tx checksumming: %s]\n",
7713 rtl_chip_infos[chipset].jumbo_max,
6ed0e08f 7714 tp->mac_version <= RTL_GIGA_MAC_VER_06 ? "ok" : "ko");
3b6cf25d
FR		 7715 }
7716
9dbe7896 7717 if (r8168_check_dash(tp))
3b6cf25d 7718 rtl8168_driver_start(tp);
3b6cf25d 7719
a92a0849
HK		 7720 if (pci_dev_run_wake(pdev))
7721 pm_runtime_put_sync(&pdev->dev);
7722
4c45d24a 7723 return 0;
f1e911d5
HK		 7724
7725err_mdio_unregister:
7726 mdiobus_unregister(tp->mii_bus);
7727 return rc;
3b6cf25d
FR		 7728}
7729
1da177e4
LT		 7730static struct pci_driver rtl8169_pci_driver = {
7731 .name = MODULENAME,
7732 .id_table = rtl8169_pci_tbl,
3b6cf25d 7733 .probe = rtl_init_one,
baf63293 7734 .remove = rtl_remove_one,
1765f95d 7735 .shutdown = rtl_shutdown,
861ab440 7736 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7737};
7738
3eeb7da9 7739module_pci_driver(rtl8169_pci_driver);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git