]> git.ipfire.org Git - thirdparty/kernel/stable.git/blame - drivers/net/ethernet/realtek/r8169.c
projects / thirdparty / kernel / stable.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'tun-races'
[thirdparty/kernel/stable.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
c2f6f3ee 16#include <linux/clk.h>
1da177e4
LT		 17#include <linux/delay.h>
18#include <linux/ethtool.h>
f1e911d5 19#include <linux/phy.h>
1da177e4
LT		 20#include <linux/if_vlan.h>
21#include <linux/crc32.h>
22#include <linux/in.h>
098b01ad 23#include <linux/io.h>
1da177e4
LT		 24#include <linux/ip.h>
25#include <linux/tcp.h>
a6b7a407 26#include <linux/interrupt.h>
1da177e4 27#include <linux/dma-mapping.h>
e1759441 28#include <linux/pm_runtime.h>
bca03d5f 29#include <linux/firmware.h>
70c71606 30#include <linux/prefetch.h>
e974604b 31#include <linux/ipv6.h>
32#include <net/ip6_checksum.h>
1da177e4 33
1da177e4 34#define MODULENAME "r8169"
1da177e4 35
bca03d5f 36#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
37#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 38#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
39#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 40#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 41#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
42#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 43#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 44#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 45#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 46#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 47#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 48#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 49#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 50#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 51#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
52#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
53#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
54#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 55
b57b7e5a 56#define R8169_MSG_DEFAULT \
f0e837d9 57 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 58
477206a0
JD		 59#define TX_SLOTS_AVAIL(tp) \
60 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
61
62/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
63#define TX_FRAGS_READY_FOR(tp,nr_frags) \
64 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 65
1da177e4
LT		 66/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 68static const int multicast_filter_limit = 32;
1da177e4 69
aee77e4a 70#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
1d0254dd 74#define R8169_RX_BUF_SIZE (SZ_16K - 1)
1da177e4 75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 76#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 77#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
78#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
79
80#define RTL8169_TX_TIMEOUT (6*HZ)
1da177e4
LT		 81
82/* write/read MMIO register */
1ef7286e
AS		 83#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
84#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
85#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
86#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
87#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
88#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
1da177e4
LT		 89
90enum mac_version {
85bffe6c
FR		 91 RTL_GIGA_MAC_VER_01 = 0,
92 RTL_GIGA_MAC_VER_02,
93 RTL_GIGA_MAC_VER_03,
94 RTL_GIGA_MAC_VER_04,
95 RTL_GIGA_MAC_VER_05,
96 RTL_GIGA_MAC_VER_06,
97 RTL_GIGA_MAC_VER_07,
98 RTL_GIGA_MAC_VER_08,
99 RTL_GIGA_MAC_VER_09,
100 RTL_GIGA_MAC_VER_10,
101 RTL_GIGA_MAC_VER_11,
102 RTL_GIGA_MAC_VER_12,
103 RTL_GIGA_MAC_VER_13,
104 RTL_GIGA_MAC_VER_14,
105 RTL_GIGA_MAC_VER_15,
106 RTL_GIGA_MAC_VER_16,
107 RTL_GIGA_MAC_VER_17,
108 RTL_GIGA_MAC_VER_18,
109 RTL_GIGA_MAC_VER_19,
110 RTL_GIGA_MAC_VER_20,
111 RTL_GIGA_MAC_VER_21,
112 RTL_GIGA_MAC_VER_22,
113 RTL_GIGA_MAC_VER_23,
114 RTL_GIGA_MAC_VER_24,
115 RTL_GIGA_MAC_VER_25,
116 RTL_GIGA_MAC_VER_26,
117 RTL_GIGA_MAC_VER_27,
118 RTL_GIGA_MAC_VER_28,
119 RTL_GIGA_MAC_VER_29,
120 RTL_GIGA_MAC_VER_30,
121 RTL_GIGA_MAC_VER_31,
122 RTL_GIGA_MAC_VER_32,
123 RTL_GIGA_MAC_VER_33,
70090424 124 RTL_GIGA_MAC_VER_34,
c2218925
HW		 125 RTL_GIGA_MAC_VER_35,
126 RTL_GIGA_MAC_VER_36,
7e18dca1 127 RTL_GIGA_MAC_VER_37,
b3d7b2f2 128 RTL_GIGA_MAC_VER_38,
5598bfe5 129 RTL_GIGA_MAC_VER_39,
c558386b
HW		 130 RTL_GIGA_MAC_VER_40,
131 RTL_GIGA_MAC_VER_41,
57538c4a 132 RTL_GIGA_MAC_VER_42,
58152cd4 133 RTL_GIGA_MAC_VER_43,
45dd95c4 134 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 135 RTL_GIGA_MAC_VER_45,
136 RTL_GIGA_MAC_VER_46,
137 RTL_GIGA_MAC_VER_47,
138 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 139 RTL_GIGA_MAC_VER_49,
140 RTL_GIGA_MAC_VER_50,
141 RTL_GIGA_MAC_VER_51,
85bffe6c 142 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 143};
144
d58d46b5
FR		 145#define JUMBO_1K ETH_DATA_LEN
146#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
147#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
148#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
149#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
150
3c6bee1d 151static const struct {
1da177e4 152 const char *name;
953a12cc 153 const char *fw_name;
85bffe6c
FR		 154} rtl_chip_infos[] = {
155 /* PCI devices. */
abe8b2f7
HK		 156 [RTL_GIGA_MAC_VER_01] = {"RTL8169" },
157 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
158 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
159 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
160 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
161 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
85bffe6c 162 /* PCI-E devices. */
abe8b2f7
HK		 163 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
164 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
165 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
166 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
167 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
168 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
169 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
170 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
171 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
172 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
173 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
174 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
175 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
176 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
177 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
178 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
179 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
180 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
181 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
182 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
183 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
184 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
185 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
186 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
187 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
188 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
189 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
190 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
191 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
192 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
193 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
194 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
195 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
196 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
197 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
198 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
199 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
200 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
201 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
202 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
203 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
204 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
205 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
206 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
207 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
953a12cc
FR		 208};
209
bcf0bf90
FR		 210enum cfg_version {
211 RTL_CFG_0 = 0x00,
212 RTL_CFG_1,
213 RTL_CFG_2
214};
215
9baa3c34 216static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 217 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 218 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
610c9087 219 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
d81bf551 220 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 221 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
9fd0e09a 222 { PCI_DEVICE(PCI_VENDOR_ID_NCUBE, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 223 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 224 { PCI_VENDOR_ID_DLINK, 0x4300,
225 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 226 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 227 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 228 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 229 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
230 { PCI_VENDOR_ID_LINKSYS, 0x1032,
231 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 232 { 0x0001, 0x8168,
233 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 234 {0,},
235};
236
237MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
238
27896c83 239static int use_dac = -1;
b57b7e5a
SH		 240static struct {
241 u32 msg_enable;
242} debug = { -1 };
1da177e4 243
07d3f51f
FR		 244enum rtl_registers {
245 MAC0 = 0, /* Ethernet hardware address. */
773d2021 246 MAC4 = 4,
07d3f51f
FR		 247 MAR0 = 8, /* Multicast filter. */
248 CounterAddrLow = 0x10,
249 CounterAddrHigh = 0x14,
250 TxDescStartAddrLow = 0x20,
251 TxDescStartAddrHigh = 0x24,
252 TxHDescStartAddrLow = 0x28,
253 TxHDescStartAddrHigh = 0x2c,
254 FLASH = 0x30,
255 ERSR = 0x36,
256 ChipCmd = 0x37,
257 TxPoll = 0x38,
258 IntrMask = 0x3c,
259 IntrStatus = 0x3e,
4f6b00e5 260
07d3f51f 261 TxConfig = 0x40,
4f6b00e5
HW		 262#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
263#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 264
4f6b00e5
HW		 265 RxConfig = 0x44,
266#define RX128_INT_EN (1 << 15) /* 8111c and later */
267#define RX_MULTI_EN (1 << 14) /* 8111c only */
268#define RXCFG_FIFO_SHIFT 13
269 /* No threshold before first PCI xfer */
270#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 271#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 272#define RXCFG_DMA_SHIFT 8
273 /* Unlimited maximum PCI burst. */
274#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 275
07d3f51f
FR		 276 RxMissed = 0x4c,
277 Cfg9346 = 0x50,
278 Config0 = 0x51,
279 Config1 = 0x52,
280 Config2 = 0x53,
d387b427
FR		 281#define PME_SIGNAL (1 << 5) /* 8168c and later */
282
07d3f51f
FR		 283 Config3 = 0x54,
284 Config4 = 0x55,
285 Config5 = 0x56,
286 MultiIntr = 0x5c,
287 PHYAR = 0x60,
07d3f51f
FR		 288 PHYstatus = 0x6c,
289 RxMaxSize = 0xda,
290 CPlusCmd = 0xe0,
291 IntrMitigate = 0xe2,
50970831
FR		 292
293#define RTL_COALESCE_MASK 0x0f
294#define RTL_COALESCE_SHIFT 4
295#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
296#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
297
07d3f51f
FR		 298 RxDescAddrLow = 0xe4,
299 RxDescAddrHigh = 0xe8,
f0298f81 300 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
301
302#define NoEarlyTx 0x3f /* Max value : no early transmit. */
303
304 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
305
306#define TxPacketMax (8064 >> 7)
3090bd9a 307#define EarlySize 0x27
f0298f81 308
07d3f51f
FR		 309 FuncEvent = 0xf0,
310 FuncEventMask = 0xf4,
311 FuncPresetState = 0xf8,
935e2218
CHL		 312 IBCR0 = 0xf8,
313 IBCR2 = 0xf9,
314 IBIMR0 = 0xfa,
315 IBISR0 = 0xfb,
07d3f51f 316 FuncForceEvent = 0xfc,
1da177e4
LT		 317};
318
f162a5d1
FR		 319enum rtl8168_8101_registers {
320 CSIDR = 0x64,
321 CSIAR = 0x68,
322#define CSIAR_FLAG 0x80000000
323#define CSIAR_WRITE_CMD 0x80000000
ff1d7331
HK		 324#define CSIAR_BYTE_ENABLE 0x0000f000
325#define CSIAR_ADDR_MASK 0x00000fff
065c27c1 326 PMCH = 0x6f,
f162a5d1
FR		 327 EPHYAR = 0x80,
328#define EPHYAR_FLAG 0x80000000
329#define EPHYAR_WRITE_CMD 0x80000000
330#define EPHYAR_REG_MASK 0x1f
331#define EPHYAR_REG_SHIFT 16
332#define EPHYAR_DATA_MASK 0xffff
5a5e4443 333 DLLPR = 0xd0,
4f6b00e5 334#define PFM_EN (1 << 6)
6e1d0b89 335#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 336 DBG_REG = 0xd1,
337#define FIX_NAK_1 (1 << 4)
338#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 339 TWSI = 0xd2,
340 MCU = 0xd3,
4f6b00e5 341#define NOW_IS_OOB (1 << 7)
c558386b
HW		 342#define TX_EMPTY (1 << 5)
343#define RX_EMPTY (1 << 4)
344#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 345#define EN_NDP (1 << 3)
346#define EN_OOB_RESET (1 << 2)
c558386b 347#define LINK_LIST_RDY (1 << 1)
daf9df6d 348 EFUSEAR = 0xdc,
349#define EFUSEAR_FLAG 0x80000000
350#define EFUSEAR_WRITE_CMD 0x80000000
351#define EFUSEAR_READ_CMD 0x00000000
352#define EFUSEAR_REG_MASK 0x03ff
353#define EFUSEAR_REG_SHIFT 8
354#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 355 MISC_1 = 0xf2,
356#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 357};
358
c0e45c1c 359enum rtl8168_registers {
4f6b00e5
HW		 360 LED_FREQ = 0x1a,
361 EEE_LED = 0x1b,
b646d900 362 ERIDR = 0x70,
363 ERIAR = 0x74,
364#define ERIAR_FLAG 0x80000000
365#define ERIAR_WRITE_CMD 0x80000000
366#define ERIAR_READ_CMD 0x00000000
367#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 368#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 369#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
370#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
371#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 372#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 373#define ERIAR_MASK_SHIFT 12
374#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
375#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 376#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 377#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 378#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 379 EPHY_RXER_NUM = 0x7c,
380 OCPDR = 0xb0, /* OCP GPHY access */
381#define OCPDR_WRITE_CMD 0x80000000
382#define OCPDR_READ_CMD 0x00000000
383#define OCPDR_REG_MASK 0x7f
384#define OCPDR_GPHY_REG_SHIFT 16
385#define OCPDR_DATA_MASK 0xffff
386 OCPAR = 0xb4,
387#define OCPAR_FLAG 0x80000000
388#define OCPAR_GPHY_WRITE_CMD 0x8000f060
389#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 390 GPHY_OCP = 0xb8,
01dc7fec 391 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
392 MISC = 0xf0, /* 8168e only. */
cecb5fd7 393#define TXPLA_RST (1 << 29)
5598bfe5 394#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 395#define PWM_EN (1 << 22)
c558386b 396#define RXDV_GATED_EN (1 << 19)
5598bfe5 397#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 398};
399
07d3f51f 400enum rtl_register_content {
1da177e4 401 /* InterruptStatusBits */
07d3f51f
FR		 402 SYSErr = 0x8000,
403 PCSTimeout = 0x4000,
404 SWInt = 0x0100,
405 TxDescUnavail = 0x0080,
406 RxFIFOOver = 0x0040,
407 LinkChg = 0x0020,
408 RxOverflow = 0x0010,
409 TxErr = 0x0008,
410 TxOK = 0x0004,
411 RxErr = 0x0002,
412 RxOK = 0x0001,
1da177e4
LT		 413
414 /* RxStatusDesc */
e03f33af 415 RxBOVF = (1 << 24),
9dccf611
FR		 416 RxFOVF = (1 << 23),
417 RxRWT = (1 << 22),
418 RxRES = (1 << 21),
419 RxRUNT = (1 << 20),
420 RxCRC = (1 << 19),
1da177e4
LT		 421
422 /* ChipCmdBits */
4f6b00e5 423 StopReq = 0x80,
07d3f51f
FR		 424 CmdReset = 0x10,
425 CmdRxEnb = 0x08,
426 CmdTxEnb = 0x04,
427 RxBufEmpty = 0x01,
1da177e4 428
275391a4
FR		 429 /* TXPoll register p.5 */
430 HPQ = 0x80, /* Poll cmd on the high prio queue */
431 NPQ = 0x40, /* Poll cmd on the low prio queue */
432 FSWInt = 0x01, /* Forced software interrupt */
433
1da177e4 434 /* Cfg9346Bits */
07d3f51f
FR		 435 Cfg9346_Lock = 0x00,
436 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 437
438 /* rx_mode_bits */
07d3f51f
FR		 439 AcceptErr = 0x20,
440 AcceptRunt = 0x10,
441 AcceptBroadcast = 0x08,
442 AcceptMulticast = 0x04,
443 AcceptMyPhys = 0x02,
444 AcceptAllPhys = 0x01,
1687b566 445#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 446
1da177e4
LT		 447 /* TxConfigBits */
448 TxInterFrameGapShift = 24,
449 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
450
5d06a99f 451 /* Config1 register p.24 */
f162a5d1
FR		 452 LEDS1 = (1 << 7),
453 LEDS0 = (1 << 6),
f162a5d1
FR		 454 Speed_down = (1 << 4),
455 MEMMAP = (1 << 3),
456 IOMAP = (1 << 2),
457 VPD = (1 << 1),
5d06a99f
FR		 458 PMEnable = (1 << 0), /* Power Management Enable */
459
6dccd16b 460 /* Config2 register p. 25 */
57538c4a 461 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 462 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 463 PCI_Clock_66MHz = 0x01,
464 PCI_Clock_33MHz = 0x00,
465
61a4dcc2
FR		 466 /* Config3 register p.25 */
467 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
468 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 469 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 470 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 471 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 472
d58d46b5
FR		 473 /* Config4 register */
474 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
475
5d06a99f 476 /* Config5 register p.27 */
61a4dcc2
FR		 477 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
478 MWF = (1 << 5), /* Accept Multicast wakeup frame */
479 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 480 Spi_en = (1 << 3),
61a4dcc2 481 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 482 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 483 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 484
1da177e4 485 /* CPlusCmd p.31 */
f162a5d1
FR		 486 EnableBist = (1 << 15), // 8168 8101
487 Mac_dbgo_oe = (1 << 14), // 8168 8101
488 Normal_mode = (1 << 13), // unused
489 Force_half_dup = (1 << 12), // 8168 8101
490 Force_rxflow_en = (1 << 11), // 8168 8101
491 Force_txflow_en = (1 << 10), // 8168 8101
492 Cxpl_dbg_sel = (1 << 9), // 8168 8101
493 ASF = (1 << 8), // 8168 8101
494 PktCntrDisable = (1 << 7), // 8168 8101
495 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 496 RxVlan = (1 << 6),
497 RxChkSum = (1 << 5),
498 PCIDAC = (1 << 4),
499 PCIMulRW = (1 << 3),
9a3c81fa 500#define INTT_MASK GENMASK(1, 0)
0e485150
FR		 501 INTT_0 = 0x0000, // 8168
502 INTT_1 = 0x0001, // 8168
503 INTT_2 = 0x0002, // 8168
504 INTT_3 = 0x0003, // 8168
1da177e4
LT		 505
506 /* rtl8169_PHYstatus */
07d3f51f
FR		 507 TBI_Enable = 0x80,
508 TxFlowCtrl = 0x40,
509 RxFlowCtrl = 0x20,
510 _1000bpsF = 0x10,
511 _100bps = 0x08,
512 _10bps = 0x04,
513 LinkStatus = 0x02,
514 FullDup = 0x01,
1da177e4 515
1da177e4 516 /* _TBICSRBit */
07d3f51f 517 TBILinkOK = 0x02000000,
d4a3a0fc 518
6e85d5ad
CV		 519 /* ResetCounterCommand */
520 CounterReset = 0x1,
521
d4a3a0fc 522 /* DumpCounterCommand */
07d3f51f 523 CounterDump = 0x8,
6e1d0b89
CHL		 524
525 /* magic enable v2 */
526 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 527};
528
2b7b4318
FR		 529enum rtl_desc_bit {
530 /* First doubleword. */
1da177e4
LT		 531 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
532 RingEnd = (1 << 30), /* End of descriptor ring */
533 FirstFrag = (1 << 29), /* First segment of a packet */
534 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 535};
536
537/* Generic case. */
538enum rtl_tx_desc_bit {
539 /* First doubleword. */
540 TD_LSO = (1 << 27), /* Large Send Offload */
541#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 542
2b7b4318
FR		 543 /* Second doubleword. */
544 TxVlanTag = (1 << 17), /* Add VLAN tag */
545};
546
547/* 8169, 8168b and 810x except 8102e. */
548enum rtl_tx_desc_bit_0 {
549 /* First doubleword. */
550#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
551 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
552 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
553 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
554};
555
556/* 8102e, 8168c and beyond. */
557enum rtl_tx_desc_bit_1 {
bdfa4ed6 558 /* First doubleword. */
559 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 560 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 561#define GTTCPHO_SHIFT 18
e974604b 562#define GTTCPHO_MAX 0x7fU
bdfa4ed6 563
2b7b4318 564 /* Second doubleword. */
e974604b 565#define TCPHO_SHIFT 18
566#define TCPHO_MAX 0x3ffU
2b7b4318 567#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 568 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
569 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 570 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
571 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
572};
1da177e4 573
2b7b4318 574enum rtl_rx_desc_bit {
1da177e4
LT		 575 /* Rx private */
576 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 577 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 578
579#define RxProtoUDP (PID1)
580#define RxProtoTCP (PID0)
581#define RxProtoIP (PID1 | PID0)
582#define RxProtoMask RxProtoIP
583
584 IPFail = (1 << 16), /* IP checksum failed */
585 UDPFail = (1 << 15), /* UDP/IP checksum failed */
586 TCPFail = (1 << 14), /* TCP/IP checksum failed */
587 RxVlanTag = (1 << 16), /* VLAN tag available */
588};
589
590#define RsvdMask 0x3fffc000
12d42c50 591#define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
1da177e4
LT		 592
593struct TxDesc {
6cccd6e7
REB		 594 __le32 opts1;
595 __le32 opts2;
596 __le64 addr;
1da177e4
LT		 597};
598
599struct RxDesc {
6cccd6e7
REB		 600 __le32 opts1;
601 __le32 opts2;
602 __le64 addr;
1da177e4
LT		 603};
604
605struct ring_info {
606 struct sk_buff *skb;
607 u32 len;
608 u8 __pad[sizeof(void *) - sizeof(u32)];
609};
610
355423d0
IV		 611struct rtl8169_counters {
612 __le64 tx_packets;
613 __le64 rx_packets;
614 __le64 tx_errors;
615 __le32 rx_errors;
616 __le16 rx_missed;
617 __le16 align_errors;
618 __le32 tx_one_collision;
619 __le32 tx_multi_collision;
620 __le64 rx_unicast;
621 __le64 rx_broadcast;
622 __le32 rx_multicast;
623 __le16 tx_aborted;
624 __le16 tx_underun;
625};
626
6e85d5ad
CV		 627struct rtl8169_tc_offsets {
628 bool inited;
629 __le64 tx_errors;
630 __le32 tx_multi_collision;
6e85d5ad
CV		 631 __le16 tx_aborted;
632};
633
da78dbff 634enum rtl_flag {
6ad56901 635 RTL_FLAG_TASK_ENABLED = 0,
da78dbff
FR		 636 RTL_FLAG_TASK_SLOW_PENDING,
637 RTL_FLAG_TASK_RESET_PENDING,
da78dbff
FR		 638 RTL_FLAG_MAX
639};
640
8027aa24
JW		 641struct rtl8169_stats {
642 u64 packets;
643 u64 bytes;
644 struct u64_stats_sync syncp;
645};
646
1da177e4
LT		 647struct rtl8169_private {
648 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 649 struct pci_dev *pci_dev;
c4028958 650 struct net_device *dev;
bea3348e 651 struct napi_struct napi;
b57b7e5a 652 u32 msg_enable;
2b7b4318 653 u16 mac_version;
1da177e4
LT		 654 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
655 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 656 u32 dirty_tx;
8027aa24
JW		 657 struct rtl8169_stats rx_stats;
658 struct rtl8169_stats tx_stats;
1da177e4
LT		 659 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
660 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
661 dma_addr_t TxPhyAddr;
662 dma_addr_t RxPhyAddr;
6f0333b8 663 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 664 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4 665 u16 cp_cmd;
da78dbff
FR		 666
667 u16 event_slow;
50970831 668 const struct rtl_coalesce_info *coalesce_info;
c2f6f3ee 669 struct clk *clk;
c0e45c1c 670
671 struct mdio_ops {
24192210
FR		 672 void (*write)(struct rtl8169_private *, int, int);
673 int (*read)(struct rtl8169_private *, int);
c0e45c1c 674 } mdio_ops;
675
d58d46b5
FR		 676 struct jumbo_ops {
677 void (*enable)(struct rtl8169_private *);
678 void (*disable)(struct rtl8169_private *);
679 } jumbo_ops;
680
61cb532d 681 void (*hw_start)(struct rtl8169_private *tp);
5888d3fc 682 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 683
684 struct {
da78dbff
FR		 685 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
686 struct mutex mutex;
4422bcd4
FR		 687 struct work_struct work;
688 } wk;
689
f7ffa9ae 690 unsigned supports_gmii:1;
f1e911d5 691 struct mii_bus *mii_bus;
42020320
CV		 692 dma_addr_t counters_phys_addr;
693 struct rtl8169_counters *counters;
6e85d5ad 694 struct rtl8169_tc_offsets tc_offset;
e1759441 695 u32 saved_wolopts;
f1e02ed1 696
b6ffd97f
FR		 697 struct rtl_fw {
698 const struct firmware *fw;
1c361efb
FR		 699
700#define RTL_VER_SIZE 32
701
702 char version[RTL_VER_SIZE];
703
704 struct rtl_fw_phy_action {
705 __le32 *code;
706 size_t size;
707 } phy_action;
b6ffd97f 708 } *rtl_fw;
497888cf 709#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 710
711 u32 ocp_base;
1da177e4
LT		 712};
713
979b6c13 714MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 715MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 716module_param(use_dac, int, 0);
4300e8c7 717MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 718module_param_named(debug, debug.msg_enable, int, 0);
719MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4 720MODULE_LICENSE("GPL");
bca03d5f 721MODULE_FIRMWARE(FIRMWARE_8168D_1);
722MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 723MODULE_FIRMWARE(FIRMWARE_8168E_1);
724MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 725MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 726MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 727MODULE_FIRMWARE(FIRMWARE_8168F_1);
728MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 729MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 730MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 731MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 732MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 733MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 734MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 735MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 736MODULE_FIRMWARE(FIRMWARE_8168H_1);
737MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 738MODULE_FIRMWARE(FIRMWARE_8107E_1);
739MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 740
1e1205b7
HK		 741static inline struct device *tp_to_dev(struct rtl8169_private *tp)
742{
743 return &tp->pci_dev->dev;
744}
745
da78dbff
FR		 746static void rtl_lock_work(struct rtl8169_private *tp)
747{
748 mutex_lock(&tp->wk.mutex);
749}
750
751static void rtl_unlock_work(struct rtl8169_private *tp)
752{
753 mutex_unlock(&tp->wk.mutex);
754}
755
cb73200c 756static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
d58d46b5 757{
cb73200c 758 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
7d7903b2 759 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 760}
761
ffc46952
FR		 762struct rtl_cond {
763 bool (*check)(struct rtl8169_private *);
764 const char *msg;
765};
766
767static void rtl_udelay(unsigned int d)
768{
769 udelay(d);
770}
771
772static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
773 void (*delay)(unsigned int), unsigned int d, int n,
774 bool high)
775{
776 int i;
777
778 for (i = 0; i < n; i++) {
779 delay(d);
780 if (c->check(tp) == high)
781 return true;
782 }
82e316ef
FR		 783 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
784 c->msg, !high, n, d);
ffc46952
FR		 785 return false;
786}
787
788static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
789 const struct rtl_cond *c,
790 unsigned int d, int n)
791{
792 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
793}
794
795static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
796 const struct rtl_cond *c,
797 unsigned int d, int n)
798{
799 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
800}
801
802static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
803 const struct rtl_cond *c,
804 unsigned int d, int n)
805{
806 return rtl_loop_wait(tp, c, msleep, d, n, true);
807}
808
809static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
810 const struct rtl_cond *c,
811 unsigned int d, int n)
812{
813 return rtl_loop_wait(tp, c, msleep, d, n, false);
814}
815
816#define DECLARE_RTL_COND(name) \
817static bool name ## _check(struct rtl8169_private *); \
818 \
819static const struct rtl_cond name = { \
820 .check = name ## _check, \
821 .msg = #name \
822}; \
823 \
824static bool name ## _check(struct rtl8169_private *tp)
825
c558386b
HW		 826static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
827{
828 if (reg & 0xffff0001) {
829 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
830 return true;
831 }
832 return false;
833}
834
835DECLARE_RTL_COND(rtl_ocp_gphy_cond)
836{
1ef7286e 837 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
c558386b
HW		 838}
839
840static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
841{
c558386b
HW		 842 if (rtl_ocp_reg_failure(tp, reg))
843 return;
844
1ef7286e 845 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 846
847 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
848}
849
850static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
851{
c558386b
HW		 852 if (rtl_ocp_reg_failure(tp, reg))
853 return 0;
854
1ef7286e 855 RTL_W32(tp, GPHY_OCP, reg << 15);
c558386b
HW		 856
857 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1ef7286e 858 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
c558386b
HW		 859}
860
c558386b
HW		 861static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
862{
c558386b
HW		 863 if (rtl_ocp_reg_failure(tp, reg))
864 return;
865
1ef7286e 866 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 867}
868
869static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
870{
c558386b
HW		 871 if (rtl_ocp_reg_failure(tp, reg))
872 return 0;
873
1ef7286e 874 RTL_W32(tp, OCPDR, reg << 15);
c558386b 875
1ef7286e 876 return RTL_R32(tp, OCPDR);
c558386b
HW		 877}
878
879#define OCP_STD_PHY_BASE 0xa400
880
881static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
882{
883 if (reg == 0x1f) {
884 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
885 return;
886 }
887
888 if (tp->ocp_base != OCP_STD_PHY_BASE)
889 reg -= 0x10;
890
891 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
892}
893
894static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
895{
896 if (tp->ocp_base != OCP_STD_PHY_BASE)
897 reg -= 0x10;
898
899 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
900}
901
eee3786f 902static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
903{
904 if (reg == 0x1f) {
905 tp->ocp_base = value << 4;
906 return;
907 }
908
909 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
910}
911
912static int mac_mcu_read(struct rtl8169_private *tp, int reg)
913{
914 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
915}
916
ffc46952
FR		 917DECLARE_RTL_COND(rtl_phyar_cond)
918{
1ef7286e 919 return RTL_R32(tp, PHYAR) & 0x80000000;
ffc46952
FR		 920}
921
24192210 922static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 923{
1ef7286e 924 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 925
ffc46952 926 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 927 /*
81a95f04
TT		 928 * According to hardware specs a 20us delay is required after write
929 * complete indication, but before sending next command.
024a07ba 930 */
81a95f04 931 udelay(20);
1da177e4
LT		 932}
933
24192210 934static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 935{
ffc46952 936 int value;
1da177e4 937
1ef7286e 938 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 939
ffc46952 940 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1ef7286e 941 RTL_R32(tp, PHYAR) & 0xffff : ~0;
ffc46952 942
81a95f04
TT		 943 /*
944 * According to hardware specs a 20us delay is required after read
945 * complete indication, but before sending next command.
946 */
947 udelay(20);
948
1da177e4
LT		 949 return value;
950}
951
935e2218
CHL		 952DECLARE_RTL_COND(rtl_ocpar_cond)
953{
1ef7286e 954 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
935e2218
CHL		 955}
956
24192210 957static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 958{
1ef7286e
AS		 959 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
960 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
961 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 962
ffc46952 963 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 964}
965
24192210 966static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 967{
24192210
FR		 968 r8168dp_1_mdio_access(tp, reg,
969 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 970}
971
24192210 972static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 973{
24192210 974 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 975
976 mdelay(1);
1ef7286e
AS		 977 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
978 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 979
ffc46952 980 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1ef7286e 981 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 982}
983
e6de30d6 984#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
985
1ef7286e 986static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
e6de30d6 987{
1ef7286e 988 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 989}
990
1ef7286e 991static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
e6de30d6 992{
1ef7286e 993 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 994}
995
24192210 996static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 997{
1ef7286e 998 r8168dp_2_mdio_start(tp);
e6de30d6 999
24192210 1000 r8169_mdio_write(tp, reg, value);
e6de30d6 1001
1ef7286e 1002 r8168dp_2_mdio_stop(tp);
e6de30d6 1003}
1004
24192210 1005static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1006{
1007 int value;
1008
1ef7286e 1009 r8168dp_2_mdio_start(tp);
e6de30d6 1010
24192210 1011 value = r8169_mdio_read(tp, reg);
e6de30d6 1012
1ef7286e 1013 r8168dp_2_mdio_stop(tp);
e6de30d6 1014
1015 return value;
1016}
1017
4da19633 1018static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1019{
24192210 1020 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1021}
1022
4da19633 1023static int rtl_readphy(struct rtl8169_private *tp, int location)
1024{
24192210 1025 return tp->mdio_ops.read(tp, location);
4da19633 1026}
1027
1028static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1029{
1030 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1031}
1032
76564428 1033static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1034{
1035 int val;
1036
4da19633 1037 val = rtl_readphy(tp, reg_addr);
76564428 1038 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1039}
1040
ffc46952
FR		 1041DECLARE_RTL_COND(rtl_ephyar_cond)
1042{
1ef7286e 1043 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
ffc46952
FR		 1044}
1045
fdf6fc06 1046static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1047{
1ef7286e 1048 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
dacf8154
FR		 1049 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1050
ffc46952
FR		 1051 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1052
1053 udelay(10);
dacf8154
FR		 1054}
1055
fdf6fc06 1056static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1057{
1ef7286e 1058 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
dacf8154 1059
ffc46952 1060 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1ef7286e 1061 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1062}
1063
935e2218
CHL		 1064DECLARE_RTL_COND(rtl_eriar_cond)
1065{
1ef7286e 1066 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
935e2218
CHL		 1067}
1068
fdf6fc06
FR		 1069static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1070 u32 val, int type)
133ac40a 1071{
133ac40a 1072 BUG_ON((addr & 3) || (mask == 0));
1ef7286e
AS		 1073 RTL_W32(tp, ERIDR, val);
1074 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
133ac40a 1075
ffc46952 1076 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1077}
1078
fdf6fc06 1079static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1080{
1ef7286e 1081 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
133ac40a 1082
ffc46952 1083 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1ef7286e 1084 RTL_R32(tp, ERIDR) : ~0;
133ac40a
HW		 1085}
1086
706123d0 1087static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1088 u32 m, int type)
133ac40a
HW		 1089{
1090 u32 val;
1091
fdf6fc06
FR		 1092 val = rtl_eri_read(tp, addr, type);
1093 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1094}
1095
935e2218
CHL		 1096static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1097{
1ef7286e 1098 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218 1099 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1ef7286e 1100 RTL_R32(tp, OCPDR) : ~0;
935e2218
CHL		 1101}
1102
1103static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1104{
1105 return rtl_eri_read(tp, reg, ERIAR_OOB);
1106}
1107
1108static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1109{
1110 switch (tp->mac_version) {
1111 case RTL_GIGA_MAC_VER_27:
1112 case RTL_GIGA_MAC_VER_28:
1113 case RTL_GIGA_MAC_VER_31:
1114 return r8168dp_ocp_read(tp, mask, reg);
1115 case RTL_GIGA_MAC_VER_49:
1116 case RTL_GIGA_MAC_VER_50:
1117 case RTL_GIGA_MAC_VER_51:
1118 return r8168ep_ocp_read(tp, mask, reg);
1119 default:
1120 BUG();
1121 return ~0;
1122 }
1123}
1124
1125static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1126 u32 data)
1127{
1ef7286e
AS		 1128 RTL_W32(tp, OCPDR, data);
1129 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218
CHL		 1130 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1131}
1132
1133static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1134 u32 data)
1135{
1136 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1137 data, ERIAR_OOB);
1138}
1139
1140static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1141{
1142 switch (tp->mac_version) {
1143 case RTL_GIGA_MAC_VER_27:
1144 case RTL_GIGA_MAC_VER_28:
1145 case RTL_GIGA_MAC_VER_31:
1146 r8168dp_ocp_write(tp, mask, reg, data);
1147 break;
1148 case RTL_GIGA_MAC_VER_49:
1149 case RTL_GIGA_MAC_VER_50:
1150 case RTL_GIGA_MAC_VER_51:
1151 r8168ep_ocp_write(tp, mask, reg, data);
1152 break;
1153 default:
1154 BUG();
1155 break;
1156 }
1157}
1158
2a9b4d96
CHL		 1159static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1160{
1161 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1162
1163 ocp_write(tp, 0x1, 0x30, 0x00000001);
1164}
1165
1166#define OOB_CMD_RESET 0x00
1167#define OOB_CMD_DRIVER_START 0x05
1168#define OOB_CMD_DRIVER_STOP 0x06
1169
1170static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1171{
1172 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1173}
1174
1175DECLARE_RTL_COND(rtl_ocp_read_cond)
1176{
1177 u16 reg;
1178
1179 reg = rtl8168_get_ocp_reg(tp);
1180
1181 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1182}
1183
935e2218 1184DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1185{
935e2218
CHL		 1186 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1187}
1188
1189DECLARE_RTL_COND(rtl_ocp_tx_cond)
1190{
1ef7286e 1191 return RTL_R8(tp, IBISR0) & 0x20;
935e2218 1192}
2a9b4d96 1193
003609da
CHL		 1194static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1195{
1ef7286e 1196 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
086ca23d 1197 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1ef7286e
AS		 1198 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1199 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
003609da
CHL		 1200}
1201
935e2218
CHL		 1202static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1203{
1204 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
2a9b4d96
CHL		 1205 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1206}
1207
935e2218 1208static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1209{
935e2218
CHL		 1210 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1211 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1212 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1213}
1214
1215static void rtl8168_driver_start(struct rtl8169_private *tp)
1216{
1217 switch (tp->mac_version) {
1218 case RTL_GIGA_MAC_VER_27:
1219 case RTL_GIGA_MAC_VER_28:
1220 case RTL_GIGA_MAC_VER_31:
1221 rtl8168dp_driver_start(tp);
1222 break;
1223 case RTL_GIGA_MAC_VER_49:
1224 case RTL_GIGA_MAC_VER_50:
1225 case RTL_GIGA_MAC_VER_51:
1226 rtl8168ep_driver_start(tp);
1227 break;
1228 default:
1229 BUG();
1230 break;
1231 }
1232}
2a9b4d96 1233
935e2218
CHL		 1234static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1235{
1236 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
2a9b4d96
CHL		 1237 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1238}
1239
935e2218
CHL		 1240static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1241{
003609da 1242 rtl8168ep_stop_cmac(tp);
935e2218
CHL		 1243 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1244 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1245 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1246}
1247
1248static void rtl8168_driver_stop(struct rtl8169_private *tp)
1249{
1250 switch (tp->mac_version) {
1251 case RTL_GIGA_MAC_VER_27:
1252 case RTL_GIGA_MAC_VER_28:
1253 case RTL_GIGA_MAC_VER_31:
1254 rtl8168dp_driver_stop(tp);
1255 break;
1256 case RTL_GIGA_MAC_VER_49:
1257 case RTL_GIGA_MAC_VER_50:
1258 case RTL_GIGA_MAC_VER_51:
1259 rtl8168ep_driver_stop(tp);
1260 break;
1261 default:
1262 BUG();
1263 break;
1264 }
1265}
1266
9dbe7896 1267static bool r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1268{
1269 u16 reg = rtl8168_get_ocp_reg(tp);
1270
9dbe7896 1271 return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
2a9b4d96
CHL		 1272}
1273
9dbe7896 1274static bool r8168ep_check_dash(struct rtl8169_private *tp)
935e2218 1275{
9dbe7896 1276 return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
935e2218
CHL		 1277}
1278
9dbe7896 1279static bool r8168_check_dash(struct rtl8169_private *tp)
935e2218
CHL		 1280{
1281 switch (tp->mac_version) {
1282 case RTL_GIGA_MAC_VER_27:
1283 case RTL_GIGA_MAC_VER_28:
1284 case RTL_GIGA_MAC_VER_31:
1285 return r8168dp_check_dash(tp);
1286 case RTL_GIGA_MAC_VER_49:
1287 case RTL_GIGA_MAC_VER_50:
1288 case RTL_GIGA_MAC_VER_51:
1289 return r8168ep_check_dash(tp);
1290 default:
9dbe7896 1291 return false;
935e2218
CHL		 1292 }
1293}
1294
c28aa385 1295struct exgmac_reg {
1296 u16 addr;
1297 u16 mask;
1298 u32 val;
1299};
1300
fdf6fc06 1301static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1302 const struct exgmac_reg *r, int len)
1303{
1304 while (len-- > 0) {
fdf6fc06 1305 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1306 r++;
1307 }
1308}
1309
ffc46952
FR		 1310DECLARE_RTL_COND(rtl_efusear_cond)
1311{
1ef7286e 1312 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
ffc46952
FR		 1313}
1314
fdf6fc06 1315static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1316{
1ef7286e 1317 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
daf9df6d 1318
ffc46952 1319 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1ef7286e 1320 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1321}
1322
9085cdfa
FR		 1323static u16 rtl_get_events(struct rtl8169_private *tp)
1324{
1ef7286e 1325 return RTL_R16(tp, IntrStatus);
9085cdfa
FR		 1326}
1327
1328static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1329{
1ef7286e 1330 RTL_W16(tp, IntrStatus, bits);
9085cdfa
FR		 1331 mmiowb();
1332}
1333
1334static void rtl_irq_disable(struct rtl8169_private *tp)
1335{
1ef7286e 1336 RTL_W16(tp, IntrMask, 0);
9085cdfa
FR		 1337 mmiowb();
1338}
1339
3e990ff5
FR		 1340static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1341{
1ef7286e 1342 RTL_W16(tp, IntrMask, bits);
3e990ff5
FR		 1343}
1344
da78dbff
FR		 1345#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1346#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1347#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1348
1349static void rtl_irq_enable_all(struct rtl8169_private *tp)
1350{
1351 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1352}
1353
811fd301 1354static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1355{
9085cdfa 1356 rtl_irq_disable(tp);
da78dbff 1357 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1ef7286e 1358 RTL_R8(tp, ChipCmd);
1da177e4
LT		 1359}
1360
70090424
HW		 1361static void rtl_link_chg_patch(struct rtl8169_private *tp)
1362{
70090424 1363 struct net_device *dev = tp->dev;
29a12b49 1364 struct phy_device *phydev = dev->phydev;
70090424
HW		 1365
1366 if (!netif_running(dev))
1367 return;
1368
b3d7b2f2
HW		 1369 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1370 tp->mac_version == RTL_GIGA_MAC_VER_38) {
29a12b49 1371 if (phydev->speed == SPEED_1000) {
fdf6fc06
FR		 1372 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1373 ERIAR_EXGMAC);
1374 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1375 ERIAR_EXGMAC);
29a12b49 1376 } else if (phydev->speed == SPEED_100) {
fdf6fc06
FR		 1377 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1378 ERIAR_EXGMAC);
1379 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1380 ERIAR_EXGMAC);
70090424 1381 } else {
fdf6fc06
FR		 1382 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1383 ERIAR_EXGMAC);
1384 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1385 ERIAR_EXGMAC);
70090424
HW		 1386 }
1387 /* Reset packet filter */
706123d0 1388 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1389 ERIAR_EXGMAC);
706123d0 1390 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1391 ERIAR_EXGMAC);
c2218925
HW		 1392 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1393 tp->mac_version == RTL_GIGA_MAC_VER_36) {
29a12b49 1394 if (phydev->speed == SPEED_1000) {
fdf6fc06
FR		 1395 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1396 ERIAR_EXGMAC);
1397 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1398 ERIAR_EXGMAC);
c2218925 1399 } else {
fdf6fc06
FR		 1400 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1401 ERIAR_EXGMAC);
1402 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1403 ERIAR_EXGMAC);
c2218925 1404 }
7e18dca1 1405 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
29a12b49 1406 if (phydev->speed == SPEED_10) {
fdf6fc06
FR		 1407 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1408 ERIAR_EXGMAC);
1409 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1410 ERIAR_EXGMAC);
7e18dca1 1411 } else {
fdf6fc06
FR		 1412 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1413 ERIAR_EXGMAC);
7e18dca1 1414 }
70090424
HW		 1415 }
1416}
1417
e1759441
RW		 1418#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1419
1420static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1421{
61a4dcc2 1422 u8 options;
e1759441 1423 u32 wolopts = 0;
61a4dcc2 1424
1ef7286e 1425 options = RTL_R8(tp, Config1);
61a4dcc2 1426 if (!(options & PMEnable))
e1759441 1427 return 0;
61a4dcc2 1428
1ef7286e 1429 options = RTL_R8(tp, Config3);
61a4dcc2 1430 if (options & LinkUp)
e1759441 1431 wolopts |= WAKE_PHY;
6e1d0b89 1432 switch (tp->mac_version) {
2a71883c
HK		 1433 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1434 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1435 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1436 wolopts |= WAKE_MAGIC;
1437 break;
1438 default:
1439 if (options & MagicPacket)
1440 wolopts |= WAKE_MAGIC;
1441 break;
1442 }
61a4dcc2 1443
1ef7286e 1444 options = RTL_R8(tp, Config5);
61a4dcc2 1445 if (options & UWF)
e1759441 1446 wolopts |= WAKE_UCAST;
61a4dcc2 1447 if (options & BWF)
e1759441 1448 wolopts |= WAKE_BCAST;
61a4dcc2 1449 if (options & MWF)
e1759441 1450 wolopts |= WAKE_MCAST;
61a4dcc2 1451
e1759441 1452 return wolopts;
61a4dcc2
FR		 1453}
1454
e1759441 1455static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1456{
1457 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1458
da78dbff 1459 rtl_lock_work(tp);
e1759441 1460 wol->supported = WAKE_ANY;
433f9d0d 1461 wol->wolopts = tp->saved_wolopts;
da78dbff 1462 rtl_unlock_work(tp);
e1759441
RW		 1463}
1464
1465static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1466{
6e1d0b89 1467 unsigned int i, tmp;
350f7596 1468 static const struct {
61a4dcc2
FR		 1469 u32 opt;
1470 u16 reg;
1471 u8 mask;
1472 } cfg[] = {
61a4dcc2 1473 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1474 { WAKE_UCAST, Config5, UWF },
1475 { WAKE_BCAST, Config5, BWF },
1476 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1477 { WAKE_ANY, Config5, LanWake },
1478 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1479 };
851e6022 1480 u8 options;
61a4dcc2 1481
1ef7286e 1482 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
61a4dcc2 1483
6e1d0b89 1484 switch (tp->mac_version) {
2a71883c
HK		 1485 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1486 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1487 tmp = ARRAY_SIZE(cfg) - 1;
1488 if (wolopts & WAKE_MAGIC)
706123d0 1489 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1490 0x0dc,
1491 ERIAR_MASK_0100,
1492 MagicPacket_v2,
1493 0x0000,
1494 ERIAR_EXGMAC);
1495 else
706123d0 1496 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1497 0x0dc,
1498 ERIAR_MASK_0100,
1499 0x0000,
1500 MagicPacket_v2,
1501 ERIAR_EXGMAC);
1502 break;
1503 default:
1504 tmp = ARRAY_SIZE(cfg);
1505 break;
1506 }
1507
1508 for (i = 0; i < tmp; i++) {
1ef7286e 1509 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
e1759441 1510 if (wolopts & cfg[i].opt)
61a4dcc2 1511 options |= cfg[i].mask;
1ef7286e 1512 RTL_W8(tp, cfg[i].reg, options);
61a4dcc2
FR		 1513 }
1514
851e6022
FR		 1515 switch (tp->mac_version) {
1516 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1ef7286e 1517 options = RTL_R8(tp, Config1) & ~PMEnable;
851e6022
FR		 1518 if (wolopts)
1519 options |= PMEnable;
1ef7286e 1520 RTL_W8(tp, Config1, options);
851e6022
FR		 1521 break;
1522 default:
1ef7286e 1523 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
d387b427
FR		 1524 if (wolopts)
1525 options |= PME_SIGNAL;
1ef7286e 1526 RTL_W8(tp, Config2, options);
851e6022
FR		 1527 break;
1528 }
1529
1ef7286e 1530 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
e1759441
RW		 1531}
1532
1533static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1534{
1535 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1536 struct device *d = tp_to_dev(tp);
5fa80a32 1537
2f533f6b
HK		 1538 if (wol->wolopts & ~WAKE_ANY)
1539 return -EINVAL;
1540
5fa80a32 1541 pm_runtime_get_noresume(d);
e1759441 1542
da78dbff 1543 rtl_lock_work(tp);
61a4dcc2 1544
2f533f6b 1545 tp->saved_wolopts = wol->wolopts;
433f9d0d 1546
5fa80a32 1547 if (pm_runtime_active(d))
433f9d0d 1548 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff
FR		 1549
1550 rtl_unlock_work(tp);
61a4dcc2 1551
433f9d0d 1552 device_set_wakeup_enable(d, tp->saved_wolopts);
ea80907f 1553
5fa80a32
CHL		 1554 pm_runtime_put_noidle(d);
1555
61a4dcc2
FR		 1556 return 0;
1557}
1558
31bd204f
FR		 1559static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1560{
85bffe6c 1561 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1562}
1563
1da177e4
LT		 1564static void rtl8169_get_drvinfo(struct net_device *dev,
1565 struct ethtool_drvinfo *info)
1566{
1567 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1568 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1569
68aad78c 1570 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
68aad78c 1571 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1572 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1573 if (!IS_ERR_OR_NULL(rtl_fw))
1574 strlcpy(info->fw_version, rtl_fw->version,
1575 sizeof(info->fw_version));
1da177e4
LT		 1576}
1577
1578static int rtl8169_get_regs_len(struct net_device *dev)
1579{
1580 return R8169_REGS_SIZE;
1581}
1582
c8f44aff
MM		 1583static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1584 netdev_features_t features)
1da177e4 1585{
d58d46b5
FR		 1586 struct rtl8169_private *tp = netdev_priv(dev);
1587
2b7b4318 1588 if (dev->mtu > TD_MSS_MAX)
350fb32a 1589 features &= ~NETIF_F_ALL_TSO;
1da177e4 1590
d58d46b5 1591 if (dev->mtu > JUMBO_1K &&
6ed0e08f 1592 tp->mac_version > RTL_GIGA_MAC_VER_06)
d58d46b5
FR		 1593 features &= ~NETIF_F_IP_CSUM;
1594
350fb32a 1595 return features;
1da177e4
LT		 1596}
1597
a3984578
HK		 1598static int rtl8169_set_features(struct net_device *dev,
1599 netdev_features_t features)
1da177e4
LT		 1600{
1601 struct rtl8169_private *tp = netdev_priv(dev);
929a031d 1602 u32 rx_config;
1da177e4 1603
a3984578
HK		 1604 rtl_lock_work(tp);
1605
1ef7286e 1606 rx_config = RTL_R32(tp, RxConfig);
929a031d 1607 if (features & NETIF_F_RXALL)
1608 rx_config |= (AcceptErr | AcceptRunt);
1609 else
1610 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 1611
1ef7286e 1612 RTL_W32(tp, RxConfig, rx_config);
350fb32a 1613
929a031d 1614 if (features & NETIF_F_RXCSUM)
1615 tp->cp_cmd |= RxChkSum;
1616 else
1617 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1618
929a031d 1619 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1620 tp->cp_cmd |= RxVlan;
1621 else
1622 tp->cp_cmd &= ~RxVlan;
1623
1ef7286e
AS		 1624 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1625 RTL_R16(tp, CPlusCmd);
1da177e4 1626
da78dbff 1627 rtl_unlock_work(tp);
1da177e4
LT		 1628
1629 return 0;
1630}
1631
810f4893 1632static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1633{
df8a39de
JP		 1634 return (skb_vlan_tag_present(skb)) ?
1635 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 1636}
1637
7a8fc77b 1638static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1639{
1640 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1641
7a8fc77b 1642 if (opts2 & RxVlanTag)
86a9bad3 1643 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1644}
1645
1da177e4
LT		 1646static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1647 void *p)
1648{
5b0384f4 1649 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 1650 u32 __iomem *data = tp->mmio_addr;
1651 u32 *dw = p;
1652 int i;
1da177e4 1653
da78dbff 1654 rtl_lock_work(tp);
15edae91
PW		 1655 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1656 memcpy_fromio(dw++, data++, 4);
da78dbff 1657 rtl_unlock_work(tp);
1da177e4
LT		 1658}
1659
b57b7e5a
SH		 1660static u32 rtl8169_get_msglevel(struct net_device *dev)
1661{
1662 struct rtl8169_private *tp = netdev_priv(dev);
1663
1664 return tp->msg_enable;
1665}
1666
1667static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1668{
1669 struct rtl8169_private *tp = netdev_priv(dev);
1670
1671 tp->msg_enable = value;
1672}
1673
d4a3a0fc
SH		 1674static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1675 "tx_packets",
1676 "rx_packets",
1677 "tx_errors",
1678 "rx_errors",
1679 "rx_missed",
1680 "align_errors",
1681 "tx_single_collisions",
1682 "tx_multi_collisions",
1683 "unicast",
1684 "broadcast",
1685 "multicast",
1686 "tx_aborted",
1687 "tx_underrun",
1688};
1689
b9f2c044 1690static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1691{
b9f2c044
JG		 1692 switch (sset) {
1693 case ETH_SS_STATS:
1694 return ARRAY_SIZE(rtl8169_gstrings);
1695 default:
1696 return -EOPNOTSUPP;
1697 }
d4a3a0fc
SH		 1698}
1699
42020320 1700DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 1701{
1ef7286e 1702 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 1703}
1704
e71c9ce2 1705static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
6e85d5ad 1706{
42020320
CV		 1707 dma_addr_t paddr = tp->counters_phys_addr;
1708 u32 cmd;
6e85d5ad 1709
1ef7286e
AS		 1710 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1711 RTL_R32(tp, CounterAddrHigh);
42020320 1712 cmd = (u64)paddr & DMA_BIT_MASK(32);
1ef7286e
AS		 1713 RTL_W32(tp, CounterAddrLow, cmd);
1714 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
6e85d5ad 1715
a78e9366 1716 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 1717}
1718
e71c9ce2 1719static bool rtl8169_reset_counters(struct rtl8169_private *tp)
6e85d5ad 1720{
6e85d5ad
CV		 1721 /*
1722 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1723 * tally counters.
1724 */
1725 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1726 return true;
1727
e71c9ce2 1728 return rtl8169_do_counters(tp, CounterReset);
ffc46952
FR		 1729}
1730
e71c9ce2 1731static bool rtl8169_update_counters(struct rtl8169_private *tp)
d4a3a0fc 1732{
355423d0
IV		 1733 /*
1734 * Some chips are unable to dump tally counters when the receiver
1735 * is disabled.
1736 */
1ef7286e 1737 if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
6e85d5ad 1738 return true;
d4a3a0fc 1739
e71c9ce2 1740 return rtl8169_do_counters(tp, CounterDump);
6e85d5ad
CV		 1741}
1742
e71c9ce2 1743static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
6e85d5ad 1744{
42020320 1745 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 1746 bool ret = false;
1747
1748 /*
1749 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1750 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1751 * reset by a power cycle, while the counter values collected by the
1752 * driver are reset at every driver unload/load cycle.
1753 *
1754 * To make sure the HW values returned by @get_stats64 match the SW
1755 * values, we collect the initial values at first open(*) and use them
1756 * as offsets to normalize the values returned by @get_stats64.
1757 *
1758 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1759 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1760 * set at open time by rtl_hw_start.
1761 */
1762
1763 if (tp->tc_offset.inited)
1764 return true;
1765
1766 /* If both, reset and update fail, propagate to caller. */
e71c9ce2 1767 if (rtl8169_reset_counters(tp))
6e85d5ad
CV		 1768 ret = true;
1769
e71c9ce2 1770 if (rtl8169_update_counters(tp))
6e85d5ad
CV		 1771 ret = true;
1772
42020320
CV		 1773 tp->tc_offset.tx_errors = counters->tx_errors;
1774 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1775 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 1776 tp->tc_offset.inited = true;
1777
1778 return ret;
d4a3a0fc
SH		 1779}
1780
355423d0
IV		 1781static void rtl8169_get_ethtool_stats(struct net_device *dev,
1782 struct ethtool_stats *stats, u64 *data)
1783{
1784 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1785 struct device *d = tp_to_dev(tp);
42020320 1786 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 1787
1788 ASSERT_RTNL();
1789
e0636236
CHL		 1790 pm_runtime_get_noresume(d);
1791
1792 if (pm_runtime_active(d))
e71c9ce2 1793 rtl8169_update_counters(tp);
e0636236
CHL		 1794
1795 pm_runtime_put_noidle(d);
355423d0 1796
42020320
CV		 1797 data[0] = le64_to_cpu(counters->tx_packets);
1798 data[1] = le64_to_cpu(counters->rx_packets);
1799 data[2] = le64_to_cpu(counters->tx_errors);
1800 data[3] = le32_to_cpu(counters->rx_errors);
1801 data[4] = le16_to_cpu(counters->rx_missed);
1802 data[5] = le16_to_cpu(counters->align_errors);
1803 data[6] = le32_to_cpu(counters->tx_one_collision);
1804 data[7] = le32_to_cpu(counters->tx_multi_collision);
1805 data[8] = le64_to_cpu(counters->rx_unicast);
1806 data[9] = le64_to_cpu(counters->rx_broadcast);
1807 data[10] = le32_to_cpu(counters->rx_multicast);
1808 data[11] = le16_to_cpu(counters->tx_aborted);
1809 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 1810}
1811
d4a3a0fc
SH		 1812static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1813{
1814 switch(stringset) {
1815 case ETH_SS_STATS:
1816 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1817 break;
1818 }
1819}
1820
50970831
FR		 1821/*
1822 * Interrupt coalescing
1823 *
1824 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1825 * > 8169, 8168 and 810x line of chipsets
1826 *
1827 * 8169, 8168, and 8136(810x) serial chipsets support it.
1828 *
1829 * > 2 - the Tx timer unit at gigabit speed
1830 *
1831 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1832 * (0xe0) bit 1 and bit 0.
1833 *
1834 * For 8169
1835 * bit[1:0] \ speed 1000M 100M 10M
1836 * 0 0 320ns 2.56us 40.96us
1837 * 0 1 2.56us 20.48us 327.7us
1838 * 1 0 5.12us 40.96us 655.4us
1839 * 1 1 10.24us 81.92us 1.31ms
1840 *
1841 * For the other
1842 * bit[1:0] \ speed 1000M 100M 10M
1843 * 0 0 5us 2.56us 40.96us
1844 * 0 1 40us 20.48us 327.7us
1845 * 1 0 80us 40.96us 655.4us
1846 * 1 1 160us 81.92us 1.31ms
1847 */
1848
1849/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1850struct rtl_coalesce_scale {
1851 /* Rx / Tx */
1852 u32 nsecs[2];
1853};
1854
1855/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1856struct rtl_coalesce_info {
1857 u32 speed;
1858 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1859};
1860
1861/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1862#define rxtx_x1822(r, t) { \
1863 {{(r), (t)}}, \
1864 {{(r)*8, (t)*8}}, \
1865 {{(r)*8*2, (t)*8*2}}, \
1866 {{(r)*8*2*2, (t)*8*2*2}}, \
1867}
1868static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1869 /* speed delays: rx00 tx00 */
1870 { SPEED_10, rxtx_x1822(40960, 40960) },
1871 { SPEED_100, rxtx_x1822( 2560, 2560) },
1872 { SPEED_1000, rxtx_x1822( 320, 320) },
1873 { 0 },
1874};
1875
1876static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1877 /* speed delays: rx00 tx00 */
1878 { SPEED_10, rxtx_x1822(40960, 40960) },
1879 { SPEED_100, rxtx_x1822( 2560, 2560) },
1880 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1881 { 0 },
1882};
1883#undef rxtx_x1822
1884
1885/* get rx/tx scale vector corresponding to current speed */
1886static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1887{
1888 struct rtl8169_private *tp = netdev_priv(dev);
1889 struct ethtool_link_ksettings ecmd;
1890 const struct rtl_coalesce_info *ci;
1891 int rc;
1892
45772433 1893 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
50970831
FR		 1894 if (rc < 0)
1895 return ERR_PTR(rc);
1896
1897 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1898 if (ecmd.base.speed == ci->speed) {
1899 return ci;
1900 }
1901 }
1902
1903 return ERR_PTR(-ELNRNG);
1904}
1905
1906static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1907{
1908 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1909 const struct rtl_coalesce_info *ci;
1910 const struct rtl_coalesce_scale *scale;
1911 struct {
1912 u32 *max_frames;
1913 u32 *usecs;
1914 } coal_settings [] = {
1915 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1916 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1917 }, *p = coal_settings;
1918 int i;
1919 u16 w;
1920
1921 memset(ec, 0, sizeof(*ec));
1922
1923 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1924 ci = rtl_coalesce_info(dev);
1925 if (IS_ERR(ci))
1926 return PTR_ERR(ci);
1927
0ae0974e 1928 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
50970831
FR		 1929
1930 /* read IntrMitigate and adjust according to scale */
1ef7286e 1931 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
50970831
FR		 1932 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1933 w >>= RTL_COALESCE_SHIFT;
1934 *p->usecs = w & RTL_COALESCE_MASK;
1935 }
1936
1937 for (i = 0; i < 2; i++) {
1938 p = coal_settings + i;
1939 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1940
1941 /*
1942 * ethtool_coalesce says it is illegal to set both usecs and
1943 * max_frames to 0.
1944 */
1945 if (!*p->usecs && !*p->max_frames)
1946 *p->max_frames = 1;
1947 }
1948
1949 return 0;
1950}
1951
1952/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1953static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1954 struct net_device *dev, u32 nsec, u16 *cp01)
1955{
1956 const struct rtl_coalesce_info *ci;
1957 u16 i;
1958
1959 ci = rtl_coalesce_info(dev);
1960 if (IS_ERR(ci))
1961 return ERR_CAST(ci);
1962
1963 for (i = 0; i < 4; i++) {
1964 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1965 ci->scalev[i].nsecs[1]);
1966 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1967 *cp01 = i;
1968 return &ci->scalev[i];
1969 }
1970 }
1971
1972 return ERR_PTR(-EINVAL);
1973}
1974
1975static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1976{
1977 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1978 const struct rtl_coalesce_scale *scale;
1979 struct {
1980 u32 frames;
1981 u32 usecs;
1982 } coal_settings [] = {
1983 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1984 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1985 }, *p = coal_settings;
1986 u16 w = 0, cp01;
1987 int i;
1988
1989 scale = rtl_coalesce_choose_scale(dev,
1990 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1991 if (IS_ERR(scale))
1992 return PTR_ERR(scale);
1993
1994 for (i = 0; i < 2; i++, p++) {
1995 u32 units;
1996
1997 /*
1998 * accept max_frames=1 we returned in rtl_get_coalesce.
1999 * accept it not only when usecs=0 because of e.g. the following scenario:
2000 *
2001 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2002 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2003 * - then user does `ethtool -C eth0 rx-usecs 100`
2004 *
2005 * since ethtool sends to kernel whole ethtool_coalesce
2006 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2007 * we'll reject it below in `frames % 4 != 0`.
2008 */
2009 if (p->frames == 1) {
2010 p->frames = 0;
2011 }
2012
2013 units = p->usecs * 1000 / scale->nsecs[i];
2014 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2015 return -EINVAL;
2016
2017 w <<= RTL_COALESCE_SHIFT;
2018 w |= units;
2019 w <<= RTL_COALESCE_SHIFT;
2020 w |= p->frames >> 2;
2021 }
2022
2023 rtl_lock_work(tp);
2024
1ef7286e 2025 RTL_W16(tp, IntrMitigate, swab16(w));
50970831 2026
9a3c81fa 2027 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1ef7286e
AS		 2028 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2029 RTL_R16(tp, CPlusCmd);
50970831
FR		 2030
2031 rtl_unlock_work(tp);
2032
2033 return 0;
2034}
2035
7282d491 2036static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2037 .get_drvinfo = rtl8169_get_drvinfo,
2038 .get_regs_len = rtl8169_get_regs_len,
2039 .get_link = ethtool_op_get_link,
50970831
FR		 2040 .get_coalesce = rtl_get_coalesce,
2041 .set_coalesce = rtl_set_coalesce,
b57b7e5a
SH		 2042 .get_msglevel = rtl8169_get_msglevel,
2043 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2044 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2045 .get_wol = rtl8169_get_wol,
2046 .set_wol = rtl8169_set_wol,
d4a3a0fc 2047 .get_strings = rtl8169_get_strings,
b9f2c044 2048 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2049 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2050 .get_ts_info = ethtool_op_get_ts_info,
dd84957e 2051 .nway_reset = phy_ethtool_nway_reset,
45772433
HK		 2052 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2053 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1da177e4
LT		 2054};
2055
07d3f51f 2056static void rtl8169_get_mac_version(struct rtl8169_private *tp,
22148df0 2057 u8 default_version)
1da177e4 2058{
0e485150
FR		 2059 /*
2060 * The driver currently handles the 8168Bf and the 8168Be identically
2061 * but they can be identified more specifically through the test below
2062 * if needed:
2063 *
1ef7286e 2064 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2065 *
2066 * Same thing for the 8101Eb and the 8101Ec:
2067 *
1ef7286e 2068 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2069 */
3744100e 2070 static const struct rtl_mac_info {
1da177e4 2071 u32 mask;
e3cf0cc0 2072 u32 val;
1da177e4
LT		 2073 int mac_version;
2074 } mac_info[] = {
935e2218
CHL		 2075 /* 8168EP family. */
2076 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2077 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2078 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2079
6e1d0b89
CHL		 2080 /* 8168H family. */
2081 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2082 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2083
c558386b 2084 /* 8168G family. */
45dd95c4 2085 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2086 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2087 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2088 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2089
c2218925 2090 /* 8168F family. */
b3d7b2f2 2091 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2092 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2093 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2094
01dc7fec 2095 /* 8168E family. */
70090424 2096 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2097 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2098 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2099
5b538df9 2100 /* 8168D family. */
daf9df6d 2101 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2102 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2103
e6de30d6 2104 /* 8168DP family. */
2105 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2106 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2107 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2108
ef808d50 2109 /* 8168C family. */
ef3386f0 2110 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2111 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2112 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2113 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2114 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2115 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
ef808d50 2116 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2117
2118 /* 8168B family. */
2119 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
e3cf0cc0
FR		 2120 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2121 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2122
2123 /* 8101 family. */
5598bfe5 2124 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2125 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
5a5e4443
HW		 2126 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2127 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2128 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2129 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2130 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2131 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2132 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2133 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2134 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2135 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2136 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2137 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2138 /* FIXME: where did these entries come from ? -- FR */
2139 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2140 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2141
2142 /* 8110 family. */
2143 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2144 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2145 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2146 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2147 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2148 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2149
f21b75e9
JD		 2150 /* Catch-all */
2151 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2152 };
2153 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2154 u32 reg;
2155
1ef7286e 2156 reg = RTL_R32(tp, TxConfig);
e3cf0cc0 2157 while ((reg & p->mask) != p->val)
1da177e4
LT		 2158 p++;
2159 tp->mac_version = p->mac_version;
5d320a20
FR		 2160
2161 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
22148df0
HK		 2162 dev_notice(tp_to_dev(tp),
2163 "unknown MAC, using family default\n");
5d320a20 2164 tp->mac_version = default_version;
58152cd4 2165 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
f7ffa9ae 2166 tp->mac_version = tp->supports_gmii ?
58152cd4 2167 RTL_GIGA_MAC_VER_42 :
2168 RTL_GIGA_MAC_VER_43;
6e1d0b89 2169 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
f7ffa9ae 2170 tp->mac_version = tp->supports_gmii ?
6e1d0b89
CHL		 2171 RTL_GIGA_MAC_VER_45 :
2172 RTL_GIGA_MAC_VER_47;
2173 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
f7ffa9ae 2174 tp->mac_version = tp->supports_gmii ?
6e1d0b89
CHL		 2175 RTL_GIGA_MAC_VER_46 :
2176 RTL_GIGA_MAC_VER_48;
5d320a20 2177 }
1da177e4
LT		 2178}
2179
2180static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2181{
49d17512 2182 netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2183}
2184
867763c1
FR		 2185struct phy_reg {
2186 u16 reg;
2187 u16 val;
2188};
2189
4da19633 2190static void rtl_writephy_batch(struct rtl8169_private *tp,
2191 const struct phy_reg *regs, int len)
867763c1
FR		 2192{
2193 while (len-- > 0) {
4da19633 2194 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2195 regs++;
2196 }
2197}
2198
bca03d5f 2199#define PHY_READ 0x00000000
2200#define PHY_DATA_OR 0x10000000
2201#define PHY_DATA_AND 0x20000000
2202#define PHY_BJMPN 0x30000000
eee3786f 2203#define PHY_MDIO_CHG 0x40000000
bca03d5f 2204#define PHY_CLEAR_READCOUNT 0x70000000
2205#define PHY_WRITE 0x80000000
2206#define PHY_READCOUNT_EQ_SKIP 0x90000000
2207#define PHY_COMP_EQ_SKIPN 0xa0000000
2208#define PHY_COMP_NEQ_SKIPN 0xb0000000
2209#define PHY_WRITE_PREVIOUS 0xc0000000
2210#define PHY_SKIPN 0xd0000000
2211#define PHY_DELAY_MS 0xe0000000
bca03d5f 2212
960aee6c
HW		 2213struct fw_info {
2214 u32 magic;
2215 char version[RTL_VER_SIZE];
2216 __le32 fw_start;
2217 __le32 fw_len;
2218 u8 chksum;
2219} __packed;
2220
1c361efb
FR		 2221#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2222
2223static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2224{
b6ffd97f 2225 const struct firmware *fw = rtl_fw->fw;
960aee6c 2226 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2227 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2228 char *version = rtl_fw->version;
2229 bool rc = false;
2230
2231 if (fw->size < FW_OPCODE_SIZE)
2232 goto out;
960aee6c
HW		 2233
2234 if (!fw_info->magic) {
2235 size_t i, size, start;
2236 u8 checksum = 0;
2237
2238 if (fw->size < sizeof(*fw_info))
2239 goto out;
2240
2241 for (i = 0; i < fw->size; i++)
2242 checksum += fw->data[i];
2243 if (checksum != 0)
2244 goto out;
2245
2246 start = le32_to_cpu(fw_info->fw_start);
2247 if (start > fw->size)
2248 goto out;
2249
2250 size = le32_to_cpu(fw_info->fw_len);
2251 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2252 goto out;
2253
2254 memcpy(version, fw_info->version, RTL_VER_SIZE);
2255
2256 pa->code = (__le32 *)(fw->data + start);
2257 pa->size = size;
2258 } else {
1c361efb
FR		 2259 if (fw->size % FW_OPCODE_SIZE)
2260 goto out;
2261
2262 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2263
2264 pa->code = (__le32 *)fw->data;
2265 pa->size = fw->size / FW_OPCODE_SIZE;
2266 }
2267 version[RTL_VER_SIZE - 1] = 0;
2268
2269 rc = true;
2270out:
2271 return rc;
2272}
2273
fd112f2e
FR		 2274static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2275 struct rtl_fw_phy_action *pa)
1c361efb 2276{
fd112f2e 2277 bool rc = false;
1c361efb 2278 size_t index;
bca03d5f 2279
1c361efb
FR		 2280 for (index = 0; index < pa->size; index++) {
2281 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2282 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2283
42b82dc1 2284 switch(action & 0xf0000000) {
2285 case PHY_READ:
2286 case PHY_DATA_OR:
2287 case PHY_DATA_AND:
eee3786f 2288 case PHY_MDIO_CHG:
42b82dc1 2289 case PHY_CLEAR_READCOUNT:
2290 case PHY_WRITE:
2291 case PHY_WRITE_PREVIOUS:
2292 case PHY_DELAY_MS:
2293 break;
2294
2295 case PHY_BJMPN:
2296 if (regno > index) {
fd112f2e 2297 netif_err(tp, ifup, tp->dev,
cecb5fd7 2298 "Out of range of firmware\n");
fd112f2e 2299 goto out;
42b82dc1 2300 }
2301 break;
2302 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2303 if (index + 2 >= pa->size) {
fd112f2e 2304 netif_err(tp, ifup, tp->dev,
cecb5fd7 2305 "Out of range of firmware\n");
fd112f2e 2306 goto out;
42b82dc1 2307 }
2308 break;
2309 case PHY_COMP_EQ_SKIPN:
2310 case PHY_COMP_NEQ_SKIPN:
2311 case PHY_SKIPN:
1c361efb 2312 if (index + 1 + regno >= pa->size) {
fd112f2e 2313 netif_err(tp, ifup, tp->dev,
cecb5fd7 2314 "Out of range of firmware\n");
fd112f2e 2315 goto out;
42b82dc1 2316 }
bca03d5f 2317 break;
2318
42b82dc1 2319 default:
fd112f2e 2320 netif_err(tp, ifup, tp->dev,
42b82dc1 2321 "Invalid action 0x%08x\n", action);
fd112f2e 2322 goto out;
bca03d5f 2323 }
2324 }
fd112f2e
FR		 2325 rc = true;
2326out:
2327 return rc;
2328}
bca03d5f 2329
fd112f2e
FR		 2330static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2331{
2332 struct net_device *dev = tp->dev;
2333 int rc = -EINVAL;
2334
2335 if (!rtl_fw_format_ok(tp, rtl_fw)) {
5c2d2b14 2336 netif_err(tp, ifup, dev, "invalid firmware\n");
fd112f2e
FR		 2337 goto out;
2338 }
2339
2340 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2341 rc = 0;
2342out:
2343 return rc;
2344}
2345
2346static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2347{
2348 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2349 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2350 u32 predata, count;
2351 size_t index;
2352
2353 predata = count = 0;
eee3786f 2354 org.write = ops->write;
2355 org.read = ops->read;
42b82dc1 2356
1c361efb
FR		 2357 for (index = 0; index < pa->size; ) {
2358 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2359 u32 data = action & 0x0000ffff;
42b82dc1 2360 u32 regno = (action & 0x0fff0000) >> 16;
2361
2362 if (!action)
2363 break;
bca03d5f 2364
2365 switch(action & 0xf0000000) {
42b82dc1 2366 case PHY_READ:
2367 predata = rtl_readphy(tp, regno);
2368 count++;
2369 index++;
2370 break;
2371 case PHY_DATA_OR:
2372 predata |= data;
2373 index++;
2374 break;
2375 case PHY_DATA_AND:
2376 predata &= data;
2377 index++;
2378 break;
2379 case PHY_BJMPN:
2380 index -= regno;
2381 break;
eee3786f 2382 case PHY_MDIO_CHG:
2383 if (data == 0) {
2384 ops->write = org.write;
2385 ops->read = org.read;
2386 } else if (data == 1) {
2387 ops->write = mac_mcu_write;
2388 ops->read = mac_mcu_read;
2389 }
2390
42b82dc1 2391 index++;
2392 break;
2393 case PHY_CLEAR_READCOUNT:
2394 count = 0;
2395 index++;
2396 break;
bca03d5f 2397 case PHY_WRITE:
42b82dc1 2398 rtl_writephy(tp, regno, data);
2399 index++;
2400 break;
2401 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2402 index += (count == data) ? 2 : 1;
bca03d5f 2403 break;
42b82dc1 2404 case PHY_COMP_EQ_SKIPN:
2405 if (predata == data)
2406 index += regno;
2407 index++;
2408 break;
2409 case PHY_COMP_NEQ_SKIPN:
2410 if (predata != data)
2411 index += regno;
2412 index++;
2413 break;
2414 case PHY_WRITE_PREVIOUS:
2415 rtl_writephy(tp, regno, predata);
2416 index++;
2417 break;
2418 case PHY_SKIPN:
2419 index += regno + 1;
2420 break;
2421 case PHY_DELAY_MS:
2422 mdelay(data);
2423 index++;
2424 break;
2425
bca03d5f 2426 default:
2427 BUG();
2428 }
2429 }
eee3786f 2430
2431 ops->write = org.write;
2432 ops->read = org.read;
bca03d5f 2433}
2434
f1e02ed1 2435static void rtl_release_firmware(struct rtl8169_private *tp)
2436{
b6ffd97f
FR		 2437 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2438 release_firmware(tp->rtl_fw->fw);
2439 kfree(tp->rtl_fw);
2440 }
2441 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2442}
2443
953a12cc 2444static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2445{
b6ffd97f 2446 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2447
2448 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2449 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2450 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2451}
2452
2453static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2454{
2455 if (rtl_readphy(tp, reg) != val)
2456 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2457 else
2458 rtl_apply_firmware(tp);
f1e02ed1 2459}
2460
4da19633 2461static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2462{
350f7596 2463 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2464 { 0x1f, 0x0001 },
2465 { 0x06, 0x006e },
2466 { 0x08, 0x0708 },
2467 { 0x15, 0x4000 },
2468 { 0x18, 0x65c7 },
1da177e4 2469
0b9b571d 2470 { 0x1f, 0x0001 },
2471 { 0x03, 0x00a1 },
2472 { 0x02, 0x0008 },
2473 { 0x01, 0x0120 },
2474 { 0x00, 0x1000 },
2475 { 0x04, 0x0800 },
2476 { 0x04, 0x0000 },
1da177e4 2477
0b9b571d 2478 { 0x03, 0xff41 },
2479 { 0x02, 0xdf60 },
2480 { 0x01, 0x0140 },
2481 { 0x00, 0x0077 },
2482 { 0x04, 0x7800 },
2483 { 0x04, 0x7000 },
2484
2485 { 0x03, 0x802f },
2486 { 0x02, 0x4f02 },
2487 { 0x01, 0x0409 },
2488 { 0x00, 0xf0f9 },
2489 { 0x04, 0x9800 },
2490 { 0x04, 0x9000 },
2491
2492 { 0x03, 0xdf01 },
2493 { 0x02, 0xdf20 },
2494 { 0x01, 0xff95 },
2495 { 0x00, 0xba00 },
2496 { 0x04, 0xa800 },
2497 { 0x04, 0xa000 },
2498
2499 { 0x03, 0xff41 },
2500 { 0x02, 0xdf20 },
2501 { 0x01, 0x0140 },
2502 { 0x00, 0x00bb },
2503 { 0x04, 0xb800 },
2504 { 0x04, 0xb000 },
2505
2506 { 0x03, 0xdf41 },
2507 { 0x02, 0xdc60 },
2508 { 0x01, 0x6340 },
2509 { 0x00, 0x007d },
2510 { 0x04, 0xd800 },
2511 { 0x04, 0xd000 },
2512
2513 { 0x03, 0xdf01 },
2514 { 0x02, 0xdf20 },
2515 { 0x01, 0x100a },
2516 { 0x00, 0xa0ff },
2517 { 0x04, 0xf800 },
2518 { 0x04, 0xf000 },
2519
2520 { 0x1f, 0x0000 },
2521 { 0x0b, 0x0000 },
2522 { 0x00, 0x9200 }
2523 };
1da177e4 2524
4da19633 2525 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2526}
2527
4da19633 2528static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2529{
350f7596 2530 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2531 { 0x1f, 0x0002 },
2532 { 0x01, 0x90d0 },
2533 { 0x1f, 0x0000 }
2534 };
2535
4da19633 2536 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2537}
2538
4da19633 2539static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2540{
2541 struct pci_dev *pdev = tp->pci_dev;
2e955856 2542
ccbae55e
SS		 2543 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2544 (pdev->subsystem_device != 0xe000))
2e955856 2545 return;
2546
4da19633 2547 rtl_writephy(tp, 0x1f, 0x0001);
2548 rtl_writephy(tp, 0x10, 0xf01b);
2549 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2550}
2551
4da19633 2552static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2553{
350f7596 2554 static const struct phy_reg phy_reg_init[] = {
2e955856 2555 { 0x1f, 0x0001 },
2556 { 0x04, 0x0000 },
2557 { 0x03, 0x00a1 },
2558 { 0x02, 0x0008 },
2559 { 0x01, 0x0120 },
2560 { 0x00, 0x1000 },
2561 { 0x04, 0x0800 },
2562 { 0x04, 0x9000 },
2563 { 0x03, 0x802f },
2564 { 0x02, 0x4f02 },
2565 { 0x01, 0x0409 },
2566 { 0x00, 0xf099 },
2567 { 0x04, 0x9800 },
2568 { 0x04, 0xa000 },
2569 { 0x03, 0xdf01 },
2570 { 0x02, 0xdf20 },
2571 { 0x01, 0xff95 },
2572 { 0x00, 0xba00 },
2573 { 0x04, 0xa800 },
2574 { 0x04, 0xf000 },
2575 { 0x03, 0xdf01 },
2576 { 0x02, 0xdf20 },
2577 { 0x01, 0x101a },
2578 { 0x00, 0xa0ff },
2579 { 0x04, 0xf800 },
2580 { 0x04, 0x0000 },
2581 { 0x1f, 0x0000 },
2582
2583 { 0x1f, 0x0001 },
2584 { 0x10, 0xf41b },
2585 { 0x14, 0xfb54 },
2586 { 0x18, 0xf5c7 },
2587 { 0x1f, 0x0000 },
2588
2589 { 0x1f, 0x0001 },
2590 { 0x17, 0x0cc0 },
2591 { 0x1f, 0x0000 }
2592 };
2593
4da19633 2594 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2595
4da19633 2596 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2597}
2598
4da19633 2599static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2600{
350f7596 2601 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2602 { 0x1f, 0x0001 },
2603 { 0x04, 0x0000 },
2604 { 0x03, 0x00a1 },
2605 { 0x02, 0x0008 },
2606 { 0x01, 0x0120 },
2607 { 0x00, 0x1000 },
2608 { 0x04, 0x0800 },
2609 { 0x04, 0x9000 },
2610 { 0x03, 0x802f },
2611 { 0x02, 0x4f02 },
2612 { 0x01, 0x0409 },
2613 { 0x00, 0xf099 },
2614 { 0x04, 0x9800 },
2615 { 0x04, 0xa000 },
2616 { 0x03, 0xdf01 },
2617 { 0x02, 0xdf20 },
2618 { 0x01, 0xff95 },
2619 { 0x00, 0xba00 },
2620 { 0x04, 0xa800 },
2621 { 0x04, 0xf000 },
2622 { 0x03, 0xdf01 },
2623 { 0x02, 0xdf20 },
2624 { 0x01, 0x101a },
2625 { 0x00, 0xa0ff },
2626 { 0x04, 0xf800 },
2627 { 0x04, 0x0000 },
2628 { 0x1f, 0x0000 },
2629
2630 { 0x1f, 0x0001 },
2631 { 0x0b, 0x8480 },
2632 { 0x1f, 0x0000 },
2633
2634 { 0x1f, 0x0001 },
2635 { 0x18, 0x67c7 },
2636 { 0x04, 0x2000 },
2637 { 0x03, 0x002f },
2638 { 0x02, 0x4360 },
2639 { 0x01, 0x0109 },
2640 { 0x00, 0x3022 },
2641 { 0x04, 0x2800 },
2642 { 0x1f, 0x0000 },
2643
2644 { 0x1f, 0x0001 },
2645 { 0x17, 0x0cc0 },
2646 { 0x1f, 0x0000 }
2647 };
2648
4da19633 2649 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2650}
2651
4da19633 2652static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2653{
350f7596 2654 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2655 { 0x10, 0xf41b },
2656 { 0x1f, 0x0000 }
2657 };
2658
4da19633 2659 rtl_writephy(tp, 0x1f, 0x0001);
2660 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2661
4da19633 2662 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2663}
2664
4da19633 2665static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2666{
350f7596 2667 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2668 { 0x1f, 0x0001 },
2669 { 0x10, 0xf41b },
2670 { 0x1f, 0x0000 }
2671 };
2672
4da19633 2673 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2674}
2675
4da19633 2676static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2677{
350f7596 2678 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2679 { 0x1f, 0x0000 },
2680 { 0x1d, 0x0f00 },
2681 { 0x1f, 0x0002 },
2682 { 0x0c, 0x1ec8 },
2683 { 0x1f, 0x0000 }
2684 };
2685
4da19633 2686 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2687}
2688
4da19633 2689static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2690{
350f7596 2691 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2692 { 0x1f, 0x0001 },
2693 { 0x1d, 0x3d98 },
2694 { 0x1f, 0x0000 }
2695 };
2696
4da19633 2697 rtl_writephy(tp, 0x1f, 0x0000);
2698 rtl_patchphy(tp, 0x14, 1 << 5);
2699 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2700
4da19633 2701 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2702}
2703
4da19633 2704static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2705{
350f7596 2706 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2707 { 0x1f, 0x0001 },
2708 { 0x12, 0x2300 },
867763c1
FR		 2709 { 0x1f, 0x0002 },
2710 { 0x00, 0x88d4 },
2711 { 0x01, 0x82b1 },
2712 { 0x03, 0x7002 },
2713 { 0x08, 0x9e30 },
2714 { 0x09, 0x01f0 },
2715 { 0x0a, 0x5500 },
2716 { 0x0c, 0x00c8 },
2717 { 0x1f, 0x0003 },
2718 { 0x12, 0xc096 },
2719 { 0x16, 0x000a },
f50d4275
FR		 2720 { 0x1f, 0x0000 },
2721 { 0x1f, 0x0000 },
2722 { 0x09, 0x2000 },
2723 { 0x09, 0x0000 }
867763c1
FR		 2724 };
2725
4da19633 2726 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2727
4da19633 2728 rtl_patchphy(tp, 0x14, 1 << 5);
2729 rtl_patchphy(tp, 0x0d, 1 << 5);
2730 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2731}
2732
4da19633 2733static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2734{
350f7596 2735 static const struct phy_reg phy_reg_init[] = {
f50d4275 2736 { 0x1f, 0x0001 },
7da97ec9 2737 { 0x12, 0x2300 },
f50d4275
FR		 2738 { 0x03, 0x802f },
2739 { 0x02, 0x4f02 },
2740 { 0x01, 0x0409 },
2741 { 0x00, 0xf099 },
2742 { 0x04, 0x9800 },
2743 { 0x04, 0x9000 },
2744 { 0x1d, 0x3d98 },
7da97ec9
FR		 2745 { 0x1f, 0x0002 },
2746 { 0x0c, 0x7eb8 },
f50d4275
FR		 2747 { 0x06, 0x0761 },
2748 { 0x1f, 0x0003 },
2749 { 0x16, 0x0f0a },
7da97ec9
FR		 2750 { 0x1f, 0x0000 }
2751 };
2752
4da19633 2753 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2754
4da19633 2755 rtl_patchphy(tp, 0x16, 1 << 0);
2756 rtl_patchphy(tp, 0x14, 1 << 5);
2757 rtl_patchphy(tp, 0x0d, 1 << 5);
2758 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2759}
2760
4da19633 2761static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2762{
350f7596 2763 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2764 { 0x1f, 0x0001 },
2765 { 0x12, 0x2300 },
2766 { 0x1d, 0x3d98 },
2767 { 0x1f, 0x0002 },
2768 { 0x0c, 0x7eb8 },
2769 { 0x06, 0x5461 },
2770 { 0x1f, 0x0003 },
2771 { 0x16, 0x0f0a },
2772 { 0x1f, 0x0000 }
2773 };
2774
4da19633 2775 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2776
4da19633 2777 rtl_patchphy(tp, 0x16, 1 << 0);
2778 rtl_patchphy(tp, 0x14, 1 << 5);
2779 rtl_patchphy(tp, 0x0d, 1 << 5);
2780 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2781}
2782
4da19633 2783static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2784{
4da19633 2785 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2786}
2787
bca03d5f 2788static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2789{
350f7596 2790 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2791 /* Channel Estimation */
5b538df9 2792 { 0x1f, 0x0001 },
daf9df6d 2793 { 0x06, 0x4064 },
2794 { 0x07, 0x2863 },
2795 { 0x08, 0x059c },
2796 { 0x09, 0x26b4 },
2797 { 0x0a, 0x6a19 },
2798 { 0x0b, 0xdcc8 },
2799 { 0x10, 0xf06d },
2800 { 0x14, 0x7f68 },
2801 { 0x18, 0x7fd9 },
2802 { 0x1c, 0xf0ff },
2803 { 0x1d, 0x3d9c },
5b538df9 2804 { 0x1f, 0x0003 },
daf9df6d 2805 { 0x12, 0xf49f },
2806 { 0x13, 0x070b },
2807 { 0x1a, 0x05ad },
bca03d5f 2808 { 0x14, 0x94c0 },
2809
2810 /*
2811 * Tx Error Issue
cecb5fd7 2812 * Enhance line driver power
bca03d5f 2813 */
5b538df9 2814 { 0x1f, 0x0002 },
daf9df6d 2815 { 0x06, 0x5561 },
2816 { 0x1f, 0x0005 },
2817 { 0x05, 0x8332 },
bca03d5f 2818 { 0x06, 0x5561 },
2819
2820 /*
2821 * Can not link to 1Gbps with bad cable
2822 * Decrease SNR threshold form 21.07dB to 19.04dB
2823 */
2824 { 0x1f, 0x0001 },
2825 { 0x17, 0x0cc0 },
daf9df6d 2826
5b538df9 2827 { 0x1f, 0x0000 },
bca03d5f 2828 { 0x0d, 0xf880 }
daf9df6d 2829 };
2830
4da19633 2831 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2832
bca03d5f 2833 /*
2834 * Rx Error Issue
2835 * Fine Tune Switching regulator parameter
2836 */
4da19633 2837 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2838 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2839 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2840
fdf6fc06 2841 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2842 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2843 { 0x1f, 0x0002 },
2844 { 0x05, 0x669a },
2845 { 0x1f, 0x0005 },
2846 { 0x05, 0x8330 },
2847 { 0x06, 0x669a },
2848 { 0x1f, 0x0002 }
2849 };
2850 int val;
2851
4da19633 2852 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2853
4da19633 2854 val = rtl_readphy(tp, 0x0d);
daf9df6d 2855
2856 if ((val & 0x00ff) != 0x006c) {
350f7596 2857 static const u32 set[] = {
daf9df6d 2858 0x0065, 0x0066, 0x0067, 0x0068,
2859 0x0069, 0x006a, 0x006b, 0x006c
2860 };
2861 int i;
2862
4da19633 2863 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2864
2865 val &= 0xff00;
2866 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2867 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2868 }
2869 } else {
350f7596 2870 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2871 { 0x1f, 0x0002 },
2872 { 0x05, 0x6662 },
2873 { 0x1f, 0x0005 },
2874 { 0x05, 0x8330 },
2875 { 0x06, 0x6662 }
2876 };
2877
4da19633 2878 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2879 }
2880
bca03d5f 2881 /* RSET couple improve */
4da19633 2882 rtl_writephy(tp, 0x1f, 0x0002);
2883 rtl_patchphy(tp, 0x0d, 0x0300);
2884 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2885
bca03d5f 2886 /* Fine tune PLL performance */
4da19633 2887 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2888 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2889 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2890
4da19633 2891 rtl_writephy(tp, 0x1f, 0x0005);
2892 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2893
2894 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2895
4da19633 2896 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2897}
2898
bca03d5f 2899static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2900{
350f7596 2901 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2902 /* Channel Estimation */
daf9df6d 2903 { 0x1f, 0x0001 },
2904 { 0x06, 0x4064 },
2905 { 0x07, 0x2863 },
2906 { 0x08, 0x059c },
2907 { 0x09, 0x26b4 },
2908 { 0x0a, 0x6a19 },
2909 { 0x0b, 0xdcc8 },
2910 { 0x10, 0xf06d },
2911 { 0x14, 0x7f68 },
2912 { 0x18, 0x7fd9 },
2913 { 0x1c, 0xf0ff },
2914 { 0x1d, 0x3d9c },
2915 { 0x1f, 0x0003 },
2916 { 0x12, 0xf49f },
2917 { 0x13, 0x070b },
2918 { 0x1a, 0x05ad },
2919 { 0x14, 0x94c0 },
2920
bca03d5f 2921 /*
2922 * Tx Error Issue
cecb5fd7 2923 * Enhance line driver power
bca03d5f 2924 */
daf9df6d 2925 { 0x1f, 0x0002 },
2926 { 0x06, 0x5561 },
2927 { 0x1f, 0x0005 },
2928 { 0x05, 0x8332 },
bca03d5f 2929 { 0x06, 0x5561 },
2930
2931 /*
2932 * Can not link to 1Gbps with bad cable
2933 * Decrease SNR threshold form 21.07dB to 19.04dB
2934 */
2935 { 0x1f, 0x0001 },
2936 { 0x17, 0x0cc0 },
daf9df6d 2937
2938 { 0x1f, 0x0000 },
bca03d5f 2939 { 0x0d, 0xf880 }
5b538df9
FR		 2940 };
2941
4da19633 2942 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2943
fdf6fc06 2944 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2945 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2946 { 0x1f, 0x0002 },
2947 { 0x05, 0x669a },
5b538df9 2948 { 0x1f, 0x0005 },
daf9df6d 2949 { 0x05, 0x8330 },
2950 { 0x06, 0x669a },
2951
2952 { 0x1f, 0x0002 }
2953 };
2954 int val;
2955
4da19633 2956 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2957
4da19633 2958 val = rtl_readphy(tp, 0x0d);
daf9df6d 2959 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2960 static const u32 set[] = {
daf9df6d 2961 0x0065, 0x0066, 0x0067, 0x0068,
2962 0x0069, 0x006a, 0x006b, 0x006c
2963 };
2964 int i;
2965
4da19633 2966 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2967
2968 val &= 0xff00;
2969 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2970 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2971 }
2972 } else {
350f7596 2973 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2974 { 0x1f, 0x0002 },
2975 { 0x05, 0x2642 },
5b538df9 2976 { 0x1f, 0x0005 },
daf9df6d 2977 { 0x05, 0x8330 },
2978 { 0x06, 0x2642 }
5b538df9
FR		 2979 };
2980
4da19633 2981 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2982 }
2983
bca03d5f 2984 /* Fine tune PLL performance */
4da19633 2985 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2986 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2987 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2988
bca03d5f 2989 /* Switching regulator Slew rate */
4da19633 2990 rtl_writephy(tp, 0x1f, 0x0002);
2991 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2992
4da19633 2993 rtl_writephy(tp, 0x1f, 0x0005);
2994 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2995
2996 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2997
4da19633 2998 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2999}
3000
4da19633 3001static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3002{
350f7596 3003 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3004 { 0x1f, 0x0002 },
3005 { 0x10, 0x0008 },
3006 { 0x0d, 0x006c },
3007
3008 { 0x1f, 0x0000 },
3009 { 0x0d, 0xf880 },
3010
3011 { 0x1f, 0x0001 },
3012 { 0x17, 0x0cc0 },
3013
3014 { 0x1f, 0x0001 },
3015 { 0x0b, 0xa4d8 },
3016 { 0x09, 0x281c },
3017 { 0x07, 0x2883 },
3018 { 0x0a, 0x6b35 },
3019 { 0x1d, 0x3da4 },
3020 { 0x1c, 0xeffd },
3021 { 0x14, 0x7f52 },
3022 { 0x18, 0x7fc6 },
3023 { 0x08, 0x0601 },
3024 { 0x06, 0x4063 },
3025 { 0x10, 0xf074 },
3026 { 0x1f, 0x0003 },
3027 { 0x13, 0x0789 },
3028 { 0x12, 0xf4bd },
3029 { 0x1a, 0x04fd },
3030 { 0x14, 0x84b0 },
3031 { 0x1f, 0x0000 },
3032 { 0x00, 0x9200 },
3033
3034 { 0x1f, 0x0005 },
3035 { 0x01, 0x0340 },
3036 { 0x1f, 0x0001 },
3037 { 0x04, 0x4000 },
3038 { 0x03, 0x1d21 },
3039 { 0x02, 0x0c32 },
3040 { 0x01, 0x0200 },
3041 { 0x00, 0x5554 },
3042 { 0x04, 0x4800 },
3043 { 0x04, 0x4000 },
3044 { 0x04, 0xf000 },
3045 { 0x03, 0xdf01 },
3046 { 0x02, 0xdf20 },
3047 { 0x01, 0x101a },
3048 { 0x00, 0xa0ff },
3049 { 0x04, 0xf800 },
3050 { 0x04, 0xf000 },
3051 { 0x1f, 0x0000 },
3052
3053 { 0x1f, 0x0007 },
3054 { 0x1e, 0x0023 },
3055 { 0x16, 0x0000 },
3056 { 0x1f, 0x0000 }
3057 };
3058
4da19633 3059 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3060}
3061
e6de30d6 3062static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3063{
3064 static const struct phy_reg phy_reg_init[] = {
3065 { 0x1f, 0x0001 },
3066 { 0x17, 0x0cc0 },
3067
3068 { 0x1f, 0x0007 },
3069 { 0x1e, 0x002d },
3070 { 0x18, 0x0040 },
3071 { 0x1f, 0x0000 }
3072 };
3073
3074 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3075 rtl_patchphy(tp, 0x0d, 1 << 5);
3076}
3077
70090424 3078static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3079{
3080 static const struct phy_reg phy_reg_init[] = {
3081 /* Enable Delay cap */
3082 { 0x1f, 0x0005 },
3083 { 0x05, 0x8b80 },
3084 { 0x06, 0xc896 },
3085 { 0x1f, 0x0000 },
3086
3087 /* Channel estimation fine tune */
3088 { 0x1f, 0x0001 },
3089 { 0x0b, 0x6c20 },
3090 { 0x07, 0x2872 },
3091 { 0x1c, 0xefff },
3092 { 0x1f, 0x0003 },
3093 { 0x14, 0x6420 },
3094 { 0x1f, 0x0000 },
3095
3096 /* Update PFM & 10M TX idle timer */
3097 { 0x1f, 0x0007 },
3098 { 0x1e, 0x002f },
3099 { 0x15, 0x1919 },
3100 { 0x1f, 0x0000 },
3101
3102 { 0x1f, 0x0007 },
3103 { 0x1e, 0x00ac },
3104 { 0x18, 0x0006 },
3105 { 0x1f, 0x0000 }
3106 };
3107
15ecd039
FR		 3108 rtl_apply_firmware(tp);
3109
01dc7fec 3110 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3111
3112 /* DCO enable for 10M IDLE Power */
3113 rtl_writephy(tp, 0x1f, 0x0007);
3114 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3115 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3116 rtl_writephy(tp, 0x1f, 0x0000);
3117
3118 /* For impedance matching */
3119 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3120 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3121 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3122
3123 /* PHY auto speed down */
3124 rtl_writephy(tp, 0x1f, 0x0007);
3125 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3126 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3127 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3128 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3129
3130 rtl_writephy(tp, 0x1f, 0x0005);
3131 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3132 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3133 rtl_writephy(tp, 0x1f, 0x0000);
3134
3135 rtl_writephy(tp, 0x1f, 0x0005);
3136 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3137 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3138 rtl_writephy(tp, 0x1f, 0x0007);
3139 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3140 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3141 rtl_writephy(tp, 0x1f, 0x0006);
3142 rtl_writephy(tp, 0x00, 0x5a00);
3143 rtl_writephy(tp, 0x1f, 0x0000);
3144 rtl_writephy(tp, 0x0d, 0x0007);
3145 rtl_writephy(tp, 0x0e, 0x003c);
3146 rtl_writephy(tp, 0x0d, 0x4007);
3147 rtl_writephy(tp, 0x0e, 0x0000);
3148 rtl_writephy(tp, 0x0d, 0x0000);
3149}
3150
9ecb9aab 3151static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3152{
3153 const u16 w[] = {
3154 addr[0] | (addr[1] << 8),
3155 addr[2] | (addr[3] << 8),
3156 addr[4] | (addr[5] << 8)
3157 };
3158 const struct exgmac_reg e[] = {
3159 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3160 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3161 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3162 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3163 };
3164
3165 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3166}
3167
70090424
HW		 3168static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3169{
3170 static const struct phy_reg phy_reg_init[] = {
3171 /* Enable Delay cap */
3172 { 0x1f, 0x0004 },
3173 { 0x1f, 0x0007 },
3174 { 0x1e, 0x00ac },
3175 { 0x18, 0x0006 },
3176 { 0x1f, 0x0002 },
3177 { 0x1f, 0x0000 },
3178 { 0x1f, 0x0000 },
3179
3180 /* Channel estimation fine tune */
3181 { 0x1f, 0x0003 },
3182 { 0x09, 0xa20f },
3183 { 0x1f, 0x0000 },
3184 { 0x1f, 0x0000 },
3185
3186 /* Green Setting */
3187 { 0x1f, 0x0005 },
3188 { 0x05, 0x8b5b },
3189 { 0x06, 0x9222 },
3190 { 0x05, 0x8b6d },
3191 { 0x06, 0x8000 },
3192 { 0x05, 0x8b76 },
3193 { 0x06, 0x8000 },
3194 { 0x1f, 0x0000 }
3195 };
3196
3197 rtl_apply_firmware(tp);
3198
3199 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3200
3201 /* For 4-corner performance improve */
3202 rtl_writephy(tp, 0x1f, 0x0005);
3203 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3204 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3205 rtl_writephy(tp, 0x1f, 0x0000);
3206
3207 /* PHY auto speed down */
3208 rtl_writephy(tp, 0x1f, 0x0004);
3209 rtl_writephy(tp, 0x1f, 0x0007);
3210 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3211 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3212 rtl_writephy(tp, 0x1f, 0x0002);
3213 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3214 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3215
3216 /* improve 10M EEE waveform */
3217 rtl_writephy(tp, 0x1f, 0x0005);
3218 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3219 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3220 rtl_writephy(tp, 0x1f, 0x0000);
3221
3222 /* Improve 2-pair detection performance */
3223 rtl_writephy(tp, 0x1f, 0x0005);
3224 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3225 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3226 rtl_writephy(tp, 0x1f, 0x0000);
3227
3228 /* EEE setting */
1814d6a8 3229 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
70090424
HW		 3230 rtl_writephy(tp, 0x1f, 0x0005);
3231 rtl_writephy(tp, 0x05, 0x8b85);
1814d6a8 3232 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
70090424
HW		 3233 rtl_writephy(tp, 0x1f, 0x0004);
3234 rtl_writephy(tp, 0x1f, 0x0007);
3235 rtl_writephy(tp, 0x1e, 0x0020);
1814d6a8 3236 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
70090424
HW		 3237 rtl_writephy(tp, 0x1f, 0x0002);
3238 rtl_writephy(tp, 0x1f, 0x0000);
3239 rtl_writephy(tp, 0x0d, 0x0007);
3240 rtl_writephy(tp, 0x0e, 0x003c);
3241 rtl_writephy(tp, 0x0d, 0x4007);
1814d6a8 3242 rtl_writephy(tp, 0x0e, 0x0006);
70090424
HW		 3243 rtl_writephy(tp, 0x0d, 0x0000);
3244
3245 /* Green feature */
3246 rtl_writephy(tp, 0x1f, 0x0003);
1814d6a8
HK		 3247 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3248 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
70090424 3249 rtl_writephy(tp, 0x1f, 0x0000);
b399a394
HK		 3250 rtl_writephy(tp, 0x1f, 0x0005);
3251 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3252 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3253
9ecb9aab 3254 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3255 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3256}
3257
5f886e08
HW		 3258static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3259{
3260 /* For 4-corner performance improve */
3261 rtl_writephy(tp, 0x1f, 0x0005);
3262 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3263 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3264 rtl_writephy(tp, 0x1f, 0x0000);
3265
3266 /* PHY auto speed down */
3267 rtl_writephy(tp, 0x1f, 0x0007);
3268 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3269 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3270 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3271 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3272
3273 /* Improve 10M EEE waveform */
3274 rtl_writephy(tp, 0x1f, 0x0005);
3275 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3276 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3277 rtl_writephy(tp, 0x1f, 0x0000);
3278}
3279
c2218925
HW		 3280static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3281{
3282 static const struct phy_reg phy_reg_init[] = {
3283 /* Channel estimation fine tune */
3284 { 0x1f, 0x0003 },
3285 { 0x09, 0xa20f },
3286 { 0x1f, 0x0000 },
3287
3288 /* Modify green table for giga & fnet */
3289 { 0x1f, 0x0005 },
3290 { 0x05, 0x8b55 },
3291 { 0x06, 0x0000 },
3292 { 0x05, 0x8b5e },
3293 { 0x06, 0x0000 },
3294 { 0x05, 0x8b67 },
3295 { 0x06, 0x0000 },
3296 { 0x05, 0x8b70 },
3297 { 0x06, 0x0000 },
3298 { 0x1f, 0x0000 },
3299 { 0x1f, 0x0007 },
3300 { 0x1e, 0x0078 },
3301 { 0x17, 0x0000 },
3302 { 0x19, 0x00fb },
3303 { 0x1f, 0x0000 },
3304
3305 /* Modify green table for 10M */
3306 { 0x1f, 0x0005 },
3307 { 0x05, 0x8b79 },
3308 { 0x06, 0xaa00 },
3309 { 0x1f, 0x0000 },
3310
3311 /* Disable hiimpedance detection (RTCT) */
3312 { 0x1f, 0x0003 },
3313 { 0x01, 0x328a },
3314 { 0x1f, 0x0000 }
3315 };
3316
3317 rtl_apply_firmware(tp);
3318
3319 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3320
5f886e08 3321 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3322
3323 /* Improve 2-pair detection performance */
3324 rtl_writephy(tp, 0x1f, 0x0005);
3325 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3326 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3327 rtl_writephy(tp, 0x1f, 0x0000);
3328}
3329
3330static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3331{
3332 rtl_apply_firmware(tp);
3333
5f886e08 3334 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3335}
3336
b3d7b2f2
HW		 3337static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3338{
b3d7b2f2
HW		 3339 static const struct phy_reg phy_reg_init[] = {
3340 /* Channel estimation fine tune */
3341 { 0x1f, 0x0003 },
3342 { 0x09, 0xa20f },
3343 { 0x1f, 0x0000 },
3344
3345 /* Modify green table for giga & fnet */
3346 { 0x1f, 0x0005 },
3347 { 0x05, 0x8b55 },
3348 { 0x06, 0x0000 },
3349 { 0x05, 0x8b5e },
3350 { 0x06, 0x0000 },
3351 { 0x05, 0x8b67 },
3352 { 0x06, 0x0000 },
3353 { 0x05, 0x8b70 },
3354 { 0x06, 0x0000 },
3355 { 0x1f, 0x0000 },
3356 { 0x1f, 0x0007 },
3357 { 0x1e, 0x0078 },
3358 { 0x17, 0x0000 },
3359 { 0x19, 0x00aa },
3360 { 0x1f, 0x0000 },
3361
3362 /* Modify green table for 10M */
3363 { 0x1f, 0x0005 },
3364 { 0x05, 0x8b79 },
3365 { 0x06, 0xaa00 },
3366 { 0x1f, 0x0000 },
3367
3368 /* Disable hiimpedance detection (RTCT) */
3369 { 0x1f, 0x0003 },
3370 { 0x01, 0x328a },
3371 { 0x1f, 0x0000 }
3372 };
3373
3374
3375 rtl_apply_firmware(tp);
3376
3377 rtl8168f_hw_phy_config(tp);
3378
3379 /* Improve 2-pair detection performance */
3380 rtl_writephy(tp, 0x1f, 0x0005);
3381 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3382 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3383 rtl_writephy(tp, 0x1f, 0x0000);
3384
3385 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3386
3387 /* Modify green table for giga */
3388 rtl_writephy(tp, 0x1f, 0x0005);
3389 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3390 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3391 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3392 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3393 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3394 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3395 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3396 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3397 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3398 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3399 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3400 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3401 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3402 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3403 rtl_writephy(tp, 0x1f, 0x0000);
3404
3405 /* uc same-seed solution */
3406 rtl_writephy(tp, 0x1f, 0x0005);
3407 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3408 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3409 rtl_writephy(tp, 0x1f, 0x0000);
3410
3411 /* eee setting */
706123d0 3412 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3413 rtl_writephy(tp, 0x1f, 0x0005);
3414 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3415 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3416 rtl_writephy(tp, 0x1f, 0x0004);
3417 rtl_writephy(tp, 0x1f, 0x0007);
3418 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3419 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3420 rtl_writephy(tp, 0x1f, 0x0000);
3421 rtl_writephy(tp, 0x0d, 0x0007);
3422 rtl_writephy(tp, 0x0e, 0x003c);
3423 rtl_writephy(tp, 0x0d, 0x4007);
3424 rtl_writephy(tp, 0x0e, 0x0000);
3425 rtl_writephy(tp, 0x0d, 0x0000);
3426
3427 /* Green feature */
3428 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3429 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3430 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3431 rtl_writephy(tp, 0x1f, 0x0000);
3432}
3433
c558386b
HW		 3434static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3435{
c558386b
HW		 3436 rtl_apply_firmware(tp);
3437
41f44d13 3438 rtl_writephy(tp, 0x1f, 0x0a46);
3439 if (rtl_readphy(tp, 0x10) & 0x0100) {
3440 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3441 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3442 } else {
3443 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3444 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3445 }
c558386b 3446
41f44d13 3447 rtl_writephy(tp, 0x1f, 0x0a46);
3448 if (rtl_readphy(tp, 0x13) & 0x0100) {
3449 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3450 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 3451 } else {
fe7524c0 3452 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3453 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3454 }
c558386b 3455
41f44d13 3456 /* Enable PHY auto speed down */
3457 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3458 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3459
fe7524c0 3460 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3461 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 3462 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3463 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 3464 rtl_writephy(tp, 0x1f, 0x0a43);
3465 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 3466 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3467 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 3468
41f44d13 3469 /* EEE auto-fallback function */
3470 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 3471 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3472
41f44d13 3473 /* Enable UC LPF tune function */
3474 rtl_writephy(tp, 0x1f, 0x0a43);
3475 rtl_writephy(tp, 0x13, 0x8012);
76564428 3476 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 3477
3478 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 3479 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 3480
fe7524c0 3481 /* Improve SWR Efficiency */
3482 rtl_writephy(tp, 0x1f, 0x0bcd);
3483 rtl_writephy(tp, 0x14, 0x5065);
3484 rtl_writephy(tp, 0x14, 0xd065);
3485 rtl_writephy(tp, 0x1f, 0x0bc8);
3486 rtl_writephy(tp, 0x11, 0x5655);
3487 rtl_writephy(tp, 0x1f, 0x0bcd);
3488 rtl_writephy(tp, 0x14, 0x1065);
3489 rtl_writephy(tp, 0x14, 0x9065);
3490 rtl_writephy(tp, 0x14, 0x1065);
3491
1bac1072
DC		 3492 /* Check ALDPS bit, disable it if enabled */
3493 rtl_writephy(tp, 0x1f, 0x0a43);
3494 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3495 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 3496
41f44d13 3497 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3498}
3499
57538c4a 3500static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3501{
3502 rtl_apply_firmware(tp);
3503}
3504
6e1d0b89
CHL		 3505static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3506{
3507 u16 dout_tapbin;
3508 u32 data;
3509
3510 rtl_apply_firmware(tp);
3511
3512 /* CHN EST parameters adjust - giga master */
3513 rtl_writephy(tp, 0x1f, 0x0a43);
3514 rtl_writephy(tp, 0x13, 0x809b);
76564428 3515 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 3516 rtl_writephy(tp, 0x13, 0x80a2);
76564428 3517 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 3518 rtl_writephy(tp, 0x13, 0x80a4);
76564428 3519 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 3520 rtl_writephy(tp, 0x13, 0x809c);
76564428 3521 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 3522 rtl_writephy(tp, 0x1f, 0x0000);
3523
3524 /* CHN EST parameters adjust - giga slave */
3525 rtl_writephy(tp, 0x1f, 0x0a43);
3526 rtl_writephy(tp, 0x13, 0x80ad);
76564428 3527 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 3528 rtl_writephy(tp, 0x13, 0x80b4);
76564428 3529 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 3530 rtl_writephy(tp, 0x13, 0x80ac);
76564428 3531 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 3532 rtl_writephy(tp, 0x1f, 0x0000);
3533
3534 /* CHN EST parameters adjust - fnet */
3535 rtl_writephy(tp, 0x1f, 0x0a43);
3536 rtl_writephy(tp, 0x13, 0x808e);
76564428 3537 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 3538 rtl_writephy(tp, 0x13, 0x8090);
76564428 3539 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 3540 rtl_writephy(tp, 0x13, 0x8092);
76564428 3541 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 3542 rtl_writephy(tp, 0x1f, 0x0000);
3543
3544 /* enable R-tune & PGA-retune function */
3545 dout_tapbin = 0;
3546 rtl_writephy(tp, 0x1f, 0x0a46);
3547 data = rtl_readphy(tp, 0x13);
3548 data &= 3;
3549 data <<= 2;
3550 dout_tapbin |= data;
3551 data = rtl_readphy(tp, 0x12);
3552 data &= 0xc000;
3553 data >>= 14;
3554 dout_tapbin |= data;
3555 dout_tapbin = ~(dout_tapbin^0x08);
3556 dout_tapbin <<= 12;
3557 dout_tapbin &= 0xf000;
3558 rtl_writephy(tp, 0x1f, 0x0a43);
3559 rtl_writephy(tp, 0x13, 0x827a);
76564428 3560 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3561 rtl_writephy(tp, 0x13, 0x827b);
76564428 3562 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3563 rtl_writephy(tp, 0x13, 0x827c);
76564428 3564 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3565 rtl_writephy(tp, 0x13, 0x827d);
76564428 3566 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 3567
3568 rtl_writephy(tp, 0x1f, 0x0a43);
3569 rtl_writephy(tp, 0x13, 0x0811);
76564428 3570 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3571 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3572 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3573 rtl_writephy(tp, 0x1f, 0x0000);
3574
3575 /* enable GPHY 10M */
3576 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3577 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3578 rtl_writephy(tp, 0x1f, 0x0000);
3579
3580 /* SAR ADC performance */
3581 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 3582 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 3583 rtl_writephy(tp, 0x1f, 0x0000);
3584
3585 rtl_writephy(tp, 0x1f, 0x0a43);
3586 rtl_writephy(tp, 0x13, 0x803f);
76564428 3587 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3588 rtl_writephy(tp, 0x13, 0x8047);
76564428 3589 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3590 rtl_writephy(tp, 0x13, 0x804f);
76564428 3591 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3592 rtl_writephy(tp, 0x13, 0x8057);
76564428 3593 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3594 rtl_writephy(tp, 0x13, 0x805f);
76564428 3595 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3596 rtl_writephy(tp, 0x13, 0x8067);
76564428 3597 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3598 rtl_writephy(tp, 0x13, 0x806f);
76564428 3599 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 3600 rtl_writephy(tp, 0x1f, 0x0000);
3601
3602 /* disable phy pfm mode */
3603 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3604 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3605 rtl_writephy(tp, 0x1f, 0x0000);
3606
3607 /* Check ALDPS bit, disable it if enabled */
3608 rtl_writephy(tp, 0x1f, 0x0a43);
3609 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3610 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3611
3612 rtl_writephy(tp, 0x1f, 0x0000);
3613}
3614
3615static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3616{
3617 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3618 u16 rlen;
3619 u32 data;
3620
3621 rtl_apply_firmware(tp);
3622
3623 /* CHIN EST parameter update */
3624 rtl_writephy(tp, 0x1f, 0x0a43);
3625 rtl_writephy(tp, 0x13, 0x808a);
76564428 3626 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 3627 rtl_writephy(tp, 0x1f, 0x0000);
3628
3629 /* enable R-tune & PGA-retune function */
3630 rtl_writephy(tp, 0x1f, 0x0a43);
3631 rtl_writephy(tp, 0x13, 0x0811);
76564428 3632 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3633 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3634 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3635 rtl_writephy(tp, 0x1f, 0x0000);
3636
3637 /* enable GPHY 10M */
3638 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3639 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3640 rtl_writephy(tp, 0x1f, 0x0000);
3641
3642 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3643 data = r8168_mac_ocp_read(tp, 0xdd02);
3644 ioffset_p3 = ((data & 0x80)>>7);
3645 ioffset_p3 <<= 3;
3646
3647 data = r8168_mac_ocp_read(tp, 0xdd00);
3648 ioffset_p3 |= ((data & (0xe000))>>13);
3649 ioffset_p2 = ((data & (0x1e00))>>9);
3650 ioffset_p1 = ((data & (0x01e0))>>5);
3651 ioffset_p0 = ((data & 0x0010)>>4);
3652 ioffset_p0 <<= 3;
3653 ioffset_p0 |= (data & (0x07));
3654 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3655
05b9687b 3656 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
e2e2788e 3657 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
6e1d0b89
CHL		 3658 rtl_writephy(tp, 0x1f, 0x0bcf);
3659 rtl_writephy(tp, 0x16, data);
3660 rtl_writephy(tp, 0x1f, 0x0000);
3661 }
3662
3663 /* Modify rlen (TX LPF corner frequency) level */
3664 rtl_writephy(tp, 0x1f, 0x0bcd);
3665 data = rtl_readphy(tp, 0x16);
3666 data &= 0x000f;
3667 rlen = 0;
3668 if (data > 3)
3669 rlen = data - 3;
3670 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3671 rtl_writephy(tp, 0x17, data);
3672 rtl_writephy(tp, 0x1f, 0x0bcd);
3673 rtl_writephy(tp, 0x1f, 0x0000);
3674
3675 /* disable phy pfm mode */
3676 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3677 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3678 rtl_writephy(tp, 0x1f, 0x0000);
3679
3680 /* Check ALDPS bit, disable it if enabled */
3681 rtl_writephy(tp, 0x1f, 0x0a43);
3682 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3683 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3684
3685 rtl_writephy(tp, 0x1f, 0x0000);
3686}
3687
935e2218
CHL		 3688static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3689{
3690 /* Enable PHY auto speed down */
3691 rtl_writephy(tp, 0x1f, 0x0a44);
3692 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3693 rtl_writephy(tp, 0x1f, 0x0000);
3694
3695 /* patch 10M & ALDPS */
3696 rtl_writephy(tp, 0x1f, 0x0bcc);
3697 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3698 rtl_writephy(tp, 0x1f, 0x0a44);
3699 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3700 rtl_writephy(tp, 0x1f, 0x0a43);
3701 rtl_writephy(tp, 0x13, 0x8084);
3702 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3703 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3704 rtl_writephy(tp, 0x1f, 0x0000);
3705
3706 /* Enable EEE auto-fallback function */
3707 rtl_writephy(tp, 0x1f, 0x0a4b);
3708 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3709 rtl_writephy(tp, 0x1f, 0x0000);
3710
3711 /* Enable UC LPF tune function */
3712 rtl_writephy(tp, 0x1f, 0x0a43);
3713 rtl_writephy(tp, 0x13, 0x8012);
3714 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3715 rtl_writephy(tp, 0x1f, 0x0000);
3716
3717 /* set rg_sel_sdm_rate */
3718 rtl_writephy(tp, 0x1f, 0x0c42);
3719 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3720 rtl_writephy(tp, 0x1f, 0x0000);
3721
3722 /* Check ALDPS bit, disable it if enabled */
3723 rtl_writephy(tp, 0x1f, 0x0a43);
3724 if (rtl_readphy(tp, 0x10) & 0x0004)
3725 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3726
3727 rtl_writephy(tp, 0x1f, 0x0000);
3728}
3729
3730static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3731{
3732 /* patch 10M & ALDPS */
3733 rtl_writephy(tp, 0x1f, 0x0bcc);
3734 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3735 rtl_writephy(tp, 0x1f, 0x0a44);
3736 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3737 rtl_writephy(tp, 0x1f, 0x0a43);
3738 rtl_writephy(tp, 0x13, 0x8084);
3739 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3740 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3741 rtl_writephy(tp, 0x1f, 0x0000);
3742
3743 /* Enable UC LPF tune function */
3744 rtl_writephy(tp, 0x1f, 0x0a43);
3745 rtl_writephy(tp, 0x13, 0x8012);
3746 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3747 rtl_writephy(tp, 0x1f, 0x0000);
3748
3749 /* Set rg_sel_sdm_rate */
3750 rtl_writephy(tp, 0x1f, 0x0c42);
3751 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3752 rtl_writephy(tp, 0x1f, 0x0000);
3753
3754 /* Channel estimation parameters */
3755 rtl_writephy(tp, 0x1f, 0x0a43);
3756 rtl_writephy(tp, 0x13, 0x80f3);
3757 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3758 rtl_writephy(tp, 0x13, 0x80f0);
3759 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3760 rtl_writephy(tp, 0x13, 0x80ef);
3761 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3762 rtl_writephy(tp, 0x13, 0x80f6);
3763 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3764 rtl_writephy(tp, 0x13, 0x80ec);
3765 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3766 rtl_writephy(tp, 0x13, 0x80ed);
3767 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3768 rtl_writephy(tp, 0x13, 0x80f2);
3769 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3770 rtl_writephy(tp, 0x13, 0x80f4);
3771 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3772 rtl_writephy(tp, 0x1f, 0x0a43);
3773 rtl_writephy(tp, 0x13, 0x8110);
3774 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3775 rtl_writephy(tp, 0x13, 0x810f);
3776 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3777 rtl_writephy(tp, 0x13, 0x8111);
3778 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3779 rtl_writephy(tp, 0x13, 0x8113);
3780 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3781 rtl_writephy(tp, 0x13, 0x8115);
3782 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3783 rtl_writephy(tp, 0x13, 0x810e);
3784 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3785 rtl_writephy(tp, 0x13, 0x810c);
3786 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3787 rtl_writephy(tp, 0x13, 0x810b);
3788 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3789 rtl_writephy(tp, 0x1f, 0x0a43);
3790 rtl_writephy(tp, 0x13, 0x80d1);
3791 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3792 rtl_writephy(tp, 0x13, 0x80cd);
3793 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3794 rtl_writephy(tp, 0x13, 0x80d3);
3795 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3796 rtl_writephy(tp, 0x13, 0x80d5);
3797 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3798 rtl_writephy(tp, 0x13, 0x80d7);
3799 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3800
3801 /* Force PWM-mode */
3802 rtl_writephy(tp, 0x1f, 0x0bcd);
3803 rtl_writephy(tp, 0x14, 0x5065);
3804 rtl_writephy(tp, 0x14, 0xd065);
3805 rtl_writephy(tp, 0x1f, 0x0bc8);
3806 rtl_writephy(tp, 0x12, 0x00ed);
3807 rtl_writephy(tp, 0x1f, 0x0bcd);
3808 rtl_writephy(tp, 0x14, 0x1065);
3809 rtl_writephy(tp, 0x14, 0x9065);
3810 rtl_writephy(tp, 0x14, 0x1065);
3811 rtl_writephy(tp, 0x1f, 0x0000);
3812
3813 /* Check ALDPS bit, disable it if enabled */
3814 rtl_writephy(tp, 0x1f, 0x0a43);
3815 if (rtl_readphy(tp, 0x10) & 0x0004)
3816 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3817
3818 rtl_writephy(tp, 0x1f, 0x0000);
3819}
3820
4da19633 3821static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3822{
350f7596 3823 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3824 { 0x1f, 0x0003 },
3825 { 0x08, 0x441d },
3826 { 0x01, 0x9100 },
3827 { 0x1f, 0x0000 }
3828 };
3829
4da19633 3830 rtl_writephy(tp, 0x1f, 0x0000);
3831 rtl_patchphy(tp, 0x11, 1 << 12);
3832 rtl_patchphy(tp, 0x19, 1 << 13);
3833 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3834
4da19633 3835 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3836}
3837
5a5e4443
HW		 3838static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3839{
3840 static const struct phy_reg phy_reg_init[] = {
3841 { 0x1f, 0x0005 },
3842 { 0x1a, 0x0000 },
3843 { 0x1f, 0x0000 },
3844
3845 { 0x1f, 0x0004 },
3846 { 0x1c, 0x0000 },
3847 { 0x1f, 0x0000 },
3848
3849 { 0x1f, 0x0001 },
3850 { 0x15, 0x7701 },
3851 { 0x1f, 0x0000 }
3852 };
3853
3854 /* Disable ALDPS before ram code */
eef63cc1
FR		 3855 rtl_writephy(tp, 0x1f, 0x0000);
3856 rtl_writephy(tp, 0x18, 0x0310);
3857 msleep(100);
5a5e4443 3858
953a12cc 3859 rtl_apply_firmware(tp);
5a5e4443
HW		 3860
3861 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3862}
3863
7e18dca1
HW		 3864static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3865{
7e18dca1 3866 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3867 rtl_writephy(tp, 0x1f, 0x0000);
3868 rtl_writephy(tp, 0x18, 0x0310);
3869 msleep(20);
7e18dca1
HW		 3870
3871 rtl_apply_firmware(tp);
3872
3873 /* EEE setting */
fdf6fc06 3874 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3875 rtl_writephy(tp, 0x1f, 0x0004);
3876 rtl_writephy(tp, 0x10, 0x401f);
3877 rtl_writephy(tp, 0x19, 0x7030);
3878 rtl_writephy(tp, 0x1f, 0x0000);
3879}
3880
5598bfe5
HW		 3881static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3882{
5598bfe5
HW		 3883 static const struct phy_reg phy_reg_init[] = {
3884 { 0x1f, 0x0004 },
3885 { 0x10, 0xc07f },
3886 { 0x19, 0x7030 },
3887 { 0x1f, 0x0000 }
3888 };
3889
3890 /* Disable ALDPS before ram code */
eef63cc1
FR		 3891 rtl_writephy(tp, 0x1f, 0x0000);
3892 rtl_writephy(tp, 0x18, 0x0310);
3893 msleep(100);
5598bfe5
HW		 3894
3895 rtl_apply_firmware(tp);
3896
fdf6fc06 3897 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3898 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3899
fdf6fc06 3900 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3901}
3902
5615d9f1
FR		 3903static void rtl_hw_phy_config(struct net_device *dev)
3904{
3905 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3906
3907 rtl8169_print_mac_version(tp);
3908
3909 switch (tp->mac_version) {
3910 case RTL_GIGA_MAC_VER_01:
3911 break;
3912 case RTL_GIGA_MAC_VER_02:
3913 case RTL_GIGA_MAC_VER_03:
4da19633 3914 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3915 break;
3916 case RTL_GIGA_MAC_VER_04:
4da19633 3917 rtl8169sb_hw_phy_config(tp);
5615d9f1 3918 break;
2e955856 3919 case RTL_GIGA_MAC_VER_05:
4da19633 3920 rtl8169scd_hw_phy_config(tp);
2e955856 3921 break;
8c7006aa 3922 case RTL_GIGA_MAC_VER_06:
4da19633 3923 rtl8169sce_hw_phy_config(tp);
8c7006aa 3924 break;
2857ffb7
FR		 3925 case RTL_GIGA_MAC_VER_07:
3926 case RTL_GIGA_MAC_VER_08:
3927 case RTL_GIGA_MAC_VER_09:
4da19633 3928 rtl8102e_hw_phy_config(tp);
2857ffb7 3929 break;
236b8082 3930 case RTL_GIGA_MAC_VER_11:
4da19633 3931 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3932 break;
3933 case RTL_GIGA_MAC_VER_12:
4da19633 3934 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3935 break;
3936 case RTL_GIGA_MAC_VER_17:
4da19633 3937 rtl8168bef_hw_phy_config(tp);
236b8082 3938 break;
867763c1 3939 case RTL_GIGA_MAC_VER_18:
4da19633 3940 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3941 break;
3942 case RTL_GIGA_MAC_VER_19:
4da19633 3943 rtl8168c_1_hw_phy_config(tp);
867763c1 3944 break;
7da97ec9 3945 case RTL_GIGA_MAC_VER_20:
4da19633 3946 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3947 break;
197ff761 3948 case RTL_GIGA_MAC_VER_21:
4da19633 3949 rtl8168c_3_hw_phy_config(tp);
197ff761 3950 break;
6fb07058 3951 case RTL_GIGA_MAC_VER_22:
4da19633 3952 rtl8168c_4_hw_phy_config(tp);
6fb07058 3953 break;
ef3386f0 3954 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3955 case RTL_GIGA_MAC_VER_24:
4da19633 3956 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3957 break;
5b538df9 3958 case RTL_GIGA_MAC_VER_25:
bca03d5f 3959 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3960 break;
3961 case RTL_GIGA_MAC_VER_26:
bca03d5f 3962 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3963 break;
3964 case RTL_GIGA_MAC_VER_27:
4da19633 3965 rtl8168d_3_hw_phy_config(tp);
5b538df9 3966 break;
e6de30d6 3967 case RTL_GIGA_MAC_VER_28:
3968 rtl8168d_4_hw_phy_config(tp);
3969 break;
5a5e4443
HW		 3970 case RTL_GIGA_MAC_VER_29:
3971 case RTL_GIGA_MAC_VER_30:
3972 rtl8105e_hw_phy_config(tp);
3973 break;
cecb5fd7
FR		 3974 case RTL_GIGA_MAC_VER_31:
3975 /* None. */
3976 break;
01dc7fec 3977 case RTL_GIGA_MAC_VER_32:
01dc7fec 3978 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3979 rtl8168e_1_hw_phy_config(tp);
3980 break;
3981 case RTL_GIGA_MAC_VER_34:
3982 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3983 break;
c2218925
HW		 3984 case RTL_GIGA_MAC_VER_35:
3985 rtl8168f_1_hw_phy_config(tp);
3986 break;
3987 case RTL_GIGA_MAC_VER_36:
3988 rtl8168f_2_hw_phy_config(tp);
3989 break;
ef3386f0 3990
7e18dca1
HW		 3991 case RTL_GIGA_MAC_VER_37:
3992 rtl8402_hw_phy_config(tp);
3993 break;
3994
b3d7b2f2
HW		 3995 case RTL_GIGA_MAC_VER_38:
3996 rtl8411_hw_phy_config(tp);
3997 break;
3998
5598bfe5
HW		 3999 case RTL_GIGA_MAC_VER_39:
4000 rtl8106e_hw_phy_config(tp);
4001 break;
4002
c558386b
HW		 4003 case RTL_GIGA_MAC_VER_40:
4004 rtl8168g_1_hw_phy_config(tp);
4005 break;
57538c4a 4006 case RTL_GIGA_MAC_VER_42:
58152cd4 4007 case RTL_GIGA_MAC_VER_43:
45dd95c4 4008 case RTL_GIGA_MAC_VER_44:
57538c4a 4009 rtl8168g_2_hw_phy_config(tp);
4010 break;
6e1d0b89
CHL		 4011 case RTL_GIGA_MAC_VER_45:
4012 case RTL_GIGA_MAC_VER_47:
4013 rtl8168h_1_hw_phy_config(tp);
4014 break;
4015 case RTL_GIGA_MAC_VER_46:
4016 case RTL_GIGA_MAC_VER_48:
4017 rtl8168h_2_hw_phy_config(tp);
4018 break;
c558386b 4019
935e2218
CHL		 4020 case RTL_GIGA_MAC_VER_49:
4021 rtl8168ep_1_hw_phy_config(tp);
4022 break;
4023 case RTL_GIGA_MAC_VER_50:
4024 case RTL_GIGA_MAC_VER_51:
4025 rtl8168ep_2_hw_phy_config(tp);
4026 break;
4027
c558386b 4028 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 4029 default:
4030 break;
4031 }
4032}
4033
da78dbff
FR		 4034static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4035{
da78dbff
FR		 4036 if (!test_and_set_bit(flag, tp->wk.flags))
4037 schedule_work(&tp->wk.work);
da78dbff
FR		 4038}
4039
2544bfc0
FR		 4040static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4041{
2544bfc0 4042 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
e397286b 4043 (RTL_R8(tp, PHYstatus) & TBI_Enable);
2544bfc0
FR		 4044}
4045
4ff96fa6
FR		 4046static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4047{
5615d9f1 4048 rtl_hw_phy_config(dev);
4ff96fa6 4049
77332894 4050 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
49d17512
HK		 4051 netif_dbg(tp, drv, dev,
4052 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 4053 RTL_W8(tp, 0x82, 0x01);
77332894 4054 }
4ff96fa6 4055
6dccd16b
FR		 4056 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4057
4058 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4059 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4060
bcf0bf90 4061 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
49d17512
HK		 4062 netif_dbg(tp, drv, dev,
4063 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 4064 RTL_W8(tp, 0x82, 0x01);
49d17512
HK		 4065 netif_dbg(tp, drv, dev,
4066 "Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4067 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4068 }
4069
5b7ad4b7
HK		 4070 /* We may have called phy_speed_down before */
4071 phy_speed_up(dev->phydev);
4072
f75222bc 4073 genphy_soft_reset(dev->phydev);
10bc6a60
HK		 4074
4075 /* It was reported that chip version 33 ends up with 10MBit/Half on a
4076 * 1GBit link after resuming from S3. For whatever reason the PHY on
4077 * this chip doesn't properly start a renegotiation when soft-reset.
4078 * Explicitly requesting a renegotiation fixes this.
4079 */
4080 if (tp->mac_version == RTL_GIGA_MAC_VER_33 &&
4081 dev->phydev->autoneg == AUTONEG_ENABLE)
4082 phy_restart_aneg(dev->phydev);
4ff96fa6
FR		 4083}
4084
773d2021
FR		 4085static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4086{
da78dbff 4087 rtl_lock_work(tp);
773d2021 4088
1ef7286e 4089 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
908ba2bf 4090
1ef7286e
AS		 4091 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4092 RTL_R32(tp, MAC4);
908ba2bf 4093
1ef7286e
AS		 4094 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4095 RTL_R32(tp, MAC0);
908ba2bf 4096
9ecb9aab 4097 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4098 rtl_rar_exgmac_set(tp, addr);
c28aa385 4099
1ef7286e 4100 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
773d2021 4101
da78dbff 4102 rtl_unlock_work(tp);
773d2021
FR		 4103}
4104
4105static int rtl_set_mac_address(struct net_device *dev, void *p)
4106{
4107 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 4108 struct device *d = tp_to_dev(tp);
1f7aa2bc 4109 int ret;
773d2021 4110
1f7aa2bc
HK		 4111 ret = eth_mac_addr(dev, p);
4112 if (ret)
4113 return ret;
773d2021 4114
f51d4a10
CHL		 4115 pm_runtime_get_noresume(d);
4116
4117 if (pm_runtime_active(d))
4118 rtl_rar_set(tp, dev->dev_addr);
4119
4120 pm_runtime_put_noidle(d);
773d2021
FR		 4121
4122 return 0;
4123}
4124
e397286b 4125static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8b4ab28d 4126{
69b3c59f
HK		 4127 if (!netif_running(dev))
4128 return -ENODEV;
e397286b 4129
69b3c59f 4130 return phy_mii_ioctl(dev->phydev, ifr, cmd);
8b4ab28d
FR		 4131}
4132
baf63293 4133static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4134{
4135 struct mdio_ops *ops = &tp->mdio_ops;
4136
4137 switch (tp->mac_version) {
4138 case RTL_GIGA_MAC_VER_27:
4139 ops->write = r8168dp_1_mdio_write;
4140 ops->read = r8168dp_1_mdio_read;
4141 break;
e6de30d6 4142 case RTL_GIGA_MAC_VER_28:
4804b3b3 4143 case RTL_GIGA_MAC_VER_31:
e6de30d6 4144 ops->write = r8168dp_2_mdio_write;
4145 ops->read = r8168dp_2_mdio_read;
4146 break;
2a71883c 4147 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
c558386b
HW		 4148 ops->write = r8168g_mdio_write;
4149 ops->read = r8168g_mdio_read;
4150 break;
c0e45c1c 4151 default:
4152 ops->write = r8169_mdio_write;
4153 ops->read = r8169_mdio_read;
4154 break;
4155 }
4156}
4157
649b3b8c 4158static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4159{
649b3b8c 4160 switch (tp->mac_version) {
b00e69de
CB		 4161 case RTL_GIGA_MAC_VER_25:
4162 case RTL_GIGA_MAC_VER_26:
649b3b8c 4163 case RTL_GIGA_MAC_VER_29:
4164 case RTL_GIGA_MAC_VER_30:
4165 case RTL_GIGA_MAC_VER_32:
4166 case RTL_GIGA_MAC_VER_33:
4167 case RTL_GIGA_MAC_VER_34:
2a71883c 4168 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4169 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
649b3b8c 4170 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4171 break;
4172 default:
4173 break;
4174 }
4175}
4176
4177static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4178{
6fcf9b1d 4179 if (!netif_running(tp->dev) || !__rtl8169_get_wol(tp))
649b3b8c 4180 return false;
4181
5b7ad4b7 4182 phy_speed_down(tp->dev->phydev, false);
649b3b8c 4183 rtl_wol_suspend_quirk(tp);
4184
4185 return true;
4186}
4187
065c27c1 4188static void r8168_pll_power_down(struct rtl8169_private *tp)
4189{
9dbe7896 4190 if (r8168_check_dash(tp))
065c27c1 4191 return;
4192
01dc7fec 4193 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4194 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4195 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4196
649b3b8c 4197 if (rtl_wol_pll_power_down(tp))
065c27c1 4198 return;
065c27c1 4199
065c27c1 4200 switch (tp->mac_version) {
2a71883c 4201 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4202 case RTL_GIGA_MAC_VER_37:
4203 case RTL_GIGA_MAC_VER_39:
4204 case RTL_GIGA_MAC_VER_43:
42fde737 4205 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4206 case RTL_GIGA_MAC_VER_45:
4207 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4208 case RTL_GIGA_MAC_VER_47:
4209 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4210 case RTL_GIGA_MAC_VER_50:
4211 case RTL_GIGA_MAC_VER_51:
1ef7286e 4212 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
065c27c1 4213 break;
beb330a4 4214 case RTL_GIGA_MAC_VER_40:
4215 case RTL_GIGA_MAC_VER_41:
935e2218 4216 case RTL_GIGA_MAC_VER_49:
706123d0 4217 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 4218 0xfc000000, ERIAR_EXGMAC);
1ef7286e 4219 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
beb330a4 4220 break;
065c27c1 4221 }
4222}
4223
4224static void r8168_pll_power_up(struct rtl8169_private *tp)
4225{
065c27c1 4226 switch (tp->mac_version) {
2a71883c 4227 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4228 case RTL_GIGA_MAC_VER_37:
4229 case RTL_GIGA_MAC_VER_39:
4230 case RTL_GIGA_MAC_VER_43:
1ef7286e 4231 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
065c27c1 4232 break;
42fde737 4233 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4234 case RTL_GIGA_MAC_VER_45:
4235 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4236 case RTL_GIGA_MAC_VER_47:
4237 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4238 case RTL_GIGA_MAC_VER_50:
4239 case RTL_GIGA_MAC_VER_51:
1ef7286e 4240 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
6e1d0b89 4241 break;
beb330a4 4242 case RTL_GIGA_MAC_VER_40:
4243 case RTL_GIGA_MAC_VER_41:
935e2218 4244 case RTL_GIGA_MAC_VER_49:
1ef7286e 4245 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
706123d0 4246 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 4247 0x00000000, ERIAR_EXGMAC);
4248 break;
065c27c1 4249 }
4250
242cd9b5
HK		 4251 phy_resume(tp->dev->phydev);
4252 /* give MAC/PHY some time to resume */
4253 msleep(20);
065c27c1 4254}
4255
065c27c1 4256static void rtl_pll_power_down(struct rtl8169_private *tp)
4257{
4f447d29
HK		 4258 switch (tp->mac_version) {
4259 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4260 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4261 break;
4262 default:
4263 r8168_pll_power_down(tp);
4264 }
065c27c1 4265}
4266
4267static void rtl_pll_power_up(struct rtl8169_private *tp)
4268{
065c27c1 4269 switch (tp->mac_version) {
4f447d29
HK		 4270 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4271 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
065c27c1 4272 break;
065c27c1 4273 default:
4f447d29 4274 r8168_pll_power_up(tp);
065c27c1 4275 }
4276}
4277
e542a226
HW		 4278static void rtl_init_rxcfg(struct rtl8169_private *tp)
4279{
e542a226 4280 switch (tp->mac_version) {
2a71883c
HK		 4281 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4282 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
1ef7286e 4283 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
e542a226 4284 break;
2a71883c 4285 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
eb2dc35d 4286 case RTL_GIGA_MAC_VER_34:
3ced8c95 4287 case RTL_GIGA_MAC_VER_35:
1ef7286e 4288 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
e542a226 4289 break;
2a71883c 4290 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4291 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 4292 break;
e542a226 4293 default:
1ef7286e 4294 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
e542a226
HW		 4295 break;
4296 }
4297}
4298
92fc43b4
HW		 4299static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4300{
9fba0812 4301 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4302}
4303
d58d46b5
FR		 4304static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4305{
eda40b8c
HK		 4306 if (tp->jumbo_ops.enable) {
4307 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4308 tp->jumbo_ops.enable(tp);
4309 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4310 }
d58d46b5
FR		 4311}
4312
4313static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4314{
eda40b8c
HK		 4315 if (tp->jumbo_ops.disable) {
4316 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4317 tp->jumbo_ops.disable(tp);
4318 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4319 }
d58d46b5
FR		 4320}
4321
4322static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4323{
1ef7286e
AS		 4324 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4325 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
cb73200c 4326 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4327}
4328
4329static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4330{
1ef7286e
AS		 4331 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4332 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
8d98aa39 4333 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4334}
4335
4336static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4337{
1ef7286e 4338 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
d58d46b5
FR		 4339}
4340
4341static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4342{
1ef7286e 4343 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
d58d46b5
FR		 4344}
4345
4346static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4347{
1ef7286e
AS		 4348 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4349 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4350 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
cb73200c 4351 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4352}
4353
4354static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4355{
1ef7286e
AS		 4356 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4357 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4358 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
8d98aa39 4359 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4360}
4361
4362static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4363{
cb73200c 4364 rtl_tx_performance_tweak(tp,
f65d539c 4365 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4366}
4367
4368static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4369{
cb73200c 4370 rtl_tx_performance_tweak(tp,
8d98aa39 4371 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4372}
4373
4374static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4375{
d58d46b5
FR		 4376 r8168b_0_hw_jumbo_enable(tp);
4377
1ef7286e 4378 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
d58d46b5
FR		 4379}
4380
4381static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4382{
d58d46b5
FR		 4383 r8168b_0_hw_jumbo_disable(tp);
4384
1ef7286e 4385 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
d58d46b5
FR		 4386}
4387
baf63293 4388static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4389{
4390 struct jumbo_ops *ops = &tp->jumbo_ops;
4391
4392 switch (tp->mac_version) {
4393 case RTL_GIGA_MAC_VER_11:
4394 ops->disable = r8168b_0_hw_jumbo_disable;
4395 ops->enable = r8168b_0_hw_jumbo_enable;
4396 break;
4397 case RTL_GIGA_MAC_VER_12:
4398 case RTL_GIGA_MAC_VER_17:
4399 ops->disable = r8168b_1_hw_jumbo_disable;
4400 ops->enable = r8168b_1_hw_jumbo_enable;
4401 break;
4402 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4403 case RTL_GIGA_MAC_VER_19:
4404 case RTL_GIGA_MAC_VER_20:
4405 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4406 case RTL_GIGA_MAC_VER_22:
4407 case RTL_GIGA_MAC_VER_23:
4408 case RTL_GIGA_MAC_VER_24:
4409 case RTL_GIGA_MAC_VER_25:
4410 case RTL_GIGA_MAC_VER_26:
4411 ops->disable = r8168c_hw_jumbo_disable;
4412 ops->enable = r8168c_hw_jumbo_enable;
4413 break;
4414 case RTL_GIGA_MAC_VER_27:
4415 case RTL_GIGA_MAC_VER_28:
4416 ops->disable = r8168dp_hw_jumbo_disable;
4417 ops->enable = r8168dp_hw_jumbo_enable;
4418 break;
4419 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4420 case RTL_GIGA_MAC_VER_32:
4421 case RTL_GIGA_MAC_VER_33:
4422 case RTL_GIGA_MAC_VER_34:
4423 ops->disable = r8168e_hw_jumbo_disable;
4424 ops->enable = r8168e_hw_jumbo_enable;
4425 break;
4426
4427 /*
4428 * No action needed for jumbo frames with 8169.
4429 * No jumbo for 810x at all.
4430 */
2a71883c 4431 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 4432 default:
4433 ops->disable = NULL;
4434 ops->enable = NULL;
4435 break;
4436 }
4437}
4438
ffc46952
FR		 4439DECLARE_RTL_COND(rtl_chipcmd_cond)
4440{
1ef7286e 4441 return RTL_R8(tp, ChipCmd) & CmdReset;
ffc46952
FR		 4442}
4443
6f43adc8
FR		 4444static void rtl_hw_reset(struct rtl8169_private *tp)
4445{
1ef7286e 4446 RTL_W8(tp, ChipCmd, CmdReset);
6f43adc8 4447
ffc46952 4448 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4449}
4450
b6ffd97f 4451static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4452{
b6ffd97f
FR		 4453 struct rtl_fw *rtl_fw;
4454 const char *name;
4455 int rc = -ENOMEM;
953a12cc 4456
b6ffd97f
FR		 4457 name = rtl_lookup_firmware_name(tp);
4458 if (!name)
4459 goto out_no_firmware;
953a12cc 4460
b6ffd97f
FR		 4461 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4462 if (!rtl_fw)
4463 goto err_warn;
31bd204f 4464
1e1205b7 4465 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
b6ffd97f
FR		 4466 if (rc < 0)
4467 goto err_free;
4468
fd112f2e
FR		 4469 rc = rtl_check_firmware(tp, rtl_fw);
4470 if (rc < 0)
4471 goto err_release_firmware;
4472
b6ffd97f
FR		 4473 tp->rtl_fw = rtl_fw;
4474out:
4475 return;
4476
fd112f2e
FR		 4477err_release_firmware:
4478 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4479err_free:
4480 kfree(rtl_fw);
4481err_warn:
4482 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4483 name, rc);
4484out_no_firmware:
4485 tp->rtl_fw = NULL;
4486 goto out;
4487}
4488
4489static void rtl_request_firmware(struct rtl8169_private *tp)
4490{
4491 if (IS_ERR(tp->rtl_fw))
4492 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4493}
4494
92fc43b4
HW		 4495static void rtl_rx_close(struct rtl8169_private *tp)
4496{
1ef7286e 4497 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4498}
4499
ffc46952
FR		 4500DECLARE_RTL_COND(rtl_npq_cond)
4501{
1ef7286e 4502 return RTL_R8(tp, TxPoll) & NPQ;
ffc46952
FR		 4503}
4504
4505DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4506{
1ef7286e 4507 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
ffc46952
FR		 4508}
4509
e6de30d6 4510static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4
LT		 4511{
4512 /* Disable interrupts */
811fd301 4513 rtl8169_irq_mask_and_ack(tp);
1da177e4 4514
92fc43b4
HW		 4515 rtl_rx_close(tp);
4516
b2d43e6e
HK		 4517 switch (tp->mac_version) {
4518 case RTL_GIGA_MAC_VER_27:
4519 case RTL_GIGA_MAC_VER_28:
4520 case RTL_GIGA_MAC_VER_31:
ffc46952 4521 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
b2d43e6e
HK		 4522 break;
4523 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4524 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4525 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
ffc46952 4526 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
b2d43e6e
HK		 4527 break;
4528 default:
1ef7286e 4529 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
92fc43b4 4530 udelay(100);
b2d43e6e 4531 break;
e6de30d6 4532 }
4533
92fc43b4 4534 rtl_hw_reset(tp);
1da177e4
LT		 4535}
4536
05212ba8 4537static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
9cb427b6 4538{
9cb427b6 4539 /* Set DMA burst size and Interframe Gap Time */
1ef7286e 4540 RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
9cb427b6
FR		 4541 (InterFrameGap << TxInterFrameGapShift));
4542}
4543
4fd48c4a 4544static void rtl_set_rx_max_size(struct rtl8169_private *tp)
1da177e4 4545{
4fd48c4a
HK		 4546 /* Low hurts. Let's disable the filtering. */
4547 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
07ce4064
FR		 4548}
4549
1ef7286e 4550static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
7f796d83
FR		 4551{
4552 /*
4553 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4554 * register to be written before TxDescAddrLow to work.
4555 * Switching from MMIO to I/O access fixes the issue as well.
4556 */
1ef7286e
AS		 4557 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4558 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4559 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4560 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4561}
4562
1ef7286e 4563static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
6dccd16b 4564{
3744100e 4565 static const struct rtl_cfg2_info {
6dccd16b
FR		 4566 u32 mac_version;
4567 u32 clk;
4568 u32 val;
4569 } cfg2_info [] = {
4570 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4571 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4572 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4573 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4574 };
4575 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4576 unsigned int i;
4577 u32 clk;
4578
1ef7286e 4579 clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
cadf1855 4580 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b 4581 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1ef7286e 4582 RTL_W32(tp, 0x7c, p->val);
6dccd16b
FR		 4583 break;
4584 }
4585 }
4586}
4587
e6b763ea
FR		 4588static void rtl_set_rx_mode(struct net_device *dev)
4589{
4590 struct rtl8169_private *tp = netdev_priv(dev);
e6b763ea
FR		 4591 u32 mc_filter[2]; /* Multicast hash filter */
4592 int rx_mode;
4593 u32 tmp = 0;
4594
4595 if (dev->flags & IFF_PROMISC) {
4596 /* Unconditionally log net taps. */
4597 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4598 rx_mode =
4599 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4600 AcceptAllPhys;
4601 mc_filter[1] = mc_filter[0] = 0xffffffff;
4602 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4603 (dev->flags & IFF_ALLMULTI)) {
4604 /* Too many to filter perfectly -- accept all multicasts. */
4605 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4606 mc_filter[1] = mc_filter[0] = 0xffffffff;
4607 } else {
4608 struct netdev_hw_addr *ha;
4609
4610 rx_mode = AcceptBroadcast | AcceptMyPhys;
4611 mc_filter[1] = mc_filter[0] = 0;
4612 netdev_for_each_mc_addr(ha, dev) {
4613 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4614 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4615 rx_mode |= AcceptMulticast;
4616 }
4617 }
4618
4619 if (dev->features & NETIF_F_RXALL)
4620 rx_mode |= (AcceptErr | AcceptRunt);
4621
1ef7286e 4622 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
e6b763ea
FR		 4623
4624 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4625 u32 data = mc_filter[0];
4626
4627 mc_filter[0] = swab32(mc_filter[1]);
4628 mc_filter[1] = swab32(data);
4629 }
4630
0481776b
NW		 4631 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4632 mc_filter[1] = mc_filter[0] = 0xffffffff;
4633
1ef7286e
AS		 4634 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4635 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
e6b763ea 4636
1ef7286e 4637 RTL_W32(tp, RxConfig, tmp);
e6b763ea
FR		 4638}
4639
52f8560e
HK		 4640static void rtl_hw_start(struct rtl8169_private *tp)
4641{
4642 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4643
4644 tp->hw_start(tp);
4645
4646 rtl_set_rx_max_size(tp);
4647 rtl_set_rx_tx_desc_registers(tp);
52f8560e
HK		 4648 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4649
4650 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4651 RTL_R8(tp, IntrMask);
4652 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
05212ba8 4653 rtl_init_rxcfg(tp);
f74dd480 4654 rtl_set_tx_config_registers(tp);
05212ba8 4655
52f8560e
HK		 4656 rtl_set_rx_mode(tp->dev);
4657 /* no early-rx interrupts */
4658 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4659 rtl_irq_enable_all(tp);
4660}
4661
61cb532d 4662static void rtl_hw_start_8169(struct rtl8169_private *tp)
07ce4064 4663{
0ae0974e 4664 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
61cb532d 4665 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
9cb427b6 4666
1ef7286e 4667 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
1da177e4 4668
0ae0974e 4669 tp->cp_cmd |= PCIMulRW;
1da177e4 4670
cecb5fd7
FR		 4671 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4672 tp->mac_version == RTL_GIGA_MAC_VER_03) {
49d17512
HK		 4673 netif_dbg(tp, drv, tp->dev,
4674 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
bcf0bf90 4675 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4676 }
4677
1ef7286e 4678 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
bcf0bf90 4679
1ef7286e 4680 rtl8169_set_magic_reg(tp, tp->mac_version);
6dccd16b 4681
1da177e4
LT		 4682 /*
4683 * Undocumented corner. Supposedly:
4684 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4685 */
1ef7286e 4686 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4 4687
1ef7286e 4688 RTL_W32(tp, RxMissed, 0);
07ce4064 4689}
1da177e4 4690
ffc46952
FR		 4691DECLARE_RTL_COND(rtl_csiar_cond)
4692{
1ef7286e 4693 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
ffc46952
FR		 4694}
4695
ff1d7331 4696static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
beb1fe18 4697{
ff1d7331 4698 u32 func = PCI_FUNC(tp->pci_dev->devfn);
beb1fe18 4699
1ef7286e
AS		 4700 RTL_W32(tp, CSIDR, value);
4701 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
ff1d7331 4702 CSIAR_BYTE_ENABLE | func << 16);
7e18dca1 4703
ffc46952 4704 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4705}
4706
ff1d7331 4707static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4708{
ff1d7331
HK		 4709 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4710
4711 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4712 CSIAR_BYTE_ENABLE);
7e18dca1 4713
ffc46952 4714 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 4715 RTL_R32(tp, CSIDR) : ~0;
7e18dca1
HW		 4716}
4717
ff1d7331 4718static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
45dd95c4 4719{
ff1d7331
HK		 4720 struct pci_dev *pdev = tp->pci_dev;
4721 u32 csi;
45dd95c4 4722
ff1d7331
HK		 4723 /* According to Realtek the value at config space address 0x070f
4724 * controls the L0s/L1 entrance latency. We try standard ECAM access
4725 * first and if it fails fall back to CSI.
4726 */
4727 if (pdev->cfg_size > 0x070f &&
4728 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4729 return;
4730
4731 netdev_notice_once(tp->dev,
4732 "No native access to PCI extended config space, falling back to CSI\n");
4733 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4734 rtl_csi_write(tp, 0x070c, csi | val << 24);
45dd95c4 4735}
4736
f37658da 4737static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
beb1fe18 4738{
ff1d7331 4739 rtl_csi_access_enable(tp, 0x27);
dacf8154
FR		 4740}
4741
4742struct ephy_info {
4743 unsigned int offset;
4744 u16 mask;
4745 u16 bits;
4746};
4747
fdf6fc06
FR		 4748static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4749 int len)
dacf8154
FR		 4750{
4751 u16 w;
4752
4753 while (len-- > 0) {
fdf6fc06
FR		 4754 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4755 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4756 e++;
4757 }
4758}
4759
73c86ee3 4760static void rtl_disable_clock_request(struct rtl8169_private *tp)
b726e493 4761{
73c86ee3 4762 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4763 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4764}
4765
73c86ee3 4766static void rtl_enable_clock_request(struct rtl8169_private *tp)
e6de30d6 4767{
73c86ee3 4768 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4769 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4770}
4771
b51ecea8 4772static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4773{
b51ecea8 4774 u8 data;
4775
1ef7286e 4776 data = RTL_R8(tp, Config3);
b51ecea8 4777
4778 if (enable)
4779 data |= Rdy_to_L23;
4780 else
4781 data &= ~Rdy_to_L23;
4782
1ef7286e 4783 RTL_W8(tp, Config3, data);
b51ecea8 4784}
4785
a99790bf
KHF		 4786static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4787{
4788 if (enable) {
a99790bf 4789 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
94235460 4790 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
a99790bf
KHF		 4791 } else {
4792 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4793 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4794 }
94235460
KHF		 4795
4796 udelay(10);
a99790bf
KHF		 4797}
4798
beb1fe18 4799static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4800{
1ef7286e 4801 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 4802
12d42c50 4803 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4804 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
b726e493 4805
faf1e785 4806 if (tp->dev->mtu <= ETH_DATA_LEN) {
8d98aa39 4807 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
faf1e785 4808 PCI_EXP_DEVCTL_NOSNOOP_EN);
4809 }
219a1e9d
FR		 4810}
4811
beb1fe18 4812static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4813{
beb1fe18 4814 rtl_hw_start_8168bb(tp);
b726e493 4815
1ef7286e 4816 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
b726e493 4817
1ef7286e 4818 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
219a1e9d
FR		 4819}
4820
beb1fe18 4821static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4822{
1ef7286e 4823 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
b726e493 4824
1ef7286e 4825 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 4826
faf1e785 4827 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4828 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
b726e493 4829
73c86ee3 4830 rtl_disable_clock_request(tp);
b726e493 4831
12d42c50 4832 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4833 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
219a1e9d
FR		 4834}
4835
beb1fe18 4836static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4837{
350f7596 4838 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4839 { 0x01, 0, 0x0001 },
4840 { 0x02, 0x0800, 0x1000 },
4841 { 0x03, 0, 0x0042 },
4842 { 0x06, 0x0080, 0x0000 },
4843 { 0x07, 0, 0x2000 }
4844 };
4845
f37658da 4846 rtl_set_def_aspm_entry_latency(tp);
b726e493 4847
fdf6fc06 4848 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4849
beb1fe18 4850 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4851}
4852
beb1fe18 4853static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4854{
f37658da 4855 rtl_set_def_aspm_entry_latency(tp);
ef3386f0 4856
1ef7286e 4857 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
ef3386f0 4858
faf1e785 4859 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4860 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
ef3386f0 4861
12d42c50 4862 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4863 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
ef3386f0
FR		 4864}
4865
beb1fe18 4866static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4867{
f37658da 4868 rtl_set_def_aspm_entry_latency(tp);
7f3e3d3a 4869
1ef7286e 4870 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
7f3e3d3a
FR		 4871
4872 /* Magic. */
1ef7286e 4873 RTL_W8(tp, DBG_REG, 0x20);
7f3e3d3a 4874
1ef7286e 4875 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
7f3e3d3a 4876
faf1e785 4877 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4878 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7f3e3d3a 4879
12d42c50 4880 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4881 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
7f3e3d3a
FR		 4882}
4883
beb1fe18 4884static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4885{
350f7596 4886 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4887 { 0x02, 0x0800, 0x1000 },
4888 { 0x03, 0, 0x0002 },
4889 { 0x06, 0x0080, 0x0000 }
4890 };
4891
f37658da 4892 rtl_set_def_aspm_entry_latency(tp);
b726e493 4893
1ef7286e 4894 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
b726e493 4895
fdf6fc06 4896 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 4897
beb1fe18 4898 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4899}
4900
beb1fe18 4901static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4902{
350f7596 4903 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4904 { 0x01, 0, 0x0001 },
4905 { 0x03, 0x0400, 0x0220 }
4906 };
4907
f37658da 4908 rtl_set_def_aspm_entry_latency(tp);
b726e493 4909
fdf6fc06 4910 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 4911
beb1fe18 4912 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4913}
4914
beb1fe18 4915static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4916{
beb1fe18 4917 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4918}
4919
beb1fe18 4920static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4921{
f37658da 4922 rtl_set_def_aspm_entry_latency(tp);
6fb07058 4923
beb1fe18 4924 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4925}
4926
beb1fe18 4927static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4928{
f37658da 4929 rtl_set_def_aspm_entry_latency(tp);
5b538df9 4930
73c86ee3 4931 rtl_disable_clock_request(tp);
5b538df9 4932
1ef7286e 4933 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5b538df9 4934
faf1e785 4935 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4936 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5b538df9 4937
12d42c50 4938 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4939 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5b538df9
FR		 4940}
4941
beb1fe18 4942static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4943{
f37658da 4944 rtl_set_def_aspm_entry_latency(tp);
4804b3b3 4945
faf1e785 4946 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4947 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4804b3b3 4948
1ef7286e 4949 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4804b3b3 4950
73c86ee3 4951 rtl_disable_clock_request(tp);
4804b3b3 4952}
4953
beb1fe18 4954static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4955{
4956 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 4957 { 0x0b, 0x0000, 0x0048 },
4958 { 0x19, 0x0020, 0x0050 },
4959 { 0x0c, 0x0100, 0x0020 }
e6de30d6 4960 };
e6de30d6 4961
f37658da 4962 rtl_set_def_aspm_entry_latency(tp);
e6de30d6 4963
8d98aa39 4964 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
e6de30d6 4965
1ef7286e 4966 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
e6de30d6 4967
1016a4a1 4968 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
e6de30d6 4969
73c86ee3 4970 rtl_enable_clock_request(tp);
e6de30d6 4971}
4972
beb1fe18 4973static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4974{
70090424 4975 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4976 { 0x00, 0x0200, 0x0100 },
4977 { 0x00, 0x0000, 0x0004 },
4978 { 0x06, 0x0002, 0x0001 },
4979 { 0x06, 0x0000, 0x0030 },
4980 { 0x07, 0x0000, 0x2000 },
4981 { 0x00, 0x0000, 0x0020 },
4982 { 0x03, 0x5800, 0x2000 },
4983 { 0x03, 0x0000, 0x0001 },
4984 { 0x01, 0x0800, 0x1000 },
4985 { 0x07, 0x0000, 0x4000 },
4986 { 0x1e, 0x0000, 0x2000 },
4987 { 0x19, 0xffff, 0xfe6c },
4988 { 0x0a, 0x0000, 0x0040 }
4989 };
4990
f37658da 4991 rtl_set_def_aspm_entry_latency(tp);
01dc7fec 4992
fdf6fc06 4993 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4994
faf1e785 4995 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4996 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
01dc7fec 4997
1ef7286e 4998 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
01dc7fec 4999
73c86ee3 5000 rtl_disable_clock_request(tp);
01dc7fec 5001
5002 /* Reset tx FIFO pointer */
1ef7286e
AS		 5003 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5004 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
01dc7fec 5005
1ef7286e 5006 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
01dc7fec 5007}
5008
beb1fe18 5009static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424
HW		 5010{
5011 static const struct ephy_info e_info_8168e_2[] = {
5012 { 0x09, 0x0000, 0x0080 },
5013 { 0x19, 0x0000, 0x0224 }
5014 };
5015
f37658da 5016 rtl_set_def_aspm_entry_latency(tp);
70090424 5017
fdf6fc06 5018 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5019
faf1e785 5020 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5021 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
70090424 5022
fdf6fc06
FR		 5023 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5024 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5025 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5026 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5027 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5028 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 5029 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5030 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5031
1ef7286e 5032 RTL_W8(tp, MaxTxPacketSize, EarlySize);
70090424 5033
73c86ee3 5034 rtl_disable_clock_request(tp);
4521e1a9 5035
1ef7286e
AS		 5036 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5037 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
70090424
HW		 5038
5039 /* Adjust EEE LED frequency */
1ef7286e 5040 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
70090424 5041
1ef7286e
AS		 5042 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5043 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5044 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
aa1e7d2c
HK		 5045
5046 rtl_hw_aspm_clkreq_enable(tp, true);
70090424
HW		 5047}
5048
5f886e08 5049static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5050{
f37658da 5051 rtl_set_def_aspm_entry_latency(tp);
c2218925 5052
8d98aa39 5053 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c2218925 5054
fdf6fc06
FR		 5055 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5056 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5057 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5058 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 5059 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5060 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5061 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5062 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5063 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5064 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925 5065
1ef7286e 5066 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c2218925 5067
73c86ee3 5068 rtl_disable_clock_request(tp);
4521e1a9 5069
1ef7286e
AS		 5070 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5071 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5072 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5073 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5074 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
c2218925
HW		 5075}
5076
5f886e08
HW		 5077static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5078{
5f886e08
HW		 5079 static const struct ephy_info e_info_8168f_1[] = {
5080 { 0x06, 0x00c0, 0x0020 },
5081 { 0x08, 0x0001, 0x0002 },
5082 { 0x09, 0x0000, 0x0080 },
5083 { 0x19, 0x0000, 0x0224 }
5084 };
5085
5086 rtl_hw_start_8168f(tp);
5087
fdf6fc06 5088 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5089
706123d0 5090 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5091
5092 /* Adjust EEE LED frequency */
1ef7286e 5093 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5f886e08
HW		 5094}
5095
b3d7b2f2
HW		 5096static void rtl_hw_start_8411(struct rtl8169_private *tp)
5097{
b3d7b2f2
HW		 5098 static const struct ephy_info e_info_8168f_1[] = {
5099 { 0x06, 0x00c0, 0x0020 },
5100 { 0x0f, 0xffff, 0x5200 },
5101 { 0x1e, 0x0000, 0x4000 },
5102 { 0x19, 0x0000, 0x0224 }
5103 };
5104
5105 rtl_hw_start_8168f(tp);
b51ecea8 5106 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 5107
fdf6fc06 5108 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5109
706123d0 5110 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5111}
5112
5fbea337 5113static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b 5114{
1ef7286e 5115 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
beb330a4 5116
c558386b
HW		 5117 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5118 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5119 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5120 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5121
f37658da 5122 rtl_set_def_aspm_entry_latency(tp);
c558386b 5123
8d98aa39 5124 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c558386b 5125
706123d0
CHL		 5126 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5127 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5128 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 5129
1ef7286e
AS		 5130 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5131 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c558386b
HW		 5132
5133 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5134 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5135
5136 /* Adjust EEE LED frequency */
1ef7286e 5137 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
c558386b 5138
706123d0
CHL		 5139 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5140 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 5141
5142 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 5143}
5144
5fbea337
CHL		 5145static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5146{
5fbea337
CHL		 5147 static const struct ephy_info e_info_8168g_1[] = {
5148 { 0x00, 0x0000, 0x0008 },
5149 { 0x0c, 0x37d0, 0x0820 },
5150 { 0x1e, 0x0000, 0x0001 },
5151 { 0x19, 0x8000, 0x0000 }
5152 };
5153
5154 rtl_hw_start_8168g(tp);
5155
5156 /* disable aspm and clock request before access ephy */
a99790bf 5157 rtl_hw_aspm_clkreq_enable(tp, false);
5fbea337 5158 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
a99790bf 5159 rtl_hw_aspm_clkreq_enable(tp, true);
5fbea337
CHL		 5160}
5161
57538c4a 5162static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5163{
57538c4a 5164 static const struct ephy_info e_info_8168g_2[] = {
5165 { 0x00, 0x0000, 0x0008 },
5166 { 0x0c, 0x3df0, 0x0200 },
5167 { 0x19, 0xffff, 0xfc00 },
5168 { 0x1e, 0xffff, 0x20eb }
5169 };
5170
5fbea337 5171 rtl_hw_start_8168g(tp);
57538c4a 5172
5173 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 5174 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5175 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
57538c4a 5176 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5177}
5178
45dd95c4 5179static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5180{
45dd95c4 5181 static const struct ephy_info e_info_8411_2[] = {
5182 { 0x00, 0x0000, 0x0008 },
5183 { 0x0c, 0x3df0, 0x0200 },
5184 { 0x0f, 0xffff, 0x5200 },
5185 { 0x19, 0x0020, 0x0000 },
5186 { 0x1e, 0x0000, 0x2000 }
5187 };
5188
5fbea337 5189 rtl_hw_start_8168g(tp);
45dd95c4 5190
5191 /* disable aspm and clock request before access ephy */
a99790bf 5192 rtl_hw_aspm_clkreq_enable(tp, false);
45dd95c4 5193 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
a99790bf 5194 rtl_hw_aspm_clkreq_enable(tp, true);
45dd95c4 5195}
5196
6e1d0b89
CHL		 5197static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5198{
72521ea0 5199 int rg_saw_cnt;
6e1d0b89
CHL		 5200 u32 data;
5201 static const struct ephy_info e_info_8168h_1[] = {
5202 { 0x1e, 0x0800, 0x0001 },
5203 { 0x1d, 0x0000, 0x0800 },
5204 { 0x05, 0xffff, 0x2089 },
5205 { 0x06, 0xffff, 0x5881 },
5206 { 0x04, 0xffff, 0x154a },
5207 { 0x01, 0xffff, 0x068b }
5208 };
5209
5210 /* disable aspm and clock request before access ephy */
a99790bf 5211 rtl_hw_aspm_clkreq_enable(tp, false);
6e1d0b89
CHL		 5212 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5213
1ef7286e 5214 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6e1d0b89
CHL		 5215
5216 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5217 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5218 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5219 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5220
f37658da 5221 rtl_set_def_aspm_entry_latency(tp);
6e1d0b89 5222
8d98aa39 5223 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6e1d0b89 5224
706123d0
CHL		 5225 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5226 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 5227
706123d0 5228 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 5229
706123d0 5230 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 5231
5232 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5233
1ef7286e
AS		 5234 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5235 RTL_W8(tp, MaxTxPacketSize, EarlySize);
6e1d0b89
CHL		 5236
5237 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5238 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5239
5240 /* Adjust EEE LED frequency */
1ef7286e 5241 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6e1d0b89 5242
1ef7286e
AS		 5243 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5244 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89 5245
1ef7286e 5246 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6e1d0b89 5247
706123d0 5248 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 5249
5250 rtl_pcie_state_l2l3_enable(tp, false);
5251
5252 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 5253 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 5254 rtl_writephy(tp, 0x1f, 0x0000);
5255 if (rg_saw_cnt > 0) {
5256 u16 sw_cnt_1ms_ini;
5257
5258 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5259 sw_cnt_1ms_ini &= 0x0fff;
5260 data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec0 5261 data &= ~0x0fff;
6e1d0b89
CHL		 5262 data |= sw_cnt_1ms_ini;
5263 r8168_mac_ocp_write(tp, 0xd412, data);
5264 }
5265
5266 data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec0
CHL		 5267 data &= ~0xf0;
5268 data |= 0x70;
6e1d0b89
CHL		 5269 r8168_mac_ocp_write(tp, 0xe056, data);
5270
5271 data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec0
CHL		 5272 data &= ~0x6000;
5273 data |= 0x8008;
6e1d0b89
CHL		 5274 r8168_mac_ocp_write(tp, 0xe052, data);
5275
5276 data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec0 5277 data &= ~0x01ff;
6e1d0b89
CHL		 5278 data |= 0x017f;
5279 r8168_mac_ocp_write(tp, 0xe0d6, data);
5280
5281 data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec0 5282 data &= ~0x0fff;
6e1d0b89
CHL		 5283 data |= 0x047f;
5284 r8168_mac_ocp_write(tp, 0xd420, data);
5285
5286 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5287 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5288 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5289 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
a99790bf
KHF		 5290
5291 rtl_hw_aspm_clkreq_enable(tp, true);
6e1d0b89
CHL		 5292}
5293
935e2218
CHL		 5294static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5295{
003609da
CHL		 5296 rtl8168ep_stop_cmac(tp);
5297
1ef7286e 5298 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
935e2218
CHL		 5299
5300 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5301 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5302 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5303 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5304
f37658da 5305 rtl_set_def_aspm_entry_latency(tp);
935e2218 5306
8d98aa39 5307 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
935e2218
CHL		 5308
5309 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5310 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5311
5312 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5313
5314 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5315
1ef7286e
AS		 5316 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5317 RTL_W8(tp, MaxTxPacketSize, EarlySize);
935e2218
CHL		 5318
5319 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5320 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5321
5322 /* Adjust EEE LED frequency */
1ef7286e 5323 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
935e2218
CHL		 5324
5325 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5326
1ef7286e 5327 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
935e2218
CHL		 5328
5329 rtl_pcie_state_l2l3_enable(tp, false);
5330}
5331
5332static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5333{
935e2218
CHL		 5334 static const struct ephy_info e_info_8168ep_1[] = {
5335 { 0x00, 0xffff, 0x10ab },
5336 { 0x06, 0xffff, 0xf030 },
5337 { 0x08, 0xffff, 0x2006 },
5338 { 0x0d, 0xffff, 0x1666 },
5339 { 0x0c, 0x3ff0, 0x0000 }
5340 };
5341
5342 /* disable aspm and clock request before access ephy */
a99790bf 5343 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5344 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5345
5346 rtl_hw_start_8168ep(tp);
a99790bf
KHF		 5347
5348 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5349}
5350
5351static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5352{
935e2218
CHL		 5353 static const struct ephy_info e_info_8168ep_2[] = {
5354 { 0x00, 0xffff, 0x10a3 },
5355 { 0x19, 0xffff, 0xfc00 },
5356 { 0x1e, 0xffff, 0x20ea }
5357 };
5358
5359 /* disable aspm and clock request before access ephy */
a99790bf 5360 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5361 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5362
5363 rtl_hw_start_8168ep(tp);
5364
1ef7286e
AS		 5365 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5366 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
a99790bf
KHF		 5367
5368 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5369}
5370
5371static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5372{
935e2218
CHL		 5373 u32 data;
5374 static const struct ephy_info e_info_8168ep_3[] = {
5375 { 0x00, 0xffff, 0x10a3 },
5376 { 0x19, 0xffff, 0x7c00 },
5377 { 0x1e, 0xffff, 0x20eb },
5378 { 0x0d, 0xffff, 0x1666 }
5379 };
5380
5381 /* disable aspm and clock request before access ephy */
a99790bf 5382 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5383 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5384
5385 rtl_hw_start_8168ep(tp);
5386
1ef7286e
AS		 5387 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5388 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 5389
5390 data = r8168_mac_ocp_read(tp, 0xd3e2);
5391 data &= 0xf000;
5392 data |= 0x0271;
5393 r8168_mac_ocp_write(tp, 0xd3e2, data);
5394
5395 data = r8168_mac_ocp_read(tp, 0xd3e4);
5396 data &= 0xff00;
5397 r8168_mac_ocp_write(tp, 0xd3e4, data);
5398
5399 data = r8168_mac_ocp_read(tp, 0xe860);
5400 data |= 0x0080;
5401 r8168_mac_ocp_write(tp, 0xe860, data);
a99790bf
KHF		 5402
5403 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5404}
5405
61cb532d 5406static void rtl_hw_start_8168(struct rtl8169_private *tp)
07ce4064 5407{
1ef7286e 5408 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
2dd99530 5409
0ae0974e
HK		 5410 tp->cp_cmd &= ~INTT_MASK;
5411 tp->cp_cmd |= PktCntrDisable | INTT_1;
1ef7286e 5412 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2dd99530 5413
1ef7286e 5414 RTL_W16(tp, IntrMitigate, 0x5151);
2dd99530 5415
0e485150 5416 /* Work around for RxFIFO overflow. */
811fd301 5417 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5418 tp->event_slow |= RxFIFOOver | PCSTimeout;
5419 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5420 }
5421
219a1e9d
FR		 5422 switch (tp->mac_version) {
5423 case RTL_GIGA_MAC_VER_11:
beb1fe18 5424 rtl_hw_start_8168bb(tp);
4804b3b3 5425 break;
219a1e9d
FR		 5426
5427 case RTL_GIGA_MAC_VER_12:
5428 case RTL_GIGA_MAC_VER_17:
beb1fe18 5429 rtl_hw_start_8168bef(tp);
4804b3b3 5430 break;
219a1e9d
FR		 5431
5432 case RTL_GIGA_MAC_VER_18:
beb1fe18 5433 rtl_hw_start_8168cp_1(tp);
4804b3b3 5434 break;
219a1e9d
FR		 5435
5436 case RTL_GIGA_MAC_VER_19:
beb1fe18 5437 rtl_hw_start_8168c_1(tp);
4804b3b3 5438 break;
219a1e9d
FR		 5439
5440 case RTL_GIGA_MAC_VER_20:
beb1fe18 5441 rtl_hw_start_8168c_2(tp);
4804b3b3 5442 break;
219a1e9d 5443
197ff761 5444 case RTL_GIGA_MAC_VER_21:
beb1fe18 5445 rtl_hw_start_8168c_3(tp);
4804b3b3 5446 break;
197ff761 5447
6fb07058 5448 case RTL_GIGA_MAC_VER_22:
beb1fe18 5449 rtl_hw_start_8168c_4(tp);
4804b3b3 5450 break;
6fb07058 5451
ef3386f0 5452 case RTL_GIGA_MAC_VER_23:
beb1fe18 5453 rtl_hw_start_8168cp_2(tp);
4804b3b3 5454 break;
ef3386f0 5455
7f3e3d3a 5456 case RTL_GIGA_MAC_VER_24:
beb1fe18 5457 rtl_hw_start_8168cp_3(tp);
4804b3b3 5458 break;
7f3e3d3a 5459
5b538df9 5460 case RTL_GIGA_MAC_VER_25:
daf9df6d 5461 case RTL_GIGA_MAC_VER_26:
5462 case RTL_GIGA_MAC_VER_27:
beb1fe18 5463 rtl_hw_start_8168d(tp);
4804b3b3 5464 break;
5b538df9 5465
e6de30d6 5466 case RTL_GIGA_MAC_VER_28:
beb1fe18 5467 rtl_hw_start_8168d_4(tp);
4804b3b3 5468 break;
cecb5fd7 5469
4804b3b3 5470 case RTL_GIGA_MAC_VER_31:
beb1fe18 5471 rtl_hw_start_8168dp(tp);
4804b3b3 5472 break;
5473
01dc7fec 5474 case RTL_GIGA_MAC_VER_32:
5475 case RTL_GIGA_MAC_VER_33:
beb1fe18 5476 rtl_hw_start_8168e_1(tp);
70090424
HW		 5477 break;
5478 case RTL_GIGA_MAC_VER_34:
beb1fe18 5479 rtl_hw_start_8168e_2(tp);
01dc7fec 5480 break;
e6de30d6 5481
c2218925
HW		 5482 case RTL_GIGA_MAC_VER_35:
5483 case RTL_GIGA_MAC_VER_36:
beb1fe18 5484 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5485 break;
5486
b3d7b2f2
HW		 5487 case RTL_GIGA_MAC_VER_38:
5488 rtl_hw_start_8411(tp);
5489 break;
5490
c558386b
HW		 5491 case RTL_GIGA_MAC_VER_40:
5492 case RTL_GIGA_MAC_VER_41:
5493 rtl_hw_start_8168g_1(tp);
5494 break;
57538c4a 5495 case RTL_GIGA_MAC_VER_42:
5496 rtl_hw_start_8168g_2(tp);
5497 break;
c558386b 5498
45dd95c4 5499 case RTL_GIGA_MAC_VER_44:
5500 rtl_hw_start_8411_2(tp);
5501 break;
5502
6e1d0b89
CHL		 5503 case RTL_GIGA_MAC_VER_45:
5504 case RTL_GIGA_MAC_VER_46:
5505 rtl_hw_start_8168h_1(tp);
5506 break;
5507
935e2218
CHL		 5508 case RTL_GIGA_MAC_VER_49:
5509 rtl_hw_start_8168ep_1(tp);
5510 break;
5511
5512 case RTL_GIGA_MAC_VER_50:
5513 rtl_hw_start_8168ep_2(tp);
5514 break;
5515
5516 case RTL_GIGA_MAC_VER_51:
5517 rtl_hw_start_8168ep_3(tp);
5518 break;
5519
219a1e9d 5520 default:
49d17512
HK		 5521 netif_err(tp, drv, tp->dev,
5522 "unknown chipset (mac_version = %d)\n",
5523 tp->mac_version);
4804b3b3 5524 break;
219a1e9d 5525 }
07ce4064 5526}
1da177e4 5527
beb1fe18 5528static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5529{
350f7596 5530 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5531 { 0x01, 0, 0x6e65 },
5532 { 0x02, 0, 0x091f },
5533 { 0x03, 0, 0xc2f9 },
5534 { 0x06, 0, 0xafb5 },
5535 { 0x07, 0, 0x0e00 },
5536 { 0x19, 0, 0xec80 },
5537 { 0x01, 0, 0x2e65 },
5538 { 0x01, 0, 0x6e65 }
5539 };
5540 u8 cfg1;
5541
f37658da 5542 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5543
1ef7286e 5544 RTL_W8(tp, DBG_REG, FIX_NAK_1);
2857ffb7 5545
8d98aa39 5546 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 5547
1ef7286e 5548 RTL_W8(tp, Config1,
2857ffb7 5549 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
1ef7286e 5550 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7 5551
1ef7286e 5552 cfg1 = RTL_R8(tp, Config1);
2857ffb7 5553 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
1ef7286e 5554 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
2857ffb7 5555
fdf6fc06 5556 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5557}
5558
beb1fe18 5559static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5560{
f37658da 5561 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5562
8d98aa39 5563 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 5564
1ef7286e
AS		 5565 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5566 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7
FR		 5567}
5568
beb1fe18 5569static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5570{
beb1fe18 5571 rtl_hw_start_8102e_2(tp);
2857ffb7 5572
fdf6fc06 5573 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5574}
5575
beb1fe18 5576static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443
HW		 5577{
5578 static const struct ephy_info e_info_8105e_1[] = {
5579 { 0x07, 0, 0x4000 },
5580 { 0x19, 0, 0x0200 },
5581 { 0x19, 0, 0x0020 },
5582 { 0x1e, 0, 0x2000 },
5583 { 0x03, 0, 0x0001 },
5584 { 0x19, 0, 0x0100 },
5585 { 0x19, 0, 0x0004 },
5586 { 0x0a, 0, 0x0020 }
5587 };
5588
cecb5fd7 5589 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5590 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5a5e4443 5591
cecb5fd7 5592 /* Disable Early Tally Counter */
1ef7286e 5593 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5a5e4443 5594
1ef7286e
AS		 5595 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5596 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5a5e4443 5597
fdf6fc06 5598 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 5599
5600 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 5601}
5602
beb1fe18 5603static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5604{
beb1fe18 5605 rtl_hw_start_8105e_1(tp);
fdf6fc06 5606 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5607}
5608
7e18dca1
HW		 5609static void rtl_hw_start_8402(struct rtl8169_private *tp)
5610{
7e18dca1
HW		 5611 static const struct ephy_info e_info_8402[] = {
5612 { 0x19, 0xffff, 0xff64 },
5613 { 0x1e, 0, 0x4000 }
5614 };
5615
f37658da 5616 rtl_set_def_aspm_entry_latency(tp);
7e18dca1
HW		 5617
5618 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5619 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
7e18dca1 5620
1ef7286e
AS		 5621 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5622 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7e18dca1 5623
fdf6fc06 5624 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1 5625
8d98aa39 5626 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7e18dca1 5627
fdf6fc06
FR		 5628 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5629 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 5630 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5631 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5632 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5633 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 5634 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 5635
5636 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 5637}
5638
5598bfe5
HW		 5639static void rtl_hw_start_8106(struct rtl8169_private *tp)
5640{
0866cd15
KHF		 5641 rtl_hw_aspm_clkreq_enable(tp, false);
5642
5598bfe5 5643 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5644 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5598bfe5 5645
1ef7286e
AS		 5646 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5647 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5648 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
b51ecea8 5649
5650 rtl_pcie_state_l2l3_enable(tp, false);
0866cd15 5651 rtl_hw_aspm_clkreq_enable(tp, true);
5598bfe5
HW		 5652}
5653
61cb532d 5654static void rtl_hw_start_8101(struct rtl8169_private *tp)
07ce4064 5655{
da78dbff
FR		 5656 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5657 tp->event_slow &= ~RxFIFOOver;
811fd301 5658
cecb5fd7 5659 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5660 tp->mac_version == RTL_GIGA_MAC_VER_16)
61cb532d 5661 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
8200bc72 5662 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5663
1ef7286e 5664 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
1a964649 5665
12d42c50 5666 tp->cp_cmd &= CPCMD_QUIRK_MASK;
1ef7286e 5667 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1a964649 5668
2857ffb7
FR		 5669 switch (tp->mac_version) {
5670 case RTL_GIGA_MAC_VER_07:
beb1fe18 5671 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5672 break;
5673
5674 case RTL_GIGA_MAC_VER_08:
beb1fe18 5675 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5676 break;
5677
5678 case RTL_GIGA_MAC_VER_09:
beb1fe18 5679 rtl_hw_start_8102e_2(tp);
2857ffb7 5680 break;
5a5e4443
HW		 5681
5682 case RTL_GIGA_MAC_VER_29:
beb1fe18 5683 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5684 break;
5685 case RTL_GIGA_MAC_VER_30:
beb1fe18 5686 rtl_hw_start_8105e_2(tp);
5a5e4443 5687 break;
7e18dca1
HW		 5688
5689 case RTL_GIGA_MAC_VER_37:
5690 rtl_hw_start_8402(tp);
5691 break;
5598bfe5
HW		 5692
5693 case RTL_GIGA_MAC_VER_39:
5694 rtl_hw_start_8106(tp);
5695 break;
58152cd4 5696 case RTL_GIGA_MAC_VER_43:
5697 rtl_hw_start_8168g_2(tp);
5698 break;
6e1d0b89
CHL		 5699 case RTL_GIGA_MAC_VER_47:
5700 case RTL_GIGA_MAC_VER_48:
5701 rtl_hw_start_8168h_1(tp);
5702 break;
cdf1a608
FR		 5703 }
5704
1ef7286e 5705 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4
LT		 5706}
5707
5708static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5709{
d58d46b5
FR		 5710 struct rtl8169_private *tp = netdev_priv(dev);
5711
d58d46b5
FR		 5712 if (new_mtu > ETH_DATA_LEN)
5713 rtl_hw_jumbo_enable(tp);
5714 else
5715 rtl_hw_jumbo_disable(tp);
5716
1da177e4 5717 dev->mtu = new_mtu;
350fb32a
MM		 5718 netdev_update_features(dev);
5719
323bb685 5720 return 0;
1da177e4
LT		 5721}
5722
5723static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5724{
95e0918d 5725 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5726 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5727}
5728
6f0333b8
ED		 5729static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5730 void **data_buff, struct RxDesc *desc)
1da177e4 5731{
1d0254dd
HK		 5732 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5733 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
48addcc9 5734
6f0333b8
ED		 5735 kfree(*data_buff);
5736 *data_buff = NULL;
1da177e4
LT		 5737 rtl8169_make_unusable_by_asic(desc);
5738}
5739
1d0254dd 5740static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
1da177e4
LT		 5741{
5742 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5743
a0750138
AD		 5744 /* Force memory writes to complete before releasing descriptor */
5745 dma_wmb();
5746
1d0254dd 5747 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
1da177e4
LT		 5748}
5749
6f0333b8
ED		 5750static inline void *rtl8169_align(void *data)
5751{
5752 return (void *)ALIGN((long)data, 16);
5753}
5754
0ecbe1ca
SG		 5755static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5756 struct RxDesc *desc)
1da177e4 5757{
6f0333b8 5758 void *data;
1da177e4 5759 dma_addr_t mapping;
1e1205b7 5760 struct device *d = tp_to_dev(tp);
d3b404c2 5761 int node = dev_to_node(d);
1da177e4 5762
1d0254dd 5763 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
6f0333b8
ED		 5764 if (!data)
5765 return NULL;
e9f63f30 5766
6f0333b8
ED		 5767 if (rtl8169_align(data) != data) {
5768 kfree(data);
1d0254dd 5769 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
6f0333b8
ED		 5770 if (!data)
5771 return NULL;
5772 }
3eafe507 5773
1d0254dd 5774 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
231aee63 5775 DMA_FROM_DEVICE);
d827d86b
SG		 5776 if (unlikely(dma_mapping_error(d, mapping))) {
5777 if (net_ratelimit())
5778 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5779 goto err_out;
d827d86b 5780 }
1da177e4 5781
d731af78
HK		 5782 desc->addr = cpu_to_le64(mapping);
5783 rtl8169_mark_to_asic(desc);
6f0333b8 5784 return data;
3eafe507
SG		 5785
5786err_out:
5787 kfree(data);
5788 return NULL;
1da177e4
LT		 5789}
5790
5791static void rtl8169_rx_clear(struct rtl8169_private *tp)
5792{
07d3f51f 5793 unsigned int i;
1da177e4
LT		 5794
5795 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5796 if (tp->Rx_databuff[i]) {
5797 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5798 tp->RxDescArray + i);
5799 }
5800 }
5801}
5802
0ecbe1ca 5803static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5804{
0ecbe1ca
SG		 5805 desc->opts1 |= cpu_to_le32(RingEnd);
5806}
5b0384f4 5807
0ecbe1ca
SG		 5808static int rtl8169_rx_fill(struct rtl8169_private *tp)
5809{
5810 unsigned int i;
1da177e4 5811
0ecbe1ca
SG		 5812 for (i = 0; i < NUM_RX_DESC; i++) {
5813 void *data;
4ae47c2d 5814
0ecbe1ca 5815 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5816 if (!data) {
5817 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5818 goto err_out;
6f0333b8
ED		 5819 }
5820 tp->Rx_databuff[i] = data;
1da177e4 5821 }
1da177e4 5822
0ecbe1ca
SG		 5823 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5824 return 0;
5825
5826err_out:
5827 rtl8169_rx_clear(tp);
5828 return -ENOMEM;
1da177e4
LT		 5829}
5830
b1127e64 5831static int rtl8169_init_ring(struct rtl8169_private *tp)
1da177e4 5832{
1da177e4
LT		 5833 rtl8169_init_ring_indexes(tp);
5834
b1127e64
HK		 5835 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5836 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
1da177e4 5837
0ecbe1ca 5838 return rtl8169_rx_fill(tp);
1da177e4
LT		 5839}
5840
48addcc9 5841static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5842 struct TxDesc *desc)
5843{
5844 unsigned int len = tx_skb->len;
5845
48addcc9
SG		 5846 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5847
1da177e4
LT		 5848 desc->opts1 = 0x00;
5849 desc->opts2 = 0x00;
5850 desc->addr = 0x00;
5851 tx_skb->len = 0;
5852}
5853
3eafe507
SG		 5854static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5855 unsigned int n)
1da177e4
LT		 5856{
5857 unsigned int i;
5858
3eafe507
SG		 5859 for (i = 0; i < n; i++) {
5860 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5861 struct ring_info *tx_skb = tp->tx_skb + entry;
5862 unsigned int len = tx_skb->len;
5863
5864 if (len) {
5865 struct sk_buff *skb = tx_skb->skb;
5866
1e1205b7 5867 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
1da177e4
LT		 5868 tp->TxDescArray + entry);
5869 if (skb) {
7a4b813c 5870 dev_consume_skb_any(skb);
1da177e4
LT		 5871 tx_skb->skb = NULL;
5872 }
1da177e4
LT		 5873 }
5874 }
3eafe507
SG		 5875}
5876
5877static void rtl8169_tx_clear(struct rtl8169_private *tp)
5878{
5879 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5880 tp->cur_tx = tp->dirty_tx = 0;
5881}
5882
4422bcd4 5883static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5884{
c4028958 5885 struct net_device *dev = tp->dev;
56de414c 5886 int i;
1da177e4 5887
da78dbff
FR		 5888 napi_disable(&tp->napi);
5889 netif_stop_queue(dev);
5890 synchronize_sched();
1da177e4 5891
c7c2c39b 5892 rtl8169_hw_reset(tp);
5893
56de414c 5894 for (i = 0; i < NUM_RX_DESC; i++)
1d0254dd 5895 rtl8169_mark_to_asic(tp->RxDescArray + i);
56de414c 5896
1da177e4 5897 rtl8169_tx_clear(tp);
c7c2c39b 5898 rtl8169_init_ring_indexes(tp);
1da177e4 5899
da78dbff 5900 napi_enable(&tp->napi);
61cb532d 5901 rtl_hw_start(tp);
56de414c 5902 netif_wake_queue(dev);
1da177e4
LT		 5903}
5904
5905static void rtl8169_tx_timeout(struct net_device *dev)
5906{
da78dbff
FR		 5907 struct rtl8169_private *tp = netdev_priv(dev);
5908
5909 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5910}
5911
5912static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5913 u32 *opts)
1da177e4
LT		 5914{
5915 struct skb_shared_info *info = skb_shinfo(skb);
5916 unsigned int cur_frag, entry;
6e1d0b89 5917 struct TxDesc *uninitialized_var(txd);
1e1205b7 5918 struct device *d = tp_to_dev(tp);
1da177e4
LT		 5919
5920 entry = tp->cur_tx;
5921 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5922 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5923 dma_addr_t mapping;
5924 u32 status, len;
5925 void *addr;
5926
5927 entry = (entry + 1) % NUM_TX_DESC;
5928
5929 txd = tp->TxDescArray + entry;
9e903e08 5930 len = skb_frag_size(frag);
929f6189 5931 addr = skb_frag_address(frag);
48addcc9 5932 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5933 if (unlikely(dma_mapping_error(d, mapping))) {
5934 if (net_ratelimit())
5935 netif_err(tp, drv, tp->dev,
5936 "Failed to map TX fragments DMA!\n");
3eafe507 5937 goto err_out;
d827d86b 5938 }
1da177e4 5939
cecb5fd7 5940 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5941 status = opts[0] | len |
5942 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5943
5944 txd->opts1 = cpu_to_le32(status);
2b7b4318 5945 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5946 txd->addr = cpu_to_le64(mapping);
5947
5948 tp->tx_skb[entry].len = len;
5949 }
5950
5951 if (cur_frag) {
5952 tp->tx_skb[entry].skb = skb;
5953 txd->opts1 |= cpu_to_le32(LastFrag);
5954 }
5955
5956 return cur_frag;
3eafe507
SG		 5957
5958err_out:
5959 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5960 return -EIO;
1da177e4
LT		 5961}
5962
b423e9ae 5963static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5964{
5965 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5966}
5967
e974604b 5968static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5969 struct net_device *dev);
5970/* r8169_csum_workaround()
5971 * The hw limites the value the transport offset. When the offset is out of the
5972 * range, calculate the checksum by sw.
5973 */
5974static void r8169_csum_workaround(struct rtl8169_private *tp,
5975 struct sk_buff *skb)
5976{
5977 if (skb_shinfo(skb)->gso_size) {
5978 netdev_features_t features = tp->dev->features;
5979 struct sk_buff *segs, *nskb;
5980
5981 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5982 segs = skb_gso_segment(skb, features);
5983 if (IS_ERR(segs) || !segs)
5984 goto drop;
5985
5986 do {
5987 nskb = segs;
5988 segs = segs->next;
5989 nskb->next = NULL;
5990 rtl8169_start_xmit(nskb, tp->dev);
5991 } while (segs);
5992
eb781397 5993 dev_consume_skb_any(skb);
e974604b 5994 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5995 if (skb_checksum_help(skb) < 0)
5996 goto drop;
5997
5998 rtl8169_start_xmit(skb, tp->dev);
5999 } else {
6000 struct net_device_stats *stats;
6001
6002drop:
6003 stats = &tp->dev->stats;
6004 stats->tx_dropped++;
eb781397 6005 dev_kfree_skb_any(skb);
e974604b 6006 }
6007}
6008
6009/* msdn_giant_send_check()
6010 * According to the document of microsoft, the TCP Pseudo Header excludes the
6011 * packet length for IPv6 TCP large packets.
6012 */
6013static int msdn_giant_send_check(struct sk_buff *skb)
6014{
6015 const struct ipv6hdr *ipv6h;
6016 struct tcphdr *th;
6017 int ret;
6018
6019 ret = skb_cow_head(skb, 0);
6020 if (ret)
6021 return ret;
6022
6023 ipv6h = ipv6_hdr(skb);
6024 th = tcp_hdr(skb);
6025
6026 th->check = 0;
6027 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6028
6029 return ret;
6030}
6031
5888d3fc 6032static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6033 struct sk_buff *skb, u32 *opts)
1da177e4 6034{
350fb32a
MM		 6035 u32 mss = skb_shinfo(skb)->gso_size;
6036
2b7b4318
FR		 6037 if (mss) {
6038 opts[0] |= TD_LSO;
5888d3fc 6039 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6040 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6041 const struct iphdr *ip = ip_hdr(skb);
6042
6043 if (ip->protocol == IPPROTO_TCP)
6044 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6045 else if (ip->protocol == IPPROTO_UDP)
6046 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6047 else
6048 WARN_ON_ONCE(1);
6049 }
6050
6051 return true;
6052}
6053
6054static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6055 struct sk_buff *skb, u32 *opts)
6056{
bdfa4ed6 6057 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 6058 u32 mss = skb_shinfo(skb)->gso_size;
6059
6060 if (mss) {
e974604b 6061 if (transport_offset > GTTCPHO_MAX) {
6062 netif_warn(tp, tx_err, tp->dev,
6063 "Invalid transport offset 0x%x for TSO\n",
6064 transport_offset);
6065 return false;
6066 }
6067
4ff36466 6068 switch (vlan_get_protocol(skb)) {
e974604b 6069 case htons(ETH_P_IP):
6070 opts[0] |= TD1_GTSENV4;
6071 break;
6072
6073 case htons(ETH_P_IPV6):
6074 if (msdn_giant_send_check(skb))
6075 return false;
6076
6077 opts[0] |= TD1_GTSENV6;
6078 break;
6079
6080 default:
6081 WARN_ON_ONCE(1);
6082 break;
6083 }
6084
bdfa4ed6 6085 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 6086 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 6087 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 6088 u8 ip_protocol;
1da177e4 6089
b423e9ae 6090 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6091 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
b423e9ae 6092
e974604b 6093 if (transport_offset > TCPHO_MAX) {
6094 netif_warn(tp, tx_err, tp->dev,
6095 "Invalid transport offset 0x%x\n",
6096 transport_offset);
6097 return false;
6098 }
6099
4ff36466 6100 switch (vlan_get_protocol(skb)) {
e974604b 6101 case htons(ETH_P_IP):
6102 opts[1] |= TD1_IPv4_CS;
6103 ip_protocol = ip_hdr(skb)->protocol;
6104 break;
6105
6106 case htons(ETH_P_IPV6):
6107 opts[1] |= TD1_IPv6_CS;
6108 ip_protocol = ipv6_hdr(skb)->nexthdr;
6109 break;
6110
6111 default:
6112 ip_protocol = IPPROTO_RAW;
6113 break;
6114 }
6115
6116 if (ip_protocol == IPPROTO_TCP)
6117 opts[1] |= TD1_TCP_CS;
6118 else if (ip_protocol == IPPROTO_UDP)
6119 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 6120 else
6121 WARN_ON_ONCE(1);
e974604b 6122
6123 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 6124 } else {
6125 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6126 return !eth_skb_pad(skb);
1da177e4 6127 }
5888d3fc 6128
b423e9ae 6129 return true;
1da177e4
LT		 6130}
6131
61357325
SH		 6132static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6133 struct net_device *dev)
1da177e4
LT		 6134{
6135 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 6136 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4 6137 struct TxDesc *txd = tp->TxDescArray + entry;
1e1205b7 6138 struct device *d = tp_to_dev(tp);
1da177e4
LT		 6139 dma_addr_t mapping;
6140 u32 status, len;
2b7b4318 6141 u32 opts[2];
3eafe507 6142 int frags;
5b0384f4 6143
477206a0 6144 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 6145 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 6146 goto err_stop_0;
1da177e4
LT		 6147 }
6148
6149 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 6150 goto err_stop_0;
6151
b423e9ae 6152 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6153 opts[0] = DescOwn;
6154
e974604b 6155 if (!tp->tso_csum(tp, skb, opts)) {
6156 r8169_csum_workaround(tp, skb);
6157 return NETDEV_TX_OK;
6158 }
b423e9ae 6159
3eafe507 6160 len = skb_headlen(skb);
48addcc9 6161 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 6162 if (unlikely(dma_mapping_error(d, mapping))) {
6163 if (net_ratelimit())
6164 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 6165 goto err_dma_0;
d827d86b 6166 }
3eafe507
SG		 6167
6168 tp->tx_skb[entry].len = len;
6169 txd->addr = cpu_to_le64(mapping);
1da177e4 6170
2b7b4318 6171 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 6172 if (frags < 0)
6173 goto err_dma_1;
6174 else if (frags)
2b7b4318 6175 opts[0] |= FirstFrag;
3eafe507 6176 else {
2b7b4318 6177 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 6178 tp->tx_skb[entry].skb = skb;
6179 }
6180
2b7b4318
FR		 6181 txd->opts2 = cpu_to_le32(opts[1]);
6182
5047fb5d
RC		 6183 skb_tx_timestamp(skb);
6184
a0750138
AD		 6185 /* Force memory writes to complete before releasing descriptor */
6186 dma_wmb();
1da177e4 6187
cecb5fd7 6188 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 6189 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6190 txd->opts1 = cpu_to_le32(status);
6191
a0750138 6192 /* Force all memory writes to complete before notifying device */
4c020a96 6193 wmb();
1da177e4 6194
a0750138
AD		 6195 tp->cur_tx += frags + 1;
6196
1ef7286e 6197 RTL_W8(tp, TxPoll, NPQ);
1da177e4 6198
87cda7cb 6199 mmiowb();
da78dbff 6200
87cda7cb 6201 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 6202 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6203 * not miss a ring update when it notices a stopped queue.
6204 */
6205 smp_wmb();
1da177e4 6206 netif_stop_queue(dev);
ae1f23fb
FR		 6207 /* Sync with rtl_tx:
6208 * - publish queue status and cur_tx ring index (write barrier)
6209 * - refresh dirty_tx ring index (read barrier).
6210 * May the current thread have a pessimistic view of the ring
6211 * status and forget to wake up queue, a racing rtl_tx thread
6212 * can't.
6213 */
1e874e04 6214 smp_mb();
477206a0 6215 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 6216 netif_wake_queue(dev);
6217 }
6218
61357325 6219 return NETDEV_TX_OK;
1da177e4 6220
3eafe507 6221err_dma_1:
48addcc9 6222 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 6223err_dma_0:
989c9ba1 6224 dev_kfree_skb_any(skb);
3eafe507
SG		 6225 dev->stats.tx_dropped++;
6226 return NETDEV_TX_OK;
6227
6228err_stop_0:
1da177e4 6229 netif_stop_queue(dev);
cebf8cc7 6230 dev->stats.tx_dropped++;
61357325 6231 return NETDEV_TX_BUSY;
1da177e4
LT		 6232}
6233
6234static void rtl8169_pcierr_interrupt(struct net_device *dev)
6235{
6236 struct rtl8169_private *tp = netdev_priv(dev);
6237 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 6238 u16 pci_status, pci_cmd;
6239
6240 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6241 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6242
bf82c189
JP		 6243 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6244 pci_cmd, pci_status);
1da177e4
LT		 6245
6246 /*
6247 * The recovery sequence below admits a very elaborated explanation:
6248 * - it seems to work;
d03902b8
FR		 6249 * - I did not see what else could be done;
6250 * - it makes iop3xx happy.
1da177e4
LT		 6251 *
6252 * Feel free to adjust to your needs.
6253 */
a27993f3 6254 if (pdev->broken_parity_status)
d03902b8
FR		 6255 pci_cmd &= ~PCI_COMMAND_PARITY;
6256 else
6257 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6258
6259 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 6260
6261 pci_write_config_word(pdev, PCI_STATUS,
6262 pci_status & (PCI_STATUS_DETECTED_PARITY |
6263 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6264 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6265
6266 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 6267 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
bf82c189 6268 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4 6269 tp->cp_cmd &= ~PCIDAC;
1ef7286e 6270 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1da177e4 6271 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 6272 }
6273
e6de30d6 6274 rtl8169_hw_reset(tp);
d03902b8 6275
98ddf986 6276 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6277}
6278
da78dbff 6279static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 6280{
6281 unsigned int dirty_tx, tx_left;
6282
1da177e4
LT		 6283 dirty_tx = tp->dirty_tx;
6284 smp_rmb();
6285 tx_left = tp->cur_tx - dirty_tx;
6286
6287 while (tx_left > 0) {
6288 unsigned int entry = dirty_tx % NUM_TX_DESC;
6289 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 6290 u32 status;
6291
1da177e4
LT		 6292 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6293 if (status & DescOwn)
6294 break;
6295
a0750138
AD		 6296 /* This barrier is needed to keep us from reading
6297 * any other fields out of the Tx descriptor until
6298 * we know the status of DescOwn
6299 */
6300 dma_rmb();
6301
1e1205b7 6302 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
48addcc9 6303 tp->TxDescArray + entry);
1da177e4 6304 if (status & LastFrag) {
87cda7cb
DM		 6305 u64_stats_update_begin(&tp->tx_stats.syncp);
6306 tp->tx_stats.packets++;
6307 tp->tx_stats.bytes += tx_skb->skb->len;
6308 u64_stats_update_end(&tp->tx_stats.syncp);
7a4b813c 6309 dev_consume_skb_any(tx_skb->skb);
1da177e4
LT		 6310 tx_skb->skb = NULL;
6311 }
6312 dirty_tx++;
6313 tx_left--;
6314 }
6315
6316 if (tp->dirty_tx != dirty_tx) {
6317 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6318 /* Sync with rtl8169_start_xmit:
6319 * - publish dirty_tx ring index (write barrier)
6320 * - refresh cur_tx ring index and queue status (read barrier)
6321 * May the current thread miss the stopped queue condition,
6322 * a racing xmit thread can only have a right view of the
6323 * ring status.
6324 */
1e874e04 6325 smp_mb();
1da177e4 6326 if (netif_queue_stopped(dev) &&
477206a0 6327 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6328 netif_wake_queue(dev);
6329 }
d78ae2dc
FR		 6330 /*
6331 * 8168 hack: TxPoll requests are lost when the Tx packets are
6332 * too close. Let's kick an extra TxPoll request when a burst
6333 * of start_xmit activity is detected (if it is not detected,
6334 * it is slow enough). -- FR
6335 */
1ef7286e
AS		 6336 if (tp->cur_tx != dirty_tx)
6337 RTL_W8(tp, TxPoll, NPQ);
1da177e4
LT		 6338 }
6339}
6340
126fa4b9
FR		 6341static inline int rtl8169_fragmented_frame(u32 status)
6342{
6343 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6344}
6345
adea1ac7 6346static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6347{
1da177e4
LT		 6348 u32 status = opts1 & RxProtoMask;
6349
6350 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6351 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6352 skb->ip_summed = CHECKSUM_UNNECESSARY;
6353 else
bc8acf2c 6354 skb_checksum_none_assert(skb);
1da177e4
LT		 6355}
6356
6f0333b8
ED		 6357static struct sk_buff *rtl8169_try_rx_copy(void *data,
6358 struct rtl8169_private *tp,
6359 int pkt_size,
6360 dma_addr_t addr)
1da177e4 6361{
b449655f 6362 struct sk_buff *skb;
1e1205b7 6363 struct device *d = tp_to_dev(tp);
b449655f 6364
6f0333b8 6365 data = rtl8169_align(data);
48addcc9 6366 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8 6367 prefetch(data);
e2338f86 6368 skb = napi_alloc_skb(&tp->napi, pkt_size);
6f0333b8 6369 if (skb)
8a67aa86 6370 skb_copy_to_linear_data(skb, data, pkt_size);
48addcc9
SG		 6371 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6372
6f0333b8 6373 return skb;
1da177e4
LT		 6374}
6375
da78dbff 6376static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6377{
6378 unsigned int cur_rx, rx_left;
6f0333b8 6379 unsigned int count;
1da177e4 6380
1da177e4 6381 cur_rx = tp->cur_rx;
1da177e4 6382
9fba0812 6383 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6384 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6385 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6386 u32 status;
6387
6202806e 6388 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 6389 if (status & DescOwn)
6390 break;
a0750138
AD		 6391
6392 /* This barrier is needed to keep us from reading
6393 * any other fields out of the Rx descriptor until
6394 * we know the status of DescOwn
6395 */
6396 dma_rmb();
6397
4dcb7d33 6398 if (unlikely(status & RxRES)) {
bf82c189
JP		 6399 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6400 status);
cebf8cc7 6401 dev->stats.rx_errors++;
1da177e4 6402 if (status & (RxRWT | RxRUNT))
cebf8cc7 6403 dev->stats.rx_length_errors++;
1da177e4 6404 if (status & RxCRC)
cebf8cc7 6405 dev->stats.rx_crc_errors++;
6202806e
HK		 6406 /* RxFOVF is a reserved bit on later chip versions */
6407 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6408 status & RxFOVF) {
da78dbff 6409 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6410 dev->stats.rx_fifo_errors++;
6202806e
HK		 6411 } else if (status & (RxRUNT | RxCRC) &&
6412 !(status & RxRWT) &&
6413 dev->features & NETIF_F_RXALL) {
6bbe021d 6414 goto process_pkt;
6202806e 6415 }
1da177e4 6416 } else {
6f0333b8 6417 struct sk_buff *skb;
6bbe021d
BG		 6418 dma_addr_t addr;
6419 int pkt_size;
6420
6421process_pkt:
6422 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6423 if (likely(!(dev->features & NETIF_F_RXFCS)))
6424 pkt_size = (status & 0x00003fff) - 4;
6425 else
6426 pkt_size = status & 0x00003fff;
1da177e4 6427
126fa4b9
FR		 6428 /*
6429 * The driver does not support incoming fragmented
6430 * frames. They are seen as a symptom of over-mtu
6431 * sized frames.
6432 */
6433 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6434 dev->stats.rx_dropped++;
6435 dev->stats.rx_length_errors++;
ce11ff5e 6436 goto release_descriptor;
126fa4b9
FR		 6437 }
6438
6f0333b8
ED		 6439 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6440 tp, pkt_size, addr);
6f0333b8
ED		 6441 if (!skb) {
6442 dev->stats.rx_dropped++;
ce11ff5e 6443 goto release_descriptor;
1da177e4
LT		 6444 }
6445
adea1ac7 6446 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6447 skb_put(skb, pkt_size);
6448 skb->protocol = eth_type_trans(skb, dev);
6449
7a8fc77b
FR		 6450 rtl8169_rx_vlan_tag(desc, skb);
6451
39174291 6452 if (skb->pkt_type == PACKET_MULTICAST)
6453 dev->stats.multicast++;
6454
56de414c 6455 napi_gro_receive(&tp->napi, skb);
1da177e4 6456
8027aa24
JW		 6457 u64_stats_update_begin(&tp->rx_stats.syncp);
6458 tp->rx_stats.packets++;
6459 tp->rx_stats.bytes += pkt_size;
6460 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6461 }
ce11ff5e 6462release_descriptor:
6463 desc->opts2 = 0;
1d0254dd 6464 rtl8169_mark_to_asic(desc);
1da177e4
LT		 6465 }
6466
6467 count = cur_rx - tp->cur_rx;
6468 tp->cur_rx = cur_rx;
6469
1da177e4
LT		 6470 return count;
6471}
6472
07d3f51f 6473static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6474{
ebcd5daa 6475 struct rtl8169_private *tp = dev_instance;
05bbe558 6476 u16 status = rtl_get_events(tp);
1da177e4 6477
05bbe558
HK		 6478 if (status == 0xffff || !(status & (RTL_EVENT_NAPI | tp->event_slow)))
6479 return IRQ_NONE;
1da177e4 6480
05bbe558
HK		 6481 rtl_irq_disable(tp);
6482 napi_schedule_irqoff(&tp->napi);
6483
6484 return IRQ_HANDLED;
da78dbff 6485}
1da177e4 6486
da78dbff
FR		 6487/*
6488 * Workqueue context.
6489 */
6490static void rtl_slow_event_work(struct rtl8169_private *tp)
6491{
6492 struct net_device *dev = tp->dev;
6493 u16 status;
6494
6495 status = rtl_get_events(tp) & tp->event_slow;
6496 rtl_ack_events(tp, status);
1da177e4 6497
da78dbff
FR		 6498 if (unlikely(status & RxFIFOOver)) {
6499 switch (tp->mac_version) {
6500 /* Work around for rx fifo overflow */
6501 case RTL_GIGA_MAC_VER_11:
6502 netif_stop_queue(dev);
934714d0
FR		 6503 /* XXX - Hack alert. See rtl_task(). */
6504 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6505 default:
f11a377b
DD		 6506 break;
6507 }
da78dbff 6508 }
1da177e4 6509
da78dbff
FR		 6510 if (unlikely(status & SYSErr))
6511 rtl8169_pcierr_interrupt(dev);
0e485150 6512
da78dbff 6513 if (status & LinkChg)
f1e911d5 6514 phy_mac_interrupt(dev->phydev);
1da177e4 6515
7dbb4918 6516 rtl_irq_enable_all(tp);
1da177e4
LT		 6517}
6518
4422bcd4
FR		 6519static void rtl_task(struct work_struct *work)
6520{
da78dbff
FR		 6521 static const struct {
6522 int bitnr;
6523 void (*action)(struct rtl8169_private *);
6524 } rtl_work[] = {
934714d0 6525 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6526 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6527 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
da78dbff 6528 };
4422bcd4
FR		 6529 struct rtl8169_private *tp =
6530 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6531 struct net_device *dev = tp->dev;
6532 int i;
6533
6534 rtl_lock_work(tp);
6535
6c4a70c5
FR		 6536 if (!netif_running(dev) ||
6537 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6538 goto out_unlock;
6539
6540 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6541 bool pending;
6542
da78dbff 6543 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6544 if (pending)
6545 rtl_work[i].action(tp);
6546 }
4422bcd4 6547
da78dbff
FR		 6548out_unlock:
6549 rtl_unlock_work(tp);
4422bcd4
FR		 6550}
6551
bea3348e 6552static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6553{
bea3348e
SH		 6554 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6555 struct net_device *dev = tp->dev;
da78dbff
FR		 6556 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6557 int work_done= 0;
6558 u16 status;
6559
6560 status = rtl_get_events(tp);
6561 rtl_ack_events(tp, status & ~tp->event_slow);
6562
6563 if (status & RTL_EVENT_NAPI_RX)
6564 work_done = rtl_rx(dev, tp, (u32) budget);
6565
6566 if (status & RTL_EVENT_NAPI_TX)
6567 rtl_tx(dev, tp);
1da177e4 6568
da78dbff
FR		 6569 if (status & tp->event_slow) {
6570 enable_mask &= ~tp->event_slow;
6571
6572 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6573 }
1da177e4 6574
bea3348e 6575 if (work_done < budget) {
6ad20165 6576 napi_complete_done(napi, work_done);
f11a377b 6577
da78dbff
FR		 6578 rtl_irq_enable(tp, enable_mask);
6579 mmiowb();
1da177e4
LT		 6580 }
6581
bea3348e 6582 return work_done;
1da177e4 6583}
1da177e4 6584
1ef7286e 6585static void rtl8169_rx_missed(struct net_device *dev)
523a6094
FR		 6586{
6587 struct rtl8169_private *tp = netdev_priv(dev);
6588
6589 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6590 return;
6591
1ef7286e
AS		 6592 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6593 RTL_W32(tp, RxMissed, 0);
523a6094
FR		 6594}
6595
f1e911d5
HK		 6596static void r8169_phylink_handler(struct net_device *ndev)
6597{
6598 struct rtl8169_private *tp = netdev_priv(ndev);
6599
6600 if (netif_carrier_ok(ndev)) {
6601 rtl_link_chg_patch(tp);
6602 pm_request_resume(&tp->pci_dev->dev);
6603 } else {
6604 pm_runtime_idle(&tp->pci_dev->dev);
6605 }
6606
6607 if (net_ratelimit())
6608 phy_print_status(ndev->phydev);
6609}
6610
6611static int r8169_phy_connect(struct rtl8169_private *tp)
6612{
6613 struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6614 phy_interface_t phy_mode;
6615 int ret;
6616
f7ffa9ae 6617 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
f1e911d5
HK		 6618 PHY_INTERFACE_MODE_MII;
6619
6620 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6621 phy_mode);
6622 if (ret)
6623 return ret;
6624
f7ffa9ae 6625 if (!tp->supports_gmii)
f1e911d5
HK		 6626 phy_set_max_speed(phydev, SPEED_100);
6627
6628 /* Ensure to advertise everything, incl. pause */
6629 phydev->advertising = phydev->supported;
6630
6631 phy_attached_info(phydev);
6632
6633 return 0;
6634}
6635
1da177e4
LT		 6636static void rtl8169_down(struct net_device *dev)
6637{
6638 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6639
f1e911d5
HK		 6640 phy_stop(dev->phydev);
6641
93dd79e8 6642 napi_disable(&tp->napi);
da78dbff 6643 netif_stop_queue(dev);
1da177e4 6644
92fc43b4 6645 rtl8169_hw_reset(tp);
323bb685
SG		 6646 /*
6647 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6648 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6649 * and napi is disabled (rtl8169_poll).
323bb685 6650 */
1ef7286e 6651 rtl8169_rx_missed(dev);
1da177e4 6652
1da177e4 6653 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6654 synchronize_sched();
1da177e4 6655
1da177e4
LT		 6656 rtl8169_tx_clear(tp);
6657
6658 rtl8169_rx_clear(tp);
065c27c1 6659
6660 rtl_pll_power_down(tp);
1da177e4
LT		 6661}
6662
6663static int rtl8169_close(struct net_device *dev)
6664{
6665 struct rtl8169_private *tp = netdev_priv(dev);
6666 struct pci_dev *pdev = tp->pci_dev;
6667
e1759441
RW		 6668 pm_runtime_get_sync(&pdev->dev);
6669
cecb5fd7 6670 /* Update counters before going down */
e71c9ce2 6671 rtl8169_update_counters(tp);
355423d0 6672
da78dbff 6673 rtl_lock_work(tp);
6ad56901
KHF		 6674 /* Clear all task flags */
6675 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
da78dbff 6676
1da177e4 6677 rtl8169_down(dev);
da78dbff 6678 rtl_unlock_work(tp);
1da177e4 6679
4ea72445
L		 6680 cancel_work_sync(&tp->wk.work);
6681
f1e911d5
HK		 6682 phy_disconnect(dev->phydev);
6683
ebcd5daa 6684 pci_free_irq(pdev, 0, tp);
1da177e4 6685
82553bb6
SG		 6686 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6687 tp->RxPhyAddr);
6688 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6689 tp->TxPhyAddr);
1da177e4
LT		 6690 tp->TxDescArray = NULL;
6691 tp->RxDescArray = NULL;
6692
e1759441
RW		 6693 pm_runtime_put_sync(&pdev->dev);
6694
1da177e4
LT		 6695 return 0;
6696}
6697
dc1c00ce
FR		 6698#ifdef CONFIG_NET_POLL_CONTROLLER
6699static void rtl8169_netpoll(struct net_device *dev)
6700{
6701 struct rtl8169_private *tp = netdev_priv(dev);
6702
6d8b8349 6703 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
dc1c00ce
FR		 6704}
6705#endif
6706
df43ac78
FR		 6707static int rtl_open(struct net_device *dev)
6708{
6709 struct rtl8169_private *tp = netdev_priv(dev);
df43ac78
FR		 6710 struct pci_dev *pdev = tp->pci_dev;
6711 int retval = -ENOMEM;
6712
6713 pm_runtime_get_sync(&pdev->dev);
6714
6715 /*
e75d6606 6716 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6717 * dma_alloc_coherent provides more.
6718 */
6719 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6720 &tp->TxPhyAddr, GFP_KERNEL);
6721 if (!tp->TxDescArray)
6722 goto err_pm_runtime_put;
6723
6724 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6725 &tp->RxPhyAddr, GFP_KERNEL);
6726 if (!tp->RxDescArray)
6727 goto err_free_tx_0;
6728
b1127e64 6729 retval = rtl8169_init_ring(tp);
df43ac78
FR		 6730 if (retval < 0)
6731 goto err_free_rx_1;
6732
6733 INIT_WORK(&tp->wk.work, rtl_task);
6734
6735 smp_mb();
6736
6737 rtl_request_firmware(tp);
6738
ebcd5daa 6739 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6c6aa15f 6740 dev->name);
df43ac78
FR		 6741 if (retval < 0)
6742 goto err_release_fw_2;
6743
f1e911d5
HK		 6744 retval = r8169_phy_connect(tp);
6745 if (retval)
6746 goto err_free_irq;
6747
df43ac78
FR		 6748 rtl_lock_work(tp);
6749
6750 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6751
6752 napi_enable(&tp->napi);
6753
6754 rtl8169_init_phy(dev, tp);
6755
df43ac78
FR		 6756 rtl_pll_power_up(tp);
6757
61cb532d 6758 rtl_hw_start(tp);
df43ac78 6759
e71c9ce2 6760 if (!rtl8169_init_counter_offsets(tp))
6e85d5ad
CV		 6761 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6762
f1e911d5 6763 phy_start(dev->phydev);
df43ac78
FR		 6764 netif_start_queue(dev);
6765
6766 rtl_unlock_work(tp);
6767
a92a0849 6768 pm_runtime_put_sync(&pdev->dev);
df43ac78
FR		 6769out:
6770 return retval;
6771
f1e911d5
HK		 6772err_free_irq:
6773 pci_free_irq(pdev, 0, tp);
df43ac78
FR		 6774err_release_fw_2:
6775 rtl_release_firmware(tp);
6776 rtl8169_rx_clear(tp);
6777err_free_rx_1:
6778 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6779 tp->RxPhyAddr);
6780 tp->RxDescArray = NULL;
6781err_free_tx_0:
6782 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6783 tp->TxPhyAddr);
6784 tp->TxDescArray = NULL;
6785err_pm_runtime_put:
6786 pm_runtime_put_noidle(&pdev->dev);
6787 goto out;
6788}
6789
bc1f4470 6790static void
8027aa24 6791rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6792{
6793 struct rtl8169_private *tp = netdev_priv(dev);
f09cf4b7 6794 struct pci_dev *pdev = tp->pci_dev;
42020320 6795 struct rtl8169_counters *counters = tp->counters;
8027aa24 6796 unsigned int start;
1da177e4 6797
f09cf4b7
CHL		 6798 pm_runtime_get_noresume(&pdev->dev);
6799
6800 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
1ef7286e 6801 rtl8169_rx_missed(dev);
5b0384f4 6802
8027aa24 6803 do {
57a7744e 6804 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 6805 stats->rx_packets = tp->rx_stats.packets;
6806 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 6807 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 6808
8027aa24 6809 do {
57a7744e 6810 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 6811 stats->tx_packets = tp->tx_stats.packets;
6812 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 6813 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 6814
6815 stats->rx_dropped = dev->stats.rx_dropped;
6816 stats->tx_dropped = dev->stats.tx_dropped;
6817 stats->rx_length_errors = dev->stats.rx_length_errors;
6818 stats->rx_errors = dev->stats.rx_errors;
6819 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6820 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6821 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 6822 stats->multicast = dev->stats.multicast;
8027aa24 6823
6e85d5ad
CV		 6824 /*
6825 * Fetch additonal counter values missing in stats collected by driver
6826 * from tally counters.
6827 */
f09cf4b7 6828 if (pm_runtime_active(&pdev->dev))
e71c9ce2 6829 rtl8169_update_counters(tp);
6e85d5ad
CV		 6830
6831 /*
6832 * Subtract values fetched during initalization.
6833 * See rtl8169_init_counter_offsets for a description why we do that.
6834 */
42020320 6835 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 6836 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 6837 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 6838 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 6839 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 6840 le16_to_cpu(tp->tc_offset.tx_aborted);
6841
f09cf4b7 6842 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 6843}
6844
861ab440 6845static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6846{
065c27c1 6847 struct rtl8169_private *tp = netdev_priv(dev);
6848
5d06a99f 6849 if (!netif_running(dev))
861ab440 6850 return;
5d06a99f 6851
f1e911d5 6852 phy_stop(dev->phydev);
5d06a99f
FR		 6853 netif_device_detach(dev);
6854 netif_stop_queue(dev);
da78dbff
FR		 6855
6856 rtl_lock_work(tp);
6857 napi_disable(&tp->napi);
6ad56901
KHF		 6858 /* Clear all task flags */
6859 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6860
da78dbff
FR		 6861 rtl_unlock_work(tp);
6862
6863 rtl_pll_power_down(tp);
861ab440
RW		 6864}
6865
6866#ifdef CONFIG_PM
6867
6868static int rtl8169_suspend(struct device *device)
6869{
6870 struct pci_dev *pdev = to_pci_dev(device);
6871 struct net_device *dev = pci_get_drvdata(pdev);
ac8bd9e1 6872 struct rtl8169_private *tp = netdev_priv(dev);
5d06a99f 6873
861ab440 6874 rtl8169_net_suspend(dev);
ac8bd9e1 6875 clk_disable_unprepare(tp->clk);
1371fa6d 6876
5d06a99f
FR		 6877 return 0;
6878}
6879
e1759441
RW		 6880static void __rtl8169_resume(struct net_device *dev)
6881{
065c27c1 6882 struct rtl8169_private *tp = netdev_priv(dev);
6883
e1759441 6884 netif_device_attach(dev);
065c27c1 6885
6886 rtl_pll_power_up(tp);
92bad850 6887 rtl8169_init_phy(dev, tp);
065c27c1 6888
f1e911d5
HK		 6889 phy_start(tp->dev->phydev);
6890
cff4c162
AS		 6891 rtl_lock_work(tp);
6892 napi_enable(&tp->napi);
6c4a70c5 6893 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6894 rtl_unlock_work(tp);
da78dbff 6895
98ddf986 6896 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6897}
6898
861ab440 6899static int rtl8169_resume(struct device *device)
5d06a99f 6900{
861ab440 6901 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6902 struct net_device *dev = pci_get_drvdata(pdev);
ac8bd9e1
HG		 6903 struct rtl8169_private *tp = netdev_priv(dev);
6904
6905 clk_prepare_enable(tp->clk);
5d06a99f 6906
e1759441
RW		 6907 if (netif_running(dev))
6908 __rtl8169_resume(dev);
5d06a99f 6909
e1759441
RW		 6910 return 0;
6911}
6912
6913static int rtl8169_runtime_suspend(struct device *device)
6914{
6915 struct pci_dev *pdev = to_pci_dev(device);
6916 struct net_device *dev = pci_get_drvdata(pdev);
6917 struct rtl8169_private *tp = netdev_priv(dev);
6918
07df5bd8 6919 if (!tp->TxDescArray)
e1759441
RW		 6920 return 0;
6921
da78dbff 6922 rtl_lock_work(tp);
e1759441 6923 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6924 rtl_unlock_work(tp);
e1759441
RW		 6925
6926 rtl8169_net_suspend(dev);
6927
f09cf4b7 6928 /* Update counters before going runtime suspend */
1ef7286e 6929 rtl8169_rx_missed(dev);
e71c9ce2 6930 rtl8169_update_counters(tp);
f09cf4b7 6931
e1759441
RW		 6932 return 0;
6933}
6934
6935static int rtl8169_runtime_resume(struct device *device)
6936{
6937 struct pci_dev *pdev = to_pci_dev(device);
6938 struct net_device *dev = pci_get_drvdata(pdev);
6939 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 6940 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 6941
6942 if (!tp->TxDescArray)
6943 return 0;
6944
da78dbff 6945 rtl_lock_work(tp);
e1759441 6946 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff 6947 rtl_unlock_work(tp);
e1759441
RW		 6948
6949 __rtl8169_resume(dev);
5d06a99f 6950
5d06a99f
FR		 6951 return 0;
6952}
6953
e1759441
RW		 6954static int rtl8169_runtime_idle(struct device *device)
6955{
6956 struct pci_dev *pdev = to_pci_dev(device);
6957 struct net_device *dev = pci_get_drvdata(pdev);
e1759441 6958
a92a0849
HK		 6959 if (!netif_running(dev) || !netif_carrier_ok(dev))
6960 pm_schedule_suspend(device, 10000);
6961
6962 return -EBUSY;
e1759441
RW		 6963}
6964
47145210 6965static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6966 .suspend = rtl8169_suspend,
6967 .resume = rtl8169_resume,
6968 .freeze = rtl8169_suspend,
6969 .thaw = rtl8169_resume,
6970 .poweroff = rtl8169_suspend,
6971 .restore = rtl8169_resume,
6972 .runtime_suspend = rtl8169_runtime_suspend,
6973 .runtime_resume = rtl8169_runtime_resume,
6974 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6975};
6976
6977#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6978
6979#else /* !CONFIG_PM */
6980
6981#define RTL8169_PM_OPS NULL
6982
6983#endif /* !CONFIG_PM */
6984
649b3b8c 6985static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6986{
649b3b8c 6987 /* WoL fails with 8168b when the receiver is disabled. */
6988 switch (tp->mac_version) {
6989 case RTL_GIGA_MAC_VER_11:
6990 case RTL_GIGA_MAC_VER_12:
6991 case RTL_GIGA_MAC_VER_17:
6992 pci_clear_master(tp->pci_dev);
6993
1ef7286e 6994 RTL_W8(tp, ChipCmd, CmdRxEnb);
649b3b8c 6995 /* PCI commit */
1ef7286e 6996 RTL_R8(tp, ChipCmd);
649b3b8c 6997 break;
6998 default:
6999 break;
7000 }
7001}
7002
1765f95d
FR		 7003static void rtl_shutdown(struct pci_dev *pdev)
7004{
861ab440 7005 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 7006 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 7007
7008 rtl8169_net_suspend(dev);
1765f95d 7009
cecb5fd7 7010 /* Restore original MAC address */
cc098dc7
IV		 7011 rtl_rar_set(tp, dev->perm_addr);
7012
92fc43b4 7013 rtl8169_hw_reset(tp);
4bb3f522 7014
861ab440 7015 if (system_state == SYSTEM_POWER_OFF) {
433f9d0d 7016 if (tp->saved_wolopts) {
649b3b8c 7017 rtl_wol_suspend_quirk(tp);
7018 rtl_wol_shutdown_quirk(tp);
ca52efd5 7019 }
7020
861ab440
RW		 7021 pci_wake_from_d3(pdev, true);
7022 pci_set_power_state(pdev, PCI_D3hot);
7023 }
7024}
5d06a99f 7025
baf63293 7026static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 7027{
7028 struct net_device *dev = pci_get_drvdata(pdev);
7029 struct rtl8169_private *tp = netdev_priv(dev);
7030
9dbe7896 7031 if (r8168_check_dash(tp))
e27566ed 7032 rtl8168_driver_stop(tp);
e27566ed 7033
ad1be8d3
DN		 7034 netif_napi_del(&tp->napi);
7035
e27566ed 7036 unregister_netdev(dev);
f1e911d5 7037 mdiobus_unregister(tp->mii_bus);
e27566ed
FR		 7038
7039 rtl_release_firmware(tp);
7040
7041 if (pci_dev_run_wake(pdev))
7042 pm_runtime_get_noresume(&pdev->dev);
7043
7044 /* restore original MAC address */
7045 rtl_rar_set(tp, dev->perm_addr);
e27566ed
FR		 7046}
7047
fa9c385e 7048static const struct net_device_ops rtl_netdev_ops = {
df43ac78 7049 .ndo_open = rtl_open,
fa9c385e
FR		 7050 .ndo_stop = rtl8169_close,
7051 .ndo_get_stats64 = rtl8169_get_stats64,
7052 .ndo_start_xmit = rtl8169_start_xmit,
7053 .ndo_tx_timeout = rtl8169_tx_timeout,
7054 .ndo_validate_addr = eth_validate_addr,
7055 .ndo_change_mtu = rtl8169_change_mtu,
7056 .ndo_fix_features = rtl8169_fix_features,
7057 .ndo_set_features = rtl8169_set_features,
7058 .ndo_set_mac_address = rtl_set_mac_address,
7059 .ndo_do_ioctl = rtl8169_ioctl,
7060 .ndo_set_rx_mode = rtl_set_rx_mode,
7061#ifdef CONFIG_NET_POLL_CONTROLLER
7062 .ndo_poll_controller = rtl8169_netpoll,
7063#endif
7064
7065};
7066
31fa8b18 7067static const struct rtl_cfg_info {
61cb532d 7068 void (*hw_start)(struct rtl8169_private *tp);
31fa8b18 7069 u16 event_slow;
14967f94 7070 unsigned int has_gmii:1;
50970831 7071 const struct rtl_coalesce_info *coalesce_info;
31fa8b18
FR		 7072 u8 default_ver;
7073} rtl_cfg_infos [] = {
7074 [RTL_CFG_0] = {
7075 .hw_start = rtl_hw_start_8169,
31fa8b18 7076 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
14967f94 7077 .has_gmii = 1,
50970831 7078 .coalesce_info = rtl_coalesce_info_8169,
31fa8b18
FR		 7079 .default_ver = RTL_GIGA_MAC_VER_01,
7080 },
7081 [RTL_CFG_1] = {
7082 .hw_start = rtl_hw_start_8168,
31fa8b18 7083 .event_slow = SYSErr | LinkChg | RxOverflow,
14967f94 7084 .has_gmii = 1,
50970831 7085 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 7086 .default_ver = RTL_GIGA_MAC_VER_11,
7087 },
7088 [RTL_CFG_2] = {
7089 .hw_start = rtl_hw_start_8101,
31fa8b18
FR		 7090 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7091 PCSTimeout,
50970831 7092 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 7093 .default_ver = RTL_GIGA_MAC_VER_13,
7094 }
7095};
7096
6c6aa15f 7097static int rtl_alloc_irq(struct rtl8169_private *tp)
31fa8b18 7098{
6c6aa15f 7099 unsigned int flags;
31fa8b18 7100
7bb05b85
JHP		 7101 switch (tp->mac_version) {
7102 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
1ef7286e
AS		 7103 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7104 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7105 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6c6aa15f 7106 flags = PCI_IRQ_LEGACY;
7bb05b85
JHP		 7107 break;
7108 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_40:
7c53a722
HK		 7109 /* This version was reported to have issues with resume
7110 * from suspend when using MSI-X
7111 */
7112 flags = PCI_IRQ_LEGACY | PCI_IRQ_MSI;
7bb05b85
JHP		 7113 break;
7114 default:
6c6aa15f 7115 flags = PCI_IRQ_ALL_TYPES;
31fa8b18 7116 }
6c6aa15f
HK		 7117
7118 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
31fa8b18
FR		 7119}
7120
c558386b
HW		 7121DECLARE_RTL_COND(rtl_link_list_ready_cond)
7122{
1ef7286e 7123 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
c558386b
HW		 7124}
7125
7126DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7127{
1ef7286e 7128 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
c558386b
HW		 7129}
7130
f1e911d5
HK		 7131static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7132{
7133 struct rtl8169_private *tp = mii_bus->priv;
7134
7135 if (phyaddr > 0)
7136 return -ENODEV;
7137
7138 return rtl_readphy(tp, phyreg);
7139}
7140
7141static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7142 int phyreg, u16 val)
7143{
7144 struct rtl8169_private *tp = mii_bus->priv;
7145
7146 if (phyaddr > 0)
7147 return -ENODEV;
7148
7149 rtl_writephy(tp, phyreg, val);
7150
7151 return 0;
7152}
7153
7154static int r8169_mdio_register(struct rtl8169_private *tp)
7155{
7156 struct pci_dev *pdev = tp->pci_dev;
7157 struct phy_device *phydev;
7158 struct mii_bus *new_bus;
7159 int ret;
7160
7161 new_bus = devm_mdiobus_alloc(&pdev->dev);
7162 if (!new_bus)
7163 return -ENOMEM;
7164
7165 new_bus->name = "r8169";
7166 new_bus->priv = tp;
7167 new_bus->parent = &pdev->dev;
7168 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7169 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7170 PCI_DEVID(pdev->bus->number, pdev->devfn));
7171
7172 new_bus->read = r8169_mdio_read_reg;
7173 new_bus->write = r8169_mdio_write_reg;
7174
7175 ret = mdiobus_register(new_bus);
7176 if (ret)
7177 return ret;
7178
7179 phydev = mdiobus_get_phy(new_bus, 0);
7180 if (!phydev) {
7181 mdiobus_unregister(new_bus);
7182 return -ENODEV;
7183 }
7184
242cd9b5
HK		 7185 /* PHY will be woken up in rtl_open() */
7186 phy_suspend(phydev);
7187
f1e911d5
HK		 7188 tp->mii_bus = new_bus;
7189
7190 return 0;
7191}
7192
baf63293 7193static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b 7194{
c558386b
HW		 7195 u32 data;
7196
7197 tp->ocp_base = OCP_STD_PHY_BASE;
7198
1ef7286e 7199 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
c558386b
HW		 7200
7201 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7202 return;
7203
7204 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7205 return;
7206
1ef7286e 7207 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
c558386b 7208 msleep(1);
1ef7286e 7209 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
c558386b 7210
5f8bcce9 7211 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7212 data &= ~(1 << 14);
7213 r8168_mac_ocp_write(tp, 0xe8de, data);
7214
7215 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7216 return;
7217
5f8bcce9 7218 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7219 data |= (1 << 15);
7220 r8168_mac_ocp_write(tp, 0xe8de, data);
7221
7222 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7223 return;
7224}
7225
003609da
CHL		 7226static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7227{
7228 rtl8168ep_stop_cmac(tp);
7229 rtl_hw_init_8168g(tp);
7230}
7231
baf63293 7232static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 7233{
7234 switch (tp->mac_version) {
2a71883c 7235 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
003609da
CHL		 7236 rtl_hw_init_8168g(tp);
7237 break;
2a71883c 7238 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
003609da 7239 rtl_hw_init_8168ep(tp);
c558386b 7240 break;
c558386b
HW		 7241 default:
7242 break;
7243 }
7244}
7245
eb88f5f7
HK		 7246/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7247static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7248{
7249 switch (tp->mac_version) {
7250 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7251 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7252 return false;
7253 default:
7254 return true;
7255 }
7256}
7257
abe8b2f7
HK		 7258static int rtl_jumbo_max(struct rtl8169_private *tp)
7259{
7260 /* Non-GBit versions don't support jumbo frames */
7261 if (!tp->supports_gmii)
7262 return JUMBO_1K;
7263
7264 switch (tp->mac_version) {
7265 /* RTL8169 */
7266 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7267 return JUMBO_7K;
7268 /* RTL8168b */
7269 case RTL_GIGA_MAC_VER_11:
7270 case RTL_GIGA_MAC_VER_12:
7271 case RTL_GIGA_MAC_VER_17:
7272 return JUMBO_4K;
7273 /* RTL8168c */
7274 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7275 return JUMBO_6K;
7276 default:
7277 return JUMBO_9K;
7278 }
7279}
7280
c2f6f3ee
HG		 7281static void rtl_disable_clk(void *data)
7282{
7283 clk_disable_unprepare(data);
7284}
7285
929a031d 7286static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 7287{
7288 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3b6cf25d 7289 struct rtl8169_private *tp;
3b6cf25d 7290 struct net_device *dev;
c8d48d9c 7291 int chipset, region, i;
abe8b2f7 7292 int jumbo_max, rc;
3b6cf25d 7293
4c45d24a
HK		 7294 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7295 if (!dev)
7296 return -ENOMEM;
3b6cf25d
FR		 7297
7298 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 7299 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 7300 tp = netdev_priv(dev);
7301 tp->dev = dev;
7302 tp->pci_dev = pdev;
7303 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
f7ffa9ae 7304 tp->supports_gmii = cfg->has_gmii;
3b6cf25d 7305
c2f6f3ee
HG		 7306 /* Get the *optional* external "ether_clk" used on some boards */
7307 tp->clk = devm_clk_get(&pdev->dev, "ether_clk");
7308 if (IS_ERR(tp->clk)) {
7309 rc = PTR_ERR(tp->clk);
7310 if (rc == -ENOENT) {
7311 /* clk-core allows NULL (for suspend / resume) */
7312 tp->clk = NULL;
7313 } else if (rc == -EPROBE_DEFER) {
7314 return rc;
7315 } else {
7316 dev_err(&pdev->dev, "failed to get clk: %d\n", rc);
7317 return rc;
7318 }
7319 } else {
7320 rc = clk_prepare_enable(tp->clk);
7321 if (rc) {
7322 dev_err(&pdev->dev, "failed to enable clk: %d\n", rc);
7323 return rc;
7324 }
7325
7326 rc = devm_add_action_or_reset(&pdev->dev, rtl_disable_clk,
7327 tp->clk);
7328 if (rc)
7329 return rc;
7330 }
7331
3b6cf25d 7332 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4c45d24a 7333 rc = pcim_enable_device(pdev);
3b6cf25d 7334 if (rc < 0) {
22148df0 7335 dev_err(&pdev->dev, "enable failure\n");
4c45d24a 7336 return rc;
3b6cf25d
FR		 7337 }
7338
4c45d24a 7339 if (pcim_set_mwi(pdev) < 0)
22148df0 7340 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
3b6cf25d 7341
c8d48d9c
HK		 7342 /* use first MMIO region */
7343 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7344 if (region < 0) {
22148df0 7345 dev_err(&pdev->dev, "no MMIO resource found\n");
4c45d24a 7346 return -ENODEV;
3b6cf25d
FR		 7347 }
7348
7349 /* check for weird/broken PCI region reporting */
7350 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
22148df0 7351 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
4c45d24a 7352 return -ENODEV;
3b6cf25d
FR		 7353 }
7354
93a00d4d 7355 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
3b6cf25d 7356 if (rc < 0) {
22148df0 7357 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
4c45d24a 7358 return rc;
3b6cf25d
FR		 7359 }
7360
93a00d4d 7361 tp->mmio_addr = pcim_iomap_table(pdev)[region];
3b6cf25d
FR		 7362
7363 if (!pci_is_pcie(pdev))
22148df0 7364 dev_info(&pdev->dev, "not PCI Express\n");
3b6cf25d
FR		 7365
7366 /* Identify chip attached to board */
22148df0 7367 rtl8169_get_mac_version(tp, cfg->default_ver);
3b6cf25d 7368
e397286b
HK		 7369 if (rtl_tbi_enabled(tp)) {
7370 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7371 return -ENODEV;
7372 }
7373
0ae0974e 7374 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
27896c83
AB		 7375
7376 if ((sizeof(dma_addr_t) > 4) &&
7377 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7378 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
f0076436
AB		 7379 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7380 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
27896c83
AB		 7381
7382 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7383 if (!pci_is_pcie(pdev))
7384 tp->cp_cmd |= PCIDAC;
7385 dev->features |= NETIF_F_HIGHDMA;
7386 } else {
7387 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7388 if (rc < 0) {
22148df0 7389 dev_err(&pdev->dev, "DMA configuration failed\n");
4c45d24a 7390 return rc;
27896c83
AB		 7391 }
7392 }
7393
3b6cf25d
FR		 7394 rtl_init_rxcfg(tp);
7395
7396 rtl_irq_disable(tp);
7397
c558386b
HW		 7398 rtl_hw_initialize(tp);
7399
3b6cf25d
FR		 7400 rtl_hw_reset(tp);
7401
7402 rtl_ack_events(tp, 0xffff);
7403
7404 pci_set_master(pdev);
7405
3b6cf25d 7406 rtl_init_mdio_ops(tp);
3b6cf25d
FR		 7407 rtl_init_jumbo_ops(tp);
7408
7409 rtl8169_print_mac_version(tp);
7410
7411 chipset = tp->mac_version;
3b6cf25d 7412
6c6aa15f
HK		 7413 rc = rtl_alloc_irq(tp);
7414 if (rc < 0) {
22148df0 7415 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6c6aa15f
HK		 7416 return rc;
7417 }
3b6cf25d 7418
18041b52 7419 tp->saved_wolopts = __rtl8169_get_wol(tp);
7edf6d31 7420
3b6cf25d 7421 mutex_init(&tp->wk.mutex);
340fea3d
KM		 7422 u64_stats_init(&tp->rx_stats.syncp);
7423 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 7424
7425 /* Get MAC address */
b2d43e6e 7426 switch (tp->mac_version) {
353af85e 7427 u8 mac_addr[ETH_ALEN] __aligned(4);
b2d43e6e
HK		 7428 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7429 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
05b9687b 7430 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
353af85e 7431 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89 7432
353af85e
HK		 7433 if (is_valid_ether_addr(mac_addr))
7434 rtl_rar_set(tp, mac_addr);
b2d43e6e
HK		 7435 break;
7436 default:
7437 break;
6e1d0b89 7438 }
3b6cf25d 7439 for (i = 0; i < ETH_ALEN; i++)
1ef7286e 7440 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
3b6cf25d 7441
7ad24ea4 7442 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 7443 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d 7444
37621493 7445 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
3b6cf25d
FR		 7446
7447 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7448 * properly for all devices */
7449 dev->features |= NETIF_F_RXCSUM |
f646968f 7450 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7451
7452 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 7453 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7454 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7455 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7456 NETIF_F_HIGHDMA;
2d0ec544 7457 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3b6cf25d 7458
929a031d 7459 tp->cp_cmd |= RxChkSum | RxVlan;
7460
7461 /*
7462 * Pretend we are using VLANs; This bypasses a nasty bug where
7463 * Interrupts stop flowing on high load on 8110SCd controllers.
7464 */
3b6cf25d 7465 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 7466 /* Disallow toggling */
f646968f 7467 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 7468
eb88f5f7 7469 if (rtl_chip_supports_csum_v2(tp)) {
5888d3fc 7470 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 7471 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
eb88f5f7
HK		 7472 } else {
7473 tp->tso_csum = rtl8169_tso_csum_v1;
a4328ddb 7474 }
5888d3fc 7475
3b6cf25d
FR		 7476 dev->hw_features |= NETIF_F_RXALL;
7477 dev->hw_features |= NETIF_F_RXFCS;
7478
c7315a95
JW		 7479 /* MTU range: 60 - hw-specific max */
7480 dev->min_mtu = ETH_ZLEN;
abe8b2f7
HK		 7481 jumbo_max = rtl_jumbo_max(tp);
7482 dev->max_mtu = jumbo_max;
c7315a95 7483
3b6cf25d
FR		 7484 tp->hw_start = cfg->hw_start;
7485 tp->event_slow = cfg->event_slow;
50970831 7486 tp->coalesce_info = cfg->coalesce_info;
3b6cf25d 7487
3b6cf25d
FR		 7488 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7489
4c45d24a
HK		 7490 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7491 &tp->counters_phys_addr,
7492 GFP_KERNEL);
4cf964af
HK		 7493 if (!tp->counters)
7494 return -ENOMEM;
42020320 7495
19c9ea36
HK		 7496 pci_set_drvdata(pdev, dev);
7497
f1e911d5
HK		 7498 rc = r8169_mdio_register(tp);
7499 if (rc)
4cf964af 7500 return rc;
3b6cf25d 7501
07df5bd8
HK		 7502 /* chip gets powered up in rtl_open() */
7503 rtl_pll_power_down(tp);
7504
f1e911d5
HK		 7505 rc = register_netdev(dev);
7506 if (rc)
7507 goto err_mdio_unregister;
7508
2d6c5a61
HK		 7509 netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7510 rtl_chip_infos[chipset].name, dev->dev_addr,
90b989c5 7511 (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
29274991 7512 pci_irq_vector(pdev, 0));
abe8b2f7
HK		 7513
7514 if (jumbo_max > JUMBO_1K)
7515 netif_info(tp, probe, dev,
7516 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7517 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7518 "ok" : "ko");
3b6cf25d 7519
9dbe7896 7520 if (r8168_check_dash(tp))
3b6cf25d 7521 rtl8168_driver_start(tp);
3b6cf25d 7522
a92a0849
HK		 7523 if (pci_dev_run_wake(pdev))
7524 pm_runtime_put_sync(&pdev->dev);
7525
4c45d24a 7526 return 0;
f1e911d5
HK		 7527
7528err_mdio_unregister:
7529 mdiobus_unregister(tp->mii_bus);
7530 return rc;
3b6cf25d
FR		 7531}
7532
1da177e4
LT		 7533static struct pci_driver rtl8169_pci_driver = {
7534 .name = MODULENAME,
7535 .id_table = rtl8169_pci_tbl,
3b6cf25d 7536 .probe = rtl_init_one,
baf63293 7537 .remove = rtl_remove_one,
1765f95d 7538 .shutdown = rtl_shutdown,
861ab440 7539 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7540};
7541
3eeb7da9 7542module_pci_driver(rtl8169_pci_driver);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git