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Commit | Line | Data |
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1da177e4 | 1 | /* |
07d3f51f FR |
2 | * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
3 | * | |
4 | * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> | |
5 | * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> | |
6 | * Copyright (c) a lot of people too. Please respect their work. | |
7 | * | |
8 | * See MAINTAINERS file for support contact information. | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/mii.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/in.h> | |
22 | #include <linux/ip.h> | |
23 | #include <linux/tcp.h> | |
a6b7a407 | 24 | #include <linux/interrupt.h> |
1da177e4 | 25 | #include <linux/dma-mapping.h> |
e1759441 | 26 | #include <linux/pm_runtime.h> |
bca03d5f | 27 | #include <linux/firmware.h> |
ba04c7c9 | 28 | #include <linux/pci-aspm.h> |
70c71606 | 29 | #include <linux/prefetch.h> |
e974604b | 30 | #include <linux/ipv6.h> |
31 | #include <net/ip6_checksum.h> | |
1da177e4 LT |
32 | |
33 | #include <asm/io.h> | |
34 | #include <asm/irq.h> | |
35 | ||
865c652d | 36 | #define RTL8169_VERSION "2.3LK-NAPI" |
1da177e4 LT |
37 | #define MODULENAME "r8169" |
38 | #define PFX MODULENAME ": " | |
39 | ||
bca03d5f | 40 | #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" |
41 | #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" | |
01dc7fec | 42 | #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" |
43 | #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" | |
70090424 | 44 | #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" |
c2218925 HW |
45 | #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" |
46 | #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" | |
5a5e4443 | 47 | #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" |
7e18dca1 | 48 | #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" |
b3d7b2f2 | 49 | #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" |
45dd95c4 | 50 | #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" |
5598bfe5 | 51 | #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" |
58152cd4 | 52 | #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" |
beb330a4 | 53 | #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" |
57538c4a | 54 | #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" |
6e1d0b89 CHL |
55 | #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" |
56 | #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" | |
57 | #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" | |
58 | #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" | |
bca03d5f | 59 | |
1da177e4 LT |
60 | #ifdef RTL8169_DEBUG |
61 | #define assert(expr) \ | |
5b0384f4 FR |
62 | if (!(expr)) { \ |
63 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
b39d66a8 | 64 | #expr,__FILE__,__func__,__LINE__); \ |
5b0384f4 | 65 | } |
06fa7358 JP |
66 | #define dprintk(fmt, args...) \ |
67 | do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) | |
1da177e4 LT |
68 | #else |
69 | #define assert(expr) do {} while (0) | |
70 | #define dprintk(fmt, args...) do {} while (0) | |
71 | #endif /* RTL8169_DEBUG */ | |
72 | ||
b57b7e5a | 73 | #define R8169_MSG_DEFAULT \ |
f0e837d9 | 74 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
b57b7e5a | 75 | |
477206a0 JD |
76 | #define TX_SLOTS_AVAIL(tp) \ |
77 | (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx) | |
78 | ||
79 | /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ | |
80 | #define TX_FRAGS_READY_FOR(tp,nr_frags) \ | |
81 | (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1)) | |
1da177e4 | 82 | |
1da177e4 LT |
83 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
84 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 85 | static const int multicast_filter_limit = 32; |
1da177e4 | 86 | |
9c14ceaf | 87 | #define MAX_READ_REQUEST_SHIFT 12 |
aee77e4a | 88 | #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ |
1da177e4 LT |
89 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
90 | ||
91 | #define R8169_REGS_SIZE 256 | |
92 | #define R8169_NAPI_WEIGHT 64 | |
93 | #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ | |
9fba0812 | 94 | #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ |
1da177e4 LT |
95 | #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) |
96 | #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) | |
97 | ||
98 | #define RTL8169_TX_TIMEOUT (6*HZ) | |
99 | #define RTL8169_PHY_TIMEOUT (10*HZ) | |
100 | ||
101 | /* write/read MMIO register */ | |
102 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) | |
103 | #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) | |
104 | #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) | |
105 | #define RTL_R8(reg) readb (ioaddr + (reg)) | |
106 | #define RTL_R16(reg) readw (ioaddr + (reg)) | |
06f555f3 | 107 | #define RTL_R32(reg) readl (ioaddr + (reg)) |
1da177e4 LT |
108 | |
109 | enum mac_version { | |
85bffe6c FR |
110 | RTL_GIGA_MAC_VER_01 = 0, |
111 | RTL_GIGA_MAC_VER_02, | |
112 | RTL_GIGA_MAC_VER_03, | |
113 | RTL_GIGA_MAC_VER_04, | |
114 | RTL_GIGA_MAC_VER_05, | |
115 | RTL_GIGA_MAC_VER_06, | |
116 | RTL_GIGA_MAC_VER_07, | |
117 | RTL_GIGA_MAC_VER_08, | |
118 | RTL_GIGA_MAC_VER_09, | |
119 | RTL_GIGA_MAC_VER_10, | |
120 | RTL_GIGA_MAC_VER_11, | |
121 | RTL_GIGA_MAC_VER_12, | |
122 | RTL_GIGA_MAC_VER_13, | |
123 | RTL_GIGA_MAC_VER_14, | |
124 | RTL_GIGA_MAC_VER_15, | |
125 | RTL_GIGA_MAC_VER_16, | |
126 | RTL_GIGA_MAC_VER_17, | |
127 | RTL_GIGA_MAC_VER_18, | |
128 | RTL_GIGA_MAC_VER_19, | |
129 | RTL_GIGA_MAC_VER_20, | |
130 | RTL_GIGA_MAC_VER_21, | |
131 | RTL_GIGA_MAC_VER_22, | |
132 | RTL_GIGA_MAC_VER_23, | |
133 | RTL_GIGA_MAC_VER_24, | |
134 | RTL_GIGA_MAC_VER_25, | |
135 | RTL_GIGA_MAC_VER_26, | |
136 | RTL_GIGA_MAC_VER_27, | |
137 | RTL_GIGA_MAC_VER_28, | |
138 | RTL_GIGA_MAC_VER_29, | |
139 | RTL_GIGA_MAC_VER_30, | |
140 | RTL_GIGA_MAC_VER_31, | |
141 | RTL_GIGA_MAC_VER_32, | |
142 | RTL_GIGA_MAC_VER_33, | |
70090424 | 143 | RTL_GIGA_MAC_VER_34, |
c2218925 HW |
144 | RTL_GIGA_MAC_VER_35, |
145 | RTL_GIGA_MAC_VER_36, | |
7e18dca1 | 146 | RTL_GIGA_MAC_VER_37, |
b3d7b2f2 | 147 | RTL_GIGA_MAC_VER_38, |
5598bfe5 | 148 | RTL_GIGA_MAC_VER_39, |
c558386b HW |
149 | RTL_GIGA_MAC_VER_40, |
150 | RTL_GIGA_MAC_VER_41, | |
57538c4a | 151 | RTL_GIGA_MAC_VER_42, |
58152cd4 | 152 | RTL_GIGA_MAC_VER_43, |
45dd95c4 | 153 | RTL_GIGA_MAC_VER_44, |
6e1d0b89 CHL |
154 | RTL_GIGA_MAC_VER_45, |
155 | RTL_GIGA_MAC_VER_46, | |
156 | RTL_GIGA_MAC_VER_47, | |
157 | RTL_GIGA_MAC_VER_48, | |
935e2218 CHL |
158 | RTL_GIGA_MAC_VER_49, |
159 | RTL_GIGA_MAC_VER_50, | |
160 | RTL_GIGA_MAC_VER_51, | |
85bffe6c | 161 | RTL_GIGA_MAC_NONE = 0xff, |
1da177e4 LT |
162 | }; |
163 | ||
2b7b4318 FR |
164 | enum rtl_tx_desc_version { |
165 | RTL_TD_0 = 0, | |
166 | RTL_TD_1 = 1, | |
167 | }; | |
168 | ||
d58d46b5 FR |
169 | #define JUMBO_1K ETH_DATA_LEN |
170 | #define JUMBO_4K (4*1024 - ETH_HLEN - 2) | |
171 | #define JUMBO_6K (6*1024 - ETH_HLEN - 2) | |
172 | #define JUMBO_7K (7*1024 - ETH_HLEN - 2) | |
173 | #define JUMBO_9K (9*1024 - ETH_HLEN - 2) | |
174 | ||
175 | #define _R(NAME,TD,FW,SZ,B) { \ | |
176 | .name = NAME, \ | |
177 | .txd_version = TD, \ | |
178 | .fw_name = FW, \ | |
179 | .jumbo_max = SZ, \ | |
180 | .jumbo_tx_csum = B \ | |
181 | } | |
1da177e4 | 182 | |
3c6bee1d | 183 | static const struct { |
1da177e4 | 184 | const char *name; |
2b7b4318 | 185 | enum rtl_tx_desc_version txd_version; |
953a12cc | 186 | const char *fw_name; |
d58d46b5 FR |
187 | u16 jumbo_max; |
188 | bool jumbo_tx_csum; | |
85bffe6c FR |
189 | } rtl_chip_infos[] = { |
190 | /* PCI devices. */ | |
191 | [RTL_GIGA_MAC_VER_01] = | |
d58d46b5 | 192 | _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 193 | [RTL_GIGA_MAC_VER_02] = |
d58d46b5 | 194 | _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 195 | [RTL_GIGA_MAC_VER_03] = |
d58d46b5 | 196 | _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 197 | [RTL_GIGA_MAC_VER_04] = |
d58d46b5 | 198 | _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 199 | [RTL_GIGA_MAC_VER_05] = |
d58d46b5 | 200 | _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 201 | [RTL_GIGA_MAC_VER_06] = |
d58d46b5 | 202 | _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c FR |
203 | /* PCI-E devices. */ |
204 | [RTL_GIGA_MAC_VER_07] = | |
d58d46b5 | 205 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
85bffe6c | 206 | [RTL_GIGA_MAC_VER_08] = |
d58d46b5 | 207 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
85bffe6c | 208 | [RTL_GIGA_MAC_VER_09] = |
d58d46b5 | 209 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
85bffe6c | 210 | [RTL_GIGA_MAC_VER_10] = |
d58d46b5 | 211 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 212 | [RTL_GIGA_MAC_VER_11] = |
d58d46b5 | 213 | _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
85bffe6c | 214 | [RTL_GIGA_MAC_VER_12] = |
d58d46b5 | 215 | _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
85bffe6c | 216 | [RTL_GIGA_MAC_VER_13] = |
d58d46b5 | 217 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 218 | [RTL_GIGA_MAC_VER_14] = |
d58d46b5 | 219 | _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 220 | [RTL_GIGA_MAC_VER_15] = |
d58d46b5 | 221 | _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 222 | [RTL_GIGA_MAC_VER_16] = |
d58d46b5 | 223 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 224 | [RTL_GIGA_MAC_VER_17] = |
f75761b6 | 225 | _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
85bffe6c | 226 | [RTL_GIGA_MAC_VER_18] = |
d58d46b5 | 227 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 228 | [RTL_GIGA_MAC_VER_19] = |
d58d46b5 | 229 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 230 | [RTL_GIGA_MAC_VER_20] = |
d58d46b5 | 231 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 232 | [RTL_GIGA_MAC_VER_21] = |
d58d46b5 | 233 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 234 | [RTL_GIGA_MAC_VER_22] = |
d58d46b5 | 235 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 236 | [RTL_GIGA_MAC_VER_23] = |
d58d46b5 | 237 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 238 | [RTL_GIGA_MAC_VER_24] = |
d58d46b5 | 239 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 240 | [RTL_GIGA_MAC_VER_25] = |
d58d46b5 FR |
241 | _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, |
242 | JUMBO_9K, false), | |
85bffe6c | 243 | [RTL_GIGA_MAC_VER_26] = |
d58d46b5 FR |
244 | _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, |
245 | JUMBO_9K, false), | |
85bffe6c | 246 | [RTL_GIGA_MAC_VER_27] = |
d58d46b5 | 247 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
85bffe6c | 248 | [RTL_GIGA_MAC_VER_28] = |
d58d46b5 | 249 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
85bffe6c | 250 | [RTL_GIGA_MAC_VER_29] = |
d58d46b5 FR |
251 | _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
252 | JUMBO_1K, true), | |
85bffe6c | 253 | [RTL_GIGA_MAC_VER_30] = |
d58d46b5 FR |
254 | _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
255 | JUMBO_1K, true), | |
85bffe6c | 256 | [RTL_GIGA_MAC_VER_31] = |
d58d46b5 | 257 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
85bffe6c | 258 | [RTL_GIGA_MAC_VER_32] = |
d58d46b5 FR |
259 | _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, |
260 | JUMBO_9K, false), | |
85bffe6c | 261 | [RTL_GIGA_MAC_VER_33] = |
d58d46b5 FR |
262 | _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, |
263 | JUMBO_9K, false), | |
70090424 | 264 | [RTL_GIGA_MAC_VER_34] = |
d58d46b5 FR |
265 | _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, |
266 | JUMBO_9K, false), | |
c2218925 | 267 | [RTL_GIGA_MAC_VER_35] = |
d58d46b5 FR |
268 | _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, |
269 | JUMBO_9K, false), | |
c2218925 | 270 | [RTL_GIGA_MAC_VER_36] = |
d58d46b5 FR |
271 | _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, |
272 | JUMBO_9K, false), | |
7e18dca1 HW |
273 | [RTL_GIGA_MAC_VER_37] = |
274 | _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1, | |
275 | JUMBO_1K, true), | |
b3d7b2f2 HW |
276 | [RTL_GIGA_MAC_VER_38] = |
277 | _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1, | |
278 | JUMBO_9K, false), | |
5598bfe5 HW |
279 | [RTL_GIGA_MAC_VER_39] = |
280 | _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1, | |
281 | JUMBO_1K, true), | |
c558386b | 282 | [RTL_GIGA_MAC_VER_40] = |
beb330a4 | 283 | _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2, |
c558386b HW |
284 | JUMBO_9K, false), |
285 | [RTL_GIGA_MAC_VER_41] = | |
286 | _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false), | |
57538c4a | 287 | [RTL_GIGA_MAC_VER_42] = |
288 | _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3, | |
289 | JUMBO_9K, false), | |
58152cd4 | 290 | [RTL_GIGA_MAC_VER_43] = |
291 | _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2, | |
292 | JUMBO_1K, true), | |
45dd95c4 | 293 | [RTL_GIGA_MAC_VER_44] = |
294 | _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2, | |
295 | JUMBO_9K, false), | |
6e1d0b89 CHL |
296 | [RTL_GIGA_MAC_VER_45] = |
297 | _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1, | |
298 | JUMBO_9K, false), | |
299 | [RTL_GIGA_MAC_VER_46] = | |
300 | _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2, | |
301 | JUMBO_9K, false), | |
302 | [RTL_GIGA_MAC_VER_47] = | |
303 | _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1, | |
304 | JUMBO_1K, false), | |
305 | [RTL_GIGA_MAC_VER_48] = | |
306 | _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2, | |
307 | JUMBO_1K, false), | |
935e2218 CHL |
308 | [RTL_GIGA_MAC_VER_49] = |
309 | _R("RTL8168ep/8111ep", RTL_TD_1, NULL, | |
310 | JUMBO_9K, false), | |
311 | [RTL_GIGA_MAC_VER_50] = | |
312 | _R("RTL8168ep/8111ep", RTL_TD_1, NULL, | |
313 | JUMBO_9K, false), | |
314 | [RTL_GIGA_MAC_VER_51] = | |
315 | _R("RTL8168ep/8111ep", RTL_TD_1, NULL, | |
316 | JUMBO_9K, false), | |
953a12cc | 317 | }; |
85bffe6c | 318 | #undef _R |
953a12cc | 319 | |
bcf0bf90 FR |
320 | enum cfg_version { |
321 | RTL_CFG_0 = 0x00, | |
322 | RTL_CFG_1, | |
323 | RTL_CFG_2 | |
324 | }; | |
325 | ||
9baa3c34 | 326 | static const struct pci_device_id rtl8169_pci_tbl[] = { |
bcf0bf90 | 327 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
d2eed8cf | 328 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
610c9087 | 329 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 }, |
d81bf551 | 330 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
07ce4064 | 331 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
bcf0bf90 | 332 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
2a35cfa5 FR |
333 | { PCI_VENDOR_ID_DLINK, 0x4300, |
334 | PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 }, | |
bcf0bf90 | 335 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, |
93a3aa25 | 336 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 }, |
bc1660b5 | 337 | { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
bcf0bf90 FR |
338 | { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
339 | { PCI_VENDOR_ID_LINKSYS, 0x1032, | |
340 | PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, | |
11d2e282 CM |
341 | { 0x0001, 0x8168, |
342 | PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, | |
1da177e4 LT |
343 | {0,}, |
344 | }; | |
345 | ||
346 | MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); | |
347 | ||
6f0333b8 | 348 | static int rx_buf_sz = 16383; |
27896c83 | 349 | static int use_dac = -1; |
b57b7e5a SH |
350 | static struct { |
351 | u32 msg_enable; | |
352 | } debug = { -1 }; | |
1da177e4 | 353 | |
07d3f51f FR |
354 | enum rtl_registers { |
355 | MAC0 = 0, /* Ethernet hardware address. */ | |
773d2021 | 356 | MAC4 = 4, |
07d3f51f FR |
357 | MAR0 = 8, /* Multicast filter. */ |
358 | CounterAddrLow = 0x10, | |
359 | CounterAddrHigh = 0x14, | |
360 | TxDescStartAddrLow = 0x20, | |
361 | TxDescStartAddrHigh = 0x24, | |
362 | TxHDescStartAddrLow = 0x28, | |
363 | TxHDescStartAddrHigh = 0x2c, | |
364 | FLASH = 0x30, | |
365 | ERSR = 0x36, | |
366 | ChipCmd = 0x37, | |
367 | TxPoll = 0x38, | |
368 | IntrMask = 0x3c, | |
369 | IntrStatus = 0x3e, | |
4f6b00e5 | 370 | |
07d3f51f | 371 | TxConfig = 0x40, |
4f6b00e5 HW |
372 | #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ |
373 | #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ | |
2b7b4318 | 374 | |
4f6b00e5 HW |
375 | RxConfig = 0x44, |
376 | #define RX128_INT_EN (1 << 15) /* 8111c and later */ | |
377 | #define RX_MULTI_EN (1 << 14) /* 8111c only */ | |
378 | #define RXCFG_FIFO_SHIFT 13 | |
379 | /* No threshold before first PCI xfer */ | |
380 | #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) | |
beb330a4 | 381 | #define RX_EARLY_OFF (1 << 11) |
4f6b00e5 HW |
382 | #define RXCFG_DMA_SHIFT 8 |
383 | /* Unlimited maximum PCI burst. */ | |
384 | #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) | |
2b7b4318 | 385 | |
07d3f51f FR |
386 | RxMissed = 0x4c, |
387 | Cfg9346 = 0x50, | |
388 | Config0 = 0x51, | |
389 | Config1 = 0x52, | |
390 | Config2 = 0x53, | |
d387b427 FR |
391 | #define PME_SIGNAL (1 << 5) /* 8168c and later */ |
392 | ||
07d3f51f FR |
393 | Config3 = 0x54, |
394 | Config4 = 0x55, | |
395 | Config5 = 0x56, | |
396 | MultiIntr = 0x5c, | |
397 | PHYAR = 0x60, | |
07d3f51f FR |
398 | PHYstatus = 0x6c, |
399 | RxMaxSize = 0xda, | |
400 | CPlusCmd = 0xe0, | |
401 | IntrMitigate = 0xe2, | |
50970831 FR |
402 | |
403 | #define RTL_COALESCE_MASK 0x0f | |
404 | #define RTL_COALESCE_SHIFT 4 | |
405 | #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK) | |
406 | #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2) | |
407 | ||
07d3f51f FR |
408 | RxDescAddrLow = 0xe4, |
409 | RxDescAddrHigh = 0xe8, | |
f0298f81 | 410 | EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ |
411 | ||
412 | #define NoEarlyTx 0x3f /* Max value : no early transmit. */ | |
413 | ||
414 | MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ | |
415 | ||
416 | #define TxPacketMax (8064 >> 7) | |
3090bd9a | 417 | #define EarlySize 0x27 |
f0298f81 | 418 | |
07d3f51f FR |
419 | FuncEvent = 0xf0, |
420 | FuncEventMask = 0xf4, | |
421 | FuncPresetState = 0xf8, | |
935e2218 CHL |
422 | IBCR0 = 0xf8, |
423 | IBCR2 = 0xf9, | |
424 | IBIMR0 = 0xfa, | |
425 | IBISR0 = 0xfb, | |
07d3f51f | 426 | FuncForceEvent = 0xfc, |
1da177e4 LT |
427 | }; |
428 | ||
f162a5d1 FR |
429 | enum rtl8110_registers { |
430 | TBICSR = 0x64, | |
431 | TBI_ANAR = 0x68, | |
432 | TBI_LPAR = 0x6a, | |
433 | }; | |
434 | ||
435 | enum rtl8168_8101_registers { | |
436 | CSIDR = 0x64, | |
437 | CSIAR = 0x68, | |
438 | #define CSIAR_FLAG 0x80000000 | |
439 | #define CSIAR_WRITE_CMD 0x80000000 | |
440 | #define CSIAR_BYTE_ENABLE 0x0f | |
441 | #define CSIAR_BYTE_ENABLE_SHIFT 12 | |
442 | #define CSIAR_ADDR_MASK 0x0fff | |
7e18dca1 HW |
443 | #define CSIAR_FUNC_CARD 0x00000000 |
444 | #define CSIAR_FUNC_SDIO 0x00010000 | |
445 | #define CSIAR_FUNC_NIC 0x00020000 | |
45dd95c4 | 446 | #define CSIAR_FUNC_NIC2 0x00010000 |
065c27c1 | 447 | PMCH = 0x6f, |
f162a5d1 FR |
448 | EPHYAR = 0x80, |
449 | #define EPHYAR_FLAG 0x80000000 | |
450 | #define EPHYAR_WRITE_CMD 0x80000000 | |
451 | #define EPHYAR_REG_MASK 0x1f | |
452 | #define EPHYAR_REG_SHIFT 16 | |
453 | #define EPHYAR_DATA_MASK 0xffff | |
5a5e4443 | 454 | DLLPR = 0xd0, |
4f6b00e5 | 455 | #define PFM_EN (1 << 6) |
6e1d0b89 | 456 | #define TX_10M_PS_EN (1 << 7) |
f162a5d1 FR |
457 | DBG_REG = 0xd1, |
458 | #define FIX_NAK_1 (1 << 4) | |
459 | #define FIX_NAK_2 (1 << 3) | |
5a5e4443 HW |
460 | TWSI = 0xd2, |
461 | MCU = 0xd3, | |
4f6b00e5 | 462 | #define NOW_IS_OOB (1 << 7) |
c558386b HW |
463 | #define TX_EMPTY (1 << 5) |
464 | #define RX_EMPTY (1 << 4) | |
465 | #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) | |
5a5e4443 HW |
466 | #define EN_NDP (1 << 3) |
467 | #define EN_OOB_RESET (1 << 2) | |
c558386b | 468 | #define LINK_LIST_RDY (1 << 1) |
daf9df6d | 469 | EFUSEAR = 0xdc, |
470 | #define EFUSEAR_FLAG 0x80000000 | |
471 | #define EFUSEAR_WRITE_CMD 0x80000000 | |
472 | #define EFUSEAR_READ_CMD 0x00000000 | |
473 | #define EFUSEAR_REG_MASK 0x03ff | |
474 | #define EFUSEAR_REG_SHIFT 8 | |
475 | #define EFUSEAR_DATA_MASK 0xff | |
6e1d0b89 CHL |
476 | MISC_1 = 0xf2, |
477 | #define PFM_D3COLD_EN (1 << 6) | |
f162a5d1 FR |
478 | }; |
479 | ||
c0e45c1c | 480 | enum rtl8168_registers { |
4f6b00e5 HW |
481 | LED_FREQ = 0x1a, |
482 | EEE_LED = 0x1b, | |
b646d900 | 483 | ERIDR = 0x70, |
484 | ERIAR = 0x74, | |
485 | #define ERIAR_FLAG 0x80000000 | |
486 | #define ERIAR_WRITE_CMD 0x80000000 | |
487 | #define ERIAR_READ_CMD 0x00000000 | |
488 | #define ERIAR_ADDR_BYTE_ALIGN 4 | |
b646d900 | 489 | #define ERIAR_TYPE_SHIFT 16 |
4f6b00e5 HW |
490 | #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) |
491 | #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) | |
492 | #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) | |
935e2218 | 493 | #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) |
4f6b00e5 HW |
494 | #define ERIAR_MASK_SHIFT 12 |
495 | #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) | |
496 | #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) | |
6e1d0b89 | 497 | #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) |
c558386b | 498 | #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) |
4f6b00e5 | 499 | #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) |
c0e45c1c | 500 | EPHY_RXER_NUM = 0x7c, |
501 | OCPDR = 0xb0, /* OCP GPHY access */ | |
502 | #define OCPDR_WRITE_CMD 0x80000000 | |
503 | #define OCPDR_READ_CMD 0x00000000 | |
504 | #define OCPDR_REG_MASK 0x7f | |
505 | #define OCPDR_GPHY_REG_SHIFT 16 | |
506 | #define OCPDR_DATA_MASK 0xffff | |
507 | OCPAR = 0xb4, | |
508 | #define OCPAR_FLAG 0x80000000 | |
509 | #define OCPAR_GPHY_WRITE_CMD 0x8000f060 | |
510 | #define OCPAR_GPHY_READ_CMD 0x0000f060 | |
c558386b | 511 | GPHY_OCP = 0xb8, |
01dc7fec | 512 | RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ |
513 | MISC = 0xf0, /* 8168e only. */ | |
cecb5fd7 | 514 | #define TXPLA_RST (1 << 29) |
5598bfe5 | 515 | #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ |
4f6b00e5 | 516 | #define PWM_EN (1 << 22) |
c558386b | 517 | #define RXDV_GATED_EN (1 << 19) |
5598bfe5 | 518 | #define EARLY_TALLY_EN (1 << 16) |
c0e45c1c | 519 | }; |
520 | ||
07d3f51f | 521 | enum rtl_register_content { |
1da177e4 | 522 | /* InterruptStatusBits */ |
07d3f51f FR |
523 | SYSErr = 0x8000, |
524 | PCSTimeout = 0x4000, | |
525 | SWInt = 0x0100, | |
526 | TxDescUnavail = 0x0080, | |
527 | RxFIFOOver = 0x0040, | |
528 | LinkChg = 0x0020, | |
529 | RxOverflow = 0x0010, | |
530 | TxErr = 0x0008, | |
531 | TxOK = 0x0004, | |
532 | RxErr = 0x0002, | |
533 | RxOK = 0x0001, | |
1da177e4 LT |
534 | |
535 | /* RxStatusDesc */ | |
e03f33af | 536 | RxBOVF = (1 << 24), |
9dccf611 FR |
537 | RxFOVF = (1 << 23), |
538 | RxRWT = (1 << 22), | |
539 | RxRES = (1 << 21), | |
540 | RxRUNT = (1 << 20), | |
541 | RxCRC = (1 << 19), | |
1da177e4 LT |
542 | |
543 | /* ChipCmdBits */ | |
4f6b00e5 | 544 | StopReq = 0x80, |
07d3f51f FR |
545 | CmdReset = 0x10, |
546 | CmdRxEnb = 0x08, | |
547 | CmdTxEnb = 0x04, | |
548 | RxBufEmpty = 0x01, | |
1da177e4 | 549 | |
275391a4 FR |
550 | /* TXPoll register p.5 */ |
551 | HPQ = 0x80, /* Poll cmd on the high prio queue */ | |
552 | NPQ = 0x40, /* Poll cmd on the low prio queue */ | |
553 | FSWInt = 0x01, /* Forced software interrupt */ | |
554 | ||
1da177e4 | 555 | /* Cfg9346Bits */ |
07d3f51f FR |
556 | Cfg9346_Lock = 0x00, |
557 | Cfg9346_Unlock = 0xc0, | |
1da177e4 LT |
558 | |
559 | /* rx_mode_bits */ | |
07d3f51f FR |
560 | AcceptErr = 0x20, |
561 | AcceptRunt = 0x10, | |
562 | AcceptBroadcast = 0x08, | |
563 | AcceptMulticast = 0x04, | |
564 | AcceptMyPhys = 0x02, | |
565 | AcceptAllPhys = 0x01, | |
1687b566 | 566 | #define RX_CONFIG_ACCEPT_MASK 0x3f |
1da177e4 | 567 | |
1da177e4 LT |
568 | /* TxConfigBits */ |
569 | TxInterFrameGapShift = 24, | |
570 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
571 | ||
5d06a99f | 572 | /* Config1 register p.24 */ |
f162a5d1 FR |
573 | LEDS1 = (1 << 7), |
574 | LEDS0 = (1 << 6), | |
f162a5d1 FR |
575 | Speed_down = (1 << 4), |
576 | MEMMAP = (1 << 3), | |
577 | IOMAP = (1 << 2), | |
578 | VPD = (1 << 1), | |
5d06a99f FR |
579 | PMEnable = (1 << 0), /* Power Management Enable */ |
580 | ||
6dccd16b | 581 | /* Config2 register p. 25 */ |
57538c4a | 582 | ClkReqEn = (1 << 7), /* Clock Request Enable */ |
2ca6cf06 | 583 | MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ |
6dccd16b FR |
584 | PCI_Clock_66MHz = 0x01, |
585 | PCI_Clock_33MHz = 0x00, | |
586 | ||
61a4dcc2 FR |
587 | /* Config3 register p.25 */ |
588 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
589 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
d58d46b5 | 590 | Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ |
b51ecea8 | 591 | Rdy_to_L23 = (1 << 1), /* L23 Enable */ |
f162a5d1 | 592 | Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
61a4dcc2 | 593 | |
d58d46b5 FR |
594 | /* Config4 register */ |
595 | Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ | |
596 | ||
5d06a99f | 597 | /* Config5 register p.27 */ |
61a4dcc2 FR |
598 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
599 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ | |
600 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ | |
cecb5fd7 | 601 | Spi_en = (1 << 3), |
61a4dcc2 | 602 | LanWake = (1 << 1), /* LanWake enable/disable */ |
5d06a99f | 603 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
57538c4a | 604 | ASPM_en = (1 << 0), /* ASPM enable */ |
5d06a99f | 605 | |
1da177e4 LT |
606 | /* TBICSR p.28 */ |
607 | TBIReset = 0x80000000, | |
608 | TBILoopback = 0x40000000, | |
609 | TBINwEnable = 0x20000000, | |
610 | TBINwRestart = 0x10000000, | |
611 | TBILinkOk = 0x02000000, | |
612 | TBINwComplete = 0x01000000, | |
613 | ||
614 | /* CPlusCmd p.31 */ | |
f162a5d1 FR |
615 | EnableBist = (1 << 15), // 8168 8101 |
616 | Mac_dbgo_oe = (1 << 14), // 8168 8101 | |
617 | Normal_mode = (1 << 13), // unused | |
618 | Force_half_dup = (1 << 12), // 8168 8101 | |
619 | Force_rxflow_en = (1 << 11), // 8168 8101 | |
620 | Force_txflow_en = (1 << 10), // 8168 8101 | |
621 | Cxpl_dbg_sel = (1 << 9), // 8168 8101 | |
622 | ASF = (1 << 8), // 8168 8101 | |
623 | PktCntrDisable = (1 << 7), // 8168 8101 | |
624 | Mac_dbgo_sel = 0x001c, // 8168 | |
1da177e4 LT |
625 | RxVlan = (1 << 6), |
626 | RxChkSum = (1 << 5), | |
627 | PCIDAC = (1 << 4), | |
628 | PCIMulRW = (1 << 3), | |
0e485150 FR |
629 | INTT_0 = 0x0000, // 8168 |
630 | INTT_1 = 0x0001, // 8168 | |
631 | INTT_2 = 0x0002, // 8168 | |
632 | INTT_3 = 0x0003, // 8168 | |
1da177e4 LT |
633 | |
634 | /* rtl8169_PHYstatus */ | |
07d3f51f FR |
635 | TBI_Enable = 0x80, |
636 | TxFlowCtrl = 0x40, | |
637 | RxFlowCtrl = 0x20, | |
638 | _1000bpsF = 0x10, | |
639 | _100bps = 0x08, | |
640 | _10bps = 0x04, | |
641 | LinkStatus = 0x02, | |
642 | FullDup = 0x01, | |
1da177e4 | 643 | |
1da177e4 | 644 | /* _TBICSRBit */ |
07d3f51f | 645 | TBILinkOK = 0x02000000, |
d4a3a0fc | 646 | |
6e85d5ad CV |
647 | /* ResetCounterCommand */ |
648 | CounterReset = 0x1, | |
649 | ||
d4a3a0fc | 650 | /* DumpCounterCommand */ |
07d3f51f | 651 | CounterDump = 0x8, |
6e1d0b89 CHL |
652 | |
653 | /* magic enable v2 */ | |
654 | MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ | |
1da177e4 LT |
655 | }; |
656 | ||
2b7b4318 FR |
657 | enum rtl_desc_bit { |
658 | /* First doubleword. */ | |
1da177e4 LT |
659 | DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
660 | RingEnd = (1 << 30), /* End of descriptor ring */ | |
661 | FirstFrag = (1 << 29), /* First segment of a packet */ | |
662 | LastFrag = (1 << 28), /* Final segment of a packet */ | |
2b7b4318 FR |
663 | }; |
664 | ||
665 | /* Generic case. */ | |
666 | enum rtl_tx_desc_bit { | |
667 | /* First doubleword. */ | |
668 | TD_LSO = (1 << 27), /* Large Send Offload */ | |
669 | #define TD_MSS_MAX 0x07ffu /* MSS value */ | |
1da177e4 | 670 | |
2b7b4318 FR |
671 | /* Second doubleword. */ |
672 | TxVlanTag = (1 << 17), /* Add VLAN tag */ | |
673 | }; | |
674 | ||
675 | /* 8169, 8168b and 810x except 8102e. */ | |
676 | enum rtl_tx_desc_bit_0 { | |
677 | /* First doubleword. */ | |
678 | #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ | |
679 | TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ | |
680 | TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ | |
681 | TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ | |
682 | }; | |
683 | ||
684 | /* 8102e, 8168c and beyond. */ | |
685 | enum rtl_tx_desc_bit_1 { | |
bdfa4ed6 | 686 | /* First doubleword. */ |
687 | TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ | |
e974604b | 688 | TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ |
bdfa4ed6 | 689 | #define GTTCPHO_SHIFT 18 |
e974604b | 690 | #define GTTCPHO_MAX 0x7fU |
bdfa4ed6 | 691 | |
2b7b4318 | 692 | /* Second doubleword. */ |
e974604b | 693 | #define TCPHO_SHIFT 18 |
694 | #define TCPHO_MAX 0x3ffU | |
2b7b4318 | 695 | #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ |
e974604b | 696 | TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ |
697 | TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ | |
2b7b4318 FR |
698 | TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ |
699 | TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ | |
700 | }; | |
1da177e4 | 701 | |
2b7b4318 | 702 | enum rtl_rx_desc_bit { |
1da177e4 LT |
703 | /* Rx private */ |
704 | PID1 = (1 << 18), /* Protocol ID bit 1/2 */ | |
9b60047a | 705 | PID0 = (1 << 17), /* Protocol ID bit 0/2 */ |
1da177e4 LT |
706 | |
707 | #define RxProtoUDP (PID1) | |
708 | #define RxProtoTCP (PID0) | |
709 | #define RxProtoIP (PID1 | PID0) | |
710 | #define RxProtoMask RxProtoIP | |
711 | ||
712 | IPFail = (1 << 16), /* IP checksum failed */ | |
713 | UDPFail = (1 << 15), /* UDP/IP checksum failed */ | |
714 | TCPFail = (1 << 14), /* TCP/IP checksum failed */ | |
715 | RxVlanTag = (1 << 16), /* VLAN tag available */ | |
716 | }; | |
717 | ||
718 | #define RsvdMask 0x3fffc000 | |
719 | ||
720 | struct TxDesc { | |
6cccd6e7 REB |
721 | __le32 opts1; |
722 | __le32 opts2; | |
723 | __le64 addr; | |
1da177e4 LT |
724 | }; |
725 | ||
726 | struct RxDesc { | |
6cccd6e7 REB |
727 | __le32 opts1; |
728 | __le32 opts2; | |
729 | __le64 addr; | |
1da177e4 LT |
730 | }; |
731 | ||
732 | struct ring_info { | |
733 | struct sk_buff *skb; | |
734 | u32 len; | |
735 | u8 __pad[sizeof(void *) - sizeof(u32)]; | |
736 | }; | |
737 | ||
f23e7fda | 738 | enum features { |
ccdffb9a FR |
739 | RTL_FEATURE_WOL = (1 << 0), |
740 | RTL_FEATURE_MSI = (1 << 1), | |
741 | RTL_FEATURE_GMII = (1 << 2), | |
f23e7fda FR |
742 | }; |
743 | ||
355423d0 IV |
744 | struct rtl8169_counters { |
745 | __le64 tx_packets; | |
746 | __le64 rx_packets; | |
747 | __le64 tx_errors; | |
748 | __le32 rx_errors; | |
749 | __le16 rx_missed; | |
750 | __le16 align_errors; | |
751 | __le32 tx_one_collision; | |
752 | __le32 tx_multi_collision; | |
753 | __le64 rx_unicast; | |
754 | __le64 rx_broadcast; | |
755 | __le32 rx_multicast; | |
756 | __le16 tx_aborted; | |
757 | __le16 tx_underun; | |
758 | }; | |
759 | ||
6e85d5ad CV |
760 | struct rtl8169_tc_offsets { |
761 | bool inited; | |
762 | __le64 tx_errors; | |
763 | __le32 tx_multi_collision; | |
6e85d5ad CV |
764 | __le16 tx_aborted; |
765 | }; | |
766 | ||
da78dbff | 767 | enum rtl_flag { |
6c4a70c5 | 768 | RTL_FLAG_TASK_ENABLED, |
da78dbff FR |
769 | RTL_FLAG_TASK_SLOW_PENDING, |
770 | RTL_FLAG_TASK_RESET_PENDING, | |
771 | RTL_FLAG_TASK_PHY_PENDING, | |
772 | RTL_FLAG_MAX | |
773 | }; | |
774 | ||
8027aa24 JW |
775 | struct rtl8169_stats { |
776 | u64 packets; | |
777 | u64 bytes; | |
778 | struct u64_stats_sync syncp; | |
779 | }; | |
780 | ||
1da177e4 LT |
781 | struct rtl8169_private { |
782 | void __iomem *mmio_addr; /* memory map physical address */ | |
cecb5fd7 | 783 | struct pci_dev *pci_dev; |
c4028958 | 784 | struct net_device *dev; |
bea3348e | 785 | struct napi_struct napi; |
b57b7e5a | 786 | u32 msg_enable; |
2b7b4318 FR |
787 | u16 txd_version; |
788 | u16 mac_version; | |
1da177e4 LT |
789 | u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
790 | u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ | |
1da177e4 | 791 | u32 dirty_tx; |
8027aa24 JW |
792 | struct rtl8169_stats rx_stats; |
793 | struct rtl8169_stats tx_stats; | |
1da177e4 LT |
794 | struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ |
795 | struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ | |
796 | dma_addr_t TxPhyAddr; | |
797 | dma_addr_t RxPhyAddr; | |
6f0333b8 | 798 | void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ |
1da177e4 | 799 | struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
1da177e4 LT |
800 | struct timer_list timer; |
801 | u16 cp_cmd; | |
da78dbff FR |
802 | |
803 | u16 event_slow; | |
50970831 | 804 | const struct rtl_coalesce_info *coalesce_info; |
c0e45c1c | 805 | |
806 | struct mdio_ops { | |
24192210 FR |
807 | void (*write)(struct rtl8169_private *, int, int); |
808 | int (*read)(struct rtl8169_private *, int); | |
c0e45c1c | 809 | } mdio_ops; |
810 | ||
065c27c1 | 811 | struct pll_power_ops { |
812 | void (*down)(struct rtl8169_private *); | |
813 | void (*up)(struct rtl8169_private *); | |
814 | } pll_power_ops; | |
815 | ||
d58d46b5 FR |
816 | struct jumbo_ops { |
817 | void (*enable)(struct rtl8169_private *); | |
818 | void (*disable)(struct rtl8169_private *); | |
819 | } jumbo_ops; | |
820 | ||
beb1fe18 | 821 | struct csi_ops { |
52989f0e FR |
822 | void (*write)(struct rtl8169_private *, int, int); |
823 | u32 (*read)(struct rtl8169_private *, int); | |
beb1fe18 HW |
824 | } csi_ops; |
825 | ||
54405cde | 826 | int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv); |
6fa1ba61 PR |
827 | int (*get_link_ksettings)(struct net_device *, |
828 | struct ethtool_link_ksettings *); | |
4da19633 | 829 | void (*phy_reset_enable)(struct rtl8169_private *tp); |
07ce4064 | 830 | void (*hw_start)(struct net_device *); |
4da19633 | 831 | unsigned int (*phy_reset_pending)(struct rtl8169_private *tp); |
1da177e4 | 832 | unsigned int (*link_ok)(void __iomem *); |
8b4ab28d | 833 | int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); |
5888d3fc | 834 | bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *); |
4422bcd4 FR |
835 | |
836 | struct { | |
da78dbff FR |
837 | DECLARE_BITMAP(flags, RTL_FLAG_MAX); |
838 | struct mutex mutex; | |
4422bcd4 FR |
839 | struct work_struct work; |
840 | } wk; | |
841 | ||
f23e7fda | 842 | unsigned features; |
ccdffb9a FR |
843 | |
844 | struct mii_if_info mii; | |
42020320 CV |
845 | dma_addr_t counters_phys_addr; |
846 | struct rtl8169_counters *counters; | |
6e85d5ad | 847 | struct rtl8169_tc_offsets tc_offset; |
e1759441 | 848 | u32 saved_wolopts; |
e03f33af | 849 | u32 opts1_mask; |
f1e02ed1 | 850 | |
b6ffd97f FR |
851 | struct rtl_fw { |
852 | const struct firmware *fw; | |
1c361efb FR |
853 | |
854 | #define RTL_VER_SIZE 32 | |
855 | ||
856 | char version[RTL_VER_SIZE]; | |
857 | ||
858 | struct rtl_fw_phy_action { | |
859 | __le32 *code; | |
860 | size_t size; | |
861 | } phy_action; | |
b6ffd97f | 862 | } *rtl_fw; |
497888cf | 863 | #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN) |
c558386b HW |
864 | |
865 | u32 ocp_base; | |
1da177e4 LT |
866 | }; |
867 | ||
979b6c13 | 868 | MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
1da177e4 | 869 | MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
1da177e4 | 870 | module_param(use_dac, int, 0); |
4300e8c7 | 871 | MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
b57b7e5a SH |
872 | module_param_named(debug, debug.msg_enable, int, 0); |
873 | MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); | |
1da177e4 LT |
874 | MODULE_LICENSE("GPL"); |
875 | MODULE_VERSION(RTL8169_VERSION); | |
bca03d5f | 876 | MODULE_FIRMWARE(FIRMWARE_8168D_1); |
877 | MODULE_FIRMWARE(FIRMWARE_8168D_2); | |
01dc7fec | 878 | MODULE_FIRMWARE(FIRMWARE_8168E_1); |
879 | MODULE_FIRMWARE(FIRMWARE_8168E_2); | |
bbb8af75 | 880 | MODULE_FIRMWARE(FIRMWARE_8168E_3); |
5a5e4443 | 881 | MODULE_FIRMWARE(FIRMWARE_8105E_1); |
c2218925 HW |
882 | MODULE_FIRMWARE(FIRMWARE_8168F_1); |
883 | MODULE_FIRMWARE(FIRMWARE_8168F_2); | |
7e18dca1 | 884 | MODULE_FIRMWARE(FIRMWARE_8402_1); |
b3d7b2f2 | 885 | MODULE_FIRMWARE(FIRMWARE_8411_1); |
45dd95c4 | 886 | MODULE_FIRMWARE(FIRMWARE_8411_2); |
5598bfe5 | 887 | MODULE_FIRMWARE(FIRMWARE_8106E_1); |
58152cd4 | 888 | MODULE_FIRMWARE(FIRMWARE_8106E_2); |
beb330a4 | 889 | MODULE_FIRMWARE(FIRMWARE_8168G_2); |
57538c4a | 890 | MODULE_FIRMWARE(FIRMWARE_8168G_3); |
6e1d0b89 CHL |
891 | MODULE_FIRMWARE(FIRMWARE_8168H_1); |
892 | MODULE_FIRMWARE(FIRMWARE_8168H_2); | |
a3bf5c42 FR |
893 | MODULE_FIRMWARE(FIRMWARE_8107E_1); |
894 | MODULE_FIRMWARE(FIRMWARE_8107E_2); | |
1da177e4 | 895 | |
da78dbff FR |
896 | static void rtl_lock_work(struct rtl8169_private *tp) |
897 | { | |
898 | mutex_lock(&tp->wk.mutex); | |
899 | } | |
900 | ||
901 | static void rtl_unlock_work(struct rtl8169_private *tp) | |
902 | { | |
903 | mutex_unlock(&tp->wk.mutex); | |
904 | } | |
905 | ||
d58d46b5 FR |
906 | static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
907 | { | |
7d7903b2 JL |
908 | pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL, |
909 | PCI_EXP_DEVCTL_READRQ, force); | |
d58d46b5 FR |
910 | } |
911 | ||
ffc46952 FR |
912 | struct rtl_cond { |
913 | bool (*check)(struct rtl8169_private *); | |
914 | const char *msg; | |
915 | }; | |
916 | ||
917 | static void rtl_udelay(unsigned int d) | |
918 | { | |
919 | udelay(d); | |
920 | } | |
921 | ||
922 | static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, | |
923 | void (*delay)(unsigned int), unsigned int d, int n, | |
924 | bool high) | |
925 | { | |
926 | int i; | |
927 | ||
928 | for (i = 0; i < n; i++) { | |
929 | delay(d); | |
930 | if (c->check(tp) == high) | |
931 | return true; | |
932 | } | |
82e316ef FR |
933 | netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n", |
934 | c->msg, !high, n, d); | |
ffc46952 FR |
935 | return false; |
936 | } | |
937 | ||
938 | static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, | |
939 | const struct rtl_cond *c, | |
940 | unsigned int d, int n) | |
941 | { | |
942 | return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); | |
943 | } | |
944 | ||
945 | static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, | |
946 | const struct rtl_cond *c, | |
947 | unsigned int d, int n) | |
948 | { | |
949 | return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); | |
950 | } | |
951 | ||
952 | static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, | |
953 | const struct rtl_cond *c, | |
954 | unsigned int d, int n) | |
955 | { | |
956 | return rtl_loop_wait(tp, c, msleep, d, n, true); | |
957 | } | |
958 | ||
959 | static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, | |
960 | const struct rtl_cond *c, | |
961 | unsigned int d, int n) | |
962 | { | |
963 | return rtl_loop_wait(tp, c, msleep, d, n, false); | |
964 | } | |
965 | ||
966 | #define DECLARE_RTL_COND(name) \ | |
967 | static bool name ## _check(struct rtl8169_private *); \ | |
968 | \ | |
969 | static const struct rtl_cond name = { \ | |
970 | .check = name ## _check, \ | |
971 | .msg = #name \ | |
972 | }; \ | |
973 | \ | |
974 | static bool name ## _check(struct rtl8169_private *tp) | |
975 | ||
c558386b HW |
976 | static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) |
977 | { | |
978 | if (reg & 0xffff0001) { | |
979 | netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg); | |
980 | return true; | |
981 | } | |
982 | return false; | |
983 | } | |
984 | ||
985 | DECLARE_RTL_COND(rtl_ocp_gphy_cond) | |
986 | { | |
987 | void __iomem *ioaddr = tp->mmio_addr; | |
988 | ||
989 | return RTL_R32(GPHY_OCP) & OCPAR_FLAG; | |
990 | } | |
991 | ||
992 | static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) | |
993 | { | |
994 | void __iomem *ioaddr = tp->mmio_addr; | |
995 | ||
996 | if (rtl_ocp_reg_failure(tp, reg)) | |
997 | return; | |
998 | ||
999 | RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); | |
1000 | ||
1001 | rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); | |
1002 | } | |
1003 | ||
1004 | static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) | |
1005 | { | |
1006 | void __iomem *ioaddr = tp->mmio_addr; | |
1007 | ||
1008 | if (rtl_ocp_reg_failure(tp, reg)) | |
1009 | return 0; | |
1010 | ||
1011 | RTL_W32(GPHY_OCP, reg << 15); | |
1012 | ||
1013 | return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? | |
1014 | (RTL_R32(GPHY_OCP) & 0xffff) : ~0; | |
1015 | } | |
1016 | ||
c558386b HW |
1017 | static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) |
1018 | { | |
1019 | void __iomem *ioaddr = tp->mmio_addr; | |
1020 | ||
1021 | if (rtl_ocp_reg_failure(tp, reg)) | |
1022 | return; | |
1023 | ||
1024 | RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data); | |
c558386b HW |
1025 | } |
1026 | ||
1027 | static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) | |
1028 | { | |
1029 | void __iomem *ioaddr = tp->mmio_addr; | |
1030 | ||
1031 | if (rtl_ocp_reg_failure(tp, reg)) | |
1032 | return 0; | |
1033 | ||
1034 | RTL_W32(OCPDR, reg << 15); | |
1035 | ||
3a83ad12 | 1036 | return RTL_R32(OCPDR); |
c558386b HW |
1037 | } |
1038 | ||
1039 | #define OCP_STD_PHY_BASE 0xa400 | |
1040 | ||
1041 | static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) | |
1042 | { | |
1043 | if (reg == 0x1f) { | |
1044 | tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; | |
1045 | return; | |
1046 | } | |
1047 | ||
1048 | if (tp->ocp_base != OCP_STD_PHY_BASE) | |
1049 | reg -= 0x10; | |
1050 | ||
1051 | r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); | |
1052 | } | |
1053 | ||
1054 | static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) | |
1055 | { | |
1056 | if (tp->ocp_base != OCP_STD_PHY_BASE) | |
1057 | reg -= 0x10; | |
1058 | ||
1059 | return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); | |
1060 | } | |
1061 | ||
eee3786f | 1062 | static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) |
1063 | { | |
1064 | if (reg == 0x1f) { | |
1065 | tp->ocp_base = value << 4; | |
1066 | return; | |
1067 | } | |
1068 | ||
1069 | r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); | |
1070 | } | |
1071 | ||
1072 | static int mac_mcu_read(struct rtl8169_private *tp, int reg) | |
1073 | { | |
1074 | return r8168_mac_ocp_read(tp, tp->ocp_base + reg); | |
1075 | } | |
1076 | ||
ffc46952 FR |
1077 | DECLARE_RTL_COND(rtl_phyar_cond) |
1078 | { | |
1079 | void __iomem *ioaddr = tp->mmio_addr; | |
1080 | ||
1081 | return RTL_R32(PHYAR) & 0x80000000; | |
1082 | } | |
1083 | ||
24192210 | 1084 | static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) |
1da177e4 | 1085 | { |
24192210 | 1086 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 1087 | |
24192210 | 1088 | RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); |
1da177e4 | 1089 | |
ffc46952 | 1090 | rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); |
024a07ba | 1091 | /* |
81a95f04 TT |
1092 | * According to hardware specs a 20us delay is required after write |
1093 | * complete indication, but before sending next command. | |
024a07ba | 1094 | */ |
81a95f04 | 1095 | udelay(20); |
1da177e4 LT |
1096 | } |
1097 | ||
24192210 | 1098 | static int r8169_mdio_read(struct rtl8169_private *tp, int reg) |
1da177e4 | 1099 | { |
24192210 | 1100 | void __iomem *ioaddr = tp->mmio_addr; |
ffc46952 | 1101 | int value; |
1da177e4 | 1102 | |
24192210 | 1103 | RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16); |
1da177e4 | 1104 | |
ffc46952 FR |
1105 | value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? |
1106 | RTL_R32(PHYAR) & 0xffff : ~0; | |
1107 | ||
81a95f04 TT |
1108 | /* |
1109 | * According to hardware specs a 20us delay is required after read | |
1110 | * complete indication, but before sending next command. | |
1111 | */ | |
1112 | udelay(20); | |
1113 | ||
1da177e4 LT |
1114 | return value; |
1115 | } | |
1116 | ||
935e2218 CHL |
1117 | DECLARE_RTL_COND(rtl_ocpar_cond) |
1118 | { | |
1119 | void __iomem *ioaddr = tp->mmio_addr; | |
1120 | ||
1121 | return RTL_R32(OCPAR) & OCPAR_FLAG; | |
1122 | } | |
1123 | ||
24192210 | 1124 | static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) |
c0e45c1c | 1125 | { |
24192210 | 1126 | void __iomem *ioaddr = tp->mmio_addr; |
c0e45c1c | 1127 | |
24192210 | 1128 | RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); |
c0e45c1c | 1129 | RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD); |
1130 | RTL_W32(EPHY_RXER_NUM, 0); | |
1131 | ||
ffc46952 | 1132 | rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); |
c0e45c1c | 1133 | } |
1134 | ||
24192210 | 1135 | static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) |
c0e45c1c | 1136 | { |
24192210 FR |
1137 | r8168dp_1_mdio_access(tp, reg, |
1138 | OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); | |
c0e45c1c | 1139 | } |
1140 | ||
24192210 | 1141 | static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) |
c0e45c1c | 1142 | { |
24192210 | 1143 | void __iomem *ioaddr = tp->mmio_addr; |
c0e45c1c | 1144 | |
24192210 | 1145 | r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); |
c0e45c1c | 1146 | |
1147 | mdelay(1); | |
1148 | RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD); | |
1149 | RTL_W32(EPHY_RXER_NUM, 0); | |
1150 | ||
ffc46952 FR |
1151 | return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? |
1152 | RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0; | |
c0e45c1c | 1153 | } |
1154 | ||
e6de30d6 | 1155 | #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 |
1156 | ||
1157 | static void r8168dp_2_mdio_start(void __iomem *ioaddr) | |
1158 | { | |
1159 | RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); | |
1160 | } | |
1161 | ||
1162 | static void r8168dp_2_mdio_stop(void __iomem *ioaddr) | |
1163 | { | |
1164 | RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT); | |
1165 | } | |
1166 | ||
24192210 | 1167 | static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) |
e6de30d6 | 1168 | { |
24192210 FR |
1169 | void __iomem *ioaddr = tp->mmio_addr; |
1170 | ||
e6de30d6 | 1171 | r8168dp_2_mdio_start(ioaddr); |
1172 | ||
24192210 | 1173 | r8169_mdio_write(tp, reg, value); |
e6de30d6 | 1174 | |
1175 | r8168dp_2_mdio_stop(ioaddr); | |
1176 | } | |
1177 | ||
24192210 | 1178 | static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) |
e6de30d6 | 1179 | { |
24192210 | 1180 | void __iomem *ioaddr = tp->mmio_addr; |
e6de30d6 | 1181 | int value; |
1182 | ||
1183 | r8168dp_2_mdio_start(ioaddr); | |
1184 | ||
24192210 | 1185 | value = r8169_mdio_read(tp, reg); |
e6de30d6 | 1186 | |
1187 | r8168dp_2_mdio_stop(ioaddr); | |
1188 | ||
1189 | return value; | |
1190 | } | |
1191 | ||
4da19633 | 1192 | static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val) |
dacf8154 | 1193 | { |
24192210 | 1194 | tp->mdio_ops.write(tp, location, val); |
dacf8154 FR |
1195 | } |
1196 | ||
4da19633 | 1197 | static int rtl_readphy(struct rtl8169_private *tp, int location) |
1198 | { | |
24192210 | 1199 | return tp->mdio_ops.read(tp, location); |
4da19633 | 1200 | } |
1201 | ||
1202 | static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) | |
1203 | { | |
1204 | rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); | |
1205 | } | |
1206 | ||
76564428 | 1207 | static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) |
daf9df6d | 1208 | { |
1209 | int val; | |
1210 | ||
4da19633 | 1211 | val = rtl_readphy(tp, reg_addr); |
76564428 | 1212 | rtl_writephy(tp, reg_addr, (val & ~m) | p); |
daf9df6d | 1213 | } |
1214 | ||
ccdffb9a FR |
1215 | static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
1216 | int val) | |
1217 | { | |
1218 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 1219 | |
4da19633 | 1220 | rtl_writephy(tp, location, val); |
ccdffb9a FR |
1221 | } |
1222 | ||
1223 | static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) | |
1224 | { | |
1225 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 1226 | |
4da19633 | 1227 | return rtl_readphy(tp, location); |
ccdffb9a FR |
1228 | } |
1229 | ||
ffc46952 FR |
1230 | DECLARE_RTL_COND(rtl_ephyar_cond) |
1231 | { | |
1232 | void __iomem *ioaddr = tp->mmio_addr; | |
1233 | ||
1234 | return RTL_R32(EPHYAR) & EPHYAR_FLAG; | |
1235 | } | |
1236 | ||
fdf6fc06 | 1237 | static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) |
dacf8154 | 1238 | { |
fdf6fc06 | 1239 | void __iomem *ioaddr = tp->mmio_addr; |
dacf8154 FR |
1240 | |
1241 | RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | | |
1242 | (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
1243 | ||
ffc46952 FR |
1244 | rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); |
1245 | ||
1246 | udelay(10); | |
dacf8154 FR |
1247 | } |
1248 | ||
fdf6fc06 | 1249 | static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) |
dacf8154 | 1250 | { |
fdf6fc06 | 1251 | void __iomem *ioaddr = tp->mmio_addr; |
dacf8154 FR |
1252 | |
1253 | RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
1254 | ||
ffc46952 FR |
1255 | return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? |
1256 | RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0; | |
dacf8154 FR |
1257 | } |
1258 | ||
935e2218 CHL |
1259 | DECLARE_RTL_COND(rtl_eriar_cond) |
1260 | { | |
1261 | void __iomem *ioaddr = tp->mmio_addr; | |
1262 | ||
1263 | return RTL_R32(ERIAR) & ERIAR_FLAG; | |
1264 | } | |
1265 | ||
fdf6fc06 FR |
1266 | static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, |
1267 | u32 val, int type) | |
133ac40a | 1268 | { |
fdf6fc06 | 1269 | void __iomem *ioaddr = tp->mmio_addr; |
133ac40a HW |
1270 | |
1271 | BUG_ON((addr & 3) || (mask == 0)); | |
1272 | RTL_W32(ERIDR, val); | |
1273 | RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr); | |
1274 | ||
ffc46952 | 1275 | rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); |
133ac40a HW |
1276 | } |
1277 | ||
fdf6fc06 | 1278 | static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type) |
133ac40a | 1279 | { |
fdf6fc06 | 1280 | void __iomem *ioaddr = tp->mmio_addr; |
133ac40a HW |
1281 | |
1282 | RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); | |
1283 | ||
ffc46952 FR |
1284 | return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? |
1285 | RTL_R32(ERIDR) : ~0; | |
133ac40a HW |
1286 | } |
1287 | ||
706123d0 | 1288 | static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, |
fdf6fc06 | 1289 | u32 m, int type) |
133ac40a HW |
1290 | { |
1291 | u32 val; | |
1292 | ||
fdf6fc06 FR |
1293 | val = rtl_eri_read(tp, addr, type); |
1294 | rtl_eri_write(tp, addr, mask, (val & ~m) | p, type); | |
133ac40a HW |
1295 | } |
1296 | ||
935e2218 CHL |
1297 | static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) |
1298 | { | |
1299 | void __iomem *ioaddr = tp->mmio_addr; | |
1300 | ||
1301 | RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
1302 | return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? | |
1303 | RTL_R32(OCPDR) : ~0; | |
1304 | } | |
1305 | ||
1306 | static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) | |
1307 | { | |
1308 | return rtl_eri_read(tp, reg, ERIAR_OOB); | |
1309 | } | |
1310 | ||
1311 | static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) | |
1312 | { | |
1313 | switch (tp->mac_version) { | |
1314 | case RTL_GIGA_MAC_VER_27: | |
1315 | case RTL_GIGA_MAC_VER_28: | |
1316 | case RTL_GIGA_MAC_VER_31: | |
1317 | return r8168dp_ocp_read(tp, mask, reg); | |
1318 | case RTL_GIGA_MAC_VER_49: | |
1319 | case RTL_GIGA_MAC_VER_50: | |
1320 | case RTL_GIGA_MAC_VER_51: | |
1321 | return r8168ep_ocp_read(tp, mask, reg); | |
1322 | default: | |
1323 | BUG(); | |
1324 | return ~0; | |
1325 | } | |
1326 | } | |
1327 | ||
1328 | static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, | |
1329 | u32 data) | |
1330 | { | |
1331 | void __iomem *ioaddr = tp->mmio_addr; | |
1332 | ||
1333 | RTL_W32(OCPDR, data); | |
1334 | RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
1335 | rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); | |
1336 | } | |
1337 | ||
1338 | static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, | |
1339 | u32 data) | |
1340 | { | |
1341 | rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, | |
1342 | data, ERIAR_OOB); | |
1343 | } | |
1344 | ||
1345 | static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data) | |
1346 | { | |
1347 | switch (tp->mac_version) { | |
1348 | case RTL_GIGA_MAC_VER_27: | |
1349 | case RTL_GIGA_MAC_VER_28: | |
1350 | case RTL_GIGA_MAC_VER_31: | |
1351 | r8168dp_ocp_write(tp, mask, reg, data); | |
1352 | break; | |
1353 | case RTL_GIGA_MAC_VER_49: | |
1354 | case RTL_GIGA_MAC_VER_50: | |
1355 | case RTL_GIGA_MAC_VER_51: | |
1356 | r8168ep_ocp_write(tp, mask, reg, data); | |
1357 | break; | |
1358 | default: | |
1359 | BUG(); | |
1360 | break; | |
1361 | } | |
1362 | } | |
1363 | ||
2a9b4d96 CHL |
1364 | static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd) |
1365 | { | |
1366 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC); | |
1367 | ||
1368 | ocp_write(tp, 0x1, 0x30, 0x00000001); | |
1369 | } | |
1370 | ||
1371 | #define OOB_CMD_RESET 0x00 | |
1372 | #define OOB_CMD_DRIVER_START 0x05 | |
1373 | #define OOB_CMD_DRIVER_STOP 0x06 | |
1374 | ||
1375 | static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) | |
1376 | { | |
1377 | return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; | |
1378 | } | |
1379 | ||
1380 | DECLARE_RTL_COND(rtl_ocp_read_cond) | |
1381 | { | |
1382 | u16 reg; | |
1383 | ||
1384 | reg = rtl8168_get_ocp_reg(tp); | |
1385 | ||
1386 | return ocp_read(tp, 0x0f, reg) & 0x00000800; | |
1387 | } | |
1388 | ||
935e2218 | 1389 | DECLARE_RTL_COND(rtl_ep_ocp_read_cond) |
2a9b4d96 | 1390 | { |
935e2218 CHL |
1391 | return ocp_read(tp, 0x0f, 0x124) & 0x00000001; |
1392 | } | |
1393 | ||
1394 | DECLARE_RTL_COND(rtl_ocp_tx_cond) | |
1395 | { | |
1396 | void __iomem *ioaddr = tp->mmio_addr; | |
1397 | ||
1398 | return RTL_R8(IBISR0) & 0x02; | |
1399 | } | |
2a9b4d96 | 1400 | |
003609da CHL |
1401 | static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) |
1402 | { | |
1403 | void __iomem *ioaddr = tp->mmio_addr; | |
1404 | ||
1405 | RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01); | |
1406 | rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000); | |
1407 | RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20); | |
1408 | RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01); | |
1409 | } | |
1410 | ||
935e2218 CHL |
1411 | static void rtl8168dp_driver_start(struct rtl8169_private *tp) |
1412 | { | |
1413 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START); | |
2a9b4d96 CHL |
1414 | rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10); |
1415 | } | |
1416 | ||
935e2218 | 1417 | static void rtl8168ep_driver_start(struct rtl8169_private *tp) |
2a9b4d96 | 1418 | { |
935e2218 CHL |
1419 | ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); |
1420 | ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01); | |
1421 | rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10); | |
1422 | } | |
1423 | ||
1424 | static void rtl8168_driver_start(struct rtl8169_private *tp) | |
1425 | { | |
1426 | switch (tp->mac_version) { | |
1427 | case RTL_GIGA_MAC_VER_27: | |
1428 | case RTL_GIGA_MAC_VER_28: | |
1429 | case RTL_GIGA_MAC_VER_31: | |
1430 | rtl8168dp_driver_start(tp); | |
1431 | break; | |
1432 | case RTL_GIGA_MAC_VER_49: | |
1433 | case RTL_GIGA_MAC_VER_50: | |
1434 | case RTL_GIGA_MAC_VER_51: | |
1435 | rtl8168ep_driver_start(tp); | |
1436 | break; | |
1437 | default: | |
1438 | BUG(); | |
1439 | break; | |
1440 | } | |
1441 | } | |
2a9b4d96 | 1442 | |
935e2218 CHL |
1443 | static void rtl8168dp_driver_stop(struct rtl8169_private *tp) |
1444 | { | |
1445 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP); | |
2a9b4d96 CHL |
1446 | rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10); |
1447 | } | |
1448 | ||
935e2218 CHL |
1449 | static void rtl8168ep_driver_stop(struct rtl8169_private *tp) |
1450 | { | |
003609da | 1451 | rtl8168ep_stop_cmac(tp); |
935e2218 CHL |
1452 | ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); |
1453 | ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01); | |
1454 | rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10); | |
1455 | } | |
1456 | ||
1457 | static void rtl8168_driver_stop(struct rtl8169_private *tp) | |
1458 | { | |
1459 | switch (tp->mac_version) { | |
1460 | case RTL_GIGA_MAC_VER_27: | |
1461 | case RTL_GIGA_MAC_VER_28: | |
1462 | case RTL_GIGA_MAC_VER_31: | |
1463 | rtl8168dp_driver_stop(tp); | |
1464 | break; | |
1465 | case RTL_GIGA_MAC_VER_49: | |
1466 | case RTL_GIGA_MAC_VER_50: | |
1467 | case RTL_GIGA_MAC_VER_51: | |
1468 | rtl8168ep_driver_stop(tp); | |
1469 | break; | |
1470 | default: | |
1471 | BUG(); | |
1472 | break; | |
1473 | } | |
1474 | } | |
1475 | ||
1476 | static int r8168dp_check_dash(struct rtl8169_private *tp) | |
2a9b4d96 CHL |
1477 | { |
1478 | u16 reg = rtl8168_get_ocp_reg(tp); | |
1479 | ||
1480 | return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0; | |
1481 | } | |
1482 | ||
935e2218 CHL |
1483 | static int r8168ep_check_dash(struct rtl8169_private *tp) |
1484 | { | |
1485 | return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0; | |
1486 | } | |
1487 | ||
1488 | static int r8168_check_dash(struct rtl8169_private *tp) | |
1489 | { | |
1490 | switch (tp->mac_version) { | |
1491 | case RTL_GIGA_MAC_VER_27: | |
1492 | case RTL_GIGA_MAC_VER_28: | |
1493 | case RTL_GIGA_MAC_VER_31: | |
1494 | return r8168dp_check_dash(tp); | |
1495 | case RTL_GIGA_MAC_VER_49: | |
1496 | case RTL_GIGA_MAC_VER_50: | |
1497 | case RTL_GIGA_MAC_VER_51: | |
1498 | return r8168ep_check_dash(tp); | |
1499 | default: | |
1500 | return 0; | |
1501 | } | |
1502 | } | |
1503 | ||
c28aa385 | 1504 | struct exgmac_reg { |
1505 | u16 addr; | |
1506 | u16 mask; | |
1507 | u32 val; | |
1508 | }; | |
1509 | ||
fdf6fc06 | 1510 | static void rtl_write_exgmac_batch(struct rtl8169_private *tp, |
c28aa385 | 1511 | const struct exgmac_reg *r, int len) |
1512 | { | |
1513 | while (len-- > 0) { | |
fdf6fc06 | 1514 | rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC); |
c28aa385 | 1515 | r++; |
1516 | } | |
1517 | } | |
1518 | ||
ffc46952 FR |
1519 | DECLARE_RTL_COND(rtl_efusear_cond) |
1520 | { | |
1521 | void __iomem *ioaddr = tp->mmio_addr; | |
1522 | ||
1523 | return RTL_R32(EFUSEAR) & EFUSEAR_FLAG; | |
1524 | } | |
1525 | ||
fdf6fc06 | 1526 | static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) |
daf9df6d | 1527 | { |
fdf6fc06 | 1528 | void __iomem *ioaddr = tp->mmio_addr; |
daf9df6d | 1529 | |
1530 | RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); | |
1531 | ||
ffc46952 FR |
1532 | return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? |
1533 | RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0; | |
daf9df6d | 1534 | } |
1535 | ||
9085cdfa FR |
1536 | static u16 rtl_get_events(struct rtl8169_private *tp) |
1537 | { | |
1538 | void __iomem *ioaddr = tp->mmio_addr; | |
1539 | ||
1540 | return RTL_R16(IntrStatus); | |
1541 | } | |
1542 | ||
1543 | static void rtl_ack_events(struct rtl8169_private *tp, u16 bits) | |
1544 | { | |
1545 | void __iomem *ioaddr = tp->mmio_addr; | |
1546 | ||
1547 | RTL_W16(IntrStatus, bits); | |
1548 | mmiowb(); | |
1549 | } | |
1550 | ||
1551 | static void rtl_irq_disable(struct rtl8169_private *tp) | |
1552 | { | |
1553 | void __iomem *ioaddr = tp->mmio_addr; | |
1554 | ||
1555 | RTL_W16(IntrMask, 0); | |
1556 | mmiowb(); | |
1557 | } | |
1558 | ||
3e990ff5 FR |
1559 | static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits) |
1560 | { | |
1561 | void __iomem *ioaddr = tp->mmio_addr; | |
1562 | ||
1563 | RTL_W16(IntrMask, bits); | |
1564 | } | |
1565 | ||
da78dbff FR |
1566 | #define RTL_EVENT_NAPI_RX (RxOK | RxErr) |
1567 | #define RTL_EVENT_NAPI_TX (TxOK | TxErr) | |
1568 | #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) | |
1569 | ||
1570 | static void rtl_irq_enable_all(struct rtl8169_private *tp) | |
1571 | { | |
1572 | rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow); | |
1573 | } | |
1574 | ||
811fd301 | 1575 | static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) |
1da177e4 | 1576 | { |
811fd301 | 1577 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 1578 | |
9085cdfa | 1579 | rtl_irq_disable(tp); |
da78dbff | 1580 | rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow); |
811fd301 | 1581 | RTL_R8(ChipCmd); |
1da177e4 LT |
1582 | } |
1583 | ||
4da19633 | 1584 | static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 1585 | { |
4da19633 | 1586 | void __iomem *ioaddr = tp->mmio_addr; |
1587 | ||
1da177e4 LT |
1588 | return RTL_R32(TBICSR) & TBIReset; |
1589 | } | |
1590 | ||
4da19633 | 1591 | static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 1592 | { |
4da19633 | 1593 | return rtl_readphy(tp, MII_BMCR) & BMCR_RESET; |
1da177e4 LT |
1594 | } |
1595 | ||
1596 | static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) | |
1597 | { | |
1598 | return RTL_R32(TBICSR) & TBILinkOk; | |
1599 | } | |
1600 | ||
1601 | static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) | |
1602 | { | |
1603 | return RTL_R8(PHYstatus) & LinkStatus; | |
1604 | } | |
1605 | ||
4da19633 | 1606 | static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp) |
1da177e4 | 1607 | { |
4da19633 | 1608 | void __iomem *ioaddr = tp->mmio_addr; |
1609 | ||
1da177e4 LT |
1610 | RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
1611 | } | |
1612 | ||
4da19633 | 1613 | static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp) |
1da177e4 LT |
1614 | { |
1615 | unsigned int val; | |
1616 | ||
4da19633 | 1617 | val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET; |
1618 | rtl_writephy(tp, MII_BMCR, val & 0xffff); | |
1da177e4 LT |
1619 | } |
1620 | ||
70090424 HW |
1621 | static void rtl_link_chg_patch(struct rtl8169_private *tp) |
1622 | { | |
1623 | void __iomem *ioaddr = tp->mmio_addr; | |
1624 | struct net_device *dev = tp->dev; | |
1625 | ||
1626 | if (!netif_running(dev)) | |
1627 | return; | |
1628 | ||
b3d7b2f2 HW |
1629 | if (tp->mac_version == RTL_GIGA_MAC_VER_34 || |
1630 | tp->mac_version == RTL_GIGA_MAC_VER_38) { | |
70090424 | 1631 | if (RTL_R8(PHYstatus) & _1000bpsF) { |
fdf6fc06 FR |
1632 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011, |
1633 | ERIAR_EXGMAC); | |
1634 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, | |
1635 | ERIAR_EXGMAC); | |
70090424 | 1636 | } else if (RTL_R8(PHYstatus) & _100bps) { |
fdf6fc06 FR |
1637 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
1638 | ERIAR_EXGMAC); | |
1639 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, | |
1640 | ERIAR_EXGMAC); | |
70090424 | 1641 | } else { |
fdf6fc06 FR |
1642 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
1643 | ERIAR_EXGMAC); | |
1644 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f, | |
1645 | ERIAR_EXGMAC); | |
70090424 HW |
1646 | } |
1647 | /* Reset packet filter */ | |
706123d0 | 1648 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, |
70090424 | 1649 | ERIAR_EXGMAC); |
706123d0 | 1650 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, |
70090424 | 1651 | ERIAR_EXGMAC); |
c2218925 HW |
1652 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || |
1653 | tp->mac_version == RTL_GIGA_MAC_VER_36) { | |
1654 | if (RTL_R8(PHYstatus) & _1000bpsF) { | |
fdf6fc06 FR |
1655 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011, |
1656 | ERIAR_EXGMAC); | |
1657 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, | |
1658 | ERIAR_EXGMAC); | |
c2218925 | 1659 | } else { |
fdf6fc06 FR |
1660 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
1661 | ERIAR_EXGMAC); | |
1662 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f, | |
1663 | ERIAR_EXGMAC); | |
c2218925 | 1664 | } |
7e18dca1 HW |
1665 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { |
1666 | if (RTL_R8(PHYstatus) & _10bps) { | |
fdf6fc06 FR |
1667 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02, |
1668 | ERIAR_EXGMAC); | |
1669 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060, | |
1670 | ERIAR_EXGMAC); | |
7e18dca1 | 1671 | } else { |
fdf6fc06 FR |
1672 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, |
1673 | ERIAR_EXGMAC); | |
7e18dca1 | 1674 | } |
70090424 HW |
1675 | } |
1676 | } | |
1677 | ||
e4fbce74 | 1678 | static void __rtl8169_check_link_status(struct net_device *dev, |
cecb5fd7 FR |
1679 | struct rtl8169_private *tp, |
1680 | void __iomem *ioaddr, bool pm) | |
1da177e4 | 1681 | { |
1da177e4 | 1682 | if (tp->link_ok(ioaddr)) { |
70090424 | 1683 | rtl_link_chg_patch(tp); |
e1759441 | 1684 | /* This is to cancel a scheduled suspend if there's one. */ |
e4fbce74 RW |
1685 | if (pm) |
1686 | pm_request_resume(&tp->pci_dev->dev); | |
1da177e4 | 1687 | netif_carrier_on(dev); |
1519e57f FR |
1688 | if (net_ratelimit()) |
1689 | netif_info(tp, ifup, dev, "link up\n"); | |
b57b7e5a | 1690 | } else { |
1da177e4 | 1691 | netif_carrier_off(dev); |
bf82c189 | 1692 | netif_info(tp, ifdown, dev, "link down\n"); |
e4fbce74 | 1693 | if (pm) |
10953db8 | 1694 | pm_schedule_suspend(&tp->pci_dev->dev, 5000); |
b57b7e5a | 1695 | } |
1da177e4 LT |
1696 | } |
1697 | ||
e4fbce74 RW |
1698 | static void rtl8169_check_link_status(struct net_device *dev, |
1699 | struct rtl8169_private *tp, | |
1700 | void __iomem *ioaddr) | |
1701 | { | |
1702 | __rtl8169_check_link_status(dev, tp, ioaddr, false); | |
1703 | } | |
1704 | ||
e1759441 RW |
1705 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
1706 | ||
1707 | static u32 __rtl8169_get_wol(struct rtl8169_private *tp) | |
61a4dcc2 | 1708 | { |
61a4dcc2 FR |
1709 | void __iomem *ioaddr = tp->mmio_addr; |
1710 | u8 options; | |
e1759441 | 1711 | u32 wolopts = 0; |
61a4dcc2 FR |
1712 | |
1713 | options = RTL_R8(Config1); | |
1714 | if (!(options & PMEnable)) | |
e1759441 | 1715 | return 0; |
61a4dcc2 FR |
1716 | |
1717 | options = RTL_R8(Config3); | |
1718 | if (options & LinkUp) | |
e1759441 | 1719 | wolopts |= WAKE_PHY; |
6e1d0b89 | 1720 | switch (tp->mac_version) { |
ac85bcdb CHL |
1721 | case RTL_GIGA_MAC_VER_34: |
1722 | case RTL_GIGA_MAC_VER_35: | |
1723 | case RTL_GIGA_MAC_VER_36: | |
1724 | case RTL_GIGA_MAC_VER_37: | |
1725 | case RTL_GIGA_MAC_VER_38: | |
1726 | case RTL_GIGA_MAC_VER_40: | |
1727 | case RTL_GIGA_MAC_VER_41: | |
1728 | case RTL_GIGA_MAC_VER_42: | |
1729 | case RTL_GIGA_MAC_VER_43: | |
1730 | case RTL_GIGA_MAC_VER_44: | |
6e1d0b89 CHL |
1731 | case RTL_GIGA_MAC_VER_45: |
1732 | case RTL_GIGA_MAC_VER_46: | |
ac85bcdb CHL |
1733 | case RTL_GIGA_MAC_VER_47: |
1734 | case RTL_GIGA_MAC_VER_48: | |
935e2218 CHL |
1735 | case RTL_GIGA_MAC_VER_49: |
1736 | case RTL_GIGA_MAC_VER_50: | |
1737 | case RTL_GIGA_MAC_VER_51: | |
6e1d0b89 CHL |
1738 | if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2) |
1739 | wolopts |= WAKE_MAGIC; | |
1740 | break; | |
1741 | default: | |
1742 | if (options & MagicPacket) | |
1743 | wolopts |= WAKE_MAGIC; | |
1744 | break; | |
1745 | } | |
61a4dcc2 FR |
1746 | |
1747 | options = RTL_R8(Config5); | |
1748 | if (options & UWF) | |
e1759441 | 1749 | wolopts |= WAKE_UCAST; |
61a4dcc2 | 1750 | if (options & BWF) |
e1759441 | 1751 | wolopts |= WAKE_BCAST; |
61a4dcc2 | 1752 | if (options & MWF) |
e1759441 | 1753 | wolopts |= WAKE_MCAST; |
61a4dcc2 | 1754 | |
e1759441 | 1755 | return wolopts; |
61a4dcc2 FR |
1756 | } |
1757 | ||
e1759441 | 1758 | static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
61a4dcc2 FR |
1759 | { |
1760 | struct rtl8169_private *tp = netdev_priv(dev); | |
5fa80a32 CHL |
1761 | struct device *d = &tp->pci_dev->dev; |
1762 | ||
1763 | pm_runtime_get_noresume(d); | |
e1759441 | 1764 | |
da78dbff | 1765 | rtl_lock_work(tp); |
e1759441 RW |
1766 | |
1767 | wol->supported = WAKE_ANY; | |
5fa80a32 CHL |
1768 | if (pm_runtime_active(d)) |
1769 | wol->wolopts = __rtl8169_get_wol(tp); | |
1770 | else | |
1771 | wol->wolopts = tp->saved_wolopts; | |
e1759441 | 1772 | |
da78dbff | 1773 | rtl_unlock_work(tp); |
5fa80a32 CHL |
1774 | |
1775 | pm_runtime_put_noidle(d); | |
e1759441 RW |
1776 | } |
1777 | ||
1778 | static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) | |
1779 | { | |
61a4dcc2 | 1780 | void __iomem *ioaddr = tp->mmio_addr; |
6e1d0b89 | 1781 | unsigned int i, tmp; |
350f7596 | 1782 | static const struct { |
61a4dcc2 FR |
1783 | u32 opt; |
1784 | u16 reg; | |
1785 | u8 mask; | |
1786 | } cfg[] = { | |
61a4dcc2 | 1787 | { WAKE_PHY, Config3, LinkUp }, |
61a4dcc2 FR |
1788 | { WAKE_UCAST, Config5, UWF }, |
1789 | { WAKE_BCAST, Config5, BWF }, | |
1790 | { WAKE_MCAST, Config5, MWF }, | |
6e1d0b89 CHL |
1791 | { WAKE_ANY, Config5, LanWake }, |
1792 | { WAKE_MAGIC, Config3, MagicPacket } | |
61a4dcc2 | 1793 | }; |
851e6022 | 1794 | u8 options; |
61a4dcc2 | 1795 | |
61a4dcc2 FR |
1796 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
1797 | ||
6e1d0b89 | 1798 | switch (tp->mac_version) { |
ac85bcdb CHL |
1799 | case RTL_GIGA_MAC_VER_34: |
1800 | case RTL_GIGA_MAC_VER_35: | |
1801 | case RTL_GIGA_MAC_VER_36: | |
1802 | case RTL_GIGA_MAC_VER_37: | |
1803 | case RTL_GIGA_MAC_VER_38: | |
1804 | case RTL_GIGA_MAC_VER_40: | |
1805 | case RTL_GIGA_MAC_VER_41: | |
1806 | case RTL_GIGA_MAC_VER_42: | |
1807 | case RTL_GIGA_MAC_VER_43: | |
1808 | case RTL_GIGA_MAC_VER_44: | |
6e1d0b89 CHL |
1809 | case RTL_GIGA_MAC_VER_45: |
1810 | case RTL_GIGA_MAC_VER_46: | |
ac85bcdb CHL |
1811 | case RTL_GIGA_MAC_VER_47: |
1812 | case RTL_GIGA_MAC_VER_48: | |
935e2218 CHL |
1813 | case RTL_GIGA_MAC_VER_49: |
1814 | case RTL_GIGA_MAC_VER_50: | |
1815 | case RTL_GIGA_MAC_VER_51: | |
6e1d0b89 CHL |
1816 | tmp = ARRAY_SIZE(cfg) - 1; |
1817 | if (wolopts & WAKE_MAGIC) | |
706123d0 | 1818 | rtl_w0w1_eri(tp, |
6e1d0b89 CHL |
1819 | 0x0dc, |
1820 | ERIAR_MASK_0100, | |
1821 | MagicPacket_v2, | |
1822 | 0x0000, | |
1823 | ERIAR_EXGMAC); | |
1824 | else | |
706123d0 | 1825 | rtl_w0w1_eri(tp, |
6e1d0b89 CHL |
1826 | 0x0dc, |
1827 | ERIAR_MASK_0100, | |
1828 | 0x0000, | |
1829 | MagicPacket_v2, | |
1830 | ERIAR_EXGMAC); | |
1831 | break; | |
1832 | default: | |
1833 | tmp = ARRAY_SIZE(cfg); | |
1834 | break; | |
1835 | } | |
1836 | ||
1837 | for (i = 0; i < tmp; i++) { | |
851e6022 | 1838 | options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; |
e1759441 | 1839 | if (wolopts & cfg[i].opt) |
61a4dcc2 FR |
1840 | options |= cfg[i].mask; |
1841 | RTL_W8(cfg[i].reg, options); | |
1842 | } | |
1843 | ||
851e6022 FR |
1844 | switch (tp->mac_version) { |
1845 | case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17: | |
1846 | options = RTL_R8(Config1) & ~PMEnable; | |
1847 | if (wolopts) | |
1848 | options |= PMEnable; | |
1849 | RTL_W8(Config1, options); | |
1850 | break; | |
1851 | default: | |
d387b427 FR |
1852 | options = RTL_R8(Config2) & ~PME_SIGNAL; |
1853 | if (wolopts) | |
1854 | options |= PME_SIGNAL; | |
1855 | RTL_W8(Config2, options); | |
851e6022 FR |
1856 | break; |
1857 | } | |
1858 | ||
61a4dcc2 | 1859 | RTL_W8(Cfg9346, Cfg9346_Lock); |
e1759441 RW |
1860 | } |
1861 | ||
1862 | static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1863 | { | |
1864 | struct rtl8169_private *tp = netdev_priv(dev); | |
5fa80a32 CHL |
1865 | struct device *d = &tp->pci_dev->dev; |
1866 | ||
1867 | pm_runtime_get_noresume(d); | |
e1759441 | 1868 | |
da78dbff | 1869 | rtl_lock_work(tp); |
61a4dcc2 | 1870 | |
f23e7fda FR |
1871 | if (wol->wolopts) |
1872 | tp->features |= RTL_FEATURE_WOL; | |
1873 | else | |
1874 | tp->features &= ~RTL_FEATURE_WOL; | |
5fa80a32 CHL |
1875 | if (pm_runtime_active(d)) |
1876 | __rtl8169_set_wol(tp, wol->wolopts); | |
1877 | else | |
1878 | tp->saved_wolopts = wol->wolopts; | |
da78dbff FR |
1879 | |
1880 | rtl_unlock_work(tp); | |
61a4dcc2 | 1881 | |
ea80907f | 1882 | device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
1883 | ||
5fa80a32 CHL |
1884 | pm_runtime_put_noidle(d); |
1885 | ||
61a4dcc2 FR |
1886 | return 0; |
1887 | } | |
1888 | ||
31bd204f FR |
1889 | static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp) |
1890 | { | |
85bffe6c | 1891 | return rtl_chip_infos[tp->mac_version].fw_name; |
31bd204f FR |
1892 | } |
1893 | ||
1da177e4 LT |
1894 | static void rtl8169_get_drvinfo(struct net_device *dev, |
1895 | struct ethtool_drvinfo *info) | |
1896 | { | |
1897 | struct rtl8169_private *tp = netdev_priv(dev); | |
b6ffd97f | 1898 | struct rtl_fw *rtl_fw = tp->rtl_fw; |
1da177e4 | 1899 | |
68aad78c RJ |
1900 | strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
1901 | strlcpy(info->version, RTL8169_VERSION, sizeof(info->version)); | |
1902 | strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); | |
1c361efb | 1903 | BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); |
8ac72d16 RJ |
1904 | if (!IS_ERR_OR_NULL(rtl_fw)) |
1905 | strlcpy(info->fw_version, rtl_fw->version, | |
1906 | sizeof(info->fw_version)); | |
1da177e4 LT |
1907 | } |
1908 | ||
1909 | static int rtl8169_get_regs_len(struct net_device *dev) | |
1910 | { | |
1911 | return R8169_REGS_SIZE; | |
1912 | } | |
1913 | ||
1914 | static int rtl8169_set_speed_tbi(struct net_device *dev, | |
54405cde | 1915 | u8 autoneg, u16 speed, u8 duplex, u32 ignored) |
1da177e4 LT |
1916 | { |
1917 | struct rtl8169_private *tp = netdev_priv(dev); | |
1918 | void __iomem *ioaddr = tp->mmio_addr; | |
1919 | int ret = 0; | |
1920 | u32 reg; | |
1921 | ||
1922 | reg = RTL_R32(TBICSR); | |
1923 | if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && | |
1924 | (duplex == DUPLEX_FULL)) { | |
1925 | RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); | |
1926 | } else if (autoneg == AUTONEG_ENABLE) | |
1927 | RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); | |
1928 | else { | |
bf82c189 JP |
1929 | netif_warn(tp, link, dev, |
1930 | "incorrect speed setting refused in TBI mode\n"); | |
1da177e4 LT |
1931 | ret = -EOPNOTSUPP; |
1932 | } | |
1933 | ||
1934 | return ret; | |
1935 | } | |
1936 | ||
1937 | static int rtl8169_set_speed_xmii(struct net_device *dev, | |
54405cde | 1938 | u8 autoneg, u16 speed, u8 duplex, u32 adv) |
1da177e4 LT |
1939 | { |
1940 | struct rtl8169_private *tp = netdev_priv(dev); | |
3577aa1b | 1941 | int giga_ctrl, bmcr; |
54405cde | 1942 | int rc = -EINVAL; |
1da177e4 | 1943 | |
716b50a3 | 1944 | rtl_writephy(tp, 0x1f, 0x0000); |
1da177e4 LT |
1945 | |
1946 | if (autoneg == AUTONEG_ENABLE) { | |
3577aa1b | 1947 | int auto_nego; |
1948 | ||
4da19633 | 1949 | auto_nego = rtl_readphy(tp, MII_ADVERTISE); |
54405cde ON |
1950 | auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
1951 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
1952 | ||
1953 | if (adv & ADVERTISED_10baseT_Half) | |
1954 | auto_nego |= ADVERTISE_10HALF; | |
1955 | if (adv & ADVERTISED_10baseT_Full) | |
1956 | auto_nego |= ADVERTISE_10FULL; | |
1957 | if (adv & ADVERTISED_100baseT_Half) | |
1958 | auto_nego |= ADVERTISE_100HALF; | |
1959 | if (adv & ADVERTISED_100baseT_Full) | |
1960 | auto_nego |= ADVERTISE_100FULL; | |
1961 | ||
3577aa1b | 1962 | auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1da177e4 | 1963 | |
4da19633 | 1964 | giga_ctrl = rtl_readphy(tp, MII_CTRL1000); |
3577aa1b | 1965 | giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
bcf0bf90 | 1966 | |
3577aa1b | 1967 | /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
826e6cbd | 1968 | if (tp->mii.supports_gmii) { |
54405cde ON |
1969 | if (adv & ADVERTISED_1000baseT_Half) |
1970 | giga_ctrl |= ADVERTISE_1000HALF; | |
1971 | if (adv & ADVERTISED_1000baseT_Full) | |
1972 | giga_ctrl |= ADVERTISE_1000FULL; | |
1973 | } else if (adv & (ADVERTISED_1000baseT_Half | | |
1974 | ADVERTISED_1000baseT_Full)) { | |
bf82c189 JP |
1975 | netif_info(tp, link, dev, |
1976 | "PHY does not support 1000Mbps\n"); | |
54405cde | 1977 | goto out; |
bcf0bf90 | 1978 | } |
1da177e4 | 1979 | |
3577aa1b | 1980 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
1981 | ||
4da19633 | 1982 | rtl_writephy(tp, MII_ADVERTISE, auto_nego); |
1983 | rtl_writephy(tp, MII_CTRL1000, giga_ctrl); | |
3577aa1b | 1984 | } else { |
3577aa1b | 1985 | if (speed == SPEED_10) |
1986 | bmcr = 0; | |
1987 | else if (speed == SPEED_100) | |
1988 | bmcr = BMCR_SPEED100; | |
1989 | else | |
54405cde | 1990 | goto out; |
3577aa1b | 1991 | |
1992 | if (duplex == DUPLEX_FULL) | |
1993 | bmcr |= BMCR_FULLDPLX; | |
2584fbc3 RS |
1994 | } |
1995 | ||
4da19633 | 1996 | rtl_writephy(tp, MII_BMCR, bmcr); |
3577aa1b | 1997 | |
cecb5fd7 FR |
1998 | if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
1999 | tp->mac_version == RTL_GIGA_MAC_VER_03) { | |
3577aa1b | 2000 | if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { |
4da19633 | 2001 | rtl_writephy(tp, 0x17, 0x2138); |
2002 | rtl_writephy(tp, 0x0e, 0x0260); | |
3577aa1b | 2003 | } else { |
4da19633 | 2004 | rtl_writephy(tp, 0x17, 0x2108); |
2005 | rtl_writephy(tp, 0x0e, 0x0000); | |
3577aa1b | 2006 | } |
2007 | } | |
2008 | ||
54405cde ON |
2009 | rc = 0; |
2010 | out: | |
2011 | return rc; | |
1da177e4 LT |
2012 | } |
2013 | ||
2014 | static int rtl8169_set_speed(struct net_device *dev, | |
54405cde | 2015 | u8 autoneg, u16 speed, u8 duplex, u32 advertising) |
1da177e4 LT |
2016 | { |
2017 | struct rtl8169_private *tp = netdev_priv(dev); | |
2018 | int ret; | |
2019 | ||
54405cde | 2020 | ret = tp->set_speed(dev, autoneg, speed, duplex, advertising); |
4876cc1e FR |
2021 | if (ret < 0) |
2022 | goto out; | |
1da177e4 | 2023 | |
4876cc1e | 2024 | if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) && |
c4556975 CHL |
2025 | (advertising & ADVERTISED_1000baseT_Full) && |
2026 | !pci_is_pcie(tp->pci_dev)) { | |
1da177e4 | 2027 | mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
4876cc1e FR |
2028 | } |
2029 | out: | |
1da177e4 LT |
2030 | return ret; |
2031 | } | |
2032 | ||
c8f44aff MM |
2033 | static netdev_features_t rtl8169_fix_features(struct net_device *dev, |
2034 | netdev_features_t features) | |
1da177e4 | 2035 | { |
d58d46b5 FR |
2036 | struct rtl8169_private *tp = netdev_priv(dev); |
2037 | ||
2b7b4318 | 2038 | if (dev->mtu > TD_MSS_MAX) |
350fb32a | 2039 | features &= ~NETIF_F_ALL_TSO; |
1da177e4 | 2040 | |
d58d46b5 FR |
2041 | if (dev->mtu > JUMBO_1K && |
2042 | !rtl_chip_infos[tp->mac_version].jumbo_tx_csum) | |
2043 | features &= ~NETIF_F_IP_CSUM; | |
2044 | ||
350fb32a | 2045 | return features; |
1da177e4 LT |
2046 | } |
2047 | ||
da78dbff FR |
2048 | static void __rtl8169_set_features(struct net_device *dev, |
2049 | netdev_features_t features) | |
1da177e4 LT |
2050 | { |
2051 | struct rtl8169_private *tp = netdev_priv(dev); | |
da78dbff | 2052 | void __iomem *ioaddr = tp->mmio_addr; |
929a031d | 2053 | u32 rx_config; |
1da177e4 | 2054 | |
929a031d | 2055 | rx_config = RTL_R32(RxConfig); |
2056 | if (features & NETIF_F_RXALL) | |
2057 | rx_config |= (AcceptErr | AcceptRunt); | |
2058 | else | |
2059 | rx_config &= ~(AcceptErr | AcceptRunt); | |
1da177e4 | 2060 | |
929a031d | 2061 | RTL_W32(RxConfig, rx_config); |
350fb32a | 2062 | |
929a031d | 2063 | if (features & NETIF_F_RXCSUM) |
2064 | tp->cp_cmd |= RxChkSum; | |
2065 | else | |
2066 | tp->cp_cmd &= ~RxChkSum; | |
6bbe021d | 2067 | |
929a031d | 2068 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
2069 | tp->cp_cmd |= RxVlan; | |
2070 | else | |
2071 | tp->cp_cmd &= ~RxVlan; | |
2072 | ||
2073 | tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum); | |
2074 | ||
2075 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
2076 | RTL_R16(CPlusCmd); | |
da78dbff | 2077 | } |
1da177e4 | 2078 | |
da78dbff FR |
2079 | static int rtl8169_set_features(struct net_device *dev, |
2080 | netdev_features_t features) | |
2081 | { | |
2082 | struct rtl8169_private *tp = netdev_priv(dev); | |
2083 | ||
929a031d | 2084 | features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX; |
2085 | ||
da78dbff | 2086 | rtl_lock_work(tp); |
85911d71 | 2087 | if (features ^ dev->features) |
929a031d | 2088 | __rtl8169_set_features(dev, features); |
da78dbff | 2089 | rtl_unlock_work(tp); |
1da177e4 LT |
2090 | |
2091 | return 0; | |
2092 | } | |
2093 | ||
da78dbff | 2094 | |
810f4893 | 2095 | static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) |
1da177e4 | 2096 | { |
df8a39de JP |
2097 | return (skb_vlan_tag_present(skb)) ? |
2098 | TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; | |
1da177e4 LT |
2099 | } |
2100 | ||
7a8fc77b | 2101 | static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) |
1da177e4 LT |
2102 | { |
2103 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1da177e4 | 2104 | |
7a8fc77b | 2105 | if (opts2 & RxVlanTag) |
86a9bad3 | 2106 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); |
1da177e4 LT |
2107 | } |
2108 | ||
6fa1ba61 PR |
2109 | static int rtl8169_get_link_ksettings_tbi(struct net_device *dev, |
2110 | struct ethtool_link_ksettings *cmd) | |
1da177e4 LT |
2111 | { |
2112 | struct rtl8169_private *tp = netdev_priv(dev); | |
2113 | void __iomem *ioaddr = tp->mmio_addr; | |
2114 | u32 status; | |
6fa1ba61 | 2115 | u32 supported, advertising; |
1da177e4 | 2116 | |
6fa1ba61 | 2117 | supported = |
1da177e4 | 2118 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; |
6fa1ba61 | 2119 | cmd->base.port = PORT_FIBRE; |
1da177e4 LT |
2120 | |
2121 | status = RTL_R32(TBICSR); | |
6fa1ba61 PR |
2122 | advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; |
2123 | cmd->base.autoneg = !!(status & TBINwEnable); | |
1da177e4 | 2124 | |
6fa1ba61 PR |
2125 | cmd->base.speed = SPEED_1000; |
2126 | cmd->base.duplex = DUPLEX_FULL; /* Always set */ | |
2127 | ||
2128 | ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, | |
2129 | supported); | |
2130 | ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, | |
2131 | advertising); | |
ccdffb9a FR |
2132 | |
2133 | return 0; | |
1da177e4 LT |
2134 | } |
2135 | ||
6fa1ba61 PR |
2136 | static int rtl8169_get_link_ksettings_xmii(struct net_device *dev, |
2137 | struct ethtool_link_ksettings *cmd) | |
1da177e4 LT |
2138 | { |
2139 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 2140 | |
82c01a84 | 2141 | mii_ethtool_get_link_ksettings(&tp->mii, cmd); |
2142 | ||
2143 | return 0; | |
1da177e4 LT |
2144 | } |
2145 | ||
6fa1ba61 PR |
2146 | static int rtl8169_get_link_ksettings(struct net_device *dev, |
2147 | struct ethtool_link_ksettings *cmd) | |
1da177e4 LT |
2148 | { |
2149 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 2150 | int rc; |
1da177e4 | 2151 | |
da78dbff | 2152 | rtl_lock_work(tp); |
6fa1ba61 | 2153 | rc = tp->get_link_ksettings(dev, cmd); |
da78dbff | 2154 | rtl_unlock_work(tp); |
1da177e4 | 2155 | |
ccdffb9a | 2156 | return rc; |
1da177e4 LT |
2157 | } |
2158 | ||
9e77d7a5 TJ |
2159 | static int rtl8169_set_link_ksettings(struct net_device *dev, |
2160 | const struct ethtool_link_ksettings *cmd) | |
2161 | { | |
2162 | struct rtl8169_private *tp = netdev_priv(dev); | |
2163 | int rc; | |
2164 | u32 advertising; | |
2165 | ||
2166 | if (!ethtool_convert_link_mode_to_legacy_u32(&advertising, | |
2167 | cmd->link_modes.advertising)) | |
2168 | return -EINVAL; | |
2169 | ||
2170 | del_timer_sync(&tp->timer); | |
2171 | ||
2172 | rtl_lock_work(tp); | |
2173 | rc = rtl8169_set_speed(dev, cmd->base.autoneg, cmd->base.speed, | |
2174 | cmd->base.duplex, advertising); | |
2175 | rtl_unlock_work(tp); | |
2176 | ||
2177 | return rc; | |
2178 | } | |
2179 | ||
1da177e4 LT |
2180 | static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
2181 | void *p) | |
2182 | { | |
5b0384f4 | 2183 | struct rtl8169_private *tp = netdev_priv(dev); |
15edae91 PW |
2184 | u32 __iomem *data = tp->mmio_addr; |
2185 | u32 *dw = p; | |
2186 | int i; | |
1da177e4 | 2187 | |
da78dbff | 2188 | rtl_lock_work(tp); |
15edae91 PW |
2189 | for (i = 0; i < R8169_REGS_SIZE; i += 4) |
2190 | memcpy_fromio(dw++, data++, 4); | |
da78dbff | 2191 | rtl_unlock_work(tp); |
1da177e4 LT |
2192 | } |
2193 | ||
b57b7e5a SH |
2194 | static u32 rtl8169_get_msglevel(struct net_device *dev) |
2195 | { | |
2196 | struct rtl8169_private *tp = netdev_priv(dev); | |
2197 | ||
2198 | return tp->msg_enable; | |
2199 | } | |
2200 | ||
2201 | static void rtl8169_set_msglevel(struct net_device *dev, u32 value) | |
2202 | { | |
2203 | struct rtl8169_private *tp = netdev_priv(dev); | |
2204 | ||
2205 | tp->msg_enable = value; | |
2206 | } | |
2207 | ||
d4a3a0fc SH |
2208 | static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
2209 | "tx_packets", | |
2210 | "rx_packets", | |
2211 | "tx_errors", | |
2212 | "rx_errors", | |
2213 | "rx_missed", | |
2214 | "align_errors", | |
2215 | "tx_single_collisions", | |
2216 | "tx_multi_collisions", | |
2217 | "unicast", | |
2218 | "broadcast", | |
2219 | "multicast", | |
2220 | "tx_aborted", | |
2221 | "tx_underrun", | |
2222 | }; | |
2223 | ||
b9f2c044 | 2224 | static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
d4a3a0fc | 2225 | { |
b9f2c044 JG |
2226 | switch (sset) { |
2227 | case ETH_SS_STATS: | |
2228 | return ARRAY_SIZE(rtl8169_gstrings); | |
2229 | default: | |
2230 | return -EOPNOTSUPP; | |
2231 | } | |
d4a3a0fc SH |
2232 | } |
2233 | ||
42020320 | 2234 | DECLARE_RTL_COND(rtl_counters_cond) |
6e85d5ad | 2235 | { |
6e85d5ad | 2236 | void __iomem *ioaddr = tp->mmio_addr; |
6e85d5ad | 2237 | |
42020320 | 2238 | return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump); |
6e85d5ad CV |
2239 | } |
2240 | ||
42020320 | 2241 | static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd) |
6e85d5ad CV |
2242 | { |
2243 | struct rtl8169_private *tp = netdev_priv(dev); | |
2244 | void __iomem *ioaddr = tp->mmio_addr; | |
42020320 CV |
2245 | dma_addr_t paddr = tp->counters_phys_addr; |
2246 | u32 cmd; | |
2247 | bool ret; | |
6e85d5ad | 2248 | |
42020320 CV |
2249 | RTL_W32(CounterAddrHigh, (u64)paddr >> 32); |
2250 | cmd = (u64)paddr & DMA_BIT_MASK(32); | |
2251 | RTL_W32(CounterAddrLow, cmd); | |
2252 | RTL_W32(CounterAddrLow, cmd | counter_cmd); | |
6e85d5ad | 2253 | |
42020320 | 2254 | ret = rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); |
6e85d5ad | 2255 | |
42020320 CV |
2256 | RTL_W32(CounterAddrLow, 0); |
2257 | RTL_W32(CounterAddrHigh, 0); | |
6e85d5ad | 2258 | |
42020320 | 2259 | return ret; |
6e85d5ad CV |
2260 | } |
2261 | ||
2262 | static bool rtl8169_reset_counters(struct net_device *dev) | |
2263 | { | |
2264 | struct rtl8169_private *tp = netdev_priv(dev); | |
6e85d5ad CV |
2265 | |
2266 | /* | |
2267 | * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the | |
2268 | * tally counters. | |
2269 | */ | |
2270 | if (tp->mac_version < RTL_GIGA_MAC_VER_19) | |
2271 | return true; | |
2272 | ||
42020320 | 2273 | return rtl8169_do_counters(dev, CounterReset); |
ffc46952 FR |
2274 | } |
2275 | ||
6e85d5ad | 2276 | static bool rtl8169_update_counters(struct net_device *dev) |
d4a3a0fc SH |
2277 | { |
2278 | struct rtl8169_private *tp = netdev_priv(dev); | |
2279 | void __iomem *ioaddr = tp->mmio_addr; | |
d4a3a0fc | 2280 | |
355423d0 IV |
2281 | /* |
2282 | * Some chips are unable to dump tally counters when the receiver | |
2283 | * is disabled. | |
2284 | */ | |
2285 | if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) | |
6e85d5ad | 2286 | return true; |
d4a3a0fc | 2287 | |
42020320 | 2288 | return rtl8169_do_counters(dev, CounterDump); |
6e85d5ad CV |
2289 | } |
2290 | ||
2291 | static bool rtl8169_init_counter_offsets(struct net_device *dev) | |
2292 | { | |
2293 | struct rtl8169_private *tp = netdev_priv(dev); | |
42020320 | 2294 | struct rtl8169_counters *counters = tp->counters; |
6e85d5ad CV |
2295 | bool ret = false; |
2296 | ||
2297 | /* | |
2298 | * rtl8169_init_counter_offsets is called from rtl_open. On chip | |
2299 | * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only | |
2300 | * reset by a power cycle, while the counter values collected by the | |
2301 | * driver are reset at every driver unload/load cycle. | |
2302 | * | |
2303 | * To make sure the HW values returned by @get_stats64 match the SW | |
2304 | * values, we collect the initial values at first open(*) and use them | |
2305 | * as offsets to normalize the values returned by @get_stats64. | |
2306 | * | |
2307 | * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one | |
2308 | * for the reason stated in rtl8169_update_counters; CmdRxEnb is only | |
2309 | * set at open time by rtl_hw_start. | |
2310 | */ | |
2311 | ||
2312 | if (tp->tc_offset.inited) | |
2313 | return true; | |
2314 | ||
2315 | /* If both, reset and update fail, propagate to caller. */ | |
2316 | if (rtl8169_reset_counters(dev)) | |
2317 | ret = true; | |
2318 | ||
2319 | if (rtl8169_update_counters(dev)) | |
2320 | ret = true; | |
2321 | ||
42020320 CV |
2322 | tp->tc_offset.tx_errors = counters->tx_errors; |
2323 | tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; | |
2324 | tp->tc_offset.tx_aborted = counters->tx_aborted; | |
6e85d5ad CV |
2325 | tp->tc_offset.inited = true; |
2326 | ||
2327 | return ret; | |
d4a3a0fc SH |
2328 | } |
2329 | ||
355423d0 IV |
2330 | static void rtl8169_get_ethtool_stats(struct net_device *dev, |
2331 | struct ethtool_stats *stats, u64 *data) | |
2332 | { | |
2333 | struct rtl8169_private *tp = netdev_priv(dev); | |
e0636236 | 2334 | struct device *d = &tp->pci_dev->dev; |
42020320 | 2335 | struct rtl8169_counters *counters = tp->counters; |
355423d0 IV |
2336 | |
2337 | ASSERT_RTNL(); | |
2338 | ||
e0636236 CHL |
2339 | pm_runtime_get_noresume(d); |
2340 | ||
2341 | if (pm_runtime_active(d)) | |
2342 | rtl8169_update_counters(dev); | |
2343 | ||
2344 | pm_runtime_put_noidle(d); | |
355423d0 | 2345 | |
42020320 CV |
2346 | data[0] = le64_to_cpu(counters->tx_packets); |
2347 | data[1] = le64_to_cpu(counters->rx_packets); | |
2348 | data[2] = le64_to_cpu(counters->tx_errors); | |
2349 | data[3] = le32_to_cpu(counters->rx_errors); | |
2350 | data[4] = le16_to_cpu(counters->rx_missed); | |
2351 | data[5] = le16_to_cpu(counters->align_errors); | |
2352 | data[6] = le32_to_cpu(counters->tx_one_collision); | |
2353 | data[7] = le32_to_cpu(counters->tx_multi_collision); | |
2354 | data[8] = le64_to_cpu(counters->rx_unicast); | |
2355 | data[9] = le64_to_cpu(counters->rx_broadcast); | |
2356 | data[10] = le32_to_cpu(counters->rx_multicast); | |
2357 | data[11] = le16_to_cpu(counters->tx_aborted); | |
2358 | data[12] = le16_to_cpu(counters->tx_underun); | |
355423d0 IV |
2359 | } |
2360 | ||
d4a3a0fc SH |
2361 | static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
2362 | { | |
2363 | switch(stringset) { | |
2364 | case ETH_SS_STATS: | |
2365 | memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); | |
2366 | break; | |
2367 | } | |
2368 | } | |
2369 | ||
f0903ea3 FF |
2370 | static int rtl8169_nway_reset(struct net_device *dev) |
2371 | { | |
2372 | struct rtl8169_private *tp = netdev_priv(dev); | |
2373 | ||
2374 | return mii_nway_restart(&tp->mii); | |
2375 | } | |
2376 | ||
50970831 FR |
2377 | /* |
2378 | * Interrupt coalescing | |
2379 | * | |
2380 | * > 1 - the availability of the IntrMitigate (0xe2) register through the | |
2381 | * > 8169, 8168 and 810x line of chipsets | |
2382 | * | |
2383 | * 8169, 8168, and 8136(810x) serial chipsets support it. | |
2384 | * | |
2385 | * > 2 - the Tx timer unit at gigabit speed | |
2386 | * | |
2387 | * The unit of the timer depends on both the speed and the setting of CPlusCmd | |
2388 | * (0xe0) bit 1 and bit 0. | |
2389 | * | |
2390 | * For 8169 | |
2391 | * bit[1:0] \ speed 1000M 100M 10M | |
2392 | * 0 0 320ns 2.56us 40.96us | |
2393 | * 0 1 2.56us 20.48us 327.7us | |
2394 | * 1 0 5.12us 40.96us 655.4us | |
2395 | * 1 1 10.24us 81.92us 1.31ms | |
2396 | * | |
2397 | * For the other | |
2398 | * bit[1:0] \ speed 1000M 100M 10M | |
2399 | * 0 0 5us 2.56us 40.96us | |
2400 | * 0 1 40us 20.48us 327.7us | |
2401 | * 1 0 80us 40.96us 655.4us | |
2402 | * 1 1 160us 81.92us 1.31ms | |
2403 | */ | |
2404 | ||
2405 | /* rx/tx scale factors for one particular CPlusCmd[0:1] value */ | |
2406 | struct rtl_coalesce_scale { | |
2407 | /* Rx / Tx */ | |
2408 | u32 nsecs[2]; | |
2409 | }; | |
2410 | ||
2411 | /* rx/tx scale factors for all CPlusCmd[0:1] cases */ | |
2412 | struct rtl_coalesce_info { | |
2413 | u32 speed; | |
2414 | struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */ | |
2415 | }; | |
2416 | ||
2417 | /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */ | |
2418 | #define rxtx_x1822(r, t) { \ | |
2419 | {{(r), (t)}}, \ | |
2420 | {{(r)*8, (t)*8}}, \ | |
2421 | {{(r)*8*2, (t)*8*2}}, \ | |
2422 | {{(r)*8*2*2, (t)*8*2*2}}, \ | |
2423 | } | |
2424 | static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { | |
2425 | /* speed delays: rx00 tx00 */ | |
2426 | { SPEED_10, rxtx_x1822(40960, 40960) }, | |
2427 | { SPEED_100, rxtx_x1822( 2560, 2560) }, | |
2428 | { SPEED_1000, rxtx_x1822( 320, 320) }, | |
2429 | { 0 }, | |
2430 | }; | |
2431 | ||
2432 | static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { | |
2433 | /* speed delays: rx00 tx00 */ | |
2434 | { SPEED_10, rxtx_x1822(40960, 40960) }, | |
2435 | { SPEED_100, rxtx_x1822( 2560, 2560) }, | |
2436 | { SPEED_1000, rxtx_x1822( 5000, 5000) }, | |
2437 | { 0 }, | |
2438 | }; | |
2439 | #undef rxtx_x1822 | |
2440 | ||
2441 | /* get rx/tx scale vector corresponding to current speed */ | |
2442 | static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev) | |
2443 | { | |
2444 | struct rtl8169_private *tp = netdev_priv(dev); | |
2445 | struct ethtool_link_ksettings ecmd; | |
2446 | const struct rtl_coalesce_info *ci; | |
2447 | int rc; | |
2448 | ||
2449 | rc = rtl8169_get_link_ksettings(dev, &ecmd); | |
2450 | if (rc < 0) | |
2451 | return ERR_PTR(rc); | |
2452 | ||
2453 | for (ci = tp->coalesce_info; ci->speed != 0; ci++) { | |
2454 | if (ecmd.base.speed == ci->speed) { | |
2455 | return ci; | |
2456 | } | |
2457 | } | |
2458 | ||
2459 | return ERR_PTR(-ELNRNG); | |
2460 | } | |
2461 | ||
2462 | static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
2463 | { | |
2464 | struct rtl8169_private *tp = netdev_priv(dev); | |
2465 | void __iomem *ioaddr = tp->mmio_addr; | |
2466 | const struct rtl_coalesce_info *ci; | |
2467 | const struct rtl_coalesce_scale *scale; | |
2468 | struct { | |
2469 | u32 *max_frames; | |
2470 | u32 *usecs; | |
2471 | } coal_settings [] = { | |
2472 | { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs }, | |
2473 | { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs } | |
2474 | }, *p = coal_settings; | |
2475 | int i; | |
2476 | u16 w; | |
2477 | ||
2478 | memset(ec, 0, sizeof(*ec)); | |
2479 | ||
2480 | /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ | |
2481 | ci = rtl_coalesce_info(dev); | |
2482 | if (IS_ERR(ci)) | |
2483 | return PTR_ERR(ci); | |
2484 | ||
2485 | scale = &ci->scalev[RTL_R16(CPlusCmd) & 3]; | |
2486 | ||
2487 | /* read IntrMitigate and adjust according to scale */ | |
2488 | for (w = RTL_R16(IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) { | |
2489 | *p->max_frames = (w & RTL_COALESCE_MASK) << 2; | |
2490 | w >>= RTL_COALESCE_SHIFT; | |
2491 | *p->usecs = w & RTL_COALESCE_MASK; | |
2492 | } | |
2493 | ||
2494 | for (i = 0; i < 2; i++) { | |
2495 | p = coal_settings + i; | |
2496 | *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000; | |
2497 | ||
2498 | /* | |
2499 | * ethtool_coalesce says it is illegal to set both usecs and | |
2500 | * max_frames to 0. | |
2501 | */ | |
2502 | if (!*p->usecs && !*p->max_frames) | |
2503 | *p->max_frames = 1; | |
2504 | } | |
2505 | ||
2506 | return 0; | |
2507 | } | |
2508 | ||
2509 | /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */ | |
2510 | static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale( | |
2511 | struct net_device *dev, u32 nsec, u16 *cp01) | |
2512 | { | |
2513 | const struct rtl_coalesce_info *ci; | |
2514 | u16 i; | |
2515 | ||
2516 | ci = rtl_coalesce_info(dev); | |
2517 | if (IS_ERR(ci)) | |
2518 | return ERR_CAST(ci); | |
2519 | ||
2520 | for (i = 0; i < 4; i++) { | |
2521 | u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0], | |
2522 | ci->scalev[i].nsecs[1]); | |
2523 | if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) { | |
2524 | *cp01 = i; | |
2525 | return &ci->scalev[i]; | |
2526 | } | |
2527 | } | |
2528 | ||
2529 | return ERR_PTR(-EINVAL); | |
2530 | } | |
2531 | ||
2532 | static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
2533 | { | |
2534 | struct rtl8169_private *tp = netdev_priv(dev); | |
2535 | void __iomem *ioaddr = tp->mmio_addr; | |
2536 | const struct rtl_coalesce_scale *scale; | |
2537 | struct { | |
2538 | u32 frames; | |
2539 | u32 usecs; | |
2540 | } coal_settings [] = { | |
2541 | { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs }, | |
2542 | { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs } | |
2543 | }, *p = coal_settings; | |
2544 | u16 w = 0, cp01; | |
2545 | int i; | |
2546 | ||
2547 | scale = rtl_coalesce_choose_scale(dev, | |
2548 | max(p[0].usecs, p[1].usecs) * 1000, &cp01); | |
2549 | if (IS_ERR(scale)) | |
2550 | return PTR_ERR(scale); | |
2551 | ||
2552 | for (i = 0; i < 2; i++, p++) { | |
2553 | u32 units; | |
2554 | ||
2555 | /* | |
2556 | * accept max_frames=1 we returned in rtl_get_coalesce. | |
2557 | * accept it not only when usecs=0 because of e.g. the following scenario: | |
2558 | * | |
2559 | * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) | |
2560 | * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 | |
2561 | * - then user does `ethtool -C eth0 rx-usecs 100` | |
2562 | * | |
2563 | * since ethtool sends to kernel whole ethtool_coalesce | |
2564 | * settings, if we do not handle rx_usecs=!0, rx_frames=1 | |
2565 | * we'll reject it below in `frames % 4 != 0`. | |
2566 | */ | |
2567 | if (p->frames == 1) { | |
2568 | p->frames = 0; | |
2569 | } | |
2570 | ||
2571 | units = p->usecs * 1000 / scale->nsecs[i]; | |
2572 | if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4) | |
2573 | return -EINVAL; | |
2574 | ||
2575 | w <<= RTL_COALESCE_SHIFT; | |
2576 | w |= units; | |
2577 | w <<= RTL_COALESCE_SHIFT; | |
2578 | w |= p->frames >> 2; | |
2579 | } | |
2580 | ||
2581 | rtl_lock_work(tp); | |
2582 | ||
2583 | RTL_W16(IntrMitigate, swab16(w)); | |
2584 | ||
2585 | tp->cp_cmd = (tp->cp_cmd & ~3) | cp01; | |
2586 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
2587 | RTL_R16(CPlusCmd); | |
2588 | ||
2589 | rtl_unlock_work(tp); | |
2590 | ||
2591 | return 0; | |
2592 | } | |
2593 | ||
7282d491 | 2594 | static const struct ethtool_ops rtl8169_ethtool_ops = { |
1da177e4 LT |
2595 | .get_drvinfo = rtl8169_get_drvinfo, |
2596 | .get_regs_len = rtl8169_get_regs_len, | |
2597 | .get_link = ethtool_op_get_link, | |
50970831 FR |
2598 | .get_coalesce = rtl_get_coalesce, |
2599 | .set_coalesce = rtl_set_coalesce, | |
b57b7e5a SH |
2600 | .get_msglevel = rtl8169_get_msglevel, |
2601 | .set_msglevel = rtl8169_set_msglevel, | |
1da177e4 | 2602 | .get_regs = rtl8169_get_regs, |
61a4dcc2 FR |
2603 | .get_wol = rtl8169_get_wol, |
2604 | .set_wol = rtl8169_set_wol, | |
d4a3a0fc | 2605 | .get_strings = rtl8169_get_strings, |
b9f2c044 | 2606 | .get_sset_count = rtl8169_get_sset_count, |
d4a3a0fc | 2607 | .get_ethtool_stats = rtl8169_get_ethtool_stats, |
e1593bb1 | 2608 | .get_ts_info = ethtool_op_get_ts_info, |
f0903ea3 | 2609 | .nway_reset = rtl8169_nway_reset, |
6fa1ba61 | 2610 | .get_link_ksettings = rtl8169_get_link_ksettings, |
9e77d7a5 | 2611 | .set_link_ksettings = rtl8169_set_link_ksettings, |
1da177e4 LT |
2612 | }; |
2613 | ||
07d3f51f | 2614 | static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
5d320a20 | 2615 | struct net_device *dev, u8 default_version) |
1da177e4 | 2616 | { |
5d320a20 | 2617 | void __iomem *ioaddr = tp->mmio_addr; |
0e485150 FR |
2618 | /* |
2619 | * The driver currently handles the 8168Bf and the 8168Be identically | |
2620 | * but they can be identified more specifically through the test below | |
2621 | * if needed: | |
2622 | * | |
2623 | * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be | |
0127215c FR |
2624 | * |
2625 | * Same thing for the 8101Eb and the 8101Ec: | |
2626 | * | |
2627 | * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec | |
0e485150 | 2628 | */ |
3744100e | 2629 | static const struct rtl_mac_info { |
1da177e4 | 2630 | u32 mask; |
e3cf0cc0 | 2631 | u32 val; |
1da177e4 LT |
2632 | int mac_version; |
2633 | } mac_info[] = { | |
935e2218 CHL |
2634 | /* 8168EP family. */ |
2635 | { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 }, | |
2636 | { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 }, | |
2637 | { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 }, | |
2638 | ||
6e1d0b89 CHL |
2639 | /* 8168H family. */ |
2640 | { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 }, | |
2641 | { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 }, | |
2642 | ||
c558386b | 2643 | /* 8168G family. */ |
45dd95c4 | 2644 | { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 }, |
57538c4a | 2645 | { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 }, |
c558386b HW |
2646 | { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 }, |
2647 | { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 }, | |
2648 | ||
c2218925 | 2649 | /* 8168F family. */ |
b3d7b2f2 | 2650 | { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 }, |
c2218925 HW |
2651 | { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 }, |
2652 | { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 }, | |
2653 | ||
01dc7fec | 2654 | /* 8168E family. */ |
70090424 | 2655 | { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 }, |
01dc7fec | 2656 | { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 }, |
2657 | { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 }, | |
2658 | { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 }, | |
2659 | ||
5b538df9 | 2660 | /* 8168D family. */ |
daf9df6d | 2661 | { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, |
2662 | { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, | |
daf9df6d | 2663 | { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, |
5b538df9 | 2664 | |
e6de30d6 | 2665 | /* 8168DP family. */ |
2666 | { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 }, | |
2667 | { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 }, | |
4804b3b3 | 2668 | { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 }, |
e6de30d6 | 2669 | |
ef808d50 | 2670 | /* 8168C family. */ |
17c99297 | 2671 | { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, |
ef3386f0 | 2672 | { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
ef808d50 | 2673 | { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
7f3e3d3a | 2674 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
e3cf0cc0 FR |
2675 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
2676 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, | |
197ff761 | 2677 | { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
6fb07058 | 2678 | { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
ef808d50 | 2679 | { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
e3cf0cc0 FR |
2680 | |
2681 | /* 8168B family. */ | |
2682 | { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, | |
2683 | { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, | |
2684 | { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, | |
2685 | { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, | |
2686 | ||
2687 | /* 8101 family. */ | |
5598bfe5 HW |
2688 | { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 }, |
2689 | { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 }, | |
7e18dca1 | 2690 | { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 }, |
36a0e6c2 | 2691 | { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 }, |
5a5e4443 HW |
2692 | { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 }, |
2693 | { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, | |
2694 | { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 }, | |
2857ffb7 FR |
2695 | { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
2696 | { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, | |
2697 | { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, | |
2698 | { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, | |
2699 | { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, | |
2700 | { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, | |
e3cf0cc0 | 2701 | { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
2857ffb7 | 2702 | { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
e3cf0cc0 | 2703 | { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
2857ffb7 FR |
2704 | { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
2705 | { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, | |
e3cf0cc0 FR |
2706 | { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
2707 | /* FIXME: where did these entries come from ? -- FR */ | |
2708 | { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, | |
2709 | { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, | |
2710 | ||
2711 | /* 8110 family. */ | |
2712 | { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, | |
2713 | { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, | |
2714 | { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, | |
2715 | { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, | |
2716 | { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, | |
2717 | { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, | |
2718 | ||
f21b75e9 JD |
2719 | /* Catch-all */ |
2720 | { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } | |
3744100e FR |
2721 | }; |
2722 | const struct rtl_mac_info *p = mac_info; | |
1da177e4 LT |
2723 | u32 reg; |
2724 | ||
e3cf0cc0 FR |
2725 | reg = RTL_R32(TxConfig); |
2726 | while ((reg & p->mask) != p->val) | |
1da177e4 LT |
2727 | p++; |
2728 | tp->mac_version = p->mac_version; | |
5d320a20 FR |
2729 | |
2730 | if (tp->mac_version == RTL_GIGA_MAC_NONE) { | |
2731 | netif_notice(tp, probe, dev, | |
2732 | "unknown MAC, using family default\n"); | |
2733 | tp->mac_version = default_version; | |
58152cd4 | 2734 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) { |
2735 | tp->mac_version = tp->mii.supports_gmii ? | |
2736 | RTL_GIGA_MAC_VER_42 : | |
2737 | RTL_GIGA_MAC_VER_43; | |
6e1d0b89 CHL |
2738 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) { |
2739 | tp->mac_version = tp->mii.supports_gmii ? | |
2740 | RTL_GIGA_MAC_VER_45 : | |
2741 | RTL_GIGA_MAC_VER_47; | |
2742 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) { | |
2743 | tp->mac_version = tp->mii.supports_gmii ? | |
2744 | RTL_GIGA_MAC_VER_46 : | |
2745 | RTL_GIGA_MAC_VER_48; | |
5d320a20 | 2746 | } |
1da177e4 LT |
2747 | } |
2748 | ||
2749 | static void rtl8169_print_mac_version(struct rtl8169_private *tp) | |
2750 | { | |
bcf0bf90 | 2751 | dprintk("mac_version = 0x%02x\n", tp->mac_version); |
1da177e4 LT |
2752 | } |
2753 | ||
867763c1 FR |
2754 | struct phy_reg { |
2755 | u16 reg; | |
2756 | u16 val; | |
2757 | }; | |
2758 | ||
4da19633 | 2759 | static void rtl_writephy_batch(struct rtl8169_private *tp, |
2760 | const struct phy_reg *regs, int len) | |
867763c1 FR |
2761 | { |
2762 | while (len-- > 0) { | |
4da19633 | 2763 | rtl_writephy(tp, regs->reg, regs->val); |
867763c1 FR |
2764 | regs++; |
2765 | } | |
2766 | } | |
2767 | ||
bca03d5f | 2768 | #define PHY_READ 0x00000000 |
2769 | #define PHY_DATA_OR 0x10000000 | |
2770 | #define PHY_DATA_AND 0x20000000 | |
2771 | #define PHY_BJMPN 0x30000000 | |
eee3786f | 2772 | #define PHY_MDIO_CHG 0x40000000 |
bca03d5f | 2773 | #define PHY_CLEAR_READCOUNT 0x70000000 |
2774 | #define PHY_WRITE 0x80000000 | |
2775 | #define PHY_READCOUNT_EQ_SKIP 0x90000000 | |
2776 | #define PHY_COMP_EQ_SKIPN 0xa0000000 | |
2777 | #define PHY_COMP_NEQ_SKIPN 0xb0000000 | |
2778 | #define PHY_WRITE_PREVIOUS 0xc0000000 | |
2779 | #define PHY_SKIPN 0xd0000000 | |
2780 | #define PHY_DELAY_MS 0xe0000000 | |
bca03d5f | 2781 | |
960aee6c HW |
2782 | struct fw_info { |
2783 | u32 magic; | |
2784 | char version[RTL_VER_SIZE]; | |
2785 | __le32 fw_start; | |
2786 | __le32 fw_len; | |
2787 | u8 chksum; | |
2788 | } __packed; | |
2789 | ||
1c361efb FR |
2790 | #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code)) |
2791 | ||
2792 | static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) | |
bca03d5f | 2793 | { |
b6ffd97f | 2794 | const struct firmware *fw = rtl_fw->fw; |
960aee6c | 2795 | struct fw_info *fw_info = (struct fw_info *)fw->data; |
1c361efb FR |
2796 | struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; |
2797 | char *version = rtl_fw->version; | |
2798 | bool rc = false; | |
2799 | ||
2800 | if (fw->size < FW_OPCODE_SIZE) | |
2801 | goto out; | |
960aee6c HW |
2802 | |
2803 | if (!fw_info->magic) { | |
2804 | size_t i, size, start; | |
2805 | u8 checksum = 0; | |
2806 | ||
2807 | if (fw->size < sizeof(*fw_info)) | |
2808 | goto out; | |
2809 | ||
2810 | for (i = 0; i < fw->size; i++) | |
2811 | checksum += fw->data[i]; | |
2812 | if (checksum != 0) | |
2813 | goto out; | |
2814 | ||
2815 | start = le32_to_cpu(fw_info->fw_start); | |
2816 | if (start > fw->size) | |
2817 | goto out; | |
2818 | ||
2819 | size = le32_to_cpu(fw_info->fw_len); | |
2820 | if (size > (fw->size - start) / FW_OPCODE_SIZE) | |
2821 | goto out; | |
2822 | ||
2823 | memcpy(version, fw_info->version, RTL_VER_SIZE); | |
2824 | ||
2825 | pa->code = (__le32 *)(fw->data + start); | |
2826 | pa->size = size; | |
2827 | } else { | |
1c361efb FR |
2828 | if (fw->size % FW_OPCODE_SIZE) |
2829 | goto out; | |
2830 | ||
2831 | strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE); | |
2832 | ||
2833 | pa->code = (__le32 *)fw->data; | |
2834 | pa->size = fw->size / FW_OPCODE_SIZE; | |
2835 | } | |
2836 | version[RTL_VER_SIZE - 1] = 0; | |
2837 | ||
2838 | rc = true; | |
2839 | out: | |
2840 | return rc; | |
2841 | } | |
2842 | ||
fd112f2e FR |
2843 | static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev, |
2844 | struct rtl_fw_phy_action *pa) | |
1c361efb | 2845 | { |
fd112f2e | 2846 | bool rc = false; |
1c361efb | 2847 | size_t index; |
bca03d5f | 2848 | |
1c361efb FR |
2849 | for (index = 0; index < pa->size; index++) { |
2850 | u32 action = le32_to_cpu(pa->code[index]); | |
42b82dc1 | 2851 | u32 regno = (action & 0x0fff0000) >> 16; |
bca03d5f | 2852 | |
42b82dc1 | 2853 | switch(action & 0xf0000000) { |
2854 | case PHY_READ: | |
2855 | case PHY_DATA_OR: | |
2856 | case PHY_DATA_AND: | |
eee3786f | 2857 | case PHY_MDIO_CHG: |
42b82dc1 | 2858 | case PHY_CLEAR_READCOUNT: |
2859 | case PHY_WRITE: | |
2860 | case PHY_WRITE_PREVIOUS: | |
2861 | case PHY_DELAY_MS: | |
2862 | break; | |
2863 | ||
2864 | case PHY_BJMPN: | |
2865 | if (regno > index) { | |
fd112f2e | 2866 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2867 | "Out of range of firmware\n"); |
fd112f2e | 2868 | goto out; |
42b82dc1 | 2869 | } |
2870 | break; | |
2871 | case PHY_READCOUNT_EQ_SKIP: | |
1c361efb | 2872 | if (index + 2 >= pa->size) { |
fd112f2e | 2873 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2874 | "Out of range of firmware\n"); |
fd112f2e | 2875 | goto out; |
42b82dc1 | 2876 | } |
2877 | break; | |
2878 | case PHY_COMP_EQ_SKIPN: | |
2879 | case PHY_COMP_NEQ_SKIPN: | |
2880 | case PHY_SKIPN: | |
1c361efb | 2881 | if (index + 1 + regno >= pa->size) { |
fd112f2e | 2882 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2883 | "Out of range of firmware\n"); |
fd112f2e | 2884 | goto out; |
42b82dc1 | 2885 | } |
bca03d5f | 2886 | break; |
2887 | ||
42b82dc1 | 2888 | default: |
fd112f2e | 2889 | netif_err(tp, ifup, tp->dev, |
42b82dc1 | 2890 | "Invalid action 0x%08x\n", action); |
fd112f2e | 2891 | goto out; |
bca03d5f | 2892 | } |
2893 | } | |
fd112f2e FR |
2894 | rc = true; |
2895 | out: | |
2896 | return rc; | |
2897 | } | |
bca03d5f | 2898 | |
fd112f2e FR |
2899 | static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
2900 | { | |
2901 | struct net_device *dev = tp->dev; | |
2902 | int rc = -EINVAL; | |
2903 | ||
2904 | if (!rtl_fw_format_ok(tp, rtl_fw)) { | |
5c2d2b14 | 2905 | netif_err(tp, ifup, dev, "invalid firmware\n"); |
fd112f2e FR |
2906 | goto out; |
2907 | } | |
2908 | ||
2909 | if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action)) | |
2910 | rc = 0; | |
2911 | out: | |
2912 | return rc; | |
2913 | } | |
2914 | ||
2915 | static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) | |
2916 | { | |
2917 | struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; | |
eee3786f | 2918 | struct mdio_ops org, *ops = &tp->mdio_ops; |
fd112f2e FR |
2919 | u32 predata, count; |
2920 | size_t index; | |
2921 | ||
2922 | predata = count = 0; | |
eee3786f | 2923 | org.write = ops->write; |
2924 | org.read = ops->read; | |
42b82dc1 | 2925 | |
1c361efb FR |
2926 | for (index = 0; index < pa->size; ) { |
2927 | u32 action = le32_to_cpu(pa->code[index]); | |
bca03d5f | 2928 | u32 data = action & 0x0000ffff; |
42b82dc1 | 2929 | u32 regno = (action & 0x0fff0000) >> 16; |
2930 | ||
2931 | if (!action) | |
2932 | break; | |
bca03d5f | 2933 | |
2934 | switch(action & 0xf0000000) { | |
42b82dc1 | 2935 | case PHY_READ: |
2936 | predata = rtl_readphy(tp, regno); | |
2937 | count++; | |
2938 | index++; | |
2939 | break; | |
2940 | case PHY_DATA_OR: | |
2941 | predata |= data; | |
2942 | index++; | |
2943 | break; | |
2944 | case PHY_DATA_AND: | |
2945 | predata &= data; | |
2946 | index++; | |
2947 | break; | |
2948 | case PHY_BJMPN: | |
2949 | index -= regno; | |
2950 | break; | |
eee3786f | 2951 | case PHY_MDIO_CHG: |
2952 | if (data == 0) { | |
2953 | ops->write = org.write; | |
2954 | ops->read = org.read; | |
2955 | } else if (data == 1) { | |
2956 | ops->write = mac_mcu_write; | |
2957 | ops->read = mac_mcu_read; | |
2958 | } | |
2959 | ||
42b82dc1 | 2960 | index++; |
2961 | break; | |
2962 | case PHY_CLEAR_READCOUNT: | |
2963 | count = 0; | |
2964 | index++; | |
2965 | break; | |
bca03d5f | 2966 | case PHY_WRITE: |
42b82dc1 | 2967 | rtl_writephy(tp, regno, data); |
2968 | index++; | |
2969 | break; | |
2970 | case PHY_READCOUNT_EQ_SKIP: | |
cecb5fd7 | 2971 | index += (count == data) ? 2 : 1; |
bca03d5f | 2972 | break; |
42b82dc1 | 2973 | case PHY_COMP_EQ_SKIPN: |
2974 | if (predata == data) | |
2975 | index += regno; | |
2976 | index++; | |
2977 | break; | |
2978 | case PHY_COMP_NEQ_SKIPN: | |
2979 | if (predata != data) | |
2980 | index += regno; | |
2981 | index++; | |
2982 | break; | |
2983 | case PHY_WRITE_PREVIOUS: | |
2984 | rtl_writephy(tp, regno, predata); | |
2985 | index++; | |
2986 | break; | |
2987 | case PHY_SKIPN: | |
2988 | index += regno + 1; | |
2989 | break; | |
2990 | case PHY_DELAY_MS: | |
2991 | mdelay(data); | |
2992 | index++; | |
2993 | break; | |
2994 | ||
bca03d5f | 2995 | default: |
2996 | BUG(); | |
2997 | } | |
2998 | } | |
eee3786f | 2999 | |
3000 | ops->write = org.write; | |
3001 | ops->read = org.read; | |
bca03d5f | 3002 | } |
3003 | ||
f1e02ed1 | 3004 | static void rtl_release_firmware(struct rtl8169_private *tp) |
3005 | { | |
b6ffd97f FR |
3006 | if (!IS_ERR_OR_NULL(tp->rtl_fw)) { |
3007 | release_firmware(tp->rtl_fw->fw); | |
3008 | kfree(tp->rtl_fw); | |
3009 | } | |
3010 | tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; | |
f1e02ed1 | 3011 | } |
3012 | ||
953a12cc | 3013 | static void rtl_apply_firmware(struct rtl8169_private *tp) |
f1e02ed1 | 3014 | { |
b6ffd97f | 3015 | struct rtl_fw *rtl_fw = tp->rtl_fw; |
f1e02ed1 | 3016 | |
3017 | /* TODO: release firmware once rtl_phy_write_fw signals failures. */ | |
eef63cc1 | 3018 | if (!IS_ERR_OR_NULL(rtl_fw)) |
b6ffd97f | 3019 | rtl_phy_write_fw(tp, rtl_fw); |
953a12cc FR |
3020 | } |
3021 | ||
3022 | static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) | |
3023 | { | |
3024 | if (rtl_readphy(tp, reg) != val) | |
3025 | netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); | |
3026 | else | |
3027 | rtl_apply_firmware(tp); | |
f1e02ed1 | 3028 | } |
3029 | ||
4da19633 | 3030 | static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) |
1da177e4 | 3031 | { |
350f7596 | 3032 | static const struct phy_reg phy_reg_init[] = { |
0b9b571d | 3033 | { 0x1f, 0x0001 }, |
3034 | { 0x06, 0x006e }, | |
3035 | { 0x08, 0x0708 }, | |
3036 | { 0x15, 0x4000 }, | |
3037 | { 0x18, 0x65c7 }, | |
1da177e4 | 3038 | |
0b9b571d | 3039 | { 0x1f, 0x0001 }, |
3040 | { 0x03, 0x00a1 }, | |
3041 | { 0x02, 0x0008 }, | |
3042 | { 0x01, 0x0120 }, | |
3043 | { 0x00, 0x1000 }, | |
3044 | { 0x04, 0x0800 }, | |
3045 | { 0x04, 0x0000 }, | |
1da177e4 | 3046 | |
0b9b571d | 3047 | { 0x03, 0xff41 }, |
3048 | { 0x02, 0xdf60 }, | |
3049 | { 0x01, 0x0140 }, | |
3050 | { 0x00, 0x0077 }, | |
3051 | { 0x04, 0x7800 }, | |
3052 | { 0x04, 0x7000 }, | |
3053 | ||
3054 | { 0x03, 0x802f }, | |
3055 | { 0x02, 0x4f02 }, | |
3056 | { 0x01, 0x0409 }, | |
3057 | { 0x00, 0xf0f9 }, | |
3058 | { 0x04, 0x9800 }, | |
3059 | { 0x04, 0x9000 }, | |
3060 | ||
3061 | { 0x03, 0xdf01 }, | |
3062 | { 0x02, 0xdf20 }, | |
3063 | { 0x01, 0xff95 }, | |
3064 | { 0x00, 0xba00 }, | |
3065 | { 0x04, 0xa800 }, | |
3066 | { 0x04, 0xa000 }, | |
3067 | ||
3068 | { 0x03, 0xff41 }, | |
3069 | { 0x02, 0xdf20 }, | |
3070 | { 0x01, 0x0140 }, | |
3071 | { 0x00, 0x00bb }, | |
3072 | { 0x04, 0xb800 }, | |
3073 | { 0x04, 0xb000 }, | |
3074 | ||
3075 | { 0x03, 0xdf41 }, | |
3076 | { 0x02, 0xdc60 }, | |
3077 | { 0x01, 0x6340 }, | |
3078 | { 0x00, 0x007d }, | |
3079 | { 0x04, 0xd800 }, | |
3080 | { 0x04, 0xd000 }, | |
3081 | ||
3082 | { 0x03, 0xdf01 }, | |
3083 | { 0x02, 0xdf20 }, | |
3084 | { 0x01, 0x100a }, | |
3085 | { 0x00, 0xa0ff }, | |
3086 | { 0x04, 0xf800 }, | |
3087 | { 0x04, 0xf000 }, | |
3088 | ||
3089 | { 0x1f, 0x0000 }, | |
3090 | { 0x0b, 0x0000 }, | |
3091 | { 0x00, 0x9200 } | |
3092 | }; | |
1da177e4 | 3093 | |
4da19633 | 3094 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
1da177e4 LT |
3095 | } |
3096 | ||
4da19633 | 3097 | static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) |
5615d9f1 | 3098 | { |
350f7596 | 3099 | static const struct phy_reg phy_reg_init[] = { |
a441d7b6 FR |
3100 | { 0x1f, 0x0002 }, |
3101 | { 0x01, 0x90d0 }, | |
3102 | { 0x1f, 0x0000 } | |
3103 | }; | |
3104 | ||
4da19633 | 3105 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5615d9f1 FR |
3106 | } |
3107 | ||
4da19633 | 3108 | static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) |
2e955856 | 3109 | { |
3110 | struct pci_dev *pdev = tp->pci_dev; | |
2e955856 | 3111 | |
ccbae55e SS |
3112 | if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || |
3113 | (pdev->subsystem_device != 0xe000)) | |
2e955856 | 3114 | return; |
3115 | ||
4da19633 | 3116 | rtl_writephy(tp, 0x1f, 0x0001); |
3117 | rtl_writephy(tp, 0x10, 0xf01b); | |
3118 | rtl_writephy(tp, 0x1f, 0x0000); | |
2e955856 | 3119 | } |
3120 | ||
4da19633 | 3121 | static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) |
2e955856 | 3122 | { |
350f7596 | 3123 | static const struct phy_reg phy_reg_init[] = { |
2e955856 | 3124 | { 0x1f, 0x0001 }, |
3125 | { 0x04, 0x0000 }, | |
3126 | { 0x03, 0x00a1 }, | |
3127 | { 0x02, 0x0008 }, | |
3128 | { 0x01, 0x0120 }, | |
3129 | { 0x00, 0x1000 }, | |
3130 | { 0x04, 0x0800 }, | |
3131 | { 0x04, 0x9000 }, | |
3132 | { 0x03, 0x802f }, | |
3133 | { 0x02, 0x4f02 }, | |
3134 | { 0x01, 0x0409 }, | |
3135 | { 0x00, 0xf099 }, | |
3136 | { 0x04, 0x9800 }, | |
3137 | { 0x04, 0xa000 }, | |
3138 | { 0x03, 0xdf01 }, | |
3139 | { 0x02, 0xdf20 }, | |
3140 | { 0x01, 0xff95 }, | |
3141 | { 0x00, 0xba00 }, | |
3142 | { 0x04, 0xa800 }, | |
3143 | { 0x04, 0xf000 }, | |
3144 | { 0x03, 0xdf01 }, | |
3145 | { 0x02, 0xdf20 }, | |
3146 | { 0x01, 0x101a }, | |
3147 | { 0x00, 0xa0ff }, | |
3148 | { 0x04, 0xf800 }, | |
3149 | { 0x04, 0x0000 }, | |
3150 | { 0x1f, 0x0000 }, | |
3151 | ||
3152 | { 0x1f, 0x0001 }, | |
3153 | { 0x10, 0xf41b }, | |
3154 | { 0x14, 0xfb54 }, | |
3155 | { 0x18, 0xf5c7 }, | |
3156 | { 0x1f, 0x0000 }, | |
3157 | ||
3158 | { 0x1f, 0x0001 }, | |
3159 | { 0x17, 0x0cc0 }, | |
3160 | { 0x1f, 0x0000 } | |
3161 | }; | |
3162 | ||
4da19633 | 3163 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2e955856 | 3164 | |
4da19633 | 3165 | rtl8169scd_hw_phy_config_quirk(tp); |
2e955856 | 3166 | } |
3167 | ||
4da19633 | 3168 | static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) |
8c7006aa | 3169 | { |
350f7596 | 3170 | static const struct phy_reg phy_reg_init[] = { |
8c7006aa | 3171 | { 0x1f, 0x0001 }, |
3172 | { 0x04, 0x0000 }, | |
3173 | { 0x03, 0x00a1 }, | |
3174 | { 0x02, 0x0008 }, | |
3175 | { 0x01, 0x0120 }, | |
3176 | { 0x00, 0x1000 }, | |
3177 | { 0x04, 0x0800 }, | |
3178 | { 0x04, 0x9000 }, | |
3179 | { 0x03, 0x802f }, | |
3180 | { 0x02, 0x4f02 }, | |
3181 | { 0x01, 0x0409 }, | |
3182 | { 0x00, 0xf099 }, | |
3183 | { 0x04, 0x9800 }, | |
3184 | { 0x04, 0xa000 }, | |
3185 | { 0x03, 0xdf01 }, | |
3186 | { 0x02, 0xdf20 }, | |
3187 | { 0x01, 0xff95 }, | |
3188 | { 0x00, 0xba00 }, | |
3189 | { 0x04, 0xa800 }, | |
3190 | { 0x04, 0xf000 }, | |
3191 | { 0x03, 0xdf01 }, | |
3192 | { 0x02, 0xdf20 }, | |
3193 | { 0x01, 0x101a }, | |
3194 | { 0x00, 0xa0ff }, | |
3195 | { 0x04, 0xf800 }, | |
3196 | { 0x04, 0x0000 }, | |
3197 | { 0x1f, 0x0000 }, | |
3198 | ||
3199 | { 0x1f, 0x0001 }, | |
3200 | { 0x0b, 0x8480 }, | |
3201 | { 0x1f, 0x0000 }, | |
3202 | ||
3203 | { 0x1f, 0x0001 }, | |
3204 | { 0x18, 0x67c7 }, | |
3205 | { 0x04, 0x2000 }, | |
3206 | { 0x03, 0x002f }, | |
3207 | { 0x02, 0x4360 }, | |
3208 | { 0x01, 0x0109 }, | |
3209 | { 0x00, 0x3022 }, | |
3210 | { 0x04, 0x2800 }, | |
3211 | { 0x1f, 0x0000 }, | |
3212 | ||
3213 | { 0x1f, 0x0001 }, | |
3214 | { 0x17, 0x0cc0 }, | |
3215 | { 0x1f, 0x0000 } | |
3216 | }; | |
3217 | ||
4da19633 | 3218 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
8c7006aa | 3219 | } |
3220 | ||
4da19633 | 3221 | static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 3222 | { |
350f7596 | 3223 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
3224 | { 0x10, 0xf41b }, |
3225 | { 0x1f, 0x0000 } | |
3226 | }; | |
3227 | ||
4da19633 | 3228 | rtl_writephy(tp, 0x1f, 0x0001); |
3229 | rtl_patchphy(tp, 0x16, 1 << 0); | |
236b8082 | 3230 | |
4da19633 | 3231 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
3232 | } |
3233 | ||
4da19633 | 3234 | static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 3235 | { |
350f7596 | 3236 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
3237 | { 0x1f, 0x0001 }, |
3238 | { 0x10, 0xf41b }, | |
3239 | { 0x1f, 0x0000 } | |
3240 | }; | |
3241 | ||
4da19633 | 3242 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
3243 | } |
3244 | ||
4da19633 | 3245 | static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 3246 | { |
350f7596 | 3247 | static const struct phy_reg phy_reg_init[] = { |
867763c1 FR |
3248 | { 0x1f, 0x0000 }, |
3249 | { 0x1d, 0x0f00 }, | |
3250 | { 0x1f, 0x0002 }, | |
3251 | { 0x0c, 0x1ec8 }, | |
3252 | { 0x1f, 0x0000 } | |
3253 | }; | |
3254 | ||
4da19633 | 3255 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
867763c1 FR |
3256 | } |
3257 | ||
4da19633 | 3258 | static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) |
ef3386f0 | 3259 | { |
350f7596 | 3260 | static const struct phy_reg phy_reg_init[] = { |
ef3386f0 FR |
3261 | { 0x1f, 0x0001 }, |
3262 | { 0x1d, 0x3d98 }, | |
3263 | { 0x1f, 0x0000 } | |
3264 | }; | |
3265 | ||
4da19633 | 3266 | rtl_writephy(tp, 0x1f, 0x0000); |
3267 | rtl_patchphy(tp, 0x14, 1 << 5); | |
3268 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
ef3386f0 | 3269 | |
4da19633 | 3270 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
ef3386f0 FR |
3271 | } |
3272 | ||
4da19633 | 3273 | static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 3274 | { |
350f7596 | 3275 | static const struct phy_reg phy_reg_init[] = { |
a3f80671 FR |
3276 | { 0x1f, 0x0001 }, |
3277 | { 0x12, 0x2300 }, | |
867763c1 FR |
3278 | { 0x1f, 0x0002 }, |
3279 | { 0x00, 0x88d4 }, | |
3280 | { 0x01, 0x82b1 }, | |
3281 | { 0x03, 0x7002 }, | |
3282 | { 0x08, 0x9e30 }, | |
3283 | { 0x09, 0x01f0 }, | |
3284 | { 0x0a, 0x5500 }, | |
3285 | { 0x0c, 0x00c8 }, | |
3286 | { 0x1f, 0x0003 }, | |
3287 | { 0x12, 0xc096 }, | |
3288 | { 0x16, 0x000a }, | |
f50d4275 FR |
3289 | { 0x1f, 0x0000 }, |
3290 | { 0x1f, 0x0000 }, | |
3291 | { 0x09, 0x2000 }, | |
3292 | { 0x09, 0x0000 } | |
867763c1 FR |
3293 | }; |
3294 | ||
4da19633 | 3295 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 3296 | |
4da19633 | 3297 | rtl_patchphy(tp, 0x14, 1 << 5); |
3298 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
3299 | rtl_writephy(tp, 0x1f, 0x0000); | |
867763c1 FR |
3300 | } |
3301 | ||
4da19633 | 3302 | static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) |
7da97ec9 | 3303 | { |
350f7596 | 3304 | static const struct phy_reg phy_reg_init[] = { |
f50d4275 | 3305 | { 0x1f, 0x0001 }, |
7da97ec9 | 3306 | { 0x12, 0x2300 }, |
f50d4275 FR |
3307 | { 0x03, 0x802f }, |
3308 | { 0x02, 0x4f02 }, | |
3309 | { 0x01, 0x0409 }, | |
3310 | { 0x00, 0xf099 }, | |
3311 | { 0x04, 0x9800 }, | |
3312 | { 0x04, 0x9000 }, | |
3313 | { 0x1d, 0x3d98 }, | |
7da97ec9 FR |
3314 | { 0x1f, 0x0002 }, |
3315 | { 0x0c, 0x7eb8 }, | |
f50d4275 FR |
3316 | { 0x06, 0x0761 }, |
3317 | { 0x1f, 0x0003 }, | |
3318 | { 0x16, 0x0f0a }, | |
7da97ec9 FR |
3319 | { 0x1f, 0x0000 } |
3320 | }; | |
3321 | ||
4da19633 | 3322 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 3323 | |
4da19633 | 3324 | rtl_patchphy(tp, 0x16, 1 << 0); |
3325 | rtl_patchphy(tp, 0x14, 1 << 5); | |
3326 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
3327 | rtl_writephy(tp, 0x1f, 0x0000); | |
7da97ec9 FR |
3328 | } |
3329 | ||
4da19633 | 3330 | static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) |
197ff761 | 3331 | { |
350f7596 | 3332 | static const struct phy_reg phy_reg_init[] = { |
197ff761 FR |
3333 | { 0x1f, 0x0001 }, |
3334 | { 0x12, 0x2300 }, | |
3335 | { 0x1d, 0x3d98 }, | |
3336 | { 0x1f, 0x0002 }, | |
3337 | { 0x0c, 0x7eb8 }, | |
3338 | { 0x06, 0x5461 }, | |
3339 | { 0x1f, 0x0003 }, | |
3340 | { 0x16, 0x0f0a }, | |
3341 | { 0x1f, 0x0000 } | |
3342 | }; | |
3343 | ||
4da19633 | 3344 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
197ff761 | 3345 | |
4da19633 | 3346 | rtl_patchphy(tp, 0x16, 1 << 0); |
3347 | rtl_patchphy(tp, 0x14, 1 << 5); | |
3348 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
3349 | rtl_writephy(tp, 0x1f, 0x0000); | |
197ff761 FR |
3350 | } |
3351 | ||
4da19633 | 3352 | static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) |
6fb07058 | 3353 | { |
4da19633 | 3354 | rtl8168c_3_hw_phy_config(tp); |
6fb07058 FR |
3355 | } |
3356 | ||
bca03d5f | 3357 | static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) |
5b538df9 | 3358 | { |
350f7596 | 3359 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 3360 | /* Channel Estimation */ |
5b538df9 | 3361 | { 0x1f, 0x0001 }, |
daf9df6d | 3362 | { 0x06, 0x4064 }, |
3363 | { 0x07, 0x2863 }, | |
3364 | { 0x08, 0x059c }, | |
3365 | { 0x09, 0x26b4 }, | |
3366 | { 0x0a, 0x6a19 }, | |
3367 | { 0x0b, 0xdcc8 }, | |
3368 | { 0x10, 0xf06d }, | |
3369 | { 0x14, 0x7f68 }, | |
3370 | { 0x18, 0x7fd9 }, | |
3371 | { 0x1c, 0xf0ff }, | |
3372 | { 0x1d, 0x3d9c }, | |
5b538df9 | 3373 | { 0x1f, 0x0003 }, |
daf9df6d | 3374 | { 0x12, 0xf49f }, |
3375 | { 0x13, 0x070b }, | |
3376 | { 0x1a, 0x05ad }, | |
bca03d5f | 3377 | { 0x14, 0x94c0 }, |
3378 | ||
3379 | /* | |
3380 | * Tx Error Issue | |
cecb5fd7 | 3381 | * Enhance line driver power |
bca03d5f | 3382 | */ |
5b538df9 | 3383 | { 0x1f, 0x0002 }, |
daf9df6d | 3384 | { 0x06, 0x5561 }, |
3385 | { 0x1f, 0x0005 }, | |
3386 | { 0x05, 0x8332 }, | |
bca03d5f | 3387 | { 0x06, 0x5561 }, |
3388 | ||
3389 | /* | |
3390 | * Can not link to 1Gbps with bad cable | |
3391 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
3392 | */ | |
3393 | { 0x1f, 0x0001 }, | |
3394 | { 0x17, 0x0cc0 }, | |
daf9df6d | 3395 | |
5b538df9 | 3396 | { 0x1f, 0x0000 }, |
bca03d5f | 3397 | { 0x0d, 0xf880 } |
daf9df6d | 3398 | }; |
3399 | ||
4da19633 | 3400 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
daf9df6d | 3401 | |
bca03d5f | 3402 | /* |
3403 | * Rx Error Issue | |
3404 | * Fine Tune Switching regulator parameter | |
3405 | */ | |
4da19633 | 3406 | rtl_writephy(tp, 0x1f, 0x0002); |
76564428 CHL |
3407 | rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef); |
3408 | rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00); | |
daf9df6d | 3409 | |
fdf6fc06 | 3410 | if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { |
350f7596 | 3411 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3412 | { 0x1f, 0x0002 }, |
3413 | { 0x05, 0x669a }, | |
3414 | { 0x1f, 0x0005 }, | |
3415 | { 0x05, 0x8330 }, | |
3416 | { 0x06, 0x669a }, | |
3417 | { 0x1f, 0x0002 } | |
3418 | }; | |
3419 | int val; | |
3420 | ||
4da19633 | 3421 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 3422 | |
4da19633 | 3423 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 3424 | |
3425 | if ((val & 0x00ff) != 0x006c) { | |
350f7596 | 3426 | static const u32 set[] = { |
daf9df6d | 3427 | 0x0065, 0x0066, 0x0067, 0x0068, |
3428 | 0x0069, 0x006a, 0x006b, 0x006c | |
3429 | }; | |
3430 | int i; | |
3431 | ||
4da19633 | 3432 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 3433 | |
3434 | val &= 0xff00; | |
3435 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 3436 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 3437 | } |
3438 | } else { | |
350f7596 | 3439 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3440 | { 0x1f, 0x0002 }, |
3441 | { 0x05, 0x6662 }, | |
3442 | { 0x1f, 0x0005 }, | |
3443 | { 0x05, 0x8330 }, | |
3444 | { 0x06, 0x6662 } | |
3445 | }; | |
3446 | ||
4da19633 | 3447 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 3448 | } |
3449 | ||
bca03d5f | 3450 | /* RSET couple improve */ |
4da19633 | 3451 | rtl_writephy(tp, 0x1f, 0x0002); |
3452 | rtl_patchphy(tp, 0x0d, 0x0300); | |
3453 | rtl_patchphy(tp, 0x0f, 0x0010); | |
daf9df6d | 3454 | |
bca03d5f | 3455 | /* Fine tune PLL performance */ |
4da19633 | 3456 | rtl_writephy(tp, 0x1f, 0x0002); |
76564428 CHL |
3457 | rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); |
3458 | rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 3459 | |
4da19633 | 3460 | rtl_writephy(tp, 0x1f, 0x0005); |
3461 | rtl_writephy(tp, 0x05, 0x001b); | |
953a12cc FR |
3462 | |
3463 | rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); | |
bca03d5f | 3464 | |
4da19633 | 3465 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 3466 | } |
3467 | ||
bca03d5f | 3468 | static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 3469 | { |
350f7596 | 3470 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 3471 | /* Channel Estimation */ |
daf9df6d | 3472 | { 0x1f, 0x0001 }, |
3473 | { 0x06, 0x4064 }, | |
3474 | { 0x07, 0x2863 }, | |
3475 | { 0x08, 0x059c }, | |
3476 | { 0x09, 0x26b4 }, | |
3477 | { 0x0a, 0x6a19 }, | |
3478 | { 0x0b, 0xdcc8 }, | |
3479 | { 0x10, 0xf06d }, | |
3480 | { 0x14, 0x7f68 }, | |
3481 | { 0x18, 0x7fd9 }, | |
3482 | { 0x1c, 0xf0ff }, | |
3483 | { 0x1d, 0x3d9c }, | |
3484 | { 0x1f, 0x0003 }, | |
3485 | { 0x12, 0xf49f }, | |
3486 | { 0x13, 0x070b }, | |
3487 | { 0x1a, 0x05ad }, | |
3488 | { 0x14, 0x94c0 }, | |
3489 | ||
bca03d5f | 3490 | /* |
3491 | * Tx Error Issue | |
cecb5fd7 | 3492 | * Enhance line driver power |
bca03d5f | 3493 | */ |
daf9df6d | 3494 | { 0x1f, 0x0002 }, |
3495 | { 0x06, 0x5561 }, | |
3496 | { 0x1f, 0x0005 }, | |
3497 | { 0x05, 0x8332 }, | |
bca03d5f | 3498 | { 0x06, 0x5561 }, |
3499 | ||
3500 | /* | |
3501 | * Can not link to 1Gbps with bad cable | |
3502 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
3503 | */ | |
3504 | { 0x1f, 0x0001 }, | |
3505 | { 0x17, 0x0cc0 }, | |
daf9df6d | 3506 | |
3507 | { 0x1f, 0x0000 }, | |
bca03d5f | 3508 | { 0x0d, 0xf880 } |
5b538df9 FR |
3509 | }; |
3510 | ||
4da19633 | 3511 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
5b538df9 | 3512 | |
fdf6fc06 | 3513 | if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { |
350f7596 | 3514 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3515 | { 0x1f, 0x0002 }, |
3516 | { 0x05, 0x669a }, | |
5b538df9 | 3517 | { 0x1f, 0x0005 }, |
daf9df6d | 3518 | { 0x05, 0x8330 }, |
3519 | { 0x06, 0x669a }, | |
3520 | ||
3521 | { 0x1f, 0x0002 } | |
3522 | }; | |
3523 | int val; | |
3524 | ||
4da19633 | 3525 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 3526 | |
4da19633 | 3527 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 3528 | if ((val & 0x00ff) != 0x006c) { |
b6bc7650 | 3529 | static const u32 set[] = { |
daf9df6d | 3530 | 0x0065, 0x0066, 0x0067, 0x0068, |
3531 | 0x0069, 0x006a, 0x006b, 0x006c | |
3532 | }; | |
3533 | int i; | |
3534 | ||
4da19633 | 3535 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 3536 | |
3537 | val &= 0xff00; | |
3538 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 3539 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 3540 | } |
3541 | } else { | |
350f7596 | 3542 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3543 | { 0x1f, 0x0002 }, |
3544 | { 0x05, 0x2642 }, | |
5b538df9 | 3545 | { 0x1f, 0x0005 }, |
daf9df6d | 3546 | { 0x05, 0x8330 }, |
3547 | { 0x06, 0x2642 } | |
5b538df9 FR |
3548 | }; |
3549 | ||
4da19633 | 3550 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
3551 | } |
3552 | ||
bca03d5f | 3553 | /* Fine tune PLL performance */ |
4da19633 | 3554 | rtl_writephy(tp, 0x1f, 0x0002); |
76564428 CHL |
3555 | rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); |
3556 | rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 3557 | |
bca03d5f | 3558 | /* Switching regulator Slew rate */ |
4da19633 | 3559 | rtl_writephy(tp, 0x1f, 0x0002); |
3560 | rtl_patchphy(tp, 0x0f, 0x0017); | |
daf9df6d | 3561 | |
4da19633 | 3562 | rtl_writephy(tp, 0x1f, 0x0005); |
3563 | rtl_writephy(tp, 0x05, 0x001b); | |
953a12cc FR |
3564 | |
3565 | rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); | |
bca03d5f | 3566 | |
4da19633 | 3567 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 3568 | } |
3569 | ||
4da19633 | 3570 | static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 3571 | { |
350f7596 | 3572 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3573 | { 0x1f, 0x0002 }, |
3574 | { 0x10, 0x0008 }, | |
3575 | { 0x0d, 0x006c }, | |
3576 | ||
3577 | { 0x1f, 0x0000 }, | |
3578 | { 0x0d, 0xf880 }, | |
3579 | ||
3580 | { 0x1f, 0x0001 }, | |
3581 | { 0x17, 0x0cc0 }, | |
3582 | ||
3583 | { 0x1f, 0x0001 }, | |
3584 | { 0x0b, 0xa4d8 }, | |
3585 | { 0x09, 0x281c }, | |
3586 | { 0x07, 0x2883 }, | |
3587 | { 0x0a, 0x6b35 }, | |
3588 | { 0x1d, 0x3da4 }, | |
3589 | { 0x1c, 0xeffd }, | |
3590 | { 0x14, 0x7f52 }, | |
3591 | { 0x18, 0x7fc6 }, | |
3592 | { 0x08, 0x0601 }, | |
3593 | { 0x06, 0x4063 }, | |
3594 | { 0x10, 0xf074 }, | |
3595 | { 0x1f, 0x0003 }, | |
3596 | { 0x13, 0x0789 }, | |
3597 | { 0x12, 0xf4bd }, | |
3598 | { 0x1a, 0x04fd }, | |
3599 | { 0x14, 0x84b0 }, | |
3600 | { 0x1f, 0x0000 }, | |
3601 | { 0x00, 0x9200 }, | |
3602 | ||
3603 | { 0x1f, 0x0005 }, | |
3604 | { 0x01, 0x0340 }, | |
3605 | { 0x1f, 0x0001 }, | |
3606 | { 0x04, 0x4000 }, | |
3607 | { 0x03, 0x1d21 }, | |
3608 | { 0x02, 0x0c32 }, | |
3609 | { 0x01, 0x0200 }, | |
3610 | { 0x00, 0x5554 }, | |
3611 | { 0x04, 0x4800 }, | |
3612 | { 0x04, 0x4000 }, | |
3613 | { 0x04, 0xf000 }, | |
3614 | { 0x03, 0xdf01 }, | |
3615 | { 0x02, 0xdf20 }, | |
3616 | { 0x01, 0x101a }, | |
3617 | { 0x00, 0xa0ff }, | |
3618 | { 0x04, 0xf800 }, | |
3619 | { 0x04, 0xf000 }, | |
3620 | { 0x1f, 0x0000 }, | |
3621 | ||
3622 | { 0x1f, 0x0007 }, | |
3623 | { 0x1e, 0x0023 }, | |
3624 | { 0x16, 0x0000 }, | |
3625 | { 0x1f, 0x0000 } | |
3626 | }; | |
3627 | ||
4da19633 | 3628 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
3629 | } |
3630 | ||
e6de30d6 | 3631 | static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) |
3632 | { | |
3633 | static const struct phy_reg phy_reg_init[] = { | |
3634 | { 0x1f, 0x0001 }, | |
3635 | { 0x17, 0x0cc0 }, | |
3636 | ||
3637 | { 0x1f, 0x0007 }, | |
3638 | { 0x1e, 0x002d }, | |
3639 | { 0x18, 0x0040 }, | |
3640 | { 0x1f, 0x0000 } | |
3641 | }; | |
3642 | ||
3643 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3644 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
3645 | } | |
3646 | ||
70090424 | 3647 | static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) |
01dc7fec | 3648 | { |
3649 | static const struct phy_reg phy_reg_init[] = { | |
3650 | /* Enable Delay cap */ | |
3651 | { 0x1f, 0x0005 }, | |
3652 | { 0x05, 0x8b80 }, | |
3653 | { 0x06, 0xc896 }, | |
3654 | { 0x1f, 0x0000 }, | |
3655 | ||
3656 | /* Channel estimation fine tune */ | |
3657 | { 0x1f, 0x0001 }, | |
3658 | { 0x0b, 0x6c20 }, | |
3659 | { 0x07, 0x2872 }, | |
3660 | { 0x1c, 0xefff }, | |
3661 | { 0x1f, 0x0003 }, | |
3662 | { 0x14, 0x6420 }, | |
3663 | { 0x1f, 0x0000 }, | |
3664 | ||
3665 | /* Update PFM & 10M TX idle timer */ | |
3666 | { 0x1f, 0x0007 }, | |
3667 | { 0x1e, 0x002f }, | |
3668 | { 0x15, 0x1919 }, | |
3669 | { 0x1f, 0x0000 }, | |
3670 | ||
3671 | { 0x1f, 0x0007 }, | |
3672 | { 0x1e, 0x00ac }, | |
3673 | { 0x18, 0x0006 }, | |
3674 | { 0x1f, 0x0000 } | |
3675 | }; | |
3676 | ||
15ecd039 FR |
3677 | rtl_apply_firmware(tp); |
3678 | ||
01dc7fec | 3679 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
3680 | ||
3681 | /* DCO enable for 10M IDLE Power */ | |
3682 | rtl_writephy(tp, 0x1f, 0x0007); | |
3683 | rtl_writephy(tp, 0x1e, 0x0023); | |
76564428 | 3684 | rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); |
01dc7fec | 3685 | rtl_writephy(tp, 0x1f, 0x0000); |
3686 | ||
3687 | /* For impedance matching */ | |
3688 | rtl_writephy(tp, 0x1f, 0x0002); | |
76564428 | 3689 | rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00); |
cecb5fd7 | 3690 | rtl_writephy(tp, 0x1f, 0x0000); |
01dc7fec | 3691 | |
3692 | /* PHY auto speed down */ | |
3693 | rtl_writephy(tp, 0x1f, 0x0007); | |
3694 | rtl_writephy(tp, 0x1e, 0x002d); | |
76564428 | 3695 | rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000); |
01dc7fec | 3696 | rtl_writephy(tp, 0x1f, 0x0000); |
76564428 | 3697 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); |
01dc7fec | 3698 | |
3699 | rtl_writephy(tp, 0x1f, 0x0005); | |
3700 | rtl_writephy(tp, 0x05, 0x8b86); | |
76564428 | 3701 | rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); |
01dc7fec | 3702 | rtl_writephy(tp, 0x1f, 0x0000); |
3703 | ||
3704 | rtl_writephy(tp, 0x1f, 0x0005); | |
3705 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3706 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000); |
01dc7fec | 3707 | rtl_writephy(tp, 0x1f, 0x0007); |
3708 | rtl_writephy(tp, 0x1e, 0x0020); | |
76564428 | 3709 | rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100); |
01dc7fec | 3710 | rtl_writephy(tp, 0x1f, 0x0006); |
3711 | rtl_writephy(tp, 0x00, 0x5a00); | |
3712 | rtl_writephy(tp, 0x1f, 0x0000); | |
3713 | rtl_writephy(tp, 0x0d, 0x0007); | |
3714 | rtl_writephy(tp, 0x0e, 0x003c); | |
3715 | rtl_writephy(tp, 0x0d, 0x4007); | |
3716 | rtl_writephy(tp, 0x0e, 0x0000); | |
3717 | rtl_writephy(tp, 0x0d, 0x0000); | |
3718 | } | |
3719 | ||
9ecb9aab | 3720 | static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) |
3721 | { | |
3722 | const u16 w[] = { | |
3723 | addr[0] | (addr[1] << 8), | |
3724 | addr[2] | (addr[3] << 8), | |
3725 | addr[4] | (addr[5] << 8) | |
3726 | }; | |
3727 | const struct exgmac_reg e[] = { | |
3728 | { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) }, | |
3729 | { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] }, | |
3730 | { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 }, | |
3731 | { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) } | |
3732 | }; | |
3733 | ||
3734 | rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e)); | |
3735 | } | |
3736 | ||
70090424 HW |
3737 | static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) |
3738 | { | |
3739 | static const struct phy_reg phy_reg_init[] = { | |
3740 | /* Enable Delay cap */ | |
3741 | { 0x1f, 0x0004 }, | |
3742 | { 0x1f, 0x0007 }, | |
3743 | { 0x1e, 0x00ac }, | |
3744 | { 0x18, 0x0006 }, | |
3745 | { 0x1f, 0x0002 }, | |
3746 | { 0x1f, 0x0000 }, | |
3747 | { 0x1f, 0x0000 }, | |
3748 | ||
3749 | /* Channel estimation fine tune */ | |
3750 | { 0x1f, 0x0003 }, | |
3751 | { 0x09, 0xa20f }, | |
3752 | { 0x1f, 0x0000 }, | |
3753 | { 0x1f, 0x0000 }, | |
3754 | ||
3755 | /* Green Setting */ | |
3756 | { 0x1f, 0x0005 }, | |
3757 | { 0x05, 0x8b5b }, | |
3758 | { 0x06, 0x9222 }, | |
3759 | { 0x05, 0x8b6d }, | |
3760 | { 0x06, 0x8000 }, | |
3761 | { 0x05, 0x8b76 }, | |
3762 | { 0x06, 0x8000 }, | |
3763 | { 0x1f, 0x0000 } | |
3764 | }; | |
3765 | ||
3766 | rtl_apply_firmware(tp); | |
3767 | ||
3768 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3769 | ||
3770 | /* For 4-corner performance improve */ | |
3771 | rtl_writephy(tp, 0x1f, 0x0005); | |
3772 | rtl_writephy(tp, 0x05, 0x8b80); | |
76564428 | 3773 | rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); |
70090424 HW |
3774 | rtl_writephy(tp, 0x1f, 0x0000); |
3775 | ||
3776 | /* PHY auto speed down */ | |
3777 | rtl_writephy(tp, 0x1f, 0x0004); | |
3778 | rtl_writephy(tp, 0x1f, 0x0007); | |
3779 | rtl_writephy(tp, 0x1e, 0x002d); | |
76564428 | 3780 | rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000); |
70090424 HW |
3781 | rtl_writephy(tp, 0x1f, 0x0002); |
3782 | rtl_writephy(tp, 0x1f, 0x0000); | |
76564428 | 3783 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); |
70090424 HW |
3784 | |
3785 | /* improve 10M EEE waveform */ | |
3786 | rtl_writephy(tp, 0x1f, 0x0005); | |
3787 | rtl_writephy(tp, 0x05, 0x8b86); | |
76564428 | 3788 | rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); |
70090424 HW |
3789 | rtl_writephy(tp, 0x1f, 0x0000); |
3790 | ||
3791 | /* Improve 2-pair detection performance */ | |
3792 | rtl_writephy(tp, 0x1f, 0x0005); | |
3793 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3794 | rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); |
70090424 HW |
3795 | rtl_writephy(tp, 0x1f, 0x0000); |
3796 | ||
3797 | /* EEE setting */ | |
1814d6a8 | 3798 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC); |
70090424 HW |
3799 | rtl_writephy(tp, 0x1f, 0x0005); |
3800 | rtl_writephy(tp, 0x05, 0x8b85); | |
1814d6a8 | 3801 | rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000); |
70090424 HW |
3802 | rtl_writephy(tp, 0x1f, 0x0004); |
3803 | rtl_writephy(tp, 0x1f, 0x0007); | |
3804 | rtl_writephy(tp, 0x1e, 0x0020); | |
1814d6a8 | 3805 | rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000); |
70090424 HW |
3806 | rtl_writephy(tp, 0x1f, 0x0002); |
3807 | rtl_writephy(tp, 0x1f, 0x0000); | |
3808 | rtl_writephy(tp, 0x0d, 0x0007); | |
3809 | rtl_writephy(tp, 0x0e, 0x003c); | |
3810 | rtl_writephy(tp, 0x0d, 0x4007); | |
1814d6a8 | 3811 | rtl_writephy(tp, 0x0e, 0x0006); |
70090424 HW |
3812 | rtl_writephy(tp, 0x0d, 0x0000); |
3813 | ||
3814 | /* Green feature */ | |
3815 | rtl_writephy(tp, 0x1f, 0x0003); | |
1814d6a8 HK |
3816 | rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000); |
3817 | rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000); | |
70090424 | 3818 | rtl_writephy(tp, 0x1f, 0x0000); |
b399a394 HK |
3819 | rtl_writephy(tp, 0x1f, 0x0005); |
3820 | rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000); | |
3821 | rtl_writephy(tp, 0x1f, 0x0000); | |
3822 | /* soft-reset phy */ | |
3823 | rtl_writephy(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART); | |
e0c07557 | 3824 | |
9ecb9aab | 3825 | /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */ |
3826 | rtl_rar_exgmac_set(tp, tp->dev->dev_addr); | |
70090424 HW |
3827 | } |
3828 | ||
5f886e08 HW |
3829 | static void rtl8168f_hw_phy_config(struct rtl8169_private *tp) |
3830 | { | |
3831 | /* For 4-corner performance improve */ | |
3832 | rtl_writephy(tp, 0x1f, 0x0005); | |
3833 | rtl_writephy(tp, 0x05, 0x8b80); | |
76564428 | 3834 | rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000); |
5f886e08 HW |
3835 | rtl_writephy(tp, 0x1f, 0x0000); |
3836 | ||
3837 | /* PHY auto speed down */ | |
3838 | rtl_writephy(tp, 0x1f, 0x0007); | |
3839 | rtl_writephy(tp, 0x1e, 0x002d); | |
76564428 | 3840 | rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000); |
5f886e08 | 3841 | rtl_writephy(tp, 0x1f, 0x0000); |
76564428 | 3842 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); |
5f886e08 HW |
3843 | |
3844 | /* Improve 10M EEE waveform */ | |
3845 | rtl_writephy(tp, 0x1f, 0x0005); | |
3846 | rtl_writephy(tp, 0x05, 0x8b86); | |
76564428 | 3847 | rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); |
5f886e08 HW |
3848 | rtl_writephy(tp, 0x1f, 0x0000); |
3849 | } | |
3850 | ||
c2218925 HW |
3851 | static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) |
3852 | { | |
3853 | static const struct phy_reg phy_reg_init[] = { | |
3854 | /* Channel estimation fine tune */ | |
3855 | { 0x1f, 0x0003 }, | |
3856 | { 0x09, 0xa20f }, | |
3857 | { 0x1f, 0x0000 }, | |
3858 | ||
3859 | /* Modify green table for giga & fnet */ | |
3860 | { 0x1f, 0x0005 }, | |
3861 | { 0x05, 0x8b55 }, | |
3862 | { 0x06, 0x0000 }, | |
3863 | { 0x05, 0x8b5e }, | |
3864 | { 0x06, 0x0000 }, | |
3865 | { 0x05, 0x8b67 }, | |
3866 | { 0x06, 0x0000 }, | |
3867 | { 0x05, 0x8b70 }, | |
3868 | { 0x06, 0x0000 }, | |
3869 | { 0x1f, 0x0000 }, | |
3870 | { 0x1f, 0x0007 }, | |
3871 | { 0x1e, 0x0078 }, | |
3872 | { 0x17, 0x0000 }, | |
3873 | { 0x19, 0x00fb }, | |
3874 | { 0x1f, 0x0000 }, | |
3875 | ||
3876 | /* Modify green table for 10M */ | |
3877 | { 0x1f, 0x0005 }, | |
3878 | { 0x05, 0x8b79 }, | |
3879 | { 0x06, 0xaa00 }, | |
3880 | { 0x1f, 0x0000 }, | |
3881 | ||
3882 | /* Disable hiimpedance detection (RTCT) */ | |
3883 | { 0x1f, 0x0003 }, | |
3884 | { 0x01, 0x328a }, | |
3885 | { 0x1f, 0x0000 } | |
3886 | }; | |
3887 | ||
3888 | rtl_apply_firmware(tp); | |
3889 | ||
3890 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3891 | ||
5f886e08 | 3892 | rtl8168f_hw_phy_config(tp); |
c2218925 HW |
3893 | |
3894 | /* Improve 2-pair detection performance */ | |
3895 | rtl_writephy(tp, 0x1f, 0x0005); | |
3896 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3897 | rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); |
c2218925 HW |
3898 | rtl_writephy(tp, 0x1f, 0x0000); |
3899 | } | |
3900 | ||
3901 | static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) | |
3902 | { | |
3903 | rtl_apply_firmware(tp); | |
3904 | ||
5f886e08 | 3905 | rtl8168f_hw_phy_config(tp); |
c2218925 HW |
3906 | } |
3907 | ||
b3d7b2f2 HW |
3908 | static void rtl8411_hw_phy_config(struct rtl8169_private *tp) |
3909 | { | |
b3d7b2f2 HW |
3910 | static const struct phy_reg phy_reg_init[] = { |
3911 | /* Channel estimation fine tune */ | |
3912 | { 0x1f, 0x0003 }, | |
3913 | { 0x09, 0xa20f }, | |
3914 | { 0x1f, 0x0000 }, | |
3915 | ||
3916 | /* Modify green table for giga & fnet */ | |
3917 | { 0x1f, 0x0005 }, | |
3918 | { 0x05, 0x8b55 }, | |
3919 | { 0x06, 0x0000 }, | |
3920 | { 0x05, 0x8b5e }, | |
3921 | { 0x06, 0x0000 }, | |
3922 | { 0x05, 0x8b67 }, | |
3923 | { 0x06, 0x0000 }, | |
3924 | { 0x05, 0x8b70 }, | |
3925 | { 0x06, 0x0000 }, | |
3926 | { 0x1f, 0x0000 }, | |
3927 | { 0x1f, 0x0007 }, | |
3928 | { 0x1e, 0x0078 }, | |
3929 | { 0x17, 0x0000 }, | |
3930 | { 0x19, 0x00aa }, | |
3931 | { 0x1f, 0x0000 }, | |
3932 | ||
3933 | /* Modify green table for 10M */ | |
3934 | { 0x1f, 0x0005 }, | |
3935 | { 0x05, 0x8b79 }, | |
3936 | { 0x06, 0xaa00 }, | |
3937 | { 0x1f, 0x0000 }, | |
3938 | ||
3939 | /* Disable hiimpedance detection (RTCT) */ | |
3940 | { 0x1f, 0x0003 }, | |
3941 | { 0x01, 0x328a }, | |
3942 | { 0x1f, 0x0000 } | |
3943 | }; | |
3944 | ||
3945 | ||
3946 | rtl_apply_firmware(tp); | |
3947 | ||
3948 | rtl8168f_hw_phy_config(tp); | |
3949 | ||
3950 | /* Improve 2-pair detection performance */ | |
3951 | rtl_writephy(tp, 0x1f, 0x0005); | |
3952 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3953 | rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); |
b3d7b2f2 HW |
3954 | rtl_writephy(tp, 0x1f, 0x0000); |
3955 | ||
3956 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3957 | ||
3958 | /* Modify green table for giga */ | |
3959 | rtl_writephy(tp, 0x1f, 0x0005); | |
3960 | rtl_writephy(tp, 0x05, 0x8b54); | |
76564428 | 3961 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800); |
b3d7b2f2 | 3962 | rtl_writephy(tp, 0x05, 0x8b5d); |
76564428 | 3963 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800); |
b3d7b2f2 | 3964 | rtl_writephy(tp, 0x05, 0x8a7c); |
76564428 | 3965 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); |
b3d7b2f2 | 3966 | rtl_writephy(tp, 0x05, 0x8a7f); |
76564428 | 3967 | rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000); |
b3d7b2f2 | 3968 | rtl_writephy(tp, 0x05, 0x8a82); |
76564428 | 3969 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); |
b3d7b2f2 | 3970 | rtl_writephy(tp, 0x05, 0x8a85); |
76564428 | 3971 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); |
b3d7b2f2 | 3972 | rtl_writephy(tp, 0x05, 0x8a88); |
76564428 | 3973 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); |
b3d7b2f2 HW |
3974 | rtl_writephy(tp, 0x1f, 0x0000); |
3975 | ||
3976 | /* uc same-seed solution */ | |
3977 | rtl_writephy(tp, 0x1f, 0x0005); | |
3978 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3979 | rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000); |
b3d7b2f2 HW |
3980 | rtl_writephy(tp, 0x1f, 0x0000); |
3981 | ||
3982 | /* eee setting */ | |
706123d0 | 3983 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC); |
b3d7b2f2 HW |
3984 | rtl_writephy(tp, 0x1f, 0x0005); |
3985 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3986 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000); |
b3d7b2f2 HW |
3987 | rtl_writephy(tp, 0x1f, 0x0004); |
3988 | rtl_writephy(tp, 0x1f, 0x0007); | |
3989 | rtl_writephy(tp, 0x1e, 0x0020); | |
76564428 | 3990 | rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100); |
b3d7b2f2 HW |
3991 | rtl_writephy(tp, 0x1f, 0x0000); |
3992 | rtl_writephy(tp, 0x0d, 0x0007); | |
3993 | rtl_writephy(tp, 0x0e, 0x003c); | |
3994 | rtl_writephy(tp, 0x0d, 0x4007); | |
3995 | rtl_writephy(tp, 0x0e, 0x0000); | |
3996 | rtl_writephy(tp, 0x0d, 0x0000); | |
3997 | ||
3998 | /* Green feature */ | |
3999 | rtl_writephy(tp, 0x1f, 0x0003); | |
76564428 CHL |
4000 | rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001); |
4001 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400); | |
b3d7b2f2 HW |
4002 | rtl_writephy(tp, 0x1f, 0x0000); |
4003 | } | |
4004 | ||
c558386b HW |
4005 | static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp) |
4006 | { | |
c558386b HW |
4007 | rtl_apply_firmware(tp); |
4008 | ||
41f44d13 | 4009 | rtl_writephy(tp, 0x1f, 0x0a46); |
4010 | if (rtl_readphy(tp, 0x10) & 0x0100) { | |
4011 | rtl_writephy(tp, 0x1f, 0x0bcc); | |
76564428 | 4012 | rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000); |
41f44d13 | 4013 | } else { |
4014 | rtl_writephy(tp, 0x1f, 0x0bcc); | |
76564428 | 4015 | rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000); |
41f44d13 | 4016 | } |
c558386b | 4017 | |
41f44d13 | 4018 | rtl_writephy(tp, 0x1f, 0x0a46); |
4019 | if (rtl_readphy(tp, 0x13) & 0x0100) { | |
4020 | rtl_writephy(tp, 0x1f, 0x0c41); | |
76564428 | 4021 | rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000); |
41f44d13 | 4022 | } else { |
fe7524c0 | 4023 | rtl_writephy(tp, 0x1f, 0x0c41); |
76564428 | 4024 | rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002); |
41f44d13 | 4025 | } |
c558386b | 4026 | |
41f44d13 | 4027 | /* Enable PHY auto speed down */ |
4028 | rtl_writephy(tp, 0x1f, 0x0a44); | |
76564428 | 4029 | rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000); |
c558386b | 4030 | |
fe7524c0 | 4031 | rtl_writephy(tp, 0x1f, 0x0bcc); |
76564428 | 4032 | rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000); |
fe7524c0 | 4033 | rtl_writephy(tp, 0x1f, 0x0a44); |
76564428 | 4034 | rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000); |
fe7524c0 | 4035 | rtl_writephy(tp, 0x1f, 0x0a43); |
4036 | rtl_writephy(tp, 0x13, 0x8084); | |
76564428 CHL |
4037 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000); |
4038 | rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000); | |
fe7524c0 | 4039 | |
41f44d13 | 4040 | /* EEE auto-fallback function */ |
4041 | rtl_writephy(tp, 0x1f, 0x0a4b); | |
76564428 | 4042 | rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000); |
c558386b | 4043 | |
41f44d13 | 4044 | /* Enable UC LPF tune function */ |
4045 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4046 | rtl_writephy(tp, 0x13, 0x8012); | |
76564428 | 4047 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); |
41f44d13 | 4048 | |
4049 | rtl_writephy(tp, 0x1f, 0x0c42); | |
76564428 | 4050 | rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000); |
41f44d13 | 4051 | |
fe7524c0 | 4052 | /* Improve SWR Efficiency */ |
4053 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
4054 | rtl_writephy(tp, 0x14, 0x5065); | |
4055 | rtl_writephy(tp, 0x14, 0xd065); | |
4056 | rtl_writephy(tp, 0x1f, 0x0bc8); | |
4057 | rtl_writephy(tp, 0x11, 0x5655); | |
4058 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
4059 | rtl_writephy(tp, 0x14, 0x1065); | |
4060 | rtl_writephy(tp, 0x14, 0x9065); | |
4061 | rtl_writephy(tp, 0x14, 0x1065); | |
4062 | ||
1bac1072 DC |
4063 | /* Check ALDPS bit, disable it if enabled */ |
4064 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4065 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
76564428 | 4066 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004); |
1bac1072 | 4067 | |
41f44d13 | 4068 | rtl_writephy(tp, 0x1f, 0x0000); |
c558386b HW |
4069 | } |
4070 | ||
57538c4a | 4071 | static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp) |
4072 | { | |
4073 | rtl_apply_firmware(tp); | |
4074 | } | |
4075 | ||
6e1d0b89 CHL |
4076 | static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp) |
4077 | { | |
4078 | u16 dout_tapbin; | |
4079 | u32 data; | |
4080 | ||
4081 | rtl_apply_firmware(tp); | |
4082 | ||
4083 | /* CHN EST parameters adjust - giga master */ | |
4084 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4085 | rtl_writephy(tp, 0x13, 0x809b); | |
76564428 | 4086 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800); |
6e1d0b89 | 4087 | rtl_writephy(tp, 0x13, 0x80a2); |
76564428 | 4088 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00); |
6e1d0b89 | 4089 | rtl_writephy(tp, 0x13, 0x80a4); |
76564428 | 4090 | rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00); |
6e1d0b89 | 4091 | rtl_writephy(tp, 0x13, 0x809c); |
76564428 | 4092 | rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00); |
6e1d0b89 CHL |
4093 | rtl_writephy(tp, 0x1f, 0x0000); |
4094 | ||
4095 | /* CHN EST parameters adjust - giga slave */ | |
4096 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4097 | rtl_writephy(tp, 0x13, 0x80ad); | |
76564428 | 4098 | rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800); |
6e1d0b89 | 4099 | rtl_writephy(tp, 0x13, 0x80b4); |
76564428 | 4100 | rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00); |
6e1d0b89 | 4101 | rtl_writephy(tp, 0x13, 0x80ac); |
76564428 | 4102 | rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00); |
6e1d0b89 CHL |
4103 | rtl_writephy(tp, 0x1f, 0x0000); |
4104 | ||
4105 | /* CHN EST parameters adjust - fnet */ | |
4106 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4107 | rtl_writephy(tp, 0x13, 0x808e); | |
76564428 | 4108 | rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00); |
6e1d0b89 | 4109 | rtl_writephy(tp, 0x13, 0x8090); |
76564428 | 4110 | rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00); |
6e1d0b89 | 4111 | rtl_writephy(tp, 0x13, 0x8092); |
76564428 | 4112 | rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00); |
6e1d0b89 CHL |
4113 | rtl_writephy(tp, 0x1f, 0x0000); |
4114 | ||
4115 | /* enable R-tune & PGA-retune function */ | |
4116 | dout_tapbin = 0; | |
4117 | rtl_writephy(tp, 0x1f, 0x0a46); | |
4118 | data = rtl_readphy(tp, 0x13); | |
4119 | data &= 3; | |
4120 | data <<= 2; | |
4121 | dout_tapbin |= data; | |
4122 | data = rtl_readphy(tp, 0x12); | |
4123 | data &= 0xc000; | |
4124 | data >>= 14; | |
4125 | dout_tapbin |= data; | |
4126 | dout_tapbin = ~(dout_tapbin^0x08); | |
4127 | dout_tapbin <<= 12; | |
4128 | dout_tapbin &= 0xf000; | |
4129 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4130 | rtl_writephy(tp, 0x13, 0x827a); | |
76564428 | 4131 | rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); |
6e1d0b89 | 4132 | rtl_writephy(tp, 0x13, 0x827b); |
76564428 | 4133 | rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); |
6e1d0b89 | 4134 | rtl_writephy(tp, 0x13, 0x827c); |
76564428 | 4135 | rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); |
6e1d0b89 | 4136 | rtl_writephy(tp, 0x13, 0x827d); |
76564428 | 4137 | rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); |
6e1d0b89 CHL |
4138 | |
4139 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4140 | rtl_writephy(tp, 0x13, 0x0811); | |
76564428 | 4141 | rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000); |
6e1d0b89 | 4142 | rtl_writephy(tp, 0x1f, 0x0a42); |
76564428 | 4143 | rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000); |
6e1d0b89 CHL |
4144 | rtl_writephy(tp, 0x1f, 0x0000); |
4145 | ||
4146 | /* enable GPHY 10M */ | |
4147 | rtl_writephy(tp, 0x1f, 0x0a44); | |
76564428 | 4148 | rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000); |
6e1d0b89 CHL |
4149 | rtl_writephy(tp, 0x1f, 0x0000); |
4150 | ||
4151 | /* SAR ADC performance */ | |
4152 | rtl_writephy(tp, 0x1f, 0x0bca); | |
76564428 | 4153 | rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000); |
6e1d0b89 CHL |
4154 | rtl_writephy(tp, 0x1f, 0x0000); |
4155 | ||
4156 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4157 | rtl_writephy(tp, 0x13, 0x803f); | |
76564428 | 4158 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 4159 | rtl_writephy(tp, 0x13, 0x8047); |
76564428 | 4160 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 4161 | rtl_writephy(tp, 0x13, 0x804f); |
76564428 | 4162 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 4163 | rtl_writephy(tp, 0x13, 0x8057); |
76564428 | 4164 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 4165 | rtl_writephy(tp, 0x13, 0x805f); |
76564428 | 4166 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 4167 | rtl_writephy(tp, 0x13, 0x8067); |
76564428 | 4168 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 4169 | rtl_writephy(tp, 0x13, 0x806f); |
76564428 | 4170 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 CHL |
4171 | rtl_writephy(tp, 0x1f, 0x0000); |
4172 | ||
4173 | /* disable phy pfm mode */ | |
4174 | rtl_writephy(tp, 0x1f, 0x0a44); | |
c832c35f | 4175 | rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080); |
6e1d0b89 CHL |
4176 | rtl_writephy(tp, 0x1f, 0x0000); |
4177 | ||
4178 | /* Check ALDPS bit, disable it if enabled */ | |
4179 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4180 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
76564428 | 4181 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004); |
6e1d0b89 CHL |
4182 | |
4183 | rtl_writephy(tp, 0x1f, 0x0000); | |
4184 | } | |
4185 | ||
4186 | static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp) | |
4187 | { | |
4188 | u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0; | |
4189 | u16 rlen; | |
4190 | u32 data; | |
4191 | ||
4192 | rtl_apply_firmware(tp); | |
4193 | ||
4194 | /* CHIN EST parameter update */ | |
4195 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4196 | rtl_writephy(tp, 0x13, 0x808a); | |
76564428 | 4197 | rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f); |
6e1d0b89 CHL |
4198 | rtl_writephy(tp, 0x1f, 0x0000); |
4199 | ||
4200 | /* enable R-tune & PGA-retune function */ | |
4201 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4202 | rtl_writephy(tp, 0x13, 0x0811); | |
76564428 | 4203 | rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000); |
6e1d0b89 | 4204 | rtl_writephy(tp, 0x1f, 0x0a42); |
76564428 | 4205 | rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000); |
6e1d0b89 CHL |
4206 | rtl_writephy(tp, 0x1f, 0x0000); |
4207 | ||
4208 | /* enable GPHY 10M */ | |
4209 | rtl_writephy(tp, 0x1f, 0x0a44); | |
76564428 | 4210 | rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000); |
6e1d0b89 CHL |
4211 | rtl_writephy(tp, 0x1f, 0x0000); |
4212 | ||
4213 | r8168_mac_ocp_write(tp, 0xdd02, 0x807d); | |
4214 | data = r8168_mac_ocp_read(tp, 0xdd02); | |
4215 | ioffset_p3 = ((data & 0x80)>>7); | |
4216 | ioffset_p3 <<= 3; | |
4217 | ||
4218 | data = r8168_mac_ocp_read(tp, 0xdd00); | |
4219 | ioffset_p3 |= ((data & (0xe000))>>13); | |
4220 | ioffset_p2 = ((data & (0x1e00))>>9); | |
4221 | ioffset_p1 = ((data & (0x01e0))>>5); | |
4222 | ioffset_p0 = ((data & 0x0010)>>4); | |
4223 | ioffset_p0 <<= 3; | |
4224 | ioffset_p0 |= (data & (0x07)); | |
4225 | data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0); | |
4226 | ||
05b9687b | 4227 | if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) || |
e2e2788e | 4228 | (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) { |
6e1d0b89 CHL |
4229 | rtl_writephy(tp, 0x1f, 0x0bcf); |
4230 | rtl_writephy(tp, 0x16, data); | |
4231 | rtl_writephy(tp, 0x1f, 0x0000); | |
4232 | } | |
4233 | ||
4234 | /* Modify rlen (TX LPF corner frequency) level */ | |
4235 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
4236 | data = rtl_readphy(tp, 0x16); | |
4237 | data &= 0x000f; | |
4238 | rlen = 0; | |
4239 | if (data > 3) | |
4240 | rlen = data - 3; | |
4241 | data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12); | |
4242 | rtl_writephy(tp, 0x17, data); | |
4243 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
4244 | rtl_writephy(tp, 0x1f, 0x0000); | |
4245 | ||
4246 | /* disable phy pfm mode */ | |
4247 | rtl_writephy(tp, 0x1f, 0x0a44); | |
c832c35f | 4248 | rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080); |
6e1d0b89 CHL |
4249 | rtl_writephy(tp, 0x1f, 0x0000); |
4250 | ||
4251 | /* Check ALDPS bit, disable it if enabled */ | |
4252 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4253 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
76564428 | 4254 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004); |
6e1d0b89 CHL |
4255 | |
4256 | rtl_writephy(tp, 0x1f, 0x0000); | |
4257 | } | |
4258 | ||
935e2218 CHL |
4259 | static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp) |
4260 | { | |
4261 | /* Enable PHY auto speed down */ | |
4262 | rtl_writephy(tp, 0x1f, 0x0a44); | |
4263 | rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000); | |
4264 | rtl_writephy(tp, 0x1f, 0x0000); | |
4265 | ||
4266 | /* patch 10M & ALDPS */ | |
4267 | rtl_writephy(tp, 0x1f, 0x0bcc); | |
4268 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100); | |
4269 | rtl_writephy(tp, 0x1f, 0x0a44); | |
4270 | rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000); | |
4271 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4272 | rtl_writephy(tp, 0x13, 0x8084); | |
4273 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000); | |
4274 | rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000); | |
4275 | rtl_writephy(tp, 0x1f, 0x0000); | |
4276 | ||
4277 | /* Enable EEE auto-fallback function */ | |
4278 | rtl_writephy(tp, 0x1f, 0x0a4b); | |
4279 | rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000); | |
4280 | rtl_writephy(tp, 0x1f, 0x0000); | |
4281 | ||
4282 | /* Enable UC LPF tune function */ | |
4283 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4284 | rtl_writephy(tp, 0x13, 0x8012); | |
4285 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); | |
4286 | rtl_writephy(tp, 0x1f, 0x0000); | |
4287 | ||
4288 | /* set rg_sel_sdm_rate */ | |
4289 | rtl_writephy(tp, 0x1f, 0x0c42); | |
4290 | rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000); | |
4291 | rtl_writephy(tp, 0x1f, 0x0000); | |
4292 | ||
4293 | /* Check ALDPS bit, disable it if enabled */ | |
4294 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4295 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
4296 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004); | |
4297 | ||
4298 | rtl_writephy(tp, 0x1f, 0x0000); | |
4299 | } | |
4300 | ||
4301 | static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp) | |
4302 | { | |
4303 | /* patch 10M & ALDPS */ | |
4304 | rtl_writephy(tp, 0x1f, 0x0bcc); | |
4305 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100); | |
4306 | rtl_writephy(tp, 0x1f, 0x0a44); | |
4307 | rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000); | |
4308 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4309 | rtl_writephy(tp, 0x13, 0x8084); | |
4310 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000); | |
4311 | rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000); | |
4312 | rtl_writephy(tp, 0x1f, 0x0000); | |
4313 | ||
4314 | /* Enable UC LPF tune function */ | |
4315 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4316 | rtl_writephy(tp, 0x13, 0x8012); | |
4317 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); | |
4318 | rtl_writephy(tp, 0x1f, 0x0000); | |
4319 | ||
4320 | /* Set rg_sel_sdm_rate */ | |
4321 | rtl_writephy(tp, 0x1f, 0x0c42); | |
4322 | rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000); | |
4323 | rtl_writephy(tp, 0x1f, 0x0000); | |
4324 | ||
4325 | /* Channel estimation parameters */ | |
4326 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4327 | rtl_writephy(tp, 0x13, 0x80f3); | |
4328 | rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff); | |
4329 | rtl_writephy(tp, 0x13, 0x80f0); | |
4330 | rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff); | |
4331 | rtl_writephy(tp, 0x13, 0x80ef); | |
4332 | rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff); | |
4333 | rtl_writephy(tp, 0x13, 0x80f6); | |
4334 | rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff); | |
4335 | rtl_writephy(tp, 0x13, 0x80ec); | |
4336 | rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff); | |
4337 | rtl_writephy(tp, 0x13, 0x80ed); | |
4338 | rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff); | |
4339 | rtl_writephy(tp, 0x13, 0x80f2); | |
4340 | rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff); | |
4341 | rtl_writephy(tp, 0x13, 0x80f4); | |
4342 | rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff); | |
4343 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4344 | rtl_writephy(tp, 0x13, 0x8110); | |
4345 | rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff); | |
4346 | rtl_writephy(tp, 0x13, 0x810f); | |
4347 | rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff); | |
4348 | rtl_writephy(tp, 0x13, 0x8111); | |
4349 | rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff); | |
4350 | rtl_writephy(tp, 0x13, 0x8113); | |
4351 | rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff); | |
4352 | rtl_writephy(tp, 0x13, 0x8115); | |
4353 | rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff); | |
4354 | rtl_writephy(tp, 0x13, 0x810e); | |
4355 | rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff); | |
4356 | rtl_writephy(tp, 0x13, 0x810c); | |
4357 | rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff); | |
4358 | rtl_writephy(tp, 0x13, 0x810b); | |
4359 | rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff); | |
4360 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4361 | rtl_writephy(tp, 0x13, 0x80d1); | |
4362 | rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff); | |
4363 | rtl_writephy(tp, 0x13, 0x80cd); | |
4364 | rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff); | |
4365 | rtl_writephy(tp, 0x13, 0x80d3); | |
4366 | rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff); | |
4367 | rtl_writephy(tp, 0x13, 0x80d5); | |
4368 | rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff); | |
4369 | rtl_writephy(tp, 0x13, 0x80d7); | |
4370 | rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff); | |
4371 | ||
4372 | /* Force PWM-mode */ | |
4373 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
4374 | rtl_writephy(tp, 0x14, 0x5065); | |
4375 | rtl_writephy(tp, 0x14, 0xd065); | |
4376 | rtl_writephy(tp, 0x1f, 0x0bc8); | |
4377 | rtl_writephy(tp, 0x12, 0x00ed); | |
4378 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
4379 | rtl_writephy(tp, 0x14, 0x1065); | |
4380 | rtl_writephy(tp, 0x14, 0x9065); | |
4381 | rtl_writephy(tp, 0x14, 0x1065); | |
4382 | rtl_writephy(tp, 0x1f, 0x0000); | |
4383 | ||
4384 | /* Check ALDPS bit, disable it if enabled */ | |
4385 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4386 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
4387 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004); | |
4388 | ||
4389 | rtl_writephy(tp, 0x1f, 0x0000); | |
4390 | } | |
4391 | ||
4da19633 | 4392 | static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) |
2857ffb7 | 4393 | { |
350f7596 | 4394 | static const struct phy_reg phy_reg_init[] = { |
2857ffb7 FR |
4395 | { 0x1f, 0x0003 }, |
4396 | { 0x08, 0x441d }, | |
4397 | { 0x01, 0x9100 }, | |
4398 | { 0x1f, 0x0000 } | |
4399 | }; | |
4400 | ||
4da19633 | 4401 | rtl_writephy(tp, 0x1f, 0x0000); |
4402 | rtl_patchphy(tp, 0x11, 1 << 12); | |
4403 | rtl_patchphy(tp, 0x19, 1 << 13); | |
4404 | rtl_patchphy(tp, 0x10, 1 << 15); | |
2857ffb7 | 4405 | |
4da19633 | 4406 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2857ffb7 FR |
4407 | } |
4408 | ||
5a5e4443 HW |
4409 | static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) |
4410 | { | |
4411 | static const struct phy_reg phy_reg_init[] = { | |
4412 | { 0x1f, 0x0005 }, | |
4413 | { 0x1a, 0x0000 }, | |
4414 | { 0x1f, 0x0000 }, | |
4415 | ||
4416 | { 0x1f, 0x0004 }, | |
4417 | { 0x1c, 0x0000 }, | |
4418 | { 0x1f, 0x0000 }, | |
4419 | ||
4420 | { 0x1f, 0x0001 }, | |
4421 | { 0x15, 0x7701 }, | |
4422 | { 0x1f, 0x0000 } | |
4423 | }; | |
4424 | ||
4425 | /* Disable ALDPS before ram code */ | |
eef63cc1 FR |
4426 | rtl_writephy(tp, 0x1f, 0x0000); |
4427 | rtl_writephy(tp, 0x18, 0x0310); | |
4428 | msleep(100); | |
5a5e4443 | 4429 | |
953a12cc | 4430 | rtl_apply_firmware(tp); |
5a5e4443 HW |
4431 | |
4432 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
4433 | } | |
4434 | ||
7e18dca1 HW |
4435 | static void rtl8402_hw_phy_config(struct rtl8169_private *tp) |
4436 | { | |
7e18dca1 | 4437 | /* Disable ALDPS before setting firmware */ |
eef63cc1 FR |
4438 | rtl_writephy(tp, 0x1f, 0x0000); |
4439 | rtl_writephy(tp, 0x18, 0x0310); | |
4440 | msleep(20); | |
7e18dca1 HW |
4441 | |
4442 | rtl_apply_firmware(tp); | |
4443 | ||
4444 | /* EEE setting */ | |
fdf6fc06 | 4445 | rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
7e18dca1 HW |
4446 | rtl_writephy(tp, 0x1f, 0x0004); |
4447 | rtl_writephy(tp, 0x10, 0x401f); | |
4448 | rtl_writephy(tp, 0x19, 0x7030); | |
4449 | rtl_writephy(tp, 0x1f, 0x0000); | |
4450 | } | |
4451 | ||
5598bfe5 HW |
4452 | static void rtl8106e_hw_phy_config(struct rtl8169_private *tp) |
4453 | { | |
5598bfe5 HW |
4454 | static const struct phy_reg phy_reg_init[] = { |
4455 | { 0x1f, 0x0004 }, | |
4456 | { 0x10, 0xc07f }, | |
4457 | { 0x19, 0x7030 }, | |
4458 | { 0x1f, 0x0000 } | |
4459 | }; | |
4460 | ||
4461 | /* Disable ALDPS before ram code */ | |
eef63cc1 FR |
4462 | rtl_writephy(tp, 0x1f, 0x0000); |
4463 | rtl_writephy(tp, 0x18, 0x0310); | |
4464 | msleep(100); | |
5598bfe5 HW |
4465 | |
4466 | rtl_apply_firmware(tp); | |
4467 | ||
fdf6fc06 | 4468 | rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5598bfe5 HW |
4469 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
4470 | ||
fdf6fc06 | 4471 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5598bfe5 HW |
4472 | } |
4473 | ||
5615d9f1 FR |
4474 | static void rtl_hw_phy_config(struct net_device *dev) |
4475 | { | |
4476 | struct rtl8169_private *tp = netdev_priv(dev); | |
5615d9f1 FR |
4477 | |
4478 | rtl8169_print_mac_version(tp); | |
4479 | ||
4480 | switch (tp->mac_version) { | |
4481 | case RTL_GIGA_MAC_VER_01: | |
4482 | break; | |
4483 | case RTL_GIGA_MAC_VER_02: | |
4484 | case RTL_GIGA_MAC_VER_03: | |
4da19633 | 4485 | rtl8169s_hw_phy_config(tp); |
5615d9f1 FR |
4486 | break; |
4487 | case RTL_GIGA_MAC_VER_04: | |
4da19633 | 4488 | rtl8169sb_hw_phy_config(tp); |
5615d9f1 | 4489 | break; |
2e955856 | 4490 | case RTL_GIGA_MAC_VER_05: |
4da19633 | 4491 | rtl8169scd_hw_phy_config(tp); |
2e955856 | 4492 | break; |
8c7006aa | 4493 | case RTL_GIGA_MAC_VER_06: |
4da19633 | 4494 | rtl8169sce_hw_phy_config(tp); |
8c7006aa | 4495 | break; |
2857ffb7 FR |
4496 | case RTL_GIGA_MAC_VER_07: |
4497 | case RTL_GIGA_MAC_VER_08: | |
4498 | case RTL_GIGA_MAC_VER_09: | |
4da19633 | 4499 | rtl8102e_hw_phy_config(tp); |
2857ffb7 | 4500 | break; |
236b8082 | 4501 | case RTL_GIGA_MAC_VER_11: |
4da19633 | 4502 | rtl8168bb_hw_phy_config(tp); |
236b8082 FR |
4503 | break; |
4504 | case RTL_GIGA_MAC_VER_12: | |
4da19633 | 4505 | rtl8168bef_hw_phy_config(tp); |
236b8082 FR |
4506 | break; |
4507 | case RTL_GIGA_MAC_VER_17: | |
4da19633 | 4508 | rtl8168bef_hw_phy_config(tp); |
236b8082 | 4509 | break; |
867763c1 | 4510 | case RTL_GIGA_MAC_VER_18: |
4da19633 | 4511 | rtl8168cp_1_hw_phy_config(tp); |
867763c1 FR |
4512 | break; |
4513 | case RTL_GIGA_MAC_VER_19: | |
4da19633 | 4514 | rtl8168c_1_hw_phy_config(tp); |
867763c1 | 4515 | break; |
7da97ec9 | 4516 | case RTL_GIGA_MAC_VER_20: |
4da19633 | 4517 | rtl8168c_2_hw_phy_config(tp); |
7da97ec9 | 4518 | break; |
197ff761 | 4519 | case RTL_GIGA_MAC_VER_21: |
4da19633 | 4520 | rtl8168c_3_hw_phy_config(tp); |
197ff761 | 4521 | break; |
6fb07058 | 4522 | case RTL_GIGA_MAC_VER_22: |
4da19633 | 4523 | rtl8168c_4_hw_phy_config(tp); |
6fb07058 | 4524 | break; |
ef3386f0 | 4525 | case RTL_GIGA_MAC_VER_23: |
7f3e3d3a | 4526 | case RTL_GIGA_MAC_VER_24: |
4da19633 | 4527 | rtl8168cp_2_hw_phy_config(tp); |
ef3386f0 | 4528 | break; |
5b538df9 | 4529 | case RTL_GIGA_MAC_VER_25: |
bca03d5f | 4530 | rtl8168d_1_hw_phy_config(tp); |
daf9df6d | 4531 | break; |
4532 | case RTL_GIGA_MAC_VER_26: | |
bca03d5f | 4533 | rtl8168d_2_hw_phy_config(tp); |
daf9df6d | 4534 | break; |
4535 | case RTL_GIGA_MAC_VER_27: | |
4da19633 | 4536 | rtl8168d_3_hw_phy_config(tp); |
5b538df9 | 4537 | break; |
e6de30d6 | 4538 | case RTL_GIGA_MAC_VER_28: |
4539 | rtl8168d_4_hw_phy_config(tp); | |
4540 | break; | |
5a5e4443 HW |
4541 | case RTL_GIGA_MAC_VER_29: |
4542 | case RTL_GIGA_MAC_VER_30: | |
4543 | rtl8105e_hw_phy_config(tp); | |
4544 | break; | |
cecb5fd7 FR |
4545 | case RTL_GIGA_MAC_VER_31: |
4546 | /* None. */ | |
4547 | break; | |
01dc7fec | 4548 | case RTL_GIGA_MAC_VER_32: |
01dc7fec | 4549 | case RTL_GIGA_MAC_VER_33: |
70090424 HW |
4550 | rtl8168e_1_hw_phy_config(tp); |
4551 | break; | |
4552 | case RTL_GIGA_MAC_VER_34: | |
4553 | rtl8168e_2_hw_phy_config(tp); | |
01dc7fec | 4554 | break; |
c2218925 HW |
4555 | case RTL_GIGA_MAC_VER_35: |
4556 | rtl8168f_1_hw_phy_config(tp); | |
4557 | break; | |
4558 | case RTL_GIGA_MAC_VER_36: | |
4559 | rtl8168f_2_hw_phy_config(tp); | |
4560 | break; | |
ef3386f0 | 4561 | |
7e18dca1 HW |
4562 | case RTL_GIGA_MAC_VER_37: |
4563 | rtl8402_hw_phy_config(tp); | |
4564 | break; | |
4565 | ||
b3d7b2f2 HW |
4566 | case RTL_GIGA_MAC_VER_38: |
4567 | rtl8411_hw_phy_config(tp); | |
4568 | break; | |
4569 | ||
5598bfe5 HW |
4570 | case RTL_GIGA_MAC_VER_39: |
4571 | rtl8106e_hw_phy_config(tp); | |
4572 | break; | |
4573 | ||
c558386b HW |
4574 | case RTL_GIGA_MAC_VER_40: |
4575 | rtl8168g_1_hw_phy_config(tp); | |
4576 | break; | |
57538c4a | 4577 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 4578 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 4579 | case RTL_GIGA_MAC_VER_44: |
57538c4a | 4580 | rtl8168g_2_hw_phy_config(tp); |
4581 | break; | |
6e1d0b89 CHL |
4582 | case RTL_GIGA_MAC_VER_45: |
4583 | case RTL_GIGA_MAC_VER_47: | |
4584 | rtl8168h_1_hw_phy_config(tp); | |
4585 | break; | |
4586 | case RTL_GIGA_MAC_VER_46: | |
4587 | case RTL_GIGA_MAC_VER_48: | |
4588 | rtl8168h_2_hw_phy_config(tp); | |
4589 | break; | |
c558386b | 4590 | |
935e2218 CHL |
4591 | case RTL_GIGA_MAC_VER_49: |
4592 | rtl8168ep_1_hw_phy_config(tp); | |
4593 | break; | |
4594 | case RTL_GIGA_MAC_VER_50: | |
4595 | case RTL_GIGA_MAC_VER_51: | |
4596 | rtl8168ep_2_hw_phy_config(tp); | |
4597 | break; | |
4598 | ||
c558386b | 4599 | case RTL_GIGA_MAC_VER_41: |
5615d9f1 FR |
4600 | default: |
4601 | break; | |
4602 | } | |
4603 | } | |
4604 | ||
da78dbff | 4605 | static void rtl_phy_work(struct rtl8169_private *tp) |
1da177e4 | 4606 | { |
1da177e4 LT |
4607 | struct timer_list *timer = &tp->timer; |
4608 | void __iomem *ioaddr = tp->mmio_addr; | |
4609 | unsigned long timeout = RTL8169_PHY_TIMEOUT; | |
4610 | ||
bcf0bf90 | 4611 | assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
1da177e4 | 4612 | |
4da19633 | 4613 | if (tp->phy_reset_pending(tp)) { |
5b0384f4 | 4614 | /* |
1da177e4 LT |
4615 | * A busy loop could burn quite a few cycles on nowadays CPU. |
4616 | * Let's delay the execution of the timer for a few ticks. | |
4617 | */ | |
4618 | timeout = HZ/10; | |
4619 | goto out_mod_timer; | |
4620 | } | |
4621 | ||
4622 | if (tp->link_ok(ioaddr)) | |
da78dbff | 4623 | return; |
1da177e4 | 4624 | |
9bb8eeb5 | 4625 | netif_dbg(tp, link, tp->dev, "PHY reset until link up\n"); |
1da177e4 | 4626 | |
4da19633 | 4627 | tp->phy_reset_enable(tp); |
1da177e4 LT |
4628 | |
4629 | out_mod_timer: | |
4630 | mod_timer(timer, jiffies + timeout); | |
da78dbff FR |
4631 | } |
4632 | ||
4633 | static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) | |
4634 | { | |
da78dbff FR |
4635 | if (!test_and_set_bit(flag, tp->wk.flags)) |
4636 | schedule_work(&tp->wk.work); | |
da78dbff FR |
4637 | } |
4638 | ||
9de36ccf | 4639 | static void rtl8169_phy_timer(struct timer_list *t) |
da78dbff | 4640 | { |
9de36ccf | 4641 | struct rtl8169_private *tp = from_timer(tp, t, timer); |
da78dbff | 4642 | |
98ddf986 | 4643 | rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING); |
1da177e4 LT |
4644 | } |
4645 | ||
ffc46952 FR |
4646 | DECLARE_RTL_COND(rtl_phy_reset_cond) |
4647 | { | |
4648 | return tp->phy_reset_pending(tp); | |
4649 | } | |
4650 | ||
bf793295 FR |
4651 | static void rtl8169_phy_reset(struct net_device *dev, |
4652 | struct rtl8169_private *tp) | |
4653 | { | |
4da19633 | 4654 | tp->phy_reset_enable(tp); |
ffc46952 | 4655 | rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100); |
bf793295 FR |
4656 | } |
4657 | ||
2544bfc0 FR |
4658 | static bool rtl_tbi_enabled(struct rtl8169_private *tp) |
4659 | { | |
4660 | void __iomem *ioaddr = tp->mmio_addr; | |
4661 | ||
4662 | return (tp->mac_version == RTL_GIGA_MAC_VER_01) && | |
4663 | (RTL_R8(PHYstatus) & TBI_Enable); | |
4664 | } | |
4665 | ||
4ff96fa6 FR |
4666 | static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
4667 | { | |
4668 | void __iomem *ioaddr = tp->mmio_addr; | |
4ff96fa6 | 4669 | |
5615d9f1 | 4670 | rtl_hw_phy_config(dev); |
4ff96fa6 | 4671 | |
77332894 MS |
4672 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
4673 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); | |
4674 | RTL_W8(0x82, 0x01); | |
4675 | } | |
4ff96fa6 | 4676 | |
6dccd16b FR |
4677 | pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
4678 | ||
4679 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
4680 | pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); | |
4ff96fa6 | 4681 | |
bcf0bf90 | 4682 | if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
4ff96fa6 FR |
4683 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
4684 | RTL_W8(0x82, 0x01); | |
4685 | dprintk("Set PHY Reg 0x0bh = 0x00h\n"); | |
4da19633 | 4686 | rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 |
4ff96fa6 FR |
4687 | } |
4688 | ||
bf793295 FR |
4689 | rtl8169_phy_reset(dev, tp); |
4690 | ||
54405cde | 4691 | rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, |
cecb5fd7 FR |
4692 | ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
4693 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
4694 | (tp->mii.supports_gmii ? | |
4695 | ADVERTISED_1000baseT_Half | | |
4696 | ADVERTISED_1000baseT_Full : 0)); | |
4ff96fa6 | 4697 | |
2544bfc0 | 4698 | if (rtl_tbi_enabled(tp)) |
bf82c189 | 4699 | netif_info(tp, link, dev, "TBI auto-negotiating\n"); |
4ff96fa6 FR |
4700 | } |
4701 | ||
773d2021 FR |
4702 | static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
4703 | { | |
4704 | void __iomem *ioaddr = tp->mmio_addr; | |
773d2021 | 4705 | |
da78dbff | 4706 | rtl_lock_work(tp); |
773d2021 FR |
4707 | |
4708 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
908ba2bf | 4709 | |
9ecb9aab | 4710 | RTL_W32(MAC4, addr[4] | addr[5] << 8); |
908ba2bf | 4711 | RTL_R32(MAC4); |
4712 | ||
9ecb9aab | 4713 | RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); |
908ba2bf | 4714 | RTL_R32(MAC0); |
4715 | ||
9ecb9aab | 4716 | if (tp->mac_version == RTL_GIGA_MAC_VER_34) |
4717 | rtl_rar_exgmac_set(tp, addr); | |
c28aa385 | 4718 | |
773d2021 FR |
4719 | RTL_W8(Cfg9346, Cfg9346_Lock); |
4720 | ||
da78dbff | 4721 | rtl_unlock_work(tp); |
773d2021 FR |
4722 | } |
4723 | ||
4724 | static int rtl_set_mac_address(struct net_device *dev, void *p) | |
4725 | { | |
4726 | struct rtl8169_private *tp = netdev_priv(dev); | |
f51d4a10 | 4727 | struct device *d = &tp->pci_dev->dev; |
773d2021 FR |
4728 | struct sockaddr *addr = p; |
4729 | ||
4730 | if (!is_valid_ether_addr(addr->sa_data)) | |
4731 | return -EADDRNOTAVAIL; | |
4732 | ||
4733 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
4734 | ||
f51d4a10 CHL |
4735 | pm_runtime_get_noresume(d); |
4736 | ||
4737 | if (pm_runtime_active(d)) | |
4738 | rtl_rar_set(tp, dev->dev_addr); | |
4739 | ||
4740 | pm_runtime_put_noidle(d); | |
773d2021 FR |
4741 | |
4742 | return 0; | |
4743 | } | |
4744 | ||
5f787a1a FR |
4745 | static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
4746 | { | |
4747 | struct rtl8169_private *tp = netdev_priv(dev); | |
4748 | struct mii_ioctl_data *data = if_mii(ifr); | |
4749 | ||
8b4ab28d FR |
4750 | return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; |
4751 | } | |
5f787a1a | 4752 | |
cecb5fd7 FR |
4753 | static int rtl_xmii_ioctl(struct rtl8169_private *tp, |
4754 | struct mii_ioctl_data *data, int cmd) | |
8b4ab28d | 4755 | { |
5f787a1a FR |
4756 | switch (cmd) { |
4757 | case SIOCGMIIPHY: | |
4758 | data->phy_id = 32; /* Internal PHY */ | |
4759 | return 0; | |
4760 | ||
4761 | case SIOCGMIIREG: | |
4da19633 | 4762 | data->val_out = rtl_readphy(tp, data->reg_num & 0x1f); |
5f787a1a FR |
4763 | return 0; |
4764 | ||
4765 | case SIOCSMIIREG: | |
4da19633 | 4766 | rtl_writephy(tp, data->reg_num & 0x1f, data->val_in); |
5f787a1a FR |
4767 | return 0; |
4768 | } | |
4769 | return -EOPNOTSUPP; | |
4770 | } | |
4771 | ||
8b4ab28d FR |
4772 | static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
4773 | { | |
4774 | return -EOPNOTSUPP; | |
4775 | } | |
4776 | ||
baf63293 | 4777 | static void rtl_init_mdio_ops(struct rtl8169_private *tp) |
c0e45c1c | 4778 | { |
4779 | struct mdio_ops *ops = &tp->mdio_ops; | |
4780 | ||
4781 | switch (tp->mac_version) { | |
4782 | case RTL_GIGA_MAC_VER_27: | |
4783 | ops->write = r8168dp_1_mdio_write; | |
4784 | ops->read = r8168dp_1_mdio_read; | |
4785 | break; | |
e6de30d6 | 4786 | case RTL_GIGA_MAC_VER_28: |
4804b3b3 | 4787 | case RTL_GIGA_MAC_VER_31: |
e6de30d6 | 4788 | ops->write = r8168dp_2_mdio_write; |
4789 | ops->read = r8168dp_2_mdio_read; | |
4790 | break; | |
c558386b HW |
4791 | case RTL_GIGA_MAC_VER_40: |
4792 | case RTL_GIGA_MAC_VER_41: | |
57538c4a | 4793 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 4794 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 4795 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
4796 | case RTL_GIGA_MAC_VER_45: |
4797 | case RTL_GIGA_MAC_VER_46: | |
4798 | case RTL_GIGA_MAC_VER_47: | |
4799 | case RTL_GIGA_MAC_VER_48: | |
935e2218 CHL |
4800 | case RTL_GIGA_MAC_VER_49: |
4801 | case RTL_GIGA_MAC_VER_50: | |
4802 | case RTL_GIGA_MAC_VER_51: | |
c558386b HW |
4803 | ops->write = r8168g_mdio_write; |
4804 | ops->read = r8168g_mdio_read; | |
4805 | break; | |
c0e45c1c | 4806 | default: |
4807 | ops->write = r8169_mdio_write; | |
4808 | ops->read = r8169_mdio_read; | |
4809 | break; | |
4810 | } | |
4811 | } | |
4812 | ||
e2409d83 | 4813 | static void rtl_speed_down(struct rtl8169_private *tp) |
4814 | { | |
4815 | u32 adv; | |
4816 | int lpa; | |
4817 | ||
4818 | rtl_writephy(tp, 0x1f, 0x0000); | |
4819 | lpa = rtl_readphy(tp, MII_LPA); | |
4820 | ||
4821 | if (lpa & (LPA_10HALF | LPA_10FULL)) | |
4822 | adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full; | |
4823 | else if (lpa & (LPA_100HALF | LPA_100FULL)) | |
4824 | adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
4825 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; | |
4826 | else | |
4827 | adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
4828 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
4829 | (tp->mii.supports_gmii ? | |
4830 | ADVERTISED_1000baseT_Half | | |
4831 | ADVERTISED_1000baseT_Full : 0); | |
4832 | ||
4833 | rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, | |
4834 | adv); | |
4835 | } | |
4836 | ||
649b3b8c | 4837 | static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) |
4838 | { | |
4839 | void __iomem *ioaddr = tp->mmio_addr; | |
4840 | ||
4841 | switch (tp->mac_version) { | |
b00e69de CB |
4842 | case RTL_GIGA_MAC_VER_25: |
4843 | case RTL_GIGA_MAC_VER_26: | |
649b3b8c | 4844 | case RTL_GIGA_MAC_VER_29: |
4845 | case RTL_GIGA_MAC_VER_30: | |
4846 | case RTL_GIGA_MAC_VER_32: | |
4847 | case RTL_GIGA_MAC_VER_33: | |
4848 | case RTL_GIGA_MAC_VER_34: | |
7e18dca1 | 4849 | case RTL_GIGA_MAC_VER_37: |
b3d7b2f2 | 4850 | case RTL_GIGA_MAC_VER_38: |
5598bfe5 | 4851 | case RTL_GIGA_MAC_VER_39: |
c558386b HW |
4852 | case RTL_GIGA_MAC_VER_40: |
4853 | case RTL_GIGA_MAC_VER_41: | |
57538c4a | 4854 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 4855 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 4856 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
4857 | case RTL_GIGA_MAC_VER_45: |
4858 | case RTL_GIGA_MAC_VER_46: | |
4859 | case RTL_GIGA_MAC_VER_47: | |
4860 | case RTL_GIGA_MAC_VER_48: | |
935e2218 CHL |
4861 | case RTL_GIGA_MAC_VER_49: |
4862 | case RTL_GIGA_MAC_VER_50: | |
4863 | case RTL_GIGA_MAC_VER_51: | |
649b3b8c | 4864 | RTL_W32(RxConfig, RTL_R32(RxConfig) | |
4865 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys); | |
4866 | break; | |
4867 | default: | |
4868 | break; | |
4869 | } | |
4870 | } | |
4871 | ||
4872 | static bool rtl_wol_pll_power_down(struct rtl8169_private *tp) | |
4873 | { | |
4874 | if (!(__rtl8169_get_wol(tp) & WAKE_ANY)) | |
4875 | return false; | |
4876 | ||
e2409d83 | 4877 | rtl_speed_down(tp); |
649b3b8c | 4878 | rtl_wol_suspend_quirk(tp); |
4879 | ||
4880 | return true; | |
4881 | } | |
4882 | ||
065c27c1 | 4883 | static void r810x_phy_power_down(struct rtl8169_private *tp) |
4884 | { | |
4885 | rtl_writephy(tp, 0x1f, 0x0000); | |
4886 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
4887 | } | |
4888 | ||
4889 | static void r810x_phy_power_up(struct rtl8169_private *tp) | |
4890 | { | |
4891 | rtl_writephy(tp, 0x1f, 0x0000); | |
4892 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); | |
4893 | } | |
4894 | ||
4895 | static void r810x_pll_power_down(struct rtl8169_private *tp) | |
4896 | { | |
0004299a HW |
4897 | void __iomem *ioaddr = tp->mmio_addr; |
4898 | ||
649b3b8c | 4899 | if (rtl_wol_pll_power_down(tp)) |
065c27c1 | 4900 | return; |
065c27c1 | 4901 | |
4902 | r810x_phy_power_down(tp); | |
0004299a HW |
4903 | |
4904 | switch (tp->mac_version) { | |
4905 | case RTL_GIGA_MAC_VER_07: | |
4906 | case RTL_GIGA_MAC_VER_08: | |
4907 | case RTL_GIGA_MAC_VER_09: | |
4908 | case RTL_GIGA_MAC_VER_10: | |
4909 | case RTL_GIGA_MAC_VER_13: | |
4910 | case RTL_GIGA_MAC_VER_16: | |
4911 | break; | |
4912 | default: | |
4913 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); | |
4914 | break; | |
4915 | } | |
065c27c1 | 4916 | } |
4917 | ||
4918 | static void r810x_pll_power_up(struct rtl8169_private *tp) | |
4919 | { | |
0004299a HW |
4920 | void __iomem *ioaddr = tp->mmio_addr; |
4921 | ||
065c27c1 | 4922 | r810x_phy_power_up(tp); |
0004299a HW |
4923 | |
4924 | switch (tp->mac_version) { | |
4925 | case RTL_GIGA_MAC_VER_07: | |
4926 | case RTL_GIGA_MAC_VER_08: | |
4927 | case RTL_GIGA_MAC_VER_09: | |
4928 | case RTL_GIGA_MAC_VER_10: | |
4929 | case RTL_GIGA_MAC_VER_13: | |
4930 | case RTL_GIGA_MAC_VER_16: | |
4931 | break; | |
6e1d0b89 CHL |
4932 | case RTL_GIGA_MAC_VER_47: |
4933 | case RTL_GIGA_MAC_VER_48: | |
05b9687b | 4934 | RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0); |
6e1d0b89 | 4935 | break; |
0004299a HW |
4936 | default: |
4937 | RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); | |
4938 | break; | |
4939 | } | |
065c27c1 | 4940 | } |
4941 | ||
4942 | static void r8168_phy_power_up(struct rtl8169_private *tp) | |
4943 | { | |
4944 | rtl_writephy(tp, 0x1f, 0x0000); | |
01dc7fec | 4945 | switch (tp->mac_version) { |
4946 | case RTL_GIGA_MAC_VER_11: | |
4947 | case RTL_GIGA_MAC_VER_12: | |
4948 | case RTL_GIGA_MAC_VER_17: | |
4949 | case RTL_GIGA_MAC_VER_18: | |
4950 | case RTL_GIGA_MAC_VER_19: | |
4951 | case RTL_GIGA_MAC_VER_20: | |
4952 | case RTL_GIGA_MAC_VER_21: | |
4953 | case RTL_GIGA_MAC_VER_22: | |
4954 | case RTL_GIGA_MAC_VER_23: | |
4955 | case RTL_GIGA_MAC_VER_24: | |
4956 | case RTL_GIGA_MAC_VER_25: | |
4957 | case RTL_GIGA_MAC_VER_26: | |
4958 | case RTL_GIGA_MAC_VER_27: | |
4959 | case RTL_GIGA_MAC_VER_28: | |
4960 | case RTL_GIGA_MAC_VER_31: | |
4961 | rtl_writephy(tp, 0x0e, 0x0000); | |
4962 | break; | |
4963 | default: | |
4964 | break; | |
4965 | } | |
065c27c1 | 4966 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
4967 | } | |
4968 | ||
4969 | static void r8168_phy_power_down(struct rtl8169_private *tp) | |
4970 | { | |
4971 | rtl_writephy(tp, 0x1f, 0x0000); | |
01dc7fec | 4972 | switch (tp->mac_version) { |
4973 | case RTL_GIGA_MAC_VER_32: | |
4974 | case RTL_GIGA_MAC_VER_33: | |
beb330a4 | 4975 | case RTL_GIGA_MAC_VER_40: |
4976 | case RTL_GIGA_MAC_VER_41: | |
01dc7fec | 4977 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); |
4978 | break; | |
4979 | ||
4980 | case RTL_GIGA_MAC_VER_11: | |
4981 | case RTL_GIGA_MAC_VER_12: | |
4982 | case RTL_GIGA_MAC_VER_17: | |
4983 | case RTL_GIGA_MAC_VER_18: | |
4984 | case RTL_GIGA_MAC_VER_19: | |
4985 | case RTL_GIGA_MAC_VER_20: | |
4986 | case RTL_GIGA_MAC_VER_21: | |
4987 | case RTL_GIGA_MAC_VER_22: | |
4988 | case RTL_GIGA_MAC_VER_23: | |
4989 | case RTL_GIGA_MAC_VER_24: | |
4990 | case RTL_GIGA_MAC_VER_25: | |
4991 | case RTL_GIGA_MAC_VER_26: | |
4992 | case RTL_GIGA_MAC_VER_27: | |
4993 | case RTL_GIGA_MAC_VER_28: | |
4994 | case RTL_GIGA_MAC_VER_31: | |
4995 | rtl_writephy(tp, 0x0e, 0x0200); | |
4996 | default: | |
4997 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
4998 | break; | |
4999 | } | |
065c27c1 | 5000 | } |
5001 | ||
5002 | static void r8168_pll_power_down(struct rtl8169_private *tp) | |
5003 | { | |
5004 | void __iomem *ioaddr = tp->mmio_addr; | |
5005 | ||
cecb5fd7 FR |
5006 | if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
5007 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
935e2218 CHL |
5008 | tp->mac_version == RTL_GIGA_MAC_VER_31 || |
5009 | tp->mac_version == RTL_GIGA_MAC_VER_49 || | |
5010 | tp->mac_version == RTL_GIGA_MAC_VER_50 || | |
5011 | tp->mac_version == RTL_GIGA_MAC_VER_51) && | |
2f8c040c | 5012 | r8168_check_dash(tp)) { |
065c27c1 | 5013 | return; |
5d2e1957 | 5014 | } |
065c27c1 | 5015 | |
cecb5fd7 FR |
5016 | if ((tp->mac_version == RTL_GIGA_MAC_VER_23 || |
5017 | tp->mac_version == RTL_GIGA_MAC_VER_24) && | |
065c27c1 | 5018 | (RTL_R16(CPlusCmd) & ASF)) { |
5019 | return; | |
5020 | } | |
5021 | ||
01dc7fec | 5022 | if (tp->mac_version == RTL_GIGA_MAC_VER_32 || |
5023 | tp->mac_version == RTL_GIGA_MAC_VER_33) | |
fdf6fc06 | 5024 | rtl_ephy_write(tp, 0x19, 0xff64); |
01dc7fec | 5025 | |
649b3b8c | 5026 | if (rtl_wol_pll_power_down(tp)) |
065c27c1 | 5027 | return; |
065c27c1 | 5028 | |
5029 | r8168_phy_power_down(tp); | |
5030 | ||
5031 | switch (tp->mac_version) { | |
5032 | case RTL_GIGA_MAC_VER_25: | |
5033 | case RTL_GIGA_MAC_VER_26: | |
5d2e1957 HW |
5034 | case RTL_GIGA_MAC_VER_27: |
5035 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 5036 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 5037 | case RTL_GIGA_MAC_VER_32: |
5038 | case RTL_GIGA_MAC_VER_33: | |
42fde737 | 5039 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
5040 | case RTL_GIGA_MAC_VER_45: |
5041 | case RTL_GIGA_MAC_VER_46: | |
935e2218 CHL |
5042 | case RTL_GIGA_MAC_VER_50: |
5043 | case RTL_GIGA_MAC_VER_51: | |
065c27c1 | 5044 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
5045 | break; | |
beb330a4 | 5046 | case RTL_GIGA_MAC_VER_40: |
5047 | case RTL_GIGA_MAC_VER_41: | |
935e2218 | 5048 | case RTL_GIGA_MAC_VER_49: |
706123d0 | 5049 | rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000, |
beb330a4 | 5050 | 0xfc000000, ERIAR_EXGMAC); |
b8e5e6ad | 5051 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
beb330a4 | 5052 | break; |
065c27c1 | 5053 | } |
5054 | } | |
5055 | ||
5056 | static void r8168_pll_power_up(struct rtl8169_private *tp) | |
5057 | { | |
5058 | void __iomem *ioaddr = tp->mmio_addr; | |
5059 | ||
065c27c1 | 5060 | switch (tp->mac_version) { |
5061 | case RTL_GIGA_MAC_VER_25: | |
5062 | case RTL_GIGA_MAC_VER_26: | |
5d2e1957 HW |
5063 | case RTL_GIGA_MAC_VER_27: |
5064 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 5065 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 5066 | case RTL_GIGA_MAC_VER_32: |
5067 | case RTL_GIGA_MAC_VER_33: | |
065c27c1 | 5068 | RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); |
5069 | break; | |
42fde737 | 5070 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
5071 | case RTL_GIGA_MAC_VER_45: |
5072 | case RTL_GIGA_MAC_VER_46: | |
935e2218 CHL |
5073 | case RTL_GIGA_MAC_VER_50: |
5074 | case RTL_GIGA_MAC_VER_51: | |
05b9687b | 5075 | RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0); |
6e1d0b89 | 5076 | break; |
beb330a4 | 5077 | case RTL_GIGA_MAC_VER_40: |
5078 | case RTL_GIGA_MAC_VER_41: | |
935e2218 | 5079 | case RTL_GIGA_MAC_VER_49: |
b8e5e6ad | 5080 | RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0); |
706123d0 | 5081 | rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000, |
beb330a4 | 5082 | 0x00000000, ERIAR_EXGMAC); |
5083 | break; | |
065c27c1 | 5084 | } |
5085 | ||
5086 | r8168_phy_power_up(tp); | |
5087 | } | |
5088 | ||
d58d46b5 FR |
5089 | static void rtl_generic_op(struct rtl8169_private *tp, |
5090 | void (*op)(struct rtl8169_private *)) | |
065c27c1 | 5091 | { |
5092 | if (op) | |
5093 | op(tp); | |
5094 | } | |
5095 | ||
5096 | static void rtl_pll_power_down(struct rtl8169_private *tp) | |
5097 | { | |
d58d46b5 | 5098 | rtl_generic_op(tp, tp->pll_power_ops.down); |
065c27c1 | 5099 | } |
5100 | ||
5101 | static void rtl_pll_power_up(struct rtl8169_private *tp) | |
5102 | { | |
d58d46b5 | 5103 | rtl_generic_op(tp, tp->pll_power_ops.up); |
065c27c1 | 5104 | } |
5105 | ||
baf63293 | 5106 | static void rtl_init_pll_power_ops(struct rtl8169_private *tp) |
065c27c1 | 5107 | { |
5108 | struct pll_power_ops *ops = &tp->pll_power_ops; | |
5109 | ||
5110 | switch (tp->mac_version) { | |
5111 | case RTL_GIGA_MAC_VER_07: | |
5112 | case RTL_GIGA_MAC_VER_08: | |
5113 | case RTL_GIGA_MAC_VER_09: | |
5114 | case RTL_GIGA_MAC_VER_10: | |
5115 | case RTL_GIGA_MAC_VER_16: | |
5a5e4443 HW |
5116 | case RTL_GIGA_MAC_VER_29: |
5117 | case RTL_GIGA_MAC_VER_30: | |
7e18dca1 | 5118 | case RTL_GIGA_MAC_VER_37: |
5598bfe5 | 5119 | case RTL_GIGA_MAC_VER_39: |
58152cd4 | 5120 | case RTL_GIGA_MAC_VER_43: |
6e1d0b89 CHL |
5121 | case RTL_GIGA_MAC_VER_47: |
5122 | case RTL_GIGA_MAC_VER_48: | |
065c27c1 | 5123 | ops->down = r810x_pll_power_down; |
5124 | ops->up = r810x_pll_power_up; | |
5125 | break; | |
5126 | ||
5127 | case RTL_GIGA_MAC_VER_11: | |
5128 | case RTL_GIGA_MAC_VER_12: | |
5129 | case RTL_GIGA_MAC_VER_17: | |
5130 | case RTL_GIGA_MAC_VER_18: | |
5131 | case RTL_GIGA_MAC_VER_19: | |
5132 | case RTL_GIGA_MAC_VER_20: | |
5133 | case RTL_GIGA_MAC_VER_21: | |
5134 | case RTL_GIGA_MAC_VER_22: | |
5135 | case RTL_GIGA_MAC_VER_23: | |
5136 | case RTL_GIGA_MAC_VER_24: | |
5137 | case RTL_GIGA_MAC_VER_25: | |
5138 | case RTL_GIGA_MAC_VER_26: | |
5139 | case RTL_GIGA_MAC_VER_27: | |
e6de30d6 | 5140 | case RTL_GIGA_MAC_VER_28: |
4804b3b3 | 5141 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 5142 | case RTL_GIGA_MAC_VER_32: |
5143 | case RTL_GIGA_MAC_VER_33: | |
70090424 | 5144 | case RTL_GIGA_MAC_VER_34: |
c2218925 HW |
5145 | case RTL_GIGA_MAC_VER_35: |
5146 | case RTL_GIGA_MAC_VER_36: | |
b3d7b2f2 | 5147 | case RTL_GIGA_MAC_VER_38: |
c558386b HW |
5148 | case RTL_GIGA_MAC_VER_40: |
5149 | case RTL_GIGA_MAC_VER_41: | |
57538c4a | 5150 | case RTL_GIGA_MAC_VER_42: |
45dd95c4 | 5151 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
5152 | case RTL_GIGA_MAC_VER_45: |
5153 | case RTL_GIGA_MAC_VER_46: | |
935e2218 CHL |
5154 | case RTL_GIGA_MAC_VER_49: |
5155 | case RTL_GIGA_MAC_VER_50: | |
5156 | case RTL_GIGA_MAC_VER_51: | |
065c27c1 | 5157 | ops->down = r8168_pll_power_down; |
5158 | ops->up = r8168_pll_power_up; | |
5159 | break; | |
5160 | ||
5161 | default: | |
5162 | ops->down = NULL; | |
5163 | ops->up = NULL; | |
5164 | break; | |
5165 | } | |
5166 | } | |
5167 | ||
e542a226 HW |
5168 | static void rtl_init_rxcfg(struct rtl8169_private *tp) |
5169 | { | |
5170 | void __iomem *ioaddr = tp->mmio_addr; | |
5171 | ||
5172 | switch (tp->mac_version) { | |
5173 | case RTL_GIGA_MAC_VER_01: | |
5174 | case RTL_GIGA_MAC_VER_02: | |
5175 | case RTL_GIGA_MAC_VER_03: | |
5176 | case RTL_GIGA_MAC_VER_04: | |
5177 | case RTL_GIGA_MAC_VER_05: | |
5178 | case RTL_GIGA_MAC_VER_06: | |
5179 | case RTL_GIGA_MAC_VER_10: | |
5180 | case RTL_GIGA_MAC_VER_11: | |
5181 | case RTL_GIGA_MAC_VER_12: | |
5182 | case RTL_GIGA_MAC_VER_13: | |
5183 | case RTL_GIGA_MAC_VER_14: | |
5184 | case RTL_GIGA_MAC_VER_15: | |
5185 | case RTL_GIGA_MAC_VER_16: | |
5186 | case RTL_GIGA_MAC_VER_17: | |
5187 | RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); | |
5188 | break; | |
5189 | case RTL_GIGA_MAC_VER_18: | |
5190 | case RTL_GIGA_MAC_VER_19: | |
5191 | case RTL_GIGA_MAC_VER_20: | |
5192 | case RTL_GIGA_MAC_VER_21: | |
5193 | case RTL_GIGA_MAC_VER_22: | |
5194 | case RTL_GIGA_MAC_VER_23: | |
5195 | case RTL_GIGA_MAC_VER_24: | |
eb2dc35d | 5196 | case RTL_GIGA_MAC_VER_34: |
3ced8c95 | 5197 | case RTL_GIGA_MAC_VER_35: |
e542a226 HW |
5198 | RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); |
5199 | break; | |
beb330a4 | 5200 | case RTL_GIGA_MAC_VER_40: |
5201 | case RTL_GIGA_MAC_VER_41: | |
57538c4a | 5202 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 5203 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 5204 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
5205 | case RTL_GIGA_MAC_VER_45: |
5206 | case RTL_GIGA_MAC_VER_46: | |
5207 | case RTL_GIGA_MAC_VER_47: | |
5208 | case RTL_GIGA_MAC_VER_48: | |
935e2218 CHL |
5209 | case RTL_GIGA_MAC_VER_49: |
5210 | case RTL_GIGA_MAC_VER_50: | |
5211 | case RTL_GIGA_MAC_VER_51: | |
7ebc4822 | 5212 | RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); |
beb330a4 | 5213 | break; |
e542a226 HW |
5214 | default: |
5215 | RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST); | |
5216 | break; | |
5217 | } | |
5218 | } | |
5219 | ||
92fc43b4 HW |
5220 | static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
5221 | { | |
9fba0812 | 5222 | tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; |
92fc43b4 HW |
5223 | } |
5224 | ||
d58d46b5 FR |
5225 | static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) |
5226 | { | |
9c5028e9 | 5227 | void __iomem *ioaddr = tp->mmio_addr; |
5228 | ||
5229 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
d58d46b5 | 5230 | rtl_generic_op(tp, tp->jumbo_ops.enable); |
9c5028e9 | 5231 | RTL_W8(Cfg9346, Cfg9346_Lock); |
d58d46b5 FR |
5232 | } |
5233 | ||
5234 | static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) | |
5235 | { | |
9c5028e9 | 5236 | void __iomem *ioaddr = tp->mmio_addr; |
5237 | ||
5238 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
d58d46b5 | 5239 | rtl_generic_op(tp, tp->jumbo_ops.disable); |
9c5028e9 | 5240 | RTL_W8(Cfg9346, Cfg9346_Lock); |
d58d46b5 FR |
5241 | } |
5242 | ||
5243 | static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) | |
5244 | { | |
5245 | void __iomem *ioaddr = tp->mmio_addr; | |
5246 | ||
5247 | RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); | |
5248 | RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); | |
f65d539c | 5249 | rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B); |
d58d46b5 FR |
5250 | } |
5251 | ||
5252 | static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) | |
5253 | { | |
5254 | void __iomem *ioaddr = tp->mmio_addr; | |
5255 | ||
5256 | RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); | |
5257 | RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); | |
5258 | rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5259 | } | |
5260 | ||
5261 | static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) | |
5262 | { | |
5263 | void __iomem *ioaddr = tp->mmio_addr; | |
5264 | ||
5265 | RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); | |
5266 | } | |
5267 | ||
5268 | static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) | |
5269 | { | |
5270 | void __iomem *ioaddr = tp->mmio_addr; | |
5271 | ||
5272 | RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); | |
5273 | } | |
5274 | ||
5275 | static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) | |
5276 | { | |
5277 | void __iomem *ioaddr = tp->mmio_addr; | |
d58d46b5 FR |
5278 | |
5279 | RTL_W8(MaxTxPacketSize, 0x3f); | |
5280 | RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); | |
5281 | RTL_W8(Config4, RTL_R8(Config4) | 0x01); | |
f65d539c | 5282 | rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B); |
d58d46b5 FR |
5283 | } |
5284 | ||
5285 | static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) | |
5286 | { | |
5287 | void __iomem *ioaddr = tp->mmio_addr; | |
d58d46b5 FR |
5288 | |
5289 | RTL_W8(MaxTxPacketSize, 0x0c); | |
5290 | RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); | |
5291 | RTL_W8(Config4, RTL_R8(Config4) & ~0x01); | |
4512ff9f | 5292 | rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); |
d58d46b5 FR |
5293 | } |
5294 | ||
5295 | static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) | |
5296 | { | |
5297 | rtl_tx_performance_tweak(tp->pci_dev, | |
f65d539c | 5298 | PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN); |
d58d46b5 FR |
5299 | } |
5300 | ||
5301 | static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) | |
5302 | { | |
5303 | rtl_tx_performance_tweak(tp->pci_dev, | |
5304 | (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
5305 | } | |
5306 | ||
5307 | static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) | |
5308 | { | |
5309 | void __iomem *ioaddr = tp->mmio_addr; | |
5310 | ||
5311 | r8168b_0_hw_jumbo_enable(tp); | |
5312 | ||
5313 | RTL_W8(Config4, RTL_R8(Config4) | (1 << 0)); | |
5314 | } | |
5315 | ||
5316 | static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) | |
5317 | { | |
5318 | void __iomem *ioaddr = tp->mmio_addr; | |
5319 | ||
5320 | r8168b_0_hw_jumbo_disable(tp); | |
5321 | ||
5322 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | |
5323 | } | |
5324 | ||
baf63293 | 5325 | static void rtl_init_jumbo_ops(struct rtl8169_private *tp) |
d58d46b5 FR |
5326 | { |
5327 | struct jumbo_ops *ops = &tp->jumbo_ops; | |
5328 | ||
5329 | switch (tp->mac_version) { | |
5330 | case RTL_GIGA_MAC_VER_11: | |
5331 | ops->disable = r8168b_0_hw_jumbo_disable; | |
5332 | ops->enable = r8168b_0_hw_jumbo_enable; | |
5333 | break; | |
5334 | case RTL_GIGA_MAC_VER_12: | |
5335 | case RTL_GIGA_MAC_VER_17: | |
5336 | ops->disable = r8168b_1_hw_jumbo_disable; | |
5337 | ops->enable = r8168b_1_hw_jumbo_enable; | |
5338 | break; | |
5339 | case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */ | |
5340 | case RTL_GIGA_MAC_VER_19: | |
5341 | case RTL_GIGA_MAC_VER_20: | |
5342 | case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */ | |
5343 | case RTL_GIGA_MAC_VER_22: | |
5344 | case RTL_GIGA_MAC_VER_23: | |
5345 | case RTL_GIGA_MAC_VER_24: | |
5346 | case RTL_GIGA_MAC_VER_25: | |
5347 | case RTL_GIGA_MAC_VER_26: | |
5348 | ops->disable = r8168c_hw_jumbo_disable; | |
5349 | ops->enable = r8168c_hw_jumbo_enable; | |
5350 | break; | |
5351 | case RTL_GIGA_MAC_VER_27: | |
5352 | case RTL_GIGA_MAC_VER_28: | |
5353 | ops->disable = r8168dp_hw_jumbo_disable; | |
5354 | ops->enable = r8168dp_hw_jumbo_enable; | |
5355 | break; | |
5356 | case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */ | |
5357 | case RTL_GIGA_MAC_VER_32: | |
5358 | case RTL_GIGA_MAC_VER_33: | |
5359 | case RTL_GIGA_MAC_VER_34: | |
5360 | ops->disable = r8168e_hw_jumbo_disable; | |
5361 | ops->enable = r8168e_hw_jumbo_enable; | |
5362 | break; | |
5363 | ||
5364 | /* | |
5365 | * No action needed for jumbo frames with 8169. | |
5366 | * No jumbo for 810x at all. | |
5367 | */ | |
c558386b HW |
5368 | case RTL_GIGA_MAC_VER_40: |
5369 | case RTL_GIGA_MAC_VER_41: | |
57538c4a | 5370 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 5371 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 5372 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
5373 | case RTL_GIGA_MAC_VER_45: |
5374 | case RTL_GIGA_MAC_VER_46: | |
5375 | case RTL_GIGA_MAC_VER_47: | |
5376 | case RTL_GIGA_MAC_VER_48: | |
935e2218 CHL |
5377 | case RTL_GIGA_MAC_VER_49: |
5378 | case RTL_GIGA_MAC_VER_50: | |
5379 | case RTL_GIGA_MAC_VER_51: | |
d58d46b5 FR |
5380 | default: |
5381 | ops->disable = NULL; | |
5382 | ops->enable = NULL; | |
5383 | break; | |
5384 | } | |
5385 | } | |
5386 | ||
ffc46952 FR |
5387 | DECLARE_RTL_COND(rtl_chipcmd_cond) |
5388 | { | |
5389 | void __iomem *ioaddr = tp->mmio_addr; | |
5390 | ||
5391 | return RTL_R8(ChipCmd) & CmdReset; | |
5392 | } | |
5393 | ||
6f43adc8 FR |
5394 | static void rtl_hw_reset(struct rtl8169_private *tp) |
5395 | { | |
5396 | void __iomem *ioaddr = tp->mmio_addr; | |
6f43adc8 | 5397 | |
6f43adc8 FR |
5398 | RTL_W8(ChipCmd, CmdReset); |
5399 | ||
ffc46952 | 5400 | rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); |
6f43adc8 FR |
5401 | } |
5402 | ||
b6ffd97f | 5403 | static void rtl_request_uncached_firmware(struct rtl8169_private *tp) |
953a12cc | 5404 | { |
b6ffd97f FR |
5405 | struct rtl_fw *rtl_fw; |
5406 | const char *name; | |
5407 | int rc = -ENOMEM; | |
953a12cc | 5408 | |
b6ffd97f FR |
5409 | name = rtl_lookup_firmware_name(tp); |
5410 | if (!name) | |
5411 | goto out_no_firmware; | |
953a12cc | 5412 | |
b6ffd97f FR |
5413 | rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); |
5414 | if (!rtl_fw) | |
5415 | goto err_warn; | |
31bd204f | 5416 | |
b6ffd97f FR |
5417 | rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev); |
5418 | if (rc < 0) | |
5419 | goto err_free; | |
5420 | ||
fd112f2e FR |
5421 | rc = rtl_check_firmware(tp, rtl_fw); |
5422 | if (rc < 0) | |
5423 | goto err_release_firmware; | |
5424 | ||
b6ffd97f FR |
5425 | tp->rtl_fw = rtl_fw; |
5426 | out: | |
5427 | return; | |
5428 | ||
fd112f2e FR |
5429 | err_release_firmware: |
5430 | release_firmware(rtl_fw->fw); | |
b6ffd97f FR |
5431 | err_free: |
5432 | kfree(rtl_fw); | |
5433 | err_warn: | |
5434 | netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n", | |
5435 | name, rc); | |
5436 | out_no_firmware: | |
5437 | tp->rtl_fw = NULL; | |
5438 | goto out; | |
5439 | } | |
5440 | ||
5441 | static void rtl_request_firmware(struct rtl8169_private *tp) | |
5442 | { | |
5443 | if (IS_ERR(tp->rtl_fw)) | |
5444 | rtl_request_uncached_firmware(tp); | |
953a12cc FR |
5445 | } |
5446 | ||
92fc43b4 HW |
5447 | static void rtl_rx_close(struct rtl8169_private *tp) |
5448 | { | |
5449 | void __iomem *ioaddr = tp->mmio_addr; | |
92fc43b4 | 5450 | |
1687b566 | 5451 | RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK); |
92fc43b4 HW |
5452 | } |
5453 | ||
ffc46952 FR |
5454 | DECLARE_RTL_COND(rtl_npq_cond) |
5455 | { | |
5456 | void __iomem *ioaddr = tp->mmio_addr; | |
5457 | ||
5458 | return RTL_R8(TxPoll) & NPQ; | |
5459 | } | |
5460 | ||
5461 | DECLARE_RTL_COND(rtl_txcfg_empty_cond) | |
5462 | { | |
5463 | void __iomem *ioaddr = tp->mmio_addr; | |
5464 | ||
5465 | return RTL_R32(TxConfig) & TXCFG_EMPTY; | |
5466 | } | |
5467 | ||
e6de30d6 | 5468 | static void rtl8169_hw_reset(struct rtl8169_private *tp) |
1da177e4 | 5469 | { |
e6de30d6 | 5470 | void __iomem *ioaddr = tp->mmio_addr; |
5471 | ||
1da177e4 | 5472 | /* Disable interrupts */ |
811fd301 | 5473 | rtl8169_irq_mask_and_ack(tp); |
1da177e4 | 5474 | |
92fc43b4 HW |
5475 | rtl_rx_close(tp); |
5476 | ||
5d2e1957 | 5477 | if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
4804b3b3 | 5478 | tp->mac_version == RTL_GIGA_MAC_VER_28 || |
5479 | tp->mac_version == RTL_GIGA_MAC_VER_31) { | |
ffc46952 | 5480 | rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); |
c2218925 | 5481 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 || |
6e1d0b89 CHL |
5482 | tp->mac_version == RTL_GIGA_MAC_VER_35 || |
5483 | tp->mac_version == RTL_GIGA_MAC_VER_36 || | |
5484 | tp->mac_version == RTL_GIGA_MAC_VER_37 || | |
5485 | tp->mac_version == RTL_GIGA_MAC_VER_38 || | |
5486 | tp->mac_version == RTL_GIGA_MAC_VER_40 || | |
5487 | tp->mac_version == RTL_GIGA_MAC_VER_41 || | |
5488 | tp->mac_version == RTL_GIGA_MAC_VER_42 || | |
5489 | tp->mac_version == RTL_GIGA_MAC_VER_43 || | |
5490 | tp->mac_version == RTL_GIGA_MAC_VER_44 || | |
5491 | tp->mac_version == RTL_GIGA_MAC_VER_45 || | |
5492 | tp->mac_version == RTL_GIGA_MAC_VER_46 || | |
5493 | tp->mac_version == RTL_GIGA_MAC_VER_47 || | |
935e2218 CHL |
5494 | tp->mac_version == RTL_GIGA_MAC_VER_48 || |
5495 | tp->mac_version == RTL_GIGA_MAC_VER_49 || | |
5496 | tp->mac_version == RTL_GIGA_MAC_VER_50 || | |
5497 | tp->mac_version == RTL_GIGA_MAC_VER_51) { | |
c2b0c1e7 | 5498 | RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); |
ffc46952 | 5499 | rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); |
92fc43b4 HW |
5500 | } else { |
5501 | RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); | |
5502 | udelay(100); | |
e6de30d6 | 5503 | } |
5504 | ||
92fc43b4 | 5505 | rtl_hw_reset(tp); |
1da177e4 LT |
5506 | } |
5507 | ||
7f796d83 | 5508 | static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
9cb427b6 FR |
5509 | { |
5510 | void __iomem *ioaddr = tp->mmio_addr; | |
9cb427b6 FR |
5511 | |
5512 | /* Set DMA burst size and Interframe Gap Time */ | |
5513 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
5514 | (InterFrameGap << TxInterFrameGapShift)); | |
5515 | } | |
5516 | ||
07ce4064 | 5517 | static void rtl_hw_start(struct net_device *dev) |
1da177e4 LT |
5518 | { |
5519 | struct rtl8169_private *tp = netdev_priv(dev); | |
1da177e4 | 5520 | |
07ce4064 FR |
5521 | tp->hw_start(dev); |
5522 | ||
da78dbff | 5523 | rtl_irq_enable_all(tp); |
07ce4064 FR |
5524 | } |
5525 | ||
7f796d83 FR |
5526 | static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
5527 | void __iomem *ioaddr) | |
5528 | { | |
5529 | /* | |
5530 | * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh | |
5531 | * register to be written before TxDescAddrLow to work. | |
5532 | * Switching from MMIO to I/O access fixes the issue as well. | |
5533 | */ | |
5534 | RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); | |
284901a9 | 5535 | RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 | 5536 | RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
284901a9 | 5537 | RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 FR |
5538 | } |
5539 | ||
5540 | static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) | |
5541 | { | |
5542 | u16 cmd; | |
5543 | ||
5544 | cmd = RTL_R16(CPlusCmd); | |
5545 | RTL_W16(CPlusCmd, cmd); | |
5546 | return cmd; | |
5547 | } | |
5548 | ||
fdd7b4c3 | 5549 | static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) |
7f796d83 FR |
5550 | { |
5551 | /* Low hurts. Let's disable the filtering. */ | |
207d6e87 | 5552 | RTL_W16(RxMaxSize, rx_buf_sz + 1); |
7f796d83 FR |
5553 | } |
5554 | ||
6dccd16b FR |
5555 | static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
5556 | { | |
3744100e | 5557 | static const struct rtl_cfg2_info { |
6dccd16b FR |
5558 | u32 mac_version; |
5559 | u32 clk; | |
5560 | u32 val; | |
5561 | } cfg2_info [] = { | |
5562 | { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd | |
5563 | { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, | |
5564 | { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe | |
5565 | { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } | |
3744100e FR |
5566 | }; |
5567 | const struct rtl_cfg2_info *p = cfg2_info; | |
6dccd16b FR |
5568 | unsigned int i; |
5569 | u32 clk; | |
5570 | ||
5571 | clk = RTL_R8(Config2) & PCI_Clock_66MHz; | |
cadf1855 | 5572 | for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
6dccd16b FR |
5573 | if ((p->mac_version == mac_version) && (p->clk == clk)) { |
5574 | RTL_W32(0x7c, p->val); | |
5575 | break; | |
5576 | } | |
5577 | } | |
5578 | } | |
5579 | ||
e6b763ea FR |
5580 | static void rtl_set_rx_mode(struct net_device *dev) |
5581 | { | |
5582 | struct rtl8169_private *tp = netdev_priv(dev); | |
5583 | void __iomem *ioaddr = tp->mmio_addr; | |
5584 | u32 mc_filter[2]; /* Multicast hash filter */ | |
5585 | int rx_mode; | |
5586 | u32 tmp = 0; | |
5587 | ||
5588 | if (dev->flags & IFF_PROMISC) { | |
5589 | /* Unconditionally log net taps. */ | |
5590 | netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); | |
5591 | rx_mode = | |
5592 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | | |
5593 | AcceptAllPhys; | |
5594 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
5595 | } else if ((netdev_mc_count(dev) > multicast_filter_limit) || | |
5596 | (dev->flags & IFF_ALLMULTI)) { | |
5597 | /* Too many to filter perfectly -- accept all multicasts. */ | |
5598 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
5599 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
5600 | } else { | |
5601 | struct netdev_hw_addr *ha; | |
5602 | ||
5603 | rx_mode = AcceptBroadcast | AcceptMyPhys; | |
5604 | mc_filter[1] = mc_filter[0] = 0; | |
5605 | netdev_for_each_mc_addr(ha, dev) { | |
5606 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
5607 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
5608 | rx_mode |= AcceptMulticast; | |
5609 | } | |
5610 | } | |
5611 | ||
5612 | if (dev->features & NETIF_F_RXALL) | |
5613 | rx_mode |= (AcceptErr | AcceptRunt); | |
5614 | ||
5615 | tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode; | |
5616 | ||
5617 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) { | |
5618 | u32 data = mc_filter[0]; | |
5619 | ||
5620 | mc_filter[0] = swab32(mc_filter[1]); | |
5621 | mc_filter[1] = swab32(data); | |
5622 | } | |
5623 | ||
0481776b NW |
5624 | if (tp->mac_version == RTL_GIGA_MAC_VER_35) |
5625 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
5626 | ||
e6b763ea FR |
5627 | RTL_W32(MAR0 + 4, mc_filter[1]); |
5628 | RTL_W32(MAR0 + 0, mc_filter[0]); | |
5629 | ||
5630 | RTL_W32(RxConfig, tmp); | |
5631 | } | |
5632 | ||
07ce4064 FR |
5633 | static void rtl_hw_start_8169(struct net_device *dev) |
5634 | { | |
5635 | struct rtl8169_private *tp = netdev_priv(dev); | |
5636 | void __iomem *ioaddr = tp->mmio_addr; | |
5637 | struct pci_dev *pdev = tp->pci_dev; | |
07ce4064 | 5638 | |
9cb427b6 FR |
5639 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
5640 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); | |
5641 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); | |
5642 | } | |
5643 | ||
1da177e4 | 5644 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
cecb5fd7 FR |
5645 | if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
5646 | tp->mac_version == RTL_GIGA_MAC_VER_02 || | |
5647 | tp->mac_version == RTL_GIGA_MAC_VER_03 || | |
5648 | tp->mac_version == RTL_GIGA_MAC_VER_04) | |
9cb427b6 FR |
5649 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
5650 | ||
e542a226 HW |
5651 | rtl_init_rxcfg(tp); |
5652 | ||
f0298f81 | 5653 | RTL_W8(EarlyTxThres, NoEarlyTx); |
1da177e4 | 5654 | |
6f0333b8 | 5655 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
1da177e4 | 5656 | |
cecb5fd7 FR |
5657 | if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
5658 | tp->mac_version == RTL_GIGA_MAC_VER_02 || | |
5659 | tp->mac_version == RTL_GIGA_MAC_VER_03 || | |
5660 | tp->mac_version == RTL_GIGA_MAC_VER_04) | |
c946b304 | 5661 | rtl_set_rx_tx_config_registers(tp); |
1da177e4 | 5662 | |
7f796d83 | 5663 | tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
1da177e4 | 5664 | |
cecb5fd7 FR |
5665 | if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
5666 | tp->mac_version == RTL_GIGA_MAC_VER_03) { | |
05b9687b | 5667 | dprintk("Set MAC Reg C+CR Offset 0xe0. " |
1da177e4 | 5668 | "Bit-3 and bit-14 MUST be 1\n"); |
bcf0bf90 | 5669 | tp->cp_cmd |= (1 << 14); |
1da177e4 LT |
5670 | } |
5671 | ||
bcf0bf90 FR |
5672 | RTL_W16(CPlusCmd, tp->cp_cmd); |
5673 | ||
6dccd16b FR |
5674 | rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
5675 | ||
1da177e4 LT |
5676 | /* |
5677 | * Undocumented corner. Supposedly: | |
5678 | * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets | |
5679 | */ | |
5680 | RTL_W16(IntrMitigate, 0x0000); | |
5681 | ||
7f796d83 | 5682 | rtl_set_rx_tx_desc_registers(tp, ioaddr); |
9cb427b6 | 5683 | |
cecb5fd7 FR |
5684 | if (tp->mac_version != RTL_GIGA_MAC_VER_01 && |
5685 | tp->mac_version != RTL_GIGA_MAC_VER_02 && | |
5686 | tp->mac_version != RTL_GIGA_MAC_VER_03 && | |
5687 | tp->mac_version != RTL_GIGA_MAC_VER_04) { | |
c946b304 FR |
5688 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
5689 | rtl_set_rx_tx_config_registers(tp); | |
5690 | } | |
5691 | ||
1da177e4 | 5692 | RTL_W8(Cfg9346, Cfg9346_Lock); |
b518fa8e FR |
5693 | |
5694 | /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ | |
5695 | RTL_R8(IntrMask); | |
1da177e4 LT |
5696 | |
5697 | RTL_W32(RxMissed, 0); | |
5698 | ||
07ce4064 | 5699 | rtl_set_rx_mode(dev); |
1da177e4 LT |
5700 | |
5701 | /* no early-rx interrupts */ | |
05b9687b | 5702 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
07ce4064 | 5703 | } |
1da177e4 | 5704 | |
beb1fe18 HW |
5705 | static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) |
5706 | { | |
5707 | if (tp->csi_ops.write) | |
52989f0e | 5708 | tp->csi_ops.write(tp, addr, value); |
beb1fe18 HW |
5709 | } |
5710 | ||
5711 | static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) | |
5712 | { | |
52989f0e | 5713 | return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0; |
beb1fe18 HW |
5714 | } |
5715 | ||
5716 | static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits) | |
dacf8154 FR |
5717 | { |
5718 | u32 csi; | |
5719 | ||
beb1fe18 HW |
5720 | csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; |
5721 | rtl_csi_write(tp, 0x070c, csi | bits); | |
5722 | } | |
5723 | ||
5724 | static void rtl_csi_access_enable_1(struct rtl8169_private *tp) | |
5725 | { | |
5726 | rtl_csi_access_enable(tp, 0x17000000); | |
650e8d5d | 5727 | } |
5728 | ||
beb1fe18 | 5729 | static void rtl_csi_access_enable_2(struct rtl8169_private *tp) |
e6de30d6 | 5730 | { |
beb1fe18 | 5731 | rtl_csi_access_enable(tp, 0x27000000); |
e6de30d6 | 5732 | } |
5733 | ||
ffc46952 FR |
5734 | DECLARE_RTL_COND(rtl_csiar_cond) |
5735 | { | |
5736 | void __iomem *ioaddr = tp->mmio_addr; | |
5737 | ||
5738 | return RTL_R32(CSIAR) & CSIAR_FLAG; | |
5739 | } | |
5740 | ||
52989f0e | 5741 | static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value) |
650e8d5d | 5742 | { |
52989f0e | 5743 | void __iomem *ioaddr = tp->mmio_addr; |
beb1fe18 HW |
5744 | |
5745 | RTL_W32(CSIDR, value); | |
5746 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
5747 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
5748 | ||
ffc46952 | 5749 | rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); |
beb1fe18 HW |
5750 | } |
5751 | ||
52989f0e | 5752 | static u32 r8169_csi_read(struct rtl8169_private *tp, int addr) |
beb1fe18 | 5753 | { |
52989f0e | 5754 | void __iomem *ioaddr = tp->mmio_addr; |
beb1fe18 HW |
5755 | |
5756 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | | |
5757 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
5758 | ||
ffc46952 FR |
5759 | return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? |
5760 | RTL_R32(CSIDR) : ~0; | |
beb1fe18 HW |
5761 | } |
5762 | ||
52989f0e | 5763 | static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value) |
7e18dca1 | 5764 | { |
52989f0e | 5765 | void __iomem *ioaddr = tp->mmio_addr; |
7e18dca1 HW |
5766 | |
5767 | RTL_W32(CSIDR, value); | |
5768 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
5769 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT | | |
5770 | CSIAR_FUNC_NIC); | |
5771 | ||
ffc46952 | 5772 | rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); |
7e18dca1 HW |
5773 | } |
5774 | ||
52989f0e | 5775 | static u32 r8402_csi_read(struct rtl8169_private *tp, int addr) |
7e18dca1 | 5776 | { |
52989f0e | 5777 | void __iomem *ioaddr = tp->mmio_addr; |
7e18dca1 HW |
5778 | |
5779 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC | | |
5780 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
5781 | ||
ffc46952 FR |
5782 | return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? |
5783 | RTL_R32(CSIDR) : ~0; | |
7e18dca1 HW |
5784 | } |
5785 | ||
45dd95c4 | 5786 | static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value) |
5787 | { | |
5788 | void __iomem *ioaddr = tp->mmio_addr; | |
5789 | ||
5790 | RTL_W32(CSIDR, value); | |
5791 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
5792 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT | | |
5793 | CSIAR_FUNC_NIC2); | |
5794 | ||
5795 | rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); | |
5796 | } | |
5797 | ||
5798 | static u32 r8411_csi_read(struct rtl8169_private *tp, int addr) | |
5799 | { | |
5800 | void __iomem *ioaddr = tp->mmio_addr; | |
5801 | ||
5802 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 | | |
5803 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
5804 | ||
5805 | return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? | |
5806 | RTL_R32(CSIDR) : ~0; | |
5807 | } | |
5808 | ||
baf63293 | 5809 | static void rtl_init_csi_ops(struct rtl8169_private *tp) |
beb1fe18 HW |
5810 | { |
5811 | struct csi_ops *ops = &tp->csi_ops; | |
5812 | ||
5813 | switch (tp->mac_version) { | |
5814 | case RTL_GIGA_MAC_VER_01: | |
5815 | case RTL_GIGA_MAC_VER_02: | |
5816 | case RTL_GIGA_MAC_VER_03: | |
5817 | case RTL_GIGA_MAC_VER_04: | |
5818 | case RTL_GIGA_MAC_VER_05: | |
5819 | case RTL_GIGA_MAC_VER_06: | |
5820 | case RTL_GIGA_MAC_VER_10: | |
5821 | case RTL_GIGA_MAC_VER_11: | |
5822 | case RTL_GIGA_MAC_VER_12: | |
5823 | case RTL_GIGA_MAC_VER_13: | |
5824 | case RTL_GIGA_MAC_VER_14: | |
5825 | case RTL_GIGA_MAC_VER_15: | |
5826 | case RTL_GIGA_MAC_VER_16: | |
5827 | case RTL_GIGA_MAC_VER_17: | |
5828 | ops->write = NULL; | |
5829 | ops->read = NULL; | |
5830 | break; | |
5831 | ||
7e18dca1 | 5832 | case RTL_GIGA_MAC_VER_37: |
b3d7b2f2 | 5833 | case RTL_GIGA_MAC_VER_38: |
7e18dca1 HW |
5834 | ops->write = r8402_csi_write; |
5835 | ops->read = r8402_csi_read; | |
5836 | break; | |
5837 | ||
45dd95c4 | 5838 | case RTL_GIGA_MAC_VER_44: |
5839 | ops->write = r8411_csi_write; | |
5840 | ops->read = r8411_csi_read; | |
5841 | break; | |
5842 | ||
beb1fe18 HW |
5843 | default: |
5844 | ops->write = r8169_csi_write; | |
5845 | ops->read = r8169_csi_read; | |
5846 | break; | |
5847 | } | |
dacf8154 FR |
5848 | } |
5849 | ||
5850 | struct ephy_info { | |
5851 | unsigned int offset; | |
5852 | u16 mask; | |
5853 | u16 bits; | |
5854 | }; | |
5855 | ||
fdf6fc06 FR |
5856 | static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e, |
5857 | int len) | |
dacf8154 FR |
5858 | { |
5859 | u16 w; | |
5860 | ||
5861 | while (len-- > 0) { | |
fdf6fc06 FR |
5862 | w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; |
5863 | rtl_ephy_write(tp, e->offset, w); | |
dacf8154 FR |
5864 | e++; |
5865 | } | |
5866 | } | |
5867 | ||
b726e493 FR |
5868 | static void rtl_disable_clock_request(struct pci_dev *pdev) |
5869 | { | |
7d7903b2 JL |
5870 | pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, |
5871 | PCI_EXP_LNKCTL_CLKREQ_EN); | |
b726e493 FR |
5872 | } |
5873 | ||
e6de30d6 | 5874 | static void rtl_enable_clock_request(struct pci_dev *pdev) |
5875 | { | |
7d7903b2 JL |
5876 | pcie_capability_set_word(pdev, PCI_EXP_LNKCTL, |
5877 | PCI_EXP_LNKCTL_CLKREQ_EN); | |
e6de30d6 | 5878 | } |
5879 | ||
b51ecea8 | 5880 | static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable) |
5881 | { | |
5882 | void __iomem *ioaddr = tp->mmio_addr; | |
5883 | u8 data; | |
5884 | ||
5885 | data = RTL_R8(Config3); | |
5886 | ||
5887 | if (enable) | |
5888 | data |= Rdy_to_L23; | |
5889 | else | |
5890 | data &= ~Rdy_to_L23; | |
5891 | ||
5892 | RTL_W8(Config3, data); | |
5893 | } | |
5894 | ||
b726e493 FR |
5895 | #define R8168_CPCMD_QUIRK_MASK (\ |
5896 | EnableBist | \ | |
5897 | Mac_dbgo_oe | \ | |
5898 | Force_half_dup | \ | |
5899 | Force_rxflow_en | \ | |
5900 | Force_txflow_en | \ | |
5901 | Cxpl_dbg_sel | \ | |
5902 | ASF | \ | |
5903 | PktCntrDisable | \ | |
5904 | Mac_dbgo_sel) | |
5905 | ||
beb1fe18 | 5906 | static void rtl_hw_start_8168bb(struct rtl8169_private *tp) |
219a1e9d | 5907 | { |
beb1fe18 HW |
5908 | void __iomem *ioaddr = tp->mmio_addr; |
5909 | struct pci_dev *pdev = tp->pci_dev; | |
5910 | ||
b726e493 FR |
5911 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
5912 | ||
5913 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
5914 | ||
faf1e785 | 5915 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
5916 | rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) | | |
5917 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
5918 | } | |
219a1e9d FR |
5919 | } |
5920 | ||
beb1fe18 | 5921 | static void rtl_hw_start_8168bef(struct rtl8169_private *tp) |
219a1e9d | 5922 | { |
beb1fe18 HW |
5923 | void __iomem *ioaddr = tp->mmio_addr; |
5924 | ||
5925 | rtl_hw_start_8168bb(tp); | |
b726e493 | 5926 | |
f0298f81 | 5927 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
b726e493 FR |
5928 | |
5929 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | |
219a1e9d FR |
5930 | } |
5931 | ||
beb1fe18 | 5932 | static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) |
219a1e9d | 5933 | { |
beb1fe18 HW |
5934 | void __iomem *ioaddr = tp->mmio_addr; |
5935 | struct pci_dev *pdev = tp->pci_dev; | |
5936 | ||
b726e493 FR |
5937 | RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
5938 | ||
5939 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
5940 | ||
faf1e785 | 5941 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5942 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
b726e493 FR |
5943 | |
5944 | rtl_disable_clock_request(pdev); | |
5945 | ||
5946 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
219a1e9d FR |
5947 | } |
5948 | ||
beb1fe18 | 5949 | static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) |
219a1e9d | 5950 | { |
350f7596 | 5951 | static const struct ephy_info e_info_8168cp[] = { |
b726e493 FR |
5952 | { 0x01, 0, 0x0001 }, |
5953 | { 0x02, 0x0800, 0x1000 }, | |
5954 | { 0x03, 0, 0x0042 }, | |
5955 | { 0x06, 0x0080, 0x0000 }, | |
5956 | { 0x07, 0, 0x2000 } | |
5957 | }; | |
5958 | ||
beb1fe18 | 5959 | rtl_csi_access_enable_2(tp); |
b726e493 | 5960 | |
fdf6fc06 | 5961 | rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); |
b726e493 | 5962 | |
beb1fe18 | 5963 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
5964 | } |
5965 | ||
beb1fe18 | 5966 | static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) |
ef3386f0 | 5967 | { |
beb1fe18 HW |
5968 | void __iomem *ioaddr = tp->mmio_addr; |
5969 | struct pci_dev *pdev = tp->pci_dev; | |
5970 | ||
5971 | rtl_csi_access_enable_2(tp); | |
ef3386f0 FR |
5972 | |
5973 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
5974 | ||
faf1e785 | 5975 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5976 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
ef3386f0 FR |
5977 | |
5978 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
5979 | } | |
5980 | ||
beb1fe18 | 5981 | static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) |
7f3e3d3a | 5982 | { |
beb1fe18 HW |
5983 | void __iomem *ioaddr = tp->mmio_addr; |
5984 | struct pci_dev *pdev = tp->pci_dev; | |
5985 | ||
5986 | rtl_csi_access_enable_2(tp); | |
7f3e3d3a FR |
5987 | |
5988 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
5989 | ||
5990 | /* Magic. */ | |
5991 | RTL_W8(DBG_REG, 0x20); | |
5992 | ||
f0298f81 | 5993 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
7f3e3d3a | 5994 | |
faf1e785 | 5995 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5996 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
7f3e3d3a FR |
5997 | |
5998 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
5999 | } | |
6000 | ||
beb1fe18 | 6001 | static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) |
219a1e9d | 6002 | { |
beb1fe18 | 6003 | void __iomem *ioaddr = tp->mmio_addr; |
350f7596 | 6004 | static const struct ephy_info e_info_8168c_1[] = { |
b726e493 FR |
6005 | { 0x02, 0x0800, 0x1000 }, |
6006 | { 0x03, 0, 0x0002 }, | |
6007 | { 0x06, 0x0080, 0x0000 } | |
6008 | }; | |
6009 | ||
beb1fe18 | 6010 | rtl_csi_access_enable_2(tp); |
b726e493 FR |
6011 | |
6012 | RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); | |
6013 | ||
fdf6fc06 | 6014 | rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); |
b726e493 | 6015 | |
beb1fe18 | 6016 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
6017 | } |
6018 | ||
beb1fe18 | 6019 | static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) |
219a1e9d | 6020 | { |
350f7596 | 6021 | static const struct ephy_info e_info_8168c_2[] = { |
b726e493 FR |
6022 | { 0x01, 0, 0x0001 }, |
6023 | { 0x03, 0x0400, 0x0220 } | |
6024 | }; | |
6025 | ||
beb1fe18 | 6026 | rtl_csi_access_enable_2(tp); |
b726e493 | 6027 | |
fdf6fc06 | 6028 | rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); |
b726e493 | 6029 | |
beb1fe18 | 6030 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
6031 | } |
6032 | ||
beb1fe18 | 6033 | static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) |
197ff761 | 6034 | { |
beb1fe18 | 6035 | rtl_hw_start_8168c_2(tp); |
197ff761 FR |
6036 | } |
6037 | ||
beb1fe18 | 6038 | static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) |
6fb07058 | 6039 | { |
beb1fe18 | 6040 | rtl_csi_access_enable_2(tp); |
6fb07058 | 6041 | |
beb1fe18 | 6042 | __rtl_hw_start_8168cp(tp); |
6fb07058 FR |
6043 | } |
6044 | ||
beb1fe18 | 6045 | static void rtl_hw_start_8168d(struct rtl8169_private *tp) |
5b538df9 | 6046 | { |
beb1fe18 HW |
6047 | void __iomem *ioaddr = tp->mmio_addr; |
6048 | struct pci_dev *pdev = tp->pci_dev; | |
6049 | ||
6050 | rtl_csi_access_enable_2(tp); | |
5b538df9 FR |
6051 | |
6052 | rtl_disable_clock_request(pdev); | |
6053 | ||
f0298f81 | 6054 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
5b538df9 | 6055 | |
faf1e785 | 6056 | if (tp->dev->mtu <= ETH_DATA_LEN) |
6057 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5b538df9 FR |
6058 | |
6059 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
6060 | } | |
6061 | ||
beb1fe18 | 6062 | static void rtl_hw_start_8168dp(struct rtl8169_private *tp) |
4804b3b3 | 6063 | { |
beb1fe18 HW |
6064 | void __iomem *ioaddr = tp->mmio_addr; |
6065 | struct pci_dev *pdev = tp->pci_dev; | |
6066 | ||
6067 | rtl_csi_access_enable_1(tp); | |
4804b3b3 | 6068 | |
faf1e785 | 6069 | if (tp->dev->mtu <= ETH_DATA_LEN) |
6070 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4804b3b3 | 6071 | |
6072 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
6073 | ||
6074 | rtl_disable_clock_request(pdev); | |
6075 | } | |
6076 | ||
beb1fe18 | 6077 | static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) |
e6de30d6 | 6078 | { |
beb1fe18 HW |
6079 | void __iomem *ioaddr = tp->mmio_addr; |
6080 | struct pci_dev *pdev = tp->pci_dev; | |
e6de30d6 | 6081 | static const struct ephy_info e_info_8168d_4[] = { |
1016a4a1 CHL |
6082 | { 0x0b, 0x0000, 0x0048 }, |
6083 | { 0x19, 0x0020, 0x0050 }, | |
6084 | { 0x0c, 0x0100, 0x0020 } | |
e6de30d6 | 6085 | }; |
e6de30d6 | 6086 | |
beb1fe18 | 6087 | rtl_csi_access_enable_1(tp); |
e6de30d6 | 6088 | |
6089 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
6090 | ||
6091 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
6092 | ||
1016a4a1 | 6093 | rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4)); |
e6de30d6 | 6094 | |
6095 | rtl_enable_clock_request(pdev); | |
6096 | } | |
6097 | ||
beb1fe18 | 6098 | static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) |
01dc7fec | 6099 | { |
beb1fe18 HW |
6100 | void __iomem *ioaddr = tp->mmio_addr; |
6101 | struct pci_dev *pdev = tp->pci_dev; | |
70090424 | 6102 | static const struct ephy_info e_info_8168e_1[] = { |
01dc7fec | 6103 | { 0x00, 0x0200, 0x0100 }, |
6104 | { 0x00, 0x0000, 0x0004 }, | |
6105 | { 0x06, 0x0002, 0x0001 }, | |
6106 | { 0x06, 0x0000, 0x0030 }, | |
6107 | { 0x07, 0x0000, 0x2000 }, | |
6108 | { 0x00, 0x0000, 0x0020 }, | |
6109 | { 0x03, 0x5800, 0x2000 }, | |
6110 | { 0x03, 0x0000, 0x0001 }, | |
6111 | { 0x01, 0x0800, 0x1000 }, | |
6112 | { 0x07, 0x0000, 0x4000 }, | |
6113 | { 0x1e, 0x0000, 0x2000 }, | |
6114 | { 0x19, 0xffff, 0xfe6c }, | |
6115 | { 0x0a, 0x0000, 0x0040 } | |
6116 | }; | |
6117 | ||
beb1fe18 | 6118 | rtl_csi_access_enable_2(tp); |
01dc7fec | 6119 | |
fdf6fc06 | 6120 | rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); |
01dc7fec | 6121 | |
faf1e785 | 6122 | if (tp->dev->mtu <= ETH_DATA_LEN) |
6123 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
01dc7fec | 6124 | |
6125 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
6126 | ||
6127 | rtl_disable_clock_request(pdev); | |
6128 | ||
6129 | /* Reset tx FIFO pointer */ | |
cecb5fd7 FR |
6130 | RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST); |
6131 | RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST); | |
01dc7fec | 6132 | |
cecb5fd7 | 6133 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
01dc7fec | 6134 | } |
6135 | ||
beb1fe18 | 6136 | static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) |
70090424 | 6137 | { |
beb1fe18 HW |
6138 | void __iomem *ioaddr = tp->mmio_addr; |
6139 | struct pci_dev *pdev = tp->pci_dev; | |
70090424 HW |
6140 | static const struct ephy_info e_info_8168e_2[] = { |
6141 | { 0x09, 0x0000, 0x0080 }, | |
6142 | { 0x19, 0x0000, 0x0224 } | |
6143 | }; | |
6144 | ||
beb1fe18 | 6145 | rtl_csi_access_enable_1(tp); |
70090424 | 6146 | |
fdf6fc06 | 6147 | rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); |
70090424 | 6148 | |
faf1e785 | 6149 | if (tp->dev->mtu <= ETH_DATA_LEN) |
6150 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
70090424 | 6151 | |
fdf6fc06 FR |
6152 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
6153 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
6154 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); | |
6155 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
6156 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); | |
6157 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC); | |
706123d0 CHL |
6158 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
6159 | rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC); | |
70090424 | 6160 | |
3090bd9a | 6161 | RTL_W8(MaxTxPacketSize, EarlySize); |
70090424 | 6162 | |
4521e1a9 FR |
6163 | rtl_disable_clock_request(pdev); |
6164 | ||
70090424 HW |
6165 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
6166 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
6167 | ||
6168 | /* Adjust EEE LED frequency */ | |
6169 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
6170 | ||
6171 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); | |
6172 | RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); | |
4521e1a9 | 6173 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
70090424 HW |
6174 | } |
6175 | ||
5f886e08 | 6176 | static void rtl_hw_start_8168f(struct rtl8169_private *tp) |
c2218925 | 6177 | { |
beb1fe18 HW |
6178 | void __iomem *ioaddr = tp->mmio_addr; |
6179 | struct pci_dev *pdev = tp->pci_dev; | |
c2218925 | 6180 | |
5f886e08 | 6181 | rtl_csi_access_enable_2(tp); |
c2218925 HW |
6182 | |
6183 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
6184 | ||
fdf6fc06 FR |
6185 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
6186 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
6187 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); | |
6188 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
706123d0 CHL |
6189 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
6190 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
6191 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | |
6192 | rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | |
fdf6fc06 FR |
6193 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); |
6194 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC); | |
c2218925 HW |
6195 | |
6196 | RTL_W8(MaxTxPacketSize, EarlySize); | |
6197 | ||
4521e1a9 FR |
6198 | rtl_disable_clock_request(pdev); |
6199 | ||
c2218925 HW |
6200 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
6201 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
c2218925 | 6202 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
4521e1a9 FR |
6203 | RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); |
6204 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); | |
c2218925 HW |
6205 | } |
6206 | ||
5f886e08 HW |
6207 | static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) |
6208 | { | |
6209 | void __iomem *ioaddr = tp->mmio_addr; | |
6210 | static const struct ephy_info e_info_8168f_1[] = { | |
6211 | { 0x06, 0x00c0, 0x0020 }, | |
6212 | { 0x08, 0x0001, 0x0002 }, | |
6213 | { 0x09, 0x0000, 0x0080 }, | |
6214 | { 0x19, 0x0000, 0x0224 } | |
6215 | }; | |
6216 | ||
6217 | rtl_hw_start_8168f(tp); | |
6218 | ||
fdf6fc06 | 6219 | rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
5f886e08 | 6220 | |
706123d0 | 6221 | rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC); |
5f886e08 HW |
6222 | |
6223 | /* Adjust EEE LED frequency */ | |
6224 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
6225 | } | |
6226 | ||
b3d7b2f2 HW |
6227 | static void rtl_hw_start_8411(struct rtl8169_private *tp) |
6228 | { | |
b3d7b2f2 HW |
6229 | static const struct ephy_info e_info_8168f_1[] = { |
6230 | { 0x06, 0x00c0, 0x0020 }, | |
6231 | { 0x0f, 0xffff, 0x5200 }, | |
6232 | { 0x1e, 0x0000, 0x4000 }, | |
6233 | { 0x19, 0x0000, 0x0224 } | |
6234 | }; | |
6235 | ||
6236 | rtl_hw_start_8168f(tp); | |
b51ecea8 | 6237 | rtl_pcie_state_l2l3_enable(tp, false); |
b3d7b2f2 | 6238 | |
fdf6fc06 | 6239 | rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
b3d7b2f2 | 6240 | |
706123d0 | 6241 | rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC); |
b3d7b2f2 HW |
6242 | } |
6243 | ||
5fbea337 | 6244 | static void rtl_hw_start_8168g(struct rtl8169_private *tp) |
c558386b HW |
6245 | { |
6246 | void __iomem *ioaddr = tp->mmio_addr; | |
6247 | struct pci_dev *pdev = tp->pci_dev; | |
6248 | ||
beb330a4 | 6249 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
6250 | ||
c558386b HW |
6251 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC); |
6252 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC); | |
6253 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC); | |
6254 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
6255 | ||
6256 | rtl_csi_access_enable_1(tp); | |
6257 | ||
6258 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
6259 | ||
706123d0 CHL |
6260 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
6261 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
beb330a4 | 6262 | rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC); |
c558386b | 6263 | |
4521e1a9 | 6264 | RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN); |
c558386b HW |
6265 | RTL_W8(MaxTxPacketSize, EarlySize); |
6266 | ||
6267 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
6268 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
6269 | ||
6270 | /* Adjust EEE LED frequency */ | |
6271 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
6272 | ||
706123d0 CHL |
6273 | rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC); |
6274 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC); | |
b51ecea8 | 6275 | |
6276 | rtl_pcie_state_l2l3_enable(tp, false); | |
c558386b HW |
6277 | } |
6278 | ||
5fbea337 CHL |
6279 | static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) |
6280 | { | |
6281 | void __iomem *ioaddr = tp->mmio_addr; | |
6282 | static const struct ephy_info e_info_8168g_1[] = { | |
6283 | { 0x00, 0x0000, 0x0008 }, | |
6284 | { 0x0c, 0x37d0, 0x0820 }, | |
6285 | { 0x1e, 0x0000, 0x0001 }, | |
6286 | { 0x19, 0x8000, 0x0000 } | |
6287 | }; | |
6288 | ||
6289 | rtl_hw_start_8168g(tp); | |
6290 | ||
6291 | /* disable aspm and clock request before access ephy */ | |
6292 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
6293 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
6294 | rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1)); | |
6295 | } | |
6296 | ||
57538c4a | 6297 | static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) |
6298 | { | |
6299 | void __iomem *ioaddr = tp->mmio_addr; | |
6300 | static const struct ephy_info e_info_8168g_2[] = { | |
6301 | { 0x00, 0x0000, 0x0008 }, | |
6302 | { 0x0c, 0x3df0, 0x0200 }, | |
6303 | { 0x19, 0xffff, 0xfc00 }, | |
6304 | { 0x1e, 0xffff, 0x20eb } | |
6305 | }; | |
6306 | ||
5fbea337 | 6307 | rtl_hw_start_8168g(tp); |
57538c4a | 6308 | |
6309 | /* disable aspm and clock request before access ephy */ | |
6310 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
6311 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
6312 | rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2)); | |
6313 | } | |
6314 | ||
45dd95c4 | 6315 | static void rtl_hw_start_8411_2(struct rtl8169_private *tp) |
6316 | { | |
6317 | void __iomem *ioaddr = tp->mmio_addr; | |
6318 | static const struct ephy_info e_info_8411_2[] = { | |
6319 | { 0x00, 0x0000, 0x0008 }, | |
6320 | { 0x0c, 0x3df0, 0x0200 }, | |
6321 | { 0x0f, 0xffff, 0x5200 }, | |
6322 | { 0x19, 0x0020, 0x0000 }, | |
6323 | { 0x1e, 0x0000, 0x2000 } | |
6324 | }; | |
6325 | ||
5fbea337 | 6326 | rtl_hw_start_8168g(tp); |
45dd95c4 | 6327 | |
6328 | /* disable aspm and clock request before access ephy */ | |
6329 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
6330 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
6331 | rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2)); | |
6332 | } | |
6333 | ||
6e1d0b89 CHL |
6334 | static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) |
6335 | { | |
6336 | void __iomem *ioaddr = tp->mmio_addr; | |
6337 | struct pci_dev *pdev = tp->pci_dev; | |
72521ea0 | 6338 | int rg_saw_cnt; |
6e1d0b89 CHL |
6339 | u32 data; |
6340 | static const struct ephy_info e_info_8168h_1[] = { | |
6341 | { 0x1e, 0x0800, 0x0001 }, | |
6342 | { 0x1d, 0x0000, 0x0800 }, | |
6343 | { 0x05, 0xffff, 0x2089 }, | |
6344 | { 0x06, 0xffff, 0x5881 }, | |
6345 | { 0x04, 0xffff, 0x154a }, | |
6346 | { 0x01, 0xffff, 0x068b } | |
6347 | }; | |
6348 | ||
6349 | /* disable aspm and clock request before access ephy */ | |
6350 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
6351 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
6352 | rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1)); | |
6353 | ||
6354 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); | |
6355 | ||
6356 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC); | |
6357 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC); | |
6358 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC); | |
6359 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
6360 | ||
6361 | rtl_csi_access_enable_1(tp); | |
6362 | ||
6363 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
6364 | ||
706123d0 CHL |
6365 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
6366 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
6e1d0b89 | 6367 | |
706123d0 | 6368 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC); |
6e1d0b89 | 6369 | |
706123d0 | 6370 | rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC); |
6e1d0b89 CHL |
6371 | |
6372 | rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC); | |
6373 | ||
6e1d0b89 CHL |
6374 | RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN); |
6375 | RTL_W8(MaxTxPacketSize, EarlySize); | |
6376 | ||
6377 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
6378 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
6379 | ||
6380 | /* Adjust EEE LED frequency */ | |
6381 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
6382 | ||
6383 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN); | |
69f3dc37 | 6384 | RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN); |
6e1d0b89 CHL |
6385 | |
6386 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN); | |
6387 | ||
706123d0 | 6388 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC); |
6e1d0b89 CHL |
6389 | |
6390 | rtl_pcie_state_l2l3_enable(tp, false); | |
6391 | ||
6392 | rtl_writephy(tp, 0x1f, 0x0c42); | |
58493333 | 6393 | rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff); |
6e1d0b89 CHL |
6394 | rtl_writephy(tp, 0x1f, 0x0000); |
6395 | if (rg_saw_cnt > 0) { | |
6396 | u16 sw_cnt_1ms_ini; | |
6397 | ||
6398 | sw_cnt_1ms_ini = 16000000/rg_saw_cnt; | |
6399 | sw_cnt_1ms_ini &= 0x0fff; | |
6400 | data = r8168_mac_ocp_read(tp, 0xd412); | |
a2cb7ec0 | 6401 | data &= ~0x0fff; |
6e1d0b89 CHL |
6402 | data |= sw_cnt_1ms_ini; |
6403 | r8168_mac_ocp_write(tp, 0xd412, data); | |
6404 | } | |
6405 | ||
6406 | data = r8168_mac_ocp_read(tp, 0xe056); | |
a2cb7ec0 CHL |
6407 | data &= ~0xf0; |
6408 | data |= 0x70; | |
6e1d0b89 CHL |
6409 | r8168_mac_ocp_write(tp, 0xe056, data); |
6410 | ||
6411 | data = r8168_mac_ocp_read(tp, 0xe052); | |
a2cb7ec0 CHL |
6412 | data &= ~0x6000; |
6413 | data |= 0x8008; | |
6e1d0b89 CHL |
6414 | r8168_mac_ocp_write(tp, 0xe052, data); |
6415 | ||
6416 | data = r8168_mac_ocp_read(tp, 0xe0d6); | |
a2cb7ec0 | 6417 | data &= ~0x01ff; |
6e1d0b89 CHL |
6418 | data |= 0x017f; |
6419 | r8168_mac_ocp_write(tp, 0xe0d6, data); | |
6420 | ||
6421 | data = r8168_mac_ocp_read(tp, 0xd420); | |
a2cb7ec0 | 6422 | data &= ~0x0fff; |
6e1d0b89 CHL |
6423 | data |= 0x047f; |
6424 | r8168_mac_ocp_write(tp, 0xd420, data); | |
6425 | ||
6426 | r8168_mac_ocp_write(tp, 0xe63e, 0x0001); | |
6427 | r8168_mac_ocp_write(tp, 0xe63e, 0x0000); | |
6428 | r8168_mac_ocp_write(tp, 0xc094, 0x0000); | |
6429 | r8168_mac_ocp_write(tp, 0xc09e, 0x0000); | |
6430 | } | |
6431 | ||
935e2218 CHL |
6432 | static void rtl_hw_start_8168ep(struct rtl8169_private *tp) |
6433 | { | |
6434 | void __iomem *ioaddr = tp->mmio_addr; | |
6435 | struct pci_dev *pdev = tp->pci_dev; | |
6436 | ||
003609da CHL |
6437 | rtl8168ep_stop_cmac(tp); |
6438 | ||
935e2218 CHL |
6439 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
6440 | ||
6441 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC); | |
6442 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC); | |
6443 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC); | |
6444 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
6445 | ||
6446 | rtl_csi_access_enable_1(tp); | |
6447 | ||
6448 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
6449 | ||
6450 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); | |
6451 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
6452 | ||
6453 | rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC); | |
6454 | ||
6455 | rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC); | |
6456 | ||
935e2218 CHL |
6457 | RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN); |
6458 | RTL_W8(MaxTxPacketSize, EarlySize); | |
6459 | ||
6460 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
6461 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
6462 | ||
6463 | /* Adjust EEE LED frequency */ | |
6464 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
6465 | ||
6466 | rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC); | |
6467 | ||
6468 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN); | |
6469 | ||
6470 | rtl_pcie_state_l2l3_enable(tp, false); | |
6471 | } | |
6472 | ||
6473 | static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) | |
6474 | { | |
6475 | void __iomem *ioaddr = tp->mmio_addr; | |
6476 | static const struct ephy_info e_info_8168ep_1[] = { | |
6477 | { 0x00, 0xffff, 0x10ab }, | |
6478 | { 0x06, 0xffff, 0xf030 }, | |
6479 | { 0x08, 0xffff, 0x2006 }, | |
6480 | { 0x0d, 0xffff, 0x1666 }, | |
6481 | { 0x0c, 0x3ff0, 0x0000 } | |
6482 | }; | |
6483 | ||
6484 | /* disable aspm and clock request before access ephy */ | |
6485 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
6486 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
6487 | rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1)); | |
6488 | ||
6489 | rtl_hw_start_8168ep(tp); | |
6490 | } | |
6491 | ||
6492 | static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) | |
6493 | { | |
6494 | void __iomem *ioaddr = tp->mmio_addr; | |
6495 | static const struct ephy_info e_info_8168ep_2[] = { | |
6496 | { 0x00, 0xffff, 0x10a3 }, | |
6497 | { 0x19, 0xffff, 0xfc00 }, | |
6498 | { 0x1e, 0xffff, 0x20ea } | |
6499 | }; | |
6500 | ||
6501 | /* disable aspm and clock request before access ephy */ | |
6502 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
6503 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
6504 | rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2)); | |
6505 | ||
6506 | rtl_hw_start_8168ep(tp); | |
6507 | ||
6508 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN); | |
69f3dc37 | 6509 | RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN); |
935e2218 CHL |
6510 | } |
6511 | ||
6512 | static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) | |
6513 | { | |
6514 | void __iomem *ioaddr = tp->mmio_addr; | |
6515 | u32 data; | |
6516 | static const struct ephy_info e_info_8168ep_3[] = { | |
6517 | { 0x00, 0xffff, 0x10a3 }, | |
6518 | { 0x19, 0xffff, 0x7c00 }, | |
6519 | { 0x1e, 0xffff, 0x20eb }, | |
6520 | { 0x0d, 0xffff, 0x1666 } | |
6521 | }; | |
6522 | ||
6523 | /* disable aspm and clock request before access ephy */ | |
6524 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
6525 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
6526 | rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3)); | |
6527 | ||
6528 | rtl_hw_start_8168ep(tp); | |
6529 | ||
6530 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN); | |
69f3dc37 | 6531 | RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN); |
935e2218 CHL |
6532 | |
6533 | data = r8168_mac_ocp_read(tp, 0xd3e2); | |
6534 | data &= 0xf000; | |
6535 | data |= 0x0271; | |
6536 | r8168_mac_ocp_write(tp, 0xd3e2, data); | |
6537 | ||
6538 | data = r8168_mac_ocp_read(tp, 0xd3e4); | |
6539 | data &= 0xff00; | |
6540 | r8168_mac_ocp_write(tp, 0xd3e4, data); | |
6541 | ||
6542 | data = r8168_mac_ocp_read(tp, 0xe860); | |
6543 | data |= 0x0080; | |
6544 | r8168_mac_ocp_write(tp, 0xe860, data); | |
6545 | } | |
6546 | ||
07ce4064 FR |
6547 | static void rtl_hw_start_8168(struct net_device *dev) |
6548 | { | |
2dd99530 FR |
6549 | struct rtl8169_private *tp = netdev_priv(dev); |
6550 | void __iomem *ioaddr = tp->mmio_addr; | |
6551 | ||
6552 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
6553 | ||
f0298f81 | 6554 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
2dd99530 | 6555 | |
6f0333b8 | 6556 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
2dd99530 | 6557 | |
0e485150 | 6558 | tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
2dd99530 FR |
6559 | |
6560 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
6561 | ||
0e485150 | 6562 | RTL_W16(IntrMitigate, 0x5151); |
2dd99530 | 6563 | |
0e485150 | 6564 | /* Work around for RxFIFO overflow. */ |
811fd301 | 6565 | if (tp->mac_version == RTL_GIGA_MAC_VER_11) { |
da78dbff FR |
6566 | tp->event_slow |= RxFIFOOver | PCSTimeout; |
6567 | tp->event_slow &= ~RxOverflow; | |
0e485150 FR |
6568 | } |
6569 | ||
6570 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
2dd99530 | 6571 | |
1a964649 | 6572 | rtl_set_rx_tx_config_registers(tp); |
2dd99530 FR |
6573 | |
6574 | RTL_R8(IntrMask); | |
6575 | ||
219a1e9d FR |
6576 | switch (tp->mac_version) { |
6577 | case RTL_GIGA_MAC_VER_11: | |
beb1fe18 | 6578 | rtl_hw_start_8168bb(tp); |
4804b3b3 | 6579 | break; |
219a1e9d FR |
6580 | |
6581 | case RTL_GIGA_MAC_VER_12: | |
6582 | case RTL_GIGA_MAC_VER_17: | |
beb1fe18 | 6583 | rtl_hw_start_8168bef(tp); |
4804b3b3 | 6584 | break; |
219a1e9d FR |
6585 | |
6586 | case RTL_GIGA_MAC_VER_18: | |
beb1fe18 | 6587 | rtl_hw_start_8168cp_1(tp); |
4804b3b3 | 6588 | break; |
219a1e9d FR |
6589 | |
6590 | case RTL_GIGA_MAC_VER_19: | |
beb1fe18 | 6591 | rtl_hw_start_8168c_1(tp); |
4804b3b3 | 6592 | break; |
219a1e9d FR |
6593 | |
6594 | case RTL_GIGA_MAC_VER_20: | |
beb1fe18 | 6595 | rtl_hw_start_8168c_2(tp); |
4804b3b3 | 6596 | break; |
219a1e9d | 6597 | |
197ff761 | 6598 | case RTL_GIGA_MAC_VER_21: |
beb1fe18 | 6599 | rtl_hw_start_8168c_3(tp); |
4804b3b3 | 6600 | break; |
197ff761 | 6601 | |
6fb07058 | 6602 | case RTL_GIGA_MAC_VER_22: |
beb1fe18 | 6603 | rtl_hw_start_8168c_4(tp); |
4804b3b3 | 6604 | break; |
6fb07058 | 6605 | |
ef3386f0 | 6606 | case RTL_GIGA_MAC_VER_23: |
beb1fe18 | 6607 | rtl_hw_start_8168cp_2(tp); |
4804b3b3 | 6608 | break; |
ef3386f0 | 6609 | |
7f3e3d3a | 6610 | case RTL_GIGA_MAC_VER_24: |
beb1fe18 | 6611 | rtl_hw_start_8168cp_3(tp); |
4804b3b3 | 6612 | break; |
7f3e3d3a | 6613 | |
5b538df9 | 6614 | case RTL_GIGA_MAC_VER_25: |
daf9df6d | 6615 | case RTL_GIGA_MAC_VER_26: |
6616 | case RTL_GIGA_MAC_VER_27: | |
beb1fe18 | 6617 | rtl_hw_start_8168d(tp); |
4804b3b3 | 6618 | break; |
5b538df9 | 6619 | |
e6de30d6 | 6620 | case RTL_GIGA_MAC_VER_28: |
beb1fe18 | 6621 | rtl_hw_start_8168d_4(tp); |
4804b3b3 | 6622 | break; |
cecb5fd7 | 6623 | |
4804b3b3 | 6624 | case RTL_GIGA_MAC_VER_31: |
beb1fe18 | 6625 | rtl_hw_start_8168dp(tp); |
4804b3b3 | 6626 | break; |
6627 | ||
01dc7fec | 6628 | case RTL_GIGA_MAC_VER_32: |
6629 | case RTL_GIGA_MAC_VER_33: | |
beb1fe18 | 6630 | rtl_hw_start_8168e_1(tp); |
70090424 HW |
6631 | break; |
6632 | case RTL_GIGA_MAC_VER_34: | |
beb1fe18 | 6633 | rtl_hw_start_8168e_2(tp); |
01dc7fec | 6634 | break; |
e6de30d6 | 6635 | |
c2218925 HW |
6636 | case RTL_GIGA_MAC_VER_35: |
6637 | case RTL_GIGA_MAC_VER_36: | |
beb1fe18 | 6638 | rtl_hw_start_8168f_1(tp); |
c2218925 HW |
6639 | break; |
6640 | ||
b3d7b2f2 HW |
6641 | case RTL_GIGA_MAC_VER_38: |
6642 | rtl_hw_start_8411(tp); | |
6643 | break; | |
6644 | ||
c558386b HW |
6645 | case RTL_GIGA_MAC_VER_40: |
6646 | case RTL_GIGA_MAC_VER_41: | |
6647 | rtl_hw_start_8168g_1(tp); | |
6648 | break; | |
57538c4a | 6649 | case RTL_GIGA_MAC_VER_42: |
6650 | rtl_hw_start_8168g_2(tp); | |
6651 | break; | |
c558386b | 6652 | |
45dd95c4 | 6653 | case RTL_GIGA_MAC_VER_44: |
6654 | rtl_hw_start_8411_2(tp); | |
6655 | break; | |
6656 | ||
6e1d0b89 CHL |
6657 | case RTL_GIGA_MAC_VER_45: |
6658 | case RTL_GIGA_MAC_VER_46: | |
6659 | rtl_hw_start_8168h_1(tp); | |
6660 | break; | |
6661 | ||
935e2218 CHL |
6662 | case RTL_GIGA_MAC_VER_49: |
6663 | rtl_hw_start_8168ep_1(tp); | |
6664 | break; | |
6665 | ||
6666 | case RTL_GIGA_MAC_VER_50: | |
6667 | rtl_hw_start_8168ep_2(tp); | |
6668 | break; | |
6669 | ||
6670 | case RTL_GIGA_MAC_VER_51: | |
6671 | rtl_hw_start_8168ep_3(tp); | |
6672 | break; | |
6673 | ||
219a1e9d FR |
6674 | default: |
6675 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", | |
6676 | dev->name, tp->mac_version); | |
4804b3b3 | 6677 | break; |
219a1e9d | 6678 | } |
2dd99530 | 6679 | |
1a964649 | 6680 | RTL_W8(Cfg9346, Cfg9346_Lock); |
6681 | ||
0e485150 FR |
6682 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
6683 | ||
1a964649 | 6684 | rtl_set_rx_mode(dev); |
b8363901 | 6685 | |
05b9687b | 6686 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
07ce4064 | 6687 | } |
1da177e4 | 6688 | |
2857ffb7 FR |
6689 | #define R810X_CPCMD_QUIRK_MASK (\ |
6690 | EnableBist | \ | |
6691 | Mac_dbgo_oe | \ | |
6692 | Force_half_dup | \ | |
5edcc537 | 6693 | Force_rxflow_en | \ |
2857ffb7 FR |
6694 | Force_txflow_en | \ |
6695 | Cxpl_dbg_sel | \ | |
6696 | ASF | \ | |
6697 | PktCntrDisable | \ | |
d24e9aaf | 6698 | Mac_dbgo_sel) |
2857ffb7 | 6699 | |
beb1fe18 | 6700 | static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) |
2857ffb7 | 6701 | { |
beb1fe18 HW |
6702 | void __iomem *ioaddr = tp->mmio_addr; |
6703 | struct pci_dev *pdev = tp->pci_dev; | |
350f7596 | 6704 | static const struct ephy_info e_info_8102e_1[] = { |
2857ffb7 FR |
6705 | { 0x01, 0, 0x6e65 }, |
6706 | { 0x02, 0, 0x091f }, | |
6707 | { 0x03, 0, 0xc2f9 }, | |
6708 | { 0x06, 0, 0xafb5 }, | |
6709 | { 0x07, 0, 0x0e00 }, | |
6710 | { 0x19, 0, 0xec80 }, | |
6711 | { 0x01, 0, 0x2e65 }, | |
6712 | { 0x01, 0, 0x6e65 } | |
6713 | }; | |
6714 | u8 cfg1; | |
6715 | ||
beb1fe18 | 6716 | rtl_csi_access_enable_2(tp); |
2857ffb7 FR |
6717 | |
6718 | RTL_W8(DBG_REG, FIX_NAK_1); | |
6719 | ||
6720 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
6721 | ||
6722 | RTL_W8(Config1, | |
6723 | LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); | |
6724 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
6725 | ||
6726 | cfg1 = RTL_R8(Config1); | |
6727 | if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) | |
6728 | RTL_W8(Config1, cfg1 & ~LEDS0); | |
6729 | ||
fdf6fc06 | 6730 | rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
2857ffb7 FR |
6731 | } |
6732 | ||
beb1fe18 | 6733 | static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) |
2857ffb7 | 6734 | { |
beb1fe18 HW |
6735 | void __iomem *ioaddr = tp->mmio_addr; |
6736 | struct pci_dev *pdev = tp->pci_dev; | |
6737 | ||
6738 | rtl_csi_access_enable_2(tp); | |
2857ffb7 FR |
6739 | |
6740 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
6741 | ||
6742 | RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); | |
6743 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2857ffb7 FR |
6744 | } |
6745 | ||
beb1fe18 | 6746 | static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) |
2857ffb7 | 6747 | { |
beb1fe18 | 6748 | rtl_hw_start_8102e_2(tp); |
2857ffb7 | 6749 | |
fdf6fc06 | 6750 | rtl_ephy_write(tp, 0x03, 0xc2f9); |
2857ffb7 FR |
6751 | } |
6752 | ||
beb1fe18 | 6753 | static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) |
5a5e4443 | 6754 | { |
beb1fe18 | 6755 | void __iomem *ioaddr = tp->mmio_addr; |
5a5e4443 HW |
6756 | static const struct ephy_info e_info_8105e_1[] = { |
6757 | { 0x07, 0, 0x4000 }, | |
6758 | { 0x19, 0, 0x0200 }, | |
6759 | { 0x19, 0, 0x0020 }, | |
6760 | { 0x1e, 0, 0x2000 }, | |
6761 | { 0x03, 0, 0x0001 }, | |
6762 | { 0x19, 0, 0x0100 }, | |
6763 | { 0x19, 0, 0x0004 }, | |
6764 | { 0x0a, 0, 0x0020 } | |
6765 | }; | |
6766 | ||
cecb5fd7 | 6767 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ |
5a5e4443 HW |
6768 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); |
6769 | ||
cecb5fd7 | 6770 | /* Disable Early Tally Counter */ |
5a5e4443 HW |
6771 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000); |
6772 | ||
6773 | RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); | |
4f6b00e5 | 6774 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
5a5e4443 | 6775 | |
fdf6fc06 | 6776 | rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); |
b51ecea8 | 6777 | |
6778 | rtl_pcie_state_l2l3_enable(tp, false); | |
5a5e4443 HW |
6779 | } |
6780 | ||
beb1fe18 | 6781 | static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) |
5a5e4443 | 6782 | { |
beb1fe18 | 6783 | rtl_hw_start_8105e_1(tp); |
fdf6fc06 | 6784 | rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); |
5a5e4443 HW |
6785 | } |
6786 | ||
7e18dca1 HW |
6787 | static void rtl_hw_start_8402(struct rtl8169_private *tp) |
6788 | { | |
6789 | void __iomem *ioaddr = tp->mmio_addr; | |
6790 | static const struct ephy_info e_info_8402[] = { | |
6791 | { 0x19, 0xffff, 0xff64 }, | |
6792 | { 0x1e, 0, 0x4000 } | |
6793 | }; | |
6794 | ||
6795 | rtl_csi_access_enable_2(tp); | |
6796 | ||
6797 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ | |
6798 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); | |
6799 | ||
6800 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); | |
6801 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
6802 | ||
fdf6fc06 | 6803 | rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402)); |
7e18dca1 HW |
6804 | |
6805 | rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
6806 | ||
fdf6fc06 FR |
6807 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC); |
6808 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC); | |
706123d0 CHL |
6809 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
6810 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
fdf6fc06 FR |
6811 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
6812 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
706123d0 | 6813 | rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC); |
b51ecea8 | 6814 | |
6815 | rtl_pcie_state_l2l3_enable(tp, false); | |
7e18dca1 HW |
6816 | } |
6817 | ||
5598bfe5 HW |
6818 | static void rtl_hw_start_8106(struct rtl8169_private *tp) |
6819 | { | |
6820 | void __iomem *ioaddr = tp->mmio_addr; | |
6821 | ||
6822 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ | |
6823 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); | |
6824 | ||
4521e1a9 | 6825 | RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); |
5598bfe5 HW |
6826 | RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); |
6827 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN); | |
b51ecea8 | 6828 | |
6829 | rtl_pcie_state_l2l3_enable(tp, false); | |
5598bfe5 HW |
6830 | } |
6831 | ||
07ce4064 FR |
6832 | static void rtl_hw_start_8101(struct net_device *dev) |
6833 | { | |
cdf1a608 FR |
6834 | struct rtl8169_private *tp = netdev_priv(dev); |
6835 | void __iomem *ioaddr = tp->mmio_addr; | |
6836 | struct pci_dev *pdev = tp->pci_dev; | |
6837 | ||
da78dbff FR |
6838 | if (tp->mac_version >= RTL_GIGA_MAC_VER_30) |
6839 | tp->event_slow &= ~RxFIFOOver; | |
811fd301 | 6840 | |
cecb5fd7 | 6841 | if (tp->mac_version == RTL_GIGA_MAC_VER_13 || |
7d7903b2 | 6842 | tp->mac_version == RTL_GIGA_MAC_VER_16) |
8200bc72 BH |
6843 | pcie_capability_set_word(pdev, PCI_EXP_DEVCTL, |
6844 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
cdf1a608 | 6845 | |
d24e9aaf HW |
6846 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
6847 | ||
1a964649 | 6848 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
6849 | ||
6850 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); | |
6851 | ||
6852 | tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK; | |
6853 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
6854 | ||
6855 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
6856 | ||
6857 | rtl_set_rx_tx_config_registers(tp); | |
6858 | ||
2857ffb7 FR |
6859 | switch (tp->mac_version) { |
6860 | case RTL_GIGA_MAC_VER_07: | |
beb1fe18 | 6861 | rtl_hw_start_8102e_1(tp); |
2857ffb7 FR |
6862 | break; |
6863 | ||
6864 | case RTL_GIGA_MAC_VER_08: | |
beb1fe18 | 6865 | rtl_hw_start_8102e_3(tp); |
2857ffb7 FR |
6866 | break; |
6867 | ||
6868 | case RTL_GIGA_MAC_VER_09: | |
beb1fe18 | 6869 | rtl_hw_start_8102e_2(tp); |
2857ffb7 | 6870 | break; |
5a5e4443 HW |
6871 | |
6872 | case RTL_GIGA_MAC_VER_29: | |
beb1fe18 | 6873 | rtl_hw_start_8105e_1(tp); |
5a5e4443 HW |
6874 | break; |
6875 | case RTL_GIGA_MAC_VER_30: | |
beb1fe18 | 6876 | rtl_hw_start_8105e_2(tp); |
5a5e4443 | 6877 | break; |
7e18dca1 HW |
6878 | |
6879 | case RTL_GIGA_MAC_VER_37: | |
6880 | rtl_hw_start_8402(tp); | |
6881 | break; | |
5598bfe5 HW |
6882 | |
6883 | case RTL_GIGA_MAC_VER_39: | |
6884 | rtl_hw_start_8106(tp); | |
6885 | break; | |
58152cd4 | 6886 | case RTL_GIGA_MAC_VER_43: |
6887 | rtl_hw_start_8168g_2(tp); | |
6888 | break; | |
6e1d0b89 CHL |
6889 | case RTL_GIGA_MAC_VER_47: |
6890 | case RTL_GIGA_MAC_VER_48: | |
6891 | rtl_hw_start_8168h_1(tp); | |
6892 | break; | |
cdf1a608 FR |
6893 | } |
6894 | ||
d24e9aaf | 6895 | RTL_W8(Cfg9346, Cfg9346_Lock); |
cdf1a608 | 6896 | |
cdf1a608 FR |
6897 | RTL_W16(IntrMitigate, 0x0000); |
6898 | ||
cdf1a608 | 6899 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
cdf1a608 | 6900 | |
cdf1a608 FR |
6901 | rtl_set_rx_mode(dev); |
6902 | ||
1a964649 | 6903 | RTL_R8(IntrMask); |
6904 | ||
cdf1a608 | 6905 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
1da177e4 LT |
6906 | } |
6907 | ||
6908 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) | |
6909 | { | |
d58d46b5 FR |
6910 | struct rtl8169_private *tp = netdev_priv(dev); |
6911 | ||
d58d46b5 FR |
6912 | if (new_mtu > ETH_DATA_LEN) |
6913 | rtl_hw_jumbo_enable(tp); | |
6914 | else | |
6915 | rtl_hw_jumbo_disable(tp); | |
6916 | ||
1da177e4 | 6917 | dev->mtu = new_mtu; |
350fb32a MM |
6918 | netdev_update_features(dev); |
6919 | ||
323bb685 | 6920 | return 0; |
1da177e4 LT |
6921 | } |
6922 | ||
6923 | static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) | |
6924 | { | |
95e0918d | 6925 | desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
1da177e4 LT |
6926 | desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
6927 | } | |
6928 | ||
6f0333b8 ED |
6929 | static void rtl8169_free_rx_databuff(struct rtl8169_private *tp, |
6930 | void **data_buff, struct RxDesc *desc) | |
1da177e4 | 6931 | { |
48addcc9 | 6932 | dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz, |
231aee63 | 6933 | DMA_FROM_DEVICE); |
48addcc9 | 6934 | |
6f0333b8 ED |
6935 | kfree(*data_buff); |
6936 | *data_buff = NULL; | |
1da177e4 LT |
6937 | rtl8169_make_unusable_by_asic(desc); |
6938 | } | |
6939 | ||
6940 | static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) | |
6941 | { | |
6942 | u32 eor = le32_to_cpu(desc->opts1) & RingEnd; | |
6943 | ||
a0750138 AD |
6944 | /* Force memory writes to complete before releasing descriptor */ |
6945 | dma_wmb(); | |
6946 | ||
1da177e4 LT |
6947 | desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); |
6948 | } | |
6949 | ||
6950 | static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, | |
6951 | u32 rx_buf_sz) | |
6952 | { | |
6953 | desc->addr = cpu_to_le64(mapping); | |
1da177e4 LT |
6954 | rtl8169_mark_to_asic(desc, rx_buf_sz); |
6955 | } | |
6956 | ||
6f0333b8 ED |
6957 | static inline void *rtl8169_align(void *data) |
6958 | { | |
6959 | return (void *)ALIGN((long)data, 16); | |
6960 | } | |
6961 | ||
0ecbe1ca SG |
6962 | static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp, |
6963 | struct RxDesc *desc) | |
1da177e4 | 6964 | { |
6f0333b8 | 6965 | void *data; |
1da177e4 | 6966 | dma_addr_t mapping; |
48addcc9 | 6967 | struct device *d = &tp->pci_dev->dev; |
0ecbe1ca | 6968 | struct net_device *dev = tp->dev; |
6f0333b8 | 6969 | int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1; |
1da177e4 | 6970 | |
6f0333b8 ED |
6971 | data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); |
6972 | if (!data) | |
6973 | return NULL; | |
e9f63f30 | 6974 | |
6f0333b8 ED |
6975 | if (rtl8169_align(data) != data) { |
6976 | kfree(data); | |
6977 | data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node); | |
6978 | if (!data) | |
6979 | return NULL; | |
6980 | } | |
3eafe507 | 6981 | |
48addcc9 | 6982 | mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz, |
231aee63 | 6983 | DMA_FROM_DEVICE); |
d827d86b SG |
6984 | if (unlikely(dma_mapping_error(d, mapping))) { |
6985 | if (net_ratelimit()) | |
6986 | netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); | |
3eafe507 | 6987 | goto err_out; |
d827d86b | 6988 | } |
1da177e4 LT |
6989 | |
6990 | rtl8169_map_to_asic(desc, mapping, rx_buf_sz); | |
6f0333b8 | 6991 | return data; |
3eafe507 SG |
6992 | |
6993 | err_out: | |
6994 | kfree(data); | |
6995 | return NULL; | |
1da177e4 LT |
6996 | } |
6997 | ||
6998 | static void rtl8169_rx_clear(struct rtl8169_private *tp) | |
6999 | { | |
07d3f51f | 7000 | unsigned int i; |
1da177e4 LT |
7001 | |
7002 | for (i = 0; i < NUM_RX_DESC; i++) { | |
6f0333b8 ED |
7003 | if (tp->Rx_databuff[i]) { |
7004 | rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i, | |
1da177e4 LT |
7005 | tp->RxDescArray + i); |
7006 | } | |
7007 | } | |
7008 | } | |
7009 | ||
0ecbe1ca | 7010 | static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
1da177e4 | 7011 | { |
0ecbe1ca SG |
7012 | desc->opts1 |= cpu_to_le32(RingEnd); |
7013 | } | |
5b0384f4 | 7014 | |
0ecbe1ca SG |
7015 | static int rtl8169_rx_fill(struct rtl8169_private *tp) |
7016 | { | |
7017 | unsigned int i; | |
1da177e4 | 7018 | |
0ecbe1ca SG |
7019 | for (i = 0; i < NUM_RX_DESC; i++) { |
7020 | void *data; | |
4ae47c2d | 7021 | |
6f0333b8 | 7022 | if (tp->Rx_databuff[i]) |
1da177e4 | 7023 | continue; |
bcf0bf90 | 7024 | |
0ecbe1ca | 7025 | data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); |
6f0333b8 ED |
7026 | if (!data) { |
7027 | rtl8169_make_unusable_by_asic(tp->RxDescArray + i); | |
0ecbe1ca | 7028 | goto err_out; |
6f0333b8 ED |
7029 | } |
7030 | tp->Rx_databuff[i] = data; | |
1da177e4 | 7031 | } |
1da177e4 | 7032 | |
0ecbe1ca SG |
7033 | rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
7034 | return 0; | |
7035 | ||
7036 | err_out: | |
7037 | rtl8169_rx_clear(tp); | |
7038 | return -ENOMEM; | |
1da177e4 LT |
7039 | } |
7040 | ||
1da177e4 LT |
7041 | static int rtl8169_init_ring(struct net_device *dev) |
7042 | { | |
7043 | struct rtl8169_private *tp = netdev_priv(dev); | |
7044 | ||
7045 | rtl8169_init_ring_indexes(tp); | |
7046 | ||
7047 | memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); | |
6f0333b8 | 7048 | memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *)); |
1da177e4 | 7049 | |
0ecbe1ca | 7050 | return rtl8169_rx_fill(tp); |
1da177e4 LT |
7051 | } |
7052 | ||
48addcc9 | 7053 | static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, |
1da177e4 LT |
7054 | struct TxDesc *desc) |
7055 | { | |
7056 | unsigned int len = tx_skb->len; | |
7057 | ||
48addcc9 SG |
7058 | dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); |
7059 | ||
1da177e4 LT |
7060 | desc->opts1 = 0x00; |
7061 | desc->opts2 = 0x00; | |
7062 | desc->addr = 0x00; | |
7063 | tx_skb->len = 0; | |
7064 | } | |
7065 | ||
3eafe507 SG |
7066 | static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, |
7067 | unsigned int n) | |
1da177e4 LT |
7068 | { |
7069 | unsigned int i; | |
7070 | ||
3eafe507 SG |
7071 | for (i = 0; i < n; i++) { |
7072 | unsigned int entry = (start + i) % NUM_TX_DESC; | |
1da177e4 LT |
7073 | struct ring_info *tx_skb = tp->tx_skb + entry; |
7074 | unsigned int len = tx_skb->len; | |
7075 | ||
7076 | if (len) { | |
7077 | struct sk_buff *skb = tx_skb->skb; | |
7078 | ||
48addcc9 | 7079 | rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
1da177e4 LT |
7080 | tp->TxDescArray + entry); |
7081 | if (skb) { | |
7a4b813c | 7082 | dev_consume_skb_any(skb); |
1da177e4 LT |
7083 | tx_skb->skb = NULL; |
7084 | } | |
1da177e4 LT |
7085 | } |
7086 | } | |
3eafe507 SG |
7087 | } |
7088 | ||
7089 | static void rtl8169_tx_clear(struct rtl8169_private *tp) | |
7090 | { | |
7091 | rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); | |
1da177e4 LT |
7092 | tp->cur_tx = tp->dirty_tx = 0; |
7093 | } | |
7094 | ||
4422bcd4 | 7095 | static void rtl_reset_work(struct rtl8169_private *tp) |
1da177e4 | 7096 | { |
c4028958 | 7097 | struct net_device *dev = tp->dev; |
56de414c | 7098 | int i; |
1da177e4 | 7099 | |
da78dbff FR |
7100 | napi_disable(&tp->napi); |
7101 | netif_stop_queue(dev); | |
7102 | synchronize_sched(); | |
1da177e4 | 7103 | |
c7c2c39b | 7104 | rtl8169_hw_reset(tp); |
7105 | ||
56de414c FR |
7106 | for (i = 0; i < NUM_RX_DESC; i++) |
7107 | rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz); | |
7108 | ||
1da177e4 | 7109 | rtl8169_tx_clear(tp); |
c7c2c39b | 7110 | rtl8169_init_ring_indexes(tp); |
1da177e4 | 7111 | |
da78dbff | 7112 | napi_enable(&tp->napi); |
56de414c FR |
7113 | rtl_hw_start(dev); |
7114 | netif_wake_queue(dev); | |
7115 | rtl8169_check_link_status(dev, tp, tp->mmio_addr); | |
1da177e4 LT |
7116 | } |
7117 | ||
7118 | static void rtl8169_tx_timeout(struct net_device *dev) | |
7119 | { | |
da78dbff FR |
7120 | struct rtl8169_private *tp = netdev_priv(dev); |
7121 | ||
7122 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); | |
1da177e4 LT |
7123 | } |
7124 | ||
7125 | static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, | |
2b7b4318 | 7126 | u32 *opts) |
1da177e4 LT |
7127 | { |
7128 | struct skb_shared_info *info = skb_shinfo(skb); | |
7129 | unsigned int cur_frag, entry; | |
6e1d0b89 | 7130 | struct TxDesc *uninitialized_var(txd); |
48addcc9 | 7131 | struct device *d = &tp->pci_dev->dev; |
1da177e4 LT |
7132 | |
7133 | entry = tp->cur_tx; | |
7134 | for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { | |
9e903e08 | 7135 | const skb_frag_t *frag = info->frags + cur_frag; |
1da177e4 LT |
7136 | dma_addr_t mapping; |
7137 | u32 status, len; | |
7138 | void *addr; | |
7139 | ||
7140 | entry = (entry + 1) % NUM_TX_DESC; | |
7141 | ||
7142 | txd = tp->TxDescArray + entry; | |
9e903e08 | 7143 | len = skb_frag_size(frag); |
929f6189 | 7144 | addr = skb_frag_address(frag); |
48addcc9 | 7145 | mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); |
d827d86b SG |
7146 | if (unlikely(dma_mapping_error(d, mapping))) { |
7147 | if (net_ratelimit()) | |
7148 | netif_err(tp, drv, tp->dev, | |
7149 | "Failed to map TX fragments DMA!\n"); | |
3eafe507 | 7150 | goto err_out; |
d827d86b | 7151 | } |
1da177e4 | 7152 | |
cecb5fd7 | 7153 | /* Anti gcc 2.95.3 bugware (sic) */ |
2b7b4318 FR |
7154 | status = opts[0] | len | |
7155 | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
1da177e4 LT |
7156 | |
7157 | txd->opts1 = cpu_to_le32(status); | |
2b7b4318 | 7158 | txd->opts2 = cpu_to_le32(opts[1]); |
1da177e4 LT |
7159 | txd->addr = cpu_to_le64(mapping); |
7160 | ||
7161 | tp->tx_skb[entry].len = len; | |
7162 | } | |
7163 | ||
7164 | if (cur_frag) { | |
7165 | tp->tx_skb[entry].skb = skb; | |
7166 | txd->opts1 |= cpu_to_le32(LastFrag); | |
7167 | } | |
7168 | ||
7169 | return cur_frag; | |
3eafe507 SG |
7170 | |
7171 | err_out: | |
7172 | rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); | |
7173 | return -EIO; | |
1da177e4 LT |
7174 | } |
7175 | ||
b423e9ae | 7176 | static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) |
7177 | { | |
7178 | return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; | |
7179 | } | |
7180 | ||
e974604b | 7181 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
7182 | struct net_device *dev); | |
7183 | /* r8169_csum_workaround() | |
7184 | * The hw limites the value the transport offset. When the offset is out of the | |
7185 | * range, calculate the checksum by sw. | |
7186 | */ | |
7187 | static void r8169_csum_workaround(struct rtl8169_private *tp, | |
7188 | struct sk_buff *skb) | |
7189 | { | |
7190 | if (skb_shinfo(skb)->gso_size) { | |
7191 | netdev_features_t features = tp->dev->features; | |
7192 | struct sk_buff *segs, *nskb; | |
7193 | ||
7194 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); | |
7195 | segs = skb_gso_segment(skb, features); | |
7196 | if (IS_ERR(segs) || !segs) | |
7197 | goto drop; | |
7198 | ||
7199 | do { | |
7200 | nskb = segs; | |
7201 | segs = segs->next; | |
7202 | nskb->next = NULL; | |
7203 | rtl8169_start_xmit(nskb, tp->dev); | |
7204 | } while (segs); | |
7205 | ||
eb781397 | 7206 | dev_consume_skb_any(skb); |
e974604b | 7207 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
7208 | if (skb_checksum_help(skb) < 0) | |
7209 | goto drop; | |
7210 | ||
7211 | rtl8169_start_xmit(skb, tp->dev); | |
7212 | } else { | |
7213 | struct net_device_stats *stats; | |
7214 | ||
7215 | drop: | |
7216 | stats = &tp->dev->stats; | |
7217 | stats->tx_dropped++; | |
eb781397 | 7218 | dev_kfree_skb_any(skb); |
e974604b | 7219 | } |
7220 | } | |
7221 | ||
7222 | /* msdn_giant_send_check() | |
7223 | * According to the document of microsoft, the TCP Pseudo Header excludes the | |
7224 | * packet length for IPv6 TCP large packets. | |
7225 | */ | |
7226 | static int msdn_giant_send_check(struct sk_buff *skb) | |
7227 | { | |
7228 | const struct ipv6hdr *ipv6h; | |
7229 | struct tcphdr *th; | |
7230 | int ret; | |
7231 | ||
7232 | ret = skb_cow_head(skb, 0); | |
7233 | if (ret) | |
7234 | return ret; | |
7235 | ||
7236 | ipv6h = ipv6_hdr(skb); | |
7237 | th = tcp_hdr(skb); | |
7238 | ||
7239 | th->check = 0; | |
7240 | th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); | |
7241 | ||
7242 | return ret; | |
7243 | } | |
7244 | ||
7245 | static inline __be16 get_protocol(struct sk_buff *skb) | |
7246 | { | |
7247 | __be16 protocol; | |
7248 | ||
7249 | if (skb->protocol == htons(ETH_P_8021Q)) | |
7250 | protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; | |
7251 | else | |
7252 | protocol = skb->protocol; | |
7253 | ||
7254 | return protocol; | |
7255 | } | |
7256 | ||
5888d3fc | 7257 | static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp, |
7258 | struct sk_buff *skb, u32 *opts) | |
1da177e4 | 7259 | { |
350fb32a MM |
7260 | u32 mss = skb_shinfo(skb)->gso_size; |
7261 | ||
2b7b4318 FR |
7262 | if (mss) { |
7263 | opts[0] |= TD_LSO; | |
5888d3fc | 7264 | opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT; |
7265 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
7266 | const struct iphdr *ip = ip_hdr(skb); | |
7267 | ||
7268 | if (ip->protocol == IPPROTO_TCP) | |
7269 | opts[0] |= TD0_IP_CS | TD0_TCP_CS; | |
7270 | else if (ip->protocol == IPPROTO_UDP) | |
7271 | opts[0] |= TD0_IP_CS | TD0_UDP_CS; | |
7272 | else | |
7273 | WARN_ON_ONCE(1); | |
7274 | } | |
7275 | ||
7276 | return true; | |
7277 | } | |
7278 | ||
7279 | static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, | |
7280 | struct sk_buff *skb, u32 *opts) | |
7281 | { | |
bdfa4ed6 | 7282 | u32 transport_offset = (u32)skb_transport_offset(skb); |
5888d3fc | 7283 | u32 mss = skb_shinfo(skb)->gso_size; |
7284 | ||
7285 | if (mss) { | |
e974604b | 7286 | if (transport_offset > GTTCPHO_MAX) { |
7287 | netif_warn(tp, tx_err, tp->dev, | |
7288 | "Invalid transport offset 0x%x for TSO\n", | |
7289 | transport_offset); | |
7290 | return false; | |
7291 | } | |
7292 | ||
7293 | switch (get_protocol(skb)) { | |
7294 | case htons(ETH_P_IP): | |
7295 | opts[0] |= TD1_GTSENV4; | |
7296 | break; | |
7297 | ||
7298 | case htons(ETH_P_IPV6): | |
7299 | if (msdn_giant_send_check(skb)) | |
7300 | return false; | |
7301 | ||
7302 | opts[0] |= TD1_GTSENV6; | |
7303 | break; | |
7304 | ||
7305 | default: | |
7306 | WARN_ON_ONCE(1); | |
7307 | break; | |
7308 | } | |
7309 | ||
bdfa4ed6 | 7310 | opts[0] |= transport_offset << GTTCPHO_SHIFT; |
5888d3fc | 7311 | opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT; |
2b7b4318 | 7312 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
e974604b | 7313 | u8 ip_protocol; |
1da177e4 | 7314 | |
b423e9ae | 7315 | if (unlikely(rtl_test_hw_pad_bug(tp, skb))) |
207c5f44 | 7316 | return !(skb_checksum_help(skb) || eth_skb_pad(skb)); |
b423e9ae | 7317 | |
e974604b | 7318 | if (transport_offset > TCPHO_MAX) { |
7319 | netif_warn(tp, tx_err, tp->dev, | |
7320 | "Invalid transport offset 0x%x\n", | |
7321 | transport_offset); | |
7322 | return false; | |
7323 | } | |
7324 | ||
7325 | switch (get_protocol(skb)) { | |
7326 | case htons(ETH_P_IP): | |
7327 | opts[1] |= TD1_IPv4_CS; | |
7328 | ip_protocol = ip_hdr(skb)->protocol; | |
7329 | break; | |
7330 | ||
7331 | case htons(ETH_P_IPV6): | |
7332 | opts[1] |= TD1_IPv6_CS; | |
7333 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
7334 | break; | |
7335 | ||
7336 | default: | |
7337 | ip_protocol = IPPROTO_RAW; | |
7338 | break; | |
7339 | } | |
7340 | ||
7341 | if (ip_protocol == IPPROTO_TCP) | |
7342 | opts[1] |= TD1_TCP_CS; | |
7343 | else if (ip_protocol == IPPROTO_UDP) | |
7344 | opts[1] |= TD1_UDP_CS; | |
2b7b4318 FR |
7345 | else |
7346 | WARN_ON_ONCE(1); | |
e974604b | 7347 | |
7348 | opts[1] |= transport_offset << TCPHO_SHIFT; | |
b423e9ae | 7349 | } else { |
7350 | if (unlikely(rtl_test_hw_pad_bug(tp, skb))) | |
207c5f44 | 7351 | return !eth_skb_pad(skb); |
1da177e4 | 7352 | } |
5888d3fc | 7353 | |
b423e9ae | 7354 | return true; |
1da177e4 LT |
7355 | } |
7356 | ||
61357325 SH |
7357 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
7358 | struct net_device *dev) | |
1da177e4 LT |
7359 | { |
7360 | struct rtl8169_private *tp = netdev_priv(dev); | |
3eafe507 | 7361 | unsigned int entry = tp->cur_tx % NUM_TX_DESC; |
1da177e4 LT |
7362 | struct TxDesc *txd = tp->TxDescArray + entry; |
7363 | void __iomem *ioaddr = tp->mmio_addr; | |
48addcc9 | 7364 | struct device *d = &tp->pci_dev->dev; |
1da177e4 LT |
7365 | dma_addr_t mapping; |
7366 | u32 status, len; | |
2b7b4318 | 7367 | u32 opts[2]; |
3eafe507 | 7368 | int frags; |
5b0384f4 | 7369 | |
477206a0 | 7370 | if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) { |
bf82c189 | 7371 | netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); |
3eafe507 | 7372 | goto err_stop_0; |
1da177e4 LT |
7373 | } |
7374 | ||
7375 | if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) | |
3eafe507 SG |
7376 | goto err_stop_0; |
7377 | ||
b423e9ae | 7378 | opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb)); |
7379 | opts[0] = DescOwn; | |
7380 | ||
e974604b | 7381 | if (!tp->tso_csum(tp, skb, opts)) { |
7382 | r8169_csum_workaround(tp, skb); | |
7383 | return NETDEV_TX_OK; | |
7384 | } | |
b423e9ae | 7385 | |
3eafe507 | 7386 | len = skb_headlen(skb); |
48addcc9 | 7387 | mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); |
d827d86b SG |
7388 | if (unlikely(dma_mapping_error(d, mapping))) { |
7389 | if (net_ratelimit()) | |
7390 | netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); | |
3eafe507 | 7391 | goto err_dma_0; |
d827d86b | 7392 | } |
3eafe507 SG |
7393 | |
7394 | tp->tx_skb[entry].len = len; | |
7395 | txd->addr = cpu_to_le64(mapping); | |
1da177e4 | 7396 | |
2b7b4318 | 7397 | frags = rtl8169_xmit_frags(tp, skb, opts); |
3eafe507 SG |
7398 | if (frags < 0) |
7399 | goto err_dma_1; | |
7400 | else if (frags) | |
2b7b4318 | 7401 | opts[0] |= FirstFrag; |
3eafe507 | 7402 | else { |
2b7b4318 | 7403 | opts[0] |= FirstFrag | LastFrag; |
1da177e4 LT |
7404 | tp->tx_skb[entry].skb = skb; |
7405 | } | |
7406 | ||
2b7b4318 FR |
7407 | txd->opts2 = cpu_to_le32(opts[1]); |
7408 | ||
5047fb5d RC |
7409 | skb_tx_timestamp(skb); |
7410 | ||
a0750138 AD |
7411 | /* Force memory writes to complete before releasing descriptor */ |
7412 | dma_wmb(); | |
1da177e4 | 7413 | |
cecb5fd7 | 7414 | /* Anti gcc 2.95.3 bugware (sic) */ |
2b7b4318 | 7415 | status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
1da177e4 LT |
7416 | txd->opts1 = cpu_to_le32(status); |
7417 | ||
a0750138 | 7418 | /* Force all memory writes to complete before notifying device */ |
4c020a96 | 7419 | wmb(); |
1da177e4 | 7420 | |
a0750138 AD |
7421 | tp->cur_tx += frags + 1; |
7422 | ||
87cda7cb | 7423 | RTL_W8(TxPoll, NPQ); |
1da177e4 | 7424 | |
87cda7cb | 7425 | mmiowb(); |
da78dbff | 7426 | |
87cda7cb | 7427 | if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) { |
ae1f23fb FR |
7428 | /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must |
7429 | * not miss a ring update when it notices a stopped queue. | |
7430 | */ | |
7431 | smp_wmb(); | |
1da177e4 | 7432 | netif_stop_queue(dev); |
ae1f23fb FR |
7433 | /* Sync with rtl_tx: |
7434 | * - publish queue status and cur_tx ring index (write barrier) | |
7435 | * - refresh dirty_tx ring index (read barrier). | |
7436 | * May the current thread have a pessimistic view of the ring | |
7437 | * status and forget to wake up queue, a racing rtl_tx thread | |
7438 | * can't. | |
7439 | */ | |
1e874e04 | 7440 | smp_mb(); |
477206a0 | 7441 | if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) |
1da177e4 LT |
7442 | netif_wake_queue(dev); |
7443 | } | |
7444 | ||
61357325 | 7445 | return NETDEV_TX_OK; |
1da177e4 | 7446 | |
3eafe507 | 7447 | err_dma_1: |
48addcc9 | 7448 | rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); |
3eafe507 | 7449 | err_dma_0: |
989c9ba1 | 7450 | dev_kfree_skb_any(skb); |
3eafe507 SG |
7451 | dev->stats.tx_dropped++; |
7452 | return NETDEV_TX_OK; | |
7453 | ||
7454 | err_stop_0: | |
1da177e4 | 7455 | netif_stop_queue(dev); |
cebf8cc7 | 7456 | dev->stats.tx_dropped++; |
61357325 | 7457 | return NETDEV_TX_BUSY; |
1da177e4 LT |
7458 | } |
7459 | ||
7460 | static void rtl8169_pcierr_interrupt(struct net_device *dev) | |
7461 | { | |
7462 | struct rtl8169_private *tp = netdev_priv(dev); | |
7463 | struct pci_dev *pdev = tp->pci_dev; | |
1da177e4 LT |
7464 | u16 pci_status, pci_cmd; |
7465 | ||
7466 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
7467 | pci_read_config_word(pdev, PCI_STATUS, &pci_status); | |
7468 | ||
bf82c189 JP |
7469 | netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", |
7470 | pci_cmd, pci_status); | |
1da177e4 LT |
7471 | |
7472 | /* | |
7473 | * The recovery sequence below admits a very elaborated explanation: | |
7474 | * - it seems to work; | |
d03902b8 FR |
7475 | * - I did not see what else could be done; |
7476 | * - it makes iop3xx happy. | |
1da177e4 LT |
7477 | * |
7478 | * Feel free to adjust to your needs. | |
7479 | */ | |
a27993f3 | 7480 | if (pdev->broken_parity_status) |
d03902b8 FR |
7481 | pci_cmd &= ~PCI_COMMAND_PARITY; |
7482 | else | |
7483 | pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; | |
7484 | ||
7485 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1da177e4 LT |
7486 | |
7487 | pci_write_config_word(pdev, PCI_STATUS, | |
7488 | pci_status & (PCI_STATUS_DETECTED_PARITY | | |
7489 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | | |
7490 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); | |
7491 | ||
7492 | /* The infamous DAC f*ckup only happens at boot time */ | |
9fba0812 | 7493 | if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) { |
e6de30d6 | 7494 | void __iomem *ioaddr = tp->mmio_addr; |
7495 | ||
bf82c189 | 7496 | netif_info(tp, intr, dev, "disabling PCI DAC\n"); |
1da177e4 LT |
7497 | tp->cp_cmd &= ~PCIDAC; |
7498 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
7499 | dev->features &= ~NETIF_F_HIGHDMA; | |
1da177e4 LT |
7500 | } |
7501 | ||
e6de30d6 | 7502 | rtl8169_hw_reset(tp); |
d03902b8 | 7503 | |
98ddf986 | 7504 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
1da177e4 LT |
7505 | } |
7506 | ||
da78dbff | 7507 | static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp) |
1da177e4 LT |
7508 | { |
7509 | unsigned int dirty_tx, tx_left; | |
7510 | ||
1da177e4 LT |
7511 | dirty_tx = tp->dirty_tx; |
7512 | smp_rmb(); | |
7513 | tx_left = tp->cur_tx - dirty_tx; | |
7514 | ||
7515 | while (tx_left > 0) { | |
7516 | unsigned int entry = dirty_tx % NUM_TX_DESC; | |
7517 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
1da177e4 LT |
7518 | u32 status; |
7519 | ||
1da177e4 LT |
7520 | status = le32_to_cpu(tp->TxDescArray[entry].opts1); |
7521 | if (status & DescOwn) | |
7522 | break; | |
7523 | ||
a0750138 AD |
7524 | /* This barrier is needed to keep us from reading |
7525 | * any other fields out of the Tx descriptor until | |
7526 | * we know the status of DescOwn | |
7527 | */ | |
7528 | dma_rmb(); | |
7529 | ||
48addcc9 SG |
7530 | rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
7531 | tp->TxDescArray + entry); | |
1da177e4 | 7532 | if (status & LastFrag) { |
87cda7cb DM |
7533 | u64_stats_update_begin(&tp->tx_stats.syncp); |
7534 | tp->tx_stats.packets++; | |
7535 | tp->tx_stats.bytes += tx_skb->skb->len; | |
7536 | u64_stats_update_end(&tp->tx_stats.syncp); | |
7a4b813c | 7537 | dev_consume_skb_any(tx_skb->skb); |
1da177e4 LT |
7538 | tx_skb->skb = NULL; |
7539 | } | |
7540 | dirty_tx++; | |
7541 | tx_left--; | |
7542 | } | |
7543 | ||
7544 | if (tp->dirty_tx != dirty_tx) { | |
7545 | tp->dirty_tx = dirty_tx; | |
ae1f23fb FR |
7546 | /* Sync with rtl8169_start_xmit: |
7547 | * - publish dirty_tx ring index (write barrier) | |
7548 | * - refresh cur_tx ring index and queue status (read barrier) | |
7549 | * May the current thread miss the stopped queue condition, | |
7550 | * a racing xmit thread can only have a right view of the | |
7551 | * ring status. | |
7552 | */ | |
1e874e04 | 7553 | smp_mb(); |
1da177e4 | 7554 | if (netif_queue_stopped(dev) && |
477206a0 | 7555 | TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) { |
1da177e4 LT |
7556 | netif_wake_queue(dev); |
7557 | } | |
d78ae2dc FR |
7558 | /* |
7559 | * 8168 hack: TxPoll requests are lost when the Tx packets are | |
7560 | * too close. Let's kick an extra TxPoll request when a burst | |
7561 | * of start_xmit activity is detected (if it is not detected, | |
7562 | * it is slow enough). -- FR | |
7563 | */ | |
da78dbff FR |
7564 | if (tp->cur_tx != dirty_tx) { |
7565 | void __iomem *ioaddr = tp->mmio_addr; | |
7566 | ||
d78ae2dc | 7567 | RTL_W8(TxPoll, NPQ); |
da78dbff | 7568 | } |
1da177e4 LT |
7569 | } |
7570 | } | |
7571 | ||
126fa4b9 FR |
7572 | static inline int rtl8169_fragmented_frame(u32 status) |
7573 | { | |
7574 | return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); | |
7575 | } | |
7576 | ||
adea1ac7 | 7577 | static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) |
1da177e4 | 7578 | { |
1da177e4 LT |
7579 | u32 status = opts1 & RxProtoMask; |
7580 | ||
7581 | if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || | |
d5d3ebe3 | 7582 | ((status == RxProtoUDP) && !(opts1 & UDPFail))) |
1da177e4 LT |
7583 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
7584 | else | |
bc8acf2c | 7585 | skb_checksum_none_assert(skb); |
1da177e4 LT |
7586 | } |
7587 | ||
6f0333b8 ED |
7588 | static struct sk_buff *rtl8169_try_rx_copy(void *data, |
7589 | struct rtl8169_private *tp, | |
7590 | int pkt_size, | |
7591 | dma_addr_t addr) | |
1da177e4 | 7592 | { |
b449655f | 7593 | struct sk_buff *skb; |
48addcc9 | 7594 | struct device *d = &tp->pci_dev->dev; |
b449655f | 7595 | |
6f0333b8 | 7596 | data = rtl8169_align(data); |
48addcc9 | 7597 | dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
6f0333b8 | 7598 | prefetch(data); |
e2338f86 | 7599 | skb = napi_alloc_skb(&tp->napi, pkt_size); |
6f0333b8 ED |
7600 | if (skb) |
7601 | memcpy(skb->data, data, pkt_size); | |
48addcc9 SG |
7602 | dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); |
7603 | ||
6f0333b8 | 7604 | return skb; |
1da177e4 LT |
7605 | } |
7606 | ||
da78dbff | 7607 | static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) |
1da177e4 LT |
7608 | { |
7609 | unsigned int cur_rx, rx_left; | |
6f0333b8 | 7610 | unsigned int count; |
1da177e4 | 7611 | |
1da177e4 | 7612 | cur_rx = tp->cur_rx; |
1da177e4 | 7613 | |
9fba0812 | 7614 | for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { |
1da177e4 | 7615 | unsigned int entry = cur_rx % NUM_RX_DESC; |
126fa4b9 | 7616 | struct RxDesc *desc = tp->RxDescArray + entry; |
1da177e4 LT |
7617 | u32 status; |
7618 | ||
e03f33af | 7619 | status = le32_to_cpu(desc->opts1) & tp->opts1_mask; |
1da177e4 LT |
7620 | if (status & DescOwn) |
7621 | break; | |
a0750138 AD |
7622 | |
7623 | /* This barrier is needed to keep us from reading | |
7624 | * any other fields out of the Rx descriptor until | |
7625 | * we know the status of DescOwn | |
7626 | */ | |
7627 | dma_rmb(); | |
7628 | ||
4dcb7d33 | 7629 | if (unlikely(status & RxRES)) { |
bf82c189 JP |
7630 | netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", |
7631 | status); | |
cebf8cc7 | 7632 | dev->stats.rx_errors++; |
1da177e4 | 7633 | if (status & (RxRWT | RxRUNT)) |
cebf8cc7 | 7634 | dev->stats.rx_length_errors++; |
1da177e4 | 7635 | if (status & RxCRC) |
cebf8cc7 | 7636 | dev->stats.rx_crc_errors++; |
9dccf611 | 7637 | if (status & RxFOVF) { |
da78dbff | 7638 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
cebf8cc7 | 7639 | dev->stats.rx_fifo_errors++; |
9dccf611 | 7640 | } |
6bbe021d BG |
7641 | if ((status & (RxRUNT | RxCRC)) && |
7642 | !(status & (RxRWT | RxFOVF)) && | |
7643 | (dev->features & NETIF_F_RXALL)) | |
7644 | goto process_pkt; | |
1da177e4 | 7645 | } else { |
6f0333b8 | 7646 | struct sk_buff *skb; |
6bbe021d BG |
7647 | dma_addr_t addr; |
7648 | int pkt_size; | |
7649 | ||
7650 | process_pkt: | |
7651 | addr = le64_to_cpu(desc->addr); | |
79d0c1d2 BG |
7652 | if (likely(!(dev->features & NETIF_F_RXFCS))) |
7653 | pkt_size = (status & 0x00003fff) - 4; | |
7654 | else | |
7655 | pkt_size = status & 0x00003fff; | |
1da177e4 | 7656 | |
126fa4b9 FR |
7657 | /* |
7658 | * The driver does not support incoming fragmented | |
7659 | * frames. They are seen as a symptom of over-mtu | |
7660 | * sized frames. | |
7661 | */ | |
7662 | if (unlikely(rtl8169_fragmented_frame(status))) { | |
cebf8cc7 FR |
7663 | dev->stats.rx_dropped++; |
7664 | dev->stats.rx_length_errors++; | |
ce11ff5e | 7665 | goto release_descriptor; |
126fa4b9 FR |
7666 | } |
7667 | ||
6f0333b8 ED |
7668 | skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry], |
7669 | tp, pkt_size, addr); | |
6f0333b8 ED |
7670 | if (!skb) { |
7671 | dev->stats.rx_dropped++; | |
ce11ff5e | 7672 | goto release_descriptor; |
1da177e4 LT |
7673 | } |
7674 | ||
adea1ac7 | 7675 | rtl8169_rx_csum(skb, status); |
1da177e4 LT |
7676 | skb_put(skb, pkt_size); |
7677 | skb->protocol = eth_type_trans(skb, dev); | |
7678 | ||
7a8fc77b FR |
7679 | rtl8169_rx_vlan_tag(desc, skb); |
7680 | ||
39174291 | 7681 | if (skb->pkt_type == PACKET_MULTICAST) |
7682 | dev->stats.multicast++; | |
7683 | ||
56de414c | 7684 | napi_gro_receive(&tp->napi, skb); |
1da177e4 | 7685 | |
8027aa24 JW |
7686 | u64_stats_update_begin(&tp->rx_stats.syncp); |
7687 | tp->rx_stats.packets++; | |
7688 | tp->rx_stats.bytes += pkt_size; | |
7689 | u64_stats_update_end(&tp->rx_stats.syncp); | |
1da177e4 | 7690 | } |
ce11ff5e | 7691 | release_descriptor: |
7692 | desc->opts2 = 0; | |
ce11ff5e | 7693 | rtl8169_mark_to_asic(desc, rx_buf_sz); |
1da177e4 LT |
7694 | } |
7695 | ||
7696 | count = cur_rx - tp->cur_rx; | |
7697 | tp->cur_rx = cur_rx; | |
7698 | ||
1da177e4 LT |
7699 | return count; |
7700 | } | |
7701 | ||
07d3f51f | 7702 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
1da177e4 | 7703 | { |
07d3f51f | 7704 | struct net_device *dev = dev_instance; |
1da177e4 | 7705 | struct rtl8169_private *tp = netdev_priv(dev); |
1da177e4 | 7706 | int handled = 0; |
9085cdfa | 7707 | u16 status; |
1da177e4 | 7708 | |
9085cdfa | 7709 | status = rtl_get_events(tp); |
da78dbff FR |
7710 | if (status && status != 0xffff) { |
7711 | status &= RTL_EVENT_NAPI | tp->event_slow; | |
7712 | if (status) { | |
7713 | handled = 1; | |
1da177e4 | 7714 | |
da78dbff FR |
7715 | rtl_irq_disable(tp); |
7716 | napi_schedule(&tp->napi); | |
f11a377b | 7717 | } |
da78dbff FR |
7718 | } |
7719 | return IRQ_RETVAL(handled); | |
7720 | } | |
1da177e4 | 7721 | |
da78dbff FR |
7722 | /* |
7723 | * Workqueue context. | |
7724 | */ | |
7725 | static void rtl_slow_event_work(struct rtl8169_private *tp) | |
7726 | { | |
7727 | struct net_device *dev = tp->dev; | |
7728 | u16 status; | |
7729 | ||
7730 | status = rtl_get_events(tp) & tp->event_slow; | |
7731 | rtl_ack_events(tp, status); | |
1da177e4 | 7732 | |
da78dbff FR |
7733 | if (unlikely(status & RxFIFOOver)) { |
7734 | switch (tp->mac_version) { | |
7735 | /* Work around for rx fifo overflow */ | |
7736 | case RTL_GIGA_MAC_VER_11: | |
7737 | netif_stop_queue(dev); | |
934714d0 FR |
7738 | /* XXX - Hack alert. See rtl_task(). */ |
7739 | set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags); | |
da78dbff | 7740 | default: |
f11a377b DD |
7741 | break; |
7742 | } | |
da78dbff | 7743 | } |
1da177e4 | 7744 | |
da78dbff FR |
7745 | if (unlikely(status & SYSErr)) |
7746 | rtl8169_pcierr_interrupt(dev); | |
0e485150 | 7747 | |
da78dbff FR |
7748 | if (status & LinkChg) |
7749 | __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true); | |
1da177e4 | 7750 | |
7dbb4918 | 7751 | rtl_irq_enable_all(tp); |
1da177e4 LT |
7752 | } |
7753 | ||
4422bcd4 FR |
7754 | static void rtl_task(struct work_struct *work) |
7755 | { | |
da78dbff FR |
7756 | static const struct { |
7757 | int bitnr; | |
7758 | void (*action)(struct rtl8169_private *); | |
7759 | } rtl_work[] = { | |
934714d0 | 7760 | /* XXX - keep rtl_slow_event_work() as first element. */ |
da78dbff FR |
7761 | { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work }, |
7762 | { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work }, | |
7763 | { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work } | |
7764 | }; | |
4422bcd4 FR |
7765 | struct rtl8169_private *tp = |
7766 | container_of(work, struct rtl8169_private, wk.work); | |
da78dbff FR |
7767 | struct net_device *dev = tp->dev; |
7768 | int i; | |
7769 | ||
7770 | rtl_lock_work(tp); | |
7771 | ||
6c4a70c5 FR |
7772 | if (!netif_running(dev) || |
7773 | !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) | |
da78dbff FR |
7774 | goto out_unlock; |
7775 | ||
7776 | for (i = 0; i < ARRAY_SIZE(rtl_work); i++) { | |
7777 | bool pending; | |
7778 | ||
da78dbff | 7779 | pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags); |
da78dbff FR |
7780 | if (pending) |
7781 | rtl_work[i].action(tp); | |
7782 | } | |
4422bcd4 | 7783 | |
da78dbff FR |
7784 | out_unlock: |
7785 | rtl_unlock_work(tp); | |
4422bcd4 FR |
7786 | } |
7787 | ||
bea3348e | 7788 | static int rtl8169_poll(struct napi_struct *napi, int budget) |
1da177e4 | 7789 | { |
bea3348e SH |
7790 | struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
7791 | struct net_device *dev = tp->dev; | |
da78dbff FR |
7792 | u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow; |
7793 | int work_done= 0; | |
7794 | u16 status; | |
7795 | ||
7796 | status = rtl_get_events(tp); | |
7797 | rtl_ack_events(tp, status & ~tp->event_slow); | |
7798 | ||
7799 | if (status & RTL_EVENT_NAPI_RX) | |
7800 | work_done = rtl_rx(dev, tp, (u32) budget); | |
7801 | ||
7802 | if (status & RTL_EVENT_NAPI_TX) | |
7803 | rtl_tx(dev, tp); | |
1da177e4 | 7804 | |
da78dbff FR |
7805 | if (status & tp->event_slow) { |
7806 | enable_mask &= ~tp->event_slow; | |
7807 | ||
7808 | rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING); | |
7809 | } | |
1da177e4 | 7810 | |
bea3348e | 7811 | if (work_done < budget) { |
6ad20165 | 7812 | napi_complete_done(napi, work_done); |
f11a377b | 7813 | |
da78dbff FR |
7814 | rtl_irq_enable(tp, enable_mask); |
7815 | mmiowb(); | |
1da177e4 LT |
7816 | } |
7817 | ||
bea3348e | 7818 | return work_done; |
1da177e4 | 7819 | } |
1da177e4 | 7820 | |
523a6094 FR |
7821 | static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
7822 | { | |
7823 | struct rtl8169_private *tp = netdev_priv(dev); | |
7824 | ||
7825 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) | |
7826 | return; | |
7827 | ||
7828 | dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); | |
7829 | RTL_W32(RxMissed, 0); | |
7830 | } | |
7831 | ||
1da177e4 LT |
7832 | static void rtl8169_down(struct net_device *dev) |
7833 | { | |
7834 | struct rtl8169_private *tp = netdev_priv(dev); | |
7835 | void __iomem *ioaddr = tp->mmio_addr; | |
1da177e4 | 7836 | |
4876cc1e | 7837 | del_timer_sync(&tp->timer); |
1da177e4 | 7838 | |
93dd79e8 | 7839 | napi_disable(&tp->napi); |
da78dbff | 7840 | netif_stop_queue(dev); |
1da177e4 | 7841 | |
92fc43b4 | 7842 | rtl8169_hw_reset(tp); |
323bb685 SG |
7843 | /* |
7844 | * At this point device interrupts can not be enabled in any function, | |
209e5ac8 FR |
7845 | * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task) |
7846 | * and napi is disabled (rtl8169_poll). | |
323bb685 | 7847 | */ |
523a6094 | 7848 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 | 7849 | |
1da177e4 | 7850 | /* Give a racing hard_start_xmit a few cycles to complete. */ |
da78dbff | 7851 | synchronize_sched(); |
1da177e4 | 7852 | |
1da177e4 LT |
7853 | rtl8169_tx_clear(tp); |
7854 | ||
7855 | rtl8169_rx_clear(tp); | |
065c27c1 | 7856 | |
7857 | rtl_pll_power_down(tp); | |
1da177e4 LT |
7858 | } |
7859 | ||
7860 | static int rtl8169_close(struct net_device *dev) | |
7861 | { | |
7862 | struct rtl8169_private *tp = netdev_priv(dev); | |
7863 | struct pci_dev *pdev = tp->pci_dev; | |
7864 | ||
e1759441 RW |
7865 | pm_runtime_get_sync(&pdev->dev); |
7866 | ||
cecb5fd7 | 7867 | /* Update counters before going down */ |
355423d0 IV |
7868 | rtl8169_update_counters(dev); |
7869 | ||
da78dbff | 7870 | rtl_lock_work(tp); |
6c4a70c5 | 7871 | clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
da78dbff | 7872 | |
1da177e4 | 7873 | rtl8169_down(dev); |
da78dbff | 7874 | rtl_unlock_work(tp); |
1da177e4 | 7875 | |
4ea72445 L |
7876 | cancel_work_sync(&tp->wk.work); |
7877 | ||
92a7c4e7 | 7878 | free_irq(pdev->irq, dev); |
1da177e4 | 7879 | |
82553bb6 SG |
7880 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
7881 | tp->RxPhyAddr); | |
7882 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
7883 | tp->TxPhyAddr); | |
1da177e4 LT |
7884 | tp->TxDescArray = NULL; |
7885 | tp->RxDescArray = NULL; | |
7886 | ||
e1759441 RW |
7887 | pm_runtime_put_sync(&pdev->dev); |
7888 | ||
1da177e4 LT |
7889 | return 0; |
7890 | } | |
7891 | ||
dc1c00ce FR |
7892 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7893 | static void rtl8169_netpoll(struct net_device *dev) | |
7894 | { | |
7895 | struct rtl8169_private *tp = netdev_priv(dev); | |
7896 | ||
7897 | rtl8169_interrupt(tp->pci_dev->irq, dev); | |
7898 | } | |
7899 | #endif | |
7900 | ||
df43ac78 FR |
7901 | static int rtl_open(struct net_device *dev) |
7902 | { | |
7903 | struct rtl8169_private *tp = netdev_priv(dev); | |
7904 | void __iomem *ioaddr = tp->mmio_addr; | |
7905 | struct pci_dev *pdev = tp->pci_dev; | |
7906 | int retval = -ENOMEM; | |
7907 | ||
7908 | pm_runtime_get_sync(&pdev->dev); | |
7909 | ||
7910 | /* | |
e75d6606 | 7911 | * Rx and Tx descriptors needs 256 bytes alignment. |
df43ac78 FR |
7912 | * dma_alloc_coherent provides more. |
7913 | */ | |
7914 | tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, | |
7915 | &tp->TxPhyAddr, GFP_KERNEL); | |
7916 | if (!tp->TxDescArray) | |
7917 | goto err_pm_runtime_put; | |
7918 | ||
7919 | tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, | |
7920 | &tp->RxPhyAddr, GFP_KERNEL); | |
7921 | if (!tp->RxDescArray) | |
7922 | goto err_free_tx_0; | |
7923 | ||
7924 | retval = rtl8169_init_ring(dev); | |
7925 | if (retval < 0) | |
7926 | goto err_free_rx_1; | |
7927 | ||
7928 | INIT_WORK(&tp->wk.work, rtl_task); | |
7929 | ||
7930 | smp_mb(); | |
7931 | ||
7932 | rtl_request_firmware(tp); | |
7933 | ||
92a7c4e7 | 7934 | retval = request_irq(pdev->irq, rtl8169_interrupt, |
df43ac78 FR |
7935 | (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, |
7936 | dev->name, dev); | |
7937 | if (retval < 0) | |
7938 | goto err_release_fw_2; | |
7939 | ||
7940 | rtl_lock_work(tp); | |
7941 | ||
7942 | set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); | |
7943 | ||
7944 | napi_enable(&tp->napi); | |
7945 | ||
7946 | rtl8169_init_phy(dev, tp); | |
7947 | ||
7948 | __rtl8169_set_features(dev, dev->features); | |
7949 | ||
7950 | rtl_pll_power_up(tp); | |
7951 | ||
7952 | rtl_hw_start(dev); | |
7953 | ||
6e85d5ad CV |
7954 | if (!rtl8169_init_counter_offsets(dev)) |
7955 | netif_warn(tp, hw, dev, "counter reset/update failed\n"); | |
7956 | ||
df43ac78 FR |
7957 | netif_start_queue(dev); |
7958 | ||
7959 | rtl_unlock_work(tp); | |
7960 | ||
7961 | tp->saved_wolopts = 0; | |
7962 | pm_runtime_put_noidle(&pdev->dev); | |
7963 | ||
7964 | rtl8169_check_link_status(dev, tp, ioaddr); | |
7965 | out: | |
7966 | return retval; | |
7967 | ||
7968 | err_release_fw_2: | |
7969 | rtl_release_firmware(tp); | |
7970 | rtl8169_rx_clear(tp); | |
7971 | err_free_rx_1: | |
7972 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, | |
7973 | tp->RxPhyAddr); | |
7974 | tp->RxDescArray = NULL; | |
7975 | err_free_tx_0: | |
7976 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
7977 | tp->TxPhyAddr); | |
7978 | tp->TxDescArray = NULL; | |
7979 | err_pm_runtime_put: | |
7980 | pm_runtime_put_noidle(&pdev->dev); | |
7981 | goto out; | |
7982 | } | |
7983 | ||
bc1f4470 | 7984 | static void |
8027aa24 | 7985 | rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) |
1da177e4 LT |
7986 | { |
7987 | struct rtl8169_private *tp = netdev_priv(dev); | |
7988 | void __iomem *ioaddr = tp->mmio_addr; | |
f09cf4b7 | 7989 | struct pci_dev *pdev = tp->pci_dev; |
42020320 | 7990 | struct rtl8169_counters *counters = tp->counters; |
8027aa24 | 7991 | unsigned int start; |
1da177e4 | 7992 | |
f09cf4b7 CHL |
7993 | pm_runtime_get_noresume(&pdev->dev); |
7994 | ||
7995 | if (netif_running(dev) && pm_runtime_active(&pdev->dev)) | |
523a6094 | 7996 | rtl8169_rx_missed(dev, ioaddr); |
5b0384f4 | 7997 | |
8027aa24 | 7998 | do { |
57a7744e | 7999 | start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); |
8027aa24 JW |
8000 | stats->rx_packets = tp->rx_stats.packets; |
8001 | stats->rx_bytes = tp->rx_stats.bytes; | |
57a7744e | 8002 | } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); |
8027aa24 | 8003 | |
8027aa24 | 8004 | do { |
57a7744e | 8005 | start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); |
8027aa24 JW |
8006 | stats->tx_packets = tp->tx_stats.packets; |
8007 | stats->tx_bytes = tp->tx_stats.bytes; | |
57a7744e | 8008 | } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); |
8027aa24 JW |
8009 | |
8010 | stats->rx_dropped = dev->stats.rx_dropped; | |
8011 | stats->tx_dropped = dev->stats.tx_dropped; | |
8012 | stats->rx_length_errors = dev->stats.rx_length_errors; | |
8013 | stats->rx_errors = dev->stats.rx_errors; | |
8014 | stats->rx_crc_errors = dev->stats.rx_crc_errors; | |
8015 | stats->rx_fifo_errors = dev->stats.rx_fifo_errors; | |
8016 | stats->rx_missed_errors = dev->stats.rx_missed_errors; | |
d7d2d89d | 8017 | stats->multicast = dev->stats.multicast; |
8027aa24 | 8018 | |
6e85d5ad CV |
8019 | /* |
8020 | * Fetch additonal counter values missing in stats collected by driver | |
8021 | * from tally counters. | |
8022 | */ | |
f09cf4b7 CHL |
8023 | if (pm_runtime_active(&pdev->dev)) |
8024 | rtl8169_update_counters(dev); | |
6e85d5ad CV |
8025 | |
8026 | /* | |
8027 | * Subtract values fetched during initalization. | |
8028 | * See rtl8169_init_counter_offsets for a description why we do that. | |
8029 | */ | |
42020320 | 8030 | stats->tx_errors = le64_to_cpu(counters->tx_errors) - |
6e85d5ad | 8031 | le64_to_cpu(tp->tc_offset.tx_errors); |
42020320 | 8032 | stats->collisions = le32_to_cpu(counters->tx_multi_collision) - |
6e85d5ad | 8033 | le32_to_cpu(tp->tc_offset.tx_multi_collision); |
42020320 | 8034 | stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - |
6e85d5ad CV |
8035 | le16_to_cpu(tp->tc_offset.tx_aborted); |
8036 | ||
f09cf4b7 | 8037 | pm_runtime_put_noidle(&pdev->dev); |
1da177e4 LT |
8038 | } |
8039 | ||
861ab440 | 8040 | static void rtl8169_net_suspend(struct net_device *dev) |
5d06a99f | 8041 | { |
065c27c1 | 8042 | struct rtl8169_private *tp = netdev_priv(dev); |
8043 | ||
5d06a99f | 8044 | if (!netif_running(dev)) |
861ab440 | 8045 | return; |
5d06a99f FR |
8046 | |
8047 | netif_device_detach(dev); | |
8048 | netif_stop_queue(dev); | |
da78dbff FR |
8049 | |
8050 | rtl_lock_work(tp); | |
8051 | napi_disable(&tp->napi); | |
6c4a70c5 | 8052 | clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
da78dbff FR |
8053 | rtl_unlock_work(tp); |
8054 | ||
8055 | rtl_pll_power_down(tp); | |
861ab440 RW |
8056 | } |
8057 | ||
8058 | #ifdef CONFIG_PM | |
8059 | ||
8060 | static int rtl8169_suspend(struct device *device) | |
8061 | { | |
8062 | struct pci_dev *pdev = to_pci_dev(device); | |
8063 | struct net_device *dev = pci_get_drvdata(pdev); | |
5d06a99f | 8064 | |
861ab440 | 8065 | rtl8169_net_suspend(dev); |
1371fa6d | 8066 | |
5d06a99f FR |
8067 | return 0; |
8068 | } | |
8069 | ||
e1759441 RW |
8070 | static void __rtl8169_resume(struct net_device *dev) |
8071 | { | |
065c27c1 | 8072 | struct rtl8169_private *tp = netdev_priv(dev); |
8073 | ||
e1759441 | 8074 | netif_device_attach(dev); |
065c27c1 | 8075 | |
8076 | rtl_pll_power_up(tp); | |
8077 | ||
cff4c162 AS |
8078 | rtl_lock_work(tp); |
8079 | napi_enable(&tp->napi); | |
6c4a70c5 | 8080 | set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
cff4c162 | 8081 | rtl_unlock_work(tp); |
da78dbff | 8082 | |
98ddf986 | 8083 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
e1759441 RW |
8084 | } |
8085 | ||
861ab440 | 8086 | static int rtl8169_resume(struct device *device) |
5d06a99f | 8087 | { |
861ab440 | 8088 | struct pci_dev *pdev = to_pci_dev(device); |
5d06a99f | 8089 | struct net_device *dev = pci_get_drvdata(pdev); |
fccec10b SG |
8090 | struct rtl8169_private *tp = netdev_priv(dev); |
8091 | ||
8092 | rtl8169_init_phy(dev, tp); | |
5d06a99f | 8093 | |
e1759441 RW |
8094 | if (netif_running(dev)) |
8095 | __rtl8169_resume(dev); | |
5d06a99f | 8096 | |
e1759441 RW |
8097 | return 0; |
8098 | } | |
8099 | ||
8100 | static int rtl8169_runtime_suspend(struct device *device) | |
8101 | { | |
8102 | struct pci_dev *pdev = to_pci_dev(device); | |
8103 | struct net_device *dev = pci_get_drvdata(pdev); | |
8104 | struct rtl8169_private *tp = netdev_priv(dev); | |
8105 | ||
8106 | if (!tp->TxDescArray) | |
8107 | return 0; | |
8108 | ||
da78dbff | 8109 | rtl_lock_work(tp); |
e1759441 RW |
8110 | tp->saved_wolopts = __rtl8169_get_wol(tp); |
8111 | __rtl8169_set_wol(tp, WAKE_ANY); | |
da78dbff | 8112 | rtl_unlock_work(tp); |
e1759441 RW |
8113 | |
8114 | rtl8169_net_suspend(dev); | |
8115 | ||
f09cf4b7 CHL |
8116 | /* Update counters before going runtime suspend */ |
8117 | rtl8169_rx_missed(dev, tp->mmio_addr); | |
8118 | rtl8169_update_counters(dev); | |
8119 | ||
e1759441 RW |
8120 | return 0; |
8121 | } | |
8122 | ||
8123 | static int rtl8169_runtime_resume(struct device *device) | |
8124 | { | |
8125 | struct pci_dev *pdev = to_pci_dev(device); | |
8126 | struct net_device *dev = pci_get_drvdata(pdev); | |
8127 | struct rtl8169_private *tp = netdev_priv(dev); | |
f51d4a10 | 8128 | rtl_rar_set(tp, dev->dev_addr); |
e1759441 RW |
8129 | |
8130 | if (!tp->TxDescArray) | |
8131 | return 0; | |
8132 | ||
da78dbff | 8133 | rtl_lock_work(tp); |
e1759441 RW |
8134 | __rtl8169_set_wol(tp, tp->saved_wolopts); |
8135 | tp->saved_wolopts = 0; | |
da78dbff | 8136 | rtl_unlock_work(tp); |
e1759441 | 8137 | |
fccec10b SG |
8138 | rtl8169_init_phy(dev, tp); |
8139 | ||
e1759441 | 8140 | __rtl8169_resume(dev); |
5d06a99f | 8141 | |
5d06a99f FR |
8142 | return 0; |
8143 | } | |
8144 | ||
e1759441 RW |
8145 | static int rtl8169_runtime_idle(struct device *device) |
8146 | { | |
8147 | struct pci_dev *pdev = to_pci_dev(device); | |
8148 | struct net_device *dev = pci_get_drvdata(pdev); | |
8149 | struct rtl8169_private *tp = netdev_priv(dev); | |
8150 | ||
e4fbce74 | 8151 | return tp->TxDescArray ? -EBUSY : 0; |
e1759441 RW |
8152 | } |
8153 | ||
47145210 | 8154 | static const struct dev_pm_ops rtl8169_pm_ops = { |
cecb5fd7 FR |
8155 | .suspend = rtl8169_suspend, |
8156 | .resume = rtl8169_resume, | |
8157 | .freeze = rtl8169_suspend, | |
8158 | .thaw = rtl8169_resume, | |
8159 | .poweroff = rtl8169_suspend, | |
8160 | .restore = rtl8169_resume, | |
8161 | .runtime_suspend = rtl8169_runtime_suspend, | |
8162 | .runtime_resume = rtl8169_runtime_resume, | |
8163 | .runtime_idle = rtl8169_runtime_idle, | |
861ab440 RW |
8164 | }; |
8165 | ||
8166 | #define RTL8169_PM_OPS (&rtl8169_pm_ops) | |
8167 | ||
8168 | #else /* !CONFIG_PM */ | |
8169 | ||
8170 | #define RTL8169_PM_OPS NULL | |
8171 | ||
8172 | #endif /* !CONFIG_PM */ | |
8173 | ||
649b3b8c | 8174 | static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) |
8175 | { | |
8176 | void __iomem *ioaddr = tp->mmio_addr; | |
8177 | ||
8178 | /* WoL fails with 8168b when the receiver is disabled. */ | |
8179 | switch (tp->mac_version) { | |
8180 | case RTL_GIGA_MAC_VER_11: | |
8181 | case RTL_GIGA_MAC_VER_12: | |
8182 | case RTL_GIGA_MAC_VER_17: | |
8183 | pci_clear_master(tp->pci_dev); | |
8184 | ||
8185 | RTL_W8(ChipCmd, CmdRxEnb); | |
8186 | /* PCI commit */ | |
8187 | RTL_R8(ChipCmd); | |
8188 | break; | |
8189 | default: | |
8190 | break; | |
8191 | } | |
8192 | } | |
8193 | ||
1765f95d FR |
8194 | static void rtl_shutdown(struct pci_dev *pdev) |
8195 | { | |
861ab440 | 8196 | struct net_device *dev = pci_get_drvdata(pdev); |
4bb3f522 | 8197 | struct rtl8169_private *tp = netdev_priv(dev); |
2a15cd2f | 8198 | struct device *d = &pdev->dev; |
8199 | ||
8200 | pm_runtime_get_sync(d); | |
861ab440 RW |
8201 | |
8202 | rtl8169_net_suspend(dev); | |
1765f95d | 8203 | |
cecb5fd7 | 8204 | /* Restore original MAC address */ |
cc098dc7 IV |
8205 | rtl_rar_set(tp, dev->perm_addr); |
8206 | ||
92fc43b4 | 8207 | rtl8169_hw_reset(tp); |
4bb3f522 | 8208 | |
861ab440 | 8209 | if (system_state == SYSTEM_POWER_OFF) { |
649b3b8c | 8210 | if (__rtl8169_get_wol(tp) & WAKE_ANY) { |
8211 | rtl_wol_suspend_quirk(tp); | |
8212 | rtl_wol_shutdown_quirk(tp); | |
ca52efd5 | 8213 | } |
8214 | ||
861ab440 RW |
8215 | pci_wake_from_d3(pdev, true); |
8216 | pci_set_power_state(pdev, PCI_D3hot); | |
8217 | } | |
2a15cd2f | 8218 | |
8219 | pm_runtime_put_noidle(d); | |
861ab440 | 8220 | } |
5d06a99f | 8221 | |
baf63293 | 8222 | static void rtl_remove_one(struct pci_dev *pdev) |
e27566ed FR |
8223 | { |
8224 | struct net_device *dev = pci_get_drvdata(pdev); | |
8225 | struct rtl8169_private *tp = netdev_priv(dev); | |
8226 | ||
ee7a1beb CHL |
8227 | if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
8228 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
935e2218 CHL |
8229 | tp->mac_version == RTL_GIGA_MAC_VER_31 || |
8230 | tp->mac_version == RTL_GIGA_MAC_VER_49 || | |
8231 | tp->mac_version == RTL_GIGA_MAC_VER_50 || | |
8232 | tp->mac_version == RTL_GIGA_MAC_VER_51) && | |
ee7a1beb | 8233 | r8168_check_dash(tp)) { |
e27566ed FR |
8234 | rtl8168_driver_stop(tp); |
8235 | } | |
8236 | ||
ad1be8d3 DN |
8237 | netif_napi_del(&tp->napi); |
8238 | ||
e27566ed FR |
8239 | unregister_netdev(dev); |
8240 | ||
8241 | rtl_release_firmware(tp); | |
8242 | ||
8243 | if (pci_dev_run_wake(pdev)) | |
8244 | pm_runtime_get_noresume(&pdev->dev); | |
8245 | ||
8246 | /* restore original MAC address */ | |
8247 | rtl_rar_set(tp, dev->perm_addr); | |
e27566ed FR |
8248 | } |
8249 | ||
fa9c385e | 8250 | static const struct net_device_ops rtl_netdev_ops = { |
df43ac78 | 8251 | .ndo_open = rtl_open, |
fa9c385e FR |
8252 | .ndo_stop = rtl8169_close, |
8253 | .ndo_get_stats64 = rtl8169_get_stats64, | |
8254 | .ndo_start_xmit = rtl8169_start_xmit, | |
8255 | .ndo_tx_timeout = rtl8169_tx_timeout, | |
8256 | .ndo_validate_addr = eth_validate_addr, | |
8257 | .ndo_change_mtu = rtl8169_change_mtu, | |
8258 | .ndo_fix_features = rtl8169_fix_features, | |
8259 | .ndo_set_features = rtl8169_set_features, | |
8260 | .ndo_set_mac_address = rtl_set_mac_address, | |
8261 | .ndo_do_ioctl = rtl8169_ioctl, | |
8262 | .ndo_set_rx_mode = rtl_set_rx_mode, | |
8263 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
8264 | .ndo_poll_controller = rtl8169_netpoll, | |
8265 | #endif | |
8266 | ||
8267 | }; | |
8268 | ||
31fa8b18 FR |
8269 | static const struct rtl_cfg_info { |
8270 | void (*hw_start)(struct net_device *); | |
8271 | unsigned int region; | |
8272 | unsigned int align; | |
8273 | u16 event_slow; | |
8274 | unsigned features; | |
50970831 | 8275 | const struct rtl_coalesce_info *coalesce_info; |
31fa8b18 FR |
8276 | u8 default_ver; |
8277 | } rtl_cfg_infos [] = { | |
8278 | [RTL_CFG_0] = { | |
8279 | .hw_start = rtl_hw_start_8169, | |
8280 | .region = 1, | |
8281 | .align = 0, | |
8282 | .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver, | |
8283 | .features = RTL_FEATURE_GMII, | |
50970831 | 8284 | .coalesce_info = rtl_coalesce_info_8169, |
31fa8b18 FR |
8285 | .default_ver = RTL_GIGA_MAC_VER_01, |
8286 | }, | |
8287 | [RTL_CFG_1] = { | |
8288 | .hw_start = rtl_hw_start_8168, | |
8289 | .region = 2, | |
8290 | .align = 8, | |
8291 | .event_slow = SYSErr | LinkChg | RxOverflow, | |
8292 | .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, | |
50970831 | 8293 | .coalesce_info = rtl_coalesce_info_8168_8136, |
31fa8b18 FR |
8294 | .default_ver = RTL_GIGA_MAC_VER_11, |
8295 | }, | |
8296 | [RTL_CFG_2] = { | |
8297 | .hw_start = rtl_hw_start_8101, | |
8298 | .region = 2, | |
8299 | .align = 8, | |
8300 | .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver | | |
8301 | PCSTimeout, | |
8302 | .features = RTL_FEATURE_MSI, | |
50970831 | 8303 | .coalesce_info = rtl_coalesce_info_8168_8136, |
31fa8b18 FR |
8304 | .default_ver = RTL_GIGA_MAC_VER_13, |
8305 | } | |
8306 | }; | |
8307 | ||
8308 | /* Cfg9346_Unlock assumed. */ | |
8309 | static unsigned rtl_try_msi(struct rtl8169_private *tp, | |
8310 | const struct rtl_cfg_info *cfg) | |
8311 | { | |
8312 | void __iomem *ioaddr = tp->mmio_addr; | |
8313 | unsigned msi = 0; | |
8314 | u8 cfg2; | |
8315 | ||
8316 | cfg2 = RTL_R8(Config2) & ~MSIEnable; | |
8317 | if (cfg->features & RTL_FEATURE_MSI) { | |
8318 | if (pci_enable_msi(tp->pci_dev)) { | |
8319 | netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n"); | |
8320 | } else { | |
8321 | cfg2 |= MSIEnable; | |
8322 | msi = RTL_FEATURE_MSI; | |
8323 | } | |
8324 | } | |
8325 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
8326 | RTL_W8(Config2, cfg2); | |
8327 | return msi; | |
8328 | } | |
8329 | ||
c558386b HW |
8330 | DECLARE_RTL_COND(rtl_link_list_ready_cond) |
8331 | { | |
8332 | void __iomem *ioaddr = tp->mmio_addr; | |
8333 | ||
8334 | return RTL_R8(MCU) & LINK_LIST_RDY; | |
8335 | } | |
8336 | ||
8337 | DECLARE_RTL_COND(rtl_rxtx_empty_cond) | |
8338 | { | |
8339 | void __iomem *ioaddr = tp->mmio_addr; | |
8340 | ||
8341 | return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY; | |
8342 | } | |
8343 | ||
baf63293 | 8344 | static void rtl_hw_init_8168g(struct rtl8169_private *tp) |
c558386b HW |
8345 | { |
8346 | void __iomem *ioaddr = tp->mmio_addr; | |
8347 | u32 data; | |
8348 | ||
8349 | tp->ocp_base = OCP_STD_PHY_BASE; | |
8350 | ||
8351 | RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN); | |
8352 | ||
8353 | if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42)) | |
8354 | return; | |
8355 | ||
8356 | if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) | |
8357 | return; | |
8358 | ||
8359 | RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); | |
8360 | msleep(1); | |
8361 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
8362 | ||
5f8bcce9 | 8363 | data = r8168_mac_ocp_read(tp, 0xe8de); |
c558386b HW |
8364 | data &= ~(1 << 14); |
8365 | r8168_mac_ocp_write(tp, 0xe8de, data); | |
8366 | ||
8367 | if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) | |
8368 | return; | |
8369 | ||
5f8bcce9 | 8370 | data = r8168_mac_ocp_read(tp, 0xe8de); |
c558386b HW |
8371 | data |= (1 << 15); |
8372 | r8168_mac_ocp_write(tp, 0xe8de, data); | |
8373 | ||
8374 | if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) | |
8375 | return; | |
8376 | } | |
8377 | ||
003609da CHL |
8378 | static void rtl_hw_init_8168ep(struct rtl8169_private *tp) |
8379 | { | |
8380 | rtl8168ep_stop_cmac(tp); | |
8381 | rtl_hw_init_8168g(tp); | |
8382 | } | |
8383 | ||
baf63293 | 8384 | static void rtl_hw_initialize(struct rtl8169_private *tp) |
c558386b HW |
8385 | { |
8386 | switch (tp->mac_version) { | |
8387 | case RTL_GIGA_MAC_VER_40: | |
8388 | case RTL_GIGA_MAC_VER_41: | |
57538c4a | 8389 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 8390 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 8391 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
8392 | case RTL_GIGA_MAC_VER_45: |
8393 | case RTL_GIGA_MAC_VER_46: | |
8394 | case RTL_GIGA_MAC_VER_47: | |
8395 | case RTL_GIGA_MAC_VER_48: | |
003609da CHL |
8396 | rtl_hw_init_8168g(tp); |
8397 | break; | |
935e2218 CHL |
8398 | case RTL_GIGA_MAC_VER_49: |
8399 | case RTL_GIGA_MAC_VER_50: | |
8400 | case RTL_GIGA_MAC_VER_51: | |
003609da | 8401 | rtl_hw_init_8168ep(tp); |
c558386b | 8402 | break; |
c558386b HW |
8403 | default: |
8404 | break; | |
8405 | } | |
8406 | } | |
8407 | ||
929a031d | 8408 | static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
3b6cf25d FR |
8409 | { |
8410 | const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; | |
8411 | const unsigned int region = cfg->region; | |
8412 | struct rtl8169_private *tp; | |
8413 | struct mii_if_info *mii; | |
8414 | struct net_device *dev; | |
8415 | void __iomem *ioaddr; | |
8416 | int chipset, i; | |
8417 | int rc; | |
8418 | ||
8419 | if (netif_msg_drv(&debug)) { | |
8420 | printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", | |
8421 | MODULENAME, RTL8169_VERSION); | |
8422 | } | |
8423 | ||
4c45d24a HK |
8424 | dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); |
8425 | if (!dev) | |
8426 | return -ENOMEM; | |
3b6cf25d FR |
8427 | |
8428 | SET_NETDEV_DEV(dev, &pdev->dev); | |
fa9c385e | 8429 | dev->netdev_ops = &rtl_netdev_ops; |
3b6cf25d FR |
8430 | tp = netdev_priv(dev); |
8431 | tp->dev = dev; | |
8432 | tp->pci_dev = pdev; | |
8433 | tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); | |
8434 | ||
8435 | mii = &tp->mii; | |
8436 | mii->dev = dev; | |
8437 | mii->mdio_read = rtl_mdio_read; | |
8438 | mii->mdio_write = rtl_mdio_write; | |
8439 | mii->phy_id_mask = 0x1f; | |
8440 | mii->reg_num_mask = 0x1f; | |
8441 | mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); | |
8442 | ||
8443 | /* disable ASPM completely as that cause random device stop working | |
8444 | * problems as well as full system hangs for some PCIe devices users */ | |
8445 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
8446 | PCIE_LINK_STATE_CLKPM); | |
8447 | ||
8448 | /* enable device (incl. PCI PM wakeup and hotplug setup) */ | |
4c45d24a | 8449 | rc = pcim_enable_device(pdev); |
3b6cf25d FR |
8450 | if (rc < 0) { |
8451 | netif_err(tp, probe, dev, "enable failure\n"); | |
4c45d24a | 8452 | return rc; |
3b6cf25d FR |
8453 | } |
8454 | ||
4c45d24a | 8455 | if (pcim_set_mwi(pdev) < 0) |
3b6cf25d FR |
8456 | netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n"); |
8457 | ||
8458 | /* make sure PCI base addr 1 is MMIO */ | |
8459 | if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { | |
8460 | netif_err(tp, probe, dev, | |
8461 | "region #%d not an MMIO resource, aborting\n", | |
8462 | region); | |
4c45d24a | 8463 | return -ENODEV; |
3b6cf25d FR |
8464 | } |
8465 | ||
8466 | /* check for weird/broken PCI region reporting */ | |
8467 | if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { | |
8468 | netif_err(tp, probe, dev, | |
8469 | "Invalid PCI region size(s), aborting\n"); | |
4c45d24a | 8470 | return -ENODEV; |
3b6cf25d FR |
8471 | } |
8472 | ||
8473 | rc = pci_request_regions(pdev, MODULENAME); | |
8474 | if (rc < 0) { | |
8475 | netif_err(tp, probe, dev, "could not request regions\n"); | |
4c45d24a | 8476 | return rc; |
3b6cf25d FR |
8477 | } |
8478 | ||
3b6cf25d | 8479 | /* ioremap MMIO region */ |
4c45d24a HK |
8480 | ioaddr = devm_ioremap(&pdev->dev, pci_resource_start(pdev, region), |
8481 | R8169_REGS_SIZE); | |
3b6cf25d FR |
8482 | if (!ioaddr) { |
8483 | netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n"); | |
4c45d24a | 8484 | return -EIO; |
3b6cf25d FR |
8485 | } |
8486 | tp->mmio_addr = ioaddr; | |
8487 | ||
8488 | if (!pci_is_pcie(pdev)) | |
8489 | netif_info(tp, probe, dev, "not PCI Express\n"); | |
8490 | ||
8491 | /* Identify chip attached to board */ | |
8492 | rtl8169_get_mac_version(tp, dev, cfg->default_ver); | |
8493 | ||
27896c83 AB |
8494 | tp->cp_cmd = 0; |
8495 | ||
8496 | if ((sizeof(dma_addr_t) > 4) && | |
8497 | (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) && | |
8498 | tp->mac_version >= RTL_GIGA_MAC_VER_18)) && | |
f0076436 AB |
8499 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && |
8500 | !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
27896c83 AB |
8501 | |
8502 | /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */ | |
8503 | if (!pci_is_pcie(pdev)) | |
8504 | tp->cp_cmd |= PCIDAC; | |
8505 | dev->features |= NETIF_F_HIGHDMA; | |
8506 | } else { | |
8507 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
8508 | if (rc < 0) { | |
8509 | netif_err(tp, probe, dev, "DMA configuration failed\n"); | |
4c45d24a | 8510 | return rc; |
27896c83 AB |
8511 | } |
8512 | } | |
8513 | ||
3b6cf25d FR |
8514 | rtl_init_rxcfg(tp); |
8515 | ||
8516 | rtl_irq_disable(tp); | |
8517 | ||
c558386b HW |
8518 | rtl_hw_initialize(tp); |
8519 | ||
3b6cf25d FR |
8520 | rtl_hw_reset(tp); |
8521 | ||
8522 | rtl_ack_events(tp, 0xffff); | |
8523 | ||
8524 | pci_set_master(pdev); | |
8525 | ||
3b6cf25d FR |
8526 | rtl_init_mdio_ops(tp); |
8527 | rtl_init_pll_power_ops(tp); | |
8528 | rtl_init_jumbo_ops(tp); | |
beb1fe18 | 8529 | rtl_init_csi_ops(tp); |
3b6cf25d FR |
8530 | |
8531 | rtl8169_print_mac_version(tp); | |
8532 | ||
8533 | chipset = tp->mac_version; | |
8534 | tp->txd_version = rtl_chip_infos[chipset].txd_version; | |
8535 | ||
8536 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
8537 | RTL_W8(Config1, RTL_R8(Config1) | PMEnable); | |
8f9d5138 | 8538 | RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus)); |
6e1d0b89 | 8539 | switch (tp->mac_version) { |
ac85bcdb CHL |
8540 | case RTL_GIGA_MAC_VER_34: |
8541 | case RTL_GIGA_MAC_VER_35: | |
8542 | case RTL_GIGA_MAC_VER_36: | |
8543 | case RTL_GIGA_MAC_VER_37: | |
8544 | case RTL_GIGA_MAC_VER_38: | |
8545 | case RTL_GIGA_MAC_VER_40: | |
8546 | case RTL_GIGA_MAC_VER_41: | |
8547 | case RTL_GIGA_MAC_VER_42: | |
8548 | case RTL_GIGA_MAC_VER_43: | |
8549 | case RTL_GIGA_MAC_VER_44: | |
6e1d0b89 CHL |
8550 | case RTL_GIGA_MAC_VER_45: |
8551 | case RTL_GIGA_MAC_VER_46: | |
ac85bcdb CHL |
8552 | case RTL_GIGA_MAC_VER_47: |
8553 | case RTL_GIGA_MAC_VER_48: | |
935e2218 CHL |
8554 | case RTL_GIGA_MAC_VER_49: |
8555 | case RTL_GIGA_MAC_VER_50: | |
8556 | case RTL_GIGA_MAC_VER_51: | |
6e1d0b89 CHL |
8557 | if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2) |
8558 | tp->features |= RTL_FEATURE_WOL; | |
8559 | if ((RTL_R8(Config3) & LinkUp) != 0) | |
8560 | tp->features |= RTL_FEATURE_WOL; | |
8561 | break; | |
8562 | default: | |
8563 | if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) | |
8564 | tp->features |= RTL_FEATURE_WOL; | |
8565 | break; | |
8566 | } | |
3b6cf25d FR |
8567 | if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) |
8568 | tp->features |= RTL_FEATURE_WOL; | |
8569 | tp->features |= rtl_try_msi(tp, cfg); | |
8570 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
8571 | ||
8572 | if (rtl_tbi_enabled(tp)) { | |
8573 | tp->set_speed = rtl8169_set_speed_tbi; | |
6fa1ba61 | 8574 | tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi; |
3b6cf25d FR |
8575 | tp->phy_reset_enable = rtl8169_tbi_reset_enable; |
8576 | tp->phy_reset_pending = rtl8169_tbi_reset_pending; | |
8577 | tp->link_ok = rtl8169_tbi_link_ok; | |
8578 | tp->do_ioctl = rtl_tbi_ioctl; | |
8579 | } else { | |
8580 | tp->set_speed = rtl8169_set_speed_xmii; | |
6fa1ba61 | 8581 | tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii; |
3b6cf25d FR |
8582 | tp->phy_reset_enable = rtl8169_xmii_reset_enable; |
8583 | tp->phy_reset_pending = rtl8169_xmii_reset_pending; | |
8584 | tp->link_ok = rtl8169_xmii_link_ok; | |
8585 | tp->do_ioctl = rtl_xmii_ioctl; | |
8586 | } | |
8587 | ||
8588 | mutex_init(&tp->wk.mutex); | |
340fea3d KM |
8589 | u64_stats_init(&tp->rx_stats.syncp); |
8590 | u64_stats_init(&tp->tx_stats.syncp); | |
3b6cf25d FR |
8591 | |
8592 | /* Get MAC address */ | |
89cceb27 CHL |
8593 | if (tp->mac_version == RTL_GIGA_MAC_VER_35 || |
8594 | tp->mac_version == RTL_GIGA_MAC_VER_36 || | |
8595 | tp->mac_version == RTL_GIGA_MAC_VER_37 || | |
8596 | tp->mac_version == RTL_GIGA_MAC_VER_38 || | |
8597 | tp->mac_version == RTL_GIGA_MAC_VER_40 || | |
8598 | tp->mac_version == RTL_GIGA_MAC_VER_41 || | |
8599 | tp->mac_version == RTL_GIGA_MAC_VER_42 || | |
8600 | tp->mac_version == RTL_GIGA_MAC_VER_43 || | |
8601 | tp->mac_version == RTL_GIGA_MAC_VER_44 || | |
8602 | tp->mac_version == RTL_GIGA_MAC_VER_45 || | |
6e1d0b89 CHL |
8603 | tp->mac_version == RTL_GIGA_MAC_VER_46 || |
8604 | tp->mac_version == RTL_GIGA_MAC_VER_47 || | |
935e2218 CHL |
8605 | tp->mac_version == RTL_GIGA_MAC_VER_48 || |
8606 | tp->mac_version == RTL_GIGA_MAC_VER_49 || | |
8607 | tp->mac_version == RTL_GIGA_MAC_VER_50 || | |
8608 | tp->mac_version == RTL_GIGA_MAC_VER_51) { | |
6e1d0b89 CHL |
8609 | u16 mac_addr[3]; |
8610 | ||
05b9687b CHL |
8611 | *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC); |
8612 | *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC); | |
6e1d0b89 CHL |
8613 | |
8614 | if (is_valid_ether_addr((u8 *)mac_addr)) | |
8615 | rtl_rar_set(tp, (u8 *)mac_addr); | |
8616 | } | |
3b6cf25d FR |
8617 | for (i = 0; i < ETH_ALEN; i++) |
8618 | dev->dev_addr[i] = RTL_R8(MAC0 + i); | |
3b6cf25d | 8619 | |
7ad24ea4 | 8620 | dev->ethtool_ops = &rtl8169_ethtool_ops; |
3b6cf25d | 8621 | dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
3b6cf25d FR |
8622 | |
8623 | netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); | |
8624 | ||
8625 | /* don't enable SG, IP_CSUM and TSO by default - it might not work | |
8626 | * properly for all devices */ | |
8627 | dev->features |= NETIF_F_RXCSUM | | |
f646968f | 8628 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
3b6cf25d FR |
8629 | |
8630 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | | |
f646968f PM |
8631 | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | |
8632 | NETIF_F_HW_VLAN_CTAG_RX; | |
3b6cf25d FR |
8633 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
8634 | NETIF_F_HIGHDMA; | |
8635 | ||
929a031d | 8636 | tp->cp_cmd |= RxChkSum | RxVlan; |
8637 | ||
8638 | /* | |
8639 | * Pretend we are using VLANs; This bypasses a nasty bug where | |
8640 | * Interrupts stop flowing on high load on 8110SCd controllers. | |
8641 | */ | |
3b6cf25d | 8642 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) |
929a031d | 8643 | /* Disallow toggling */ |
f646968f | 8644 | dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; |
3b6cf25d | 8645 | |
5888d3fc | 8646 | if (tp->txd_version == RTL_TD_0) |
8647 | tp->tso_csum = rtl8169_tso_csum_v1; | |
e974604b | 8648 | else if (tp->txd_version == RTL_TD_1) { |
5888d3fc | 8649 | tp->tso_csum = rtl8169_tso_csum_v2; |
e974604b | 8650 | dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; |
8651 | } else | |
5888d3fc | 8652 | WARN_ON_ONCE(1); |
8653 | ||
3b6cf25d FR |
8654 | dev->hw_features |= NETIF_F_RXALL; |
8655 | dev->hw_features |= NETIF_F_RXFCS; | |
8656 | ||
c7315a95 JW |
8657 | /* MTU range: 60 - hw-specific max */ |
8658 | dev->min_mtu = ETH_ZLEN; | |
8659 | dev->max_mtu = rtl_chip_infos[chipset].jumbo_max; | |
8660 | ||
3b6cf25d FR |
8661 | tp->hw_start = cfg->hw_start; |
8662 | tp->event_slow = cfg->event_slow; | |
50970831 | 8663 | tp->coalesce_info = cfg->coalesce_info; |
3b6cf25d FR |
8664 | |
8665 | tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ? | |
8666 | ~(RxBOVF | RxFOVF) : ~0; | |
8667 | ||
9de36ccf | 8668 | timer_setup(&tp->timer, rtl8169_phy_timer, 0); |
3b6cf25d FR |
8669 | |
8670 | tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; | |
8671 | ||
4c45d24a HK |
8672 | tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), |
8673 | &tp->counters_phys_addr, | |
8674 | GFP_KERNEL); | |
42020320 CV |
8675 | if (!tp->counters) { |
8676 | rc = -ENOMEM; | |
27896c83 | 8677 | goto err_out_msi_5; |
42020320 CV |
8678 | } |
8679 | ||
3b6cf25d FR |
8680 | rc = register_netdev(dev); |
8681 | if (rc < 0) | |
4c45d24a | 8682 | goto err_out_msi_5; |
3b6cf25d FR |
8683 | |
8684 | pci_set_drvdata(pdev, dev); | |
8685 | ||
92a7c4e7 FR |
8686 | netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n", |
8687 | rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr, | |
8688 | (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq); | |
3b6cf25d FR |
8689 | if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) { |
8690 | netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, " | |
8691 | "tx checksumming: %s]\n", | |
8692 | rtl_chip_infos[chipset].jumbo_max, | |
8693 | rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko"); | |
8694 | } | |
8695 | ||
ee7a1beb CHL |
8696 | if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
8697 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
935e2218 CHL |
8698 | tp->mac_version == RTL_GIGA_MAC_VER_31 || |
8699 | tp->mac_version == RTL_GIGA_MAC_VER_49 || | |
8700 | tp->mac_version == RTL_GIGA_MAC_VER_50 || | |
8701 | tp->mac_version == RTL_GIGA_MAC_VER_51) && | |
ee7a1beb | 8702 | r8168_check_dash(tp)) { |
3b6cf25d FR |
8703 | rtl8168_driver_start(tp); |
8704 | } | |
8705 | ||
3b6cf25d FR |
8706 | if (pci_dev_run_wake(pdev)) |
8707 | pm_runtime_put_noidle(&pdev->dev); | |
8708 | ||
8709 | netif_carrier_off(dev); | |
8710 | ||
4c45d24a | 8711 | return 0; |
3b6cf25d | 8712 | |
27896c83 | 8713 | err_out_msi_5: |
ad1be8d3 | 8714 | netif_napi_del(&tp->napi); |
4c45d24a HK |
8715 | |
8716 | return rc; | |
3b6cf25d FR |
8717 | } |
8718 | ||
1da177e4 LT |
8719 | static struct pci_driver rtl8169_pci_driver = { |
8720 | .name = MODULENAME, | |
8721 | .id_table = rtl8169_pci_tbl, | |
3b6cf25d | 8722 | .probe = rtl_init_one, |
baf63293 | 8723 | .remove = rtl_remove_one, |
1765f95d | 8724 | .shutdown = rtl_shutdown, |
861ab440 | 8725 | .driver.pm = RTL8169_PM_OPS, |
1da177e4 LT |
8726 | }; |
8727 | ||
3eeb7da9 | 8728 | module_pci_driver(rtl8169_pci_driver); |