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r8169: add RTL8106E support.
[thirdparty/kernel/stable.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4
LT		 31
32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 36#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 43#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 44#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 46#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 47#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 48#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
bca03d5f 50
1da177e4
LT		 51#ifdef RTL8169_DEBUG
52#define assert(expr) \
5b0384f4
FR		 53 if (!(expr)) { \
54 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 55 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 56 }
06fa7358
JP		 57#define dprintk(fmt, args...) \
58 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 59#else
60#define assert(expr) do {} while (0)
61#define dprintk(fmt, args...) do {} while (0)
62#endif /* RTL8169_DEBUG */
63
b57b7e5a 64#define R8169_MSG_DEFAULT \
f0e837d9 65 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 66
477206a0
JD		 67#define TX_SLOTS_AVAIL(tp) \
68 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
69
70/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
71#define TX_FRAGS_READY_FOR(tp,nr_frags) \
72 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 73
1da177e4
LT		 74/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
75 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 76static const int multicast_filter_limit = 32;
1da177e4 77
9c14ceaf 78#define MAX_READ_REQUEST_SHIFT 12
1da177e4 79#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 80#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
81#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
82
83#define R8169_REGS_SIZE 256
84#define R8169_NAPI_WEIGHT 64
85#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
86#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
87#define RX_BUF_SIZE 1536 /* Rx Buffer size */
88#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
89#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
90
91#define RTL8169_TX_TIMEOUT (6*HZ)
92#define RTL8169_PHY_TIMEOUT (10*HZ)
93
ea8dbdd1 94#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
95#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 96#define RTL_EEPROM_SIG_ADDR 0x0000
97
1da177e4
LT		 98/* write/read MMIO register */
99#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
100#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
101#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
102#define RTL_R8(reg) readb (ioaddr + (reg))
103#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 104#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 105
106enum mac_version {
85bffe6c
FR		 107 RTL_GIGA_MAC_VER_01 = 0,
108 RTL_GIGA_MAC_VER_02,
109 RTL_GIGA_MAC_VER_03,
110 RTL_GIGA_MAC_VER_04,
111 RTL_GIGA_MAC_VER_05,
112 RTL_GIGA_MAC_VER_06,
113 RTL_GIGA_MAC_VER_07,
114 RTL_GIGA_MAC_VER_08,
115 RTL_GIGA_MAC_VER_09,
116 RTL_GIGA_MAC_VER_10,
117 RTL_GIGA_MAC_VER_11,
118 RTL_GIGA_MAC_VER_12,
119 RTL_GIGA_MAC_VER_13,
120 RTL_GIGA_MAC_VER_14,
121 RTL_GIGA_MAC_VER_15,
122 RTL_GIGA_MAC_VER_16,
123 RTL_GIGA_MAC_VER_17,
124 RTL_GIGA_MAC_VER_18,
125 RTL_GIGA_MAC_VER_19,
126 RTL_GIGA_MAC_VER_20,
127 RTL_GIGA_MAC_VER_21,
128 RTL_GIGA_MAC_VER_22,
129 RTL_GIGA_MAC_VER_23,
130 RTL_GIGA_MAC_VER_24,
131 RTL_GIGA_MAC_VER_25,
132 RTL_GIGA_MAC_VER_26,
133 RTL_GIGA_MAC_VER_27,
134 RTL_GIGA_MAC_VER_28,
135 RTL_GIGA_MAC_VER_29,
136 RTL_GIGA_MAC_VER_30,
137 RTL_GIGA_MAC_VER_31,
138 RTL_GIGA_MAC_VER_32,
139 RTL_GIGA_MAC_VER_33,
70090424 140 RTL_GIGA_MAC_VER_34,
c2218925
HW		 141 RTL_GIGA_MAC_VER_35,
142 RTL_GIGA_MAC_VER_36,
7e18dca1 143 RTL_GIGA_MAC_VER_37,
b3d7b2f2 144 RTL_GIGA_MAC_VER_38,
5598bfe5 145 RTL_GIGA_MAC_VER_39,
85bffe6c 146 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 147};
148
2b7b4318
FR		 149enum rtl_tx_desc_version {
150 RTL_TD_0 = 0,
151 RTL_TD_1 = 1,
152};
153
d58d46b5
FR		 154#define JUMBO_1K ETH_DATA_LEN
155#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
156#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
157#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
158#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
159
160#define _R(NAME,TD,FW,SZ,B) { \
161 .name = NAME, \
162 .txd_version = TD, \
163 .fw_name = FW, \
164 .jumbo_max = SZ, \
165 .jumbo_tx_csum = B \
166}
1da177e4 167
3c6bee1d 168static const struct {
1da177e4 169 const char *name;
2b7b4318 170 enum rtl_tx_desc_version txd_version;
953a12cc 171 const char *fw_name;
d58d46b5
FR		 172 u16 jumbo_max;
173 bool jumbo_tx_csum;
85bffe6c
FR		 174} rtl_chip_infos[] = {
175 /* PCI devices. */
176 [RTL_GIGA_MAC_VER_01] =
d58d46b5 177 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 178 [RTL_GIGA_MAC_VER_02] =
d58d46b5 179 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 180 [RTL_GIGA_MAC_VER_03] =
d58d46b5 181 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 182 [RTL_GIGA_MAC_VER_04] =
d58d46b5 183 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 184 [RTL_GIGA_MAC_VER_05] =
d58d46b5 185 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 186 [RTL_GIGA_MAC_VER_06] =
d58d46b5 187 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 188 /* PCI-E devices. */
189 [RTL_GIGA_MAC_VER_07] =
d58d46b5 190 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 191 [RTL_GIGA_MAC_VER_08] =
d58d46b5 192 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 193 [RTL_GIGA_MAC_VER_09] =
d58d46b5 194 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 195 [RTL_GIGA_MAC_VER_10] =
d58d46b5 196 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 197 [RTL_GIGA_MAC_VER_11] =
d58d46b5 198 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 199 [RTL_GIGA_MAC_VER_12] =
d58d46b5 200 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 201 [RTL_GIGA_MAC_VER_13] =
d58d46b5 202 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 203 [RTL_GIGA_MAC_VER_14] =
d58d46b5 204 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 205 [RTL_GIGA_MAC_VER_15] =
d58d46b5 206 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 207 [RTL_GIGA_MAC_VER_16] =
d58d46b5 208 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 209 [RTL_GIGA_MAC_VER_17] =
d58d46b5 210 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 211 [RTL_GIGA_MAC_VER_18] =
d58d46b5 212 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 213 [RTL_GIGA_MAC_VER_19] =
d58d46b5 214 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 215 [RTL_GIGA_MAC_VER_20] =
d58d46b5 216 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 217 [RTL_GIGA_MAC_VER_21] =
d58d46b5 218 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 219 [RTL_GIGA_MAC_VER_22] =
d58d46b5 220 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 221 [RTL_GIGA_MAC_VER_23] =
d58d46b5 222 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 223 [RTL_GIGA_MAC_VER_24] =
d58d46b5 224 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 225 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 226 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
227 JUMBO_9K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 229 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
230 JUMBO_9K, false),
85bffe6c 231 [RTL_GIGA_MAC_VER_27] =
d58d46b5 232 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 233 [RTL_GIGA_MAC_VER_28] =
d58d46b5 234 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 235 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 236 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
237 JUMBO_1K, true),
85bffe6c 238 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 239 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
240 JUMBO_1K, true),
85bffe6c 241 [RTL_GIGA_MAC_VER_31] =
d58d46b5 242 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 244 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
245 JUMBO_9K, false),
85bffe6c 246 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 247 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
248 JUMBO_9K, false),
70090424 249 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 250 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
251 JUMBO_9K, false),
c2218925 252 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 253 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
254 JUMBO_9K, false),
c2218925 255 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 256 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
257 JUMBO_9K, false),
7e18dca1
HW		 258 [RTL_GIGA_MAC_VER_37] =
259 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
260 JUMBO_1K, true),
b3d7b2f2
HW		 261 [RTL_GIGA_MAC_VER_38] =
262 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
263 JUMBO_9K, false),
5598bfe5
HW		 264 [RTL_GIGA_MAC_VER_39] =
265 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
266 JUMBO_1K, true),
953a12cc 267};
85bffe6c 268#undef _R
953a12cc 269
bcf0bf90
FR		 270enum cfg_version {
271 RTL_CFG_0 = 0x00,
272 RTL_CFG_1,
273 RTL_CFG_2
274};
275
a3aa1884 276static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 277 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 278 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 279 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 280 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 281 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
282 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 283 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 284 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 285 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
286 { PCI_VENDOR_ID_LINKSYS, 0x1032,
287 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 288 { 0x0001, 0x8168,
289 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 290 {0,},
291};
292
293MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
294
6f0333b8 295static int rx_buf_sz = 16383;
4300e8c7 296static int use_dac;
b57b7e5a
SH		 297static struct {
298 u32 msg_enable;
299} debug = { -1 };
1da177e4 300
07d3f51f
FR		 301enum rtl_registers {
302 MAC0 = 0, /* Ethernet hardware address. */
773d2021 303 MAC4 = 4,
07d3f51f
FR		 304 MAR0 = 8, /* Multicast filter. */
305 CounterAddrLow = 0x10,
306 CounterAddrHigh = 0x14,
307 TxDescStartAddrLow = 0x20,
308 TxDescStartAddrHigh = 0x24,
309 TxHDescStartAddrLow = 0x28,
310 TxHDescStartAddrHigh = 0x2c,
311 FLASH = 0x30,
312 ERSR = 0x36,
313 ChipCmd = 0x37,
314 TxPoll = 0x38,
315 IntrMask = 0x3c,
316 IntrStatus = 0x3e,
4f6b00e5 317
07d3f51f 318 TxConfig = 0x40,
4f6b00e5
HW		 319#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
320#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 321
4f6b00e5
HW		 322 RxConfig = 0x44,
323#define RX128_INT_EN (1 << 15) /* 8111c and later */
324#define RX_MULTI_EN (1 << 14) /* 8111c only */
325#define RXCFG_FIFO_SHIFT 13
326 /* No threshold before first PCI xfer */
327#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
328#define RXCFG_DMA_SHIFT 8
329 /* Unlimited maximum PCI burst. */
330#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 331
07d3f51f
FR		 332 RxMissed = 0x4c,
333 Cfg9346 = 0x50,
334 Config0 = 0x51,
335 Config1 = 0x52,
336 Config2 = 0x53,
d387b427
FR		 337#define PME_SIGNAL (1 << 5) /* 8168c and later */
338
07d3f51f
FR		 339 Config3 = 0x54,
340 Config4 = 0x55,
341 Config5 = 0x56,
342 MultiIntr = 0x5c,
343 PHYAR = 0x60,
07d3f51f
FR		 344 PHYstatus = 0x6c,
345 RxMaxSize = 0xda,
346 CPlusCmd = 0xe0,
347 IntrMitigate = 0xe2,
348 RxDescAddrLow = 0xe4,
349 RxDescAddrHigh = 0xe8,
f0298f81 350 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
351
352#define NoEarlyTx 0x3f /* Max value : no early transmit. */
353
354 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
355
356#define TxPacketMax (8064 >> 7)
3090bd9a 357#define EarlySize 0x27
f0298f81 358
07d3f51f
FR		 359 FuncEvent = 0xf0,
360 FuncEventMask = 0xf4,
361 FuncPresetState = 0xf8,
362 FuncForceEvent = 0xfc,
1da177e4
LT		 363};
364
f162a5d1
FR		 365enum rtl8110_registers {
366 TBICSR = 0x64,
367 TBI_ANAR = 0x68,
368 TBI_LPAR = 0x6a,
369};
370
371enum rtl8168_8101_registers {
372 CSIDR = 0x64,
373 CSIAR = 0x68,
374#define CSIAR_FLAG 0x80000000
375#define CSIAR_WRITE_CMD 0x80000000
376#define CSIAR_BYTE_ENABLE 0x0f
377#define CSIAR_BYTE_ENABLE_SHIFT 12
378#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 379#define CSIAR_FUNC_CARD 0x00000000
380#define CSIAR_FUNC_SDIO 0x00010000
381#define CSIAR_FUNC_NIC 0x00020000
065c27c1 382 PMCH = 0x6f,
f162a5d1
FR		 383 EPHYAR = 0x80,
384#define EPHYAR_FLAG 0x80000000
385#define EPHYAR_WRITE_CMD 0x80000000
386#define EPHYAR_REG_MASK 0x1f
387#define EPHYAR_REG_SHIFT 16
388#define EPHYAR_DATA_MASK 0xffff
5a5e4443 389 DLLPR = 0xd0,
4f6b00e5 390#define PFM_EN (1 << 6)
f162a5d1
FR		 391 DBG_REG = 0xd1,
392#define FIX_NAK_1 (1 << 4)
393#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 394 TWSI = 0xd2,
395 MCU = 0xd3,
4f6b00e5 396#define NOW_IS_OOB (1 << 7)
5a5e4443
HW		 397#define EN_NDP (1 << 3)
398#define EN_OOB_RESET (1 << 2)
daf9df6d 399 EFUSEAR = 0xdc,
400#define EFUSEAR_FLAG 0x80000000
401#define EFUSEAR_WRITE_CMD 0x80000000
402#define EFUSEAR_READ_CMD 0x00000000
403#define EFUSEAR_REG_MASK 0x03ff
404#define EFUSEAR_REG_SHIFT 8
405#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 406};
407
c0e45c1c 408enum rtl8168_registers {
4f6b00e5
HW		 409 LED_FREQ = 0x1a,
410 EEE_LED = 0x1b,
b646d900 411 ERIDR = 0x70,
412 ERIAR = 0x74,
413#define ERIAR_FLAG 0x80000000
414#define ERIAR_WRITE_CMD 0x80000000
415#define ERIAR_READ_CMD 0x00000000
416#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 417#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 418#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
419#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
420#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
421#define ERIAR_MASK_SHIFT 12
422#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
423#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
424#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 425 EPHY_RXER_NUM = 0x7c,
426 OCPDR = 0xb0, /* OCP GPHY access */
427#define OCPDR_WRITE_CMD 0x80000000
428#define OCPDR_READ_CMD 0x00000000
429#define OCPDR_REG_MASK 0x7f
430#define OCPDR_GPHY_REG_SHIFT 16
431#define OCPDR_DATA_MASK 0xffff
432 OCPAR = 0xb4,
433#define OCPAR_FLAG 0x80000000
434#define OCPAR_GPHY_WRITE_CMD 0x8000f060
435#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 436 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
437 MISC = 0xf0, /* 8168e only. */
cecb5fd7 438#define TXPLA_RST (1 << 29)
5598bfe5 439#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 440#define PWM_EN (1 << 22)
5598bfe5 441#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 442};
443
07d3f51f 444enum rtl_register_content {
1da177e4 445 /* InterruptStatusBits */
07d3f51f
FR		 446 SYSErr = 0x8000,
447 PCSTimeout = 0x4000,
448 SWInt = 0x0100,
449 TxDescUnavail = 0x0080,
450 RxFIFOOver = 0x0040,
451 LinkChg = 0x0020,
452 RxOverflow = 0x0010,
453 TxErr = 0x0008,
454 TxOK = 0x0004,
455 RxErr = 0x0002,
456 RxOK = 0x0001,
1da177e4
LT		 457
458 /* RxStatusDesc */
e03f33af 459 RxBOVF = (1 << 24),
9dccf611
FR		 460 RxFOVF = (1 << 23),
461 RxRWT = (1 << 22),
462 RxRES = (1 << 21),
463 RxRUNT = (1 << 20),
464 RxCRC = (1 << 19),
1da177e4
LT		 465
466 /* ChipCmdBits */
4f6b00e5 467 StopReq = 0x80,
07d3f51f
FR		 468 CmdReset = 0x10,
469 CmdRxEnb = 0x08,
470 CmdTxEnb = 0x04,
471 RxBufEmpty = 0x01,
1da177e4 472
275391a4
FR		 473 /* TXPoll register p.5 */
474 HPQ = 0x80, /* Poll cmd on the high prio queue */
475 NPQ = 0x40, /* Poll cmd on the low prio queue */
476 FSWInt = 0x01, /* Forced software interrupt */
477
1da177e4 478 /* Cfg9346Bits */
07d3f51f
FR		 479 Cfg9346_Lock = 0x00,
480 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 481
482 /* rx_mode_bits */
07d3f51f
FR		 483 AcceptErr = 0x20,
484 AcceptRunt = 0x10,
485 AcceptBroadcast = 0x08,
486 AcceptMulticast = 0x04,
487 AcceptMyPhys = 0x02,
488 AcceptAllPhys = 0x01,
1687b566 489#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 490
1da177e4
LT		 491 /* TxConfigBits */
492 TxInterFrameGapShift = 24,
493 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
494
5d06a99f 495 /* Config1 register p.24 */
f162a5d1
FR		 496 LEDS1 = (1 << 7),
497 LEDS0 = (1 << 6),
f162a5d1
FR		 498 Speed_down = (1 << 4),
499 MEMMAP = (1 << 3),
500 IOMAP = (1 << 2),
501 VPD = (1 << 1),
5d06a99f
FR		 502 PMEnable = (1 << 0), /* Power Management Enable */
503
6dccd16b 504 /* Config2 register p. 25 */
2ca6cf06 505 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 506 PCI_Clock_66MHz = 0x01,
507 PCI_Clock_33MHz = 0x00,
508
61a4dcc2
FR		 509 /* Config3 register p.25 */
510 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
511 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 512 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 513 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 514
d58d46b5
FR		 515 /* Config4 register */
516 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
517
5d06a99f 518 /* Config5 register p.27 */
61a4dcc2
FR		 519 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
520 MWF = (1 << 5), /* Accept Multicast wakeup frame */
521 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 522 Spi_en = (1 << 3),
61a4dcc2 523 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 524 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
525
1da177e4
LT		 526 /* TBICSR p.28 */
527 TBIReset = 0x80000000,
528 TBILoopback = 0x40000000,
529 TBINwEnable = 0x20000000,
530 TBINwRestart = 0x10000000,
531 TBILinkOk = 0x02000000,
532 TBINwComplete = 0x01000000,
533
534 /* CPlusCmd p.31 */
f162a5d1
FR		 535 EnableBist = (1 << 15), // 8168 8101
536 Mac_dbgo_oe = (1 << 14), // 8168 8101
537 Normal_mode = (1 << 13), // unused
538 Force_half_dup = (1 << 12), // 8168 8101
539 Force_rxflow_en = (1 << 11), // 8168 8101
540 Force_txflow_en = (1 << 10), // 8168 8101
541 Cxpl_dbg_sel = (1 << 9), // 8168 8101
542 ASF = (1 << 8), // 8168 8101
543 PktCntrDisable = (1 << 7), // 8168 8101
544 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 545 RxVlan = (1 << 6),
546 RxChkSum = (1 << 5),
547 PCIDAC = (1 << 4),
548 PCIMulRW = (1 << 3),
0e485150
FR		 549 INTT_0 = 0x0000, // 8168
550 INTT_1 = 0x0001, // 8168
551 INTT_2 = 0x0002, // 8168
552 INTT_3 = 0x0003, // 8168
1da177e4
LT		 553
554 /* rtl8169_PHYstatus */
07d3f51f
FR		 555 TBI_Enable = 0x80,
556 TxFlowCtrl = 0x40,
557 RxFlowCtrl = 0x20,
558 _1000bpsF = 0x10,
559 _100bps = 0x08,
560 _10bps = 0x04,
561 LinkStatus = 0x02,
562 FullDup = 0x01,
1da177e4 563
1da177e4 564 /* _TBICSRBit */
07d3f51f 565 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 566
567 /* DumpCounterCommand */
07d3f51f 568 CounterDump = 0x8,
1da177e4
LT		 569};
570
2b7b4318
FR		 571enum rtl_desc_bit {
572 /* First doubleword. */
1da177e4
LT		 573 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
574 RingEnd = (1 << 30), /* End of descriptor ring */
575 FirstFrag = (1 << 29), /* First segment of a packet */
576 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 577};
578
579/* Generic case. */
580enum rtl_tx_desc_bit {
581 /* First doubleword. */
582 TD_LSO = (1 << 27), /* Large Send Offload */
583#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 584
2b7b4318
FR		 585 /* Second doubleword. */
586 TxVlanTag = (1 << 17), /* Add VLAN tag */
587};
588
589/* 8169, 8168b and 810x except 8102e. */
590enum rtl_tx_desc_bit_0 {
591 /* First doubleword. */
592#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
593 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
594 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
595 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
596};
597
598/* 8102e, 8168c and beyond. */
599enum rtl_tx_desc_bit_1 {
600 /* Second doubleword. */
601#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
602 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
603 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
604 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
605};
1da177e4 606
2b7b4318
FR		 607static const struct rtl_tx_desc_info {
608 struct {
609 u32 udp;
610 u32 tcp;
611 } checksum;
612 u16 mss_shift;
613 u16 opts_offset;
614} tx_desc_info [] = {
615 [RTL_TD_0] = {
616 .checksum = {
617 .udp = TD0_IP_CS | TD0_UDP_CS,
618 .tcp = TD0_IP_CS | TD0_TCP_CS
619 },
620 .mss_shift = TD0_MSS_SHIFT,
621 .opts_offset = 0
622 },
623 [RTL_TD_1] = {
624 .checksum = {
625 .udp = TD1_IP_CS | TD1_UDP_CS,
626 .tcp = TD1_IP_CS | TD1_TCP_CS
627 },
628 .mss_shift = TD1_MSS_SHIFT,
629 .opts_offset = 1
630 }
631};
632
633enum rtl_rx_desc_bit {
1da177e4
LT		 634 /* Rx private */
635 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
636 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
637
638#define RxProtoUDP (PID1)
639#define RxProtoTCP (PID0)
640#define RxProtoIP (PID1 | PID0)
641#define RxProtoMask RxProtoIP
642
643 IPFail = (1 << 16), /* IP checksum failed */
644 UDPFail = (1 << 15), /* UDP/IP checksum failed */
645 TCPFail = (1 << 14), /* TCP/IP checksum failed */
646 RxVlanTag = (1 << 16), /* VLAN tag available */
647};
648
649#define RsvdMask 0x3fffc000
650
651struct TxDesc {
6cccd6e7
REB		 652 __le32 opts1;
653 __le32 opts2;
654 __le64 addr;
1da177e4
LT		 655};
656
657struct RxDesc {
6cccd6e7
REB		 658 __le32 opts1;
659 __le32 opts2;
660 __le64 addr;
1da177e4
LT		 661};
662
663struct ring_info {
664 struct sk_buff *skb;
665 u32 len;
666 u8 __pad[sizeof(void *) - sizeof(u32)];
667};
668
f23e7fda 669enum features {
ccdffb9a
FR		 670 RTL_FEATURE_WOL = (1 << 0),
671 RTL_FEATURE_MSI = (1 << 1),
672 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 673};
674
355423d0
IV		 675struct rtl8169_counters {
676 __le64 tx_packets;
677 __le64 rx_packets;
678 __le64 tx_errors;
679 __le32 rx_errors;
680 __le16 rx_missed;
681 __le16 align_errors;
682 __le32 tx_one_collision;
683 __le32 tx_multi_collision;
684 __le64 rx_unicast;
685 __le64 rx_broadcast;
686 __le32 rx_multicast;
687 __le16 tx_aborted;
688 __le16 tx_underun;
689};
690
da78dbff 691enum rtl_flag {
6c4a70c5 692 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 693 RTL_FLAG_TASK_SLOW_PENDING,
694 RTL_FLAG_TASK_RESET_PENDING,
695 RTL_FLAG_TASK_PHY_PENDING,
696 RTL_FLAG_MAX
697};
698
8027aa24
JW		 699struct rtl8169_stats {
700 u64 packets;
701 u64 bytes;
702 struct u64_stats_sync syncp;
703};
704
1da177e4
LT		 705struct rtl8169_private {
706 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 707 struct pci_dev *pci_dev;
c4028958 708 struct net_device *dev;
bea3348e 709 struct napi_struct napi;
b57b7e5a 710 u32 msg_enable;
2b7b4318
FR		 711 u16 txd_version;
712 u16 mac_version;
1da177e4
LT		 713 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
714 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
715 u32 dirty_rx;
716 u32 dirty_tx;
8027aa24
JW		 717 struct rtl8169_stats rx_stats;
718 struct rtl8169_stats tx_stats;
1da177e4
LT		 719 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
720 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
721 dma_addr_t TxPhyAddr;
722 dma_addr_t RxPhyAddr;
6f0333b8 723 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 724 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 725 struct timer_list timer;
726 u16 cp_cmd;
da78dbff
FR		 727
728 u16 event_slow;
c0e45c1c 729
730 struct mdio_ops {
731 void (*write)(void __iomem *, int, int);
732 int (*read)(void __iomem *, int);
733 } mdio_ops;
734
065c27c1 735 struct pll_power_ops {
736 void (*down)(struct rtl8169_private *);
737 void (*up)(struct rtl8169_private *);
738 } pll_power_ops;
739
d58d46b5
FR		 740 struct jumbo_ops {
741 void (*enable)(struct rtl8169_private *);
742 void (*disable)(struct rtl8169_private *);
743 } jumbo_ops;
744
beb1fe18
HW		 745 struct csi_ops {
746 void (*write)(void __iomem *, int, int);
747 u32 (*read)(void __iomem *, int);
748 } csi_ops;
749
54405cde 750 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 751 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 752 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 753 void (*hw_start)(struct net_device *);
4da19633 754 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 755 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 756 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 757
758 struct {
da78dbff
FR		 759 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
760 struct mutex mutex;
4422bcd4
FR		 761 struct work_struct work;
762 } wk;
763
f23e7fda 764 unsigned features;
ccdffb9a
FR		 765
766 struct mii_if_info mii;
355423d0 767 struct rtl8169_counters counters;
e1759441 768 u32 saved_wolopts;
e03f33af 769 u32 opts1_mask;
f1e02ed1 770
b6ffd97f
FR		 771 struct rtl_fw {
772 const struct firmware *fw;
1c361efb
FR		 773
774#define RTL_VER_SIZE 32
775
776 char version[RTL_VER_SIZE];
777
778 struct rtl_fw_phy_action {
779 __le32 *code;
780 size_t size;
781 } phy_action;
b6ffd97f 782 } *rtl_fw;
497888cf 783#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
1da177e4
LT		 784};
785
979b6c13 786MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 787MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 788module_param(use_dac, int, 0);
4300e8c7 789MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 790module_param_named(debug, debug.msg_enable, int, 0);
791MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 792MODULE_LICENSE("GPL");
793MODULE_VERSION(RTL8169_VERSION);
bca03d5f 794MODULE_FIRMWARE(FIRMWARE_8168D_1);
795MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 796MODULE_FIRMWARE(FIRMWARE_8168E_1);
797MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 798MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 799MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 800MODULE_FIRMWARE(FIRMWARE_8168F_1);
801MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 802MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 803MODULE_FIRMWARE(FIRMWARE_8411_1);
5598bfe5 804MODULE_FIRMWARE(FIRMWARE_8106E_1);
1da177e4 805
da78dbff
FR		 806static void rtl_lock_work(struct rtl8169_private *tp)
807{
808 mutex_lock(&tp->wk.mutex);
809}
810
811static void rtl_unlock_work(struct rtl8169_private *tp)
812{
813 mutex_unlock(&tp->wk.mutex);
814}
815
d58d46b5
FR		 816static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
817{
818 int cap = pci_pcie_cap(pdev);
819
820 if (cap) {
821 u16 ctl;
822
823 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
824 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
825 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
826 }
827}
828
b646d900 829static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
830{
831 void __iomem *ioaddr = tp->mmio_addr;
832 int i;
833
834 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
835 for (i = 0; i < 20; i++) {
836 udelay(100);
837 if (RTL_R32(OCPAR) & OCPAR_FLAG)
838 break;
839 }
840 return RTL_R32(OCPDR);
841}
842
843static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
844{
845 void __iomem *ioaddr = tp->mmio_addr;
846 int i;
847
848 RTL_W32(OCPDR, data);
849 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
850 for (i = 0; i < 20; i++) {
851 udelay(100);
852 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
853 break;
854 }
855}
856
fac5b3ca 857static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 858{
fac5b3ca 859 void __iomem *ioaddr = tp->mmio_addr;
b646d900 860 int i;
861
862 RTL_W8(ERIDR, cmd);
863 RTL_W32(ERIAR, 0x800010e8);
864 msleep(2);
865 for (i = 0; i < 5; i++) {
866 udelay(100);
1e4e82ba 867 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
b646d900 868 break;
869 }
870
fac5b3ca 871 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 872}
873
874#define OOB_CMD_RESET 0x00
875#define OOB_CMD_DRIVER_START 0x05
876#define OOB_CMD_DRIVER_STOP 0x06
877
cecb5fd7
FR		 878static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
879{
880 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
881}
882
b646d900 883static void rtl8168_driver_start(struct rtl8169_private *tp)
884{
cecb5fd7 885 u16 reg;
b646d900 886 int i;
887
888 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
889
cecb5fd7 890 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 891
b646d900 892 for (i = 0; i < 10; i++) {
893 msleep(10);
4804b3b3 894 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 895 break;
896 }
897}
898
899static void rtl8168_driver_stop(struct rtl8169_private *tp)
900{
cecb5fd7 901 u16 reg;
b646d900 902 int i;
903
904 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
905
cecb5fd7 906 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 907
b646d900 908 for (i = 0; i < 10; i++) {
909 msleep(10);
4804b3b3 910 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 911 break;
912 }
913}
914
4804b3b3 915static int r8168dp_check_dash(struct rtl8169_private *tp)
916{
cecb5fd7 917 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 918
cecb5fd7 919 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 920}
b646d900 921
4da19633 922static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 923{
924 int i;
925
a6baf3af 926 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 927
2371408c 928 for (i = 20; i > 0; i--) {
07d3f51f
FR		 929 /*
930 * Check if the RTL8169 has completed writing to the specified
931 * MII register.
932 */
5b0384f4 933 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 934 break;
2371408c 935 udelay(25);
1da177e4 936 }
024a07ba 937 /*
81a95f04
TT		 938 * According to hardware specs a 20us delay is required after write
939 * complete indication, but before sending next command.
024a07ba 940 */
81a95f04 941 udelay(20);
1da177e4
LT		 942}
943
4da19633 944static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 945{
946 int i, value = -1;
947
a6baf3af 948 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 949
2371408c 950 for (i = 20; i > 0; i--) {
07d3f51f
FR		 951 /*
952 * Check if the RTL8169 has completed retrieving data from
953 * the specified MII register.
954 */
1da177e4 955 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 956 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 957 break;
958 }
2371408c 959 udelay(25);
1da177e4 960 }
81a95f04
TT		 961 /*
962 * According to hardware specs a 20us delay is required after read
963 * complete indication, but before sending next command.
964 */
965 udelay(20);
966
1da177e4
LT		 967 return value;
968}
969
c0e45c1c 970static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
971{
972 int i;
973
974 RTL_W32(OCPDR, data |
975 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
976 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
977 RTL_W32(EPHY_RXER_NUM, 0);
978
979 for (i = 0; i < 100; i++) {
980 mdelay(1);
981 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
982 break;
983 }
984}
985
986static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
987{
988 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
989 (value & OCPDR_DATA_MASK));
990}
991
992static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
993{
994 int i;
995
996 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
997
998 mdelay(1);
999 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1000 RTL_W32(EPHY_RXER_NUM, 0);
1001
1002 for (i = 0; i < 100; i++) {
1003 mdelay(1);
1004 if (RTL_R32(OCPAR) & OCPAR_FLAG)
1005 break;
1006 }
1007
1008 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
1009}
1010
e6de30d6 1011#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1012
1013static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1014{
1015 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1016}
1017
1018static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1019{
1020 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1021}
1022
1023static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1024{
1025 r8168dp_2_mdio_start(ioaddr);
1026
1027 r8169_mdio_write(ioaddr, reg_addr, value);
1028
1029 r8168dp_2_mdio_stop(ioaddr);
1030}
1031
1032static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1033{
1034 int value;
1035
1036 r8168dp_2_mdio_start(ioaddr);
1037
1038 value = r8169_mdio_read(ioaddr, reg_addr);
1039
1040 r8168dp_2_mdio_stop(ioaddr);
1041
1042 return value;
1043}
1044
4da19633 1045static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1046{
c0e45c1c 1047 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 1048}
1049
4da19633 1050static int rtl_readphy(struct rtl8169_private *tp, int location)
1051{
c0e45c1c 1052 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 1053}
1054
1055static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1056{
1057 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1058}
1059
1060static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1061{
1062 int val;
1063
4da19633 1064 val = rtl_readphy(tp, reg_addr);
1065 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1066}
1067
ccdffb9a
FR		 1068static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1069 int val)
1070{
1071 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1072
4da19633 1073 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1074}
1075
1076static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1077{
1078 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1079
4da19633 1080 return rtl_readphy(tp, location);
ccdffb9a
FR		 1081}
1082
dacf8154
FR		 1083static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1084{
1085 unsigned int i;
1086
1087 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1088 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1089
1090 for (i = 0; i < 100; i++) {
1091 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1092 break;
1093 udelay(10);
1094 }
1095}
1096
1097static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1098{
1099 u16 value = 0xffff;
1100 unsigned int i;
1101
1102 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1103
1104 for (i = 0; i < 100; i++) {
1105 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1106 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1107 break;
1108 }
1109 udelay(10);
1110 }
1111
1112 return value;
1113}
1114
133ac40a
HW		 1115static
1116void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1117{
1118 unsigned int i;
1119
1120 BUG_ON((addr & 3) || (mask == 0));
1121 RTL_W32(ERIDR, val);
1122 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1123
1124 for (i = 0; i < 100; i++) {
1125 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1126 break;
1127 udelay(100);
1128 }
1129}
1130
1131static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1132{
1133 u32 value = ~0x00;
1134 unsigned int i;
1135
1136 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1137
1138 for (i = 0; i < 100; i++) {
1139 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1140 value = RTL_R32(ERIDR);
1141 break;
1142 }
1143 udelay(100);
1144 }
1145
1146 return value;
1147}
1148
1149static void
1150rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1151{
1152 u32 val;
1153
1154 val = rtl_eri_read(ioaddr, addr, type);
1155 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1156}
1157
c28aa385 1158struct exgmac_reg {
1159 u16 addr;
1160 u16 mask;
1161 u32 val;
1162};
1163
1164static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1165 const struct exgmac_reg *r, int len)
1166{
1167 while (len-- > 0) {
1168 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1169 r++;
1170 }
1171}
1172
daf9df6d 1173static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1174{
1175 u8 value = 0xff;
1176 unsigned int i;
1177
1178 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1179
1180 for (i = 0; i < 300; i++) {
1181 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1182 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1183 break;
1184 }
1185 udelay(100);
1186 }
1187
1188 return value;
1189}
1190
9085cdfa
FR		 1191static u16 rtl_get_events(struct rtl8169_private *tp)
1192{
1193 void __iomem *ioaddr = tp->mmio_addr;
1194
1195 return RTL_R16(IntrStatus);
1196}
1197
1198static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1199{
1200 void __iomem *ioaddr = tp->mmio_addr;
1201
1202 RTL_W16(IntrStatus, bits);
1203 mmiowb();
1204}
1205
1206static void rtl_irq_disable(struct rtl8169_private *tp)
1207{
1208 void __iomem *ioaddr = tp->mmio_addr;
1209
1210 RTL_W16(IntrMask, 0);
1211 mmiowb();
1212}
1213
3e990ff5
FR		 1214static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1215{
1216 void __iomem *ioaddr = tp->mmio_addr;
1217
1218 RTL_W16(IntrMask, bits);
1219}
1220
da78dbff
FR		 1221#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1222#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1223#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1224
1225static void rtl_irq_enable_all(struct rtl8169_private *tp)
1226{
1227 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1228}
1229
811fd301 1230static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1231{
811fd301 1232 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1233
9085cdfa 1234 rtl_irq_disable(tp);
da78dbff 1235 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1236 RTL_R8(ChipCmd);
1da177e4
LT		 1237}
1238
4da19633 1239static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1240{
4da19633 1241 void __iomem *ioaddr = tp->mmio_addr;
1242
1da177e4
LT		 1243 return RTL_R32(TBICSR) & TBIReset;
1244}
1245
4da19633 1246static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1247{
4da19633 1248 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1249}
1250
1251static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1252{
1253 return RTL_R32(TBICSR) & TBILinkOk;
1254}
1255
1256static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1257{
1258 return RTL_R8(PHYstatus) & LinkStatus;
1259}
1260
4da19633 1261static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1262{
4da19633 1263 void __iomem *ioaddr = tp->mmio_addr;
1264
1da177e4
LT		 1265 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1266}
1267
4da19633 1268static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1269{
1270 unsigned int val;
1271
4da19633 1272 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1273 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1274}
1275
70090424
HW		 1276static void rtl_link_chg_patch(struct rtl8169_private *tp)
1277{
1278 void __iomem *ioaddr = tp->mmio_addr;
1279 struct net_device *dev = tp->dev;
1280
1281 if (!netif_running(dev))
1282 return;
1283
b3d7b2f2
HW		 1284 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1285 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424
HW		 1286 if (RTL_R8(PHYstatus) & _1000bpsF) {
1287 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1288 0x00000011, ERIAR_EXGMAC);
1289 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1290 0x00000005, ERIAR_EXGMAC);
1291 } else if (RTL_R8(PHYstatus) & _100bps) {
1292 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1293 0x0000001f, ERIAR_EXGMAC);
1294 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1295 0x00000005, ERIAR_EXGMAC);
1296 } else {
1297 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1298 0x0000001f, ERIAR_EXGMAC);
1299 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1300 0x0000003f, ERIAR_EXGMAC);
1301 }
1302 /* Reset packet filter */
1303 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1304 ERIAR_EXGMAC);
1305 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1306 ERIAR_EXGMAC);
c2218925
HW		 1307 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1308 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1309 if (RTL_R8(PHYstatus) & _1000bpsF) {
1310 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1311 0x00000011, ERIAR_EXGMAC);
1312 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1313 0x00000005, ERIAR_EXGMAC);
1314 } else {
1315 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1316 0x0000001f, ERIAR_EXGMAC);
1317 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1318 0x0000003f, ERIAR_EXGMAC);
1319 }
7e18dca1
HW		 1320 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1321 if (RTL_R8(PHYstatus) & _10bps) {
1322 rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011,
1323 0x4d02, ERIAR_EXGMAC);
1324 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_0011,
1325 0x0060, ERIAR_EXGMAC);
1326 } else {
1327 rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011,
1328 0x0000, ERIAR_EXGMAC);
1329 }
70090424
HW		 1330 }
1331}
1332
e4fbce74 1333static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1334 struct rtl8169_private *tp,
1335 void __iomem *ioaddr, bool pm)
1da177e4 1336{
1da177e4 1337 if (tp->link_ok(ioaddr)) {
70090424 1338 rtl_link_chg_patch(tp);
e1759441 1339 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1340 if (pm)
1341 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1342 netif_carrier_on(dev);
1519e57f
FR		 1343 if (net_ratelimit())
1344 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1345 } else {
1da177e4 1346 netif_carrier_off(dev);
bf82c189 1347 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1348 if (pm)
10953db8 1349 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1350 }
1da177e4
LT		 1351}
1352
e4fbce74
RW		 1353static void rtl8169_check_link_status(struct net_device *dev,
1354 struct rtl8169_private *tp,
1355 void __iomem *ioaddr)
1356{
1357 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1358}
1359
e1759441
RW		 1360#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1361
1362static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1363{
61a4dcc2
FR		 1364 void __iomem *ioaddr = tp->mmio_addr;
1365 u8 options;
e1759441 1366 u32 wolopts = 0;
61a4dcc2
FR		 1367
1368 options = RTL_R8(Config1);
1369 if (!(options & PMEnable))
e1759441 1370 return 0;
61a4dcc2
FR		 1371
1372 options = RTL_R8(Config3);
1373 if (options & LinkUp)
e1759441 1374 wolopts |= WAKE_PHY;
61a4dcc2 1375 if (options & MagicPacket)
e1759441 1376 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1377
1378 options = RTL_R8(Config5);
1379 if (options & UWF)
e1759441 1380 wolopts |= WAKE_UCAST;
61a4dcc2 1381 if (options & BWF)
e1759441 1382 wolopts |= WAKE_BCAST;
61a4dcc2 1383 if (options & MWF)
e1759441 1384 wolopts |= WAKE_MCAST;
61a4dcc2 1385
e1759441 1386 return wolopts;
61a4dcc2
FR		 1387}
1388
e1759441 1389static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1390{
1391 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1392
da78dbff 1393 rtl_lock_work(tp);
e1759441
RW		 1394
1395 wol->supported = WAKE_ANY;
1396 wol->wolopts = __rtl8169_get_wol(tp);
1397
da78dbff 1398 rtl_unlock_work(tp);
e1759441
RW		 1399}
1400
1401static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1402{
61a4dcc2 1403 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1404 unsigned int i;
350f7596 1405 static const struct {
61a4dcc2
FR		 1406 u32 opt;
1407 u16 reg;
1408 u8 mask;
1409 } cfg[] = {
61a4dcc2
FR		 1410 { WAKE_PHY, Config3, LinkUp },
1411 { WAKE_MAGIC, Config3, MagicPacket },
1412 { WAKE_UCAST, Config5, UWF },
1413 { WAKE_BCAST, Config5, BWF },
1414 { WAKE_MCAST, Config5, MWF },
1415 { WAKE_ANY, Config5, LanWake }
1416 };
851e6022 1417 u8 options;
61a4dcc2 1418
61a4dcc2
FR		 1419 RTL_W8(Cfg9346, Cfg9346_Unlock);
1420
1421 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
851e6022 1422 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1423 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1424 options |= cfg[i].mask;
1425 RTL_W8(cfg[i].reg, options);
1426 }
1427
851e6022
FR		 1428 switch (tp->mac_version) {
1429 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1430 options = RTL_R8(Config1) & ~PMEnable;
1431 if (wolopts)
1432 options |= PMEnable;
1433 RTL_W8(Config1, options);
1434 break;
1435 default:
d387b427
FR		 1436 options = RTL_R8(Config2) & ~PME_SIGNAL;
1437 if (wolopts)
1438 options |= PME_SIGNAL;
1439 RTL_W8(Config2, options);
851e6022
FR		 1440 break;
1441 }
1442
61a4dcc2 1443 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1444}
1445
1446static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1447{
1448 struct rtl8169_private *tp = netdev_priv(dev);
1449
da78dbff 1450 rtl_lock_work(tp);
61a4dcc2 1451
f23e7fda
FR		 1452 if (wol->wolopts)
1453 tp->features |= RTL_FEATURE_WOL;
1454 else
1455 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1456 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1457
1458 rtl_unlock_work(tp);
61a4dcc2 1459
ea80907f 1460 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1461
61a4dcc2
FR		 1462 return 0;
1463}
1464
31bd204f
FR		 1465static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1466{
85bffe6c 1467 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1468}
1469
1da177e4
LT		 1470static void rtl8169_get_drvinfo(struct net_device *dev,
1471 struct ethtool_drvinfo *info)
1472{
1473 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1474 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1475
68aad78c
RJ		 1476 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1477 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1478 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1479 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1480 if (!IS_ERR_OR_NULL(rtl_fw))
1481 strlcpy(info->fw_version, rtl_fw->version,
1482 sizeof(info->fw_version));
1da177e4
LT		 1483}
1484
1485static int rtl8169_get_regs_len(struct net_device *dev)
1486{
1487 return R8169_REGS_SIZE;
1488}
1489
1490static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1491 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1492{
1493 struct rtl8169_private *tp = netdev_priv(dev);
1494 void __iomem *ioaddr = tp->mmio_addr;
1495 int ret = 0;
1496 u32 reg;
1497
1498 reg = RTL_R32(TBICSR);
1499 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1500 (duplex == DUPLEX_FULL)) {
1501 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1502 } else if (autoneg == AUTONEG_ENABLE)
1503 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1504 else {
bf82c189
JP		 1505 netif_warn(tp, link, dev,
1506 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1507 ret = -EOPNOTSUPP;
1508 }
1509
1510 return ret;
1511}
1512
1513static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1514 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1515{
1516 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1517 int giga_ctrl, bmcr;
54405cde 1518 int rc = -EINVAL;
1da177e4 1519
716b50a3 1520 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1521
1522 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1523 int auto_nego;
1524
4da19633 1525 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1526 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1527 ADVERTISE_100HALF | ADVERTISE_100FULL);
1528
1529 if (adv & ADVERTISED_10baseT_Half)
1530 auto_nego |= ADVERTISE_10HALF;
1531 if (adv & ADVERTISED_10baseT_Full)
1532 auto_nego |= ADVERTISE_10FULL;
1533 if (adv & ADVERTISED_100baseT_Half)
1534 auto_nego |= ADVERTISE_100HALF;
1535 if (adv & ADVERTISED_100baseT_Full)
1536 auto_nego |= ADVERTISE_100FULL;
1537
3577aa1b 1538 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1539
4da19633 1540 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1541 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1542
3577aa1b 1543 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1544 if (tp->mii.supports_gmii) {
54405cde
ON		 1545 if (adv & ADVERTISED_1000baseT_Half)
1546 giga_ctrl |= ADVERTISE_1000HALF;
1547 if (adv & ADVERTISED_1000baseT_Full)
1548 giga_ctrl |= ADVERTISE_1000FULL;
1549 } else if (adv & (ADVERTISED_1000baseT_Half |
1550 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1551 netif_info(tp, link, dev,
1552 "PHY does not support 1000Mbps\n");
54405cde 1553 goto out;
bcf0bf90 1554 }
1da177e4 1555
3577aa1b 1556 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1557
4da19633 1558 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1559 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1560 } else {
1561 giga_ctrl = 0;
1562
1563 if (speed == SPEED_10)
1564 bmcr = 0;
1565 else if (speed == SPEED_100)
1566 bmcr = BMCR_SPEED100;
1567 else
54405cde 1568 goto out;
3577aa1b 1569
1570 if (duplex == DUPLEX_FULL)
1571 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1572 }
1573
4da19633 1574 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1575
cecb5fd7
FR		 1576 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1577 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1578 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1579 rtl_writephy(tp, 0x17, 0x2138);
1580 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1581 } else {
4da19633 1582 rtl_writephy(tp, 0x17, 0x2108);
1583 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1584 }
1585 }
1586
54405cde
ON		 1587 rc = 0;
1588out:
1589 return rc;
1da177e4
LT		 1590}
1591
1592static int rtl8169_set_speed(struct net_device *dev,
54405cde 1593 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1594{
1595 struct rtl8169_private *tp = netdev_priv(dev);
1596 int ret;
1597
54405cde 1598 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1599 if (ret < 0)
1600 goto out;
1da177e4 1601
4876cc1e
FR		 1602 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1603 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1604 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1605 }
1606out:
1da177e4
LT		 1607 return ret;
1608}
1609
1610static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1611{
1612 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1613 int ret;
1614
4876cc1e
FR		 1615 del_timer_sync(&tp->timer);
1616
da78dbff 1617 rtl_lock_work(tp);
cecb5fd7 1618 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1619 cmd->duplex, cmd->advertising);
da78dbff 1620 rtl_unlock_work(tp);
5b0384f4 1621
1da177e4
LT		 1622 return ret;
1623}
1624
c8f44aff
MM		 1625static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1626 netdev_features_t features)
1da177e4 1627{
d58d46b5
FR		 1628 struct rtl8169_private *tp = netdev_priv(dev);
1629
2b7b4318 1630 if (dev->mtu > TD_MSS_MAX)
350fb32a 1631 features &= ~NETIF_F_ALL_TSO;
1da177e4 1632
d58d46b5
FR		 1633 if (dev->mtu > JUMBO_1K &&
1634 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1635 features &= ~NETIF_F_IP_CSUM;
1636
350fb32a 1637 return features;
1da177e4
LT		 1638}
1639
da78dbff
FR		 1640static void __rtl8169_set_features(struct net_device *dev,
1641 netdev_features_t features)
1da177e4
LT		 1642{
1643 struct rtl8169_private *tp = netdev_priv(dev);
6bbe021d 1644 netdev_features_t changed = features ^ dev->features;
da78dbff 1645 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1646
6bbe021d
BG		 1647 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1648 return;
1da177e4 1649
6bbe021d
BG		 1650 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1651 if (features & NETIF_F_RXCSUM)
1652 tp->cp_cmd |= RxChkSum;
1653 else
1654 tp->cp_cmd &= ~RxChkSum;
350fb32a 1655
6bbe021d
BG		 1656 if (dev->features & NETIF_F_HW_VLAN_RX)
1657 tp->cp_cmd |= RxVlan;
1658 else
1659 tp->cp_cmd &= ~RxVlan;
1660
1661 RTL_W16(CPlusCmd, tp->cp_cmd);
1662 RTL_R16(CPlusCmd);
1663 }
1664 if (changed & NETIF_F_RXALL) {
1665 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1666 if (features & NETIF_F_RXALL)
1667 tmp |= (AcceptErr | AcceptRunt);
1668 RTL_W32(RxConfig, tmp);
1669 }
da78dbff 1670}
1da177e4 1671
da78dbff
FR		 1672static int rtl8169_set_features(struct net_device *dev,
1673 netdev_features_t features)
1674{
1675 struct rtl8169_private *tp = netdev_priv(dev);
1676
1677 rtl_lock_work(tp);
1678 __rtl8169_set_features(dev, features);
1679 rtl_unlock_work(tp);
1da177e4
LT		 1680
1681 return 0;
1682}
1683
da78dbff 1684
1da177e4
LT		 1685static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1686 struct sk_buff *skb)
1687{
eab6d18d 1688 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1689 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1690}
1691
7a8fc77b 1692static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1693{
1694 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1695
7a8fc77b
FR		 1696 if (opts2 & RxVlanTag)
1697 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1698
1da177e4 1699 desc->opts2 = 0;
1da177e4
LT		 1700}
1701
ccdffb9a 1702static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1703{
1704 struct rtl8169_private *tp = netdev_priv(dev);
1705 void __iomem *ioaddr = tp->mmio_addr;
1706 u32 status;
1707
1708 cmd->supported =
1709 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1710 cmd->port = PORT_FIBRE;
1711 cmd->transceiver = XCVR_INTERNAL;
1712
1713 status = RTL_R32(TBICSR);
1714 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1715 cmd->autoneg = !!(status & TBINwEnable);
1716
70739497 1717 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1718 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1719
1720 return 0;
1da177e4
LT		 1721}
1722
ccdffb9a 1723static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1724{
1725 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1726
1727 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1728}
1729
1730static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1731{
1732 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1733 int rc;
1da177e4 1734
da78dbff 1735 rtl_lock_work(tp);
ccdffb9a 1736 rc = tp->get_settings(dev, cmd);
da78dbff 1737 rtl_unlock_work(tp);
1da177e4 1738
ccdffb9a 1739 return rc;
1da177e4
LT		 1740}
1741
1742static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1743 void *p)
1744{
5b0384f4 1745 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1746
5b0384f4
FR		 1747 if (regs->len > R8169_REGS_SIZE)
1748 regs->len = R8169_REGS_SIZE;
1da177e4 1749
da78dbff 1750 rtl_lock_work(tp);
5b0384f4 1751 memcpy_fromio(p, tp->mmio_addr, regs->len);
da78dbff 1752 rtl_unlock_work(tp);
1da177e4
LT		 1753}
1754
b57b7e5a
SH		 1755static u32 rtl8169_get_msglevel(struct net_device *dev)
1756{
1757 struct rtl8169_private *tp = netdev_priv(dev);
1758
1759 return tp->msg_enable;
1760}
1761
1762static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1763{
1764 struct rtl8169_private *tp = netdev_priv(dev);
1765
1766 tp->msg_enable = value;
1767}
1768
d4a3a0fc
SH		 1769static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1770 "tx_packets",
1771 "rx_packets",
1772 "tx_errors",
1773 "rx_errors",
1774 "rx_missed",
1775 "align_errors",
1776 "tx_single_collisions",
1777 "tx_multi_collisions",
1778 "unicast",
1779 "broadcast",
1780 "multicast",
1781 "tx_aborted",
1782 "tx_underrun",
1783};
1784
b9f2c044 1785static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1786{
b9f2c044
JG		 1787 switch (sset) {
1788 case ETH_SS_STATS:
1789 return ARRAY_SIZE(rtl8169_gstrings);
1790 default:
1791 return -EOPNOTSUPP;
1792 }
d4a3a0fc
SH		 1793}
1794
355423d0 1795static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1796{
1797 struct rtl8169_private *tp = netdev_priv(dev);
1798 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1799 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1800 struct rtl8169_counters *counters;
1801 dma_addr_t paddr;
1802 u32 cmd;
355423d0 1803 int wait = 1000;
d4a3a0fc 1804
355423d0
IV		 1805 /*
1806 * Some chips are unable to dump tally counters when the receiver
1807 * is disabled.
1808 */
1809 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1810 return;
d4a3a0fc 1811
48addcc9 1812 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1813 if (!counters)
1814 return;
1815
1816 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1817 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1818 RTL_W32(CounterAddrLow, cmd);
1819 RTL_W32(CounterAddrLow, cmd | CounterDump);
1820
355423d0
IV		 1821 while (wait--) {
1822 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1823 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1824 break;
355423d0
IV		 1825 }
1826 udelay(10);
d4a3a0fc
SH		 1827 }
1828
1829 RTL_W32(CounterAddrLow, 0);
1830 RTL_W32(CounterAddrHigh, 0);
1831
48addcc9 1832 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1833}
1834
355423d0
IV		 1835static void rtl8169_get_ethtool_stats(struct net_device *dev,
1836 struct ethtool_stats *stats, u64 *data)
1837{
1838 struct rtl8169_private *tp = netdev_priv(dev);
1839
1840 ASSERT_RTNL();
1841
1842 rtl8169_update_counters(dev);
1843
1844 data[0] = le64_to_cpu(tp->counters.tx_packets);
1845 data[1] = le64_to_cpu(tp->counters.rx_packets);
1846 data[2] = le64_to_cpu(tp->counters.tx_errors);
1847 data[3] = le32_to_cpu(tp->counters.rx_errors);
1848 data[4] = le16_to_cpu(tp->counters.rx_missed);
1849 data[5] = le16_to_cpu(tp->counters.align_errors);
1850 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1851 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1852 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1853 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1854 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1855 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1856 data[12] = le16_to_cpu(tp->counters.tx_underun);
1857}
1858
d4a3a0fc
SH		 1859static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1860{
1861 switch(stringset) {
1862 case ETH_SS_STATS:
1863 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1864 break;
1865 }
1866}
1867
7282d491 1868static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1869 .get_drvinfo = rtl8169_get_drvinfo,
1870 .get_regs_len = rtl8169_get_regs_len,
1871 .get_link = ethtool_op_get_link,
1872 .get_settings = rtl8169_get_settings,
1873 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1874 .get_msglevel = rtl8169_get_msglevel,
1875 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1876 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1877 .get_wol = rtl8169_get_wol,
1878 .set_wol = rtl8169_set_wol,
d4a3a0fc 1879 .get_strings = rtl8169_get_strings,
b9f2c044 1880 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1881 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 1882 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 1883};
1884
07d3f51f 1885static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1886 struct net_device *dev, u8 default_version)
1da177e4 1887{
5d320a20 1888 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1889 /*
1890 * The driver currently handles the 8168Bf and the 8168Be identically
1891 * but they can be identified more specifically through the test below
1892 * if needed:
1893 *
1894 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1895 *
1896 * Same thing for the 8101Eb and the 8101Ec:
1897 *
1898 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1899 */
3744100e 1900 static const struct rtl_mac_info {
1da177e4 1901 u32 mask;
e3cf0cc0 1902 u32 val;
1da177e4
LT		 1903 int mac_version;
1904 } mac_info[] = {
c2218925 1905 /* 8168F family. */
b3d7b2f2 1906 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 1907 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1908 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1909
01dc7fec 1910 /* 8168E family. */
70090424 1911 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 1912 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1913 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1914 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1915
5b538df9 1916 /* 8168D family. */
daf9df6d 1917 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1918 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1919 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1920
e6de30d6 1921 /* 8168DP family. */
1922 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1923 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1924 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1925
ef808d50 1926 /* 8168C family. */
17c99297 1927 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1928 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1929 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1930 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1931 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1932 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1933 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1934 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1935 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1936
1937 /* 8168B family. */
1938 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1939 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1940 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1941 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1942
1943 /* 8101 family. */
5598bfe5
HW		 1944 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
1945 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 1946 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 1947 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1948 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1949 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1950 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1951 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1952 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1953 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1954 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1955 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1956 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1957 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1958 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1959 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1960 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1961 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1962 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1963 /* FIXME: where did these entries come from ? -- FR */
1964 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1965 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1966
1967 /* 8110 family. */
1968 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1969 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1970 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1971 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1972 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1973 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1974
f21b75e9
JD		 1975 /* Catch-all */
1976 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 1977 };
1978 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 1979 u32 reg;
1980
e3cf0cc0
FR		 1981 reg = RTL_R32(TxConfig);
1982 while ((reg & p->mask) != p->val)
1da177e4
LT		 1983 p++;
1984 tp->mac_version = p->mac_version;
5d320a20
FR		 1985
1986 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1987 netif_notice(tp, probe, dev,
1988 "unknown MAC, using family default\n");
1989 tp->mac_version = default_version;
1990 }
1da177e4
LT		 1991}
1992
1993static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1994{
bcf0bf90 1995 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1996}
1997
867763c1
FR		 1998struct phy_reg {
1999 u16 reg;
2000 u16 val;
2001};
2002
4da19633 2003static void rtl_writephy_batch(struct rtl8169_private *tp,
2004 const struct phy_reg *regs, int len)
867763c1
FR		 2005{
2006 while (len-- > 0) {
4da19633 2007 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2008 regs++;
2009 }
2010}
2011
bca03d5f 2012#define PHY_READ 0x00000000
2013#define PHY_DATA_OR 0x10000000
2014#define PHY_DATA_AND 0x20000000
2015#define PHY_BJMPN 0x30000000
2016#define PHY_READ_EFUSE 0x40000000
2017#define PHY_READ_MAC_BYTE 0x50000000
2018#define PHY_WRITE_MAC_BYTE 0x60000000
2019#define PHY_CLEAR_READCOUNT 0x70000000
2020#define PHY_WRITE 0x80000000
2021#define PHY_READCOUNT_EQ_SKIP 0x90000000
2022#define PHY_COMP_EQ_SKIPN 0xa0000000
2023#define PHY_COMP_NEQ_SKIPN 0xb0000000
2024#define PHY_WRITE_PREVIOUS 0xc0000000
2025#define PHY_SKIPN 0xd0000000
2026#define PHY_DELAY_MS 0xe0000000
2027#define PHY_WRITE_ERI_WORD 0xf0000000
2028
960aee6c
HW		 2029struct fw_info {
2030 u32 magic;
2031 char version[RTL_VER_SIZE];
2032 __le32 fw_start;
2033 __le32 fw_len;
2034 u8 chksum;
2035} __packed;
2036
1c361efb
FR		 2037#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2038
2039static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2040{
b6ffd97f 2041 const struct firmware *fw = rtl_fw->fw;
960aee6c 2042 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2043 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2044 char *version = rtl_fw->version;
2045 bool rc = false;
2046
2047 if (fw->size < FW_OPCODE_SIZE)
2048 goto out;
960aee6c
HW		 2049
2050 if (!fw_info->magic) {
2051 size_t i, size, start;
2052 u8 checksum = 0;
2053
2054 if (fw->size < sizeof(*fw_info))
2055 goto out;
2056
2057 for (i = 0; i < fw->size; i++)
2058 checksum += fw->data[i];
2059 if (checksum != 0)
2060 goto out;
2061
2062 start = le32_to_cpu(fw_info->fw_start);
2063 if (start > fw->size)
2064 goto out;
2065
2066 size = le32_to_cpu(fw_info->fw_len);
2067 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2068 goto out;
2069
2070 memcpy(version, fw_info->version, RTL_VER_SIZE);
2071
2072 pa->code = (__le32 *)(fw->data + start);
2073 pa->size = size;
2074 } else {
1c361efb
FR		 2075 if (fw->size % FW_OPCODE_SIZE)
2076 goto out;
2077
2078 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2079
2080 pa->code = (__le32 *)fw->data;
2081 pa->size = fw->size / FW_OPCODE_SIZE;
2082 }
2083 version[RTL_VER_SIZE - 1] = 0;
2084
2085 rc = true;
2086out:
2087 return rc;
2088}
2089
fd112f2e
FR		 2090static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2091 struct rtl_fw_phy_action *pa)
1c361efb 2092{
fd112f2e 2093 bool rc = false;
1c361efb 2094 size_t index;
bca03d5f 2095
1c361efb
FR		 2096 for (index = 0; index < pa->size; index++) {
2097 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2098 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2099
42b82dc1 2100 switch(action & 0xf0000000) {
2101 case PHY_READ:
2102 case PHY_DATA_OR:
2103 case PHY_DATA_AND:
2104 case PHY_READ_EFUSE:
2105 case PHY_CLEAR_READCOUNT:
2106 case PHY_WRITE:
2107 case PHY_WRITE_PREVIOUS:
2108 case PHY_DELAY_MS:
2109 break;
2110
2111 case PHY_BJMPN:
2112 if (regno > index) {
fd112f2e 2113 netif_err(tp, ifup, tp->dev,
cecb5fd7 2114 "Out of range of firmware\n");
fd112f2e 2115 goto out;
42b82dc1 2116 }
2117 break;
2118 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2119 if (index + 2 >= pa->size) {
fd112f2e 2120 netif_err(tp, ifup, tp->dev,
cecb5fd7 2121 "Out of range of firmware\n");
fd112f2e 2122 goto out;
42b82dc1 2123 }
2124 break;
2125 case PHY_COMP_EQ_SKIPN:
2126 case PHY_COMP_NEQ_SKIPN:
2127 case PHY_SKIPN:
1c361efb 2128 if (index + 1 + regno >= pa->size) {
fd112f2e 2129 netif_err(tp, ifup, tp->dev,
cecb5fd7 2130 "Out of range of firmware\n");
fd112f2e 2131 goto out;
42b82dc1 2132 }
bca03d5f 2133 break;
2134
42b82dc1 2135 case PHY_READ_MAC_BYTE:
2136 case PHY_WRITE_MAC_BYTE:
2137 case PHY_WRITE_ERI_WORD:
2138 default:
fd112f2e 2139 netif_err(tp, ifup, tp->dev,
42b82dc1 2140 "Invalid action 0x%08x\n", action);
fd112f2e 2141 goto out;
bca03d5f 2142 }
2143 }
fd112f2e
FR		 2144 rc = true;
2145out:
2146 return rc;
2147}
bca03d5f 2148
fd112f2e
FR		 2149static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2150{
2151 struct net_device *dev = tp->dev;
2152 int rc = -EINVAL;
2153
2154 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2155 netif_err(tp, ifup, dev, "invalid firwmare\n");
2156 goto out;
2157 }
2158
2159 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2160 rc = 0;
2161out:
2162 return rc;
2163}
2164
2165static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2166{
2167 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2168 u32 predata, count;
2169 size_t index;
2170
2171 predata = count = 0;
42b82dc1 2172
1c361efb
FR		 2173 for (index = 0; index < pa->size; ) {
2174 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2175 u32 data = action & 0x0000ffff;
42b82dc1 2176 u32 regno = (action & 0x0fff0000) >> 16;
2177
2178 if (!action)
2179 break;
bca03d5f 2180
2181 switch(action & 0xf0000000) {
42b82dc1 2182 case PHY_READ:
2183 predata = rtl_readphy(tp, regno);
2184 count++;
2185 index++;
2186 break;
2187 case PHY_DATA_OR:
2188 predata |= data;
2189 index++;
2190 break;
2191 case PHY_DATA_AND:
2192 predata &= data;
2193 index++;
2194 break;
2195 case PHY_BJMPN:
2196 index -= regno;
2197 break;
2198 case PHY_READ_EFUSE:
2199 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2200 index++;
2201 break;
2202 case PHY_CLEAR_READCOUNT:
2203 count = 0;
2204 index++;
2205 break;
bca03d5f 2206 case PHY_WRITE:
42b82dc1 2207 rtl_writephy(tp, regno, data);
2208 index++;
2209 break;
2210 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2211 index += (count == data) ? 2 : 1;
bca03d5f 2212 break;
42b82dc1 2213 case PHY_COMP_EQ_SKIPN:
2214 if (predata == data)
2215 index += regno;
2216 index++;
2217 break;
2218 case PHY_COMP_NEQ_SKIPN:
2219 if (predata != data)
2220 index += regno;
2221 index++;
2222 break;
2223 case PHY_WRITE_PREVIOUS:
2224 rtl_writephy(tp, regno, predata);
2225 index++;
2226 break;
2227 case PHY_SKIPN:
2228 index += regno + 1;
2229 break;
2230 case PHY_DELAY_MS:
2231 mdelay(data);
2232 index++;
2233 break;
2234
2235 case PHY_READ_MAC_BYTE:
2236 case PHY_WRITE_MAC_BYTE:
2237 case PHY_WRITE_ERI_WORD:
bca03d5f 2238 default:
2239 BUG();
2240 }
2241 }
2242}
2243
f1e02ed1 2244static void rtl_release_firmware(struct rtl8169_private *tp)
2245{
b6ffd97f
FR		 2246 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2247 release_firmware(tp->rtl_fw->fw);
2248 kfree(tp->rtl_fw);
2249 }
2250 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2251}
2252
953a12cc 2253static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2254{
b6ffd97f 2255 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2256
2257 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
b6ffd97f
FR		 2258 if (!IS_ERR_OR_NULL(rtl_fw))
2259 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2260}
2261
2262static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2263{
2264 if (rtl_readphy(tp, reg) != val)
2265 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2266 else
2267 rtl_apply_firmware(tp);
f1e02ed1 2268}
2269
4da19633 2270static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2271{
350f7596 2272 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2273 { 0x1f, 0x0001 },
2274 { 0x06, 0x006e },
2275 { 0x08, 0x0708 },
2276 { 0x15, 0x4000 },
2277 { 0x18, 0x65c7 },
1da177e4 2278
0b9b571d 2279 { 0x1f, 0x0001 },
2280 { 0x03, 0x00a1 },
2281 { 0x02, 0x0008 },
2282 { 0x01, 0x0120 },
2283 { 0x00, 0x1000 },
2284 { 0x04, 0x0800 },
2285 { 0x04, 0x0000 },
1da177e4 2286
0b9b571d 2287 { 0x03, 0xff41 },
2288 { 0x02, 0xdf60 },
2289 { 0x01, 0x0140 },
2290 { 0x00, 0x0077 },
2291 { 0x04, 0x7800 },
2292 { 0x04, 0x7000 },
2293
2294 { 0x03, 0x802f },
2295 { 0x02, 0x4f02 },
2296 { 0x01, 0x0409 },
2297 { 0x00, 0xf0f9 },
2298 { 0x04, 0x9800 },
2299 { 0x04, 0x9000 },
2300
2301 { 0x03, 0xdf01 },
2302 { 0x02, 0xdf20 },
2303 { 0x01, 0xff95 },
2304 { 0x00, 0xba00 },
2305 { 0x04, 0xa800 },
2306 { 0x04, 0xa000 },
2307
2308 { 0x03, 0xff41 },
2309 { 0x02, 0xdf20 },
2310 { 0x01, 0x0140 },
2311 { 0x00, 0x00bb },
2312 { 0x04, 0xb800 },
2313 { 0x04, 0xb000 },
2314
2315 { 0x03, 0xdf41 },
2316 { 0x02, 0xdc60 },
2317 { 0x01, 0x6340 },
2318 { 0x00, 0x007d },
2319 { 0x04, 0xd800 },
2320 { 0x04, 0xd000 },
2321
2322 { 0x03, 0xdf01 },
2323 { 0x02, 0xdf20 },
2324 { 0x01, 0x100a },
2325 { 0x00, 0xa0ff },
2326 { 0x04, 0xf800 },
2327 { 0x04, 0xf000 },
2328
2329 { 0x1f, 0x0000 },
2330 { 0x0b, 0x0000 },
2331 { 0x00, 0x9200 }
2332 };
1da177e4 2333
4da19633 2334 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2335}
2336
4da19633 2337static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2338{
350f7596 2339 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2340 { 0x1f, 0x0002 },
2341 { 0x01, 0x90d0 },
2342 { 0x1f, 0x0000 }
2343 };
2344
4da19633 2345 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2346}
2347
4da19633 2348static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2349{
2350 struct pci_dev *pdev = tp->pci_dev;
2e955856 2351
ccbae55e
SS		 2352 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2353 (pdev->subsystem_device != 0xe000))
2e955856 2354 return;
2355
4da19633 2356 rtl_writephy(tp, 0x1f, 0x0001);
2357 rtl_writephy(tp, 0x10, 0xf01b);
2358 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2359}
2360
4da19633 2361static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2362{
350f7596 2363 static const struct phy_reg phy_reg_init[] = {
2e955856 2364 { 0x1f, 0x0001 },
2365 { 0x04, 0x0000 },
2366 { 0x03, 0x00a1 },
2367 { 0x02, 0x0008 },
2368 { 0x01, 0x0120 },
2369 { 0x00, 0x1000 },
2370 { 0x04, 0x0800 },
2371 { 0x04, 0x9000 },
2372 { 0x03, 0x802f },
2373 { 0x02, 0x4f02 },
2374 { 0x01, 0x0409 },
2375 { 0x00, 0xf099 },
2376 { 0x04, 0x9800 },
2377 { 0x04, 0xa000 },
2378 { 0x03, 0xdf01 },
2379 { 0x02, 0xdf20 },
2380 { 0x01, 0xff95 },
2381 { 0x00, 0xba00 },
2382 { 0x04, 0xa800 },
2383 { 0x04, 0xf000 },
2384 { 0x03, 0xdf01 },
2385 { 0x02, 0xdf20 },
2386 { 0x01, 0x101a },
2387 { 0x00, 0xa0ff },
2388 { 0x04, 0xf800 },
2389 { 0x04, 0x0000 },
2390 { 0x1f, 0x0000 },
2391
2392 { 0x1f, 0x0001 },
2393 { 0x10, 0xf41b },
2394 { 0x14, 0xfb54 },
2395 { 0x18, 0xf5c7 },
2396 { 0x1f, 0x0000 },
2397
2398 { 0x1f, 0x0001 },
2399 { 0x17, 0x0cc0 },
2400 { 0x1f, 0x0000 }
2401 };
2402
4da19633 2403 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2404
4da19633 2405 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2406}
2407
4da19633 2408static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2409{
350f7596 2410 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2411 { 0x1f, 0x0001 },
2412 { 0x04, 0x0000 },
2413 { 0x03, 0x00a1 },
2414 { 0x02, 0x0008 },
2415 { 0x01, 0x0120 },
2416 { 0x00, 0x1000 },
2417 { 0x04, 0x0800 },
2418 { 0x04, 0x9000 },
2419 { 0x03, 0x802f },
2420 { 0x02, 0x4f02 },
2421 { 0x01, 0x0409 },
2422 { 0x00, 0xf099 },
2423 { 0x04, 0x9800 },
2424 { 0x04, 0xa000 },
2425 { 0x03, 0xdf01 },
2426 { 0x02, 0xdf20 },
2427 { 0x01, 0xff95 },
2428 { 0x00, 0xba00 },
2429 { 0x04, 0xa800 },
2430 { 0x04, 0xf000 },
2431 { 0x03, 0xdf01 },
2432 { 0x02, 0xdf20 },
2433 { 0x01, 0x101a },
2434 { 0x00, 0xa0ff },
2435 { 0x04, 0xf800 },
2436 { 0x04, 0x0000 },
2437 { 0x1f, 0x0000 },
2438
2439 { 0x1f, 0x0001 },
2440 { 0x0b, 0x8480 },
2441 { 0x1f, 0x0000 },
2442
2443 { 0x1f, 0x0001 },
2444 { 0x18, 0x67c7 },
2445 { 0x04, 0x2000 },
2446 { 0x03, 0x002f },
2447 { 0x02, 0x4360 },
2448 { 0x01, 0x0109 },
2449 { 0x00, 0x3022 },
2450 { 0x04, 0x2800 },
2451 { 0x1f, 0x0000 },
2452
2453 { 0x1f, 0x0001 },
2454 { 0x17, 0x0cc0 },
2455 { 0x1f, 0x0000 }
2456 };
2457
4da19633 2458 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2459}
2460
4da19633 2461static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2462{
350f7596 2463 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2464 { 0x10, 0xf41b },
2465 { 0x1f, 0x0000 }
2466 };
2467
4da19633 2468 rtl_writephy(tp, 0x1f, 0x0001);
2469 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2470
4da19633 2471 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2472}
2473
4da19633 2474static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2475{
350f7596 2476 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2477 { 0x1f, 0x0001 },
2478 { 0x10, 0xf41b },
2479 { 0x1f, 0x0000 }
2480 };
2481
4da19633 2482 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2483}
2484
4da19633 2485static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2486{
350f7596 2487 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2488 { 0x1f, 0x0000 },
2489 { 0x1d, 0x0f00 },
2490 { 0x1f, 0x0002 },
2491 { 0x0c, 0x1ec8 },
2492 { 0x1f, 0x0000 }
2493 };
2494
4da19633 2495 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2496}
2497
4da19633 2498static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2499{
350f7596 2500 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2501 { 0x1f, 0x0001 },
2502 { 0x1d, 0x3d98 },
2503 { 0x1f, 0x0000 }
2504 };
2505
4da19633 2506 rtl_writephy(tp, 0x1f, 0x0000);
2507 rtl_patchphy(tp, 0x14, 1 << 5);
2508 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2509
4da19633 2510 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2511}
2512
4da19633 2513static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2514{
350f7596 2515 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2516 { 0x1f, 0x0001 },
2517 { 0x12, 0x2300 },
867763c1
FR		 2518 { 0x1f, 0x0002 },
2519 { 0x00, 0x88d4 },
2520 { 0x01, 0x82b1 },
2521 { 0x03, 0x7002 },
2522 { 0x08, 0x9e30 },
2523 { 0x09, 0x01f0 },
2524 { 0x0a, 0x5500 },
2525 { 0x0c, 0x00c8 },
2526 { 0x1f, 0x0003 },
2527 { 0x12, 0xc096 },
2528 { 0x16, 0x000a },
f50d4275
FR		 2529 { 0x1f, 0x0000 },
2530 { 0x1f, 0x0000 },
2531 { 0x09, 0x2000 },
2532 { 0x09, 0x0000 }
867763c1
FR		 2533 };
2534
4da19633 2535 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2536
4da19633 2537 rtl_patchphy(tp, 0x14, 1 << 5);
2538 rtl_patchphy(tp, 0x0d, 1 << 5);
2539 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2540}
2541
4da19633 2542static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2543{
350f7596 2544 static const struct phy_reg phy_reg_init[] = {
f50d4275 2545 { 0x1f, 0x0001 },
7da97ec9 2546 { 0x12, 0x2300 },
f50d4275
FR		 2547 { 0x03, 0x802f },
2548 { 0x02, 0x4f02 },
2549 { 0x01, 0x0409 },
2550 { 0x00, 0xf099 },
2551 { 0x04, 0x9800 },
2552 { 0x04, 0x9000 },
2553 { 0x1d, 0x3d98 },
7da97ec9
FR		 2554 { 0x1f, 0x0002 },
2555 { 0x0c, 0x7eb8 },
f50d4275
FR		 2556 { 0x06, 0x0761 },
2557 { 0x1f, 0x0003 },
2558 { 0x16, 0x0f0a },
7da97ec9
FR		 2559 { 0x1f, 0x0000 }
2560 };
2561
4da19633 2562 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2563
4da19633 2564 rtl_patchphy(tp, 0x16, 1 << 0);
2565 rtl_patchphy(tp, 0x14, 1 << 5);
2566 rtl_patchphy(tp, 0x0d, 1 << 5);
2567 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2568}
2569
4da19633 2570static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2571{
350f7596 2572 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2573 { 0x1f, 0x0001 },
2574 { 0x12, 0x2300 },
2575 { 0x1d, 0x3d98 },
2576 { 0x1f, 0x0002 },
2577 { 0x0c, 0x7eb8 },
2578 { 0x06, 0x5461 },
2579 { 0x1f, 0x0003 },
2580 { 0x16, 0x0f0a },
2581 { 0x1f, 0x0000 }
2582 };
2583
4da19633 2584 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2585
4da19633 2586 rtl_patchphy(tp, 0x16, 1 << 0);
2587 rtl_patchphy(tp, 0x14, 1 << 5);
2588 rtl_patchphy(tp, 0x0d, 1 << 5);
2589 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2590}
2591
4da19633 2592static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2593{
4da19633 2594 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2595}
2596
bca03d5f 2597static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2598{
350f7596 2599 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2600 /* Channel Estimation */
5b538df9 2601 { 0x1f, 0x0001 },
daf9df6d 2602 { 0x06, 0x4064 },
2603 { 0x07, 0x2863 },
2604 { 0x08, 0x059c },
2605 { 0x09, 0x26b4 },
2606 { 0x0a, 0x6a19 },
2607 { 0x0b, 0xdcc8 },
2608 { 0x10, 0xf06d },
2609 { 0x14, 0x7f68 },
2610 { 0x18, 0x7fd9 },
2611 { 0x1c, 0xf0ff },
2612 { 0x1d, 0x3d9c },
5b538df9 2613 { 0x1f, 0x0003 },
daf9df6d 2614 { 0x12, 0xf49f },
2615 { 0x13, 0x070b },
2616 { 0x1a, 0x05ad },
bca03d5f 2617 { 0x14, 0x94c0 },
2618
2619 /*
2620 * Tx Error Issue
cecb5fd7 2621 * Enhance line driver power
bca03d5f 2622 */
5b538df9 2623 { 0x1f, 0x0002 },
daf9df6d 2624 { 0x06, 0x5561 },
2625 { 0x1f, 0x0005 },
2626 { 0x05, 0x8332 },
bca03d5f 2627 { 0x06, 0x5561 },
2628
2629 /*
2630 * Can not link to 1Gbps with bad cable
2631 * Decrease SNR threshold form 21.07dB to 19.04dB
2632 */
2633 { 0x1f, 0x0001 },
2634 { 0x17, 0x0cc0 },
daf9df6d 2635
5b538df9 2636 { 0x1f, 0x0000 },
bca03d5f 2637 { 0x0d, 0xf880 }
daf9df6d 2638 };
bca03d5f 2639 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2640
4da19633 2641 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2642
bca03d5f 2643 /*
2644 * Rx Error Issue
2645 * Fine Tune Switching regulator parameter
2646 */
4da19633 2647 rtl_writephy(tp, 0x1f, 0x0002);
2648 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2649 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2650
daf9df6d 2651 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2652 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2653 { 0x1f, 0x0002 },
2654 { 0x05, 0x669a },
2655 { 0x1f, 0x0005 },
2656 { 0x05, 0x8330 },
2657 { 0x06, 0x669a },
2658 { 0x1f, 0x0002 }
2659 };
2660 int val;
2661
4da19633 2662 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2663
4da19633 2664 val = rtl_readphy(tp, 0x0d);
daf9df6d 2665
2666 if ((val & 0x00ff) != 0x006c) {
350f7596 2667 static const u32 set[] = {
daf9df6d 2668 0x0065, 0x0066, 0x0067, 0x0068,
2669 0x0069, 0x006a, 0x006b, 0x006c
2670 };
2671 int i;
2672
4da19633 2673 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2674
2675 val &= 0xff00;
2676 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2677 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2678 }
2679 } else {
350f7596 2680 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2681 { 0x1f, 0x0002 },
2682 { 0x05, 0x6662 },
2683 { 0x1f, 0x0005 },
2684 { 0x05, 0x8330 },
2685 { 0x06, 0x6662 }
2686 };
2687
4da19633 2688 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2689 }
2690
bca03d5f 2691 /* RSET couple improve */
4da19633 2692 rtl_writephy(tp, 0x1f, 0x0002);
2693 rtl_patchphy(tp, 0x0d, 0x0300);
2694 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2695
bca03d5f 2696 /* Fine tune PLL performance */
4da19633 2697 rtl_writephy(tp, 0x1f, 0x0002);
2698 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2699 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2700
4da19633 2701 rtl_writephy(tp, 0x1f, 0x0005);
2702 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2703
2704 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2705
4da19633 2706 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2707}
2708
bca03d5f 2709static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2710{
350f7596 2711 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2712 /* Channel Estimation */
daf9df6d 2713 { 0x1f, 0x0001 },
2714 { 0x06, 0x4064 },
2715 { 0x07, 0x2863 },
2716 { 0x08, 0x059c },
2717 { 0x09, 0x26b4 },
2718 { 0x0a, 0x6a19 },
2719 { 0x0b, 0xdcc8 },
2720 { 0x10, 0xf06d },
2721 { 0x14, 0x7f68 },
2722 { 0x18, 0x7fd9 },
2723 { 0x1c, 0xf0ff },
2724 { 0x1d, 0x3d9c },
2725 { 0x1f, 0x0003 },
2726 { 0x12, 0xf49f },
2727 { 0x13, 0x070b },
2728 { 0x1a, 0x05ad },
2729 { 0x14, 0x94c0 },
2730
bca03d5f 2731 /*
2732 * Tx Error Issue
cecb5fd7 2733 * Enhance line driver power
bca03d5f 2734 */
daf9df6d 2735 { 0x1f, 0x0002 },
2736 { 0x06, 0x5561 },
2737 { 0x1f, 0x0005 },
2738 { 0x05, 0x8332 },
bca03d5f 2739 { 0x06, 0x5561 },
2740
2741 /*
2742 * Can not link to 1Gbps with bad cable
2743 * Decrease SNR threshold form 21.07dB to 19.04dB
2744 */
2745 { 0x1f, 0x0001 },
2746 { 0x17, 0x0cc0 },
daf9df6d 2747
2748 { 0x1f, 0x0000 },
bca03d5f 2749 { 0x0d, 0xf880 }
5b538df9 2750 };
bca03d5f 2751 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2752
4da19633 2753 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2754
daf9df6d 2755 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2756 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2757 { 0x1f, 0x0002 },
2758 { 0x05, 0x669a },
5b538df9 2759 { 0x1f, 0x0005 },
daf9df6d 2760 { 0x05, 0x8330 },
2761 { 0x06, 0x669a },
2762
2763 { 0x1f, 0x0002 }
2764 };
2765 int val;
2766
4da19633 2767 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2768
4da19633 2769 val = rtl_readphy(tp, 0x0d);
daf9df6d 2770 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2771 static const u32 set[] = {
daf9df6d 2772 0x0065, 0x0066, 0x0067, 0x0068,
2773 0x0069, 0x006a, 0x006b, 0x006c
2774 };
2775 int i;
2776
4da19633 2777 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2778
2779 val &= 0xff00;
2780 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2781 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2782 }
2783 } else {
350f7596 2784 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2785 { 0x1f, 0x0002 },
2786 { 0x05, 0x2642 },
5b538df9 2787 { 0x1f, 0x0005 },
daf9df6d 2788 { 0x05, 0x8330 },
2789 { 0x06, 0x2642 }
5b538df9
FR		 2790 };
2791
4da19633 2792 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2793 }
2794
bca03d5f 2795 /* Fine tune PLL performance */
4da19633 2796 rtl_writephy(tp, 0x1f, 0x0002);
2797 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2798 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2799
bca03d5f 2800 /* Switching regulator Slew rate */
4da19633 2801 rtl_writephy(tp, 0x1f, 0x0002);
2802 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2803
4da19633 2804 rtl_writephy(tp, 0x1f, 0x0005);
2805 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2806
2807 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2808
4da19633 2809 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2810}
2811
4da19633 2812static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2813{
350f7596 2814 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2815 { 0x1f, 0x0002 },
2816 { 0x10, 0x0008 },
2817 { 0x0d, 0x006c },
2818
2819 { 0x1f, 0x0000 },
2820 { 0x0d, 0xf880 },
2821
2822 { 0x1f, 0x0001 },
2823 { 0x17, 0x0cc0 },
2824
2825 { 0x1f, 0x0001 },
2826 { 0x0b, 0xa4d8 },
2827 { 0x09, 0x281c },
2828 { 0x07, 0x2883 },
2829 { 0x0a, 0x6b35 },
2830 { 0x1d, 0x3da4 },
2831 { 0x1c, 0xeffd },
2832 { 0x14, 0x7f52 },
2833 { 0x18, 0x7fc6 },
2834 { 0x08, 0x0601 },
2835 { 0x06, 0x4063 },
2836 { 0x10, 0xf074 },
2837 { 0x1f, 0x0003 },
2838 { 0x13, 0x0789 },
2839 { 0x12, 0xf4bd },
2840 { 0x1a, 0x04fd },
2841 { 0x14, 0x84b0 },
2842 { 0x1f, 0x0000 },
2843 { 0x00, 0x9200 },
2844
2845 { 0x1f, 0x0005 },
2846 { 0x01, 0x0340 },
2847 { 0x1f, 0x0001 },
2848 { 0x04, 0x4000 },
2849 { 0x03, 0x1d21 },
2850 { 0x02, 0x0c32 },
2851 { 0x01, 0x0200 },
2852 { 0x00, 0x5554 },
2853 { 0x04, 0x4800 },
2854 { 0x04, 0x4000 },
2855 { 0x04, 0xf000 },
2856 { 0x03, 0xdf01 },
2857 { 0x02, 0xdf20 },
2858 { 0x01, 0x101a },
2859 { 0x00, 0xa0ff },
2860 { 0x04, 0xf800 },
2861 { 0x04, 0xf000 },
2862 { 0x1f, 0x0000 },
2863
2864 { 0x1f, 0x0007 },
2865 { 0x1e, 0x0023 },
2866 { 0x16, 0x0000 },
2867 { 0x1f, 0x0000 }
2868 };
2869
4da19633 2870 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2871}
2872
e6de30d6 2873static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2874{
2875 static const struct phy_reg phy_reg_init[] = {
2876 { 0x1f, 0x0001 },
2877 { 0x17, 0x0cc0 },
2878
2879 { 0x1f, 0x0007 },
2880 { 0x1e, 0x002d },
2881 { 0x18, 0x0040 },
2882 { 0x1f, 0x0000 }
2883 };
2884
2885 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2886 rtl_patchphy(tp, 0x0d, 1 << 5);
2887}
2888
70090424 2889static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 2890{
2891 static const struct phy_reg phy_reg_init[] = {
2892 /* Enable Delay cap */
2893 { 0x1f, 0x0005 },
2894 { 0x05, 0x8b80 },
2895 { 0x06, 0xc896 },
2896 { 0x1f, 0x0000 },
2897
2898 /* Channel estimation fine tune */
2899 { 0x1f, 0x0001 },
2900 { 0x0b, 0x6c20 },
2901 { 0x07, 0x2872 },
2902 { 0x1c, 0xefff },
2903 { 0x1f, 0x0003 },
2904 { 0x14, 0x6420 },
2905 { 0x1f, 0x0000 },
2906
2907 /* Update PFM & 10M TX idle timer */
2908 { 0x1f, 0x0007 },
2909 { 0x1e, 0x002f },
2910 { 0x15, 0x1919 },
2911 { 0x1f, 0x0000 },
2912
2913 { 0x1f, 0x0007 },
2914 { 0x1e, 0x00ac },
2915 { 0x18, 0x0006 },
2916 { 0x1f, 0x0000 }
2917 };
2918
15ecd039
FR		 2919 rtl_apply_firmware(tp);
2920
01dc7fec 2921 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2922
2923 /* DCO enable for 10M IDLE Power */
2924 rtl_writephy(tp, 0x1f, 0x0007);
2925 rtl_writephy(tp, 0x1e, 0x0023);
2926 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2927 rtl_writephy(tp, 0x1f, 0x0000);
2928
2929 /* For impedance matching */
2930 rtl_writephy(tp, 0x1f, 0x0002);
2931 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2932 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2933
2934 /* PHY auto speed down */
2935 rtl_writephy(tp, 0x1f, 0x0007);
2936 rtl_writephy(tp, 0x1e, 0x002d);
2937 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2938 rtl_writephy(tp, 0x1f, 0x0000);
2939 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2940
2941 rtl_writephy(tp, 0x1f, 0x0005);
2942 rtl_writephy(tp, 0x05, 0x8b86);
2943 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2944 rtl_writephy(tp, 0x1f, 0x0000);
2945
2946 rtl_writephy(tp, 0x1f, 0x0005);
2947 rtl_writephy(tp, 0x05, 0x8b85);
2948 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2949 rtl_writephy(tp, 0x1f, 0x0007);
2950 rtl_writephy(tp, 0x1e, 0x0020);
2951 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2952 rtl_writephy(tp, 0x1f, 0x0006);
2953 rtl_writephy(tp, 0x00, 0x5a00);
2954 rtl_writephy(tp, 0x1f, 0x0000);
2955 rtl_writephy(tp, 0x0d, 0x0007);
2956 rtl_writephy(tp, 0x0e, 0x003c);
2957 rtl_writephy(tp, 0x0d, 0x4007);
2958 rtl_writephy(tp, 0x0e, 0x0000);
2959 rtl_writephy(tp, 0x0d, 0x0000);
2960}
2961
70090424
HW		 2962static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2963{
2964 static const struct phy_reg phy_reg_init[] = {
2965 /* Enable Delay cap */
2966 { 0x1f, 0x0004 },
2967 { 0x1f, 0x0007 },
2968 { 0x1e, 0x00ac },
2969 { 0x18, 0x0006 },
2970 { 0x1f, 0x0002 },
2971 { 0x1f, 0x0000 },
2972 { 0x1f, 0x0000 },
2973
2974 /* Channel estimation fine tune */
2975 { 0x1f, 0x0003 },
2976 { 0x09, 0xa20f },
2977 { 0x1f, 0x0000 },
2978 { 0x1f, 0x0000 },
2979
2980 /* Green Setting */
2981 { 0x1f, 0x0005 },
2982 { 0x05, 0x8b5b },
2983 { 0x06, 0x9222 },
2984 { 0x05, 0x8b6d },
2985 { 0x06, 0x8000 },
2986 { 0x05, 0x8b76 },
2987 { 0x06, 0x8000 },
2988 { 0x1f, 0x0000 }
2989 };
2990
2991 rtl_apply_firmware(tp);
2992
2993 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2994
2995 /* For 4-corner performance improve */
2996 rtl_writephy(tp, 0x1f, 0x0005);
2997 rtl_writephy(tp, 0x05, 0x8b80);
2998 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2999 rtl_writephy(tp, 0x1f, 0x0000);
3000
3001 /* PHY auto speed down */
3002 rtl_writephy(tp, 0x1f, 0x0004);
3003 rtl_writephy(tp, 0x1f, 0x0007);
3004 rtl_writephy(tp, 0x1e, 0x002d);
3005 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3006 rtl_writephy(tp, 0x1f, 0x0002);
3007 rtl_writephy(tp, 0x1f, 0x0000);
3008 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3009
3010 /* improve 10M EEE waveform */
3011 rtl_writephy(tp, 0x1f, 0x0005);
3012 rtl_writephy(tp, 0x05, 0x8b86);
3013 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3014 rtl_writephy(tp, 0x1f, 0x0000);
3015
3016 /* Improve 2-pair detection performance */
3017 rtl_writephy(tp, 0x1f, 0x0005);
3018 rtl_writephy(tp, 0x05, 0x8b85);
3019 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3020 rtl_writephy(tp, 0x1f, 0x0000);
3021
3022 /* EEE setting */
3023 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
3024 ERIAR_EXGMAC);
3025 rtl_writephy(tp, 0x1f, 0x0005);
3026 rtl_writephy(tp, 0x05, 0x8b85);
3027 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3028 rtl_writephy(tp, 0x1f, 0x0004);
3029 rtl_writephy(tp, 0x1f, 0x0007);
3030 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3031 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3032 rtl_writephy(tp, 0x1f, 0x0002);
3033 rtl_writephy(tp, 0x1f, 0x0000);
3034 rtl_writephy(tp, 0x0d, 0x0007);
3035 rtl_writephy(tp, 0x0e, 0x003c);
3036 rtl_writephy(tp, 0x0d, 0x4007);
3037 rtl_writephy(tp, 0x0e, 0x0000);
3038 rtl_writephy(tp, 0x0d, 0x0000);
3039
3040 /* Green feature */
3041 rtl_writephy(tp, 0x1f, 0x0003);
3042 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3043 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3044 rtl_writephy(tp, 0x1f, 0x0000);
3045}
3046
5f886e08
HW		 3047static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3048{
3049 /* For 4-corner performance improve */
3050 rtl_writephy(tp, 0x1f, 0x0005);
3051 rtl_writephy(tp, 0x05, 0x8b80);
3052 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3053 rtl_writephy(tp, 0x1f, 0x0000);
3054
3055 /* PHY auto speed down */
3056 rtl_writephy(tp, 0x1f, 0x0007);
3057 rtl_writephy(tp, 0x1e, 0x002d);
3058 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3059 rtl_writephy(tp, 0x1f, 0x0000);
3060 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3061
3062 /* Improve 10M EEE waveform */
3063 rtl_writephy(tp, 0x1f, 0x0005);
3064 rtl_writephy(tp, 0x05, 0x8b86);
3065 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3066 rtl_writephy(tp, 0x1f, 0x0000);
3067}
3068
c2218925
HW		 3069static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3070{
3071 static const struct phy_reg phy_reg_init[] = {
3072 /* Channel estimation fine tune */
3073 { 0x1f, 0x0003 },
3074 { 0x09, 0xa20f },
3075 { 0x1f, 0x0000 },
3076
3077 /* Modify green table for giga & fnet */
3078 { 0x1f, 0x0005 },
3079 { 0x05, 0x8b55 },
3080 { 0x06, 0x0000 },
3081 { 0x05, 0x8b5e },
3082 { 0x06, 0x0000 },
3083 { 0x05, 0x8b67 },
3084 { 0x06, 0x0000 },
3085 { 0x05, 0x8b70 },
3086 { 0x06, 0x0000 },
3087 { 0x1f, 0x0000 },
3088 { 0x1f, 0x0007 },
3089 { 0x1e, 0x0078 },
3090 { 0x17, 0x0000 },
3091 { 0x19, 0x00fb },
3092 { 0x1f, 0x0000 },
3093
3094 /* Modify green table for 10M */
3095 { 0x1f, 0x0005 },
3096 { 0x05, 0x8b79 },
3097 { 0x06, 0xaa00 },
3098 { 0x1f, 0x0000 },
3099
3100 /* Disable hiimpedance detection (RTCT) */
3101 { 0x1f, 0x0003 },
3102 { 0x01, 0x328a },
3103 { 0x1f, 0x0000 }
3104 };
3105
3106 rtl_apply_firmware(tp);
3107
3108 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3109
5f886e08 3110 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3111
3112 /* Improve 2-pair detection performance */
3113 rtl_writephy(tp, 0x1f, 0x0005);
3114 rtl_writephy(tp, 0x05, 0x8b85);
3115 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3116 rtl_writephy(tp, 0x1f, 0x0000);
3117}
3118
3119static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3120{
3121 rtl_apply_firmware(tp);
3122
5f886e08 3123 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3124}
3125
b3d7b2f2
HW		 3126static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3127{
3128 void __iomem *ioaddr = tp->mmio_addr;
3129 static const struct phy_reg phy_reg_init[] = {
3130 /* Channel estimation fine tune */
3131 { 0x1f, 0x0003 },
3132 { 0x09, 0xa20f },
3133 { 0x1f, 0x0000 },
3134
3135 /* Modify green table for giga & fnet */
3136 { 0x1f, 0x0005 },
3137 { 0x05, 0x8b55 },
3138 { 0x06, 0x0000 },
3139 { 0x05, 0x8b5e },
3140 { 0x06, 0x0000 },
3141 { 0x05, 0x8b67 },
3142 { 0x06, 0x0000 },
3143 { 0x05, 0x8b70 },
3144 { 0x06, 0x0000 },
3145 { 0x1f, 0x0000 },
3146 { 0x1f, 0x0007 },
3147 { 0x1e, 0x0078 },
3148 { 0x17, 0x0000 },
3149 { 0x19, 0x00aa },
3150 { 0x1f, 0x0000 },
3151
3152 /* Modify green table for 10M */
3153 { 0x1f, 0x0005 },
3154 { 0x05, 0x8b79 },
3155 { 0x06, 0xaa00 },
3156 { 0x1f, 0x0000 },
3157
3158 /* Disable hiimpedance detection (RTCT) */
3159 { 0x1f, 0x0003 },
3160 { 0x01, 0x328a },
3161 { 0x1f, 0x0000 }
3162 };
3163
3164
3165 rtl_apply_firmware(tp);
3166
3167 rtl8168f_hw_phy_config(tp);
3168
3169 /* Improve 2-pair detection performance */
3170 rtl_writephy(tp, 0x1f, 0x0005);
3171 rtl_writephy(tp, 0x05, 0x8b85);
3172 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3173 rtl_writephy(tp, 0x1f, 0x0000);
3174
3175 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3176
3177 /* Modify green table for giga */
3178 rtl_writephy(tp, 0x1f, 0x0005);
3179 rtl_writephy(tp, 0x05, 0x8b54);
3180 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3181 rtl_writephy(tp, 0x05, 0x8b5d);
3182 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3183 rtl_writephy(tp, 0x05, 0x8a7c);
3184 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3185 rtl_writephy(tp, 0x05, 0x8a7f);
3186 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3187 rtl_writephy(tp, 0x05, 0x8a82);
3188 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3189 rtl_writephy(tp, 0x05, 0x8a85);
3190 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3191 rtl_writephy(tp, 0x05, 0x8a88);
3192 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3193 rtl_writephy(tp, 0x1f, 0x0000);
3194
3195 /* uc same-seed solution */
3196 rtl_writephy(tp, 0x1f, 0x0005);
3197 rtl_writephy(tp, 0x05, 0x8b85);
3198 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3199 rtl_writephy(tp, 0x1f, 0x0000);
3200
3201 /* eee setting */
3202 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3203 rtl_writephy(tp, 0x1f, 0x0005);
3204 rtl_writephy(tp, 0x05, 0x8b85);
3205 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3206 rtl_writephy(tp, 0x1f, 0x0004);
3207 rtl_writephy(tp, 0x1f, 0x0007);
3208 rtl_writephy(tp, 0x1e, 0x0020);
3209 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3210 rtl_writephy(tp, 0x1f, 0x0000);
3211 rtl_writephy(tp, 0x0d, 0x0007);
3212 rtl_writephy(tp, 0x0e, 0x003c);
3213 rtl_writephy(tp, 0x0d, 0x4007);
3214 rtl_writephy(tp, 0x0e, 0x0000);
3215 rtl_writephy(tp, 0x0d, 0x0000);
3216
3217 /* Green feature */
3218 rtl_writephy(tp, 0x1f, 0x0003);
3219 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3220 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3221 rtl_writephy(tp, 0x1f, 0x0000);
3222}
3223
4da19633 3224static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3225{
350f7596 3226 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3227 { 0x1f, 0x0003 },
3228 { 0x08, 0x441d },
3229 { 0x01, 0x9100 },
3230 { 0x1f, 0x0000 }
3231 };
3232
4da19633 3233 rtl_writephy(tp, 0x1f, 0x0000);
3234 rtl_patchphy(tp, 0x11, 1 << 12);
3235 rtl_patchphy(tp, 0x19, 1 << 13);
3236 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3237
4da19633 3238 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3239}
3240
5a5e4443
HW		 3241static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3242{
3243 static const struct phy_reg phy_reg_init[] = {
3244 { 0x1f, 0x0005 },
3245 { 0x1a, 0x0000 },
3246 { 0x1f, 0x0000 },
3247
3248 { 0x1f, 0x0004 },
3249 { 0x1c, 0x0000 },
3250 { 0x1f, 0x0000 },
3251
3252 { 0x1f, 0x0001 },
3253 { 0x15, 0x7701 },
3254 { 0x1f, 0x0000 }
3255 };
3256
3257 /* Disable ALDPS before ram code */
3258 rtl_writephy(tp, 0x1f, 0x0000);
3259 rtl_writephy(tp, 0x18, 0x0310);
3260 msleep(100);
3261
953a12cc 3262 rtl_apply_firmware(tp);
5a5e4443
HW		 3263
3264 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3265}
3266
7e18dca1
HW		 3267static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3268{
3269 void __iomem *ioaddr = tp->mmio_addr;
3270
3271 /* Disable ALDPS before setting firmware */
3272 rtl_writephy(tp, 0x1f, 0x0000);
3273 rtl_writephy(tp, 0x18, 0x0310);
3274 msleep(20);
3275
3276 rtl_apply_firmware(tp);
3277
3278 /* EEE setting */
3279 rtl_eri_write(ioaddr, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3280 rtl_writephy(tp, 0x1f, 0x0004);
3281 rtl_writephy(tp, 0x10, 0x401f);
3282 rtl_writephy(tp, 0x19, 0x7030);
3283 rtl_writephy(tp, 0x1f, 0x0000);
3284}
3285
5598bfe5
HW		 3286static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3287{
3288 void __iomem *ioaddr = tp->mmio_addr;
3289
3290 static const struct phy_reg phy_reg_init[] = {
3291 { 0x1f, 0x0004 },
3292 { 0x10, 0xc07f },
3293 { 0x19, 0x7030 },
3294 { 0x1f, 0x0000 }
3295 };
3296
3297 /* Disable ALDPS before ram code */
3298 rtl_writephy(tp, 0x1f, 0x0000);
3299 rtl_writephy(tp, 0x18, 0x0310);
3300 msleep(100);
3301
3302 rtl_apply_firmware(tp);
3303
3304 rtl_eri_write(ioaddr, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3305 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3306
3307 rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3308}
3309
5615d9f1
FR		 3310static void rtl_hw_phy_config(struct net_device *dev)
3311{
3312 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3313
3314 rtl8169_print_mac_version(tp);
3315
3316 switch (tp->mac_version) {
3317 case RTL_GIGA_MAC_VER_01:
3318 break;
3319 case RTL_GIGA_MAC_VER_02:
3320 case RTL_GIGA_MAC_VER_03:
4da19633 3321 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3322 break;
3323 case RTL_GIGA_MAC_VER_04:
4da19633 3324 rtl8169sb_hw_phy_config(tp);
5615d9f1 3325 break;
2e955856 3326 case RTL_GIGA_MAC_VER_05:
4da19633 3327 rtl8169scd_hw_phy_config(tp);
2e955856 3328 break;
8c7006aa 3329 case RTL_GIGA_MAC_VER_06:
4da19633 3330 rtl8169sce_hw_phy_config(tp);
8c7006aa 3331 break;
2857ffb7
FR		 3332 case RTL_GIGA_MAC_VER_07:
3333 case RTL_GIGA_MAC_VER_08:
3334 case RTL_GIGA_MAC_VER_09:
4da19633 3335 rtl8102e_hw_phy_config(tp);
2857ffb7 3336 break;
236b8082 3337 case RTL_GIGA_MAC_VER_11:
4da19633 3338 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3339 break;
3340 case RTL_GIGA_MAC_VER_12:
4da19633 3341 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3342 break;
3343 case RTL_GIGA_MAC_VER_17:
4da19633 3344 rtl8168bef_hw_phy_config(tp);
236b8082 3345 break;
867763c1 3346 case RTL_GIGA_MAC_VER_18:
4da19633 3347 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3348 break;
3349 case RTL_GIGA_MAC_VER_19:
4da19633 3350 rtl8168c_1_hw_phy_config(tp);
867763c1 3351 break;
7da97ec9 3352 case RTL_GIGA_MAC_VER_20:
4da19633 3353 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3354 break;
197ff761 3355 case RTL_GIGA_MAC_VER_21:
4da19633 3356 rtl8168c_3_hw_phy_config(tp);
197ff761 3357 break;
6fb07058 3358 case RTL_GIGA_MAC_VER_22:
4da19633 3359 rtl8168c_4_hw_phy_config(tp);
6fb07058 3360 break;
ef3386f0 3361 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3362 case RTL_GIGA_MAC_VER_24:
4da19633 3363 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3364 break;
5b538df9 3365 case RTL_GIGA_MAC_VER_25:
bca03d5f 3366 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3367 break;
3368 case RTL_GIGA_MAC_VER_26:
bca03d5f 3369 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3370 break;
3371 case RTL_GIGA_MAC_VER_27:
4da19633 3372 rtl8168d_3_hw_phy_config(tp);
5b538df9 3373 break;
e6de30d6 3374 case RTL_GIGA_MAC_VER_28:
3375 rtl8168d_4_hw_phy_config(tp);
3376 break;
5a5e4443
HW		 3377 case RTL_GIGA_MAC_VER_29:
3378 case RTL_GIGA_MAC_VER_30:
3379 rtl8105e_hw_phy_config(tp);
3380 break;
cecb5fd7
FR		 3381 case RTL_GIGA_MAC_VER_31:
3382 /* None. */
3383 break;
01dc7fec 3384 case RTL_GIGA_MAC_VER_32:
01dc7fec 3385 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3386 rtl8168e_1_hw_phy_config(tp);
3387 break;
3388 case RTL_GIGA_MAC_VER_34:
3389 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3390 break;
c2218925
HW		 3391 case RTL_GIGA_MAC_VER_35:
3392 rtl8168f_1_hw_phy_config(tp);
3393 break;
3394 case RTL_GIGA_MAC_VER_36:
3395 rtl8168f_2_hw_phy_config(tp);
3396 break;
ef3386f0 3397
7e18dca1
HW		 3398 case RTL_GIGA_MAC_VER_37:
3399 rtl8402_hw_phy_config(tp);
3400 break;
3401
b3d7b2f2
HW		 3402 case RTL_GIGA_MAC_VER_38:
3403 rtl8411_hw_phy_config(tp);
3404 break;
3405
5598bfe5
HW		 3406 case RTL_GIGA_MAC_VER_39:
3407 rtl8106e_hw_phy_config(tp);
3408 break;
3409
5615d9f1
FR		 3410 default:
3411 break;
3412 }
3413}
3414
da78dbff 3415static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3416{
1da177e4
LT		 3417 struct timer_list *timer = &tp->timer;
3418 void __iomem *ioaddr = tp->mmio_addr;
3419 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3420
bcf0bf90 3421 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3422
4da19633 3423 if (tp->phy_reset_pending(tp)) {
5b0384f4 3424 /*
1da177e4
LT		 3425 * A busy loop could burn quite a few cycles on nowadays CPU.
3426 * Let's delay the execution of the timer for a few ticks.
3427 */
3428 timeout = HZ/10;
3429 goto out_mod_timer;
3430 }
3431
3432 if (tp->link_ok(ioaddr))
da78dbff 3433 return;
1da177e4 3434
da78dbff 3435 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3436
4da19633 3437 tp->phy_reset_enable(tp);
1da177e4
LT		 3438
3439out_mod_timer:
3440 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3441}
3442
3443static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3444{
da78dbff
FR		 3445 if (!test_and_set_bit(flag, tp->wk.flags))
3446 schedule_work(&tp->wk.work);
da78dbff
FR		 3447}
3448
3449static void rtl8169_phy_timer(unsigned long __opaque)
3450{
3451 struct net_device *dev = (struct net_device *)__opaque;
3452 struct rtl8169_private *tp = netdev_priv(dev);
3453
98ddf986 3454 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3455}
3456
1da177e4
LT		 3457static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3458 void __iomem *ioaddr)
3459{
3460 iounmap(ioaddr);
3461 pci_release_regions(pdev);
87aeec76 3462 pci_clear_mwi(pdev);
1da177e4
LT		 3463 pci_disable_device(pdev);
3464 free_netdev(dev);
3465}
3466
bf793295
FR		 3467static void rtl8169_phy_reset(struct net_device *dev,
3468 struct rtl8169_private *tp)
3469{
07d3f51f 3470 unsigned int i;
bf793295 3471
4da19633 3472 tp->phy_reset_enable(tp);
bf793295 3473 for (i = 0; i < 100; i++) {
4da19633 3474 if (!tp->phy_reset_pending(tp))
bf793295
FR		 3475 return;
3476 msleep(1);
3477 }
bf82c189 3478 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 3479}
3480
2544bfc0
FR		 3481static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3482{
3483 void __iomem *ioaddr = tp->mmio_addr;
3484
3485 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3486 (RTL_R8(PHYstatus) & TBI_Enable);
3487}
3488
4ff96fa6
FR		 3489static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3490{
3491 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3492
5615d9f1 3493 rtl_hw_phy_config(dev);
4ff96fa6 3494
77332894
MS		 3495 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3496 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3497 RTL_W8(0x82, 0x01);
3498 }
4ff96fa6 3499
6dccd16b
FR		 3500 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3501
3502 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3503 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3504
bcf0bf90 3505 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3506 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3507 RTL_W8(0x82, 0x01);
3508 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3509 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3510 }
3511
bf793295
FR		 3512 rtl8169_phy_reset(dev, tp);
3513
54405cde 3514 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3515 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3516 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3517 (tp->mii.supports_gmii ?
3518 ADVERTISED_1000baseT_Half |
3519 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3520
2544bfc0 3521 if (rtl_tbi_enabled(tp))
bf82c189 3522 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3523}
3524
773d2021
FR		 3525static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3526{
3527 void __iomem *ioaddr = tp->mmio_addr;
3528 u32 high;
3529 u32 low;
3530
3531 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3532 high = addr[4] | (addr[5] << 8);
3533
da78dbff 3534 rtl_lock_work(tp);
773d2021
FR		 3535
3536 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3537
773d2021 3538 RTL_W32(MAC4, high);
908ba2bf 3539 RTL_R32(MAC4);
3540
78f1cd02 3541 RTL_W32(MAC0, low);
908ba2bf 3542 RTL_R32(MAC0);
3543
c28aa385 3544 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3545 const struct exgmac_reg e[] = {
3546 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3547 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3548 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3549 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3550 low >> 16 },
3551 };
3552
3553 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3554 }
3555
773d2021
FR		 3556 RTL_W8(Cfg9346, Cfg9346_Lock);
3557
da78dbff 3558 rtl_unlock_work(tp);
773d2021
FR		 3559}
3560
3561static int rtl_set_mac_address(struct net_device *dev, void *p)
3562{
3563 struct rtl8169_private *tp = netdev_priv(dev);
3564 struct sockaddr *addr = p;
3565
3566 if (!is_valid_ether_addr(addr->sa_data))
3567 return -EADDRNOTAVAIL;
3568
3569 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3570
3571 rtl_rar_set(tp, dev->dev_addr);
3572
3573 return 0;
3574}
3575
5f787a1a
FR		 3576static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3577{
3578 struct rtl8169_private *tp = netdev_priv(dev);
3579 struct mii_ioctl_data *data = if_mii(ifr);
3580
8b4ab28d
FR		 3581 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3582}
5f787a1a 3583
cecb5fd7
FR		 3584static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3585 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3586{
5f787a1a
FR		 3587 switch (cmd) {
3588 case SIOCGMIIPHY:
3589 data->phy_id = 32; /* Internal PHY */
3590 return 0;
3591
3592 case SIOCGMIIREG:
4da19633 3593 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3594 return 0;
3595
3596 case SIOCSMIIREG:
4da19633 3597 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3598 return 0;
3599 }
3600 return -EOPNOTSUPP;
3601}
3602
8b4ab28d
FR		 3603static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3604{
3605 return -EOPNOTSUPP;
3606}
3607
fbac58fc
FR		 3608static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3609{
3610 if (tp->features & RTL_FEATURE_MSI) {
3611 pci_disable_msi(pdev);
3612 tp->features &= ~RTL_FEATURE_MSI;
3613 }
3614}
3615
c0e45c1c 3616static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3617{
3618 struct mdio_ops *ops = &tp->mdio_ops;
3619
3620 switch (tp->mac_version) {
3621 case RTL_GIGA_MAC_VER_27:
3622 ops->write = r8168dp_1_mdio_write;
3623 ops->read = r8168dp_1_mdio_read;
3624 break;
e6de30d6 3625 case RTL_GIGA_MAC_VER_28:
4804b3b3 3626 case RTL_GIGA_MAC_VER_31:
e6de30d6 3627 ops->write = r8168dp_2_mdio_write;
3628 ops->read = r8168dp_2_mdio_read;
3629 break;
c0e45c1c 3630 default:
3631 ops->write = r8169_mdio_write;
3632 ops->read = r8169_mdio_read;
3633 break;
3634 }
3635}
3636
649b3b8c 3637static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3638{
3639 void __iomem *ioaddr = tp->mmio_addr;
3640
3641 switch (tp->mac_version) {
3642 case RTL_GIGA_MAC_VER_29:
3643 case RTL_GIGA_MAC_VER_30:
3644 case RTL_GIGA_MAC_VER_32:
3645 case RTL_GIGA_MAC_VER_33:
3646 case RTL_GIGA_MAC_VER_34:
7e18dca1 3647 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 3648 case RTL_GIGA_MAC_VER_38:
5598bfe5 3649 case RTL_GIGA_MAC_VER_39:
649b3b8c 3650 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3651 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3652 break;
3653 default:
3654 break;
3655 }
3656}
3657
3658static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3659{
3660 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3661 return false;
3662
3663 rtl_writephy(tp, 0x1f, 0x0000);
3664 rtl_writephy(tp, MII_BMCR, 0x0000);
3665
3666 rtl_wol_suspend_quirk(tp);
3667
3668 return true;
3669}
3670
065c27c1 3671static void r810x_phy_power_down(struct rtl8169_private *tp)
3672{
3673 rtl_writephy(tp, 0x1f, 0x0000);
3674 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3675}
3676
3677static void r810x_phy_power_up(struct rtl8169_private *tp)
3678{
3679 rtl_writephy(tp, 0x1f, 0x0000);
3680 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3681}
3682
3683static void r810x_pll_power_down(struct rtl8169_private *tp)
3684{
0004299a
HW		 3685 void __iomem *ioaddr = tp->mmio_addr;
3686
649b3b8c 3687 if (rtl_wol_pll_power_down(tp))
065c27c1 3688 return;
065c27c1 3689
3690 r810x_phy_power_down(tp);
0004299a
HW		 3691
3692 switch (tp->mac_version) {
3693 case RTL_GIGA_MAC_VER_07:
3694 case RTL_GIGA_MAC_VER_08:
3695 case RTL_GIGA_MAC_VER_09:
3696 case RTL_GIGA_MAC_VER_10:
3697 case RTL_GIGA_MAC_VER_13:
3698 case RTL_GIGA_MAC_VER_16:
3699 break;
3700 default:
3701 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3702 break;
3703 }
065c27c1 3704}
3705
3706static void r810x_pll_power_up(struct rtl8169_private *tp)
3707{
0004299a
HW		 3708 void __iomem *ioaddr = tp->mmio_addr;
3709
065c27c1 3710 r810x_phy_power_up(tp);
0004299a
HW		 3711
3712 switch (tp->mac_version) {
3713 case RTL_GIGA_MAC_VER_07:
3714 case RTL_GIGA_MAC_VER_08:
3715 case RTL_GIGA_MAC_VER_09:
3716 case RTL_GIGA_MAC_VER_10:
3717 case RTL_GIGA_MAC_VER_13:
3718 case RTL_GIGA_MAC_VER_16:
3719 break;
3720 default:
3721 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3722 break;
3723 }
065c27c1 3724}
3725
3726static void r8168_phy_power_up(struct rtl8169_private *tp)
3727{
3728 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3729 switch (tp->mac_version) {
3730 case RTL_GIGA_MAC_VER_11:
3731 case RTL_GIGA_MAC_VER_12:
3732 case RTL_GIGA_MAC_VER_17:
3733 case RTL_GIGA_MAC_VER_18:
3734 case RTL_GIGA_MAC_VER_19:
3735 case RTL_GIGA_MAC_VER_20:
3736 case RTL_GIGA_MAC_VER_21:
3737 case RTL_GIGA_MAC_VER_22:
3738 case RTL_GIGA_MAC_VER_23:
3739 case RTL_GIGA_MAC_VER_24:
3740 case RTL_GIGA_MAC_VER_25:
3741 case RTL_GIGA_MAC_VER_26:
3742 case RTL_GIGA_MAC_VER_27:
3743 case RTL_GIGA_MAC_VER_28:
3744 case RTL_GIGA_MAC_VER_31:
3745 rtl_writephy(tp, 0x0e, 0x0000);
3746 break;
3747 default:
3748 break;
3749 }
065c27c1 3750 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3751}
3752
3753static void r8168_phy_power_down(struct rtl8169_private *tp)
3754{
3755 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3756 switch (tp->mac_version) {
3757 case RTL_GIGA_MAC_VER_32:
3758 case RTL_GIGA_MAC_VER_33:
3759 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3760 break;
3761
3762 case RTL_GIGA_MAC_VER_11:
3763 case RTL_GIGA_MAC_VER_12:
3764 case RTL_GIGA_MAC_VER_17:
3765 case RTL_GIGA_MAC_VER_18:
3766 case RTL_GIGA_MAC_VER_19:
3767 case RTL_GIGA_MAC_VER_20:
3768 case RTL_GIGA_MAC_VER_21:
3769 case RTL_GIGA_MAC_VER_22:
3770 case RTL_GIGA_MAC_VER_23:
3771 case RTL_GIGA_MAC_VER_24:
3772 case RTL_GIGA_MAC_VER_25:
3773 case RTL_GIGA_MAC_VER_26:
3774 case RTL_GIGA_MAC_VER_27:
3775 case RTL_GIGA_MAC_VER_28:
3776 case RTL_GIGA_MAC_VER_31:
3777 rtl_writephy(tp, 0x0e, 0x0200);
3778 default:
3779 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3780 break;
3781 }
065c27c1 3782}
3783
3784static void r8168_pll_power_down(struct rtl8169_private *tp)
3785{
3786 void __iomem *ioaddr = tp->mmio_addr;
3787
cecb5fd7
FR		 3788 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3789 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3790 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3791 r8168dp_check_dash(tp)) {
065c27c1 3792 return;
5d2e1957 3793 }
065c27c1 3794
cecb5fd7
FR		 3795 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3796 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3797 (RTL_R16(CPlusCmd) & ASF)) {
3798 return;
3799 }
3800
01dc7fec 3801 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3802 tp->mac_version == RTL_GIGA_MAC_VER_33)
3803 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3804
649b3b8c 3805 if (rtl_wol_pll_power_down(tp))
065c27c1 3806 return;
065c27c1 3807
3808 r8168_phy_power_down(tp);
3809
3810 switch (tp->mac_version) {
3811 case RTL_GIGA_MAC_VER_25:
3812 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3813 case RTL_GIGA_MAC_VER_27:
3814 case RTL_GIGA_MAC_VER_28:
4804b3b3 3815 case RTL_GIGA_MAC_VER_31:
01dc7fec 3816 case RTL_GIGA_MAC_VER_32:
3817 case RTL_GIGA_MAC_VER_33:
065c27c1 3818 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3819 break;
3820 }
3821}
3822
3823static void r8168_pll_power_up(struct rtl8169_private *tp)
3824{
3825 void __iomem *ioaddr = tp->mmio_addr;
3826
065c27c1 3827 switch (tp->mac_version) {
3828 case RTL_GIGA_MAC_VER_25:
3829 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3830 case RTL_GIGA_MAC_VER_27:
3831 case RTL_GIGA_MAC_VER_28:
4804b3b3 3832 case RTL_GIGA_MAC_VER_31:
01dc7fec 3833 case RTL_GIGA_MAC_VER_32:
3834 case RTL_GIGA_MAC_VER_33:
065c27c1 3835 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3836 break;
3837 }
3838
3839 r8168_phy_power_up(tp);
3840}
3841
d58d46b5
FR		 3842static void rtl_generic_op(struct rtl8169_private *tp,
3843 void (*op)(struct rtl8169_private *))
065c27c1 3844{
3845 if (op)
3846 op(tp);
3847}
3848
3849static void rtl_pll_power_down(struct rtl8169_private *tp)
3850{
d58d46b5 3851 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 3852}
3853
3854static void rtl_pll_power_up(struct rtl8169_private *tp)
3855{
d58d46b5 3856 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 3857}
3858
3859static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3860{
3861 struct pll_power_ops *ops = &tp->pll_power_ops;
3862
3863 switch (tp->mac_version) {
3864 case RTL_GIGA_MAC_VER_07:
3865 case RTL_GIGA_MAC_VER_08:
3866 case RTL_GIGA_MAC_VER_09:
3867 case RTL_GIGA_MAC_VER_10:
3868 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3869 case RTL_GIGA_MAC_VER_29:
3870 case RTL_GIGA_MAC_VER_30:
7e18dca1 3871 case RTL_GIGA_MAC_VER_37:
5598bfe5 3872 case RTL_GIGA_MAC_VER_39:
065c27c1 3873 ops->down = r810x_pll_power_down;
3874 ops->up = r810x_pll_power_up;
3875 break;
3876
3877 case RTL_GIGA_MAC_VER_11:
3878 case RTL_GIGA_MAC_VER_12:
3879 case RTL_GIGA_MAC_VER_17:
3880 case RTL_GIGA_MAC_VER_18:
3881 case RTL_GIGA_MAC_VER_19:
3882 case RTL_GIGA_MAC_VER_20:
3883 case RTL_GIGA_MAC_VER_21:
3884 case RTL_GIGA_MAC_VER_22:
3885 case RTL_GIGA_MAC_VER_23:
3886 case RTL_GIGA_MAC_VER_24:
3887 case RTL_GIGA_MAC_VER_25:
3888 case RTL_GIGA_MAC_VER_26:
3889 case RTL_GIGA_MAC_VER_27:
e6de30d6 3890 case RTL_GIGA_MAC_VER_28:
4804b3b3 3891 case RTL_GIGA_MAC_VER_31:
01dc7fec 3892 case RTL_GIGA_MAC_VER_32:
3893 case RTL_GIGA_MAC_VER_33:
70090424 3894 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 3895 case RTL_GIGA_MAC_VER_35:
3896 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 3897 case RTL_GIGA_MAC_VER_38:
065c27c1 3898 ops->down = r8168_pll_power_down;
3899 ops->up = r8168_pll_power_up;
3900 break;
3901
3902 default:
3903 ops->down = NULL;
3904 ops->up = NULL;
3905 break;
3906 }
3907}
3908
e542a226
HW		 3909static void rtl_init_rxcfg(struct rtl8169_private *tp)
3910{
3911 void __iomem *ioaddr = tp->mmio_addr;
3912
3913 switch (tp->mac_version) {
3914 case RTL_GIGA_MAC_VER_01:
3915 case RTL_GIGA_MAC_VER_02:
3916 case RTL_GIGA_MAC_VER_03:
3917 case RTL_GIGA_MAC_VER_04:
3918 case RTL_GIGA_MAC_VER_05:
3919 case RTL_GIGA_MAC_VER_06:
3920 case RTL_GIGA_MAC_VER_10:
3921 case RTL_GIGA_MAC_VER_11:
3922 case RTL_GIGA_MAC_VER_12:
3923 case RTL_GIGA_MAC_VER_13:
3924 case RTL_GIGA_MAC_VER_14:
3925 case RTL_GIGA_MAC_VER_15:
3926 case RTL_GIGA_MAC_VER_16:
3927 case RTL_GIGA_MAC_VER_17:
3928 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3929 break;
3930 case RTL_GIGA_MAC_VER_18:
3931 case RTL_GIGA_MAC_VER_19:
3932 case RTL_GIGA_MAC_VER_20:
3933 case RTL_GIGA_MAC_VER_21:
3934 case RTL_GIGA_MAC_VER_22:
3935 case RTL_GIGA_MAC_VER_23:
3936 case RTL_GIGA_MAC_VER_24:
eb2dc35d 3937 case RTL_GIGA_MAC_VER_34:
e542a226
HW		 3938 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3939 break;
3940 default:
3941 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3942 break;
3943 }
3944}
3945
92fc43b4
HW		 3946static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3947{
3948 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3949}
3950
d58d46b5
FR		 3951static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3952{
9c5028e9 3953 void __iomem *ioaddr = tp->mmio_addr;
3954
3955 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 3956 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 3957 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 3958}
3959
3960static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3961{
9c5028e9 3962 void __iomem *ioaddr = tp->mmio_addr;
3963
3964 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 3965 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 3966 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 3967}
3968
3969static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3970{
3971 void __iomem *ioaddr = tp->mmio_addr;
3972
3973 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3974 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3975 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3976}
3977
3978static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3979{
3980 void __iomem *ioaddr = tp->mmio_addr;
3981
3982 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3983 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3984 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3985}
3986
3987static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3988{
3989 void __iomem *ioaddr = tp->mmio_addr;
3990
3991 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3992}
3993
3994static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3995{
3996 void __iomem *ioaddr = tp->mmio_addr;
3997
3998 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3999}
4000
4001static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4002{
4003 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4004
4005 RTL_W8(MaxTxPacketSize, 0x3f);
4006 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4007 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4008 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4009}
4010
4011static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4012{
4013 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4014
4015 RTL_W8(MaxTxPacketSize, 0x0c);
4016 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4017 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4018 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4019}
4020
4021static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4022{
4023 rtl_tx_performance_tweak(tp->pci_dev,
4024 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4025}
4026
4027static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4028{
4029 rtl_tx_performance_tweak(tp->pci_dev,
4030 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4031}
4032
4033static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4034{
4035 void __iomem *ioaddr = tp->mmio_addr;
4036
4037 r8168b_0_hw_jumbo_enable(tp);
4038
4039 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4040}
4041
4042static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4043{
4044 void __iomem *ioaddr = tp->mmio_addr;
4045
4046 r8168b_0_hw_jumbo_disable(tp);
4047
4048 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4049}
4050
4051static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
4052{
4053 struct jumbo_ops *ops = &tp->jumbo_ops;
4054
4055 switch (tp->mac_version) {
4056 case RTL_GIGA_MAC_VER_11:
4057 ops->disable = r8168b_0_hw_jumbo_disable;
4058 ops->enable = r8168b_0_hw_jumbo_enable;
4059 break;
4060 case RTL_GIGA_MAC_VER_12:
4061 case RTL_GIGA_MAC_VER_17:
4062 ops->disable = r8168b_1_hw_jumbo_disable;
4063 ops->enable = r8168b_1_hw_jumbo_enable;
4064 break;
4065 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4066 case RTL_GIGA_MAC_VER_19:
4067 case RTL_GIGA_MAC_VER_20:
4068 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4069 case RTL_GIGA_MAC_VER_22:
4070 case RTL_GIGA_MAC_VER_23:
4071 case RTL_GIGA_MAC_VER_24:
4072 case RTL_GIGA_MAC_VER_25:
4073 case RTL_GIGA_MAC_VER_26:
4074 ops->disable = r8168c_hw_jumbo_disable;
4075 ops->enable = r8168c_hw_jumbo_enable;
4076 break;
4077 case RTL_GIGA_MAC_VER_27:
4078 case RTL_GIGA_MAC_VER_28:
4079 ops->disable = r8168dp_hw_jumbo_disable;
4080 ops->enable = r8168dp_hw_jumbo_enable;
4081 break;
4082 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4083 case RTL_GIGA_MAC_VER_32:
4084 case RTL_GIGA_MAC_VER_33:
4085 case RTL_GIGA_MAC_VER_34:
4086 ops->disable = r8168e_hw_jumbo_disable;
4087 ops->enable = r8168e_hw_jumbo_enable;
4088 break;
4089
4090 /*
4091 * No action needed for jumbo frames with 8169.
4092 * No jumbo for 810x at all.
4093 */
4094 default:
4095 ops->disable = NULL;
4096 ops->enable = NULL;
4097 break;
4098 }
4099}
4100
6f43adc8
FR		 4101static void rtl_hw_reset(struct rtl8169_private *tp)
4102{
4103 void __iomem *ioaddr = tp->mmio_addr;
4104 int i;
4105
4106 /* Soft reset the chip. */
4107 RTL_W8(ChipCmd, CmdReset);
4108
4109 /* Check that the chip has finished the reset. */
4110 for (i = 0; i < 100; i++) {
4111 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
4112 break;
92fc43b4 4113 udelay(100);
6f43adc8
FR		 4114 }
4115}
4116
b6ffd97f 4117static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4118{
b6ffd97f
FR		 4119 struct rtl_fw *rtl_fw;
4120 const char *name;
4121 int rc = -ENOMEM;
953a12cc 4122
b6ffd97f
FR		 4123 name = rtl_lookup_firmware_name(tp);
4124 if (!name)
4125 goto out_no_firmware;
953a12cc 4126
b6ffd97f
FR		 4127 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4128 if (!rtl_fw)
4129 goto err_warn;
31bd204f 4130
b6ffd97f
FR		 4131 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4132 if (rc < 0)
4133 goto err_free;
4134
fd112f2e
FR		 4135 rc = rtl_check_firmware(tp, rtl_fw);
4136 if (rc < 0)
4137 goto err_release_firmware;
4138
b6ffd97f
FR		 4139 tp->rtl_fw = rtl_fw;
4140out:
4141 return;
4142
fd112f2e
FR		 4143err_release_firmware:
4144 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4145err_free:
4146 kfree(rtl_fw);
4147err_warn:
4148 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4149 name, rc);
4150out_no_firmware:
4151 tp->rtl_fw = NULL;
4152 goto out;
4153}
4154
4155static void rtl_request_firmware(struct rtl8169_private *tp)
4156{
4157 if (IS_ERR(tp->rtl_fw))
4158 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4159}
4160
92fc43b4
HW		 4161static void rtl_rx_close(struct rtl8169_private *tp)
4162{
4163 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4164
1687b566 4165 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4166}
4167
e6de30d6 4168static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4169{
e6de30d6 4170 void __iomem *ioaddr = tp->mmio_addr;
4171
1da177e4 4172 /* Disable interrupts */
811fd301 4173 rtl8169_irq_mask_and_ack(tp);
1da177e4 4174
92fc43b4
HW		 4175 rtl_rx_close(tp);
4176
5d2e1957 4177 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4178 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4179 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 4180 while (RTL_R8(TxPoll) & NPQ)
4181 udelay(20);
c2218925
HW		 4182 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4183 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
7e18dca1 4184 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
b3d7b2f2
HW		 4185 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4186 tp->mac_version == RTL_GIGA_MAC_VER_38) {
c2b0c1e7 4187 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
70090424
HW		 4188 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4189 udelay(100);
92fc43b4
HW		 4190 } else {
4191 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4192 udelay(100);
e6de30d6 4193 }
4194
92fc43b4 4195 rtl_hw_reset(tp);
1da177e4
LT		 4196}
4197
7f796d83 4198static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4199{
4200 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4201
4202 /* Set DMA burst size and Interframe Gap Time */
4203 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4204 (InterFrameGap << TxInterFrameGapShift));
4205}
4206
07ce4064 4207static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4208{
4209 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4210
07ce4064
FR		 4211 tp->hw_start(dev);
4212
da78dbff 4213 rtl_irq_enable_all(tp);
07ce4064
FR		 4214}
4215
7f796d83
FR		 4216static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4217 void __iomem *ioaddr)
4218{
4219 /*
4220 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4221 * register to be written before TxDescAddrLow to work.
4222 * Switching from MMIO to I/O access fixes the issue as well.
4223 */
4224 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4225 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4226 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4227 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4228}
4229
4230static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4231{
4232 u16 cmd;
4233
4234 cmd = RTL_R16(CPlusCmd);
4235 RTL_W16(CPlusCmd, cmd);
4236 return cmd;
4237}
4238
fdd7b4c3 4239static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4240{
4241 /* Low hurts. Let's disable the filtering. */
207d6e87 4242 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4243}
4244
6dccd16b
FR		 4245static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4246{
3744100e 4247 static const struct rtl_cfg2_info {
6dccd16b
FR		 4248 u32 mac_version;
4249 u32 clk;
4250 u32 val;
4251 } cfg2_info [] = {
4252 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4253 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4254 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4255 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4256 };
4257 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4258 unsigned int i;
4259 u32 clk;
4260
4261 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4262 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4263 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4264 RTL_W32(0x7c, p->val);
4265 break;
4266 }
4267 }
4268}
4269
e6b763ea
FR		 4270static void rtl_set_rx_mode(struct net_device *dev)
4271{
4272 struct rtl8169_private *tp = netdev_priv(dev);
4273 void __iomem *ioaddr = tp->mmio_addr;
4274 u32 mc_filter[2]; /* Multicast hash filter */
4275 int rx_mode;
4276 u32 tmp = 0;
4277
4278 if (dev->flags & IFF_PROMISC) {
4279 /* Unconditionally log net taps. */
4280 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4281 rx_mode =
4282 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4283 AcceptAllPhys;
4284 mc_filter[1] = mc_filter[0] = 0xffffffff;
4285 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4286 (dev->flags & IFF_ALLMULTI)) {
4287 /* Too many to filter perfectly -- accept all multicasts. */
4288 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4289 mc_filter[1] = mc_filter[0] = 0xffffffff;
4290 } else {
4291 struct netdev_hw_addr *ha;
4292
4293 rx_mode = AcceptBroadcast | AcceptMyPhys;
4294 mc_filter[1] = mc_filter[0] = 0;
4295 netdev_for_each_mc_addr(ha, dev) {
4296 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4297 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4298 rx_mode |= AcceptMulticast;
4299 }
4300 }
4301
4302 if (dev->features & NETIF_F_RXALL)
4303 rx_mode |= (AcceptErr | AcceptRunt);
4304
4305 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4306
4307 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4308 u32 data = mc_filter[0];
4309
4310 mc_filter[0] = swab32(mc_filter[1]);
4311 mc_filter[1] = swab32(data);
4312 }
4313
4314 RTL_W32(MAR0 + 4, mc_filter[1]);
4315 RTL_W32(MAR0 + 0, mc_filter[0]);
4316
4317 RTL_W32(RxConfig, tmp);
4318}
4319
07ce4064
FR		 4320static void rtl_hw_start_8169(struct net_device *dev)
4321{
4322 struct rtl8169_private *tp = netdev_priv(dev);
4323 void __iomem *ioaddr = tp->mmio_addr;
4324 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4325
9cb427b6
FR		 4326 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4327 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4328 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4329 }
4330
1da177e4 4331 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4332 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4333 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4334 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4335 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4336 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4337
e542a226
HW		 4338 rtl_init_rxcfg(tp);
4339
f0298f81 4340 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4341
6f0333b8 4342 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4343
cecb5fd7
FR		 4344 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4345 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4346 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4347 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4348 rtl_set_rx_tx_config_registers(tp);
1da177e4 4349
7f796d83 4350 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4351
cecb5fd7
FR		 4352 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4353 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4354 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4355 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4356 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4357 }
4358
bcf0bf90
FR		 4359 RTL_W16(CPlusCmd, tp->cp_cmd);
4360
6dccd16b
FR		 4361 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4362
1da177e4
LT		 4363 /*
4364 * Undocumented corner. Supposedly:
4365 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4366 */
4367 RTL_W16(IntrMitigate, 0x0000);
4368
7f796d83 4369 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4370
cecb5fd7
FR		 4371 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4372 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4373 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4374 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4375 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4376 rtl_set_rx_tx_config_registers(tp);
4377 }
4378
1da177e4 4379 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4380
4381 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4382 RTL_R8(IntrMask);
1da177e4
LT		 4383
4384 RTL_W32(RxMissed, 0);
4385
07ce4064 4386 rtl_set_rx_mode(dev);
1da177e4
LT		 4387
4388 /* no early-rx interrupts */
4389 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4390}
1da177e4 4391
beb1fe18
HW		 4392static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4393{
4394 if (tp->csi_ops.write)
4395 tp->csi_ops.write(tp->mmio_addr, addr, value);
4396}
4397
4398static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4399{
4400 if (tp->csi_ops.read)
4401 return tp->csi_ops.read(tp->mmio_addr, addr);
4402 else
4403 return ~0;
4404}
4405
4406static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 4407{
4408 u32 csi;
4409
beb1fe18
HW		 4410 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4411 rtl_csi_write(tp, 0x070c, csi | bits);
4412}
4413
4414static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4415{
4416 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 4417}
4418
beb1fe18 4419static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 4420{
beb1fe18 4421 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 4422}
4423
beb1fe18 4424static void r8169_csi_write(void __iomem *ioaddr, int addr, int value)
650e8d5d 4425{
beb1fe18
HW		 4426 unsigned int i;
4427
4428 RTL_W32(CSIDR, value);
4429 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4430 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4431
4432 for (i = 0; i < 100; i++) {
4433 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
4434 break;
4435 udelay(10);
4436 }
4437}
4438
4439static u32 r8169_csi_read(void __iomem *ioaddr, int addr)
4440{
4441 u32 value = ~0x00;
4442 unsigned int i;
4443
4444 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4445 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4446
4447 for (i = 0; i < 100; i++) {
4448 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
4449 value = RTL_R32(CSIDR);
4450 break;
4451 }
4452 udelay(10);
4453 }
4454
4455 return value;
4456}
4457
7e18dca1
HW		 4458static void r8402_csi_write(void __iomem *ioaddr, int addr, int value)
4459{
4460 unsigned int i;
4461
4462 RTL_W32(CSIDR, value);
4463 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4464 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4465 CSIAR_FUNC_NIC);
4466
4467 for (i = 0; i < 100; i++) {
4468 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
4469 break;
4470 udelay(10);
4471 }
4472}
4473
4474static u32 r8402_csi_read(void __iomem *ioaddr, int addr)
4475{
4476 u32 value = ~0x00;
4477 unsigned int i;
4478
4479 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4480 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4481
4482 for (i = 0; i < 100; i++) {
4483 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
4484 value = RTL_R32(CSIDR);
4485 break;
4486 }
4487 udelay(10);
4488 }
4489
4490 return value;
4491}
4492
beb1fe18
HW		 4493static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp)
4494{
4495 struct csi_ops *ops = &tp->csi_ops;
4496
4497 switch (tp->mac_version) {
4498 case RTL_GIGA_MAC_VER_01:
4499 case RTL_GIGA_MAC_VER_02:
4500 case RTL_GIGA_MAC_VER_03:
4501 case RTL_GIGA_MAC_VER_04:
4502 case RTL_GIGA_MAC_VER_05:
4503 case RTL_GIGA_MAC_VER_06:
4504 case RTL_GIGA_MAC_VER_10:
4505 case RTL_GIGA_MAC_VER_11:
4506 case RTL_GIGA_MAC_VER_12:
4507 case RTL_GIGA_MAC_VER_13:
4508 case RTL_GIGA_MAC_VER_14:
4509 case RTL_GIGA_MAC_VER_15:
4510 case RTL_GIGA_MAC_VER_16:
4511 case RTL_GIGA_MAC_VER_17:
4512 ops->write = NULL;
4513 ops->read = NULL;
4514 break;
4515
7e18dca1 4516 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4517 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 4518 ops->write = r8402_csi_write;
4519 ops->read = r8402_csi_read;
4520 break;
4521
beb1fe18
HW		 4522 default:
4523 ops->write = r8169_csi_write;
4524 ops->read = r8169_csi_read;
4525 break;
4526 }
dacf8154
FR		 4527}
4528
4529struct ephy_info {
4530 unsigned int offset;
4531 u16 mask;
4532 u16 bits;
4533};
4534
350f7596 4535static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 4536{
4537 u16 w;
4538
4539 while (len-- > 0) {
4540 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4541 rtl_ephy_write(ioaddr, e->offset, w);
4542 e++;
4543 }
4544}
4545
b726e493
FR		 4546static void rtl_disable_clock_request(struct pci_dev *pdev)
4547{
e44daade 4548 int cap = pci_pcie_cap(pdev);
b726e493
FR		 4549
4550 if (cap) {
4551 u16 ctl;
4552
4553 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4554 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4555 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4556 }
4557}
4558
e6de30d6 4559static void rtl_enable_clock_request(struct pci_dev *pdev)
4560{
e44daade 4561 int cap = pci_pcie_cap(pdev);
e6de30d6 4562
4563 if (cap) {
4564 u16 ctl;
4565
4566 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4567 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4568 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4569 }
4570}
4571
b726e493
FR		 4572#define R8168_CPCMD_QUIRK_MASK (\
4573 EnableBist | \
4574 Mac_dbgo_oe | \
4575 Force_half_dup | \
4576 Force_rxflow_en | \
4577 Force_txflow_en | \
4578 Cxpl_dbg_sel | \
4579 ASF | \
4580 PktCntrDisable | \
4581 Mac_dbgo_sel)
4582
beb1fe18 4583static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4584{
beb1fe18
HW		 4585 void __iomem *ioaddr = tp->mmio_addr;
4586 struct pci_dev *pdev = tp->pci_dev;
4587
b726e493
FR		 4588 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4589
4590 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4591
2e68ae44
FR		 4592 rtl_tx_performance_tweak(pdev,
4593 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4594}
4595
beb1fe18 4596static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4597{
beb1fe18
HW		 4598 void __iomem *ioaddr = tp->mmio_addr;
4599
4600 rtl_hw_start_8168bb(tp);
b726e493 4601
f0298f81 4602 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4603
4604 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4605}
4606
beb1fe18 4607static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4608{
beb1fe18
HW		 4609 void __iomem *ioaddr = tp->mmio_addr;
4610 struct pci_dev *pdev = tp->pci_dev;
4611
b726e493
FR		 4612 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4613
4614 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4615
219a1e9d 4616 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4617
4618 rtl_disable_clock_request(pdev);
4619
4620 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4621}
4622
beb1fe18 4623static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4624{
beb1fe18 4625 void __iomem *ioaddr = tp->mmio_addr;
350f7596 4626 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4627 { 0x01, 0, 0x0001 },
4628 { 0x02, 0x0800, 0x1000 },
4629 { 0x03, 0, 0x0042 },
4630 { 0x06, 0x0080, 0x0000 },
4631 { 0x07, 0, 0x2000 }
4632 };
4633
beb1fe18 4634 rtl_csi_access_enable_2(tp);
b726e493
FR		 4635
4636 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4637
beb1fe18 4638 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4639}
4640
beb1fe18 4641static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4642{
beb1fe18
HW		 4643 void __iomem *ioaddr = tp->mmio_addr;
4644 struct pci_dev *pdev = tp->pci_dev;
4645
4646 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 4647
4648 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4649
4650 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4651
4652 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4653}
4654
beb1fe18 4655static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4656{
beb1fe18
HW		 4657 void __iomem *ioaddr = tp->mmio_addr;
4658 struct pci_dev *pdev = tp->pci_dev;
4659
4660 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 4661
4662 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4663
4664 /* Magic. */
4665 RTL_W8(DBG_REG, 0x20);
4666
f0298f81 4667 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4668
4669 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4670
4671 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4672}
4673
beb1fe18 4674static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4675{
beb1fe18 4676 void __iomem *ioaddr = tp->mmio_addr;
350f7596 4677 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4678 { 0x02, 0x0800, 0x1000 },
4679 { 0x03, 0, 0x0002 },
4680 { 0x06, 0x0080, 0x0000 }
4681 };
4682
beb1fe18 4683 rtl_csi_access_enable_2(tp);
b726e493
FR		 4684
4685 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4686
4687 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4688
beb1fe18 4689 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4690}
4691
beb1fe18 4692static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4693{
beb1fe18 4694 void __iomem *ioaddr = tp->mmio_addr;
350f7596 4695 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4696 { 0x01, 0, 0x0001 },
4697 { 0x03, 0x0400, 0x0220 }
4698 };
4699
beb1fe18 4700 rtl_csi_access_enable_2(tp);
b726e493
FR		 4701
4702 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4703
beb1fe18 4704 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4705}
4706
beb1fe18 4707static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4708{
beb1fe18 4709 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4710}
4711
beb1fe18 4712static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4713{
beb1fe18 4714 rtl_csi_access_enable_2(tp);
6fb07058 4715
beb1fe18 4716 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4717}
4718
beb1fe18 4719static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4720{
beb1fe18
HW		 4721 void __iomem *ioaddr = tp->mmio_addr;
4722 struct pci_dev *pdev = tp->pci_dev;
4723
4724 rtl_csi_access_enable_2(tp);
5b538df9
FR		 4725
4726 rtl_disable_clock_request(pdev);
4727
f0298f81 4728 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4729
4730 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4731
4732 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4733}
4734
beb1fe18 4735static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4736{
beb1fe18
HW		 4737 void __iomem *ioaddr = tp->mmio_addr;
4738 struct pci_dev *pdev = tp->pci_dev;
4739
4740 rtl_csi_access_enable_1(tp);
4804b3b3 4741
4742 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4743
4744 RTL_W8(MaxTxPacketSize, TxPacketMax);
4745
4746 rtl_disable_clock_request(pdev);
4747}
4748
beb1fe18 4749static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4750{
beb1fe18
HW		 4751 void __iomem *ioaddr = tp->mmio_addr;
4752 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 4753 static const struct ephy_info e_info_8168d_4[] = {
4754 { 0x0b, ~0, 0x48 },
4755 { 0x19, 0x20, 0x50 },
4756 { 0x0c, ~0, 0x20 }
4757 };
4758 int i;
4759
beb1fe18 4760 rtl_csi_access_enable_1(tp);
e6de30d6 4761
4762 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4763
4764 RTL_W8(MaxTxPacketSize, TxPacketMax);
4765
4766 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4767 const struct ephy_info *e = e_info_8168d_4 + i;
4768 u16 w;
4769
4770 w = rtl_ephy_read(ioaddr, e->offset);
4771 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4772 }
4773
4774 rtl_enable_clock_request(pdev);
4775}
4776
beb1fe18 4777static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4778{
beb1fe18
HW		 4779 void __iomem *ioaddr = tp->mmio_addr;
4780 struct pci_dev *pdev = tp->pci_dev;
70090424 4781 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4782 { 0x00, 0x0200, 0x0100 },
4783 { 0x00, 0x0000, 0x0004 },
4784 { 0x06, 0x0002, 0x0001 },
4785 { 0x06, 0x0000, 0x0030 },
4786 { 0x07, 0x0000, 0x2000 },
4787 { 0x00, 0x0000, 0x0020 },
4788 { 0x03, 0x5800, 0x2000 },
4789 { 0x03, 0x0000, 0x0001 },
4790 { 0x01, 0x0800, 0x1000 },
4791 { 0x07, 0x0000, 0x4000 },
4792 { 0x1e, 0x0000, 0x2000 },
4793 { 0x19, 0xffff, 0xfe6c },
4794 { 0x0a, 0x0000, 0x0040 }
4795 };
4796
beb1fe18 4797 rtl_csi_access_enable_2(tp);
01dc7fec 4798
70090424 4799 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4800
4801 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4802
4803 RTL_W8(MaxTxPacketSize, TxPacketMax);
4804
4805 rtl_disable_clock_request(pdev);
4806
4807 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4808 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4809 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4810
cecb5fd7 4811 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4812}
4813
beb1fe18 4814static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 4815{
beb1fe18
HW		 4816 void __iomem *ioaddr = tp->mmio_addr;
4817 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 4818 static const struct ephy_info e_info_8168e_2[] = {
4819 { 0x09, 0x0000, 0x0080 },
4820 { 0x19, 0x0000, 0x0224 }
4821 };
4822
beb1fe18 4823 rtl_csi_access_enable_1(tp);
70090424
HW		 4824
4825 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4826
4827 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4828
4829 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4830 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4831 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4832 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4833 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4834 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4835 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4836 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4837 ERIAR_EXGMAC);
4838
3090bd9a 4839 RTL_W8(MaxTxPacketSize, EarlySize);
70090424
HW		 4840
4841 rtl_disable_clock_request(pdev);
4842
4843 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4844 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4845
4846 /* Adjust EEE LED frequency */
4847 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4848
4849 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4850 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4851 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4852}
4853
5f886e08 4854static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 4855{
beb1fe18
HW		 4856 void __iomem *ioaddr = tp->mmio_addr;
4857 struct pci_dev *pdev = tp->pci_dev;
c2218925 4858
5f886e08 4859 rtl_csi_access_enable_2(tp);
c2218925
HW		 4860
4861 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4862
4863 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4864 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4865 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4866 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4867 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4868 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4869 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4870 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4871 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4872 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 4873
4874 RTL_W8(MaxTxPacketSize, EarlySize);
4875
4876 rtl_disable_clock_request(pdev);
4877
4878 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4879 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925
HW		 4880 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4881 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4882 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4883}
4884
5f886e08
HW		 4885static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4886{
4887 void __iomem *ioaddr = tp->mmio_addr;
4888 static const struct ephy_info e_info_8168f_1[] = {
4889 { 0x06, 0x00c0, 0x0020 },
4890 { 0x08, 0x0001, 0x0002 },
4891 { 0x09, 0x0000, 0x0080 },
4892 { 0x19, 0x0000, 0x0224 }
4893 };
4894
4895 rtl_hw_start_8168f(tp);
4896
4897 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4898
4899 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4900 ERIAR_EXGMAC);
4901
4902 /* Adjust EEE LED frequency */
4903 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4904}
4905
b3d7b2f2
HW		 4906static void rtl_hw_start_8411(struct rtl8169_private *tp)
4907{
4908 void __iomem *ioaddr = tp->mmio_addr;
4909 static const struct ephy_info e_info_8168f_1[] = {
4910 { 0x06, 0x00c0, 0x0020 },
4911 { 0x0f, 0xffff, 0x5200 },
4912 { 0x1e, 0x0000, 0x4000 },
4913 { 0x19, 0x0000, 0x0224 }
4914 };
4915
4916 rtl_hw_start_8168f(tp);
4917
4918 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4919
4920 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000,
4921 ERIAR_EXGMAC);
4922}
4923
07ce4064
FR		 4924static void rtl_hw_start_8168(struct net_device *dev)
4925{
2dd99530
FR		 4926 struct rtl8169_private *tp = netdev_priv(dev);
4927 void __iomem *ioaddr = tp->mmio_addr;
4928
4929 RTL_W8(Cfg9346, Cfg9346_Unlock);
4930
f0298f81 4931 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4932
6f0333b8 4933 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4934
0e485150 4935 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4936
4937 RTL_W16(CPlusCmd, tp->cp_cmd);
4938
0e485150 4939 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4940
0e485150 4941 /* Work around for RxFIFO overflow. */
811fd301 4942 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 4943 tp->event_slow |= RxFIFOOver | PCSTimeout;
4944 tp->event_slow &= ~RxOverflow;
0e485150
FR		 4945 }
4946
4947 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4948
b8363901
FR		 4949 rtl_set_rx_mode(dev);
4950
4951 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4952 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4953
4954 RTL_R8(IntrMask);
4955
219a1e9d
FR		 4956 switch (tp->mac_version) {
4957 case RTL_GIGA_MAC_VER_11:
beb1fe18 4958 rtl_hw_start_8168bb(tp);
4804b3b3 4959 break;
219a1e9d
FR		 4960
4961 case RTL_GIGA_MAC_VER_12:
4962 case RTL_GIGA_MAC_VER_17:
beb1fe18 4963 rtl_hw_start_8168bef(tp);
4804b3b3 4964 break;
219a1e9d
FR		 4965
4966 case RTL_GIGA_MAC_VER_18:
beb1fe18 4967 rtl_hw_start_8168cp_1(tp);
4804b3b3 4968 break;
219a1e9d
FR		 4969
4970 case RTL_GIGA_MAC_VER_19:
beb1fe18 4971 rtl_hw_start_8168c_1(tp);
4804b3b3 4972 break;
219a1e9d
FR		 4973
4974 case RTL_GIGA_MAC_VER_20:
beb1fe18 4975 rtl_hw_start_8168c_2(tp);
4804b3b3 4976 break;
219a1e9d 4977
197ff761 4978 case RTL_GIGA_MAC_VER_21:
beb1fe18 4979 rtl_hw_start_8168c_3(tp);
4804b3b3 4980 break;
197ff761 4981
6fb07058 4982 case RTL_GIGA_MAC_VER_22:
beb1fe18 4983 rtl_hw_start_8168c_4(tp);
4804b3b3 4984 break;
6fb07058 4985
ef3386f0 4986 case RTL_GIGA_MAC_VER_23:
beb1fe18 4987 rtl_hw_start_8168cp_2(tp);
4804b3b3 4988 break;
ef3386f0 4989
7f3e3d3a 4990 case RTL_GIGA_MAC_VER_24:
beb1fe18 4991 rtl_hw_start_8168cp_3(tp);
4804b3b3 4992 break;
7f3e3d3a 4993
5b538df9 4994 case RTL_GIGA_MAC_VER_25:
daf9df6d 4995 case RTL_GIGA_MAC_VER_26:
4996 case RTL_GIGA_MAC_VER_27:
beb1fe18 4997 rtl_hw_start_8168d(tp);
4804b3b3 4998 break;
5b538df9 4999
e6de30d6 5000 case RTL_GIGA_MAC_VER_28:
beb1fe18 5001 rtl_hw_start_8168d_4(tp);
4804b3b3 5002 break;
cecb5fd7 5003
4804b3b3 5004 case RTL_GIGA_MAC_VER_31:
beb1fe18 5005 rtl_hw_start_8168dp(tp);
4804b3b3 5006 break;
5007
01dc7fec 5008 case RTL_GIGA_MAC_VER_32:
5009 case RTL_GIGA_MAC_VER_33:
beb1fe18 5010 rtl_hw_start_8168e_1(tp);
70090424
HW		 5011 break;
5012 case RTL_GIGA_MAC_VER_34:
beb1fe18 5013 rtl_hw_start_8168e_2(tp);
01dc7fec 5014 break;
e6de30d6 5015
c2218925
HW		 5016 case RTL_GIGA_MAC_VER_35:
5017 case RTL_GIGA_MAC_VER_36:
beb1fe18 5018 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5019 break;
5020
b3d7b2f2
HW		 5021 case RTL_GIGA_MAC_VER_38:
5022 rtl_hw_start_8411(tp);
5023 break;
5024
219a1e9d
FR		 5025 default:
5026 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5027 dev->name, tp->mac_version);
4804b3b3 5028 break;
219a1e9d 5029 }
2dd99530 5030
0e485150
FR		 5031 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5032
b8363901
FR		 5033 RTL_W8(Cfg9346, Cfg9346_Lock);
5034
2dd99530 5035 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5036}
1da177e4 5037
2857ffb7
FR		 5038#define R810X_CPCMD_QUIRK_MASK (\
5039 EnableBist | \
5040 Mac_dbgo_oe | \
5041 Force_half_dup | \
5edcc537 5042 Force_rxflow_en | \
2857ffb7
FR		 5043 Force_txflow_en | \
5044 Cxpl_dbg_sel | \
5045 ASF | \
5046 PktCntrDisable | \
d24e9aaf 5047 Mac_dbgo_sel)
2857ffb7 5048
beb1fe18 5049static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5050{
beb1fe18
HW		 5051 void __iomem *ioaddr = tp->mmio_addr;
5052 struct pci_dev *pdev = tp->pci_dev;
350f7596 5053 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5054 { 0x01, 0, 0x6e65 },
5055 { 0x02, 0, 0x091f },
5056 { 0x03, 0, 0xc2f9 },
5057 { 0x06, 0, 0xafb5 },
5058 { 0x07, 0, 0x0e00 },
5059 { 0x19, 0, 0xec80 },
5060 { 0x01, 0, 0x2e65 },
5061 { 0x01, 0, 0x6e65 }
5062 };
5063 u8 cfg1;
5064
beb1fe18 5065 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5066
5067 RTL_W8(DBG_REG, FIX_NAK_1);
5068
5069 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5070
5071 RTL_W8(Config1,
5072 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5073 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5074
5075 cfg1 = RTL_R8(Config1);
5076 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5077 RTL_W8(Config1, cfg1 & ~LEDS0);
5078
2857ffb7
FR		 5079 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5080}
5081
beb1fe18 5082static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5083{
beb1fe18
HW		 5084 void __iomem *ioaddr = tp->mmio_addr;
5085 struct pci_dev *pdev = tp->pci_dev;
5086
5087 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5088
5089 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5090
5091 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5092 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5093}
5094
beb1fe18 5095static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5096{
beb1fe18 5097 rtl_hw_start_8102e_2(tp);
2857ffb7 5098
beb1fe18 5099 rtl_ephy_write(tp->mmio_addr, 0x03, 0xc2f9);
2857ffb7
FR		 5100}
5101
beb1fe18 5102static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 5103{
beb1fe18 5104 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 5105 static const struct ephy_info e_info_8105e_1[] = {
5106 { 0x07, 0, 0x4000 },
5107 { 0x19, 0, 0x0200 },
5108 { 0x19, 0, 0x0020 },
5109 { 0x1e, 0, 0x2000 },
5110 { 0x03, 0, 0x0001 },
5111 { 0x19, 0, 0x0100 },
5112 { 0x19, 0, 0x0004 },
5113 { 0x0a, 0, 0x0020 }
5114 };
5115
cecb5fd7 5116 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5117 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5118
cecb5fd7 5119 /* Disable Early Tally Counter */
5a5e4443
HW		 5120 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5121
5122 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5123 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443
HW		 5124
5125 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5126}
5127
beb1fe18 5128static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5129{
beb1fe18
HW		 5130 void __iomem *ioaddr = tp->mmio_addr;
5131
5132 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5133 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
5134}
5135
7e18dca1
HW		 5136static void rtl_hw_start_8402(struct rtl8169_private *tp)
5137{
5138 void __iomem *ioaddr = tp->mmio_addr;
5139 static const struct ephy_info e_info_8402[] = {
5140 { 0x19, 0xffff, 0xff64 },
5141 { 0x1e, 0, 0x4000 }
5142 };
5143
5144 rtl_csi_access_enable_2(tp);
5145
5146 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5147 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5148
5149 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5150 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5151
5152 rtl_ephy_init(ioaddr, e_info_8402, ARRAY_SIZE(e_info_8402));
5153
5154 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5155
5156 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5157 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5158 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5159 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5160 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5161 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5162 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00,
5163 ERIAR_EXGMAC);
5164}
5165
5598bfe5
HW		 5166static void rtl_hw_start_8106(struct rtl8169_private *tp)
5167{
5168 void __iomem *ioaddr = tp->mmio_addr;
5169
5170 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5171 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5172
5173 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5174 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5175 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5176}
5177
07ce4064
FR		 5178static void rtl_hw_start_8101(struct net_device *dev)
5179{
cdf1a608
FR		 5180 struct rtl8169_private *tp = netdev_priv(dev);
5181 void __iomem *ioaddr = tp->mmio_addr;
5182 struct pci_dev *pdev = tp->pci_dev;
5183
da78dbff
FR		 5184 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5185 tp->event_slow &= ~RxFIFOOver;
811fd301 5186
cecb5fd7
FR		 5187 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5188 tp->mac_version == RTL_GIGA_MAC_VER_16) {
e44daade 5189 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 5190
5191 if (cap) {
5192 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5193 PCI_EXP_DEVCTL_NOSNOOP_EN);
5194 }
cdf1a608
FR		 5195 }
5196
d24e9aaf
HW		 5197 RTL_W8(Cfg9346, Cfg9346_Unlock);
5198
2857ffb7
FR		 5199 switch (tp->mac_version) {
5200 case RTL_GIGA_MAC_VER_07:
beb1fe18 5201 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5202 break;
5203
5204 case RTL_GIGA_MAC_VER_08:
beb1fe18 5205 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5206 break;
5207
5208 case RTL_GIGA_MAC_VER_09:
beb1fe18 5209 rtl_hw_start_8102e_2(tp);
2857ffb7 5210 break;
5a5e4443
HW		 5211
5212 case RTL_GIGA_MAC_VER_29:
beb1fe18 5213 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5214 break;
5215 case RTL_GIGA_MAC_VER_30:
beb1fe18 5216 rtl_hw_start_8105e_2(tp);
5a5e4443 5217 break;
7e18dca1
HW		 5218
5219 case RTL_GIGA_MAC_VER_37:
5220 rtl_hw_start_8402(tp);
5221 break;
5598bfe5
HW		 5222
5223 case RTL_GIGA_MAC_VER_39:
5224 rtl_hw_start_8106(tp);
5225 break;
cdf1a608
FR		 5226 }
5227
d24e9aaf 5228 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5229
f0298f81 5230 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 5231
6f0333b8 5232 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 5233
d24e9aaf 5234 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 5235 RTL_W16(CPlusCmd, tp->cp_cmd);
5236
5237 RTL_W16(IntrMitigate, 0x0000);
5238
5239 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5240
5241 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5242 rtl_set_rx_tx_config_registers(tp);
5243
cdf1a608
FR		 5244 RTL_R8(IntrMask);
5245
cdf1a608
FR		 5246 rtl_set_rx_mode(dev);
5247
5248 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5249}
5250
5251static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5252{
d58d46b5
FR		 5253 struct rtl8169_private *tp = netdev_priv(dev);
5254
5255 if (new_mtu < ETH_ZLEN ||
5256 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5257 return -EINVAL;
5258
d58d46b5
FR		 5259 if (new_mtu > ETH_DATA_LEN)
5260 rtl_hw_jumbo_enable(tp);
5261 else
5262 rtl_hw_jumbo_disable(tp);
5263
1da177e4 5264 dev->mtu = new_mtu;
350fb32a
MM		 5265 netdev_update_features(dev);
5266
323bb685 5267 return 0;
1da177e4
LT		 5268}
5269
5270static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5271{
95e0918d 5272 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5273 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5274}
5275
6f0333b8
ED		 5276static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5277 void **data_buff, struct RxDesc *desc)
1da177e4 5278{
48addcc9 5279 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5280 DMA_FROM_DEVICE);
48addcc9 5281
6f0333b8
ED		 5282 kfree(*data_buff);
5283 *data_buff = NULL;
1da177e4
LT		 5284 rtl8169_make_unusable_by_asic(desc);
5285}
5286
5287static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5288{
5289 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5290
5291 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5292}
5293
5294static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5295 u32 rx_buf_sz)
5296{
5297 desc->addr = cpu_to_le64(mapping);
5298 wmb();
5299 rtl8169_mark_to_asic(desc, rx_buf_sz);
5300}
5301
6f0333b8
ED		 5302static inline void *rtl8169_align(void *data)
5303{
5304 return (void *)ALIGN((long)data, 16);
5305}
5306
0ecbe1ca
SG		 5307static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5308 struct RxDesc *desc)
1da177e4 5309{
6f0333b8 5310 void *data;
1da177e4 5311 dma_addr_t mapping;
48addcc9 5312 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5313 struct net_device *dev = tp->dev;
6f0333b8 5314 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5315
6f0333b8
ED		 5316 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5317 if (!data)
5318 return NULL;
e9f63f30 5319
6f0333b8
ED		 5320 if (rtl8169_align(data) != data) {
5321 kfree(data);
5322 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5323 if (!data)
5324 return NULL;
5325 }
3eafe507 5326
48addcc9 5327 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5328 DMA_FROM_DEVICE);
d827d86b
SG		 5329 if (unlikely(dma_mapping_error(d, mapping))) {
5330 if (net_ratelimit())
5331 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5332 goto err_out;
d827d86b 5333 }
1da177e4
LT		 5334
5335 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5336 return data;
3eafe507
SG		 5337
5338err_out:
5339 kfree(data);
5340 return NULL;
1da177e4
LT		 5341}
5342
5343static void rtl8169_rx_clear(struct rtl8169_private *tp)
5344{
07d3f51f 5345 unsigned int i;
1da177e4
LT		 5346
5347 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5348 if (tp->Rx_databuff[i]) {
5349 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5350 tp->RxDescArray + i);
5351 }
5352 }
5353}
5354
0ecbe1ca 5355static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5356{
0ecbe1ca
SG		 5357 desc->opts1 |= cpu_to_le32(RingEnd);
5358}
5b0384f4 5359
0ecbe1ca
SG		 5360static int rtl8169_rx_fill(struct rtl8169_private *tp)
5361{
5362 unsigned int i;
1da177e4 5363
0ecbe1ca
SG		 5364 for (i = 0; i < NUM_RX_DESC; i++) {
5365 void *data;
4ae47c2d 5366
6f0333b8 5367 if (tp->Rx_databuff[i])
1da177e4 5368 continue;
bcf0bf90 5369
0ecbe1ca 5370 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5371 if (!data) {
5372 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5373 goto err_out;
6f0333b8
ED		 5374 }
5375 tp->Rx_databuff[i] = data;
1da177e4 5376 }
1da177e4 5377
0ecbe1ca
SG		 5378 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5379 return 0;
5380
5381err_out:
5382 rtl8169_rx_clear(tp);
5383 return -ENOMEM;
1da177e4
LT		 5384}
5385
1da177e4
LT		 5386static int rtl8169_init_ring(struct net_device *dev)
5387{
5388 struct rtl8169_private *tp = netdev_priv(dev);
5389
5390 rtl8169_init_ring_indexes(tp);
5391
5392 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5393 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5394
0ecbe1ca 5395 return rtl8169_rx_fill(tp);
1da177e4
LT		 5396}
5397
48addcc9 5398static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5399 struct TxDesc *desc)
5400{
5401 unsigned int len = tx_skb->len;
5402
48addcc9
SG		 5403 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5404
1da177e4
LT		 5405 desc->opts1 = 0x00;
5406 desc->opts2 = 0x00;
5407 desc->addr = 0x00;
5408 tx_skb->len = 0;
5409}
5410
3eafe507
SG		 5411static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5412 unsigned int n)
1da177e4
LT		 5413{
5414 unsigned int i;
5415
3eafe507
SG		 5416 for (i = 0; i < n; i++) {
5417 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5418 struct ring_info *tx_skb = tp->tx_skb + entry;
5419 unsigned int len = tx_skb->len;
5420
5421 if (len) {
5422 struct sk_buff *skb = tx_skb->skb;
5423
48addcc9 5424 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5425 tp->TxDescArray + entry);
5426 if (skb) {
cac4b22f 5427 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5428 dev_kfree_skb(skb);
5429 tx_skb->skb = NULL;
5430 }
1da177e4
LT		 5431 }
5432 }
3eafe507
SG		 5433}
5434
5435static void rtl8169_tx_clear(struct rtl8169_private *tp)
5436{
5437 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4 5438 tp->cur_tx = tp->dirty_tx = 0;
036dafa2 5439 netdev_reset_queue(tp->dev);
1da177e4
LT		 5440}
5441
4422bcd4 5442static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5443{
c4028958 5444 struct net_device *dev = tp->dev;
56de414c 5445 int i;
1da177e4 5446
da78dbff
FR		 5447 napi_disable(&tp->napi);
5448 netif_stop_queue(dev);
5449 synchronize_sched();
1da177e4 5450
c7c2c39b 5451 rtl8169_hw_reset(tp);
5452
56de414c
FR		 5453 for (i = 0; i < NUM_RX_DESC; i++)
5454 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5455
1da177e4 5456 rtl8169_tx_clear(tp);
c7c2c39b 5457 rtl8169_init_ring_indexes(tp);
1da177e4 5458
da78dbff 5459 napi_enable(&tp->napi);
56de414c
FR		 5460 rtl_hw_start(dev);
5461 netif_wake_queue(dev);
5462 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5463}
5464
5465static void rtl8169_tx_timeout(struct net_device *dev)
5466{
da78dbff
FR		 5467 struct rtl8169_private *tp = netdev_priv(dev);
5468
5469 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5470}
5471
5472static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5473 u32 *opts)
1da177e4
LT		 5474{
5475 struct skb_shared_info *info = skb_shinfo(skb);
5476 unsigned int cur_frag, entry;
a6343afb 5477 struct TxDesc * uninitialized_var(txd);
48addcc9 5478 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5479
5480 entry = tp->cur_tx;
5481 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5482 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5483 dma_addr_t mapping;
5484 u32 status, len;
5485 void *addr;
5486
5487 entry = (entry + 1) % NUM_TX_DESC;
5488
5489 txd = tp->TxDescArray + entry;
9e903e08 5490 len = skb_frag_size(frag);
929f6189 5491 addr = skb_frag_address(frag);
48addcc9 5492 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5493 if (unlikely(dma_mapping_error(d, mapping))) {
5494 if (net_ratelimit())
5495 netif_err(tp, drv, tp->dev,
5496 "Failed to map TX fragments DMA!\n");
3eafe507 5497 goto err_out;
d827d86b 5498 }
1da177e4 5499
cecb5fd7 5500 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5501 status = opts[0] | len |
5502 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5503
5504 txd->opts1 = cpu_to_le32(status);
2b7b4318 5505 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5506 txd->addr = cpu_to_le64(mapping);
5507
5508 tp->tx_skb[entry].len = len;
5509 }
5510
5511 if (cur_frag) {
5512 tp->tx_skb[entry].skb = skb;
5513 txd->opts1 |= cpu_to_le32(LastFrag);
5514 }
5515
5516 return cur_frag;
3eafe507
SG		 5517
5518err_out:
5519 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5520 return -EIO;
1da177e4
LT		 5521}
5522
2b7b4318
FR		 5523static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5524 struct sk_buff *skb, u32 *opts)
1da177e4 5525{
2b7b4318 5526 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5527 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5528 int offset = info->opts_offset;
350fb32a 5529
2b7b4318
FR		 5530 if (mss) {
5531 opts[0] |= TD_LSO;
5532 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5533 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5534 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5535
5536 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5537 opts[offset] |= info->checksum.tcp;
1da177e4 5538 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5539 opts[offset] |= info->checksum.udp;
5540 else
5541 WARN_ON_ONCE(1);
1da177e4 5542 }
1da177e4
LT		 5543}
5544
61357325
SH		 5545static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5546 struct net_device *dev)
1da177e4
LT		 5547{
5548 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5549 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5550 struct TxDesc *txd = tp->TxDescArray + entry;
5551 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5552 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5553 dma_addr_t mapping;
5554 u32 status, len;
2b7b4318 5555 u32 opts[2];
3eafe507 5556 int frags;
5b0384f4 5557
477206a0 5558 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 5559 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5560 goto err_stop_0;
1da177e4
LT		 5561 }
5562
5563 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5564 goto err_stop_0;
5565
5566 len = skb_headlen(skb);
48addcc9 5567 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5568 if (unlikely(dma_mapping_error(d, mapping))) {
5569 if (net_ratelimit())
5570 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5571 goto err_dma_0;
d827d86b 5572 }
3eafe507
SG		 5573
5574 tp->tx_skb[entry].len = len;
5575 txd->addr = cpu_to_le64(mapping);
1da177e4 5576
2b7b4318
FR		 5577 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5578 opts[0] = DescOwn;
1da177e4 5579
2b7b4318
FR		 5580 rtl8169_tso_csum(tp, skb, opts);
5581
5582 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5583 if (frags < 0)
5584 goto err_dma_1;
5585 else if (frags)
2b7b4318 5586 opts[0] |= FirstFrag;
3eafe507 5587 else {
2b7b4318 5588 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5589 tp->tx_skb[entry].skb = skb;
5590 }
5591
2b7b4318
FR		 5592 txd->opts2 = cpu_to_le32(opts[1]);
5593
036dafa2
IM		 5594 netdev_sent_queue(dev, skb->len);
5595
5047fb5d
RC		 5596 skb_tx_timestamp(skb);
5597
1da177e4
LT		 5598 wmb();
5599
cecb5fd7 5600 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5601 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5602 txd->opts1 = cpu_to_le32(status);
5603
1da177e4
LT		 5604 tp->cur_tx += frags + 1;
5605
4c020a96 5606 wmb();
1da177e4 5607
cecb5fd7 5608 RTL_W8(TxPoll, NPQ);
1da177e4 5609
da78dbff
FR		 5610 mmiowb();
5611
477206a0 5612 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 5613 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5614 * not miss a ring update when it notices a stopped queue.
5615 */
5616 smp_wmb();
1da177e4 5617 netif_stop_queue(dev);
ae1f23fb
FR		 5618 /* Sync with rtl_tx:
5619 * - publish queue status and cur_tx ring index (write barrier)
5620 * - refresh dirty_tx ring index (read barrier).
5621 * May the current thread have a pessimistic view of the ring
5622 * status and forget to wake up queue, a racing rtl_tx thread
5623 * can't.
5624 */
1e874e04 5625 smp_mb();
477206a0 5626 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 5627 netif_wake_queue(dev);
5628 }
5629
61357325 5630 return NETDEV_TX_OK;
1da177e4 5631
3eafe507 5632err_dma_1:
48addcc9 5633 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5634err_dma_0:
5635 dev_kfree_skb(skb);
5636 dev->stats.tx_dropped++;
5637 return NETDEV_TX_OK;
5638
5639err_stop_0:
1da177e4 5640 netif_stop_queue(dev);
cebf8cc7 5641 dev->stats.tx_dropped++;
61357325 5642 return NETDEV_TX_BUSY;
1da177e4
LT		 5643}
5644
5645static void rtl8169_pcierr_interrupt(struct net_device *dev)
5646{
5647 struct rtl8169_private *tp = netdev_priv(dev);
5648 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5649 u16 pci_status, pci_cmd;
5650
5651 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5652 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5653
bf82c189
JP		 5654 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5655 pci_cmd, pci_status);
1da177e4
LT		 5656
5657 /*
5658 * The recovery sequence below admits a very elaborated explanation:
5659 * - it seems to work;
d03902b8
FR		 5660 * - I did not see what else could be done;
5661 * - it makes iop3xx happy.
1da177e4
LT		 5662 *
5663 * Feel free to adjust to your needs.
5664 */
a27993f3 5665 if (pdev->broken_parity_status)
d03902b8
FR		 5666 pci_cmd &= ~PCI_COMMAND_PARITY;
5667 else
5668 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5669
5670 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5671
5672 pci_write_config_word(pdev, PCI_STATUS,
5673 pci_status & (PCI_STATUS_DETECTED_PARITY |
5674 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5675 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5676
5677 /* The infamous DAC f*ckup only happens at boot time */
5678 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5679 void __iomem *ioaddr = tp->mmio_addr;
5680
bf82c189 5681 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5682 tp->cp_cmd &= ~PCIDAC;
5683 RTL_W16(CPlusCmd, tp->cp_cmd);
5684 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5685 }
5686
e6de30d6 5687 rtl8169_hw_reset(tp);
d03902b8 5688
98ddf986 5689 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5690}
5691
036dafa2
IM		 5692struct rtl_txc {
5693 int packets;
5694 int bytes;
5695};
5696
da78dbff 5697static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4 5698{
036dafa2 5699 struct rtl8169_stats *tx_stats = &tp->tx_stats;
1da177e4 5700 unsigned int dirty_tx, tx_left;
036dafa2 5701 struct rtl_txc txc = { 0, 0 };
1da177e4 5702
1da177e4
LT		 5703 dirty_tx = tp->dirty_tx;
5704 smp_rmb();
5705 tx_left = tp->cur_tx - dirty_tx;
5706
5707 while (tx_left > 0) {
5708 unsigned int entry = dirty_tx % NUM_TX_DESC;
5709 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5710 u32 status;
5711
5712 rmb();
5713 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5714 if (status & DescOwn)
5715 break;
5716
48addcc9
SG		 5717 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5718 tp->TxDescArray + entry);
1da177e4 5719 if (status & LastFrag) {
036dafa2
IM		 5720 struct sk_buff *skb = tx_skb->skb;
5721
5722 txc.packets++;
5723 txc.bytes += skb->len;
5724 dev_kfree_skb(skb);
1da177e4
LT		 5725 tx_skb->skb = NULL;
5726 }
5727 dirty_tx++;
5728 tx_left--;
5729 }
5730
036dafa2
IM		 5731 u64_stats_update_begin(&tx_stats->syncp);
5732 tx_stats->packets += txc.packets;
5733 tx_stats->bytes += txc.bytes;
5734 u64_stats_update_end(&tx_stats->syncp);
5735
5736 netdev_completed_queue(dev, txc.packets, txc.bytes);
5737
1da177e4
LT		 5738 if (tp->dirty_tx != dirty_tx) {
5739 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 5740 /* Sync with rtl8169_start_xmit:
5741 * - publish dirty_tx ring index (write barrier)
5742 * - refresh cur_tx ring index and queue status (read barrier)
5743 * May the current thread miss the stopped queue condition,
5744 * a racing xmit thread can only have a right view of the
5745 * ring status.
5746 */
1e874e04 5747 smp_mb();
1da177e4 5748 if (netif_queue_stopped(dev) &&
477206a0 5749 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 5750 netif_wake_queue(dev);
5751 }
d78ae2dc
FR		 5752 /*
5753 * 8168 hack: TxPoll requests are lost when the Tx packets are
5754 * too close. Let's kick an extra TxPoll request when a burst
5755 * of start_xmit activity is detected (if it is not detected,
5756 * it is slow enough). -- FR
5757 */
da78dbff
FR		 5758 if (tp->cur_tx != dirty_tx) {
5759 void __iomem *ioaddr = tp->mmio_addr;
5760
d78ae2dc 5761 RTL_W8(TxPoll, NPQ);
da78dbff 5762 }
1da177e4
LT		 5763 }
5764}
5765
126fa4b9
FR		 5766static inline int rtl8169_fragmented_frame(u32 status)
5767{
5768 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5769}
5770
adea1ac7 5771static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5772{
1da177e4
LT		 5773 u32 status = opts1 & RxProtoMask;
5774
5775 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5776 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5777 skb->ip_summed = CHECKSUM_UNNECESSARY;
5778 else
bc8acf2c 5779 skb_checksum_none_assert(skb);
1da177e4
LT		 5780}
5781
6f0333b8
ED		 5782static struct sk_buff *rtl8169_try_rx_copy(void *data,
5783 struct rtl8169_private *tp,
5784 int pkt_size,
5785 dma_addr_t addr)
1da177e4 5786{
b449655f 5787 struct sk_buff *skb;
48addcc9 5788 struct device *d = &tp->pci_dev->dev;
b449655f 5789
6f0333b8 5790 data = rtl8169_align(data);
48addcc9 5791 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 5792 prefetch(data);
5793 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5794 if (skb)
5795 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 5796 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5797
6f0333b8 5798 return skb;
1da177e4
LT		 5799}
5800
da78dbff 5801static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 5802{
5803 unsigned int cur_rx, rx_left;
6f0333b8 5804 unsigned int count;
1da177e4 5805
1da177e4
LT		 5806 cur_rx = tp->cur_rx;
5807 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 5808 rx_left = min(rx_left, budget);
1da177e4 5809
4dcb7d33 5810 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 5811 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 5812 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 5813 u32 status;
5814
5815 rmb();
e03f33af 5816 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 5817
5818 if (status & DescOwn)
5819 break;
4dcb7d33 5820 if (unlikely(status & RxRES)) {
bf82c189
JP		 5821 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5822 status);
cebf8cc7 5823 dev->stats.rx_errors++;
1da177e4 5824 if (status & (RxRWT | RxRUNT))
cebf8cc7 5825 dev->stats.rx_length_errors++;
1da177e4 5826 if (status & RxCRC)
cebf8cc7 5827 dev->stats.rx_crc_errors++;
9dccf611 5828 if (status & RxFOVF) {
da78dbff 5829 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 5830 dev->stats.rx_fifo_errors++;
9dccf611 5831 }
6bbe021d
BG		 5832 if ((status & (RxRUNT | RxCRC)) &&
5833 !(status & (RxRWT | RxFOVF)) &&
5834 (dev->features & NETIF_F_RXALL))
5835 goto process_pkt;
5836
6f0333b8 5837 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 5838 } else {
6f0333b8 5839 struct sk_buff *skb;
6bbe021d
BG		 5840 dma_addr_t addr;
5841 int pkt_size;
5842
5843process_pkt:
5844 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 5845 if (likely(!(dev->features & NETIF_F_RXFCS)))
5846 pkt_size = (status & 0x00003fff) - 4;
5847 else
5848 pkt_size = status & 0x00003fff;
1da177e4 5849
126fa4b9
FR		 5850 /*
5851 * The driver does not support incoming fragmented
5852 * frames. They are seen as a symptom of over-mtu
5853 * sized frames.
5854 */
5855 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 5856 dev->stats.rx_dropped++;
5857 dev->stats.rx_length_errors++;
6f0333b8 5858 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 5859 continue;
126fa4b9
FR		 5860 }
5861
6f0333b8
ED		 5862 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5863 tp, pkt_size, addr);
5864 rtl8169_mark_to_asic(desc, rx_buf_sz);
5865 if (!skb) {
5866 dev->stats.rx_dropped++;
5867 continue;
1da177e4
LT		 5868 }
5869
adea1ac7 5870 rtl8169_rx_csum(skb, status);
1da177e4
LT		 5871 skb_put(skb, pkt_size);
5872 skb->protocol = eth_type_trans(skb, dev);
5873
7a8fc77b
FR		 5874 rtl8169_rx_vlan_tag(desc, skb);
5875
56de414c 5876 napi_gro_receive(&tp->napi, skb);
1da177e4 5877
8027aa24
JW		 5878 u64_stats_update_begin(&tp->rx_stats.syncp);
5879 tp->rx_stats.packets++;
5880 tp->rx_stats.bytes += pkt_size;
5881 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 5882 }
6dccd16b
FR		 5883
5884 /* Work around for AMD plateform. */
95e0918d 5885 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 5886 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5887 desc->opts2 = 0;
5888 cur_rx++;
5889 }
1da177e4
LT		 5890 }
5891
5892 count = cur_rx - tp->cur_rx;
5893 tp->cur_rx = cur_rx;
5894
6f0333b8 5895 tp->dirty_rx += count;
1da177e4
LT		 5896
5897 return count;
5898}
5899
07d3f51f 5900static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5901{
07d3f51f 5902 struct net_device *dev = dev_instance;
1da177e4 5903 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5904 int handled = 0;
9085cdfa 5905 u16 status;
1da177e4 5906
9085cdfa 5907 status = rtl_get_events(tp);
da78dbff
FR		 5908 if (status && status != 0xffff) {
5909 status &= RTL_EVENT_NAPI | tp->event_slow;
5910 if (status) {
5911 handled = 1;
1da177e4 5912
da78dbff
FR		 5913 rtl_irq_disable(tp);
5914 napi_schedule(&tp->napi);
f11a377b 5915 }
da78dbff
FR		 5916 }
5917 return IRQ_RETVAL(handled);
5918}
1da177e4 5919
da78dbff
FR		 5920/*
5921 * Workqueue context.
5922 */
5923static void rtl_slow_event_work(struct rtl8169_private *tp)
5924{
5925 struct net_device *dev = tp->dev;
5926 u16 status;
5927
5928 status = rtl_get_events(tp) & tp->event_slow;
5929 rtl_ack_events(tp, status);
1da177e4 5930
da78dbff
FR		 5931 if (unlikely(status & RxFIFOOver)) {
5932 switch (tp->mac_version) {
5933 /* Work around for rx fifo overflow */
5934 case RTL_GIGA_MAC_VER_11:
5935 netif_stop_queue(dev);
934714d0
FR		 5936 /* XXX - Hack alert. See rtl_task(). */
5937 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 5938 default:
f11a377b
DD		 5939 break;
5940 }
da78dbff 5941 }
1da177e4 5942
da78dbff
FR		 5943 if (unlikely(status & SYSErr))
5944 rtl8169_pcierr_interrupt(dev);
0e485150 5945
da78dbff
FR		 5946 if (status & LinkChg)
5947 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 5948
7dbb4918 5949 rtl_irq_enable_all(tp);
1da177e4
LT		 5950}
5951
4422bcd4
FR		 5952static void rtl_task(struct work_struct *work)
5953{
da78dbff
FR		 5954 static const struct {
5955 int bitnr;
5956 void (*action)(struct rtl8169_private *);
5957 } rtl_work[] = {
934714d0 5958 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 5959 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
5960 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5961 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
5962 };
4422bcd4
FR		 5963 struct rtl8169_private *tp =
5964 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 5965 struct net_device *dev = tp->dev;
5966 int i;
5967
5968 rtl_lock_work(tp);
5969
6c4a70c5
FR		 5970 if (!netif_running(dev) ||
5971 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 5972 goto out_unlock;
5973
5974 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5975 bool pending;
5976
da78dbff 5977 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 5978 if (pending)
5979 rtl_work[i].action(tp);
5980 }
4422bcd4 5981
da78dbff
FR		 5982out_unlock:
5983 rtl_unlock_work(tp);
4422bcd4
FR		 5984}
5985
bea3348e 5986static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5987{
bea3348e
SH		 5988 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5989 struct net_device *dev = tp->dev;
da78dbff
FR		 5990 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5991 int work_done= 0;
5992 u16 status;
5993
5994 status = rtl_get_events(tp);
5995 rtl_ack_events(tp, status & ~tp->event_slow);
5996
5997 if (status & RTL_EVENT_NAPI_RX)
5998 work_done = rtl_rx(dev, tp, (u32) budget);
5999
6000 if (status & RTL_EVENT_NAPI_TX)
6001 rtl_tx(dev, tp);
1da177e4 6002
da78dbff
FR		 6003 if (status & tp->event_slow) {
6004 enable_mask &= ~tp->event_slow;
6005
6006 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6007 }
1da177e4 6008
bea3348e 6009 if (work_done < budget) {
288379f0 6010 napi_complete(napi);
f11a377b 6011
da78dbff
FR		 6012 rtl_irq_enable(tp, enable_mask);
6013 mmiowb();
1da177e4
LT		 6014 }
6015
bea3348e 6016 return work_done;
1da177e4 6017}
1da177e4 6018
523a6094
FR		 6019static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6020{
6021 struct rtl8169_private *tp = netdev_priv(dev);
6022
6023 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6024 return;
6025
6026 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6027 RTL_W32(RxMissed, 0);
6028}
6029
1da177e4
LT		 6030static void rtl8169_down(struct net_device *dev)
6031{
6032 struct rtl8169_private *tp = netdev_priv(dev);
6033 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6034
4876cc1e 6035 del_timer_sync(&tp->timer);
1da177e4 6036
93dd79e8 6037 napi_disable(&tp->napi);
da78dbff 6038 netif_stop_queue(dev);
1da177e4 6039
92fc43b4 6040 rtl8169_hw_reset(tp);
323bb685
SG		 6041 /*
6042 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6043 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6044 * and napi is disabled (rtl8169_poll).
323bb685 6045 */
523a6094 6046 rtl8169_rx_missed(dev, ioaddr);
1da177e4 6047
1da177e4 6048 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6049 synchronize_sched();
1da177e4 6050
1da177e4
LT		 6051 rtl8169_tx_clear(tp);
6052
6053 rtl8169_rx_clear(tp);
065c27c1 6054
6055 rtl_pll_power_down(tp);
1da177e4
LT		 6056}
6057
6058static int rtl8169_close(struct net_device *dev)
6059{
6060 struct rtl8169_private *tp = netdev_priv(dev);
6061 struct pci_dev *pdev = tp->pci_dev;
6062
e1759441
RW		 6063 pm_runtime_get_sync(&pdev->dev);
6064
cecb5fd7 6065 /* Update counters before going down */
355423d0
IV		 6066 rtl8169_update_counters(dev);
6067
da78dbff 6068 rtl_lock_work(tp);
6c4a70c5 6069 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6070
1da177e4 6071 rtl8169_down(dev);
da78dbff 6072 rtl_unlock_work(tp);
1da177e4 6073
92a7c4e7 6074 free_irq(pdev->irq, dev);
1da177e4 6075
82553bb6
SG		 6076 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6077 tp->RxPhyAddr);
6078 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6079 tp->TxPhyAddr);
1da177e4
LT		 6080 tp->TxDescArray = NULL;
6081 tp->RxDescArray = NULL;
6082
e1759441
RW		 6083 pm_runtime_put_sync(&pdev->dev);
6084
1da177e4
LT		 6085 return 0;
6086}
6087
dc1c00ce
FR		 6088#ifdef CONFIG_NET_POLL_CONTROLLER
6089static void rtl8169_netpoll(struct net_device *dev)
6090{
6091 struct rtl8169_private *tp = netdev_priv(dev);
6092
6093 rtl8169_interrupt(tp->pci_dev->irq, dev);
6094}
6095#endif
6096
df43ac78
FR		 6097static int rtl_open(struct net_device *dev)
6098{
6099 struct rtl8169_private *tp = netdev_priv(dev);
6100 void __iomem *ioaddr = tp->mmio_addr;
6101 struct pci_dev *pdev = tp->pci_dev;
6102 int retval = -ENOMEM;
6103
6104 pm_runtime_get_sync(&pdev->dev);
6105
6106 /*
e75d6606 6107 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6108 * dma_alloc_coherent provides more.
6109 */
6110 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6111 &tp->TxPhyAddr, GFP_KERNEL);
6112 if (!tp->TxDescArray)
6113 goto err_pm_runtime_put;
6114
6115 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6116 &tp->RxPhyAddr, GFP_KERNEL);
6117 if (!tp->RxDescArray)
6118 goto err_free_tx_0;
6119
6120 retval = rtl8169_init_ring(dev);
6121 if (retval < 0)
6122 goto err_free_rx_1;
6123
6124 INIT_WORK(&tp->wk.work, rtl_task);
6125
6126 smp_mb();
6127
6128 rtl_request_firmware(tp);
6129
92a7c4e7 6130 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 6131 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6132 dev->name, dev);
6133 if (retval < 0)
6134 goto err_release_fw_2;
6135
6136 rtl_lock_work(tp);
6137
6138 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6139
6140 napi_enable(&tp->napi);
6141
6142 rtl8169_init_phy(dev, tp);
6143
6144 __rtl8169_set_features(dev, dev->features);
6145
6146 rtl_pll_power_up(tp);
6147
6148 rtl_hw_start(dev);
6149
6150 netif_start_queue(dev);
6151
6152 rtl_unlock_work(tp);
6153
6154 tp->saved_wolopts = 0;
6155 pm_runtime_put_noidle(&pdev->dev);
6156
6157 rtl8169_check_link_status(dev, tp, ioaddr);
6158out:
6159 return retval;
6160
6161err_release_fw_2:
6162 rtl_release_firmware(tp);
6163 rtl8169_rx_clear(tp);
6164err_free_rx_1:
6165 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6166 tp->RxPhyAddr);
6167 tp->RxDescArray = NULL;
6168err_free_tx_0:
6169 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6170 tp->TxPhyAddr);
6171 tp->TxDescArray = NULL;
6172err_pm_runtime_put:
6173 pm_runtime_put_noidle(&pdev->dev);
6174 goto out;
6175}
6176
8027aa24
JW		 6177static struct rtnl_link_stats64 *
6178rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6179{
6180 struct rtl8169_private *tp = netdev_priv(dev);
6181 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 6182 unsigned int start;
1da177e4 6183
da78dbff 6184 if (netif_running(dev))
523a6094 6185 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 6186
8027aa24
JW		 6187 do {
6188 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6189 stats->rx_packets = tp->rx_stats.packets;
6190 stats->rx_bytes = tp->rx_stats.bytes;
6191 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6192
6193
6194 do {
6195 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6196 stats->tx_packets = tp->tx_stats.packets;
6197 stats->tx_bytes = tp->tx_stats.bytes;
6198 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6199
6200 stats->rx_dropped = dev->stats.rx_dropped;
6201 stats->tx_dropped = dev->stats.tx_dropped;
6202 stats->rx_length_errors = dev->stats.rx_length_errors;
6203 stats->rx_errors = dev->stats.rx_errors;
6204 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6205 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6206 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6207
6208 return stats;
1da177e4
LT		 6209}
6210
861ab440 6211static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6212{
065c27c1 6213 struct rtl8169_private *tp = netdev_priv(dev);
6214
5d06a99f 6215 if (!netif_running(dev))
861ab440 6216 return;
5d06a99f
FR		 6217
6218 netif_device_detach(dev);
6219 netif_stop_queue(dev);
da78dbff
FR		 6220
6221 rtl_lock_work(tp);
6222 napi_disable(&tp->napi);
6c4a70c5 6223 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 6224 rtl_unlock_work(tp);
6225
6226 rtl_pll_power_down(tp);
861ab440
RW		 6227}
6228
6229#ifdef CONFIG_PM
6230
6231static int rtl8169_suspend(struct device *device)
6232{
6233 struct pci_dev *pdev = to_pci_dev(device);
6234 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6235
861ab440 6236 rtl8169_net_suspend(dev);
1371fa6d 6237
5d06a99f
FR		 6238 return 0;
6239}
6240
e1759441
RW		 6241static void __rtl8169_resume(struct net_device *dev)
6242{
065c27c1 6243 struct rtl8169_private *tp = netdev_priv(dev);
6244
e1759441 6245 netif_device_attach(dev);
065c27c1 6246
6247 rtl_pll_power_up(tp);
6248
cff4c162
AS		 6249 rtl_lock_work(tp);
6250 napi_enable(&tp->napi);
6c4a70c5 6251 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6252 rtl_unlock_work(tp);
da78dbff 6253
98ddf986 6254 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6255}
6256
861ab440 6257static int rtl8169_resume(struct device *device)
5d06a99f 6258{
861ab440 6259 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6260 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6261 struct rtl8169_private *tp = netdev_priv(dev);
6262
6263 rtl8169_init_phy(dev, tp);
5d06a99f 6264
e1759441
RW		 6265 if (netif_running(dev))
6266 __rtl8169_resume(dev);
5d06a99f 6267
e1759441
RW		 6268 return 0;
6269}
6270
6271static int rtl8169_runtime_suspend(struct device *device)
6272{
6273 struct pci_dev *pdev = to_pci_dev(device);
6274 struct net_device *dev = pci_get_drvdata(pdev);
6275 struct rtl8169_private *tp = netdev_priv(dev);
6276
6277 if (!tp->TxDescArray)
6278 return 0;
6279
da78dbff 6280 rtl_lock_work(tp);
e1759441
RW		 6281 tp->saved_wolopts = __rtl8169_get_wol(tp);
6282 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6283 rtl_unlock_work(tp);
e1759441
RW		 6284
6285 rtl8169_net_suspend(dev);
6286
6287 return 0;
6288}
6289
6290static int rtl8169_runtime_resume(struct device *device)
6291{
6292 struct pci_dev *pdev = to_pci_dev(device);
6293 struct net_device *dev = pci_get_drvdata(pdev);
6294 struct rtl8169_private *tp = netdev_priv(dev);
6295
6296 if (!tp->TxDescArray)
6297 return 0;
6298
da78dbff 6299 rtl_lock_work(tp);
e1759441
RW		 6300 __rtl8169_set_wol(tp, tp->saved_wolopts);
6301 tp->saved_wolopts = 0;
da78dbff 6302 rtl_unlock_work(tp);
e1759441 6303
fccec10b
SG		 6304 rtl8169_init_phy(dev, tp);
6305
e1759441 6306 __rtl8169_resume(dev);
5d06a99f 6307
5d06a99f
FR		 6308 return 0;
6309}
6310
e1759441
RW		 6311static int rtl8169_runtime_idle(struct device *device)
6312{
6313 struct pci_dev *pdev = to_pci_dev(device);
6314 struct net_device *dev = pci_get_drvdata(pdev);
6315 struct rtl8169_private *tp = netdev_priv(dev);
6316
e4fbce74 6317 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6318}
6319
47145210 6320static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6321 .suspend = rtl8169_suspend,
6322 .resume = rtl8169_resume,
6323 .freeze = rtl8169_suspend,
6324 .thaw = rtl8169_resume,
6325 .poweroff = rtl8169_suspend,
6326 .restore = rtl8169_resume,
6327 .runtime_suspend = rtl8169_runtime_suspend,
6328 .runtime_resume = rtl8169_runtime_resume,
6329 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6330};
6331
6332#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6333
6334#else /* !CONFIG_PM */
6335
6336#define RTL8169_PM_OPS NULL
6337
6338#endif /* !CONFIG_PM */
6339
649b3b8c 6340static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6341{
6342 void __iomem *ioaddr = tp->mmio_addr;
6343
6344 /* WoL fails with 8168b when the receiver is disabled. */
6345 switch (tp->mac_version) {
6346 case RTL_GIGA_MAC_VER_11:
6347 case RTL_GIGA_MAC_VER_12:
6348 case RTL_GIGA_MAC_VER_17:
6349 pci_clear_master(tp->pci_dev);
6350
6351 RTL_W8(ChipCmd, CmdRxEnb);
6352 /* PCI commit */
6353 RTL_R8(ChipCmd);
6354 break;
6355 default:
6356 break;
6357 }
6358}
6359
1765f95d
FR		 6360static void rtl_shutdown(struct pci_dev *pdev)
6361{
861ab440 6362 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6363 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 6364 struct device *d = &pdev->dev;
6365
6366 pm_runtime_get_sync(d);
861ab440
RW		 6367
6368 rtl8169_net_suspend(dev);
1765f95d 6369
cecb5fd7 6370 /* Restore original MAC address */
cc098dc7
IV		 6371 rtl_rar_set(tp, dev->perm_addr);
6372
92fc43b4 6373 rtl8169_hw_reset(tp);
4bb3f522 6374
861ab440 6375 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6376 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6377 rtl_wol_suspend_quirk(tp);
6378 rtl_wol_shutdown_quirk(tp);
ca52efd5 6379 }
6380
861ab440
RW		 6381 pci_wake_from_d3(pdev, true);
6382 pci_set_power_state(pdev, PCI_D3hot);
6383 }
2a15cd2f 6384
6385 pm_runtime_put_noidle(d);
861ab440 6386}
5d06a99f 6387
e27566ed
FR		 6388static void __devexit rtl_remove_one(struct pci_dev *pdev)
6389{
6390 struct net_device *dev = pci_get_drvdata(pdev);
6391 struct rtl8169_private *tp = netdev_priv(dev);
6392
6393 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6394 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6395 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6396 rtl8168_driver_stop(tp);
6397 }
6398
6399 cancel_work_sync(&tp->wk.work);
6400
ad1be8d3
DN		 6401 netif_napi_del(&tp->napi);
6402
e27566ed
FR		 6403 unregister_netdev(dev);
6404
6405 rtl_release_firmware(tp);
6406
6407 if (pci_dev_run_wake(pdev))
6408 pm_runtime_get_noresume(&pdev->dev);
6409
6410 /* restore original MAC address */
6411 rtl_rar_set(tp, dev->perm_addr);
6412
6413 rtl_disable_msi(pdev, tp);
6414 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6415 pci_set_drvdata(pdev, NULL);
6416}
6417
fa9c385e 6418static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6419 .ndo_open = rtl_open,
fa9c385e
FR		 6420 .ndo_stop = rtl8169_close,
6421 .ndo_get_stats64 = rtl8169_get_stats64,
6422 .ndo_start_xmit = rtl8169_start_xmit,
6423 .ndo_tx_timeout = rtl8169_tx_timeout,
6424 .ndo_validate_addr = eth_validate_addr,
6425 .ndo_change_mtu = rtl8169_change_mtu,
6426 .ndo_fix_features = rtl8169_fix_features,
6427 .ndo_set_features = rtl8169_set_features,
6428 .ndo_set_mac_address = rtl_set_mac_address,
6429 .ndo_do_ioctl = rtl8169_ioctl,
6430 .ndo_set_rx_mode = rtl_set_rx_mode,
6431#ifdef CONFIG_NET_POLL_CONTROLLER
6432 .ndo_poll_controller = rtl8169_netpoll,
6433#endif
6434
6435};
6436
31fa8b18
FR		 6437static const struct rtl_cfg_info {
6438 void (*hw_start)(struct net_device *);
6439 unsigned int region;
6440 unsigned int align;
6441 u16 event_slow;
6442 unsigned features;
6443 u8 default_ver;
6444} rtl_cfg_infos [] = {
6445 [RTL_CFG_0] = {
6446 .hw_start = rtl_hw_start_8169,
6447 .region = 1,
6448 .align = 0,
6449 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6450 .features = RTL_FEATURE_GMII,
6451 .default_ver = RTL_GIGA_MAC_VER_01,
6452 },
6453 [RTL_CFG_1] = {
6454 .hw_start = rtl_hw_start_8168,
6455 .region = 2,
6456 .align = 8,
6457 .event_slow = SYSErr | LinkChg | RxOverflow,
6458 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6459 .default_ver = RTL_GIGA_MAC_VER_11,
6460 },
6461 [RTL_CFG_2] = {
6462 .hw_start = rtl_hw_start_8101,
6463 .region = 2,
6464 .align = 8,
6465 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6466 PCSTimeout,
6467 .features = RTL_FEATURE_MSI,
6468 .default_ver = RTL_GIGA_MAC_VER_13,
6469 }
6470};
6471
6472/* Cfg9346_Unlock assumed. */
6473static unsigned rtl_try_msi(struct rtl8169_private *tp,
6474 const struct rtl_cfg_info *cfg)
6475{
6476 void __iomem *ioaddr = tp->mmio_addr;
6477 unsigned msi = 0;
6478 u8 cfg2;
6479
6480 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6481 if (cfg->features & RTL_FEATURE_MSI) {
6482 if (pci_enable_msi(tp->pci_dev)) {
6483 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6484 } else {
6485 cfg2 |= MSIEnable;
6486 msi = RTL_FEATURE_MSI;
6487 }
6488 }
6489 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6490 RTL_W8(Config2, cfg2);
6491 return msi;
6492}
6493
3b6cf25d
FR		 6494static int __devinit
6495rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6496{
6497 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6498 const unsigned int region = cfg->region;
6499 struct rtl8169_private *tp;
6500 struct mii_if_info *mii;
6501 struct net_device *dev;
6502 void __iomem *ioaddr;
6503 int chipset, i;
6504 int rc;
6505
6506 if (netif_msg_drv(&debug)) {
6507 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6508 MODULENAME, RTL8169_VERSION);
6509 }
6510
6511 dev = alloc_etherdev(sizeof (*tp));
6512 if (!dev) {
6513 rc = -ENOMEM;
6514 goto out;
6515 }
6516
6517 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 6518 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 6519 tp = netdev_priv(dev);
6520 tp->dev = dev;
6521 tp->pci_dev = pdev;
6522 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6523
6524 mii = &tp->mii;
6525 mii->dev = dev;
6526 mii->mdio_read = rtl_mdio_read;
6527 mii->mdio_write = rtl_mdio_write;
6528 mii->phy_id_mask = 0x1f;
6529 mii->reg_num_mask = 0x1f;
6530 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6531
6532 /* disable ASPM completely as that cause random device stop working
6533 * problems as well as full system hangs for some PCIe devices users */
6534 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6535 PCIE_LINK_STATE_CLKPM);
6536
6537 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6538 rc = pci_enable_device(pdev);
6539 if (rc < 0) {
6540 netif_err(tp, probe, dev, "enable failure\n");
6541 goto err_out_free_dev_1;
6542 }
6543
6544 if (pci_set_mwi(pdev) < 0)
6545 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6546
6547 /* make sure PCI base addr 1 is MMIO */
6548 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6549 netif_err(tp, probe, dev,
6550 "region #%d not an MMIO resource, aborting\n",
6551 region);
6552 rc = -ENODEV;
6553 goto err_out_mwi_2;
6554 }
6555
6556 /* check for weird/broken PCI region reporting */
6557 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6558 netif_err(tp, probe, dev,
6559 "Invalid PCI region size(s), aborting\n");
6560 rc = -ENODEV;
6561 goto err_out_mwi_2;
6562 }
6563
6564 rc = pci_request_regions(pdev, MODULENAME);
6565 if (rc < 0) {
6566 netif_err(tp, probe, dev, "could not request regions\n");
6567 goto err_out_mwi_2;
6568 }
6569
6570 tp->cp_cmd = RxChkSum;
6571
6572 if ((sizeof(dma_addr_t) > 4) &&
6573 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6574 tp->cp_cmd |= PCIDAC;
6575 dev->features |= NETIF_F_HIGHDMA;
6576 } else {
6577 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6578 if (rc < 0) {
6579 netif_err(tp, probe, dev, "DMA configuration failed\n");
6580 goto err_out_free_res_3;
6581 }
6582 }
6583
6584 /* ioremap MMIO region */
6585 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6586 if (!ioaddr) {
6587 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6588 rc = -EIO;
6589 goto err_out_free_res_3;
6590 }
6591 tp->mmio_addr = ioaddr;
6592
6593 if (!pci_is_pcie(pdev))
6594 netif_info(tp, probe, dev, "not PCI Express\n");
6595
6596 /* Identify chip attached to board */
6597 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6598
6599 rtl_init_rxcfg(tp);
6600
6601 rtl_irq_disable(tp);
6602
6603 rtl_hw_reset(tp);
6604
6605 rtl_ack_events(tp, 0xffff);
6606
6607 pci_set_master(pdev);
6608
6609 /*
6610 * Pretend we are using VLANs; This bypasses a nasty bug where
6611 * Interrupts stop flowing on high load on 8110SCd controllers.
6612 */
6613 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6614 tp->cp_cmd |= RxVlan;
6615
6616 rtl_init_mdio_ops(tp);
6617 rtl_init_pll_power_ops(tp);
6618 rtl_init_jumbo_ops(tp);
beb1fe18 6619 rtl_init_csi_ops(tp);
3b6cf25d
FR		 6620
6621 rtl8169_print_mac_version(tp);
6622
6623 chipset = tp->mac_version;
6624 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6625
6626 RTL_W8(Cfg9346, Cfg9346_Unlock);
6627 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6628 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6629 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6630 tp->features |= RTL_FEATURE_WOL;
6631 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6632 tp->features |= RTL_FEATURE_WOL;
6633 tp->features |= rtl_try_msi(tp, cfg);
6634 RTL_W8(Cfg9346, Cfg9346_Lock);
6635
6636 if (rtl_tbi_enabled(tp)) {
6637 tp->set_speed = rtl8169_set_speed_tbi;
6638 tp->get_settings = rtl8169_gset_tbi;
6639 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6640 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6641 tp->link_ok = rtl8169_tbi_link_ok;
6642 tp->do_ioctl = rtl_tbi_ioctl;
6643 } else {
6644 tp->set_speed = rtl8169_set_speed_xmii;
6645 tp->get_settings = rtl8169_gset_xmii;
6646 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6647 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6648 tp->link_ok = rtl8169_xmii_link_ok;
6649 tp->do_ioctl = rtl_xmii_ioctl;
6650 }
6651
6652 mutex_init(&tp->wk.mutex);
6653
6654 /* Get MAC address */
6655 for (i = 0; i < ETH_ALEN; i++)
6656 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6657 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6658
6659 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6660 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 6661
6662 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6663
6664 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6665 * properly for all devices */
6666 dev->features |= NETIF_F_RXCSUM |
6667 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6668
6669 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6670 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6671 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6672 NETIF_F_HIGHDMA;
6673
6674 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6675 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6676 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6677
6678 dev->hw_features |= NETIF_F_RXALL;
6679 dev->hw_features |= NETIF_F_RXFCS;
6680
6681 tp->hw_start = cfg->hw_start;
6682 tp->event_slow = cfg->event_slow;
6683
6684 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6685 ~(RxBOVF | RxFOVF) : ~0;
6686
6687 init_timer(&tp->timer);
6688 tp->timer.data = (unsigned long) dev;
6689 tp->timer.function = rtl8169_phy_timer;
6690
6691 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6692
6693 rc = register_netdev(dev);
6694 if (rc < 0)
6695 goto err_out_msi_4;
6696
6697 pci_set_drvdata(pdev, dev);
6698
92a7c4e7
FR		 6699 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6700 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6701 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 6702 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6703 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6704 "tx checksumming: %s]\n",
6705 rtl_chip_infos[chipset].jumbo_max,
6706 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6707 }
6708
6709 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6710 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6711 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6712 rtl8168_driver_start(tp);
6713 }
6714
6715 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6716
6717 if (pci_dev_run_wake(pdev))
6718 pm_runtime_put_noidle(&pdev->dev);
6719
6720 netif_carrier_off(dev);
6721
6722out:
6723 return rc;
6724
6725err_out_msi_4:
ad1be8d3 6726 netif_napi_del(&tp->napi);
3b6cf25d
FR		 6727 rtl_disable_msi(pdev, tp);
6728 iounmap(ioaddr);
6729err_out_free_res_3:
6730 pci_release_regions(pdev);
6731err_out_mwi_2:
6732 pci_clear_mwi(pdev);
6733 pci_disable_device(pdev);
6734err_out_free_dev_1:
6735 free_netdev(dev);
6736 goto out;
6737}
6738
1da177e4
LT		 6739static struct pci_driver rtl8169_pci_driver = {
6740 .name = MODULENAME,
6741 .id_table = rtl8169_pci_tbl,
3b6cf25d 6742 .probe = rtl_init_one,
e27566ed 6743 .remove = __devexit_p(rtl_remove_one),
1765f95d 6744 .shutdown = rtl_shutdown,
861ab440 6745 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 6746};
6747
07d3f51f 6748static int __init rtl8169_init_module(void)
1da177e4 6749{
29917620 6750 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 6751}
6752
07d3f51f 6753static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 6754{
6755 pci_unregister_driver(&rtl8169_pci_driver);
6756}
6757
6758module_init(rtl8169_init_module);
6759module_exit(rtl8169_cleanup_module);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git