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tipc: optimize function tipc_node_timeout()
[thirdparty/kernel/stable.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
a6b7a407 24#include <linux/interrupt.h>
1da177e4 25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
70c71606 28#include <linux/prefetch.h>
e974604b 29#include <linux/ipv6.h>
30#include <net/ip6_checksum.h>
1da177e4
LT		 31
32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4 36#define MODULENAME "r8169"
1da177e4 37
bca03d5f 38#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 40#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 42#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 43#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 45#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 46#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 47#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 48#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 50#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 51#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 52#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 53#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
54#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
55#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
56#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 57
b57b7e5a 58#define R8169_MSG_DEFAULT \
f0e837d9 59 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 60
477206a0
JD		 61#define TX_SLOTS_AVAIL(tp) \
62 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
63
64/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
65#define TX_FRAGS_READY_FOR(tp,nr_frags) \
66 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 67
1da177e4
LT		 68/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 70static const int multicast_filter_limit = 32;
1da177e4 71
aee77e4a 72#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 73#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
74
75#define R8169_REGS_SIZE 256
1d0254dd 76#define R8169_RX_BUF_SIZE (SZ_16K - 1)
1da177e4 77#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 78#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 79#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
80#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81
82#define RTL8169_TX_TIMEOUT (6*HZ)
83#define RTL8169_PHY_TIMEOUT (10*HZ)
84
85/* write/read MMIO register */
1ef7286e
AS		 86#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
87#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
88#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
89#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
90#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
91#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
1da177e4
LT		 92
93enum mac_version {
85bffe6c
FR		 94 RTL_GIGA_MAC_VER_01 = 0,
95 RTL_GIGA_MAC_VER_02,
96 RTL_GIGA_MAC_VER_03,
97 RTL_GIGA_MAC_VER_04,
98 RTL_GIGA_MAC_VER_05,
99 RTL_GIGA_MAC_VER_06,
100 RTL_GIGA_MAC_VER_07,
101 RTL_GIGA_MAC_VER_08,
102 RTL_GIGA_MAC_VER_09,
103 RTL_GIGA_MAC_VER_10,
104 RTL_GIGA_MAC_VER_11,
105 RTL_GIGA_MAC_VER_12,
106 RTL_GIGA_MAC_VER_13,
107 RTL_GIGA_MAC_VER_14,
108 RTL_GIGA_MAC_VER_15,
109 RTL_GIGA_MAC_VER_16,
110 RTL_GIGA_MAC_VER_17,
111 RTL_GIGA_MAC_VER_18,
112 RTL_GIGA_MAC_VER_19,
113 RTL_GIGA_MAC_VER_20,
114 RTL_GIGA_MAC_VER_21,
115 RTL_GIGA_MAC_VER_22,
116 RTL_GIGA_MAC_VER_23,
117 RTL_GIGA_MAC_VER_24,
118 RTL_GIGA_MAC_VER_25,
119 RTL_GIGA_MAC_VER_26,
120 RTL_GIGA_MAC_VER_27,
121 RTL_GIGA_MAC_VER_28,
122 RTL_GIGA_MAC_VER_29,
123 RTL_GIGA_MAC_VER_30,
124 RTL_GIGA_MAC_VER_31,
125 RTL_GIGA_MAC_VER_32,
126 RTL_GIGA_MAC_VER_33,
70090424 127 RTL_GIGA_MAC_VER_34,
c2218925
HW		 128 RTL_GIGA_MAC_VER_35,
129 RTL_GIGA_MAC_VER_36,
7e18dca1 130 RTL_GIGA_MAC_VER_37,
b3d7b2f2 131 RTL_GIGA_MAC_VER_38,
5598bfe5 132 RTL_GIGA_MAC_VER_39,
c558386b
HW		 133 RTL_GIGA_MAC_VER_40,
134 RTL_GIGA_MAC_VER_41,
57538c4a 135 RTL_GIGA_MAC_VER_42,
58152cd4 136 RTL_GIGA_MAC_VER_43,
45dd95c4 137 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 138 RTL_GIGA_MAC_VER_45,
139 RTL_GIGA_MAC_VER_46,
140 RTL_GIGA_MAC_VER_47,
141 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 142 RTL_GIGA_MAC_VER_49,
143 RTL_GIGA_MAC_VER_50,
144 RTL_GIGA_MAC_VER_51,
85bffe6c 145 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 146};
147
2b7b4318
FR		 148enum rtl_tx_desc_version {
149 RTL_TD_0 = 0,
150 RTL_TD_1 = 1,
151};
152
d58d46b5
FR		 153#define JUMBO_1K ETH_DATA_LEN
154#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
155#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
156#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
157#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
158
6ed0e08f 159#define _R(NAME,TD,FW,SZ) { \
d58d46b5
FR		 160 .name = NAME, \
161 .txd_version = TD, \
162 .fw_name = FW, \
163 .jumbo_max = SZ, \
d58d46b5 164}
1da177e4 165
3c6bee1d 166static const struct {
1da177e4 167 const char *name;
2b7b4318 168 enum rtl_tx_desc_version txd_version;
953a12cc 169 const char *fw_name;
d58d46b5 170 u16 jumbo_max;
85bffe6c
FR		 171} rtl_chip_infos[] = {
172 /* PCI devices. */
173 [RTL_GIGA_MAC_VER_01] =
6ed0e08f 174 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 175 [RTL_GIGA_MAC_VER_02] =
6ed0e08f 176 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 177 [RTL_GIGA_MAC_VER_03] =
6ed0e08f 178 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 179 [RTL_GIGA_MAC_VER_04] =
6ed0e08f 180 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 181 [RTL_GIGA_MAC_VER_05] =
6ed0e08f 182 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 183 [RTL_GIGA_MAC_VER_06] =
6ed0e08f 184 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c
FR		 185 /* PCI-E devices. */
186 [RTL_GIGA_MAC_VER_07] =
6ed0e08f 187 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
85bffe6c 188 [RTL_GIGA_MAC_VER_08] =
6ed0e08f 189 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
85bffe6c 190 [RTL_GIGA_MAC_VER_09] =
6ed0e08f 191 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
85bffe6c 192 [RTL_GIGA_MAC_VER_10] =
6ed0e08f 193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 194 [RTL_GIGA_MAC_VER_11] =
6ed0e08f 195 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
85bffe6c 196 [RTL_GIGA_MAC_VER_12] =
6ed0e08f 197 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
85bffe6c 198 [RTL_GIGA_MAC_VER_13] =
6ed0e08f 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 200 [RTL_GIGA_MAC_VER_14] =
6ed0e08f 201 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 202 [RTL_GIGA_MAC_VER_15] =
6ed0e08f 203 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 204 [RTL_GIGA_MAC_VER_16] =
6ed0e08f 205 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 206 [RTL_GIGA_MAC_VER_17] =
6ed0e08f 207 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
85bffe6c 208 [RTL_GIGA_MAC_VER_18] =
6ed0e08f 209 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 210 [RTL_GIGA_MAC_VER_19] =
6ed0e08f 211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 212 [RTL_GIGA_MAC_VER_20] =
6ed0e08f 213 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 214 [RTL_GIGA_MAC_VER_21] =
6ed0e08f 215 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 216 [RTL_GIGA_MAC_VER_22] =
6ed0e08f 217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 218 [RTL_GIGA_MAC_VER_23] =
6ed0e08f 219 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 220 [RTL_GIGA_MAC_VER_24] =
6ed0e08f 221 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 222 [RTL_GIGA_MAC_VER_25] =
6ed0e08f 223 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, JUMBO_9K),
85bffe6c 224 [RTL_GIGA_MAC_VER_26] =
6ed0e08f 225 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, JUMBO_9K),
85bffe6c 226 [RTL_GIGA_MAC_VER_27] =
6ed0e08f 227 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
85bffe6c 228 [RTL_GIGA_MAC_VER_28] =
6ed0e08f 229 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
85bffe6c 230 [RTL_GIGA_MAC_VER_29] =
6ed0e08f 231 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
85bffe6c 232 [RTL_GIGA_MAC_VER_30] =
6ed0e08f 233 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
85bffe6c 234 [RTL_GIGA_MAC_VER_31] =
6ed0e08f 235 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
85bffe6c 236 [RTL_GIGA_MAC_VER_32] =
6ed0e08f 237 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, JUMBO_9K),
85bffe6c 238 [RTL_GIGA_MAC_VER_33] =
6ed0e08f 239 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, JUMBO_9K),
70090424 240 [RTL_GIGA_MAC_VER_34] =
6ed0e08f 241 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, JUMBO_9K),
c2218925 242 [RTL_GIGA_MAC_VER_35] =
6ed0e08f 243 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, JUMBO_9K),
c2218925 244 [RTL_GIGA_MAC_VER_36] =
6ed0e08f 245 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, JUMBO_9K),
7e18dca1 246 [RTL_GIGA_MAC_VER_37] =
6ed0e08f 247 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1, JUMBO_1K),
b3d7b2f2 248 [RTL_GIGA_MAC_VER_38] =
6ed0e08f 249 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1, JUMBO_9K),
5598bfe5 250 [RTL_GIGA_MAC_VER_39] =
6ed0e08f 251 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1, JUMBO_1K),
c558386b 252 [RTL_GIGA_MAC_VER_40] =
6ed0e08f 253 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2, JUMBO_9K),
c558386b 254 [RTL_GIGA_MAC_VER_41] =
6ed0e08f 255 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K),
57538c4a 256 [RTL_GIGA_MAC_VER_42] =
6ed0e08f 257 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3, JUMBO_9K),
58152cd4 258 [RTL_GIGA_MAC_VER_43] =
6ed0e08f 259 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2, JUMBO_1K),
45dd95c4 260 [RTL_GIGA_MAC_VER_44] =
6ed0e08f 261 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2, JUMBO_9K),
6e1d0b89 262 [RTL_GIGA_MAC_VER_45] =
6ed0e08f 263 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1, JUMBO_9K),
6e1d0b89 264 [RTL_GIGA_MAC_VER_46] =
6ed0e08f 265 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2, JUMBO_9K),
6e1d0b89 266 [RTL_GIGA_MAC_VER_47] =
6ed0e08f 267 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1, JUMBO_1K),
6e1d0b89 268 [RTL_GIGA_MAC_VER_48] =
6ed0e08f 269 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2, JUMBO_1K),
935e2218 270 [RTL_GIGA_MAC_VER_49] =
6ed0e08f 271 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
935e2218 272 [RTL_GIGA_MAC_VER_50] =
6ed0e08f 273 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
935e2218 274 [RTL_GIGA_MAC_VER_51] =
6ed0e08f 275 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
953a12cc 276};
85bffe6c 277#undef _R
953a12cc 278
bcf0bf90
FR		 279enum cfg_version {
280 RTL_CFG_0 = 0x00,
281 RTL_CFG_1,
282 RTL_CFG_2
283};
284
9baa3c34 285static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 286 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 287 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
610c9087 288 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
d81bf551 289 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 290 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 291 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 292 { PCI_VENDOR_ID_DLINK, 0x4300,
293 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 294 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 295 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 296 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 297 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
298 { PCI_VENDOR_ID_LINKSYS, 0x1032,
299 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 300 { 0x0001, 0x8168,
301 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 302 {0,},
303};
304
305MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
306
27896c83 307static int use_dac = -1;
b57b7e5a
SH		 308static struct {
309 u32 msg_enable;
310} debug = { -1 };
1da177e4 311
07d3f51f
FR		 312enum rtl_registers {
313 MAC0 = 0, /* Ethernet hardware address. */
773d2021 314 MAC4 = 4,
07d3f51f
FR		 315 MAR0 = 8, /* Multicast filter. */
316 CounterAddrLow = 0x10,
317 CounterAddrHigh = 0x14,
318 TxDescStartAddrLow = 0x20,
319 TxDescStartAddrHigh = 0x24,
320 TxHDescStartAddrLow = 0x28,
321 TxHDescStartAddrHigh = 0x2c,
322 FLASH = 0x30,
323 ERSR = 0x36,
324 ChipCmd = 0x37,
325 TxPoll = 0x38,
326 IntrMask = 0x3c,
327 IntrStatus = 0x3e,
4f6b00e5 328
07d3f51f 329 TxConfig = 0x40,
4f6b00e5
HW		 330#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
331#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 332
4f6b00e5
HW		 333 RxConfig = 0x44,
334#define RX128_INT_EN (1 << 15) /* 8111c and later */
335#define RX_MULTI_EN (1 << 14) /* 8111c only */
336#define RXCFG_FIFO_SHIFT 13
337 /* No threshold before first PCI xfer */
338#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 339#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 340#define RXCFG_DMA_SHIFT 8
341 /* Unlimited maximum PCI burst. */
342#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 343
07d3f51f
FR		 344 RxMissed = 0x4c,
345 Cfg9346 = 0x50,
346 Config0 = 0x51,
347 Config1 = 0x52,
348 Config2 = 0x53,
d387b427
FR		 349#define PME_SIGNAL (1 << 5) /* 8168c and later */
350
07d3f51f
FR		 351 Config3 = 0x54,
352 Config4 = 0x55,
353 Config5 = 0x56,
354 MultiIntr = 0x5c,
355 PHYAR = 0x60,
07d3f51f
FR		 356 PHYstatus = 0x6c,
357 RxMaxSize = 0xda,
358 CPlusCmd = 0xe0,
359 IntrMitigate = 0xe2,
50970831
FR		 360
361#define RTL_COALESCE_MASK 0x0f
362#define RTL_COALESCE_SHIFT 4
363#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
364#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
365
07d3f51f
FR		 366 RxDescAddrLow = 0xe4,
367 RxDescAddrHigh = 0xe8,
f0298f81 368 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
369
370#define NoEarlyTx 0x3f /* Max value : no early transmit. */
371
372 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
373
374#define TxPacketMax (8064 >> 7)
3090bd9a 375#define EarlySize 0x27
f0298f81 376
07d3f51f
FR		 377 FuncEvent = 0xf0,
378 FuncEventMask = 0xf4,
379 FuncPresetState = 0xf8,
935e2218
CHL		 380 IBCR0 = 0xf8,
381 IBCR2 = 0xf9,
382 IBIMR0 = 0xfa,
383 IBISR0 = 0xfb,
07d3f51f 384 FuncForceEvent = 0xfc,
1da177e4
LT		 385};
386
f162a5d1
FR		 387enum rtl8110_registers {
388 TBICSR = 0x64,
389 TBI_ANAR = 0x68,
390 TBI_LPAR = 0x6a,
391};
392
393enum rtl8168_8101_registers {
394 CSIDR = 0x64,
395 CSIAR = 0x68,
396#define CSIAR_FLAG 0x80000000
397#define CSIAR_WRITE_CMD 0x80000000
ff1d7331
HK		 398#define CSIAR_BYTE_ENABLE 0x0000f000
399#define CSIAR_ADDR_MASK 0x00000fff
065c27c1 400 PMCH = 0x6f,
f162a5d1
FR		 401 EPHYAR = 0x80,
402#define EPHYAR_FLAG 0x80000000
403#define EPHYAR_WRITE_CMD 0x80000000
404#define EPHYAR_REG_MASK 0x1f
405#define EPHYAR_REG_SHIFT 16
406#define EPHYAR_DATA_MASK 0xffff
5a5e4443 407 DLLPR = 0xd0,
4f6b00e5 408#define PFM_EN (1 << 6)
6e1d0b89 409#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 410 DBG_REG = 0xd1,
411#define FIX_NAK_1 (1 << 4)
412#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 413 TWSI = 0xd2,
414 MCU = 0xd3,
4f6b00e5 415#define NOW_IS_OOB (1 << 7)
c558386b
HW		 416#define TX_EMPTY (1 << 5)
417#define RX_EMPTY (1 << 4)
418#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 419#define EN_NDP (1 << 3)
420#define EN_OOB_RESET (1 << 2)
c558386b 421#define LINK_LIST_RDY (1 << 1)
daf9df6d 422 EFUSEAR = 0xdc,
423#define EFUSEAR_FLAG 0x80000000
424#define EFUSEAR_WRITE_CMD 0x80000000
425#define EFUSEAR_READ_CMD 0x00000000
426#define EFUSEAR_REG_MASK 0x03ff
427#define EFUSEAR_REG_SHIFT 8
428#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 429 MISC_1 = 0xf2,
430#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 431};
432
c0e45c1c 433enum rtl8168_registers {
4f6b00e5
HW		 434 LED_FREQ = 0x1a,
435 EEE_LED = 0x1b,
b646d900 436 ERIDR = 0x70,
437 ERIAR = 0x74,
438#define ERIAR_FLAG 0x80000000
439#define ERIAR_WRITE_CMD 0x80000000
440#define ERIAR_READ_CMD 0x00000000
441#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 442#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 443#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
444#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
445#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 446#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 447#define ERIAR_MASK_SHIFT 12
448#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
449#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 450#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 451#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 452#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 453 EPHY_RXER_NUM = 0x7c,
454 OCPDR = 0xb0, /* OCP GPHY access */
455#define OCPDR_WRITE_CMD 0x80000000
456#define OCPDR_READ_CMD 0x00000000
457#define OCPDR_REG_MASK 0x7f
458#define OCPDR_GPHY_REG_SHIFT 16
459#define OCPDR_DATA_MASK 0xffff
460 OCPAR = 0xb4,
461#define OCPAR_FLAG 0x80000000
462#define OCPAR_GPHY_WRITE_CMD 0x8000f060
463#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 464 GPHY_OCP = 0xb8,
01dc7fec 465 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
466 MISC = 0xf0, /* 8168e only. */
cecb5fd7 467#define TXPLA_RST (1 << 29)
5598bfe5 468#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 469#define PWM_EN (1 << 22)
c558386b 470#define RXDV_GATED_EN (1 << 19)
5598bfe5 471#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 472};
473
07d3f51f 474enum rtl_register_content {
1da177e4 475 /* InterruptStatusBits */
07d3f51f
FR		 476 SYSErr = 0x8000,
477 PCSTimeout = 0x4000,
478 SWInt = 0x0100,
479 TxDescUnavail = 0x0080,
480 RxFIFOOver = 0x0040,
481 LinkChg = 0x0020,
482 RxOverflow = 0x0010,
483 TxErr = 0x0008,
484 TxOK = 0x0004,
485 RxErr = 0x0002,
486 RxOK = 0x0001,
1da177e4
LT		 487
488 /* RxStatusDesc */
e03f33af 489 RxBOVF = (1 << 24),
9dccf611
FR		 490 RxFOVF = (1 << 23),
491 RxRWT = (1 << 22),
492 RxRES = (1 << 21),
493 RxRUNT = (1 << 20),
494 RxCRC = (1 << 19),
1da177e4
LT		 495
496 /* ChipCmdBits */
4f6b00e5 497 StopReq = 0x80,
07d3f51f
FR		 498 CmdReset = 0x10,
499 CmdRxEnb = 0x08,
500 CmdTxEnb = 0x04,
501 RxBufEmpty = 0x01,
1da177e4 502
275391a4
FR		 503 /* TXPoll register p.5 */
504 HPQ = 0x80, /* Poll cmd on the high prio queue */
505 NPQ = 0x40, /* Poll cmd on the low prio queue */
506 FSWInt = 0x01, /* Forced software interrupt */
507
1da177e4 508 /* Cfg9346Bits */
07d3f51f
FR		 509 Cfg9346_Lock = 0x00,
510 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 511
512 /* rx_mode_bits */
07d3f51f
FR		 513 AcceptErr = 0x20,
514 AcceptRunt = 0x10,
515 AcceptBroadcast = 0x08,
516 AcceptMulticast = 0x04,
517 AcceptMyPhys = 0x02,
518 AcceptAllPhys = 0x01,
1687b566 519#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 520
1da177e4
LT		 521 /* TxConfigBits */
522 TxInterFrameGapShift = 24,
523 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
524
5d06a99f 525 /* Config1 register p.24 */
f162a5d1
FR		 526 LEDS1 = (1 << 7),
527 LEDS0 = (1 << 6),
f162a5d1
FR		 528 Speed_down = (1 << 4),
529 MEMMAP = (1 << 3),
530 IOMAP = (1 << 2),
531 VPD = (1 << 1),
5d06a99f
FR		 532 PMEnable = (1 << 0), /* Power Management Enable */
533
6dccd16b 534 /* Config2 register p. 25 */
57538c4a 535 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 536 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 537 PCI_Clock_66MHz = 0x01,
538 PCI_Clock_33MHz = 0x00,
539
61a4dcc2
FR		 540 /* Config3 register p.25 */
541 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
542 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 543 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 544 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 545 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 546
d58d46b5
FR		 547 /* Config4 register */
548 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
549
5d06a99f 550 /* Config5 register p.27 */
61a4dcc2
FR		 551 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
552 MWF = (1 << 5), /* Accept Multicast wakeup frame */
553 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 554 Spi_en = (1 << 3),
61a4dcc2 555 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 556 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 557 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 558
1da177e4
LT		 559 /* TBICSR p.28 */
560 TBIReset = 0x80000000,
561 TBILoopback = 0x40000000,
562 TBINwEnable = 0x20000000,
563 TBINwRestart = 0x10000000,
564 TBILinkOk = 0x02000000,
565 TBINwComplete = 0x01000000,
566
567 /* CPlusCmd p.31 */
f162a5d1
FR		 568 EnableBist = (1 << 15), // 8168 8101
569 Mac_dbgo_oe = (1 << 14), // 8168 8101
570 Normal_mode = (1 << 13), // unused
571 Force_half_dup = (1 << 12), // 8168 8101
572 Force_rxflow_en = (1 << 11), // 8168 8101
573 Force_txflow_en = (1 << 10), // 8168 8101
574 Cxpl_dbg_sel = (1 << 9), // 8168 8101
575 ASF = (1 << 8), // 8168 8101
576 PktCntrDisable = (1 << 7), // 8168 8101
577 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 578 RxVlan = (1 << 6),
579 RxChkSum = (1 << 5),
580 PCIDAC = (1 << 4),
581 PCIMulRW = (1 << 3),
9a3c81fa 582#define INTT_MASK GENMASK(1, 0)
0e485150
FR		 583 INTT_0 = 0x0000, // 8168
584 INTT_1 = 0x0001, // 8168
585 INTT_2 = 0x0002, // 8168
586 INTT_3 = 0x0003, // 8168
1da177e4
LT		 587
588 /* rtl8169_PHYstatus */
07d3f51f
FR		 589 TBI_Enable = 0x80,
590 TxFlowCtrl = 0x40,
591 RxFlowCtrl = 0x20,
592 _1000bpsF = 0x10,
593 _100bps = 0x08,
594 _10bps = 0x04,
595 LinkStatus = 0x02,
596 FullDup = 0x01,
1da177e4 597
1da177e4 598 /* _TBICSRBit */
07d3f51f 599 TBILinkOK = 0x02000000,
d4a3a0fc 600
6e85d5ad
CV		 601 /* ResetCounterCommand */
602 CounterReset = 0x1,
603
d4a3a0fc 604 /* DumpCounterCommand */
07d3f51f 605 CounterDump = 0x8,
6e1d0b89
CHL		 606
607 /* magic enable v2 */
608 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 609};
610
2b7b4318
FR		 611enum rtl_desc_bit {
612 /* First doubleword. */
1da177e4
LT		 613 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
614 RingEnd = (1 << 30), /* End of descriptor ring */
615 FirstFrag = (1 << 29), /* First segment of a packet */
616 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 617};
618
619/* Generic case. */
620enum rtl_tx_desc_bit {
621 /* First doubleword. */
622 TD_LSO = (1 << 27), /* Large Send Offload */
623#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 624
2b7b4318
FR		 625 /* Second doubleword. */
626 TxVlanTag = (1 << 17), /* Add VLAN tag */
627};
628
629/* 8169, 8168b and 810x except 8102e. */
630enum rtl_tx_desc_bit_0 {
631 /* First doubleword. */
632#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
633 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
634 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
635 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
636};
637
638/* 8102e, 8168c and beyond. */
639enum rtl_tx_desc_bit_1 {
bdfa4ed6 640 /* First doubleword. */
641 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 642 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 643#define GTTCPHO_SHIFT 18
e974604b 644#define GTTCPHO_MAX 0x7fU
bdfa4ed6 645
2b7b4318 646 /* Second doubleword. */
e974604b 647#define TCPHO_SHIFT 18
648#define TCPHO_MAX 0x3ffU
2b7b4318 649#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 650 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
651 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 652 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
653 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
654};
1da177e4 655
2b7b4318 656enum rtl_rx_desc_bit {
1da177e4
LT		 657 /* Rx private */
658 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 659 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 660
661#define RxProtoUDP (PID1)
662#define RxProtoTCP (PID0)
663#define RxProtoIP (PID1 | PID0)
664#define RxProtoMask RxProtoIP
665
666 IPFail = (1 << 16), /* IP checksum failed */
667 UDPFail = (1 << 15), /* UDP/IP checksum failed */
668 TCPFail = (1 << 14), /* TCP/IP checksum failed */
669 RxVlanTag = (1 << 16), /* VLAN tag available */
670};
671
672#define RsvdMask 0x3fffc000
12d42c50 673#define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
1da177e4
LT		 674
675struct TxDesc {
6cccd6e7
REB		 676 __le32 opts1;
677 __le32 opts2;
678 __le64 addr;
1da177e4
LT		 679};
680
681struct RxDesc {
6cccd6e7
REB		 682 __le32 opts1;
683 __le32 opts2;
684 __le64 addr;
1da177e4
LT		 685};
686
687struct ring_info {
688 struct sk_buff *skb;
689 u32 len;
690 u8 __pad[sizeof(void *) - sizeof(u32)];
691};
692
355423d0
IV		 693struct rtl8169_counters {
694 __le64 tx_packets;
695 __le64 rx_packets;
696 __le64 tx_errors;
697 __le32 rx_errors;
698 __le16 rx_missed;
699 __le16 align_errors;
700 __le32 tx_one_collision;
701 __le32 tx_multi_collision;
702 __le64 rx_unicast;
703 __le64 rx_broadcast;
704 __le32 rx_multicast;
705 __le16 tx_aborted;
706 __le16 tx_underun;
707};
708
6e85d5ad
CV		 709struct rtl8169_tc_offsets {
710 bool inited;
711 __le64 tx_errors;
712 __le32 tx_multi_collision;
6e85d5ad
CV		 713 __le16 tx_aborted;
714};
715
da78dbff 716enum rtl_flag {
6c4a70c5 717 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 718 RTL_FLAG_TASK_SLOW_PENDING,
719 RTL_FLAG_TASK_RESET_PENDING,
720 RTL_FLAG_TASK_PHY_PENDING,
721 RTL_FLAG_MAX
722};
723
8027aa24
JW		 724struct rtl8169_stats {
725 u64 packets;
726 u64 bytes;
727 struct u64_stats_sync syncp;
728};
729
1da177e4
LT		 730struct rtl8169_private {
731 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 732 struct pci_dev *pci_dev;
c4028958 733 struct net_device *dev;
bea3348e 734 struct napi_struct napi;
b57b7e5a 735 u32 msg_enable;
2b7b4318 736 u16 mac_version;
1da177e4
LT		 737 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
738 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 739 u32 dirty_tx;
8027aa24
JW		 740 struct rtl8169_stats rx_stats;
741 struct rtl8169_stats tx_stats;
1da177e4
LT		 742 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
743 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
744 dma_addr_t TxPhyAddr;
745 dma_addr_t RxPhyAddr;
6f0333b8 746 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 747 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 748 struct timer_list timer;
749 u16 cp_cmd;
da78dbff
FR		 750
751 u16 event_slow;
50970831 752 const struct rtl_coalesce_info *coalesce_info;
c0e45c1c 753
754 struct mdio_ops {
24192210
FR		 755 void (*write)(struct rtl8169_private *, int, int);
756 int (*read)(struct rtl8169_private *, int);
c0e45c1c 757 } mdio_ops;
758
d58d46b5
FR		 759 struct jumbo_ops {
760 void (*enable)(struct rtl8169_private *);
761 void (*disable)(struct rtl8169_private *);
762 } jumbo_ops;
763
54405cde 764 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
6fa1ba61
PR		 765 int (*get_link_ksettings)(struct net_device *,
766 struct ethtool_link_ksettings *);
4da19633 767 void (*phy_reset_enable)(struct rtl8169_private *tp);
61cb532d 768 void (*hw_start)(struct rtl8169_private *tp);
4da19633 769 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1ef7286e 770 unsigned int (*link_ok)(struct rtl8169_private *tp);
8b4ab28d 771 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
5888d3fc 772 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 773
774 struct {
da78dbff
FR		 775 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
776 struct mutex mutex;
4422bcd4
FR		 777 struct work_struct work;
778 } wk;
779
ccdffb9a 780 struct mii_if_info mii;
42020320
CV		 781 dma_addr_t counters_phys_addr;
782 struct rtl8169_counters *counters;
6e85d5ad 783 struct rtl8169_tc_offsets tc_offset;
e1759441 784 u32 saved_wolopts;
f1e02ed1 785
b6ffd97f
FR		 786 struct rtl_fw {
787 const struct firmware *fw;
1c361efb
FR		 788
789#define RTL_VER_SIZE 32
790
791 char version[RTL_VER_SIZE];
792
793 struct rtl_fw_phy_action {
794 __le32 *code;
795 size_t size;
796 } phy_action;
b6ffd97f 797 } *rtl_fw;
497888cf 798#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 799
800 u32 ocp_base;
1da177e4
LT		 801};
802
979b6c13 803MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 804MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 805module_param(use_dac, int, 0);
4300e8c7 806MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 807module_param_named(debug, debug.msg_enable, int, 0);
808MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 809MODULE_LICENSE("GPL");
810MODULE_VERSION(RTL8169_VERSION);
bca03d5f 811MODULE_FIRMWARE(FIRMWARE_8168D_1);
812MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 813MODULE_FIRMWARE(FIRMWARE_8168E_1);
814MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 815MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 816MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 817MODULE_FIRMWARE(FIRMWARE_8168F_1);
818MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 819MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 820MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 821MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 822MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 823MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 824MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 825MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 826MODULE_FIRMWARE(FIRMWARE_8168H_1);
827MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 828MODULE_FIRMWARE(FIRMWARE_8107E_1);
829MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 830
1e1205b7
HK		 831static inline struct device *tp_to_dev(struct rtl8169_private *tp)
832{
833 return &tp->pci_dev->dev;
834}
835
da78dbff
FR		 836static void rtl_lock_work(struct rtl8169_private *tp)
837{
838 mutex_lock(&tp->wk.mutex);
839}
840
841static void rtl_unlock_work(struct rtl8169_private *tp)
842{
843 mutex_unlock(&tp->wk.mutex);
844}
845
cb73200c 846static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
d58d46b5 847{
cb73200c 848 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
7d7903b2 849 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 850}
851
ffc46952
FR		 852struct rtl_cond {
853 bool (*check)(struct rtl8169_private *);
854 const char *msg;
855};
856
857static void rtl_udelay(unsigned int d)
858{
859 udelay(d);
860}
861
862static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
863 void (*delay)(unsigned int), unsigned int d, int n,
864 bool high)
865{
866 int i;
867
868 for (i = 0; i < n; i++) {
869 delay(d);
870 if (c->check(tp) == high)
871 return true;
872 }
82e316ef
FR		 873 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
874 c->msg, !high, n, d);
ffc46952
FR		 875 return false;
876}
877
878static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
879 const struct rtl_cond *c,
880 unsigned int d, int n)
881{
882 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
883}
884
885static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
886 const struct rtl_cond *c,
887 unsigned int d, int n)
888{
889 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
890}
891
892static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
893 const struct rtl_cond *c,
894 unsigned int d, int n)
895{
896 return rtl_loop_wait(tp, c, msleep, d, n, true);
897}
898
899static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
900 const struct rtl_cond *c,
901 unsigned int d, int n)
902{
903 return rtl_loop_wait(tp, c, msleep, d, n, false);
904}
905
906#define DECLARE_RTL_COND(name) \
907static bool name ## _check(struct rtl8169_private *); \
908 \
909static const struct rtl_cond name = { \
910 .check = name ## _check, \
911 .msg = #name \
912}; \
913 \
914static bool name ## _check(struct rtl8169_private *tp)
915
c558386b
HW		 916static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
917{
918 if (reg & 0xffff0001) {
919 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
920 return true;
921 }
922 return false;
923}
924
925DECLARE_RTL_COND(rtl_ocp_gphy_cond)
926{
1ef7286e 927 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
c558386b
HW		 928}
929
930static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
931{
c558386b
HW		 932 if (rtl_ocp_reg_failure(tp, reg))
933 return;
934
1ef7286e 935 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 936
937 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
938}
939
940static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
941{
c558386b
HW		 942 if (rtl_ocp_reg_failure(tp, reg))
943 return 0;
944
1ef7286e 945 RTL_W32(tp, GPHY_OCP, reg << 15);
c558386b
HW		 946
947 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1ef7286e 948 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
c558386b
HW		 949}
950
c558386b
HW		 951static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
952{
c558386b
HW		 953 if (rtl_ocp_reg_failure(tp, reg))
954 return;
955
1ef7286e 956 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 957}
958
959static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
960{
c558386b
HW		 961 if (rtl_ocp_reg_failure(tp, reg))
962 return 0;
963
1ef7286e 964 RTL_W32(tp, OCPDR, reg << 15);
c558386b 965
1ef7286e 966 return RTL_R32(tp, OCPDR);
c558386b
HW		 967}
968
969#define OCP_STD_PHY_BASE 0xa400
970
971static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
972{
973 if (reg == 0x1f) {
974 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
975 return;
976 }
977
978 if (tp->ocp_base != OCP_STD_PHY_BASE)
979 reg -= 0x10;
980
981 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
982}
983
984static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
985{
986 if (tp->ocp_base != OCP_STD_PHY_BASE)
987 reg -= 0x10;
988
989 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
990}
991
eee3786f 992static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
993{
994 if (reg == 0x1f) {
995 tp->ocp_base = value << 4;
996 return;
997 }
998
999 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1000}
1001
1002static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1003{
1004 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1005}
1006
ffc46952
FR		 1007DECLARE_RTL_COND(rtl_phyar_cond)
1008{
1ef7286e 1009 return RTL_R32(tp, PHYAR) & 0x80000000;
ffc46952
FR		 1010}
1011
24192210 1012static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1013{
1ef7286e 1014 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1015
ffc46952 1016 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1017 /*
81a95f04
TT		 1018 * According to hardware specs a 20us delay is required after write
1019 * complete indication, but before sending next command.
024a07ba 1020 */
81a95f04 1021 udelay(20);
1da177e4
LT		 1022}
1023
24192210 1024static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1025{
ffc46952 1026 int value;
1da177e4 1027
1ef7286e 1028 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1029
ffc46952 1030 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1ef7286e 1031 RTL_R32(tp, PHYAR) & 0xffff : ~0;
ffc46952 1032
81a95f04
TT		 1033 /*
1034 * According to hardware specs a 20us delay is required after read
1035 * complete indication, but before sending next command.
1036 */
1037 udelay(20);
1038
1da177e4
LT		 1039 return value;
1040}
1041
935e2218
CHL		 1042DECLARE_RTL_COND(rtl_ocpar_cond)
1043{
1ef7286e 1044 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
935e2218
CHL		 1045}
1046
24192210 1047static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1048{
1ef7286e
AS		 1049 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1050 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
1051 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 1052
ffc46952 1053 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1054}
1055
24192210 1056static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1057{
24192210
FR		 1058 r8168dp_1_mdio_access(tp, reg,
1059 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1060}
1061
24192210 1062static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1063{
24192210 1064 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1065
1066 mdelay(1);
1ef7286e
AS		 1067 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1068 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 1069
ffc46952 1070 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1ef7286e 1071 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1072}
1073
e6de30d6 1074#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1075
1ef7286e 1076static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
e6de30d6 1077{
1ef7286e 1078 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1079}
1080
1ef7286e 1081static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
e6de30d6 1082{
1ef7286e 1083 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1084}
1085
24192210 1086static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1087{
1ef7286e 1088 r8168dp_2_mdio_start(tp);
e6de30d6 1089
24192210 1090 r8169_mdio_write(tp, reg, value);
e6de30d6 1091
1ef7286e 1092 r8168dp_2_mdio_stop(tp);
e6de30d6 1093}
1094
24192210 1095static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1096{
1097 int value;
1098
1ef7286e 1099 r8168dp_2_mdio_start(tp);
e6de30d6 1100
24192210 1101 value = r8169_mdio_read(tp, reg);
e6de30d6 1102
1ef7286e 1103 r8168dp_2_mdio_stop(tp);
e6de30d6 1104
1105 return value;
1106}
1107
4da19633 1108static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1109{
24192210 1110 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1111}
1112
4da19633 1113static int rtl_readphy(struct rtl8169_private *tp, int location)
1114{
24192210 1115 return tp->mdio_ops.read(tp, location);
4da19633 1116}
1117
1118static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1119{
1120 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1121}
1122
76564428 1123static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1124{
1125 int val;
1126
4da19633 1127 val = rtl_readphy(tp, reg_addr);
76564428 1128 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1129}
1130
ccdffb9a
FR		 1131static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1132 int val)
1133{
1134 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1135
4da19633 1136 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1137}
1138
1139static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1140{
1141 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1142
4da19633 1143 return rtl_readphy(tp, location);
ccdffb9a
FR		 1144}
1145
ffc46952
FR		 1146DECLARE_RTL_COND(rtl_ephyar_cond)
1147{
1ef7286e 1148 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
ffc46952
FR		 1149}
1150
fdf6fc06 1151static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1152{
1ef7286e 1153 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
dacf8154
FR		 1154 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1155
ffc46952
FR		 1156 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1157
1158 udelay(10);
dacf8154
FR		 1159}
1160
fdf6fc06 1161static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1162{
1ef7286e 1163 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
dacf8154 1164
ffc46952 1165 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1ef7286e 1166 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1167}
1168
935e2218
CHL		 1169DECLARE_RTL_COND(rtl_eriar_cond)
1170{
1ef7286e 1171 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
935e2218
CHL		 1172}
1173
fdf6fc06
FR		 1174static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1175 u32 val, int type)
133ac40a 1176{
133ac40a 1177 BUG_ON((addr & 3) || (mask == 0));
1ef7286e
AS		 1178 RTL_W32(tp, ERIDR, val);
1179 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
133ac40a 1180
ffc46952 1181 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1182}
1183
fdf6fc06 1184static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1185{
1ef7286e 1186 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
133ac40a 1187
ffc46952 1188 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1ef7286e 1189 RTL_R32(tp, ERIDR) : ~0;
133ac40a
HW		 1190}
1191
706123d0 1192static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1193 u32 m, int type)
133ac40a
HW		 1194{
1195 u32 val;
1196
fdf6fc06
FR		 1197 val = rtl_eri_read(tp, addr, type);
1198 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1199}
1200
935e2218
CHL		 1201static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1202{
1ef7286e 1203 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218 1204 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1ef7286e 1205 RTL_R32(tp, OCPDR) : ~0;
935e2218
CHL		 1206}
1207
1208static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1209{
1210 return rtl_eri_read(tp, reg, ERIAR_OOB);
1211}
1212
1213static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1214{
1215 switch (tp->mac_version) {
1216 case RTL_GIGA_MAC_VER_27:
1217 case RTL_GIGA_MAC_VER_28:
1218 case RTL_GIGA_MAC_VER_31:
1219 return r8168dp_ocp_read(tp, mask, reg);
1220 case RTL_GIGA_MAC_VER_49:
1221 case RTL_GIGA_MAC_VER_50:
1222 case RTL_GIGA_MAC_VER_51:
1223 return r8168ep_ocp_read(tp, mask, reg);
1224 default:
1225 BUG();
1226 return ~0;
1227 }
1228}
1229
1230static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1231 u32 data)
1232{
1ef7286e
AS		 1233 RTL_W32(tp, OCPDR, data);
1234 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218
CHL		 1235 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1236}
1237
1238static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1239 u32 data)
1240{
1241 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1242 data, ERIAR_OOB);
1243}
1244
1245static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1246{
1247 switch (tp->mac_version) {
1248 case RTL_GIGA_MAC_VER_27:
1249 case RTL_GIGA_MAC_VER_28:
1250 case RTL_GIGA_MAC_VER_31:
1251 r8168dp_ocp_write(tp, mask, reg, data);
1252 break;
1253 case RTL_GIGA_MAC_VER_49:
1254 case RTL_GIGA_MAC_VER_50:
1255 case RTL_GIGA_MAC_VER_51:
1256 r8168ep_ocp_write(tp, mask, reg, data);
1257 break;
1258 default:
1259 BUG();
1260 break;
1261 }
1262}
1263
2a9b4d96
CHL		 1264static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1265{
1266 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1267
1268 ocp_write(tp, 0x1, 0x30, 0x00000001);
1269}
1270
1271#define OOB_CMD_RESET 0x00
1272#define OOB_CMD_DRIVER_START 0x05
1273#define OOB_CMD_DRIVER_STOP 0x06
1274
1275static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1276{
1277 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1278}
1279
1280DECLARE_RTL_COND(rtl_ocp_read_cond)
1281{
1282 u16 reg;
1283
1284 reg = rtl8168_get_ocp_reg(tp);
1285
1286 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1287}
1288
935e2218 1289DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1290{
935e2218
CHL		 1291 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1292}
1293
1294DECLARE_RTL_COND(rtl_ocp_tx_cond)
1295{
1ef7286e 1296 return RTL_R8(tp, IBISR0) & 0x20;
935e2218 1297}
2a9b4d96 1298
003609da
CHL		 1299static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1300{
1ef7286e 1301 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
086ca23d 1302 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1ef7286e
AS		 1303 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1304 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
003609da
CHL		 1305}
1306
935e2218
CHL		 1307static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1308{
1309 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
2a9b4d96
CHL		 1310 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1311}
1312
935e2218 1313static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1314{
935e2218
CHL		 1315 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1316 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1317 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1318}
1319
1320static void rtl8168_driver_start(struct rtl8169_private *tp)
1321{
1322 switch (tp->mac_version) {
1323 case RTL_GIGA_MAC_VER_27:
1324 case RTL_GIGA_MAC_VER_28:
1325 case RTL_GIGA_MAC_VER_31:
1326 rtl8168dp_driver_start(tp);
1327 break;
1328 case RTL_GIGA_MAC_VER_49:
1329 case RTL_GIGA_MAC_VER_50:
1330 case RTL_GIGA_MAC_VER_51:
1331 rtl8168ep_driver_start(tp);
1332 break;
1333 default:
1334 BUG();
1335 break;
1336 }
1337}
2a9b4d96 1338
935e2218
CHL		 1339static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1340{
1341 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
2a9b4d96
CHL		 1342 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1343}
1344
935e2218
CHL		 1345static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1346{
003609da 1347 rtl8168ep_stop_cmac(tp);
935e2218
CHL		 1348 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1349 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1350 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1351}
1352
1353static void rtl8168_driver_stop(struct rtl8169_private *tp)
1354{
1355 switch (tp->mac_version) {
1356 case RTL_GIGA_MAC_VER_27:
1357 case RTL_GIGA_MAC_VER_28:
1358 case RTL_GIGA_MAC_VER_31:
1359 rtl8168dp_driver_stop(tp);
1360 break;
1361 case RTL_GIGA_MAC_VER_49:
1362 case RTL_GIGA_MAC_VER_50:
1363 case RTL_GIGA_MAC_VER_51:
1364 rtl8168ep_driver_stop(tp);
1365 break;
1366 default:
1367 BUG();
1368 break;
1369 }
1370}
1371
9dbe7896 1372static bool r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1373{
1374 u16 reg = rtl8168_get_ocp_reg(tp);
1375
9dbe7896 1376 return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
2a9b4d96
CHL		 1377}
1378
9dbe7896 1379static bool r8168ep_check_dash(struct rtl8169_private *tp)
935e2218 1380{
9dbe7896 1381 return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
935e2218
CHL		 1382}
1383
9dbe7896 1384static bool r8168_check_dash(struct rtl8169_private *tp)
935e2218
CHL		 1385{
1386 switch (tp->mac_version) {
1387 case RTL_GIGA_MAC_VER_27:
1388 case RTL_GIGA_MAC_VER_28:
1389 case RTL_GIGA_MAC_VER_31:
1390 return r8168dp_check_dash(tp);
1391 case RTL_GIGA_MAC_VER_49:
1392 case RTL_GIGA_MAC_VER_50:
1393 case RTL_GIGA_MAC_VER_51:
1394 return r8168ep_check_dash(tp);
1395 default:
9dbe7896 1396 return false;
935e2218
CHL		 1397 }
1398}
1399
c28aa385 1400struct exgmac_reg {
1401 u16 addr;
1402 u16 mask;
1403 u32 val;
1404};
1405
fdf6fc06 1406static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1407 const struct exgmac_reg *r, int len)
1408{
1409 while (len-- > 0) {
fdf6fc06 1410 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1411 r++;
1412 }
1413}
1414
ffc46952
FR		 1415DECLARE_RTL_COND(rtl_efusear_cond)
1416{
1ef7286e 1417 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
ffc46952
FR		 1418}
1419
fdf6fc06 1420static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1421{
1ef7286e 1422 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
daf9df6d 1423
ffc46952 1424 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1ef7286e 1425 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1426}
1427
9085cdfa
FR		 1428static u16 rtl_get_events(struct rtl8169_private *tp)
1429{
1ef7286e 1430 return RTL_R16(tp, IntrStatus);
9085cdfa
FR		 1431}
1432
1433static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1434{
1ef7286e 1435 RTL_W16(tp, IntrStatus, bits);
9085cdfa
FR		 1436 mmiowb();
1437}
1438
1439static void rtl_irq_disable(struct rtl8169_private *tp)
1440{
1ef7286e 1441 RTL_W16(tp, IntrMask, 0);
9085cdfa
FR		 1442 mmiowb();
1443}
1444
3e990ff5
FR		 1445static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1446{
1ef7286e 1447 RTL_W16(tp, IntrMask, bits);
3e990ff5
FR		 1448}
1449
da78dbff
FR		 1450#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1451#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1452#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1453
1454static void rtl_irq_enable_all(struct rtl8169_private *tp)
1455{
1456 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1457}
1458
811fd301 1459static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1460{
9085cdfa 1461 rtl_irq_disable(tp);
da78dbff 1462 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1ef7286e 1463 RTL_R8(tp, ChipCmd);
1da177e4
LT		 1464}
1465
4da19633 1466static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1467{
1ef7286e 1468 return RTL_R32(tp, TBICSR) & TBIReset;
1da177e4
LT		 1469}
1470
4da19633 1471static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1472{
4da19633 1473 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1474}
1475
1ef7286e 1476static unsigned int rtl8169_tbi_link_ok(struct rtl8169_private *tp)
1da177e4 1477{
1ef7286e 1478 return RTL_R32(tp, TBICSR) & TBILinkOk;
1da177e4
LT		 1479}
1480
1ef7286e 1481static unsigned int rtl8169_xmii_link_ok(struct rtl8169_private *tp)
1da177e4 1482{
1ef7286e 1483 return RTL_R8(tp, PHYstatus) & LinkStatus;
1da177e4
LT		 1484}
1485
4da19633 1486static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1487{
1ef7286e 1488 RTL_W32(tp, TBICSR, RTL_R32(tp, TBICSR) | TBIReset);
1da177e4
LT		 1489}
1490
4da19633 1491static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1492{
1493 unsigned int val;
1494
4da19633 1495 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1496 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1497}
1498
70090424
HW		 1499static void rtl_link_chg_patch(struct rtl8169_private *tp)
1500{
70090424
HW		 1501 struct net_device *dev = tp->dev;
1502
1503 if (!netif_running(dev))
1504 return;
1505
b3d7b2f2
HW		 1506 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1507 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1ef7286e 1508 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1509 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1510 ERIAR_EXGMAC);
1511 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1512 ERIAR_EXGMAC);
1ef7286e 1513 } else if (RTL_R8(tp, PHYstatus) & _100bps) {
fdf6fc06
FR		 1514 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1515 ERIAR_EXGMAC);
1516 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1517 ERIAR_EXGMAC);
70090424 1518 } else {
fdf6fc06
FR		 1519 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1520 ERIAR_EXGMAC);
1521 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1522 ERIAR_EXGMAC);
70090424
HW		 1523 }
1524 /* Reset packet filter */
706123d0 1525 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1526 ERIAR_EXGMAC);
706123d0 1527 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1528 ERIAR_EXGMAC);
c2218925
HW		 1529 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1530 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1ef7286e 1531 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1532 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1533 ERIAR_EXGMAC);
1534 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1535 ERIAR_EXGMAC);
c2218925 1536 } else {
fdf6fc06
FR		 1537 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1538 ERIAR_EXGMAC);
1539 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1540 ERIAR_EXGMAC);
c2218925 1541 }
7e18dca1 1542 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1ef7286e 1543 if (RTL_R8(tp, PHYstatus) & _10bps) {
fdf6fc06
FR		 1544 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1545 ERIAR_EXGMAC);
1546 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1547 ERIAR_EXGMAC);
7e18dca1 1548 } else {
fdf6fc06
FR		 1549 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1550 ERIAR_EXGMAC);
7e18dca1 1551 }
70090424
HW		 1552 }
1553}
1554
ef4d5fcc 1555static void rtl8169_check_link_status(struct net_device *dev,
1ef7286e 1556 struct rtl8169_private *tp)
1da177e4 1557{
1e1205b7
HK		 1558 struct device *d = tp_to_dev(tp);
1559
1ef7286e 1560 if (tp->link_ok(tp)) {
70090424 1561 rtl_link_chg_patch(tp);
e1759441 1562 /* This is to cancel a scheduled suspend if there's one. */
1e1205b7 1563 pm_request_resume(d);
1da177e4 1564 netif_carrier_on(dev);
1519e57f
FR		 1565 if (net_ratelimit())
1566 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1567 } else {
1da177e4 1568 netif_carrier_off(dev);
bf82c189 1569 netif_info(tp, ifdown, dev, "link down\n");
1e1205b7 1570 pm_runtime_idle(d);
b57b7e5a 1571 }
1da177e4
LT		 1572}
1573
e1759441
RW		 1574#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1575
433f9d0d
HK		 1576/* Currently we only enable WoL if explicitly told by userspace to circumvent
1577 * issues on certain platforms, see commit bde135a672bf ("r8169: only enable
1578 * PCI wakeups when WOL is active"). Let's keep __rtl8169_get_wol() for the
1579 * case that we want to respect BIOS settings again.
1580 */
1581#if 0
e1759441 1582static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1583{
61a4dcc2 1584 u8 options;
e1759441 1585 u32 wolopts = 0;
61a4dcc2 1586
1ef7286e 1587 options = RTL_R8(tp, Config1);
61a4dcc2 1588 if (!(options & PMEnable))
e1759441 1589 return 0;
61a4dcc2 1590
1ef7286e 1591 options = RTL_R8(tp, Config3);
61a4dcc2 1592 if (options & LinkUp)
e1759441 1593 wolopts |= WAKE_PHY;
6e1d0b89 1594 switch (tp->mac_version) {
2a71883c
HK		 1595 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1596 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1597 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1598 wolopts |= WAKE_MAGIC;
1599 break;
1600 default:
1601 if (options & MagicPacket)
1602 wolopts |= WAKE_MAGIC;
1603 break;
1604 }
61a4dcc2 1605
1ef7286e 1606 options = RTL_R8(tp, Config5);
61a4dcc2 1607 if (options & UWF)
e1759441 1608 wolopts |= WAKE_UCAST;
61a4dcc2 1609 if (options & BWF)
e1759441 1610 wolopts |= WAKE_BCAST;
61a4dcc2 1611 if (options & MWF)
e1759441 1612 wolopts |= WAKE_MCAST;
61a4dcc2 1613
e1759441 1614 return wolopts;
61a4dcc2 1615}
433f9d0d 1616#endif
61a4dcc2 1617
e1759441 1618static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1619{
1620 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1621
da78dbff 1622 rtl_lock_work(tp);
e1759441 1623 wol->supported = WAKE_ANY;
433f9d0d 1624 wol->wolopts = tp->saved_wolopts;
da78dbff 1625 rtl_unlock_work(tp);
e1759441
RW		 1626}
1627
1628static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1629{
6e1d0b89 1630 unsigned int i, tmp;
350f7596 1631 static const struct {
61a4dcc2
FR		 1632 u32 opt;
1633 u16 reg;
1634 u8 mask;
1635 } cfg[] = {
61a4dcc2 1636 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1637 { WAKE_UCAST, Config5, UWF },
1638 { WAKE_BCAST, Config5, BWF },
1639 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1640 { WAKE_ANY, Config5, LanWake },
1641 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1642 };
851e6022 1643 u8 options;
61a4dcc2 1644
1ef7286e 1645 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
61a4dcc2 1646
6e1d0b89 1647 switch (tp->mac_version) {
2a71883c
HK		 1648 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1649 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1650 tmp = ARRAY_SIZE(cfg) - 1;
1651 if (wolopts & WAKE_MAGIC)
706123d0 1652 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1653 0x0dc,
1654 ERIAR_MASK_0100,
1655 MagicPacket_v2,
1656 0x0000,
1657 ERIAR_EXGMAC);
1658 else
706123d0 1659 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1660 0x0dc,
1661 ERIAR_MASK_0100,
1662 0x0000,
1663 MagicPacket_v2,
1664 ERIAR_EXGMAC);
1665 break;
1666 default:
1667 tmp = ARRAY_SIZE(cfg);
1668 break;
1669 }
1670
1671 for (i = 0; i < tmp; i++) {
1ef7286e 1672 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
e1759441 1673 if (wolopts & cfg[i].opt)
61a4dcc2 1674 options |= cfg[i].mask;
1ef7286e 1675 RTL_W8(tp, cfg[i].reg, options);
61a4dcc2
FR		 1676 }
1677
851e6022
FR		 1678 switch (tp->mac_version) {
1679 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1ef7286e 1680 options = RTL_R8(tp, Config1) & ~PMEnable;
851e6022
FR		 1681 if (wolopts)
1682 options |= PMEnable;
1ef7286e 1683 RTL_W8(tp, Config1, options);
851e6022
FR		 1684 break;
1685 default:
1ef7286e 1686 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
d387b427
FR		 1687 if (wolopts)
1688 options |= PME_SIGNAL;
1ef7286e 1689 RTL_W8(tp, Config2, options);
851e6022
FR		 1690 break;
1691 }
1692
1ef7286e 1693 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
e1759441
RW		 1694}
1695
1696static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1697{
1698 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1699 struct device *d = tp_to_dev(tp);
5fa80a32 1700
2f533f6b
HK		 1701 if (wol->wolopts & ~WAKE_ANY)
1702 return -EINVAL;
1703
5fa80a32 1704 pm_runtime_get_noresume(d);
e1759441 1705
da78dbff 1706 rtl_lock_work(tp);
61a4dcc2 1707
2f533f6b 1708 tp->saved_wolopts = wol->wolopts;
433f9d0d 1709
5fa80a32 1710 if (pm_runtime_active(d))
433f9d0d 1711 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff
FR		 1712
1713 rtl_unlock_work(tp);
61a4dcc2 1714
433f9d0d 1715 device_set_wakeup_enable(d, tp->saved_wolopts);
ea80907f 1716
5fa80a32
CHL		 1717 pm_runtime_put_noidle(d);
1718
61a4dcc2
FR		 1719 return 0;
1720}
1721
31bd204f
FR		 1722static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1723{
85bffe6c 1724 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1725}
1726
1da177e4
LT		 1727static void rtl8169_get_drvinfo(struct net_device *dev,
1728 struct ethtool_drvinfo *info)
1729{
1730 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1731 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1732
68aad78c
RJ		 1733 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1734 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1735 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1736 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1737 if (!IS_ERR_OR_NULL(rtl_fw))
1738 strlcpy(info->fw_version, rtl_fw->version,
1739 sizeof(info->fw_version));
1da177e4
LT		 1740}
1741
1742static int rtl8169_get_regs_len(struct net_device *dev)
1743{
1744 return R8169_REGS_SIZE;
1745}
1746
1747static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1748 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1749{
1750 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1751 int ret = 0;
1752 u32 reg;
1753
1ef7286e 1754 reg = RTL_R32(tp, TBICSR);
1da177e4
LT		 1755 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1756 (duplex == DUPLEX_FULL)) {
1ef7286e 1757 RTL_W32(tp, TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1da177e4 1758 } else if (autoneg == AUTONEG_ENABLE)
1ef7286e 1759 RTL_W32(tp, TBICSR, reg | TBINwEnable | TBINwRestart);
1da177e4 1760 else {
bf82c189
JP		 1761 netif_warn(tp, link, dev,
1762 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1763 ret = -EOPNOTSUPP;
1764 }
1765
1766 return ret;
1767}
1768
1769static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1770 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1771{
1772 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1773 int giga_ctrl, bmcr;
54405cde 1774 int rc = -EINVAL;
1da177e4 1775
716b50a3 1776 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1777
1778 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1779 int auto_nego;
1780
4da19633 1781 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1782 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1783 ADVERTISE_100HALF | ADVERTISE_100FULL);
1784
1785 if (adv & ADVERTISED_10baseT_Half)
1786 auto_nego |= ADVERTISE_10HALF;
1787 if (adv & ADVERTISED_10baseT_Full)
1788 auto_nego |= ADVERTISE_10FULL;
1789 if (adv & ADVERTISED_100baseT_Half)
1790 auto_nego |= ADVERTISE_100HALF;
1791 if (adv & ADVERTISED_100baseT_Full)
1792 auto_nego |= ADVERTISE_100FULL;
1793
3577aa1b 1794 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1795
4da19633 1796 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1797 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1798
3577aa1b 1799 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1800 if (tp->mii.supports_gmii) {
54405cde
ON		 1801 if (adv & ADVERTISED_1000baseT_Half)
1802 giga_ctrl |= ADVERTISE_1000HALF;
1803 if (adv & ADVERTISED_1000baseT_Full)
1804 giga_ctrl |= ADVERTISE_1000FULL;
1805 } else if (adv & (ADVERTISED_1000baseT_Half |
1806 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1807 netif_info(tp, link, dev,
1808 "PHY does not support 1000Mbps\n");
54405cde 1809 goto out;
bcf0bf90 1810 }
1da177e4 1811
3577aa1b 1812 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1813
4da19633 1814 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1815 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1816 } else {
3577aa1b 1817 if (speed == SPEED_10)
1818 bmcr = 0;
1819 else if (speed == SPEED_100)
1820 bmcr = BMCR_SPEED100;
1821 else
54405cde 1822 goto out;
3577aa1b 1823
1824 if (duplex == DUPLEX_FULL)
1825 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1826 }
1827
4da19633 1828 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1829
cecb5fd7
FR		 1830 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1831 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1832 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1833 rtl_writephy(tp, 0x17, 0x2138);
1834 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1835 } else {
4da19633 1836 rtl_writephy(tp, 0x17, 0x2108);
1837 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1838 }
1839 }
1840
54405cde
ON		 1841 rc = 0;
1842out:
1843 return rc;
1da177e4
LT		 1844}
1845
1846static int rtl8169_set_speed(struct net_device *dev,
54405cde 1847 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1848{
1849 struct rtl8169_private *tp = netdev_priv(dev);
1850 int ret;
1851
54405cde 1852 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1853 if (ret < 0)
1854 goto out;
1da177e4 1855
4876cc1e 1856 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
c4556975
CHL		 1857 (advertising & ADVERTISED_1000baseT_Full) &&
1858 !pci_is_pcie(tp->pci_dev)) {
1da177e4 1859 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1860 }
1861out:
1da177e4
LT		 1862 return ret;
1863}
1864
c8f44aff
MM		 1865static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1866 netdev_features_t features)
1da177e4 1867{
d58d46b5
FR		 1868 struct rtl8169_private *tp = netdev_priv(dev);
1869
2b7b4318 1870 if (dev->mtu > TD_MSS_MAX)
350fb32a 1871 features &= ~NETIF_F_ALL_TSO;
1da177e4 1872
d58d46b5 1873 if (dev->mtu > JUMBO_1K &&
6ed0e08f 1874 tp->mac_version > RTL_GIGA_MAC_VER_06)
d58d46b5
FR		 1875 features &= ~NETIF_F_IP_CSUM;
1876
350fb32a 1877 return features;
1da177e4
LT		 1878}
1879
a3984578
HK		 1880static int rtl8169_set_features(struct net_device *dev,
1881 netdev_features_t features)
1da177e4
LT		 1882{
1883 struct rtl8169_private *tp = netdev_priv(dev);
929a031d 1884 u32 rx_config;
1da177e4 1885
a3984578
HK		 1886 rtl_lock_work(tp);
1887
1ef7286e 1888 rx_config = RTL_R32(tp, RxConfig);
929a031d 1889 if (features & NETIF_F_RXALL)
1890 rx_config |= (AcceptErr | AcceptRunt);
1891 else
1892 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 1893
1ef7286e 1894 RTL_W32(tp, RxConfig, rx_config);
350fb32a 1895
929a031d 1896 if (features & NETIF_F_RXCSUM)
1897 tp->cp_cmd |= RxChkSum;
1898 else
1899 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1900
929a031d 1901 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1902 tp->cp_cmd |= RxVlan;
1903 else
1904 tp->cp_cmd &= ~RxVlan;
1905
1ef7286e
AS		 1906 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1907 RTL_R16(tp, CPlusCmd);
1da177e4 1908
da78dbff 1909 rtl_unlock_work(tp);
1da177e4
LT		 1910
1911 return 0;
1912}
1913
810f4893 1914static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1915{
df8a39de
JP		 1916 return (skb_vlan_tag_present(skb)) ?
1917 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 1918}
1919
7a8fc77b 1920static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1921{
1922 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1923
7a8fc77b 1924 if (opts2 & RxVlanTag)
86a9bad3 1925 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1926}
1927
6fa1ba61
PR		 1928static int rtl8169_get_link_ksettings_tbi(struct net_device *dev,
1929 struct ethtool_link_ksettings *cmd)
1da177e4
LT		 1930{
1931 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1932 u32 status;
6fa1ba61 1933 u32 supported, advertising;
1da177e4 1934
6fa1ba61 1935 supported =
1da177e4 1936 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
6fa1ba61 1937 cmd->base.port = PORT_FIBRE;
1da177e4 1938
1ef7286e 1939 status = RTL_R32(tp, TBICSR);
6fa1ba61
PR		 1940 advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1941 cmd->base.autoneg = !!(status & TBINwEnable);
1da177e4 1942
6fa1ba61
PR		 1943 cmd->base.speed = SPEED_1000;
1944 cmd->base.duplex = DUPLEX_FULL; /* Always set */
1945
1946 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1947 supported);
1948 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1949 advertising);
ccdffb9a
FR		 1950
1951 return 0;
1da177e4
LT		 1952}
1953
6fa1ba61
PR		 1954static int rtl8169_get_link_ksettings_xmii(struct net_device *dev,
1955 struct ethtool_link_ksettings *cmd)
1da177e4
LT		 1956{
1957 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1958
82c01a84 1959 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
1960
1961 return 0;
1da177e4
LT		 1962}
1963
6fa1ba61
PR		 1964static int rtl8169_get_link_ksettings(struct net_device *dev,
1965 struct ethtool_link_ksettings *cmd)
1da177e4
LT		 1966{
1967 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1968 int rc;
1da177e4 1969
da78dbff 1970 rtl_lock_work(tp);
6fa1ba61 1971 rc = tp->get_link_ksettings(dev, cmd);
da78dbff 1972 rtl_unlock_work(tp);
1da177e4 1973
ccdffb9a 1974 return rc;
1da177e4
LT		 1975}
1976
9e77d7a5
TJ		 1977static int rtl8169_set_link_ksettings(struct net_device *dev,
1978 const struct ethtool_link_ksettings *cmd)
1979{
1980 struct rtl8169_private *tp = netdev_priv(dev);
1981 int rc;
1982 u32 advertising;
1983
1984 if (!ethtool_convert_link_mode_to_legacy_u32(&advertising,
1985 cmd->link_modes.advertising))
1986 return -EINVAL;
1987
1988 del_timer_sync(&tp->timer);
1989
1990 rtl_lock_work(tp);
1991 rc = rtl8169_set_speed(dev, cmd->base.autoneg, cmd->base.speed,
1992 cmd->base.duplex, advertising);
1993 rtl_unlock_work(tp);
1994
1995 return rc;
1996}
1997
1da177e4
LT		 1998static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1999 void *p)
2000{
5b0384f4 2001 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 2002 u32 __iomem *data = tp->mmio_addr;
2003 u32 *dw = p;
2004 int i;
1da177e4 2005
da78dbff 2006 rtl_lock_work(tp);
15edae91
PW		 2007 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2008 memcpy_fromio(dw++, data++, 4);
da78dbff 2009 rtl_unlock_work(tp);
1da177e4
LT		 2010}
2011
b57b7e5a
SH		 2012static u32 rtl8169_get_msglevel(struct net_device *dev)
2013{
2014 struct rtl8169_private *tp = netdev_priv(dev);
2015
2016 return tp->msg_enable;
2017}
2018
2019static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2020{
2021 struct rtl8169_private *tp = netdev_priv(dev);
2022
2023 tp->msg_enable = value;
2024}
2025
d4a3a0fc
SH		 2026static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2027 "tx_packets",
2028 "rx_packets",
2029 "tx_errors",
2030 "rx_errors",
2031 "rx_missed",
2032 "align_errors",
2033 "tx_single_collisions",
2034 "tx_multi_collisions",
2035 "unicast",
2036 "broadcast",
2037 "multicast",
2038 "tx_aborted",
2039 "tx_underrun",
2040};
2041
b9f2c044 2042static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 2043{
b9f2c044
JG		 2044 switch (sset) {
2045 case ETH_SS_STATS:
2046 return ARRAY_SIZE(rtl8169_gstrings);
2047 default:
2048 return -EOPNOTSUPP;
2049 }
d4a3a0fc
SH		 2050}
2051
42020320 2052DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 2053{
1ef7286e 2054 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 2055}
2056
e71c9ce2 2057static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
6e85d5ad 2058{
42020320
CV		 2059 dma_addr_t paddr = tp->counters_phys_addr;
2060 u32 cmd;
6e85d5ad 2061
1ef7286e
AS		 2062 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
2063 RTL_R32(tp, CounterAddrHigh);
42020320 2064 cmd = (u64)paddr & DMA_BIT_MASK(32);
1ef7286e
AS		 2065 RTL_W32(tp, CounterAddrLow, cmd);
2066 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
6e85d5ad 2067
a78e9366 2068 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 2069}
2070
e71c9ce2 2071static bool rtl8169_reset_counters(struct rtl8169_private *tp)
6e85d5ad 2072{
6e85d5ad
CV		 2073 /*
2074 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2075 * tally counters.
2076 */
2077 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2078 return true;
2079
e71c9ce2 2080 return rtl8169_do_counters(tp, CounterReset);
ffc46952
FR		 2081}
2082
e71c9ce2 2083static bool rtl8169_update_counters(struct rtl8169_private *tp)
d4a3a0fc 2084{
355423d0
IV		 2085 /*
2086 * Some chips are unable to dump tally counters when the receiver
2087 * is disabled.
2088 */
1ef7286e 2089 if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
6e85d5ad 2090 return true;
d4a3a0fc 2091
e71c9ce2 2092 return rtl8169_do_counters(tp, CounterDump);
6e85d5ad
CV		 2093}
2094
e71c9ce2 2095static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
6e85d5ad 2096{
42020320 2097 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 2098 bool ret = false;
2099
2100 /*
2101 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2102 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2103 * reset by a power cycle, while the counter values collected by the
2104 * driver are reset at every driver unload/load cycle.
2105 *
2106 * To make sure the HW values returned by @get_stats64 match the SW
2107 * values, we collect the initial values at first open(*) and use them
2108 * as offsets to normalize the values returned by @get_stats64.
2109 *
2110 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2111 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2112 * set at open time by rtl_hw_start.
2113 */
2114
2115 if (tp->tc_offset.inited)
2116 return true;
2117
2118 /* If both, reset and update fail, propagate to caller. */
e71c9ce2 2119 if (rtl8169_reset_counters(tp))
6e85d5ad
CV		 2120 ret = true;
2121
e71c9ce2 2122 if (rtl8169_update_counters(tp))
6e85d5ad
CV		 2123 ret = true;
2124
42020320
CV		 2125 tp->tc_offset.tx_errors = counters->tx_errors;
2126 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2127 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 2128 tp->tc_offset.inited = true;
2129
2130 return ret;
d4a3a0fc
SH		 2131}
2132
355423d0
IV		 2133static void rtl8169_get_ethtool_stats(struct net_device *dev,
2134 struct ethtool_stats *stats, u64 *data)
2135{
2136 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 2137 struct device *d = tp_to_dev(tp);
42020320 2138 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 2139
2140 ASSERT_RTNL();
2141
e0636236
CHL		 2142 pm_runtime_get_noresume(d);
2143
2144 if (pm_runtime_active(d))
e71c9ce2 2145 rtl8169_update_counters(tp);
e0636236
CHL		 2146
2147 pm_runtime_put_noidle(d);
355423d0 2148
42020320
CV		 2149 data[0] = le64_to_cpu(counters->tx_packets);
2150 data[1] = le64_to_cpu(counters->rx_packets);
2151 data[2] = le64_to_cpu(counters->tx_errors);
2152 data[3] = le32_to_cpu(counters->rx_errors);
2153 data[4] = le16_to_cpu(counters->rx_missed);
2154 data[5] = le16_to_cpu(counters->align_errors);
2155 data[6] = le32_to_cpu(counters->tx_one_collision);
2156 data[7] = le32_to_cpu(counters->tx_multi_collision);
2157 data[8] = le64_to_cpu(counters->rx_unicast);
2158 data[9] = le64_to_cpu(counters->rx_broadcast);
2159 data[10] = le32_to_cpu(counters->rx_multicast);
2160 data[11] = le16_to_cpu(counters->tx_aborted);
2161 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 2162}
2163
d4a3a0fc
SH		 2164static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2165{
2166 switch(stringset) {
2167 case ETH_SS_STATS:
2168 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2169 break;
2170 }
2171}
2172
f0903ea3
FF		 2173static int rtl8169_nway_reset(struct net_device *dev)
2174{
2175 struct rtl8169_private *tp = netdev_priv(dev);
2176
2177 return mii_nway_restart(&tp->mii);
2178}
2179
50970831
FR		 2180/*
2181 * Interrupt coalescing
2182 *
2183 * > 1 - the availability of the IntrMitigate (0xe2) register through the
2184 * > 8169, 8168 and 810x line of chipsets
2185 *
2186 * 8169, 8168, and 8136(810x) serial chipsets support it.
2187 *
2188 * > 2 - the Tx timer unit at gigabit speed
2189 *
2190 * The unit of the timer depends on both the speed and the setting of CPlusCmd
2191 * (0xe0) bit 1 and bit 0.
2192 *
2193 * For 8169
2194 * bit[1:0] \ speed 1000M 100M 10M
2195 * 0 0 320ns 2.56us 40.96us
2196 * 0 1 2.56us 20.48us 327.7us
2197 * 1 0 5.12us 40.96us 655.4us
2198 * 1 1 10.24us 81.92us 1.31ms
2199 *
2200 * For the other
2201 * bit[1:0] \ speed 1000M 100M 10M
2202 * 0 0 5us 2.56us 40.96us
2203 * 0 1 40us 20.48us 327.7us
2204 * 1 0 80us 40.96us 655.4us
2205 * 1 1 160us 81.92us 1.31ms
2206 */
2207
2208/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
2209struct rtl_coalesce_scale {
2210 /* Rx / Tx */
2211 u32 nsecs[2];
2212};
2213
2214/* rx/tx scale factors for all CPlusCmd[0:1] cases */
2215struct rtl_coalesce_info {
2216 u32 speed;
2217 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
2218};
2219
2220/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
2221#define rxtx_x1822(r, t) { \
2222 {{(r), (t)}}, \
2223 {{(r)*8, (t)*8}}, \
2224 {{(r)*8*2, (t)*8*2}}, \
2225 {{(r)*8*2*2, (t)*8*2*2}}, \
2226}
2227static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
2228 /* speed delays: rx00 tx00 */
2229 { SPEED_10, rxtx_x1822(40960, 40960) },
2230 { SPEED_100, rxtx_x1822( 2560, 2560) },
2231 { SPEED_1000, rxtx_x1822( 320, 320) },
2232 { 0 },
2233};
2234
2235static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
2236 /* speed delays: rx00 tx00 */
2237 { SPEED_10, rxtx_x1822(40960, 40960) },
2238 { SPEED_100, rxtx_x1822( 2560, 2560) },
2239 { SPEED_1000, rxtx_x1822( 5000, 5000) },
2240 { 0 },
2241};
2242#undef rxtx_x1822
2243
2244/* get rx/tx scale vector corresponding to current speed */
2245static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
2246{
2247 struct rtl8169_private *tp = netdev_priv(dev);
2248 struct ethtool_link_ksettings ecmd;
2249 const struct rtl_coalesce_info *ci;
2250 int rc;
2251
2252 rc = rtl8169_get_link_ksettings(dev, &ecmd);
2253 if (rc < 0)
2254 return ERR_PTR(rc);
2255
2256 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
2257 if (ecmd.base.speed == ci->speed) {
2258 return ci;
2259 }
2260 }
2261
2262 return ERR_PTR(-ELNRNG);
2263}
2264
2265static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2266{
2267 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 2268 const struct rtl_coalesce_info *ci;
2269 const struct rtl_coalesce_scale *scale;
2270 struct {
2271 u32 *max_frames;
2272 u32 *usecs;
2273 } coal_settings [] = {
2274 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
2275 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
2276 }, *p = coal_settings;
2277 int i;
2278 u16 w;
2279
2280 memset(ec, 0, sizeof(*ec));
2281
2282 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2283 ci = rtl_coalesce_info(dev);
2284 if (IS_ERR(ci))
2285 return PTR_ERR(ci);
2286
0ae0974e 2287 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
50970831
FR		 2288
2289 /* read IntrMitigate and adjust according to scale */
1ef7286e 2290 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
50970831
FR		 2291 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2292 w >>= RTL_COALESCE_SHIFT;
2293 *p->usecs = w & RTL_COALESCE_MASK;
2294 }
2295
2296 for (i = 0; i < 2; i++) {
2297 p = coal_settings + i;
2298 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2299
2300 /*
2301 * ethtool_coalesce says it is illegal to set both usecs and
2302 * max_frames to 0.
2303 */
2304 if (!*p->usecs && !*p->max_frames)
2305 *p->max_frames = 1;
2306 }
2307
2308 return 0;
2309}
2310
2311/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2312static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2313 struct net_device *dev, u32 nsec, u16 *cp01)
2314{
2315 const struct rtl_coalesce_info *ci;
2316 u16 i;
2317
2318 ci = rtl_coalesce_info(dev);
2319 if (IS_ERR(ci))
2320 return ERR_CAST(ci);
2321
2322 for (i = 0; i < 4; i++) {
2323 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2324 ci->scalev[i].nsecs[1]);
2325 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2326 *cp01 = i;
2327 return &ci->scalev[i];
2328 }
2329 }
2330
2331 return ERR_PTR(-EINVAL);
2332}
2333
2334static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2335{
2336 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 2337 const struct rtl_coalesce_scale *scale;
2338 struct {
2339 u32 frames;
2340 u32 usecs;
2341 } coal_settings [] = {
2342 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2343 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2344 }, *p = coal_settings;
2345 u16 w = 0, cp01;
2346 int i;
2347
2348 scale = rtl_coalesce_choose_scale(dev,
2349 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2350 if (IS_ERR(scale))
2351 return PTR_ERR(scale);
2352
2353 for (i = 0; i < 2; i++, p++) {
2354 u32 units;
2355
2356 /*
2357 * accept max_frames=1 we returned in rtl_get_coalesce.
2358 * accept it not only when usecs=0 because of e.g. the following scenario:
2359 *
2360 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2361 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2362 * - then user does `ethtool -C eth0 rx-usecs 100`
2363 *
2364 * since ethtool sends to kernel whole ethtool_coalesce
2365 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2366 * we'll reject it below in `frames % 4 != 0`.
2367 */
2368 if (p->frames == 1) {
2369 p->frames = 0;
2370 }
2371
2372 units = p->usecs * 1000 / scale->nsecs[i];
2373 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2374 return -EINVAL;
2375
2376 w <<= RTL_COALESCE_SHIFT;
2377 w |= units;
2378 w <<= RTL_COALESCE_SHIFT;
2379 w |= p->frames >> 2;
2380 }
2381
2382 rtl_lock_work(tp);
2383
1ef7286e 2384 RTL_W16(tp, IntrMitigate, swab16(w));
50970831 2385
9a3c81fa 2386 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1ef7286e
AS		 2387 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2388 RTL_R16(tp, CPlusCmd);
50970831
FR		 2389
2390 rtl_unlock_work(tp);
2391
2392 return 0;
2393}
2394
7282d491 2395static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2396 .get_drvinfo = rtl8169_get_drvinfo,
2397 .get_regs_len = rtl8169_get_regs_len,
2398 .get_link = ethtool_op_get_link,
50970831
FR		 2399 .get_coalesce = rtl_get_coalesce,
2400 .set_coalesce = rtl_set_coalesce,
b57b7e5a
SH		 2401 .get_msglevel = rtl8169_get_msglevel,
2402 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2403 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2404 .get_wol = rtl8169_get_wol,
2405 .set_wol = rtl8169_set_wol,
d4a3a0fc 2406 .get_strings = rtl8169_get_strings,
b9f2c044 2407 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2408 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2409 .get_ts_info = ethtool_op_get_ts_info,
f0903ea3 2410 .nway_reset = rtl8169_nway_reset,
6fa1ba61 2411 .get_link_ksettings = rtl8169_get_link_ksettings,
9e77d7a5 2412 .set_link_ksettings = rtl8169_set_link_ksettings,
1da177e4
LT		 2413};
2414
07d3f51f 2415static void rtl8169_get_mac_version(struct rtl8169_private *tp,
22148df0 2416 u8 default_version)
1da177e4 2417{
0e485150
FR		 2418 /*
2419 * The driver currently handles the 8168Bf and the 8168Be identically
2420 * but they can be identified more specifically through the test below
2421 * if needed:
2422 *
1ef7286e 2423 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2424 *
2425 * Same thing for the 8101Eb and the 8101Ec:
2426 *
1ef7286e 2427 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2428 */
3744100e 2429 static const struct rtl_mac_info {
1da177e4 2430 u32 mask;
e3cf0cc0 2431 u32 val;
1da177e4
LT		 2432 int mac_version;
2433 } mac_info[] = {
935e2218
CHL		 2434 /* 8168EP family. */
2435 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2436 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2437 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2438
6e1d0b89
CHL		 2439 /* 8168H family. */
2440 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2441 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2442
c558386b 2443 /* 8168G family. */
45dd95c4 2444 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2445 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2446 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2447 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2448
c2218925 2449 /* 8168F family. */
b3d7b2f2 2450 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2451 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2452 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2453
01dc7fec 2454 /* 8168E family. */
70090424 2455 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2456 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2457 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2458
5b538df9 2459 /* 8168D family. */
daf9df6d 2460 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2461 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2462
e6de30d6 2463 /* 8168DP family. */
2464 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2465 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2466 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2467
ef808d50 2468 /* 8168C family. */
ef3386f0 2469 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2470 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2471 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2472 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2473 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2474 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
ef808d50 2475 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2476
2477 /* 8168B family. */
2478 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
e3cf0cc0
FR		 2479 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2480 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2481
2482 /* 8101 family. */
5598bfe5 2483 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2484 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
5a5e4443
HW		 2485 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2486 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2487 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2488 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2489 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2490 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2491 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2492 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2493 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2494 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2495 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2496 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2497 /* FIXME: where did these entries come from ? -- FR */
2498 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2499 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2500
2501 /* 8110 family. */
2502 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2503 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2504 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2505 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2506 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2507 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2508
f21b75e9
JD		 2509 /* Catch-all */
2510 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2511 };
2512 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2513 u32 reg;
2514
1ef7286e 2515 reg = RTL_R32(tp, TxConfig);
e3cf0cc0 2516 while ((reg & p->mask) != p->val)
1da177e4
LT		 2517 p++;
2518 tp->mac_version = p->mac_version;
5d320a20
FR		 2519
2520 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
22148df0
HK		 2521 dev_notice(tp_to_dev(tp),
2522 "unknown MAC, using family default\n");
5d320a20 2523 tp->mac_version = default_version;
58152cd4 2524 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2525 tp->mac_version = tp->mii.supports_gmii ?
2526 RTL_GIGA_MAC_VER_42 :
2527 RTL_GIGA_MAC_VER_43;
6e1d0b89
CHL		 2528 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2529 tp->mac_version = tp->mii.supports_gmii ?
2530 RTL_GIGA_MAC_VER_45 :
2531 RTL_GIGA_MAC_VER_47;
2532 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2533 tp->mac_version = tp->mii.supports_gmii ?
2534 RTL_GIGA_MAC_VER_46 :
2535 RTL_GIGA_MAC_VER_48;
5d320a20 2536 }
1da177e4
LT		 2537}
2538
2539static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2540{
49d17512 2541 netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2542}
2543
867763c1
FR		 2544struct phy_reg {
2545 u16 reg;
2546 u16 val;
2547};
2548
4da19633 2549static void rtl_writephy_batch(struct rtl8169_private *tp,
2550 const struct phy_reg *regs, int len)
867763c1
FR		 2551{
2552 while (len-- > 0) {
4da19633 2553 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2554 regs++;
2555 }
2556}
2557
bca03d5f 2558#define PHY_READ 0x00000000
2559#define PHY_DATA_OR 0x10000000
2560#define PHY_DATA_AND 0x20000000
2561#define PHY_BJMPN 0x30000000
eee3786f 2562#define PHY_MDIO_CHG 0x40000000
bca03d5f 2563#define PHY_CLEAR_READCOUNT 0x70000000
2564#define PHY_WRITE 0x80000000
2565#define PHY_READCOUNT_EQ_SKIP 0x90000000
2566#define PHY_COMP_EQ_SKIPN 0xa0000000
2567#define PHY_COMP_NEQ_SKIPN 0xb0000000
2568#define PHY_WRITE_PREVIOUS 0xc0000000
2569#define PHY_SKIPN 0xd0000000
2570#define PHY_DELAY_MS 0xe0000000
bca03d5f 2571
960aee6c
HW		 2572struct fw_info {
2573 u32 magic;
2574 char version[RTL_VER_SIZE];
2575 __le32 fw_start;
2576 __le32 fw_len;
2577 u8 chksum;
2578} __packed;
2579
1c361efb
FR		 2580#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2581
2582static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2583{
b6ffd97f 2584 const struct firmware *fw = rtl_fw->fw;
960aee6c 2585 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2586 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2587 char *version = rtl_fw->version;
2588 bool rc = false;
2589
2590 if (fw->size < FW_OPCODE_SIZE)
2591 goto out;
960aee6c
HW		 2592
2593 if (!fw_info->magic) {
2594 size_t i, size, start;
2595 u8 checksum = 0;
2596
2597 if (fw->size < sizeof(*fw_info))
2598 goto out;
2599
2600 for (i = 0; i < fw->size; i++)
2601 checksum += fw->data[i];
2602 if (checksum != 0)
2603 goto out;
2604
2605 start = le32_to_cpu(fw_info->fw_start);
2606 if (start > fw->size)
2607 goto out;
2608
2609 size = le32_to_cpu(fw_info->fw_len);
2610 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2611 goto out;
2612
2613 memcpy(version, fw_info->version, RTL_VER_SIZE);
2614
2615 pa->code = (__le32 *)(fw->data + start);
2616 pa->size = size;
2617 } else {
1c361efb
FR		 2618 if (fw->size % FW_OPCODE_SIZE)
2619 goto out;
2620
2621 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2622
2623 pa->code = (__le32 *)fw->data;
2624 pa->size = fw->size / FW_OPCODE_SIZE;
2625 }
2626 version[RTL_VER_SIZE - 1] = 0;
2627
2628 rc = true;
2629out:
2630 return rc;
2631}
2632
fd112f2e
FR		 2633static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2634 struct rtl_fw_phy_action *pa)
1c361efb 2635{
fd112f2e 2636 bool rc = false;
1c361efb 2637 size_t index;
bca03d5f 2638
1c361efb
FR		 2639 for (index = 0; index < pa->size; index++) {
2640 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2641 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2642
42b82dc1 2643 switch(action & 0xf0000000) {
2644 case PHY_READ:
2645 case PHY_DATA_OR:
2646 case PHY_DATA_AND:
eee3786f 2647 case PHY_MDIO_CHG:
42b82dc1 2648 case PHY_CLEAR_READCOUNT:
2649 case PHY_WRITE:
2650 case PHY_WRITE_PREVIOUS:
2651 case PHY_DELAY_MS:
2652 break;
2653
2654 case PHY_BJMPN:
2655 if (regno > index) {
fd112f2e 2656 netif_err(tp, ifup, tp->dev,
cecb5fd7 2657 "Out of range of firmware\n");
fd112f2e 2658 goto out;
42b82dc1 2659 }
2660 break;
2661 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2662 if (index + 2 >= pa->size) {
fd112f2e 2663 netif_err(tp, ifup, tp->dev,
cecb5fd7 2664 "Out of range of firmware\n");
fd112f2e 2665 goto out;
42b82dc1 2666 }
2667 break;
2668 case PHY_COMP_EQ_SKIPN:
2669 case PHY_COMP_NEQ_SKIPN:
2670 case PHY_SKIPN:
1c361efb 2671 if (index + 1 + regno >= pa->size) {
fd112f2e 2672 netif_err(tp, ifup, tp->dev,
cecb5fd7 2673 "Out of range of firmware\n");
fd112f2e 2674 goto out;
42b82dc1 2675 }
bca03d5f 2676 break;
2677
42b82dc1 2678 default:
fd112f2e 2679 netif_err(tp, ifup, tp->dev,
42b82dc1 2680 "Invalid action 0x%08x\n", action);
fd112f2e 2681 goto out;
bca03d5f 2682 }
2683 }
fd112f2e
FR		 2684 rc = true;
2685out:
2686 return rc;
2687}
bca03d5f 2688
fd112f2e
FR		 2689static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2690{
2691 struct net_device *dev = tp->dev;
2692 int rc = -EINVAL;
2693
2694 if (!rtl_fw_format_ok(tp, rtl_fw)) {
5c2d2b14 2695 netif_err(tp, ifup, dev, "invalid firmware\n");
fd112f2e
FR		 2696 goto out;
2697 }
2698
2699 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2700 rc = 0;
2701out:
2702 return rc;
2703}
2704
2705static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2706{
2707 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2708 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2709 u32 predata, count;
2710 size_t index;
2711
2712 predata = count = 0;
eee3786f 2713 org.write = ops->write;
2714 org.read = ops->read;
42b82dc1 2715
1c361efb
FR		 2716 for (index = 0; index < pa->size; ) {
2717 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2718 u32 data = action & 0x0000ffff;
42b82dc1 2719 u32 regno = (action & 0x0fff0000) >> 16;
2720
2721 if (!action)
2722 break;
bca03d5f 2723
2724 switch(action & 0xf0000000) {
42b82dc1 2725 case PHY_READ:
2726 predata = rtl_readphy(tp, regno);
2727 count++;
2728 index++;
2729 break;
2730 case PHY_DATA_OR:
2731 predata |= data;
2732 index++;
2733 break;
2734 case PHY_DATA_AND:
2735 predata &= data;
2736 index++;
2737 break;
2738 case PHY_BJMPN:
2739 index -= regno;
2740 break;
eee3786f 2741 case PHY_MDIO_CHG:
2742 if (data == 0) {
2743 ops->write = org.write;
2744 ops->read = org.read;
2745 } else if (data == 1) {
2746 ops->write = mac_mcu_write;
2747 ops->read = mac_mcu_read;
2748 }
2749
42b82dc1 2750 index++;
2751 break;
2752 case PHY_CLEAR_READCOUNT:
2753 count = 0;
2754 index++;
2755 break;
bca03d5f 2756 case PHY_WRITE:
42b82dc1 2757 rtl_writephy(tp, regno, data);
2758 index++;
2759 break;
2760 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2761 index += (count == data) ? 2 : 1;
bca03d5f 2762 break;
42b82dc1 2763 case PHY_COMP_EQ_SKIPN:
2764 if (predata == data)
2765 index += regno;
2766 index++;
2767 break;
2768 case PHY_COMP_NEQ_SKIPN:
2769 if (predata != data)
2770 index += regno;
2771 index++;
2772 break;
2773 case PHY_WRITE_PREVIOUS:
2774 rtl_writephy(tp, regno, predata);
2775 index++;
2776 break;
2777 case PHY_SKIPN:
2778 index += regno + 1;
2779 break;
2780 case PHY_DELAY_MS:
2781 mdelay(data);
2782 index++;
2783 break;
2784
bca03d5f 2785 default:
2786 BUG();
2787 }
2788 }
eee3786f 2789
2790 ops->write = org.write;
2791 ops->read = org.read;
bca03d5f 2792}
2793
f1e02ed1 2794static void rtl_release_firmware(struct rtl8169_private *tp)
2795{
b6ffd97f
FR		 2796 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2797 release_firmware(tp->rtl_fw->fw);
2798 kfree(tp->rtl_fw);
2799 }
2800 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2801}
2802
953a12cc 2803static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2804{
b6ffd97f 2805 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2806
2807 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2808 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2809 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2810}
2811
2812static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2813{
2814 if (rtl_readphy(tp, reg) != val)
2815 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2816 else
2817 rtl_apply_firmware(tp);
f1e02ed1 2818}
2819
4da19633 2820static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2821{
350f7596 2822 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2823 { 0x1f, 0x0001 },
2824 { 0x06, 0x006e },
2825 { 0x08, 0x0708 },
2826 { 0x15, 0x4000 },
2827 { 0x18, 0x65c7 },
1da177e4 2828
0b9b571d 2829 { 0x1f, 0x0001 },
2830 { 0x03, 0x00a1 },
2831 { 0x02, 0x0008 },
2832 { 0x01, 0x0120 },
2833 { 0x00, 0x1000 },
2834 { 0x04, 0x0800 },
2835 { 0x04, 0x0000 },
1da177e4 2836
0b9b571d 2837 { 0x03, 0xff41 },
2838 { 0x02, 0xdf60 },
2839 { 0x01, 0x0140 },
2840 { 0x00, 0x0077 },
2841 { 0x04, 0x7800 },
2842 { 0x04, 0x7000 },
2843
2844 { 0x03, 0x802f },
2845 { 0x02, 0x4f02 },
2846 { 0x01, 0x0409 },
2847 { 0x00, 0xf0f9 },
2848 { 0x04, 0x9800 },
2849 { 0x04, 0x9000 },
2850
2851 { 0x03, 0xdf01 },
2852 { 0x02, 0xdf20 },
2853 { 0x01, 0xff95 },
2854 { 0x00, 0xba00 },
2855 { 0x04, 0xa800 },
2856 { 0x04, 0xa000 },
2857
2858 { 0x03, 0xff41 },
2859 { 0x02, 0xdf20 },
2860 { 0x01, 0x0140 },
2861 { 0x00, 0x00bb },
2862 { 0x04, 0xb800 },
2863 { 0x04, 0xb000 },
2864
2865 { 0x03, 0xdf41 },
2866 { 0x02, 0xdc60 },
2867 { 0x01, 0x6340 },
2868 { 0x00, 0x007d },
2869 { 0x04, 0xd800 },
2870 { 0x04, 0xd000 },
2871
2872 { 0x03, 0xdf01 },
2873 { 0x02, 0xdf20 },
2874 { 0x01, 0x100a },
2875 { 0x00, 0xa0ff },
2876 { 0x04, 0xf800 },
2877 { 0x04, 0xf000 },
2878
2879 { 0x1f, 0x0000 },
2880 { 0x0b, 0x0000 },
2881 { 0x00, 0x9200 }
2882 };
1da177e4 2883
4da19633 2884 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2885}
2886
4da19633 2887static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2888{
350f7596 2889 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2890 { 0x1f, 0x0002 },
2891 { 0x01, 0x90d0 },
2892 { 0x1f, 0x0000 }
2893 };
2894
4da19633 2895 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2896}
2897
4da19633 2898static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2899{
2900 struct pci_dev *pdev = tp->pci_dev;
2e955856 2901
ccbae55e
SS		 2902 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2903 (pdev->subsystem_device != 0xe000))
2e955856 2904 return;
2905
4da19633 2906 rtl_writephy(tp, 0x1f, 0x0001);
2907 rtl_writephy(tp, 0x10, 0xf01b);
2908 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2909}
2910
4da19633 2911static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2912{
350f7596 2913 static const struct phy_reg phy_reg_init[] = {
2e955856 2914 { 0x1f, 0x0001 },
2915 { 0x04, 0x0000 },
2916 { 0x03, 0x00a1 },
2917 { 0x02, 0x0008 },
2918 { 0x01, 0x0120 },
2919 { 0x00, 0x1000 },
2920 { 0x04, 0x0800 },
2921 { 0x04, 0x9000 },
2922 { 0x03, 0x802f },
2923 { 0x02, 0x4f02 },
2924 { 0x01, 0x0409 },
2925 { 0x00, 0xf099 },
2926 { 0x04, 0x9800 },
2927 { 0x04, 0xa000 },
2928 { 0x03, 0xdf01 },
2929 { 0x02, 0xdf20 },
2930 { 0x01, 0xff95 },
2931 { 0x00, 0xba00 },
2932 { 0x04, 0xa800 },
2933 { 0x04, 0xf000 },
2934 { 0x03, 0xdf01 },
2935 { 0x02, 0xdf20 },
2936 { 0x01, 0x101a },
2937 { 0x00, 0xa0ff },
2938 { 0x04, 0xf800 },
2939 { 0x04, 0x0000 },
2940 { 0x1f, 0x0000 },
2941
2942 { 0x1f, 0x0001 },
2943 { 0x10, 0xf41b },
2944 { 0x14, 0xfb54 },
2945 { 0x18, 0xf5c7 },
2946 { 0x1f, 0x0000 },
2947
2948 { 0x1f, 0x0001 },
2949 { 0x17, 0x0cc0 },
2950 { 0x1f, 0x0000 }
2951 };
2952
4da19633 2953 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2954
4da19633 2955 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2956}
2957
4da19633 2958static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2959{
350f7596 2960 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2961 { 0x1f, 0x0001 },
2962 { 0x04, 0x0000 },
2963 { 0x03, 0x00a1 },
2964 { 0x02, 0x0008 },
2965 { 0x01, 0x0120 },
2966 { 0x00, 0x1000 },
2967 { 0x04, 0x0800 },
2968 { 0x04, 0x9000 },
2969 { 0x03, 0x802f },
2970 { 0x02, 0x4f02 },
2971 { 0x01, 0x0409 },
2972 { 0x00, 0xf099 },
2973 { 0x04, 0x9800 },
2974 { 0x04, 0xa000 },
2975 { 0x03, 0xdf01 },
2976 { 0x02, 0xdf20 },
2977 { 0x01, 0xff95 },
2978 { 0x00, 0xba00 },
2979 { 0x04, 0xa800 },
2980 { 0x04, 0xf000 },
2981 { 0x03, 0xdf01 },
2982 { 0x02, 0xdf20 },
2983 { 0x01, 0x101a },
2984 { 0x00, 0xa0ff },
2985 { 0x04, 0xf800 },
2986 { 0x04, 0x0000 },
2987 { 0x1f, 0x0000 },
2988
2989 { 0x1f, 0x0001 },
2990 { 0x0b, 0x8480 },
2991 { 0x1f, 0x0000 },
2992
2993 { 0x1f, 0x0001 },
2994 { 0x18, 0x67c7 },
2995 { 0x04, 0x2000 },
2996 { 0x03, 0x002f },
2997 { 0x02, 0x4360 },
2998 { 0x01, 0x0109 },
2999 { 0x00, 0x3022 },
3000 { 0x04, 0x2800 },
3001 { 0x1f, 0x0000 },
3002
3003 { 0x1f, 0x0001 },
3004 { 0x17, 0x0cc0 },
3005 { 0x1f, 0x0000 }
3006 };
3007
4da19633 3008 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 3009}
3010
4da19633 3011static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 3012{
350f7596 3013 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 3014 { 0x10, 0xf41b },
3015 { 0x1f, 0x0000 }
3016 };
3017
4da19633 3018 rtl_writephy(tp, 0x1f, 0x0001);
3019 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 3020
4da19633 3021 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 3022}
3023
4da19633 3024static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 3025{
350f7596 3026 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 3027 { 0x1f, 0x0001 },
3028 { 0x10, 0xf41b },
3029 { 0x1f, 0x0000 }
3030 };
3031
4da19633 3032 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 3033}
3034
4da19633 3035static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 3036{
350f7596 3037 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 3038 { 0x1f, 0x0000 },
3039 { 0x1d, 0x0f00 },
3040 { 0x1f, 0x0002 },
3041 { 0x0c, 0x1ec8 },
3042 { 0x1f, 0x0000 }
3043 };
3044
4da19633 3045 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 3046}
3047
4da19633 3048static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 3049{
350f7596 3050 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 3051 { 0x1f, 0x0001 },
3052 { 0x1d, 0x3d98 },
3053 { 0x1f, 0x0000 }
3054 };
3055
4da19633 3056 rtl_writephy(tp, 0x1f, 0x0000);
3057 rtl_patchphy(tp, 0x14, 1 << 5);
3058 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 3059
4da19633 3060 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 3061}
3062
4da19633 3063static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 3064{
350f7596 3065 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 3066 { 0x1f, 0x0001 },
3067 { 0x12, 0x2300 },
867763c1
FR		 3068 { 0x1f, 0x0002 },
3069 { 0x00, 0x88d4 },
3070 { 0x01, 0x82b1 },
3071 { 0x03, 0x7002 },
3072 { 0x08, 0x9e30 },
3073 { 0x09, 0x01f0 },
3074 { 0x0a, 0x5500 },
3075 { 0x0c, 0x00c8 },
3076 { 0x1f, 0x0003 },
3077 { 0x12, 0xc096 },
3078 { 0x16, 0x000a },
f50d4275
FR		 3079 { 0x1f, 0x0000 },
3080 { 0x1f, 0x0000 },
3081 { 0x09, 0x2000 },
3082 { 0x09, 0x0000 }
867763c1
FR		 3083 };
3084
4da19633 3085 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3086
4da19633 3087 rtl_patchphy(tp, 0x14, 1 << 5);
3088 rtl_patchphy(tp, 0x0d, 1 << 5);
3089 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 3090}
3091
4da19633 3092static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 3093{
350f7596 3094 static const struct phy_reg phy_reg_init[] = {
f50d4275 3095 { 0x1f, 0x0001 },
7da97ec9 3096 { 0x12, 0x2300 },
f50d4275
FR		 3097 { 0x03, 0x802f },
3098 { 0x02, 0x4f02 },
3099 { 0x01, 0x0409 },
3100 { 0x00, 0xf099 },
3101 { 0x04, 0x9800 },
3102 { 0x04, 0x9000 },
3103 { 0x1d, 0x3d98 },
7da97ec9
FR		 3104 { 0x1f, 0x0002 },
3105 { 0x0c, 0x7eb8 },
f50d4275
FR		 3106 { 0x06, 0x0761 },
3107 { 0x1f, 0x0003 },
3108 { 0x16, 0x0f0a },
7da97ec9
FR		 3109 { 0x1f, 0x0000 }
3110 };
3111
4da19633 3112 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3113
4da19633 3114 rtl_patchphy(tp, 0x16, 1 << 0);
3115 rtl_patchphy(tp, 0x14, 1 << 5);
3116 rtl_patchphy(tp, 0x0d, 1 << 5);
3117 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 3118}
3119
4da19633 3120static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 3121{
350f7596 3122 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 3123 { 0x1f, 0x0001 },
3124 { 0x12, 0x2300 },
3125 { 0x1d, 0x3d98 },
3126 { 0x1f, 0x0002 },
3127 { 0x0c, 0x7eb8 },
3128 { 0x06, 0x5461 },
3129 { 0x1f, 0x0003 },
3130 { 0x16, 0x0f0a },
3131 { 0x1f, 0x0000 }
3132 };
3133
4da19633 3134 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 3135
4da19633 3136 rtl_patchphy(tp, 0x16, 1 << 0);
3137 rtl_patchphy(tp, 0x14, 1 << 5);
3138 rtl_patchphy(tp, 0x0d, 1 << 5);
3139 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 3140}
3141
4da19633 3142static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 3143{
4da19633 3144 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 3145}
3146
bca03d5f 3147static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 3148{
350f7596 3149 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3150 /* Channel Estimation */
5b538df9 3151 { 0x1f, 0x0001 },
daf9df6d 3152 { 0x06, 0x4064 },
3153 { 0x07, 0x2863 },
3154 { 0x08, 0x059c },
3155 { 0x09, 0x26b4 },
3156 { 0x0a, 0x6a19 },
3157 { 0x0b, 0xdcc8 },
3158 { 0x10, 0xf06d },
3159 { 0x14, 0x7f68 },
3160 { 0x18, 0x7fd9 },
3161 { 0x1c, 0xf0ff },
3162 { 0x1d, 0x3d9c },
5b538df9 3163 { 0x1f, 0x0003 },
daf9df6d 3164 { 0x12, 0xf49f },
3165 { 0x13, 0x070b },
3166 { 0x1a, 0x05ad },
bca03d5f 3167 { 0x14, 0x94c0 },
3168
3169 /*
3170 * Tx Error Issue
cecb5fd7 3171 * Enhance line driver power
bca03d5f 3172 */
5b538df9 3173 { 0x1f, 0x0002 },
daf9df6d 3174 { 0x06, 0x5561 },
3175 { 0x1f, 0x0005 },
3176 { 0x05, 0x8332 },
bca03d5f 3177 { 0x06, 0x5561 },
3178
3179 /*
3180 * Can not link to 1Gbps with bad cable
3181 * Decrease SNR threshold form 21.07dB to 19.04dB
3182 */
3183 { 0x1f, 0x0001 },
3184 { 0x17, 0x0cc0 },
daf9df6d 3185
5b538df9 3186 { 0x1f, 0x0000 },
bca03d5f 3187 { 0x0d, 0xf880 }
daf9df6d 3188 };
3189
4da19633 3190 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 3191
bca03d5f 3192 /*
3193 * Rx Error Issue
3194 * Fine Tune Switching regulator parameter
3195 */
4da19633 3196 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3197 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3198 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 3199
fdf6fc06 3200 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3201 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3202 { 0x1f, 0x0002 },
3203 { 0x05, 0x669a },
3204 { 0x1f, 0x0005 },
3205 { 0x05, 0x8330 },
3206 { 0x06, 0x669a },
3207 { 0x1f, 0x0002 }
3208 };
3209 int val;
3210
4da19633 3211 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3212
4da19633 3213 val = rtl_readphy(tp, 0x0d);
daf9df6d 3214
3215 if ((val & 0x00ff) != 0x006c) {
350f7596 3216 static const u32 set[] = {
daf9df6d 3217 0x0065, 0x0066, 0x0067, 0x0068,
3218 0x0069, 0x006a, 0x006b, 0x006c
3219 };
3220 int i;
3221
4da19633 3222 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3223
3224 val &= 0xff00;
3225 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3226 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3227 }
3228 } else {
350f7596 3229 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3230 { 0x1f, 0x0002 },
3231 { 0x05, 0x6662 },
3232 { 0x1f, 0x0005 },
3233 { 0x05, 0x8330 },
3234 { 0x06, 0x6662 }
3235 };
3236
4da19633 3237 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3238 }
3239
bca03d5f 3240 /* RSET couple improve */
4da19633 3241 rtl_writephy(tp, 0x1f, 0x0002);
3242 rtl_patchphy(tp, 0x0d, 0x0300);
3243 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 3244
bca03d5f 3245 /* Fine tune PLL performance */
4da19633 3246 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3247 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3248 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3249
4da19633 3250 rtl_writephy(tp, 0x1f, 0x0005);
3251 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3252
3253 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 3254
4da19633 3255 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3256}
3257
bca03d5f 3258static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3259{
350f7596 3260 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3261 /* Channel Estimation */
daf9df6d 3262 { 0x1f, 0x0001 },
3263 { 0x06, 0x4064 },
3264 { 0x07, 0x2863 },
3265 { 0x08, 0x059c },
3266 { 0x09, 0x26b4 },
3267 { 0x0a, 0x6a19 },
3268 { 0x0b, 0xdcc8 },
3269 { 0x10, 0xf06d },
3270 { 0x14, 0x7f68 },
3271 { 0x18, 0x7fd9 },
3272 { 0x1c, 0xf0ff },
3273 { 0x1d, 0x3d9c },
3274 { 0x1f, 0x0003 },
3275 { 0x12, 0xf49f },
3276 { 0x13, 0x070b },
3277 { 0x1a, 0x05ad },
3278 { 0x14, 0x94c0 },
3279
bca03d5f 3280 /*
3281 * Tx Error Issue
cecb5fd7 3282 * Enhance line driver power
bca03d5f 3283 */
daf9df6d 3284 { 0x1f, 0x0002 },
3285 { 0x06, 0x5561 },
3286 { 0x1f, 0x0005 },
3287 { 0x05, 0x8332 },
bca03d5f 3288 { 0x06, 0x5561 },
3289
3290 /*
3291 * Can not link to 1Gbps with bad cable
3292 * Decrease SNR threshold form 21.07dB to 19.04dB
3293 */
3294 { 0x1f, 0x0001 },
3295 { 0x17, 0x0cc0 },
daf9df6d 3296
3297 { 0x1f, 0x0000 },
bca03d5f 3298 { 0x0d, 0xf880 }
5b538df9
FR		 3299 };
3300
4da19633 3301 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 3302
fdf6fc06 3303 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3304 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3305 { 0x1f, 0x0002 },
3306 { 0x05, 0x669a },
5b538df9 3307 { 0x1f, 0x0005 },
daf9df6d 3308 { 0x05, 0x8330 },
3309 { 0x06, 0x669a },
3310
3311 { 0x1f, 0x0002 }
3312 };
3313 int val;
3314
4da19633 3315 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3316
4da19633 3317 val = rtl_readphy(tp, 0x0d);
daf9df6d 3318 if ((val & 0x00ff) != 0x006c) {
b6bc7650 3319 static const u32 set[] = {
daf9df6d 3320 0x0065, 0x0066, 0x0067, 0x0068,
3321 0x0069, 0x006a, 0x006b, 0x006c
3322 };
3323 int i;
3324
4da19633 3325 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3326
3327 val &= 0xff00;
3328 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3329 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3330 }
3331 } else {
350f7596 3332 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3333 { 0x1f, 0x0002 },
3334 { 0x05, 0x2642 },
5b538df9 3335 { 0x1f, 0x0005 },
daf9df6d 3336 { 0x05, 0x8330 },
3337 { 0x06, 0x2642 }
5b538df9
FR		 3338 };
3339
4da19633 3340 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3341 }
3342
bca03d5f 3343 /* Fine tune PLL performance */
4da19633 3344 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3345 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3346 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3347
bca03d5f 3348 /* Switching regulator Slew rate */
4da19633 3349 rtl_writephy(tp, 0x1f, 0x0002);
3350 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 3351
4da19633 3352 rtl_writephy(tp, 0x1f, 0x0005);
3353 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3354
3355 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 3356
4da19633 3357 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3358}
3359
4da19633 3360static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3361{
350f7596 3362 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3363 { 0x1f, 0x0002 },
3364 { 0x10, 0x0008 },
3365 { 0x0d, 0x006c },
3366
3367 { 0x1f, 0x0000 },
3368 { 0x0d, 0xf880 },
3369
3370 { 0x1f, 0x0001 },
3371 { 0x17, 0x0cc0 },
3372
3373 { 0x1f, 0x0001 },
3374 { 0x0b, 0xa4d8 },
3375 { 0x09, 0x281c },
3376 { 0x07, 0x2883 },
3377 { 0x0a, 0x6b35 },
3378 { 0x1d, 0x3da4 },
3379 { 0x1c, 0xeffd },
3380 { 0x14, 0x7f52 },
3381 { 0x18, 0x7fc6 },
3382 { 0x08, 0x0601 },
3383 { 0x06, 0x4063 },
3384 { 0x10, 0xf074 },
3385 { 0x1f, 0x0003 },
3386 { 0x13, 0x0789 },
3387 { 0x12, 0xf4bd },
3388 { 0x1a, 0x04fd },
3389 { 0x14, 0x84b0 },
3390 { 0x1f, 0x0000 },
3391 { 0x00, 0x9200 },
3392
3393 { 0x1f, 0x0005 },
3394 { 0x01, 0x0340 },
3395 { 0x1f, 0x0001 },
3396 { 0x04, 0x4000 },
3397 { 0x03, 0x1d21 },
3398 { 0x02, 0x0c32 },
3399 { 0x01, 0x0200 },
3400 { 0x00, 0x5554 },
3401 { 0x04, 0x4800 },
3402 { 0x04, 0x4000 },
3403 { 0x04, 0xf000 },
3404 { 0x03, 0xdf01 },
3405 { 0x02, 0xdf20 },
3406 { 0x01, 0x101a },
3407 { 0x00, 0xa0ff },
3408 { 0x04, 0xf800 },
3409 { 0x04, 0xf000 },
3410 { 0x1f, 0x0000 },
3411
3412 { 0x1f, 0x0007 },
3413 { 0x1e, 0x0023 },
3414 { 0x16, 0x0000 },
3415 { 0x1f, 0x0000 }
3416 };
3417
4da19633 3418 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3419}
3420
e6de30d6 3421static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3422{
3423 static const struct phy_reg phy_reg_init[] = {
3424 { 0x1f, 0x0001 },
3425 { 0x17, 0x0cc0 },
3426
3427 { 0x1f, 0x0007 },
3428 { 0x1e, 0x002d },
3429 { 0x18, 0x0040 },
3430 { 0x1f, 0x0000 }
3431 };
3432
3433 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3434 rtl_patchphy(tp, 0x0d, 1 << 5);
3435}
3436
70090424 3437static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3438{
3439 static const struct phy_reg phy_reg_init[] = {
3440 /* Enable Delay cap */
3441 { 0x1f, 0x0005 },
3442 { 0x05, 0x8b80 },
3443 { 0x06, 0xc896 },
3444 { 0x1f, 0x0000 },
3445
3446 /* Channel estimation fine tune */
3447 { 0x1f, 0x0001 },
3448 { 0x0b, 0x6c20 },
3449 { 0x07, 0x2872 },
3450 { 0x1c, 0xefff },
3451 { 0x1f, 0x0003 },
3452 { 0x14, 0x6420 },
3453 { 0x1f, 0x0000 },
3454
3455 /* Update PFM & 10M TX idle timer */
3456 { 0x1f, 0x0007 },
3457 { 0x1e, 0x002f },
3458 { 0x15, 0x1919 },
3459 { 0x1f, 0x0000 },
3460
3461 { 0x1f, 0x0007 },
3462 { 0x1e, 0x00ac },
3463 { 0x18, 0x0006 },
3464 { 0x1f, 0x0000 }
3465 };
3466
15ecd039
FR		 3467 rtl_apply_firmware(tp);
3468
01dc7fec 3469 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3470
3471 /* DCO enable for 10M IDLE Power */
3472 rtl_writephy(tp, 0x1f, 0x0007);
3473 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3474 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3475 rtl_writephy(tp, 0x1f, 0x0000);
3476
3477 /* For impedance matching */
3478 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3479 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3480 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3481
3482 /* PHY auto speed down */
3483 rtl_writephy(tp, 0x1f, 0x0007);
3484 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3485 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3486 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3487 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3488
3489 rtl_writephy(tp, 0x1f, 0x0005);
3490 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3491 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3492 rtl_writephy(tp, 0x1f, 0x0000);
3493
3494 rtl_writephy(tp, 0x1f, 0x0005);
3495 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3496 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3497 rtl_writephy(tp, 0x1f, 0x0007);
3498 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3499 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3500 rtl_writephy(tp, 0x1f, 0x0006);
3501 rtl_writephy(tp, 0x00, 0x5a00);
3502 rtl_writephy(tp, 0x1f, 0x0000);
3503 rtl_writephy(tp, 0x0d, 0x0007);
3504 rtl_writephy(tp, 0x0e, 0x003c);
3505 rtl_writephy(tp, 0x0d, 0x4007);
3506 rtl_writephy(tp, 0x0e, 0x0000);
3507 rtl_writephy(tp, 0x0d, 0x0000);
3508}
3509
9ecb9aab 3510static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3511{
3512 const u16 w[] = {
3513 addr[0] | (addr[1] << 8),
3514 addr[2] | (addr[3] << 8),
3515 addr[4] | (addr[5] << 8)
3516 };
3517 const struct exgmac_reg e[] = {
3518 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3519 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3520 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3521 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3522 };
3523
3524 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3525}
3526
70090424
HW		 3527static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3528{
3529 static const struct phy_reg phy_reg_init[] = {
3530 /* Enable Delay cap */
3531 { 0x1f, 0x0004 },
3532 { 0x1f, 0x0007 },
3533 { 0x1e, 0x00ac },
3534 { 0x18, 0x0006 },
3535 { 0x1f, 0x0002 },
3536 { 0x1f, 0x0000 },
3537 { 0x1f, 0x0000 },
3538
3539 /* Channel estimation fine tune */
3540 { 0x1f, 0x0003 },
3541 { 0x09, 0xa20f },
3542 { 0x1f, 0x0000 },
3543 { 0x1f, 0x0000 },
3544
3545 /* Green Setting */
3546 { 0x1f, 0x0005 },
3547 { 0x05, 0x8b5b },
3548 { 0x06, 0x9222 },
3549 { 0x05, 0x8b6d },
3550 { 0x06, 0x8000 },
3551 { 0x05, 0x8b76 },
3552 { 0x06, 0x8000 },
3553 { 0x1f, 0x0000 }
3554 };
3555
3556 rtl_apply_firmware(tp);
3557
3558 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3559
3560 /* For 4-corner performance improve */
3561 rtl_writephy(tp, 0x1f, 0x0005);
3562 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3563 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3564 rtl_writephy(tp, 0x1f, 0x0000);
3565
3566 /* PHY auto speed down */
3567 rtl_writephy(tp, 0x1f, 0x0004);
3568 rtl_writephy(tp, 0x1f, 0x0007);
3569 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3570 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3571 rtl_writephy(tp, 0x1f, 0x0002);
3572 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3573 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3574
3575 /* improve 10M EEE waveform */
3576 rtl_writephy(tp, 0x1f, 0x0005);
3577 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3578 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3579 rtl_writephy(tp, 0x1f, 0x0000);
3580
3581 /* Improve 2-pair detection performance */
3582 rtl_writephy(tp, 0x1f, 0x0005);
3583 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3584 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3585 rtl_writephy(tp, 0x1f, 0x0000);
3586
3587 /* EEE setting */
1814d6a8 3588 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
70090424
HW		 3589 rtl_writephy(tp, 0x1f, 0x0005);
3590 rtl_writephy(tp, 0x05, 0x8b85);
1814d6a8 3591 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
70090424
HW		 3592 rtl_writephy(tp, 0x1f, 0x0004);
3593 rtl_writephy(tp, 0x1f, 0x0007);
3594 rtl_writephy(tp, 0x1e, 0x0020);
1814d6a8 3595 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
70090424
HW		 3596 rtl_writephy(tp, 0x1f, 0x0002);
3597 rtl_writephy(tp, 0x1f, 0x0000);
3598 rtl_writephy(tp, 0x0d, 0x0007);
3599 rtl_writephy(tp, 0x0e, 0x003c);
3600 rtl_writephy(tp, 0x0d, 0x4007);
1814d6a8 3601 rtl_writephy(tp, 0x0e, 0x0006);
70090424
HW		 3602 rtl_writephy(tp, 0x0d, 0x0000);
3603
3604 /* Green feature */
3605 rtl_writephy(tp, 0x1f, 0x0003);
1814d6a8
HK		 3606 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3607 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
70090424 3608 rtl_writephy(tp, 0x1f, 0x0000);
b399a394
HK		 3609 rtl_writephy(tp, 0x1f, 0x0005);
3610 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3611 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3612
9ecb9aab 3613 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3614 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3615}
3616
5f886e08
HW		 3617static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3618{
3619 /* For 4-corner performance improve */
3620 rtl_writephy(tp, 0x1f, 0x0005);
3621 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3622 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3623 rtl_writephy(tp, 0x1f, 0x0000);
3624
3625 /* PHY auto speed down */
3626 rtl_writephy(tp, 0x1f, 0x0007);
3627 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3628 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3629 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3630 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3631
3632 /* Improve 10M EEE waveform */
3633 rtl_writephy(tp, 0x1f, 0x0005);
3634 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3635 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3636 rtl_writephy(tp, 0x1f, 0x0000);
3637}
3638
c2218925
HW		 3639static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3640{
3641 static const struct phy_reg phy_reg_init[] = {
3642 /* Channel estimation fine tune */
3643 { 0x1f, 0x0003 },
3644 { 0x09, 0xa20f },
3645 { 0x1f, 0x0000 },
3646
3647 /* Modify green table for giga & fnet */
3648 { 0x1f, 0x0005 },
3649 { 0x05, 0x8b55 },
3650 { 0x06, 0x0000 },
3651 { 0x05, 0x8b5e },
3652 { 0x06, 0x0000 },
3653 { 0x05, 0x8b67 },
3654 { 0x06, 0x0000 },
3655 { 0x05, 0x8b70 },
3656 { 0x06, 0x0000 },
3657 { 0x1f, 0x0000 },
3658 { 0x1f, 0x0007 },
3659 { 0x1e, 0x0078 },
3660 { 0x17, 0x0000 },
3661 { 0x19, 0x00fb },
3662 { 0x1f, 0x0000 },
3663
3664 /* Modify green table for 10M */
3665 { 0x1f, 0x0005 },
3666 { 0x05, 0x8b79 },
3667 { 0x06, 0xaa00 },
3668 { 0x1f, 0x0000 },
3669
3670 /* Disable hiimpedance detection (RTCT) */
3671 { 0x1f, 0x0003 },
3672 { 0x01, 0x328a },
3673 { 0x1f, 0x0000 }
3674 };
3675
3676 rtl_apply_firmware(tp);
3677
3678 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3679
5f886e08 3680 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3681
3682 /* Improve 2-pair detection performance */
3683 rtl_writephy(tp, 0x1f, 0x0005);
3684 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3685 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3686 rtl_writephy(tp, 0x1f, 0x0000);
3687}
3688
3689static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3690{
3691 rtl_apply_firmware(tp);
3692
5f886e08 3693 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3694}
3695
b3d7b2f2
HW		 3696static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3697{
b3d7b2f2
HW		 3698 static const struct phy_reg phy_reg_init[] = {
3699 /* Channel estimation fine tune */
3700 { 0x1f, 0x0003 },
3701 { 0x09, 0xa20f },
3702 { 0x1f, 0x0000 },
3703
3704 /* Modify green table for giga & fnet */
3705 { 0x1f, 0x0005 },
3706 { 0x05, 0x8b55 },
3707 { 0x06, 0x0000 },
3708 { 0x05, 0x8b5e },
3709 { 0x06, 0x0000 },
3710 { 0x05, 0x8b67 },
3711 { 0x06, 0x0000 },
3712 { 0x05, 0x8b70 },
3713 { 0x06, 0x0000 },
3714 { 0x1f, 0x0000 },
3715 { 0x1f, 0x0007 },
3716 { 0x1e, 0x0078 },
3717 { 0x17, 0x0000 },
3718 { 0x19, 0x00aa },
3719 { 0x1f, 0x0000 },
3720
3721 /* Modify green table for 10M */
3722 { 0x1f, 0x0005 },
3723 { 0x05, 0x8b79 },
3724 { 0x06, 0xaa00 },
3725 { 0x1f, 0x0000 },
3726
3727 /* Disable hiimpedance detection (RTCT) */
3728 { 0x1f, 0x0003 },
3729 { 0x01, 0x328a },
3730 { 0x1f, 0x0000 }
3731 };
3732
3733
3734 rtl_apply_firmware(tp);
3735
3736 rtl8168f_hw_phy_config(tp);
3737
3738 /* Improve 2-pair detection performance */
3739 rtl_writephy(tp, 0x1f, 0x0005);
3740 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3741 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3742 rtl_writephy(tp, 0x1f, 0x0000);
3743
3744 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3745
3746 /* Modify green table for giga */
3747 rtl_writephy(tp, 0x1f, 0x0005);
3748 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3749 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3750 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3751 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3752 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3753 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3754 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3755 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3756 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3757 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3758 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3759 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3760 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3761 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3762 rtl_writephy(tp, 0x1f, 0x0000);
3763
3764 /* uc same-seed solution */
3765 rtl_writephy(tp, 0x1f, 0x0005);
3766 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3767 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3768 rtl_writephy(tp, 0x1f, 0x0000);
3769
3770 /* eee setting */
706123d0 3771 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3772 rtl_writephy(tp, 0x1f, 0x0005);
3773 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3774 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3775 rtl_writephy(tp, 0x1f, 0x0004);
3776 rtl_writephy(tp, 0x1f, 0x0007);
3777 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3778 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3779 rtl_writephy(tp, 0x1f, 0x0000);
3780 rtl_writephy(tp, 0x0d, 0x0007);
3781 rtl_writephy(tp, 0x0e, 0x003c);
3782 rtl_writephy(tp, 0x0d, 0x4007);
3783 rtl_writephy(tp, 0x0e, 0x0000);
3784 rtl_writephy(tp, 0x0d, 0x0000);
3785
3786 /* Green feature */
3787 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3788 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3789 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3790 rtl_writephy(tp, 0x1f, 0x0000);
3791}
3792
c558386b
HW		 3793static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3794{
c558386b
HW		 3795 rtl_apply_firmware(tp);
3796
41f44d13 3797 rtl_writephy(tp, 0x1f, 0x0a46);
3798 if (rtl_readphy(tp, 0x10) & 0x0100) {
3799 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3800 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3801 } else {
3802 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3803 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3804 }
c558386b 3805
41f44d13 3806 rtl_writephy(tp, 0x1f, 0x0a46);
3807 if (rtl_readphy(tp, 0x13) & 0x0100) {
3808 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3809 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 3810 } else {
fe7524c0 3811 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3812 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3813 }
c558386b 3814
41f44d13 3815 /* Enable PHY auto speed down */
3816 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3817 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3818
fe7524c0 3819 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3820 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 3821 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3822 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 3823 rtl_writephy(tp, 0x1f, 0x0a43);
3824 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 3825 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3826 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 3827
41f44d13 3828 /* EEE auto-fallback function */
3829 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 3830 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3831
41f44d13 3832 /* Enable UC LPF tune function */
3833 rtl_writephy(tp, 0x1f, 0x0a43);
3834 rtl_writephy(tp, 0x13, 0x8012);
76564428 3835 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 3836
3837 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 3838 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 3839
fe7524c0 3840 /* Improve SWR Efficiency */
3841 rtl_writephy(tp, 0x1f, 0x0bcd);
3842 rtl_writephy(tp, 0x14, 0x5065);
3843 rtl_writephy(tp, 0x14, 0xd065);
3844 rtl_writephy(tp, 0x1f, 0x0bc8);
3845 rtl_writephy(tp, 0x11, 0x5655);
3846 rtl_writephy(tp, 0x1f, 0x0bcd);
3847 rtl_writephy(tp, 0x14, 0x1065);
3848 rtl_writephy(tp, 0x14, 0x9065);
3849 rtl_writephy(tp, 0x14, 0x1065);
3850
1bac1072
DC		 3851 /* Check ALDPS bit, disable it if enabled */
3852 rtl_writephy(tp, 0x1f, 0x0a43);
3853 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3854 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 3855
41f44d13 3856 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3857}
3858
57538c4a 3859static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3860{
3861 rtl_apply_firmware(tp);
3862}
3863
6e1d0b89
CHL		 3864static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3865{
3866 u16 dout_tapbin;
3867 u32 data;
3868
3869 rtl_apply_firmware(tp);
3870
3871 /* CHN EST parameters adjust - giga master */
3872 rtl_writephy(tp, 0x1f, 0x0a43);
3873 rtl_writephy(tp, 0x13, 0x809b);
76564428 3874 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 3875 rtl_writephy(tp, 0x13, 0x80a2);
76564428 3876 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 3877 rtl_writephy(tp, 0x13, 0x80a4);
76564428 3878 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 3879 rtl_writephy(tp, 0x13, 0x809c);
76564428 3880 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 3881 rtl_writephy(tp, 0x1f, 0x0000);
3882
3883 /* CHN EST parameters adjust - giga slave */
3884 rtl_writephy(tp, 0x1f, 0x0a43);
3885 rtl_writephy(tp, 0x13, 0x80ad);
76564428 3886 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 3887 rtl_writephy(tp, 0x13, 0x80b4);
76564428 3888 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 3889 rtl_writephy(tp, 0x13, 0x80ac);
76564428 3890 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 3891 rtl_writephy(tp, 0x1f, 0x0000);
3892
3893 /* CHN EST parameters adjust - fnet */
3894 rtl_writephy(tp, 0x1f, 0x0a43);
3895 rtl_writephy(tp, 0x13, 0x808e);
76564428 3896 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 3897 rtl_writephy(tp, 0x13, 0x8090);
76564428 3898 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 3899 rtl_writephy(tp, 0x13, 0x8092);
76564428 3900 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 3901 rtl_writephy(tp, 0x1f, 0x0000);
3902
3903 /* enable R-tune & PGA-retune function */
3904 dout_tapbin = 0;
3905 rtl_writephy(tp, 0x1f, 0x0a46);
3906 data = rtl_readphy(tp, 0x13);
3907 data &= 3;
3908 data <<= 2;
3909 dout_tapbin |= data;
3910 data = rtl_readphy(tp, 0x12);
3911 data &= 0xc000;
3912 data >>= 14;
3913 dout_tapbin |= data;
3914 dout_tapbin = ~(dout_tapbin^0x08);
3915 dout_tapbin <<= 12;
3916 dout_tapbin &= 0xf000;
3917 rtl_writephy(tp, 0x1f, 0x0a43);
3918 rtl_writephy(tp, 0x13, 0x827a);
76564428 3919 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3920 rtl_writephy(tp, 0x13, 0x827b);
76564428 3921 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3922 rtl_writephy(tp, 0x13, 0x827c);
76564428 3923 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3924 rtl_writephy(tp, 0x13, 0x827d);
76564428 3925 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 3926
3927 rtl_writephy(tp, 0x1f, 0x0a43);
3928 rtl_writephy(tp, 0x13, 0x0811);
76564428 3929 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3930 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3931 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3932 rtl_writephy(tp, 0x1f, 0x0000);
3933
3934 /* enable GPHY 10M */
3935 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3936 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3937 rtl_writephy(tp, 0x1f, 0x0000);
3938
3939 /* SAR ADC performance */
3940 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 3941 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 3942 rtl_writephy(tp, 0x1f, 0x0000);
3943
3944 rtl_writephy(tp, 0x1f, 0x0a43);
3945 rtl_writephy(tp, 0x13, 0x803f);
76564428 3946 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3947 rtl_writephy(tp, 0x13, 0x8047);
76564428 3948 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3949 rtl_writephy(tp, 0x13, 0x804f);
76564428 3950 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3951 rtl_writephy(tp, 0x13, 0x8057);
76564428 3952 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3953 rtl_writephy(tp, 0x13, 0x805f);
76564428 3954 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3955 rtl_writephy(tp, 0x13, 0x8067);
76564428 3956 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3957 rtl_writephy(tp, 0x13, 0x806f);
76564428 3958 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 3959 rtl_writephy(tp, 0x1f, 0x0000);
3960
3961 /* disable phy pfm mode */
3962 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3963 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3964 rtl_writephy(tp, 0x1f, 0x0000);
3965
3966 /* Check ALDPS bit, disable it if enabled */
3967 rtl_writephy(tp, 0x1f, 0x0a43);
3968 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3969 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3970
3971 rtl_writephy(tp, 0x1f, 0x0000);
3972}
3973
3974static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3975{
3976 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3977 u16 rlen;
3978 u32 data;
3979
3980 rtl_apply_firmware(tp);
3981
3982 /* CHIN EST parameter update */
3983 rtl_writephy(tp, 0x1f, 0x0a43);
3984 rtl_writephy(tp, 0x13, 0x808a);
76564428 3985 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 3986 rtl_writephy(tp, 0x1f, 0x0000);
3987
3988 /* enable R-tune & PGA-retune function */
3989 rtl_writephy(tp, 0x1f, 0x0a43);
3990 rtl_writephy(tp, 0x13, 0x0811);
76564428 3991 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3992 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3993 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3994 rtl_writephy(tp, 0x1f, 0x0000);
3995
3996 /* enable GPHY 10M */
3997 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3998 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3999 rtl_writephy(tp, 0x1f, 0x0000);
4000
4001 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
4002 data = r8168_mac_ocp_read(tp, 0xdd02);
4003 ioffset_p3 = ((data & 0x80)>>7);
4004 ioffset_p3 <<= 3;
4005
4006 data = r8168_mac_ocp_read(tp, 0xdd00);
4007 ioffset_p3 |= ((data & (0xe000))>>13);
4008 ioffset_p2 = ((data & (0x1e00))>>9);
4009 ioffset_p1 = ((data & (0x01e0))>>5);
4010 ioffset_p0 = ((data & 0x0010)>>4);
4011 ioffset_p0 <<= 3;
4012 ioffset_p0 |= (data & (0x07));
4013 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
4014
05b9687b 4015 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
e2e2788e 4016 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
6e1d0b89
CHL		 4017 rtl_writephy(tp, 0x1f, 0x0bcf);
4018 rtl_writephy(tp, 0x16, data);
4019 rtl_writephy(tp, 0x1f, 0x0000);
4020 }
4021
4022 /* Modify rlen (TX LPF corner frequency) level */
4023 rtl_writephy(tp, 0x1f, 0x0bcd);
4024 data = rtl_readphy(tp, 0x16);
4025 data &= 0x000f;
4026 rlen = 0;
4027 if (data > 3)
4028 rlen = data - 3;
4029 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
4030 rtl_writephy(tp, 0x17, data);
4031 rtl_writephy(tp, 0x1f, 0x0bcd);
4032 rtl_writephy(tp, 0x1f, 0x0000);
4033
4034 /* disable phy pfm mode */
4035 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 4036 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 4037 rtl_writephy(tp, 0x1f, 0x0000);
4038
4039 /* Check ALDPS bit, disable it if enabled */
4040 rtl_writephy(tp, 0x1f, 0x0a43);
4041 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 4042 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 4043
4044 rtl_writephy(tp, 0x1f, 0x0000);
4045}
4046
935e2218
CHL		 4047static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4048{
4049 /* Enable PHY auto speed down */
4050 rtl_writephy(tp, 0x1f, 0x0a44);
4051 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4052 rtl_writephy(tp, 0x1f, 0x0000);
4053
4054 /* patch 10M & ALDPS */
4055 rtl_writephy(tp, 0x1f, 0x0bcc);
4056 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4057 rtl_writephy(tp, 0x1f, 0x0a44);
4058 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4059 rtl_writephy(tp, 0x1f, 0x0a43);
4060 rtl_writephy(tp, 0x13, 0x8084);
4061 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4062 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4063 rtl_writephy(tp, 0x1f, 0x0000);
4064
4065 /* Enable EEE auto-fallback function */
4066 rtl_writephy(tp, 0x1f, 0x0a4b);
4067 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4068 rtl_writephy(tp, 0x1f, 0x0000);
4069
4070 /* Enable UC LPF tune function */
4071 rtl_writephy(tp, 0x1f, 0x0a43);
4072 rtl_writephy(tp, 0x13, 0x8012);
4073 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4074 rtl_writephy(tp, 0x1f, 0x0000);
4075
4076 /* set rg_sel_sdm_rate */
4077 rtl_writephy(tp, 0x1f, 0x0c42);
4078 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4079 rtl_writephy(tp, 0x1f, 0x0000);
4080
4081 /* Check ALDPS bit, disable it if enabled */
4082 rtl_writephy(tp, 0x1f, 0x0a43);
4083 if (rtl_readphy(tp, 0x10) & 0x0004)
4084 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4085
4086 rtl_writephy(tp, 0x1f, 0x0000);
4087}
4088
4089static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4090{
4091 /* patch 10M & ALDPS */
4092 rtl_writephy(tp, 0x1f, 0x0bcc);
4093 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4094 rtl_writephy(tp, 0x1f, 0x0a44);
4095 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4096 rtl_writephy(tp, 0x1f, 0x0a43);
4097 rtl_writephy(tp, 0x13, 0x8084);
4098 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4099 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4100 rtl_writephy(tp, 0x1f, 0x0000);
4101
4102 /* Enable UC LPF tune function */
4103 rtl_writephy(tp, 0x1f, 0x0a43);
4104 rtl_writephy(tp, 0x13, 0x8012);
4105 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4106 rtl_writephy(tp, 0x1f, 0x0000);
4107
4108 /* Set rg_sel_sdm_rate */
4109 rtl_writephy(tp, 0x1f, 0x0c42);
4110 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4111 rtl_writephy(tp, 0x1f, 0x0000);
4112
4113 /* Channel estimation parameters */
4114 rtl_writephy(tp, 0x1f, 0x0a43);
4115 rtl_writephy(tp, 0x13, 0x80f3);
4116 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4117 rtl_writephy(tp, 0x13, 0x80f0);
4118 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4119 rtl_writephy(tp, 0x13, 0x80ef);
4120 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4121 rtl_writephy(tp, 0x13, 0x80f6);
4122 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4123 rtl_writephy(tp, 0x13, 0x80ec);
4124 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4125 rtl_writephy(tp, 0x13, 0x80ed);
4126 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4127 rtl_writephy(tp, 0x13, 0x80f2);
4128 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4129 rtl_writephy(tp, 0x13, 0x80f4);
4130 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4131 rtl_writephy(tp, 0x1f, 0x0a43);
4132 rtl_writephy(tp, 0x13, 0x8110);
4133 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4134 rtl_writephy(tp, 0x13, 0x810f);
4135 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4136 rtl_writephy(tp, 0x13, 0x8111);
4137 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4138 rtl_writephy(tp, 0x13, 0x8113);
4139 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4140 rtl_writephy(tp, 0x13, 0x8115);
4141 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4142 rtl_writephy(tp, 0x13, 0x810e);
4143 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4144 rtl_writephy(tp, 0x13, 0x810c);
4145 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4146 rtl_writephy(tp, 0x13, 0x810b);
4147 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4148 rtl_writephy(tp, 0x1f, 0x0a43);
4149 rtl_writephy(tp, 0x13, 0x80d1);
4150 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4151 rtl_writephy(tp, 0x13, 0x80cd);
4152 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4153 rtl_writephy(tp, 0x13, 0x80d3);
4154 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4155 rtl_writephy(tp, 0x13, 0x80d5);
4156 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4157 rtl_writephy(tp, 0x13, 0x80d7);
4158 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4159
4160 /* Force PWM-mode */
4161 rtl_writephy(tp, 0x1f, 0x0bcd);
4162 rtl_writephy(tp, 0x14, 0x5065);
4163 rtl_writephy(tp, 0x14, 0xd065);
4164 rtl_writephy(tp, 0x1f, 0x0bc8);
4165 rtl_writephy(tp, 0x12, 0x00ed);
4166 rtl_writephy(tp, 0x1f, 0x0bcd);
4167 rtl_writephy(tp, 0x14, 0x1065);
4168 rtl_writephy(tp, 0x14, 0x9065);
4169 rtl_writephy(tp, 0x14, 0x1065);
4170 rtl_writephy(tp, 0x1f, 0x0000);
4171
4172 /* Check ALDPS bit, disable it if enabled */
4173 rtl_writephy(tp, 0x1f, 0x0a43);
4174 if (rtl_readphy(tp, 0x10) & 0x0004)
4175 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4176
4177 rtl_writephy(tp, 0x1f, 0x0000);
4178}
4179
4da19633 4180static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 4181{
350f7596 4182 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 4183 { 0x1f, 0x0003 },
4184 { 0x08, 0x441d },
4185 { 0x01, 0x9100 },
4186 { 0x1f, 0x0000 }
4187 };
4188
4da19633 4189 rtl_writephy(tp, 0x1f, 0x0000);
4190 rtl_patchphy(tp, 0x11, 1 << 12);
4191 rtl_patchphy(tp, 0x19, 1 << 13);
4192 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 4193
4da19633 4194 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 4195}
4196
5a5e4443
HW		 4197static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4198{
4199 static const struct phy_reg phy_reg_init[] = {
4200 { 0x1f, 0x0005 },
4201 { 0x1a, 0x0000 },
4202 { 0x1f, 0x0000 },
4203
4204 { 0x1f, 0x0004 },
4205 { 0x1c, 0x0000 },
4206 { 0x1f, 0x0000 },
4207
4208 { 0x1f, 0x0001 },
4209 { 0x15, 0x7701 },
4210 { 0x1f, 0x0000 }
4211 };
4212
4213 /* Disable ALDPS before ram code */
eef63cc1
FR		 4214 rtl_writephy(tp, 0x1f, 0x0000);
4215 rtl_writephy(tp, 0x18, 0x0310);
4216 msleep(100);
5a5e4443 4217
953a12cc 4218 rtl_apply_firmware(tp);
5a5e4443
HW		 4219
4220 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4221}
4222
7e18dca1
HW		 4223static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4224{
7e18dca1 4225 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 4226 rtl_writephy(tp, 0x1f, 0x0000);
4227 rtl_writephy(tp, 0x18, 0x0310);
4228 msleep(20);
7e18dca1
HW		 4229
4230 rtl_apply_firmware(tp);
4231
4232 /* EEE setting */
fdf6fc06 4233 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 4234 rtl_writephy(tp, 0x1f, 0x0004);
4235 rtl_writephy(tp, 0x10, 0x401f);
4236 rtl_writephy(tp, 0x19, 0x7030);
4237 rtl_writephy(tp, 0x1f, 0x0000);
4238}
4239
5598bfe5
HW		 4240static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4241{
5598bfe5
HW		 4242 static const struct phy_reg phy_reg_init[] = {
4243 { 0x1f, 0x0004 },
4244 { 0x10, 0xc07f },
4245 { 0x19, 0x7030 },
4246 { 0x1f, 0x0000 }
4247 };
4248
4249 /* Disable ALDPS before ram code */
eef63cc1
FR		 4250 rtl_writephy(tp, 0x1f, 0x0000);
4251 rtl_writephy(tp, 0x18, 0x0310);
4252 msleep(100);
5598bfe5
HW		 4253
4254 rtl_apply_firmware(tp);
4255
fdf6fc06 4256 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4257 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4258
fdf6fc06 4259 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4260}
4261
5615d9f1
FR		 4262static void rtl_hw_phy_config(struct net_device *dev)
4263{
4264 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 4265
4266 rtl8169_print_mac_version(tp);
4267
4268 switch (tp->mac_version) {
4269 case RTL_GIGA_MAC_VER_01:
4270 break;
4271 case RTL_GIGA_MAC_VER_02:
4272 case RTL_GIGA_MAC_VER_03:
4da19633 4273 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 4274 break;
4275 case RTL_GIGA_MAC_VER_04:
4da19633 4276 rtl8169sb_hw_phy_config(tp);
5615d9f1 4277 break;
2e955856 4278 case RTL_GIGA_MAC_VER_05:
4da19633 4279 rtl8169scd_hw_phy_config(tp);
2e955856 4280 break;
8c7006aa 4281 case RTL_GIGA_MAC_VER_06:
4da19633 4282 rtl8169sce_hw_phy_config(tp);
8c7006aa 4283 break;
2857ffb7
FR		 4284 case RTL_GIGA_MAC_VER_07:
4285 case RTL_GIGA_MAC_VER_08:
4286 case RTL_GIGA_MAC_VER_09:
4da19633 4287 rtl8102e_hw_phy_config(tp);
2857ffb7 4288 break;
236b8082 4289 case RTL_GIGA_MAC_VER_11:
4da19633 4290 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 4291 break;
4292 case RTL_GIGA_MAC_VER_12:
4da19633 4293 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 4294 break;
4295 case RTL_GIGA_MAC_VER_17:
4da19633 4296 rtl8168bef_hw_phy_config(tp);
236b8082 4297 break;
867763c1 4298 case RTL_GIGA_MAC_VER_18:
4da19633 4299 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 4300 break;
4301 case RTL_GIGA_MAC_VER_19:
4da19633 4302 rtl8168c_1_hw_phy_config(tp);
867763c1 4303 break;
7da97ec9 4304 case RTL_GIGA_MAC_VER_20:
4da19633 4305 rtl8168c_2_hw_phy_config(tp);
7da97ec9 4306 break;
197ff761 4307 case RTL_GIGA_MAC_VER_21:
4da19633 4308 rtl8168c_3_hw_phy_config(tp);
197ff761 4309 break;
6fb07058 4310 case RTL_GIGA_MAC_VER_22:
4da19633 4311 rtl8168c_4_hw_phy_config(tp);
6fb07058 4312 break;
ef3386f0 4313 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 4314 case RTL_GIGA_MAC_VER_24:
4da19633 4315 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 4316 break;
5b538df9 4317 case RTL_GIGA_MAC_VER_25:
bca03d5f 4318 rtl8168d_1_hw_phy_config(tp);
daf9df6d 4319 break;
4320 case RTL_GIGA_MAC_VER_26:
bca03d5f 4321 rtl8168d_2_hw_phy_config(tp);
daf9df6d 4322 break;
4323 case RTL_GIGA_MAC_VER_27:
4da19633 4324 rtl8168d_3_hw_phy_config(tp);
5b538df9 4325 break;
e6de30d6 4326 case RTL_GIGA_MAC_VER_28:
4327 rtl8168d_4_hw_phy_config(tp);
4328 break;
5a5e4443
HW		 4329 case RTL_GIGA_MAC_VER_29:
4330 case RTL_GIGA_MAC_VER_30:
4331 rtl8105e_hw_phy_config(tp);
4332 break;
cecb5fd7
FR		 4333 case RTL_GIGA_MAC_VER_31:
4334 /* None. */
4335 break;
01dc7fec 4336 case RTL_GIGA_MAC_VER_32:
01dc7fec 4337 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4338 rtl8168e_1_hw_phy_config(tp);
4339 break;
4340 case RTL_GIGA_MAC_VER_34:
4341 rtl8168e_2_hw_phy_config(tp);
01dc7fec 4342 break;
c2218925
HW		 4343 case RTL_GIGA_MAC_VER_35:
4344 rtl8168f_1_hw_phy_config(tp);
4345 break;
4346 case RTL_GIGA_MAC_VER_36:
4347 rtl8168f_2_hw_phy_config(tp);
4348 break;
ef3386f0 4349
7e18dca1
HW		 4350 case RTL_GIGA_MAC_VER_37:
4351 rtl8402_hw_phy_config(tp);
4352 break;
4353
b3d7b2f2
HW		 4354 case RTL_GIGA_MAC_VER_38:
4355 rtl8411_hw_phy_config(tp);
4356 break;
4357
5598bfe5
HW		 4358 case RTL_GIGA_MAC_VER_39:
4359 rtl8106e_hw_phy_config(tp);
4360 break;
4361
c558386b
HW		 4362 case RTL_GIGA_MAC_VER_40:
4363 rtl8168g_1_hw_phy_config(tp);
4364 break;
57538c4a 4365 case RTL_GIGA_MAC_VER_42:
58152cd4 4366 case RTL_GIGA_MAC_VER_43:
45dd95c4 4367 case RTL_GIGA_MAC_VER_44:
57538c4a 4368 rtl8168g_2_hw_phy_config(tp);
4369 break;
6e1d0b89
CHL		 4370 case RTL_GIGA_MAC_VER_45:
4371 case RTL_GIGA_MAC_VER_47:
4372 rtl8168h_1_hw_phy_config(tp);
4373 break;
4374 case RTL_GIGA_MAC_VER_46:
4375 case RTL_GIGA_MAC_VER_48:
4376 rtl8168h_2_hw_phy_config(tp);
4377 break;
c558386b 4378
935e2218
CHL		 4379 case RTL_GIGA_MAC_VER_49:
4380 rtl8168ep_1_hw_phy_config(tp);
4381 break;
4382 case RTL_GIGA_MAC_VER_50:
4383 case RTL_GIGA_MAC_VER_51:
4384 rtl8168ep_2_hw_phy_config(tp);
4385 break;
4386
c558386b 4387 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 4388 default:
4389 break;
4390 }
4391}
4392
da78dbff 4393static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 4394{
1da177e4 4395 struct timer_list *timer = &tp->timer;
1da177e4
LT		 4396 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4397
4da19633 4398 if (tp->phy_reset_pending(tp)) {
5b0384f4 4399 /*
1da177e4
LT		 4400 * A busy loop could burn quite a few cycles on nowadays CPU.
4401 * Let's delay the execution of the timer for a few ticks.
4402 */
4403 timeout = HZ/10;
4404 goto out_mod_timer;
4405 }
4406
1ef7286e 4407 if (tp->link_ok(tp))
da78dbff 4408 return;
1da177e4 4409
9bb8eeb5 4410 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 4411
4da19633 4412 tp->phy_reset_enable(tp);
1da177e4
LT		 4413
4414out_mod_timer:
4415 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 4416}
4417
4418static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4419{
da78dbff
FR		 4420 if (!test_and_set_bit(flag, tp->wk.flags))
4421 schedule_work(&tp->wk.work);
da78dbff
FR		 4422}
4423
9de36ccf 4424static void rtl8169_phy_timer(struct timer_list *t)
da78dbff 4425{
9de36ccf 4426 struct rtl8169_private *tp = from_timer(tp, t, timer);
da78dbff 4427
98ddf986 4428 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 4429}
4430
ffc46952
FR		 4431DECLARE_RTL_COND(rtl_phy_reset_cond)
4432{
4433 return tp->phy_reset_pending(tp);
4434}
4435
bf793295
FR		 4436static void rtl8169_phy_reset(struct net_device *dev,
4437 struct rtl8169_private *tp)
4438{
4da19633 4439 tp->phy_reset_enable(tp);
ffc46952 4440 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 4441}
4442
2544bfc0
FR		 4443static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4444{
2544bfc0 4445 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
1ef7286e 4446 (RTL_R8(tp, PHYstatus) & TBI_Enable);
2544bfc0
FR		 4447}
4448
4ff96fa6
FR		 4449static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4450{
5615d9f1 4451 rtl_hw_phy_config(dev);
4ff96fa6 4452
77332894 4453 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
49d17512
HK		 4454 netif_dbg(tp, drv, dev,
4455 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 4456 RTL_W8(tp, 0x82, 0x01);
77332894 4457 }
4ff96fa6 4458
6dccd16b
FR		 4459 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4460
4461 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4462 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4463
bcf0bf90 4464 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
49d17512
HK		 4465 netif_dbg(tp, drv, dev,
4466 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 4467 RTL_W8(tp, 0x82, 0x01);
49d17512
HK		 4468 netif_dbg(tp, drv, dev,
4469 "Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4470 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4471 }
4472
bf793295
FR		 4473 rtl8169_phy_reset(dev, tp);
4474
54405cde 4475 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 4476 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4477 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4478 (tp->mii.supports_gmii ?
4479 ADVERTISED_1000baseT_Half |
4480 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 4481
2544bfc0 4482 if (rtl_tbi_enabled(tp))
bf82c189 4483 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 4484}
4485
773d2021
FR		 4486static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4487{
da78dbff 4488 rtl_lock_work(tp);
773d2021 4489
1ef7286e 4490 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
908ba2bf 4491
1ef7286e
AS		 4492 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4493 RTL_R32(tp, MAC4);
908ba2bf 4494
1ef7286e
AS		 4495 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4496 RTL_R32(tp, MAC0);
908ba2bf 4497
9ecb9aab 4498 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4499 rtl_rar_exgmac_set(tp, addr);
c28aa385 4500
1ef7286e 4501 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
773d2021 4502
da78dbff 4503 rtl_unlock_work(tp);
773d2021
FR		 4504}
4505
4506static int rtl_set_mac_address(struct net_device *dev, void *p)
4507{
4508 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 4509 struct device *d = tp_to_dev(tp);
1f7aa2bc 4510 int ret;
773d2021 4511
1f7aa2bc
HK		 4512 ret = eth_mac_addr(dev, p);
4513 if (ret)
4514 return ret;
773d2021 4515
f51d4a10
CHL		 4516 pm_runtime_get_noresume(d);
4517
4518 if (pm_runtime_active(d))
4519 rtl_rar_set(tp, dev->dev_addr);
4520
4521 pm_runtime_put_noidle(d);
773d2021
FR		 4522
4523 return 0;
4524}
4525
5f787a1a
FR		 4526static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4527{
4528 struct rtl8169_private *tp = netdev_priv(dev);
4529 struct mii_ioctl_data *data = if_mii(ifr);
4530
8b4ab28d
FR		 4531 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4532}
5f787a1a 4533
cecb5fd7
FR		 4534static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4535 struct mii_ioctl_data *data, int cmd)
8b4ab28d 4536{
5f787a1a
FR		 4537 switch (cmd) {
4538 case SIOCGMIIPHY:
4539 data->phy_id = 32; /* Internal PHY */
4540 return 0;
4541
4542 case SIOCGMIIREG:
4da19633 4543 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 4544 return 0;
4545
4546 case SIOCSMIIREG:
4da19633 4547 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 4548 return 0;
4549 }
4550 return -EOPNOTSUPP;
4551}
4552
8b4ab28d
FR		 4553static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4554{
4555 return -EOPNOTSUPP;
4556}
4557
baf63293 4558static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4559{
4560 struct mdio_ops *ops = &tp->mdio_ops;
4561
4562 switch (tp->mac_version) {
4563 case RTL_GIGA_MAC_VER_27:
4564 ops->write = r8168dp_1_mdio_write;
4565 ops->read = r8168dp_1_mdio_read;
4566 break;
e6de30d6 4567 case RTL_GIGA_MAC_VER_28:
4804b3b3 4568 case RTL_GIGA_MAC_VER_31:
e6de30d6 4569 ops->write = r8168dp_2_mdio_write;
4570 ops->read = r8168dp_2_mdio_read;
4571 break;
2a71883c 4572 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
c558386b
HW		 4573 ops->write = r8168g_mdio_write;
4574 ops->read = r8168g_mdio_read;
4575 break;
c0e45c1c 4576 default:
4577 ops->write = r8169_mdio_write;
4578 ops->read = r8169_mdio_read;
4579 break;
4580 }
4581}
4582
e2409d83 4583static void rtl_speed_down(struct rtl8169_private *tp)
4584{
4585 u32 adv;
4586 int lpa;
4587
4588 rtl_writephy(tp, 0x1f, 0x0000);
4589 lpa = rtl_readphy(tp, MII_LPA);
4590
4591 if (lpa & (LPA_10HALF | LPA_10FULL))
4592 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4593 else if (lpa & (LPA_100HALF | LPA_100FULL))
4594 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4595 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4596 else
4597 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4598 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4599 (tp->mii.supports_gmii ?
4600 ADVERTISED_1000baseT_Half |
4601 ADVERTISED_1000baseT_Full : 0);
4602
4603 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4604 adv);
4605}
4606
649b3b8c 4607static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4608{
649b3b8c 4609 switch (tp->mac_version) {
b00e69de
CB		 4610 case RTL_GIGA_MAC_VER_25:
4611 case RTL_GIGA_MAC_VER_26:
649b3b8c 4612 case RTL_GIGA_MAC_VER_29:
4613 case RTL_GIGA_MAC_VER_30:
4614 case RTL_GIGA_MAC_VER_32:
4615 case RTL_GIGA_MAC_VER_33:
4616 case RTL_GIGA_MAC_VER_34:
2a71883c 4617 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4618 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
649b3b8c 4619 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4620 break;
4621 default:
4622 break;
4623 }
4624}
4625
4626static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4627{
fe87bef0 4628 if (!netif_running(tp->dev) || !tp->saved_wolopts)
649b3b8c 4629 return false;
4630
e2409d83 4631 rtl_speed_down(tp);
649b3b8c 4632 rtl_wol_suspend_quirk(tp);
4633
4634 return true;
4635}
4636
065c27c1 4637static void r8168_phy_power_up(struct rtl8169_private *tp)
4638{
4639 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4640 switch (tp->mac_version) {
4641 case RTL_GIGA_MAC_VER_11:
4642 case RTL_GIGA_MAC_VER_12:
2a71883c 4643 case RTL_GIGA_MAC_VER_17 ... RTL_GIGA_MAC_VER_28:
01dc7fec 4644 case RTL_GIGA_MAC_VER_31:
4645 rtl_writephy(tp, 0x0e, 0x0000);
4646 break;
4647 default:
4648 break;
4649 }
065c27c1 4650 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
b2d6cee1
DM		 4651
4652 /* give MAC/PHY some time to resume */
4653 msleep(20);
065c27c1 4654}
4655
4656static void r8168_phy_power_down(struct rtl8169_private *tp)
4657{
4658 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4659 switch (tp->mac_version) {
4660 case RTL_GIGA_MAC_VER_32:
4661 case RTL_GIGA_MAC_VER_33:
beb330a4 4662 case RTL_GIGA_MAC_VER_40:
4663 case RTL_GIGA_MAC_VER_41:
01dc7fec 4664 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4665 break;
4666
4667 case RTL_GIGA_MAC_VER_11:
4668 case RTL_GIGA_MAC_VER_12:
2a71883c 4669 case RTL_GIGA_MAC_VER_17 ... RTL_GIGA_MAC_VER_28:
01dc7fec 4670 case RTL_GIGA_MAC_VER_31:
4671 rtl_writephy(tp, 0x0e, 0x0200);
4672 default:
4673 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4674 break;
4675 }
065c27c1 4676}
4677
4678static void r8168_pll_power_down(struct rtl8169_private *tp)
4679{
9dbe7896 4680 if (r8168_check_dash(tp))
065c27c1 4681 return;
4682
01dc7fec 4683 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4684 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4685 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4686
649b3b8c 4687 if (rtl_wol_pll_power_down(tp))
065c27c1 4688 return;
065c27c1 4689
4690 r8168_phy_power_down(tp);
4691
4692 switch (tp->mac_version) {
2a71883c 4693 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4694 case RTL_GIGA_MAC_VER_37:
4695 case RTL_GIGA_MAC_VER_39:
4696 case RTL_GIGA_MAC_VER_43:
42fde737 4697 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4698 case RTL_GIGA_MAC_VER_45:
4699 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4700 case RTL_GIGA_MAC_VER_47:
4701 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4702 case RTL_GIGA_MAC_VER_50:
4703 case RTL_GIGA_MAC_VER_51:
1ef7286e 4704 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
065c27c1 4705 break;
beb330a4 4706 case RTL_GIGA_MAC_VER_40:
4707 case RTL_GIGA_MAC_VER_41:
935e2218 4708 case RTL_GIGA_MAC_VER_49:
706123d0 4709 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 4710 0xfc000000, ERIAR_EXGMAC);
1ef7286e 4711 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
beb330a4 4712 break;
065c27c1 4713 }
4714}
4715
4716static void r8168_pll_power_up(struct rtl8169_private *tp)
4717{
065c27c1 4718 switch (tp->mac_version) {
2a71883c 4719 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4720 case RTL_GIGA_MAC_VER_37:
4721 case RTL_GIGA_MAC_VER_39:
4722 case RTL_GIGA_MAC_VER_43:
1ef7286e 4723 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
065c27c1 4724 break;
42fde737 4725 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4726 case RTL_GIGA_MAC_VER_45:
4727 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4728 case RTL_GIGA_MAC_VER_47:
4729 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4730 case RTL_GIGA_MAC_VER_50:
4731 case RTL_GIGA_MAC_VER_51:
1ef7286e 4732 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
6e1d0b89 4733 break;
beb330a4 4734 case RTL_GIGA_MAC_VER_40:
4735 case RTL_GIGA_MAC_VER_41:
935e2218 4736 case RTL_GIGA_MAC_VER_49:
1ef7286e 4737 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
706123d0 4738 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 4739 0x00000000, ERIAR_EXGMAC);
4740 break;
065c27c1 4741 }
4742
4743 r8168_phy_power_up(tp);
4744}
4745
065c27c1 4746static void rtl_pll_power_down(struct rtl8169_private *tp)
4747{
4f447d29
HK		 4748 switch (tp->mac_version) {
4749 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4750 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4751 break;
4752 default:
4753 r8168_pll_power_down(tp);
4754 }
065c27c1 4755}
4756
4757static void rtl_pll_power_up(struct rtl8169_private *tp)
4758{
065c27c1 4759 switch (tp->mac_version) {
4f447d29
HK		 4760 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4761 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
065c27c1 4762 break;
065c27c1 4763 default:
4f447d29 4764 r8168_pll_power_up(tp);
065c27c1 4765 }
4766}
4767
e542a226
HW		 4768static void rtl_init_rxcfg(struct rtl8169_private *tp)
4769{
e542a226 4770 switch (tp->mac_version) {
2a71883c
HK		 4771 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4772 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
1ef7286e 4773 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
e542a226 4774 break;
2a71883c 4775 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
eb2dc35d 4776 case RTL_GIGA_MAC_VER_34:
3ced8c95 4777 case RTL_GIGA_MAC_VER_35:
1ef7286e 4778 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
e542a226 4779 break;
2a71883c 4780 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4781 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 4782 break;
e542a226 4783 default:
1ef7286e 4784 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
e542a226
HW		 4785 break;
4786 }
4787}
4788
92fc43b4
HW		 4789static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4790{
9fba0812 4791 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4792}
4793
d58d46b5
FR		 4794static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4795{
eda40b8c
HK		 4796 if (tp->jumbo_ops.enable) {
4797 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4798 tp->jumbo_ops.enable(tp);
4799 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4800 }
d58d46b5
FR		 4801}
4802
4803static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4804{
eda40b8c
HK		 4805 if (tp->jumbo_ops.disable) {
4806 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4807 tp->jumbo_ops.disable(tp);
4808 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4809 }
d58d46b5
FR		 4810}
4811
4812static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4813{
1ef7286e
AS		 4814 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4815 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
cb73200c 4816 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4817}
4818
4819static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4820{
1ef7286e
AS		 4821 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4822 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
8d98aa39 4823 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4824}
4825
4826static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4827{
1ef7286e 4828 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
d58d46b5
FR		 4829}
4830
4831static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4832{
1ef7286e 4833 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
d58d46b5
FR		 4834}
4835
4836static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4837{
1ef7286e
AS		 4838 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4839 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4840 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
cb73200c 4841 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4842}
4843
4844static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4845{
1ef7286e
AS		 4846 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4847 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4848 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
8d98aa39 4849 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4850}
4851
4852static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4853{
cb73200c 4854 rtl_tx_performance_tweak(tp,
f65d539c 4855 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4856}
4857
4858static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4859{
cb73200c 4860 rtl_tx_performance_tweak(tp,
8d98aa39 4861 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4862}
4863
4864static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4865{
d58d46b5
FR		 4866 r8168b_0_hw_jumbo_enable(tp);
4867
1ef7286e 4868 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
d58d46b5
FR		 4869}
4870
4871static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4872{
d58d46b5
FR		 4873 r8168b_0_hw_jumbo_disable(tp);
4874
1ef7286e 4875 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
d58d46b5
FR		 4876}
4877
baf63293 4878static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4879{
4880 struct jumbo_ops *ops = &tp->jumbo_ops;
4881
4882 switch (tp->mac_version) {
4883 case RTL_GIGA_MAC_VER_11:
4884 ops->disable = r8168b_0_hw_jumbo_disable;
4885 ops->enable = r8168b_0_hw_jumbo_enable;
4886 break;
4887 case RTL_GIGA_MAC_VER_12:
4888 case RTL_GIGA_MAC_VER_17:
4889 ops->disable = r8168b_1_hw_jumbo_disable;
4890 ops->enable = r8168b_1_hw_jumbo_enable;
4891 break;
4892 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4893 case RTL_GIGA_MAC_VER_19:
4894 case RTL_GIGA_MAC_VER_20:
4895 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4896 case RTL_GIGA_MAC_VER_22:
4897 case RTL_GIGA_MAC_VER_23:
4898 case RTL_GIGA_MAC_VER_24:
4899 case RTL_GIGA_MAC_VER_25:
4900 case RTL_GIGA_MAC_VER_26:
4901 ops->disable = r8168c_hw_jumbo_disable;
4902 ops->enable = r8168c_hw_jumbo_enable;
4903 break;
4904 case RTL_GIGA_MAC_VER_27:
4905 case RTL_GIGA_MAC_VER_28:
4906 ops->disable = r8168dp_hw_jumbo_disable;
4907 ops->enable = r8168dp_hw_jumbo_enable;
4908 break;
4909 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4910 case RTL_GIGA_MAC_VER_32:
4911 case RTL_GIGA_MAC_VER_33:
4912 case RTL_GIGA_MAC_VER_34:
4913 ops->disable = r8168e_hw_jumbo_disable;
4914 ops->enable = r8168e_hw_jumbo_enable;
4915 break;
4916
4917 /*
4918 * No action needed for jumbo frames with 8169.
4919 * No jumbo for 810x at all.
4920 */
2a71883c 4921 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 4922 default:
4923 ops->disable = NULL;
4924 ops->enable = NULL;
4925 break;
4926 }
4927}
4928
ffc46952
FR		 4929DECLARE_RTL_COND(rtl_chipcmd_cond)
4930{
1ef7286e 4931 return RTL_R8(tp, ChipCmd) & CmdReset;
ffc46952
FR		 4932}
4933
6f43adc8
FR		 4934static void rtl_hw_reset(struct rtl8169_private *tp)
4935{
1ef7286e 4936 RTL_W8(tp, ChipCmd, CmdReset);
6f43adc8 4937
ffc46952 4938 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4939}
4940
b6ffd97f 4941static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4942{
b6ffd97f
FR		 4943 struct rtl_fw *rtl_fw;
4944 const char *name;
4945 int rc = -ENOMEM;
953a12cc 4946
b6ffd97f
FR		 4947 name = rtl_lookup_firmware_name(tp);
4948 if (!name)
4949 goto out_no_firmware;
953a12cc 4950
b6ffd97f
FR		 4951 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4952 if (!rtl_fw)
4953 goto err_warn;
31bd204f 4954
1e1205b7 4955 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
b6ffd97f
FR		 4956 if (rc < 0)
4957 goto err_free;
4958
fd112f2e
FR		 4959 rc = rtl_check_firmware(tp, rtl_fw);
4960 if (rc < 0)
4961 goto err_release_firmware;
4962
b6ffd97f
FR		 4963 tp->rtl_fw = rtl_fw;
4964out:
4965 return;
4966
fd112f2e
FR		 4967err_release_firmware:
4968 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4969err_free:
4970 kfree(rtl_fw);
4971err_warn:
4972 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4973 name, rc);
4974out_no_firmware:
4975 tp->rtl_fw = NULL;
4976 goto out;
4977}
4978
4979static void rtl_request_firmware(struct rtl8169_private *tp)
4980{
4981 if (IS_ERR(tp->rtl_fw))
4982 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4983}
4984
92fc43b4
HW		 4985static void rtl_rx_close(struct rtl8169_private *tp)
4986{
1ef7286e 4987 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4988}
4989
ffc46952
FR		 4990DECLARE_RTL_COND(rtl_npq_cond)
4991{
1ef7286e 4992 return RTL_R8(tp, TxPoll) & NPQ;
ffc46952
FR		 4993}
4994
4995DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4996{
1ef7286e 4997 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
ffc46952
FR		 4998}
4999
e6de30d6 5000static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4
LT		 5001{
5002 /* Disable interrupts */
811fd301 5003 rtl8169_irq_mask_and_ack(tp);
1da177e4 5004
92fc43b4
HW		 5005 rtl_rx_close(tp);
5006
b2d43e6e
HK		 5007 switch (tp->mac_version) {
5008 case RTL_GIGA_MAC_VER_27:
5009 case RTL_GIGA_MAC_VER_28:
5010 case RTL_GIGA_MAC_VER_31:
ffc46952 5011 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
b2d43e6e
HK		 5012 break;
5013 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
5014 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 5015 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
ffc46952 5016 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
b2d43e6e
HK		 5017 break;
5018 default:
1ef7286e 5019 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
92fc43b4 5020 udelay(100);
b2d43e6e 5021 break;
e6de30d6 5022 }
5023
92fc43b4 5024 rtl_hw_reset(tp);
1da177e4
LT		 5025}
5026
7f796d83 5027static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6 5028{
9cb427b6 5029 /* Set DMA burst size and Interframe Gap Time */
1ef7286e 5030 RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
9cb427b6
FR		 5031 (InterFrameGap << TxInterFrameGapShift));
5032}
5033
4fd48c4a 5034static void rtl_set_rx_max_size(struct rtl8169_private *tp)
1da177e4 5035{
4fd48c4a
HK		 5036 /* Low hurts. Let's disable the filtering. */
5037 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
07ce4064
FR		 5038}
5039
1ef7286e 5040static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
7f796d83
FR		 5041{
5042 /*
5043 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5044 * register to be written before TxDescAddrLow to work.
5045 * Switching from MMIO to I/O access fixes the issue as well.
5046 */
1ef7286e
AS		 5047 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5048 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5049 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5050 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 5051}
5052
1ef7286e 5053static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
6dccd16b 5054{
3744100e 5055 static const struct rtl_cfg2_info {
6dccd16b
FR		 5056 u32 mac_version;
5057 u32 clk;
5058 u32 val;
5059 } cfg2_info [] = {
5060 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5061 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5062 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5063 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 5064 };
5065 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 5066 unsigned int i;
5067 u32 clk;
5068
1ef7286e 5069 clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
cadf1855 5070 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b 5071 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1ef7286e 5072 RTL_W32(tp, 0x7c, p->val);
6dccd16b
FR		 5073 break;
5074 }
5075 }
5076}
5077
e6b763ea
FR		 5078static void rtl_set_rx_mode(struct net_device *dev)
5079{
5080 struct rtl8169_private *tp = netdev_priv(dev);
e6b763ea
FR		 5081 u32 mc_filter[2]; /* Multicast hash filter */
5082 int rx_mode;
5083 u32 tmp = 0;
5084
5085 if (dev->flags & IFF_PROMISC) {
5086 /* Unconditionally log net taps. */
5087 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5088 rx_mode =
5089 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5090 AcceptAllPhys;
5091 mc_filter[1] = mc_filter[0] = 0xffffffff;
5092 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5093 (dev->flags & IFF_ALLMULTI)) {
5094 /* Too many to filter perfectly -- accept all multicasts. */
5095 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5096 mc_filter[1] = mc_filter[0] = 0xffffffff;
5097 } else {
5098 struct netdev_hw_addr *ha;
5099
5100 rx_mode = AcceptBroadcast | AcceptMyPhys;
5101 mc_filter[1] = mc_filter[0] = 0;
5102 netdev_for_each_mc_addr(ha, dev) {
5103 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5104 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5105 rx_mode |= AcceptMulticast;
5106 }
5107 }
5108
5109 if (dev->features & NETIF_F_RXALL)
5110 rx_mode |= (AcceptErr | AcceptRunt);
5111
1ef7286e 5112 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
e6b763ea
FR		 5113
5114 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5115 u32 data = mc_filter[0];
5116
5117 mc_filter[0] = swab32(mc_filter[1]);
5118 mc_filter[1] = swab32(data);
5119 }
5120
0481776b
NW		 5121 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5122 mc_filter[1] = mc_filter[0] = 0xffffffff;
5123
1ef7286e
AS		 5124 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
5125 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
e6b763ea 5126
1ef7286e 5127 RTL_W32(tp, RxConfig, tmp);
e6b763ea
FR		 5128}
5129
52f8560e
HK		 5130static void rtl_hw_start(struct rtl8169_private *tp)
5131{
5132 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
5133
5134 tp->hw_start(tp);
5135
5136 rtl_set_rx_max_size(tp);
5137 rtl_set_rx_tx_desc_registers(tp);
5138 rtl_set_rx_tx_config_registers(tp);
5139 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
5140
5141 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5142 RTL_R8(tp, IntrMask);
5143 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5144 rtl_set_rx_mode(tp->dev);
5145 /* no early-rx interrupts */
5146 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
5147 rtl_irq_enable_all(tp);
5148}
5149
61cb532d 5150static void rtl_hw_start_8169(struct rtl8169_private *tp)
07ce4064 5151{
0ae0974e 5152 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
61cb532d 5153 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
9cb427b6 5154
1ef7286e 5155 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
1da177e4 5156
0ae0974e 5157 tp->cp_cmd |= PCIMulRW;
1da177e4 5158
cecb5fd7
FR		 5159 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5160 tp->mac_version == RTL_GIGA_MAC_VER_03) {
49d17512
HK		 5161 netif_dbg(tp, drv, tp->dev,
5162 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
bcf0bf90 5163 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 5164 }
5165
1ef7286e 5166 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
bcf0bf90 5167
1ef7286e 5168 rtl8169_set_magic_reg(tp, tp->mac_version);
6dccd16b 5169
1da177e4
LT		 5170 /*
5171 * Undocumented corner. Supposedly:
5172 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5173 */
1ef7286e 5174 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4 5175
1ef7286e 5176 RTL_W32(tp, RxMissed, 0);
07ce4064 5177}
1da177e4 5178
ffc46952
FR		 5179DECLARE_RTL_COND(rtl_csiar_cond)
5180{
1ef7286e 5181 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
ffc46952
FR		 5182}
5183
ff1d7331 5184static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
beb1fe18 5185{
ff1d7331 5186 u32 func = PCI_FUNC(tp->pci_dev->devfn);
beb1fe18 5187
1ef7286e
AS		 5188 RTL_W32(tp, CSIDR, value);
5189 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
ff1d7331 5190 CSIAR_BYTE_ENABLE | func << 16);
7e18dca1 5191
ffc46952 5192 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 5193}
5194
ff1d7331 5195static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 5196{
ff1d7331
HK		 5197 u32 func = PCI_FUNC(tp->pci_dev->devfn);
5198
5199 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
5200 CSIAR_BYTE_ENABLE);
7e18dca1 5201
ffc46952 5202 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 5203 RTL_R32(tp, CSIDR) : ~0;
7e18dca1
HW		 5204}
5205
ff1d7331 5206static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
45dd95c4 5207{
ff1d7331
HK		 5208 struct pci_dev *pdev = tp->pci_dev;
5209 u32 csi;
45dd95c4 5210
ff1d7331
HK		 5211 /* According to Realtek the value at config space address 0x070f
5212 * controls the L0s/L1 entrance latency. We try standard ECAM access
5213 * first and if it fails fall back to CSI.
5214 */
5215 if (pdev->cfg_size > 0x070f &&
5216 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
5217 return;
5218
5219 netdev_notice_once(tp->dev,
5220 "No native access to PCI extended config space, falling back to CSI\n");
5221 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5222 rtl_csi_write(tp, 0x070c, csi | val << 24);
45dd95c4 5223}
5224
f37658da 5225static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
beb1fe18 5226{
ff1d7331 5227 rtl_csi_access_enable(tp, 0x27);
dacf8154
FR		 5228}
5229
5230struct ephy_info {
5231 unsigned int offset;
5232 u16 mask;
5233 u16 bits;
5234};
5235
fdf6fc06
FR		 5236static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5237 int len)
dacf8154
FR		 5238{
5239 u16 w;
5240
5241 while (len-- > 0) {
fdf6fc06
FR		 5242 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5243 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 5244 e++;
5245 }
5246}
5247
73c86ee3 5248static void rtl_disable_clock_request(struct rtl8169_private *tp)
b726e493 5249{
73c86ee3 5250 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 5251 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 5252}
5253
73c86ee3 5254static void rtl_enable_clock_request(struct rtl8169_private *tp)
e6de30d6 5255{
73c86ee3 5256 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 5257 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 5258}
5259
b51ecea8 5260static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5261{
b51ecea8 5262 u8 data;
5263
1ef7286e 5264 data = RTL_R8(tp, Config3);
b51ecea8 5265
5266 if (enable)
5267 data |= Rdy_to_L23;
5268 else
5269 data &= ~Rdy_to_L23;
5270
1ef7286e 5271 RTL_W8(tp, Config3, data);
b51ecea8 5272}
5273
a99790bf
KHF		 5274static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
5275{
5276 if (enable) {
5277 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
5278 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
5279 } else {
5280 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5281 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5282 }
5283}
5284
beb1fe18 5285static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 5286{
1ef7286e 5287 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 5288
12d42c50 5289 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 5290 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
b726e493 5291
faf1e785 5292 if (tp->dev->mtu <= ETH_DATA_LEN) {
8d98aa39 5293 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
faf1e785 5294 PCI_EXP_DEVCTL_NOSNOOP_EN);
5295 }
219a1e9d
FR		 5296}
5297
beb1fe18 5298static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 5299{
beb1fe18 5300 rtl_hw_start_8168bb(tp);
b726e493 5301
1ef7286e 5302 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
b726e493 5303
1ef7286e 5304 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
219a1e9d
FR		 5305}
5306
beb1fe18 5307static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 5308{
1ef7286e 5309 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
b726e493 5310
1ef7286e 5311 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 5312
faf1e785 5313 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5314 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
b726e493 5315
73c86ee3 5316 rtl_disable_clock_request(tp);
b726e493 5317
12d42c50 5318 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 5319 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
219a1e9d
FR		 5320}
5321
beb1fe18 5322static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 5323{
350f7596 5324 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 5325 { 0x01, 0, 0x0001 },
5326 { 0x02, 0x0800, 0x1000 },
5327 { 0x03, 0, 0x0042 },
5328 { 0x06, 0x0080, 0x0000 },
5329 { 0x07, 0, 0x2000 }
5330 };
5331
f37658da 5332 rtl_set_def_aspm_entry_latency(tp);
b726e493 5333
fdf6fc06 5334 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 5335
beb1fe18 5336 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5337}
5338
beb1fe18 5339static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 5340{
f37658da 5341 rtl_set_def_aspm_entry_latency(tp);
ef3386f0 5342
1ef7286e 5343 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
ef3386f0 5344
faf1e785 5345 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5346 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
ef3386f0 5347
12d42c50 5348 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 5349 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
ef3386f0
FR		 5350}
5351
beb1fe18 5352static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 5353{
f37658da 5354 rtl_set_def_aspm_entry_latency(tp);
7f3e3d3a 5355
1ef7286e 5356 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
7f3e3d3a
FR		 5357
5358 /* Magic. */
1ef7286e 5359 RTL_W8(tp, DBG_REG, 0x20);
7f3e3d3a 5360
1ef7286e 5361 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
7f3e3d3a 5362
faf1e785 5363 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5364 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7f3e3d3a 5365
12d42c50 5366 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 5367 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
7f3e3d3a
FR		 5368}
5369
beb1fe18 5370static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 5371{
350f7596 5372 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 5373 { 0x02, 0x0800, 0x1000 },
5374 { 0x03, 0, 0x0002 },
5375 { 0x06, 0x0080, 0x0000 }
5376 };
5377
f37658da 5378 rtl_set_def_aspm_entry_latency(tp);
b726e493 5379
1ef7286e 5380 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
b726e493 5381
fdf6fc06 5382 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 5383
beb1fe18 5384 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5385}
5386
beb1fe18 5387static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 5388{
350f7596 5389 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 5390 { 0x01, 0, 0x0001 },
5391 { 0x03, 0x0400, 0x0220 }
5392 };
5393
f37658da 5394 rtl_set_def_aspm_entry_latency(tp);
b726e493 5395
fdf6fc06 5396 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 5397
beb1fe18 5398 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5399}
5400
beb1fe18 5401static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 5402{
beb1fe18 5403 rtl_hw_start_8168c_2(tp);
197ff761
FR		 5404}
5405
beb1fe18 5406static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 5407{
f37658da 5408 rtl_set_def_aspm_entry_latency(tp);
6fb07058 5409
beb1fe18 5410 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 5411}
5412
beb1fe18 5413static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 5414{
f37658da 5415 rtl_set_def_aspm_entry_latency(tp);
5b538df9 5416
73c86ee3 5417 rtl_disable_clock_request(tp);
5b538df9 5418
1ef7286e 5419 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5b538df9 5420
faf1e785 5421 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5422 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5b538df9 5423
12d42c50 5424 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 5425 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5b538df9
FR		 5426}
5427
beb1fe18 5428static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 5429{
f37658da 5430 rtl_set_def_aspm_entry_latency(tp);
4804b3b3 5431
faf1e785 5432 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5433 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4804b3b3 5434
1ef7286e 5435 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4804b3b3 5436
73c86ee3 5437 rtl_disable_clock_request(tp);
4804b3b3 5438}
5439
beb1fe18 5440static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 5441{
5442 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 5443 { 0x0b, 0x0000, 0x0048 },
5444 { 0x19, 0x0020, 0x0050 },
5445 { 0x0c, 0x0100, 0x0020 }
e6de30d6 5446 };
e6de30d6 5447
f37658da 5448 rtl_set_def_aspm_entry_latency(tp);
e6de30d6 5449
8d98aa39 5450 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
e6de30d6 5451
1ef7286e 5452 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
e6de30d6 5453
1016a4a1 5454 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
e6de30d6 5455
73c86ee3 5456 rtl_enable_clock_request(tp);
e6de30d6 5457}
5458
beb1fe18 5459static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 5460{
70090424 5461 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5462 { 0x00, 0x0200, 0x0100 },
5463 { 0x00, 0x0000, 0x0004 },
5464 { 0x06, 0x0002, 0x0001 },
5465 { 0x06, 0x0000, 0x0030 },
5466 { 0x07, 0x0000, 0x2000 },
5467 { 0x00, 0x0000, 0x0020 },
5468 { 0x03, 0x5800, 0x2000 },
5469 { 0x03, 0x0000, 0x0001 },
5470 { 0x01, 0x0800, 0x1000 },
5471 { 0x07, 0x0000, 0x4000 },
5472 { 0x1e, 0x0000, 0x2000 },
5473 { 0x19, 0xffff, 0xfe6c },
5474 { 0x0a, 0x0000, 0x0040 }
5475 };
5476
f37658da 5477 rtl_set_def_aspm_entry_latency(tp);
01dc7fec 5478
fdf6fc06 5479 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5480
faf1e785 5481 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5482 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
01dc7fec 5483
1ef7286e 5484 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
01dc7fec 5485
73c86ee3 5486 rtl_disable_clock_request(tp);
01dc7fec 5487
5488 /* Reset tx FIFO pointer */
1ef7286e
AS		 5489 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5490 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
01dc7fec 5491
1ef7286e 5492 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
01dc7fec 5493}
5494
beb1fe18 5495static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424
HW		 5496{
5497 static const struct ephy_info e_info_8168e_2[] = {
5498 { 0x09, 0x0000, 0x0080 },
5499 { 0x19, 0x0000, 0x0224 }
5500 };
5501
f37658da 5502 rtl_set_def_aspm_entry_latency(tp);
70090424 5503
fdf6fc06 5504 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5505
faf1e785 5506 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5507 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
70090424 5508
fdf6fc06
FR		 5509 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5510 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5511 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5512 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5513 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5514 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 5515 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5516 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5517
1ef7286e 5518 RTL_W8(tp, MaxTxPacketSize, EarlySize);
70090424 5519
73c86ee3 5520 rtl_disable_clock_request(tp);
4521e1a9 5521
1ef7286e
AS		 5522 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5523 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
70090424
HW		 5524
5525 /* Adjust EEE LED frequency */
1ef7286e 5526 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
70090424 5527
1ef7286e
AS		 5528 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5529 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5530 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
aa1e7d2c
HK		 5531
5532 rtl_hw_aspm_clkreq_enable(tp, true);
70090424
HW		 5533}
5534
5f886e08 5535static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5536{
f37658da 5537 rtl_set_def_aspm_entry_latency(tp);
c2218925 5538
8d98aa39 5539 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c2218925 5540
fdf6fc06
FR		 5541 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5542 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5543 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5544 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 5545 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5546 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5547 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5548 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5549 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5550 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925 5551
1ef7286e 5552 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c2218925 5553
73c86ee3 5554 rtl_disable_clock_request(tp);
4521e1a9 5555
1ef7286e
AS		 5556 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5557 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5558 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5559 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5560 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
c2218925
HW		 5561}
5562
5f886e08
HW		 5563static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5564{
5f886e08
HW		 5565 static const struct ephy_info e_info_8168f_1[] = {
5566 { 0x06, 0x00c0, 0x0020 },
5567 { 0x08, 0x0001, 0x0002 },
5568 { 0x09, 0x0000, 0x0080 },
5569 { 0x19, 0x0000, 0x0224 }
5570 };
5571
5572 rtl_hw_start_8168f(tp);
5573
fdf6fc06 5574 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5575
706123d0 5576 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5577
5578 /* Adjust EEE LED frequency */
1ef7286e 5579 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5f886e08
HW		 5580}
5581
b3d7b2f2
HW		 5582static void rtl_hw_start_8411(struct rtl8169_private *tp)
5583{
b3d7b2f2
HW		 5584 static const struct ephy_info e_info_8168f_1[] = {
5585 { 0x06, 0x00c0, 0x0020 },
5586 { 0x0f, 0xffff, 0x5200 },
5587 { 0x1e, 0x0000, 0x4000 },
5588 { 0x19, 0x0000, 0x0224 }
5589 };
5590
5591 rtl_hw_start_8168f(tp);
b51ecea8 5592 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 5593
fdf6fc06 5594 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5595
706123d0 5596 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5597}
5598
5fbea337 5599static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b 5600{
1ef7286e 5601 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
beb330a4 5602
c558386b
HW		 5603 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5604 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5605 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5606 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5607
f37658da 5608 rtl_set_def_aspm_entry_latency(tp);
c558386b 5609
8d98aa39 5610 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c558386b 5611
706123d0
CHL		 5612 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5613 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5614 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 5615
1ef7286e
AS		 5616 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5617 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c558386b
HW		 5618
5619 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5620 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5621
5622 /* Adjust EEE LED frequency */
1ef7286e 5623 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
c558386b 5624
706123d0
CHL		 5625 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5626 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 5627
5628 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 5629}
5630
5fbea337
CHL		 5631static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5632{
5fbea337
CHL		 5633 static const struct ephy_info e_info_8168g_1[] = {
5634 { 0x00, 0x0000, 0x0008 },
5635 { 0x0c, 0x37d0, 0x0820 },
5636 { 0x1e, 0x0000, 0x0001 },
5637 { 0x19, 0x8000, 0x0000 }
5638 };
5639
5640 rtl_hw_start_8168g(tp);
5641
5642 /* disable aspm and clock request before access ephy */
a99790bf 5643 rtl_hw_aspm_clkreq_enable(tp, false);
5fbea337 5644 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
a99790bf 5645 rtl_hw_aspm_clkreq_enable(tp, true);
5fbea337
CHL		 5646}
5647
57538c4a 5648static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5649{
57538c4a 5650 static const struct ephy_info e_info_8168g_2[] = {
5651 { 0x00, 0x0000, 0x0008 },
5652 { 0x0c, 0x3df0, 0x0200 },
5653 { 0x19, 0xffff, 0xfc00 },
5654 { 0x1e, 0xffff, 0x20eb }
5655 };
5656
5fbea337 5657 rtl_hw_start_8168g(tp);
57538c4a 5658
5659 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 5660 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5661 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
57538c4a 5662 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5663}
5664
45dd95c4 5665static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5666{
45dd95c4 5667 static const struct ephy_info e_info_8411_2[] = {
5668 { 0x00, 0x0000, 0x0008 },
5669 { 0x0c, 0x3df0, 0x0200 },
5670 { 0x0f, 0xffff, 0x5200 },
5671 { 0x19, 0x0020, 0x0000 },
5672 { 0x1e, 0x0000, 0x2000 }
5673 };
5674
5fbea337 5675 rtl_hw_start_8168g(tp);
45dd95c4 5676
5677 /* disable aspm and clock request before access ephy */
a99790bf 5678 rtl_hw_aspm_clkreq_enable(tp, false);
45dd95c4 5679 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
a99790bf 5680 rtl_hw_aspm_clkreq_enable(tp, true);
45dd95c4 5681}
5682
6e1d0b89
CHL		 5683static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5684{
72521ea0 5685 int rg_saw_cnt;
6e1d0b89
CHL		 5686 u32 data;
5687 static const struct ephy_info e_info_8168h_1[] = {
5688 { 0x1e, 0x0800, 0x0001 },
5689 { 0x1d, 0x0000, 0x0800 },
5690 { 0x05, 0xffff, 0x2089 },
5691 { 0x06, 0xffff, 0x5881 },
5692 { 0x04, 0xffff, 0x154a },
5693 { 0x01, 0xffff, 0x068b }
5694 };
5695
5696 /* disable aspm and clock request before access ephy */
a99790bf 5697 rtl_hw_aspm_clkreq_enable(tp, false);
6e1d0b89
CHL		 5698 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5699
1ef7286e 5700 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6e1d0b89
CHL		 5701
5702 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5703 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5704 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5705 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5706
f37658da 5707 rtl_set_def_aspm_entry_latency(tp);
6e1d0b89 5708
8d98aa39 5709 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6e1d0b89 5710
706123d0
CHL		 5711 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5712 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 5713
706123d0 5714 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 5715
706123d0 5716 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 5717
5718 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5719
1ef7286e
AS		 5720 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5721 RTL_W8(tp, MaxTxPacketSize, EarlySize);
6e1d0b89
CHL		 5722
5723 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5724 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5725
5726 /* Adjust EEE LED frequency */
1ef7286e 5727 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6e1d0b89 5728
1ef7286e
AS		 5729 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5730 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89 5731
1ef7286e 5732 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6e1d0b89 5733
706123d0 5734 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 5735
5736 rtl_pcie_state_l2l3_enable(tp, false);
5737
5738 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 5739 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 5740 rtl_writephy(tp, 0x1f, 0x0000);
5741 if (rg_saw_cnt > 0) {
5742 u16 sw_cnt_1ms_ini;
5743
5744 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5745 sw_cnt_1ms_ini &= 0x0fff;
5746 data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec0 5747 data &= ~0x0fff;
6e1d0b89
CHL		 5748 data |= sw_cnt_1ms_ini;
5749 r8168_mac_ocp_write(tp, 0xd412, data);
5750 }
5751
5752 data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec0
CHL		 5753 data &= ~0xf0;
5754 data |= 0x70;
6e1d0b89
CHL		 5755 r8168_mac_ocp_write(tp, 0xe056, data);
5756
5757 data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec0
CHL		 5758 data &= ~0x6000;
5759 data |= 0x8008;
6e1d0b89
CHL		 5760 r8168_mac_ocp_write(tp, 0xe052, data);
5761
5762 data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec0 5763 data &= ~0x01ff;
6e1d0b89
CHL		 5764 data |= 0x017f;
5765 r8168_mac_ocp_write(tp, 0xe0d6, data);
5766
5767 data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec0 5768 data &= ~0x0fff;
6e1d0b89
CHL		 5769 data |= 0x047f;
5770 r8168_mac_ocp_write(tp, 0xd420, data);
5771
5772 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5773 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5774 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5775 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
a99790bf
KHF		 5776
5777 rtl_hw_aspm_clkreq_enable(tp, true);
6e1d0b89
CHL		 5778}
5779
935e2218
CHL		 5780static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5781{
003609da
CHL		 5782 rtl8168ep_stop_cmac(tp);
5783
1ef7286e 5784 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
935e2218
CHL		 5785
5786 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5787 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5788 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5789 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5790
f37658da 5791 rtl_set_def_aspm_entry_latency(tp);
935e2218 5792
8d98aa39 5793 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
935e2218
CHL		 5794
5795 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5796 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5797
5798 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5799
5800 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5801
1ef7286e
AS		 5802 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5803 RTL_W8(tp, MaxTxPacketSize, EarlySize);
935e2218
CHL		 5804
5805 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5806 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5807
5808 /* Adjust EEE LED frequency */
1ef7286e 5809 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
935e2218
CHL		 5810
5811 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5812
1ef7286e 5813 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
935e2218
CHL		 5814
5815 rtl_pcie_state_l2l3_enable(tp, false);
5816}
5817
5818static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5819{
935e2218
CHL		 5820 static const struct ephy_info e_info_8168ep_1[] = {
5821 { 0x00, 0xffff, 0x10ab },
5822 { 0x06, 0xffff, 0xf030 },
5823 { 0x08, 0xffff, 0x2006 },
5824 { 0x0d, 0xffff, 0x1666 },
5825 { 0x0c, 0x3ff0, 0x0000 }
5826 };
5827
5828 /* disable aspm and clock request before access ephy */
a99790bf 5829 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5830 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5831
5832 rtl_hw_start_8168ep(tp);
a99790bf
KHF		 5833
5834 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5835}
5836
5837static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5838{
935e2218
CHL		 5839 static const struct ephy_info e_info_8168ep_2[] = {
5840 { 0x00, 0xffff, 0x10a3 },
5841 { 0x19, 0xffff, 0xfc00 },
5842 { 0x1e, 0xffff, 0x20ea }
5843 };
5844
5845 /* disable aspm and clock request before access ephy */
a99790bf 5846 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5847 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5848
5849 rtl_hw_start_8168ep(tp);
5850
1ef7286e
AS		 5851 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5852 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
a99790bf
KHF		 5853
5854 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5855}
5856
5857static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5858{
935e2218
CHL		 5859 u32 data;
5860 static const struct ephy_info e_info_8168ep_3[] = {
5861 { 0x00, 0xffff, 0x10a3 },
5862 { 0x19, 0xffff, 0x7c00 },
5863 { 0x1e, 0xffff, 0x20eb },
5864 { 0x0d, 0xffff, 0x1666 }
5865 };
5866
5867 /* disable aspm and clock request before access ephy */
a99790bf 5868 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5869 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5870
5871 rtl_hw_start_8168ep(tp);
5872
1ef7286e
AS		 5873 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5874 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 5875
5876 data = r8168_mac_ocp_read(tp, 0xd3e2);
5877 data &= 0xf000;
5878 data |= 0x0271;
5879 r8168_mac_ocp_write(tp, 0xd3e2, data);
5880
5881 data = r8168_mac_ocp_read(tp, 0xd3e4);
5882 data &= 0xff00;
5883 r8168_mac_ocp_write(tp, 0xd3e4, data);
5884
5885 data = r8168_mac_ocp_read(tp, 0xe860);
5886 data |= 0x0080;
5887 r8168_mac_ocp_write(tp, 0xe860, data);
a99790bf
KHF		 5888
5889 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5890}
5891
61cb532d 5892static void rtl_hw_start_8168(struct rtl8169_private *tp)
07ce4064 5893{
1ef7286e 5894 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
2dd99530 5895
0ae0974e
HK		 5896 tp->cp_cmd &= ~INTT_MASK;
5897 tp->cp_cmd |= PktCntrDisable | INTT_1;
1ef7286e 5898 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2dd99530 5899
1ef7286e 5900 RTL_W16(tp, IntrMitigate, 0x5151);
2dd99530 5901
0e485150 5902 /* Work around for RxFIFO overflow. */
811fd301 5903 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5904 tp->event_slow |= RxFIFOOver | PCSTimeout;
5905 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5906 }
5907
219a1e9d
FR		 5908 switch (tp->mac_version) {
5909 case RTL_GIGA_MAC_VER_11:
beb1fe18 5910 rtl_hw_start_8168bb(tp);
4804b3b3 5911 break;
219a1e9d
FR		 5912
5913 case RTL_GIGA_MAC_VER_12:
5914 case RTL_GIGA_MAC_VER_17:
beb1fe18 5915 rtl_hw_start_8168bef(tp);
4804b3b3 5916 break;
219a1e9d
FR		 5917
5918 case RTL_GIGA_MAC_VER_18:
beb1fe18 5919 rtl_hw_start_8168cp_1(tp);
4804b3b3 5920 break;
219a1e9d
FR		 5921
5922 case RTL_GIGA_MAC_VER_19:
beb1fe18 5923 rtl_hw_start_8168c_1(tp);
4804b3b3 5924 break;
219a1e9d
FR		 5925
5926 case RTL_GIGA_MAC_VER_20:
beb1fe18 5927 rtl_hw_start_8168c_2(tp);
4804b3b3 5928 break;
219a1e9d 5929
197ff761 5930 case RTL_GIGA_MAC_VER_21:
beb1fe18 5931 rtl_hw_start_8168c_3(tp);
4804b3b3 5932 break;
197ff761 5933
6fb07058 5934 case RTL_GIGA_MAC_VER_22:
beb1fe18 5935 rtl_hw_start_8168c_4(tp);
4804b3b3 5936 break;
6fb07058 5937
ef3386f0 5938 case RTL_GIGA_MAC_VER_23:
beb1fe18 5939 rtl_hw_start_8168cp_2(tp);
4804b3b3 5940 break;
ef3386f0 5941
7f3e3d3a 5942 case RTL_GIGA_MAC_VER_24:
beb1fe18 5943 rtl_hw_start_8168cp_3(tp);
4804b3b3 5944 break;
7f3e3d3a 5945
5b538df9 5946 case RTL_GIGA_MAC_VER_25:
daf9df6d 5947 case RTL_GIGA_MAC_VER_26:
5948 case RTL_GIGA_MAC_VER_27:
beb1fe18 5949 rtl_hw_start_8168d(tp);
4804b3b3 5950 break;
5b538df9 5951
e6de30d6 5952 case RTL_GIGA_MAC_VER_28:
beb1fe18 5953 rtl_hw_start_8168d_4(tp);
4804b3b3 5954 break;
cecb5fd7 5955
4804b3b3 5956 case RTL_GIGA_MAC_VER_31:
beb1fe18 5957 rtl_hw_start_8168dp(tp);
4804b3b3 5958 break;
5959
01dc7fec 5960 case RTL_GIGA_MAC_VER_32:
5961 case RTL_GIGA_MAC_VER_33:
beb1fe18 5962 rtl_hw_start_8168e_1(tp);
70090424
HW		 5963 break;
5964 case RTL_GIGA_MAC_VER_34:
beb1fe18 5965 rtl_hw_start_8168e_2(tp);
01dc7fec 5966 break;
e6de30d6 5967
c2218925
HW		 5968 case RTL_GIGA_MAC_VER_35:
5969 case RTL_GIGA_MAC_VER_36:
beb1fe18 5970 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5971 break;
5972
b3d7b2f2
HW		 5973 case RTL_GIGA_MAC_VER_38:
5974 rtl_hw_start_8411(tp);
5975 break;
5976
c558386b
HW		 5977 case RTL_GIGA_MAC_VER_40:
5978 case RTL_GIGA_MAC_VER_41:
5979 rtl_hw_start_8168g_1(tp);
5980 break;
57538c4a 5981 case RTL_GIGA_MAC_VER_42:
5982 rtl_hw_start_8168g_2(tp);
5983 break;
c558386b 5984
45dd95c4 5985 case RTL_GIGA_MAC_VER_44:
5986 rtl_hw_start_8411_2(tp);
5987 break;
5988
6e1d0b89
CHL		 5989 case RTL_GIGA_MAC_VER_45:
5990 case RTL_GIGA_MAC_VER_46:
5991 rtl_hw_start_8168h_1(tp);
5992 break;
5993
935e2218
CHL		 5994 case RTL_GIGA_MAC_VER_49:
5995 rtl_hw_start_8168ep_1(tp);
5996 break;
5997
5998 case RTL_GIGA_MAC_VER_50:
5999 rtl_hw_start_8168ep_2(tp);
6000 break;
6001
6002 case RTL_GIGA_MAC_VER_51:
6003 rtl_hw_start_8168ep_3(tp);
6004 break;
6005
219a1e9d 6006 default:
49d17512
HK		 6007 netif_err(tp, drv, tp->dev,
6008 "unknown chipset (mac_version = %d)\n",
6009 tp->mac_version);
4804b3b3 6010 break;
219a1e9d 6011 }
07ce4064 6012}
1da177e4 6013
beb1fe18 6014static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 6015{
350f7596 6016 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 6017 { 0x01, 0, 0x6e65 },
6018 { 0x02, 0, 0x091f },
6019 { 0x03, 0, 0xc2f9 },
6020 { 0x06, 0, 0xafb5 },
6021 { 0x07, 0, 0x0e00 },
6022 { 0x19, 0, 0xec80 },
6023 { 0x01, 0, 0x2e65 },
6024 { 0x01, 0, 0x6e65 }
6025 };
6026 u8 cfg1;
6027
f37658da 6028 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 6029
1ef7286e 6030 RTL_W8(tp, DBG_REG, FIX_NAK_1);
2857ffb7 6031
8d98aa39 6032 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 6033
1ef7286e 6034 RTL_W8(tp, Config1,
2857ffb7 6035 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
1ef7286e 6036 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7 6037
1ef7286e 6038 cfg1 = RTL_R8(tp, Config1);
2857ffb7 6039 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
1ef7286e 6040 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
2857ffb7 6041
fdf6fc06 6042 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 6043}
6044
beb1fe18 6045static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 6046{
f37658da 6047 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 6048
8d98aa39 6049 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 6050
1ef7286e
AS		 6051 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
6052 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7
FR		 6053}
6054
beb1fe18 6055static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 6056{
beb1fe18 6057 rtl_hw_start_8102e_2(tp);
2857ffb7 6058
fdf6fc06 6059 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 6060}
6061
beb1fe18 6062static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443
HW		 6063{
6064 static const struct ephy_info e_info_8105e_1[] = {
6065 { 0x07, 0, 0x4000 },
6066 { 0x19, 0, 0x0200 },
6067 { 0x19, 0, 0x0020 },
6068 { 0x1e, 0, 0x2000 },
6069 { 0x03, 0, 0x0001 },
6070 { 0x19, 0, 0x0100 },
6071 { 0x19, 0, 0x0004 },
6072 { 0x0a, 0, 0x0020 }
6073 };
6074
cecb5fd7 6075 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 6076 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5a5e4443 6077
cecb5fd7 6078 /* Disable Early Tally Counter */
1ef7286e 6079 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5a5e4443 6080
1ef7286e
AS		 6081 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
6082 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5a5e4443 6083
fdf6fc06 6084 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 6085
6086 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 6087}
6088
beb1fe18 6089static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 6090{
beb1fe18 6091 rtl_hw_start_8105e_1(tp);
fdf6fc06 6092 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 6093}
6094
7e18dca1
HW		 6095static void rtl_hw_start_8402(struct rtl8169_private *tp)
6096{
7e18dca1
HW		 6097 static const struct ephy_info e_info_8402[] = {
6098 { 0x19, 0xffff, 0xff64 },
6099 { 0x1e, 0, 0x4000 }
6100 };
6101
f37658da 6102 rtl_set_def_aspm_entry_latency(tp);
7e18dca1
HW		 6103
6104 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 6105 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
7e18dca1 6106
1ef7286e
AS		 6107 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6108 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7e18dca1 6109
fdf6fc06 6110 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1 6111
8d98aa39 6112 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7e18dca1 6113
fdf6fc06
FR		 6114 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6115 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 6116 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6117 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 6118 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6119 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 6120 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 6121
6122 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 6123}
6124
5598bfe5
HW		 6125static void rtl_hw_start_8106(struct rtl8169_private *tp)
6126{
5598bfe5 6127 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 6128 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5598bfe5 6129
1ef7286e
AS		 6130 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6131 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
6132 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
b51ecea8 6133
6134 rtl_pcie_state_l2l3_enable(tp, false);
5598bfe5
HW		 6135}
6136
61cb532d 6137static void rtl_hw_start_8101(struct rtl8169_private *tp)
07ce4064 6138{
da78dbff
FR		 6139 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6140 tp->event_slow &= ~RxFIFOOver;
811fd301 6141
cecb5fd7 6142 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 6143 tp->mac_version == RTL_GIGA_MAC_VER_16)
61cb532d 6144 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
8200bc72 6145 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 6146
1ef7286e 6147 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
1a964649 6148
12d42c50 6149 tp->cp_cmd &= CPCMD_QUIRK_MASK;
1ef7286e 6150 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1a964649 6151
2857ffb7
FR		 6152 switch (tp->mac_version) {
6153 case RTL_GIGA_MAC_VER_07:
beb1fe18 6154 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 6155 break;
6156
6157 case RTL_GIGA_MAC_VER_08:
beb1fe18 6158 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 6159 break;
6160
6161 case RTL_GIGA_MAC_VER_09:
beb1fe18 6162 rtl_hw_start_8102e_2(tp);
2857ffb7 6163 break;
5a5e4443
HW		 6164
6165 case RTL_GIGA_MAC_VER_29:
beb1fe18 6166 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 6167 break;
6168 case RTL_GIGA_MAC_VER_30:
beb1fe18 6169 rtl_hw_start_8105e_2(tp);
5a5e4443 6170 break;
7e18dca1
HW		 6171
6172 case RTL_GIGA_MAC_VER_37:
6173 rtl_hw_start_8402(tp);
6174 break;
5598bfe5
HW		 6175
6176 case RTL_GIGA_MAC_VER_39:
6177 rtl_hw_start_8106(tp);
6178 break;
58152cd4 6179 case RTL_GIGA_MAC_VER_43:
6180 rtl_hw_start_8168g_2(tp);
6181 break;
6e1d0b89
CHL		 6182 case RTL_GIGA_MAC_VER_47:
6183 case RTL_GIGA_MAC_VER_48:
6184 rtl_hw_start_8168h_1(tp);
6185 break;
cdf1a608
FR		 6186 }
6187
1ef7286e 6188 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4
LT		 6189}
6190
6191static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6192{
d58d46b5
FR		 6193 struct rtl8169_private *tp = netdev_priv(dev);
6194
d58d46b5
FR		 6195 if (new_mtu > ETH_DATA_LEN)
6196 rtl_hw_jumbo_enable(tp);
6197 else
6198 rtl_hw_jumbo_disable(tp);
6199
1da177e4 6200 dev->mtu = new_mtu;
350fb32a
MM		 6201 netdev_update_features(dev);
6202
323bb685 6203 return 0;
1da177e4
LT		 6204}
6205
6206static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6207{
95e0918d 6208 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 6209 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6210}
6211
6f0333b8
ED		 6212static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6213 void **data_buff, struct RxDesc *desc)
1da177e4 6214{
1d0254dd
HK		 6215 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
6216 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
48addcc9 6217
6f0333b8
ED		 6218 kfree(*data_buff);
6219 *data_buff = NULL;
1da177e4
LT		 6220 rtl8169_make_unusable_by_asic(desc);
6221}
6222
1d0254dd 6223static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
1da177e4
LT		 6224{
6225 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6226
a0750138
AD		 6227 /* Force memory writes to complete before releasing descriptor */
6228 dma_wmb();
6229
1d0254dd 6230 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
1da177e4
LT		 6231}
6232
6f0333b8
ED		 6233static inline void *rtl8169_align(void *data)
6234{
6235 return (void *)ALIGN((long)data, 16);
6236}
6237
0ecbe1ca
SG		 6238static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6239 struct RxDesc *desc)
1da177e4 6240{
6f0333b8 6241 void *data;
1da177e4 6242 dma_addr_t mapping;
1e1205b7 6243 struct device *d = tp_to_dev(tp);
d3b404c2 6244 int node = dev_to_node(d);
1da177e4 6245
1d0254dd 6246 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
6f0333b8
ED		 6247 if (!data)
6248 return NULL;
e9f63f30 6249
6f0333b8
ED		 6250 if (rtl8169_align(data) != data) {
6251 kfree(data);
1d0254dd 6252 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
6f0333b8
ED		 6253 if (!data)
6254 return NULL;
6255 }
3eafe507 6256
1d0254dd 6257 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
231aee63 6258 DMA_FROM_DEVICE);
d827d86b
SG		 6259 if (unlikely(dma_mapping_error(d, mapping))) {
6260 if (net_ratelimit())
6261 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 6262 goto err_out;
d827d86b 6263 }
1da177e4 6264
d731af78
HK		 6265 desc->addr = cpu_to_le64(mapping);
6266 rtl8169_mark_to_asic(desc);
6f0333b8 6267 return data;
3eafe507
SG		 6268
6269err_out:
6270 kfree(data);
6271 return NULL;
1da177e4
LT		 6272}
6273
6274static void rtl8169_rx_clear(struct rtl8169_private *tp)
6275{
07d3f51f 6276 unsigned int i;
1da177e4
LT		 6277
6278 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 6279 if (tp->Rx_databuff[i]) {
6280 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 6281 tp->RxDescArray + i);
6282 }
6283 }
6284}
6285
0ecbe1ca 6286static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 6287{
0ecbe1ca
SG		 6288 desc->opts1 |= cpu_to_le32(RingEnd);
6289}
5b0384f4 6290
0ecbe1ca
SG		 6291static int rtl8169_rx_fill(struct rtl8169_private *tp)
6292{
6293 unsigned int i;
1da177e4 6294
0ecbe1ca
SG		 6295 for (i = 0; i < NUM_RX_DESC; i++) {
6296 void *data;
4ae47c2d 6297
0ecbe1ca 6298 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 6299 if (!data) {
6300 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 6301 goto err_out;
6f0333b8
ED		 6302 }
6303 tp->Rx_databuff[i] = data;
1da177e4 6304 }
1da177e4 6305
0ecbe1ca
SG		 6306 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6307 return 0;
6308
6309err_out:
6310 rtl8169_rx_clear(tp);
6311 return -ENOMEM;
1da177e4
LT		 6312}
6313
b1127e64 6314static int rtl8169_init_ring(struct rtl8169_private *tp)
1da177e4 6315{
1da177e4
LT		 6316 rtl8169_init_ring_indexes(tp);
6317
b1127e64
HK		 6318 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
6319 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
1da177e4 6320
0ecbe1ca 6321 return rtl8169_rx_fill(tp);
1da177e4
LT		 6322}
6323
48addcc9 6324static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 6325 struct TxDesc *desc)
6326{
6327 unsigned int len = tx_skb->len;
6328
48addcc9
SG		 6329 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6330
1da177e4
LT		 6331 desc->opts1 = 0x00;
6332 desc->opts2 = 0x00;
6333 desc->addr = 0x00;
6334 tx_skb->len = 0;
6335}
6336
3eafe507
SG		 6337static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6338 unsigned int n)
1da177e4
LT		 6339{
6340 unsigned int i;
6341
3eafe507
SG		 6342 for (i = 0; i < n; i++) {
6343 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 6344 struct ring_info *tx_skb = tp->tx_skb + entry;
6345 unsigned int len = tx_skb->len;
6346
6347 if (len) {
6348 struct sk_buff *skb = tx_skb->skb;
6349
1e1205b7 6350 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
1da177e4
LT		 6351 tp->TxDescArray + entry);
6352 if (skb) {
7a4b813c 6353 dev_consume_skb_any(skb);
1da177e4
LT		 6354 tx_skb->skb = NULL;
6355 }
1da177e4
LT		 6356 }
6357 }
3eafe507
SG		 6358}
6359
6360static void rtl8169_tx_clear(struct rtl8169_private *tp)
6361{
6362 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 6363 tp->cur_tx = tp->dirty_tx = 0;
6364}
6365
4422bcd4 6366static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 6367{
c4028958 6368 struct net_device *dev = tp->dev;
56de414c 6369 int i;
1da177e4 6370
da78dbff
FR		 6371 napi_disable(&tp->napi);
6372 netif_stop_queue(dev);
6373 synchronize_sched();
1da177e4 6374
c7c2c39b 6375 rtl8169_hw_reset(tp);
6376
56de414c 6377 for (i = 0; i < NUM_RX_DESC; i++)
1d0254dd 6378 rtl8169_mark_to_asic(tp->RxDescArray + i);
56de414c 6379
1da177e4 6380 rtl8169_tx_clear(tp);
c7c2c39b 6381 rtl8169_init_ring_indexes(tp);
1da177e4 6382
da78dbff 6383 napi_enable(&tp->napi);
61cb532d 6384 rtl_hw_start(tp);
56de414c 6385 netif_wake_queue(dev);
1ef7286e 6386 rtl8169_check_link_status(dev, tp);
1da177e4
LT		 6387}
6388
6389static void rtl8169_tx_timeout(struct net_device *dev)
6390{
da78dbff
FR		 6391 struct rtl8169_private *tp = netdev_priv(dev);
6392
6393 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6394}
6395
6396static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 6397 u32 *opts)
1da177e4
LT		 6398{
6399 struct skb_shared_info *info = skb_shinfo(skb);
6400 unsigned int cur_frag, entry;
6e1d0b89 6401 struct TxDesc *uninitialized_var(txd);
1e1205b7 6402 struct device *d = tp_to_dev(tp);
1da177e4
LT		 6403
6404 entry = tp->cur_tx;
6405 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 6406 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 6407 dma_addr_t mapping;
6408 u32 status, len;
6409 void *addr;
6410
6411 entry = (entry + 1) % NUM_TX_DESC;
6412
6413 txd = tp->TxDescArray + entry;
9e903e08 6414 len = skb_frag_size(frag);
929f6189 6415 addr = skb_frag_address(frag);
48addcc9 6416 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 6417 if (unlikely(dma_mapping_error(d, mapping))) {
6418 if (net_ratelimit())
6419 netif_err(tp, drv, tp->dev,
6420 "Failed to map TX fragments DMA!\n");
3eafe507 6421 goto err_out;
d827d86b 6422 }
1da177e4 6423
cecb5fd7 6424 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 6425 status = opts[0] | len |
6426 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6427
6428 txd->opts1 = cpu_to_le32(status);
2b7b4318 6429 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 6430 txd->addr = cpu_to_le64(mapping);
6431
6432 tp->tx_skb[entry].len = len;
6433 }
6434
6435 if (cur_frag) {
6436 tp->tx_skb[entry].skb = skb;
6437 txd->opts1 |= cpu_to_le32(LastFrag);
6438 }
6439
6440 return cur_frag;
3eafe507
SG		 6441
6442err_out:
6443 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6444 return -EIO;
1da177e4
LT		 6445}
6446
b423e9ae 6447static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6448{
6449 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6450}
6451
e974604b 6452static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6453 struct net_device *dev);
6454/* r8169_csum_workaround()
6455 * The hw limites the value the transport offset. When the offset is out of the
6456 * range, calculate the checksum by sw.
6457 */
6458static void r8169_csum_workaround(struct rtl8169_private *tp,
6459 struct sk_buff *skb)
6460{
6461 if (skb_shinfo(skb)->gso_size) {
6462 netdev_features_t features = tp->dev->features;
6463 struct sk_buff *segs, *nskb;
6464
6465 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6466 segs = skb_gso_segment(skb, features);
6467 if (IS_ERR(segs) || !segs)
6468 goto drop;
6469
6470 do {
6471 nskb = segs;
6472 segs = segs->next;
6473 nskb->next = NULL;
6474 rtl8169_start_xmit(nskb, tp->dev);
6475 } while (segs);
6476
eb781397 6477 dev_consume_skb_any(skb);
e974604b 6478 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6479 if (skb_checksum_help(skb) < 0)
6480 goto drop;
6481
6482 rtl8169_start_xmit(skb, tp->dev);
6483 } else {
6484 struct net_device_stats *stats;
6485
6486drop:
6487 stats = &tp->dev->stats;
6488 stats->tx_dropped++;
eb781397 6489 dev_kfree_skb_any(skb);
e974604b 6490 }
6491}
6492
6493/* msdn_giant_send_check()
6494 * According to the document of microsoft, the TCP Pseudo Header excludes the
6495 * packet length for IPv6 TCP large packets.
6496 */
6497static int msdn_giant_send_check(struct sk_buff *skb)
6498{
6499 const struct ipv6hdr *ipv6h;
6500 struct tcphdr *th;
6501 int ret;
6502
6503 ret = skb_cow_head(skb, 0);
6504 if (ret)
6505 return ret;
6506
6507 ipv6h = ipv6_hdr(skb);
6508 th = tcp_hdr(skb);
6509
6510 th->check = 0;
6511 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6512
6513 return ret;
6514}
6515
5888d3fc 6516static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6517 struct sk_buff *skb, u32 *opts)
1da177e4 6518{
350fb32a
MM		 6519 u32 mss = skb_shinfo(skb)->gso_size;
6520
2b7b4318
FR		 6521 if (mss) {
6522 opts[0] |= TD_LSO;
5888d3fc 6523 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6524 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6525 const struct iphdr *ip = ip_hdr(skb);
6526
6527 if (ip->protocol == IPPROTO_TCP)
6528 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6529 else if (ip->protocol == IPPROTO_UDP)
6530 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6531 else
6532 WARN_ON_ONCE(1);
6533 }
6534
6535 return true;
6536}
6537
6538static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6539 struct sk_buff *skb, u32 *opts)
6540{
bdfa4ed6 6541 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 6542 u32 mss = skb_shinfo(skb)->gso_size;
6543
6544 if (mss) {
e974604b 6545 if (transport_offset > GTTCPHO_MAX) {
6546 netif_warn(tp, tx_err, tp->dev,
6547 "Invalid transport offset 0x%x for TSO\n",
6548 transport_offset);
6549 return false;
6550 }
6551
4ff36466 6552 switch (vlan_get_protocol(skb)) {
e974604b 6553 case htons(ETH_P_IP):
6554 opts[0] |= TD1_GTSENV4;
6555 break;
6556
6557 case htons(ETH_P_IPV6):
6558 if (msdn_giant_send_check(skb))
6559 return false;
6560
6561 opts[0] |= TD1_GTSENV6;
6562 break;
6563
6564 default:
6565 WARN_ON_ONCE(1);
6566 break;
6567 }
6568
bdfa4ed6 6569 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 6570 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 6571 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 6572 u8 ip_protocol;
1da177e4 6573
b423e9ae 6574 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6575 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
b423e9ae 6576
e974604b 6577 if (transport_offset > TCPHO_MAX) {
6578 netif_warn(tp, tx_err, tp->dev,
6579 "Invalid transport offset 0x%x\n",
6580 transport_offset);
6581 return false;
6582 }
6583
4ff36466 6584 switch (vlan_get_protocol(skb)) {
e974604b 6585 case htons(ETH_P_IP):
6586 opts[1] |= TD1_IPv4_CS;
6587 ip_protocol = ip_hdr(skb)->protocol;
6588 break;
6589
6590 case htons(ETH_P_IPV6):
6591 opts[1] |= TD1_IPv6_CS;
6592 ip_protocol = ipv6_hdr(skb)->nexthdr;
6593 break;
6594
6595 default:
6596 ip_protocol = IPPROTO_RAW;
6597 break;
6598 }
6599
6600 if (ip_protocol == IPPROTO_TCP)
6601 opts[1] |= TD1_TCP_CS;
6602 else if (ip_protocol == IPPROTO_UDP)
6603 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 6604 else
6605 WARN_ON_ONCE(1);
e974604b 6606
6607 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 6608 } else {
6609 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6610 return !eth_skb_pad(skb);
1da177e4 6611 }
5888d3fc 6612
b423e9ae 6613 return true;
1da177e4
LT		 6614}
6615
61357325
SH		 6616static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6617 struct net_device *dev)
1da177e4
LT		 6618{
6619 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 6620 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4 6621 struct TxDesc *txd = tp->TxDescArray + entry;
1e1205b7 6622 struct device *d = tp_to_dev(tp);
1da177e4
LT		 6623 dma_addr_t mapping;
6624 u32 status, len;
2b7b4318 6625 u32 opts[2];
3eafe507 6626 int frags;
5b0384f4 6627
477206a0 6628 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 6629 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 6630 goto err_stop_0;
1da177e4
LT		 6631 }
6632
6633 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 6634 goto err_stop_0;
6635
b423e9ae 6636 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6637 opts[0] = DescOwn;
6638
e974604b 6639 if (!tp->tso_csum(tp, skb, opts)) {
6640 r8169_csum_workaround(tp, skb);
6641 return NETDEV_TX_OK;
6642 }
b423e9ae 6643
3eafe507 6644 len = skb_headlen(skb);
48addcc9 6645 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 6646 if (unlikely(dma_mapping_error(d, mapping))) {
6647 if (net_ratelimit())
6648 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 6649 goto err_dma_0;
d827d86b 6650 }
3eafe507
SG		 6651
6652 tp->tx_skb[entry].len = len;
6653 txd->addr = cpu_to_le64(mapping);
1da177e4 6654
2b7b4318 6655 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 6656 if (frags < 0)
6657 goto err_dma_1;
6658 else if (frags)
2b7b4318 6659 opts[0] |= FirstFrag;
3eafe507 6660 else {
2b7b4318 6661 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 6662 tp->tx_skb[entry].skb = skb;
6663 }
6664
2b7b4318
FR		 6665 txd->opts2 = cpu_to_le32(opts[1]);
6666
5047fb5d
RC		 6667 skb_tx_timestamp(skb);
6668
a0750138
AD		 6669 /* Force memory writes to complete before releasing descriptor */
6670 dma_wmb();
1da177e4 6671
cecb5fd7 6672 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 6673 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6674 txd->opts1 = cpu_to_le32(status);
6675
a0750138 6676 /* Force all memory writes to complete before notifying device */
4c020a96 6677 wmb();
1da177e4 6678
a0750138
AD		 6679 tp->cur_tx += frags + 1;
6680
1ef7286e 6681 RTL_W8(tp, TxPoll, NPQ);
1da177e4 6682
87cda7cb 6683 mmiowb();
da78dbff 6684
87cda7cb 6685 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 6686 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6687 * not miss a ring update when it notices a stopped queue.
6688 */
6689 smp_wmb();
1da177e4 6690 netif_stop_queue(dev);
ae1f23fb
FR		 6691 /* Sync with rtl_tx:
6692 * - publish queue status and cur_tx ring index (write barrier)
6693 * - refresh dirty_tx ring index (read barrier).
6694 * May the current thread have a pessimistic view of the ring
6695 * status and forget to wake up queue, a racing rtl_tx thread
6696 * can't.
6697 */
1e874e04 6698 smp_mb();
477206a0 6699 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 6700 netif_wake_queue(dev);
6701 }
6702
61357325 6703 return NETDEV_TX_OK;
1da177e4 6704
3eafe507 6705err_dma_1:
48addcc9 6706 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 6707err_dma_0:
989c9ba1 6708 dev_kfree_skb_any(skb);
3eafe507
SG		 6709 dev->stats.tx_dropped++;
6710 return NETDEV_TX_OK;
6711
6712err_stop_0:
1da177e4 6713 netif_stop_queue(dev);
cebf8cc7 6714 dev->stats.tx_dropped++;
61357325 6715 return NETDEV_TX_BUSY;
1da177e4
LT		 6716}
6717
6718static void rtl8169_pcierr_interrupt(struct net_device *dev)
6719{
6720 struct rtl8169_private *tp = netdev_priv(dev);
6721 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 6722 u16 pci_status, pci_cmd;
6723
6724 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6725 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6726
bf82c189
JP		 6727 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6728 pci_cmd, pci_status);
1da177e4
LT		 6729
6730 /*
6731 * The recovery sequence below admits a very elaborated explanation:
6732 * - it seems to work;
d03902b8
FR		 6733 * - I did not see what else could be done;
6734 * - it makes iop3xx happy.
1da177e4
LT		 6735 *
6736 * Feel free to adjust to your needs.
6737 */
a27993f3 6738 if (pdev->broken_parity_status)
d03902b8
FR		 6739 pci_cmd &= ~PCI_COMMAND_PARITY;
6740 else
6741 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6742
6743 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 6744
6745 pci_write_config_word(pdev, PCI_STATUS,
6746 pci_status & (PCI_STATUS_DETECTED_PARITY |
6747 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6748 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6749
6750 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 6751 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
bf82c189 6752 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4 6753 tp->cp_cmd &= ~PCIDAC;
1ef7286e 6754 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1da177e4 6755 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 6756 }
6757
e6de30d6 6758 rtl8169_hw_reset(tp);
d03902b8 6759
98ddf986 6760 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6761}
6762
da78dbff 6763static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 6764{
6765 unsigned int dirty_tx, tx_left;
6766
1da177e4
LT		 6767 dirty_tx = tp->dirty_tx;
6768 smp_rmb();
6769 tx_left = tp->cur_tx - dirty_tx;
6770
6771 while (tx_left > 0) {
6772 unsigned int entry = dirty_tx % NUM_TX_DESC;
6773 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 6774 u32 status;
6775
1da177e4
LT		 6776 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6777 if (status & DescOwn)
6778 break;
6779
a0750138
AD		 6780 /* This barrier is needed to keep us from reading
6781 * any other fields out of the Tx descriptor until
6782 * we know the status of DescOwn
6783 */
6784 dma_rmb();
6785
1e1205b7 6786 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
48addcc9 6787 tp->TxDescArray + entry);
1da177e4 6788 if (status & LastFrag) {
87cda7cb
DM		 6789 u64_stats_update_begin(&tp->tx_stats.syncp);
6790 tp->tx_stats.packets++;
6791 tp->tx_stats.bytes += tx_skb->skb->len;
6792 u64_stats_update_end(&tp->tx_stats.syncp);
7a4b813c 6793 dev_consume_skb_any(tx_skb->skb);
1da177e4
LT		 6794 tx_skb->skb = NULL;
6795 }
6796 dirty_tx++;
6797 tx_left--;
6798 }
6799
6800 if (tp->dirty_tx != dirty_tx) {
6801 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6802 /* Sync with rtl8169_start_xmit:
6803 * - publish dirty_tx ring index (write barrier)
6804 * - refresh cur_tx ring index and queue status (read barrier)
6805 * May the current thread miss the stopped queue condition,
6806 * a racing xmit thread can only have a right view of the
6807 * ring status.
6808 */
1e874e04 6809 smp_mb();
1da177e4 6810 if (netif_queue_stopped(dev) &&
477206a0 6811 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6812 netif_wake_queue(dev);
6813 }
d78ae2dc
FR		 6814 /*
6815 * 8168 hack: TxPoll requests are lost when the Tx packets are
6816 * too close. Let's kick an extra TxPoll request when a burst
6817 * of start_xmit activity is detected (if it is not detected,
6818 * it is slow enough). -- FR
6819 */
1ef7286e
AS		 6820 if (tp->cur_tx != dirty_tx)
6821 RTL_W8(tp, TxPoll, NPQ);
1da177e4
LT		 6822 }
6823}
6824
126fa4b9
FR		 6825static inline int rtl8169_fragmented_frame(u32 status)
6826{
6827 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6828}
6829
adea1ac7 6830static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6831{
1da177e4
LT		 6832 u32 status = opts1 & RxProtoMask;
6833
6834 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6835 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6836 skb->ip_summed = CHECKSUM_UNNECESSARY;
6837 else
bc8acf2c 6838 skb_checksum_none_assert(skb);
1da177e4
LT		 6839}
6840
6f0333b8
ED		 6841static struct sk_buff *rtl8169_try_rx_copy(void *data,
6842 struct rtl8169_private *tp,
6843 int pkt_size,
6844 dma_addr_t addr)
1da177e4 6845{
b449655f 6846 struct sk_buff *skb;
1e1205b7 6847 struct device *d = tp_to_dev(tp);
b449655f 6848
6f0333b8 6849 data = rtl8169_align(data);
48addcc9 6850 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8 6851 prefetch(data);
e2338f86 6852 skb = napi_alloc_skb(&tp->napi, pkt_size);
6f0333b8 6853 if (skb)
8a67aa86 6854 skb_copy_to_linear_data(skb, data, pkt_size);
48addcc9
SG		 6855 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6856
6f0333b8 6857 return skb;
1da177e4
LT		 6858}
6859
da78dbff 6860static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6861{
6862 unsigned int cur_rx, rx_left;
6f0333b8 6863 unsigned int count;
1da177e4 6864
1da177e4 6865 cur_rx = tp->cur_rx;
1da177e4 6866
9fba0812 6867 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6868 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6869 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6870 u32 status;
6871
6202806e 6872 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 6873 if (status & DescOwn)
6874 break;
a0750138
AD		 6875
6876 /* This barrier is needed to keep us from reading
6877 * any other fields out of the Rx descriptor until
6878 * we know the status of DescOwn
6879 */
6880 dma_rmb();
6881
4dcb7d33 6882 if (unlikely(status & RxRES)) {
bf82c189
JP		 6883 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6884 status);
cebf8cc7 6885 dev->stats.rx_errors++;
1da177e4 6886 if (status & (RxRWT | RxRUNT))
cebf8cc7 6887 dev->stats.rx_length_errors++;
1da177e4 6888 if (status & RxCRC)
cebf8cc7 6889 dev->stats.rx_crc_errors++;
6202806e
HK		 6890 /* RxFOVF is a reserved bit on later chip versions */
6891 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6892 status & RxFOVF) {
da78dbff 6893 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6894 dev->stats.rx_fifo_errors++;
6202806e
HK		 6895 } else if (status & (RxRUNT | RxCRC) &&
6896 !(status & RxRWT) &&
6897 dev->features & NETIF_F_RXALL) {
6bbe021d 6898 goto process_pkt;
6202806e 6899 }
1da177e4 6900 } else {
6f0333b8 6901 struct sk_buff *skb;
6bbe021d
BG		 6902 dma_addr_t addr;
6903 int pkt_size;
6904
6905process_pkt:
6906 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6907 if (likely(!(dev->features & NETIF_F_RXFCS)))
6908 pkt_size = (status & 0x00003fff) - 4;
6909 else
6910 pkt_size = status & 0x00003fff;
1da177e4 6911
126fa4b9
FR		 6912 /*
6913 * The driver does not support incoming fragmented
6914 * frames. They are seen as a symptom of over-mtu
6915 * sized frames.
6916 */
6917 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6918 dev->stats.rx_dropped++;
6919 dev->stats.rx_length_errors++;
ce11ff5e 6920 goto release_descriptor;
126fa4b9
FR		 6921 }
6922
6f0333b8
ED		 6923 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6924 tp, pkt_size, addr);
6f0333b8
ED		 6925 if (!skb) {
6926 dev->stats.rx_dropped++;
ce11ff5e 6927 goto release_descriptor;
1da177e4
LT		 6928 }
6929
adea1ac7 6930 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6931 skb_put(skb, pkt_size);
6932 skb->protocol = eth_type_trans(skb, dev);
6933
7a8fc77b
FR		 6934 rtl8169_rx_vlan_tag(desc, skb);
6935
39174291 6936 if (skb->pkt_type == PACKET_MULTICAST)
6937 dev->stats.multicast++;
6938
56de414c 6939 napi_gro_receive(&tp->napi, skb);
1da177e4 6940
8027aa24
JW		 6941 u64_stats_update_begin(&tp->rx_stats.syncp);
6942 tp->rx_stats.packets++;
6943 tp->rx_stats.bytes += pkt_size;
6944 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6945 }
ce11ff5e 6946release_descriptor:
6947 desc->opts2 = 0;
1d0254dd 6948 rtl8169_mark_to_asic(desc);
1da177e4
LT		 6949 }
6950
6951 count = cur_rx - tp->cur_rx;
6952 tp->cur_rx = cur_rx;
6953
1da177e4
LT		 6954 return count;
6955}
6956
07d3f51f 6957static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6958{
ebcd5daa 6959 struct rtl8169_private *tp = dev_instance;
1da177e4 6960 int handled = 0;
9085cdfa 6961 u16 status;
1da177e4 6962
9085cdfa 6963 status = rtl_get_events(tp);
da78dbff
FR		 6964 if (status && status != 0xffff) {
6965 status &= RTL_EVENT_NAPI | tp->event_slow;
6966 if (status) {
6967 handled = 1;
1da177e4 6968
da78dbff 6969 rtl_irq_disable(tp);
9a899a35 6970 napi_schedule_irqoff(&tp->napi);
f11a377b 6971 }
da78dbff
FR		 6972 }
6973 return IRQ_RETVAL(handled);
6974}
1da177e4 6975
da78dbff
FR		 6976/*
6977 * Workqueue context.
6978 */
6979static void rtl_slow_event_work(struct rtl8169_private *tp)
6980{
6981 struct net_device *dev = tp->dev;
6982 u16 status;
6983
6984 status = rtl_get_events(tp) & tp->event_slow;
6985 rtl_ack_events(tp, status);
1da177e4 6986
da78dbff
FR		 6987 if (unlikely(status & RxFIFOOver)) {
6988 switch (tp->mac_version) {
6989 /* Work around for rx fifo overflow */
6990 case RTL_GIGA_MAC_VER_11:
6991 netif_stop_queue(dev);
934714d0
FR		 6992 /* XXX - Hack alert. See rtl_task(). */
6993 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6994 default:
f11a377b
DD		 6995 break;
6996 }
da78dbff 6997 }
1da177e4 6998
da78dbff
FR		 6999 if (unlikely(status & SYSErr))
7000 rtl8169_pcierr_interrupt(dev);
0e485150 7001
da78dbff 7002 if (status & LinkChg)
1ef7286e 7003 rtl8169_check_link_status(dev, tp);
1da177e4 7004
7dbb4918 7005 rtl_irq_enable_all(tp);
1da177e4
LT		 7006}
7007
4422bcd4
FR		 7008static void rtl_task(struct work_struct *work)
7009{
da78dbff
FR		 7010 static const struct {
7011 int bitnr;
7012 void (*action)(struct rtl8169_private *);
7013 } rtl_work[] = {
934714d0 7014 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 7015 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7016 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7017 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7018 };
4422bcd4
FR		 7019 struct rtl8169_private *tp =
7020 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 7021 struct net_device *dev = tp->dev;
7022 int i;
7023
7024 rtl_lock_work(tp);
7025
6c4a70c5
FR		 7026 if (!netif_running(dev) ||
7027 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 7028 goto out_unlock;
7029
7030 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7031 bool pending;
7032
da78dbff 7033 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 7034 if (pending)
7035 rtl_work[i].action(tp);
7036 }
4422bcd4 7037
da78dbff
FR		 7038out_unlock:
7039 rtl_unlock_work(tp);
4422bcd4
FR		 7040}
7041
bea3348e 7042static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 7043{
bea3348e
SH		 7044 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7045 struct net_device *dev = tp->dev;
da78dbff
FR		 7046 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7047 int work_done= 0;
7048 u16 status;
7049
7050 status = rtl_get_events(tp);
7051 rtl_ack_events(tp, status & ~tp->event_slow);
7052
7053 if (status & RTL_EVENT_NAPI_RX)
7054 work_done = rtl_rx(dev, tp, (u32) budget);
7055
7056 if (status & RTL_EVENT_NAPI_TX)
7057 rtl_tx(dev, tp);
1da177e4 7058
da78dbff
FR		 7059 if (status & tp->event_slow) {
7060 enable_mask &= ~tp->event_slow;
7061
7062 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7063 }
1da177e4 7064
bea3348e 7065 if (work_done < budget) {
6ad20165 7066 napi_complete_done(napi, work_done);
f11a377b 7067
da78dbff
FR		 7068 rtl_irq_enable(tp, enable_mask);
7069 mmiowb();
1da177e4
LT		 7070 }
7071
bea3348e 7072 return work_done;
1da177e4 7073}
1da177e4 7074
1ef7286e 7075static void rtl8169_rx_missed(struct net_device *dev)
523a6094
FR		 7076{
7077 struct rtl8169_private *tp = netdev_priv(dev);
7078
7079 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7080 return;
7081
1ef7286e
AS		 7082 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
7083 RTL_W32(tp, RxMissed, 0);
523a6094
FR		 7084}
7085
1da177e4
LT		 7086static void rtl8169_down(struct net_device *dev)
7087{
7088 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 7089
4876cc1e 7090 del_timer_sync(&tp->timer);
1da177e4 7091
93dd79e8 7092 napi_disable(&tp->napi);
da78dbff 7093 netif_stop_queue(dev);
1da177e4 7094
92fc43b4 7095 rtl8169_hw_reset(tp);
323bb685
SG		 7096 /*
7097 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 7098 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7099 * and napi is disabled (rtl8169_poll).
323bb685 7100 */
1ef7286e 7101 rtl8169_rx_missed(dev);
1da177e4 7102
1da177e4 7103 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 7104 synchronize_sched();
1da177e4 7105
1da177e4
LT		 7106 rtl8169_tx_clear(tp);
7107
7108 rtl8169_rx_clear(tp);
065c27c1 7109
7110 rtl_pll_power_down(tp);
1da177e4
LT		 7111}
7112
7113static int rtl8169_close(struct net_device *dev)
7114{
7115 struct rtl8169_private *tp = netdev_priv(dev);
7116 struct pci_dev *pdev = tp->pci_dev;
7117
e1759441
RW		 7118 pm_runtime_get_sync(&pdev->dev);
7119
cecb5fd7 7120 /* Update counters before going down */
e71c9ce2 7121 rtl8169_update_counters(tp);
355423d0 7122
da78dbff 7123 rtl_lock_work(tp);
6c4a70c5 7124 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 7125
1da177e4 7126 rtl8169_down(dev);
da78dbff 7127 rtl_unlock_work(tp);
1da177e4 7128
4ea72445
L		 7129 cancel_work_sync(&tp->wk.work);
7130
ebcd5daa 7131 pci_free_irq(pdev, 0, tp);
1da177e4 7132
82553bb6
SG		 7133 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7134 tp->RxPhyAddr);
7135 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7136 tp->TxPhyAddr);
1da177e4
LT		 7137 tp->TxDescArray = NULL;
7138 tp->RxDescArray = NULL;
7139
e1759441
RW		 7140 pm_runtime_put_sync(&pdev->dev);
7141
1da177e4
LT		 7142 return 0;
7143}
7144
dc1c00ce
FR		 7145#ifdef CONFIG_NET_POLL_CONTROLLER
7146static void rtl8169_netpoll(struct net_device *dev)
7147{
7148 struct rtl8169_private *tp = netdev_priv(dev);
7149
6d8b8349 7150 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
dc1c00ce
FR		 7151}
7152#endif
7153
df43ac78
FR		 7154static int rtl_open(struct net_device *dev)
7155{
7156 struct rtl8169_private *tp = netdev_priv(dev);
df43ac78
FR		 7157 struct pci_dev *pdev = tp->pci_dev;
7158 int retval = -ENOMEM;
7159
7160 pm_runtime_get_sync(&pdev->dev);
7161
7162 /*
e75d6606 7163 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 7164 * dma_alloc_coherent provides more.
7165 */
7166 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7167 &tp->TxPhyAddr, GFP_KERNEL);
7168 if (!tp->TxDescArray)
7169 goto err_pm_runtime_put;
7170
7171 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7172 &tp->RxPhyAddr, GFP_KERNEL);
7173 if (!tp->RxDescArray)
7174 goto err_free_tx_0;
7175
b1127e64 7176 retval = rtl8169_init_ring(tp);
df43ac78
FR		 7177 if (retval < 0)
7178 goto err_free_rx_1;
7179
7180 INIT_WORK(&tp->wk.work, rtl_task);
7181
7182 smp_mb();
7183
7184 rtl_request_firmware(tp);
7185
ebcd5daa 7186 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6c6aa15f 7187 dev->name);
df43ac78
FR		 7188 if (retval < 0)
7189 goto err_release_fw_2;
7190
7191 rtl_lock_work(tp);
7192
7193 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7194
7195 napi_enable(&tp->napi);
7196
7197 rtl8169_init_phy(dev, tp);
7198
df43ac78
FR		 7199 rtl_pll_power_up(tp);
7200
61cb532d 7201 rtl_hw_start(tp);
df43ac78 7202
e71c9ce2 7203 if (!rtl8169_init_counter_offsets(tp))
6e85d5ad
CV		 7204 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7205
df43ac78
FR		 7206 netif_start_queue(dev);
7207
7208 rtl_unlock_work(tp);
7209
a92a0849 7210 pm_runtime_put_sync(&pdev->dev);
df43ac78 7211
1ef7286e 7212 rtl8169_check_link_status(dev, tp);
df43ac78
FR		 7213out:
7214 return retval;
7215
7216err_release_fw_2:
7217 rtl_release_firmware(tp);
7218 rtl8169_rx_clear(tp);
7219err_free_rx_1:
7220 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7221 tp->RxPhyAddr);
7222 tp->RxDescArray = NULL;
7223err_free_tx_0:
7224 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7225 tp->TxPhyAddr);
7226 tp->TxDescArray = NULL;
7227err_pm_runtime_put:
7228 pm_runtime_put_noidle(&pdev->dev);
7229 goto out;
7230}
7231
bc1f4470 7232static void
8027aa24 7233rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 7234{
7235 struct rtl8169_private *tp = netdev_priv(dev);
f09cf4b7 7236 struct pci_dev *pdev = tp->pci_dev;
42020320 7237 struct rtl8169_counters *counters = tp->counters;
8027aa24 7238 unsigned int start;
1da177e4 7239
f09cf4b7
CHL		 7240 pm_runtime_get_noresume(&pdev->dev);
7241
7242 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
1ef7286e 7243 rtl8169_rx_missed(dev);
5b0384f4 7244
8027aa24 7245 do {
57a7744e 7246 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 7247 stats->rx_packets = tp->rx_stats.packets;
7248 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 7249 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 7250
8027aa24 7251 do {
57a7744e 7252 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 7253 stats->tx_packets = tp->tx_stats.packets;
7254 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 7255 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 7256
7257 stats->rx_dropped = dev->stats.rx_dropped;
7258 stats->tx_dropped = dev->stats.tx_dropped;
7259 stats->rx_length_errors = dev->stats.rx_length_errors;
7260 stats->rx_errors = dev->stats.rx_errors;
7261 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7262 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7263 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 7264 stats->multicast = dev->stats.multicast;
8027aa24 7265
6e85d5ad
CV		 7266 /*
7267 * Fetch additonal counter values missing in stats collected by driver
7268 * from tally counters.
7269 */
f09cf4b7 7270 if (pm_runtime_active(&pdev->dev))
e71c9ce2 7271 rtl8169_update_counters(tp);
6e85d5ad
CV		 7272
7273 /*
7274 * Subtract values fetched during initalization.
7275 * See rtl8169_init_counter_offsets for a description why we do that.
7276 */
42020320 7277 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 7278 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 7279 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 7280 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 7281 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 7282 le16_to_cpu(tp->tc_offset.tx_aborted);
7283
f09cf4b7 7284 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 7285}
7286
861ab440 7287static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 7288{
065c27c1 7289 struct rtl8169_private *tp = netdev_priv(dev);
7290
5d06a99f 7291 if (!netif_running(dev))
861ab440 7292 return;
5d06a99f
FR		 7293
7294 netif_device_detach(dev);
7295 netif_stop_queue(dev);
da78dbff
FR		 7296
7297 rtl_lock_work(tp);
7298 napi_disable(&tp->napi);
6c4a70c5 7299 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 7300 rtl_unlock_work(tp);
7301
7302 rtl_pll_power_down(tp);
861ab440
RW		 7303}
7304
7305#ifdef CONFIG_PM
7306
7307static int rtl8169_suspend(struct device *device)
7308{
7309 struct pci_dev *pdev = to_pci_dev(device);
7310 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 7311
861ab440 7312 rtl8169_net_suspend(dev);
1371fa6d 7313
5d06a99f
FR		 7314 return 0;
7315}
7316
e1759441
RW		 7317static void __rtl8169_resume(struct net_device *dev)
7318{
065c27c1 7319 struct rtl8169_private *tp = netdev_priv(dev);
7320
e1759441 7321 netif_device_attach(dev);
065c27c1 7322
7323 rtl_pll_power_up(tp);
92bad850 7324 rtl8169_init_phy(dev, tp);
065c27c1 7325
cff4c162
AS		 7326 rtl_lock_work(tp);
7327 napi_enable(&tp->napi);
6c4a70c5 7328 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 7329 rtl_unlock_work(tp);
da78dbff 7330
98ddf986 7331 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 7332}
7333
861ab440 7334static int rtl8169_resume(struct device *device)
5d06a99f 7335{
861ab440 7336 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f
FR		 7337 struct net_device *dev = pci_get_drvdata(pdev);
7338
e1759441
RW		 7339 if (netif_running(dev))
7340 __rtl8169_resume(dev);
5d06a99f 7341
e1759441
RW		 7342 return 0;
7343}
7344
7345static int rtl8169_runtime_suspend(struct device *device)
7346{
7347 struct pci_dev *pdev = to_pci_dev(device);
7348 struct net_device *dev = pci_get_drvdata(pdev);
7349 struct rtl8169_private *tp = netdev_priv(dev);
7350
a92a0849
HK		 7351 if (!tp->TxDescArray) {
7352 rtl_pll_power_down(tp);
e1759441 7353 return 0;
a92a0849 7354 }
e1759441 7355
da78dbff 7356 rtl_lock_work(tp);
e1759441 7357 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 7358 rtl_unlock_work(tp);
e1759441
RW		 7359
7360 rtl8169_net_suspend(dev);
7361
f09cf4b7 7362 /* Update counters before going runtime suspend */
1ef7286e 7363 rtl8169_rx_missed(dev);
e71c9ce2 7364 rtl8169_update_counters(tp);
f09cf4b7 7365
e1759441
RW		 7366 return 0;
7367}
7368
7369static int rtl8169_runtime_resume(struct device *device)
7370{
7371 struct pci_dev *pdev = to_pci_dev(device);
7372 struct net_device *dev = pci_get_drvdata(pdev);
7373 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 7374 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 7375
7376 if (!tp->TxDescArray)
7377 return 0;
7378
da78dbff 7379 rtl_lock_work(tp);
e1759441 7380 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff 7381 rtl_unlock_work(tp);
e1759441
RW		 7382
7383 __rtl8169_resume(dev);
5d06a99f 7384
5d06a99f
FR		 7385 return 0;
7386}
7387
e1759441
RW		 7388static int rtl8169_runtime_idle(struct device *device)
7389{
7390 struct pci_dev *pdev = to_pci_dev(device);
7391 struct net_device *dev = pci_get_drvdata(pdev);
e1759441 7392
a92a0849
HK		 7393 if (!netif_running(dev) || !netif_carrier_ok(dev))
7394 pm_schedule_suspend(device, 10000);
7395
7396 return -EBUSY;
e1759441
RW		 7397}
7398
47145210 7399static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 7400 .suspend = rtl8169_suspend,
7401 .resume = rtl8169_resume,
7402 .freeze = rtl8169_suspend,
7403 .thaw = rtl8169_resume,
7404 .poweroff = rtl8169_suspend,
7405 .restore = rtl8169_resume,
7406 .runtime_suspend = rtl8169_runtime_suspend,
7407 .runtime_resume = rtl8169_runtime_resume,
7408 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 7409};
7410
7411#define RTL8169_PM_OPS (&rtl8169_pm_ops)
7412
7413#else /* !CONFIG_PM */
7414
7415#define RTL8169_PM_OPS NULL
7416
7417#endif /* !CONFIG_PM */
7418
649b3b8c 7419static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7420{
649b3b8c 7421 /* WoL fails with 8168b when the receiver is disabled. */
7422 switch (tp->mac_version) {
7423 case RTL_GIGA_MAC_VER_11:
7424 case RTL_GIGA_MAC_VER_12:
7425 case RTL_GIGA_MAC_VER_17:
7426 pci_clear_master(tp->pci_dev);
7427
1ef7286e 7428 RTL_W8(tp, ChipCmd, CmdRxEnb);
649b3b8c 7429 /* PCI commit */
1ef7286e 7430 RTL_R8(tp, ChipCmd);
649b3b8c 7431 break;
7432 default:
7433 break;
7434 }
7435}
7436
1765f95d
FR		 7437static void rtl_shutdown(struct pci_dev *pdev)
7438{
861ab440 7439 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 7440 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 7441
7442 rtl8169_net_suspend(dev);
1765f95d 7443
cecb5fd7 7444 /* Restore original MAC address */
cc098dc7
IV		 7445 rtl_rar_set(tp, dev->perm_addr);
7446
92fc43b4 7447 rtl8169_hw_reset(tp);
4bb3f522 7448
861ab440 7449 if (system_state == SYSTEM_POWER_OFF) {
433f9d0d 7450 if (tp->saved_wolopts) {
649b3b8c 7451 rtl_wol_suspend_quirk(tp);
7452 rtl_wol_shutdown_quirk(tp);
ca52efd5 7453 }
7454
861ab440
RW		 7455 pci_wake_from_d3(pdev, true);
7456 pci_set_power_state(pdev, PCI_D3hot);
7457 }
7458}
5d06a99f 7459
baf63293 7460static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 7461{
7462 struct net_device *dev = pci_get_drvdata(pdev);
7463 struct rtl8169_private *tp = netdev_priv(dev);
7464
9dbe7896 7465 if (r8168_check_dash(tp))
e27566ed 7466 rtl8168_driver_stop(tp);
e27566ed 7467
ad1be8d3
DN		 7468 netif_napi_del(&tp->napi);
7469
e27566ed
FR		 7470 unregister_netdev(dev);
7471
7472 rtl_release_firmware(tp);
7473
7474 if (pci_dev_run_wake(pdev))
7475 pm_runtime_get_noresume(&pdev->dev);
7476
7477 /* restore original MAC address */
7478 rtl_rar_set(tp, dev->perm_addr);
e27566ed
FR		 7479}
7480
fa9c385e 7481static const struct net_device_ops rtl_netdev_ops = {
df43ac78 7482 .ndo_open = rtl_open,
fa9c385e
FR		 7483 .ndo_stop = rtl8169_close,
7484 .ndo_get_stats64 = rtl8169_get_stats64,
7485 .ndo_start_xmit = rtl8169_start_xmit,
7486 .ndo_tx_timeout = rtl8169_tx_timeout,
7487 .ndo_validate_addr = eth_validate_addr,
7488 .ndo_change_mtu = rtl8169_change_mtu,
7489 .ndo_fix_features = rtl8169_fix_features,
7490 .ndo_set_features = rtl8169_set_features,
7491 .ndo_set_mac_address = rtl_set_mac_address,
7492 .ndo_do_ioctl = rtl8169_ioctl,
7493 .ndo_set_rx_mode = rtl_set_rx_mode,
7494#ifdef CONFIG_NET_POLL_CONTROLLER
7495 .ndo_poll_controller = rtl8169_netpoll,
7496#endif
7497
7498};
7499
31fa8b18 7500static const struct rtl_cfg_info {
61cb532d 7501 void (*hw_start)(struct rtl8169_private *tp);
31fa8b18 7502 u16 event_slow;
14967f94 7503 unsigned int has_gmii:1;
50970831 7504 const struct rtl_coalesce_info *coalesce_info;
31fa8b18
FR		 7505 u8 default_ver;
7506} rtl_cfg_infos [] = {
7507 [RTL_CFG_0] = {
7508 .hw_start = rtl_hw_start_8169,
31fa8b18 7509 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
14967f94 7510 .has_gmii = 1,
50970831 7511 .coalesce_info = rtl_coalesce_info_8169,
31fa8b18
FR		 7512 .default_ver = RTL_GIGA_MAC_VER_01,
7513 },
7514 [RTL_CFG_1] = {
7515 .hw_start = rtl_hw_start_8168,
31fa8b18 7516 .event_slow = SYSErr | LinkChg | RxOverflow,
14967f94 7517 .has_gmii = 1,
50970831 7518 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 7519 .default_ver = RTL_GIGA_MAC_VER_11,
7520 },
7521 [RTL_CFG_2] = {
7522 .hw_start = rtl_hw_start_8101,
31fa8b18
FR		 7523 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7524 PCSTimeout,
50970831 7525 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 7526 .default_ver = RTL_GIGA_MAC_VER_13,
7527 }
7528};
7529
6c6aa15f 7530static int rtl_alloc_irq(struct rtl8169_private *tp)
31fa8b18 7531{
6c6aa15f 7532 unsigned int flags;
31fa8b18 7533
6c6aa15f 7534 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1ef7286e
AS		 7535 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7536 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7537 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6c6aa15f
HK		 7538 flags = PCI_IRQ_LEGACY;
7539 } else {
7540 flags = PCI_IRQ_ALL_TYPES;
31fa8b18 7541 }
6c6aa15f
HK		 7542
7543 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
31fa8b18
FR		 7544}
7545
c558386b
HW		 7546DECLARE_RTL_COND(rtl_link_list_ready_cond)
7547{
1ef7286e 7548 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
c558386b
HW		 7549}
7550
7551DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7552{
1ef7286e 7553 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
c558386b
HW		 7554}
7555
baf63293 7556static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b 7557{
c558386b
HW		 7558 u32 data;
7559
7560 tp->ocp_base = OCP_STD_PHY_BASE;
7561
1ef7286e 7562 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
c558386b
HW		 7563
7564 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7565 return;
7566
7567 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7568 return;
7569
1ef7286e 7570 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
c558386b 7571 msleep(1);
1ef7286e 7572 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
c558386b 7573
5f8bcce9 7574 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7575 data &= ~(1 << 14);
7576 r8168_mac_ocp_write(tp, 0xe8de, data);
7577
7578 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7579 return;
7580
5f8bcce9 7581 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7582 data |= (1 << 15);
7583 r8168_mac_ocp_write(tp, 0xe8de, data);
7584
7585 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7586 return;
7587}
7588
003609da
CHL		 7589static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7590{
7591 rtl8168ep_stop_cmac(tp);
7592 rtl_hw_init_8168g(tp);
7593}
7594
baf63293 7595static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 7596{
7597 switch (tp->mac_version) {
2a71883c 7598 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
003609da
CHL		 7599 rtl_hw_init_8168g(tp);
7600 break;
2a71883c 7601 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
003609da 7602 rtl_hw_init_8168ep(tp);
c558386b 7603 break;
c558386b
HW		 7604 default:
7605 break;
7606 }
7607}
7608
929a031d 7609static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 7610{
7611 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3b6cf25d
FR		 7612 struct rtl8169_private *tp;
7613 struct mii_if_info *mii;
7614 struct net_device *dev;
c8d48d9c 7615 int chipset, region, i;
3b6cf25d
FR		 7616 int rc;
7617
7618 if (netif_msg_drv(&debug)) {
7619 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
7620 MODULENAME, RTL8169_VERSION);
7621 }
7622
4c45d24a
HK		 7623 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7624 if (!dev)
7625 return -ENOMEM;
3b6cf25d
FR		 7626
7627 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 7628 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 7629 tp = netdev_priv(dev);
7630 tp->dev = dev;
7631 tp->pci_dev = pdev;
7632 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7633
7634 mii = &tp->mii;
7635 mii->dev = dev;
7636 mii->mdio_read = rtl_mdio_read;
7637 mii->mdio_write = rtl_mdio_write;
7638 mii->phy_id_mask = 0x1f;
7639 mii->reg_num_mask = 0x1f;
14967f94 7640 mii->supports_gmii = cfg->has_gmii;
3b6cf25d 7641
3b6cf25d 7642 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4c45d24a 7643 rc = pcim_enable_device(pdev);
3b6cf25d 7644 if (rc < 0) {
22148df0 7645 dev_err(&pdev->dev, "enable failure\n");
4c45d24a 7646 return rc;
3b6cf25d
FR		 7647 }
7648
4c45d24a 7649 if (pcim_set_mwi(pdev) < 0)
22148df0 7650 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
3b6cf25d 7651
c8d48d9c
HK		 7652 /* use first MMIO region */
7653 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7654 if (region < 0) {
22148df0 7655 dev_err(&pdev->dev, "no MMIO resource found\n");
4c45d24a 7656 return -ENODEV;
3b6cf25d
FR		 7657 }
7658
7659 /* check for weird/broken PCI region reporting */
7660 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
22148df0 7661 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
4c45d24a 7662 return -ENODEV;
3b6cf25d
FR		 7663 }
7664
93a00d4d 7665 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
3b6cf25d 7666 if (rc < 0) {
22148df0 7667 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
4c45d24a 7668 return rc;
3b6cf25d
FR		 7669 }
7670
93a00d4d 7671 tp->mmio_addr = pcim_iomap_table(pdev)[region];
3b6cf25d
FR		 7672
7673 if (!pci_is_pcie(pdev))
22148df0 7674 dev_info(&pdev->dev, "not PCI Express\n");
3b6cf25d
FR		 7675
7676 /* Identify chip attached to board */
22148df0 7677 rtl8169_get_mac_version(tp, cfg->default_ver);
3b6cf25d 7678
0ae0974e 7679 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
27896c83
AB		 7680
7681 if ((sizeof(dma_addr_t) > 4) &&
7682 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7683 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
f0076436
AB		 7684 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7685 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
27896c83
AB		 7686
7687 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7688 if (!pci_is_pcie(pdev))
7689 tp->cp_cmd |= PCIDAC;
7690 dev->features |= NETIF_F_HIGHDMA;
7691 } else {
7692 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7693 if (rc < 0) {
22148df0 7694 dev_err(&pdev->dev, "DMA configuration failed\n");
4c45d24a 7695 return rc;
27896c83
AB		 7696 }
7697 }
7698
3b6cf25d
FR		 7699 rtl_init_rxcfg(tp);
7700
7701 rtl_irq_disable(tp);
7702
c558386b
HW		 7703 rtl_hw_initialize(tp);
7704
3b6cf25d
FR		 7705 rtl_hw_reset(tp);
7706
7707 rtl_ack_events(tp, 0xffff);
7708
7709 pci_set_master(pdev);
7710
3b6cf25d 7711 rtl_init_mdio_ops(tp);
3b6cf25d
FR		 7712 rtl_init_jumbo_ops(tp);
7713
7714 rtl8169_print_mac_version(tp);
7715
7716 chipset = tp->mac_version;
3b6cf25d 7717
6c6aa15f
HK		 7718 rc = rtl_alloc_irq(tp);
7719 if (rc < 0) {
22148df0 7720 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6c6aa15f
HK		 7721 return rc;
7722 }
3b6cf25d 7723
7edf6d31
HK		 7724 /* override BIOS settings, use userspace tools to enable WOL */
7725 __rtl8169_set_wol(tp, 0);
7726
3b6cf25d
FR		 7727 if (rtl_tbi_enabled(tp)) {
7728 tp->set_speed = rtl8169_set_speed_tbi;
6fa1ba61 7729 tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi;
3b6cf25d
FR		 7730 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7731 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7732 tp->link_ok = rtl8169_tbi_link_ok;
7733 tp->do_ioctl = rtl_tbi_ioctl;
7734 } else {
7735 tp->set_speed = rtl8169_set_speed_xmii;
6fa1ba61 7736 tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii;
3b6cf25d
FR		 7737 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7738 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7739 tp->link_ok = rtl8169_xmii_link_ok;
7740 tp->do_ioctl = rtl_xmii_ioctl;
7741 }
7742
7743 mutex_init(&tp->wk.mutex);
340fea3d
KM		 7744 u64_stats_init(&tp->rx_stats.syncp);
7745 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 7746
7747 /* Get MAC address */
b2d43e6e 7748 switch (tp->mac_version) {
353af85e 7749 u8 mac_addr[ETH_ALEN] __aligned(4);
b2d43e6e
HK		 7750 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7751 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
05b9687b 7752 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
353af85e 7753 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89 7754
353af85e
HK		 7755 if (is_valid_ether_addr(mac_addr))
7756 rtl_rar_set(tp, mac_addr);
b2d43e6e
HK		 7757 break;
7758 default:
7759 break;
6e1d0b89 7760 }
3b6cf25d 7761 for (i = 0; i < ETH_ALEN; i++)
1ef7286e 7762 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
3b6cf25d 7763
7ad24ea4 7764 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 7765 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d 7766
37621493 7767 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
3b6cf25d
FR		 7768
7769 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7770 * properly for all devices */
7771 dev->features |= NETIF_F_RXCSUM |
f646968f 7772 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7773
7774 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 7775 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7776 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7777 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7778 NETIF_F_HIGHDMA;
7779
929a031d 7780 tp->cp_cmd |= RxChkSum | RxVlan;
7781
7782 /*
7783 * Pretend we are using VLANs; This bypasses a nasty bug where
7784 * Interrupts stop flowing on high load on 8110SCd controllers.
7785 */
3b6cf25d 7786 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 7787 /* Disallow toggling */
f646968f 7788 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 7789
a4328ddb
HK		 7790 switch (rtl_chip_infos[chipset].txd_version) {
7791 case RTL_TD_0:
5888d3fc 7792 tp->tso_csum = rtl8169_tso_csum_v1;
a4328ddb
HK		 7793 break;
7794 case RTL_TD_1:
5888d3fc 7795 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 7796 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
a4328ddb
HK		 7797 break;
7798 default:
5888d3fc 7799 WARN_ON_ONCE(1);
a4328ddb 7800 }
5888d3fc 7801
3b6cf25d
FR		 7802 dev->hw_features |= NETIF_F_RXALL;
7803 dev->hw_features |= NETIF_F_RXFCS;
7804
c7315a95
JW		 7805 /* MTU range: 60 - hw-specific max */
7806 dev->min_mtu = ETH_ZLEN;
7807 dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
7808
3b6cf25d
FR		 7809 tp->hw_start = cfg->hw_start;
7810 tp->event_slow = cfg->event_slow;
50970831 7811 tp->coalesce_info = cfg->coalesce_info;
3b6cf25d 7812
9de36ccf 7813 timer_setup(&tp->timer, rtl8169_phy_timer, 0);
3b6cf25d
FR		 7814
7815 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7816
4c45d24a
HK		 7817 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7818 &tp->counters_phys_addr,
7819 GFP_KERNEL);
4cf964af
HK		 7820 if (!tp->counters)
7821 return -ENOMEM;
42020320 7822
19c9ea36
HK		 7823 pci_set_drvdata(pdev, dev);
7824
3b6cf25d
FR		 7825 rc = register_netdev(dev);
7826 if (rc < 0)
4cf964af 7827 return rc;
3b6cf25d 7828
2d6c5a61
HK		 7829 netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7830 rtl_chip_infos[chipset].name, dev->dev_addr,
90b989c5 7831 (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
29274991 7832 pci_irq_vector(pdev, 0));
3b6cf25d
FR		 7833 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7834 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7835 "tx checksumming: %s]\n",
7836 rtl_chip_infos[chipset].jumbo_max,
6ed0e08f 7837 tp->mac_version <= RTL_GIGA_MAC_VER_06 ? "ok" : "ko");
3b6cf25d
FR		 7838 }
7839
9dbe7896 7840 if (r8168_check_dash(tp))
3b6cf25d 7841 rtl8168_driver_start(tp);
3b6cf25d 7842
3b6cf25d
FR		 7843 netif_carrier_off(dev);
7844
a92a0849
HK		 7845 if (pci_dev_run_wake(pdev))
7846 pm_runtime_put_sync(&pdev->dev);
7847
4c45d24a 7848 return 0;
3b6cf25d
FR		 7849}
7850
1da177e4
LT		 7851static struct pci_driver rtl8169_pci_driver = {
7852 .name = MODULENAME,
7853 .id_table = rtl8169_pci_tbl,
3b6cf25d 7854 .probe = rtl_init_one,
baf63293 7855 .remove = rtl_remove_one,
1765f95d 7856 .shutdown = rtl_shutdown,
861ab440 7857 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7858};
7859
3eeb7da9 7860module_pci_driver(rtl8169_pci_driver);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git