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selftests: Add fib-onlink-tests.sh to TEST_PROGS
[thirdparty/kernel/stable.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
a6b7a407 24#include <linux/interrupt.h>
1da177e4 25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
31#include <net/ip6_checksum.h>
1da177e4
LT		 32
33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 48#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 49#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 50#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 51#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 52#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 53#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 54#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 55#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 59
1da177e4
LT		 60#ifdef RTL8169_DEBUG
61#define assert(expr) \
5b0384f4
FR		 62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 64 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 65 }
06fa7358
JP		 66#define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 68#else
69#define assert(expr) do {} while (0)
70#define dprintk(fmt, args...) do {} while (0)
71#endif /* RTL8169_DEBUG */
72
b57b7e5a 73#define R8169_MSG_DEFAULT \
f0e837d9 74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 75
477206a0
JD		 76#define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80#define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 82
1da177e4
LT		 83/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 85static const int multicast_filter_limit = 32;
1da177e4 86
9c14ceaf 87#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 88#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 89#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91#define R8169_REGS_SIZE 256
92#define R8169_NAPI_WEIGHT 64
93#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 94#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 95#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98#define RTL8169_TX_TIMEOUT (6*HZ)
99#define RTL8169_PHY_TIMEOUT (10*HZ)
100
101/* write/read MMIO register */
102#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105#define RTL_R8(reg) readb (ioaddr + (reg))
106#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 107#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 108
109enum mac_version {
85bffe6c
FR		 110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
70090424 143 RTL_GIGA_MAC_VER_34,
c2218925
HW		 144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
7e18dca1 146 RTL_GIGA_MAC_VER_37,
b3d7b2f2 147 RTL_GIGA_MAC_VER_38,
5598bfe5 148 RTL_GIGA_MAC_VER_39,
c558386b
HW		 149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
57538c4a 151 RTL_GIGA_MAC_VER_42,
58152cd4 152 RTL_GIGA_MAC_VER_43,
45dd95c4 153 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 158 RTL_GIGA_MAC_VER_49,
159 RTL_GIGA_MAC_VER_50,
160 RTL_GIGA_MAC_VER_51,
85bffe6c 161 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 162};
163
2b7b4318
FR		 164enum rtl_tx_desc_version {
165 RTL_TD_0 = 0,
166 RTL_TD_1 = 1,
167};
168
d58d46b5
FR		 169#define JUMBO_1K ETH_DATA_LEN
170#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
174
175#define _R(NAME,TD,FW,SZ,B) { \
176 .name = NAME, \
177 .txd_version = TD, \
178 .fw_name = FW, \
179 .jumbo_max = SZ, \
180 .jumbo_tx_csum = B \
181}
1da177e4 182
3c6bee1d 183static const struct {
1da177e4 184 const char *name;
2b7b4318 185 enum rtl_tx_desc_version txd_version;
953a12cc 186 const char *fw_name;
d58d46b5
FR		 187 u16 jumbo_max;
188 bool jumbo_tx_csum;
85bffe6c
FR		 189} rtl_chip_infos[] = {
190 /* PCI devices. */
191 [RTL_GIGA_MAC_VER_01] =
d58d46b5 192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 193 [RTL_GIGA_MAC_VER_02] =
d58d46b5 194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 195 [RTL_GIGA_MAC_VER_03] =
d58d46b5 196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 197 [RTL_GIGA_MAC_VER_04] =
d58d46b5 198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 199 [RTL_GIGA_MAC_VER_05] =
d58d46b5 200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 201 [RTL_GIGA_MAC_VER_06] =
d58d46b5 202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 203 /* PCI-E devices. */
204 [RTL_GIGA_MAC_VER_07] =
d58d46b5 205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_08] =
d58d46b5 207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 208 [RTL_GIGA_MAC_VER_09] =
d58d46b5 209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 210 [RTL_GIGA_MAC_VER_10] =
d58d46b5 211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 212 [RTL_GIGA_MAC_VER_11] =
d58d46b5 213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_12] =
d58d46b5 215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_13] =
d58d46b5 217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 218 [RTL_GIGA_MAC_VER_14] =
d58d46b5 219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 220 [RTL_GIGA_MAC_VER_15] =
d58d46b5 221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 222 [RTL_GIGA_MAC_VER_16] =
d58d46b5 223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 224 [RTL_GIGA_MAC_VER_17] =
f75761b6 225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 226 [RTL_GIGA_MAC_VER_18] =
d58d46b5 227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_19] =
d58d46b5 229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 230 [RTL_GIGA_MAC_VER_20] =
d58d46b5 231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 232 [RTL_GIGA_MAC_VER_21] =
d58d46b5 233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_22] =
d58d46b5 235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 236 [RTL_GIGA_MAC_VER_23] =
d58d46b5 237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 238 [RTL_GIGA_MAC_VER_24] =
d58d46b5 239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 240 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
242 JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
245 JUMBO_9K, false),
85bffe6c 246 [RTL_GIGA_MAC_VER_27] =
d58d46b5 247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 248 [RTL_GIGA_MAC_VER_28] =
d58d46b5 249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 250 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
85bffe6c 253 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
255 JUMBO_1K, true),
85bffe6c 256 [RTL_GIGA_MAC_VER_31] =
d58d46b5 257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 258 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
260 JUMBO_9K, false),
85bffe6c 261 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
263 JUMBO_9K, false),
70090424 264 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
266 JUMBO_9K, false),
c2218925 267 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
269 JUMBO_9K, false),
c2218925 270 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
272 JUMBO_9K, false),
7e18dca1
HW		 273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
275 JUMBO_1K, true),
b3d7b2f2
HW		 276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
278 JUMBO_9K, false),
5598bfe5
HW		 279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
281 JUMBO_1K, true),
c558386b 282 [RTL_GIGA_MAC_VER_40] =
beb330a4 283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
c558386b
HW		 284 JUMBO_9K, false),
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
57538c4a 287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
289 JUMBO_9K, false),
58152cd4 290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
292 JUMBO_1K, true),
45dd95c4 293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
295 JUMBO_9K, false),
6e1d0b89
CHL		 296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
301 JUMBO_9K, false),
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
304 JUMBO_1K, false),
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
307 JUMBO_1K, false),
935e2218
CHL		 308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
310 JUMBO_9K, false),
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
313 JUMBO_9K, false),
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
316 JUMBO_9K, false),
953a12cc 317};
85bffe6c 318#undef _R
953a12cc 319
bcf0bf90
FR		 320enum cfg_version {
321 RTL_CFG_0 = 0x00,
322 RTL_CFG_1,
323 RTL_CFG_2
324};
325
9baa3c34 326static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
610c9087 329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
d81bf551 330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 332 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 333 { PCI_VENDOR_ID_DLINK, 0x4300,
334 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 336 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 337 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 338 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
339 { PCI_VENDOR_ID_LINKSYS, 0x1032,
340 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 341 { 0x0001, 0x8168,
342 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 343 {0,},
344};
345
346MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
347
6f0333b8 348static int rx_buf_sz = 16383;
27896c83 349static int use_dac = -1;
b57b7e5a
SH		 350static struct {
351 u32 msg_enable;
352} debug = { -1 };
1da177e4 353
07d3f51f
FR		 354enum rtl_registers {
355 MAC0 = 0, /* Ethernet hardware address. */
773d2021 356 MAC4 = 4,
07d3f51f
FR		 357 MAR0 = 8, /* Multicast filter. */
358 CounterAddrLow = 0x10,
359 CounterAddrHigh = 0x14,
360 TxDescStartAddrLow = 0x20,
361 TxDescStartAddrHigh = 0x24,
362 TxHDescStartAddrLow = 0x28,
363 TxHDescStartAddrHigh = 0x2c,
364 FLASH = 0x30,
365 ERSR = 0x36,
366 ChipCmd = 0x37,
367 TxPoll = 0x38,
368 IntrMask = 0x3c,
369 IntrStatus = 0x3e,
4f6b00e5 370
07d3f51f 371 TxConfig = 0x40,
4f6b00e5
HW		 372#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
373#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 374
4f6b00e5
HW		 375 RxConfig = 0x44,
376#define RX128_INT_EN (1 << 15) /* 8111c and later */
377#define RX_MULTI_EN (1 << 14) /* 8111c only */
378#define RXCFG_FIFO_SHIFT 13
379 /* No threshold before first PCI xfer */
380#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 381#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 382#define RXCFG_DMA_SHIFT 8
383 /* Unlimited maximum PCI burst. */
384#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 385
07d3f51f
FR		 386 RxMissed = 0x4c,
387 Cfg9346 = 0x50,
388 Config0 = 0x51,
389 Config1 = 0x52,
390 Config2 = 0x53,
d387b427
FR		 391#define PME_SIGNAL (1 << 5) /* 8168c and later */
392
07d3f51f
FR		 393 Config3 = 0x54,
394 Config4 = 0x55,
395 Config5 = 0x56,
396 MultiIntr = 0x5c,
397 PHYAR = 0x60,
07d3f51f
FR		 398 PHYstatus = 0x6c,
399 RxMaxSize = 0xda,
400 CPlusCmd = 0xe0,
401 IntrMitigate = 0xe2,
50970831
FR		 402
403#define RTL_COALESCE_MASK 0x0f
404#define RTL_COALESCE_SHIFT 4
405#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
406#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
407
07d3f51f
FR		 408 RxDescAddrLow = 0xe4,
409 RxDescAddrHigh = 0xe8,
f0298f81 410 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
411
412#define NoEarlyTx 0x3f /* Max value : no early transmit. */
413
414 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
415
416#define TxPacketMax (8064 >> 7)
3090bd9a 417#define EarlySize 0x27
f0298f81 418
07d3f51f
FR		 419 FuncEvent = 0xf0,
420 FuncEventMask = 0xf4,
421 FuncPresetState = 0xf8,
935e2218
CHL		 422 IBCR0 = 0xf8,
423 IBCR2 = 0xf9,
424 IBIMR0 = 0xfa,
425 IBISR0 = 0xfb,
07d3f51f 426 FuncForceEvent = 0xfc,
1da177e4
LT		 427};
428
f162a5d1
FR		 429enum rtl8110_registers {
430 TBICSR = 0x64,
431 TBI_ANAR = 0x68,
432 TBI_LPAR = 0x6a,
433};
434
435enum rtl8168_8101_registers {
436 CSIDR = 0x64,
437 CSIAR = 0x68,
438#define CSIAR_FLAG 0x80000000
439#define CSIAR_WRITE_CMD 0x80000000
440#define CSIAR_BYTE_ENABLE 0x0f
441#define CSIAR_BYTE_ENABLE_SHIFT 12
442#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 443#define CSIAR_FUNC_CARD 0x00000000
444#define CSIAR_FUNC_SDIO 0x00010000
445#define CSIAR_FUNC_NIC 0x00020000
45dd95c4 446#define CSIAR_FUNC_NIC2 0x00010000
065c27c1 447 PMCH = 0x6f,
f162a5d1
FR		 448 EPHYAR = 0x80,
449#define EPHYAR_FLAG 0x80000000
450#define EPHYAR_WRITE_CMD 0x80000000
451#define EPHYAR_REG_MASK 0x1f
452#define EPHYAR_REG_SHIFT 16
453#define EPHYAR_DATA_MASK 0xffff
5a5e4443 454 DLLPR = 0xd0,
4f6b00e5 455#define PFM_EN (1 << 6)
6e1d0b89 456#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 457 DBG_REG = 0xd1,
458#define FIX_NAK_1 (1 << 4)
459#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 460 TWSI = 0xd2,
461 MCU = 0xd3,
4f6b00e5 462#define NOW_IS_OOB (1 << 7)
c558386b
HW		 463#define TX_EMPTY (1 << 5)
464#define RX_EMPTY (1 << 4)
465#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 466#define EN_NDP (1 << 3)
467#define EN_OOB_RESET (1 << 2)
c558386b 468#define LINK_LIST_RDY (1 << 1)
daf9df6d 469 EFUSEAR = 0xdc,
470#define EFUSEAR_FLAG 0x80000000
471#define EFUSEAR_WRITE_CMD 0x80000000
472#define EFUSEAR_READ_CMD 0x00000000
473#define EFUSEAR_REG_MASK 0x03ff
474#define EFUSEAR_REG_SHIFT 8
475#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 476 MISC_1 = 0xf2,
477#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 478};
479
c0e45c1c 480enum rtl8168_registers {
4f6b00e5
HW		 481 LED_FREQ = 0x1a,
482 EEE_LED = 0x1b,
b646d900 483 ERIDR = 0x70,
484 ERIAR = 0x74,
485#define ERIAR_FLAG 0x80000000
486#define ERIAR_WRITE_CMD 0x80000000
487#define ERIAR_READ_CMD 0x00000000
488#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 489#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 490#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
491#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
492#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 493#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 494#define ERIAR_MASK_SHIFT 12
495#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
496#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 497#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 498#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 499#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 500 EPHY_RXER_NUM = 0x7c,
501 OCPDR = 0xb0, /* OCP GPHY access */
502#define OCPDR_WRITE_CMD 0x80000000
503#define OCPDR_READ_CMD 0x00000000
504#define OCPDR_REG_MASK 0x7f
505#define OCPDR_GPHY_REG_SHIFT 16
506#define OCPDR_DATA_MASK 0xffff
507 OCPAR = 0xb4,
508#define OCPAR_FLAG 0x80000000
509#define OCPAR_GPHY_WRITE_CMD 0x8000f060
510#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 511 GPHY_OCP = 0xb8,
01dc7fec 512 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
513 MISC = 0xf0, /* 8168e only. */
cecb5fd7 514#define TXPLA_RST (1 << 29)
5598bfe5 515#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 516#define PWM_EN (1 << 22)
c558386b 517#define RXDV_GATED_EN (1 << 19)
5598bfe5 518#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 519};
520
07d3f51f 521enum rtl_register_content {
1da177e4 522 /* InterruptStatusBits */
07d3f51f
FR		 523 SYSErr = 0x8000,
524 PCSTimeout = 0x4000,
525 SWInt = 0x0100,
526 TxDescUnavail = 0x0080,
527 RxFIFOOver = 0x0040,
528 LinkChg = 0x0020,
529 RxOverflow = 0x0010,
530 TxErr = 0x0008,
531 TxOK = 0x0004,
532 RxErr = 0x0002,
533 RxOK = 0x0001,
1da177e4
LT		 534
535 /* RxStatusDesc */
e03f33af 536 RxBOVF = (1 << 24),
9dccf611
FR		 537 RxFOVF = (1 << 23),
538 RxRWT = (1 << 22),
539 RxRES = (1 << 21),
540 RxRUNT = (1 << 20),
541 RxCRC = (1 << 19),
1da177e4
LT		 542
543 /* ChipCmdBits */
4f6b00e5 544 StopReq = 0x80,
07d3f51f
FR		 545 CmdReset = 0x10,
546 CmdRxEnb = 0x08,
547 CmdTxEnb = 0x04,
548 RxBufEmpty = 0x01,
1da177e4 549
275391a4
FR		 550 /* TXPoll register p.5 */
551 HPQ = 0x80, /* Poll cmd on the high prio queue */
552 NPQ = 0x40, /* Poll cmd on the low prio queue */
553 FSWInt = 0x01, /* Forced software interrupt */
554
1da177e4 555 /* Cfg9346Bits */
07d3f51f
FR		 556 Cfg9346_Lock = 0x00,
557 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 558
559 /* rx_mode_bits */
07d3f51f
FR		 560 AcceptErr = 0x20,
561 AcceptRunt = 0x10,
562 AcceptBroadcast = 0x08,
563 AcceptMulticast = 0x04,
564 AcceptMyPhys = 0x02,
565 AcceptAllPhys = 0x01,
1687b566 566#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 567
1da177e4
LT		 568 /* TxConfigBits */
569 TxInterFrameGapShift = 24,
570 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
571
5d06a99f 572 /* Config1 register p.24 */
f162a5d1
FR		 573 LEDS1 = (1 << 7),
574 LEDS0 = (1 << 6),
f162a5d1
FR		 575 Speed_down = (1 << 4),
576 MEMMAP = (1 << 3),
577 IOMAP = (1 << 2),
578 VPD = (1 << 1),
5d06a99f
FR		 579 PMEnable = (1 << 0), /* Power Management Enable */
580
6dccd16b 581 /* Config2 register p. 25 */
57538c4a 582 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 583 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 584 PCI_Clock_66MHz = 0x01,
585 PCI_Clock_33MHz = 0x00,
586
61a4dcc2
FR		 587 /* Config3 register p.25 */
588 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
589 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 590 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 591 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 592 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 593
d58d46b5
FR		 594 /* Config4 register */
595 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
596
5d06a99f 597 /* Config5 register p.27 */
61a4dcc2
FR		 598 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
599 MWF = (1 << 5), /* Accept Multicast wakeup frame */
600 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 601 Spi_en = (1 << 3),
61a4dcc2 602 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 603 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 604 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 605
1da177e4
LT		 606 /* TBICSR p.28 */
607 TBIReset = 0x80000000,
608 TBILoopback = 0x40000000,
609 TBINwEnable = 0x20000000,
610 TBINwRestart = 0x10000000,
611 TBILinkOk = 0x02000000,
612 TBINwComplete = 0x01000000,
613
614 /* CPlusCmd p.31 */
f162a5d1
FR		 615 EnableBist = (1 << 15), // 8168 8101
616 Mac_dbgo_oe = (1 << 14), // 8168 8101
617 Normal_mode = (1 << 13), // unused
618 Force_half_dup = (1 << 12), // 8168 8101
619 Force_rxflow_en = (1 << 11), // 8168 8101
620 Force_txflow_en = (1 << 10), // 8168 8101
621 Cxpl_dbg_sel = (1 << 9), // 8168 8101
622 ASF = (1 << 8), // 8168 8101
623 PktCntrDisable = (1 << 7), // 8168 8101
624 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 625 RxVlan = (1 << 6),
626 RxChkSum = (1 << 5),
627 PCIDAC = (1 << 4),
628 PCIMulRW = (1 << 3),
0e485150
FR		 629 INTT_0 = 0x0000, // 8168
630 INTT_1 = 0x0001, // 8168
631 INTT_2 = 0x0002, // 8168
632 INTT_3 = 0x0003, // 8168
1da177e4
LT		 633
634 /* rtl8169_PHYstatus */
07d3f51f
FR		 635 TBI_Enable = 0x80,
636 TxFlowCtrl = 0x40,
637 RxFlowCtrl = 0x20,
638 _1000bpsF = 0x10,
639 _100bps = 0x08,
640 _10bps = 0x04,
641 LinkStatus = 0x02,
642 FullDup = 0x01,
1da177e4 643
1da177e4 644 /* _TBICSRBit */
07d3f51f 645 TBILinkOK = 0x02000000,
d4a3a0fc 646
6e85d5ad
CV		 647 /* ResetCounterCommand */
648 CounterReset = 0x1,
649
d4a3a0fc 650 /* DumpCounterCommand */
07d3f51f 651 CounterDump = 0x8,
6e1d0b89
CHL		 652
653 /* magic enable v2 */
654 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 655};
656
2b7b4318
FR		 657enum rtl_desc_bit {
658 /* First doubleword. */
1da177e4
LT		 659 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
660 RingEnd = (1 << 30), /* End of descriptor ring */
661 FirstFrag = (1 << 29), /* First segment of a packet */
662 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 663};
664
665/* Generic case. */
666enum rtl_tx_desc_bit {
667 /* First doubleword. */
668 TD_LSO = (1 << 27), /* Large Send Offload */
669#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 670
2b7b4318
FR		 671 /* Second doubleword. */
672 TxVlanTag = (1 << 17), /* Add VLAN tag */
673};
674
675/* 8169, 8168b and 810x except 8102e. */
676enum rtl_tx_desc_bit_0 {
677 /* First doubleword. */
678#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
679 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
680 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
681 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
682};
683
684/* 8102e, 8168c and beyond. */
685enum rtl_tx_desc_bit_1 {
bdfa4ed6 686 /* First doubleword. */
687 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 688 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 689#define GTTCPHO_SHIFT 18
e974604b 690#define GTTCPHO_MAX 0x7fU
bdfa4ed6 691
2b7b4318 692 /* Second doubleword. */
e974604b 693#define TCPHO_SHIFT 18
694#define TCPHO_MAX 0x3ffU
2b7b4318 695#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 696 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
697 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 698 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
699 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
700};
1da177e4 701
2b7b4318 702enum rtl_rx_desc_bit {
1da177e4
LT		 703 /* Rx private */
704 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 705 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 706
707#define RxProtoUDP (PID1)
708#define RxProtoTCP (PID0)
709#define RxProtoIP (PID1 | PID0)
710#define RxProtoMask RxProtoIP
711
712 IPFail = (1 << 16), /* IP checksum failed */
713 UDPFail = (1 << 15), /* UDP/IP checksum failed */
714 TCPFail = (1 << 14), /* TCP/IP checksum failed */
715 RxVlanTag = (1 << 16), /* VLAN tag available */
716};
717
718#define RsvdMask 0x3fffc000
719
720struct TxDesc {
6cccd6e7
REB		 721 __le32 opts1;
722 __le32 opts2;
723 __le64 addr;
1da177e4
LT		 724};
725
726struct RxDesc {
6cccd6e7
REB		 727 __le32 opts1;
728 __le32 opts2;
729 __le64 addr;
1da177e4
LT		 730};
731
732struct ring_info {
733 struct sk_buff *skb;
734 u32 len;
735 u8 __pad[sizeof(void *) - sizeof(u32)];
736};
737
f23e7fda 738enum features {
022ddbca
HK		 739 RTL_FEATURE_MSI = (1 << 0),
740 RTL_FEATURE_GMII = (1 << 1),
f23e7fda
FR		 741};
742
355423d0
IV		 743struct rtl8169_counters {
744 __le64 tx_packets;
745 __le64 rx_packets;
746 __le64 tx_errors;
747 __le32 rx_errors;
748 __le16 rx_missed;
749 __le16 align_errors;
750 __le32 tx_one_collision;
751 __le32 tx_multi_collision;
752 __le64 rx_unicast;
753 __le64 rx_broadcast;
754 __le32 rx_multicast;
755 __le16 tx_aborted;
756 __le16 tx_underun;
757};
758
6e85d5ad
CV		 759struct rtl8169_tc_offsets {
760 bool inited;
761 __le64 tx_errors;
762 __le32 tx_multi_collision;
6e85d5ad
CV		 763 __le16 tx_aborted;
764};
765
da78dbff 766enum rtl_flag {
6c4a70c5 767 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 768 RTL_FLAG_TASK_SLOW_PENDING,
769 RTL_FLAG_TASK_RESET_PENDING,
770 RTL_FLAG_TASK_PHY_PENDING,
771 RTL_FLAG_MAX
772};
773
8027aa24
JW		 774struct rtl8169_stats {
775 u64 packets;
776 u64 bytes;
777 struct u64_stats_sync syncp;
778};
779
1da177e4
LT		 780struct rtl8169_private {
781 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 782 struct pci_dev *pci_dev;
c4028958 783 struct net_device *dev;
bea3348e 784 struct napi_struct napi;
b57b7e5a 785 u32 msg_enable;
2b7b4318
FR		 786 u16 txd_version;
787 u16 mac_version;
1da177e4
LT		 788 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
789 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 790 u32 dirty_tx;
8027aa24
JW		 791 struct rtl8169_stats rx_stats;
792 struct rtl8169_stats tx_stats;
1da177e4
LT		 793 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
794 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
795 dma_addr_t TxPhyAddr;
796 dma_addr_t RxPhyAddr;
6f0333b8 797 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 798 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 799 struct timer_list timer;
800 u16 cp_cmd;
da78dbff
FR		 801
802 u16 event_slow;
50970831 803 const struct rtl_coalesce_info *coalesce_info;
c0e45c1c 804
805 struct mdio_ops {
24192210
FR		 806 void (*write)(struct rtl8169_private *, int, int);
807 int (*read)(struct rtl8169_private *, int);
c0e45c1c 808 } mdio_ops;
809
065c27c1 810 struct pll_power_ops {
811 void (*down)(struct rtl8169_private *);
812 void (*up)(struct rtl8169_private *);
813 } pll_power_ops;
814
d58d46b5
FR		 815 struct jumbo_ops {
816 void (*enable)(struct rtl8169_private *);
817 void (*disable)(struct rtl8169_private *);
818 } jumbo_ops;
819
beb1fe18 820 struct csi_ops {
52989f0e
FR		 821 void (*write)(struct rtl8169_private *, int, int);
822 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 823 } csi_ops;
824
54405cde 825 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
6fa1ba61
PR		 826 int (*get_link_ksettings)(struct net_device *,
827 struct ethtool_link_ksettings *);
4da19633 828 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 829 void (*hw_start)(struct net_device *);
4da19633 830 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 831 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 832 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
5888d3fc 833 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 834
835 struct {
da78dbff
FR		 836 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
837 struct mutex mutex;
4422bcd4
FR		 838 struct work_struct work;
839 } wk;
840
f23e7fda 841 unsigned features;
ccdffb9a
FR		 842
843 struct mii_if_info mii;
42020320
CV		 844 dma_addr_t counters_phys_addr;
845 struct rtl8169_counters *counters;
6e85d5ad 846 struct rtl8169_tc_offsets tc_offset;
e1759441 847 u32 saved_wolopts;
e03f33af 848 u32 opts1_mask;
f1e02ed1 849
b6ffd97f
FR		 850 struct rtl_fw {
851 const struct firmware *fw;
1c361efb
FR		 852
853#define RTL_VER_SIZE 32
854
855 char version[RTL_VER_SIZE];
856
857 struct rtl_fw_phy_action {
858 __le32 *code;
859 size_t size;
860 } phy_action;
b6ffd97f 861 } *rtl_fw;
497888cf 862#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 863
864 u32 ocp_base;
1da177e4
LT		 865};
866
979b6c13 867MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 868MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 869module_param(use_dac, int, 0);
4300e8c7 870MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 871module_param_named(debug, debug.msg_enable, int, 0);
872MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 873MODULE_LICENSE("GPL");
874MODULE_VERSION(RTL8169_VERSION);
bca03d5f 875MODULE_FIRMWARE(FIRMWARE_8168D_1);
876MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 877MODULE_FIRMWARE(FIRMWARE_8168E_1);
878MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 879MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 880MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 881MODULE_FIRMWARE(FIRMWARE_8168F_1);
882MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 883MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 884MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 885MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 886MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 887MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 888MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 889MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 890MODULE_FIRMWARE(FIRMWARE_8168H_1);
891MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 892MODULE_FIRMWARE(FIRMWARE_8107E_1);
893MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 894
da78dbff
FR		 895static void rtl_lock_work(struct rtl8169_private *tp)
896{
897 mutex_lock(&tp->wk.mutex);
898}
899
900static void rtl_unlock_work(struct rtl8169_private *tp)
901{
902 mutex_unlock(&tp->wk.mutex);
903}
904
d58d46b5
FR		 905static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
906{
7d7903b2
JL		 907 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
908 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 909}
910
ffc46952
FR		 911struct rtl_cond {
912 bool (*check)(struct rtl8169_private *);
913 const char *msg;
914};
915
916static void rtl_udelay(unsigned int d)
917{
918 udelay(d);
919}
920
921static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
922 void (*delay)(unsigned int), unsigned int d, int n,
923 bool high)
924{
925 int i;
926
927 for (i = 0; i < n; i++) {
928 delay(d);
929 if (c->check(tp) == high)
930 return true;
931 }
82e316ef
FR		 932 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
933 c->msg, !high, n, d);
ffc46952
FR		 934 return false;
935}
936
937static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
938 const struct rtl_cond *c,
939 unsigned int d, int n)
940{
941 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
942}
943
944static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
945 const struct rtl_cond *c,
946 unsigned int d, int n)
947{
948 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
949}
950
951static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
952 const struct rtl_cond *c,
953 unsigned int d, int n)
954{
955 return rtl_loop_wait(tp, c, msleep, d, n, true);
956}
957
958static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
959 const struct rtl_cond *c,
960 unsigned int d, int n)
961{
962 return rtl_loop_wait(tp, c, msleep, d, n, false);
963}
964
965#define DECLARE_RTL_COND(name) \
966static bool name ## _check(struct rtl8169_private *); \
967 \
968static const struct rtl_cond name = { \
969 .check = name ## _check, \
970 .msg = #name \
971}; \
972 \
973static bool name ## _check(struct rtl8169_private *tp)
974
c558386b
HW		 975static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
976{
977 if (reg & 0xffff0001) {
978 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
979 return true;
980 }
981 return false;
982}
983
984DECLARE_RTL_COND(rtl_ocp_gphy_cond)
985{
986 void __iomem *ioaddr = tp->mmio_addr;
987
988 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
989}
990
991static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
992{
993 void __iomem *ioaddr = tp->mmio_addr;
994
995 if (rtl_ocp_reg_failure(tp, reg))
996 return;
997
998 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
999
1000 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1001}
1002
1003static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1004{
1005 void __iomem *ioaddr = tp->mmio_addr;
1006
1007 if (rtl_ocp_reg_failure(tp, reg))
1008 return 0;
1009
1010 RTL_W32(GPHY_OCP, reg << 15);
1011
1012 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1013 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1014}
1015
c558386b
HW		 1016static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1017{
1018 void __iomem *ioaddr = tp->mmio_addr;
1019
1020 if (rtl_ocp_reg_failure(tp, reg))
1021 return;
1022
1023 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1024}
1025
1026static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1027{
1028 void __iomem *ioaddr = tp->mmio_addr;
1029
1030 if (rtl_ocp_reg_failure(tp, reg))
1031 return 0;
1032
1033 RTL_W32(OCPDR, reg << 15);
1034
3a83ad12 1035 return RTL_R32(OCPDR);
c558386b
HW		 1036}
1037
1038#define OCP_STD_PHY_BASE 0xa400
1039
1040static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1041{
1042 if (reg == 0x1f) {
1043 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1044 return;
1045 }
1046
1047 if (tp->ocp_base != OCP_STD_PHY_BASE)
1048 reg -= 0x10;
1049
1050 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1051}
1052
1053static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1054{
1055 if (tp->ocp_base != OCP_STD_PHY_BASE)
1056 reg -= 0x10;
1057
1058 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1059}
1060
eee3786f 1061static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1062{
1063 if (reg == 0x1f) {
1064 tp->ocp_base = value << 4;
1065 return;
1066 }
1067
1068 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1069}
1070
1071static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1072{
1073 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1074}
1075
ffc46952
FR		 1076DECLARE_RTL_COND(rtl_phyar_cond)
1077{
1078 void __iomem *ioaddr = tp->mmio_addr;
1079
1080 return RTL_R32(PHYAR) & 0x80000000;
1081}
1082
24192210 1083static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1084{
24192210 1085 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1086
24192210 1087 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1088
ffc46952 1089 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1090 /*
81a95f04
TT		 1091 * According to hardware specs a 20us delay is required after write
1092 * complete indication, but before sending next command.
024a07ba 1093 */
81a95f04 1094 udelay(20);
1da177e4
LT		 1095}
1096
24192210 1097static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1098{
24192210 1099 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1100 int value;
1da177e4 1101
24192210 1102 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1103
ffc46952
FR		 1104 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1105 RTL_R32(PHYAR) & 0xffff : ~0;
1106
81a95f04
TT		 1107 /*
1108 * According to hardware specs a 20us delay is required after read
1109 * complete indication, but before sending next command.
1110 */
1111 udelay(20);
1112
1da177e4
LT		 1113 return value;
1114}
1115
935e2218
CHL		 1116DECLARE_RTL_COND(rtl_ocpar_cond)
1117{
1118 void __iomem *ioaddr = tp->mmio_addr;
1119
1120 return RTL_R32(OCPAR) & OCPAR_FLAG;
1121}
1122
24192210 1123static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1124{
24192210 1125 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1126
24192210 1127 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1128 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1129 RTL_W32(EPHY_RXER_NUM, 0);
1130
ffc46952 1131 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1132}
1133
24192210 1134static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1135{
24192210
FR		 1136 r8168dp_1_mdio_access(tp, reg,
1137 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1138}
1139
24192210 1140static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1141{
24192210 1142 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1143
24192210 1144 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1145
1146 mdelay(1);
1147 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1148 RTL_W32(EPHY_RXER_NUM, 0);
1149
ffc46952
FR		 1150 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1151 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1152}
1153
e6de30d6 1154#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1155
1156static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1157{
1158 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1159}
1160
1161static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1162{
1163 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1164}
1165
24192210 1166static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1167{
24192210
FR		 1168 void __iomem *ioaddr = tp->mmio_addr;
1169
e6de30d6 1170 r8168dp_2_mdio_start(ioaddr);
1171
24192210 1172 r8169_mdio_write(tp, reg, value);
e6de30d6 1173
1174 r8168dp_2_mdio_stop(ioaddr);
1175}
1176
24192210 1177static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1178{
24192210 1179 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1180 int value;
1181
1182 r8168dp_2_mdio_start(ioaddr);
1183
24192210 1184 value = r8169_mdio_read(tp, reg);
e6de30d6 1185
1186 r8168dp_2_mdio_stop(ioaddr);
1187
1188 return value;
1189}
1190
4da19633 1191static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1192{
24192210 1193 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1194}
1195
4da19633 1196static int rtl_readphy(struct rtl8169_private *tp, int location)
1197{
24192210 1198 return tp->mdio_ops.read(tp, location);
4da19633 1199}
1200
1201static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1202{
1203 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1204}
1205
76564428 1206static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1207{
1208 int val;
1209
4da19633 1210 val = rtl_readphy(tp, reg_addr);
76564428 1211 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1212}
1213
ccdffb9a
FR		 1214static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1215 int val)
1216{
1217 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1218
4da19633 1219 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1220}
1221
1222static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1223{
1224 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1225
4da19633 1226 return rtl_readphy(tp, location);
ccdffb9a
FR		 1227}
1228
ffc46952
FR		 1229DECLARE_RTL_COND(rtl_ephyar_cond)
1230{
1231 void __iomem *ioaddr = tp->mmio_addr;
1232
1233 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1234}
1235
fdf6fc06 1236static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1237{
fdf6fc06 1238 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1239
1240 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1241 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1242
ffc46952
FR		 1243 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1244
1245 udelay(10);
dacf8154
FR		 1246}
1247
fdf6fc06 1248static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1249{
fdf6fc06 1250 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1251
1252 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1253
ffc46952
FR		 1254 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1255 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1256}
1257
935e2218
CHL		 1258DECLARE_RTL_COND(rtl_eriar_cond)
1259{
1260 void __iomem *ioaddr = tp->mmio_addr;
1261
1262 return RTL_R32(ERIAR) & ERIAR_FLAG;
1263}
1264
fdf6fc06
FR		 1265static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1266 u32 val, int type)
133ac40a 1267{
fdf6fc06 1268 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1269
1270 BUG_ON((addr & 3) || (mask == 0));
1271 RTL_W32(ERIDR, val);
1272 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1273
ffc46952 1274 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1275}
1276
fdf6fc06 1277static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1278{
fdf6fc06 1279 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1280
1281 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1282
ffc46952
FR		 1283 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1284 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1285}
1286
706123d0 1287static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1288 u32 m, int type)
133ac40a
HW		 1289{
1290 u32 val;
1291
fdf6fc06
FR		 1292 val = rtl_eri_read(tp, addr, type);
1293 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1294}
1295
935e2218
CHL		 1296static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1297{
1298 void __iomem *ioaddr = tp->mmio_addr;
1299
1300 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1301 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1302 RTL_R32(OCPDR) : ~0;
1303}
1304
1305static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1306{
1307 return rtl_eri_read(tp, reg, ERIAR_OOB);
1308}
1309
1310static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1311{
1312 switch (tp->mac_version) {
1313 case RTL_GIGA_MAC_VER_27:
1314 case RTL_GIGA_MAC_VER_28:
1315 case RTL_GIGA_MAC_VER_31:
1316 return r8168dp_ocp_read(tp, mask, reg);
1317 case RTL_GIGA_MAC_VER_49:
1318 case RTL_GIGA_MAC_VER_50:
1319 case RTL_GIGA_MAC_VER_51:
1320 return r8168ep_ocp_read(tp, mask, reg);
1321 default:
1322 BUG();
1323 return ~0;
1324 }
1325}
1326
1327static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1328 u32 data)
1329{
1330 void __iomem *ioaddr = tp->mmio_addr;
1331
1332 RTL_W32(OCPDR, data);
1333 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1334 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1335}
1336
1337static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1338 u32 data)
1339{
1340 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1341 data, ERIAR_OOB);
1342}
1343
1344static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1345{
1346 switch (tp->mac_version) {
1347 case RTL_GIGA_MAC_VER_27:
1348 case RTL_GIGA_MAC_VER_28:
1349 case RTL_GIGA_MAC_VER_31:
1350 r8168dp_ocp_write(tp, mask, reg, data);
1351 break;
1352 case RTL_GIGA_MAC_VER_49:
1353 case RTL_GIGA_MAC_VER_50:
1354 case RTL_GIGA_MAC_VER_51:
1355 r8168ep_ocp_write(tp, mask, reg, data);
1356 break;
1357 default:
1358 BUG();
1359 break;
1360 }
1361}
1362
2a9b4d96
CHL		 1363static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1364{
1365 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1366
1367 ocp_write(tp, 0x1, 0x30, 0x00000001);
1368}
1369
1370#define OOB_CMD_RESET 0x00
1371#define OOB_CMD_DRIVER_START 0x05
1372#define OOB_CMD_DRIVER_STOP 0x06
1373
1374static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1375{
1376 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1377}
1378
1379DECLARE_RTL_COND(rtl_ocp_read_cond)
1380{
1381 u16 reg;
1382
1383 reg = rtl8168_get_ocp_reg(tp);
1384
1385 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1386}
1387
935e2218 1388DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1389{
935e2218
CHL		 1390 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1391}
1392
1393DECLARE_RTL_COND(rtl_ocp_tx_cond)
1394{
1395 void __iomem *ioaddr = tp->mmio_addr;
1396
086ca23d 1397 return RTL_R8(IBISR0) & 0x20;
935e2218 1398}
2a9b4d96 1399
003609da
CHL		 1400static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1401{
1402 void __iomem *ioaddr = tp->mmio_addr;
1403
1404 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
086ca23d 1405 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
003609da
CHL		 1406 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1407 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1408}
1409
935e2218
CHL		 1410static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1411{
1412 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
2a9b4d96
CHL		 1413 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1414}
1415
935e2218 1416static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1417{
935e2218
CHL		 1418 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1419 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1420 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1421}
1422
1423static void rtl8168_driver_start(struct rtl8169_private *tp)
1424{
1425 switch (tp->mac_version) {
1426 case RTL_GIGA_MAC_VER_27:
1427 case RTL_GIGA_MAC_VER_28:
1428 case RTL_GIGA_MAC_VER_31:
1429 rtl8168dp_driver_start(tp);
1430 break;
1431 case RTL_GIGA_MAC_VER_49:
1432 case RTL_GIGA_MAC_VER_50:
1433 case RTL_GIGA_MAC_VER_51:
1434 rtl8168ep_driver_start(tp);
1435 break;
1436 default:
1437 BUG();
1438 break;
1439 }
1440}
2a9b4d96 1441
935e2218
CHL		 1442static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1443{
1444 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
2a9b4d96
CHL		 1445 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1446}
1447
935e2218
CHL		 1448static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1449{
003609da 1450 rtl8168ep_stop_cmac(tp);
935e2218
CHL		 1451 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1452 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1453 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1454}
1455
1456static void rtl8168_driver_stop(struct rtl8169_private *tp)
1457{
1458 switch (tp->mac_version) {
1459 case RTL_GIGA_MAC_VER_27:
1460 case RTL_GIGA_MAC_VER_28:
1461 case RTL_GIGA_MAC_VER_31:
1462 rtl8168dp_driver_stop(tp);
1463 break;
1464 case RTL_GIGA_MAC_VER_49:
1465 case RTL_GIGA_MAC_VER_50:
1466 case RTL_GIGA_MAC_VER_51:
1467 rtl8168ep_driver_stop(tp);
1468 break;
1469 default:
1470 BUG();
1471 break;
1472 }
1473}
1474
9dbe7896 1475static bool r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1476{
1477 u16 reg = rtl8168_get_ocp_reg(tp);
1478
9dbe7896 1479 return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
2a9b4d96
CHL		 1480}
1481
9dbe7896 1482static bool r8168ep_check_dash(struct rtl8169_private *tp)
935e2218 1483{
9dbe7896 1484 return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
935e2218
CHL		 1485}
1486
9dbe7896 1487static bool r8168_check_dash(struct rtl8169_private *tp)
935e2218
CHL		 1488{
1489 switch (tp->mac_version) {
1490 case RTL_GIGA_MAC_VER_27:
1491 case RTL_GIGA_MAC_VER_28:
1492 case RTL_GIGA_MAC_VER_31:
1493 return r8168dp_check_dash(tp);
1494 case RTL_GIGA_MAC_VER_49:
1495 case RTL_GIGA_MAC_VER_50:
1496 case RTL_GIGA_MAC_VER_51:
1497 return r8168ep_check_dash(tp);
1498 default:
9dbe7896 1499 return false;
935e2218
CHL		 1500 }
1501}
1502
c28aa385 1503struct exgmac_reg {
1504 u16 addr;
1505 u16 mask;
1506 u32 val;
1507};
1508
fdf6fc06 1509static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1510 const struct exgmac_reg *r, int len)
1511{
1512 while (len-- > 0) {
fdf6fc06 1513 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1514 r++;
1515 }
1516}
1517
ffc46952
FR		 1518DECLARE_RTL_COND(rtl_efusear_cond)
1519{
1520 void __iomem *ioaddr = tp->mmio_addr;
1521
1522 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1523}
1524
fdf6fc06 1525static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1526{
fdf6fc06 1527 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1528
1529 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1530
ffc46952
FR		 1531 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1532 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1533}
1534
9085cdfa
FR		 1535static u16 rtl_get_events(struct rtl8169_private *tp)
1536{
1537 void __iomem *ioaddr = tp->mmio_addr;
1538
1539 return RTL_R16(IntrStatus);
1540}
1541
1542static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1543{
1544 void __iomem *ioaddr = tp->mmio_addr;
1545
1546 RTL_W16(IntrStatus, bits);
1547 mmiowb();
1548}
1549
1550static void rtl_irq_disable(struct rtl8169_private *tp)
1551{
1552 void __iomem *ioaddr = tp->mmio_addr;
1553
1554 RTL_W16(IntrMask, 0);
1555 mmiowb();
1556}
1557
3e990ff5
FR		 1558static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1559{
1560 void __iomem *ioaddr = tp->mmio_addr;
1561
1562 RTL_W16(IntrMask, bits);
1563}
1564
da78dbff
FR		 1565#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1566#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1567#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1568
1569static void rtl_irq_enable_all(struct rtl8169_private *tp)
1570{
1571 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1572}
1573
811fd301 1574static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1575{
811fd301 1576 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1577
9085cdfa 1578 rtl_irq_disable(tp);
da78dbff 1579 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1580 RTL_R8(ChipCmd);
1da177e4
LT		 1581}
1582
4da19633 1583static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1584{
4da19633 1585 void __iomem *ioaddr = tp->mmio_addr;
1586
1da177e4
LT		 1587 return RTL_R32(TBICSR) & TBIReset;
1588}
1589
4da19633 1590static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1591{
4da19633 1592 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1593}
1594
1595static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1596{
1597 return RTL_R32(TBICSR) & TBILinkOk;
1598}
1599
1600static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1601{
1602 return RTL_R8(PHYstatus) & LinkStatus;
1603}
1604
4da19633 1605static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1606{
4da19633 1607 void __iomem *ioaddr = tp->mmio_addr;
1608
1da177e4
LT		 1609 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1610}
1611
4da19633 1612static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1613{
1614 unsigned int val;
1615
4da19633 1616 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1617 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1618}
1619
70090424
HW		 1620static void rtl_link_chg_patch(struct rtl8169_private *tp)
1621{
1622 void __iomem *ioaddr = tp->mmio_addr;
1623 struct net_device *dev = tp->dev;
1624
1625 if (!netif_running(dev))
1626 return;
1627
b3d7b2f2
HW		 1628 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1629 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1630 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1631 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1632 ERIAR_EXGMAC);
1633 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1634 ERIAR_EXGMAC);
70090424 1635 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1636 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1637 ERIAR_EXGMAC);
1638 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1639 ERIAR_EXGMAC);
70090424 1640 } else {
fdf6fc06
FR		 1641 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1642 ERIAR_EXGMAC);
1643 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1644 ERIAR_EXGMAC);
70090424
HW		 1645 }
1646 /* Reset packet filter */
706123d0 1647 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1648 ERIAR_EXGMAC);
706123d0 1649 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1650 ERIAR_EXGMAC);
c2218925
HW		 1651 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1652 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1653 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1654 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1655 ERIAR_EXGMAC);
1656 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1657 ERIAR_EXGMAC);
c2218925 1658 } else {
fdf6fc06
FR		 1659 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1660 ERIAR_EXGMAC);
1661 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1662 ERIAR_EXGMAC);
c2218925 1663 }
7e18dca1
HW		 1664 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1665 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1666 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1667 ERIAR_EXGMAC);
1668 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1669 ERIAR_EXGMAC);
7e18dca1 1670 } else {
fdf6fc06
FR		 1671 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1672 ERIAR_EXGMAC);
7e18dca1 1673 }
70090424
HW		 1674 }
1675}
1676
ef4d5fcc
HK		 1677static void rtl8169_check_link_status(struct net_device *dev,
1678 struct rtl8169_private *tp,
1679 void __iomem *ioaddr)
1da177e4 1680{
1da177e4 1681 if (tp->link_ok(ioaddr)) {
70090424 1682 rtl_link_chg_patch(tp);
e1759441 1683 /* This is to cancel a scheduled suspend if there's one. */
ef4d5fcc 1684 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1685 netif_carrier_on(dev);
1519e57f
FR		 1686 if (net_ratelimit())
1687 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1688 } else {
1da177e4 1689 netif_carrier_off(dev);
bf82c189 1690 netif_info(tp, ifdown, dev, "link down\n");
a92a0849 1691 pm_runtime_idle(&tp->pci_dev->dev);
b57b7e5a 1692 }
1da177e4
LT		 1693}
1694
e1759441
RW		 1695#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1696
1697static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1698{
61a4dcc2
FR		 1699 void __iomem *ioaddr = tp->mmio_addr;
1700 u8 options;
e1759441 1701 u32 wolopts = 0;
61a4dcc2
FR		 1702
1703 options = RTL_R8(Config1);
1704 if (!(options & PMEnable))
e1759441 1705 return 0;
61a4dcc2
FR		 1706
1707 options = RTL_R8(Config3);
1708 if (options & LinkUp)
e1759441 1709 wolopts |= WAKE_PHY;
6e1d0b89 1710 switch (tp->mac_version) {
ac85bcdb
CHL		 1711 case RTL_GIGA_MAC_VER_34:
1712 case RTL_GIGA_MAC_VER_35:
1713 case RTL_GIGA_MAC_VER_36:
1714 case RTL_GIGA_MAC_VER_37:
1715 case RTL_GIGA_MAC_VER_38:
1716 case RTL_GIGA_MAC_VER_40:
1717 case RTL_GIGA_MAC_VER_41:
1718 case RTL_GIGA_MAC_VER_42:
1719 case RTL_GIGA_MAC_VER_43:
1720 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1721 case RTL_GIGA_MAC_VER_45:
1722 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1723 case RTL_GIGA_MAC_VER_47:
1724 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 1725 case RTL_GIGA_MAC_VER_49:
1726 case RTL_GIGA_MAC_VER_50:
1727 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1728 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1729 wolopts |= WAKE_MAGIC;
1730 break;
1731 default:
1732 if (options & MagicPacket)
1733 wolopts |= WAKE_MAGIC;
1734 break;
1735 }
61a4dcc2
FR		 1736
1737 options = RTL_R8(Config5);
1738 if (options & UWF)
e1759441 1739 wolopts |= WAKE_UCAST;
61a4dcc2 1740 if (options & BWF)
e1759441 1741 wolopts |= WAKE_BCAST;
61a4dcc2 1742 if (options & MWF)
e1759441 1743 wolopts |= WAKE_MCAST;
61a4dcc2 1744
e1759441 1745 return wolopts;
61a4dcc2
FR		 1746}
1747
e1759441 1748static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1749{
1750 struct rtl8169_private *tp = netdev_priv(dev);
5fa80a32
CHL		 1751 struct device *d = &tp->pci_dev->dev;
1752
1753 pm_runtime_get_noresume(d);
e1759441 1754
da78dbff 1755 rtl_lock_work(tp);
e1759441
RW		 1756
1757 wol->supported = WAKE_ANY;
5fa80a32
CHL		 1758 if (pm_runtime_active(d))
1759 wol->wolopts = __rtl8169_get_wol(tp);
1760 else
1761 wol->wolopts = tp->saved_wolopts;
e1759441 1762
da78dbff 1763 rtl_unlock_work(tp);
5fa80a32
CHL		 1764
1765 pm_runtime_put_noidle(d);
e1759441
RW		 1766}
1767
1768static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1769{
61a4dcc2 1770 void __iomem *ioaddr = tp->mmio_addr;
6e1d0b89 1771 unsigned int i, tmp;
350f7596 1772 static const struct {
61a4dcc2
FR		 1773 u32 opt;
1774 u16 reg;
1775 u8 mask;
1776 } cfg[] = {
61a4dcc2 1777 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1778 { WAKE_UCAST, Config5, UWF },
1779 { WAKE_BCAST, Config5, BWF },
1780 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1781 { WAKE_ANY, Config5, LanWake },
1782 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1783 };
851e6022 1784 u8 options;
61a4dcc2 1785
61a4dcc2
FR		 1786 RTL_W8(Cfg9346, Cfg9346_Unlock);
1787
6e1d0b89 1788 switch (tp->mac_version) {
ac85bcdb
CHL		 1789 case RTL_GIGA_MAC_VER_34:
1790 case RTL_GIGA_MAC_VER_35:
1791 case RTL_GIGA_MAC_VER_36:
1792 case RTL_GIGA_MAC_VER_37:
1793 case RTL_GIGA_MAC_VER_38:
1794 case RTL_GIGA_MAC_VER_40:
1795 case RTL_GIGA_MAC_VER_41:
1796 case RTL_GIGA_MAC_VER_42:
1797 case RTL_GIGA_MAC_VER_43:
1798 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1799 case RTL_GIGA_MAC_VER_45:
1800 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1801 case RTL_GIGA_MAC_VER_47:
1802 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 1803 case RTL_GIGA_MAC_VER_49:
1804 case RTL_GIGA_MAC_VER_50:
1805 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1806 tmp = ARRAY_SIZE(cfg) - 1;
1807 if (wolopts & WAKE_MAGIC)
706123d0 1808 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1809 0x0dc,
1810 ERIAR_MASK_0100,
1811 MagicPacket_v2,
1812 0x0000,
1813 ERIAR_EXGMAC);
1814 else
706123d0 1815 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1816 0x0dc,
1817 ERIAR_MASK_0100,
1818 0x0000,
1819 MagicPacket_v2,
1820 ERIAR_EXGMAC);
1821 break;
1822 default:
1823 tmp = ARRAY_SIZE(cfg);
1824 break;
1825 }
1826
1827 for (i = 0; i < tmp; i++) {
851e6022 1828 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1829 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1830 options |= cfg[i].mask;
1831 RTL_W8(cfg[i].reg, options);
1832 }
1833
851e6022
FR		 1834 switch (tp->mac_version) {
1835 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1836 options = RTL_R8(Config1) & ~PMEnable;
1837 if (wolopts)
1838 options |= PMEnable;
1839 RTL_W8(Config1, options);
1840 break;
1841 default:
d387b427
FR		 1842 options = RTL_R8(Config2) & ~PME_SIGNAL;
1843 if (wolopts)
1844 options |= PME_SIGNAL;
1845 RTL_W8(Config2, options);
851e6022
FR		 1846 break;
1847 }
1848
61a4dcc2 1849 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1850}
1851
1852static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1853{
1854 struct rtl8169_private *tp = netdev_priv(dev);
5fa80a32
CHL		 1855 struct device *d = &tp->pci_dev->dev;
1856
1857 pm_runtime_get_noresume(d);
e1759441 1858
da78dbff 1859 rtl_lock_work(tp);
61a4dcc2 1860
5fa80a32
CHL		 1861 if (pm_runtime_active(d))
1862 __rtl8169_set_wol(tp, wol->wolopts);
1863 else
1864 tp->saved_wolopts = wol->wolopts;
da78dbff
FR		 1865
1866 rtl_unlock_work(tp);
61a4dcc2 1867
ea80907f 1868 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1869
5fa80a32
CHL		 1870 pm_runtime_put_noidle(d);
1871
61a4dcc2
FR		 1872 return 0;
1873}
1874
31bd204f
FR		 1875static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1876{
85bffe6c 1877 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1878}
1879
1da177e4
LT		 1880static void rtl8169_get_drvinfo(struct net_device *dev,
1881 struct ethtool_drvinfo *info)
1882{
1883 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1884 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1885
68aad78c
RJ		 1886 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1887 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1888 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1889 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1890 if (!IS_ERR_OR_NULL(rtl_fw))
1891 strlcpy(info->fw_version, rtl_fw->version,
1892 sizeof(info->fw_version));
1da177e4
LT		 1893}
1894
1895static int rtl8169_get_regs_len(struct net_device *dev)
1896{
1897 return R8169_REGS_SIZE;
1898}
1899
1900static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1901 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1902{
1903 struct rtl8169_private *tp = netdev_priv(dev);
1904 void __iomem *ioaddr = tp->mmio_addr;
1905 int ret = 0;
1906 u32 reg;
1907
1908 reg = RTL_R32(TBICSR);
1909 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1910 (duplex == DUPLEX_FULL)) {
1911 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1912 } else if (autoneg == AUTONEG_ENABLE)
1913 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1914 else {
bf82c189
JP		 1915 netif_warn(tp, link, dev,
1916 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1917 ret = -EOPNOTSUPP;
1918 }
1919
1920 return ret;
1921}
1922
1923static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1924 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1925{
1926 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1927 int giga_ctrl, bmcr;
54405cde 1928 int rc = -EINVAL;
1da177e4 1929
716b50a3 1930 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1931
1932 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1933 int auto_nego;
1934
4da19633 1935 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1936 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1937 ADVERTISE_100HALF | ADVERTISE_100FULL);
1938
1939 if (adv & ADVERTISED_10baseT_Half)
1940 auto_nego |= ADVERTISE_10HALF;
1941 if (adv & ADVERTISED_10baseT_Full)
1942 auto_nego |= ADVERTISE_10FULL;
1943 if (adv & ADVERTISED_100baseT_Half)
1944 auto_nego |= ADVERTISE_100HALF;
1945 if (adv & ADVERTISED_100baseT_Full)
1946 auto_nego |= ADVERTISE_100FULL;
1947
3577aa1b 1948 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1949
4da19633 1950 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1951 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1952
3577aa1b 1953 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1954 if (tp->mii.supports_gmii) {
54405cde
ON		 1955 if (adv & ADVERTISED_1000baseT_Half)
1956 giga_ctrl |= ADVERTISE_1000HALF;
1957 if (adv & ADVERTISED_1000baseT_Full)
1958 giga_ctrl |= ADVERTISE_1000FULL;
1959 } else if (adv & (ADVERTISED_1000baseT_Half |
1960 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1961 netif_info(tp, link, dev,
1962 "PHY does not support 1000Mbps\n");
54405cde 1963 goto out;
bcf0bf90 1964 }
1da177e4 1965
3577aa1b 1966 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1967
4da19633 1968 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1969 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1970 } else {
3577aa1b 1971 if (speed == SPEED_10)
1972 bmcr = 0;
1973 else if (speed == SPEED_100)
1974 bmcr = BMCR_SPEED100;
1975 else
54405cde 1976 goto out;
3577aa1b 1977
1978 if (duplex == DUPLEX_FULL)
1979 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1980 }
1981
4da19633 1982 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1983
cecb5fd7
FR		 1984 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1985 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1986 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1987 rtl_writephy(tp, 0x17, 0x2138);
1988 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1989 } else {
4da19633 1990 rtl_writephy(tp, 0x17, 0x2108);
1991 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1992 }
1993 }
1994
54405cde
ON		 1995 rc = 0;
1996out:
1997 return rc;
1da177e4
LT		 1998}
1999
2000static int rtl8169_set_speed(struct net_device *dev,
54405cde 2001 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 2002{
2003 struct rtl8169_private *tp = netdev_priv(dev);
2004 int ret;
2005
54405cde 2006 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 2007 if (ret < 0)
2008 goto out;
1da177e4 2009
4876cc1e 2010 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
c4556975
CHL		 2011 (advertising & ADVERTISED_1000baseT_Full) &&
2012 !pci_is_pcie(tp->pci_dev)) {
1da177e4 2013 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 2014 }
2015out:
1da177e4
LT		 2016 return ret;
2017}
2018
c8f44aff
MM		 2019static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2020 netdev_features_t features)
1da177e4 2021{
d58d46b5
FR		 2022 struct rtl8169_private *tp = netdev_priv(dev);
2023
2b7b4318 2024 if (dev->mtu > TD_MSS_MAX)
350fb32a 2025 features &= ~NETIF_F_ALL_TSO;
1da177e4 2026
d58d46b5
FR		 2027 if (dev->mtu > JUMBO_1K &&
2028 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2029 features &= ~NETIF_F_IP_CSUM;
2030
350fb32a 2031 return features;
1da177e4
LT		 2032}
2033
da78dbff
FR		 2034static void __rtl8169_set_features(struct net_device *dev,
2035 netdev_features_t features)
1da177e4
LT		 2036{
2037 struct rtl8169_private *tp = netdev_priv(dev);
da78dbff 2038 void __iomem *ioaddr = tp->mmio_addr;
929a031d 2039 u32 rx_config;
1da177e4 2040
929a031d 2041 rx_config = RTL_R32(RxConfig);
2042 if (features & NETIF_F_RXALL)
2043 rx_config |= (AcceptErr | AcceptRunt);
2044 else
2045 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 2046
929a031d 2047 RTL_W32(RxConfig, rx_config);
350fb32a 2048
929a031d 2049 if (features & NETIF_F_RXCSUM)
2050 tp->cp_cmd |= RxChkSum;
2051 else
2052 tp->cp_cmd &= ~RxChkSum;
6bbe021d 2053
929a031d 2054 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2055 tp->cp_cmd |= RxVlan;
2056 else
2057 tp->cp_cmd &= ~RxVlan;
2058
2059 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2060
2061 RTL_W16(CPlusCmd, tp->cp_cmd);
2062 RTL_R16(CPlusCmd);
da78dbff 2063}
1da177e4 2064
da78dbff
FR		 2065static int rtl8169_set_features(struct net_device *dev,
2066 netdev_features_t features)
2067{
2068 struct rtl8169_private *tp = netdev_priv(dev);
2069
929a031d 2070 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2071
da78dbff 2072 rtl_lock_work(tp);
85911d71 2073 if (features ^ dev->features)
929a031d 2074 __rtl8169_set_features(dev, features);
da78dbff 2075 rtl_unlock_work(tp);
1da177e4
LT		 2076
2077 return 0;
2078}
2079
da78dbff 2080
810f4893 2081static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 2082{
df8a39de
JP		 2083 return (skb_vlan_tag_present(skb)) ?
2084 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 2085}
2086
7a8fc77b 2087static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 2088{
2089 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 2090
7a8fc77b 2091 if (opts2 & RxVlanTag)
86a9bad3 2092 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 2093}
2094
6fa1ba61
PR		 2095static int rtl8169_get_link_ksettings_tbi(struct net_device *dev,
2096 struct ethtool_link_ksettings *cmd)
1da177e4
LT		 2097{
2098 struct rtl8169_private *tp = netdev_priv(dev);
2099 void __iomem *ioaddr = tp->mmio_addr;
2100 u32 status;
6fa1ba61 2101 u32 supported, advertising;
1da177e4 2102
6fa1ba61 2103 supported =
1da177e4 2104 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
6fa1ba61 2105 cmd->base.port = PORT_FIBRE;
1da177e4
LT		 2106
2107 status = RTL_R32(TBICSR);
6fa1ba61
PR		 2108 advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2109 cmd->base.autoneg = !!(status & TBINwEnable);
1da177e4 2110
6fa1ba61
PR		 2111 cmd->base.speed = SPEED_1000;
2112 cmd->base.duplex = DUPLEX_FULL; /* Always set */
2113
2114 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2115 supported);
2116 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2117 advertising);
ccdffb9a
FR		 2118
2119 return 0;
1da177e4
LT		 2120}
2121
6fa1ba61
PR		 2122static int rtl8169_get_link_ksettings_xmii(struct net_device *dev,
2123 struct ethtool_link_ksettings *cmd)
1da177e4
LT		 2124{
2125 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 2126
82c01a84 2127 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
2128
2129 return 0;
1da177e4
LT		 2130}
2131
6fa1ba61
PR		 2132static int rtl8169_get_link_ksettings(struct net_device *dev,
2133 struct ethtool_link_ksettings *cmd)
1da177e4
LT		 2134{
2135 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 2136 int rc;
1da177e4 2137
da78dbff 2138 rtl_lock_work(tp);
6fa1ba61 2139 rc = tp->get_link_ksettings(dev, cmd);
da78dbff 2140 rtl_unlock_work(tp);
1da177e4 2141
ccdffb9a 2142 return rc;
1da177e4
LT		 2143}
2144
9e77d7a5
TJ		 2145static int rtl8169_set_link_ksettings(struct net_device *dev,
2146 const struct ethtool_link_ksettings *cmd)
2147{
2148 struct rtl8169_private *tp = netdev_priv(dev);
2149 int rc;
2150 u32 advertising;
2151
2152 if (!ethtool_convert_link_mode_to_legacy_u32(&advertising,
2153 cmd->link_modes.advertising))
2154 return -EINVAL;
2155
2156 del_timer_sync(&tp->timer);
2157
2158 rtl_lock_work(tp);
2159 rc = rtl8169_set_speed(dev, cmd->base.autoneg, cmd->base.speed,
2160 cmd->base.duplex, advertising);
2161 rtl_unlock_work(tp);
2162
2163 return rc;
2164}
2165
1da177e4
LT		 2166static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2167 void *p)
2168{
5b0384f4 2169 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 2170 u32 __iomem *data = tp->mmio_addr;
2171 u32 *dw = p;
2172 int i;
1da177e4 2173
da78dbff 2174 rtl_lock_work(tp);
15edae91
PW		 2175 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2176 memcpy_fromio(dw++, data++, 4);
da78dbff 2177 rtl_unlock_work(tp);
1da177e4
LT		 2178}
2179
b57b7e5a
SH		 2180static u32 rtl8169_get_msglevel(struct net_device *dev)
2181{
2182 struct rtl8169_private *tp = netdev_priv(dev);
2183
2184 return tp->msg_enable;
2185}
2186
2187static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2188{
2189 struct rtl8169_private *tp = netdev_priv(dev);
2190
2191 tp->msg_enable = value;
2192}
2193
d4a3a0fc
SH		 2194static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2195 "tx_packets",
2196 "rx_packets",
2197 "tx_errors",
2198 "rx_errors",
2199 "rx_missed",
2200 "align_errors",
2201 "tx_single_collisions",
2202 "tx_multi_collisions",
2203 "unicast",
2204 "broadcast",
2205 "multicast",
2206 "tx_aborted",
2207 "tx_underrun",
2208};
2209
b9f2c044 2210static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 2211{
b9f2c044
JG		 2212 switch (sset) {
2213 case ETH_SS_STATS:
2214 return ARRAY_SIZE(rtl8169_gstrings);
2215 default:
2216 return -EOPNOTSUPP;
2217 }
d4a3a0fc
SH		 2218}
2219
42020320 2220DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 2221{
6e85d5ad 2222 void __iomem *ioaddr = tp->mmio_addr;
6e85d5ad 2223
42020320 2224 return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 2225}
2226
42020320 2227static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
6e85d5ad
CV		 2228{
2229 struct rtl8169_private *tp = netdev_priv(dev);
2230 void __iomem *ioaddr = tp->mmio_addr;
42020320
CV		 2231 dma_addr_t paddr = tp->counters_phys_addr;
2232 u32 cmd;
6e85d5ad 2233
42020320 2234 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
a78e9366 2235 RTL_R32(CounterAddrHigh);
42020320
CV		 2236 cmd = (u64)paddr & DMA_BIT_MASK(32);
2237 RTL_W32(CounterAddrLow, cmd);
2238 RTL_W32(CounterAddrLow, cmd | counter_cmd);
6e85d5ad 2239
a78e9366 2240 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 2241}
2242
2243static bool rtl8169_reset_counters(struct net_device *dev)
2244{
2245 struct rtl8169_private *tp = netdev_priv(dev);
6e85d5ad
CV		 2246
2247 /*
2248 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2249 * tally counters.
2250 */
2251 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2252 return true;
2253
42020320 2254 return rtl8169_do_counters(dev, CounterReset);
ffc46952
FR		 2255}
2256
6e85d5ad 2257static bool rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 2258{
2259 struct rtl8169_private *tp = netdev_priv(dev);
2260 void __iomem *ioaddr = tp->mmio_addr;
d4a3a0fc 2261
355423d0
IV		 2262 /*
2263 * Some chips are unable to dump tally counters when the receiver
2264 * is disabled.
2265 */
2266 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
6e85d5ad 2267 return true;
d4a3a0fc 2268
42020320 2269 return rtl8169_do_counters(dev, CounterDump);
6e85d5ad
CV		 2270}
2271
2272static bool rtl8169_init_counter_offsets(struct net_device *dev)
2273{
2274 struct rtl8169_private *tp = netdev_priv(dev);
42020320 2275 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 2276 bool ret = false;
2277
2278 /*
2279 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2280 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2281 * reset by a power cycle, while the counter values collected by the
2282 * driver are reset at every driver unload/load cycle.
2283 *
2284 * To make sure the HW values returned by @get_stats64 match the SW
2285 * values, we collect the initial values at first open(*) and use them
2286 * as offsets to normalize the values returned by @get_stats64.
2287 *
2288 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2289 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2290 * set at open time by rtl_hw_start.
2291 */
2292
2293 if (tp->tc_offset.inited)
2294 return true;
2295
2296 /* If both, reset and update fail, propagate to caller. */
2297 if (rtl8169_reset_counters(dev))
2298 ret = true;
2299
2300 if (rtl8169_update_counters(dev))
2301 ret = true;
2302
42020320
CV		 2303 tp->tc_offset.tx_errors = counters->tx_errors;
2304 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2305 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 2306 tp->tc_offset.inited = true;
2307
2308 return ret;
d4a3a0fc
SH		 2309}
2310
355423d0
IV		 2311static void rtl8169_get_ethtool_stats(struct net_device *dev,
2312 struct ethtool_stats *stats, u64 *data)
2313{
2314 struct rtl8169_private *tp = netdev_priv(dev);
e0636236 2315 struct device *d = &tp->pci_dev->dev;
42020320 2316 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 2317
2318 ASSERT_RTNL();
2319
e0636236
CHL		 2320 pm_runtime_get_noresume(d);
2321
2322 if (pm_runtime_active(d))
2323 rtl8169_update_counters(dev);
2324
2325 pm_runtime_put_noidle(d);
355423d0 2326
42020320
CV		 2327 data[0] = le64_to_cpu(counters->tx_packets);
2328 data[1] = le64_to_cpu(counters->rx_packets);
2329 data[2] = le64_to_cpu(counters->tx_errors);
2330 data[3] = le32_to_cpu(counters->rx_errors);
2331 data[4] = le16_to_cpu(counters->rx_missed);
2332 data[5] = le16_to_cpu(counters->align_errors);
2333 data[6] = le32_to_cpu(counters->tx_one_collision);
2334 data[7] = le32_to_cpu(counters->tx_multi_collision);
2335 data[8] = le64_to_cpu(counters->rx_unicast);
2336 data[9] = le64_to_cpu(counters->rx_broadcast);
2337 data[10] = le32_to_cpu(counters->rx_multicast);
2338 data[11] = le16_to_cpu(counters->tx_aborted);
2339 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 2340}
2341
d4a3a0fc
SH		 2342static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2343{
2344 switch(stringset) {
2345 case ETH_SS_STATS:
2346 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2347 break;
2348 }
2349}
2350
f0903ea3
FF		 2351static int rtl8169_nway_reset(struct net_device *dev)
2352{
2353 struct rtl8169_private *tp = netdev_priv(dev);
2354
2355 return mii_nway_restart(&tp->mii);
2356}
2357
50970831
FR		 2358/*
2359 * Interrupt coalescing
2360 *
2361 * > 1 - the availability of the IntrMitigate (0xe2) register through the
2362 * > 8169, 8168 and 810x line of chipsets
2363 *
2364 * 8169, 8168, and 8136(810x) serial chipsets support it.
2365 *
2366 * > 2 - the Tx timer unit at gigabit speed
2367 *
2368 * The unit of the timer depends on both the speed and the setting of CPlusCmd
2369 * (0xe0) bit 1 and bit 0.
2370 *
2371 * For 8169
2372 * bit[1:0] \ speed 1000M 100M 10M
2373 * 0 0 320ns 2.56us 40.96us
2374 * 0 1 2.56us 20.48us 327.7us
2375 * 1 0 5.12us 40.96us 655.4us
2376 * 1 1 10.24us 81.92us 1.31ms
2377 *
2378 * For the other
2379 * bit[1:0] \ speed 1000M 100M 10M
2380 * 0 0 5us 2.56us 40.96us
2381 * 0 1 40us 20.48us 327.7us
2382 * 1 0 80us 40.96us 655.4us
2383 * 1 1 160us 81.92us 1.31ms
2384 */
2385
2386/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
2387struct rtl_coalesce_scale {
2388 /* Rx / Tx */
2389 u32 nsecs[2];
2390};
2391
2392/* rx/tx scale factors for all CPlusCmd[0:1] cases */
2393struct rtl_coalesce_info {
2394 u32 speed;
2395 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
2396};
2397
2398/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
2399#define rxtx_x1822(r, t) { \
2400 {{(r), (t)}}, \
2401 {{(r)*8, (t)*8}}, \
2402 {{(r)*8*2, (t)*8*2}}, \
2403 {{(r)*8*2*2, (t)*8*2*2}}, \
2404}
2405static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
2406 /* speed delays: rx00 tx00 */
2407 { SPEED_10, rxtx_x1822(40960, 40960) },
2408 { SPEED_100, rxtx_x1822( 2560, 2560) },
2409 { SPEED_1000, rxtx_x1822( 320, 320) },
2410 { 0 },
2411};
2412
2413static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
2414 /* speed delays: rx00 tx00 */
2415 { SPEED_10, rxtx_x1822(40960, 40960) },
2416 { SPEED_100, rxtx_x1822( 2560, 2560) },
2417 { SPEED_1000, rxtx_x1822( 5000, 5000) },
2418 { 0 },
2419};
2420#undef rxtx_x1822
2421
2422/* get rx/tx scale vector corresponding to current speed */
2423static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
2424{
2425 struct rtl8169_private *tp = netdev_priv(dev);
2426 struct ethtool_link_ksettings ecmd;
2427 const struct rtl_coalesce_info *ci;
2428 int rc;
2429
2430 rc = rtl8169_get_link_ksettings(dev, &ecmd);
2431 if (rc < 0)
2432 return ERR_PTR(rc);
2433
2434 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
2435 if (ecmd.base.speed == ci->speed) {
2436 return ci;
2437 }
2438 }
2439
2440 return ERR_PTR(-ELNRNG);
2441}
2442
2443static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2444{
2445 struct rtl8169_private *tp = netdev_priv(dev);
2446 void __iomem *ioaddr = tp->mmio_addr;
2447 const struct rtl_coalesce_info *ci;
2448 const struct rtl_coalesce_scale *scale;
2449 struct {
2450 u32 *max_frames;
2451 u32 *usecs;
2452 } coal_settings [] = {
2453 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
2454 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
2455 }, *p = coal_settings;
2456 int i;
2457 u16 w;
2458
2459 memset(ec, 0, sizeof(*ec));
2460
2461 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2462 ci = rtl_coalesce_info(dev);
2463 if (IS_ERR(ci))
2464 return PTR_ERR(ci);
2465
2466 scale = &ci->scalev[RTL_R16(CPlusCmd) & 3];
2467
2468 /* read IntrMitigate and adjust according to scale */
2469 for (w = RTL_R16(IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
2470 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2471 w >>= RTL_COALESCE_SHIFT;
2472 *p->usecs = w & RTL_COALESCE_MASK;
2473 }
2474
2475 for (i = 0; i < 2; i++) {
2476 p = coal_settings + i;
2477 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2478
2479 /*
2480 * ethtool_coalesce says it is illegal to set both usecs and
2481 * max_frames to 0.
2482 */
2483 if (!*p->usecs && !*p->max_frames)
2484 *p->max_frames = 1;
2485 }
2486
2487 return 0;
2488}
2489
2490/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2491static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2492 struct net_device *dev, u32 nsec, u16 *cp01)
2493{
2494 const struct rtl_coalesce_info *ci;
2495 u16 i;
2496
2497 ci = rtl_coalesce_info(dev);
2498 if (IS_ERR(ci))
2499 return ERR_CAST(ci);
2500
2501 for (i = 0; i < 4; i++) {
2502 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2503 ci->scalev[i].nsecs[1]);
2504 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2505 *cp01 = i;
2506 return &ci->scalev[i];
2507 }
2508 }
2509
2510 return ERR_PTR(-EINVAL);
2511}
2512
2513static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2514{
2515 struct rtl8169_private *tp = netdev_priv(dev);
2516 void __iomem *ioaddr = tp->mmio_addr;
2517 const struct rtl_coalesce_scale *scale;
2518 struct {
2519 u32 frames;
2520 u32 usecs;
2521 } coal_settings [] = {
2522 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2523 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2524 }, *p = coal_settings;
2525 u16 w = 0, cp01;
2526 int i;
2527
2528 scale = rtl_coalesce_choose_scale(dev,
2529 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2530 if (IS_ERR(scale))
2531 return PTR_ERR(scale);
2532
2533 for (i = 0; i < 2; i++, p++) {
2534 u32 units;
2535
2536 /*
2537 * accept max_frames=1 we returned in rtl_get_coalesce.
2538 * accept it not only when usecs=0 because of e.g. the following scenario:
2539 *
2540 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2541 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2542 * - then user does `ethtool -C eth0 rx-usecs 100`
2543 *
2544 * since ethtool sends to kernel whole ethtool_coalesce
2545 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2546 * we'll reject it below in `frames % 4 != 0`.
2547 */
2548 if (p->frames == 1) {
2549 p->frames = 0;
2550 }
2551
2552 units = p->usecs * 1000 / scale->nsecs[i];
2553 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2554 return -EINVAL;
2555
2556 w <<= RTL_COALESCE_SHIFT;
2557 w |= units;
2558 w <<= RTL_COALESCE_SHIFT;
2559 w |= p->frames >> 2;
2560 }
2561
2562 rtl_lock_work(tp);
2563
2564 RTL_W16(IntrMitigate, swab16(w));
2565
2566 tp->cp_cmd = (tp->cp_cmd & ~3) | cp01;
2567 RTL_W16(CPlusCmd, tp->cp_cmd);
2568 RTL_R16(CPlusCmd);
2569
2570 rtl_unlock_work(tp);
2571
2572 return 0;
2573}
2574
7282d491 2575static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2576 .get_drvinfo = rtl8169_get_drvinfo,
2577 .get_regs_len = rtl8169_get_regs_len,
2578 .get_link = ethtool_op_get_link,
50970831
FR		 2579 .get_coalesce = rtl_get_coalesce,
2580 .set_coalesce = rtl_set_coalesce,
b57b7e5a
SH		 2581 .get_msglevel = rtl8169_get_msglevel,
2582 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2583 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2584 .get_wol = rtl8169_get_wol,
2585 .set_wol = rtl8169_set_wol,
d4a3a0fc 2586 .get_strings = rtl8169_get_strings,
b9f2c044 2587 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2588 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2589 .get_ts_info = ethtool_op_get_ts_info,
f0903ea3 2590 .nway_reset = rtl8169_nway_reset,
6fa1ba61 2591 .get_link_ksettings = rtl8169_get_link_ksettings,
9e77d7a5 2592 .set_link_ksettings = rtl8169_set_link_ksettings,
1da177e4
LT		 2593};
2594
07d3f51f 2595static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2596 struct net_device *dev, u8 default_version)
1da177e4 2597{
5d320a20 2598 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2599 /*
2600 * The driver currently handles the 8168Bf and the 8168Be identically
2601 * but they can be identified more specifically through the test below
2602 * if needed:
2603 *
2604 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2605 *
2606 * Same thing for the 8101Eb and the 8101Ec:
2607 *
2608 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2609 */
3744100e 2610 static const struct rtl_mac_info {
1da177e4 2611 u32 mask;
e3cf0cc0 2612 u32 val;
1da177e4
LT		 2613 int mac_version;
2614 } mac_info[] = {
935e2218
CHL		 2615 /* 8168EP family. */
2616 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2617 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2618 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2619
6e1d0b89
CHL		 2620 /* 8168H family. */
2621 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2622 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2623
c558386b 2624 /* 8168G family. */
45dd95c4 2625 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2626 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2627 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2628 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2629
c2218925 2630 /* 8168F family. */
b3d7b2f2 2631 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2632 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2633 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2634
01dc7fec 2635 /* 8168E family. */
70090424 2636 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2637 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2638 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2639 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2640
5b538df9 2641 /* 8168D family. */
daf9df6d 2642 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2643 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2644 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2645
e6de30d6 2646 /* 8168DP family. */
2647 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2648 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2649 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2650
ef808d50 2651 /* 8168C family. */
17c99297 2652 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2653 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2654 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2655 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2656 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2657 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2658 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2659 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2660 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2661
2662 /* 8168B family. */
2663 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2664 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2665 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2666 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2667
2668 /* 8101 family. */
5598bfe5
HW		 2669 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2670 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2671 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2672 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2673 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2674 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2675 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2676 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2677 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2678 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2679 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2680 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2681 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2682 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2683 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2684 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2685 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2686 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2687 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2688 /* FIXME: where did these entries come from ? -- FR */
2689 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2690 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2691
2692 /* 8110 family. */
2693 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2694 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2695 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2696 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2697 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2698 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2699
f21b75e9
JD		 2700 /* Catch-all */
2701 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2702 };
2703 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2704 u32 reg;
2705
e3cf0cc0
FR		 2706 reg = RTL_R32(TxConfig);
2707 while ((reg & p->mask) != p->val)
1da177e4
LT		 2708 p++;
2709 tp->mac_version = p->mac_version;
5d320a20
FR		 2710
2711 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2712 netif_notice(tp, probe, dev,
2713 "unknown MAC, using family default\n");
2714 tp->mac_version = default_version;
58152cd4 2715 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2716 tp->mac_version = tp->mii.supports_gmii ?
2717 RTL_GIGA_MAC_VER_42 :
2718 RTL_GIGA_MAC_VER_43;
6e1d0b89
CHL		 2719 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2720 tp->mac_version = tp->mii.supports_gmii ?
2721 RTL_GIGA_MAC_VER_45 :
2722 RTL_GIGA_MAC_VER_47;
2723 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2724 tp->mac_version = tp->mii.supports_gmii ?
2725 RTL_GIGA_MAC_VER_46 :
2726 RTL_GIGA_MAC_VER_48;
5d320a20 2727 }
1da177e4
LT		 2728}
2729
2730static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2731{
bcf0bf90 2732 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2733}
2734
867763c1
FR		 2735struct phy_reg {
2736 u16 reg;
2737 u16 val;
2738};
2739
4da19633 2740static void rtl_writephy_batch(struct rtl8169_private *tp,
2741 const struct phy_reg *regs, int len)
867763c1
FR		 2742{
2743 while (len-- > 0) {
4da19633 2744 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2745 regs++;
2746 }
2747}
2748
bca03d5f 2749#define PHY_READ 0x00000000
2750#define PHY_DATA_OR 0x10000000
2751#define PHY_DATA_AND 0x20000000
2752#define PHY_BJMPN 0x30000000
eee3786f 2753#define PHY_MDIO_CHG 0x40000000
bca03d5f 2754#define PHY_CLEAR_READCOUNT 0x70000000
2755#define PHY_WRITE 0x80000000
2756#define PHY_READCOUNT_EQ_SKIP 0x90000000
2757#define PHY_COMP_EQ_SKIPN 0xa0000000
2758#define PHY_COMP_NEQ_SKIPN 0xb0000000
2759#define PHY_WRITE_PREVIOUS 0xc0000000
2760#define PHY_SKIPN 0xd0000000
2761#define PHY_DELAY_MS 0xe0000000
bca03d5f 2762
960aee6c
HW		 2763struct fw_info {
2764 u32 magic;
2765 char version[RTL_VER_SIZE];
2766 __le32 fw_start;
2767 __le32 fw_len;
2768 u8 chksum;
2769} __packed;
2770
1c361efb
FR		 2771#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2772
2773static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2774{
b6ffd97f 2775 const struct firmware *fw = rtl_fw->fw;
960aee6c 2776 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2777 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2778 char *version = rtl_fw->version;
2779 bool rc = false;
2780
2781 if (fw->size < FW_OPCODE_SIZE)
2782 goto out;
960aee6c
HW		 2783
2784 if (!fw_info->magic) {
2785 size_t i, size, start;
2786 u8 checksum = 0;
2787
2788 if (fw->size < sizeof(*fw_info))
2789 goto out;
2790
2791 for (i = 0; i < fw->size; i++)
2792 checksum += fw->data[i];
2793 if (checksum != 0)
2794 goto out;
2795
2796 start = le32_to_cpu(fw_info->fw_start);
2797 if (start > fw->size)
2798 goto out;
2799
2800 size = le32_to_cpu(fw_info->fw_len);
2801 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2802 goto out;
2803
2804 memcpy(version, fw_info->version, RTL_VER_SIZE);
2805
2806 pa->code = (__le32 *)(fw->data + start);
2807 pa->size = size;
2808 } else {
1c361efb
FR		 2809 if (fw->size % FW_OPCODE_SIZE)
2810 goto out;
2811
2812 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2813
2814 pa->code = (__le32 *)fw->data;
2815 pa->size = fw->size / FW_OPCODE_SIZE;
2816 }
2817 version[RTL_VER_SIZE - 1] = 0;
2818
2819 rc = true;
2820out:
2821 return rc;
2822}
2823
fd112f2e
FR		 2824static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2825 struct rtl_fw_phy_action *pa)
1c361efb 2826{
fd112f2e 2827 bool rc = false;
1c361efb 2828 size_t index;
bca03d5f 2829
1c361efb
FR		 2830 for (index = 0; index < pa->size; index++) {
2831 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2832 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2833
42b82dc1 2834 switch(action & 0xf0000000) {
2835 case PHY_READ:
2836 case PHY_DATA_OR:
2837 case PHY_DATA_AND:
eee3786f 2838 case PHY_MDIO_CHG:
42b82dc1 2839 case PHY_CLEAR_READCOUNT:
2840 case PHY_WRITE:
2841 case PHY_WRITE_PREVIOUS:
2842 case PHY_DELAY_MS:
2843 break;
2844
2845 case PHY_BJMPN:
2846 if (regno > index) {
fd112f2e 2847 netif_err(tp, ifup, tp->dev,
cecb5fd7 2848 "Out of range of firmware\n");
fd112f2e 2849 goto out;
42b82dc1 2850 }
2851 break;
2852 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2853 if (index + 2 >= pa->size) {
fd112f2e 2854 netif_err(tp, ifup, tp->dev,
cecb5fd7 2855 "Out of range of firmware\n");
fd112f2e 2856 goto out;
42b82dc1 2857 }
2858 break;
2859 case PHY_COMP_EQ_SKIPN:
2860 case PHY_COMP_NEQ_SKIPN:
2861 case PHY_SKIPN:
1c361efb 2862 if (index + 1 + regno >= pa->size) {
fd112f2e 2863 netif_err(tp, ifup, tp->dev,
cecb5fd7 2864 "Out of range of firmware\n");
fd112f2e 2865 goto out;
42b82dc1 2866 }
bca03d5f 2867 break;
2868
42b82dc1 2869 default:
fd112f2e 2870 netif_err(tp, ifup, tp->dev,
42b82dc1 2871 "Invalid action 0x%08x\n", action);
fd112f2e 2872 goto out;
bca03d5f 2873 }
2874 }
fd112f2e
FR		 2875 rc = true;
2876out:
2877 return rc;
2878}
bca03d5f 2879
fd112f2e
FR		 2880static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2881{
2882 struct net_device *dev = tp->dev;
2883 int rc = -EINVAL;
2884
2885 if (!rtl_fw_format_ok(tp, rtl_fw)) {
5c2d2b14 2886 netif_err(tp, ifup, dev, "invalid firmware\n");
fd112f2e
FR		 2887 goto out;
2888 }
2889
2890 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2891 rc = 0;
2892out:
2893 return rc;
2894}
2895
2896static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2897{
2898 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2899 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2900 u32 predata, count;
2901 size_t index;
2902
2903 predata = count = 0;
eee3786f 2904 org.write = ops->write;
2905 org.read = ops->read;
42b82dc1 2906
1c361efb
FR		 2907 for (index = 0; index < pa->size; ) {
2908 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2909 u32 data = action & 0x0000ffff;
42b82dc1 2910 u32 regno = (action & 0x0fff0000) >> 16;
2911
2912 if (!action)
2913 break;
bca03d5f 2914
2915 switch(action & 0xf0000000) {
42b82dc1 2916 case PHY_READ:
2917 predata = rtl_readphy(tp, regno);
2918 count++;
2919 index++;
2920 break;
2921 case PHY_DATA_OR:
2922 predata |= data;
2923 index++;
2924 break;
2925 case PHY_DATA_AND:
2926 predata &= data;
2927 index++;
2928 break;
2929 case PHY_BJMPN:
2930 index -= regno;
2931 break;
eee3786f 2932 case PHY_MDIO_CHG:
2933 if (data == 0) {
2934 ops->write = org.write;
2935 ops->read = org.read;
2936 } else if (data == 1) {
2937 ops->write = mac_mcu_write;
2938 ops->read = mac_mcu_read;
2939 }
2940
42b82dc1 2941 index++;
2942 break;
2943 case PHY_CLEAR_READCOUNT:
2944 count = 0;
2945 index++;
2946 break;
bca03d5f 2947 case PHY_WRITE:
42b82dc1 2948 rtl_writephy(tp, regno, data);
2949 index++;
2950 break;
2951 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2952 index += (count == data) ? 2 : 1;
bca03d5f 2953 break;
42b82dc1 2954 case PHY_COMP_EQ_SKIPN:
2955 if (predata == data)
2956 index += regno;
2957 index++;
2958 break;
2959 case PHY_COMP_NEQ_SKIPN:
2960 if (predata != data)
2961 index += regno;
2962 index++;
2963 break;
2964 case PHY_WRITE_PREVIOUS:
2965 rtl_writephy(tp, regno, predata);
2966 index++;
2967 break;
2968 case PHY_SKIPN:
2969 index += regno + 1;
2970 break;
2971 case PHY_DELAY_MS:
2972 mdelay(data);
2973 index++;
2974 break;
2975
bca03d5f 2976 default:
2977 BUG();
2978 }
2979 }
eee3786f 2980
2981 ops->write = org.write;
2982 ops->read = org.read;
bca03d5f 2983}
2984
f1e02ed1 2985static void rtl_release_firmware(struct rtl8169_private *tp)
2986{
b6ffd97f
FR		 2987 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2988 release_firmware(tp->rtl_fw->fw);
2989 kfree(tp->rtl_fw);
2990 }
2991 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2992}
2993
953a12cc 2994static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2995{
b6ffd97f 2996 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2997
2998 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2999 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 3000 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 3001}
3002
3003static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
3004{
3005 if (rtl_readphy(tp, reg) != val)
3006 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
3007 else
3008 rtl_apply_firmware(tp);
f1e02ed1 3009}
3010
4da19633 3011static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 3012{
350f7596 3013 static const struct phy_reg phy_reg_init[] = {
0b9b571d 3014 { 0x1f, 0x0001 },
3015 { 0x06, 0x006e },
3016 { 0x08, 0x0708 },
3017 { 0x15, 0x4000 },
3018 { 0x18, 0x65c7 },
1da177e4 3019
0b9b571d 3020 { 0x1f, 0x0001 },
3021 { 0x03, 0x00a1 },
3022 { 0x02, 0x0008 },
3023 { 0x01, 0x0120 },
3024 { 0x00, 0x1000 },
3025 { 0x04, 0x0800 },
3026 { 0x04, 0x0000 },
1da177e4 3027
0b9b571d 3028 { 0x03, 0xff41 },
3029 { 0x02, 0xdf60 },
3030 { 0x01, 0x0140 },
3031 { 0x00, 0x0077 },
3032 { 0x04, 0x7800 },
3033 { 0x04, 0x7000 },
3034
3035 { 0x03, 0x802f },
3036 { 0x02, 0x4f02 },
3037 { 0x01, 0x0409 },
3038 { 0x00, 0xf0f9 },
3039 { 0x04, 0x9800 },
3040 { 0x04, 0x9000 },
3041
3042 { 0x03, 0xdf01 },
3043 { 0x02, 0xdf20 },
3044 { 0x01, 0xff95 },
3045 { 0x00, 0xba00 },
3046 { 0x04, 0xa800 },
3047 { 0x04, 0xa000 },
3048
3049 { 0x03, 0xff41 },
3050 { 0x02, 0xdf20 },
3051 { 0x01, 0x0140 },
3052 { 0x00, 0x00bb },
3053 { 0x04, 0xb800 },
3054 { 0x04, 0xb000 },
3055
3056 { 0x03, 0xdf41 },
3057 { 0x02, 0xdc60 },
3058 { 0x01, 0x6340 },
3059 { 0x00, 0x007d },
3060 { 0x04, 0xd800 },
3061 { 0x04, 0xd000 },
3062
3063 { 0x03, 0xdf01 },
3064 { 0x02, 0xdf20 },
3065 { 0x01, 0x100a },
3066 { 0x00, 0xa0ff },
3067 { 0x04, 0xf800 },
3068 { 0x04, 0xf000 },
3069
3070 { 0x1f, 0x0000 },
3071 { 0x0b, 0x0000 },
3072 { 0x00, 0x9200 }
3073 };
1da177e4 3074
4da19633 3075 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 3076}
3077
4da19633 3078static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 3079{
350f7596 3080 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 3081 { 0x1f, 0x0002 },
3082 { 0x01, 0x90d0 },
3083 { 0x1f, 0x0000 }
3084 };
3085
4da19633 3086 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 3087}
3088
4da19633 3089static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 3090{
3091 struct pci_dev *pdev = tp->pci_dev;
2e955856 3092
ccbae55e
SS		 3093 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
3094 (pdev->subsystem_device != 0xe000))
2e955856 3095 return;
3096
4da19633 3097 rtl_writephy(tp, 0x1f, 0x0001);
3098 rtl_writephy(tp, 0x10, 0xf01b);
3099 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 3100}
3101
4da19633 3102static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 3103{
350f7596 3104 static const struct phy_reg phy_reg_init[] = {
2e955856 3105 { 0x1f, 0x0001 },
3106 { 0x04, 0x0000 },
3107 { 0x03, 0x00a1 },
3108 { 0x02, 0x0008 },
3109 { 0x01, 0x0120 },
3110 { 0x00, 0x1000 },
3111 { 0x04, 0x0800 },
3112 { 0x04, 0x9000 },
3113 { 0x03, 0x802f },
3114 { 0x02, 0x4f02 },
3115 { 0x01, 0x0409 },
3116 { 0x00, 0xf099 },
3117 { 0x04, 0x9800 },
3118 { 0x04, 0xa000 },
3119 { 0x03, 0xdf01 },
3120 { 0x02, 0xdf20 },
3121 { 0x01, 0xff95 },
3122 { 0x00, 0xba00 },
3123 { 0x04, 0xa800 },
3124 { 0x04, 0xf000 },
3125 { 0x03, 0xdf01 },
3126 { 0x02, 0xdf20 },
3127 { 0x01, 0x101a },
3128 { 0x00, 0xa0ff },
3129 { 0x04, 0xf800 },
3130 { 0x04, 0x0000 },
3131 { 0x1f, 0x0000 },
3132
3133 { 0x1f, 0x0001 },
3134 { 0x10, 0xf41b },
3135 { 0x14, 0xfb54 },
3136 { 0x18, 0xf5c7 },
3137 { 0x1f, 0x0000 },
3138
3139 { 0x1f, 0x0001 },
3140 { 0x17, 0x0cc0 },
3141 { 0x1f, 0x0000 }
3142 };
3143
4da19633 3144 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 3145
4da19633 3146 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 3147}
3148
4da19633 3149static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 3150{
350f7596 3151 static const struct phy_reg phy_reg_init[] = {
8c7006aa 3152 { 0x1f, 0x0001 },
3153 { 0x04, 0x0000 },
3154 { 0x03, 0x00a1 },
3155 { 0x02, 0x0008 },
3156 { 0x01, 0x0120 },
3157 { 0x00, 0x1000 },
3158 { 0x04, 0x0800 },
3159 { 0x04, 0x9000 },
3160 { 0x03, 0x802f },
3161 { 0x02, 0x4f02 },
3162 { 0x01, 0x0409 },
3163 { 0x00, 0xf099 },
3164 { 0x04, 0x9800 },
3165 { 0x04, 0xa000 },
3166 { 0x03, 0xdf01 },
3167 { 0x02, 0xdf20 },
3168 { 0x01, 0xff95 },
3169 { 0x00, 0xba00 },
3170 { 0x04, 0xa800 },
3171 { 0x04, 0xf000 },
3172 { 0x03, 0xdf01 },
3173 { 0x02, 0xdf20 },
3174 { 0x01, 0x101a },
3175 { 0x00, 0xa0ff },
3176 { 0x04, 0xf800 },
3177 { 0x04, 0x0000 },
3178 { 0x1f, 0x0000 },
3179
3180 { 0x1f, 0x0001 },
3181 { 0x0b, 0x8480 },
3182 { 0x1f, 0x0000 },
3183
3184 { 0x1f, 0x0001 },
3185 { 0x18, 0x67c7 },
3186 { 0x04, 0x2000 },
3187 { 0x03, 0x002f },
3188 { 0x02, 0x4360 },
3189 { 0x01, 0x0109 },
3190 { 0x00, 0x3022 },
3191 { 0x04, 0x2800 },
3192 { 0x1f, 0x0000 },
3193
3194 { 0x1f, 0x0001 },
3195 { 0x17, 0x0cc0 },
3196 { 0x1f, 0x0000 }
3197 };
3198
4da19633 3199 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 3200}
3201
4da19633 3202static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 3203{
350f7596 3204 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 3205 { 0x10, 0xf41b },
3206 { 0x1f, 0x0000 }
3207 };
3208
4da19633 3209 rtl_writephy(tp, 0x1f, 0x0001);
3210 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 3211
4da19633 3212 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 3213}
3214
4da19633 3215static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 3216{
350f7596 3217 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 3218 { 0x1f, 0x0001 },
3219 { 0x10, 0xf41b },
3220 { 0x1f, 0x0000 }
3221 };
3222
4da19633 3223 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 3224}
3225
4da19633 3226static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 3227{
350f7596 3228 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 3229 { 0x1f, 0x0000 },
3230 { 0x1d, 0x0f00 },
3231 { 0x1f, 0x0002 },
3232 { 0x0c, 0x1ec8 },
3233 { 0x1f, 0x0000 }
3234 };
3235
4da19633 3236 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 3237}
3238
4da19633 3239static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 3240{
350f7596 3241 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 3242 { 0x1f, 0x0001 },
3243 { 0x1d, 0x3d98 },
3244 { 0x1f, 0x0000 }
3245 };
3246
4da19633 3247 rtl_writephy(tp, 0x1f, 0x0000);
3248 rtl_patchphy(tp, 0x14, 1 << 5);
3249 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 3250
4da19633 3251 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 3252}
3253
4da19633 3254static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 3255{
350f7596 3256 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 3257 { 0x1f, 0x0001 },
3258 { 0x12, 0x2300 },
867763c1
FR		 3259 { 0x1f, 0x0002 },
3260 { 0x00, 0x88d4 },
3261 { 0x01, 0x82b1 },
3262 { 0x03, 0x7002 },
3263 { 0x08, 0x9e30 },
3264 { 0x09, 0x01f0 },
3265 { 0x0a, 0x5500 },
3266 { 0x0c, 0x00c8 },
3267 { 0x1f, 0x0003 },
3268 { 0x12, 0xc096 },
3269 { 0x16, 0x000a },
f50d4275
FR		 3270 { 0x1f, 0x0000 },
3271 { 0x1f, 0x0000 },
3272 { 0x09, 0x2000 },
3273 { 0x09, 0x0000 }
867763c1
FR		 3274 };
3275
4da19633 3276 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3277
4da19633 3278 rtl_patchphy(tp, 0x14, 1 << 5);
3279 rtl_patchphy(tp, 0x0d, 1 << 5);
3280 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 3281}
3282
4da19633 3283static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 3284{
350f7596 3285 static const struct phy_reg phy_reg_init[] = {
f50d4275 3286 { 0x1f, 0x0001 },
7da97ec9 3287 { 0x12, 0x2300 },
f50d4275
FR		 3288 { 0x03, 0x802f },
3289 { 0x02, 0x4f02 },
3290 { 0x01, 0x0409 },
3291 { 0x00, 0xf099 },
3292 { 0x04, 0x9800 },
3293 { 0x04, 0x9000 },
3294 { 0x1d, 0x3d98 },
7da97ec9
FR		 3295 { 0x1f, 0x0002 },
3296 { 0x0c, 0x7eb8 },
f50d4275
FR		 3297 { 0x06, 0x0761 },
3298 { 0x1f, 0x0003 },
3299 { 0x16, 0x0f0a },
7da97ec9
FR		 3300 { 0x1f, 0x0000 }
3301 };
3302
4da19633 3303 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3304
4da19633 3305 rtl_patchphy(tp, 0x16, 1 << 0);
3306 rtl_patchphy(tp, 0x14, 1 << 5);
3307 rtl_patchphy(tp, 0x0d, 1 << 5);
3308 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 3309}
3310
4da19633 3311static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 3312{
350f7596 3313 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 3314 { 0x1f, 0x0001 },
3315 { 0x12, 0x2300 },
3316 { 0x1d, 0x3d98 },
3317 { 0x1f, 0x0002 },
3318 { 0x0c, 0x7eb8 },
3319 { 0x06, 0x5461 },
3320 { 0x1f, 0x0003 },
3321 { 0x16, 0x0f0a },
3322 { 0x1f, 0x0000 }
3323 };
3324
4da19633 3325 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 3326
4da19633 3327 rtl_patchphy(tp, 0x16, 1 << 0);
3328 rtl_patchphy(tp, 0x14, 1 << 5);
3329 rtl_patchphy(tp, 0x0d, 1 << 5);
3330 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 3331}
3332
4da19633 3333static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 3334{
4da19633 3335 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 3336}
3337
bca03d5f 3338static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 3339{
350f7596 3340 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3341 /* Channel Estimation */
5b538df9 3342 { 0x1f, 0x0001 },
daf9df6d 3343 { 0x06, 0x4064 },
3344 { 0x07, 0x2863 },
3345 { 0x08, 0x059c },
3346 { 0x09, 0x26b4 },
3347 { 0x0a, 0x6a19 },
3348 { 0x0b, 0xdcc8 },
3349 { 0x10, 0xf06d },
3350 { 0x14, 0x7f68 },
3351 { 0x18, 0x7fd9 },
3352 { 0x1c, 0xf0ff },
3353 { 0x1d, 0x3d9c },
5b538df9 3354 { 0x1f, 0x0003 },
daf9df6d 3355 { 0x12, 0xf49f },
3356 { 0x13, 0x070b },
3357 { 0x1a, 0x05ad },
bca03d5f 3358 { 0x14, 0x94c0 },
3359
3360 /*
3361 * Tx Error Issue
cecb5fd7 3362 * Enhance line driver power
bca03d5f 3363 */
5b538df9 3364 { 0x1f, 0x0002 },
daf9df6d 3365 { 0x06, 0x5561 },
3366 { 0x1f, 0x0005 },
3367 { 0x05, 0x8332 },
bca03d5f 3368 { 0x06, 0x5561 },
3369
3370 /*
3371 * Can not link to 1Gbps with bad cable
3372 * Decrease SNR threshold form 21.07dB to 19.04dB
3373 */
3374 { 0x1f, 0x0001 },
3375 { 0x17, 0x0cc0 },
daf9df6d 3376
5b538df9 3377 { 0x1f, 0x0000 },
bca03d5f 3378 { 0x0d, 0xf880 }
daf9df6d 3379 };
3380
4da19633 3381 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 3382
bca03d5f 3383 /*
3384 * Rx Error Issue
3385 * Fine Tune Switching regulator parameter
3386 */
4da19633 3387 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3388 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3389 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 3390
fdf6fc06 3391 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3392 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3393 { 0x1f, 0x0002 },
3394 { 0x05, 0x669a },
3395 { 0x1f, 0x0005 },
3396 { 0x05, 0x8330 },
3397 { 0x06, 0x669a },
3398 { 0x1f, 0x0002 }
3399 };
3400 int val;
3401
4da19633 3402 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3403
4da19633 3404 val = rtl_readphy(tp, 0x0d);
daf9df6d 3405
3406 if ((val & 0x00ff) != 0x006c) {
350f7596 3407 static const u32 set[] = {
daf9df6d 3408 0x0065, 0x0066, 0x0067, 0x0068,
3409 0x0069, 0x006a, 0x006b, 0x006c
3410 };
3411 int i;
3412
4da19633 3413 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3414
3415 val &= 0xff00;
3416 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3417 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3418 }
3419 } else {
350f7596 3420 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3421 { 0x1f, 0x0002 },
3422 { 0x05, 0x6662 },
3423 { 0x1f, 0x0005 },
3424 { 0x05, 0x8330 },
3425 { 0x06, 0x6662 }
3426 };
3427
4da19633 3428 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3429 }
3430
bca03d5f 3431 /* RSET couple improve */
4da19633 3432 rtl_writephy(tp, 0x1f, 0x0002);
3433 rtl_patchphy(tp, 0x0d, 0x0300);
3434 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 3435
bca03d5f 3436 /* Fine tune PLL performance */
4da19633 3437 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3438 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3439 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3440
4da19633 3441 rtl_writephy(tp, 0x1f, 0x0005);
3442 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3443
3444 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 3445
4da19633 3446 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3447}
3448
bca03d5f 3449static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3450{
350f7596 3451 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3452 /* Channel Estimation */
daf9df6d 3453 { 0x1f, 0x0001 },
3454 { 0x06, 0x4064 },
3455 { 0x07, 0x2863 },
3456 { 0x08, 0x059c },
3457 { 0x09, 0x26b4 },
3458 { 0x0a, 0x6a19 },
3459 { 0x0b, 0xdcc8 },
3460 { 0x10, 0xf06d },
3461 { 0x14, 0x7f68 },
3462 { 0x18, 0x7fd9 },
3463 { 0x1c, 0xf0ff },
3464 { 0x1d, 0x3d9c },
3465 { 0x1f, 0x0003 },
3466 { 0x12, 0xf49f },
3467 { 0x13, 0x070b },
3468 { 0x1a, 0x05ad },
3469 { 0x14, 0x94c0 },
3470
bca03d5f 3471 /*
3472 * Tx Error Issue
cecb5fd7 3473 * Enhance line driver power
bca03d5f 3474 */
daf9df6d 3475 { 0x1f, 0x0002 },
3476 { 0x06, 0x5561 },
3477 { 0x1f, 0x0005 },
3478 { 0x05, 0x8332 },
bca03d5f 3479 { 0x06, 0x5561 },
3480
3481 /*
3482 * Can not link to 1Gbps with bad cable
3483 * Decrease SNR threshold form 21.07dB to 19.04dB
3484 */
3485 { 0x1f, 0x0001 },
3486 { 0x17, 0x0cc0 },
daf9df6d 3487
3488 { 0x1f, 0x0000 },
bca03d5f 3489 { 0x0d, 0xf880 }
5b538df9
FR		 3490 };
3491
4da19633 3492 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 3493
fdf6fc06 3494 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3495 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3496 { 0x1f, 0x0002 },
3497 { 0x05, 0x669a },
5b538df9 3498 { 0x1f, 0x0005 },
daf9df6d 3499 { 0x05, 0x8330 },
3500 { 0x06, 0x669a },
3501
3502 { 0x1f, 0x0002 }
3503 };
3504 int val;
3505
4da19633 3506 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3507
4da19633 3508 val = rtl_readphy(tp, 0x0d);
daf9df6d 3509 if ((val & 0x00ff) != 0x006c) {
b6bc7650 3510 static const u32 set[] = {
daf9df6d 3511 0x0065, 0x0066, 0x0067, 0x0068,
3512 0x0069, 0x006a, 0x006b, 0x006c
3513 };
3514 int i;
3515
4da19633 3516 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3517
3518 val &= 0xff00;
3519 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3520 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3521 }
3522 } else {
350f7596 3523 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3524 { 0x1f, 0x0002 },
3525 { 0x05, 0x2642 },
5b538df9 3526 { 0x1f, 0x0005 },
daf9df6d 3527 { 0x05, 0x8330 },
3528 { 0x06, 0x2642 }
5b538df9
FR		 3529 };
3530
4da19633 3531 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3532 }
3533
bca03d5f 3534 /* Fine tune PLL performance */
4da19633 3535 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3536 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3537 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3538
bca03d5f 3539 /* Switching regulator Slew rate */
4da19633 3540 rtl_writephy(tp, 0x1f, 0x0002);
3541 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 3542
4da19633 3543 rtl_writephy(tp, 0x1f, 0x0005);
3544 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3545
3546 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 3547
4da19633 3548 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3549}
3550
4da19633 3551static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3552{
350f7596 3553 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3554 { 0x1f, 0x0002 },
3555 { 0x10, 0x0008 },
3556 { 0x0d, 0x006c },
3557
3558 { 0x1f, 0x0000 },
3559 { 0x0d, 0xf880 },
3560
3561 { 0x1f, 0x0001 },
3562 { 0x17, 0x0cc0 },
3563
3564 { 0x1f, 0x0001 },
3565 { 0x0b, 0xa4d8 },
3566 { 0x09, 0x281c },
3567 { 0x07, 0x2883 },
3568 { 0x0a, 0x6b35 },
3569 { 0x1d, 0x3da4 },
3570 { 0x1c, 0xeffd },
3571 { 0x14, 0x7f52 },
3572 { 0x18, 0x7fc6 },
3573 { 0x08, 0x0601 },
3574 { 0x06, 0x4063 },
3575 { 0x10, 0xf074 },
3576 { 0x1f, 0x0003 },
3577 { 0x13, 0x0789 },
3578 { 0x12, 0xf4bd },
3579 { 0x1a, 0x04fd },
3580 { 0x14, 0x84b0 },
3581 { 0x1f, 0x0000 },
3582 { 0x00, 0x9200 },
3583
3584 { 0x1f, 0x0005 },
3585 { 0x01, 0x0340 },
3586 { 0x1f, 0x0001 },
3587 { 0x04, 0x4000 },
3588 { 0x03, 0x1d21 },
3589 { 0x02, 0x0c32 },
3590 { 0x01, 0x0200 },
3591 { 0x00, 0x5554 },
3592 { 0x04, 0x4800 },
3593 { 0x04, 0x4000 },
3594 { 0x04, 0xf000 },
3595 { 0x03, 0xdf01 },
3596 { 0x02, 0xdf20 },
3597 { 0x01, 0x101a },
3598 { 0x00, 0xa0ff },
3599 { 0x04, 0xf800 },
3600 { 0x04, 0xf000 },
3601 { 0x1f, 0x0000 },
3602
3603 { 0x1f, 0x0007 },
3604 { 0x1e, 0x0023 },
3605 { 0x16, 0x0000 },
3606 { 0x1f, 0x0000 }
3607 };
3608
4da19633 3609 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3610}
3611
e6de30d6 3612static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3613{
3614 static const struct phy_reg phy_reg_init[] = {
3615 { 0x1f, 0x0001 },
3616 { 0x17, 0x0cc0 },
3617
3618 { 0x1f, 0x0007 },
3619 { 0x1e, 0x002d },
3620 { 0x18, 0x0040 },
3621 { 0x1f, 0x0000 }
3622 };
3623
3624 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3625 rtl_patchphy(tp, 0x0d, 1 << 5);
3626}
3627
70090424 3628static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3629{
3630 static const struct phy_reg phy_reg_init[] = {
3631 /* Enable Delay cap */
3632 { 0x1f, 0x0005 },
3633 { 0x05, 0x8b80 },
3634 { 0x06, 0xc896 },
3635 { 0x1f, 0x0000 },
3636
3637 /* Channel estimation fine tune */
3638 { 0x1f, 0x0001 },
3639 { 0x0b, 0x6c20 },
3640 { 0x07, 0x2872 },
3641 { 0x1c, 0xefff },
3642 { 0x1f, 0x0003 },
3643 { 0x14, 0x6420 },
3644 { 0x1f, 0x0000 },
3645
3646 /* Update PFM & 10M TX idle timer */
3647 { 0x1f, 0x0007 },
3648 { 0x1e, 0x002f },
3649 { 0x15, 0x1919 },
3650 { 0x1f, 0x0000 },
3651
3652 { 0x1f, 0x0007 },
3653 { 0x1e, 0x00ac },
3654 { 0x18, 0x0006 },
3655 { 0x1f, 0x0000 }
3656 };
3657
15ecd039
FR		 3658 rtl_apply_firmware(tp);
3659
01dc7fec 3660 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3661
3662 /* DCO enable for 10M IDLE Power */
3663 rtl_writephy(tp, 0x1f, 0x0007);
3664 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3665 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3666 rtl_writephy(tp, 0x1f, 0x0000);
3667
3668 /* For impedance matching */
3669 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3670 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3671 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3672
3673 /* PHY auto speed down */
3674 rtl_writephy(tp, 0x1f, 0x0007);
3675 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3676 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3677 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3678 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3679
3680 rtl_writephy(tp, 0x1f, 0x0005);
3681 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3682 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3683 rtl_writephy(tp, 0x1f, 0x0000);
3684
3685 rtl_writephy(tp, 0x1f, 0x0005);
3686 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3687 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3688 rtl_writephy(tp, 0x1f, 0x0007);
3689 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3690 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3691 rtl_writephy(tp, 0x1f, 0x0006);
3692 rtl_writephy(tp, 0x00, 0x5a00);
3693 rtl_writephy(tp, 0x1f, 0x0000);
3694 rtl_writephy(tp, 0x0d, 0x0007);
3695 rtl_writephy(tp, 0x0e, 0x003c);
3696 rtl_writephy(tp, 0x0d, 0x4007);
3697 rtl_writephy(tp, 0x0e, 0x0000);
3698 rtl_writephy(tp, 0x0d, 0x0000);
3699}
3700
9ecb9aab 3701static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3702{
3703 const u16 w[] = {
3704 addr[0] | (addr[1] << 8),
3705 addr[2] | (addr[3] << 8),
3706 addr[4] | (addr[5] << 8)
3707 };
3708 const struct exgmac_reg e[] = {
3709 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3710 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3711 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3712 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3713 };
3714
3715 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3716}
3717
70090424
HW		 3718static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3719{
3720 static const struct phy_reg phy_reg_init[] = {
3721 /* Enable Delay cap */
3722 { 0x1f, 0x0004 },
3723 { 0x1f, 0x0007 },
3724 { 0x1e, 0x00ac },
3725 { 0x18, 0x0006 },
3726 { 0x1f, 0x0002 },
3727 { 0x1f, 0x0000 },
3728 { 0x1f, 0x0000 },
3729
3730 /* Channel estimation fine tune */
3731 { 0x1f, 0x0003 },
3732 { 0x09, 0xa20f },
3733 { 0x1f, 0x0000 },
3734 { 0x1f, 0x0000 },
3735
3736 /* Green Setting */
3737 { 0x1f, 0x0005 },
3738 { 0x05, 0x8b5b },
3739 { 0x06, 0x9222 },
3740 { 0x05, 0x8b6d },
3741 { 0x06, 0x8000 },
3742 { 0x05, 0x8b76 },
3743 { 0x06, 0x8000 },
3744 { 0x1f, 0x0000 }
3745 };
3746
3747 rtl_apply_firmware(tp);
3748
3749 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3750
3751 /* For 4-corner performance improve */
3752 rtl_writephy(tp, 0x1f, 0x0005);
3753 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3754 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3755 rtl_writephy(tp, 0x1f, 0x0000);
3756
3757 /* PHY auto speed down */
3758 rtl_writephy(tp, 0x1f, 0x0004);
3759 rtl_writephy(tp, 0x1f, 0x0007);
3760 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3761 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3762 rtl_writephy(tp, 0x1f, 0x0002);
3763 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3764 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3765
3766 /* improve 10M EEE waveform */
3767 rtl_writephy(tp, 0x1f, 0x0005);
3768 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3769 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3770 rtl_writephy(tp, 0x1f, 0x0000);
3771
3772 /* Improve 2-pair detection performance */
3773 rtl_writephy(tp, 0x1f, 0x0005);
3774 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3775 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3776 rtl_writephy(tp, 0x1f, 0x0000);
3777
3778 /* EEE setting */
1814d6a8 3779 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
70090424
HW		 3780 rtl_writephy(tp, 0x1f, 0x0005);
3781 rtl_writephy(tp, 0x05, 0x8b85);
1814d6a8 3782 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
70090424
HW		 3783 rtl_writephy(tp, 0x1f, 0x0004);
3784 rtl_writephy(tp, 0x1f, 0x0007);
3785 rtl_writephy(tp, 0x1e, 0x0020);
1814d6a8 3786 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
70090424
HW		 3787 rtl_writephy(tp, 0x1f, 0x0002);
3788 rtl_writephy(tp, 0x1f, 0x0000);
3789 rtl_writephy(tp, 0x0d, 0x0007);
3790 rtl_writephy(tp, 0x0e, 0x003c);
3791 rtl_writephy(tp, 0x0d, 0x4007);
1814d6a8 3792 rtl_writephy(tp, 0x0e, 0x0006);
70090424
HW		 3793 rtl_writephy(tp, 0x0d, 0x0000);
3794
3795 /* Green feature */
3796 rtl_writephy(tp, 0x1f, 0x0003);
1814d6a8
HK		 3797 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3798 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
70090424 3799 rtl_writephy(tp, 0x1f, 0x0000);
b399a394
HK		 3800 rtl_writephy(tp, 0x1f, 0x0005);
3801 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3802 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3803
9ecb9aab 3804 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3805 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3806}
3807
5f886e08
HW		 3808static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3809{
3810 /* For 4-corner performance improve */
3811 rtl_writephy(tp, 0x1f, 0x0005);
3812 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3813 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3814 rtl_writephy(tp, 0x1f, 0x0000);
3815
3816 /* PHY auto speed down */
3817 rtl_writephy(tp, 0x1f, 0x0007);
3818 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3819 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3820 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3821 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3822
3823 /* Improve 10M EEE waveform */
3824 rtl_writephy(tp, 0x1f, 0x0005);
3825 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3826 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3827 rtl_writephy(tp, 0x1f, 0x0000);
3828}
3829
c2218925
HW		 3830static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3831{
3832 static const struct phy_reg phy_reg_init[] = {
3833 /* Channel estimation fine tune */
3834 { 0x1f, 0x0003 },
3835 { 0x09, 0xa20f },
3836 { 0x1f, 0x0000 },
3837
3838 /* Modify green table for giga & fnet */
3839 { 0x1f, 0x0005 },
3840 { 0x05, 0x8b55 },
3841 { 0x06, 0x0000 },
3842 { 0x05, 0x8b5e },
3843 { 0x06, 0x0000 },
3844 { 0x05, 0x8b67 },
3845 { 0x06, 0x0000 },
3846 { 0x05, 0x8b70 },
3847 { 0x06, 0x0000 },
3848 { 0x1f, 0x0000 },
3849 { 0x1f, 0x0007 },
3850 { 0x1e, 0x0078 },
3851 { 0x17, 0x0000 },
3852 { 0x19, 0x00fb },
3853 { 0x1f, 0x0000 },
3854
3855 /* Modify green table for 10M */
3856 { 0x1f, 0x0005 },
3857 { 0x05, 0x8b79 },
3858 { 0x06, 0xaa00 },
3859 { 0x1f, 0x0000 },
3860
3861 /* Disable hiimpedance detection (RTCT) */
3862 { 0x1f, 0x0003 },
3863 { 0x01, 0x328a },
3864 { 0x1f, 0x0000 }
3865 };
3866
3867 rtl_apply_firmware(tp);
3868
3869 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3870
5f886e08 3871 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3872
3873 /* Improve 2-pair detection performance */
3874 rtl_writephy(tp, 0x1f, 0x0005);
3875 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3876 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3877 rtl_writephy(tp, 0x1f, 0x0000);
3878}
3879
3880static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3881{
3882 rtl_apply_firmware(tp);
3883
5f886e08 3884 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3885}
3886
b3d7b2f2
HW		 3887static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3888{
b3d7b2f2
HW		 3889 static const struct phy_reg phy_reg_init[] = {
3890 /* Channel estimation fine tune */
3891 { 0x1f, 0x0003 },
3892 { 0x09, 0xa20f },
3893 { 0x1f, 0x0000 },
3894
3895 /* Modify green table for giga & fnet */
3896 { 0x1f, 0x0005 },
3897 { 0x05, 0x8b55 },
3898 { 0x06, 0x0000 },
3899 { 0x05, 0x8b5e },
3900 { 0x06, 0x0000 },
3901 { 0x05, 0x8b67 },
3902 { 0x06, 0x0000 },
3903 { 0x05, 0x8b70 },
3904 { 0x06, 0x0000 },
3905 { 0x1f, 0x0000 },
3906 { 0x1f, 0x0007 },
3907 { 0x1e, 0x0078 },
3908 { 0x17, 0x0000 },
3909 { 0x19, 0x00aa },
3910 { 0x1f, 0x0000 },
3911
3912 /* Modify green table for 10M */
3913 { 0x1f, 0x0005 },
3914 { 0x05, 0x8b79 },
3915 { 0x06, 0xaa00 },
3916 { 0x1f, 0x0000 },
3917
3918 /* Disable hiimpedance detection (RTCT) */
3919 { 0x1f, 0x0003 },
3920 { 0x01, 0x328a },
3921 { 0x1f, 0x0000 }
3922 };
3923
3924
3925 rtl_apply_firmware(tp);
3926
3927 rtl8168f_hw_phy_config(tp);
3928
3929 /* Improve 2-pair detection performance */
3930 rtl_writephy(tp, 0x1f, 0x0005);
3931 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3932 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3933 rtl_writephy(tp, 0x1f, 0x0000);
3934
3935 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3936
3937 /* Modify green table for giga */
3938 rtl_writephy(tp, 0x1f, 0x0005);
3939 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3940 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3941 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3942 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3943 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3944 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3945 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3946 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3947 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3948 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3949 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3950 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3951 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3952 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3953 rtl_writephy(tp, 0x1f, 0x0000);
3954
3955 /* uc same-seed solution */
3956 rtl_writephy(tp, 0x1f, 0x0005);
3957 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3958 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3959 rtl_writephy(tp, 0x1f, 0x0000);
3960
3961 /* eee setting */
706123d0 3962 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3963 rtl_writephy(tp, 0x1f, 0x0005);
3964 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3965 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3966 rtl_writephy(tp, 0x1f, 0x0004);
3967 rtl_writephy(tp, 0x1f, 0x0007);
3968 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3969 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3970 rtl_writephy(tp, 0x1f, 0x0000);
3971 rtl_writephy(tp, 0x0d, 0x0007);
3972 rtl_writephy(tp, 0x0e, 0x003c);
3973 rtl_writephy(tp, 0x0d, 0x4007);
3974 rtl_writephy(tp, 0x0e, 0x0000);
3975 rtl_writephy(tp, 0x0d, 0x0000);
3976
3977 /* Green feature */
3978 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3979 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3980 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3981 rtl_writephy(tp, 0x1f, 0x0000);
3982}
3983
c558386b
HW		 3984static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3985{
c558386b
HW		 3986 rtl_apply_firmware(tp);
3987
41f44d13 3988 rtl_writephy(tp, 0x1f, 0x0a46);
3989 if (rtl_readphy(tp, 0x10) & 0x0100) {
3990 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3991 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3992 } else {
3993 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3994 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3995 }
c558386b 3996
41f44d13 3997 rtl_writephy(tp, 0x1f, 0x0a46);
3998 if (rtl_readphy(tp, 0x13) & 0x0100) {
3999 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 4000 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 4001 } else {
fe7524c0 4002 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 4003 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 4004 }
c558386b 4005
41f44d13 4006 /* Enable PHY auto speed down */
4007 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 4008 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 4009
fe7524c0 4010 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 4011 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 4012 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 4013 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 4014 rtl_writephy(tp, 0x1f, 0x0a43);
4015 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 4016 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4017 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 4018
41f44d13 4019 /* EEE auto-fallback function */
4020 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 4021 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 4022
41f44d13 4023 /* Enable UC LPF tune function */
4024 rtl_writephy(tp, 0x1f, 0x0a43);
4025 rtl_writephy(tp, 0x13, 0x8012);
76564428 4026 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 4027
4028 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 4029 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 4030
fe7524c0 4031 /* Improve SWR Efficiency */
4032 rtl_writephy(tp, 0x1f, 0x0bcd);
4033 rtl_writephy(tp, 0x14, 0x5065);
4034 rtl_writephy(tp, 0x14, 0xd065);
4035 rtl_writephy(tp, 0x1f, 0x0bc8);
4036 rtl_writephy(tp, 0x11, 0x5655);
4037 rtl_writephy(tp, 0x1f, 0x0bcd);
4038 rtl_writephy(tp, 0x14, 0x1065);
4039 rtl_writephy(tp, 0x14, 0x9065);
4040 rtl_writephy(tp, 0x14, 0x1065);
4041
1bac1072
DC		 4042 /* Check ALDPS bit, disable it if enabled */
4043 rtl_writephy(tp, 0x1f, 0x0a43);
4044 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 4045 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 4046
41f44d13 4047 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 4048}
4049
57538c4a 4050static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
4051{
4052 rtl_apply_firmware(tp);
4053}
4054
6e1d0b89
CHL		 4055static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
4056{
4057 u16 dout_tapbin;
4058 u32 data;
4059
4060 rtl_apply_firmware(tp);
4061
4062 /* CHN EST parameters adjust - giga master */
4063 rtl_writephy(tp, 0x1f, 0x0a43);
4064 rtl_writephy(tp, 0x13, 0x809b);
76564428 4065 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 4066 rtl_writephy(tp, 0x13, 0x80a2);
76564428 4067 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 4068 rtl_writephy(tp, 0x13, 0x80a4);
76564428 4069 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 4070 rtl_writephy(tp, 0x13, 0x809c);
76564428 4071 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 4072 rtl_writephy(tp, 0x1f, 0x0000);
4073
4074 /* CHN EST parameters adjust - giga slave */
4075 rtl_writephy(tp, 0x1f, 0x0a43);
4076 rtl_writephy(tp, 0x13, 0x80ad);
76564428 4077 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 4078 rtl_writephy(tp, 0x13, 0x80b4);
76564428 4079 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 4080 rtl_writephy(tp, 0x13, 0x80ac);
76564428 4081 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 4082 rtl_writephy(tp, 0x1f, 0x0000);
4083
4084 /* CHN EST parameters adjust - fnet */
4085 rtl_writephy(tp, 0x1f, 0x0a43);
4086 rtl_writephy(tp, 0x13, 0x808e);
76564428 4087 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 4088 rtl_writephy(tp, 0x13, 0x8090);
76564428 4089 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 4090 rtl_writephy(tp, 0x13, 0x8092);
76564428 4091 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 4092 rtl_writephy(tp, 0x1f, 0x0000);
4093
4094 /* enable R-tune & PGA-retune function */
4095 dout_tapbin = 0;
4096 rtl_writephy(tp, 0x1f, 0x0a46);
4097 data = rtl_readphy(tp, 0x13);
4098 data &= 3;
4099 data <<= 2;
4100 dout_tapbin |= data;
4101 data = rtl_readphy(tp, 0x12);
4102 data &= 0xc000;
4103 data >>= 14;
4104 dout_tapbin |= data;
4105 dout_tapbin = ~(dout_tapbin^0x08);
4106 dout_tapbin <<= 12;
4107 dout_tapbin &= 0xf000;
4108 rtl_writephy(tp, 0x1f, 0x0a43);
4109 rtl_writephy(tp, 0x13, 0x827a);
76564428 4110 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 4111 rtl_writephy(tp, 0x13, 0x827b);
76564428 4112 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 4113 rtl_writephy(tp, 0x13, 0x827c);
76564428 4114 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 4115 rtl_writephy(tp, 0x13, 0x827d);
76564428 4116 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 4117
4118 rtl_writephy(tp, 0x1f, 0x0a43);
4119 rtl_writephy(tp, 0x13, 0x0811);
76564428 4120 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 4121 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 4122 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 4123 rtl_writephy(tp, 0x1f, 0x0000);
4124
4125 /* enable GPHY 10M */
4126 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 4127 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 4128 rtl_writephy(tp, 0x1f, 0x0000);
4129
4130 /* SAR ADC performance */
4131 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 4132 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 4133 rtl_writephy(tp, 0x1f, 0x0000);
4134
4135 rtl_writephy(tp, 0x1f, 0x0a43);
4136 rtl_writephy(tp, 0x13, 0x803f);
76564428 4137 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4138 rtl_writephy(tp, 0x13, 0x8047);
76564428 4139 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4140 rtl_writephy(tp, 0x13, 0x804f);
76564428 4141 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4142 rtl_writephy(tp, 0x13, 0x8057);
76564428 4143 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4144 rtl_writephy(tp, 0x13, 0x805f);
76564428 4145 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4146 rtl_writephy(tp, 0x13, 0x8067);
76564428 4147 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4148 rtl_writephy(tp, 0x13, 0x806f);
76564428 4149 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 4150 rtl_writephy(tp, 0x1f, 0x0000);
4151
4152 /* disable phy pfm mode */
4153 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 4154 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 4155 rtl_writephy(tp, 0x1f, 0x0000);
4156
4157 /* Check ALDPS bit, disable it if enabled */
4158 rtl_writephy(tp, 0x1f, 0x0a43);
4159 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 4160 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 4161
4162 rtl_writephy(tp, 0x1f, 0x0000);
4163}
4164
4165static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
4166{
4167 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
4168 u16 rlen;
4169 u32 data;
4170
4171 rtl_apply_firmware(tp);
4172
4173 /* CHIN EST parameter update */
4174 rtl_writephy(tp, 0x1f, 0x0a43);
4175 rtl_writephy(tp, 0x13, 0x808a);
76564428 4176 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 4177 rtl_writephy(tp, 0x1f, 0x0000);
4178
4179 /* enable R-tune & PGA-retune function */
4180 rtl_writephy(tp, 0x1f, 0x0a43);
4181 rtl_writephy(tp, 0x13, 0x0811);
76564428 4182 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 4183 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 4184 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 4185 rtl_writephy(tp, 0x1f, 0x0000);
4186
4187 /* enable GPHY 10M */
4188 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 4189 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 4190 rtl_writephy(tp, 0x1f, 0x0000);
4191
4192 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
4193 data = r8168_mac_ocp_read(tp, 0xdd02);
4194 ioffset_p3 = ((data & 0x80)>>7);
4195 ioffset_p3 <<= 3;
4196
4197 data = r8168_mac_ocp_read(tp, 0xdd00);
4198 ioffset_p3 |= ((data & (0xe000))>>13);
4199 ioffset_p2 = ((data & (0x1e00))>>9);
4200 ioffset_p1 = ((data & (0x01e0))>>5);
4201 ioffset_p0 = ((data & 0x0010)>>4);
4202 ioffset_p0 <<= 3;
4203 ioffset_p0 |= (data & (0x07));
4204 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
4205
05b9687b 4206 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
e2e2788e 4207 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
6e1d0b89
CHL		 4208 rtl_writephy(tp, 0x1f, 0x0bcf);
4209 rtl_writephy(tp, 0x16, data);
4210 rtl_writephy(tp, 0x1f, 0x0000);
4211 }
4212
4213 /* Modify rlen (TX LPF corner frequency) level */
4214 rtl_writephy(tp, 0x1f, 0x0bcd);
4215 data = rtl_readphy(tp, 0x16);
4216 data &= 0x000f;
4217 rlen = 0;
4218 if (data > 3)
4219 rlen = data - 3;
4220 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
4221 rtl_writephy(tp, 0x17, data);
4222 rtl_writephy(tp, 0x1f, 0x0bcd);
4223 rtl_writephy(tp, 0x1f, 0x0000);
4224
4225 /* disable phy pfm mode */
4226 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 4227 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 4228 rtl_writephy(tp, 0x1f, 0x0000);
4229
4230 /* Check ALDPS bit, disable it if enabled */
4231 rtl_writephy(tp, 0x1f, 0x0a43);
4232 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 4233 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 4234
4235 rtl_writephy(tp, 0x1f, 0x0000);
4236}
4237
935e2218
CHL		 4238static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4239{
4240 /* Enable PHY auto speed down */
4241 rtl_writephy(tp, 0x1f, 0x0a44);
4242 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4243 rtl_writephy(tp, 0x1f, 0x0000);
4244
4245 /* patch 10M & ALDPS */
4246 rtl_writephy(tp, 0x1f, 0x0bcc);
4247 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4248 rtl_writephy(tp, 0x1f, 0x0a44);
4249 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4250 rtl_writephy(tp, 0x1f, 0x0a43);
4251 rtl_writephy(tp, 0x13, 0x8084);
4252 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4253 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4254 rtl_writephy(tp, 0x1f, 0x0000);
4255
4256 /* Enable EEE auto-fallback function */
4257 rtl_writephy(tp, 0x1f, 0x0a4b);
4258 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4259 rtl_writephy(tp, 0x1f, 0x0000);
4260
4261 /* Enable UC LPF tune function */
4262 rtl_writephy(tp, 0x1f, 0x0a43);
4263 rtl_writephy(tp, 0x13, 0x8012);
4264 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4265 rtl_writephy(tp, 0x1f, 0x0000);
4266
4267 /* set rg_sel_sdm_rate */
4268 rtl_writephy(tp, 0x1f, 0x0c42);
4269 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4270 rtl_writephy(tp, 0x1f, 0x0000);
4271
4272 /* Check ALDPS bit, disable it if enabled */
4273 rtl_writephy(tp, 0x1f, 0x0a43);
4274 if (rtl_readphy(tp, 0x10) & 0x0004)
4275 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4276
4277 rtl_writephy(tp, 0x1f, 0x0000);
4278}
4279
4280static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4281{
4282 /* patch 10M & ALDPS */
4283 rtl_writephy(tp, 0x1f, 0x0bcc);
4284 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4285 rtl_writephy(tp, 0x1f, 0x0a44);
4286 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4287 rtl_writephy(tp, 0x1f, 0x0a43);
4288 rtl_writephy(tp, 0x13, 0x8084);
4289 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4290 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4291 rtl_writephy(tp, 0x1f, 0x0000);
4292
4293 /* Enable UC LPF tune function */
4294 rtl_writephy(tp, 0x1f, 0x0a43);
4295 rtl_writephy(tp, 0x13, 0x8012);
4296 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4297 rtl_writephy(tp, 0x1f, 0x0000);
4298
4299 /* Set rg_sel_sdm_rate */
4300 rtl_writephy(tp, 0x1f, 0x0c42);
4301 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4302 rtl_writephy(tp, 0x1f, 0x0000);
4303
4304 /* Channel estimation parameters */
4305 rtl_writephy(tp, 0x1f, 0x0a43);
4306 rtl_writephy(tp, 0x13, 0x80f3);
4307 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4308 rtl_writephy(tp, 0x13, 0x80f0);
4309 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4310 rtl_writephy(tp, 0x13, 0x80ef);
4311 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4312 rtl_writephy(tp, 0x13, 0x80f6);
4313 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4314 rtl_writephy(tp, 0x13, 0x80ec);
4315 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4316 rtl_writephy(tp, 0x13, 0x80ed);
4317 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4318 rtl_writephy(tp, 0x13, 0x80f2);
4319 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4320 rtl_writephy(tp, 0x13, 0x80f4);
4321 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4322 rtl_writephy(tp, 0x1f, 0x0a43);
4323 rtl_writephy(tp, 0x13, 0x8110);
4324 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4325 rtl_writephy(tp, 0x13, 0x810f);
4326 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4327 rtl_writephy(tp, 0x13, 0x8111);
4328 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4329 rtl_writephy(tp, 0x13, 0x8113);
4330 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4331 rtl_writephy(tp, 0x13, 0x8115);
4332 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4333 rtl_writephy(tp, 0x13, 0x810e);
4334 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4335 rtl_writephy(tp, 0x13, 0x810c);
4336 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4337 rtl_writephy(tp, 0x13, 0x810b);
4338 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4339 rtl_writephy(tp, 0x1f, 0x0a43);
4340 rtl_writephy(tp, 0x13, 0x80d1);
4341 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4342 rtl_writephy(tp, 0x13, 0x80cd);
4343 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4344 rtl_writephy(tp, 0x13, 0x80d3);
4345 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4346 rtl_writephy(tp, 0x13, 0x80d5);
4347 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4348 rtl_writephy(tp, 0x13, 0x80d7);
4349 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4350
4351 /* Force PWM-mode */
4352 rtl_writephy(tp, 0x1f, 0x0bcd);
4353 rtl_writephy(tp, 0x14, 0x5065);
4354 rtl_writephy(tp, 0x14, 0xd065);
4355 rtl_writephy(tp, 0x1f, 0x0bc8);
4356 rtl_writephy(tp, 0x12, 0x00ed);
4357 rtl_writephy(tp, 0x1f, 0x0bcd);
4358 rtl_writephy(tp, 0x14, 0x1065);
4359 rtl_writephy(tp, 0x14, 0x9065);
4360 rtl_writephy(tp, 0x14, 0x1065);
4361 rtl_writephy(tp, 0x1f, 0x0000);
4362
4363 /* Check ALDPS bit, disable it if enabled */
4364 rtl_writephy(tp, 0x1f, 0x0a43);
4365 if (rtl_readphy(tp, 0x10) & 0x0004)
4366 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4367
4368 rtl_writephy(tp, 0x1f, 0x0000);
4369}
4370
4da19633 4371static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 4372{
350f7596 4373 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 4374 { 0x1f, 0x0003 },
4375 { 0x08, 0x441d },
4376 { 0x01, 0x9100 },
4377 { 0x1f, 0x0000 }
4378 };
4379
4da19633 4380 rtl_writephy(tp, 0x1f, 0x0000);
4381 rtl_patchphy(tp, 0x11, 1 << 12);
4382 rtl_patchphy(tp, 0x19, 1 << 13);
4383 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 4384
4da19633 4385 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 4386}
4387
5a5e4443
HW		 4388static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4389{
4390 static const struct phy_reg phy_reg_init[] = {
4391 { 0x1f, 0x0005 },
4392 { 0x1a, 0x0000 },
4393 { 0x1f, 0x0000 },
4394
4395 { 0x1f, 0x0004 },
4396 { 0x1c, 0x0000 },
4397 { 0x1f, 0x0000 },
4398
4399 { 0x1f, 0x0001 },
4400 { 0x15, 0x7701 },
4401 { 0x1f, 0x0000 }
4402 };
4403
4404 /* Disable ALDPS before ram code */
eef63cc1
FR		 4405 rtl_writephy(tp, 0x1f, 0x0000);
4406 rtl_writephy(tp, 0x18, 0x0310);
4407 msleep(100);
5a5e4443 4408
953a12cc 4409 rtl_apply_firmware(tp);
5a5e4443
HW		 4410
4411 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4412}
4413
7e18dca1
HW		 4414static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4415{
7e18dca1 4416 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 4417 rtl_writephy(tp, 0x1f, 0x0000);
4418 rtl_writephy(tp, 0x18, 0x0310);
4419 msleep(20);
7e18dca1
HW		 4420
4421 rtl_apply_firmware(tp);
4422
4423 /* EEE setting */
fdf6fc06 4424 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 4425 rtl_writephy(tp, 0x1f, 0x0004);
4426 rtl_writephy(tp, 0x10, 0x401f);
4427 rtl_writephy(tp, 0x19, 0x7030);
4428 rtl_writephy(tp, 0x1f, 0x0000);
4429}
4430
5598bfe5
HW		 4431static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4432{
5598bfe5
HW		 4433 static const struct phy_reg phy_reg_init[] = {
4434 { 0x1f, 0x0004 },
4435 { 0x10, 0xc07f },
4436 { 0x19, 0x7030 },
4437 { 0x1f, 0x0000 }
4438 };
4439
4440 /* Disable ALDPS before ram code */
eef63cc1
FR		 4441 rtl_writephy(tp, 0x1f, 0x0000);
4442 rtl_writephy(tp, 0x18, 0x0310);
4443 msleep(100);
5598bfe5
HW		 4444
4445 rtl_apply_firmware(tp);
4446
fdf6fc06 4447 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4448 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4449
fdf6fc06 4450 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4451}
4452
5615d9f1
FR		 4453static void rtl_hw_phy_config(struct net_device *dev)
4454{
4455 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 4456
4457 rtl8169_print_mac_version(tp);
4458
4459 switch (tp->mac_version) {
4460 case RTL_GIGA_MAC_VER_01:
4461 break;
4462 case RTL_GIGA_MAC_VER_02:
4463 case RTL_GIGA_MAC_VER_03:
4da19633 4464 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 4465 break;
4466 case RTL_GIGA_MAC_VER_04:
4da19633 4467 rtl8169sb_hw_phy_config(tp);
5615d9f1 4468 break;
2e955856 4469 case RTL_GIGA_MAC_VER_05:
4da19633 4470 rtl8169scd_hw_phy_config(tp);
2e955856 4471 break;
8c7006aa 4472 case RTL_GIGA_MAC_VER_06:
4da19633 4473 rtl8169sce_hw_phy_config(tp);
8c7006aa 4474 break;
2857ffb7
FR		 4475 case RTL_GIGA_MAC_VER_07:
4476 case RTL_GIGA_MAC_VER_08:
4477 case RTL_GIGA_MAC_VER_09:
4da19633 4478 rtl8102e_hw_phy_config(tp);
2857ffb7 4479 break;
236b8082 4480 case RTL_GIGA_MAC_VER_11:
4da19633 4481 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 4482 break;
4483 case RTL_GIGA_MAC_VER_12:
4da19633 4484 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 4485 break;
4486 case RTL_GIGA_MAC_VER_17:
4da19633 4487 rtl8168bef_hw_phy_config(tp);
236b8082 4488 break;
867763c1 4489 case RTL_GIGA_MAC_VER_18:
4da19633 4490 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 4491 break;
4492 case RTL_GIGA_MAC_VER_19:
4da19633 4493 rtl8168c_1_hw_phy_config(tp);
867763c1 4494 break;
7da97ec9 4495 case RTL_GIGA_MAC_VER_20:
4da19633 4496 rtl8168c_2_hw_phy_config(tp);
7da97ec9 4497 break;
197ff761 4498 case RTL_GIGA_MAC_VER_21:
4da19633 4499 rtl8168c_3_hw_phy_config(tp);
197ff761 4500 break;
6fb07058 4501 case RTL_GIGA_MAC_VER_22:
4da19633 4502 rtl8168c_4_hw_phy_config(tp);
6fb07058 4503 break;
ef3386f0 4504 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 4505 case RTL_GIGA_MAC_VER_24:
4da19633 4506 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 4507 break;
5b538df9 4508 case RTL_GIGA_MAC_VER_25:
bca03d5f 4509 rtl8168d_1_hw_phy_config(tp);
daf9df6d 4510 break;
4511 case RTL_GIGA_MAC_VER_26:
bca03d5f 4512 rtl8168d_2_hw_phy_config(tp);
daf9df6d 4513 break;
4514 case RTL_GIGA_MAC_VER_27:
4da19633 4515 rtl8168d_3_hw_phy_config(tp);
5b538df9 4516 break;
e6de30d6 4517 case RTL_GIGA_MAC_VER_28:
4518 rtl8168d_4_hw_phy_config(tp);
4519 break;
5a5e4443
HW		 4520 case RTL_GIGA_MAC_VER_29:
4521 case RTL_GIGA_MAC_VER_30:
4522 rtl8105e_hw_phy_config(tp);
4523 break;
cecb5fd7
FR		 4524 case RTL_GIGA_MAC_VER_31:
4525 /* None. */
4526 break;
01dc7fec 4527 case RTL_GIGA_MAC_VER_32:
01dc7fec 4528 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4529 rtl8168e_1_hw_phy_config(tp);
4530 break;
4531 case RTL_GIGA_MAC_VER_34:
4532 rtl8168e_2_hw_phy_config(tp);
01dc7fec 4533 break;
c2218925
HW		 4534 case RTL_GIGA_MAC_VER_35:
4535 rtl8168f_1_hw_phy_config(tp);
4536 break;
4537 case RTL_GIGA_MAC_VER_36:
4538 rtl8168f_2_hw_phy_config(tp);
4539 break;
ef3386f0 4540
7e18dca1
HW		 4541 case RTL_GIGA_MAC_VER_37:
4542 rtl8402_hw_phy_config(tp);
4543 break;
4544
b3d7b2f2
HW		 4545 case RTL_GIGA_MAC_VER_38:
4546 rtl8411_hw_phy_config(tp);
4547 break;
4548
5598bfe5
HW		 4549 case RTL_GIGA_MAC_VER_39:
4550 rtl8106e_hw_phy_config(tp);
4551 break;
4552
c558386b
HW		 4553 case RTL_GIGA_MAC_VER_40:
4554 rtl8168g_1_hw_phy_config(tp);
4555 break;
57538c4a 4556 case RTL_GIGA_MAC_VER_42:
58152cd4 4557 case RTL_GIGA_MAC_VER_43:
45dd95c4 4558 case RTL_GIGA_MAC_VER_44:
57538c4a 4559 rtl8168g_2_hw_phy_config(tp);
4560 break;
6e1d0b89
CHL		 4561 case RTL_GIGA_MAC_VER_45:
4562 case RTL_GIGA_MAC_VER_47:
4563 rtl8168h_1_hw_phy_config(tp);
4564 break;
4565 case RTL_GIGA_MAC_VER_46:
4566 case RTL_GIGA_MAC_VER_48:
4567 rtl8168h_2_hw_phy_config(tp);
4568 break;
c558386b 4569
935e2218
CHL		 4570 case RTL_GIGA_MAC_VER_49:
4571 rtl8168ep_1_hw_phy_config(tp);
4572 break;
4573 case RTL_GIGA_MAC_VER_50:
4574 case RTL_GIGA_MAC_VER_51:
4575 rtl8168ep_2_hw_phy_config(tp);
4576 break;
4577
c558386b 4578 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 4579 default:
4580 break;
4581 }
4582}
4583
da78dbff 4584static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 4585{
1da177e4
LT		 4586 struct timer_list *timer = &tp->timer;
4587 void __iomem *ioaddr = tp->mmio_addr;
4588 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4589
bcf0bf90 4590 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 4591
4da19633 4592 if (tp->phy_reset_pending(tp)) {
5b0384f4 4593 /*
1da177e4
LT		 4594 * A busy loop could burn quite a few cycles on nowadays CPU.
4595 * Let's delay the execution of the timer for a few ticks.
4596 */
4597 timeout = HZ/10;
4598 goto out_mod_timer;
4599 }
4600
4601 if (tp->link_ok(ioaddr))
da78dbff 4602 return;
1da177e4 4603
9bb8eeb5 4604 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 4605
4da19633 4606 tp->phy_reset_enable(tp);
1da177e4
LT		 4607
4608out_mod_timer:
4609 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 4610}
4611
4612static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4613{
da78dbff
FR		 4614 if (!test_and_set_bit(flag, tp->wk.flags))
4615 schedule_work(&tp->wk.work);
da78dbff
FR		 4616}
4617
9de36ccf 4618static void rtl8169_phy_timer(struct timer_list *t)
da78dbff 4619{
9de36ccf 4620 struct rtl8169_private *tp = from_timer(tp, t, timer);
da78dbff 4621
98ddf986 4622 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 4623}
4624
ffc46952
FR		 4625DECLARE_RTL_COND(rtl_phy_reset_cond)
4626{
4627 return tp->phy_reset_pending(tp);
4628}
4629
bf793295
FR		 4630static void rtl8169_phy_reset(struct net_device *dev,
4631 struct rtl8169_private *tp)
4632{
4da19633 4633 tp->phy_reset_enable(tp);
ffc46952 4634 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 4635}
4636
2544bfc0
FR		 4637static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4638{
4639 void __iomem *ioaddr = tp->mmio_addr;
4640
4641 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4642 (RTL_R8(PHYstatus) & TBI_Enable);
4643}
4644
4ff96fa6
FR		 4645static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4646{
4647 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 4648
5615d9f1 4649 rtl_hw_phy_config(dev);
4ff96fa6 4650
77332894
MS		 4651 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4652 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4653 RTL_W8(0x82, 0x01);
4654 }
4ff96fa6 4655
6dccd16b
FR		 4656 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4657
4658 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4659 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4660
bcf0bf90 4661 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 4662 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4663 RTL_W8(0x82, 0x01);
4664 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4665 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4666 }
4667
bf793295
FR		 4668 rtl8169_phy_reset(dev, tp);
4669
54405cde 4670 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 4671 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4672 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4673 (tp->mii.supports_gmii ?
4674 ADVERTISED_1000baseT_Half |
4675 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 4676
2544bfc0 4677 if (rtl_tbi_enabled(tp))
bf82c189 4678 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 4679}
4680
773d2021
FR		 4681static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4682{
4683 void __iomem *ioaddr = tp->mmio_addr;
773d2021 4684
da78dbff 4685 rtl_lock_work(tp);
773d2021
FR		 4686
4687 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 4688
9ecb9aab 4689 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 4690 RTL_R32(MAC4);
4691
9ecb9aab 4692 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 4693 RTL_R32(MAC0);
4694
9ecb9aab 4695 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4696 rtl_rar_exgmac_set(tp, addr);
c28aa385 4697
773d2021
FR		 4698 RTL_W8(Cfg9346, Cfg9346_Lock);
4699
da78dbff 4700 rtl_unlock_work(tp);
773d2021
FR		 4701}
4702
4703static int rtl_set_mac_address(struct net_device *dev, void *p)
4704{
4705 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 4706 struct device *d = &tp->pci_dev->dev;
773d2021
FR		 4707 struct sockaddr *addr = p;
4708
4709 if (!is_valid_ether_addr(addr->sa_data))
4710 return -EADDRNOTAVAIL;
4711
4712 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4713
f51d4a10
CHL		 4714 pm_runtime_get_noresume(d);
4715
4716 if (pm_runtime_active(d))
4717 rtl_rar_set(tp, dev->dev_addr);
4718
4719 pm_runtime_put_noidle(d);
773d2021
FR		 4720
4721 return 0;
4722}
4723
5f787a1a
FR		 4724static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4725{
4726 struct rtl8169_private *tp = netdev_priv(dev);
4727 struct mii_ioctl_data *data = if_mii(ifr);
4728
8b4ab28d
FR		 4729 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4730}
5f787a1a 4731
cecb5fd7
FR		 4732static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4733 struct mii_ioctl_data *data, int cmd)
8b4ab28d 4734{
5f787a1a
FR		 4735 switch (cmd) {
4736 case SIOCGMIIPHY:
4737 data->phy_id = 32; /* Internal PHY */
4738 return 0;
4739
4740 case SIOCGMIIREG:
4da19633 4741 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 4742 return 0;
4743
4744 case SIOCSMIIREG:
4da19633 4745 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 4746 return 0;
4747 }
4748 return -EOPNOTSUPP;
4749}
4750
8b4ab28d
FR		 4751static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4752{
4753 return -EOPNOTSUPP;
4754}
4755
baf63293 4756static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4757{
4758 struct mdio_ops *ops = &tp->mdio_ops;
4759
4760 switch (tp->mac_version) {
4761 case RTL_GIGA_MAC_VER_27:
4762 ops->write = r8168dp_1_mdio_write;
4763 ops->read = r8168dp_1_mdio_read;
4764 break;
e6de30d6 4765 case RTL_GIGA_MAC_VER_28:
4804b3b3 4766 case RTL_GIGA_MAC_VER_31:
e6de30d6 4767 ops->write = r8168dp_2_mdio_write;
4768 ops->read = r8168dp_2_mdio_read;
4769 break;
c558386b
HW		 4770 case RTL_GIGA_MAC_VER_40:
4771 case RTL_GIGA_MAC_VER_41:
57538c4a 4772 case RTL_GIGA_MAC_VER_42:
58152cd4 4773 case RTL_GIGA_MAC_VER_43:
45dd95c4 4774 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4775 case RTL_GIGA_MAC_VER_45:
4776 case RTL_GIGA_MAC_VER_46:
4777 case RTL_GIGA_MAC_VER_47:
4778 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4779 case RTL_GIGA_MAC_VER_49:
4780 case RTL_GIGA_MAC_VER_50:
4781 case RTL_GIGA_MAC_VER_51:
c558386b
HW		 4782 ops->write = r8168g_mdio_write;
4783 ops->read = r8168g_mdio_read;
4784 break;
c0e45c1c 4785 default:
4786 ops->write = r8169_mdio_write;
4787 ops->read = r8169_mdio_read;
4788 break;
4789 }
4790}
4791
e2409d83 4792static void rtl_speed_down(struct rtl8169_private *tp)
4793{
4794 u32 adv;
4795 int lpa;
4796
4797 rtl_writephy(tp, 0x1f, 0x0000);
4798 lpa = rtl_readphy(tp, MII_LPA);
4799
4800 if (lpa & (LPA_10HALF | LPA_10FULL))
4801 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4802 else if (lpa & (LPA_100HALF | LPA_100FULL))
4803 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4804 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4805 else
4806 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4807 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4808 (tp->mii.supports_gmii ?
4809 ADVERTISED_1000baseT_Half |
4810 ADVERTISED_1000baseT_Full : 0);
4811
4812 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4813 adv);
4814}
4815
649b3b8c 4816static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4817{
4818 void __iomem *ioaddr = tp->mmio_addr;
4819
4820 switch (tp->mac_version) {
b00e69de
CB		 4821 case RTL_GIGA_MAC_VER_25:
4822 case RTL_GIGA_MAC_VER_26:
649b3b8c 4823 case RTL_GIGA_MAC_VER_29:
4824 case RTL_GIGA_MAC_VER_30:
4825 case RTL_GIGA_MAC_VER_32:
4826 case RTL_GIGA_MAC_VER_33:
4827 case RTL_GIGA_MAC_VER_34:
7e18dca1 4828 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4829 case RTL_GIGA_MAC_VER_38:
5598bfe5 4830 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 4831 case RTL_GIGA_MAC_VER_40:
4832 case RTL_GIGA_MAC_VER_41:
57538c4a 4833 case RTL_GIGA_MAC_VER_42:
58152cd4 4834 case RTL_GIGA_MAC_VER_43:
45dd95c4 4835 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4836 case RTL_GIGA_MAC_VER_45:
4837 case RTL_GIGA_MAC_VER_46:
4838 case RTL_GIGA_MAC_VER_47:
4839 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4840 case RTL_GIGA_MAC_VER_49:
4841 case RTL_GIGA_MAC_VER_50:
4842 case RTL_GIGA_MAC_VER_51:
649b3b8c 4843 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4844 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4845 break;
4846 default:
4847 break;
4848 }
4849}
4850
4851static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4852{
4853 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4854 return false;
4855
e2409d83 4856 rtl_speed_down(tp);
649b3b8c 4857 rtl_wol_suspend_quirk(tp);
4858
4859 return true;
4860}
4861
065c27c1 4862static void r810x_phy_power_down(struct rtl8169_private *tp)
4863{
4864 rtl_writephy(tp, 0x1f, 0x0000);
4865 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4866}
4867
4868static void r810x_phy_power_up(struct rtl8169_private *tp)
4869{
4870 rtl_writephy(tp, 0x1f, 0x0000);
4871 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4872}
4873
4874static void r810x_pll_power_down(struct rtl8169_private *tp)
4875{
0004299a
HW		 4876 void __iomem *ioaddr = tp->mmio_addr;
4877
649b3b8c 4878 if (rtl_wol_pll_power_down(tp))
065c27c1 4879 return;
065c27c1 4880
4881 r810x_phy_power_down(tp);
0004299a
HW		 4882
4883 switch (tp->mac_version) {
4884 case RTL_GIGA_MAC_VER_07:
4885 case RTL_GIGA_MAC_VER_08:
4886 case RTL_GIGA_MAC_VER_09:
4887 case RTL_GIGA_MAC_VER_10:
4888 case RTL_GIGA_MAC_VER_13:
4889 case RTL_GIGA_MAC_VER_16:
4890 break;
4891 default:
4892 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4893 break;
4894 }
065c27c1 4895}
4896
4897static void r810x_pll_power_up(struct rtl8169_private *tp)
4898{
0004299a
HW		 4899 void __iomem *ioaddr = tp->mmio_addr;
4900
065c27c1 4901 r810x_phy_power_up(tp);
0004299a
HW		 4902
4903 switch (tp->mac_version) {
4904 case RTL_GIGA_MAC_VER_07:
4905 case RTL_GIGA_MAC_VER_08:
4906 case RTL_GIGA_MAC_VER_09:
4907 case RTL_GIGA_MAC_VER_10:
4908 case RTL_GIGA_MAC_VER_13:
4909 case RTL_GIGA_MAC_VER_16:
4910 break;
6e1d0b89
CHL		 4911 case RTL_GIGA_MAC_VER_47:
4912 case RTL_GIGA_MAC_VER_48:
05b9687b 4913 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 4914 break;
0004299a
HW		 4915 default:
4916 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4917 break;
4918 }
065c27c1 4919}
4920
4921static void r8168_phy_power_up(struct rtl8169_private *tp)
4922{
4923 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4924 switch (tp->mac_version) {
4925 case RTL_GIGA_MAC_VER_11:
4926 case RTL_GIGA_MAC_VER_12:
4927 case RTL_GIGA_MAC_VER_17:
4928 case RTL_GIGA_MAC_VER_18:
4929 case RTL_GIGA_MAC_VER_19:
4930 case RTL_GIGA_MAC_VER_20:
4931 case RTL_GIGA_MAC_VER_21:
4932 case RTL_GIGA_MAC_VER_22:
4933 case RTL_GIGA_MAC_VER_23:
4934 case RTL_GIGA_MAC_VER_24:
4935 case RTL_GIGA_MAC_VER_25:
4936 case RTL_GIGA_MAC_VER_26:
4937 case RTL_GIGA_MAC_VER_27:
4938 case RTL_GIGA_MAC_VER_28:
4939 case RTL_GIGA_MAC_VER_31:
4940 rtl_writephy(tp, 0x0e, 0x0000);
4941 break;
4942 default:
4943 break;
4944 }
065c27c1 4945 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4946}
4947
4948static void r8168_phy_power_down(struct rtl8169_private *tp)
4949{
4950 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4951 switch (tp->mac_version) {
4952 case RTL_GIGA_MAC_VER_32:
4953 case RTL_GIGA_MAC_VER_33:
beb330a4 4954 case RTL_GIGA_MAC_VER_40:
4955 case RTL_GIGA_MAC_VER_41:
01dc7fec 4956 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4957 break;
4958
4959 case RTL_GIGA_MAC_VER_11:
4960 case RTL_GIGA_MAC_VER_12:
4961 case RTL_GIGA_MAC_VER_17:
4962 case RTL_GIGA_MAC_VER_18:
4963 case RTL_GIGA_MAC_VER_19:
4964 case RTL_GIGA_MAC_VER_20:
4965 case RTL_GIGA_MAC_VER_21:
4966 case RTL_GIGA_MAC_VER_22:
4967 case RTL_GIGA_MAC_VER_23:
4968 case RTL_GIGA_MAC_VER_24:
4969 case RTL_GIGA_MAC_VER_25:
4970 case RTL_GIGA_MAC_VER_26:
4971 case RTL_GIGA_MAC_VER_27:
4972 case RTL_GIGA_MAC_VER_28:
4973 case RTL_GIGA_MAC_VER_31:
4974 rtl_writephy(tp, 0x0e, 0x0200);
4975 default:
4976 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4977 break;
4978 }
065c27c1 4979}
4980
4981static void r8168_pll_power_down(struct rtl8169_private *tp)
4982{
4983 void __iomem *ioaddr = tp->mmio_addr;
4984
9dbe7896 4985 if (r8168_check_dash(tp))
065c27c1 4986 return;
4987
cecb5fd7
FR		 4988 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4989 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4990 (RTL_R16(CPlusCmd) & ASF)) {
4991 return;
4992 }
4993
01dc7fec 4994 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4995 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4996 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4997
649b3b8c 4998 if (rtl_wol_pll_power_down(tp))
065c27c1 4999 return;
065c27c1 5000
5001 r8168_phy_power_down(tp);
5002
5003 switch (tp->mac_version) {
5004 case RTL_GIGA_MAC_VER_25:
5005 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 5006 case RTL_GIGA_MAC_VER_27:
5007 case RTL_GIGA_MAC_VER_28:
4804b3b3 5008 case RTL_GIGA_MAC_VER_31:
01dc7fec 5009 case RTL_GIGA_MAC_VER_32:
5010 case RTL_GIGA_MAC_VER_33:
42fde737 5011 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5012 case RTL_GIGA_MAC_VER_45:
5013 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 5014 case RTL_GIGA_MAC_VER_50:
5015 case RTL_GIGA_MAC_VER_51:
065c27c1 5016 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
5017 break;
beb330a4 5018 case RTL_GIGA_MAC_VER_40:
5019 case RTL_GIGA_MAC_VER_41:
935e2218 5020 case RTL_GIGA_MAC_VER_49:
706123d0 5021 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 5022 0xfc000000, ERIAR_EXGMAC);
b8e5e6ad 5023 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
beb330a4 5024 break;
065c27c1 5025 }
5026}
5027
5028static void r8168_pll_power_up(struct rtl8169_private *tp)
5029{
5030 void __iomem *ioaddr = tp->mmio_addr;
5031
065c27c1 5032 switch (tp->mac_version) {
5033 case RTL_GIGA_MAC_VER_25:
5034 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 5035 case RTL_GIGA_MAC_VER_27:
5036 case RTL_GIGA_MAC_VER_28:
4804b3b3 5037 case RTL_GIGA_MAC_VER_31:
01dc7fec 5038 case RTL_GIGA_MAC_VER_32:
5039 case RTL_GIGA_MAC_VER_33:
065c27c1 5040 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
5041 break;
42fde737 5042 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5043 case RTL_GIGA_MAC_VER_45:
5044 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 5045 case RTL_GIGA_MAC_VER_50:
5046 case RTL_GIGA_MAC_VER_51:
05b9687b 5047 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 5048 break;
beb330a4 5049 case RTL_GIGA_MAC_VER_40:
5050 case RTL_GIGA_MAC_VER_41:
935e2218 5051 case RTL_GIGA_MAC_VER_49:
b8e5e6ad 5052 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
706123d0 5053 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 5054 0x00000000, ERIAR_EXGMAC);
5055 break;
065c27c1 5056 }
5057
5058 r8168_phy_power_up(tp);
5059}
5060
d58d46b5
FR		 5061static void rtl_generic_op(struct rtl8169_private *tp,
5062 void (*op)(struct rtl8169_private *))
065c27c1 5063{
5064 if (op)
5065 op(tp);
5066}
5067
5068static void rtl_pll_power_down(struct rtl8169_private *tp)
5069{
d58d46b5 5070 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 5071}
5072
5073static void rtl_pll_power_up(struct rtl8169_private *tp)
5074{
d58d46b5 5075 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 5076}
5077
baf63293 5078static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 5079{
5080 struct pll_power_ops *ops = &tp->pll_power_ops;
5081
5082 switch (tp->mac_version) {
5083 case RTL_GIGA_MAC_VER_07:
5084 case RTL_GIGA_MAC_VER_08:
5085 case RTL_GIGA_MAC_VER_09:
5086 case RTL_GIGA_MAC_VER_10:
5087 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 5088 case RTL_GIGA_MAC_VER_29:
5089 case RTL_GIGA_MAC_VER_30:
7e18dca1 5090 case RTL_GIGA_MAC_VER_37:
5598bfe5 5091 case RTL_GIGA_MAC_VER_39:
58152cd4 5092 case RTL_GIGA_MAC_VER_43:
6e1d0b89
CHL		 5093 case RTL_GIGA_MAC_VER_47:
5094 case RTL_GIGA_MAC_VER_48:
065c27c1 5095 ops->down = r810x_pll_power_down;
5096 ops->up = r810x_pll_power_up;
5097 break;
5098
5099 case RTL_GIGA_MAC_VER_11:
5100 case RTL_GIGA_MAC_VER_12:
5101 case RTL_GIGA_MAC_VER_17:
5102 case RTL_GIGA_MAC_VER_18:
5103 case RTL_GIGA_MAC_VER_19:
5104 case RTL_GIGA_MAC_VER_20:
5105 case RTL_GIGA_MAC_VER_21:
5106 case RTL_GIGA_MAC_VER_22:
5107 case RTL_GIGA_MAC_VER_23:
5108 case RTL_GIGA_MAC_VER_24:
5109 case RTL_GIGA_MAC_VER_25:
5110 case RTL_GIGA_MAC_VER_26:
5111 case RTL_GIGA_MAC_VER_27:
e6de30d6 5112 case RTL_GIGA_MAC_VER_28:
4804b3b3 5113 case RTL_GIGA_MAC_VER_31:
01dc7fec 5114 case RTL_GIGA_MAC_VER_32:
5115 case RTL_GIGA_MAC_VER_33:
70090424 5116 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 5117 case RTL_GIGA_MAC_VER_35:
5118 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 5119 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 5120 case RTL_GIGA_MAC_VER_40:
5121 case RTL_GIGA_MAC_VER_41:
57538c4a 5122 case RTL_GIGA_MAC_VER_42:
45dd95c4 5123 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5124 case RTL_GIGA_MAC_VER_45:
5125 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 5126 case RTL_GIGA_MAC_VER_49:
5127 case RTL_GIGA_MAC_VER_50:
5128 case RTL_GIGA_MAC_VER_51:
065c27c1 5129 ops->down = r8168_pll_power_down;
5130 ops->up = r8168_pll_power_up;
5131 break;
5132
5133 default:
5134 ops->down = NULL;
5135 ops->up = NULL;
5136 break;
5137 }
5138}
5139
e542a226
HW		 5140static void rtl_init_rxcfg(struct rtl8169_private *tp)
5141{
5142 void __iomem *ioaddr = tp->mmio_addr;
5143
5144 switch (tp->mac_version) {
5145 case RTL_GIGA_MAC_VER_01:
5146 case RTL_GIGA_MAC_VER_02:
5147 case RTL_GIGA_MAC_VER_03:
5148 case RTL_GIGA_MAC_VER_04:
5149 case RTL_GIGA_MAC_VER_05:
5150 case RTL_GIGA_MAC_VER_06:
5151 case RTL_GIGA_MAC_VER_10:
5152 case RTL_GIGA_MAC_VER_11:
5153 case RTL_GIGA_MAC_VER_12:
5154 case RTL_GIGA_MAC_VER_13:
5155 case RTL_GIGA_MAC_VER_14:
5156 case RTL_GIGA_MAC_VER_15:
5157 case RTL_GIGA_MAC_VER_16:
5158 case RTL_GIGA_MAC_VER_17:
5159 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
5160 break;
5161 case RTL_GIGA_MAC_VER_18:
5162 case RTL_GIGA_MAC_VER_19:
5163 case RTL_GIGA_MAC_VER_20:
5164 case RTL_GIGA_MAC_VER_21:
5165 case RTL_GIGA_MAC_VER_22:
5166 case RTL_GIGA_MAC_VER_23:
5167 case RTL_GIGA_MAC_VER_24:
eb2dc35d 5168 case RTL_GIGA_MAC_VER_34:
3ced8c95 5169 case RTL_GIGA_MAC_VER_35:
e542a226
HW		 5170 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
5171 break;
beb330a4 5172 case RTL_GIGA_MAC_VER_40:
5173 case RTL_GIGA_MAC_VER_41:
57538c4a 5174 case RTL_GIGA_MAC_VER_42:
58152cd4 5175 case RTL_GIGA_MAC_VER_43:
45dd95c4 5176 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5177 case RTL_GIGA_MAC_VER_45:
5178 case RTL_GIGA_MAC_VER_46:
5179 case RTL_GIGA_MAC_VER_47:
5180 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 5181 case RTL_GIGA_MAC_VER_49:
5182 case RTL_GIGA_MAC_VER_50:
5183 case RTL_GIGA_MAC_VER_51:
7ebc4822 5184 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 5185 break;
e542a226
HW		 5186 default:
5187 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
5188 break;
5189 }
5190}
5191
92fc43b4
HW		 5192static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
5193{
9fba0812 5194 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 5195}
5196
d58d46b5
FR		 5197static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
5198{
9c5028e9 5199 void __iomem *ioaddr = tp->mmio_addr;
5200
5201 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 5202 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 5203 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 5204}
5205
5206static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5207{
9c5028e9 5208 void __iomem *ioaddr = tp->mmio_addr;
5209
5210 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 5211 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 5212 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 5213}
5214
5215static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5216{
5217 void __iomem *ioaddr = tp->mmio_addr;
5218
5219 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5220 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
f65d539c 5221 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 5222}
5223
5224static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5225{
5226 void __iomem *ioaddr = tp->mmio_addr;
5227
5228 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5229 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
5230 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5231}
5232
5233static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5234{
5235 void __iomem *ioaddr = tp->mmio_addr;
5236
5237 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5238}
5239
5240static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5241{
5242 void __iomem *ioaddr = tp->mmio_addr;
5243
5244 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5245}
5246
5247static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5248{
5249 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 5250
5251 RTL_W8(MaxTxPacketSize, 0x3f);
5252 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5253 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
f65d539c 5254 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 5255}
5256
5257static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5258{
5259 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 5260
5261 RTL_W8(MaxTxPacketSize, 0x0c);
5262 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5263 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 5264 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 5265}
5266
5267static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5268{
5269 rtl_tx_performance_tweak(tp->pci_dev,
f65d539c 5270 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 5271}
5272
5273static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5274{
5275 rtl_tx_performance_tweak(tp->pci_dev,
5276 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5277}
5278
5279static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5280{
5281 void __iomem *ioaddr = tp->mmio_addr;
5282
5283 r8168b_0_hw_jumbo_enable(tp);
5284
5285 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5286}
5287
5288static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5289{
5290 void __iomem *ioaddr = tp->mmio_addr;
5291
5292 r8168b_0_hw_jumbo_disable(tp);
5293
5294 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5295}
5296
baf63293 5297static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 5298{
5299 struct jumbo_ops *ops = &tp->jumbo_ops;
5300
5301 switch (tp->mac_version) {
5302 case RTL_GIGA_MAC_VER_11:
5303 ops->disable = r8168b_0_hw_jumbo_disable;
5304 ops->enable = r8168b_0_hw_jumbo_enable;
5305 break;
5306 case RTL_GIGA_MAC_VER_12:
5307 case RTL_GIGA_MAC_VER_17:
5308 ops->disable = r8168b_1_hw_jumbo_disable;
5309 ops->enable = r8168b_1_hw_jumbo_enable;
5310 break;
5311 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5312 case RTL_GIGA_MAC_VER_19:
5313 case RTL_GIGA_MAC_VER_20:
5314 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5315 case RTL_GIGA_MAC_VER_22:
5316 case RTL_GIGA_MAC_VER_23:
5317 case RTL_GIGA_MAC_VER_24:
5318 case RTL_GIGA_MAC_VER_25:
5319 case RTL_GIGA_MAC_VER_26:
5320 ops->disable = r8168c_hw_jumbo_disable;
5321 ops->enable = r8168c_hw_jumbo_enable;
5322 break;
5323 case RTL_GIGA_MAC_VER_27:
5324 case RTL_GIGA_MAC_VER_28:
5325 ops->disable = r8168dp_hw_jumbo_disable;
5326 ops->enable = r8168dp_hw_jumbo_enable;
5327 break;
5328 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5329 case RTL_GIGA_MAC_VER_32:
5330 case RTL_GIGA_MAC_VER_33:
5331 case RTL_GIGA_MAC_VER_34:
5332 ops->disable = r8168e_hw_jumbo_disable;
5333 ops->enable = r8168e_hw_jumbo_enable;
5334 break;
5335
5336 /*
5337 * No action needed for jumbo frames with 8169.
5338 * No jumbo for 810x at all.
5339 */
c558386b
HW		 5340 case RTL_GIGA_MAC_VER_40:
5341 case RTL_GIGA_MAC_VER_41:
57538c4a 5342 case RTL_GIGA_MAC_VER_42:
58152cd4 5343 case RTL_GIGA_MAC_VER_43:
45dd95c4 5344 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5345 case RTL_GIGA_MAC_VER_45:
5346 case RTL_GIGA_MAC_VER_46:
5347 case RTL_GIGA_MAC_VER_47:
5348 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 5349 case RTL_GIGA_MAC_VER_49:
5350 case RTL_GIGA_MAC_VER_50:
5351 case RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 5352 default:
5353 ops->disable = NULL;
5354 ops->enable = NULL;
5355 break;
5356 }
5357}
5358
ffc46952
FR		 5359DECLARE_RTL_COND(rtl_chipcmd_cond)
5360{
5361 void __iomem *ioaddr = tp->mmio_addr;
5362
5363 return RTL_R8(ChipCmd) & CmdReset;
5364}
5365
6f43adc8
FR		 5366static void rtl_hw_reset(struct rtl8169_private *tp)
5367{
5368 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 5369
6f43adc8
FR		 5370 RTL_W8(ChipCmd, CmdReset);
5371
ffc46952 5372 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 5373}
5374
b6ffd97f 5375static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 5376{
b6ffd97f
FR		 5377 struct rtl_fw *rtl_fw;
5378 const char *name;
5379 int rc = -ENOMEM;
953a12cc 5380
b6ffd97f
FR		 5381 name = rtl_lookup_firmware_name(tp);
5382 if (!name)
5383 goto out_no_firmware;
953a12cc 5384
b6ffd97f
FR		 5385 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5386 if (!rtl_fw)
5387 goto err_warn;
31bd204f 5388
b6ffd97f
FR		 5389 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5390 if (rc < 0)
5391 goto err_free;
5392
fd112f2e
FR		 5393 rc = rtl_check_firmware(tp, rtl_fw);
5394 if (rc < 0)
5395 goto err_release_firmware;
5396
b6ffd97f
FR		 5397 tp->rtl_fw = rtl_fw;
5398out:
5399 return;
5400
fd112f2e
FR		 5401err_release_firmware:
5402 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 5403err_free:
5404 kfree(rtl_fw);
5405err_warn:
5406 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5407 name, rc);
5408out_no_firmware:
5409 tp->rtl_fw = NULL;
5410 goto out;
5411}
5412
5413static void rtl_request_firmware(struct rtl8169_private *tp)
5414{
5415 if (IS_ERR(tp->rtl_fw))
5416 rtl_request_uncached_firmware(tp);
953a12cc
FR		 5417}
5418
92fc43b4
HW		 5419static void rtl_rx_close(struct rtl8169_private *tp)
5420{
5421 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 5422
1687b566 5423 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 5424}
5425
ffc46952
FR		 5426DECLARE_RTL_COND(rtl_npq_cond)
5427{
5428 void __iomem *ioaddr = tp->mmio_addr;
5429
5430 return RTL_R8(TxPoll) & NPQ;
5431}
5432
5433DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5434{
5435 void __iomem *ioaddr = tp->mmio_addr;
5436
5437 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5438}
5439
e6de30d6 5440static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 5441{
e6de30d6 5442 void __iomem *ioaddr = tp->mmio_addr;
5443
1da177e4 5444 /* Disable interrupts */
811fd301 5445 rtl8169_irq_mask_and_ack(tp);
1da177e4 5446
92fc43b4
HW		 5447 rtl_rx_close(tp);
5448
5d2e1957 5449 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 5450 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5451 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 5452 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925 5453 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
6e1d0b89
CHL		 5454 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5455 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5456 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5457 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5458 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5459 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5460 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5461 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5462 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5463 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5464 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5465 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
935e2218
CHL		 5466 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5467 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5468 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5469 tp->mac_version == RTL_GIGA_MAC_VER_51) {
c2b0c1e7 5470 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 5471 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 5472 } else {
5473 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5474 udelay(100);
e6de30d6 5475 }
5476
92fc43b4 5477 rtl_hw_reset(tp);
1da177e4
LT		 5478}
5479
7f796d83 5480static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 5481{
5482 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 5483
5484 /* Set DMA burst size and Interframe Gap Time */
5485 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5486 (InterFrameGap << TxInterFrameGapShift));
5487}
5488
07ce4064 5489static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 5490{
5491 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5492
07ce4064
FR		 5493 tp->hw_start(dev);
5494
da78dbff 5495 rtl_irq_enable_all(tp);
07ce4064
FR		 5496}
5497
7f796d83
FR		 5498static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5499 void __iomem *ioaddr)
5500{
5501 /*
5502 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5503 * register to be written before TxDescAddrLow to work.
5504 * Switching from MMIO to I/O access fixes the issue as well.
5505 */
5506 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 5507 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 5508 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 5509 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 5510}
5511
5512static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5513{
5514 u16 cmd;
5515
5516 cmd = RTL_R16(CPlusCmd);
5517 RTL_W16(CPlusCmd, cmd);
5518 return cmd;
5519}
5520
fdd7b4c3 5521static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 5522{
5523 /* Low hurts. Let's disable the filtering. */
207d6e87 5524 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 5525}
5526
6dccd16b
FR		 5527static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5528{
3744100e 5529 static const struct rtl_cfg2_info {
6dccd16b
FR		 5530 u32 mac_version;
5531 u32 clk;
5532 u32 val;
5533 } cfg2_info [] = {
5534 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5535 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5536 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5537 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 5538 };
5539 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 5540 unsigned int i;
5541 u32 clk;
5542
5543 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 5544 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 5545 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5546 RTL_W32(0x7c, p->val);
5547 break;
5548 }
5549 }
5550}
5551
e6b763ea
FR		 5552static void rtl_set_rx_mode(struct net_device *dev)
5553{
5554 struct rtl8169_private *tp = netdev_priv(dev);
5555 void __iomem *ioaddr = tp->mmio_addr;
5556 u32 mc_filter[2]; /* Multicast hash filter */
5557 int rx_mode;
5558 u32 tmp = 0;
5559
5560 if (dev->flags & IFF_PROMISC) {
5561 /* Unconditionally log net taps. */
5562 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5563 rx_mode =
5564 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5565 AcceptAllPhys;
5566 mc_filter[1] = mc_filter[0] = 0xffffffff;
5567 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5568 (dev->flags & IFF_ALLMULTI)) {
5569 /* Too many to filter perfectly -- accept all multicasts. */
5570 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5571 mc_filter[1] = mc_filter[0] = 0xffffffff;
5572 } else {
5573 struct netdev_hw_addr *ha;
5574
5575 rx_mode = AcceptBroadcast | AcceptMyPhys;
5576 mc_filter[1] = mc_filter[0] = 0;
5577 netdev_for_each_mc_addr(ha, dev) {
5578 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5579 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5580 rx_mode |= AcceptMulticast;
5581 }
5582 }
5583
5584 if (dev->features & NETIF_F_RXALL)
5585 rx_mode |= (AcceptErr | AcceptRunt);
5586
5587 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5588
5589 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5590 u32 data = mc_filter[0];
5591
5592 mc_filter[0] = swab32(mc_filter[1]);
5593 mc_filter[1] = swab32(data);
5594 }
5595
0481776b
NW		 5596 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5597 mc_filter[1] = mc_filter[0] = 0xffffffff;
5598
e6b763ea
FR		 5599 RTL_W32(MAR0 + 4, mc_filter[1]);
5600 RTL_W32(MAR0 + 0, mc_filter[0]);
5601
5602 RTL_W32(RxConfig, tmp);
5603}
5604
07ce4064
FR		 5605static void rtl_hw_start_8169(struct net_device *dev)
5606{
5607 struct rtl8169_private *tp = netdev_priv(dev);
5608 void __iomem *ioaddr = tp->mmio_addr;
5609 struct pci_dev *pdev = tp->pci_dev;
07ce4064 5610
9cb427b6
FR		 5611 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5612 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5613 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5614 }
5615
1da177e4 5616 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 5617 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5618 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5619 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5620 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 5621 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5622
e542a226
HW		 5623 rtl_init_rxcfg(tp);
5624
f0298f81 5625 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 5626
6f0333b8 5627 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 5628
cecb5fd7
FR		 5629 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5630 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5631 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5632 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 5633 rtl_set_rx_tx_config_registers(tp);
1da177e4 5634
7f796d83 5635 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 5636
cecb5fd7
FR		 5637 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5638 tp->mac_version == RTL_GIGA_MAC_VER_03) {
05b9687b 5639 dprintk("Set MAC Reg C+CR Offset 0xe0. "
1da177e4 5640 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 5641 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 5642 }
5643
bcf0bf90
FR		 5644 RTL_W16(CPlusCmd, tp->cp_cmd);
5645
6dccd16b
FR		 5646 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5647
1da177e4
LT		 5648 /*
5649 * Undocumented corner. Supposedly:
5650 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5651 */
5652 RTL_W16(IntrMitigate, 0x0000);
5653
7f796d83 5654 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 5655
cecb5fd7
FR		 5656 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5657 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5658 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5659 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 5660 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5661 rtl_set_rx_tx_config_registers(tp);
5662 }
5663
1da177e4 5664 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 5665
5666 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5667 RTL_R8(IntrMask);
1da177e4
LT		 5668
5669 RTL_W32(RxMissed, 0);
5670
07ce4064 5671 rtl_set_rx_mode(dev);
1da177e4
LT		 5672
5673 /* no early-rx interrupts */
05b9687b 5674 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 5675}
1da177e4 5676
beb1fe18
HW		 5677static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5678{
5679 if (tp->csi_ops.write)
52989f0e 5680 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 5681}
5682
5683static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5684{
52989f0e 5685 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 5686}
5687
5688static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 5689{
5690 u32 csi;
5691
beb1fe18
HW		 5692 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5693 rtl_csi_write(tp, 0x070c, csi | bits);
5694}
5695
5696static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5697{
5698 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 5699}
5700
beb1fe18 5701static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 5702{
beb1fe18 5703 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 5704}
5705
ffc46952
FR		 5706DECLARE_RTL_COND(rtl_csiar_cond)
5707{
5708 void __iomem *ioaddr = tp->mmio_addr;
5709
5710 return RTL_R32(CSIAR) & CSIAR_FLAG;
5711}
5712
52989f0e 5713static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 5714{
52989f0e 5715 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5716
5717 RTL_W32(CSIDR, value);
5718 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5719 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5720
ffc46952 5721 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 5722}
5723
52989f0e 5724static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 5725{
52989f0e 5726 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5727
5728 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5729 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5730
ffc46952
FR		 5731 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5732 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 5733}
5734
52989f0e 5735static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 5736{
52989f0e 5737 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5738
5739 RTL_W32(CSIDR, value);
5740 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5741 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5742 CSIAR_FUNC_NIC);
5743
ffc46952 5744 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 5745}
5746
52989f0e 5747static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 5748{
52989f0e 5749 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5750
5751 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5752 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5753
ffc46952
FR		 5754 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5755 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 5756}
5757
45dd95c4 5758static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5759{
5760 void __iomem *ioaddr = tp->mmio_addr;
5761
5762 RTL_W32(CSIDR, value);
5763 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5764 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5765 CSIAR_FUNC_NIC2);
5766
5767 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5768}
5769
5770static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5771{
5772 void __iomem *ioaddr = tp->mmio_addr;
5773
5774 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5775 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5776
5777 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5778 RTL_R32(CSIDR) : ~0;
5779}
5780
baf63293 5781static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 5782{
5783 struct csi_ops *ops = &tp->csi_ops;
5784
5785 switch (tp->mac_version) {
5786 case RTL_GIGA_MAC_VER_01:
5787 case RTL_GIGA_MAC_VER_02:
5788 case RTL_GIGA_MAC_VER_03:
5789 case RTL_GIGA_MAC_VER_04:
5790 case RTL_GIGA_MAC_VER_05:
5791 case RTL_GIGA_MAC_VER_06:
5792 case RTL_GIGA_MAC_VER_10:
5793 case RTL_GIGA_MAC_VER_11:
5794 case RTL_GIGA_MAC_VER_12:
5795 case RTL_GIGA_MAC_VER_13:
5796 case RTL_GIGA_MAC_VER_14:
5797 case RTL_GIGA_MAC_VER_15:
5798 case RTL_GIGA_MAC_VER_16:
5799 case RTL_GIGA_MAC_VER_17:
5800 ops->write = NULL;
5801 ops->read = NULL;
5802 break;
5803
7e18dca1 5804 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 5805 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 5806 ops->write = r8402_csi_write;
5807 ops->read = r8402_csi_read;
5808 break;
5809
45dd95c4 5810 case RTL_GIGA_MAC_VER_44:
5811 ops->write = r8411_csi_write;
5812 ops->read = r8411_csi_read;
5813 break;
5814
beb1fe18
HW		 5815 default:
5816 ops->write = r8169_csi_write;
5817 ops->read = r8169_csi_read;
5818 break;
5819 }
dacf8154
FR		 5820}
5821
5822struct ephy_info {
5823 unsigned int offset;
5824 u16 mask;
5825 u16 bits;
5826};
5827
fdf6fc06
FR		 5828static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5829 int len)
dacf8154
FR		 5830{
5831 u16 w;
5832
5833 while (len-- > 0) {
fdf6fc06
FR		 5834 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5835 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 5836 e++;
5837 }
5838}
5839
b726e493
FR		 5840static void rtl_disable_clock_request(struct pci_dev *pdev)
5841{
7d7903b2
JL		 5842 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5843 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 5844}
5845
e6de30d6 5846static void rtl_enable_clock_request(struct pci_dev *pdev)
5847{
7d7903b2
JL		 5848 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5849 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 5850}
5851
b51ecea8 5852static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5853{
5854 void __iomem *ioaddr = tp->mmio_addr;
5855 u8 data;
5856
5857 data = RTL_R8(Config3);
5858
5859 if (enable)
5860 data |= Rdy_to_L23;
5861 else
5862 data &= ~Rdy_to_L23;
5863
5864 RTL_W8(Config3, data);
5865}
5866
b726e493
FR		 5867#define R8168_CPCMD_QUIRK_MASK (\
5868 EnableBist | \
5869 Mac_dbgo_oe | \
5870 Force_half_dup | \
5871 Force_rxflow_en | \
5872 Force_txflow_en | \
5873 Cxpl_dbg_sel | \
5874 ASF | \
5875 PktCntrDisable | \
5876 Mac_dbgo_sel)
5877
beb1fe18 5878static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 5879{
beb1fe18
HW		 5880 void __iomem *ioaddr = tp->mmio_addr;
5881 struct pci_dev *pdev = tp->pci_dev;
5882
b726e493
FR		 5883 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5884
5885 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5886
faf1e785 5887 if (tp->dev->mtu <= ETH_DATA_LEN) {
5888 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5889 PCI_EXP_DEVCTL_NOSNOOP_EN);
5890 }
219a1e9d
FR		 5891}
5892
beb1fe18 5893static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 5894{
beb1fe18
HW		 5895 void __iomem *ioaddr = tp->mmio_addr;
5896
5897 rtl_hw_start_8168bb(tp);
b726e493 5898
f0298f81 5899 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 5900
5901 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 5902}
5903
beb1fe18 5904static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 5905{
beb1fe18
HW		 5906 void __iomem *ioaddr = tp->mmio_addr;
5907 struct pci_dev *pdev = tp->pci_dev;
5908
b726e493
FR		 5909 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5910
5911 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5912
faf1e785 5913 if (tp->dev->mtu <= ETH_DATA_LEN)
5914 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 5915
5916 rtl_disable_clock_request(pdev);
5917
5918 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 5919}
5920
beb1fe18 5921static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 5922{
350f7596 5923 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 5924 { 0x01, 0, 0x0001 },
5925 { 0x02, 0x0800, 0x1000 },
5926 { 0x03, 0, 0x0042 },
5927 { 0x06, 0x0080, 0x0000 },
5928 { 0x07, 0, 0x2000 }
5929 };
5930
beb1fe18 5931 rtl_csi_access_enable_2(tp);
b726e493 5932
fdf6fc06 5933 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 5934
beb1fe18 5935 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5936}
5937
beb1fe18 5938static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 5939{
beb1fe18
HW		 5940 void __iomem *ioaddr = tp->mmio_addr;
5941 struct pci_dev *pdev = tp->pci_dev;
5942
5943 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 5944
5945 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5946
faf1e785 5947 if (tp->dev->mtu <= ETH_DATA_LEN)
5948 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
ef3386f0
FR		 5949
5950 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5951}
5952
beb1fe18 5953static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 5954{
beb1fe18
HW		 5955 void __iomem *ioaddr = tp->mmio_addr;
5956 struct pci_dev *pdev = tp->pci_dev;
5957
5958 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 5959
5960 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5961
5962 /* Magic. */
5963 RTL_W8(DBG_REG, 0x20);
5964
f0298f81 5965 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a 5966
faf1e785 5967 if (tp->dev->mtu <= ETH_DATA_LEN)
5968 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
7f3e3d3a
FR		 5969
5970 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5971}
5972
beb1fe18 5973static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 5974{
beb1fe18 5975 void __iomem *ioaddr = tp->mmio_addr;
350f7596 5976 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 5977 { 0x02, 0x0800, 0x1000 },
5978 { 0x03, 0, 0x0002 },
5979 { 0x06, 0x0080, 0x0000 }
5980 };
5981
beb1fe18 5982 rtl_csi_access_enable_2(tp);
b726e493
FR		 5983
5984 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5985
fdf6fc06 5986 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 5987
beb1fe18 5988 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5989}
5990
beb1fe18 5991static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 5992{
350f7596 5993 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 5994 { 0x01, 0, 0x0001 },
5995 { 0x03, 0x0400, 0x0220 }
5996 };
5997
beb1fe18 5998 rtl_csi_access_enable_2(tp);
b726e493 5999
fdf6fc06 6000 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 6001
beb1fe18 6002 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 6003}
6004
beb1fe18 6005static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 6006{
beb1fe18 6007 rtl_hw_start_8168c_2(tp);
197ff761
FR		 6008}
6009
beb1fe18 6010static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 6011{
beb1fe18 6012 rtl_csi_access_enable_2(tp);
6fb07058 6013
beb1fe18 6014 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 6015}
6016
beb1fe18 6017static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 6018{
beb1fe18
HW		 6019 void __iomem *ioaddr = tp->mmio_addr;
6020 struct pci_dev *pdev = tp->pci_dev;
6021
6022 rtl_csi_access_enable_2(tp);
5b538df9
FR		 6023
6024 rtl_disable_clock_request(pdev);
6025
f0298f81 6026 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9 6027
faf1e785 6028 if (tp->dev->mtu <= ETH_DATA_LEN)
6029 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5b538df9
FR		 6030
6031 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
6032}
6033
beb1fe18 6034static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 6035{
beb1fe18
HW		 6036 void __iomem *ioaddr = tp->mmio_addr;
6037 struct pci_dev *pdev = tp->pci_dev;
6038
6039 rtl_csi_access_enable_1(tp);
4804b3b3 6040
faf1e785 6041 if (tp->dev->mtu <= ETH_DATA_LEN)
6042 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804b3b3 6043
6044 RTL_W8(MaxTxPacketSize, TxPacketMax);
6045
6046 rtl_disable_clock_request(pdev);
6047}
6048
beb1fe18 6049static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 6050{
beb1fe18
HW		 6051 void __iomem *ioaddr = tp->mmio_addr;
6052 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 6053 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 6054 { 0x0b, 0x0000, 0x0048 },
6055 { 0x19, 0x0020, 0x0050 },
6056 { 0x0c, 0x0100, 0x0020 }
e6de30d6 6057 };
e6de30d6 6058
beb1fe18 6059 rtl_csi_access_enable_1(tp);
e6de30d6 6060
6061 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6062
6063 RTL_W8(MaxTxPacketSize, TxPacketMax);
6064
1016a4a1 6065 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
e6de30d6 6066
6067 rtl_enable_clock_request(pdev);
6068}
6069
beb1fe18 6070static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 6071{
beb1fe18
HW		 6072 void __iomem *ioaddr = tp->mmio_addr;
6073 struct pci_dev *pdev = tp->pci_dev;
70090424 6074 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 6075 { 0x00, 0x0200, 0x0100 },
6076 { 0x00, 0x0000, 0x0004 },
6077 { 0x06, 0x0002, 0x0001 },
6078 { 0x06, 0x0000, 0x0030 },
6079 { 0x07, 0x0000, 0x2000 },
6080 { 0x00, 0x0000, 0x0020 },
6081 { 0x03, 0x5800, 0x2000 },
6082 { 0x03, 0x0000, 0x0001 },
6083 { 0x01, 0x0800, 0x1000 },
6084 { 0x07, 0x0000, 0x4000 },
6085 { 0x1e, 0x0000, 0x2000 },
6086 { 0x19, 0xffff, 0xfe6c },
6087 { 0x0a, 0x0000, 0x0040 }
6088 };
6089
beb1fe18 6090 rtl_csi_access_enable_2(tp);
01dc7fec 6091
fdf6fc06 6092 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 6093
faf1e785 6094 if (tp->dev->mtu <= ETH_DATA_LEN)
6095 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
01dc7fec 6096
6097 RTL_W8(MaxTxPacketSize, TxPacketMax);
6098
6099 rtl_disable_clock_request(pdev);
6100
6101 /* Reset tx FIFO pointer */
cecb5fd7
FR		 6102 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
6103 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 6104
cecb5fd7 6105 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 6106}
6107
beb1fe18 6108static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 6109{
beb1fe18
HW		 6110 void __iomem *ioaddr = tp->mmio_addr;
6111 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 6112 static const struct ephy_info e_info_8168e_2[] = {
6113 { 0x09, 0x0000, 0x0080 },
6114 { 0x19, 0x0000, 0x0224 }
6115 };
6116
beb1fe18 6117 rtl_csi_access_enable_1(tp);
70090424 6118
fdf6fc06 6119 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 6120
faf1e785 6121 if (tp->dev->mtu <= ETH_DATA_LEN)
6122 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
70090424 6123
fdf6fc06
FR		 6124 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6125 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6126 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
6127 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6128 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
6129 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 6130 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
6131 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 6132
3090bd9a 6133 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 6134
4521e1a9
FR		 6135 rtl_disable_clock_request(pdev);
6136
70090424
HW		 6137 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6138 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6139
6140 /* Adjust EEE LED frequency */
6141 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6142
6143 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6144 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4521e1a9 6145 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
70090424
HW		 6146}
6147
5f886e08 6148static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 6149{
beb1fe18
HW		 6150 void __iomem *ioaddr = tp->mmio_addr;
6151 struct pci_dev *pdev = tp->pci_dev;
c2218925 6152
5f886e08 6153 rtl_csi_access_enable_2(tp);
c2218925
HW		 6154
6155 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6156
fdf6fc06
FR		 6157 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6158 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6159 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
6160 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 6161 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6162 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6163 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
6164 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 6165 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
6166 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 6167
6168 RTL_W8(MaxTxPacketSize, EarlySize);
6169
4521e1a9
FR		 6170 rtl_disable_clock_request(pdev);
6171
c2218925
HW		 6172 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6173 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 6174 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4521e1a9
FR		 6175 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
6176 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
c2218925
HW		 6177}
6178
5f886e08
HW		 6179static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
6180{
6181 void __iomem *ioaddr = tp->mmio_addr;
6182 static const struct ephy_info e_info_8168f_1[] = {
6183 { 0x06, 0x00c0, 0x0020 },
6184 { 0x08, 0x0001, 0x0002 },
6185 { 0x09, 0x0000, 0x0080 },
6186 { 0x19, 0x0000, 0x0224 }
6187 };
6188
6189 rtl_hw_start_8168f(tp);
6190
fdf6fc06 6191 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 6192
706123d0 6193 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 6194
6195 /* Adjust EEE LED frequency */
6196 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6197}
6198
b3d7b2f2
HW		 6199static void rtl_hw_start_8411(struct rtl8169_private *tp)
6200{
b3d7b2f2
HW		 6201 static const struct ephy_info e_info_8168f_1[] = {
6202 { 0x06, 0x00c0, 0x0020 },
6203 { 0x0f, 0xffff, 0x5200 },
6204 { 0x1e, 0x0000, 0x4000 },
6205 { 0x19, 0x0000, 0x0224 }
6206 };
6207
6208 rtl_hw_start_8168f(tp);
b51ecea8 6209 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 6210
fdf6fc06 6211 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 6212
706123d0 6213 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 6214}
6215
5fbea337 6216static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b
HW		 6217{
6218 void __iomem *ioaddr = tp->mmio_addr;
6219 struct pci_dev *pdev = tp->pci_dev;
6220
beb330a4 6221 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6222
c558386b
HW		 6223 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6224 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6225 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6226 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6227
6228 rtl_csi_access_enable_1(tp);
6229
6230 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6231
706123d0
CHL		 6232 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6233 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 6234 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 6235
4521e1a9 6236 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
c558386b
HW		 6237 RTL_W8(MaxTxPacketSize, EarlySize);
6238
6239 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6240 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6241
6242 /* Adjust EEE LED frequency */
6243 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6244
706123d0
CHL		 6245 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6246 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 6247
6248 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 6249}
6250
5fbea337
CHL		 6251static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6252{
6253 void __iomem *ioaddr = tp->mmio_addr;
6254 static const struct ephy_info e_info_8168g_1[] = {
6255 { 0x00, 0x0000, 0x0008 },
6256 { 0x0c, 0x37d0, 0x0820 },
6257 { 0x1e, 0x0000, 0x0001 },
6258 { 0x19, 0x8000, 0x0000 }
6259 };
6260
6261 rtl_hw_start_8168g(tp);
6262
6263 /* disable aspm and clock request before access ephy */
6264 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6265 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6266 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6267}
6268
57538c4a 6269static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6270{
6271 void __iomem *ioaddr = tp->mmio_addr;
6272 static const struct ephy_info e_info_8168g_2[] = {
6273 { 0x00, 0x0000, 0x0008 },
6274 { 0x0c, 0x3df0, 0x0200 },
6275 { 0x19, 0xffff, 0xfc00 },
6276 { 0x1e, 0xffff, 0x20eb }
6277 };
6278
5fbea337 6279 rtl_hw_start_8168g(tp);
57538c4a 6280
6281 /* disable aspm and clock request before access ephy */
6282 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6283 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6284 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6285}
6286
45dd95c4 6287static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6288{
6289 void __iomem *ioaddr = tp->mmio_addr;
6290 static const struct ephy_info e_info_8411_2[] = {
6291 { 0x00, 0x0000, 0x0008 },
6292 { 0x0c, 0x3df0, 0x0200 },
6293 { 0x0f, 0xffff, 0x5200 },
6294 { 0x19, 0x0020, 0x0000 },
6295 { 0x1e, 0x0000, 0x2000 }
6296 };
6297
5fbea337 6298 rtl_hw_start_8168g(tp);
45dd95c4 6299
6300 /* disable aspm and clock request before access ephy */
6301 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6302 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6303 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6304}
6305
6e1d0b89
CHL		 6306static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6307{
6308 void __iomem *ioaddr = tp->mmio_addr;
6309 struct pci_dev *pdev = tp->pci_dev;
72521ea0 6310 int rg_saw_cnt;
6e1d0b89
CHL		 6311 u32 data;
6312 static const struct ephy_info e_info_8168h_1[] = {
6313 { 0x1e, 0x0800, 0x0001 },
6314 { 0x1d, 0x0000, 0x0800 },
6315 { 0x05, 0xffff, 0x2089 },
6316 { 0x06, 0xffff, 0x5881 },
6317 { 0x04, 0xffff, 0x154a },
6318 { 0x01, 0xffff, 0x068b }
6319 };
6320
6321 /* disable aspm and clock request before access ephy */
6322 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6323 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6324 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6325
6326 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6327
6328 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6329 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6330 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6331 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6332
6333 rtl_csi_access_enable_1(tp);
6334
6335 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6336
706123d0
CHL		 6337 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6338 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 6339
706123d0 6340 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 6341
706123d0 6342 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 6343
6344 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6345
6e1d0b89
CHL		 6346 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6347 RTL_W8(MaxTxPacketSize, EarlySize);
6348
6349 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6350 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6351
6352 /* Adjust EEE LED frequency */
6353 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6354
6355 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6356 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89
CHL		 6357
6358 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6359
706123d0 6360 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 6361
6362 rtl_pcie_state_l2l3_enable(tp, false);
6363
6364 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 6365 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 6366 rtl_writephy(tp, 0x1f, 0x0000);
6367 if (rg_saw_cnt > 0) {
6368 u16 sw_cnt_1ms_ini;
6369
6370 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6371 sw_cnt_1ms_ini &= 0x0fff;
6372 data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec0 6373 data &= ~0x0fff;
6e1d0b89
CHL		 6374 data |= sw_cnt_1ms_ini;
6375 r8168_mac_ocp_write(tp, 0xd412, data);
6376 }
6377
6378 data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec0
CHL		 6379 data &= ~0xf0;
6380 data |= 0x70;
6e1d0b89
CHL		 6381 r8168_mac_ocp_write(tp, 0xe056, data);
6382
6383 data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec0
CHL		 6384 data &= ~0x6000;
6385 data |= 0x8008;
6e1d0b89
CHL		 6386 r8168_mac_ocp_write(tp, 0xe052, data);
6387
6388 data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec0 6389 data &= ~0x01ff;
6e1d0b89
CHL		 6390 data |= 0x017f;
6391 r8168_mac_ocp_write(tp, 0xe0d6, data);
6392
6393 data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec0 6394 data &= ~0x0fff;
6e1d0b89
CHL		 6395 data |= 0x047f;
6396 r8168_mac_ocp_write(tp, 0xd420, data);
6397
6398 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6399 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6400 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6401 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6402}
6403
935e2218
CHL		 6404static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6405{
6406 void __iomem *ioaddr = tp->mmio_addr;
6407 struct pci_dev *pdev = tp->pci_dev;
6408
003609da
CHL		 6409 rtl8168ep_stop_cmac(tp);
6410
935e2218
CHL		 6411 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6412
6413 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6414 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6415 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6416 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6417
6418 rtl_csi_access_enable_1(tp);
6419
6420 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6421
6422 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6423 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6424
6425 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6426
6427 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6428
935e2218
CHL		 6429 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6430 RTL_W8(MaxTxPacketSize, EarlySize);
6431
6432 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6433 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6434
6435 /* Adjust EEE LED frequency */
6436 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6437
6438 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6439
6440 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6441
6442 rtl_pcie_state_l2l3_enable(tp, false);
6443}
6444
6445static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6446{
6447 void __iomem *ioaddr = tp->mmio_addr;
6448 static const struct ephy_info e_info_8168ep_1[] = {
6449 { 0x00, 0xffff, 0x10ab },
6450 { 0x06, 0xffff, 0xf030 },
6451 { 0x08, 0xffff, 0x2006 },
6452 { 0x0d, 0xffff, 0x1666 },
6453 { 0x0c, 0x3ff0, 0x0000 }
6454 };
6455
6456 /* disable aspm and clock request before access ephy */
6457 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6458 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6459 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6460
6461 rtl_hw_start_8168ep(tp);
6462}
6463
6464static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6465{
6466 void __iomem *ioaddr = tp->mmio_addr;
6467 static const struct ephy_info e_info_8168ep_2[] = {
6468 { 0x00, 0xffff, 0x10a3 },
6469 { 0x19, 0xffff, 0xfc00 },
6470 { 0x1e, 0xffff, 0x20ea }
6471 };
6472
6473 /* disable aspm and clock request before access ephy */
6474 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6475 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6476 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6477
6478 rtl_hw_start_8168ep(tp);
6479
6480 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6481 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 6482}
6483
6484static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6485{
6486 void __iomem *ioaddr = tp->mmio_addr;
6487 u32 data;
6488 static const struct ephy_info e_info_8168ep_3[] = {
6489 { 0x00, 0xffff, 0x10a3 },
6490 { 0x19, 0xffff, 0x7c00 },
6491 { 0x1e, 0xffff, 0x20eb },
6492 { 0x0d, 0xffff, 0x1666 }
6493 };
6494
6495 /* disable aspm and clock request before access ephy */
6496 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6497 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6498 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6499
6500 rtl_hw_start_8168ep(tp);
6501
6502 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6503 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 6504
6505 data = r8168_mac_ocp_read(tp, 0xd3e2);
6506 data &= 0xf000;
6507 data |= 0x0271;
6508 r8168_mac_ocp_write(tp, 0xd3e2, data);
6509
6510 data = r8168_mac_ocp_read(tp, 0xd3e4);
6511 data &= 0xff00;
6512 r8168_mac_ocp_write(tp, 0xd3e4, data);
6513
6514 data = r8168_mac_ocp_read(tp, 0xe860);
6515 data |= 0x0080;
6516 r8168_mac_ocp_write(tp, 0xe860, data);
6517}
6518
07ce4064
FR		 6519static void rtl_hw_start_8168(struct net_device *dev)
6520{
2dd99530
FR		 6521 struct rtl8169_private *tp = netdev_priv(dev);
6522 void __iomem *ioaddr = tp->mmio_addr;
6523
6524 RTL_W8(Cfg9346, Cfg9346_Unlock);
6525
f0298f81 6526 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 6527
6f0333b8 6528 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 6529
0e485150 6530 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 6531
6532 RTL_W16(CPlusCmd, tp->cp_cmd);
6533
0e485150 6534 RTL_W16(IntrMitigate, 0x5151);
2dd99530 6535
0e485150 6536 /* Work around for RxFIFO overflow. */
811fd301 6537 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 6538 tp->event_slow |= RxFIFOOver | PCSTimeout;
6539 tp->event_slow &= ~RxOverflow;
0e485150
FR		 6540 }
6541
6542 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 6543
1a964649 6544 rtl_set_rx_tx_config_registers(tp);
2dd99530
FR		 6545
6546 RTL_R8(IntrMask);
6547
219a1e9d
FR		 6548 switch (tp->mac_version) {
6549 case RTL_GIGA_MAC_VER_11:
beb1fe18 6550 rtl_hw_start_8168bb(tp);
4804b3b3 6551 break;
219a1e9d
FR		 6552
6553 case RTL_GIGA_MAC_VER_12:
6554 case RTL_GIGA_MAC_VER_17:
beb1fe18 6555 rtl_hw_start_8168bef(tp);
4804b3b3 6556 break;
219a1e9d
FR		 6557
6558 case RTL_GIGA_MAC_VER_18:
beb1fe18 6559 rtl_hw_start_8168cp_1(tp);
4804b3b3 6560 break;
219a1e9d
FR		 6561
6562 case RTL_GIGA_MAC_VER_19:
beb1fe18 6563 rtl_hw_start_8168c_1(tp);
4804b3b3 6564 break;
219a1e9d
FR		 6565
6566 case RTL_GIGA_MAC_VER_20:
beb1fe18 6567 rtl_hw_start_8168c_2(tp);
4804b3b3 6568 break;
219a1e9d 6569
197ff761 6570 case RTL_GIGA_MAC_VER_21:
beb1fe18 6571 rtl_hw_start_8168c_3(tp);
4804b3b3 6572 break;
197ff761 6573
6fb07058 6574 case RTL_GIGA_MAC_VER_22:
beb1fe18 6575 rtl_hw_start_8168c_4(tp);
4804b3b3 6576 break;
6fb07058 6577
ef3386f0 6578 case RTL_GIGA_MAC_VER_23:
beb1fe18 6579 rtl_hw_start_8168cp_2(tp);
4804b3b3 6580 break;
ef3386f0 6581
7f3e3d3a 6582 case RTL_GIGA_MAC_VER_24:
beb1fe18 6583 rtl_hw_start_8168cp_3(tp);
4804b3b3 6584 break;
7f3e3d3a 6585
5b538df9 6586 case RTL_GIGA_MAC_VER_25:
daf9df6d 6587 case RTL_GIGA_MAC_VER_26:
6588 case RTL_GIGA_MAC_VER_27:
beb1fe18 6589 rtl_hw_start_8168d(tp);
4804b3b3 6590 break;
5b538df9 6591
e6de30d6 6592 case RTL_GIGA_MAC_VER_28:
beb1fe18 6593 rtl_hw_start_8168d_4(tp);
4804b3b3 6594 break;
cecb5fd7 6595
4804b3b3 6596 case RTL_GIGA_MAC_VER_31:
beb1fe18 6597 rtl_hw_start_8168dp(tp);
4804b3b3 6598 break;
6599
01dc7fec 6600 case RTL_GIGA_MAC_VER_32:
6601 case RTL_GIGA_MAC_VER_33:
beb1fe18 6602 rtl_hw_start_8168e_1(tp);
70090424
HW		 6603 break;
6604 case RTL_GIGA_MAC_VER_34:
beb1fe18 6605 rtl_hw_start_8168e_2(tp);
01dc7fec 6606 break;
e6de30d6 6607
c2218925
HW		 6608 case RTL_GIGA_MAC_VER_35:
6609 case RTL_GIGA_MAC_VER_36:
beb1fe18 6610 rtl_hw_start_8168f_1(tp);
c2218925
HW		 6611 break;
6612
b3d7b2f2
HW		 6613 case RTL_GIGA_MAC_VER_38:
6614 rtl_hw_start_8411(tp);
6615 break;
6616
c558386b
HW		 6617 case RTL_GIGA_MAC_VER_40:
6618 case RTL_GIGA_MAC_VER_41:
6619 rtl_hw_start_8168g_1(tp);
6620 break;
57538c4a 6621 case RTL_GIGA_MAC_VER_42:
6622 rtl_hw_start_8168g_2(tp);
6623 break;
c558386b 6624
45dd95c4 6625 case RTL_GIGA_MAC_VER_44:
6626 rtl_hw_start_8411_2(tp);
6627 break;
6628
6e1d0b89
CHL		 6629 case RTL_GIGA_MAC_VER_45:
6630 case RTL_GIGA_MAC_VER_46:
6631 rtl_hw_start_8168h_1(tp);
6632 break;
6633
935e2218
CHL		 6634 case RTL_GIGA_MAC_VER_49:
6635 rtl_hw_start_8168ep_1(tp);
6636 break;
6637
6638 case RTL_GIGA_MAC_VER_50:
6639 rtl_hw_start_8168ep_2(tp);
6640 break;
6641
6642 case RTL_GIGA_MAC_VER_51:
6643 rtl_hw_start_8168ep_3(tp);
6644 break;
6645
219a1e9d
FR		 6646 default:
6647 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6648 dev->name, tp->mac_version);
4804b3b3 6649 break;
219a1e9d 6650 }
2dd99530 6651
1a964649 6652 RTL_W8(Cfg9346, Cfg9346_Lock);
6653
0e485150
FR		 6654 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6655
1a964649 6656 rtl_set_rx_mode(dev);
b8363901 6657
05b9687b 6658 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 6659}
1da177e4 6660
2857ffb7
FR		 6661#define R810X_CPCMD_QUIRK_MASK (\
6662 EnableBist | \
6663 Mac_dbgo_oe | \
6664 Force_half_dup | \
5edcc537 6665 Force_rxflow_en | \
2857ffb7
FR		 6666 Force_txflow_en | \
6667 Cxpl_dbg_sel | \
6668 ASF | \
6669 PktCntrDisable | \
d24e9aaf 6670 Mac_dbgo_sel)
2857ffb7 6671
beb1fe18 6672static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 6673{
beb1fe18
HW		 6674 void __iomem *ioaddr = tp->mmio_addr;
6675 struct pci_dev *pdev = tp->pci_dev;
350f7596 6676 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 6677 { 0x01, 0, 0x6e65 },
6678 { 0x02, 0, 0x091f },
6679 { 0x03, 0, 0xc2f9 },
6680 { 0x06, 0, 0xafb5 },
6681 { 0x07, 0, 0x0e00 },
6682 { 0x19, 0, 0xec80 },
6683 { 0x01, 0, 0x2e65 },
6684 { 0x01, 0, 0x6e65 }
6685 };
6686 u8 cfg1;
6687
beb1fe18 6688 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 6689
6690 RTL_W8(DBG_REG, FIX_NAK_1);
6691
6692 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6693
6694 RTL_W8(Config1,
6695 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6696 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6697
6698 cfg1 = RTL_R8(Config1);
6699 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6700 RTL_W8(Config1, cfg1 & ~LEDS0);
6701
fdf6fc06 6702 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 6703}
6704
beb1fe18 6705static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 6706{
beb1fe18
HW		 6707 void __iomem *ioaddr = tp->mmio_addr;
6708 struct pci_dev *pdev = tp->pci_dev;
6709
6710 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 6711
6712 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6713
6714 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6715 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 6716}
6717
beb1fe18 6718static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 6719{
beb1fe18 6720 rtl_hw_start_8102e_2(tp);
2857ffb7 6721
fdf6fc06 6722 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 6723}
6724
beb1fe18 6725static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 6726{
beb1fe18 6727 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 6728 static const struct ephy_info e_info_8105e_1[] = {
6729 { 0x07, 0, 0x4000 },
6730 { 0x19, 0, 0x0200 },
6731 { 0x19, 0, 0x0020 },
6732 { 0x1e, 0, 0x2000 },
6733 { 0x03, 0, 0x0001 },
6734 { 0x19, 0, 0x0100 },
6735 { 0x19, 0, 0x0004 },
6736 { 0x0a, 0, 0x0020 }
6737 };
6738
cecb5fd7 6739 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 6740 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6741
cecb5fd7 6742 /* Disable Early Tally Counter */
5a5e4443
HW		 6743 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6744
6745 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 6746 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 6747
fdf6fc06 6748 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 6749
6750 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 6751}
6752
beb1fe18 6753static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 6754{
beb1fe18 6755 rtl_hw_start_8105e_1(tp);
fdf6fc06 6756 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 6757}
6758
7e18dca1
HW		 6759static void rtl_hw_start_8402(struct rtl8169_private *tp)
6760{
6761 void __iomem *ioaddr = tp->mmio_addr;
6762 static const struct ephy_info e_info_8402[] = {
6763 { 0x19, 0xffff, 0xff64 },
6764 { 0x1e, 0, 0x4000 }
6765 };
6766
6767 rtl_csi_access_enable_2(tp);
6768
6769 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6770 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6771
6772 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6773 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6774
fdf6fc06 6775 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 6776
6777 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6778
fdf6fc06
FR		 6779 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6780 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 6781 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6782 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 6783 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6784 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 6785 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 6786
6787 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 6788}
6789
5598bfe5
HW		 6790static void rtl_hw_start_8106(struct rtl8169_private *tp)
6791{
6792 void __iomem *ioaddr = tp->mmio_addr;
6793
6794 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6795 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6796
4521e1a9 6797 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5598bfe5
HW		 6798 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6799 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
b51ecea8 6800
6801 rtl_pcie_state_l2l3_enable(tp, false);
5598bfe5
HW		 6802}
6803
07ce4064
FR		 6804static void rtl_hw_start_8101(struct net_device *dev)
6805{
cdf1a608
FR		 6806 struct rtl8169_private *tp = netdev_priv(dev);
6807 void __iomem *ioaddr = tp->mmio_addr;
6808 struct pci_dev *pdev = tp->pci_dev;
6809
da78dbff
FR		 6810 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6811 tp->event_slow &= ~RxFIFOOver;
811fd301 6812
cecb5fd7 6813 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 6814 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 6815 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6816 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 6817
d24e9aaf
HW		 6818 RTL_W8(Cfg9346, Cfg9346_Unlock);
6819
1a964649 6820 RTL_W8(MaxTxPacketSize, TxPacketMax);
6821
6822 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6823
6824 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6825 RTL_W16(CPlusCmd, tp->cp_cmd);
6826
6827 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6828
6829 rtl_set_rx_tx_config_registers(tp);
6830
2857ffb7
FR		 6831 switch (tp->mac_version) {
6832 case RTL_GIGA_MAC_VER_07:
beb1fe18 6833 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 6834 break;
6835
6836 case RTL_GIGA_MAC_VER_08:
beb1fe18 6837 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 6838 break;
6839
6840 case RTL_GIGA_MAC_VER_09:
beb1fe18 6841 rtl_hw_start_8102e_2(tp);
2857ffb7 6842 break;
5a5e4443
HW		 6843
6844 case RTL_GIGA_MAC_VER_29:
beb1fe18 6845 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 6846 break;
6847 case RTL_GIGA_MAC_VER_30:
beb1fe18 6848 rtl_hw_start_8105e_2(tp);
5a5e4443 6849 break;
7e18dca1
HW		 6850
6851 case RTL_GIGA_MAC_VER_37:
6852 rtl_hw_start_8402(tp);
6853 break;
5598bfe5
HW		 6854
6855 case RTL_GIGA_MAC_VER_39:
6856 rtl_hw_start_8106(tp);
6857 break;
58152cd4 6858 case RTL_GIGA_MAC_VER_43:
6859 rtl_hw_start_8168g_2(tp);
6860 break;
6e1d0b89
CHL		 6861 case RTL_GIGA_MAC_VER_47:
6862 case RTL_GIGA_MAC_VER_48:
6863 rtl_hw_start_8168h_1(tp);
6864 break;
cdf1a608
FR		 6865 }
6866
d24e9aaf 6867 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 6868
cdf1a608
FR		 6869 RTL_W16(IntrMitigate, 0x0000);
6870
cdf1a608 6871 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
cdf1a608 6872
cdf1a608
FR		 6873 rtl_set_rx_mode(dev);
6874
1a964649 6875 RTL_R8(IntrMask);
6876
cdf1a608 6877 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 6878}
6879
6880static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6881{
d58d46b5
FR		 6882 struct rtl8169_private *tp = netdev_priv(dev);
6883
d58d46b5
FR		 6884 if (new_mtu > ETH_DATA_LEN)
6885 rtl_hw_jumbo_enable(tp);
6886 else
6887 rtl_hw_jumbo_disable(tp);
6888
1da177e4 6889 dev->mtu = new_mtu;
350fb32a
MM		 6890 netdev_update_features(dev);
6891
323bb685 6892 return 0;
1da177e4
LT		 6893}
6894
6895static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6896{
95e0918d 6897 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 6898 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6899}
6900
6f0333b8
ED		 6901static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6902 void **data_buff, struct RxDesc *desc)
1da177e4 6903{
48addcc9 6904 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 6905 DMA_FROM_DEVICE);
48addcc9 6906
6f0333b8
ED		 6907 kfree(*data_buff);
6908 *data_buff = NULL;
1da177e4
LT		 6909 rtl8169_make_unusable_by_asic(desc);
6910}
6911
6912static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6913{
6914 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6915
a0750138
AD		 6916 /* Force memory writes to complete before releasing descriptor */
6917 dma_wmb();
6918
1da177e4
LT		 6919 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6920}
6921
6922static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6923 u32 rx_buf_sz)
6924{
6925 desc->addr = cpu_to_le64(mapping);
1da177e4
LT		 6926 rtl8169_mark_to_asic(desc, rx_buf_sz);
6927}
6928
6f0333b8
ED		 6929static inline void *rtl8169_align(void *data)
6930{
6931 return (void *)ALIGN((long)data, 16);
6932}
6933
0ecbe1ca
SG		 6934static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6935 struct RxDesc *desc)
1da177e4 6936{
6f0333b8 6937 void *data;
1da177e4 6938 dma_addr_t mapping;
48addcc9 6939 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 6940 struct net_device *dev = tp->dev;
6f0333b8 6941 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 6942
6f0333b8
ED		 6943 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6944 if (!data)
6945 return NULL;
e9f63f30 6946
6f0333b8
ED		 6947 if (rtl8169_align(data) != data) {
6948 kfree(data);
6949 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6950 if (!data)
6951 return NULL;
6952 }
3eafe507 6953
48addcc9 6954 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 6955 DMA_FROM_DEVICE);
d827d86b
SG		 6956 if (unlikely(dma_mapping_error(d, mapping))) {
6957 if (net_ratelimit())
6958 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 6959 goto err_out;
d827d86b 6960 }
1da177e4
LT		 6961
6962 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 6963 return data;
3eafe507
SG		 6964
6965err_out:
6966 kfree(data);
6967 return NULL;
1da177e4
LT		 6968}
6969
6970static void rtl8169_rx_clear(struct rtl8169_private *tp)
6971{
07d3f51f 6972 unsigned int i;
1da177e4
LT		 6973
6974 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 6975 if (tp->Rx_databuff[i]) {
6976 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 6977 tp->RxDescArray + i);
6978 }
6979 }
6980}
6981
0ecbe1ca 6982static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 6983{
0ecbe1ca
SG		 6984 desc->opts1 |= cpu_to_le32(RingEnd);
6985}
5b0384f4 6986
0ecbe1ca
SG		 6987static int rtl8169_rx_fill(struct rtl8169_private *tp)
6988{
6989 unsigned int i;
1da177e4 6990
0ecbe1ca
SG		 6991 for (i = 0; i < NUM_RX_DESC; i++) {
6992 void *data;
4ae47c2d 6993
6f0333b8 6994 if (tp->Rx_databuff[i])
1da177e4 6995 continue;
bcf0bf90 6996
0ecbe1ca 6997 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 6998 if (!data) {
6999 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 7000 goto err_out;
6f0333b8
ED		 7001 }
7002 tp->Rx_databuff[i] = data;
1da177e4 7003 }
1da177e4 7004
0ecbe1ca
SG		 7005 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
7006 return 0;
7007
7008err_out:
7009 rtl8169_rx_clear(tp);
7010 return -ENOMEM;
1da177e4
LT		 7011}
7012
1da177e4
LT		 7013static int rtl8169_init_ring(struct net_device *dev)
7014{
7015 struct rtl8169_private *tp = netdev_priv(dev);
7016
7017 rtl8169_init_ring_indexes(tp);
7018
7019 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 7020 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 7021
0ecbe1ca 7022 return rtl8169_rx_fill(tp);
1da177e4
LT		 7023}
7024
48addcc9 7025static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 7026 struct TxDesc *desc)
7027{
7028 unsigned int len = tx_skb->len;
7029
48addcc9
SG		 7030 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
7031
1da177e4
LT		 7032 desc->opts1 = 0x00;
7033 desc->opts2 = 0x00;
7034 desc->addr = 0x00;
7035 tx_skb->len = 0;
7036}
7037
3eafe507
SG		 7038static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
7039 unsigned int n)
1da177e4
LT		 7040{
7041 unsigned int i;
7042
3eafe507
SG		 7043 for (i = 0; i < n; i++) {
7044 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 7045 struct ring_info *tx_skb = tp->tx_skb + entry;
7046 unsigned int len = tx_skb->len;
7047
7048 if (len) {
7049 struct sk_buff *skb = tx_skb->skb;
7050
48addcc9 7051 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 7052 tp->TxDescArray + entry);
7053 if (skb) {
7a4b813c 7054 dev_consume_skb_any(skb);
1da177e4
LT		 7055 tx_skb->skb = NULL;
7056 }
1da177e4
LT		 7057 }
7058 }
3eafe507
SG		 7059}
7060
7061static void rtl8169_tx_clear(struct rtl8169_private *tp)
7062{
7063 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 7064 tp->cur_tx = tp->dirty_tx = 0;
7065}
7066
4422bcd4 7067static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 7068{
c4028958 7069 struct net_device *dev = tp->dev;
56de414c 7070 int i;
1da177e4 7071
da78dbff
FR		 7072 napi_disable(&tp->napi);
7073 netif_stop_queue(dev);
7074 synchronize_sched();
1da177e4 7075
c7c2c39b 7076 rtl8169_hw_reset(tp);
7077
56de414c
FR		 7078 for (i = 0; i < NUM_RX_DESC; i++)
7079 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
7080
1da177e4 7081 rtl8169_tx_clear(tp);
c7c2c39b 7082 rtl8169_init_ring_indexes(tp);
1da177e4 7083
da78dbff 7084 napi_enable(&tp->napi);
56de414c
FR		 7085 rtl_hw_start(dev);
7086 netif_wake_queue(dev);
7087 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 7088}
7089
7090static void rtl8169_tx_timeout(struct net_device *dev)
7091{
da78dbff
FR		 7092 struct rtl8169_private *tp = netdev_priv(dev);
7093
7094 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 7095}
7096
7097static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 7098 u32 *opts)
1da177e4
LT		 7099{
7100 struct skb_shared_info *info = skb_shinfo(skb);
7101 unsigned int cur_frag, entry;
6e1d0b89 7102 struct TxDesc *uninitialized_var(txd);
48addcc9 7103 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 7104
7105 entry = tp->cur_tx;
7106 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 7107 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 7108 dma_addr_t mapping;
7109 u32 status, len;
7110 void *addr;
7111
7112 entry = (entry + 1) % NUM_TX_DESC;
7113
7114 txd = tp->TxDescArray + entry;
9e903e08 7115 len = skb_frag_size(frag);
929f6189 7116 addr = skb_frag_address(frag);
48addcc9 7117 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 7118 if (unlikely(dma_mapping_error(d, mapping))) {
7119 if (net_ratelimit())
7120 netif_err(tp, drv, tp->dev,
7121 "Failed to map TX fragments DMA!\n");
3eafe507 7122 goto err_out;
d827d86b 7123 }
1da177e4 7124
cecb5fd7 7125 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 7126 status = opts[0] | len |
7127 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 7128
7129 txd->opts1 = cpu_to_le32(status);
2b7b4318 7130 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 7131 txd->addr = cpu_to_le64(mapping);
7132
7133 tp->tx_skb[entry].len = len;
7134 }
7135
7136 if (cur_frag) {
7137 tp->tx_skb[entry].skb = skb;
7138 txd->opts1 |= cpu_to_le32(LastFrag);
7139 }
7140
7141 return cur_frag;
3eafe507
SG		 7142
7143err_out:
7144 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
7145 return -EIO;
1da177e4
LT		 7146}
7147
b423e9ae 7148static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
7149{
7150 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
7151}
7152
e974604b 7153static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7154 struct net_device *dev);
7155/* r8169_csum_workaround()
7156 * The hw limites the value the transport offset. When the offset is out of the
7157 * range, calculate the checksum by sw.
7158 */
7159static void r8169_csum_workaround(struct rtl8169_private *tp,
7160 struct sk_buff *skb)
7161{
7162 if (skb_shinfo(skb)->gso_size) {
7163 netdev_features_t features = tp->dev->features;
7164 struct sk_buff *segs, *nskb;
7165
7166 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
7167 segs = skb_gso_segment(skb, features);
7168 if (IS_ERR(segs) || !segs)
7169 goto drop;
7170
7171 do {
7172 nskb = segs;
7173 segs = segs->next;
7174 nskb->next = NULL;
7175 rtl8169_start_xmit(nskb, tp->dev);
7176 } while (segs);
7177
eb781397 7178 dev_consume_skb_any(skb);
e974604b 7179 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7180 if (skb_checksum_help(skb) < 0)
7181 goto drop;
7182
7183 rtl8169_start_xmit(skb, tp->dev);
7184 } else {
7185 struct net_device_stats *stats;
7186
7187drop:
7188 stats = &tp->dev->stats;
7189 stats->tx_dropped++;
eb781397 7190 dev_kfree_skb_any(skb);
e974604b 7191 }
7192}
7193
7194/* msdn_giant_send_check()
7195 * According to the document of microsoft, the TCP Pseudo Header excludes the
7196 * packet length for IPv6 TCP large packets.
7197 */
7198static int msdn_giant_send_check(struct sk_buff *skb)
7199{
7200 const struct ipv6hdr *ipv6h;
7201 struct tcphdr *th;
7202 int ret;
7203
7204 ret = skb_cow_head(skb, 0);
7205 if (ret)
7206 return ret;
7207
7208 ipv6h = ipv6_hdr(skb);
7209 th = tcp_hdr(skb);
7210
7211 th->check = 0;
7212 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7213
7214 return ret;
7215}
7216
7217static inline __be16 get_protocol(struct sk_buff *skb)
7218{
7219 __be16 protocol;
7220
7221 if (skb->protocol == htons(ETH_P_8021Q))
7222 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7223 else
7224 protocol = skb->protocol;
7225
7226 return protocol;
7227}
7228
5888d3fc 7229static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7230 struct sk_buff *skb, u32 *opts)
1da177e4 7231{
350fb32a
MM		 7232 u32 mss = skb_shinfo(skb)->gso_size;
7233
2b7b4318
FR		 7234 if (mss) {
7235 opts[0] |= TD_LSO;
5888d3fc 7236 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7237 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7238 const struct iphdr *ip = ip_hdr(skb);
7239
7240 if (ip->protocol == IPPROTO_TCP)
7241 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7242 else if (ip->protocol == IPPROTO_UDP)
7243 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7244 else
7245 WARN_ON_ONCE(1);
7246 }
7247
7248 return true;
7249}
7250
7251static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7252 struct sk_buff *skb, u32 *opts)
7253{
bdfa4ed6 7254 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 7255 u32 mss = skb_shinfo(skb)->gso_size;
7256
7257 if (mss) {
e974604b 7258 if (transport_offset > GTTCPHO_MAX) {
7259 netif_warn(tp, tx_err, tp->dev,
7260 "Invalid transport offset 0x%x for TSO\n",
7261 transport_offset);
7262 return false;
7263 }
7264
7265 switch (get_protocol(skb)) {
7266 case htons(ETH_P_IP):
7267 opts[0] |= TD1_GTSENV4;
7268 break;
7269
7270 case htons(ETH_P_IPV6):
7271 if (msdn_giant_send_check(skb))
7272 return false;
7273
7274 opts[0] |= TD1_GTSENV6;
7275 break;
7276
7277 default:
7278 WARN_ON_ONCE(1);
7279 break;
7280 }
7281
bdfa4ed6 7282 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 7283 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 7284 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 7285 u8 ip_protocol;
1da177e4 7286
b423e9ae 7287 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 7288 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
b423e9ae 7289
e974604b 7290 if (transport_offset > TCPHO_MAX) {
7291 netif_warn(tp, tx_err, tp->dev,
7292 "Invalid transport offset 0x%x\n",
7293 transport_offset);
7294 return false;
7295 }
7296
7297 switch (get_protocol(skb)) {
7298 case htons(ETH_P_IP):
7299 opts[1] |= TD1_IPv4_CS;
7300 ip_protocol = ip_hdr(skb)->protocol;
7301 break;
7302
7303 case htons(ETH_P_IPV6):
7304 opts[1] |= TD1_IPv6_CS;
7305 ip_protocol = ipv6_hdr(skb)->nexthdr;
7306 break;
7307
7308 default:
7309 ip_protocol = IPPROTO_RAW;
7310 break;
7311 }
7312
7313 if (ip_protocol == IPPROTO_TCP)
7314 opts[1] |= TD1_TCP_CS;
7315 else if (ip_protocol == IPPROTO_UDP)
7316 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 7317 else
7318 WARN_ON_ONCE(1);
e974604b 7319
7320 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 7321 } else {
7322 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 7323 return !eth_skb_pad(skb);
1da177e4 7324 }
5888d3fc 7325
b423e9ae 7326 return true;
1da177e4
LT		 7327}
7328
61357325
SH		 7329static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7330 struct net_device *dev)
1da177e4
LT		 7331{
7332 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 7333 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 7334 struct TxDesc *txd = tp->TxDescArray + entry;
7335 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 7336 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 7337 dma_addr_t mapping;
7338 u32 status, len;
2b7b4318 7339 u32 opts[2];
3eafe507 7340 int frags;
5b0384f4 7341
477206a0 7342 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 7343 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 7344 goto err_stop_0;
1da177e4
LT		 7345 }
7346
7347 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 7348 goto err_stop_0;
7349
b423e9ae 7350 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7351 opts[0] = DescOwn;
7352
e974604b 7353 if (!tp->tso_csum(tp, skb, opts)) {
7354 r8169_csum_workaround(tp, skb);
7355 return NETDEV_TX_OK;
7356 }
b423e9ae 7357
3eafe507 7358 len = skb_headlen(skb);
48addcc9 7359 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 7360 if (unlikely(dma_mapping_error(d, mapping))) {
7361 if (net_ratelimit())
7362 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 7363 goto err_dma_0;
d827d86b 7364 }
3eafe507
SG		 7365
7366 tp->tx_skb[entry].len = len;
7367 txd->addr = cpu_to_le64(mapping);
1da177e4 7368
2b7b4318 7369 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 7370 if (frags < 0)
7371 goto err_dma_1;
7372 else if (frags)
2b7b4318 7373 opts[0] |= FirstFrag;
3eafe507 7374 else {
2b7b4318 7375 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 7376 tp->tx_skb[entry].skb = skb;
7377 }
7378
2b7b4318
FR		 7379 txd->opts2 = cpu_to_le32(opts[1]);
7380
5047fb5d
RC		 7381 skb_tx_timestamp(skb);
7382
a0750138
AD		 7383 /* Force memory writes to complete before releasing descriptor */
7384 dma_wmb();
1da177e4 7385
cecb5fd7 7386 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 7387 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 7388 txd->opts1 = cpu_to_le32(status);
7389
a0750138 7390 /* Force all memory writes to complete before notifying device */
4c020a96 7391 wmb();
1da177e4 7392
a0750138
AD		 7393 tp->cur_tx += frags + 1;
7394
87cda7cb 7395 RTL_W8(TxPoll, NPQ);
1da177e4 7396
87cda7cb 7397 mmiowb();
da78dbff 7398
87cda7cb 7399 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 7400 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7401 * not miss a ring update when it notices a stopped queue.
7402 */
7403 smp_wmb();
1da177e4 7404 netif_stop_queue(dev);
ae1f23fb
FR		 7405 /* Sync with rtl_tx:
7406 * - publish queue status and cur_tx ring index (write barrier)
7407 * - refresh dirty_tx ring index (read barrier).
7408 * May the current thread have a pessimistic view of the ring
7409 * status and forget to wake up queue, a racing rtl_tx thread
7410 * can't.
7411 */
1e874e04 7412 smp_mb();
477206a0 7413 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 7414 netif_wake_queue(dev);
7415 }
7416
61357325 7417 return NETDEV_TX_OK;
1da177e4 7418
3eafe507 7419err_dma_1:
48addcc9 7420 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 7421err_dma_0:
989c9ba1 7422 dev_kfree_skb_any(skb);
3eafe507
SG		 7423 dev->stats.tx_dropped++;
7424 return NETDEV_TX_OK;
7425
7426err_stop_0:
1da177e4 7427 netif_stop_queue(dev);
cebf8cc7 7428 dev->stats.tx_dropped++;
61357325 7429 return NETDEV_TX_BUSY;
1da177e4
LT		 7430}
7431
7432static void rtl8169_pcierr_interrupt(struct net_device *dev)
7433{
7434 struct rtl8169_private *tp = netdev_priv(dev);
7435 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 7436 u16 pci_status, pci_cmd;
7437
7438 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7439 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7440
bf82c189
JP		 7441 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7442 pci_cmd, pci_status);
1da177e4
LT		 7443
7444 /*
7445 * The recovery sequence below admits a very elaborated explanation:
7446 * - it seems to work;
d03902b8
FR		 7447 * - I did not see what else could be done;
7448 * - it makes iop3xx happy.
1da177e4
LT		 7449 *
7450 * Feel free to adjust to your needs.
7451 */
a27993f3 7452 if (pdev->broken_parity_status)
d03902b8
FR		 7453 pci_cmd &= ~PCI_COMMAND_PARITY;
7454 else
7455 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7456
7457 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 7458
7459 pci_write_config_word(pdev, PCI_STATUS,
7460 pci_status & (PCI_STATUS_DETECTED_PARITY |
7461 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7462 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7463
7464 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 7465 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
e6de30d6 7466 void __iomem *ioaddr = tp->mmio_addr;
7467
bf82c189 7468 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 7469 tp->cp_cmd &= ~PCIDAC;
7470 RTL_W16(CPlusCmd, tp->cp_cmd);
7471 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 7472 }
7473
e6de30d6 7474 rtl8169_hw_reset(tp);
d03902b8 7475
98ddf986 7476 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 7477}
7478
da78dbff 7479static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 7480{
7481 unsigned int dirty_tx, tx_left;
7482
1da177e4
LT		 7483 dirty_tx = tp->dirty_tx;
7484 smp_rmb();
7485 tx_left = tp->cur_tx - dirty_tx;
7486
7487 while (tx_left > 0) {
7488 unsigned int entry = dirty_tx % NUM_TX_DESC;
7489 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 7490 u32 status;
7491
1da177e4
LT		 7492 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7493 if (status & DescOwn)
7494 break;
7495
a0750138
AD		 7496 /* This barrier is needed to keep us from reading
7497 * any other fields out of the Tx descriptor until
7498 * we know the status of DescOwn
7499 */
7500 dma_rmb();
7501
48addcc9
SG		 7502 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7503 tp->TxDescArray + entry);
1da177e4 7504 if (status & LastFrag) {
87cda7cb
DM		 7505 u64_stats_update_begin(&tp->tx_stats.syncp);
7506 tp->tx_stats.packets++;
7507 tp->tx_stats.bytes += tx_skb->skb->len;
7508 u64_stats_update_end(&tp->tx_stats.syncp);
7a4b813c 7509 dev_consume_skb_any(tx_skb->skb);
1da177e4
LT		 7510 tx_skb->skb = NULL;
7511 }
7512 dirty_tx++;
7513 tx_left--;
7514 }
7515
7516 if (tp->dirty_tx != dirty_tx) {
7517 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 7518 /* Sync with rtl8169_start_xmit:
7519 * - publish dirty_tx ring index (write barrier)
7520 * - refresh cur_tx ring index and queue status (read barrier)
7521 * May the current thread miss the stopped queue condition,
7522 * a racing xmit thread can only have a right view of the
7523 * ring status.
7524 */
1e874e04 7525 smp_mb();
1da177e4 7526 if (netif_queue_stopped(dev) &&
477206a0 7527 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 7528 netif_wake_queue(dev);
7529 }
d78ae2dc
FR		 7530 /*
7531 * 8168 hack: TxPoll requests are lost when the Tx packets are
7532 * too close. Let's kick an extra TxPoll request when a burst
7533 * of start_xmit activity is detected (if it is not detected,
7534 * it is slow enough). -- FR
7535 */
da78dbff
FR		 7536 if (tp->cur_tx != dirty_tx) {
7537 void __iomem *ioaddr = tp->mmio_addr;
7538
d78ae2dc 7539 RTL_W8(TxPoll, NPQ);
da78dbff 7540 }
1da177e4
LT		 7541 }
7542}
7543
126fa4b9
FR		 7544static inline int rtl8169_fragmented_frame(u32 status)
7545{
7546 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7547}
7548
adea1ac7 7549static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 7550{
1da177e4
LT		 7551 u32 status = opts1 & RxProtoMask;
7552
7553 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 7554 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 7555 skb->ip_summed = CHECKSUM_UNNECESSARY;
7556 else
bc8acf2c 7557 skb_checksum_none_assert(skb);
1da177e4
LT		 7558}
7559
6f0333b8
ED		 7560static struct sk_buff *rtl8169_try_rx_copy(void *data,
7561 struct rtl8169_private *tp,
7562 int pkt_size,
7563 dma_addr_t addr)
1da177e4 7564{
b449655f 7565 struct sk_buff *skb;
48addcc9 7566 struct device *d = &tp->pci_dev->dev;
b449655f 7567
6f0333b8 7568 data = rtl8169_align(data);
48addcc9 7569 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8 7570 prefetch(data);
e2338f86 7571 skb = napi_alloc_skb(&tp->napi, pkt_size);
6f0333b8
ED		 7572 if (skb)
7573 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 7574 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7575
6f0333b8 7576 return skb;
1da177e4
LT		 7577}
7578
da78dbff 7579static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 7580{
7581 unsigned int cur_rx, rx_left;
6f0333b8 7582 unsigned int count;
1da177e4 7583
1da177e4 7584 cur_rx = tp->cur_rx;
1da177e4 7585
9fba0812 7586 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 7587 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 7588 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 7589 u32 status;
7590
e03f33af 7591 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 7592 if (status & DescOwn)
7593 break;
a0750138
AD		 7594
7595 /* This barrier is needed to keep us from reading
7596 * any other fields out of the Rx descriptor until
7597 * we know the status of DescOwn
7598 */
7599 dma_rmb();
7600
4dcb7d33 7601 if (unlikely(status & RxRES)) {
bf82c189
JP		 7602 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7603 status);
cebf8cc7 7604 dev->stats.rx_errors++;
1da177e4 7605 if (status & (RxRWT | RxRUNT))
cebf8cc7 7606 dev->stats.rx_length_errors++;
1da177e4 7607 if (status & RxCRC)
cebf8cc7 7608 dev->stats.rx_crc_errors++;
9dccf611 7609 if (status & RxFOVF) {
da78dbff 7610 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 7611 dev->stats.rx_fifo_errors++;
9dccf611 7612 }
6bbe021d
BG		 7613 if ((status & (RxRUNT | RxCRC)) &&
7614 !(status & (RxRWT | RxFOVF)) &&
7615 (dev->features & NETIF_F_RXALL))
7616 goto process_pkt;
1da177e4 7617 } else {
6f0333b8 7618 struct sk_buff *skb;
6bbe021d
BG		 7619 dma_addr_t addr;
7620 int pkt_size;
7621
7622process_pkt:
7623 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 7624 if (likely(!(dev->features & NETIF_F_RXFCS)))
7625 pkt_size = (status & 0x00003fff) - 4;
7626 else
7627 pkt_size = status & 0x00003fff;
1da177e4 7628
126fa4b9
FR		 7629 /*
7630 * The driver does not support incoming fragmented
7631 * frames. They are seen as a symptom of over-mtu
7632 * sized frames.
7633 */
7634 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 7635 dev->stats.rx_dropped++;
7636 dev->stats.rx_length_errors++;
ce11ff5e 7637 goto release_descriptor;
126fa4b9
FR		 7638 }
7639
6f0333b8
ED		 7640 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7641 tp, pkt_size, addr);
6f0333b8
ED		 7642 if (!skb) {
7643 dev->stats.rx_dropped++;
ce11ff5e 7644 goto release_descriptor;
1da177e4
LT		 7645 }
7646
adea1ac7 7647 rtl8169_rx_csum(skb, status);
1da177e4
LT		 7648 skb_put(skb, pkt_size);
7649 skb->protocol = eth_type_trans(skb, dev);
7650
7a8fc77b
FR		 7651 rtl8169_rx_vlan_tag(desc, skb);
7652
39174291 7653 if (skb->pkt_type == PACKET_MULTICAST)
7654 dev->stats.multicast++;
7655
56de414c 7656 napi_gro_receive(&tp->napi, skb);
1da177e4 7657
8027aa24
JW		 7658 u64_stats_update_begin(&tp->rx_stats.syncp);
7659 tp->rx_stats.packets++;
7660 tp->rx_stats.bytes += pkt_size;
7661 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 7662 }
ce11ff5e 7663release_descriptor:
7664 desc->opts2 = 0;
ce11ff5e 7665 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 7666 }
7667
7668 count = cur_rx - tp->cur_rx;
7669 tp->cur_rx = cur_rx;
7670
1da177e4
LT		 7671 return count;
7672}
7673
07d3f51f 7674static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 7675{
07d3f51f 7676 struct net_device *dev = dev_instance;
1da177e4 7677 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 7678 int handled = 0;
9085cdfa 7679 u16 status;
1da177e4 7680
9085cdfa 7681 status = rtl_get_events(tp);
da78dbff
FR		 7682 if (status && status != 0xffff) {
7683 status &= RTL_EVENT_NAPI | tp->event_slow;
7684 if (status) {
7685 handled = 1;
1da177e4 7686
da78dbff
FR		 7687 rtl_irq_disable(tp);
7688 napi_schedule(&tp->napi);
f11a377b 7689 }
da78dbff
FR		 7690 }
7691 return IRQ_RETVAL(handled);
7692}
1da177e4 7693
da78dbff
FR		 7694/*
7695 * Workqueue context.
7696 */
7697static void rtl_slow_event_work(struct rtl8169_private *tp)
7698{
7699 struct net_device *dev = tp->dev;
7700 u16 status;
7701
7702 status = rtl_get_events(tp) & tp->event_slow;
7703 rtl_ack_events(tp, status);
1da177e4 7704
da78dbff
FR		 7705 if (unlikely(status & RxFIFOOver)) {
7706 switch (tp->mac_version) {
7707 /* Work around for rx fifo overflow */
7708 case RTL_GIGA_MAC_VER_11:
7709 netif_stop_queue(dev);
934714d0
FR		 7710 /* XXX - Hack alert. See rtl_task(). */
7711 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 7712 default:
f11a377b
DD		 7713 break;
7714 }
da78dbff 7715 }
1da177e4 7716
da78dbff
FR		 7717 if (unlikely(status & SYSErr))
7718 rtl8169_pcierr_interrupt(dev);
0e485150 7719
da78dbff 7720 if (status & LinkChg)
ef4d5fcc 7721 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 7722
7dbb4918 7723 rtl_irq_enable_all(tp);
1da177e4
LT		 7724}
7725
4422bcd4
FR		 7726static void rtl_task(struct work_struct *work)
7727{
da78dbff
FR		 7728 static const struct {
7729 int bitnr;
7730 void (*action)(struct rtl8169_private *);
7731 } rtl_work[] = {
934714d0 7732 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 7733 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7734 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7735 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7736 };
4422bcd4
FR		 7737 struct rtl8169_private *tp =
7738 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 7739 struct net_device *dev = tp->dev;
7740 int i;
7741
7742 rtl_lock_work(tp);
7743
6c4a70c5
FR		 7744 if (!netif_running(dev) ||
7745 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 7746 goto out_unlock;
7747
7748 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7749 bool pending;
7750
da78dbff 7751 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 7752 if (pending)
7753 rtl_work[i].action(tp);
7754 }
4422bcd4 7755
da78dbff
FR		 7756out_unlock:
7757 rtl_unlock_work(tp);
4422bcd4
FR		 7758}
7759
bea3348e 7760static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 7761{
bea3348e
SH		 7762 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7763 struct net_device *dev = tp->dev;
da78dbff
FR		 7764 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7765 int work_done= 0;
7766 u16 status;
7767
7768 status = rtl_get_events(tp);
7769 rtl_ack_events(tp, status & ~tp->event_slow);
7770
7771 if (status & RTL_EVENT_NAPI_RX)
7772 work_done = rtl_rx(dev, tp, (u32) budget);
7773
7774 if (status & RTL_EVENT_NAPI_TX)
7775 rtl_tx(dev, tp);
1da177e4 7776
da78dbff
FR		 7777 if (status & tp->event_slow) {
7778 enable_mask &= ~tp->event_slow;
7779
7780 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7781 }
1da177e4 7782
bea3348e 7783 if (work_done < budget) {
6ad20165 7784 napi_complete_done(napi, work_done);
f11a377b 7785
da78dbff
FR		 7786 rtl_irq_enable(tp, enable_mask);
7787 mmiowb();
1da177e4
LT		 7788 }
7789
bea3348e 7790 return work_done;
1da177e4 7791}
1da177e4 7792
523a6094
FR		 7793static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7794{
7795 struct rtl8169_private *tp = netdev_priv(dev);
7796
7797 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7798 return;
7799
7800 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7801 RTL_W32(RxMissed, 0);
7802}
7803
1da177e4
LT		 7804static void rtl8169_down(struct net_device *dev)
7805{
7806 struct rtl8169_private *tp = netdev_priv(dev);
7807 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 7808
4876cc1e 7809 del_timer_sync(&tp->timer);
1da177e4 7810
93dd79e8 7811 napi_disable(&tp->napi);
da78dbff 7812 netif_stop_queue(dev);
1da177e4 7813
92fc43b4 7814 rtl8169_hw_reset(tp);
323bb685
SG		 7815 /*
7816 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 7817 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7818 * and napi is disabled (rtl8169_poll).
323bb685 7819 */
523a6094 7820 rtl8169_rx_missed(dev, ioaddr);
1da177e4 7821
1da177e4 7822 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 7823 synchronize_sched();
1da177e4 7824
1da177e4
LT		 7825 rtl8169_tx_clear(tp);
7826
7827 rtl8169_rx_clear(tp);
065c27c1 7828
7829 rtl_pll_power_down(tp);
1da177e4
LT		 7830}
7831
7832static int rtl8169_close(struct net_device *dev)
7833{
7834 struct rtl8169_private *tp = netdev_priv(dev);
7835 struct pci_dev *pdev = tp->pci_dev;
7836
e1759441
RW		 7837 pm_runtime_get_sync(&pdev->dev);
7838
cecb5fd7 7839 /* Update counters before going down */
355423d0
IV		 7840 rtl8169_update_counters(dev);
7841
da78dbff 7842 rtl_lock_work(tp);
6c4a70c5 7843 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 7844
1da177e4 7845 rtl8169_down(dev);
da78dbff 7846 rtl_unlock_work(tp);
1da177e4 7847
4ea72445
L		 7848 cancel_work_sync(&tp->wk.work);
7849
92a7c4e7 7850 free_irq(pdev->irq, dev);
1da177e4 7851
82553bb6
SG		 7852 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7853 tp->RxPhyAddr);
7854 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7855 tp->TxPhyAddr);
1da177e4
LT		 7856 tp->TxDescArray = NULL;
7857 tp->RxDescArray = NULL;
7858
e1759441
RW		 7859 pm_runtime_put_sync(&pdev->dev);
7860
1da177e4
LT		 7861 return 0;
7862}
7863
dc1c00ce
FR		 7864#ifdef CONFIG_NET_POLL_CONTROLLER
7865static void rtl8169_netpoll(struct net_device *dev)
7866{
7867 struct rtl8169_private *tp = netdev_priv(dev);
7868
7869 rtl8169_interrupt(tp->pci_dev->irq, dev);
7870}
7871#endif
7872
df43ac78
FR		 7873static int rtl_open(struct net_device *dev)
7874{
7875 struct rtl8169_private *tp = netdev_priv(dev);
7876 void __iomem *ioaddr = tp->mmio_addr;
7877 struct pci_dev *pdev = tp->pci_dev;
7878 int retval = -ENOMEM;
7879
7880 pm_runtime_get_sync(&pdev->dev);
7881
7882 /*
e75d6606 7883 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 7884 * dma_alloc_coherent provides more.
7885 */
7886 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7887 &tp->TxPhyAddr, GFP_KERNEL);
7888 if (!tp->TxDescArray)
7889 goto err_pm_runtime_put;
7890
7891 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7892 &tp->RxPhyAddr, GFP_KERNEL);
7893 if (!tp->RxDescArray)
7894 goto err_free_tx_0;
7895
7896 retval = rtl8169_init_ring(dev);
7897 if (retval < 0)
7898 goto err_free_rx_1;
7899
7900 INIT_WORK(&tp->wk.work, rtl_task);
7901
7902 smp_mb();
7903
7904 rtl_request_firmware(tp);
7905
92a7c4e7 7906 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 7907 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7908 dev->name, dev);
7909 if (retval < 0)
7910 goto err_release_fw_2;
7911
7912 rtl_lock_work(tp);
7913
7914 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7915
7916 napi_enable(&tp->napi);
7917
7918 rtl8169_init_phy(dev, tp);
7919
7920 __rtl8169_set_features(dev, dev->features);
7921
7922 rtl_pll_power_up(tp);
7923
7924 rtl_hw_start(dev);
7925
6e85d5ad
CV		 7926 if (!rtl8169_init_counter_offsets(dev))
7927 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7928
df43ac78
FR		 7929 netif_start_queue(dev);
7930
7931 rtl_unlock_work(tp);
7932
7933 tp->saved_wolopts = 0;
a92a0849 7934 pm_runtime_put_sync(&pdev->dev);
df43ac78
FR		 7935
7936 rtl8169_check_link_status(dev, tp, ioaddr);
7937out:
7938 return retval;
7939
7940err_release_fw_2:
7941 rtl_release_firmware(tp);
7942 rtl8169_rx_clear(tp);
7943err_free_rx_1:
7944 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7945 tp->RxPhyAddr);
7946 tp->RxDescArray = NULL;
7947err_free_tx_0:
7948 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7949 tp->TxPhyAddr);
7950 tp->TxDescArray = NULL;
7951err_pm_runtime_put:
7952 pm_runtime_put_noidle(&pdev->dev);
7953 goto out;
7954}
7955
bc1f4470 7956static void
8027aa24 7957rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 7958{
7959 struct rtl8169_private *tp = netdev_priv(dev);
7960 void __iomem *ioaddr = tp->mmio_addr;
f09cf4b7 7961 struct pci_dev *pdev = tp->pci_dev;
42020320 7962 struct rtl8169_counters *counters = tp->counters;
8027aa24 7963 unsigned int start;
1da177e4 7964
f09cf4b7
CHL		 7965 pm_runtime_get_noresume(&pdev->dev);
7966
7967 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
523a6094 7968 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 7969
8027aa24 7970 do {
57a7744e 7971 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 7972 stats->rx_packets = tp->rx_stats.packets;
7973 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 7974 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 7975
8027aa24 7976 do {
57a7744e 7977 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 7978 stats->tx_packets = tp->tx_stats.packets;
7979 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 7980 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 7981
7982 stats->rx_dropped = dev->stats.rx_dropped;
7983 stats->tx_dropped = dev->stats.tx_dropped;
7984 stats->rx_length_errors = dev->stats.rx_length_errors;
7985 stats->rx_errors = dev->stats.rx_errors;
7986 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7987 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7988 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 7989 stats->multicast = dev->stats.multicast;
8027aa24 7990
6e85d5ad
CV		 7991 /*
7992 * Fetch additonal counter values missing in stats collected by driver
7993 * from tally counters.
7994 */
f09cf4b7
CHL		 7995 if (pm_runtime_active(&pdev->dev))
7996 rtl8169_update_counters(dev);
6e85d5ad
CV		 7997
7998 /*
7999 * Subtract values fetched during initalization.
8000 * See rtl8169_init_counter_offsets for a description why we do that.
8001 */
42020320 8002 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 8003 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 8004 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 8005 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 8006 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 8007 le16_to_cpu(tp->tc_offset.tx_aborted);
8008
f09cf4b7 8009 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 8010}
8011
861ab440 8012static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 8013{
065c27c1 8014 struct rtl8169_private *tp = netdev_priv(dev);
8015
5d06a99f 8016 if (!netif_running(dev))
861ab440 8017 return;
5d06a99f
FR		 8018
8019 netif_device_detach(dev);
8020 netif_stop_queue(dev);
da78dbff
FR		 8021
8022 rtl_lock_work(tp);
8023 napi_disable(&tp->napi);
6c4a70c5 8024 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 8025 rtl_unlock_work(tp);
8026
8027 rtl_pll_power_down(tp);
861ab440
RW		 8028}
8029
8030#ifdef CONFIG_PM
8031
8032static int rtl8169_suspend(struct device *device)
8033{
8034 struct pci_dev *pdev = to_pci_dev(device);
8035 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 8036
861ab440 8037 rtl8169_net_suspend(dev);
1371fa6d 8038
5d06a99f
FR		 8039 return 0;
8040}
8041
e1759441
RW		 8042static void __rtl8169_resume(struct net_device *dev)
8043{
065c27c1 8044 struct rtl8169_private *tp = netdev_priv(dev);
8045
e1759441 8046 netif_device_attach(dev);
065c27c1 8047
8048 rtl_pll_power_up(tp);
8049
cff4c162
AS		 8050 rtl_lock_work(tp);
8051 napi_enable(&tp->napi);
6c4a70c5 8052 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 8053 rtl_unlock_work(tp);
da78dbff 8054
98ddf986 8055 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 8056}
8057
861ab440 8058static int rtl8169_resume(struct device *device)
5d06a99f 8059{
861ab440 8060 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 8061 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 8062 struct rtl8169_private *tp = netdev_priv(dev);
8063
8064 rtl8169_init_phy(dev, tp);
5d06a99f 8065
e1759441
RW		 8066 if (netif_running(dev))
8067 __rtl8169_resume(dev);
5d06a99f 8068
e1759441
RW		 8069 return 0;
8070}
8071
8072static int rtl8169_runtime_suspend(struct device *device)
8073{
8074 struct pci_dev *pdev = to_pci_dev(device);
8075 struct net_device *dev = pci_get_drvdata(pdev);
8076 struct rtl8169_private *tp = netdev_priv(dev);
8077
a92a0849
HK		 8078 if (!tp->TxDescArray) {
8079 rtl_pll_power_down(tp);
e1759441 8080 return 0;
a92a0849 8081 }
e1759441 8082
da78dbff 8083 rtl_lock_work(tp);
e1759441
RW		 8084 tp->saved_wolopts = __rtl8169_get_wol(tp);
8085 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 8086 rtl_unlock_work(tp);
e1759441
RW		 8087
8088 rtl8169_net_suspend(dev);
8089
f09cf4b7
CHL		 8090 /* Update counters before going runtime suspend */
8091 rtl8169_rx_missed(dev, tp->mmio_addr);
8092 rtl8169_update_counters(dev);
8093
e1759441
RW		 8094 return 0;
8095}
8096
8097static int rtl8169_runtime_resume(struct device *device)
8098{
8099 struct pci_dev *pdev = to_pci_dev(device);
8100 struct net_device *dev = pci_get_drvdata(pdev);
8101 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 8102 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 8103
8104 if (!tp->TxDescArray)
8105 return 0;
8106
da78dbff 8107 rtl_lock_work(tp);
e1759441
RW		 8108 __rtl8169_set_wol(tp, tp->saved_wolopts);
8109 tp->saved_wolopts = 0;
da78dbff 8110 rtl_unlock_work(tp);
e1759441 8111
fccec10b
SG		 8112 rtl8169_init_phy(dev, tp);
8113
e1759441 8114 __rtl8169_resume(dev);
5d06a99f 8115
5d06a99f
FR		 8116 return 0;
8117}
8118
e1759441
RW		 8119static int rtl8169_runtime_idle(struct device *device)
8120{
8121 struct pci_dev *pdev = to_pci_dev(device);
8122 struct net_device *dev = pci_get_drvdata(pdev);
e1759441 8123
a92a0849
HK		 8124 if (!netif_running(dev) || !netif_carrier_ok(dev))
8125 pm_schedule_suspend(device, 10000);
8126
8127 return -EBUSY;
e1759441
RW		 8128}
8129
47145210 8130static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 8131 .suspend = rtl8169_suspend,
8132 .resume = rtl8169_resume,
8133 .freeze = rtl8169_suspend,
8134 .thaw = rtl8169_resume,
8135 .poweroff = rtl8169_suspend,
8136 .restore = rtl8169_resume,
8137 .runtime_suspend = rtl8169_runtime_suspend,
8138 .runtime_resume = rtl8169_runtime_resume,
8139 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 8140};
8141
8142#define RTL8169_PM_OPS (&rtl8169_pm_ops)
8143
8144#else /* !CONFIG_PM */
8145
8146#define RTL8169_PM_OPS NULL
8147
8148#endif /* !CONFIG_PM */
8149
649b3b8c 8150static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
8151{
8152 void __iomem *ioaddr = tp->mmio_addr;
8153
8154 /* WoL fails with 8168b when the receiver is disabled. */
8155 switch (tp->mac_version) {
8156 case RTL_GIGA_MAC_VER_11:
8157 case RTL_GIGA_MAC_VER_12:
8158 case RTL_GIGA_MAC_VER_17:
8159 pci_clear_master(tp->pci_dev);
8160
8161 RTL_W8(ChipCmd, CmdRxEnb);
8162 /* PCI commit */
8163 RTL_R8(ChipCmd);
8164 break;
8165 default:
8166 break;
8167 }
8168}
8169
1765f95d
FR		 8170static void rtl_shutdown(struct pci_dev *pdev)
8171{
861ab440 8172 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 8173 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 8174
8175 rtl8169_net_suspend(dev);
1765f95d 8176
cecb5fd7 8177 /* Restore original MAC address */
cc098dc7
IV		 8178 rtl_rar_set(tp, dev->perm_addr);
8179
92fc43b4 8180 rtl8169_hw_reset(tp);
4bb3f522 8181
861ab440 8182 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 8183 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
8184 rtl_wol_suspend_quirk(tp);
8185 rtl_wol_shutdown_quirk(tp);
ca52efd5 8186 }
8187
861ab440
RW		 8188 pci_wake_from_d3(pdev, true);
8189 pci_set_power_state(pdev, PCI_D3hot);
8190 }
8191}
5d06a99f 8192
baf63293 8193static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 8194{
8195 struct net_device *dev = pci_get_drvdata(pdev);
8196 struct rtl8169_private *tp = netdev_priv(dev);
8197
9dbe7896 8198 if (r8168_check_dash(tp))
e27566ed 8199 rtl8168_driver_stop(tp);
e27566ed 8200
ad1be8d3
DN		 8201 netif_napi_del(&tp->napi);
8202
e27566ed
FR		 8203 unregister_netdev(dev);
8204
8205 rtl_release_firmware(tp);
8206
8207 if (pci_dev_run_wake(pdev))
8208 pm_runtime_get_noresume(&pdev->dev);
8209
8210 /* restore original MAC address */
8211 rtl_rar_set(tp, dev->perm_addr);
e27566ed
FR		 8212}
8213
fa9c385e 8214static const struct net_device_ops rtl_netdev_ops = {
df43ac78 8215 .ndo_open = rtl_open,
fa9c385e
FR		 8216 .ndo_stop = rtl8169_close,
8217 .ndo_get_stats64 = rtl8169_get_stats64,
8218 .ndo_start_xmit = rtl8169_start_xmit,
8219 .ndo_tx_timeout = rtl8169_tx_timeout,
8220 .ndo_validate_addr = eth_validate_addr,
8221 .ndo_change_mtu = rtl8169_change_mtu,
8222 .ndo_fix_features = rtl8169_fix_features,
8223 .ndo_set_features = rtl8169_set_features,
8224 .ndo_set_mac_address = rtl_set_mac_address,
8225 .ndo_do_ioctl = rtl8169_ioctl,
8226 .ndo_set_rx_mode = rtl_set_rx_mode,
8227#ifdef CONFIG_NET_POLL_CONTROLLER
8228 .ndo_poll_controller = rtl8169_netpoll,
8229#endif
8230
8231};
8232
31fa8b18
FR		 8233static const struct rtl_cfg_info {
8234 void (*hw_start)(struct net_device *);
8235 unsigned int region;
8236 unsigned int align;
8237 u16 event_slow;
8238 unsigned features;
50970831 8239 const struct rtl_coalesce_info *coalesce_info;
31fa8b18
FR		 8240 u8 default_ver;
8241} rtl_cfg_infos [] = {
8242 [RTL_CFG_0] = {
8243 .hw_start = rtl_hw_start_8169,
8244 .region = 1,
8245 .align = 0,
8246 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8247 .features = RTL_FEATURE_GMII,
50970831 8248 .coalesce_info = rtl_coalesce_info_8169,
31fa8b18
FR		 8249 .default_ver = RTL_GIGA_MAC_VER_01,
8250 },
8251 [RTL_CFG_1] = {
8252 .hw_start = rtl_hw_start_8168,
8253 .region = 2,
8254 .align = 8,
8255 .event_slow = SYSErr | LinkChg | RxOverflow,
8256 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
50970831 8257 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 8258 .default_ver = RTL_GIGA_MAC_VER_11,
8259 },
8260 [RTL_CFG_2] = {
8261 .hw_start = rtl_hw_start_8101,
8262 .region = 2,
8263 .align = 8,
8264 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8265 PCSTimeout,
8266 .features = RTL_FEATURE_MSI,
50970831 8267 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 8268 .default_ver = RTL_GIGA_MAC_VER_13,
8269 }
8270};
8271
8272/* Cfg9346_Unlock assumed. */
8273static unsigned rtl_try_msi(struct rtl8169_private *tp,
8274 const struct rtl_cfg_info *cfg)
8275{
8276 void __iomem *ioaddr = tp->mmio_addr;
8277 unsigned msi = 0;
8278 u8 cfg2;
8279
8280 cfg2 = RTL_R8(Config2) & ~MSIEnable;
8281 if (cfg->features & RTL_FEATURE_MSI) {
8282 if (pci_enable_msi(tp->pci_dev)) {
8283 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8284 } else {
8285 cfg2 |= MSIEnable;
8286 msi = RTL_FEATURE_MSI;
8287 }
8288 }
8289 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8290 RTL_W8(Config2, cfg2);
8291 return msi;
8292}
8293
c558386b
HW		 8294DECLARE_RTL_COND(rtl_link_list_ready_cond)
8295{
8296 void __iomem *ioaddr = tp->mmio_addr;
8297
8298 return RTL_R8(MCU) & LINK_LIST_RDY;
8299}
8300
8301DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8302{
8303 void __iomem *ioaddr = tp->mmio_addr;
8304
8305 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8306}
8307
baf63293 8308static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 8309{
8310 void __iomem *ioaddr = tp->mmio_addr;
8311 u32 data;
8312
8313 tp->ocp_base = OCP_STD_PHY_BASE;
8314
8315 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8316
8317 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8318 return;
8319
8320 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8321 return;
8322
8323 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8324 msleep(1);
8325 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8326
5f8bcce9 8327 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 8328 data &= ~(1 << 14);
8329 r8168_mac_ocp_write(tp, 0xe8de, data);
8330
8331 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8332 return;
8333
5f8bcce9 8334 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 8335 data |= (1 << 15);
8336 r8168_mac_ocp_write(tp, 0xe8de, data);
8337
8338 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8339 return;
8340}
8341
003609da
CHL		 8342static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8343{
8344 rtl8168ep_stop_cmac(tp);
8345 rtl_hw_init_8168g(tp);
8346}
8347
baf63293 8348static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 8349{
8350 switch (tp->mac_version) {
8351 case RTL_GIGA_MAC_VER_40:
8352 case RTL_GIGA_MAC_VER_41:
57538c4a 8353 case RTL_GIGA_MAC_VER_42:
58152cd4 8354 case RTL_GIGA_MAC_VER_43:
45dd95c4 8355 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 8356 case RTL_GIGA_MAC_VER_45:
8357 case RTL_GIGA_MAC_VER_46:
8358 case RTL_GIGA_MAC_VER_47:
8359 case RTL_GIGA_MAC_VER_48:
003609da
CHL		 8360 rtl_hw_init_8168g(tp);
8361 break;
935e2218
CHL		 8362 case RTL_GIGA_MAC_VER_49:
8363 case RTL_GIGA_MAC_VER_50:
8364 case RTL_GIGA_MAC_VER_51:
003609da 8365 rtl_hw_init_8168ep(tp);
c558386b 8366 break;
c558386b
HW		 8367 default:
8368 break;
8369 }
8370}
8371
929a031d 8372static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 8373{
8374 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8375 const unsigned int region = cfg->region;
8376 struct rtl8169_private *tp;
8377 struct mii_if_info *mii;
8378 struct net_device *dev;
8379 void __iomem *ioaddr;
8380 int chipset, i;
8381 int rc;
8382
8383 if (netif_msg_drv(&debug)) {
8384 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8385 MODULENAME, RTL8169_VERSION);
8386 }
8387
4c45d24a
HK		 8388 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
8389 if (!dev)
8390 return -ENOMEM;
3b6cf25d
FR		 8391
8392 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 8393 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 8394 tp = netdev_priv(dev);
8395 tp->dev = dev;
8396 tp->pci_dev = pdev;
8397 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8398
8399 mii = &tp->mii;
8400 mii->dev = dev;
8401 mii->mdio_read = rtl_mdio_read;
8402 mii->mdio_write = rtl_mdio_write;
8403 mii->phy_id_mask = 0x1f;
8404 mii->reg_num_mask = 0x1f;
8405 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8406
8407 /* disable ASPM completely as that cause random device stop working
8408 * problems as well as full system hangs for some PCIe devices users */
8409 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8410 PCIE_LINK_STATE_CLKPM);
8411
8412 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4c45d24a 8413 rc = pcim_enable_device(pdev);
3b6cf25d
FR		 8414 if (rc < 0) {
8415 netif_err(tp, probe, dev, "enable failure\n");
4c45d24a 8416 return rc;
3b6cf25d
FR		 8417 }
8418
4c45d24a 8419 if (pcim_set_mwi(pdev) < 0)
3b6cf25d
FR		 8420 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8421
8422 /* make sure PCI base addr 1 is MMIO */
8423 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8424 netif_err(tp, probe, dev,
8425 "region #%d not an MMIO resource, aborting\n",
8426 region);
4c45d24a 8427 return -ENODEV;
3b6cf25d
FR		 8428 }
8429
8430 /* check for weird/broken PCI region reporting */
8431 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8432 netif_err(tp, probe, dev,
8433 "Invalid PCI region size(s), aborting\n");
4c45d24a 8434 return -ENODEV;
3b6cf25d
FR		 8435 }
8436
8437 rc = pci_request_regions(pdev, MODULENAME);
8438 if (rc < 0) {
8439 netif_err(tp, probe, dev, "could not request regions\n");
4c45d24a 8440 return rc;
3b6cf25d
FR		 8441 }
8442
3b6cf25d 8443 /* ioremap MMIO region */
4c45d24a
HK		 8444 ioaddr = devm_ioremap(&pdev->dev, pci_resource_start(pdev, region),
8445 R8169_REGS_SIZE);
3b6cf25d
FR		 8446 if (!ioaddr) {
8447 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
4c45d24a 8448 return -EIO;
3b6cf25d
FR		 8449 }
8450 tp->mmio_addr = ioaddr;
8451
8452 if (!pci_is_pcie(pdev))
8453 netif_info(tp, probe, dev, "not PCI Express\n");
8454
8455 /* Identify chip attached to board */
8456 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8457
27896c83
AB		 8458 tp->cp_cmd = 0;
8459
8460 if ((sizeof(dma_addr_t) > 4) &&
8461 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8462 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
f0076436
AB		 8463 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8464 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
27896c83
AB		 8465
8466 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8467 if (!pci_is_pcie(pdev))
8468 tp->cp_cmd |= PCIDAC;
8469 dev->features |= NETIF_F_HIGHDMA;
8470 } else {
8471 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8472 if (rc < 0) {
8473 netif_err(tp, probe, dev, "DMA configuration failed\n");
4c45d24a 8474 return rc;
27896c83
AB		 8475 }
8476 }
8477
3b6cf25d
FR		 8478 rtl_init_rxcfg(tp);
8479
8480 rtl_irq_disable(tp);
8481
c558386b
HW		 8482 rtl_hw_initialize(tp);
8483
3b6cf25d
FR		 8484 rtl_hw_reset(tp);
8485
8486 rtl_ack_events(tp, 0xffff);
8487
8488 pci_set_master(pdev);
8489
3b6cf25d
FR		 8490 rtl_init_mdio_ops(tp);
8491 rtl_init_pll_power_ops(tp);
8492 rtl_init_jumbo_ops(tp);
beb1fe18 8493 rtl_init_csi_ops(tp);
3b6cf25d
FR		 8494
8495 rtl8169_print_mac_version(tp);
8496
8497 chipset = tp->mac_version;
8498 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8499
8500 RTL_W8(Cfg9346, Cfg9346_Unlock);
3b6cf25d
FR		 8501 tp->features |= rtl_try_msi(tp, cfg);
8502 RTL_W8(Cfg9346, Cfg9346_Lock);
8503
7edf6d31
HK		 8504 /* override BIOS settings, use userspace tools to enable WOL */
8505 __rtl8169_set_wol(tp, 0);
8506
3b6cf25d
FR		 8507 if (rtl_tbi_enabled(tp)) {
8508 tp->set_speed = rtl8169_set_speed_tbi;
6fa1ba61 8509 tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi;
3b6cf25d
FR		 8510 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8511 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8512 tp->link_ok = rtl8169_tbi_link_ok;
8513 tp->do_ioctl = rtl_tbi_ioctl;
8514 } else {
8515 tp->set_speed = rtl8169_set_speed_xmii;
6fa1ba61 8516 tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii;
3b6cf25d
FR		 8517 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8518 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8519 tp->link_ok = rtl8169_xmii_link_ok;
8520 tp->do_ioctl = rtl_xmii_ioctl;
8521 }
8522
8523 mutex_init(&tp->wk.mutex);
340fea3d
KM		 8524 u64_stats_init(&tp->rx_stats.syncp);
8525 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 8526
8527 /* Get MAC address */
89cceb27
CHL		 8528 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8529 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8530 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8531 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8532 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8533 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8534 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8535 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8536 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8537 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
6e1d0b89
CHL		 8538 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8539 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
935e2218
CHL		 8540 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8541 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8542 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8543 tp->mac_version == RTL_GIGA_MAC_VER_51) {
6e1d0b89
CHL		 8544 u16 mac_addr[3];
8545
05b9687b
CHL		 8546 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8547 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89
CHL		 8548
8549 if (is_valid_ether_addr((u8 *)mac_addr))
8550 rtl_rar_set(tp, (u8 *)mac_addr);
8551 }
3b6cf25d
FR		 8552 for (i = 0; i < ETH_ALEN; i++)
8553 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3b6cf25d 8554
7ad24ea4 8555 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 8556 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 8557
8558 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8559
8560 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8561 * properly for all devices */
8562 dev->features |= NETIF_F_RXCSUM |
f646968f 8563 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 8564
8565 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 8566 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8567 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 8568 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8569 NETIF_F_HIGHDMA;
8570
929a031d 8571 tp->cp_cmd |= RxChkSum | RxVlan;
8572
8573 /*
8574 * Pretend we are using VLANs; This bypasses a nasty bug where
8575 * Interrupts stop flowing on high load on 8110SCd controllers.
8576 */
3b6cf25d 8577 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 8578 /* Disallow toggling */
f646968f 8579 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 8580
5888d3fc 8581 if (tp->txd_version == RTL_TD_0)
8582 tp->tso_csum = rtl8169_tso_csum_v1;
e974604b 8583 else if (tp->txd_version == RTL_TD_1) {
5888d3fc 8584 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 8585 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8586 } else
5888d3fc 8587 WARN_ON_ONCE(1);
8588
3b6cf25d
FR		 8589 dev->hw_features |= NETIF_F_RXALL;
8590 dev->hw_features |= NETIF_F_RXFCS;
8591
c7315a95
JW		 8592 /* MTU range: 60 - hw-specific max */
8593 dev->min_mtu = ETH_ZLEN;
8594 dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
8595
3b6cf25d
FR		 8596 tp->hw_start = cfg->hw_start;
8597 tp->event_slow = cfg->event_slow;
50970831 8598 tp->coalesce_info = cfg->coalesce_info;
3b6cf25d
FR		 8599
8600 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8601 ~(RxBOVF | RxFOVF) : ~0;
8602
9de36ccf 8603 timer_setup(&tp->timer, rtl8169_phy_timer, 0);
3b6cf25d
FR		 8604
8605 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8606
4c45d24a
HK		 8607 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8608 &tp->counters_phys_addr,
8609 GFP_KERNEL);
4cf964af
HK		 8610 if (!tp->counters)
8611 return -ENOMEM;
42020320 8612
3b6cf25d
FR		 8613 rc = register_netdev(dev);
8614 if (rc < 0)
4cf964af 8615 return rc;
3b6cf25d
FR		 8616
8617 pci_set_drvdata(pdev, dev);
8618
92a7c4e7
FR		 8619 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8620 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8621 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 8622 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8623 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8624 "tx checksumming: %s]\n",
8625 rtl_chip_infos[chipset].jumbo_max,
8626 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8627 }
8628
9dbe7896 8629 if (r8168_check_dash(tp))
3b6cf25d 8630 rtl8168_driver_start(tp);
3b6cf25d 8631
3b6cf25d
FR		 8632 netif_carrier_off(dev);
8633
a92a0849
HK		 8634 if (pci_dev_run_wake(pdev))
8635 pm_runtime_put_sync(&pdev->dev);
8636
4c45d24a 8637 return 0;
3b6cf25d
FR		 8638}
8639
1da177e4
LT		 8640static struct pci_driver rtl8169_pci_driver = {
8641 .name = MODULENAME,
8642 .id_table = rtl8169_pci_tbl,
3b6cf25d 8643 .probe = rtl_init_one,
baf63293 8644 .remove = rtl_remove_one,
1765f95d 8645 .shutdown = rtl_shutdown,
861ab440 8646 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 8647};
8648
3eeb7da9 8649module_pci_driver(rtl8169_pci_driver);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git