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clk: x86: add "ether_clk" alias for Bay Trail / Cherry Trail
[thirdparty/kernel/stable.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
f1e911d5 18#include <linux/phy.h>
1da177e4
LT		 19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
098b01ad 22#include <linux/io.h>
1da177e4
LT		 23#include <linux/ip.h>
24#include <linux/tcp.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
31#include <net/ip6_checksum.h>
1da177e4 32
1da177e4 33#define MODULENAME "r8169"
1da177e4 34
bca03d5f 35#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
36#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 37#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
38#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 39#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 40#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
41#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 42#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 43#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 44#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 45#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 46#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 47#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 48#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 49#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 50#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
51#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
52#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
53#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 54
b57b7e5a 55#define R8169_MSG_DEFAULT \
f0e837d9 56 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 57
477206a0
JD		 58#define TX_SLOTS_AVAIL(tp) \
59 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
60
61/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
62#define TX_FRAGS_READY_FOR(tp,nr_frags) \
63 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 64
1da177e4
LT		 65/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
66 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 67static const int multicast_filter_limit = 32;
1da177e4 68
aee77e4a 69#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 70#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
71
72#define R8169_REGS_SIZE 256
1d0254dd 73#define R8169_RX_BUF_SIZE (SZ_16K - 1)
1da177e4 74#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 75#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 76#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
77#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
78
79#define RTL8169_TX_TIMEOUT (6*HZ)
1da177e4
LT		 80
81/* write/read MMIO register */
1ef7286e
AS		 82#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
83#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
84#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
85#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
86#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
87#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
1da177e4
LT		 88
89enum mac_version {
85bffe6c
FR		 90 RTL_GIGA_MAC_VER_01 = 0,
91 RTL_GIGA_MAC_VER_02,
92 RTL_GIGA_MAC_VER_03,
93 RTL_GIGA_MAC_VER_04,
94 RTL_GIGA_MAC_VER_05,
95 RTL_GIGA_MAC_VER_06,
96 RTL_GIGA_MAC_VER_07,
97 RTL_GIGA_MAC_VER_08,
98 RTL_GIGA_MAC_VER_09,
99 RTL_GIGA_MAC_VER_10,
100 RTL_GIGA_MAC_VER_11,
101 RTL_GIGA_MAC_VER_12,
102 RTL_GIGA_MAC_VER_13,
103 RTL_GIGA_MAC_VER_14,
104 RTL_GIGA_MAC_VER_15,
105 RTL_GIGA_MAC_VER_16,
106 RTL_GIGA_MAC_VER_17,
107 RTL_GIGA_MAC_VER_18,
108 RTL_GIGA_MAC_VER_19,
109 RTL_GIGA_MAC_VER_20,
110 RTL_GIGA_MAC_VER_21,
111 RTL_GIGA_MAC_VER_22,
112 RTL_GIGA_MAC_VER_23,
113 RTL_GIGA_MAC_VER_24,
114 RTL_GIGA_MAC_VER_25,
115 RTL_GIGA_MAC_VER_26,
116 RTL_GIGA_MAC_VER_27,
117 RTL_GIGA_MAC_VER_28,
118 RTL_GIGA_MAC_VER_29,
119 RTL_GIGA_MAC_VER_30,
120 RTL_GIGA_MAC_VER_31,
121 RTL_GIGA_MAC_VER_32,
122 RTL_GIGA_MAC_VER_33,
70090424 123 RTL_GIGA_MAC_VER_34,
c2218925
HW		 124 RTL_GIGA_MAC_VER_35,
125 RTL_GIGA_MAC_VER_36,
7e18dca1 126 RTL_GIGA_MAC_VER_37,
b3d7b2f2 127 RTL_GIGA_MAC_VER_38,
5598bfe5 128 RTL_GIGA_MAC_VER_39,
c558386b
HW		 129 RTL_GIGA_MAC_VER_40,
130 RTL_GIGA_MAC_VER_41,
57538c4a 131 RTL_GIGA_MAC_VER_42,
58152cd4 132 RTL_GIGA_MAC_VER_43,
45dd95c4 133 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 134 RTL_GIGA_MAC_VER_45,
135 RTL_GIGA_MAC_VER_46,
136 RTL_GIGA_MAC_VER_47,
137 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 138 RTL_GIGA_MAC_VER_49,
139 RTL_GIGA_MAC_VER_50,
140 RTL_GIGA_MAC_VER_51,
85bffe6c 141 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 142};
143
d58d46b5
FR		 144#define JUMBO_1K ETH_DATA_LEN
145#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
146#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
147#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
148#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
149
3c6bee1d 150static const struct {
1da177e4 151 const char *name;
953a12cc 152 const char *fw_name;
85bffe6c
FR		 153} rtl_chip_infos[] = {
154 /* PCI devices. */
abe8b2f7
HK		 155 [RTL_GIGA_MAC_VER_01] = {"RTL8169" },
156 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
157 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
158 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
159 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
160 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
85bffe6c 161 /* PCI-E devices. */
abe8b2f7
HK		 162 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
163 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
164 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
165 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
166 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
167 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
168 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
169 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
170 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
171 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
172 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
173 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
174 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
175 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
176 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
177 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
178 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
179 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
180 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
181 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
182 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
183 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
184 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
185 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
186 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
187 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
188 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
189 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
190 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
191 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
192 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
193 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
194 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
195 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
196 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
197 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
198 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
199 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
200 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
201 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
202 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
203 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
204 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
205 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
206 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
953a12cc
FR		 207};
208
bcf0bf90
FR		 209enum cfg_version {
210 RTL_CFG_0 = 0x00,
211 RTL_CFG_1,
212 RTL_CFG_2
213};
214
9baa3c34 215static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 216 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 217 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
610c9087 218 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
d81bf551 219 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 220 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
9fd0e09a 221 { PCI_DEVICE(PCI_VENDOR_ID_NCUBE, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 222 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 223 { PCI_VENDOR_ID_DLINK, 0x4300,
224 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 225 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 226 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 227 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 228 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
229 { PCI_VENDOR_ID_LINKSYS, 0x1032,
230 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 231 { 0x0001, 0x8168,
232 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 233 {0,},
234};
235
236MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
237
27896c83 238static int use_dac = -1;
b57b7e5a
SH		 239static struct {
240 u32 msg_enable;
241} debug = { -1 };
1da177e4 242
07d3f51f
FR		 243enum rtl_registers {
244 MAC0 = 0, /* Ethernet hardware address. */
773d2021 245 MAC4 = 4,
07d3f51f
FR		 246 MAR0 = 8, /* Multicast filter. */
247 CounterAddrLow = 0x10,
248 CounterAddrHigh = 0x14,
249 TxDescStartAddrLow = 0x20,
250 TxDescStartAddrHigh = 0x24,
251 TxHDescStartAddrLow = 0x28,
252 TxHDescStartAddrHigh = 0x2c,
253 FLASH = 0x30,
254 ERSR = 0x36,
255 ChipCmd = 0x37,
256 TxPoll = 0x38,
257 IntrMask = 0x3c,
258 IntrStatus = 0x3e,
4f6b00e5 259
07d3f51f 260 TxConfig = 0x40,
4f6b00e5
HW		 261#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
262#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 263
4f6b00e5
HW		 264 RxConfig = 0x44,
265#define RX128_INT_EN (1 << 15) /* 8111c and later */
266#define RX_MULTI_EN (1 << 14) /* 8111c only */
267#define RXCFG_FIFO_SHIFT 13
268 /* No threshold before first PCI xfer */
269#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 270#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 271#define RXCFG_DMA_SHIFT 8
272 /* Unlimited maximum PCI burst. */
273#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 274
07d3f51f
FR		 275 RxMissed = 0x4c,
276 Cfg9346 = 0x50,
277 Config0 = 0x51,
278 Config1 = 0x52,
279 Config2 = 0x53,
d387b427
FR		 280#define PME_SIGNAL (1 << 5) /* 8168c and later */
281
07d3f51f
FR		 282 Config3 = 0x54,
283 Config4 = 0x55,
284 Config5 = 0x56,
285 MultiIntr = 0x5c,
286 PHYAR = 0x60,
07d3f51f
FR		 287 PHYstatus = 0x6c,
288 RxMaxSize = 0xda,
289 CPlusCmd = 0xe0,
290 IntrMitigate = 0xe2,
50970831
FR		 291
292#define RTL_COALESCE_MASK 0x0f
293#define RTL_COALESCE_SHIFT 4
294#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
295#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
296
07d3f51f
FR		 297 RxDescAddrLow = 0xe4,
298 RxDescAddrHigh = 0xe8,
f0298f81 299 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
300
301#define NoEarlyTx 0x3f /* Max value : no early transmit. */
302
303 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
304
305#define TxPacketMax (8064 >> 7)
3090bd9a 306#define EarlySize 0x27
f0298f81 307
07d3f51f
FR		 308 FuncEvent = 0xf0,
309 FuncEventMask = 0xf4,
310 FuncPresetState = 0xf8,
935e2218
CHL		 311 IBCR0 = 0xf8,
312 IBCR2 = 0xf9,
313 IBIMR0 = 0xfa,
314 IBISR0 = 0xfb,
07d3f51f 315 FuncForceEvent = 0xfc,
1da177e4
LT		 316};
317
f162a5d1
FR		 318enum rtl8168_8101_registers {
319 CSIDR = 0x64,
320 CSIAR = 0x68,
321#define CSIAR_FLAG 0x80000000
322#define CSIAR_WRITE_CMD 0x80000000
ff1d7331
HK		 323#define CSIAR_BYTE_ENABLE 0x0000f000
324#define CSIAR_ADDR_MASK 0x00000fff
065c27c1 325 PMCH = 0x6f,
f162a5d1
FR		 326 EPHYAR = 0x80,
327#define EPHYAR_FLAG 0x80000000
328#define EPHYAR_WRITE_CMD 0x80000000
329#define EPHYAR_REG_MASK 0x1f
330#define EPHYAR_REG_SHIFT 16
331#define EPHYAR_DATA_MASK 0xffff
5a5e4443 332 DLLPR = 0xd0,
4f6b00e5 333#define PFM_EN (1 << 6)
6e1d0b89 334#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 335 DBG_REG = 0xd1,
336#define FIX_NAK_1 (1 << 4)
337#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 338 TWSI = 0xd2,
339 MCU = 0xd3,
4f6b00e5 340#define NOW_IS_OOB (1 << 7)
c558386b
HW		 341#define TX_EMPTY (1 << 5)
342#define RX_EMPTY (1 << 4)
343#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 344#define EN_NDP (1 << 3)
345#define EN_OOB_RESET (1 << 2)
c558386b 346#define LINK_LIST_RDY (1 << 1)
daf9df6d 347 EFUSEAR = 0xdc,
348#define EFUSEAR_FLAG 0x80000000
349#define EFUSEAR_WRITE_CMD 0x80000000
350#define EFUSEAR_READ_CMD 0x00000000
351#define EFUSEAR_REG_MASK 0x03ff
352#define EFUSEAR_REG_SHIFT 8
353#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 354 MISC_1 = 0xf2,
355#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 356};
357
c0e45c1c 358enum rtl8168_registers {
4f6b00e5
HW		 359 LED_FREQ = 0x1a,
360 EEE_LED = 0x1b,
b646d900 361 ERIDR = 0x70,
362 ERIAR = 0x74,
363#define ERIAR_FLAG 0x80000000
364#define ERIAR_WRITE_CMD 0x80000000
365#define ERIAR_READ_CMD 0x00000000
366#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 367#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 368#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
369#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
370#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 371#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 372#define ERIAR_MASK_SHIFT 12
373#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
374#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 375#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 376#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 377#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 378 EPHY_RXER_NUM = 0x7c,
379 OCPDR = 0xb0, /* OCP GPHY access */
380#define OCPDR_WRITE_CMD 0x80000000
381#define OCPDR_READ_CMD 0x00000000
382#define OCPDR_REG_MASK 0x7f
383#define OCPDR_GPHY_REG_SHIFT 16
384#define OCPDR_DATA_MASK 0xffff
385 OCPAR = 0xb4,
386#define OCPAR_FLAG 0x80000000
387#define OCPAR_GPHY_WRITE_CMD 0x8000f060
388#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 389 GPHY_OCP = 0xb8,
01dc7fec 390 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
391 MISC = 0xf0, /* 8168e only. */
cecb5fd7 392#define TXPLA_RST (1 << 29)
5598bfe5 393#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 394#define PWM_EN (1 << 22)
c558386b 395#define RXDV_GATED_EN (1 << 19)
5598bfe5 396#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 397};
398
07d3f51f 399enum rtl_register_content {
1da177e4 400 /* InterruptStatusBits */
07d3f51f
FR		 401 SYSErr = 0x8000,
402 PCSTimeout = 0x4000,
403 SWInt = 0x0100,
404 TxDescUnavail = 0x0080,
405 RxFIFOOver = 0x0040,
406 LinkChg = 0x0020,
407 RxOverflow = 0x0010,
408 TxErr = 0x0008,
409 TxOK = 0x0004,
410 RxErr = 0x0002,
411 RxOK = 0x0001,
1da177e4
LT		 412
413 /* RxStatusDesc */
e03f33af 414 RxBOVF = (1 << 24),
9dccf611
FR		 415 RxFOVF = (1 << 23),
416 RxRWT = (1 << 22),
417 RxRES = (1 << 21),
418 RxRUNT = (1 << 20),
419 RxCRC = (1 << 19),
1da177e4
LT		 420
421 /* ChipCmdBits */
4f6b00e5 422 StopReq = 0x80,
07d3f51f
FR		 423 CmdReset = 0x10,
424 CmdRxEnb = 0x08,
425 CmdTxEnb = 0x04,
426 RxBufEmpty = 0x01,
1da177e4 427
275391a4
FR		 428 /* TXPoll register p.5 */
429 HPQ = 0x80, /* Poll cmd on the high prio queue */
430 NPQ = 0x40, /* Poll cmd on the low prio queue */
431 FSWInt = 0x01, /* Forced software interrupt */
432
1da177e4 433 /* Cfg9346Bits */
07d3f51f
FR		 434 Cfg9346_Lock = 0x00,
435 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 436
437 /* rx_mode_bits */
07d3f51f
FR		 438 AcceptErr = 0x20,
439 AcceptRunt = 0x10,
440 AcceptBroadcast = 0x08,
441 AcceptMulticast = 0x04,
442 AcceptMyPhys = 0x02,
443 AcceptAllPhys = 0x01,
1687b566 444#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 445
1da177e4
LT		 446 /* TxConfigBits */
447 TxInterFrameGapShift = 24,
448 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
449
5d06a99f 450 /* Config1 register p.24 */
f162a5d1
FR		 451 LEDS1 = (1 << 7),
452 LEDS0 = (1 << 6),
f162a5d1
FR		 453 Speed_down = (1 << 4),
454 MEMMAP = (1 << 3),
455 IOMAP = (1 << 2),
456 VPD = (1 << 1),
5d06a99f
FR		 457 PMEnable = (1 << 0), /* Power Management Enable */
458
6dccd16b 459 /* Config2 register p. 25 */
57538c4a 460 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 461 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 462 PCI_Clock_66MHz = 0x01,
463 PCI_Clock_33MHz = 0x00,
464
61a4dcc2
FR		 465 /* Config3 register p.25 */
466 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
467 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 468 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 469 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 470 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 471
d58d46b5
FR		 472 /* Config4 register */
473 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
474
5d06a99f 475 /* Config5 register p.27 */
61a4dcc2
FR		 476 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
477 MWF = (1 << 5), /* Accept Multicast wakeup frame */
478 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 479 Spi_en = (1 << 3),
61a4dcc2 480 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 481 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 482 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 483
1da177e4 484 /* CPlusCmd p.31 */
f162a5d1
FR		 485 EnableBist = (1 << 15), // 8168 8101
486 Mac_dbgo_oe = (1 << 14), // 8168 8101
487 Normal_mode = (1 << 13), // unused
488 Force_half_dup = (1 << 12), // 8168 8101
489 Force_rxflow_en = (1 << 11), // 8168 8101
490 Force_txflow_en = (1 << 10), // 8168 8101
491 Cxpl_dbg_sel = (1 << 9), // 8168 8101
492 ASF = (1 << 8), // 8168 8101
493 PktCntrDisable = (1 << 7), // 8168 8101
494 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 495 RxVlan = (1 << 6),
496 RxChkSum = (1 << 5),
497 PCIDAC = (1 << 4),
498 PCIMulRW = (1 << 3),
9a3c81fa 499#define INTT_MASK GENMASK(1, 0)
0e485150
FR		 500 INTT_0 = 0x0000, // 8168
501 INTT_1 = 0x0001, // 8168
502 INTT_2 = 0x0002, // 8168
503 INTT_3 = 0x0003, // 8168
1da177e4
LT		 504
505 /* rtl8169_PHYstatus */
07d3f51f
FR		 506 TBI_Enable = 0x80,
507 TxFlowCtrl = 0x40,
508 RxFlowCtrl = 0x20,
509 _1000bpsF = 0x10,
510 _100bps = 0x08,
511 _10bps = 0x04,
512 LinkStatus = 0x02,
513 FullDup = 0x01,
1da177e4 514
1da177e4 515 /* _TBICSRBit */
07d3f51f 516 TBILinkOK = 0x02000000,
d4a3a0fc 517
6e85d5ad
CV		 518 /* ResetCounterCommand */
519 CounterReset = 0x1,
520
d4a3a0fc 521 /* DumpCounterCommand */
07d3f51f 522 CounterDump = 0x8,
6e1d0b89
CHL		 523
524 /* magic enable v2 */
525 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 526};
527
2b7b4318
FR		 528enum rtl_desc_bit {
529 /* First doubleword. */
1da177e4
LT		 530 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
531 RingEnd = (1 << 30), /* End of descriptor ring */
532 FirstFrag = (1 << 29), /* First segment of a packet */
533 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 534};
535
536/* Generic case. */
537enum rtl_tx_desc_bit {
538 /* First doubleword. */
539 TD_LSO = (1 << 27), /* Large Send Offload */
540#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 541
2b7b4318
FR		 542 /* Second doubleword. */
543 TxVlanTag = (1 << 17), /* Add VLAN tag */
544};
545
546/* 8169, 8168b and 810x except 8102e. */
547enum rtl_tx_desc_bit_0 {
548 /* First doubleword. */
549#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
550 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
551 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
552 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
553};
554
555/* 8102e, 8168c and beyond. */
556enum rtl_tx_desc_bit_1 {
bdfa4ed6 557 /* First doubleword. */
558 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 559 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 560#define GTTCPHO_SHIFT 18
e974604b 561#define GTTCPHO_MAX 0x7fU
bdfa4ed6 562
2b7b4318 563 /* Second doubleword. */
e974604b 564#define TCPHO_SHIFT 18
565#define TCPHO_MAX 0x3ffU
2b7b4318 566#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 567 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
568 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 569 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
570 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
571};
1da177e4 572
2b7b4318 573enum rtl_rx_desc_bit {
1da177e4
LT		 574 /* Rx private */
575 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 576 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 577
578#define RxProtoUDP (PID1)
579#define RxProtoTCP (PID0)
580#define RxProtoIP (PID1 | PID0)
581#define RxProtoMask RxProtoIP
582
583 IPFail = (1 << 16), /* IP checksum failed */
584 UDPFail = (1 << 15), /* UDP/IP checksum failed */
585 TCPFail = (1 << 14), /* TCP/IP checksum failed */
586 RxVlanTag = (1 << 16), /* VLAN tag available */
587};
588
589#define RsvdMask 0x3fffc000
12d42c50 590#define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
1da177e4
LT		 591
592struct TxDesc {
6cccd6e7
REB		 593 __le32 opts1;
594 __le32 opts2;
595 __le64 addr;
1da177e4
LT		 596};
597
598struct RxDesc {
6cccd6e7
REB		 599 __le32 opts1;
600 __le32 opts2;
601 __le64 addr;
1da177e4
LT		 602};
603
604struct ring_info {
605 struct sk_buff *skb;
606 u32 len;
607 u8 __pad[sizeof(void *) - sizeof(u32)];
608};
609
355423d0
IV		 610struct rtl8169_counters {
611 __le64 tx_packets;
612 __le64 rx_packets;
613 __le64 tx_errors;
614 __le32 rx_errors;
615 __le16 rx_missed;
616 __le16 align_errors;
617 __le32 tx_one_collision;
618 __le32 tx_multi_collision;
619 __le64 rx_unicast;
620 __le64 rx_broadcast;
621 __le32 rx_multicast;
622 __le16 tx_aborted;
623 __le16 tx_underun;
624};
625
6e85d5ad
CV		 626struct rtl8169_tc_offsets {
627 bool inited;
628 __le64 tx_errors;
629 __le32 tx_multi_collision;
6e85d5ad
CV		 630 __le16 tx_aborted;
631};
632
da78dbff 633enum rtl_flag {
6ad56901 634 RTL_FLAG_TASK_ENABLED = 0,
da78dbff
FR		 635 RTL_FLAG_TASK_SLOW_PENDING,
636 RTL_FLAG_TASK_RESET_PENDING,
da78dbff
FR		 637 RTL_FLAG_MAX
638};
639
8027aa24
JW		 640struct rtl8169_stats {
641 u64 packets;
642 u64 bytes;
643 struct u64_stats_sync syncp;
644};
645
1da177e4
LT		 646struct rtl8169_private {
647 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 648 struct pci_dev *pci_dev;
c4028958 649 struct net_device *dev;
bea3348e 650 struct napi_struct napi;
b57b7e5a 651 u32 msg_enable;
2b7b4318 652 u16 mac_version;
1da177e4
LT		 653 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
654 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 655 u32 dirty_tx;
8027aa24
JW		 656 struct rtl8169_stats rx_stats;
657 struct rtl8169_stats tx_stats;
1da177e4
LT		 658 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
659 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
660 dma_addr_t TxPhyAddr;
661 dma_addr_t RxPhyAddr;
6f0333b8 662 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 663 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4 664 u16 cp_cmd;
da78dbff
FR		 665
666 u16 event_slow;
50970831 667 const struct rtl_coalesce_info *coalesce_info;
c0e45c1c 668
669 struct mdio_ops {
24192210
FR		 670 void (*write)(struct rtl8169_private *, int, int);
671 int (*read)(struct rtl8169_private *, int);
c0e45c1c 672 } mdio_ops;
673
d58d46b5
FR		 674 struct jumbo_ops {
675 void (*enable)(struct rtl8169_private *);
676 void (*disable)(struct rtl8169_private *);
677 } jumbo_ops;
678
61cb532d 679 void (*hw_start)(struct rtl8169_private *tp);
5888d3fc 680 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 681
682 struct {
da78dbff
FR		 683 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
684 struct mutex mutex;
4422bcd4
FR		 685 struct work_struct work;
686 } wk;
687
f7ffa9ae 688 unsigned supports_gmii:1;
f1e911d5 689 struct mii_bus *mii_bus;
42020320
CV		 690 dma_addr_t counters_phys_addr;
691 struct rtl8169_counters *counters;
6e85d5ad 692 struct rtl8169_tc_offsets tc_offset;
e1759441 693 u32 saved_wolopts;
f1e02ed1 694
b6ffd97f
FR		 695 struct rtl_fw {
696 const struct firmware *fw;
1c361efb
FR		 697
698#define RTL_VER_SIZE 32
699
700 char version[RTL_VER_SIZE];
701
702 struct rtl_fw_phy_action {
703 __le32 *code;
704 size_t size;
705 } phy_action;
b6ffd97f 706 } *rtl_fw;
497888cf 707#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 708
709 u32 ocp_base;
1da177e4
LT		 710};
711
979b6c13 712MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 713MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 714module_param(use_dac, int, 0);
4300e8c7 715MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 716module_param_named(debug, debug.msg_enable, int, 0);
717MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4 718MODULE_LICENSE("GPL");
bca03d5f 719MODULE_FIRMWARE(FIRMWARE_8168D_1);
720MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 721MODULE_FIRMWARE(FIRMWARE_8168E_1);
722MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 723MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 724MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 725MODULE_FIRMWARE(FIRMWARE_8168F_1);
726MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 727MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 728MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 729MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 730MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 731MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 732MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 733MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 734MODULE_FIRMWARE(FIRMWARE_8168H_1);
735MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 736MODULE_FIRMWARE(FIRMWARE_8107E_1);
737MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 738
1e1205b7
HK		 739static inline struct device *tp_to_dev(struct rtl8169_private *tp)
740{
741 return &tp->pci_dev->dev;
742}
743
da78dbff
FR		 744static void rtl_lock_work(struct rtl8169_private *tp)
745{
746 mutex_lock(&tp->wk.mutex);
747}
748
749static void rtl_unlock_work(struct rtl8169_private *tp)
750{
751 mutex_unlock(&tp->wk.mutex);
752}
753
cb73200c 754static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
d58d46b5 755{
cb73200c 756 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
7d7903b2 757 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 758}
759
ffc46952
FR		 760struct rtl_cond {
761 bool (*check)(struct rtl8169_private *);
762 const char *msg;
763};
764
765static void rtl_udelay(unsigned int d)
766{
767 udelay(d);
768}
769
770static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
771 void (*delay)(unsigned int), unsigned int d, int n,
772 bool high)
773{
774 int i;
775
776 for (i = 0; i < n; i++) {
777 delay(d);
778 if (c->check(tp) == high)
779 return true;
780 }
82e316ef
FR		 781 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
782 c->msg, !high, n, d);
ffc46952
FR		 783 return false;
784}
785
786static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
787 const struct rtl_cond *c,
788 unsigned int d, int n)
789{
790 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
791}
792
793static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
794 const struct rtl_cond *c,
795 unsigned int d, int n)
796{
797 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
798}
799
800static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
801 const struct rtl_cond *c,
802 unsigned int d, int n)
803{
804 return rtl_loop_wait(tp, c, msleep, d, n, true);
805}
806
807static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
808 const struct rtl_cond *c,
809 unsigned int d, int n)
810{
811 return rtl_loop_wait(tp, c, msleep, d, n, false);
812}
813
814#define DECLARE_RTL_COND(name) \
815static bool name ## _check(struct rtl8169_private *); \
816 \
817static const struct rtl_cond name = { \
818 .check = name ## _check, \
819 .msg = #name \
820}; \
821 \
822static bool name ## _check(struct rtl8169_private *tp)
823
c558386b
HW		 824static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
825{
826 if (reg & 0xffff0001) {
827 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
828 return true;
829 }
830 return false;
831}
832
833DECLARE_RTL_COND(rtl_ocp_gphy_cond)
834{
1ef7286e 835 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
c558386b
HW		 836}
837
838static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
839{
c558386b
HW		 840 if (rtl_ocp_reg_failure(tp, reg))
841 return;
842
1ef7286e 843 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 844
845 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
846}
847
848static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
849{
c558386b
HW		 850 if (rtl_ocp_reg_failure(tp, reg))
851 return 0;
852
1ef7286e 853 RTL_W32(tp, GPHY_OCP, reg << 15);
c558386b
HW		 854
855 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1ef7286e 856 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
c558386b
HW		 857}
858
c558386b
HW		 859static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
860{
c558386b
HW		 861 if (rtl_ocp_reg_failure(tp, reg))
862 return;
863
1ef7286e 864 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 865}
866
867static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
868{
c558386b
HW		 869 if (rtl_ocp_reg_failure(tp, reg))
870 return 0;
871
1ef7286e 872 RTL_W32(tp, OCPDR, reg << 15);
c558386b 873
1ef7286e 874 return RTL_R32(tp, OCPDR);
c558386b
HW		 875}
876
877#define OCP_STD_PHY_BASE 0xa400
878
879static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
880{
881 if (reg == 0x1f) {
882 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
883 return;
884 }
885
886 if (tp->ocp_base != OCP_STD_PHY_BASE)
887 reg -= 0x10;
888
889 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
890}
891
892static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
893{
894 if (tp->ocp_base != OCP_STD_PHY_BASE)
895 reg -= 0x10;
896
897 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
898}
899
eee3786f 900static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
901{
902 if (reg == 0x1f) {
903 tp->ocp_base = value << 4;
904 return;
905 }
906
907 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
908}
909
910static int mac_mcu_read(struct rtl8169_private *tp, int reg)
911{
912 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
913}
914
ffc46952
FR		 915DECLARE_RTL_COND(rtl_phyar_cond)
916{
1ef7286e 917 return RTL_R32(tp, PHYAR) & 0x80000000;
ffc46952
FR		 918}
919
24192210 920static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 921{
1ef7286e 922 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 923
ffc46952 924 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 925 /*
81a95f04
TT		 926 * According to hardware specs a 20us delay is required after write
927 * complete indication, but before sending next command.
024a07ba 928 */
81a95f04 929 udelay(20);
1da177e4
LT		 930}
931
24192210 932static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 933{
ffc46952 934 int value;
1da177e4 935
1ef7286e 936 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 937
ffc46952 938 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1ef7286e 939 RTL_R32(tp, PHYAR) & 0xffff : ~0;
ffc46952 940
81a95f04
TT		 941 /*
942 * According to hardware specs a 20us delay is required after read
943 * complete indication, but before sending next command.
944 */
945 udelay(20);
946
1da177e4
LT		 947 return value;
948}
949
935e2218
CHL		 950DECLARE_RTL_COND(rtl_ocpar_cond)
951{
1ef7286e 952 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
935e2218
CHL		 953}
954
24192210 955static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 956{
1ef7286e
AS		 957 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
958 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
959 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 960
ffc46952 961 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 962}
963
24192210 964static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 965{
24192210
FR		 966 r8168dp_1_mdio_access(tp, reg,
967 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 968}
969
24192210 970static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 971{
24192210 972 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 973
974 mdelay(1);
1ef7286e
AS		 975 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
976 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 977
ffc46952 978 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1ef7286e 979 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 980}
981
e6de30d6 982#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
983
1ef7286e 984static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
e6de30d6 985{
1ef7286e 986 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 987}
988
1ef7286e 989static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
e6de30d6 990{
1ef7286e 991 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 992}
993
24192210 994static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 995{
1ef7286e 996 r8168dp_2_mdio_start(tp);
e6de30d6 997
24192210 998 r8169_mdio_write(tp, reg, value);
e6de30d6 999
1ef7286e 1000 r8168dp_2_mdio_stop(tp);
e6de30d6 1001}
1002
24192210 1003static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1004{
1005 int value;
1006
1ef7286e 1007 r8168dp_2_mdio_start(tp);
e6de30d6 1008
24192210 1009 value = r8169_mdio_read(tp, reg);
e6de30d6 1010
1ef7286e 1011 r8168dp_2_mdio_stop(tp);
e6de30d6 1012
1013 return value;
1014}
1015
4da19633 1016static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1017{
24192210 1018 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1019}
1020
4da19633 1021static int rtl_readphy(struct rtl8169_private *tp, int location)
1022{
24192210 1023 return tp->mdio_ops.read(tp, location);
4da19633 1024}
1025
1026static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1027{
1028 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1029}
1030
76564428 1031static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1032{
1033 int val;
1034
4da19633 1035 val = rtl_readphy(tp, reg_addr);
76564428 1036 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1037}
1038
ffc46952
FR		 1039DECLARE_RTL_COND(rtl_ephyar_cond)
1040{
1ef7286e 1041 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
ffc46952
FR		 1042}
1043
fdf6fc06 1044static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1045{
1ef7286e 1046 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
dacf8154
FR		 1047 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1048
ffc46952
FR		 1049 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1050
1051 udelay(10);
dacf8154
FR		 1052}
1053
fdf6fc06 1054static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1055{
1ef7286e 1056 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
dacf8154 1057
ffc46952 1058 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1ef7286e 1059 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1060}
1061
935e2218
CHL		 1062DECLARE_RTL_COND(rtl_eriar_cond)
1063{
1ef7286e 1064 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
935e2218
CHL		 1065}
1066
fdf6fc06
FR		 1067static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1068 u32 val, int type)
133ac40a 1069{
133ac40a 1070 BUG_ON((addr & 3) || (mask == 0));
1ef7286e
AS		 1071 RTL_W32(tp, ERIDR, val);
1072 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
133ac40a 1073
ffc46952 1074 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1075}
1076
fdf6fc06 1077static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1078{
1ef7286e 1079 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
133ac40a 1080
ffc46952 1081 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1ef7286e 1082 RTL_R32(tp, ERIDR) : ~0;
133ac40a
HW		 1083}
1084
706123d0 1085static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1086 u32 m, int type)
133ac40a
HW		 1087{
1088 u32 val;
1089
fdf6fc06
FR		 1090 val = rtl_eri_read(tp, addr, type);
1091 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1092}
1093
935e2218
CHL		 1094static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1095{
1ef7286e 1096 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218 1097 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1ef7286e 1098 RTL_R32(tp, OCPDR) : ~0;
935e2218
CHL		 1099}
1100
1101static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1102{
1103 return rtl_eri_read(tp, reg, ERIAR_OOB);
1104}
1105
1106static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1107{
1108 switch (tp->mac_version) {
1109 case RTL_GIGA_MAC_VER_27:
1110 case RTL_GIGA_MAC_VER_28:
1111 case RTL_GIGA_MAC_VER_31:
1112 return r8168dp_ocp_read(tp, mask, reg);
1113 case RTL_GIGA_MAC_VER_49:
1114 case RTL_GIGA_MAC_VER_50:
1115 case RTL_GIGA_MAC_VER_51:
1116 return r8168ep_ocp_read(tp, mask, reg);
1117 default:
1118 BUG();
1119 return ~0;
1120 }
1121}
1122
1123static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1124 u32 data)
1125{
1ef7286e
AS		 1126 RTL_W32(tp, OCPDR, data);
1127 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218
CHL		 1128 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1129}
1130
1131static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1132 u32 data)
1133{
1134 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1135 data, ERIAR_OOB);
1136}
1137
1138static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1139{
1140 switch (tp->mac_version) {
1141 case RTL_GIGA_MAC_VER_27:
1142 case RTL_GIGA_MAC_VER_28:
1143 case RTL_GIGA_MAC_VER_31:
1144 r8168dp_ocp_write(tp, mask, reg, data);
1145 break;
1146 case RTL_GIGA_MAC_VER_49:
1147 case RTL_GIGA_MAC_VER_50:
1148 case RTL_GIGA_MAC_VER_51:
1149 r8168ep_ocp_write(tp, mask, reg, data);
1150 break;
1151 default:
1152 BUG();
1153 break;
1154 }
1155}
1156
2a9b4d96
CHL		 1157static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1158{
1159 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1160
1161 ocp_write(tp, 0x1, 0x30, 0x00000001);
1162}
1163
1164#define OOB_CMD_RESET 0x00
1165#define OOB_CMD_DRIVER_START 0x05
1166#define OOB_CMD_DRIVER_STOP 0x06
1167
1168static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1169{
1170 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1171}
1172
1173DECLARE_RTL_COND(rtl_ocp_read_cond)
1174{
1175 u16 reg;
1176
1177 reg = rtl8168_get_ocp_reg(tp);
1178
1179 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1180}
1181
935e2218 1182DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1183{
935e2218
CHL		 1184 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1185}
1186
1187DECLARE_RTL_COND(rtl_ocp_tx_cond)
1188{
1ef7286e 1189 return RTL_R8(tp, IBISR0) & 0x20;
935e2218 1190}
2a9b4d96 1191
003609da
CHL		 1192static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1193{
1ef7286e 1194 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
086ca23d 1195 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1ef7286e
AS		 1196 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1197 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
003609da
CHL		 1198}
1199
935e2218
CHL		 1200static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1201{
1202 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
2a9b4d96
CHL		 1203 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1204}
1205
935e2218 1206static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1207{
935e2218
CHL		 1208 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1209 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1210 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1211}
1212
1213static void rtl8168_driver_start(struct rtl8169_private *tp)
1214{
1215 switch (tp->mac_version) {
1216 case RTL_GIGA_MAC_VER_27:
1217 case RTL_GIGA_MAC_VER_28:
1218 case RTL_GIGA_MAC_VER_31:
1219 rtl8168dp_driver_start(tp);
1220 break;
1221 case RTL_GIGA_MAC_VER_49:
1222 case RTL_GIGA_MAC_VER_50:
1223 case RTL_GIGA_MAC_VER_51:
1224 rtl8168ep_driver_start(tp);
1225 break;
1226 default:
1227 BUG();
1228 break;
1229 }
1230}
2a9b4d96 1231
935e2218
CHL		 1232static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1233{
1234 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
2a9b4d96
CHL		 1235 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1236}
1237
935e2218
CHL		 1238static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1239{
003609da 1240 rtl8168ep_stop_cmac(tp);
935e2218
CHL		 1241 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1242 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1243 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1244}
1245
1246static void rtl8168_driver_stop(struct rtl8169_private *tp)
1247{
1248 switch (tp->mac_version) {
1249 case RTL_GIGA_MAC_VER_27:
1250 case RTL_GIGA_MAC_VER_28:
1251 case RTL_GIGA_MAC_VER_31:
1252 rtl8168dp_driver_stop(tp);
1253 break;
1254 case RTL_GIGA_MAC_VER_49:
1255 case RTL_GIGA_MAC_VER_50:
1256 case RTL_GIGA_MAC_VER_51:
1257 rtl8168ep_driver_stop(tp);
1258 break;
1259 default:
1260 BUG();
1261 break;
1262 }
1263}
1264
9dbe7896 1265static bool r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1266{
1267 u16 reg = rtl8168_get_ocp_reg(tp);
1268
9dbe7896 1269 return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
2a9b4d96
CHL		 1270}
1271
9dbe7896 1272static bool r8168ep_check_dash(struct rtl8169_private *tp)
935e2218 1273{
9dbe7896 1274 return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
935e2218
CHL		 1275}
1276
9dbe7896 1277static bool r8168_check_dash(struct rtl8169_private *tp)
935e2218
CHL		 1278{
1279 switch (tp->mac_version) {
1280 case RTL_GIGA_MAC_VER_27:
1281 case RTL_GIGA_MAC_VER_28:
1282 case RTL_GIGA_MAC_VER_31:
1283 return r8168dp_check_dash(tp);
1284 case RTL_GIGA_MAC_VER_49:
1285 case RTL_GIGA_MAC_VER_50:
1286 case RTL_GIGA_MAC_VER_51:
1287 return r8168ep_check_dash(tp);
1288 default:
9dbe7896 1289 return false;
935e2218
CHL		 1290 }
1291}
1292
c28aa385 1293struct exgmac_reg {
1294 u16 addr;
1295 u16 mask;
1296 u32 val;
1297};
1298
fdf6fc06 1299static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1300 const struct exgmac_reg *r, int len)
1301{
1302 while (len-- > 0) {
fdf6fc06 1303 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1304 r++;
1305 }
1306}
1307
ffc46952
FR		 1308DECLARE_RTL_COND(rtl_efusear_cond)
1309{
1ef7286e 1310 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
ffc46952
FR		 1311}
1312
fdf6fc06 1313static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1314{
1ef7286e 1315 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
daf9df6d 1316
ffc46952 1317 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1ef7286e 1318 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1319}
1320
9085cdfa
FR		 1321static u16 rtl_get_events(struct rtl8169_private *tp)
1322{
1ef7286e 1323 return RTL_R16(tp, IntrStatus);
9085cdfa
FR		 1324}
1325
1326static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1327{
1ef7286e 1328 RTL_W16(tp, IntrStatus, bits);
9085cdfa
FR		 1329 mmiowb();
1330}
1331
1332static void rtl_irq_disable(struct rtl8169_private *tp)
1333{
1ef7286e 1334 RTL_W16(tp, IntrMask, 0);
9085cdfa
FR		 1335 mmiowb();
1336}
1337
3e990ff5
FR		 1338static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1339{
1ef7286e 1340 RTL_W16(tp, IntrMask, bits);
3e990ff5
FR		 1341}
1342
da78dbff
FR		 1343#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1344#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1345#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1346
1347static void rtl_irq_enable_all(struct rtl8169_private *tp)
1348{
1349 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1350}
1351
811fd301 1352static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1353{
9085cdfa 1354 rtl_irq_disable(tp);
da78dbff 1355 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1ef7286e 1356 RTL_R8(tp, ChipCmd);
1da177e4
LT		 1357}
1358
70090424
HW		 1359static void rtl_link_chg_patch(struct rtl8169_private *tp)
1360{
70090424 1361 struct net_device *dev = tp->dev;
29a12b49 1362 struct phy_device *phydev = dev->phydev;
70090424
HW		 1363
1364 if (!netif_running(dev))
1365 return;
1366
b3d7b2f2
HW		 1367 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1368 tp->mac_version == RTL_GIGA_MAC_VER_38) {
29a12b49 1369 if (phydev->speed == SPEED_1000) {
fdf6fc06
FR		 1370 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1371 ERIAR_EXGMAC);
1372 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1373 ERIAR_EXGMAC);
29a12b49 1374 } else if (phydev->speed == SPEED_100) {
fdf6fc06
FR		 1375 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1376 ERIAR_EXGMAC);
1377 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1378 ERIAR_EXGMAC);
70090424 1379 } else {
fdf6fc06
FR		 1380 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1381 ERIAR_EXGMAC);
1382 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1383 ERIAR_EXGMAC);
70090424
HW		 1384 }
1385 /* Reset packet filter */
706123d0 1386 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1387 ERIAR_EXGMAC);
706123d0 1388 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1389 ERIAR_EXGMAC);
c2218925
HW		 1390 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1391 tp->mac_version == RTL_GIGA_MAC_VER_36) {
29a12b49 1392 if (phydev->speed == SPEED_1000) {
fdf6fc06
FR		 1393 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1394 ERIAR_EXGMAC);
1395 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1396 ERIAR_EXGMAC);
c2218925 1397 } else {
fdf6fc06
FR		 1398 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1399 ERIAR_EXGMAC);
1400 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1401 ERIAR_EXGMAC);
c2218925 1402 }
7e18dca1 1403 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
29a12b49 1404 if (phydev->speed == SPEED_10) {
fdf6fc06
FR		 1405 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1406 ERIAR_EXGMAC);
1407 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1408 ERIAR_EXGMAC);
7e18dca1 1409 } else {
fdf6fc06
FR		 1410 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1411 ERIAR_EXGMAC);
7e18dca1 1412 }
70090424
HW		 1413 }
1414}
1415
e1759441
RW		 1416#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1417
1418static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1419{
61a4dcc2 1420 u8 options;
e1759441 1421 u32 wolopts = 0;
61a4dcc2 1422
1ef7286e 1423 options = RTL_R8(tp, Config1);
61a4dcc2 1424 if (!(options & PMEnable))
e1759441 1425 return 0;
61a4dcc2 1426
1ef7286e 1427 options = RTL_R8(tp, Config3);
61a4dcc2 1428 if (options & LinkUp)
e1759441 1429 wolopts |= WAKE_PHY;
6e1d0b89 1430 switch (tp->mac_version) {
2a71883c
HK		 1431 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1432 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1433 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1434 wolopts |= WAKE_MAGIC;
1435 break;
1436 default:
1437 if (options & MagicPacket)
1438 wolopts |= WAKE_MAGIC;
1439 break;
1440 }
61a4dcc2 1441
1ef7286e 1442 options = RTL_R8(tp, Config5);
61a4dcc2 1443 if (options & UWF)
e1759441 1444 wolopts |= WAKE_UCAST;
61a4dcc2 1445 if (options & BWF)
e1759441 1446 wolopts |= WAKE_BCAST;
61a4dcc2 1447 if (options & MWF)
e1759441 1448 wolopts |= WAKE_MCAST;
61a4dcc2 1449
e1759441 1450 return wolopts;
61a4dcc2
FR		 1451}
1452
e1759441 1453static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1454{
1455 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1456
da78dbff 1457 rtl_lock_work(tp);
e1759441 1458 wol->supported = WAKE_ANY;
433f9d0d 1459 wol->wolopts = tp->saved_wolopts;
da78dbff 1460 rtl_unlock_work(tp);
e1759441
RW		 1461}
1462
1463static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1464{
6e1d0b89 1465 unsigned int i, tmp;
350f7596 1466 static const struct {
61a4dcc2
FR		 1467 u32 opt;
1468 u16 reg;
1469 u8 mask;
1470 } cfg[] = {
61a4dcc2 1471 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1472 { WAKE_UCAST, Config5, UWF },
1473 { WAKE_BCAST, Config5, BWF },
1474 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1475 { WAKE_ANY, Config5, LanWake },
1476 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1477 };
851e6022 1478 u8 options;
61a4dcc2 1479
1ef7286e 1480 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
61a4dcc2 1481
6e1d0b89 1482 switch (tp->mac_version) {
2a71883c
HK		 1483 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1484 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1485 tmp = ARRAY_SIZE(cfg) - 1;
1486 if (wolopts & WAKE_MAGIC)
706123d0 1487 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1488 0x0dc,
1489 ERIAR_MASK_0100,
1490 MagicPacket_v2,
1491 0x0000,
1492 ERIAR_EXGMAC);
1493 else
706123d0 1494 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1495 0x0dc,
1496 ERIAR_MASK_0100,
1497 0x0000,
1498 MagicPacket_v2,
1499 ERIAR_EXGMAC);
1500 break;
1501 default:
1502 tmp = ARRAY_SIZE(cfg);
1503 break;
1504 }
1505
1506 for (i = 0; i < tmp; i++) {
1ef7286e 1507 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
e1759441 1508 if (wolopts & cfg[i].opt)
61a4dcc2 1509 options |= cfg[i].mask;
1ef7286e 1510 RTL_W8(tp, cfg[i].reg, options);
61a4dcc2
FR		 1511 }
1512
851e6022
FR		 1513 switch (tp->mac_version) {
1514 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1ef7286e 1515 options = RTL_R8(tp, Config1) & ~PMEnable;
851e6022
FR		 1516 if (wolopts)
1517 options |= PMEnable;
1ef7286e 1518 RTL_W8(tp, Config1, options);
851e6022
FR		 1519 break;
1520 default:
1ef7286e 1521 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
d387b427
FR		 1522 if (wolopts)
1523 options |= PME_SIGNAL;
1ef7286e 1524 RTL_W8(tp, Config2, options);
851e6022
FR		 1525 break;
1526 }
1527
1ef7286e 1528 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
e1759441
RW		 1529}
1530
1531static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1532{
1533 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1534 struct device *d = tp_to_dev(tp);
5fa80a32 1535
2f533f6b
HK		 1536 if (wol->wolopts & ~WAKE_ANY)
1537 return -EINVAL;
1538
5fa80a32 1539 pm_runtime_get_noresume(d);
e1759441 1540
da78dbff 1541 rtl_lock_work(tp);
61a4dcc2 1542
2f533f6b 1543 tp->saved_wolopts = wol->wolopts;
433f9d0d 1544
5fa80a32 1545 if (pm_runtime_active(d))
433f9d0d 1546 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff
FR		 1547
1548 rtl_unlock_work(tp);
61a4dcc2 1549
433f9d0d 1550 device_set_wakeup_enable(d, tp->saved_wolopts);
ea80907f 1551
5fa80a32
CHL		 1552 pm_runtime_put_noidle(d);
1553
61a4dcc2
FR		 1554 return 0;
1555}
1556
31bd204f
FR		 1557static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1558{
85bffe6c 1559 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1560}
1561
1da177e4
LT		 1562static void rtl8169_get_drvinfo(struct net_device *dev,
1563 struct ethtool_drvinfo *info)
1564{
1565 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1566 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1567
68aad78c 1568 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
68aad78c 1569 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1570 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1571 if (!IS_ERR_OR_NULL(rtl_fw))
1572 strlcpy(info->fw_version, rtl_fw->version,
1573 sizeof(info->fw_version));
1da177e4
LT		 1574}
1575
1576static int rtl8169_get_regs_len(struct net_device *dev)
1577{
1578 return R8169_REGS_SIZE;
1579}
1580
c8f44aff
MM		 1581static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1582 netdev_features_t features)
1da177e4 1583{
d58d46b5
FR		 1584 struct rtl8169_private *tp = netdev_priv(dev);
1585
2b7b4318 1586 if (dev->mtu > TD_MSS_MAX)
350fb32a 1587 features &= ~NETIF_F_ALL_TSO;
1da177e4 1588
d58d46b5 1589 if (dev->mtu > JUMBO_1K &&
6ed0e08f 1590 tp->mac_version > RTL_GIGA_MAC_VER_06)
d58d46b5
FR		 1591 features &= ~NETIF_F_IP_CSUM;
1592
350fb32a 1593 return features;
1da177e4
LT		 1594}
1595
a3984578
HK		 1596static int rtl8169_set_features(struct net_device *dev,
1597 netdev_features_t features)
1da177e4
LT		 1598{
1599 struct rtl8169_private *tp = netdev_priv(dev);
929a031d 1600 u32 rx_config;
1da177e4 1601
a3984578
HK		 1602 rtl_lock_work(tp);
1603
1ef7286e 1604 rx_config = RTL_R32(tp, RxConfig);
929a031d 1605 if (features & NETIF_F_RXALL)
1606 rx_config |= (AcceptErr | AcceptRunt);
1607 else
1608 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 1609
1ef7286e 1610 RTL_W32(tp, RxConfig, rx_config);
350fb32a 1611
929a031d 1612 if (features & NETIF_F_RXCSUM)
1613 tp->cp_cmd |= RxChkSum;
1614 else
1615 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1616
929a031d 1617 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1618 tp->cp_cmd |= RxVlan;
1619 else
1620 tp->cp_cmd &= ~RxVlan;
1621
1ef7286e
AS		 1622 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1623 RTL_R16(tp, CPlusCmd);
1da177e4 1624
da78dbff 1625 rtl_unlock_work(tp);
1da177e4
LT		 1626
1627 return 0;
1628}
1629
810f4893 1630static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1631{
df8a39de
JP		 1632 return (skb_vlan_tag_present(skb)) ?
1633 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 1634}
1635
7a8fc77b 1636static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1637{
1638 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1639
7a8fc77b 1640 if (opts2 & RxVlanTag)
86a9bad3 1641 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1642}
1643
1da177e4
LT		 1644static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1645 void *p)
1646{
5b0384f4 1647 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 1648 u32 __iomem *data = tp->mmio_addr;
1649 u32 *dw = p;
1650 int i;
1da177e4 1651
da78dbff 1652 rtl_lock_work(tp);
15edae91
PW		 1653 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1654 memcpy_fromio(dw++, data++, 4);
da78dbff 1655 rtl_unlock_work(tp);
1da177e4
LT		 1656}
1657
b57b7e5a
SH		 1658static u32 rtl8169_get_msglevel(struct net_device *dev)
1659{
1660 struct rtl8169_private *tp = netdev_priv(dev);
1661
1662 return tp->msg_enable;
1663}
1664
1665static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1666{
1667 struct rtl8169_private *tp = netdev_priv(dev);
1668
1669 tp->msg_enable = value;
1670}
1671
d4a3a0fc
SH		 1672static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1673 "tx_packets",
1674 "rx_packets",
1675 "tx_errors",
1676 "rx_errors",
1677 "rx_missed",
1678 "align_errors",
1679 "tx_single_collisions",
1680 "tx_multi_collisions",
1681 "unicast",
1682 "broadcast",
1683 "multicast",
1684 "tx_aborted",
1685 "tx_underrun",
1686};
1687
b9f2c044 1688static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1689{
b9f2c044
JG		 1690 switch (sset) {
1691 case ETH_SS_STATS:
1692 return ARRAY_SIZE(rtl8169_gstrings);
1693 default:
1694 return -EOPNOTSUPP;
1695 }
d4a3a0fc
SH		 1696}
1697
42020320 1698DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 1699{
1ef7286e 1700 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 1701}
1702
e71c9ce2 1703static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
6e85d5ad 1704{
42020320
CV		 1705 dma_addr_t paddr = tp->counters_phys_addr;
1706 u32 cmd;
6e85d5ad 1707
1ef7286e
AS		 1708 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1709 RTL_R32(tp, CounterAddrHigh);
42020320 1710 cmd = (u64)paddr & DMA_BIT_MASK(32);
1ef7286e
AS		 1711 RTL_W32(tp, CounterAddrLow, cmd);
1712 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
6e85d5ad 1713
a78e9366 1714 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 1715}
1716
e71c9ce2 1717static bool rtl8169_reset_counters(struct rtl8169_private *tp)
6e85d5ad 1718{
6e85d5ad
CV		 1719 /*
1720 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1721 * tally counters.
1722 */
1723 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1724 return true;
1725
e71c9ce2 1726 return rtl8169_do_counters(tp, CounterReset);
ffc46952
FR		 1727}
1728
e71c9ce2 1729static bool rtl8169_update_counters(struct rtl8169_private *tp)
d4a3a0fc 1730{
355423d0
IV		 1731 /*
1732 * Some chips are unable to dump tally counters when the receiver
1733 * is disabled.
1734 */
1ef7286e 1735 if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
6e85d5ad 1736 return true;
d4a3a0fc 1737
e71c9ce2 1738 return rtl8169_do_counters(tp, CounterDump);
6e85d5ad
CV		 1739}
1740
e71c9ce2 1741static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
6e85d5ad 1742{
42020320 1743 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 1744 bool ret = false;
1745
1746 /*
1747 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1748 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1749 * reset by a power cycle, while the counter values collected by the
1750 * driver are reset at every driver unload/load cycle.
1751 *
1752 * To make sure the HW values returned by @get_stats64 match the SW
1753 * values, we collect the initial values at first open(*) and use them
1754 * as offsets to normalize the values returned by @get_stats64.
1755 *
1756 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1757 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1758 * set at open time by rtl_hw_start.
1759 */
1760
1761 if (tp->tc_offset.inited)
1762 return true;
1763
1764 /* If both, reset and update fail, propagate to caller. */
e71c9ce2 1765 if (rtl8169_reset_counters(tp))
6e85d5ad
CV		 1766 ret = true;
1767
e71c9ce2 1768 if (rtl8169_update_counters(tp))
6e85d5ad
CV		 1769 ret = true;
1770
42020320
CV		 1771 tp->tc_offset.tx_errors = counters->tx_errors;
1772 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1773 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 1774 tp->tc_offset.inited = true;
1775
1776 return ret;
d4a3a0fc
SH		 1777}
1778
355423d0
IV		 1779static void rtl8169_get_ethtool_stats(struct net_device *dev,
1780 struct ethtool_stats *stats, u64 *data)
1781{
1782 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1783 struct device *d = tp_to_dev(tp);
42020320 1784 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 1785
1786 ASSERT_RTNL();
1787
e0636236
CHL		 1788 pm_runtime_get_noresume(d);
1789
1790 if (pm_runtime_active(d))
e71c9ce2 1791 rtl8169_update_counters(tp);
e0636236
CHL		 1792
1793 pm_runtime_put_noidle(d);
355423d0 1794
42020320
CV		 1795 data[0] = le64_to_cpu(counters->tx_packets);
1796 data[1] = le64_to_cpu(counters->rx_packets);
1797 data[2] = le64_to_cpu(counters->tx_errors);
1798 data[3] = le32_to_cpu(counters->rx_errors);
1799 data[4] = le16_to_cpu(counters->rx_missed);
1800 data[5] = le16_to_cpu(counters->align_errors);
1801 data[6] = le32_to_cpu(counters->tx_one_collision);
1802 data[7] = le32_to_cpu(counters->tx_multi_collision);
1803 data[8] = le64_to_cpu(counters->rx_unicast);
1804 data[9] = le64_to_cpu(counters->rx_broadcast);
1805 data[10] = le32_to_cpu(counters->rx_multicast);
1806 data[11] = le16_to_cpu(counters->tx_aborted);
1807 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 1808}
1809
d4a3a0fc
SH		 1810static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1811{
1812 switch(stringset) {
1813 case ETH_SS_STATS:
1814 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1815 break;
1816 }
1817}
1818
50970831
FR		 1819/*
1820 * Interrupt coalescing
1821 *
1822 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1823 * > 8169, 8168 and 810x line of chipsets
1824 *
1825 * 8169, 8168, and 8136(810x) serial chipsets support it.
1826 *
1827 * > 2 - the Tx timer unit at gigabit speed
1828 *
1829 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1830 * (0xe0) bit 1 and bit 0.
1831 *
1832 * For 8169
1833 * bit[1:0] \ speed 1000M 100M 10M
1834 * 0 0 320ns 2.56us 40.96us
1835 * 0 1 2.56us 20.48us 327.7us
1836 * 1 0 5.12us 40.96us 655.4us
1837 * 1 1 10.24us 81.92us 1.31ms
1838 *
1839 * For the other
1840 * bit[1:0] \ speed 1000M 100M 10M
1841 * 0 0 5us 2.56us 40.96us
1842 * 0 1 40us 20.48us 327.7us
1843 * 1 0 80us 40.96us 655.4us
1844 * 1 1 160us 81.92us 1.31ms
1845 */
1846
1847/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1848struct rtl_coalesce_scale {
1849 /* Rx / Tx */
1850 u32 nsecs[2];
1851};
1852
1853/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1854struct rtl_coalesce_info {
1855 u32 speed;
1856 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1857};
1858
1859/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1860#define rxtx_x1822(r, t) { \
1861 {{(r), (t)}}, \
1862 {{(r)*8, (t)*8}}, \
1863 {{(r)*8*2, (t)*8*2}}, \
1864 {{(r)*8*2*2, (t)*8*2*2}}, \
1865}
1866static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1867 /* speed delays: rx00 tx00 */
1868 { SPEED_10, rxtx_x1822(40960, 40960) },
1869 { SPEED_100, rxtx_x1822( 2560, 2560) },
1870 { SPEED_1000, rxtx_x1822( 320, 320) },
1871 { 0 },
1872};
1873
1874static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1875 /* speed delays: rx00 tx00 */
1876 { SPEED_10, rxtx_x1822(40960, 40960) },
1877 { SPEED_100, rxtx_x1822( 2560, 2560) },
1878 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1879 { 0 },
1880};
1881#undef rxtx_x1822
1882
1883/* get rx/tx scale vector corresponding to current speed */
1884static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1885{
1886 struct rtl8169_private *tp = netdev_priv(dev);
1887 struct ethtool_link_ksettings ecmd;
1888 const struct rtl_coalesce_info *ci;
1889 int rc;
1890
45772433 1891 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
50970831
FR		 1892 if (rc < 0)
1893 return ERR_PTR(rc);
1894
1895 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1896 if (ecmd.base.speed == ci->speed) {
1897 return ci;
1898 }
1899 }
1900
1901 return ERR_PTR(-ELNRNG);
1902}
1903
1904static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1905{
1906 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1907 const struct rtl_coalesce_info *ci;
1908 const struct rtl_coalesce_scale *scale;
1909 struct {
1910 u32 *max_frames;
1911 u32 *usecs;
1912 } coal_settings [] = {
1913 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1914 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1915 }, *p = coal_settings;
1916 int i;
1917 u16 w;
1918
1919 memset(ec, 0, sizeof(*ec));
1920
1921 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1922 ci = rtl_coalesce_info(dev);
1923 if (IS_ERR(ci))
1924 return PTR_ERR(ci);
1925
0ae0974e 1926 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
50970831
FR		 1927
1928 /* read IntrMitigate and adjust according to scale */
1ef7286e 1929 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
50970831
FR		 1930 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1931 w >>= RTL_COALESCE_SHIFT;
1932 *p->usecs = w & RTL_COALESCE_MASK;
1933 }
1934
1935 for (i = 0; i < 2; i++) {
1936 p = coal_settings + i;
1937 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1938
1939 /*
1940 * ethtool_coalesce says it is illegal to set both usecs and
1941 * max_frames to 0.
1942 */
1943 if (!*p->usecs && !*p->max_frames)
1944 *p->max_frames = 1;
1945 }
1946
1947 return 0;
1948}
1949
1950/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1951static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1952 struct net_device *dev, u32 nsec, u16 *cp01)
1953{
1954 const struct rtl_coalesce_info *ci;
1955 u16 i;
1956
1957 ci = rtl_coalesce_info(dev);
1958 if (IS_ERR(ci))
1959 return ERR_CAST(ci);
1960
1961 for (i = 0; i < 4; i++) {
1962 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1963 ci->scalev[i].nsecs[1]);
1964 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1965 *cp01 = i;
1966 return &ci->scalev[i];
1967 }
1968 }
1969
1970 return ERR_PTR(-EINVAL);
1971}
1972
1973static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1974{
1975 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1976 const struct rtl_coalesce_scale *scale;
1977 struct {
1978 u32 frames;
1979 u32 usecs;
1980 } coal_settings [] = {
1981 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1982 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1983 }, *p = coal_settings;
1984 u16 w = 0, cp01;
1985 int i;
1986
1987 scale = rtl_coalesce_choose_scale(dev,
1988 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1989 if (IS_ERR(scale))
1990 return PTR_ERR(scale);
1991
1992 for (i = 0; i < 2; i++, p++) {
1993 u32 units;
1994
1995 /*
1996 * accept max_frames=1 we returned in rtl_get_coalesce.
1997 * accept it not only when usecs=0 because of e.g. the following scenario:
1998 *
1999 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2000 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2001 * - then user does `ethtool -C eth0 rx-usecs 100`
2002 *
2003 * since ethtool sends to kernel whole ethtool_coalesce
2004 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2005 * we'll reject it below in `frames % 4 != 0`.
2006 */
2007 if (p->frames == 1) {
2008 p->frames = 0;
2009 }
2010
2011 units = p->usecs * 1000 / scale->nsecs[i];
2012 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2013 return -EINVAL;
2014
2015 w <<= RTL_COALESCE_SHIFT;
2016 w |= units;
2017 w <<= RTL_COALESCE_SHIFT;
2018 w |= p->frames >> 2;
2019 }
2020
2021 rtl_lock_work(tp);
2022
1ef7286e 2023 RTL_W16(tp, IntrMitigate, swab16(w));
50970831 2024
9a3c81fa 2025 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1ef7286e
AS		 2026 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2027 RTL_R16(tp, CPlusCmd);
50970831
FR		 2028
2029 rtl_unlock_work(tp);
2030
2031 return 0;
2032}
2033
7282d491 2034static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2035 .get_drvinfo = rtl8169_get_drvinfo,
2036 .get_regs_len = rtl8169_get_regs_len,
2037 .get_link = ethtool_op_get_link,
50970831
FR		 2038 .get_coalesce = rtl_get_coalesce,
2039 .set_coalesce = rtl_set_coalesce,
b57b7e5a
SH		 2040 .get_msglevel = rtl8169_get_msglevel,
2041 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2042 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2043 .get_wol = rtl8169_get_wol,
2044 .set_wol = rtl8169_set_wol,
d4a3a0fc 2045 .get_strings = rtl8169_get_strings,
b9f2c044 2046 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2047 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2048 .get_ts_info = ethtool_op_get_ts_info,
dd84957e 2049 .nway_reset = phy_ethtool_nway_reset,
45772433
HK		 2050 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2051 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1da177e4
LT		 2052};
2053
07d3f51f 2054static void rtl8169_get_mac_version(struct rtl8169_private *tp,
22148df0 2055 u8 default_version)
1da177e4 2056{
0e485150
FR		 2057 /*
2058 * The driver currently handles the 8168Bf and the 8168Be identically
2059 * but they can be identified more specifically through the test below
2060 * if needed:
2061 *
1ef7286e 2062 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2063 *
2064 * Same thing for the 8101Eb and the 8101Ec:
2065 *
1ef7286e 2066 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2067 */
3744100e 2068 static const struct rtl_mac_info {
1da177e4 2069 u32 mask;
e3cf0cc0 2070 u32 val;
1da177e4
LT		 2071 int mac_version;
2072 } mac_info[] = {
935e2218
CHL		 2073 /* 8168EP family. */
2074 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2075 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2076 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2077
6e1d0b89
CHL		 2078 /* 8168H family. */
2079 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2080 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2081
c558386b 2082 /* 8168G family. */
45dd95c4 2083 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2084 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2085 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2086 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2087
c2218925 2088 /* 8168F family. */
b3d7b2f2 2089 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2090 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2091 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2092
01dc7fec 2093 /* 8168E family. */
70090424 2094 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2095 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2096 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2097
5b538df9 2098 /* 8168D family. */
daf9df6d 2099 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2100 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2101
e6de30d6 2102 /* 8168DP family. */
2103 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2104 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2105 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2106
ef808d50 2107 /* 8168C family. */
ef3386f0 2108 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2109 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2110 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2111 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2112 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2113 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
ef808d50 2114 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2115
2116 /* 8168B family. */
2117 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
e3cf0cc0
FR		 2118 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2119 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2120
2121 /* 8101 family. */
5598bfe5 2122 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2123 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
5a5e4443
HW		 2124 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2125 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2126 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2127 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2128 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2129 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2130 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2131 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2132 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2133 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2134 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2135 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2136 /* FIXME: where did these entries come from ? -- FR */
2137 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2138 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2139
2140 /* 8110 family. */
2141 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2142 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2143 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2144 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2145 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2146 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2147
f21b75e9
JD		 2148 /* Catch-all */
2149 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2150 };
2151 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2152 u32 reg;
2153
1ef7286e 2154 reg = RTL_R32(tp, TxConfig);
e3cf0cc0 2155 while ((reg & p->mask) != p->val)
1da177e4
LT		 2156 p++;
2157 tp->mac_version = p->mac_version;
5d320a20
FR		 2158
2159 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
22148df0
HK		 2160 dev_notice(tp_to_dev(tp),
2161 "unknown MAC, using family default\n");
5d320a20 2162 tp->mac_version = default_version;
58152cd4 2163 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
f7ffa9ae 2164 tp->mac_version = tp->supports_gmii ?
58152cd4 2165 RTL_GIGA_MAC_VER_42 :
2166 RTL_GIGA_MAC_VER_43;
6e1d0b89 2167 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
f7ffa9ae 2168 tp->mac_version = tp->supports_gmii ?
6e1d0b89
CHL		 2169 RTL_GIGA_MAC_VER_45 :
2170 RTL_GIGA_MAC_VER_47;
2171 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
f7ffa9ae 2172 tp->mac_version = tp->supports_gmii ?
6e1d0b89
CHL		 2173 RTL_GIGA_MAC_VER_46 :
2174 RTL_GIGA_MAC_VER_48;
5d320a20 2175 }
1da177e4
LT		 2176}
2177
2178static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2179{
49d17512 2180 netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2181}
2182
867763c1
FR		 2183struct phy_reg {
2184 u16 reg;
2185 u16 val;
2186};
2187
4da19633 2188static void rtl_writephy_batch(struct rtl8169_private *tp,
2189 const struct phy_reg *regs, int len)
867763c1
FR		 2190{
2191 while (len-- > 0) {
4da19633 2192 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2193 regs++;
2194 }
2195}
2196
bca03d5f 2197#define PHY_READ 0x00000000
2198#define PHY_DATA_OR 0x10000000
2199#define PHY_DATA_AND 0x20000000
2200#define PHY_BJMPN 0x30000000
eee3786f 2201#define PHY_MDIO_CHG 0x40000000
bca03d5f 2202#define PHY_CLEAR_READCOUNT 0x70000000
2203#define PHY_WRITE 0x80000000
2204#define PHY_READCOUNT_EQ_SKIP 0x90000000
2205#define PHY_COMP_EQ_SKIPN 0xa0000000
2206#define PHY_COMP_NEQ_SKIPN 0xb0000000
2207#define PHY_WRITE_PREVIOUS 0xc0000000
2208#define PHY_SKIPN 0xd0000000
2209#define PHY_DELAY_MS 0xe0000000
bca03d5f 2210
960aee6c
HW		 2211struct fw_info {
2212 u32 magic;
2213 char version[RTL_VER_SIZE];
2214 __le32 fw_start;
2215 __le32 fw_len;
2216 u8 chksum;
2217} __packed;
2218
1c361efb
FR		 2219#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2220
2221static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2222{
b6ffd97f 2223 const struct firmware *fw = rtl_fw->fw;
960aee6c 2224 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2225 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2226 char *version = rtl_fw->version;
2227 bool rc = false;
2228
2229 if (fw->size < FW_OPCODE_SIZE)
2230 goto out;
960aee6c
HW		 2231
2232 if (!fw_info->magic) {
2233 size_t i, size, start;
2234 u8 checksum = 0;
2235
2236 if (fw->size < sizeof(*fw_info))
2237 goto out;
2238
2239 for (i = 0; i < fw->size; i++)
2240 checksum += fw->data[i];
2241 if (checksum != 0)
2242 goto out;
2243
2244 start = le32_to_cpu(fw_info->fw_start);
2245 if (start > fw->size)
2246 goto out;
2247
2248 size = le32_to_cpu(fw_info->fw_len);
2249 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2250 goto out;
2251
2252 memcpy(version, fw_info->version, RTL_VER_SIZE);
2253
2254 pa->code = (__le32 *)(fw->data + start);
2255 pa->size = size;
2256 } else {
1c361efb
FR		 2257 if (fw->size % FW_OPCODE_SIZE)
2258 goto out;
2259
2260 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2261
2262 pa->code = (__le32 *)fw->data;
2263 pa->size = fw->size / FW_OPCODE_SIZE;
2264 }
2265 version[RTL_VER_SIZE - 1] = 0;
2266
2267 rc = true;
2268out:
2269 return rc;
2270}
2271
fd112f2e
FR		 2272static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2273 struct rtl_fw_phy_action *pa)
1c361efb 2274{
fd112f2e 2275 bool rc = false;
1c361efb 2276 size_t index;
bca03d5f 2277
1c361efb
FR		 2278 for (index = 0; index < pa->size; index++) {
2279 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2280 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2281
42b82dc1 2282 switch(action & 0xf0000000) {
2283 case PHY_READ:
2284 case PHY_DATA_OR:
2285 case PHY_DATA_AND:
eee3786f 2286 case PHY_MDIO_CHG:
42b82dc1 2287 case PHY_CLEAR_READCOUNT:
2288 case PHY_WRITE:
2289 case PHY_WRITE_PREVIOUS:
2290 case PHY_DELAY_MS:
2291 break;
2292
2293 case PHY_BJMPN:
2294 if (regno > index) {
fd112f2e 2295 netif_err(tp, ifup, tp->dev,
cecb5fd7 2296 "Out of range of firmware\n");
fd112f2e 2297 goto out;
42b82dc1 2298 }
2299 break;
2300 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2301 if (index + 2 >= pa->size) {
fd112f2e 2302 netif_err(tp, ifup, tp->dev,
cecb5fd7 2303 "Out of range of firmware\n");
fd112f2e 2304 goto out;
42b82dc1 2305 }
2306 break;
2307 case PHY_COMP_EQ_SKIPN:
2308 case PHY_COMP_NEQ_SKIPN:
2309 case PHY_SKIPN:
1c361efb 2310 if (index + 1 + regno >= pa->size) {
fd112f2e 2311 netif_err(tp, ifup, tp->dev,
cecb5fd7 2312 "Out of range of firmware\n");
fd112f2e 2313 goto out;
42b82dc1 2314 }
bca03d5f 2315 break;
2316
42b82dc1 2317 default:
fd112f2e 2318 netif_err(tp, ifup, tp->dev,
42b82dc1 2319 "Invalid action 0x%08x\n", action);
fd112f2e 2320 goto out;
bca03d5f 2321 }
2322 }
fd112f2e
FR		 2323 rc = true;
2324out:
2325 return rc;
2326}
bca03d5f 2327
fd112f2e
FR		 2328static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2329{
2330 struct net_device *dev = tp->dev;
2331 int rc = -EINVAL;
2332
2333 if (!rtl_fw_format_ok(tp, rtl_fw)) {
5c2d2b14 2334 netif_err(tp, ifup, dev, "invalid firmware\n");
fd112f2e
FR		 2335 goto out;
2336 }
2337
2338 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2339 rc = 0;
2340out:
2341 return rc;
2342}
2343
2344static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2345{
2346 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2347 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2348 u32 predata, count;
2349 size_t index;
2350
2351 predata = count = 0;
eee3786f 2352 org.write = ops->write;
2353 org.read = ops->read;
42b82dc1 2354
1c361efb
FR		 2355 for (index = 0; index < pa->size; ) {
2356 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2357 u32 data = action & 0x0000ffff;
42b82dc1 2358 u32 regno = (action & 0x0fff0000) >> 16;
2359
2360 if (!action)
2361 break;
bca03d5f 2362
2363 switch(action & 0xf0000000) {
42b82dc1 2364 case PHY_READ:
2365 predata = rtl_readphy(tp, regno);
2366 count++;
2367 index++;
2368 break;
2369 case PHY_DATA_OR:
2370 predata |= data;
2371 index++;
2372 break;
2373 case PHY_DATA_AND:
2374 predata &= data;
2375 index++;
2376 break;
2377 case PHY_BJMPN:
2378 index -= regno;
2379 break;
eee3786f 2380 case PHY_MDIO_CHG:
2381 if (data == 0) {
2382 ops->write = org.write;
2383 ops->read = org.read;
2384 } else if (data == 1) {
2385 ops->write = mac_mcu_write;
2386 ops->read = mac_mcu_read;
2387 }
2388
42b82dc1 2389 index++;
2390 break;
2391 case PHY_CLEAR_READCOUNT:
2392 count = 0;
2393 index++;
2394 break;
bca03d5f 2395 case PHY_WRITE:
42b82dc1 2396 rtl_writephy(tp, regno, data);
2397 index++;
2398 break;
2399 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2400 index += (count == data) ? 2 : 1;
bca03d5f 2401 break;
42b82dc1 2402 case PHY_COMP_EQ_SKIPN:
2403 if (predata == data)
2404 index += regno;
2405 index++;
2406 break;
2407 case PHY_COMP_NEQ_SKIPN:
2408 if (predata != data)
2409 index += regno;
2410 index++;
2411 break;
2412 case PHY_WRITE_PREVIOUS:
2413 rtl_writephy(tp, regno, predata);
2414 index++;
2415 break;
2416 case PHY_SKIPN:
2417 index += regno + 1;
2418 break;
2419 case PHY_DELAY_MS:
2420 mdelay(data);
2421 index++;
2422 break;
2423
bca03d5f 2424 default:
2425 BUG();
2426 }
2427 }
eee3786f 2428
2429 ops->write = org.write;
2430 ops->read = org.read;
bca03d5f 2431}
2432
f1e02ed1 2433static void rtl_release_firmware(struct rtl8169_private *tp)
2434{
b6ffd97f
FR		 2435 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2436 release_firmware(tp->rtl_fw->fw);
2437 kfree(tp->rtl_fw);
2438 }
2439 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2440}
2441
953a12cc 2442static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2443{
b6ffd97f 2444 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2445
2446 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2447 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2448 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2449}
2450
2451static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2452{
2453 if (rtl_readphy(tp, reg) != val)
2454 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2455 else
2456 rtl_apply_firmware(tp);
f1e02ed1 2457}
2458
4da19633 2459static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2460{
350f7596 2461 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2462 { 0x1f, 0x0001 },
2463 { 0x06, 0x006e },
2464 { 0x08, 0x0708 },
2465 { 0x15, 0x4000 },
2466 { 0x18, 0x65c7 },
1da177e4 2467
0b9b571d 2468 { 0x1f, 0x0001 },
2469 { 0x03, 0x00a1 },
2470 { 0x02, 0x0008 },
2471 { 0x01, 0x0120 },
2472 { 0x00, 0x1000 },
2473 { 0x04, 0x0800 },
2474 { 0x04, 0x0000 },
1da177e4 2475
0b9b571d 2476 { 0x03, 0xff41 },
2477 { 0x02, 0xdf60 },
2478 { 0x01, 0x0140 },
2479 { 0x00, 0x0077 },
2480 { 0x04, 0x7800 },
2481 { 0x04, 0x7000 },
2482
2483 { 0x03, 0x802f },
2484 { 0x02, 0x4f02 },
2485 { 0x01, 0x0409 },
2486 { 0x00, 0xf0f9 },
2487 { 0x04, 0x9800 },
2488 { 0x04, 0x9000 },
2489
2490 { 0x03, 0xdf01 },
2491 { 0x02, 0xdf20 },
2492 { 0x01, 0xff95 },
2493 { 0x00, 0xba00 },
2494 { 0x04, 0xa800 },
2495 { 0x04, 0xa000 },
2496
2497 { 0x03, 0xff41 },
2498 { 0x02, 0xdf20 },
2499 { 0x01, 0x0140 },
2500 { 0x00, 0x00bb },
2501 { 0x04, 0xb800 },
2502 { 0x04, 0xb000 },
2503
2504 { 0x03, 0xdf41 },
2505 { 0x02, 0xdc60 },
2506 { 0x01, 0x6340 },
2507 { 0x00, 0x007d },
2508 { 0x04, 0xd800 },
2509 { 0x04, 0xd000 },
2510
2511 { 0x03, 0xdf01 },
2512 { 0x02, 0xdf20 },
2513 { 0x01, 0x100a },
2514 { 0x00, 0xa0ff },
2515 { 0x04, 0xf800 },
2516 { 0x04, 0xf000 },
2517
2518 { 0x1f, 0x0000 },
2519 { 0x0b, 0x0000 },
2520 { 0x00, 0x9200 }
2521 };
1da177e4 2522
4da19633 2523 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2524}
2525
4da19633 2526static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2527{
350f7596 2528 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2529 { 0x1f, 0x0002 },
2530 { 0x01, 0x90d0 },
2531 { 0x1f, 0x0000 }
2532 };
2533
4da19633 2534 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2535}
2536
4da19633 2537static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2538{
2539 struct pci_dev *pdev = tp->pci_dev;
2e955856 2540
ccbae55e
SS		 2541 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2542 (pdev->subsystem_device != 0xe000))
2e955856 2543 return;
2544
4da19633 2545 rtl_writephy(tp, 0x1f, 0x0001);
2546 rtl_writephy(tp, 0x10, 0xf01b);
2547 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2548}
2549
4da19633 2550static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2551{
350f7596 2552 static const struct phy_reg phy_reg_init[] = {
2e955856 2553 { 0x1f, 0x0001 },
2554 { 0x04, 0x0000 },
2555 { 0x03, 0x00a1 },
2556 { 0x02, 0x0008 },
2557 { 0x01, 0x0120 },
2558 { 0x00, 0x1000 },
2559 { 0x04, 0x0800 },
2560 { 0x04, 0x9000 },
2561 { 0x03, 0x802f },
2562 { 0x02, 0x4f02 },
2563 { 0x01, 0x0409 },
2564 { 0x00, 0xf099 },
2565 { 0x04, 0x9800 },
2566 { 0x04, 0xa000 },
2567 { 0x03, 0xdf01 },
2568 { 0x02, 0xdf20 },
2569 { 0x01, 0xff95 },
2570 { 0x00, 0xba00 },
2571 { 0x04, 0xa800 },
2572 { 0x04, 0xf000 },
2573 { 0x03, 0xdf01 },
2574 { 0x02, 0xdf20 },
2575 { 0x01, 0x101a },
2576 { 0x00, 0xa0ff },
2577 { 0x04, 0xf800 },
2578 { 0x04, 0x0000 },
2579 { 0x1f, 0x0000 },
2580
2581 { 0x1f, 0x0001 },
2582 { 0x10, 0xf41b },
2583 { 0x14, 0xfb54 },
2584 { 0x18, 0xf5c7 },
2585 { 0x1f, 0x0000 },
2586
2587 { 0x1f, 0x0001 },
2588 { 0x17, 0x0cc0 },
2589 { 0x1f, 0x0000 }
2590 };
2591
4da19633 2592 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2593
4da19633 2594 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2595}
2596
4da19633 2597static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2598{
350f7596 2599 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2600 { 0x1f, 0x0001 },
2601 { 0x04, 0x0000 },
2602 { 0x03, 0x00a1 },
2603 { 0x02, 0x0008 },
2604 { 0x01, 0x0120 },
2605 { 0x00, 0x1000 },
2606 { 0x04, 0x0800 },
2607 { 0x04, 0x9000 },
2608 { 0x03, 0x802f },
2609 { 0x02, 0x4f02 },
2610 { 0x01, 0x0409 },
2611 { 0x00, 0xf099 },
2612 { 0x04, 0x9800 },
2613 { 0x04, 0xa000 },
2614 { 0x03, 0xdf01 },
2615 { 0x02, 0xdf20 },
2616 { 0x01, 0xff95 },
2617 { 0x00, 0xba00 },
2618 { 0x04, 0xa800 },
2619 { 0x04, 0xf000 },
2620 { 0x03, 0xdf01 },
2621 { 0x02, 0xdf20 },
2622 { 0x01, 0x101a },
2623 { 0x00, 0xa0ff },
2624 { 0x04, 0xf800 },
2625 { 0x04, 0x0000 },
2626 { 0x1f, 0x0000 },
2627
2628 { 0x1f, 0x0001 },
2629 { 0x0b, 0x8480 },
2630 { 0x1f, 0x0000 },
2631
2632 { 0x1f, 0x0001 },
2633 { 0x18, 0x67c7 },
2634 { 0x04, 0x2000 },
2635 { 0x03, 0x002f },
2636 { 0x02, 0x4360 },
2637 { 0x01, 0x0109 },
2638 { 0x00, 0x3022 },
2639 { 0x04, 0x2800 },
2640 { 0x1f, 0x0000 },
2641
2642 { 0x1f, 0x0001 },
2643 { 0x17, 0x0cc0 },
2644 { 0x1f, 0x0000 }
2645 };
2646
4da19633 2647 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2648}
2649
4da19633 2650static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2651{
350f7596 2652 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2653 { 0x10, 0xf41b },
2654 { 0x1f, 0x0000 }
2655 };
2656
4da19633 2657 rtl_writephy(tp, 0x1f, 0x0001);
2658 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2659
4da19633 2660 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2661}
2662
4da19633 2663static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2664{
350f7596 2665 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2666 { 0x1f, 0x0001 },
2667 { 0x10, 0xf41b },
2668 { 0x1f, 0x0000 }
2669 };
2670
4da19633 2671 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2672}
2673
4da19633 2674static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2675{
350f7596 2676 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2677 { 0x1f, 0x0000 },
2678 { 0x1d, 0x0f00 },
2679 { 0x1f, 0x0002 },
2680 { 0x0c, 0x1ec8 },
2681 { 0x1f, 0x0000 }
2682 };
2683
4da19633 2684 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2685}
2686
4da19633 2687static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2688{
350f7596 2689 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2690 { 0x1f, 0x0001 },
2691 { 0x1d, 0x3d98 },
2692 { 0x1f, 0x0000 }
2693 };
2694
4da19633 2695 rtl_writephy(tp, 0x1f, 0x0000);
2696 rtl_patchphy(tp, 0x14, 1 << 5);
2697 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2698
4da19633 2699 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2700}
2701
4da19633 2702static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2703{
350f7596 2704 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2705 { 0x1f, 0x0001 },
2706 { 0x12, 0x2300 },
867763c1
FR		 2707 { 0x1f, 0x0002 },
2708 { 0x00, 0x88d4 },
2709 { 0x01, 0x82b1 },
2710 { 0x03, 0x7002 },
2711 { 0x08, 0x9e30 },
2712 { 0x09, 0x01f0 },
2713 { 0x0a, 0x5500 },
2714 { 0x0c, 0x00c8 },
2715 { 0x1f, 0x0003 },
2716 { 0x12, 0xc096 },
2717 { 0x16, 0x000a },
f50d4275
FR		 2718 { 0x1f, 0x0000 },
2719 { 0x1f, 0x0000 },
2720 { 0x09, 0x2000 },
2721 { 0x09, 0x0000 }
867763c1
FR		 2722 };
2723
4da19633 2724 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2725
4da19633 2726 rtl_patchphy(tp, 0x14, 1 << 5);
2727 rtl_patchphy(tp, 0x0d, 1 << 5);
2728 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2729}
2730
4da19633 2731static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2732{
350f7596 2733 static const struct phy_reg phy_reg_init[] = {
f50d4275 2734 { 0x1f, 0x0001 },
7da97ec9 2735 { 0x12, 0x2300 },
f50d4275
FR		 2736 { 0x03, 0x802f },
2737 { 0x02, 0x4f02 },
2738 { 0x01, 0x0409 },
2739 { 0x00, 0xf099 },
2740 { 0x04, 0x9800 },
2741 { 0x04, 0x9000 },
2742 { 0x1d, 0x3d98 },
7da97ec9
FR		 2743 { 0x1f, 0x0002 },
2744 { 0x0c, 0x7eb8 },
f50d4275
FR		 2745 { 0x06, 0x0761 },
2746 { 0x1f, 0x0003 },
2747 { 0x16, 0x0f0a },
7da97ec9
FR		 2748 { 0x1f, 0x0000 }
2749 };
2750
4da19633 2751 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2752
4da19633 2753 rtl_patchphy(tp, 0x16, 1 << 0);
2754 rtl_patchphy(tp, 0x14, 1 << 5);
2755 rtl_patchphy(tp, 0x0d, 1 << 5);
2756 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2757}
2758
4da19633 2759static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2760{
350f7596 2761 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2762 { 0x1f, 0x0001 },
2763 { 0x12, 0x2300 },
2764 { 0x1d, 0x3d98 },
2765 { 0x1f, 0x0002 },
2766 { 0x0c, 0x7eb8 },
2767 { 0x06, 0x5461 },
2768 { 0x1f, 0x0003 },
2769 { 0x16, 0x0f0a },
2770 { 0x1f, 0x0000 }
2771 };
2772
4da19633 2773 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2774
4da19633 2775 rtl_patchphy(tp, 0x16, 1 << 0);
2776 rtl_patchphy(tp, 0x14, 1 << 5);
2777 rtl_patchphy(tp, 0x0d, 1 << 5);
2778 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2779}
2780
4da19633 2781static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2782{
4da19633 2783 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2784}
2785
bca03d5f 2786static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2787{
350f7596 2788 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2789 /* Channel Estimation */
5b538df9 2790 { 0x1f, 0x0001 },
daf9df6d 2791 { 0x06, 0x4064 },
2792 { 0x07, 0x2863 },
2793 { 0x08, 0x059c },
2794 { 0x09, 0x26b4 },
2795 { 0x0a, 0x6a19 },
2796 { 0x0b, 0xdcc8 },
2797 { 0x10, 0xf06d },
2798 { 0x14, 0x7f68 },
2799 { 0x18, 0x7fd9 },
2800 { 0x1c, 0xf0ff },
2801 { 0x1d, 0x3d9c },
5b538df9 2802 { 0x1f, 0x0003 },
daf9df6d 2803 { 0x12, 0xf49f },
2804 { 0x13, 0x070b },
2805 { 0x1a, 0x05ad },
bca03d5f 2806 { 0x14, 0x94c0 },
2807
2808 /*
2809 * Tx Error Issue
cecb5fd7 2810 * Enhance line driver power
bca03d5f 2811 */
5b538df9 2812 { 0x1f, 0x0002 },
daf9df6d 2813 { 0x06, 0x5561 },
2814 { 0x1f, 0x0005 },
2815 { 0x05, 0x8332 },
bca03d5f 2816 { 0x06, 0x5561 },
2817
2818 /*
2819 * Can not link to 1Gbps with bad cable
2820 * Decrease SNR threshold form 21.07dB to 19.04dB
2821 */
2822 { 0x1f, 0x0001 },
2823 { 0x17, 0x0cc0 },
daf9df6d 2824
5b538df9 2825 { 0x1f, 0x0000 },
bca03d5f 2826 { 0x0d, 0xf880 }
daf9df6d 2827 };
2828
4da19633 2829 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2830
bca03d5f 2831 /*
2832 * Rx Error Issue
2833 * Fine Tune Switching regulator parameter
2834 */
4da19633 2835 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2836 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2837 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2838
fdf6fc06 2839 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2840 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2841 { 0x1f, 0x0002 },
2842 { 0x05, 0x669a },
2843 { 0x1f, 0x0005 },
2844 { 0x05, 0x8330 },
2845 { 0x06, 0x669a },
2846 { 0x1f, 0x0002 }
2847 };
2848 int val;
2849
4da19633 2850 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2851
4da19633 2852 val = rtl_readphy(tp, 0x0d);
daf9df6d 2853
2854 if ((val & 0x00ff) != 0x006c) {
350f7596 2855 static const u32 set[] = {
daf9df6d 2856 0x0065, 0x0066, 0x0067, 0x0068,
2857 0x0069, 0x006a, 0x006b, 0x006c
2858 };
2859 int i;
2860
4da19633 2861 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2862
2863 val &= 0xff00;
2864 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2865 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2866 }
2867 } else {
350f7596 2868 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2869 { 0x1f, 0x0002 },
2870 { 0x05, 0x6662 },
2871 { 0x1f, 0x0005 },
2872 { 0x05, 0x8330 },
2873 { 0x06, 0x6662 }
2874 };
2875
4da19633 2876 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2877 }
2878
bca03d5f 2879 /* RSET couple improve */
4da19633 2880 rtl_writephy(tp, 0x1f, 0x0002);
2881 rtl_patchphy(tp, 0x0d, 0x0300);
2882 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2883
bca03d5f 2884 /* Fine tune PLL performance */
4da19633 2885 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2886 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2887 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2888
4da19633 2889 rtl_writephy(tp, 0x1f, 0x0005);
2890 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2891
2892 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2893
4da19633 2894 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2895}
2896
bca03d5f 2897static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2898{
350f7596 2899 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2900 /* Channel Estimation */
daf9df6d 2901 { 0x1f, 0x0001 },
2902 { 0x06, 0x4064 },
2903 { 0x07, 0x2863 },
2904 { 0x08, 0x059c },
2905 { 0x09, 0x26b4 },
2906 { 0x0a, 0x6a19 },
2907 { 0x0b, 0xdcc8 },
2908 { 0x10, 0xf06d },
2909 { 0x14, 0x7f68 },
2910 { 0x18, 0x7fd9 },
2911 { 0x1c, 0xf0ff },
2912 { 0x1d, 0x3d9c },
2913 { 0x1f, 0x0003 },
2914 { 0x12, 0xf49f },
2915 { 0x13, 0x070b },
2916 { 0x1a, 0x05ad },
2917 { 0x14, 0x94c0 },
2918
bca03d5f 2919 /*
2920 * Tx Error Issue
cecb5fd7 2921 * Enhance line driver power
bca03d5f 2922 */
daf9df6d 2923 { 0x1f, 0x0002 },
2924 { 0x06, 0x5561 },
2925 { 0x1f, 0x0005 },
2926 { 0x05, 0x8332 },
bca03d5f 2927 { 0x06, 0x5561 },
2928
2929 /*
2930 * Can not link to 1Gbps with bad cable
2931 * Decrease SNR threshold form 21.07dB to 19.04dB
2932 */
2933 { 0x1f, 0x0001 },
2934 { 0x17, 0x0cc0 },
daf9df6d 2935
2936 { 0x1f, 0x0000 },
bca03d5f 2937 { 0x0d, 0xf880 }
5b538df9
FR		 2938 };
2939
4da19633 2940 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2941
fdf6fc06 2942 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2943 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2944 { 0x1f, 0x0002 },
2945 { 0x05, 0x669a },
5b538df9 2946 { 0x1f, 0x0005 },
daf9df6d 2947 { 0x05, 0x8330 },
2948 { 0x06, 0x669a },
2949
2950 { 0x1f, 0x0002 }
2951 };
2952 int val;
2953
4da19633 2954 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2955
4da19633 2956 val = rtl_readphy(tp, 0x0d);
daf9df6d 2957 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2958 static const u32 set[] = {
daf9df6d 2959 0x0065, 0x0066, 0x0067, 0x0068,
2960 0x0069, 0x006a, 0x006b, 0x006c
2961 };
2962 int i;
2963
4da19633 2964 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2965
2966 val &= 0xff00;
2967 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2968 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2969 }
2970 } else {
350f7596 2971 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2972 { 0x1f, 0x0002 },
2973 { 0x05, 0x2642 },
5b538df9 2974 { 0x1f, 0x0005 },
daf9df6d 2975 { 0x05, 0x8330 },
2976 { 0x06, 0x2642 }
5b538df9
FR		 2977 };
2978
4da19633 2979 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2980 }
2981
bca03d5f 2982 /* Fine tune PLL performance */
4da19633 2983 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2984 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2985 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2986
bca03d5f 2987 /* Switching regulator Slew rate */
4da19633 2988 rtl_writephy(tp, 0x1f, 0x0002);
2989 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2990
4da19633 2991 rtl_writephy(tp, 0x1f, 0x0005);
2992 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2993
2994 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2995
4da19633 2996 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2997}
2998
4da19633 2999static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3000{
350f7596 3001 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3002 { 0x1f, 0x0002 },
3003 { 0x10, 0x0008 },
3004 { 0x0d, 0x006c },
3005
3006 { 0x1f, 0x0000 },
3007 { 0x0d, 0xf880 },
3008
3009 { 0x1f, 0x0001 },
3010 { 0x17, 0x0cc0 },
3011
3012 { 0x1f, 0x0001 },
3013 { 0x0b, 0xa4d8 },
3014 { 0x09, 0x281c },
3015 { 0x07, 0x2883 },
3016 { 0x0a, 0x6b35 },
3017 { 0x1d, 0x3da4 },
3018 { 0x1c, 0xeffd },
3019 { 0x14, 0x7f52 },
3020 { 0x18, 0x7fc6 },
3021 { 0x08, 0x0601 },
3022 { 0x06, 0x4063 },
3023 { 0x10, 0xf074 },
3024 { 0x1f, 0x0003 },
3025 { 0x13, 0x0789 },
3026 { 0x12, 0xf4bd },
3027 { 0x1a, 0x04fd },
3028 { 0x14, 0x84b0 },
3029 { 0x1f, 0x0000 },
3030 { 0x00, 0x9200 },
3031
3032 { 0x1f, 0x0005 },
3033 { 0x01, 0x0340 },
3034 { 0x1f, 0x0001 },
3035 { 0x04, 0x4000 },
3036 { 0x03, 0x1d21 },
3037 { 0x02, 0x0c32 },
3038 { 0x01, 0x0200 },
3039 { 0x00, 0x5554 },
3040 { 0x04, 0x4800 },
3041 { 0x04, 0x4000 },
3042 { 0x04, 0xf000 },
3043 { 0x03, 0xdf01 },
3044 { 0x02, 0xdf20 },
3045 { 0x01, 0x101a },
3046 { 0x00, 0xa0ff },
3047 { 0x04, 0xf800 },
3048 { 0x04, 0xf000 },
3049 { 0x1f, 0x0000 },
3050
3051 { 0x1f, 0x0007 },
3052 { 0x1e, 0x0023 },
3053 { 0x16, 0x0000 },
3054 { 0x1f, 0x0000 }
3055 };
3056
4da19633 3057 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3058}
3059
e6de30d6 3060static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3061{
3062 static const struct phy_reg phy_reg_init[] = {
3063 { 0x1f, 0x0001 },
3064 { 0x17, 0x0cc0 },
3065
3066 { 0x1f, 0x0007 },
3067 { 0x1e, 0x002d },
3068 { 0x18, 0x0040 },
3069 { 0x1f, 0x0000 }
3070 };
3071
3072 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3073 rtl_patchphy(tp, 0x0d, 1 << 5);
3074}
3075
70090424 3076static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3077{
3078 static const struct phy_reg phy_reg_init[] = {
3079 /* Enable Delay cap */
3080 { 0x1f, 0x0005 },
3081 { 0x05, 0x8b80 },
3082 { 0x06, 0xc896 },
3083 { 0x1f, 0x0000 },
3084
3085 /* Channel estimation fine tune */
3086 { 0x1f, 0x0001 },
3087 { 0x0b, 0x6c20 },
3088 { 0x07, 0x2872 },
3089 { 0x1c, 0xefff },
3090 { 0x1f, 0x0003 },
3091 { 0x14, 0x6420 },
3092 { 0x1f, 0x0000 },
3093
3094 /* Update PFM & 10M TX idle timer */
3095 { 0x1f, 0x0007 },
3096 { 0x1e, 0x002f },
3097 { 0x15, 0x1919 },
3098 { 0x1f, 0x0000 },
3099
3100 { 0x1f, 0x0007 },
3101 { 0x1e, 0x00ac },
3102 { 0x18, 0x0006 },
3103 { 0x1f, 0x0000 }
3104 };
3105
15ecd039
FR		 3106 rtl_apply_firmware(tp);
3107
01dc7fec 3108 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3109
3110 /* DCO enable for 10M IDLE Power */
3111 rtl_writephy(tp, 0x1f, 0x0007);
3112 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3113 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3114 rtl_writephy(tp, 0x1f, 0x0000);
3115
3116 /* For impedance matching */
3117 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3118 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3119 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3120
3121 /* PHY auto speed down */
3122 rtl_writephy(tp, 0x1f, 0x0007);
3123 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3124 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3125 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3126 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3127
3128 rtl_writephy(tp, 0x1f, 0x0005);
3129 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3130 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3131 rtl_writephy(tp, 0x1f, 0x0000);
3132
3133 rtl_writephy(tp, 0x1f, 0x0005);
3134 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3135 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3136 rtl_writephy(tp, 0x1f, 0x0007);
3137 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3138 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3139 rtl_writephy(tp, 0x1f, 0x0006);
3140 rtl_writephy(tp, 0x00, 0x5a00);
3141 rtl_writephy(tp, 0x1f, 0x0000);
3142 rtl_writephy(tp, 0x0d, 0x0007);
3143 rtl_writephy(tp, 0x0e, 0x003c);
3144 rtl_writephy(tp, 0x0d, 0x4007);
3145 rtl_writephy(tp, 0x0e, 0x0000);
3146 rtl_writephy(tp, 0x0d, 0x0000);
3147}
3148
9ecb9aab 3149static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3150{
3151 const u16 w[] = {
3152 addr[0] | (addr[1] << 8),
3153 addr[2] | (addr[3] << 8),
3154 addr[4] | (addr[5] << 8)
3155 };
3156 const struct exgmac_reg e[] = {
3157 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3158 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3159 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3160 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3161 };
3162
3163 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3164}
3165
70090424
HW		 3166static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3167{
3168 static const struct phy_reg phy_reg_init[] = {
3169 /* Enable Delay cap */
3170 { 0x1f, 0x0004 },
3171 { 0x1f, 0x0007 },
3172 { 0x1e, 0x00ac },
3173 { 0x18, 0x0006 },
3174 { 0x1f, 0x0002 },
3175 { 0x1f, 0x0000 },
3176 { 0x1f, 0x0000 },
3177
3178 /* Channel estimation fine tune */
3179 { 0x1f, 0x0003 },
3180 { 0x09, 0xa20f },
3181 { 0x1f, 0x0000 },
3182 { 0x1f, 0x0000 },
3183
3184 /* Green Setting */
3185 { 0x1f, 0x0005 },
3186 { 0x05, 0x8b5b },
3187 { 0x06, 0x9222 },
3188 { 0x05, 0x8b6d },
3189 { 0x06, 0x8000 },
3190 { 0x05, 0x8b76 },
3191 { 0x06, 0x8000 },
3192 { 0x1f, 0x0000 }
3193 };
3194
3195 rtl_apply_firmware(tp);
3196
3197 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3198
3199 /* For 4-corner performance improve */
3200 rtl_writephy(tp, 0x1f, 0x0005);
3201 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3202 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3203 rtl_writephy(tp, 0x1f, 0x0000);
3204
3205 /* PHY auto speed down */
3206 rtl_writephy(tp, 0x1f, 0x0004);
3207 rtl_writephy(tp, 0x1f, 0x0007);
3208 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3209 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3210 rtl_writephy(tp, 0x1f, 0x0002);
3211 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3212 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3213
3214 /* improve 10M EEE waveform */
3215 rtl_writephy(tp, 0x1f, 0x0005);
3216 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3217 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3218 rtl_writephy(tp, 0x1f, 0x0000);
3219
3220 /* Improve 2-pair detection performance */
3221 rtl_writephy(tp, 0x1f, 0x0005);
3222 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3223 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3224 rtl_writephy(tp, 0x1f, 0x0000);
3225
3226 /* EEE setting */
1814d6a8 3227 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
70090424
HW		 3228 rtl_writephy(tp, 0x1f, 0x0005);
3229 rtl_writephy(tp, 0x05, 0x8b85);
1814d6a8 3230 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
70090424
HW		 3231 rtl_writephy(tp, 0x1f, 0x0004);
3232 rtl_writephy(tp, 0x1f, 0x0007);
3233 rtl_writephy(tp, 0x1e, 0x0020);
1814d6a8 3234 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
70090424
HW		 3235 rtl_writephy(tp, 0x1f, 0x0002);
3236 rtl_writephy(tp, 0x1f, 0x0000);
3237 rtl_writephy(tp, 0x0d, 0x0007);
3238 rtl_writephy(tp, 0x0e, 0x003c);
3239 rtl_writephy(tp, 0x0d, 0x4007);
1814d6a8 3240 rtl_writephy(tp, 0x0e, 0x0006);
70090424
HW		 3241 rtl_writephy(tp, 0x0d, 0x0000);
3242
3243 /* Green feature */
3244 rtl_writephy(tp, 0x1f, 0x0003);
1814d6a8
HK		 3245 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3246 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
70090424 3247 rtl_writephy(tp, 0x1f, 0x0000);
b399a394
HK		 3248 rtl_writephy(tp, 0x1f, 0x0005);
3249 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3250 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3251
9ecb9aab 3252 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3253 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3254}
3255
5f886e08
HW		 3256static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3257{
3258 /* For 4-corner performance improve */
3259 rtl_writephy(tp, 0x1f, 0x0005);
3260 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3261 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3262 rtl_writephy(tp, 0x1f, 0x0000);
3263
3264 /* PHY auto speed down */
3265 rtl_writephy(tp, 0x1f, 0x0007);
3266 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3267 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3268 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3269 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3270
3271 /* Improve 10M EEE waveform */
3272 rtl_writephy(tp, 0x1f, 0x0005);
3273 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3274 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3275 rtl_writephy(tp, 0x1f, 0x0000);
3276}
3277
c2218925
HW		 3278static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3279{
3280 static const struct phy_reg phy_reg_init[] = {
3281 /* Channel estimation fine tune */
3282 { 0x1f, 0x0003 },
3283 { 0x09, 0xa20f },
3284 { 0x1f, 0x0000 },
3285
3286 /* Modify green table for giga & fnet */
3287 { 0x1f, 0x0005 },
3288 { 0x05, 0x8b55 },
3289 { 0x06, 0x0000 },
3290 { 0x05, 0x8b5e },
3291 { 0x06, 0x0000 },
3292 { 0x05, 0x8b67 },
3293 { 0x06, 0x0000 },
3294 { 0x05, 0x8b70 },
3295 { 0x06, 0x0000 },
3296 { 0x1f, 0x0000 },
3297 { 0x1f, 0x0007 },
3298 { 0x1e, 0x0078 },
3299 { 0x17, 0x0000 },
3300 { 0x19, 0x00fb },
3301 { 0x1f, 0x0000 },
3302
3303 /* Modify green table for 10M */
3304 { 0x1f, 0x0005 },
3305 { 0x05, 0x8b79 },
3306 { 0x06, 0xaa00 },
3307 { 0x1f, 0x0000 },
3308
3309 /* Disable hiimpedance detection (RTCT) */
3310 { 0x1f, 0x0003 },
3311 { 0x01, 0x328a },
3312 { 0x1f, 0x0000 }
3313 };
3314
3315 rtl_apply_firmware(tp);
3316
3317 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3318
5f886e08 3319 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3320
3321 /* Improve 2-pair detection performance */
3322 rtl_writephy(tp, 0x1f, 0x0005);
3323 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3324 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3325 rtl_writephy(tp, 0x1f, 0x0000);
3326}
3327
3328static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3329{
3330 rtl_apply_firmware(tp);
3331
5f886e08 3332 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3333}
3334
b3d7b2f2
HW		 3335static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3336{
b3d7b2f2
HW		 3337 static const struct phy_reg phy_reg_init[] = {
3338 /* Channel estimation fine tune */
3339 { 0x1f, 0x0003 },
3340 { 0x09, 0xa20f },
3341 { 0x1f, 0x0000 },
3342
3343 /* Modify green table for giga & fnet */
3344 { 0x1f, 0x0005 },
3345 { 0x05, 0x8b55 },
3346 { 0x06, 0x0000 },
3347 { 0x05, 0x8b5e },
3348 { 0x06, 0x0000 },
3349 { 0x05, 0x8b67 },
3350 { 0x06, 0x0000 },
3351 { 0x05, 0x8b70 },
3352 { 0x06, 0x0000 },
3353 { 0x1f, 0x0000 },
3354 { 0x1f, 0x0007 },
3355 { 0x1e, 0x0078 },
3356 { 0x17, 0x0000 },
3357 { 0x19, 0x00aa },
3358 { 0x1f, 0x0000 },
3359
3360 /* Modify green table for 10M */
3361 { 0x1f, 0x0005 },
3362 { 0x05, 0x8b79 },
3363 { 0x06, 0xaa00 },
3364 { 0x1f, 0x0000 },
3365
3366 /* Disable hiimpedance detection (RTCT) */
3367 { 0x1f, 0x0003 },
3368 { 0x01, 0x328a },
3369 { 0x1f, 0x0000 }
3370 };
3371
3372
3373 rtl_apply_firmware(tp);
3374
3375 rtl8168f_hw_phy_config(tp);
3376
3377 /* Improve 2-pair detection performance */
3378 rtl_writephy(tp, 0x1f, 0x0005);
3379 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3380 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3381 rtl_writephy(tp, 0x1f, 0x0000);
3382
3383 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3384
3385 /* Modify green table for giga */
3386 rtl_writephy(tp, 0x1f, 0x0005);
3387 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3388 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3389 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3390 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3391 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3392 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3393 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3394 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3395 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3396 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3397 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3398 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3399 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3400 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3401 rtl_writephy(tp, 0x1f, 0x0000);
3402
3403 /* uc same-seed solution */
3404 rtl_writephy(tp, 0x1f, 0x0005);
3405 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3406 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3407 rtl_writephy(tp, 0x1f, 0x0000);
3408
3409 /* eee setting */
706123d0 3410 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3411 rtl_writephy(tp, 0x1f, 0x0005);
3412 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3413 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3414 rtl_writephy(tp, 0x1f, 0x0004);
3415 rtl_writephy(tp, 0x1f, 0x0007);
3416 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3417 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3418 rtl_writephy(tp, 0x1f, 0x0000);
3419 rtl_writephy(tp, 0x0d, 0x0007);
3420 rtl_writephy(tp, 0x0e, 0x003c);
3421 rtl_writephy(tp, 0x0d, 0x4007);
3422 rtl_writephy(tp, 0x0e, 0x0000);
3423 rtl_writephy(tp, 0x0d, 0x0000);
3424
3425 /* Green feature */
3426 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3427 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3428 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3429 rtl_writephy(tp, 0x1f, 0x0000);
3430}
3431
c558386b
HW		 3432static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3433{
c558386b
HW		 3434 rtl_apply_firmware(tp);
3435
41f44d13 3436 rtl_writephy(tp, 0x1f, 0x0a46);
3437 if (rtl_readphy(tp, 0x10) & 0x0100) {
3438 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3439 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3440 } else {
3441 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3442 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3443 }
c558386b 3444
41f44d13 3445 rtl_writephy(tp, 0x1f, 0x0a46);
3446 if (rtl_readphy(tp, 0x13) & 0x0100) {
3447 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3448 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 3449 } else {
fe7524c0 3450 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3451 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3452 }
c558386b 3453
41f44d13 3454 /* Enable PHY auto speed down */
3455 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3456 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3457
fe7524c0 3458 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3459 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 3460 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3461 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 3462 rtl_writephy(tp, 0x1f, 0x0a43);
3463 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 3464 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3465 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 3466
41f44d13 3467 /* EEE auto-fallback function */
3468 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 3469 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3470
41f44d13 3471 /* Enable UC LPF tune function */
3472 rtl_writephy(tp, 0x1f, 0x0a43);
3473 rtl_writephy(tp, 0x13, 0x8012);
76564428 3474 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 3475
3476 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 3477 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 3478
fe7524c0 3479 /* Improve SWR Efficiency */
3480 rtl_writephy(tp, 0x1f, 0x0bcd);
3481 rtl_writephy(tp, 0x14, 0x5065);
3482 rtl_writephy(tp, 0x14, 0xd065);
3483 rtl_writephy(tp, 0x1f, 0x0bc8);
3484 rtl_writephy(tp, 0x11, 0x5655);
3485 rtl_writephy(tp, 0x1f, 0x0bcd);
3486 rtl_writephy(tp, 0x14, 0x1065);
3487 rtl_writephy(tp, 0x14, 0x9065);
3488 rtl_writephy(tp, 0x14, 0x1065);
3489
1bac1072
DC		 3490 /* Check ALDPS bit, disable it if enabled */
3491 rtl_writephy(tp, 0x1f, 0x0a43);
3492 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3493 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 3494
41f44d13 3495 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3496}
3497
57538c4a 3498static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3499{
3500 rtl_apply_firmware(tp);
3501}
3502
6e1d0b89
CHL		 3503static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3504{
3505 u16 dout_tapbin;
3506 u32 data;
3507
3508 rtl_apply_firmware(tp);
3509
3510 /* CHN EST parameters adjust - giga master */
3511 rtl_writephy(tp, 0x1f, 0x0a43);
3512 rtl_writephy(tp, 0x13, 0x809b);
76564428 3513 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 3514 rtl_writephy(tp, 0x13, 0x80a2);
76564428 3515 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 3516 rtl_writephy(tp, 0x13, 0x80a4);
76564428 3517 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 3518 rtl_writephy(tp, 0x13, 0x809c);
76564428 3519 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 3520 rtl_writephy(tp, 0x1f, 0x0000);
3521
3522 /* CHN EST parameters adjust - giga slave */
3523 rtl_writephy(tp, 0x1f, 0x0a43);
3524 rtl_writephy(tp, 0x13, 0x80ad);
76564428 3525 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 3526 rtl_writephy(tp, 0x13, 0x80b4);
76564428 3527 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 3528 rtl_writephy(tp, 0x13, 0x80ac);
76564428 3529 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 3530 rtl_writephy(tp, 0x1f, 0x0000);
3531
3532 /* CHN EST parameters adjust - fnet */
3533 rtl_writephy(tp, 0x1f, 0x0a43);
3534 rtl_writephy(tp, 0x13, 0x808e);
76564428 3535 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 3536 rtl_writephy(tp, 0x13, 0x8090);
76564428 3537 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 3538 rtl_writephy(tp, 0x13, 0x8092);
76564428 3539 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 3540 rtl_writephy(tp, 0x1f, 0x0000);
3541
3542 /* enable R-tune & PGA-retune function */
3543 dout_tapbin = 0;
3544 rtl_writephy(tp, 0x1f, 0x0a46);
3545 data = rtl_readphy(tp, 0x13);
3546 data &= 3;
3547 data <<= 2;
3548 dout_tapbin |= data;
3549 data = rtl_readphy(tp, 0x12);
3550 data &= 0xc000;
3551 data >>= 14;
3552 dout_tapbin |= data;
3553 dout_tapbin = ~(dout_tapbin^0x08);
3554 dout_tapbin <<= 12;
3555 dout_tapbin &= 0xf000;
3556 rtl_writephy(tp, 0x1f, 0x0a43);
3557 rtl_writephy(tp, 0x13, 0x827a);
76564428 3558 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3559 rtl_writephy(tp, 0x13, 0x827b);
76564428 3560 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3561 rtl_writephy(tp, 0x13, 0x827c);
76564428 3562 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3563 rtl_writephy(tp, 0x13, 0x827d);
76564428 3564 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 3565
3566 rtl_writephy(tp, 0x1f, 0x0a43);
3567 rtl_writephy(tp, 0x13, 0x0811);
76564428 3568 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3569 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3570 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3571 rtl_writephy(tp, 0x1f, 0x0000);
3572
3573 /* enable GPHY 10M */
3574 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3575 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3576 rtl_writephy(tp, 0x1f, 0x0000);
3577
3578 /* SAR ADC performance */
3579 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 3580 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 3581 rtl_writephy(tp, 0x1f, 0x0000);
3582
3583 rtl_writephy(tp, 0x1f, 0x0a43);
3584 rtl_writephy(tp, 0x13, 0x803f);
76564428 3585 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3586 rtl_writephy(tp, 0x13, 0x8047);
76564428 3587 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3588 rtl_writephy(tp, 0x13, 0x804f);
76564428 3589 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3590 rtl_writephy(tp, 0x13, 0x8057);
76564428 3591 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3592 rtl_writephy(tp, 0x13, 0x805f);
76564428 3593 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3594 rtl_writephy(tp, 0x13, 0x8067);
76564428 3595 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3596 rtl_writephy(tp, 0x13, 0x806f);
76564428 3597 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 3598 rtl_writephy(tp, 0x1f, 0x0000);
3599
3600 /* disable phy pfm mode */
3601 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3602 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3603 rtl_writephy(tp, 0x1f, 0x0000);
3604
3605 /* Check ALDPS bit, disable it if enabled */
3606 rtl_writephy(tp, 0x1f, 0x0a43);
3607 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3608 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3609
3610 rtl_writephy(tp, 0x1f, 0x0000);
3611}
3612
3613static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3614{
3615 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3616 u16 rlen;
3617 u32 data;
3618
3619 rtl_apply_firmware(tp);
3620
3621 /* CHIN EST parameter update */
3622 rtl_writephy(tp, 0x1f, 0x0a43);
3623 rtl_writephy(tp, 0x13, 0x808a);
76564428 3624 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 3625 rtl_writephy(tp, 0x1f, 0x0000);
3626
3627 /* enable R-tune & PGA-retune function */
3628 rtl_writephy(tp, 0x1f, 0x0a43);
3629 rtl_writephy(tp, 0x13, 0x0811);
76564428 3630 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3631 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3632 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3633 rtl_writephy(tp, 0x1f, 0x0000);
3634
3635 /* enable GPHY 10M */
3636 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3637 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3638 rtl_writephy(tp, 0x1f, 0x0000);
3639
3640 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3641 data = r8168_mac_ocp_read(tp, 0xdd02);
3642 ioffset_p3 = ((data & 0x80)>>7);
3643 ioffset_p3 <<= 3;
3644
3645 data = r8168_mac_ocp_read(tp, 0xdd00);
3646 ioffset_p3 |= ((data & (0xe000))>>13);
3647 ioffset_p2 = ((data & (0x1e00))>>9);
3648 ioffset_p1 = ((data & (0x01e0))>>5);
3649 ioffset_p0 = ((data & 0x0010)>>4);
3650 ioffset_p0 <<= 3;
3651 ioffset_p0 |= (data & (0x07));
3652 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3653
05b9687b 3654 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
e2e2788e 3655 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
6e1d0b89
CHL		 3656 rtl_writephy(tp, 0x1f, 0x0bcf);
3657 rtl_writephy(tp, 0x16, data);
3658 rtl_writephy(tp, 0x1f, 0x0000);
3659 }
3660
3661 /* Modify rlen (TX LPF corner frequency) level */
3662 rtl_writephy(tp, 0x1f, 0x0bcd);
3663 data = rtl_readphy(tp, 0x16);
3664 data &= 0x000f;
3665 rlen = 0;
3666 if (data > 3)
3667 rlen = data - 3;
3668 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3669 rtl_writephy(tp, 0x17, data);
3670 rtl_writephy(tp, 0x1f, 0x0bcd);
3671 rtl_writephy(tp, 0x1f, 0x0000);
3672
3673 /* disable phy pfm mode */
3674 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3675 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3676 rtl_writephy(tp, 0x1f, 0x0000);
3677
3678 /* Check ALDPS bit, disable it if enabled */
3679 rtl_writephy(tp, 0x1f, 0x0a43);
3680 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3681 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3682
3683 rtl_writephy(tp, 0x1f, 0x0000);
3684}
3685
935e2218
CHL		 3686static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3687{
3688 /* Enable PHY auto speed down */
3689 rtl_writephy(tp, 0x1f, 0x0a44);
3690 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3691 rtl_writephy(tp, 0x1f, 0x0000);
3692
3693 /* patch 10M & ALDPS */
3694 rtl_writephy(tp, 0x1f, 0x0bcc);
3695 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3696 rtl_writephy(tp, 0x1f, 0x0a44);
3697 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3698 rtl_writephy(tp, 0x1f, 0x0a43);
3699 rtl_writephy(tp, 0x13, 0x8084);
3700 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3701 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3702 rtl_writephy(tp, 0x1f, 0x0000);
3703
3704 /* Enable EEE auto-fallback function */
3705 rtl_writephy(tp, 0x1f, 0x0a4b);
3706 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3707 rtl_writephy(tp, 0x1f, 0x0000);
3708
3709 /* Enable UC LPF tune function */
3710 rtl_writephy(tp, 0x1f, 0x0a43);
3711 rtl_writephy(tp, 0x13, 0x8012);
3712 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3713 rtl_writephy(tp, 0x1f, 0x0000);
3714
3715 /* set rg_sel_sdm_rate */
3716 rtl_writephy(tp, 0x1f, 0x0c42);
3717 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3718 rtl_writephy(tp, 0x1f, 0x0000);
3719
3720 /* Check ALDPS bit, disable it if enabled */
3721 rtl_writephy(tp, 0x1f, 0x0a43);
3722 if (rtl_readphy(tp, 0x10) & 0x0004)
3723 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3724
3725 rtl_writephy(tp, 0x1f, 0x0000);
3726}
3727
3728static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3729{
3730 /* patch 10M & ALDPS */
3731 rtl_writephy(tp, 0x1f, 0x0bcc);
3732 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3733 rtl_writephy(tp, 0x1f, 0x0a44);
3734 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3735 rtl_writephy(tp, 0x1f, 0x0a43);
3736 rtl_writephy(tp, 0x13, 0x8084);
3737 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3738 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3739 rtl_writephy(tp, 0x1f, 0x0000);
3740
3741 /* Enable UC LPF tune function */
3742 rtl_writephy(tp, 0x1f, 0x0a43);
3743 rtl_writephy(tp, 0x13, 0x8012);
3744 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3745 rtl_writephy(tp, 0x1f, 0x0000);
3746
3747 /* Set rg_sel_sdm_rate */
3748 rtl_writephy(tp, 0x1f, 0x0c42);
3749 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3750 rtl_writephy(tp, 0x1f, 0x0000);
3751
3752 /* Channel estimation parameters */
3753 rtl_writephy(tp, 0x1f, 0x0a43);
3754 rtl_writephy(tp, 0x13, 0x80f3);
3755 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3756 rtl_writephy(tp, 0x13, 0x80f0);
3757 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3758 rtl_writephy(tp, 0x13, 0x80ef);
3759 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3760 rtl_writephy(tp, 0x13, 0x80f6);
3761 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3762 rtl_writephy(tp, 0x13, 0x80ec);
3763 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3764 rtl_writephy(tp, 0x13, 0x80ed);
3765 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3766 rtl_writephy(tp, 0x13, 0x80f2);
3767 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3768 rtl_writephy(tp, 0x13, 0x80f4);
3769 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3770 rtl_writephy(tp, 0x1f, 0x0a43);
3771 rtl_writephy(tp, 0x13, 0x8110);
3772 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3773 rtl_writephy(tp, 0x13, 0x810f);
3774 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3775 rtl_writephy(tp, 0x13, 0x8111);
3776 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3777 rtl_writephy(tp, 0x13, 0x8113);
3778 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3779 rtl_writephy(tp, 0x13, 0x8115);
3780 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3781 rtl_writephy(tp, 0x13, 0x810e);
3782 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3783 rtl_writephy(tp, 0x13, 0x810c);
3784 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3785 rtl_writephy(tp, 0x13, 0x810b);
3786 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3787 rtl_writephy(tp, 0x1f, 0x0a43);
3788 rtl_writephy(tp, 0x13, 0x80d1);
3789 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3790 rtl_writephy(tp, 0x13, 0x80cd);
3791 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3792 rtl_writephy(tp, 0x13, 0x80d3);
3793 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3794 rtl_writephy(tp, 0x13, 0x80d5);
3795 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3796 rtl_writephy(tp, 0x13, 0x80d7);
3797 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3798
3799 /* Force PWM-mode */
3800 rtl_writephy(tp, 0x1f, 0x0bcd);
3801 rtl_writephy(tp, 0x14, 0x5065);
3802 rtl_writephy(tp, 0x14, 0xd065);
3803 rtl_writephy(tp, 0x1f, 0x0bc8);
3804 rtl_writephy(tp, 0x12, 0x00ed);
3805 rtl_writephy(tp, 0x1f, 0x0bcd);
3806 rtl_writephy(tp, 0x14, 0x1065);
3807 rtl_writephy(tp, 0x14, 0x9065);
3808 rtl_writephy(tp, 0x14, 0x1065);
3809 rtl_writephy(tp, 0x1f, 0x0000);
3810
3811 /* Check ALDPS bit, disable it if enabled */
3812 rtl_writephy(tp, 0x1f, 0x0a43);
3813 if (rtl_readphy(tp, 0x10) & 0x0004)
3814 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3815
3816 rtl_writephy(tp, 0x1f, 0x0000);
3817}
3818
4da19633 3819static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3820{
350f7596 3821 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3822 { 0x1f, 0x0003 },
3823 { 0x08, 0x441d },
3824 { 0x01, 0x9100 },
3825 { 0x1f, 0x0000 }
3826 };
3827
4da19633 3828 rtl_writephy(tp, 0x1f, 0x0000);
3829 rtl_patchphy(tp, 0x11, 1 << 12);
3830 rtl_patchphy(tp, 0x19, 1 << 13);
3831 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3832
4da19633 3833 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3834}
3835
5a5e4443
HW		 3836static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3837{
3838 static const struct phy_reg phy_reg_init[] = {
3839 { 0x1f, 0x0005 },
3840 { 0x1a, 0x0000 },
3841 { 0x1f, 0x0000 },
3842
3843 { 0x1f, 0x0004 },
3844 { 0x1c, 0x0000 },
3845 { 0x1f, 0x0000 },
3846
3847 { 0x1f, 0x0001 },
3848 { 0x15, 0x7701 },
3849 { 0x1f, 0x0000 }
3850 };
3851
3852 /* Disable ALDPS before ram code */
eef63cc1
FR		 3853 rtl_writephy(tp, 0x1f, 0x0000);
3854 rtl_writephy(tp, 0x18, 0x0310);
3855 msleep(100);
5a5e4443 3856
953a12cc 3857 rtl_apply_firmware(tp);
5a5e4443
HW		 3858
3859 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3860}
3861
7e18dca1
HW		 3862static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3863{
7e18dca1 3864 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3865 rtl_writephy(tp, 0x1f, 0x0000);
3866 rtl_writephy(tp, 0x18, 0x0310);
3867 msleep(20);
7e18dca1
HW		 3868
3869 rtl_apply_firmware(tp);
3870
3871 /* EEE setting */
fdf6fc06 3872 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3873 rtl_writephy(tp, 0x1f, 0x0004);
3874 rtl_writephy(tp, 0x10, 0x401f);
3875 rtl_writephy(tp, 0x19, 0x7030);
3876 rtl_writephy(tp, 0x1f, 0x0000);
3877}
3878
5598bfe5
HW		 3879static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3880{
5598bfe5
HW		 3881 static const struct phy_reg phy_reg_init[] = {
3882 { 0x1f, 0x0004 },
3883 { 0x10, 0xc07f },
3884 { 0x19, 0x7030 },
3885 { 0x1f, 0x0000 }
3886 };
3887
3888 /* Disable ALDPS before ram code */
eef63cc1
FR		 3889 rtl_writephy(tp, 0x1f, 0x0000);
3890 rtl_writephy(tp, 0x18, 0x0310);
3891 msleep(100);
5598bfe5
HW		 3892
3893 rtl_apply_firmware(tp);
3894
fdf6fc06 3895 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3896 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3897
fdf6fc06 3898 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3899}
3900
5615d9f1
FR		 3901static void rtl_hw_phy_config(struct net_device *dev)
3902{
3903 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3904
3905 rtl8169_print_mac_version(tp);
3906
3907 switch (tp->mac_version) {
3908 case RTL_GIGA_MAC_VER_01:
3909 break;
3910 case RTL_GIGA_MAC_VER_02:
3911 case RTL_GIGA_MAC_VER_03:
4da19633 3912 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3913 break;
3914 case RTL_GIGA_MAC_VER_04:
4da19633 3915 rtl8169sb_hw_phy_config(tp);
5615d9f1 3916 break;
2e955856 3917 case RTL_GIGA_MAC_VER_05:
4da19633 3918 rtl8169scd_hw_phy_config(tp);
2e955856 3919 break;
8c7006aa 3920 case RTL_GIGA_MAC_VER_06:
4da19633 3921 rtl8169sce_hw_phy_config(tp);
8c7006aa 3922 break;
2857ffb7
FR		 3923 case RTL_GIGA_MAC_VER_07:
3924 case RTL_GIGA_MAC_VER_08:
3925 case RTL_GIGA_MAC_VER_09:
4da19633 3926 rtl8102e_hw_phy_config(tp);
2857ffb7 3927 break;
236b8082 3928 case RTL_GIGA_MAC_VER_11:
4da19633 3929 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3930 break;
3931 case RTL_GIGA_MAC_VER_12:
4da19633 3932 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3933 break;
3934 case RTL_GIGA_MAC_VER_17:
4da19633 3935 rtl8168bef_hw_phy_config(tp);
236b8082 3936 break;
867763c1 3937 case RTL_GIGA_MAC_VER_18:
4da19633 3938 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3939 break;
3940 case RTL_GIGA_MAC_VER_19:
4da19633 3941 rtl8168c_1_hw_phy_config(tp);
867763c1 3942 break;
7da97ec9 3943 case RTL_GIGA_MAC_VER_20:
4da19633 3944 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3945 break;
197ff761 3946 case RTL_GIGA_MAC_VER_21:
4da19633 3947 rtl8168c_3_hw_phy_config(tp);
197ff761 3948 break;
6fb07058 3949 case RTL_GIGA_MAC_VER_22:
4da19633 3950 rtl8168c_4_hw_phy_config(tp);
6fb07058 3951 break;
ef3386f0 3952 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3953 case RTL_GIGA_MAC_VER_24:
4da19633 3954 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3955 break;
5b538df9 3956 case RTL_GIGA_MAC_VER_25:
bca03d5f 3957 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3958 break;
3959 case RTL_GIGA_MAC_VER_26:
bca03d5f 3960 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3961 break;
3962 case RTL_GIGA_MAC_VER_27:
4da19633 3963 rtl8168d_3_hw_phy_config(tp);
5b538df9 3964 break;
e6de30d6 3965 case RTL_GIGA_MAC_VER_28:
3966 rtl8168d_4_hw_phy_config(tp);
3967 break;
5a5e4443
HW		 3968 case RTL_GIGA_MAC_VER_29:
3969 case RTL_GIGA_MAC_VER_30:
3970 rtl8105e_hw_phy_config(tp);
3971 break;
cecb5fd7
FR		 3972 case RTL_GIGA_MAC_VER_31:
3973 /* None. */
3974 break;
01dc7fec 3975 case RTL_GIGA_MAC_VER_32:
01dc7fec 3976 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3977 rtl8168e_1_hw_phy_config(tp);
3978 break;
3979 case RTL_GIGA_MAC_VER_34:
3980 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3981 break;
c2218925
HW		 3982 case RTL_GIGA_MAC_VER_35:
3983 rtl8168f_1_hw_phy_config(tp);
3984 break;
3985 case RTL_GIGA_MAC_VER_36:
3986 rtl8168f_2_hw_phy_config(tp);
3987 break;
ef3386f0 3988
7e18dca1
HW		 3989 case RTL_GIGA_MAC_VER_37:
3990 rtl8402_hw_phy_config(tp);
3991 break;
3992
b3d7b2f2
HW		 3993 case RTL_GIGA_MAC_VER_38:
3994 rtl8411_hw_phy_config(tp);
3995 break;
3996
5598bfe5
HW		 3997 case RTL_GIGA_MAC_VER_39:
3998 rtl8106e_hw_phy_config(tp);
3999 break;
4000
c558386b
HW		 4001 case RTL_GIGA_MAC_VER_40:
4002 rtl8168g_1_hw_phy_config(tp);
4003 break;
57538c4a 4004 case RTL_GIGA_MAC_VER_42:
58152cd4 4005 case RTL_GIGA_MAC_VER_43:
45dd95c4 4006 case RTL_GIGA_MAC_VER_44:
57538c4a 4007 rtl8168g_2_hw_phy_config(tp);
4008 break;
6e1d0b89
CHL		 4009 case RTL_GIGA_MAC_VER_45:
4010 case RTL_GIGA_MAC_VER_47:
4011 rtl8168h_1_hw_phy_config(tp);
4012 break;
4013 case RTL_GIGA_MAC_VER_46:
4014 case RTL_GIGA_MAC_VER_48:
4015 rtl8168h_2_hw_phy_config(tp);
4016 break;
c558386b 4017
935e2218
CHL		 4018 case RTL_GIGA_MAC_VER_49:
4019 rtl8168ep_1_hw_phy_config(tp);
4020 break;
4021 case RTL_GIGA_MAC_VER_50:
4022 case RTL_GIGA_MAC_VER_51:
4023 rtl8168ep_2_hw_phy_config(tp);
4024 break;
4025
c558386b 4026 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 4027 default:
4028 break;
4029 }
4030}
4031
da78dbff
FR		 4032static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4033{
da78dbff
FR		 4034 if (!test_and_set_bit(flag, tp->wk.flags))
4035 schedule_work(&tp->wk.work);
da78dbff
FR		 4036}
4037
2544bfc0
FR		 4038static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4039{
2544bfc0 4040 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
e397286b 4041 (RTL_R8(tp, PHYstatus) & TBI_Enable);
2544bfc0
FR		 4042}
4043
4ff96fa6
FR		 4044static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4045{
5615d9f1 4046 rtl_hw_phy_config(dev);
4ff96fa6 4047
77332894 4048 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
49d17512
HK		 4049 netif_dbg(tp, drv, dev,
4050 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 4051 RTL_W8(tp, 0x82, 0x01);
77332894 4052 }
4ff96fa6 4053
6dccd16b
FR		 4054 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4055
4056 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4057 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4058
bcf0bf90 4059 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
49d17512
HK		 4060 netif_dbg(tp, drv, dev,
4061 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 4062 RTL_W8(tp, 0x82, 0x01);
49d17512
HK		 4063 netif_dbg(tp, drv, dev,
4064 "Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4065 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4066 }
4067
5b7ad4b7
HK		 4068 /* We may have called phy_speed_down before */
4069 phy_speed_up(dev->phydev);
4070
f75222bc 4071 genphy_soft_reset(dev->phydev);
4ff96fa6
FR		 4072}
4073
773d2021
FR		 4074static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4075{
da78dbff 4076 rtl_lock_work(tp);
773d2021 4077
1ef7286e 4078 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
908ba2bf 4079
1ef7286e
AS		 4080 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4081 RTL_R32(tp, MAC4);
908ba2bf 4082
1ef7286e
AS		 4083 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4084 RTL_R32(tp, MAC0);
908ba2bf 4085
9ecb9aab 4086 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4087 rtl_rar_exgmac_set(tp, addr);
c28aa385 4088
1ef7286e 4089 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
773d2021 4090
da78dbff 4091 rtl_unlock_work(tp);
773d2021
FR		 4092}
4093
4094static int rtl_set_mac_address(struct net_device *dev, void *p)
4095{
4096 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 4097 struct device *d = tp_to_dev(tp);
1f7aa2bc 4098 int ret;
773d2021 4099
1f7aa2bc
HK		 4100 ret = eth_mac_addr(dev, p);
4101 if (ret)
4102 return ret;
773d2021 4103
f51d4a10
CHL		 4104 pm_runtime_get_noresume(d);
4105
4106 if (pm_runtime_active(d))
4107 rtl_rar_set(tp, dev->dev_addr);
4108
4109 pm_runtime_put_noidle(d);
773d2021
FR		 4110
4111 return 0;
4112}
4113
e397286b 4114static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8b4ab28d 4115{
69b3c59f
HK		 4116 if (!netif_running(dev))
4117 return -ENODEV;
e397286b 4118
69b3c59f 4119 return phy_mii_ioctl(dev->phydev, ifr, cmd);
8b4ab28d
FR		 4120}
4121
baf63293 4122static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4123{
4124 struct mdio_ops *ops = &tp->mdio_ops;
4125
4126 switch (tp->mac_version) {
4127 case RTL_GIGA_MAC_VER_27:
4128 ops->write = r8168dp_1_mdio_write;
4129 ops->read = r8168dp_1_mdio_read;
4130 break;
e6de30d6 4131 case RTL_GIGA_MAC_VER_28:
4804b3b3 4132 case RTL_GIGA_MAC_VER_31:
e6de30d6 4133 ops->write = r8168dp_2_mdio_write;
4134 ops->read = r8168dp_2_mdio_read;
4135 break;
2a71883c 4136 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
c558386b
HW		 4137 ops->write = r8168g_mdio_write;
4138 ops->read = r8168g_mdio_read;
4139 break;
c0e45c1c 4140 default:
4141 ops->write = r8169_mdio_write;
4142 ops->read = r8169_mdio_read;
4143 break;
4144 }
4145}
4146
649b3b8c 4147static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4148{
649b3b8c 4149 switch (tp->mac_version) {
b00e69de
CB		 4150 case RTL_GIGA_MAC_VER_25:
4151 case RTL_GIGA_MAC_VER_26:
649b3b8c 4152 case RTL_GIGA_MAC_VER_29:
4153 case RTL_GIGA_MAC_VER_30:
4154 case RTL_GIGA_MAC_VER_32:
4155 case RTL_GIGA_MAC_VER_33:
4156 case RTL_GIGA_MAC_VER_34:
2a71883c 4157 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4158 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
649b3b8c 4159 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4160 break;
4161 default:
4162 break;
4163 }
4164}
4165
4166static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4167{
6fcf9b1d 4168 if (!netif_running(tp->dev) || !__rtl8169_get_wol(tp))
649b3b8c 4169 return false;
4170
5b7ad4b7 4171 phy_speed_down(tp->dev->phydev, false);
649b3b8c 4172 rtl_wol_suspend_quirk(tp);
4173
4174 return true;
4175}
4176
065c27c1 4177static void r8168_pll_power_down(struct rtl8169_private *tp)
4178{
9dbe7896 4179 if (r8168_check_dash(tp))
065c27c1 4180 return;
4181
01dc7fec 4182 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4183 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4184 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4185
649b3b8c 4186 if (rtl_wol_pll_power_down(tp))
065c27c1 4187 return;
065c27c1 4188
065c27c1 4189 switch (tp->mac_version) {
2a71883c 4190 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4191 case RTL_GIGA_MAC_VER_37:
4192 case RTL_GIGA_MAC_VER_39:
4193 case RTL_GIGA_MAC_VER_43:
42fde737 4194 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4195 case RTL_GIGA_MAC_VER_45:
4196 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4197 case RTL_GIGA_MAC_VER_47:
4198 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4199 case RTL_GIGA_MAC_VER_50:
4200 case RTL_GIGA_MAC_VER_51:
1ef7286e 4201 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
065c27c1 4202 break;
beb330a4 4203 case RTL_GIGA_MAC_VER_40:
4204 case RTL_GIGA_MAC_VER_41:
935e2218 4205 case RTL_GIGA_MAC_VER_49:
706123d0 4206 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 4207 0xfc000000, ERIAR_EXGMAC);
1ef7286e 4208 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
beb330a4 4209 break;
065c27c1 4210 }
4211}
4212
4213static void r8168_pll_power_up(struct rtl8169_private *tp)
4214{
065c27c1 4215 switch (tp->mac_version) {
2a71883c 4216 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4217 case RTL_GIGA_MAC_VER_37:
4218 case RTL_GIGA_MAC_VER_39:
4219 case RTL_GIGA_MAC_VER_43:
1ef7286e 4220 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
065c27c1 4221 break;
42fde737 4222 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4223 case RTL_GIGA_MAC_VER_45:
4224 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4225 case RTL_GIGA_MAC_VER_47:
4226 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4227 case RTL_GIGA_MAC_VER_50:
4228 case RTL_GIGA_MAC_VER_51:
1ef7286e 4229 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
6e1d0b89 4230 break;
beb330a4 4231 case RTL_GIGA_MAC_VER_40:
4232 case RTL_GIGA_MAC_VER_41:
935e2218 4233 case RTL_GIGA_MAC_VER_49:
1ef7286e 4234 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
706123d0 4235 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 4236 0x00000000, ERIAR_EXGMAC);
4237 break;
065c27c1 4238 }
4239
242cd9b5
HK		 4240 phy_resume(tp->dev->phydev);
4241 /* give MAC/PHY some time to resume */
4242 msleep(20);
065c27c1 4243}
4244
065c27c1 4245static void rtl_pll_power_down(struct rtl8169_private *tp)
4246{
4f447d29
HK		 4247 switch (tp->mac_version) {
4248 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4249 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4250 break;
4251 default:
4252 r8168_pll_power_down(tp);
4253 }
065c27c1 4254}
4255
4256static void rtl_pll_power_up(struct rtl8169_private *tp)
4257{
065c27c1 4258 switch (tp->mac_version) {
4f447d29
HK		 4259 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4260 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
065c27c1 4261 break;
065c27c1 4262 default:
4f447d29 4263 r8168_pll_power_up(tp);
065c27c1 4264 }
4265}
4266
e542a226
HW		 4267static void rtl_init_rxcfg(struct rtl8169_private *tp)
4268{
e542a226 4269 switch (tp->mac_version) {
2a71883c
HK		 4270 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4271 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
1ef7286e 4272 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
e542a226 4273 break;
2a71883c 4274 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
eb2dc35d 4275 case RTL_GIGA_MAC_VER_34:
3ced8c95 4276 case RTL_GIGA_MAC_VER_35:
1ef7286e 4277 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
e542a226 4278 break;
2a71883c 4279 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4280 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 4281 break;
e542a226 4282 default:
1ef7286e 4283 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
e542a226
HW		 4284 break;
4285 }
4286}
4287
92fc43b4
HW		 4288static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4289{
9fba0812 4290 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4291}
4292
d58d46b5
FR		 4293static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4294{
eda40b8c
HK		 4295 if (tp->jumbo_ops.enable) {
4296 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4297 tp->jumbo_ops.enable(tp);
4298 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4299 }
d58d46b5
FR		 4300}
4301
4302static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4303{
eda40b8c
HK		 4304 if (tp->jumbo_ops.disable) {
4305 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4306 tp->jumbo_ops.disable(tp);
4307 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4308 }
d58d46b5
FR		 4309}
4310
4311static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4312{
1ef7286e
AS		 4313 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4314 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
cb73200c 4315 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4316}
4317
4318static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4319{
1ef7286e
AS		 4320 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4321 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
8d98aa39 4322 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4323}
4324
4325static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4326{
1ef7286e 4327 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
d58d46b5
FR		 4328}
4329
4330static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4331{
1ef7286e 4332 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
d58d46b5
FR		 4333}
4334
4335static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4336{
1ef7286e
AS		 4337 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4338 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4339 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
cb73200c 4340 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4341}
4342
4343static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4344{
1ef7286e
AS		 4345 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4346 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4347 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
8d98aa39 4348 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4349}
4350
4351static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4352{
cb73200c 4353 rtl_tx_performance_tweak(tp,
f65d539c 4354 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4355}
4356
4357static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4358{
cb73200c 4359 rtl_tx_performance_tweak(tp,
8d98aa39 4360 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4361}
4362
4363static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4364{
d58d46b5
FR		 4365 r8168b_0_hw_jumbo_enable(tp);
4366
1ef7286e 4367 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
d58d46b5
FR		 4368}
4369
4370static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4371{
d58d46b5
FR		 4372 r8168b_0_hw_jumbo_disable(tp);
4373
1ef7286e 4374 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
d58d46b5
FR		 4375}
4376
baf63293 4377static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4378{
4379 struct jumbo_ops *ops = &tp->jumbo_ops;
4380
4381 switch (tp->mac_version) {
4382 case RTL_GIGA_MAC_VER_11:
4383 ops->disable = r8168b_0_hw_jumbo_disable;
4384 ops->enable = r8168b_0_hw_jumbo_enable;
4385 break;
4386 case RTL_GIGA_MAC_VER_12:
4387 case RTL_GIGA_MAC_VER_17:
4388 ops->disable = r8168b_1_hw_jumbo_disable;
4389 ops->enable = r8168b_1_hw_jumbo_enable;
4390 break;
4391 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4392 case RTL_GIGA_MAC_VER_19:
4393 case RTL_GIGA_MAC_VER_20:
4394 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4395 case RTL_GIGA_MAC_VER_22:
4396 case RTL_GIGA_MAC_VER_23:
4397 case RTL_GIGA_MAC_VER_24:
4398 case RTL_GIGA_MAC_VER_25:
4399 case RTL_GIGA_MAC_VER_26:
4400 ops->disable = r8168c_hw_jumbo_disable;
4401 ops->enable = r8168c_hw_jumbo_enable;
4402 break;
4403 case RTL_GIGA_MAC_VER_27:
4404 case RTL_GIGA_MAC_VER_28:
4405 ops->disable = r8168dp_hw_jumbo_disable;
4406 ops->enable = r8168dp_hw_jumbo_enable;
4407 break;
4408 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4409 case RTL_GIGA_MAC_VER_32:
4410 case RTL_GIGA_MAC_VER_33:
4411 case RTL_GIGA_MAC_VER_34:
4412 ops->disable = r8168e_hw_jumbo_disable;
4413 ops->enable = r8168e_hw_jumbo_enable;
4414 break;
4415
4416 /*
4417 * No action needed for jumbo frames with 8169.
4418 * No jumbo for 810x at all.
4419 */
2a71883c 4420 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 4421 default:
4422 ops->disable = NULL;
4423 ops->enable = NULL;
4424 break;
4425 }
4426}
4427
ffc46952
FR		 4428DECLARE_RTL_COND(rtl_chipcmd_cond)
4429{
1ef7286e 4430 return RTL_R8(tp, ChipCmd) & CmdReset;
ffc46952
FR		 4431}
4432
6f43adc8
FR		 4433static void rtl_hw_reset(struct rtl8169_private *tp)
4434{
1ef7286e 4435 RTL_W8(tp, ChipCmd, CmdReset);
6f43adc8 4436
ffc46952 4437 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4438}
4439
b6ffd97f 4440static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4441{
b6ffd97f
FR		 4442 struct rtl_fw *rtl_fw;
4443 const char *name;
4444 int rc = -ENOMEM;
953a12cc 4445
b6ffd97f
FR		 4446 name = rtl_lookup_firmware_name(tp);
4447 if (!name)
4448 goto out_no_firmware;
953a12cc 4449
b6ffd97f
FR		 4450 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4451 if (!rtl_fw)
4452 goto err_warn;
31bd204f 4453
1e1205b7 4454 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
b6ffd97f
FR		 4455 if (rc < 0)
4456 goto err_free;
4457
fd112f2e
FR		 4458 rc = rtl_check_firmware(tp, rtl_fw);
4459 if (rc < 0)
4460 goto err_release_firmware;
4461
b6ffd97f
FR		 4462 tp->rtl_fw = rtl_fw;
4463out:
4464 return;
4465
fd112f2e
FR		 4466err_release_firmware:
4467 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4468err_free:
4469 kfree(rtl_fw);
4470err_warn:
4471 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4472 name, rc);
4473out_no_firmware:
4474 tp->rtl_fw = NULL;
4475 goto out;
4476}
4477
4478static void rtl_request_firmware(struct rtl8169_private *tp)
4479{
4480 if (IS_ERR(tp->rtl_fw))
4481 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4482}
4483
92fc43b4
HW		 4484static void rtl_rx_close(struct rtl8169_private *tp)
4485{
1ef7286e 4486 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4487}
4488
ffc46952
FR		 4489DECLARE_RTL_COND(rtl_npq_cond)
4490{
1ef7286e 4491 return RTL_R8(tp, TxPoll) & NPQ;
ffc46952
FR		 4492}
4493
4494DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4495{
1ef7286e 4496 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
ffc46952
FR		 4497}
4498
e6de30d6 4499static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4
LT		 4500{
4501 /* Disable interrupts */
811fd301 4502 rtl8169_irq_mask_and_ack(tp);
1da177e4 4503
92fc43b4
HW		 4504 rtl_rx_close(tp);
4505
b2d43e6e
HK		 4506 switch (tp->mac_version) {
4507 case RTL_GIGA_MAC_VER_27:
4508 case RTL_GIGA_MAC_VER_28:
4509 case RTL_GIGA_MAC_VER_31:
ffc46952 4510 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
b2d43e6e
HK		 4511 break;
4512 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4513 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4514 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
ffc46952 4515 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
b2d43e6e
HK		 4516 break;
4517 default:
1ef7286e 4518 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
92fc43b4 4519 udelay(100);
b2d43e6e 4520 break;
e6de30d6 4521 }
4522
92fc43b4 4523 rtl_hw_reset(tp);
1da177e4
LT		 4524}
4525
05212ba8 4526static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
9cb427b6 4527{
9cb427b6 4528 /* Set DMA burst size and Interframe Gap Time */
1ef7286e 4529 RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
9cb427b6
FR		 4530 (InterFrameGap << TxInterFrameGapShift));
4531}
4532
4fd48c4a 4533static void rtl_set_rx_max_size(struct rtl8169_private *tp)
1da177e4 4534{
4fd48c4a
HK		 4535 /* Low hurts. Let's disable the filtering. */
4536 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
07ce4064
FR		 4537}
4538
1ef7286e 4539static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
7f796d83
FR		 4540{
4541 /*
4542 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4543 * register to be written before TxDescAddrLow to work.
4544 * Switching from MMIO to I/O access fixes the issue as well.
4545 */
1ef7286e
AS		 4546 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4547 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4548 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4549 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4550}
4551
1ef7286e 4552static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
6dccd16b 4553{
3744100e 4554 static const struct rtl_cfg2_info {
6dccd16b
FR		 4555 u32 mac_version;
4556 u32 clk;
4557 u32 val;
4558 } cfg2_info [] = {
4559 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4560 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4561 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4562 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4563 };
4564 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4565 unsigned int i;
4566 u32 clk;
4567
1ef7286e 4568 clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
cadf1855 4569 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b 4570 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1ef7286e 4571 RTL_W32(tp, 0x7c, p->val);
6dccd16b
FR		 4572 break;
4573 }
4574 }
4575}
4576
e6b763ea
FR		 4577static void rtl_set_rx_mode(struct net_device *dev)
4578{
4579 struct rtl8169_private *tp = netdev_priv(dev);
e6b763ea
FR		 4580 u32 mc_filter[2]; /* Multicast hash filter */
4581 int rx_mode;
4582 u32 tmp = 0;
4583
4584 if (dev->flags & IFF_PROMISC) {
4585 /* Unconditionally log net taps. */
4586 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4587 rx_mode =
4588 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4589 AcceptAllPhys;
4590 mc_filter[1] = mc_filter[0] = 0xffffffff;
4591 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4592 (dev->flags & IFF_ALLMULTI)) {
4593 /* Too many to filter perfectly -- accept all multicasts. */
4594 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4595 mc_filter[1] = mc_filter[0] = 0xffffffff;
4596 } else {
4597 struct netdev_hw_addr *ha;
4598
4599 rx_mode = AcceptBroadcast | AcceptMyPhys;
4600 mc_filter[1] = mc_filter[0] = 0;
4601 netdev_for_each_mc_addr(ha, dev) {
4602 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4603 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4604 rx_mode |= AcceptMulticast;
4605 }
4606 }
4607
4608 if (dev->features & NETIF_F_RXALL)
4609 rx_mode |= (AcceptErr | AcceptRunt);
4610
1ef7286e 4611 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
e6b763ea
FR		 4612
4613 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4614 u32 data = mc_filter[0];
4615
4616 mc_filter[0] = swab32(mc_filter[1]);
4617 mc_filter[1] = swab32(data);
4618 }
4619
0481776b
NW		 4620 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4621 mc_filter[1] = mc_filter[0] = 0xffffffff;
4622
1ef7286e
AS		 4623 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4624 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
e6b763ea 4625
1ef7286e 4626 RTL_W32(tp, RxConfig, tmp);
e6b763ea
FR		 4627}
4628
52f8560e
HK		 4629static void rtl_hw_start(struct rtl8169_private *tp)
4630{
4631 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4632
4633 tp->hw_start(tp);
4634
4635 rtl_set_rx_max_size(tp);
4636 rtl_set_rx_tx_desc_registers(tp);
52f8560e
HK		 4637 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4638
4639 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4640 RTL_R8(tp, IntrMask);
4641 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
05212ba8 4642 rtl_init_rxcfg(tp);
f74dd480 4643 rtl_set_tx_config_registers(tp);
05212ba8 4644
52f8560e
HK		 4645 rtl_set_rx_mode(tp->dev);
4646 /* no early-rx interrupts */
4647 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4648 rtl_irq_enable_all(tp);
4649}
4650
61cb532d 4651static void rtl_hw_start_8169(struct rtl8169_private *tp)
07ce4064 4652{
0ae0974e 4653 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
61cb532d 4654 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
9cb427b6 4655
1ef7286e 4656 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
1da177e4 4657
0ae0974e 4658 tp->cp_cmd |= PCIMulRW;
1da177e4 4659
cecb5fd7
FR		 4660 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4661 tp->mac_version == RTL_GIGA_MAC_VER_03) {
49d17512
HK		 4662 netif_dbg(tp, drv, tp->dev,
4663 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
bcf0bf90 4664 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4665 }
4666
1ef7286e 4667 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
bcf0bf90 4668
1ef7286e 4669 rtl8169_set_magic_reg(tp, tp->mac_version);
6dccd16b 4670
1da177e4
LT		 4671 /*
4672 * Undocumented corner. Supposedly:
4673 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4674 */
1ef7286e 4675 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4 4676
1ef7286e 4677 RTL_W32(tp, RxMissed, 0);
07ce4064 4678}
1da177e4 4679
ffc46952
FR		 4680DECLARE_RTL_COND(rtl_csiar_cond)
4681{
1ef7286e 4682 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
ffc46952
FR		 4683}
4684
ff1d7331 4685static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
beb1fe18 4686{
ff1d7331 4687 u32 func = PCI_FUNC(tp->pci_dev->devfn);
beb1fe18 4688
1ef7286e
AS		 4689 RTL_W32(tp, CSIDR, value);
4690 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
ff1d7331 4691 CSIAR_BYTE_ENABLE | func << 16);
7e18dca1 4692
ffc46952 4693 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4694}
4695
ff1d7331 4696static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4697{
ff1d7331
HK		 4698 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4699
4700 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4701 CSIAR_BYTE_ENABLE);
7e18dca1 4702
ffc46952 4703 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 4704 RTL_R32(tp, CSIDR) : ~0;
7e18dca1
HW		 4705}
4706
ff1d7331 4707static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
45dd95c4 4708{
ff1d7331
HK		 4709 struct pci_dev *pdev = tp->pci_dev;
4710 u32 csi;
45dd95c4 4711
ff1d7331
HK		 4712 /* According to Realtek the value at config space address 0x070f
4713 * controls the L0s/L1 entrance latency. We try standard ECAM access
4714 * first and if it fails fall back to CSI.
4715 */
4716 if (pdev->cfg_size > 0x070f &&
4717 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4718 return;
4719
4720 netdev_notice_once(tp->dev,
4721 "No native access to PCI extended config space, falling back to CSI\n");
4722 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4723 rtl_csi_write(tp, 0x070c, csi | val << 24);
45dd95c4 4724}
4725
f37658da 4726static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
beb1fe18 4727{
ff1d7331 4728 rtl_csi_access_enable(tp, 0x27);
dacf8154
FR		 4729}
4730
4731struct ephy_info {
4732 unsigned int offset;
4733 u16 mask;
4734 u16 bits;
4735};
4736
fdf6fc06
FR		 4737static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4738 int len)
dacf8154
FR		 4739{
4740 u16 w;
4741
4742 while (len-- > 0) {
fdf6fc06
FR		 4743 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4744 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4745 e++;
4746 }
4747}
4748
73c86ee3 4749static void rtl_disable_clock_request(struct rtl8169_private *tp)
b726e493 4750{
73c86ee3 4751 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4752 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4753}
4754
73c86ee3 4755static void rtl_enable_clock_request(struct rtl8169_private *tp)
e6de30d6 4756{
73c86ee3 4757 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4758 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4759}
4760
b51ecea8 4761static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4762{
b51ecea8 4763 u8 data;
4764
1ef7286e 4765 data = RTL_R8(tp, Config3);
b51ecea8 4766
4767 if (enable)
4768 data |= Rdy_to_L23;
4769 else
4770 data &= ~Rdy_to_L23;
4771
1ef7286e 4772 RTL_W8(tp, Config3, data);
b51ecea8 4773}
4774
a99790bf
KHF		 4775static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4776{
4777 if (enable) {
a99790bf 4778 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
94235460 4779 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
a99790bf
KHF		 4780 } else {
4781 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4782 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4783 }
94235460
KHF		 4784
4785 udelay(10);
a99790bf
KHF		 4786}
4787
beb1fe18 4788static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4789{
1ef7286e 4790 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 4791
12d42c50 4792 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4793 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
b726e493 4794
faf1e785 4795 if (tp->dev->mtu <= ETH_DATA_LEN) {
8d98aa39 4796 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
faf1e785 4797 PCI_EXP_DEVCTL_NOSNOOP_EN);
4798 }
219a1e9d
FR		 4799}
4800
beb1fe18 4801static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4802{
beb1fe18 4803 rtl_hw_start_8168bb(tp);
b726e493 4804
1ef7286e 4805 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
b726e493 4806
1ef7286e 4807 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
219a1e9d
FR		 4808}
4809
beb1fe18 4810static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4811{
1ef7286e 4812 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
b726e493 4813
1ef7286e 4814 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 4815
faf1e785 4816 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4817 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
b726e493 4818
73c86ee3 4819 rtl_disable_clock_request(tp);
b726e493 4820
12d42c50 4821 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4822 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
219a1e9d
FR		 4823}
4824
beb1fe18 4825static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4826{
350f7596 4827 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4828 { 0x01, 0, 0x0001 },
4829 { 0x02, 0x0800, 0x1000 },
4830 { 0x03, 0, 0x0042 },
4831 { 0x06, 0x0080, 0x0000 },
4832 { 0x07, 0, 0x2000 }
4833 };
4834
f37658da 4835 rtl_set_def_aspm_entry_latency(tp);
b726e493 4836
fdf6fc06 4837 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4838
beb1fe18 4839 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4840}
4841
beb1fe18 4842static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4843{
f37658da 4844 rtl_set_def_aspm_entry_latency(tp);
ef3386f0 4845
1ef7286e 4846 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
ef3386f0 4847
faf1e785 4848 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4849 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
ef3386f0 4850
12d42c50 4851 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4852 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
ef3386f0
FR		 4853}
4854
beb1fe18 4855static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4856{
f37658da 4857 rtl_set_def_aspm_entry_latency(tp);
7f3e3d3a 4858
1ef7286e 4859 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
7f3e3d3a
FR		 4860
4861 /* Magic. */
1ef7286e 4862 RTL_W8(tp, DBG_REG, 0x20);
7f3e3d3a 4863
1ef7286e 4864 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
7f3e3d3a 4865
faf1e785 4866 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4867 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7f3e3d3a 4868
12d42c50 4869 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4870 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
7f3e3d3a
FR		 4871}
4872
beb1fe18 4873static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4874{
350f7596 4875 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4876 { 0x02, 0x0800, 0x1000 },
4877 { 0x03, 0, 0x0002 },
4878 { 0x06, 0x0080, 0x0000 }
4879 };
4880
f37658da 4881 rtl_set_def_aspm_entry_latency(tp);
b726e493 4882
1ef7286e 4883 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
b726e493 4884
fdf6fc06 4885 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 4886
beb1fe18 4887 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4888}
4889
beb1fe18 4890static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4891{
350f7596 4892 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4893 { 0x01, 0, 0x0001 },
4894 { 0x03, 0x0400, 0x0220 }
4895 };
4896
f37658da 4897 rtl_set_def_aspm_entry_latency(tp);
b726e493 4898
fdf6fc06 4899 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 4900
beb1fe18 4901 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4902}
4903
beb1fe18 4904static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4905{
beb1fe18 4906 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4907}
4908
beb1fe18 4909static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4910{
f37658da 4911 rtl_set_def_aspm_entry_latency(tp);
6fb07058 4912
beb1fe18 4913 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4914}
4915
beb1fe18 4916static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4917{
f37658da 4918 rtl_set_def_aspm_entry_latency(tp);
5b538df9 4919
73c86ee3 4920 rtl_disable_clock_request(tp);
5b538df9 4921
1ef7286e 4922 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5b538df9 4923
faf1e785 4924 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4925 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5b538df9 4926
12d42c50 4927 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4928 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5b538df9
FR		 4929}
4930
beb1fe18 4931static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4932{
f37658da 4933 rtl_set_def_aspm_entry_latency(tp);
4804b3b3 4934
faf1e785 4935 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4936 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4804b3b3 4937
1ef7286e 4938 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4804b3b3 4939
73c86ee3 4940 rtl_disable_clock_request(tp);
4804b3b3 4941}
4942
beb1fe18 4943static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4944{
4945 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 4946 { 0x0b, 0x0000, 0x0048 },
4947 { 0x19, 0x0020, 0x0050 },
4948 { 0x0c, 0x0100, 0x0020 }
e6de30d6 4949 };
e6de30d6 4950
f37658da 4951 rtl_set_def_aspm_entry_latency(tp);
e6de30d6 4952
8d98aa39 4953 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
e6de30d6 4954
1ef7286e 4955 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
e6de30d6 4956
1016a4a1 4957 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
e6de30d6 4958
73c86ee3 4959 rtl_enable_clock_request(tp);
e6de30d6 4960}
4961
beb1fe18 4962static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4963{
70090424 4964 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4965 { 0x00, 0x0200, 0x0100 },
4966 { 0x00, 0x0000, 0x0004 },
4967 { 0x06, 0x0002, 0x0001 },
4968 { 0x06, 0x0000, 0x0030 },
4969 { 0x07, 0x0000, 0x2000 },
4970 { 0x00, 0x0000, 0x0020 },
4971 { 0x03, 0x5800, 0x2000 },
4972 { 0x03, 0x0000, 0x0001 },
4973 { 0x01, 0x0800, 0x1000 },
4974 { 0x07, 0x0000, 0x4000 },
4975 { 0x1e, 0x0000, 0x2000 },
4976 { 0x19, 0xffff, 0xfe6c },
4977 { 0x0a, 0x0000, 0x0040 }
4978 };
4979
f37658da 4980 rtl_set_def_aspm_entry_latency(tp);
01dc7fec 4981
fdf6fc06 4982 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4983
faf1e785 4984 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4985 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
01dc7fec 4986
1ef7286e 4987 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
01dc7fec 4988
73c86ee3 4989 rtl_disable_clock_request(tp);
01dc7fec 4990
4991 /* Reset tx FIFO pointer */
1ef7286e
AS		 4992 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4993 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
01dc7fec 4994
1ef7286e 4995 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
01dc7fec 4996}
4997
beb1fe18 4998static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424
HW		 4999{
5000 static const struct ephy_info e_info_8168e_2[] = {
5001 { 0x09, 0x0000, 0x0080 },
5002 { 0x19, 0x0000, 0x0224 }
5003 };
5004
f37658da 5005 rtl_set_def_aspm_entry_latency(tp);
70090424 5006
fdf6fc06 5007 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5008
faf1e785 5009 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5010 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
70090424 5011
fdf6fc06
FR		 5012 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5013 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5014 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5015 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5016 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5017 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 5018 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5019 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5020
1ef7286e 5021 RTL_W8(tp, MaxTxPacketSize, EarlySize);
70090424 5022
73c86ee3 5023 rtl_disable_clock_request(tp);
4521e1a9 5024
1ef7286e
AS		 5025 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5026 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
70090424
HW		 5027
5028 /* Adjust EEE LED frequency */
1ef7286e 5029 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
70090424 5030
1ef7286e
AS		 5031 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5032 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5033 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
aa1e7d2c
HK		 5034
5035 rtl_hw_aspm_clkreq_enable(tp, true);
70090424
HW		 5036}
5037
5f886e08 5038static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5039{
f37658da 5040 rtl_set_def_aspm_entry_latency(tp);
c2218925 5041
8d98aa39 5042 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c2218925 5043
fdf6fc06
FR		 5044 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5045 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5046 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5047 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 5048 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5049 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5050 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5051 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5052 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5053 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925 5054
1ef7286e 5055 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c2218925 5056
73c86ee3 5057 rtl_disable_clock_request(tp);
4521e1a9 5058
1ef7286e
AS		 5059 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5060 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5061 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5062 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5063 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
c2218925
HW		 5064}
5065
5f886e08
HW		 5066static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5067{
5f886e08
HW		 5068 static const struct ephy_info e_info_8168f_1[] = {
5069 { 0x06, 0x00c0, 0x0020 },
5070 { 0x08, 0x0001, 0x0002 },
5071 { 0x09, 0x0000, 0x0080 },
5072 { 0x19, 0x0000, 0x0224 }
5073 };
5074
5075 rtl_hw_start_8168f(tp);
5076
fdf6fc06 5077 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5078
706123d0 5079 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5080
5081 /* Adjust EEE LED frequency */
1ef7286e 5082 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5f886e08
HW		 5083}
5084
b3d7b2f2
HW		 5085static void rtl_hw_start_8411(struct rtl8169_private *tp)
5086{
b3d7b2f2
HW		 5087 static const struct ephy_info e_info_8168f_1[] = {
5088 { 0x06, 0x00c0, 0x0020 },
5089 { 0x0f, 0xffff, 0x5200 },
5090 { 0x1e, 0x0000, 0x4000 },
5091 { 0x19, 0x0000, 0x0224 }
5092 };
5093
5094 rtl_hw_start_8168f(tp);
b51ecea8 5095 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 5096
fdf6fc06 5097 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5098
706123d0 5099 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5100}
5101
5fbea337 5102static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b 5103{
1ef7286e 5104 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
beb330a4 5105
c558386b
HW		 5106 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5107 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5108 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5109 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5110
f37658da 5111 rtl_set_def_aspm_entry_latency(tp);
c558386b 5112
8d98aa39 5113 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c558386b 5114
706123d0
CHL		 5115 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5116 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5117 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 5118
1ef7286e
AS		 5119 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5120 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c558386b
HW		 5121
5122 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5123 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5124
5125 /* Adjust EEE LED frequency */
1ef7286e 5126 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
c558386b 5127
706123d0
CHL		 5128 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5129 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 5130
5131 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 5132}
5133
5fbea337
CHL		 5134static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5135{
5fbea337
CHL		 5136 static const struct ephy_info e_info_8168g_1[] = {
5137 { 0x00, 0x0000, 0x0008 },
5138 { 0x0c, 0x37d0, 0x0820 },
5139 { 0x1e, 0x0000, 0x0001 },
5140 { 0x19, 0x8000, 0x0000 }
5141 };
5142
5143 rtl_hw_start_8168g(tp);
5144
5145 /* disable aspm and clock request before access ephy */
a99790bf 5146 rtl_hw_aspm_clkreq_enable(tp, false);
5fbea337 5147 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
a99790bf 5148 rtl_hw_aspm_clkreq_enable(tp, true);
5fbea337
CHL		 5149}
5150
57538c4a 5151static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5152{
57538c4a 5153 static const struct ephy_info e_info_8168g_2[] = {
5154 { 0x00, 0x0000, 0x0008 },
5155 { 0x0c, 0x3df0, 0x0200 },
5156 { 0x19, 0xffff, 0xfc00 },
5157 { 0x1e, 0xffff, 0x20eb }
5158 };
5159
5fbea337 5160 rtl_hw_start_8168g(tp);
57538c4a 5161
5162 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 5163 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5164 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
57538c4a 5165 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5166}
5167
45dd95c4 5168static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5169{
45dd95c4 5170 static const struct ephy_info e_info_8411_2[] = {
5171 { 0x00, 0x0000, 0x0008 },
5172 { 0x0c, 0x3df0, 0x0200 },
5173 { 0x0f, 0xffff, 0x5200 },
5174 { 0x19, 0x0020, 0x0000 },
5175 { 0x1e, 0x0000, 0x2000 }
5176 };
5177
5fbea337 5178 rtl_hw_start_8168g(tp);
45dd95c4 5179
5180 /* disable aspm and clock request before access ephy */
a99790bf 5181 rtl_hw_aspm_clkreq_enable(tp, false);
45dd95c4 5182 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
a99790bf 5183 rtl_hw_aspm_clkreq_enable(tp, true);
45dd95c4 5184}
5185
6e1d0b89
CHL		 5186static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5187{
72521ea0 5188 int rg_saw_cnt;
6e1d0b89
CHL		 5189 u32 data;
5190 static const struct ephy_info e_info_8168h_1[] = {
5191 { 0x1e, 0x0800, 0x0001 },
5192 { 0x1d, 0x0000, 0x0800 },
5193 { 0x05, 0xffff, 0x2089 },
5194 { 0x06, 0xffff, 0x5881 },
5195 { 0x04, 0xffff, 0x154a },
5196 { 0x01, 0xffff, 0x068b }
5197 };
5198
5199 /* disable aspm and clock request before access ephy */
a99790bf 5200 rtl_hw_aspm_clkreq_enable(tp, false);
6e1d0b89
CHL		 5201 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5202
1ef7286e 5203 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6e1d0b89
CHL		 5204
5205 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5206 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5207 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5208 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5209
f37658da 5210 rtl_set_def_aspm_entry_latency(tp);
6e1d0b89 5211
8d98aa39 5212 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6e1d0b89 5213
706123d0
CHL		 5214 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5215 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 5216
706123d0 5217 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 5218
706123d0 5219 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 5220
5221 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5222
1ef7286e
AS		 5223 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5224 RTL_W8(tp, MaxTxPacketSize, EarlySize);
6e1d0b89
CHL		 5225
5226 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5227 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5228
5229 /* Adjust EEE LED frequency */
1ef7286e 5230 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6e1d0b89 5231
1ef7286e
AS		 5232 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5233 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89 5234
1ef7286e 5235 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6e1d0b89 5236
706123d0 5237 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 5238
5239 rtl_pcie_state_l2l3_enable(tp, false);
5240
5241 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 5242 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 5243 rtl_writephy(tp, 0x1f, 0x0000);
5244 if (rg_saw_cnt > 0) {
5245 u16 sw_cnt_1ms_ini;
5246
5247 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5248 sw_cnt_1ms_ini &= 0x0fff;
5249 data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec0 5250 data &= ~0x0fff;
6e1d0b89
CHL		 5251 data |= sw_cnt_1ms_ini;
5252 r8168_mac_ocp_write(tp, 0xd412, data);
5253 }
5254
5255 data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec0
CHL		 5256 data &= ~0xf0;
5257 data |= 0x70;
6e1d0b89
CHL		 5258 r8168_mac_ocp_write(tp, 0xe056, data);
5259
5260 data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec0
CHL		 5261 data &= ~0x6000;
5262 data |= 0x8008;
6e1d0b89
CHL		 5263 r8168_mac_ocp_write(tp, 0xe052, data);
5264
5265 data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec0 5266 data &= ~0x01ff;
6e1d0b89
CHL		 5267 data |= 0x017f;
5268 r8168_mac_ocp_write(tp, 0xe0d6, data);
5269
5270 data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec0 5271 data &= ~0x0fff;
6e1d0b89
CHL		 5272 data |= 0x047f;
5273 r8168_mac_ocp_write(tp, 0xd420, data);
5274
5275 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5276 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5277 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5278 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
a99790bf
KHF		 5279
5280 rtl_hw_aspm_clkreq_enable(tp, true);
6e1d0b89
CHL		 5281}
5282
935e2218
CHL		 5283static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5284{
003609da
CHL		 5285 rtl8168ep_stop_cmac(tp);
5286
1ef7286e 5287 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
935e2218
CHL		 5288
5289 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5290 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5291 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5292 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5293
f37658da 5294 rtl_set_def_aspm_entry_latency(tp);
935e2218 5295
8d98aa39 5296 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
935e2218
CHL		 5297
5298 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5299 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5300
5301 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5302
5303 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5304
1ef7286e
AS		 5305 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5306 RTL_W8(tp, MaxTxPacketSize, EarlySize);
935e2218
CHL		 5307
5308 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5309 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5310
5311 /* Adjust EEE LED frequency */
1ef7286e 5312 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
935e2218
CHL		 5313
5314 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5315
1ef7286e 5316 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
935e2218
CHL		 5317
5318 rtl_pcie_state_l2l3_enable(tp, false);
5319}
5320
5321static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5322{
935e2218
CHL		 5323 static const struct ephy_info e_info_8168ep_1[] = {
5324 { 0x00, 0xffff, 0x10ab },
5325 { 0x06, 0xffff, 0xf030 },
5326 { 0x08, 0xffff, 0x2006 },
5327 { 0x0d, 0xffff, 0x1666 },
5328 { 0x0c, 0x3ff0, 0x0000 }
5329 };
5330
5331 /* disable aspm and clock request before access ephy */
a99790bf 5332 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5333 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5334
5335 rtl_hw_start_8168ep(tp);
a99790bf
KHF		 5336
5337 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5338}
5339
5340static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5341{
935e2218
CHL		 5342 static const struct ephy_info e_info_8168ep_2[] = {
5343 { 0x00, 0xffff, 0x10a3 },
5344 { 0x19, 0xffff, 0xfc00 },
5345 { 0x1e, 0xffff, 0x20ea }
5346 };
5347
5348 /* disable aspm and clock request before access ephy */
a99790bf 5349 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5350 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5351
5352 rtl_hw_start_8168ep(tp);
5353
1ef7286e
AS		 5354 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5355 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
a99790bf
KHF		 5356
5357 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5358}
5359
5360static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5361{
935e2218
CHL		 5362 u32 data;
5363 static const struct ephy_info e_info_8168ep_3[] = {
5364 { 0x00, 0xffff, 0x10a3 },
5365 { 0x19, 0xffff, 0x7c00 },
5366 { 0x1e, 0xffff, 0x20eb },
5367 { 0x0d, 0xffff, 0x1666 }
5368 };
5369
5370 /* disable aspm and clock request before access ephy */
a99790bf 5371 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5372 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5373
5374 rtl_hw_start_8168ep(tp);
5375
1ef7286e
AS		 5376 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5377 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 5378
5379 data = r8168_mac_ocp_read(tp, 0xd3e2);
5380 data &= 0xf000;
5381 data |= 0x0271;
5382 r8168_mac_ocp_write(tp, 0xd3e2, data);
5383
5384 data = r8168_mac_ocp_read(tp, 0xd3e4);
5385 data &= 0xff00;
5386 r8168_mac_ocp_write(tp, 0xd3e4, data);
5387
5388 data = r8168_mac_ocp_read(tp, 0xe860);
5389 data |= 0x0080;
5390 r8168_mac_ocp_write(tp, 0xe860, data);
a99790bf
KHF		 5391
5392 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5393}
5394
61cb532d 5395static void rtl_hw_start_8168(struct rtl8169_private *tp)
07ce4064 5396{
1ef7286e 5397 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
2dd99530 5398
0ae0974e
HK		 5399 tp->cp_cmd &= ~INTT_MASK;
5400 tp->cp_cmd |= PktCntrDisable | INTT_1;
1ef7286e 5401 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2dd99530 5402
1ef7286e 5403 RTL_W16(tp, IntrMitigate, 0x5151);
2dd99530 5404
0e485150 5405 /* Work around for RxFIFO overflow. */
811fd301 5406 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5407 tp->event_slow |= RxFIFOOver | PCSTimeout;
5408 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5409 }
5410
219a1e9d
FR		 5411 switch (tp->mac_version) {
5412 case RTL_GIGA_MAC_VER_11:
beb1fe18 5413 rtl_hw_start_8168bb(tp);
4804b3b3 5414 break;
219a1e9d
FR		 5415
5416 case RTL_GIGA_MAC_VER_12:
5417 case RTL_GIGA_MAC_VER_17:
beb1fe18 5418 rtl_hw_start_8168bef(tp);
4804b3b3 5419 break;
219a1e9d
FR		 5420
5421 case RTL_GIGA_MAC_VER_18:
beb1fe18 5422 rtl_hw_start_8168cp_1(tp);
4804b3b3 5423 break;
219a1e9d
FR		 5424
5425 case RTL_GIGA_MAC_VER_19:
beb1fe18 5426 rtl_hw_start_8168c_1(tp);
4804b3b3 5427 break;
219a1e9d
FR		 5428
5429 case RTL_GIGA_MAC_VER_20:
beb1fe18 5430 rtl_hw_start_8168c_2(tp);
4804b3b3 5431 break;
219a1e9d 5432
197ff761 5433 case RTL_GIGA_MAC_VER_21:
beb1fe18 5434 rtl_hw_start_8168c_3(tp);
4804b3b3 5435 break;
197ff761 5436
6fb07058 5437 case RTL_GIGA_MAC_VER_22:
beb1fe18 5438 rtl_hw_start_8168c_4(tp);
4804b3b3 5439 break;
6fb07058 5440
ef3386f0 5441 case RTL_GIGA_MAC_VER_23:
beb1fe18 5442 rtl_hw_start_8168cp_2(tp);
4804b3b3 5443 break;
ef3386f0 5444
7f3e3d3a 5445 case RTL_GIGA_MAC_VER_24:
beb1fe18 5446 rtl_hw_start_8168cp_3(tp);
4804b3b3 5447 break;
7f3e3d3a 5448
5b538df9 5449 case RTL_GIGA_MAC_VER_25:
daf9df6d 5450 case RTL_GIGA_MAC_VER_26:
5451 case RTL_GIGA_MAC_VER_27:
beb1fe18 5452 rtl_hw_start_8168d(tp);
4804b3b3 5453 break;
5b538df9 5454
e6de30d6 5455 case RTL_GIGA_MAC_VER_28:
beb1fe18 5456 rtl_hw_start_8168d_4(tp);
4804b3b3 5457 break;
cecb5fd7 5458
4804b3b3 5459 case RTL_GIGA_MAC_VER_31:
beb1fe18 5460 rtl_hw_start_8168dp(tp);
4804b3b3 5461 break;
5462
01dc7fec 5463 case RTL_GIGA_MAC_VER_32:
5464 case RTL_GIGA_MAC_VER_33:
beb1fe18 5465 rtl_hw_start_8168e_1(tp);
70090424
HW		 5466 break;
5467 case RTL_GIGA_MAC_VER_34:
beb1fe18 5468 rtl_hw_start_8168e_2(tp);
01dc7fec 5469 break;
e6de30d6 5470
c2218925
HW		 5471 case RTL_GIGA_MAC_VER_35:
5472 case RTL_GIGA_MAC_VER_36:
beb1fe18 5473 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5474 break;
5475
b3d7b2f2
HW		 5476 case RTL_GIGA_MAC_VER_38:
5477 rtl_hw_start_8411(tp);
5478 break;
5479
c558386b
HW		 5480 case RTL_GIGA_MAC_VER_40:
5481 case RTL_GIGA_MAC_VER_41:
5482 rtl_hw_start_8168g_1(tp);
5483 break;
57538c4a 5484 case RTL_GIGA_MAC_VER_42:
5485 rtl_hw_start_8168g_2(tp);
5486 break;
c558386b 5487
45dd95c4 5488 case RTL_GIGA_MAC_VER_44:
5489 rtl_hw_start_8411_2(tp);
5490 break;
5491
6e1d0b89
CHL		 5492 case RTL_GIGA_MAC_VER_45:
5493 case RTL_GIGA_MAC_VER_46:
5494 rtl_hw_start_8168h_1(tp);
5495 break;
5496
935e2218
CHL		 5497 case RTL_GIGA_MAC_VER_49:
5498 rtl_hw_start_8168ep_1(tp);
5499 break;
5500
5501 case RTL_GIGA_MAC_VER_50:
5502 rtl_hw_start_8168ep_2(tp);
5503 break;
5504
5505 case RTL_GIGA_MAC_VER_51:
5506 rtl_hw_start_8168ep_3(tp);
5507 break;
5508
219a1e9d 5509 default:
49d17512
HK		 5510 netif_err(tp, drv, tp->dev,
5511 "unknown chipset (mac_version = %d)\n",
5512 tp->mac_version);
4804b3b3 5513 break;
219a1e9d 5514 }
07ce4064 5515}
1da177e4 5516
beb1fe18 5517static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5518{
350f7596 5519 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5520 { 0x01, 0, 0x6e65 },
5521 { 0x02, 0, 0x091f },
5522 { 0x03, 0, 0xc2f9 },
5523 { 0x06, 0, 0xafb5 },
5524 { 0x07, 0, 0x0e00 },
5525 { 0x19, 0, 0xec80 },
5526 { 0x01, 0, 0x2e65 },
5527 { 0x01, 0, 0x6e65 }
5528 };
5529 u8 cfg1;
5530
f37658da 5531 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5532
1ef7286e 5533 RTL_W8(tp, DBG_REG, FIX_NAK_1);
2857ffb7 5534
8d98aa39 5535 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 5536
1ef7286e 5537 RTL_W8(tp, Config1,
2857ffb7 5538 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
1ef7286e 5539 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7 5540
1ef7286e 5541 cfg1 = RTL_R8(tp, Config1);
2857ffb7 5542 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
1ef7286e 5543 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
2857ffb7 5544
fdf6fc06 5545 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5546}
5547
beb1fe18 5548static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5549{
f37658da 5550 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5551
8d98aa39 5552 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 5553
1ef7286e
AS		 5554 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5555 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7
FR		 5556}
5557
beb1fe18 5558static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5559{
beb1fe18 5560 rtl_hw_start_8102e_2(tp);
2857ffb7 5561
fdf6fc06 5562 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5563}
5564
beb1fe18 5565static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443
HW		 5566{
5567 static const struct ephy_info e_info_8105e_1[] = {
5568 { 0x07, 0, 0x4000 },
5569 { 0x19, 0, 0x0200 },
5570 { 0x19, 0, 0x0020 },
5571 { 0x1e, 0, 0x2000 },
5572 { 0x03, 0, 0x0001 },
5573 { 0x19, 0, 0x0100 },
5574 { 0x19, 0, 0x0004 },
5575 { 0x0a, 0, 0x0020 }
5576 };
5577
cecb5fd7 5578 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5579 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5a5e4443 5580
cecb5fd7 5581 /* Disable Early Tally Counter */
1ef7286e 5582 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5a5e4443 5583
1ef7286e
AS		 5584 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5585 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5a5e4443 5586
fdf6fc06 5587 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 5588
5589 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 5590}
5591
beb1fe18 5592static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5593{
beb1fe18 5594 rtl_hw_start_8105e_1(tp);
fdf6fc06 5595 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5596}
5597
7e18dca1
HW		 5598static void rtl_hw_start_8402(struct rtl8169_private *tp)
5599{
7e18dca1
HW		 5600 static const struct ephy_info e_info_8402[] = {
5601 { 0x19, 0xffff, 0xff64 },
5602 { 0x1e, 0, 0x4000 }
5603 };
5604
f37658da 5605 rtl_set_def_aspm_entry_latency(tp);
7e18dca1
HW		 5606
5607 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5608 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
7e18dca1 5609
1ef7286e
AS		 5610 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5611 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7e18dca1 5612
fdf6fc06 5613 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1 5614
8d98aa39 5615 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7e18dca1 5616
fdf6fc06
FR		 5617 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5618 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 5619 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5620 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5621 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5622 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 5623 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 5624
5625 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 5626}
5627
5598bfe5
HW		 5628static void rtl_hw_start_8106(struct rtl8169_private *tp)
5629{
0866cd15
KHF		 5630 rtl_hw_aspm_clkreq_enable(tp, false);
5631
5598bfe5 5632 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5633 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5598bfe5 5634
1ef7286e
AS		 5635 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5636 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5637 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
b51ecea8 5638
5639 rtl_pcie_state_l2l3_enable(tp, false);
0866cd15 5640 rtl_hw_aspm_clkreq_enable(tp, true);
5598bfe5
HW		 5641}
5642
61cb532d 5643static void rtl_hw_start_8101(struct rtl8169_private *tp)
07ce4064 5644{
da78dbff
FR		 5645 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5646 tp->event_slow &= ~RxFIFOOver;
811fd301 5647
cecb5fd7 5648 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5649 tp->mac_version == RTL_GIGA_MAC_VER_16)
61cb532d 5650 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
8200bc72 5651 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5652
1ef7286e 5653 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
1a964649 5654
12d42c50 5655 tp->cp_cmd &= CPCMD_QUIRK_MASK;
1ef7286e 5656 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1a964649 5657
2857ffb7
FR		 5658 switch (tp->mac_version) {
5659 case RTL_GIGA_MAC_VER_07:
beb1fe18 5660 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5661 break;
5662
5663 case RTL_GIGA_MAC_VER_08:
beb1fe18 5664 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5665 break;
5666
5667 case RTL_GIGA_MAC_VER_09:
beb1fe18 5668 rtl_hw_start_8102e_2(tp);
2857ffb7 5669 break;
5a5e4443
HW		 5670
5671 case RTL_GIGA_MAC_VER_29:
beb1fe18 5672 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5673 break;
5674 case RTL_GIGA_MAC_VER_30:
beb1fe18 5675 rtl_hw_start_8105e_2(tp);
5a5e4443 5676 break;
7e18dca1
HW		 5677
5678 case RTL_GIGA_MAC_VER_37:
5679 rtl_hw_start_8402(tp);
5680 break;
5598bfe5
HW		 5681
5682 case RTL_GIGA_MAC_VER_39:
5683 rtl_hw_start_8106(tp);
5684 break;
58152cd4 5685 case RTL_GIGA_MAC_VER_43:
5686 rtl_hw_start_8168g_2(tp);
5687 break;
6e1d0b89
CHL		 5688 case RTL_GIGA_MAC_VER_47:
5689 case RTL_GIGA_MAC_VER_48:
5690 rtl_hw_start_8168h_1(tp);
5691 break;
cdf1a608
FR		 5692 }
5693
1ef7286e 5694 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4
LT		 5695}
5696
5697static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5698{
d58d46b5
FR		 5699 struct rtl8169_private *tp = netdev_priv(dev);
5700
d58d46b5
FR		 5701 if (new_mtu > ETH_DATA_LEN)
5702 rtl_hw_jumbo_enable(tp);
5703 else
5704 rtl_hw_jumbo_disable(tp);
5705
1da177e4 5706 dev->mtu = new_mtu;
350fb32a
MM		 5707 netdev_update_features(dev);
5708
323bb685 5709 return 0;
1da177e4
LT		 5710}
5711
5712static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5713{
95e0918d 5714 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5715 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5716}
5717
6f0333b8
ED		 5718static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5719 void **data_buff, struct RxDesc *desc)
1da177e4 5720{
1d0254dd
HK		 5721 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5722 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
48addcc9 5723
6f0333b8
ED		 5724 kfree(*data_buff);
5725 *data_buff = NULL;
1da177e4
LT		 5726 rtl8169_make_unusable_by_asic(desc);
5727}
5728
1d0254dd 5729static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
1da177e4
LT		 5730{
5731 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5732
a0750138
AD		 5733 /* Force memory writes to complete before releasing descriptor */
5734 dma_wmb();
5735
1d0254dd 5736 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
1da177e4
LT		 5737}
5738
6f0333b8
ED		 5739static inline void *rtl8169_align(void *data)
5740{
5741 return (void *)ALIGN((long)data, 16);
5742}
5743
0ecbe1ca
SG		 5744static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5745 struct RxDesc *desc)
1da177e4 5746{
6f0333b8 5747 void *data;
1da177e4 5748 dma_addr_t mapping;
1e1205b7 5749 struct device *d = tp_to_dev(tp);
d3b404c2 5750 int node = dev_to_node(d);
1da177e4 5751
1d0254dd 5752 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
6f0333b8
ED		 5753 if (!data)
5754 return NULL;
e9f63f30 5755
6f0333b8
ED		 5756 if (rtl8169_align(data) != data) {
5757 kfree(data);
1d0254dd 5758 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
6f0333b8
ED		 5759 if (!data)
5760 return NULL;
5761 }
3eafe507 5762
1d0254dd 5763 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
231aee63 5764 DMA_FROM_DEVICE);
d827d86b
SG		 5765 if (unlikely(dma_mapping_error(d, mapping))) {
5766 if (net_ratelimit())
5767 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5768 goto err_out;
d827d86b 5769 }
1da177e4 5770
d731af78
HK		 5771 desc->addr = cpu_to_le64(mapping);
5772 rtl8169_mark_to_asic(desc);
6f0333b8 5773 return data;
3eafe507
SG		 5774
5775err_out:
5776 kfree(data);
5777 return NULL;
1da177e4
LT		 5778}
5779
5780static void rtl8169_rx_clear(struct rtl8169_private *tp)
5781{
07d3f51f 5782 unsigned int i;
1da177e4
LT		 5783
5784 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5785 if (tp->Rx_databuff[i]) {
5786 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5787 tp->RxDescArray + i);
5788 }
5789 }
5790}
5791
0ecbe1ca 5792static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5793{
0ecbe1ca
SG		 5794 desc->opts1 |= cpu_to_le32(RingEnd);
5795}
5b0384f4 5796
0ecbe1ca
SG		 5797static int rtl8169_rx_fill(struct rtl8169_private *tp)
5798{
5799 unsigned int i;
1da177e4 5800
0ecbe1ca
SG		 5801 for (i = 0; i < NUM_RX_DESC; i++) {
5802 void *data;
4ae47c2d 5803
0ecbe1ca 5804 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5805 if (!data) {
5806 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5807 goto err_out;
6f0333b8
ED		 5808 }
5809 tp->Rx_databuff[i] = data;
1da177e4 5810 }
1da177e4 5811
0ecbe1ca
SG		 5812 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5813 return 0;
5814
5815err_out:
5816 rtl8169_rx_clear(tp);
5817 return -ENOMEM;
1da177e4
LT		 5818}
5819
b1127e64 5820static int rtl8169_init_ring(struct rtl8169_private *tp)
1da177e4 5821{
1da177e4
LT		 5822 rtl8169_init_ring_indexes(tp);
5823
b1127e64
HK		 5824 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5825 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
1da177e4 5826
0ecbe1ca 5827 return rtl8169_rx_fill(tp);
1da177e4
LT		 5828}
5829
48addcc9 5830static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5831 struct TxDesc *desc)
5832{
5833 unsigned int len = tx_skb->len;
5834
48addcc9
SG		 5835 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5836
1da177e4
LT		 5837 desc->opts1 = 0x00;
5838 desc->opts2 = 0x00;
5839 desc->addr = 0x00;
5840 tx_skb->len = 0;
5841}
5842
3eafe507
SG		 5843static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5844 unsigned int n)
1da177e4
LT		 5845{
5846 unsigned int i;
5847
3eafe507
SG		 5848 for (i = 0; i < n; i++) {
5849 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5850 struct ring_info *tx_skb = tp->tx_skb + entry;
5851 unsigned int len = tx_skb->len;
5852
5853 if (len) {
5854 struct sk_buff *skb = tx_skb->skb;
5855
1e1205b7 5856 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
1da177e4
LT		 5857 tp->TxDescArray + entry);
5858 if (skb) {
7a4b813c 5859 dev_consume_skb_any(skb);
1da177e4
LT		 5860 tx_skb->skb = NULL;
5861 }
1da177e4
LT		 5862 }
5863 }
3eafe507
SG		 5864}
5865
5866static void rtl8169_tx_clear(struct rtl8169_private *tp)
5867{
5868 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5869 tp->cur_tx = tp->dirty_tx = 0;
5870}
5871
4422bcd4 5872static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5873{
c4028958 5874 struct net_device *dev = tp->dev;
56de414c 5875 int i;
1da177e4 5876
da78dbff
FR		 5877 napi_disable(&tp->napi);
5878 netif_stop_queue(dev);
5879 synchronize_sched();
1da177e4 5880
c7c2c39b 5881 rtl8169_hw_reset(tp);
5882
56de414c 5883 for (i = 0; i < NUM_RX_DESC; i++)
1d0254dd 5884 rtl8169_mark_to_asic(tp->RxDescArray + i);
56de414c 5885
1da177e4 5886 rtl8169_tx_clear(tp);
c7c2c39b 5887 rtl8169_init_ring_indexes(tp);
1da177e4 5888
da78dbff 5889 napi_enable(&tp->napi);
61cb532d 5890 rtl_hw_start(tp);
56de414c 5891 netif_wake_queue(dev);
1da177e4
LT		 5892}
5893
5894static void rtl8169_tx_timeout(struct net_device *dev)
5895{
da78dbff
FR		 5896 struct rtl8169_private *tp = netdev_priv(dev);
5897
5898 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5899}
5900
5901static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5902 u32 *opts)
1da177e4
LT		 5903{
5904 struct skb_shared_info *info = skb_shinfo(skb);
5905 unsigned int cur_frag, entry;
6e1d0b89 5906 struct TxDesc *uninitialized_var(txd);
1e1205b7 5907 struct device *d = tp_to_dev(tp);
1da177e4
LT		 5908
5909 entry = tp->cur_tx;
5910 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5911 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5912 dma_addr_t mapping;
5913 u32 status, len;
5914 void *addr;
5915
5916 entry = (entry + 1) % NUM_TX_DESC;
5917
5918 txd = tp->TxDescArray + entry;
9e903e08 5919 len = skb_frag_size(frag);
929f6189 5920 addr = skb_frag_address(frag);
48addcc9 5921 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5922 if (unlikely(dma_mapping_error(d, mapping))) {
5923 if (net_ratelimit())
5924 netif_err(tp, drv, tp->dev,
5925 "Failed to map TX fragments DMA!\n");
3eafe507 5926 goto err_out;
d827d86b 5927 }
1da177e4 5928
cecb5fd7 5929 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5930 status = opts[0] | len |
5931 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5932
5933 txd->opts1 = cpu_to_le32(status);
2b7b4318 5934 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5935 txd->addr = cpu_to_le64(mapping);
5936
5937 tp->tx_skb[entry].len = len;
5938 }
5939
5940 if (cur_frag) {
5941 tp->tx_skb[entry].skb = skb;
5942 txd->opts1 |= cpu_to_le32(LastFrag);
5943 }
5944
5945 return cur_frag;
3eafe507
SG		 5946
5947err_out:
5948 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5949 return -EIO;
1da177e4
LT		 5950}
5951
b423e9ae 5952static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5953{
5954 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5955}
5956
e974604b 5957static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5958 struct net_device *dev);
5959/* r8169_csum_workaround()
5960 * The hw limites the value the transport offset. When the offset is out of the
5961 * range, calculate the checksum by sw.
5962 */
5963static void r8169_csum_workaround(struct rtl8169_private *tp,
5964 struct sk_buff *skb)
5965{
5966 if (skb_shinfo(skb)->gso_size) {
5967 netdev_features_t features = tp->dev->features;
5968 struct sk_buff *segs, *nskb;
5969
5970 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5971 segs = skb_gso_segment(skb, features);
5972 if (IS_ERR(segs) || !segs)
5973 goto drop;
5974
5975 do {
5976 nskb = segs;
5977 segs = segs->next;
5978 nskb->next = NULL;
5979 rtl8169_start_xmit(nskb, tp->dev);
5980 } while (segs);
5981
eb781397 5982 dev_consume_skb_any(skb);
e974604b 5983 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5984 if (skb_checksum_help(skb) < 0)
5985 goto drop;
5986
5987 rtl8169_start_xmit(skb, tp->dev);
5988 } else {
5989 struct net_device_stats *stats;
5990
5991drop:
5992 stats = &tp->dev->stats;
5993 stats->tx_dropped++;
eb781397 5994 dev_kfree_skb_any(skb);
e974604b 5995 }
5996}
5997
5998/* msdn_giant_send_check()
5999 * According to the document of microsoft, the TCP Pseudo Header excludes the
6000 * packet length for IPv6 TCP large packets.
6001 */
6002static int msdn_giant_send_check(struct sk_buff *skb)
6003{
6004 const struct ipv6hdr *ipv6h;
6005 struct tcphdr *th;
6006 int ret;
6007
6008 ret = skb_cow_head(skb, 0);
6009 if (ret)
6010 return ret;
6011
6012 ipv6h = ipv6_hdr(skb);
6013 th = tcp_hdr(skb);
6014
6015 th->check = 0;
6016 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6017
6018 return ret;
6019}
6020
5888d3fc 6021static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6022 struct sk_buff *skb, u32 *opts)
1da177e4 6023{
350fb32a
MM		 6024 u32 mss = skb_shinfo(skb)->gso_size;
6025
2b7b4318
FR		 6026 if (mss) {
6027 opts[0] |= TD_LSO;
5888d3fc 6028 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6029 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6030 const struct iphdr *ip = ip_hdr(skb);
6031
6032 if (ip->protocol == IPPROTO_TCP)
6033 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6034 else if (ip->protocol == IPPROTO_UDP)
6035 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6036 else
6037 WARN_ON_ONCE(1);
6038 }
6039
6040 return true;
6041}
6042
6043static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6044 struct sk_buff *skb, u32 *opts)
6045{
bdfa4ed6 6046 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 6047 u32 mss = skb_shinfo(skb)->gso_size;
6048
6049 if (mss) {
e974604b 6050 if (transport_offset > GTTCPHO_MAX) {
6051 netif_warn(tp, tx_err, tp->dev,
6052 "Invalid transport offset 0x%x for TSO\n",
6053 transport_offset);
6054 return false;
6055 }
6056
4ff36466 6057 switch (vlan_get_protocol(skb)) {
e974604b 6058 case htons(ETH_P_IP):
6059 opts[0] |= TD1_GTSENV4;
6060 break;
6061
6062 case htons(ETH_P_IPV6):
6063 if (msdn_giant_send_check(skb))
6064 return false;
6065
6066 opts[0] |= TD1_GTSENV6;
6067 break;
6068
6069 default:
6070 WARN_ON_ONCE(1);
6071 break;
6072 }
6073
bdfa4ed6 6074 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 6075 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 6076 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 6077 u8 ip_protocol;
1da177e4 6078
b423e9ae 6079 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6080 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
b423e9ae 6081
e974604b 6082 if (transport_offset > TCPHO_MAX) {
6083 netif_warn(tp, tx_err, tp->dev,
6084 "Invalid transport offset 0x%x\n",
6085 transport_offset);
6086 return false;
6087 }
6088
4ff36466 6089 switch (vlan_get_protocol(skb)) {
e974604b 6090 case htons(ETH_P_IP):
6091 opts[1] |= TD1_IPv4_CS;
6092 ip_protocol = ip_hdr(skb)->protocol;
6093 break;
6094
6095 case htons(ETH_P_IPV6):
6096 opts[1] |= TD1_IPv6_CS;
6097 ip_protocol = ipv6_hdr(skb)->nexthdr;
6098 break;
6099
6100 default:
6101 ip_protocol = IPPROTO_RAW;
6102 break;
6103 }
6104
6105 if (ip_protocol == IPPROTO_TCP)
6106 opts[1] |= TD1_TCP_CS;
6107 else if (ip_protocol == IPPROTO_UDP)
6108 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 6109 else
6110 WARN_ON_ONCE(1);
e974604b 6111
6112 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 6113 } else {
6114 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6115 return !eth_skb_pad(skb);
1da177e4 6116 }
5888d3fc 6117
b423e9ae 6118 return true;
1da177e4
LT		 6119}
6120
61357325
SH		 6121static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6122 struct net_device *dev)
1da177e4
LT		 6123{
6124 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 6125 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4 6126 struct TxDesc *txd = tp->TxDescArray + entry;
1e1205b7 6127 struct device *d = tp_to_dev(tp);
1da177e4
LT		 6128 dma_addr_t mapping;
6129 u32 status, len;
2b7b4318 6130 u32 opts[2];
3eafe507 6131 int frags;
5b0384f4 6132
477206a0 6133 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 6134 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 6135 goto err_stop_0;
1da177e4
LT		 6136 }
6137
6138 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 6139 goto err_stop_0;
6140
b423e9ae 6141 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6142 opts[0] = DescOwn;
6143
e974604b 6144 if (!tp->tso_csum(tp, skb, opts)) {
6145 r8169_csum_workaround(tp, skb);
6146 return NETDEV_TX_OK;
6147 }
b423e9ae 6148
3eafe507 6149 len = skb_headlen(skb);
48addcc9 6150 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 6151 if (unlikely(dma_mapping_error(d, mapping))) {
6152 if (net_ratelimit())
6153 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 6154 goto err_dma_0;
d827d86b 6155 }
3eafe507
SG		 6156
6157 tp->tx_skb[entry].len = len;
6158 txd->addr = cpu_to_le64(mapping);
1da177e4 6159
2b7b4318 6160 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 6161 if (frags < 0)
6162 goto err_dma_1;
6163 else if (frags)
2b7b4318 6164 opts[0] |= FirstFrag;
3eafe507 6165 else {
2b7b4318 6166 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 6167 tp->tx_skb[entry].skb = skb;
6168 }
6169
2b7b4318
FR		 6170 txd->opts2 = cpu_to_le32(opts[1]);
6171
5047fb5d
RC		 6172 skb_tx_timestamp(skb);
6173
a0750138
AD		 6174 /* Force memory writes to complete before releasing descriptor */
6175 dma_wmb();
1da177e4 6176
cecb5fd7 6177 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 6178 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6179 txd->opts1 = cpu_to_le32(status);
6180
a0750138 6181 /* Force all memory writes to complete before notifying device */
4c020a96 6182 wmb();
1da177e4 6183
a0750138
AD		 6184 tp->cur_tx += frags + 1;
6185
1ef7286e 6186 RTL_W8(tp, TxPoll, NPQ);
1da177e4 6187
87cda7cb 6188 mmiowb();
da78dbff 6189
87cda7cb 6190 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 6191 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6192 * not miss a ring update when it notices a stopped queue.
6193 */
6194 smp_wmb();
1da177e4 6195 netif_stop_queue(dev);
ae1f23fb
FR		 6196 /* Sync with rtl_tx:
6197 * - publish queue status and cur_tx ring index (write barrier)
6198 * - refresh dirty_tx ring index (read barrier).
6199 * May the current thread have a pessimistic view of the ring
6200 * status and forget to wake up queue, a racing rtl_tx thread
6201 * can't.
6202 */
1e874e04 6203 smp_mb();
477206a0 6204 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 6205 netif_wake_queue(dev);
6206 }
6207
61357325 6208 return NETDEV_TX_OK;
1da177e4 6209
3eafe507 6210err_dma_1:
48addcc9 6211 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 6212err_dma_0:
989c9ba1 6213 dev_kfree_skb_any(skb);
3eafe507
SG		 6214 dev->stats.tx_dropped++;
6215 return NETDEV_TX_OK;
6216
6217err_stop_0:
1da177e4 6218 netif_stop_queue(dev);
cebf8cc7 6219 dev->stats.tx_dropped++;
61357325 6220 return NETDEV_TX_BUSY;
1da177e4
LT		 6221}
6222
6223static void rtl8169_pcierr_interrupt(struct net_device *dev)
6224{
6225 struct rtl8169_private *tp = netdev_priv(dev);
6226 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 6227 u16 pci_status, pci_cmd;
6228
6229 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6230 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6231
bf82c189
JP		 6232 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6233 pci_cmd, pci_status);
1da177e4
LT		 6234
6235 /*
6236 * The recovery sequence below admits a very elaborated explanation:
6237 * - it seems to work;
d03902b8
FR		 6238 * - I did not see what else could be done;
6239 * - it makes iop3xx happy.
1da177e4
LT		 6240 *
6241 * Feel free to adjust to your needs.
6242 */
a27993f3 6243 if (pdev->broken_parity_status)
d03902b8
FR		 6244 pci_cmd &= ~PCI_COMMAND_PARITY;
6245 else
6246 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6247
6248 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 6249
6250 pci_write_config_word(pdev, PCI_STATUS,
6251 pci_status & (PCI_STATUS_DETECTED_PARITY |
6252 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6253 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6254
6255 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 6256 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
bf82c189 6257 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4 6258 tp->cp_cmd &= ~PCIDAC;
1ef7286e 6259 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1da177e4 6260 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 6261 }
6262
e6de30d6 6263 rtl8169_hw_reset(tp);
d03902b8 6264
98ddf986 6265 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6266}
6267
da78dbff 6268static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 6269{
6270 unsigned int dirty_tx, tx_left;
6271
1da177e4
LT		 6272 dirty_tx = tp->dirty_tx;
6273 smp_rmb();
6274 tx_left = tp->cur_tx - dirty_tx;
6275
6276 while (tx_left > 0) {
6277 unsigned int entry = dirty_tx % NUM_TX_DESC;
6278 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 6279 u32 status;
6280
1da177e4
LT		 6281 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6282 if (status & DescOwn)
6283 break;
6284
a0750138
AD		 6285 /* This barrier is needed to keep us from reading
6286 * any other fields out of the Tx descriptor until
6287 * we know the status of DescOwn
6288 */
6289 dma_rmb();
6290
1e1205b7 6291 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
48addcc9 6292 tp->TxDescArray + entry);
1da177e4 6293 if (status & LastFrag) {
87cda7cb
DM		 6294 u64_stats_update_begin(&tp->tx_stats.syncp);
6295 tp->tx_stats.packets++;
6296 tp->tx_stats.bytes += tx_skb->skb->len;
6297 u64_stats_update_end(&tp->tx_stats.syncp);
7a4b813c 6298 dev_consume_skb_any(tx_skb->skb);
1da177e4
LT		 6299 tx_skb->skb = NULL;
6300 }
6301 dirty_tx++;
6302 tx_left--;
6303 }
6304
6305 if (tp->dirty_tx != dirty_tx) {
6306 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6307 /* Sync with rtl8169_start_xmit:
6308 * - publish dirty_tx ring index (write barrier)
6309 * - refresh cur_tx ring index and queue status (read barrier)
6310 * May the current thread miss the stopped queue condition,
6311 * a racing xmit thread can only have a right view of the
6312 * ring status.
6313 */
1e874e04 6314 smp_mb();
1da177e4 6315 if (netif_queue_stopped(dev) &&
477206a0 6316 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6317 netif_wake_queue(dev);
6318 }
d78ae2dc
FR		 6319 /*
6320 * 8168 hack: TxPoll requests are lost when the Tx packets are
6321 * too close. Let's kick an extra TxPoll request when a burst
6322 * of start_xmit activity is detected (if it is not detected,
6323 * it is slow enough). -- FR
6324 */
1ef7286e
AS		 6325 if (tp->cur_tx != dirty_tx)
6326 RTL_W8(tp, TxPoll, NPQ);
1da177e4
LT		 6327 }
6328}
6329
126fa4b9
FR		 6330static inline int rtl8169_fragmented_frame(u32 status)
6331{
6332 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6333}
6334
adea1ac7 6335static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6336{
1da177e4
LT		 6337 u32 status = opts1 & RxProtoMask;
6338
6339 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6340 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6341 skb->ip_summed = CHECKSUM_UNNECESSARY;
6342 else
bc8acf2c 6343 skb_checksum_none_assert(skb);
1da177e4
LT		 6344}
6345
6f0333b8
ED		 6346static struct sk_buff *rtl8169_try_rx_copy(void *data,
6347 struct rtl8169_private *tp,
6348 int pkt_size,
6349 dma_addr_t addr)
1da177e4 6350{
b449655f 6351 struct sk_buff *skb;
1e1205b7 6352 struct device *d = tp_to_dev(tp);
b449655f 6353
6f0333b8 6354 data = rtl8169_align(data);
48addcc9 6355 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8 6356 prefetch(data);
e2338f86 6357 skb = napi_alloc_skb(&tp->napi, pkt_size);
6f0333b8 6358 if (skb)
8a67aa86 6359 skb_copy_to_linear_data(skb, data, pkt_size);
48addcc9
SG		 6360 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6361
6f0333b8 6362 return skb;
1da177e4
LT		 6363}
6364
da78dbff 6365static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6366{
6367 unsigned int cur_rx, rx_left;
6f0333b8 6368 unsigned int count;
1da177e4 6369
1da177e4 6370 cur_rx = tp->cur_rx;
1da177e4 6371
9fba0812 6372 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6373 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6374 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6375 u32 status;
6376
6202806e 6377 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 6378 if (status & DescOwn)
6379 break;
a0750138
AD		 6380
6381 /* This barrier is needed to keep us from reading
6382 * any other fields out of the Rx descriptor until
6383 * we know the status of DescOwn
6384 */
6385 dma_rmb();
6386
4dcb7d33 6387 if (unlikely(status & RxRES)) {
bf82c189
JP		 6388 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6389 status);
cebf8cc7 6390 dev->stats.rx_errors++;
1da177e4 6391 if (status & (RxRWT | RxRUNT))
cebf8cc7 6392 dev->stats.rx_length_errors++;
1da177e4 6393 if (status & RxCRC)
cebf8cc7 6394 dev->stats.rx_crc_errors++;
6202806e
HK		 6395 /* RxFOVF is a reserved bit on later chip versions */
6396 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6397 status & RxFOVF) {
da78dbff 6398 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6399 dev->stats.rx_fifo_errors++;
6202806e
HK		 6400 } else if (status & (RxRUNT | RxCRC) &&
6401 !(status & RxRWT) &&
6402 dev->features & NETIF_F_RXALL) {
6bbe021d 6403 goto process_pkt;
6202806e 6404 }
1da177e4 6405 } else {
6f0333b8 6406 struct sk_buff *skb;
6bbe021d
BG		 6407 dma_addr_t addr;
6408 int pkt_size;
6409
6410process_pkt:
6411 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6412 if (likely(!(dev->features & NETIF_F_RXFCS)))
6413 pkt_size = (status & 0x00003fff) - 4;
6414 else
6415 pkt_size = status & 0x00003fff;
1da177e4 6416
126fa4b9
FR		 6417 /*
6418 * The driver does not support incoming fragmented
6419 * frames. They are seen as a symptom of over-mtu
6420 * sized frames.
6421 */
6422 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6423 dev->stats.rx_dropped++;
6424 dev->stats.rx_length_errors++;
ce11ff5e 6425 goto release_descriptor;
126fa4b9
FR		 6426 }
6427
6f0333b8
ED		 6428 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6429 tp, pkt_size, addr);
6f0333b8
ED		 6430 if (!skb) {
6431 dev->stats.rx_dropped++;
ce11ff5e 6432 goto release_descriptor;
1da177e4
LT		 6433 }
6434
adea1ac7 6435 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6436 skb_put(skb, pkt_size);
6437 skb->protocol = eth_type_trans(skb, dev);
6438
7a8fc77b
FR		 6439 rtl8169_rx_vlan_tag(desc, skb);
6440
39174291 6441 if (skb->pkt_type == PACKET_MULTICAST)
6442 dev->stats.multicast++;
6443
56de414c 6444 napi_gro_receive(&tp->napi, skb);
1da177e4 6445
8027aa24
JW		 6446 u64_stats_update_begin(&tp->rx_stats.syncp);
6447 tp->rx_stats.packets++;
6448 tp->rx_stats.bytes += pkt_size;
6449 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6450 }
ce11ff5e 6451release_descriptor:
6452 desc->opts2 = 0;
1d0254dd 6453 rtl8169_mark_to_asic(desc);
1da177e4
LT		 6454 }
6455
6456 count = cur_rx - tp->cur_rx;
6457 tp->cur_rx = cur_rx;
6458
1da177e4
LT		 6459 return count;
6460}
6461
07d3f51f 6462static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6463{
ebcd5daa 6464 struct rtl8169_private *tp = dev_instance;
05bbe558 6465 u16 status = rtl_get_events(tp);
1da177e4 6466
05bbe558
HK		 6467 if (status == 0xffff || !(status & (RTL_EVENT_NAPI | tp->event_slow)))
6468 return IRQ_NONE;
1da177e4 6469
05bbe558
HK		 6470 rtl_irq_disable(tp);
6471 napi_schedule_irqoff(&tp->napi);
6472
6473 return IRQ_HANDLED;
da78dbff 6474}
1da177e4 6475
da78dbff
FR		 6476/*
6477 * Workqueue context.
6478 */
6479static void rtl_slow_event_work(struct rtl8169_private *tp)
6480{
6481 struct net_device *dev = tp->dev;
6482 u16 status;
6483
6484 status = rtl_get_events(tp) & tp->event_slow;
6485 rtl_ack_events(tp, status);
1da177e4 6486
da78dbff
FR		 6487 if (unlikely(status & RxFIFOOver)) {
6488 switch (tp->mac_version) {
6489 /* Work around for rx fifo overflow */
6490 case RTL_GIGA_MAC_VER_11:
6491 netif_stop_queue(dev);
934714d0
FR		 6492 /* XXX - Hack alert. See rtl_task(). */
6493 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6494 default:
f11a377b
DD		 6495 break;
6496 }
da78dbff 6497 }
1da177e4 6498
da78dbff
FR		 6499 if (unlikely(status & SYSErr))
6500 rtl8169_pcierr_interrupt(dev);
0e485150 6501
da78dbff 6502 if (status & LinkChg)
f1e911d5 6503 phy_mac_interrupt(dev->phydev);
1da177e4 6504
7dbb4918 6505 rtl_irq_enable_all(tp);
1da177e4
LT		 6506}
6507
4422bcd4
FR		 6508static void rtl_task(struct work_struct *work)
6509{
da78dbff
FR		 6510 static const struct {
6511 int bitnr;
6512 void (*action)(struct rtl8169_private *);
6513 } rtl_work[] = {
934714d0 6514 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6515 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6516 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
da78dbff 6517 };
4422bcd4
FR		 6518 struct rtl8169_private *tp =
6519 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6520 struct net_device *dev = tp->dev;
6521 int i;
6522
6523 rtl_lock_work(tp);
6524
6c4a70c5
FR		 6525 if (!netif_running(dev) ||
6526 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6527 goto out_unlock;
6528
6529 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6530 bool pending;
6531
da78dbff 6532 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6533 if (pending)
6534 rtl_work[i].action(tp);
6535 }
4422bcd4 6536
da78dbff
FR		 6537out_unlock:
6538 rtl_unlock_work(tp);
4422bcd4
FR		 6539}
6540
bea3348e 6541static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6542{
bea3348e
SH		 6543 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6544 struct net_device *dev = tp->dev;
da78dbff
FR		 6545 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6546 int work_done= 0;
6547 u16 status;
6548
6549 status = rtl_get_events(tp);
6550 rtl_ack_events(tp, status & ~tp->event_slow);
6551
6552 if (status & RTL_EVENT_NAPI_RX)
6553 work_done = rtl_rx(dev, tp, (u32) budget);
6554
6555 if (status & RTL_EVENT_NAPI_TX)
6556 rtl_tx(dev, tp);
1da177e4 6557
da78dbff
FR		 6558 if (status & tp->event_slow) {
6559 enable_mask &= ~tp->event_slow;
6560
6561 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6562 }
1da177e4 6563
bea3348e 6564 if (work_done < budget) {
6ad20165 6565 napi_complete_done(napi, work_done);
f11a377b 6566
da78dbff
FR		 6567 rtl_irq_enable(tp, enable_mask);
6568 mmiowb();
1da177e4
LT		 6569 }
6570
bea3348e 6571 return work_done;
1da177e4 6572}
1da177e4 6573
1ef7286e 6574static void rtl8169_rx_missed(struct net_device *dev)
523a6094
FR		 6575{
6576 struct rtl8169_private *tp = netdev_priv(dev);
6577
6578 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6579 return;
6580
1ef7286e
AS		 6581 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6582 RTL_W32(tp, RxMissed, 0);
523a6094
FR		 6583}
6584
f1e911d5
HK		 6585static void r8169_phylink_handler(struct net_device *ndev)
6586{
6587 struct rtl8169_private *tp = netdev_priv(ndev);
6588
6589 if (netif_carrier_ok(ndev)) {
6590 rtl_link_chg_patch(tp);
6591 pm_request_resume(&tp->pci_dev->dev);
6592 } else {
6593 pm_runtime_idle(&tp->pci_dev->dev);
6594 }
6595
6596 if (net_ratelimit())
6597 phy_print_status(ndev->phydev);
6598}
6599
6600static int r8169_phy_connect(struct rtl8169_private *tp)
6601{
6602 struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6603 phy_interface_t phy_mode;
6604 int ret;
6605
f7ffa9ae 6606 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
f1e911d5
HK		 6607 PHY_INTERFACE_MODE_MII;
6608
6609 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6610 phy_mode);
6611 if (ret)
6612 return ret;
6613
f7ffa9ae 6614 if (!tp->supports_gmii)
f1e911d5
HK		 6615 phy_set_max_speed(phydev, SPEED_100);
6616
6617 /* Ensure to advertise everything, incl. pause */
6618 phydev->advertising = phydev->supported;
6619
6620 phy_attached_info(phydev);
6621
6622 return 0;
6623}
6624
1da177e4
LT		 6625static void rtl8169_down(struct net_device *dev)
6626{
6627 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6628
f1e911d5
HK		 6629 phy_stop(dev->phydev);
6630
93dd79e8 6631 napi_disable(&tp->napi);
da78dbff 6632 netif_stop_queue(dev);
1da177e4 6633
92fc43b4 6634 rtl8169_hw_reset(tp);
323bb685
SG		 6635 /*
6636 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6637 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6638 * and napi is disabled (rtl8169_poll).
323bb685 6639 */
1ef7286e 6640 rtl8169_rx_missed(dev);
1da177e4 6641
1da177e4 6642 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6643 synchronize_sched();
1da177e4 6644
1da177e4
LT		 6645 rtl8169_tx_clear(tp);
6646
6647 rtl8169_rx_clear(tp);
065c27c1 6648
6649 rtl_pll_power_down(tp);
1da177e4
LT		 6650}
6651
6652static int rtl8169_close(struct net_device *dev)
6653{
6654 struct rtl8169_private *tp = netdev_priv(dev);
6655 struct pci_dev *pdev = tp->pci_dev;
6656
e1759441
RW		 6657 pm_runtime_get_sync(&pdev->dev);
6658
cecb5fd7 6659 /* Update counters before going down */
e71c9ce2 6660 rtl8169_update_counters(tp);
355423d0 6661
da78dbff 6662 rtl_lock_work(tp);
6ad56901
KHF		 6663 /* Clear all task flags */
6664 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
da78dbff 6665
1da177e4 6666 rtl8169_down(dev);
da78dbff 6667 rtl_unlock_work(tp);
1da177e4 6668
4ea72445
L		 6669 cancel_work_sync(&tp->wk.work);
6670
f1e911d5
HK		 6671 phy_disconnect(dev->phydev);
6672
ebcd5daa 6673 pci_free_irq(pdev, 0, tp);
1da177e4 6674
82553bb6
SG		 6675 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6676 tp->RxPhyAddr);
6677 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6678 tp->TxPhyAddr);
1da177e4
LT		 6679 tp->TxDescArray = NULL;
6680 tp->RxDescArray = NULL;
6681
e1759441
RW		 6682 pm_runtime_put_sync(&pdev->dev);
6683
1da177e4
LT		 6684 return 0;
6685}
6686
dc1c00ce
FR		 6687#ifdef CONFIG_NET_POLL_CONTROLLER
6688static void rtl8169_netpoll(struct net_device *dev)
6689{
6690 struct rtl8169_private *tp = netdev_priv(dev);
6691
6d8b8349 6692 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
dc1c00ce
FR		 6693}
6694#endif
6695
df43ac78
FR		 6696static int rtl_open(struct net_device *dev)
6697{
6698 struct rtl8169_private *tp = netdev_priv(dev);
df43ac78
FR		 6699 struct pci_dev *pdev = tp->pci_dev;
6700 int retval = -ENOMEM;
6701
6702 pm_runtime_get_sync(&pdev->dev);
6703
6704 /*
e75d6606 6705 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6706 * dma_alloc_coherent provides more.
6707 */
6708 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6709 &tp->TxPhyAddr, GFP_KERNEL);
6710 if (!tp->TxDescArray)
6711 goto err_pm_runtime_put;
6712
6713 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6714 &tp->RxPhyAddr, GFP_KERNEL);
6715 if (!tp->RxDescArray)
6716 goto err_free_tx_0;
6717
b1127e64 6718 retval = rtl8169_init_ring(tp);
df43ac78
FR		 6719 if (retval < 0)
6720 goto err_free_rx_1;
6721
6722 INIT_WORK(&tp->wk.work, rtl_task);
6723
6724 smp_mb();
6725
6726 rtl_request_firmware(tp);
6727
ebcd5daa 6728 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6c6aa15f 6729 dev->name);
df43ac78
FR		 6730 if (retval < 0)
6731 goto err_release_fw_2;
6732
f1e911d5
HK		 6733 retval = r8169_phy_connect(tp);
6734 if (retval)
6735 goto err_free_irq;
6736
df43ac78
FR		 6737 rtl_lock_work(tp);
6738
6739 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6740
6741 napi_enable(&tp->napi);
6742
6743 rtl8169_init_phy(dev, tp);
6744
df43ac78
FR		 6745 rtl_pll_power_up(tp);
6746
61cb532d 6747 rtl_hw_start(tp);
df43ac78 6748
e71c9ce2 6749 if (!rtl8169_init_counter_offsets(tp))
6e85d5ad
CV		 6750 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6751
f1e911d5 6752 phy_start(dev->phydev);
df43ac78
FR		 6753 netif_start_queue(dev);
6754
6755 rtl_unlock_work(tp);
6756
a92a0849 6757 pm_runtime_put_sync(&pdev->dev);
df43ac78
FR		 6758out:
6759 return retval;
6760
f1e911d5
HK		 6761err_free_irq:
6762 pci_free_irq(pdev, 0, tp);
df43ac78
FR		 6763err_release_fw_2:
6764 rtl_release_firmware(tp);
6765 rtl8169_rx_clear(tp);
6766err_free_rx_1:
6767 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6768 tp->RxPhyAddr);
6769 tp->RxDescArray = NULL;
6770err_free_tx_0:
6771 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6772 tp->TxPhyAddr);
6773 tp->TxDescArray = NULL;
6774err_pm_runtime_put:
6775 pm_runtime_put_noidle(&pdev->dev);
6776 goto out;
6777}
6778
bc1f4470 6779static void
8027aa24 6780rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6781{
6782 struct rtl8169_private *tp = netdev_priv(dev);
f09cf4b7 6783 struct pci_dev *pdev = tp->pci_dev;
42020320 6784 struct rtl8169_counters *counters = tp->counters;
8027aa24 6785 unsigned int start;
1da177e4 6786
f09cf4b7
CHL		 6787 pm_runtime_get_noresume(&pdev->dev);
6788
6789 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
1ef7286e 6790 rtl8169_rx_missed(dev);
5b0384f4 6791
8027aa24 6792 do {
57a7744e 6793 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 6794 stats->rx_packets = tp->rx_stats.packets;
6795 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 6796 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 6797
8027aa24 6798 do {
57a7744e 6799 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 6800 stats->tx_packets = tp->tx_stats.packets;
6801 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 6802 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 6803
6804 stats->rx_dropped = dev->stats.rx_dropped;
6805 stats->tx_dropped = dev->stats.tx_dropped;
6806 stats->rx_length_errors = dev->stats.rx_length_errors;
6807 stats->rx_errors = dev->stats.rx_errors;
6808 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6809 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6810 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 6811 stats->multicast = dev->stats.multicast;
8027aa24 6812
6e85d5ad
CV		 6813 /*
6814 * Fetch additonal counter values missing in stats collected by driver
6815 * from tally counters.
6816 */
f09cf4b7 6817 if (pm_runtime_active(&pdev->dev))
e71c9ce2 6818 rtl8169_update_counters(tp);
6e85d5ad
CV		 6819
6820 /*
6821 * Subtract values fetched during initalization.
6822 * See rtl8169_init_counter_offsets for a description why we do that.
6823 */
42020320 6824 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 6825 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 6826 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 6827 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 6828 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 6829 le16_to_cpu(tp->tc_offset.tx_aborted);
6830
f09cf4b7 6831 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 6832}
6833
861ab440 6834static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6835{
065c27c1 6836 struct rtl8169_private *tp = netdev_priv(dev);
6837
5d06a99f 6838 if (!netif_running(dev))
861ab440 6839 return;
5d06a99f 6840
f1e911d5 6841 phy_stop(dev->phydev);
5d06a99f
FR		 6842 netif_device_detach(dev);
6843 netif_stop_queue(dev);
da78dbff
FR		 6844
6845 rtl_lock_work(tp);
6846 napi_disable(&tp->napi);
6ad56901
KHF		 6847 /* Clear all task flags */
6848 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6849
da78dbff
FR		 6850 rtl_unlock_work(tp);
6851
6852 rtl_pll_power_down(tp);
861ab440
RW		 6853}
6854
6855#ifdef CONFIG_PM
6856
6857static int rtl8169_suspend(struct device *device)
6858{
6859 struct pci_dev *pdev = to_pci_dev(device);
6860 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6861
861ab440 6862 rtl8169_net_suspend(dev);
1371fa6d 6863
5d06a99f
FR		 6864 return 0;
6865}
6866
e1759441
RW		 6867static void __rtl8169_resume(struct net_device *dev)
6868{
065c27c1 6869 struct rtl8169_private *tp = netdev_priv(dev);
6870
e1759441 6871 netif_device_attach(dev);
065c27c1 6872
6873 rtl_pll_power_up(tp);
92bad850 6874 rtl8169_init_phy(dev, tp);
065c27c1 6875
f1e911d5
HK		 6876 phy_start(tp->dev->phydev);
6877
cff4c162
AS		 6878 rtl_lock_work(tp);
6879 napi_enable(&tp->napi);
6c4a70c5 6880 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6881 rtl_unlock_work(tp);
da78dbff 6882
98ddf986 6883 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6884}
6885
861ab440 6886static int rtl8169_resume(struct device *device)
5d06a99f 6887{
861ab440 6888 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f
FR		 6889 struct net_device *dev = pci_get_drvdata(pdev);
6890
e1759441
RW		 6891 if (netif_running(dev))
6892 __rtl8169_resume(dev);
5d06a99f 6893
e1759441
RW		 6894 return 0;
6895}
6896
6897static int rtl8169_runtime_suspend(struct device *device)
6898{
6899 struct pci_dev *pdev = to_pci_dev(device);
6900 struct net_device *dev = pci_get_drvdata(pdev);
6901 struct rtl8169_private *tp = netdev_priv(dev);
6902
07df5bd8 6903 if (!tp->TxDescArray)
e1759441
RW		 6904 return 0;
6905
da78dbff 6906 rtl_lock_work(tp);
e1759441 6907 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6908 rtl_unlock_work(tp);
e1759441
RW		 6909
6910 rtl8169_net_suspend(dev);
6911
f09cf4b7 6912 /* Update counters before going runtime suspend */
1ef7286e 6913 rtl8169_rx_missed(dev);
e71c9ce2 6914 rtl8169_update_counters(tp);
f09cf4b7 6915
e1759441
RW		 6916 return 0;
6917}
6918
6919static int rtl8169_runtime_resume(struct device *device)
6920{
6921 struct pci_dev *pdev = to_pci_dev(device);
6922 struct net_device *dev = pci_get_drvdata(pdev);
6923 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 6924 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 6925
6926 if (!tp->TxDescArray)
6927 return 0;
6928
da78dbff 6929 rtl_lock_work(tp);
e1759441 6930 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff 6931 rtl_unlock_work(tp);
e1759441
RW		 6932
6933 __rtl8169_resume(dev);
5d06a99f 6934
5d06a99f
FR		 6935 return 0;
6936}
6937
e1759441
RW		 6938static int rtl8169_runtime_idle(struct device *device)
6939{
6940 struct pci_dev *pdev = to_pci_dev(device);
6941 struct net_device *dev = pci_get_drvdata(pdev);
e1759441 6942
a92a0849
HK		 6943 if (!netif_running(dev) || !netif_carrier_ok(dev))
6944 pm_schedule_suspend(device, 10000);
6945
6946 return -EBUSY;
e1759441
RW		 6947}
6948
47145210 6949static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6950 .suspend = rtl8169_suspend,
6951 .resume = rtl8169_resume,
6952 .freeze = rtl8169_suspend,
6953 .thaw = rtl8169_resume,
6954 .poweroff = rtl8169_suspend,
6955 .restore = rtl8169_resume,
6956 .runtime_suspend = rtl8169_runtime_suspend,
6957 .runtime_resume = rtl8169_runtime_resume,
6958 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6959};
6960
6961#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6962
6963#else /* !CONFIG_PM */
6964
6965#define RTL8169_PM_OPS NULL
6966
6967#endif /* !CONFIG_PM */
6968
649b3b8c 6969static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6970{
649b3b8c 6971 /* WoL fails with 8168b when the receiver is disabled. */
6972 switch (tp->mac_version) {
6973 case RTL_GIGA_MAC_VER_11:
6974 case RTL_GIGA_MAC_VER_12:
6975 case RTL_GIGA_MAC_VER_17:
6976 pci_clear_master(tp->pci_dev);
6977
1ef7286e 6978 RTL_W8(tp, ChipCmd, CmdRxEnb);
649b3b8c 6979 /* PCI commit */
1ef7286e 6980 RTL_R8(tp, ChipCmd);
649b3b8c 6981 break;
6982 default:
6983 break;
6984 }
6985}
6986
1765f95d
FR		 6987static void rtl_shutdown(struct pci_dev *pdev)
6988{
861ab440 6989 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6990 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 6991
6992 rtl8169_net_suspend(dev);
1765f95d 6993
cecb5fd7 6994 /* Restore original MAC address */
cc098dc7
IV		 6995 rtl_rar_set(tp, dev->perm_addr);
6996
92fc43b4 6997 rtl8169_hw_reset(tp);
4bb3f522 6998
861ab440 6999 if (system_state == SYSTEM_POWER_OFF) {
433f9d0d 7000 if (tp->saved_wolopts) {
649b3b8c 7001 rtl_wol_suspend_quirk(tp);
7002 rtl_wol_shutdown_quirk(tp);
ca52efd5 7003 }
7004
861ab440
RW		 7005 pci_wake_from_d3(pdev, true);
7006 pci_set_power_state(pdev, PCI_D3hot);
7007 }
7008}
5d06a99f 7009
baf63293 7010static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 7011{
7012 struct net_device *dev = pci_get_drvdata(pdev);
7013 struct rtl8169_private *tp = netdev_priv(dev);
7014
9dbe7896 7015 if (r8168_check_dash(tp))
e27566ed 7016 rtl8168_driver_stop(tp);
e27566ed 7017
ad1be8d3
DN		 7018 netif_napi_del(&tp->napi);
7019
e27566ed 7020 unregister_netdev(dev);
f1e911d5 7021 mdiobus_unregister(tp->mii_bus);
e27566ed
FR		 7022
7023 rtl_release_firmware(tp);
7024
7025 if (pci_dev_run_wake(pdev))
7026 pm_runtime_get_noresume(&pdev->dev);
7027
7028 /* restore original MAC address */
7029 rtl_rar_set(tp, dev->perm_addr);
e27566ed
FR		 7030}
7031
fa9c385e 7032static const struct net_device_ops rtl_netdev_ops = {
df43ac78 7033 .ndo_open = rtl_open,
fa9c385e
FR		 7034 .ndo_stop = rtl8169_close,
7035 .ndo_get_stats64 = rtl8169_get_stats64,
7036 .ndo_start_xmit = rtl8169_start_xmit,
7037 .ndo_tx_timeout = rtl8169_tx_timeout,
7038 .ndo_validate_addr = eth_validate_addr,
7039 .ndo_change_mtu = rtl8169_change_mtu,
7040 .ndo_fix_features = rtl8169_fix_features,
7041 .ndo_set_features = rtl8169_set_features,
7042 .ndo_set_mac_address = rtl_set_mac_address,
7043 .ndo_do_ioctl = rtl8169_ioctl,
7044 .ndo_set_rx_mode = rtl_set_rx_mode,
7045#ifdef CONFIG_NET_POLL_CONTROLLER
7046 .ndo_poll_controller = rtl8169_netpoll,
7047#endif
7048
7049};
7050
31fa8b18 7051static const struct rtl_cfg_info {
61cb532d 7052 void (*hw_start)(struct rtl8169_private *tp);
31fa8b18 7053 u16 event_slow;
14967f94 7054 unsigned int has_gmii:1;
50970831 7055 const struct rtl_coalesce_info *coalesce_info;
31fa8b18
FR		 7056 u8 default_ver;
7057} rtl_cfg_infos [] = {
7058 [RTL_CFG_0] = {
7059 .hw_start = rtl_hw_start_8169,
31fa8b18 7060 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
14967f94 7061 .has_gmii = 1,
50970831 7062 .coalesce_info = rtl_coalesce_info_8169,
31fa8b18
FR		 7063 .default_ver = RTL_GIGA_MAC_VER_01,
7064 },
7065 [RTL_CFG_1] = {
7066 .hw_start = rtl_hw_start_8168,
31fa8b18 7067 .event_slow = SYSErr | LinkChg | RxOverflow,
14967f94 7068 .has_gmii = 1,
50970831 7069 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 7070 .default_ver = RTL_GIGA_MAC_VER_11,
7071 },
7072 [RTL_CFG_2] = {
7073 .hw_start = rtl_hw_start_8101,
31fa8b18
FR		 7074 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7075 PCSTimeout,
50970831 7076 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 7077 .default_ver = RTL_GIGA_MAC_VER_13,
7078 }
7079};
7080
6c6aa15f 7081static int rtl_alloc_irq(struct rtl8169_private *tp)
31fa8b18 7082{
6c6aa15f 7083 unsigned int flags;
31fa8b18 7084
7bb05b85
JHP		 7085 switch (tp->mac_version) {
7086 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
1ef7286e
AS		 7087 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7088 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7089 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6c6aa15f 7090 flags = PCI_IRQ_LEGACY;
7bb05b85
JHP		 7091 break;
7092 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_40:
7c53a722
HK		 7093 /* This version was reported to have issues with resume
7094 * from suspend when using MSI-X
7095 */
7096 flags = PCI_IRQ_LEGACY | PCI_IRQ_MSI;
7bb05b85
JHP		 7097 break;
7098 default:
6c6aa15f 7099 flags = PCI_IRQ_ALL_TYPES;
31fa8b18 7100 }
6c6aa15f
HK		 7101
7102 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
31fa8b18
FR		 7103}
7104
c558386b
HW		 7105DECLARE_RTL_COND(rtl_link_list_ready_cond)
7106{
1ef7286e 7107 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
c558386b
HW		 7108}
7109
7110DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7111{
1ef7286e 7112 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
c558386b
HW		 7113}
7114
f1e911d5
HK		 7115static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7116{
7117 struct rtl8169_private *tp = mii_bus->priv;
7118
7119 if (phyaddr > 0)
7120 return -ENODEV;
7121
7122 return rtl_readphy(tp, phyreg);
7123}
7124
7125static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7126 int phyreg, u16 val)
7127{
7128 struct rtl8169_private *tp = mii_bus->priv;
7129
7130 if (phyaddr > 0)
7131 return -ENODEV;
7132
7133 rtl_writephy(tp, phyreg, val);
7134
7135 return 0;
7136}
7137
7138static int r8169_mdio_register(struct rtl8169_private *tp)
7139{
7140 struct pci_dev *pdev = tp->pci_dev;
7141 struct phy_device *phydev;
7142 struct mii_bus *new_bus;
7143 int ret;
7144
7145 new_bus = devm_mdiobus_alloc(&pdev->dev);
7146 if (!new_bus)
7147 return -ENOMEM;
7148
7149 new_bus->name = "r8169";
7150 new_bus->priv = tp;
7151 new_bus->parent = &pdev->dev;
7152 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7153 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7154 PCI_DEVID(pdev->bus->number, pdev->devfn));
7155
7156 new_bus->read = r8169_mdio_read_reg;
7157 new_bus->write = r8169_mdio_write_reg;
7158
7159 ret = mdiobus_register(new_bus);
7160 if (ret)
7161 return ret;
7162
7163 phydev = mdiobus_get_phy(new_bus, 0);
7164 if (!phydev) {
7165 mdiobus_unregister(new_bus);
7166 return -ENODEV;
7167 }
7168
242cd9b5
HK		 7169 /* PHY will be woken up in rtl_open() */
7170 phy_suspend(phydev);
7171
f1e911d5
HK		 7172 tp->mii_bus = new_bus;
7173
7174 return 0;
7175}
7176
baf63293 7177static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b 7178{
c558386b
HW		 7179 u32 data;
7180
7181 tp->ocp_base = OCP_STD_PHY_BASE;
7182
1ef7286e 7183 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
c558386b
HW		 7184
7185 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7186 return;
7187
7188 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7189 return;
7190
1ef7286e 7191 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
c558386b 7192 msleep(1);
1ef7286e 7193 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
c558386b 7194
5f8bcce9 7195 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7196 data &= ~(1 << 14);
7197 r8168_mac_ocp_write(tp, 0xe8de, data);
7198
7199 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7200 return;
7201
5f8bcce9 7202 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7203 data |= (1 << 15);
7204 r8168_mac_ocp_write(tp, 0xe8de, data);
7205
7206 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7207 return;
7208}
7209
003609da
CHL		 7210static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7211{
7212 rtl8168ep_stop_cmac(tp);
7213 rtl_hw_init_8168g(tp);
7214}
7215
baf63293 7216static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 7217{
7218 switch (tp->mac_version) {
2a71883c 7219 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
003609da
CHL		 7220 rtl_hw_init_8168g(tp);
7221 break;
2a71883c 7222 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
003609da 7223 rtl_hw_init_8168ep(tp);
c558386b 7224 break;
c558386b
HW		 7225 default:
7226 break;
7227 }
7228}
7229
eb88f5f7
HK		 7230/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7231static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7232{
7233 switch (tp->mac_version) {
7234 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7235 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7236 return false;
7237 default:
7238 return true;
7239 }
7240}
7241
abe8b2f7
HK		 7242static int rtl_jumbo_max(struct rtl8169_private *tp)
7243{
7244 /* Non-GBit versions don't support jumbo frames */
7245 if (!tp->supports_gmii)
7246 return JUMBO_1K;
7247
7248 switch (tp->mac_version) {
7249 /* RTL8169 */
7250 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7251 return JUMBO_7K;
7252 /* RTL8168b */
7253 case RTL_GIGA_MAC_VER_11:
7254 case RTL_GIGA_MAC_VER_12:
7255 case RTL_GIGA_MAC_VER_17:
7256 return JUMBO_4K;
7257 /* RTL8168c */
7258 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7259 return JUMBO_6K;
7260 default:
7261 return JUMBO_9K;
7262 }
7263}
7264
929a031d 7265static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 7266{
7267 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3b6cf25d 7268 struct rtl8169_private *tp;
3b6cf25d 7269 struct net_device *dev;
c8d48d9c 7270 int chipset, region, i;
abe8b2f7 7271 int jumbo_max, rc;
3b6cf25d 7272
4c45d24a
HK		 7273 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7274 if (!dev)
7275 return -ENOMEM;
3b6cf25d
FR		 7276
7277 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 7278 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 7279 tp = netdev_priv(dev);
7280 tp->dev = dev;
7281 tp->pci_dev = pdev;
7282 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
f7ffa9ae 7283 tp->supports_gmii = cfg->has_gmii;
3b6cf25d 7284
3b6cf25d 7285 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4c45d24a 7286 rc = pcim_enable_device(pdev);
3b6cf25d 7287 if (rc < 0) {
22148df0 7288 dev_err(&pdev->dev, "enable failure\n");
4c45d24a 7289 return rc;
3b6cf25d
FR		 7290 }
7291
4c45d24a 7292 if (pcim_set_mwi(pdev) < 0)
22148df0 7293 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
3b6cf25d 7294
c8d48d9c
HK		 7295 /* use first MMIO region */
7296 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7297 if (region < 0) {
22148df0 7298 dev_err(&pdev->dev, "no MMIO resource found\n");
4c45d24a 7299 return -ENODEV;
3b6cf25d
FR		 7300 }
7301
7302 /* check for weird/broken PCI region reporting */
7303 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
22148df0 7304 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
4c45d24a 7305 return -ENODEV;
3b6cf25d
FR		 7306 }
7307
93a00d4d 7308 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
3b6cf25d 7309 if (rc < 0) {
22148df0 7310 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
4c45d24a 7311 return rc;
3b6cf25d
FR		 7312 }
7313
93a00d4d 7314 tp->mmio_addr = pcim_iomap_table(pdev)[region];
3b6cf25d
FR		 7315
7316 if (!pci_is_pcie(pdev))
22148df0 7317 dev_info(&pdev->dev, "not PCI Express\n");
3b6cf25d
FR		 7318
7319 /* Identify chip attached to board */
22148df0 7320 rtl8169_get_mac_version(tp, cfg->default_ver);
3b6cf25d 7321
e397286b
HK		 7322 if (rtl_tbi_enabled(tp)) {
7323 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7324 return -ENODEV;
7325 }
7326
0ae0974e 7327 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
27896c83
AB		 7328
7329 if ((sizeof(dma_addr_t) > 4) &&
7330 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7331 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
f0076436
AB		 7332 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7333 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
27896c83
AB		 7334
7335 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7336 if (!pci_is_pcie(pdev))
7337 tp->cp_cmd |= PCIDAC;
7338 dev->features |= NETIF_F_HIGHDMA;
7339 } else {
7340 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7341 if (rc < 0) {
22148df0 7342 dev_err(&pdev->dev, "DMA configuration failed\n");
4c45d24a 7343 return rc;
27896c83
AB		 7344 }
7345 }
7346
3b6cf25d
FR		 7347 rtl_init_rxcfg(tp);
7348
7349 rtl_irq_disable(tp);
7350
c558386b
HW		 7351 rtl_hw_initialize(tp);
7352
3b6cf25d
FR		 7353 rtl_hw_reset(tp);
7354
7355 rtl_ack_events(tp, 0xffff);
7356
7357 pci_set_master(pdev);
7358
3b6cf25d 7359 rtl_init_mdio_ops(tp);
3b6cf25d
FR		 7360 rtl_init_jumbo_ops(tp);
7361
7362 rtl8169_print_mac_version(tp);
7363
7364 chipset = tp->mac_version;
3b6cf25d 7365
6c6aa15f
HK		 7366 rc = rtl_alloc_irq(tp);
7367 if (rc < 0) {
22148df0 7368 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6c6aa15f
HK		 7369 return rc;
7370 }
3b6cf25d 7371
18041b52 7372 tp->saved_wolopts = __rtl8169_get_wol(tp);
7edf6d31 7373
3b6cf25d 7374 mutex_init(&tp->wk.mutex);
340fea3d
KM		 7375 u64_stats_init(&tp->rx_stats.syncp);
7376 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 7377
7378 /* Get MAC address */
b2d43e6e 7379 switch (tp->mac_version) {
353af85e 7380 u8 mac_addr[ETH_ALEN] __aligned(4);
b2d43e6e
HK		 7381 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7382 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
05b9687b 7383 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
353af85e 7384 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89 7385
353af85e
HK		 7386 if (is_valid_ether_addr(mac_addr))
7387 rtl_rar_set(tp, mac_addr);
b2d43e6e
HK		 7388 break;
7389 default:
7390 break;
6e1d0b89 7391 }
3b6cf25d 7392 for (i = 0; i < ETH_ALEN; i++)
1ef7286e 7393 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
3b6cf25d 7394
7ad24ea4 7395 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 7396 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d 7397
37621493 7398 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
3b6cf25d
FR		 7399
7400 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7401 * properly for all devices */
7402 dev->features |= NETIF_F_RXCSUM |
f646968f 7403 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7404
7405 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 7406 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7407 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7408 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7409 NETIF_F_HIGHDMA;
2d0ec544 7410 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3b6cf25d 7411
929a031d 7412 tp->cp_cmd |= RxChkSum | RxVlan;
7413
7414 /*
7415 * Pretend we are using VLANs; This bypasses a nasty bug where
7416 * Interrupts stop flowing on high load on 8110SCd controllers.
7417 */
3b6cf25d 7418 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 7419 /* Disallow toggling */
f646968f 7420 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 7421
eb88f5f7 7422 if (rtl_chip_supports_csum_v2(tp)) {
5888d3fc 7423 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 7424 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
eb88f5f7
HK		 7425 } else {
7426 tp->tso_csum = rtl8169_tso_csum_v1;
a4328ddb 7427 }
5888d3fc 7428
3b6cf25d
FR		 7429 dev->hw_features |= NETIF_F_RXALL;
7430 dev->hw_features |= NETIF_F_RXFCS;
7431
c7315a95
JW		 7432 /* MTU range: 60 - hw-specific max */
7433 dev->min_mtu = ETH_ZLEN;
abe8b2f7
HK		 7434 jumbo_max = rtl_jumbo_max(tp);
7435 dev->max_mtu = jumbo_max;
c7315a95 7436
3b6cf25d
FR		 7437 tp->hw_start = cfg->hw_start;
7438 tp->event_slow = cfg->event_slow;
50970831 7439 tp->coalesce_info = cfg->coalesce_info;
3b6cf25d 7440
3b6cf25d
FR		 7441 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7442
4c45d24a
HK		 7443 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7444 &tp->counters_phys_addr,
7445 GFP_KERNEL);
4cf964af
HK		 7446 if (!tp->counters)
7447 return -ENOMEM;
42020320 7448
19c9ea36
HK		 7449 pci_set_drvdata(pdev, dev);
7450
f1e911d5
HK		 7451 rc = r8169_mdio_register(tp);
7452 if (rc)
4cf964af 7453 return rc;
3b6cf25d 7454
07df5bd8
HK		 7455 /* chip gets powered up in rtl_open() */
7456 rtl_pll_power_down(tp);
7457
f1e911d5
HK		 7458 rc = register_netdev(dev);
7459 if (rc)
7460 goto err_mdio_unregister;
7461
2d6c5a61
HK		 7462 netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7463 rtl_chip_infos[chipset].name, dev->dev_addr,
90b989c5 7464 (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
29274991 7465 pci_irq_vector(pdev, 0));
abe8b2f7
HK		 7466
7467 if (jumbo_max > JUMBO_1K)
7468 netif_info(tp, probe, dev,
7469 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7470 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7471 "ok" : "ko");
3b6cf25d 7472
9dbe7896 7473 if (r8168_check_dash(tp))
3b6cf25d 7474 rtl8168_driver_start(tp);
3b6cf25d 7475
a92a0849
HK		 7476 if (pci_dev_run_wake(pdev))
7477 pm_runtime_put_sync(&pdev->dev);
7478
4c45d24a 7479 return 0;
f1e911d5
HK		 7480
7481err_mdio_unregister:
7482 mdiobus_unregister(tp->mii_bus);
7483 return rc;
3b6cf25d
FR		 7484}
7485
1da177e4
LT		 7486static struct pci_driver rtl8169_pci_driver = {
7487 .name = MODULENAME,
7488 .id_table = rtl8169_pci_tbl,
3b6cf25d 7489 .probe = rtl_init_one,
baf63293 7490 .remove = rtl_remove_one,
1765f95d 7491 .shutdown = rtl_shutdown,
861ab440 7492 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7493};
7494
3eeb7da9 7495module_pci_driver(rtl8169_pci_driver);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git