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Merge branch 'smc-pnetid-and-SMC-D-support'
[thirdparty/kernel/stable.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
a6b7a407 24#include <linux/interrupt.h>
1da177e4 25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
70c71606 28#include <linux/prefetch.h>
e974604b 29#include <linux/ipv6.h>
30#include <net/ip6_checksum.h>
1da177e4
LT		 31
32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 36#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 43#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 44#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 46#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 47#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 48#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 49#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 50#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 51#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 52#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 53#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 54#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
55#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
56#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
57#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 58
1da177e4
LT		 59#ifdef RTL8169_DEBUG
60#define assert(expr) \
5b0384f4
FR		 61 if (!(expr)) { \
62 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 63 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 64 }
06fa7358
JP		 65#define dprintk(fmt, args...) \
66 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 67#else
68#define assert(expr) do {} while (0)
69#define dprintk(fmt, args...) do {} while (0)
70#endif /* RTL8169_DEBUG */
71
b57b7e5a 72#define R8169_MSG_DEFAULT \
f0e837d9 73 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 74
477206a0
JD		 75#define TX_SLOTS_AVAIL(tp) \
76 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
77
78/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
79#define TX_FRAGS_READY_FOR(tp,nr_frags) \
80 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 81
1da177e4
LT		 82/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
83 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 84static const int multicast_filter_limit = 32;
1da177e4 85
aee77e4a 86#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 87#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
88
89#define R8169_REGS_SIZE 256
1d0254dd 90#define R8169_RX_BUF_SIZE (SZ_16K - 1)
1da177e4 91#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 92#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 93#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
94#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
95
96#define RTL8169_TX_TIMEOUT (6*HZ)
97#define RTL8169_PHY_TIMEOUT (10*HZ)
98
99/* write/read MMIO register */
1ef7286e
AS		 100#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
101#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
102#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
103#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
104#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
105#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
1da177e4
LT		 106
107enum mac_version {
85bffe6c
FR		 108 RTL_GIGA_MAC_VER_01 = 0,
109 RTL_GIGA_MAC_VER_02,
110 RTL_GIGA_MAC_VER_03,
111 RTL_GIGA_MAC_VER_04,
112 RTL_GIGA_MAC_VER_05,
113 RTL_GIGA_MAC_VER_06,
114 RTL_GIGA_MAC_VER_07,
115 RTL_GIGA_MAC_VER_08,
116 RTL_GIGA_MAC_VER_09,
117 RTL_GIGA_MAC_VER_10,
118 RTL_GIGA_MAC_VER_11,
119 RTL_GIGA_MAC_VER_12,
120 RTL_GIGA_MAC_VER_13,
121 RTL_GIGA_MAC_VER_14,
122 RTL_GIGA_MAC_VER_15,
123 RTL_GIGA_MAC_VER_16,
124 RTL_GIGA_MAC_VER_17,
125 RTL_GIGA_MAC_VER_18,
126 RTL_GIGA_MAC_VER_19,
127 RTL_GIGA_MAC_VER_20,
128 RTL_GIGA_MAC_VER_21,
129 RTL_GIGA_MAC_VER_22,
130 RTL_GIGA_MAC_VER_23,
131 RTL_GIGA_MAC_VER_24,
132 RTL_GIGA_MAC_VER_25,
133 RTL_GIGA_MAC_VER_26,
134 RTL_GIGA_MAC_VER_27,
135 RTL_GIGA_MAC_VER_28,
136 RTL_GIGA_MAC_VER_29,
137 RTL_GIGA_MAC_VER_30,
138 RTL_GIGA_MAC_VER_31,
139 RTL_GIGA_MAC_VER_32,
140 RTL_GIGA_MAC_VER_33,
70090424 141 RTL_GIGA_MAC_VER_34,
c2218925
HW		 142 RTL_GIGA_MAC_VER_35,
143 RTL_GIGA_MAC_VER_36,
7e18dca1 144 RTL_GIGA_MAC_VER_37,
b3d7b2f2 145 RTL_GIGA_MAC_VER_38,
5598bfe5 146 RTL_GIGA_MAC_VER_39,
c558386b
HW		 147 RTL_GIGA_MAC_VER_40,
148 RTL_GIGA_MAC_VER_41,
57538c4a 149 RTL_GIGA_MAC_VER_42,
58152cd4 150 RTL_GIGA_MAC_VER_43,
45dd95c4 151 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 152 RTL_GIGA_MAC_VER_45,
153 RTL_GIGA_MAC_VER_46,
154 RTL_GIGA_MAC_VER_47,
155 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 156 RTL_GIGA_MAC_VER_49,
157 RTL_GIGA_MAC_VER_50,
158 RTL_GIGA_MAC_VER_51,
85bffe6c 159 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 160};
161
2b7b4318
FR		 162enum rtl_tx_desc_version {
163 RTL_TD_0 = 0,
164 RTL_TD_1 = 1,
165};
166
d58d46b5
FR		 167#define JUMBO_1K ETH_DATA_LEN
168#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
169#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
170#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
171#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
172
6ed0e08f 173#define _R(NAME,TD,FW,SZ) { \
d58d46b5
FR		 174 .name = NAME, \
175 .txd_version = TD, \
176 .fw_name = FW, \
177 .jumbo_max = SZ, \
d58d46b5 178}
1da177e4 179
3c6bee1d 180static const struct {
1da177e4 181 const char *name;
2b7b4318 182 enum rtl_tx_desc_version txd_version;
953a12cc 183 const char *fw_name;
d58d46b5 184 u16 jumbo_max;
85bffe6c
FR		 185} rtl_chip_infos[] = {
186 /* PCI devices. */
187 [RTL_GIGA_MAC_VER_01] =
6ed0e08f 188 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 189 [RTL_GIGA_MAC_VER_02] =
6ed0e08f 190 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 191 [RTL_GIGA_MAC_VER_03] =
6ed0e08f 192 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 193 [RTL_GIGA_MAC_VER_04] =
6ed0e08f 194 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 195 [RTL_GIGA_MAC_VER_05] =
6ed0e08f 196 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c 197 [RTL_GIGA_MAC_VER_06] =
6ed0e08f 198 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K),
85bffe6c
FR		 199 /* PCI-E devices. */
200 [RTL_GIGA_MAC_VER_07] =
6ed0e08f 201 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
85bffe6c 202 [RTL_GIGA_MAC_VER_08] =
6ed0e08f 203 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
85bffe6c 204 [RTL_GIGA_MAC_VER_09] =
6ed0e08f 205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K),
85bffe6c 206 [RTL_GIGA_MAC_VER_10] =
6ed0e08f 207 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 208 [RTL_GIGA_MAC_VER_11] =
6ed0e08f 209 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
85bffe6c 210 [RTL_GIGA_MAC_VER_12] =
6ed0e08f 211 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
85bffe6c 212 [RTL_GIGA_MAC_VER_13] =
6ed0e08f 213 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 214 [RTL_GIGA_MAC_VER_14] =
6ed0e08f 215 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 216 [RTL_GIGA_MAC_VER_15] =
6ed0e08f 217 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 218 [RTL_GIGA_MAC_VER_16] =
6ed0e08f 219 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K),
85bffe6c 220 [RTL_GIGA_MAC_VER_17] =
6ed0e08f 221 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K),
85bffe6c 222 [RTL_GIGA_MAC_VER_18] =
6ed0e08f 223 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 224 [RTL_GIGA_MAC_VER_19] =
6ed0e08f 225 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 226 [RTL_GIGA_MAC_VER_20] =
6ed0e08f 227 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 228 [RTL_GIGA_MAC_VER_21] =
6ed0e08f 229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 230 [RTL_GIGA_MAC_VER_22] =
6ed0e08f 231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 232 [RTL_GIGA_MAC_VER_23] =
6ed0e08f 233 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 234 [RTL_GIGA_MAC_VER_24] =
6ed0e08f 235 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K),
85bffe6c 236 [RTL_GIGA_MAC_VER_25] =
6ed0e08f 237 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, JUMBO_9K),
85bffe6c 238 [RTL_GIGA_MAC_VER_26] =
6ed0e08f 239 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, JUMBO_9K),
85bffe6c 240 [RTL_GIGA_MAC_VER_27] =
6ed0e08f 241 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
85bffe6c 242 [RTL_GIGA_MAC_VER_28] =
6ed0e08f 243 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
85bffe6c 244 [RTL_GIGA_MAC_VER_29] =
6ed0e08f 245 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
85bffe6c 246 [RTL_GIGA_MAC_VER_30] =
6ed0e08f 247 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
85bffe6c 248 [RTL_GIGA_MAC_VER_31] =
6ed0e08f 249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K),
85bffe6c 250 [RTL_GIGA_MAC_VER_32] =
6ed0e08f 251 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, JUMBO_9K),
85bffe6c 252 [RTL_GIGA_MAC_VER_33] =
6ed0e08f 253 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, JUMBO_9K),
70090424 254 [RTL_GIGA_MAC_VER_34] =
6ed0e08f 255 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, JUMBO_9K),
c2218925 256 [RTL_GIGA_MAC_VER_35] =
6ed0e08f 257 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, JUMBO_9K),
c2218925 258 [RTL_GIGA_MAC_VER_36] =
6ed0e08f 259 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, JUMBO_9K),
7e18dca1 260 [RTL_GIGA_MAC_VER_37] =
6ed0e08f 261 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1, JUMBO_1K),
b3d7b2f2 262 [RTL_GIGA_MAC_VER_38] =
6ed0e08f 263 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1, JUMBO_9K),
5598bfe5 264 [RTL_GIGA_MAC_VER_39] =
6ed0e08f 265 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1, JUMBO_1K),
c558386b 266 [RTL_GIGA_MAC_VER_40] =
6ed0e08f 267 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2, JUMBO_9K),
c558386b 268 [RTL_GIGA_MAC_VER_41] =
6ed0e08f 269 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K),
57538c4a 270 [RTL_GIGA_MAC_VER_42] =
6ed0e08f 271 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3, JUMBO_9K),
58152cd4 272 [RTL_GIGA_MAC_VER_43] =
6ed0e08f 273 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2, JUMBO_1K),
45dd95c4 274 [RTL_GIGA_MAC_VER_44] =
6ed0e08f 275 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2, JUMBO_9K),
6e1d0b89 276 [RTL_GIGA_MAC_VER_45] =
6ed0e08f 277 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1, JUMBO_9K),
6e1d0b89 278 [RTL_GIGA_MAC_VER_46] =
6ed0e08f 279 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2, JUMBO_9K),
6e1d0b89 280 [RTL_GIGA_MAC_VER_47] =
6ed0e08f 281 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1, JUMBO_1K),
6e1d0b89 282 [RTL_GIGA_MAC_VER_48] =
6ed0e08f 283 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2, JUMBO_1K),
935e2218 284 [RTL_GIGA_MAC_VER_49] =
6ed0e08f 285 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
935e2218 286 [RTL_GIGA_MAC_VER_50] =
6ed0e08f 287 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
935e2218 288 [RTL_GIGA_MAC_VER_51] =
6ed0e08f 289 _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K),
953a12cc 290};
85bffe6c 291#undef _R
953a12cc 292
bcf0bf90
FR		 293enum cfg_version {
294 RTL_CFG_0 = 0x00,
295 RTL_CFG_1,
296 RTL_CFG_2
297};
298
9baa3c34 299static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 300 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 301 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
610c9087 302 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
d81bf551 303 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 304 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 305 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 306 { PCI_VENDOR_ID_DLINK, 0x4300,
307 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 308 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 309 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 310 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 311 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
312 { PCI_VENDOR_ID_LINKSYS, 0x1032,
313 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 314 { 0x0001, 0x8168,
315 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 316 {0,},
317};
318
319MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
320
27896c83 321static int use_dac = -1;
b57b7e5a
SH		 322static struct {
323 u32 msg_enable;
324} debug = { -1 };
1da177e4 325
07d3f51f
FR		 326enum rtl_registers {
327 MAC0 = 0, /* Ethernet hardware address. */
773d2021 328 MAC4 = 4,
07d3f51f
FR		 329 MAR0 = 8, /* Multicast filter. */
330 CounterAddrLow = 0x10,
331 CounterAddrHigh = 0x14,
332 TxDescStartAddrLow = 0x20,
333 TxDescStartAddrHigh = 0x24,
334 TxHDescStartAddrLow = 0x28,
335 TxHDescStartAddrHigh = 0x2c,
336 FLASH = 0x30,
337 ERSR = 0x36,
338 ChipCmd = 0x37,
339 TxPoll = 0x38,
340 IntrMask = 0x3c,
341 IntrStatus = 0x3e,
4f6b00e5 342
07d3f51f 343 TxConfig = 0x40,
4f6b00e5
HW		 344#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
345#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 346
4f6b00e5
HW		 347 RxConfig = 0x44,
348#define RX128_INT_EN (1 << 15) /* 8111c and later */
349#define RX_MULTI_EN (1 << 14) /* 8111c only */
350#define RXCFG_FIFO_SHIFT 13
351 /* No threshold before first PCI xfer */
352#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 353#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 354#define RXCFG_DMA_SHIFT 8
355 /* Unlimited maximum PCI burst. */
356#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 357
07d3f51f
FR		 358 RxMissed = 0x4c,
359 Cfg9346 = 0x50,
360 Config0 = 0x51,
361 Config1 = 0x52,
362 Config2 = 0x53,
d387b427
FR		 363#define PME_SIGNAL (1 << 5) /* 8168c and later */
364
07d3f51f
FR		 365 Config3 = 0x54,
366 Config4 = 0x55,
367 Config5 = 0x56,
368 MultiIntr = 0x5c,
369 PHYAR = 0x60,
07d3f51f
FR		 370 PHYstatus = 0x6c,
371 RxMaxSize = 0xda,
372 CPlusCmd = 0xe0,
373 IntrMitigate = 0xe2,
50970831
FR		 374
375#define RTL_COALESCE_MASK 0x0f
376#define RTL_COALESCE_SHIFT 4
377#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
378#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
379
07d3f51f
FR		 380 RxDescAddrLow = 0xe4,
381 RxDescAddrHigh = 0xe8,
f0298f81 382 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
383
384#define NoEarlyTx 0x3f /* Max value : no early transmit. */
385
386 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
387
388#define TxPacketMax (8064 >> 7)
3090bd9a 389#define EarlySize 0x27
f0298f81 390
07d3f51f
FR		 391 FuncEvent = 0xf0,
392 FuncEventMask = 0xf4,
393 FuncPresetState = 0xf8,
935e2218
CHL		 394 IBCR0 = 0xf8,
395 IBCR2 = 0xf9,
396 IBIMR0 = 0xfa,
397 IBISR0 = 0xfb,
07d3f51f 398 FuncForceEvent = 0xfc,
1da177e4
LT		 399};
400
f162a5d1
FR		 401enum rtl8110_registers {
402 TBICSR = 0x64,
403 TBI_ANAR = 0x68,
404 TBI_LPAR = 0x6a,
405};
406
407enum rtl8168_8101_registers {
408 CSIDR = 0x64,
409 CSIAR = 0x68,
410#define CSIAR_FLAG 0x80000000
411#define CSIAR_WRITE_CMD 0x80000000
ff1d7331
HK		 412#define CSIAR_BYTE_ENABLE 0x0000f000
413#define CSIAR_ADDR_MASK 0x00000fff
065c27c1 414 PMCH = 0x6f,
f162a5d1
FR		 415 EPHYAR = 0x80,
416#define EPHYAR_FLAG 0x80000000
417#define EPHYAR_WRITE_CMD 0x80000000
418#define EPHYAR_REG_MASK 0x1f
419#define EPHYAR_REG_SHIFT 16
420#define EPHYAR_DATA_MASK 0xffff
5a5e4443 421 DLLPR = 0xd0,
4f6b00e5 422#define PFM_EN (1 << 6)
6e1d0b89 423#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 424 DBG_REG = 0xd1,
425#define FIX_NAK_1 (1 << 4)
426#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 427 TWSI = 0xd2,
428 MCU = 0xd3,
4f6b00e5 429#define NOW_IS_OOB (1 << 7)
c558386b
HW		 430#define TX_EMPTY (1 << 5)
431#define RX_EMPTY (1 << 4)
432#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 433#define EN_NDP (1 << 3)
434#define EN_OOB_RESET (1 << 2)
c558386b 435#define LINK_LIST_RDY (1 << 1)
daf9df6d 436 EFUSEAR = 0xdc,
437#define EFUSEAR_FLAG 0x80000000
438#define EFUSEAR_WRITE_CMD 0x80000000
439#define EFUSEAR_READ_CMD 0x00000000
440#define EFUSEAR_REG_MASK 0x03ff
441#define EFUSEAR_REG_SHIFT 8
442#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 443 MISC_1 = 0xf2,
444#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 445};
446
c0e45c1c 447enum rtl8168_registers {
4f6b00e5
HW		 448 LED_FREQ = 0x1a,
449 EEE_LED = 0x1b,
b646d900 450 ERIDR = 0x70,
451 ERIAR = 0x74,
452#define ERIAR_FLAG 0x80000000
453#define ERIAR_WRITE_CMD 0x80000000
454#define ERIAR_READ_CMD 0x00000000
455#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 456#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 457#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
458#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
459#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 460#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 461#define ERIAR_MASK_SHIFT 12
462#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
463#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 464#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 465#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 466#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 467 EPHY_RXER_NUM = 0x7c,
468 OCPDR = 0xb0, /* OCP GPHY access */
469#define OCPDR_WRITE_CMD 0x80000000
470#define OCPDR_READ_CMD 0x00000000
471#define OCPDR_REG_MASK 0x7f
472#define OCPDR_GPHY_REG_SHIFT 16
473#define OCPDR_DATA_MASK 0xffff
474 OCPAR = 0xb4,
475#define OCPAR_FLAG 0x80000000
476#define OCPAR_GPHY_WRITE_CMD 0x8000f060
477#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 478 GPHY_OCP = 0xb8,
01dc7fec 479 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
480 MISC = 0xf0, /* 8168e only. */
cecb5fd7 481#define TXPLA_RST (1 << 29)
5598bfe5 482#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 483#define PWM_EN (1 << 22)
c558386b 484#define RXDV_GATED_EN (1 << 19)
5598bfe5 485#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 486};
487
07d3f51f 488enum rtl_register_content {
1da177e4 489 /* InterruptStatusBits */
07d3f51f
FR		 490 SYSErr = 0x8000,
491 PCSTimeout = 0x4000,
492 SWInt = 0x0100,
493 TxDescUnavail = 0x0080,
494 RxFIFOOver = 0x0040,
495 LinkChg = 0x0020,
496 RxOverflow = 0x0010,
497 TxErr = 0x0008,
498 TxOK = 0x0004,
499 RxErr = 0x0002,
500 RxOK = 0x0001,
1da177e4
LT		 501
502 /* RxStatusDesc */
e03f33af 503 RxBOVF = (1 << 24),
9dccf611
FR		 504 RxFOVF = (1 << 23),
505 RxRWT = (1 << 22),
506 RxRES = (1 << 21),
507 RxRUNT = (1 << 20),
508 RxCRC = (1 << 19),
1da177e4
LT		 509
510 /* ChipCmdBits */
4f6b00e5 511 StopReq = 0x80,
07d3f51f
FR		 512 CmdReset = 0x10,
513 CmdRxEnb = 0x08,
514 CmdTxEnb = 0x04,
515 RxBufEmpty = 0x01,
1da177e4 516
275391a4
FR		 517 /* TXPoll register p.5 */
518 HPQ = 0x80, /* Poll cmd on the high prio queue */
519 NPQ = 0x40, /* Poll cmd on the low prio queue */
520 FSWInt = 0x01, /* Forced software interrupt */
521
1da177e4 522 /* Cfg9346Bits */
07d3f51f
FR		 523 Cfg9346_Lock = 0x00,
524 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 525
526 /* rx_mode_bits */
07d3f51f
FR		 527 AcceptErr = 0x20,
528 AcceptRunt = 0x10,
529 AcceptBroadcast = 0x08,
530 AcceptMulticast = 0x04,
531 AcceptMyPhys = 0x02,
532 AcceptAllPhys = 0x01,
1687b566 533#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 534
1da177e4
LT		 535 /* TxConfigBits */
536 TxInterFrameGapShift = 24,
537 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
538
5d06a99f 539 /* Config1 register p.24 */
f162a5d1
FR		 540 LEDS1 = (1 << 7),
541 LEDS0 = (1 << 6),
f162a5d1
FR		 542 Speed_down = (1 << 4),
543 MEMMAP = (1 << 3),
544 IOMAP = (1 << 2),
545 VPD = (1 << 1),
5d06a99f
FR		 546 PMEnable = (1 << 0), /* Power Management Enable */
547
6dccd16b 548 /* Config2 register p. 25 */
57538c4a 549 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 550 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 551 PCI_Clock_66MHz = 0x01,
552 PCI_Clock_33MHz = 0x00,
553
61a4dcc2
FR		 554 /* Config3 register p.25 */
555 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
556 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 557 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 558 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 559 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 560
d58d46b5
FR		 561 /* Config4 register */
562 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
563
5d06a99f 564 /* Config5 register p.27 */
61a4dcc2
FR		 565 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
566 MWF = (1 << 5), /* Accept Multicast wakeup frame */
567 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 568 Spi_en = (1 << 3),
61a4dcc2 569 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 570 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 571 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 572
1da177e4
LT		 573 /* TBICSR p.28 */
574 TBIReset = 0x80000000,
575 TBILoopback = 0x40000000,
576 TBINwEnable = 0x20000000,
577 TBINwRestart = 0x10000000,
578 TBILinkOk = 0x02000000,
579 TBINwComplete = 0x01000000,
580
581 /* CPlusCmd p.31 */
f162a5d1
FR		 582 EnableBist = (1 << 15), // 8168 8101
583 Mac_dbgo_oe = (1 << 14), // 8168 8101
584 Normal_mode = (1 << 13), // unused
585 Force_half_dup = (1 << 12), // 8168 8101
586 Force_rxflow_en = (1 << 11), // 8168 8101
587 Force_txflow_en = (1 << 10), // 8168 8101
588 Cxpl_dbg_sel = (1 << 9), // 8168 8101
589 ASF = (1 << 8), // 8168 8101
590 PktCntrDisable = (1 << 7), // 8168 8101
591 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 592 RxVlan = (1 << 6),
593 RxChkSum = (1 << 5),
594 PCIDAC = (1 << 4),
595 PCIMulRW = (1 << 3),
9a3c81fa 596#define INTT_MASK GENMASK(1, 0)
0e485150
FR		 597 INTT_0 = 0x0000, // 8168
598 INTT_1 = 0x0001, // 8168
599 INTT_2 = 0x0002, // 8168
600 INTT_3 = 0x0003, // 8168
1da177e4
LT		 601
602 /* rtl8169_PHYstatus */
07d3f51f
FR		 603 TBI_Enable = 0x80,
604 TxFlowCtrl = 0x40,
605 RxFlowCtrl = 0x20,
606 _1000bpsF = 0x10,
607 _100bps = 0x08,
608 _10bps = 0x04,
609 LinkStatus = 0x02,
610 FullDup = 0x01,
1da177e4 611
1da177e4 612 /* _TBICSRBit */
07d3f51f 613 TBILinkOK = 0x02000000,
d4a3a0fc 614
6e85d5ad
CV		 615 /* ResetCounterCommand */
616 CounterReset = 0x1,
617
d4a3a0fc 618 /* DumpCounterCommand */
07d3f51f 619 CounterDump = 0x8,
6e1d0b89
CHL		 620
621 /* magic enable v2 */
622 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 623};
624
2b7b4318
FR		 625enum rtl_desc_bit {
626 /* First doubleword. */
1da177e4
LT		 627 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
628 RingEnd = (1 << 30), /* End of descriptor ring */
629 FirstFrag = (1 << 29), /* First segment of a packet */
630 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 631};
632
633/* Generic case. */
634enum rtl_tx_desc_bit {
635 /* First doubleword. */
636 TD_LSO = (1 << 27), /* Large Send Offload */
637#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 638
2b7b4318
FR		 639 /* Second doubleword. */
640 TxVlanTag = (1 << 17), /* Add VLAN tag */
641};
642
643/* 8169, 8168b and 810x except 8102e. */
644enum rtl_tx_desc_bit_0 {
645 /* First doubleword. */
646#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
647 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
648 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
649 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
650};
651
652/* 8102e, 8168c and beyond. */
653enum rtl_tx_desc_bit_1 {
bdfa4ed6 654 /* First doubleword. */
655 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 656 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 657#define GTTCPHO_SHIFT 18
e974604b 658#define GTTCPHO_MAX 0x7fU
bdfa4ed6 659
2b7b4318 660 /* Second doubleword. */
e974604b 661#define TCPHO_SHIFT 18
662#define TCPHO_MAX 0x3ffU
2b7b4318 663#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 664 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
665 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 666 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
667 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
668};
1da177e4 669
2b7b4318 670enum rtl_rx_desc_bit {
1da177e4
LT		 671 /* Rx private */
672 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 673 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 674
675#define RxProtoUDP (PID1)
676#define RxProtoTCP (PID0)
677#define RxProtoIP (PID1 | PID0)
678#define RxProtoMask RxProtoIP
679
680 IPFail = (1 << 16), /* IP checksum failed */
681 UDPFail = (1 << 15), /* UDP/IP checksum failed */
682 TCPFail = (1 << 14), /* TCP/IP checksum failed */
683 RxVlanTag = (1 << 16), /* VLAN tag available */
684};
685
686#define RsvdMask 0x3fffc000
12d42c50 687#define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
1da177e4
LT		 688
689struct TxDesc {
6cccd6e7
REB		 690 __le32 opts1;
691 __le32 opts2;
692 __le64 addr;
1da177e4
LT		 693};
694
695struct RxDesc {
6cccd6e7
REB		 696 __le32 opts1;
697 __le32 opts2;
698 __le64 addr;
1da177e4
LT		 699};
700
701struct ring_info {
702 struct sk_buff *skb;
703 u32 len;
704 u8 __pad[sizeof(void *) - sizeof(u32)];
705};
706
355423d0
IV		 707struct rtl8169_counters {
708 __le64 tx_packets;
709 __le64 rx_packets;
710 __le64 tx_errors;
711 __le32 rx_errors;
712 __le16 rx_missed;
713 __le16 align_errors;
714 __le32 tx_one_collision;
715 __le32 tx_multi_collision;
716 __le64 rx_unicast;
717 __le64 rx_broadcast;
718 __le32 rx_multicast;
719 __le16 tx_aborted;
720 __le16 tx_underun;
721};
722
6e85d5ad
CV		 723struct rtl8169_tc_offsets {
724 bool inited;
725 __le64 tx_errors;
726 __le32 tx_multi_collision;
6e85d5ad
CV		 727 __le16 tx_aborted;
728};
729
da78dbff 730enum rtl_flag {
6c4a70c5 731 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 732 RTL_FLAG_TASK_SLOW_PENDING,
733 RTL_FLAG_TASK_RESET_PENDING,
734 RTL_FLAG_TASK_PHY_PENDING,
735 RTL_FLAG_MAX
736};
737
8027aa24
JW		 738struct rtl8169_stats {
739 u64 packets;
740 u64 bytes;
741 struct u64_stats_sync syncp;
742};
743
1da177e4
LT		 744struct rtl8169_private {
745 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 746 struct pci_dev *pci_dev;
c4028958 747 struct net_device *dev;
bea3348e 748 struct napi_struct napi;
b57b7e5a 749 u32 msg_enable;
2b7b4318 750 u16 mac_version;
1da177e4
LT		 751 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
752 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 753 u32 dirty_tx;
8027aa24
JW		 754 struct rtl8169_stats rx_stats;
755 struct rtl8169_stats tx_stats;
1da177e4
LT		 756 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
757 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
758 dma_addr_t TxPhyAddr;
759 dma_addr_t RxPhyAddr;
6f0333b8 760 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 761 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 762 struct timer_list timer;
763 u16 cp_cmd;
da78dbff
FR		 764
765 u16 event_slow;
50970831 766 const struct rtl_coalesce_info *coalesce_info;
c0e45c1c 767
768 struct mdio_ops {
24192210
FR		 769 void (*write)(struct rtl8169_private *, int, int);
770 int (*read)(struct rtl8169_private *, int);
c0e45c1c 771 } mdio_ops;
772
d58d46b5
FR		 773 struct jumbo_ops {
774 void (*enable)(struct rtl8169_private *);
775 void (*disable)(struct rtl8169_private *);
776 } jumbo_ops;
777
54405cde 778 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
6fa1ba61
PR		 779 int (*get_link_ksettings)(struct net_device *,
780 struct ethtool_link_ksettings *);
4da19633 781 void (*phy_reset_enable)(struct rtl8169_private *tp);
61cb532d 782 void (*hw_start)(struct rtl8169_private *tp);
4da19633 783 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1ef7286e 784 unsigned int (*link_ok)(struct rtl8169_private *tp);
8b4ab28d 785 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
5888d3fc 786 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 787
788 struct {
da78dbff
FR		 789 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
790 struct mutex mutex;
4422bcd4
FR		 791 struct work_struct work;
792 } wk;
793
ccdffb9a 794 struct mii_if_info mii;
42020320
CV		 795 dma_addr_t counters_phys_addr;
796 struct rtl8169_counters *counters;
6e85d5ad 797 struct rtl8169_tc_offsets tc_offset;
e1759441 798 u32 saved_wolopts;
f1e02ed1 799
b6ffd97f
FR		 800 struct rtl_fw {
801 const struct firmware *fw;
1c361efb
FR		 802
803#define RTL_VER_SIZE 32
804
805 char version[RTL_VER_SIZE];
806
807 struct rtl_fw_phy_action {
808 __le32 *code;
809 size_t size;
810 } phy_action;
b6ffd97f 811 } *rtl_fw;
497888cf 812#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 813
814 u32 ocp_base;
1da177e4
LT		 815};
816
979b6c13 817MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 818MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 819module_param(use_dac, int, 0);
4300e8c7 820MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 821module_param_named(debug, debug.msg_enable, int, 0);
822MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 823MODULE_LICENSE("GPL");
824MODULE_VERSION(RTL8169_VERSION);
bca03d5f 825MODULE_FIRMWARE(FIRMWARE_8168D_1);
826MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 827MODULE_FIRMWARE(FIRMWARE_8168E_1);
828MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 829MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 830MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 831MODULE_FIRMWARE(FIRMWARE_8168F_1);
832MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 833MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 834MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 835MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 836MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 837MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 838MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 839MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 840MODULE_FIRMWARE(FIRMWARE_8168H_1);
841MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 842MODULE_FIRMWARE(FIRMWARE_8107E_1);
843MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 844
1e1205b7
HK		 845static inline struct device *tp_to_dev(struct rtl8169_private *tp)
846{
847 return &tp->pci_dev->dev;
848}
849
da78dbff
FR		 850static void rtl_lock_work(struct rtl8169_private *tp)
851{
852 mutex_lock(&tp->wk.mutex);
853}
854
855static void rtl_unlock_work(struct rtl8169_private *tp)
856{
857 mutex_unlock(&tp->wk.mutex);
858}
859
cb73200c 860static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
d58d46b5 861{
cb73200c 862 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
7d7903b2 863 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 864}
865
ffc46952
FR		 866struct rtl_cond {
867 bool (*check)(struct rtl8169_private *);
868 const char *msg;
869};
870
871static void rtl_udelay(unsigned int d)
872{
873 udelay(d);
874}
875
876static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
877 void (*delay)(unsigned int), unsigned int d, int n,
878 bool high)
879{
880 int i;
881
882 for (i = 0; i < n; i++) {
883 delay(d);
884 if (c->check(tp) == high)
885 return true;
886 }
82e316ef
FR		 887 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
888 c->msg, !high, n, d);
ffc46952
FR		 889 return false;
890}
891
892static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
893 const struct rtl_cond *c,
894 unsigned int d, int n)
895{
896 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
897}
898
899static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
900 const struct rtl_cond *c,
901 unsigned int d, int n)
902{
903 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
904}
905
906static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
907 const struct rtl_cond *c,
908 unsigned int d, int n)
909{
910 return rtl_loop_wait(tp, c, msleep, d, n, true);
911}
912
913static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
914 const struct rtl_cond *c,
915 unsigned int d, int n)
916{
917 return rtl_loop_wait(tp, c, msleep, d, n, false);
918}
919
920#define DECLARE_RTL_COND(name) \
921static bool name ## _check(struct rtl8169_private *); \
922 \
923static const struct rtl_cond name = { \
924 .check = name ## _check, \
925 .msg = #name \
926}; \
927 \
928static bool name ## _check(struct rtl8169_private *tp)
929
c558386b
HW		 930static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
931{
932 if (reg & 0xffff0001) {
933 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
934 return true;
935 }
936 return false;
937}
938
939DECLARE_RTL_COND(rtl_ocp_gphy_cond)
940{
1ef7286e 941 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
c558386b
HW		 942}
943
944static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
945{
c558386b
HW		 946 if (rtl_ocp_reg_failure(tp, reg))
947 return;
948
1ef7286e 949 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 950
951 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
952}
953
954static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
955{
c558386b
HW		 956 if (rtl_ocp_reg_failure(tp, reg))
957 return 0;
958
1ef7286e 959 RTL_W32(tp, GPHY_OCP, reg << 15);
c558386b
HW		 960
961 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1ef7286e 962 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
c558386b
HW		 963}
964
c558386b
HW		 965static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
966{
c558386b
HW		 967 if (rtl_ocp_reg_failure(tp, reg))
968 return;
969
1ef7286e 970 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 971}
972
973static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
974{
c558386b
HW		 975 if (rtl_ocp_reg_failure(tp, reg))
976 return 0;
977
1ef7286e 978 RTL_W32(tp, OCPDR, reg << 15);
c558386b 979
1ef7286e 980 return RTL_R32(tp, OCPDR);
c558386b
HW		 981}
982
983#define OCP_STD_PHY_BASE 0xa400
984
985static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
986{
987 if (reg == 0x1f) {
988 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
989 return;
990 }
991
992 if (tp->ocp_base != OCP_STD_PHY_BASE)
993 reg -= 0x10;
994
995 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
996}
997
998static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
999{
1000 if (tp->ocp_base != OCP_STD_PHY_BASE)
1001 reg -= 0x10;
1002
1003 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1004}
1005
eee3786f 1006static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1007{
1008 if (reg == 0x1f) {
1009 tp->ocp_base = value << 4;
1010 return;
1011 }
1012
1013 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1014}
1015
1016static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1017{
1018 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1019}
1020
ffc46952
FR		 1021DECLARE_RTL_COND(rtl_phyar_cond)
1022{
1ef7286e 1023 return RTL_R32(tp, PHYAR) & 0x80000000;
ffc46952
FR		 1024}
1025
24192210 1026static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1027{
1ef7286e 1028 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1029
ffc46952 1030 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1031 /*
81a95f04
TT		 1032 * According to hardware specs a 20us delay is required after write
1033 * complete indication, but before sending next command.
024a07ba 1034 */
81a95f04 1035 udelay(20);
1da177e4
LT		 1036}
1037
24192210 1038static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1039{
ffc46952 1040 int value;
1da177e4 1041
1ef7286e 1042 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1043
ffc46952 1044 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1ef7286e 1045 RTL_R32(tp, PHYAR) & 0xffff : ~0;
ffc46952 1046
81a95f04
TT		 1047 /*
1048 * According to hardware specs a 20us delay is required after read
1049 * complete indication, but before sending next command.
1050 */
1051 udelay(20);
1052
1da177e4
LT		 1053 return value;
1054}
1055
935e2218
CHL		 1056DECLARE_RTL_COND(rtl_ocpar_cond)
1057{
1ef7286e 1058 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
935e2218
CHL		 1059}
1060
24192210 1061static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1062{
1ef7286e
AS		 1063 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1064 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
1065 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 1066
ffc46952 1067 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1068}
1069
24192210 1070static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1071{
24192210
FR		 1072 r8168dp_1_mdio_access(tp, reg,
1073 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1074}
1075
24192210 1076static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1077{
24192210 1078 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1079
1080 mdelay(1);
1ef7286e
AS		 1081 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1082 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 1083
ffc46952 1084 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1ef7286e 1085 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1086}
1087
e6de30d6 1088#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1089
1ef7286e 1090static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
e6de30d6 1091{
1ef7286e 1092 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1093}
1094
1ef7286e 1095static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
e6de30d6 1096{
1ef7286e 1097 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 1098}
1099
24192210 1100static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1101{
1ef7286e 1102 r8168dp_2_mdio_start(tp);
e6de30d6 1103
24192210 1104 r8169_mdio_write(tp, reg, value);
e6de30d6 1105
1ef7286e 1106 r8168dp_2_mdio_stop(tp);
e6de30d6 1107}
1108
24192210 1109static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1110{
1111 int value;
1112
1ef7286e 1113 r8168dp_2_mdio_start(tp);
e6de30d6 1114
24192210 1115 value = r8169_mdio_read(tp, reg);
e6de30d6 1116
1ef7286e 1117 r8168dp_2_mdio_stop(tp);
e6de30d6 1118
1119 return value;
1120}
1121
4da19633 1122static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1123{
24192210 1124 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1125}
1126
4da19633 1127static int rtl_readphy(struct rtl8169_private *tp, int location)
1128{
24192210 1129 return tp->mdio_ops.read(tp, location);
4da19633 1130}
1131
1132static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1133{
1134 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1135}
1136
76564428 1137static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1138{
1139 int val;
1140
4da19633 1141 val = rtl_readphy(tp, reg_addr);
76564428 1142 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1143}
1144
ccdffb9a
FR		 1145static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1146 int val)
1147{
1148 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1149
4da19633 1150 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1151}
1152
1153static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1154{
1155 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1156
4da19633 1157 return rtl_readphy(tp, location);
ccdffb9a
FR		 1158}
1159
ffc46952
FR		 1160DECLARE_RTL_COND(rtl_ephyar_cond)
1161{
1ef7286e 1162 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
ffc46952
FR		 1163}
1164
fdf6fc06 1165static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1166{
1ef7286e 1167 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
dacf8154
FR		 1168 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1169
ffc46952
FR		 1170 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1171
1172 udelay(10);
dacf8154
FR		 1173}
1174
fdf6fc06 1175static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1176{
1ef7286e 1177 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
dacf8154 1178
ffc46952 1179 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1ef7286e 1180 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1181}
1182
935e2218
CHL		 1183DECLARE_RTL_COND(rtl_eriar_cond)
1184{
1ef7286e 1185 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
935e2218
CHL		 1186}
1187
fdf6fc06
FR		 1188static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1189 u32 val, int type)
133ac40a 1190{
133ac40a 1191 BUG_ON((addr & 3) || (mask == 0));
1ef7286e
AS		 1192 RTL_W32(tp, ERIDR, val);
1193 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
133ac40a 1194
ffc46952 1195 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1196}
1197
fdf6fc06 1198static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1199{
1ef7286e 1200 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
133ac40a 1201
ffc46952 1202 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1ef7286e 1203 RTL_R32(tp, ERIDR) : ~0;
133ac40a
HW		 1204}
1205
706123d0 1206static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1207 u32 m, int type)
133ac40a
HW		 1208{
1209 u32 val;
1210
fdf6fc06
FR		 1211 val = rtl_eri_read(tp, addr, type);
1212 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1213}
1214
935e2218
CHL		 1215static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1216{
1ef7286e 1217 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218 1218 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1ef7286e 1219 RTL_R32(tp, OCPDR) : ~0;
935e2218
CHL		 1220}
1221
1222static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1223{
1224 return rtl_eri_read(tp, reg, ERIAR_OOB);
1225}
1226
1227static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1228{
1229 switch (tp->mac_version) {
1230 case RTL_GIGA_MAC_VER_27:
1231 case RTL_GIGA_MAC_VER_28:
1232 case RTL_GIGA_MAC_VER_31:
1233 return r8168dp_ocp_read(tp, mask, reg);
1234 case RTL_GIGA_MAC_VER_49:
1235 case RTL_GIGA_MAC_VER_50:
1236 case RTL_GIGA_MAC_VER_51:
1237 return r8168ep_ocp_read(tp, mask, reg);
1238 default:
1239 BUG();
1240 return ~0;
1241 }
1242}
1243
1244static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1245 u32 data)
1246{
1ef7286e
AS		 1247 RTL_W32(tp, OCPDR, data);
1248 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218
CHL		 1249 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1250}
1251
1252static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1253 u32 data)
1254{
1255 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1256 data, ERIAR_OOB);
1257}
1258
1259static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1260{
1261 switch (tp->mac_version) {
1262 case RTL_GIGA_MAC_VER_27:
1263 case RTL_GIGA_MAC_VER_28:
1264 case RTL_GIGA_MAC_VER_31:
1265 r8168dp_ocp_write(tp, mask, reg, data);
1266 break;
1267 case RTL_GIGA_MAC_VER_49:
1268 case RTL_GIGA_MAC_VER_50:
1269 case RTL_GIGA_MAC_VER_51:
1270 r8168ep_ocp_write(tp, mask, reg, data);
1271 break;
1272 default:
1273 BUG();
1274 break;
1275 }
1276}
1277
2a9b4d96
CHL		 1278static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1279{
1280 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1281
1282 ocp_write(tp, 0x1, 0x30, 0x00000001);
1283}
1284
1285#define OOB_CMD_RESET 0x00
1286#define OOB_CMD_DRIVER_START 0x05
1287#define OOB_CMD_DRIVER_STOP 0x06
1288
1289static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1290{
1291 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1292}
1293
1294DECLARE_RTL_COND(rtl_ocp_read_cond)
1295{
1296 u16 reg;
1297
1298 reg = rtl8168_get_ocp_reg(tp);
1299
1300 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1301}
1302
935e2218 1303DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1304{
935e2218
CHL		 1305 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1306}
1307
1308DECLARE_RTL_COND(rtl_ocp_tx_cond)
1309{
1ef7286e 1310 return RTL_R8(tp, IBISR0) & 0x20;
935e2218 1311}
2a9b4d96 1312
003609da
CHL		 1313static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1314{
1ef7286e 1315 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
086ca23d 1316 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1ef7286e
AS		 1317 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1318 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
003609da
CHL		 1319}
1320
935e2218
CHL		 1321static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1322{
1323 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
2a9b4d96
CHL		 1324 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1325}
1326
935e2218 1327static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1328{
935e2218
CHL		 1329 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1330 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1331 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1332}
1333
1334static void rtl8168_driver_start(struct rtl8169_private *tp)
1335{
1336 switch (tp->mac_version) {
1337 case RTL_GIGA_MAC_VER_27:
1338 case RTL_GIGA_MAC_VER_28:
1339 case RTL_GIGA_MAC_VER_31:
1340 rtl8168dp_driver_start(tp);
1341 break;
1342 case RTL_GIGA_MAC_VER_49:
1343 case RTL_GIGA_MAC_VER_50:
1344 case RTL_GIGA_MAC_VER_51:
1345 rtl8168ep_driver_start(tp);
1346 break;
1347 default:
1348 BUG();
1349 break;
1350 }
1351}
2a9b4d96 1352
935e2218
CHL		 1353static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1354{
1355 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
2a9b4d96
CHL		 1356 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1357}
1358
935e2218
CHL		 1359static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1360{
003609da 1361 rtl8168ep_stop_cmac(tp);
935e2218
CHL		 1362 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1363 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1364 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1365}
1366
1367static void rtl8168_driver_stop(struct rtl8169_private *tp)
1368{
1369 switch (tp->mac_version) {
1370 case RTL_GIGA_MAC_VER_27:
1371 case RTL_GIGA_MAC_VER_28:
1372 case RTL_GIGA_MAC_VER_31:
1373 rtl8168dp_driver_stop(tp);
1374 break;
1375 case RTL_GIGA_MAC_VER_49:
1376 case RTL_GIGA_MAC_VER_50:
1377 case RTL_GIGA_MAC_VER_51:
1378 rtl8168ep_driver_stop(tp);
1379 break;
1380 default:
1381 BUG();
1382 break;
1383 }
1384}
1385
9dbe7896 1386static bool r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1387{
1388 u16 reg = rtl8168_get_ocp_reg(tp);
1389
9dbe7896 1390 return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
2a9b4d96
CHL		 1391}
1392
9dbe7896 1393static bool r8168ep_check_dash(struct rtl8169_private *tp)
935e2218 1394{
9dbe7896 1395 return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
935e2218
CHL		 1396}
1397
9dbe7896 1398static bool r8168_check_dash(struct rtl8169_private *tp)
935e2218
CHL		 1399{
1400 switch (tp->mac_version) {
1401 case RTL_GIGA_MAC_VER_27:
1402 case RTL_GIGA_MAC_VER_28:
1403 case RTL_GIGA_MAC_VER_31:
1404 return r8168dp_check_dash(tp);
1405 case RTL_GIGA_MAC_VER_49:
1406 case RTL_GIGA_MAC_VER_50:
1407 case RTL_GIGA_MAC_VER_51:
1408 return r8168ep_check_dash(tp);
1409 default:
9dbe7896 1410 return false;
935e2218
CHL		 1411 }
1412}
1413
c28aa385 1414struct exgmac_reg {
1415 u16 addr;
1416 u16 mask;
1417 u32 val;
1418};
1419
fdf6fc06 1420static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1421 const struct exgmac_reg *r, int len)
1422{
1423 while (len-- > 0) {
fdf6fc06 1424 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1425 r++;
1426 }
1427}
1428
ffc46952
FR		 1429DECLARE_RTL_COND(rtl_efusear_cond)
1430{
1ef7286e 1431 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
ffc46952
FR		 1432}
1433
fdf6fc06 1434static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1435{
1ef7286e 1436 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
daf9df6d 1437
ffc46952 1438 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1ef7286e 1439 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1440}
1441
9085cdfa
FR		 1442static u16 rtl_get_events(struct rtl8169_private *tp)
1443{
1ef7286e 1444 return RTL_R16(tp, IntrStatus);
9085cdfa
FR		 1445}
1446
1447static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1448{
1ef7286e 1449 RTL_W16(tp, IntrStatus, bits);
9085cdfa
FR		 1450 mmiowb();
1451}
1452
1453static void rtl_irq_disable(struct rtl8169_private *tp)
1454{
1ef7286e 1455 RTL_W16(tp, IntrMask, 0);
9085cdfa
FR		 1456 mmiowb();
1457}
1458
3e990ff5
FR		 1459static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1460{
1ef7286e 1461 RTL_W16(tp, IntrMask, bits);
3e990ff5
FR		 1462}
1463
da78dbff
FR		 1464#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1465#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1466#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1467
1468static void rtl_irq_enable_all(struct rtl8169_private *tp)
1469{
1470 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1471}
1472
811fd301 1473static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1474{
9085cdfa 1475 rtl_irq_disable(tp);
da78dbff 1476 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1ef7286e 1477 RTL_R8(tp, ChipCmd);
1da177e4
LT		 1478}
1479
4da19633 1480static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1481{
1ef7286e 1482 return RTL_R32(tp, TBICSR) & TBIReset;
1da177e4
LT		 1483}
1484
4da19633 1485static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1486{
4da19633 1487 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1488}
1489
1ef7286e 1490static unsigned int rtl8169_tbi_link_ok(struct rtl8169_private *tp)
1da177e4 1491{
1ef7286e 1492 return RTL_R32(tp, TBICSR) & TBILinkOk;
1da177e4
LT		 1493}
1494
1ef7286e 1495static unsigned int rtl8169_xmii_link_ok(struct rtl8169_private *tp)
1da177e4 1496{
1ef7286e 1497 return RTL_R8(tp, PHYstatus) & LinkStatus;
1da177e4
LT		 1498}
1499
4da19633 1500static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1501{
1ef7286e 1502 RTL_W32(tp, TBICSR, RTL_R32(tp, TBICSR) | TBIReset);
1da177e4
LT		 1503}
1504
4da19633 1505static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1506{
1507 unsigned int val;
1508
4da19633 1509 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1510 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1511}
1512
70090424
HW		 1513static void rtl_link_chg_patch(struct rtl8169_private *tp)
1514{
70090424
HW		 1515 struct net_device *dev = tp->dev;
1516
1517 if (!netif_running(dev))
1518 return;
1519
b3d7b2f2
HW		 1520 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1521 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1ef7286e 1522 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1523 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1524 ERIAR_EXGMAC);
1525 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1526 ERIAR_EXGMAC);
1ef7286e 1527 } else if (RTL_R8(tp, PHYstatus) & _100bps) {
fdf6fc06
FR		 1528 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1529 ERIAR_EXGMAC);
1530 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1531 ERIAR_EXGMAC);
70090424 1532 } else {
fdf6fc06
FR		 1533 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1534 ERIAR_EXGMAC);
1535 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1536 ERIAR_EXGMAC);
70090424
HW		 1537 }
1538 /* Reset packet filter */
706123d0 1539 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1540 ERIAR_EXGMAC);
706123d0 1541 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1542 ERIAR_EXGMAC);
c2218925
HW		 1543 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1544 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1ef7286e 1545 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1546 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1547 ERIAR_EXGMAC);
1548 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1549 ERIAR_EXGMAC);
c2218925 1550 } else {
fdf6fc06
FR		 1551 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1552 ERIAR_EXGMAC);
1553 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1554 ERIAR_EXGMAC);
c2218925 1555 }
7e18dca1 1556 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1ef7286e 1557 if (RTL_R8(tp, PHYstatus) & _10bps) {
fdf6fc06
FR		 1558 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1559 ERIAR_EXGMAC);
1560 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1561 ERIAR_EXGMAC);
7e18dca1 1562 } else {
fdf6fc06
FR		 1563 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1564 ERIAR_EXGMAC);
7e18dca1 1565 }
70090424
HW		 1566 }
1567}
1568
ef4d5fcc 1569static void rtl8169_check_link_status(struct net_device *dev,
1ef7286e 1570 struct rtl8169_private *tp)
1da177e4 1571{
1e1205b7
HK		 1572 struct device *d = tp_to_dev(tp);
1573
1ef7286e 1574 if (tp->link_ok(tp)) {
70090424 1575 rtl_link_chg_patch(tp);
e1759441 1576 /* This is to cancel a scheduled suspend if there's one. */
1e1205b7 1577 pm_request_resume(d);
1da177e4 1578 netif_carrier_on(dev);
1519e57f
FR		 1579 if (net_ratelimit())
1580 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1581 } else {
1da177e4 1582 netif_carrier_off(dev);
bf82c189 1583 netif_info(tp, ifdown, dev, "link down\n");
1e1205b7 1584 pm_runtime_idle(d);
b57b7e5a 1585 }
1da177e4
LT		 1586}
1587
e1759441
RW		 1588#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1589
433f9d0d
HK		 1590/* Currently we only enable WoL if explicitly told by userspace to circumvent
1591 * issues on certain platforms, see commit bde135a672bf ("r8169: only enable
1592 * PCI wakeups when WOL is active"). Let's keep __rtl8169_get_wol() for the
1593 * case that we want to respect BIOS settings again.
1594 */
1595#if 0
e1759441 1596static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1597{
61a4dcc2 1598 u8 options;
e1759441 1599 u32 wolopts = 0;
61a4dcc2 1600
1ef7286e 1601 options = RTL_R8(tp, Config1);
61a4dcc2 1602 if (!(options & PMEnable))
e1759441 1603 return 0;
61a4dcc2 1604
1ef7286e 1605 options = RTL_R8(tp, Config3);
61a4dcc2 1606 if (options & LinkUp)
e1759441 1607 wolopts |= WAKE_PHY;
6e1d0b89 1608 switch (tp->mac_version) {
2a71883c
HK		 1609 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1610 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1611 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1612 wolopts |= WAKE_MAGIC;
1613 break;
1614 default:
1615 if (options & MagicPacket)
1616 wolopts |= WAKE_MAGIC;
1617 break;
1618 }
61a4dcc2 1619
1ef7286e 1620 options = RTL_R8(tp, Config5);
61a4dcc2 1621 if (options & UWF)
e1759441 1622 wolopts |= WAKE_UCAST;
61a4dcc2 1623 if (options & BWF)
e1759441 1624 wolopts |= WAKE_BCAST;
61a4dcc2 1625 if (options & MWF)
e1759441 1626 wolopts |= WAKE_MCAST;
61a4dcc2 1627
e1759441 1628 return wolopts;
61a4dcc2 1629}
433f9d0d 1630#endif
61a4dcc2 1631
e1759441 1632static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1633{
1634 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1635
da78dbff 1636 rtl_lock_work(tp);
e1759441 1637 wol->supported = WAKE_ANY;
433f9d0d 1638 wol->wolopts = tp->saved_wolopts;
da78dbff 1639 rtl_unlock_work(tp);
e1759441
RW		 1640}
1641
1642static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1643{
6e1d0b89 1644 unsigned int i, tmp;
350f7596 1645 static const struct {
61a4dcc2
FR		 1646 u32 opt;
1647 u16 reg;
1648 u8 mask;
1649 } cfg[] = {
61a4dcc2 1650 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1651 { WAKE_UCAST, Config5, UWF },
1652 { WAKE_BCAST, Config5, BWF },
1653 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1654 { WAKE_ANY, Config5, LanWake },
1655 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1656 };
851e6022 1657 u8 options;
61a4dcc2 1658
1ef7286e 1659 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
61a4dcc2 1660
6e1d0b89 1661 switch (tp->mac_version) {
2a71883c
HK		 1662 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1663 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1664 tmp = ARRAY_SIZE(cfg) - 1;
1665 if (wolopts & WAKE_MAGIC)
706123d0 1666 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1667 0x0dc,
1668 ERIAR_MASK_0100,
1669 MagicPacket_v2,
1670 0x0000,
1671 ERIAR_EXGMAC);
1672 else
706123d0 1673 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1674 0x0dc,
1675 ERIAR_MASK_0100,
1676 0x0000,
1677 MagicPacket_v2,
1678 ERIAR_EXGMAC);
1679 break;
1680 default:
1681 tmp = ARRAY_SIZE(cfg);
1682 break;
1683 }
1684
1685 for (i = 0; i < tmp; i++) {
1ef7286e 1686 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
e1759441 1687 if (wolopts & cfg[i].opt)
61a4dcc2 1688 options |= cfg[i].mask;
1ef7286e 1689 RTL_W8(tp, cfg[i].reg, options);
61a4dcc2
FR		 1690 }
1691
851e6022
FR		 1692 switch (tp->mac_version) {
1693 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1ef7286e 1694 options = RTL_R8(tp, Config1) & ~PMEnable;
851e6022
FR		 1695 if (wolopts)
1696 options |= PMEnable;
1ef7286e 1697 RTL_W8(tp, Config1, options);
851e6022
FR		 1698 break;
1699 default:
1ef7286e 1700 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
d387b427
FR		 1701 if (wolopts)
1702 options |= PME_SIGNAL;
1ef7286e 1703 RTL_W8(tp, Config2, options);
851e6022
FR		 1704 break;
1705 }
1706
1ef7286e 1707 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
e1759441
RW		 1708}
1709
1710static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1711{
1712 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1713 struct device *d = tp_to_dev(tp);
5fa80a32 1714
2f533f6b
HK		 1715 if (wol->wolopts & ~WAKE_ANY)
1716 return -EINVAL;
1717
5fa80a32 1718 pm_runtime_get_noresume(d);
e1759441 1719
da78dbff 1720 rtl_lock_work(tp);
61a4dcc2 1721
2f533f6b 1722 tp->saved_wolopts = wol->wolopts;
433f9d0d 1723
5fa80a32 1724 if (pm_runtime_active(d))
433f9d0d 1725 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff
FR		 1726
1727 rtl_unlock_work(tp);
61a4dcc2 1728
433f9d0d 1729 device_set_wakeup_enable(d, tp->saved_wolopts);
ea80907f 1730
5fa80a32
CHL		 1731 pm_runtime_put_noidle(d);
1732
61a4dcc2
FR		 1733 return 0;
1734}
1735
31bd204f
FR		 1736static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1737{
85bffe6c 1738 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1739}
1740
1da177e4
LT		 1741static void rtl8169_get_drvinfo(struct net_device *dev,
1742 struct ethtool_drvinfo *info)
1743{
1744 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1745 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1746
68aad78c
RJ		 1747 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1748 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1749 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1750 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1751 if (!IS_ERR_OR_NULL(rtl_fw))
1752 strlcpy(info->fw_version, rtl_fw->version,
1753 sizeof(info->fw_version));
1da177e4
LT		 1754}
1755
1756static int rtl8169_get_regs_len(struct net_device *dev)
1757{
1758 return R8169_REGS_SIZE;
1759}
1760
1761static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1762 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1763{
1764 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1765 int ret = 0;
1766 u32 reg;
1767
1ef7286e 1768 reg = RTL_R32(tp, TBICSR);
1da177e4
LT		 1769 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1770 (duplex == DUPLEX_FULL)) {
1ef7286e 1771 RTL_W32(tp, TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1da177e4 1772 } else if (autoneg == AUTONEG_ENABLE)
1ef7286e 1773 RTL_W32(tp, TBICSR, reg | TBINwEnable | TBINwRestart);
1da177e4 1774 else {
bf82c189
JP		 1775 netif_warn(tp, link, dev,
1776 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1777 ret = -EOPNOTSUPP;
1778 }
1779
1780 return ret;
1781}
1782
1783static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1784 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1785{
1786 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1787 int giga_ctrl, bmcr;
54405cde 1788 int rc = -EINVAL;
1da177e4 1789
716b50a3 1790 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1791
1792 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1793 int auto_nego;
1794
4da19633 1795 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1796 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1797 ADVERTISE_100HALF | ADVERTISE_100FULL);
1798
1799 if (adv & ADVERTISED_10baseT_Half)
1800 auto_nego |= ADVERTISE_10HALF;
1801 if (adv & ADVERTISED_10baseT_Full)
1802 auto_nego |= ADVERTISE_10FULL;
1803 if (adv & ADVERTISED_100baseT_Half)
1804 auto_nego |= ADVERTISE_100HALF;
1805 if (adv & ADVERTISED_100baseT_Full)
1806 auto_nego |= ADVERTISE_100FULL;
1807
3577aa1b 1808 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1809
4da19633 1810 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1811 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1812
3577aa1b 1813 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1814 if (tp->mii.supports_gmii) {
54405cde
ON		 1815 if (adv & ADVERTISED_1000baseT_Half)
1816 giga_ctrl |= ADVERTISE_1000HALF;
1817 if (adv & ADVERTISED_1000baseT_Full)
1818 giga_ctrl |= ADVERTISE_1000FULL;
1819 } else if (adv & (ADVERTISED_1000baseT_Half |
1820 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1821 netif_info(tp, link, dev,
1822 "PHY does not support 1000Mbps\n");
54405cde 1823 goto out;
bcf0bf90 1824 }
1da177e4 1825
3577aa1b 1826 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1827
4da19633 1828 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1829 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1830 } else {
3577aa1b 1831 if (speed == SPEED_10)
1832 bmcr = 0;
1833 else if (speed == SPEED_100)
1834 bmcr = BMCR_SPEED100;
1835 else
54405cde 1836 goto out;
3577aa1b 1837
1838 if (duplex == DUPLEX_FULL)
1839 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1840 }
1841
4da19633 1842 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1843
cecb5fd7
FR		 1844 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1845 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1846 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1847 rtl_writephy(tp, 0x17, 0x2138);
1848 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1849 } else {
4da19633 1850 rtl_writephy(tp, 0x17, 0x2108);
1851 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1852 }
1853 }
1854
54405cde
ON		 1855 rc = 0;
1856out:
1857 return rc;
1da177e4
LT		 1858}
1859
1860static int rtl8169_set_speed(struct net_device *dev,
54405cde 1861 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1862{
1863 struct rtl8169_private *tp = netdev_priv(dev);
1864 int ret;
1865
54405cde 1866 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1867 if (ret < 0)
1868 goto out;
1da177e4 1869
4876cc1e 1870 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
c4556975
CHL		 1871 (advertising & ADVERTISED_1000baseT_Full) &&
1872 !pci_is_pcie(tp->pci_dev)) {
1da177e4 1873 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1874 }
1875out:
1da177e4
LT		 1876 return ret;
1877}
1878
c8f44aff
MM		 1879static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1880 netdev_features_t features)
1da177e4 1881{
d58d46b5
FR		 1882 struct rtl8169_private *tp = netdev_priv(dev);
1883
2b7b4318 1884 if (dev->mtu > TD_MSS_MAX)
350fb32a 1885 features &= ~NETIF_F_ALL_TSO;
1da177e4 1886
d58d46b5 1887 if (dev->mtu > JUMBO_1K &&
6ed0e08f 1888 tp->mac_version > RTL_GIGA_MAC_VER_06)
d58d46b5
FR		 1889 features &= ~NETIF_F_IP_CSUM;
1890
350fb32a 1891 return features;
1da177e4
LT		 1892}
1893
a3984578
HK		 1894static int rtl8169_set_features(struct net_device *dev,
1895 netdev_features_t features)
1da177e4
LT		 1896{
1897 struct rtl8169_private *tp = netdev_priv(dev);
929a031d 1898 u32 rx_config;
1da177e4 1899
a3984578
HK		 1900 rtl_lock_work(tp);
1901
1ef7286e 1902 rx_config = RTL_R32(tp, RxConfig);
929a031d 1903 if (features & NETIF_F_RXALL)
1904 rx_config |= (AcceptErr | AcceptRunt);
1905 else
1906 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 1907
1ef7286e 1908 RTL_W32(tp, RxConfig, rx_config);
350fb32a 1909
929a031d 1910 if (features & NETIF_F_RXCSUM)
1911 tp->cp_cmd |= RxChkSum;
1912 else
1913 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1914
929a031d 1915 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1916 tp->cp_cmd |= RxVlan;
1917 else
1918 tp->cp_cmd &= ~RxVlan;
1919
1ef7286e
AS		 1920 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1921 RTL_R16(tp, CPlusCmd);
1da177e4 1922
da78dbff 1923 rtl_unlock_work(tp);
1da177e4
LT		 1924
1925 return 0;
1926}
1927
810f4893 1928static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1929{
df8a39de
JP		 1930 return (skb_vlan_tag_present(skb)) ?
1931 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 1932}
1933
7a8fc77b 1934static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1935{
1936 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1937
7a8fc77b 1938 if (opts2 & RxVlanTag)
86a9bad3 1939 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1940}
1941
6fa1ba61
PR		 1942static int rtl8169_get_link_ksettings_tbi(struct net_device *dev,
1943 struct ethtool_link_ksettings *cmd)
1da177e4
LT		 1944{
1945 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1946 u32 status;
6fa1ba61 1947 u32 supported, advertising;
1da177e4 1948
6fa1ba61 1949 supported =
1da177e4 1950 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
6fa1ba61 1951 cmd->base.port = PORT_FIBRE;
1da177e4 1952
1ef7286e 1953 status = RTL_R32(tp, TBICSR);
6fa1ba61
PR		 1954 advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1955 cmd->base.autoneg = !!(status & TBINwEnable);
1da177e4 1956
6fa1ba61
PR		 1957 cmd->base.speed = SPEED_1000;
1958 cmd->base.duplex = DUPLEX_FULL; /* Always set */
1959
1960 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1961 supported);
1962 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1963 advertising);
ccdffb9a
FR		 1964
1965 return 0;
1da177e4
LT		 1966}
1967
6fa1ba61
PR		 1968static int rtl8169_get_link_ksettings_xmii(struct net_device *dev,
1969 struct ethtool_link_ksettings *cmd)
1da177e4
LT		 1970{
1971 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1972
82c01a84 1973 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
1974
1975 return 0;
1da177e4
LT		 1976}
1977
6fa1ba61
PR		 1978static int rtl8169_get_link_ksettings(struct net_device *dev,
1979 struct ethtool_link_ksettings *cmd)
1da177e4
LT		 1980{
1981 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1982 int rc;
1da177e4 1983
da78dbff 1984 rtl_lock_work(tp);
6fa1ba61 1985 rc = tp->get_link_ksettings(dev, cmd);
da78dbff 1986 rtl_unlock_work(tp);
1da177e4 1987
ccdffb9a 1988 return rc;
1da177e4
LT		 1989}
1990
9e77d7a5
TJ		 1991static int rtl8169_set_link_ksettings(struct net_device *dev,
1992 const struct ethtool_link_ksettings *cmd)
1993{
1994 struct rtl8169_private *tp = netdev_priv(dev);
1995 int rc;
1996 u32 advertising;
1997
1998 if (!ethtool_convert_link_mode_to_legacy_u32(&advertising,
1999 cmd->link_modes.advertising))
2000 return -EINVAL;
2001
2002 del_timer_sync(&tp->timer);
2003
2004 rtl_lock_work(tp);
2005 rc = rtl8169_set_speed(dev, cmd->base.autoneg, cmd->base.speed,
2006 cmd->base.duplex, advertising);
2007 rtl_unlock_work(tp);
2008
2009 return rc;
2010}
2011
1da177e4
LT		 2012static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2013 void *p)
2014{
5b0384f4 2015 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 2016 u32 __iomem *data = tp->mmio_addr;
2017 u32 *dw = p;
2018 int i;
1da177e4 2019
da78dbff 2020 rtl_lock_work(tp);
15edae91
PW		 2021 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2022 memcpy_fromio(dw++, data++, 4);
da78dbff 2023 rtl_unlock_work(tp);
1da177e4
LT		 2024}
2025
b57b7e5a
SH		 2026static u32 rtl8169_get_msglevel(struct net_device *dev)
2027{
2028 struct rtl8169_private *tp = netdev_priv(dev);
2029
2030 return tp->msg_enable;
2031}
2032
2033static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2034{
2035 struct rtl8169_private *tp = netdev_priv(dev);
2036
2037 tp->msg_enable = value;
2038}
2039
d4a3a0fc
SH		 2040static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2041 "tx_packets",
2042 "rx_packets",
2043 "tx_errors",
2044 "rx_errors",
2045 "rx_missed",
2046 "align_errors",
2047 "tx_single_collisions",
2048 "tx_multi_collisions",
2049 "unicast",
2050 "broadcast",
2051 "multicast",
2052 "tx_aborted",
2053 "tx_underrun",
2054};
2055
b9f2c044 2056static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 2057{
b9f2c044
JG		 2058 switch (sset) {
2059 case ETH_SS_STATS:
2060 return ARRAY_SIZE(rtl8169_gstrings);
2061 default:
2062 return -EOPNOTSUPP;
2063 }
d4a3a0fc
SH		 2064}
2065
42020320 2066DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 2067{
1ef7286e 2068 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 2069}
2070
e71c9ce2 2071static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
6e85d5ad 2072{
42020320
CV		 2073 dma_addr_t paddr = tp->counters_phys_addr;
2074 u32 cmd;
6e85d5ad 2075
1ef7286e
AS		 2076 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
2077 RTL_R32(tp, CounterAddrHigh);
42020320 2078 cmd = (u64)paddr & DMA_BIT_MASK(32);
1ef7286e
AS		 2079 RTL_W32(tp, CounterAddrLow, cmd);
2080 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
6e85d5ad 2081
a78e9366 2082 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 2083}
2084
e71c9ce2 2085static bool rtl8169_reset_counters(struct rtl8169_private *tp)
6e85d5ad 2086{
6e85d5ad
CV		 2087 /*
2088 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2089 * tally counters.
2090 */
2091 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2092 return true;
2093
e71c9ce2 2094 return rtl8169_do_counters(tp, CounterReset);
ffc46952
FR		 2095}
2096
e71c9ce2 2097static bool rtl8169_update_counters(struct rtl8169_private *tp)
d4a3a0fc 2098{
355423d0
IV		 2099 /*
2100 * Some chips are unable to dump tally counters when the receiver
2101 * is disabled.
2102 */
1ef7286e 2103 if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
6e85d5ad 2104 return true;
d4a3a0fc 2105
e71c9ce2 2106 return rtl8169_do_counters(tp, CounterDump);
6e85d5ad
CV		 2107}
2108
e71c9ce2 2109static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
6e85d5ad 2110{
42020320 2111 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 2112 bool ret = false;
2113
2114 /*
2115 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2116 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2117 * reset by a power cycle, while the counter values collected by the
2118 * driver are reset at every driver unload/load cycle.
2119 *
2120 * To make sure the HW values returned by @get_stats64 match the SW
2121 * values, we collect the initial values at first open(*) and use them
2122 * as offsets to normalize the values returned by @get_stats64.
2123 *
2124 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2125 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2126 * set at open time by rtl_hw_start.
2127 */
2128
2129 if (tp->tc_offset.inited)
2130 return true;
2131
2132 /* If both, reset and update fail, propagate to caller. */
e71c9ce2 2133 if (rtl8169_reset_counters(tp))
6e85d5ad
CV		 2134 ret = true;
2135
e71c9ce2 2136 if (rtl8169_update_counters(tp))
6e85d5ad
CV		 2137 ret = true;
2138
42020320
CV		 2139 tp->tc_offset.tx_errors = counters->tx_errors;
2140 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2141 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 2142 tp->tc_offset.inited = true;
2143
2144 return ret;
d4a3a0fc
SH		 2145}
2146
355423d0
IV		 2147static void rtl8169_get_ethtool_stats(struct net_device *dev,
2148 struct ethtool_stats *stats, u64 *data)
2149{
2150 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 2151 struct device *d = tp_to_dev(tp);
42020320 2152 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 2153
2154 ASSERT_RTNL();
2155
e0636236
CHL		 2156 pm_runtime_get_noresume(d);
2157
2158 if (pm_runtime_active(d))
e71c9ce2 2159 rtl8169_update_counters(tp);
e0636236
CHL		 2160
2161 pm_runtime_put_noidle(d);
355423d0 2162
42020320
CV		 2163 data[0] = le64_to_cpu(counters->tx_packets);
2164 data[1] = le64_to_cpu(counters->rx_packets);
2165 data[2] = le64_to_cpu(counters->tx_errors);
2166 data[3] = le32_to_cpu(counters->rx_errors);
2167 data[4] = le16_to_cpu(counters->rx_missed);
2168 data[5] = le16_to_cpu(counters->align_errors);
2169 data[6] = le32_to_cpu(counters->tx_one_collision);
2170 data[7] = le32_to_cpu(counters->tx_multi_collision);
2171 data[8] = le64_to_cpu(counters->rx_unicast);
2172 data[9] = le64_to_cpu(counters->rx_broadcast);
2173 data[10] = le32_to_cpu(counters->rx_multicast);
2174 data[11] = le16_to_cpu(counters->tx_aborted);
2175 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 2176}
2177
d4a3a0fc
SH		 2178static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2179{
2180 switch(stringset) {
2181 case ETH_SS_STATS:
2182 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2183 break;
2184 }
2185}
2186
f0903ea3
FF		 2187static int rtl8169_nway_reset(struct net_device *dev)
2188{
2189 struct rtl8169_private *tp = netdev_priv(dev);
2190
2191 return mii_nway_restart(&tp->mii);
2192}
2193
50970831
FR		 2194/*
2195 * Interrupt coalescing
2196 *
2197 * > 1 - the availability of the IntrMitigate (0xe2) register through the
2198 * > 8169, 8168 and 810x line of chipsets
2199 *
2200 * 8169, 8168, and 8136(810x) serial chipsets support it.
2201 *
2202 * > 2 - the Tx timer unit at gigabit speed
2203 *
2204 * The unit of the timer depends on both the speed and the setting of CPlusCmd
2205 * (0xe0) bit 1 and bit 0.
2206 *
2207 * For 8169
2208 * bit[1:0] \ speed 1000M 100M 10M
2209 * 0 0 320ns 2.56us 40.96us
2210 * 0 1 2.56us 20.48us 327.7us
2211 * 1 0 5.12us 40.96us 655.4us
2212 * 1 1 10.24us 81.92us 1.31ms
2213 *
2214 * For the other
2215 * bit[1:0] \ speed 1000M 100M 10M
2216 * 0 0 5us 2.56us 40.96us
2217 * 0 1 40us 20.48us 327.7us
2218 * 1 0 80us 40.96us 655.4us
2219 * 1 1 160us 81.92us 1.31ms
2220 */
2221
2222/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
2223struct rtl_coalesce_scale {
2224 /* Rx / Tx */
2225 u32 nsecs[2];
2226};
2227
2228/* rx/tx scale factors for all CPlusCmd[0:1] cases */
2229struct rtl_coalesce_info {
2230 u32 speed;
2231 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
2232};
2233
2234/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
2235#define rxtx_x1822(r, t) { \
2236 {{(r), (t)}}, \
2237 {{(r)*8, (t)*8}}, \
2238 {{(r)*8*2, (t)*8*2}}, \
2239 {{(r)*8*2*2, (t)*8*2*2}}, \
2240}
2241static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
2242 /* speed delays: rx00 tx00 */
2243 { SPEED_10, rxtx_x1822(40960, 40960) },
2244 { SPEED_100, rxtx_x1822( 2560, 2560) },
2245 { SPEED_1000, rxtx_x1822( 320, 320) },
2246 { 0 },
2247};
2248
2249static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
2250 /* speed delays: rx00 tx00 */
2251 { SPEED_10, rxtx_x1822(40960, 40960) },
2252 { SPEED_100, rxtx_x1822( 2560, 2560) },
2253 { SPEED_1000, rxtx_x1822( 5000, 5000) },
2254 { 0 },
2255};
2256#undef rxtx_x1822
2257
2258/* get rx/tx scale vector corresponding to current speed */
2259static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
2260{
2261 struct rtl8169_private *tp = netdev_priv(dev);
2262 struct ethtool_link_ksettings ecmd;
2263 const struct rtl_coalesce_info *ci;
2264 int rc;
2265
2266 rc = rtl8169_get_link_ksettings(dev, &ecmd);
2267 if (rc < 0)
2268 return ERR_PTR(rc);
2269
2270 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
2271 if (ecmd.base.speed == ci->speed) {
2272 return ci;
2273 }
2274 }
2275
2276 return ERR_PTR(-ELNRNG);
2277}
2278
2279static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2280{
2281 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 2282 const struct rtl_coalesce_info *ci;
2283 const struct rtl_coalesce_scale *scale;
2284 struct {
2285 u32 *max_frames;
2286 u32 *usecs;
2287 } coal_settings [] = {
2288 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
2289 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
2290 }, *p = coal_settings;
2291 int i;
2292 u16 w;
2293
2294 memset(ec, 0, sizeof(*ec));
2295
2296 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2297 ci = rtl_coalesce_info(dev);
2298 if (IS_ERR(ci))
2299 return PTR_ERR(ci);
2300
0ae0974e 2301 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
50970831
FR		 2302
2303 /* read IntrMitigate and adjust according to scale */
1ef7286e 2304 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
50970831
FR		 2305 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2306 w >>= RTL_COALESCE_SHIFT;
2307 *p->usecs = w & RTL_COALESCE_MASK;
2308 }
2309
2310 for (i = 0; i < 2; i++) {
2311 p = coal_settings + i;
2312 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2313
2314 /*
2315 * ethtool_coalesce says it is illegal to set both usecs and
2316 * max_frames to 0.
2317 */
2318 if (!*p->usecs && !*p->max_frames)
2319 *p->max_frames = 1;
2320 }
2321
2322 return 0;
2323}
2324
2325/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2326static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2327 struct net_device *dev, u32 nsec, u16 *cp01)
2328{
2329 const struct rtl_coalesce_info *ci;
2330 u16 i;
2331
2332 ci = rtl_coalesce_info(dev);
2333 if (IS_ERR(ci))
2334 return ERR_CAST(ci);
2335
2336 for (i = 0; i < 4; i++) {
2337 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2338 ci->scalev[i].nsecs[1]);
2339 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2340 *cp01 = i;
2341 return &ci->scalev[i];
2342 }
2343 }
2344
2345 return ERR_PTR(-EINVAL);
2346}
2347
2348static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2349{
2350 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 2351 const struct rtl_coalesce_scale *scale;
2352 struct {
2353 u32 frames;
2354 u32 usecs;
2355 } coal_settings [] = {
2356 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2357 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2358 }, *p = coal_settings;
2359 u16 w = 0, cp01;
2360 int i;
2361
2362 scale = rtl_coalesce_choose_scale(dev,
2363 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2364 if (IS_ERR(scale))
2365 return PTR_ERR(scale);
2366
2367 for (i = 0; i < 2; i++, p++) {
2368 u32 units;
2369
2370 /*
2371 * accept max_frames=1 we returned in rtl_get_coalesce.
2372 * accept it not only when usecs=0 because of e.g. the following scenario:
2373 *
2374 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2375 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2376 * - then user does `ethtool -C eth0 rx-usecs 100`
2377 *
2378 * since ethtool sends to kernel whole ethtool_coalesce
2379 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2380 * we'll reject it below in `frames % 4 != 0`.
2381 */
2382 if (p->frames == 1) {
2383 p->frames = 0;
2384 }
2385
2386 units = p->usecs * 1000 / scale->nsecs[i];
2387 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2388 return -EINVAL;
2389
2390 w <<= RTL_COALESCE_SHIFT;
2391 w |= units;
2392 w <<= RTL_COALESCE_SHIFT;
2393 w |= p->frames >> 2;
2394 }
2395
2396 rtl_lock_work(tp);
2397
1ef7286e 2398 RTL_W16(tp, IntrMitigate, swab16(w));
50970831 2399
9a3c81fa 2400 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1ef7286e
AS		 2401 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2402 RTL_R16(tp, CPlusCmd);
50970831
FR		 2403
2404 rtl_unlock_work(tp);
2405
2406 return 0;
2407}
2408
7282d491 2409static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2410 .get_drvinfo = rtl8169_get_drvinfo,
2411 .get_regs_len = rtl8169_get_regs_len,
2412 .get_link = ethtool_op_get_link,
50970831
FR		 2413 .get_coalesce = rtl_get_coalesce,
2414 .set_coalesce = rtl_set_coalesce,
b57b7e5a
SH		 2415 .get_msglevel = rtl8169_get_msglevel,
2416 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2417 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2418 .get_wol = rtl8169_get_wol,
2419 .set_wol = rtl8169_set_wol,
d4a3a0fc 2420 .get_strings = rtl8169_get_strings,
b9f2c044 2421 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2422 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2423 .get_ts_info = ethtool_op_get_ts_info,
f0903ea3 2424 .nway_reset = rtl8169_nway_reset,
6fa1ba61 2425 .get_link_ksettings = rtl8169_get_link_ksettings,
9e77d7a5 2426 .set_link_ksettings = rtl8169_set_link_ksettings,
1da177e4
LT		 2427};
2428
07d3f51f 2429static void rtl8169_get_mac_version(struct rtl8169_private *tp,
22148df0 2430 u8 default_version)
1da177e4 2431{
0e485150
FR		 2432 /*
2433 * The driver currently handles the 8168Bf and the 8168Be identically
2434 * but they can be identified more specifically through the test below
2435 * if needed:
2436 *
1ef7286e 2437 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2438 *
2439 * Same thing for the 8101Eb and the 8101Ec:
2440 *
1ef7286e 2441 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2442 */
3744100e 2443 static const struct rtl_mac_info {
1da177e4 2444 u32 mask;
e3cf0cc0 2445 u32 val;
1da177e4
LT		 2446 int mac_version;
2447 } mac_info[] = {
935e2218
CHL		 2448 /* 8168EP family. */
2449 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2450 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2451 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2452
6e1d0b89
CHL		 2453 /* 8168H family. */
2454 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2455 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2456
c558386b 2457 /* 8168G family. */
45dd95c4 2458 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2459 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2460 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2461 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2462
c2218925 2463 /* 8168F family. */
b3d7b2f2 2464 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2465 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2466 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2467
01dc7fec 2468 /* 8168E family. */
70090424 2469 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2470 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2471 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2472
5b538df9 2473 /* 8168D family. */
daf9df6d 2474 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2475 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2476
e6de30d6 2477 /* 8168DP family. */
2478 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2479 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2480 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2481
ef808d50 2482 /* 8168C family. */
ef3386f0 2483 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2484 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2485 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2486 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2487 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2488 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
ef808d50 2489 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2490
2491 /* 8168B family. */
2492 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
e3cf0cc0
FR		 2493 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2494 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2495
2496 /* 8101 family. */
5598bfe5 2497 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2498 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
5a5e4443
HW		 2499 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2500 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2501 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2502 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2503 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2504 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2505 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2506 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2507 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2508 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2509 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2510 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2511 /* FIXME: where did these entries come from ? -- FR */
2512 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2513 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2514
2515 /* 8110 family. */
2516 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2517 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2518 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2519 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2520 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2521 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2522
f21b75e9
JD		 2523 /* Catch-all */
2524 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2525 };
2526 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2527 u32 reg;
2528
1ef7286e 2529 reg = RTL_R32(tp, TxConfig);
e3cf0cc0 2530 while ((reg & p->mask) != p->val)
1da177e4
LT		 2531 p++;
2532 tp->mac_version = p->mac_version;
5d320a20
FR		 2533
2534 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
22148df0
HK		 2535 dev_notice(tp_to_dev(tp),
2536 "unknown MAC, using family default\n");
5d320a20 2537 tp->mac_version = default_version;
58152cd4 2538 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2539 tp->mac_version = tp->mii.supports_gmii ?
2540 RTL_GIGA_MAC_VER_42 :
2541 RTL_GIGA_MAC_VER_43;
6e1d0b89
CHL		 2542 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2543 tp->mac_version = tp->mii.supports_gmii ?
2544 RTL_GIGA_MAC_VER_45 :
2545 RTL_GIGA_MAC_VER_47;
2546 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2547 tp->mac_version = tp->mii.supports_gmii ?
2548 RTL_GIGA_MAC_VER_46 :
2549 RTL_GIGA_MAC_VER_48;
5d320a20 2550 }
1da177e4
LT		 2551}
2552
2553static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2554{
bcf0bf90 2555 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2556}
2557
867763c1
FR		 2558struct phy_reg {
2559 u16 reg;
2560 u16 val;
2561};
2562
4da19633 2563static void rtl_writephy_batch(struct rtl8169_private *tp,
2564 const struct phy_reg *regs, int len)
867763c1
FR		 2565{
2566 while (len-- > 0) {
4da19633 2567 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2568 regs++;
2569 }
2570}
2571
bca03d5f 2572#define PHY_READ 0x00000000
2573#define PHY_DATA_OR 0x10000000
2574#define PHY_DATA_AND 0x20000000
2575#define PHY_BJMPN 0x30000000
eee3786f 2576#define PHY_MDIO_CHG 0x40000000
bca03d5f 2577#define PHY_CLEAR_READCOUNT 0x70000000
2578#define PHY_WRITE 0x80000000
2579#define PHY_READCOUNT_EQ_SKIP 0x90000000
2580#define PHY_COMP_EQ_SKIPN 0xa0000000
2581#define PHY_COMP_NEQ_SKIPN 0xb0000000
2582#define PHY_WRITE_PREVIOUS 0xc0000000
2583#define PHY_SKIPN 0xd0000000
2584#define PHY_DELAY_MS 0xe0000000
bca03d5f 2585
960aee6c
HW		 2586struct fw_info {
2587 u32 magic;
2588 char version[RTL_VER_SIZE];
2589 __le32 fw_start;
2590 __le32 fw_len;
2591 u8 chksum;
2592} __packed;
2593
1c361efb
FR		 2594#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2595
2596static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2597{
b6ffd97f 2598 const struct firmware *fw = rtl_fw->fw;
960aee6c 2599 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2600 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2601 char *version = rtl_fw->version;
2602 bool rc = false;
2603
2604 if (fw->size < FW_OPCODE_SIZE)
2605 goto out;
960aee6c
HW		 2606
2607 if (!fw_info->magic) {
2608 size_t i, size, start;
2609 u8 checksum = 0;
2610
2611 if (fw->size < sizeof(*fw_info))
2612 goto out;
2613
2614 for (i = 0; i < fw->size; i++)
2615 checksum += fw->data[i];
2616 if (checksum != 0)
2617 goto out;
2618
2619 start = le32_to_cpu(fw_info->fw_start);
2620 if (start > fw->size)
2621 goto out;
2622
2623 size = le32_to_cpu(fw_info->fw_len);
2624 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2625 goto out;
2626
2627 memcpy(version, fw_info->version, RTL_VER_SIZE);
2628
2629 pa->code = (__le32 *)(fw->data + start);
2630 pa->size = size;
2631 } else {
1c361efb
FR		 2632 if (fw->size % FW_OPCODE_SIZE)
2633 goto out;
2634
2635 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2636
2637 pa->code = (__le32 *)fw->data;
2638 pa->size = fw->size / FW_OPCODE_SIZE;
2639 }
2640 version[RTL_VER_SIZE - 1] = 0;
2641
2642 rc = true;
2643out:
2644 return rc;
2645}
2646
fd112f2e
FR		 2647static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2648 struct rtl_fw_phy_action *pa)
1c361efb 2649{
fd112f2e 2650 bool rc = false;
1c361efb 2651 size_t index;
bca03d5f 2652
1c361efb
FR		 2653 for (index = 0; index < pa->size; index++) {
2654 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2655 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2656
42b82dc1 2657 switch(action & 0xf0000000) {
2658 case PHY_READ:
2659 case PHY_DATA_OR:
2660 case PHY_DATA_AND:
eee3786f 2661 case PHY_MDIO_CHG:
42b82dc1 2662 case PHY_CLEAR_READCOUNT:
2663 case PHY_WRITE:
2664 case PHY_WRITE_PREVIOUS:
2665 case PHY_DELAY_MS:
2666 break;
2667
2668 case PHY_BJMPN:
2669 if (regno > index) {
fd112f2e 2670 netif_err(tp, ifup, tp->dev,
cecb5fd7 2671 "Out of range of firmware\n");
fd112f2e 2672 goto out;
42b82dc1 2673 }
2674 break;
2675 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2676 if (index + 2 >= pa->size) {
fd112f2e 2677 netif_err(tp, ifup, tp->dev,
cecb5fd7 2678 "Out of range of firmware\n");
fd112f2e 2679 goto out;
42b82dc1 2680 }
2681 break;
2682 case PHY_COMP_EQ_SKIPN:
2683 case PHY_COMP_NEQ_SKIPN:
2684 case PHY_SKIPN:
1c361efb 2685 if (index + 1 + regno >= pa->size) {
fd112f2e 2686 netif_err(tp, ifup, tp->dev,
cecb5fd7 2687 "Out of range of firmware\n");
fd112f2e 2688 goto out;
42b82dc1 2689 }
bca03d5f 2690 break;
2691
42b82dc1 2692 default:
fd112f2e 2693 netif_err(tp, ifup, tp->dev,
42b82dc1 2694 "Invalid action 0x%08x\n", action);
fd112f2e 2695 goto out;
bca03d5f 2696 }
2697 }
fd112f2e
FR		 2698 rc = true;
2699out:
2700 return rc;
2701}
bca03d5f 2702
fd112f2e
FR		 2703static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2704{
2705 struct net_device *dev = tp->dev;
2706 int rc = -EINVAL;
2707
2708 if (!rtl_fw_format_ok(tp, rtl_fw)) {
5c2d2b14 2709 netif_err(tp, ifup, dev, "invalid firmware\n");
fd112f2e
FR		 2710 goto out;
2711 }
2712
2713 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2714 rc = 0;
2715out:
2716 return rc;
2717}
2718
2719static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2720{
2721 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2722 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2723 u32 predata, count;
2724 size_t index;
2725
2726 predata = count = 0;
eee3786f 2727 org.write = ops->write;
2728 org.read = ops->read;
42b82dc1 2729
1c361efb
FR		 2730 for (index = 0; index < pa->size; ) {
2731 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2732 u32 data = action & 0x0000ffff;
42b82dc1 2733 u32 regno = (action & 0x0fff0000) >> 16;
2734
2735 if (!action)
2736 break;
bca03d5f 2737
2738 switch(action & 0xf0000000) {
42b82dc1 2739 case PHY_READ:
2740 predata = rtl_readphy(tp, regno);
2741 count++;
2742 index++;
2743 break;
2744 case PHY_DATA_OR:
2745 predata |= data;
2746 index++;
2747 break;
2748 case PHY_DATA_AND:
2749 predata &= data;
2750 index++;
2751 break;
2752 case PHY_BJMPN:
2753 index -= regno;
2754 break;
eee3786f 2755 case PHY_MDIO_CHG:
2756 if (data == 0) {
2757 ops->write = org.write;
2758 ops->read = org.read;
2759 } else if (data == 1) {
2760 ops->write = mac_mcu_write;
2761 ops->read = mac_mcu_read;
2762 }
2763
42b82dc1 2764 index++;
2765 break;
2766 case PHY_CLEAR_READCOUNT:
2767 count = 0;
2768 index++;
2769 break;
bca03d5f 2770 case PHY_WRITE:
42b82dc1 2771 rtl_writephy(tp, regno, data);
2772 index++;
2773 break;
2774 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2775 index += (count == data) ? 2 : 1;
bca03d5f 2776 break;
42b82dc1 2777 case PHY_COMP_EQ_SKIPN:
2778 if (predata == data)
2779 index += regno;
2780 index++;
2781 break;
2782 case PHY_COMP_NEQ_SKIPN:
2783 if (predata != data)
2784 index += regno;
2785 index++;
2786 break;
2787 case PHY_WRITE_PREVIOUS:
2788 rtl_writephy(tp, regno, predata);
2789 index++;
2790 break;
2791 case PHY_SKIPN:
2792 index += regno + 1;
2793 break;
2794 case PHY_DELAY_MS:
2795 mdelay(data);
2796 index++;
2797 break;
2798
bca03d5f 2799 default:
2800 BUG();
2801 }
2802 }
eee3786f 2803
2804 ops->write = org.write;
2805 ops->read = org.read;
bca03d5f 2806}
2807
f1e02ed1 2808static void rtl_release_firmware(struct rtl8169_private *tp)
2809{
b6ffd97f
FR		 2810 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2811 release_firmware(tp->rtl_fw->fw);
2812 kfree(tp->rtl_fw);
2813 }
2814 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2815}
2816
953a12cc 2817static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2818{
b6ffd97f 2819 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2820
2821 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2822 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2823 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2824}
2825
2826static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2827{
2828 if (rtl_readphy(tp, reg) != val)
2829 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2830 else
2831 rtl_apply_firmware(tp);
f1e02ed1 2832}
2833
4da19633 2834static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2835{
350f7596 2836 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2837 { 0x1f, 0x0001 },
2838 { 0x06, 0x006e },
2839 { 0x08, 0x0708 },
2840 { 0x15, 0x4000 },
2841 { 0x18, 0x65c7 },
1da177e4 2842
0b9b571d 2843 { 0x1f, 0x0001 },
2844 { 0x03, 0x00a1 },
2845 { 0x02, 0x0008 },
2846 { 0x01, 0x0120 },
2847 { 0x00, 0x1000 },
2848 { 0x04, 0x0800 },
2849 { 0x04, 0x0000 },
1da177e4 2850
0b9b571d 2851 { 0x03, 0xff41 },
2852 { 0x02, 0xdf60 },
2853 { 0x01, 0x0140 },
2854 { 0x00, 0x0077 },
2855 { 0x04, 0x7800 },
2856 { 0x04, 0x7000 },
2857
2858 { 0x03, 0x802f },
2859 { 0x02, 0x4f02 },
2860 { 0x01, 0x0409 },
2861 { 0x00, 0xf0f9 },
2862 { 0x04, 0x9800 },
2863 { 0x04, 0x9000 },
2864
2865 { 0x03, 0xdf01 },
2866 { 0x02, 0xdf20 },
2867 { 0x01, 0xff95 },
2868 { 0x00, 0xba00 },
2869 { 0x04, 0xa800 },
2870 { 0x04, 0xa000 },
2871
2872 { 0x03, 0xff41 },
2873 { 0x02, 0xdf20 },
2874 { 0x01, 0x0140 },
2875 { 0x00, 0x00bb },
2876 { 0x04, 0xb800 },
2877 { 0x04, 0xb000 },
2878
2879 { 0x03, 0xdf41 },
2880 { 0x02, 0xdc60 },
2881 { 0x01, 0x6340 },
2882 { 0x00, 0x007d },
2883 { 0x04, 0xd800 },
2884 { 0x04, 0xd000 },
2885
2886 { 0x03, 0xdf01 },
2887 { 0x02, 0xdf20 },
2888 { 0x01, 0x100a },
2889 { 0x00, 0xa0ff },
2890 { 0x04, 0xf800 },
2891 { 0x04, 0xf000 },
2892
2893 { 0x1f, 0x0000 },
2894 { 0x0b, 0x0000 },
2895 { 0x00, 0x9200 }
2896 };
1da177e4 2897
4da19633 2898 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2899}
2900
4da19633 2901static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2902{
350f7596 2903 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2904 { 0x1f, 0x0002 },
2905 { 0x01, 0x90d0 },
2906 { 0x1f, 0x0000 }
2907 };
2908
4da19633 2909 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2910}
2911
4da19633 2912static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2913{
2914 struct pci_dev *pdev = tp->pci_dev;
2e955856 2915
ccbae55e
SS		 2916 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2917 (pdev->subsystem_device != 0xe000))
2e955856 2918 return;
2919
4da19633 2920 rtl_writephy(tp, 0x1f, 0x0001);
2921 rtl_writephy(tp, 0x10, 0xf01b);
2922 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2923}
2924
4da19633 2925static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2926{
350f7596 2927 static const struct phy_reg phy_reg_init[] = {
2e955856 2928 { 0x1f, 0x0001 },
2929 { 0x04, 0x0000 },
2930 { 0x03, 0x00a1 },
2931 { 0x02, 0x0008 },
2932 { 0x01, 0x0120 },
2933 { 0x00, 0x1000 },
2934 { 0x04, 0x0800 },
2935 { 0x04, 0x9000 },
2936 { 0x03, 0x802f },
2937 { 0x02, 0x4f02 },
2938 { 0x01, 0x0409 },
2939 { 0x00, 0xf099 },
2940 { 0x04, 0x9800 },
2941 { 0x04, 0xa000 },
2942 { 0x03, 0xdf01 },
2943 { 0x02, 0xdf20 },
2944 { 0x01, 0xff95 },
2945 { 0x00, 0xba00 },
2946 { 0x04, 0xa800 },
2947 { 0x04, 0xf000 },
2948 { 0x03, 0xdf01 },
2949 { 0x02, 0xdf20 },
2950 { 0x01, 0x101a },
2951 { 0x00, 0xa0ff },
2952 { 0x04, 0xf800 },
2953 { 0x04, 0x0000 },
2954 { 0x1f, 0x0000 },
2955
2956 { 0x1f, 0x0001 },
2957 { 0x10, 0xf41b },
2958 { 0x14, 0xfb54 },
2959 { 0x18, 0xf5c7 },
2960 { 0x1f, 0x0000 },
2961
2962 { 0x1f, 0x0001 },
2963 { 0x17, 0x0cc0 },
2964 { 0x1f, 0x0000 }
2965 };
2966
4da19633 2967 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2968
4da19633 2969 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2970}
2971
4da19633 2972static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2973{
350f7596 2974 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2975 { 0x1f, 0x0001 },
2976 { 0x04, 0x0000 },
2977 { 0x03, 0x00a1 },
2978 { 0x02, 0x0008 },
2979 { 0x01, 0x0120 },
2980 { 0x00, 0x1000 },
2981 { 0x04, 0x0800 },
2982 { 0x04, 0x9000 },
2983 { 0x03, 0x802f },
2984 { 0x02, 0x4f02 },
2985 { 0x01, 0x0409 },
2986 { 0x00, 0xf099 },
2987 { 0x04, 0x9800 },
2988 { 0x04, 0xa000 },
2989 { 0x03, 0xdf01 },
2990 { 0x02, 0xdf20 },
2991 { 0x01, 0xff95 },
2992 { 0x00, 0xba00 },
2993 { 0x04, 0xa800 },
2994 { 0x04, 0xf000 },
2995 { 0x03, 0xdf01 },
2996 { 0x02, 0xdf20 },
2997 { 0x01, 0x101a },
2998 { 0x00, 0xa0ff },
2999 { 0x04, 0xf800 },
3000 { 0x04, 0x0000 },
3001 { 0x1f, 0x0000 },
3002
3003 { 0x1f, 0x0001 },
3004 { 0x0b, 0x8480 },
3005 { 0x1f, 0x0000 },
3006
3007 { 0x1f, 0x0001 },
3008 { 0x18, 0x67c7 },
3009 { 0x04, 0x2000 },
3010 { 0x03, 0x002f },
3011 { 0x02, 0x4360 },
3012 { 0x01, 0x0109 },
3013 { 0x00, 0x3022 },
3014 { 0x04, 0x2800 },
3015 { 0x1f, 0x0000 },
3016
3017 { 0x1f, 0x0001 },
3018 { 0x17, 0x0cc0 },
3019 { 0x1f, 0x0000 }
3020 };
3021
4da19633 3022 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 3023}
3024
4da19633 3025static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 3026{
350f7596 3027 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 3028 { 0x10, 0xf41b },
3029 { 0x1f, 0x0000 }
3030 };
3031
4da19633 3032 rtl_writephy(tp, 0x1f, 0x0001);
3033 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 3034
4da19633 3035 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 3036}
3037
4da19633 3038static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 3039{
350f7596 3040 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 3041 { 0x1f, 0x0001 },
3042 { 0x10, 0xf41b },
3043 { 0x1f, 0x0000 }
3044 };
3045
4da19633 3046 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 3047}
3048
4da19633 3049static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 3050{
350f7596 3051 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 3052 { 0x1f, 0x0000 },
3053 { 0x1d, 0x0f00 },
3054 { 0x1f, 0x0002 },
3055 { 0x0c, 0x1ec8 },
3056 { 0x1f, 0x0000 }
3057 };
3058
4da19633 3059 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 3060}
3061
4da19633 3062static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 3063{
350f7596 3064 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 3065 { 0x1f, 0x0001 },
3066 { 0x1d, 0x3d98 },
3067 { 0x1f, 0x0000 }
3068 };
3069
4da19633 3070 rtl_writephy(tp, 0x1f, 0x0000);
3071 rtl_patchphy(tp, 0x14, 1 << 5);
3072 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 3073
4da19633 3074 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 3075}
3076
4da19633 3077static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 3078{
350f7596 3079 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 3080 { 0x1f, 0x0001 },
3081 { 0x12, 0x2300 },
867763c1
FR		 3082 { 0x1f, 0x0002 },
3083 { 0x00, 0x88d4 },
3084 { 0x01, 0x82b1 },
3085 { 0x03, 0x7002 },
3086 { 0x08, 0x9e30 },
3087 { 0x09, 0x01f0 },
3088 { 0x0a, 0x5500 },
3089 { 0x0c, 0x00c8 },
3090 { 0x1f, 0x0003 },
3091 { 0x12, 0xc096 },
3092 { 0x16, 0x000a },
f50d4275
FR		 3093 { 0x1f, 0x0000 },
3094 { 0x1f, 0x0000 },
3095 { 0x09, 0x2000 },
3096 { 0x09, 0x0000 }
867763c1
FR		 3097 };
3098
4da19633 3099 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3100
4da19633 3101 rtl_patchphy(tp, 0x14, 1 << 5);
3102 rtl_patchphy(tp, 0x0d, 1 << 5);
3103 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 3104}
3105
4da19633 3106static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 3107{
350f7596 3108 static const struct phy_reg phy_reg_init[] = {
f50d4275 3109 { 0x1f, 0x0001 },
7da97ec9 3110 { 0x12, 0x2300 },
f50d4275
FR		 3111 { 0x03, 0x802f },
3112 { 0x02, 0x4f02 },
3113 { 0x01, 0x0409 },
3114 { 0x00, 0xf099 },
3115 { 0x04, 0x9800 },
3116 { 0x04, 0x9000 },
3117 { 0x1d, 0x3d98 },
7da97ec9
FR		 3118 { 0x1f, 0x0002 },
3119 { 0x0c, 0x7eb8 },
f50d4275
FR		 3120 { 0x06, 0x0761 },
3121 { 0x1f, 0x0003 },
3122 { 0x16, 0x0f0a },
7da97ec9
FR		 3123 { 0x1f, 0x0000 }
3124 };
3125
4da19633 3126 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3127
4da19633 3128 rtl_patchphy(tp, 0x16, 1 << 0);
3129 rtl_patchphy(tp, 0x14, 1 << 5);
3130 rtl_patchphy(tp, 0x0d, 1 << 5);
3131 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 3132}
3133
4da19633 3134static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 3135{
350f7596 3136 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 3137 { 0x1f, 0x0001 },
3138 { 0x12, 0x2300 },
3139 { 0x1d, 0x3d98 },
3140 { 0x1f, 0x0002 },
3141 { 0x0c, 0x7eb8 },
3142 { 0x06, 0x5461 },
3143 { 0x1f, 0x0003 },
3144 { 0x16, 0x0f0a },
3145 { 0x1f, 0x0000 }
3146 };
3147
4da19633 3148 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 3149
4da19633 3150 rtl_patchphy(tp, 0x16, 1 << 0);
3151 rtl_patchphy(tp, 0x14, 1 << 5);
3152 rtl_patchphy(tp, 0x0d, 1 << 5);
3153 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 3154}
3155
4da19633 3156static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 3157{
4da19633 3158 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 3159}
3160
bca03d5f 3161static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 3162{
350f7596 3163 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3164 /* Channel Estimation */
5b538df9 3165 { 0x1f, 0x0001 },
daf9df6d 3166 { 0x06, 0x4064 },
3167 { 0x07, 0x2863 },
3168 { 0x08, 0x059c },
3169 { 0x09, 0x26b4 },
3170 { 0x0a, 0x6a19 },
3171 { 0x0b, 0xdcc8 },
3172 { 0x10, 0xf06d },
3173 { 0x14, 0x7f68 },
3174 { 0x18, 0x7fd9 },
3175 { 0x1c, 0xf0ff },
3176 { 0x1d, 0x3d9c },
5b538df9 3177 { 0x1f, 0x0003 },
daf9df6d 3178 { 0x12, 0xf49f },
3179 { 0x13, 0x070b },
3180 { 0x1a, 0x05ad },
bca03d5f 3181 { 0x14, 0x94c0 },
3182
3183 /*
3184 * Tx Error Issue
cecb5fd7 3185 * Enhance line driver power
bca03d5f 3186 */
5b538df9 3187 { 0x1f, 0x0002 },
daf9df6d 3188 { 0x06, 0x5561 },
3189 { 0x1f, 0x0005 },
3190 { 0x05, 0x8332 },
bca03d5f 3191 { 0x06, 0x5561 },
3192
3193 /*
3194 * Can not link to 1Gbps with bad cable
3195 * Decrease SNR threshold form 21.07dB to 19.04dB
3196 */
3197 { 0x1f, 0x0001 },
3198 { 0x17, 0x0cc0 },
daf9df6d 3199
5b538df9 3200 { 0x1f, 0x0000 },
bca03d5f 3201 { 0x0d, 0xf880 }
daf9df6d 3202 };
3203
4da19633 3204 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 3205
bca03d5f 3206 /*
3207 * Rx Error Issue
3208 * Fine Tune Switching regulator parameter
3209 */
4da19633 3210 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3211 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3212 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 3213
fdf6fc06 3214 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3215 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3216 { 0x1f, 0x0002 },
3217 { 0x05, 0x669a },
3218 { 0x1f, 0x0005 },
3219 { 0x05, 0x8330 },
3220 { 0x06, 0x669a },
3221 { 0x1f, 0x0002 }
3222 };
3223 int val;
3224
4da19633 3225 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3226
4da19633 3227 val = rtl_readphy(tp, 0x0d);
daf9df6d 3228
3229 if ((val & 0x00ff) != 0x006c) {
350f7596 3230 static const u32 set[] = {
daf9df6d 3231 0x0065, 0x0066, 0x0067, 0x0068,
3232 0x0069, 0x006a, 0x006b, 0x006c
3233 };
3234 int i;
3235
4da19633 3236 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3237
3238 val &= 0xff00;
3239 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3240 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3241 }
3242 } else {
350f7596 3243 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3244 { 0x1f, 0x0002 },
3245 { 0x05, 0x6662 },
3246 { 0x1f, 0x0005 },
3247 { 0x05, 0x8330 },
3248 { 0x06, 0x6662 }
3249 };
3250
4da19633 3251 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3252 }
3253
bca03d5f 3254 /* RSET couple improve */
4da19633 3255 rtl_writephy(tp, 0x1f, 0x0002);
3256 rtl_patchphy(tp, 0x0d, 0x0300);
3257 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 3258
bca03d5f 3259 /* Fine tune PLL performance */
4da19633 3260 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3261 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3262 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3263
4da19633 3264 rtl_writephy(tp, 0x1f, 0x0005);
3265 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3266
3267 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 3268
4da19633 3269 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3270}
3271
bca03d5f 3272static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3273{
350f7596 3274 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3275 /* Channel Estimation */
daf9df6d 3276 { 0x1f, 0x0001 },
3277 { 0x06, 0x4064 },
3278 { 0x07, 0x2863 },
3279 { 0x08, 0x059c },
3280 { 0x09, 0x26b4 },
3281 { 0x0a, 0x6a19 },
3282 { 0x0b, 0xdcc8 },
3283 { 0x10, 0xf06d },
3284 { 0x14, 0x7f68 },
3285 { 0x18, 0x7fd9 },
3286 { 0x1c, 0xf0ff },
3287 { 0x1d, 0x3d9c },
3288 { 0x1f, 0x0003 },
3289 { 0x12, 0xf49f },
3290 { 0x13, 0x070b },
3291 { 0x1a, 0x05ad },
3292 { 0x14, 0x94c0 },
3293
bca03d5f 3294 /*
3295 * Tx Error Issue
cecb5fd7 3296 * Enhance line driver power
bca03d5f 3297 */
daf9df6d 3298 { 0x1f, 0x0002 },
3299 { 0x06, 0x5561 },
3300 { 0x1f, 0x0005 },
3301 { 0x05, 0x8332 },
bca03d5f 3302 { 0x06, 0x5561 },
3303
3304 /*
3305 * Can not link to 1Gbps with bad cable
3306 * Decrease SNR threshold form 21.07dB to 19.04dB
3307 */
3308 { 0x1f, 0x0001 },
3309 { 0x17, 0x0cc0 },
daf9df6d 3310
3311 { 0x1f, 0x0000 },
bca03d5f 3312 { 0x0d, 0xf880 }
5b538df9
FR		 3313 };
3314
4da19633 3315 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 3316
fdf6fc06 3317 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3318 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3319 { 0x1f, 0x0002 },
3320 { 0x05, 0x669a },
5b538df9 3321 { 0x1f, 0x0005 },
daf9df6d 3322 { 0x05, 0x8330 },
3323 { 0x06, 0x669a },
3324
3325 { 0x1f, 0x0002 }
3326 };
3327 int val;
3328
4da19633 3329 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3330
4da19633 3331 val = rtl_readphy(tp, 0x0d);
daf9df6d 3332 if ((val & 0x00ff) != 0x006c) {
b6bc7650 3333 static const u32 set[] = {
daf9df6d 3334 0x0065, 0x0066, 0x0067, 0x0068,
3335 0x0069, 0x006a, 0x006b, 0x006c
3336 };
3337 int i;
3338
4da19633 3339 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3340
3341 val &= 0xff00;
3342 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3343 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3344 }
3345 } else {
350f7596 3346 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3347 { 0x1f, 0x0002 },
3348 { 0x05, 0x2642 },
5b538df9 3349 { 0x1f, 0x0005 },
daf9df6d 3350 { 0x05, 0x8330 },
3351 { 0x06, 0x2642 }
5b538df9
FR		 3352 };
3353
4da19633 3354 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3355 }
3356
bca03d5f 3357 /* Fine tune PLL performance */
4da19633 3358 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3359 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3360 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3361
bca03d5f 3362 /* Switching regulator Slew rate */
4da19633 3363 rtl_writephy(tp, 0x1f, 0x0002);
3364 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 3365
4da19633 3366 rtl_writephy(tp, 0x1f, 0x0005);
3367 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3368
3369 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 3370
4da19633 3371 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3372}
3373
4da19633 3374static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3375{
350f7596 3376 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3377 { 0x1f, 0x0002 },
3378 { 0x10, 0x0008 },
3379 { 0x0d, 0x006c },
3380
3381 { 0x1f, 0x0000 },
3382 { 0x0d, 0xf880 },
3383
3384 { 0x1f, 0x0001 },
3385 { 0x17, 0x0cc0 },
3386
3387 { 0x1f, 0x0001 },
3388 { 0x0b, 0xa4d8 },
3389 { 0x09, 0x281c },
3390 { 0x07, 0x2883 },
3391 { 0x0a, 0x6b35 },
3392 { 0x1d, 0x3da4 },
3393 { 0x1c, 0xeffd },
3394 { 0x14, 0x7f52 },
3395 { 0x18, 0x7fc6 },
3396 { 0x08, 0x0601 },
3397 { 0x06, 0x4063 },
3398 { 0x10, 0xf074 },
3399 { 0x1f, 0x0003 },
3400 { 0x13, 0x0789 },
3401 { 0x12, 0xf4bd },
3402 { 0x1a, 0x04fd },
3403 { 0x14, 0x84b0 },
3404 { 0x1f, 0x0000 },
3405 { 0x00, 0x9200 },
3406
3407 { 0x1f, 0x0005 },
3408 { 0x01, 0x0340 },
3409 { 0x1f, 0x0001 },
3410 { 0x04, 0x4000 },
3411 { 0x03, 0x1d21 },
3412 { 0x02, 0x0c32 },
3413 { 0x01, 0x0200 },
3414 { 0x00, 0x5554 },
3415 { 0x04, 0x4800 },
3416 { 0x04, 0x4000 },
3417 { 0x04, 0xf000 },
3418 { 0x03, 0xdf01 },
3419 { 0x02, 0xdf20 },
3420 { 0x01, 0x101a },
3421 { 0x00, 0xa0ff },
3422 { 0x04, 0xf800 },
3423 { 0x04, 0xf000 },
3424 { 0x1f, 0x0000 },
3425
3426 { 0x1f, 0x0007 },
3427 { 0x1e, 0x0023 },
3428 { 0x16, 0x0000 },
3429 { 0x1f, 0x0000 }
3430 };
3431
4da19633 3432 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3433}
3434
e6de30d6 3435static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3436{
3437 static const struct phy_reg phy_reg_init[] = {
3438 { 0x1f, 0x0001 },
3439 { 0x17, 0x0cc0 },
3440
3441 { 0x1f, 0x0007 },
3442 { 0x1e, 0x002d },
3443 { 0x18, 0x0040 },
3444 { 0x1f, 0x0000 }
3445 };
3446
3447 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3448 rtl_patchphy(tp, 0x0d, 1 << 5);
3449}
3450
70090424 3451static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3452{
3453 static const struct phy_reg phy_reg_init[] = {
3454 /* Enable Delay cap */
3455 { 0x1f, 0x0005 },
3456 { 0x05, 0x8b80 },
3457 { 0x06, 0xc896 },
3458 { 0x1f, 0x0000 },
3459
3460 /* Channel estimation fine tune */
3461 { 0x1f, 0x0001 },
3462 { 0x0b, 0x6c20 },
3463 { 0x07, 0x2872 },
3464 { 0x1c, 0xefff },
3465 { 0x1f, 0x0003 },
3466 { 0x14, 0x6420 },
3467 { 0x1f, 0x0000 },
3468
3469 /* Update PFM & 10M TX idle timer */
3470 { 0x1f, 0x0007 },
3471 { 0x1e, 0x002f },
3472 { 0x15, 0x1919 },
3473 { 0x1f, 0x0000 },
3474
3475 { 0x1f, 0x0007 },
3476 { 0x1e, 0x00ac },
3477 { 0x18, 0x0006 },
3478 { 0x1f, 0x0000 }
3479 };
3480
15ecd039
FR		 3481 rtl_apply_firmware(tp);
3482
01dc7fec 3483 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3484
3485 /* DCO enable for 10M IDLE Power */
3486 rtl_writephy(tp, 0x1f, 0x0007);
3487 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3488 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3489 rtl_writephy(tp, 0x1f, 0x0000);
3490
3491 /* For impedance matching */
3492 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3493 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3494 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3495
3496 /* PHY auto speed down */
3497 rtl_writephy(tp, 0x1f, 0x0007);
3498 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3499 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3500 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3501 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3502
3503 rtl_writephy(tp, 0x1f, 0x0005);
3504 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3505 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3506 rtl_writephy(tp, 0x1f, 0x0000);
3507
3508 rtl_writephy(tp, 0x1f, 0x0005);
3509 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3510 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3511 rtl_writephy(tp, 0x1f, 0x0007);
3512 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3513 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3514 rtl_writephy(tp, 0x1f, 0x0006);
3515 rtl_writephy(tp, 0x00, 0x5a00);
3516 rtl_writephy(tp, 0x1f, 0x0000);
3517 rtl_writephy(tp, 0x0d, 0x0007);
3518 rtl_writephy(tp, 0x0e, 0x003c);
3519 rtl_writephy(tp, 0x0d, 0x4007);
3520 rtl_writephy(tp, 0x0e, 0x0000);
3521 rtl_writephy(tp, 0x0d, 0x0000);
3522}
3523
9ecb9aab 3524static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3525{
3526 const u16 w[] = {
3527 addr[0] | (addr[1] << 8),
3528 addr[2] | (addr[3] << 8),
3529 addr[4] | (addr[5] << 8)
3530 };
3531 const struct exgmac_reg e[] = {
3532 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3533 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3534 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3535 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3536 };
3537
3538 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3539}
3540
70090424
HW		 3541static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3542{
3543 static const struct phy_reg phy_reg_init[] = {
3544 /* Enable Delay cap */
3545 { 0x1f, 0x0004 },
3546 { 0x1f, 0x0007 },
3547 { 0x1e, 0x00ac },
3548 { 0x18, 0x0006 },
3549 { 0x1f, 0x0002 },
3550 { 0x1f, 0x0000 },
3551 { 0x1f, 0x0000 },
3552
3553 /* Channel estimation fine tune */
3554 { 0x1f, 0x0003 },
3555 { 0x09, 0xa20f },
3556 { 0x1f, 0x0000 },
3557 { 0x1f, 0x0000 },
3558
3559 /* Green Setting */
3560 { 0x1f, 0x0005 },
3561 { 0x05, 0x8b5b },
3562 { 0x06, 0x9222 },
3563 { 0x05, 0x8b6d },
3564 { 0x06, 0x8000 },
3565 { 0x05, 0x8b76 },
3566 { 0x06, 0x8000 },
3567 { 0x1f, 0x0000 }
3568 };
3569
3570 rtl_apply_firmware(tp);
3571
3572 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3573
3574 /* For 4-corner performance improve */
3575 rtl_writephy(tp, 0x1f, 0x0005);
3576 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3577 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3578 rtl_writephy(tp, 0x1f, 0x0000);
3579
3580 /* PHY auto speed down */
3581 rtl_writephy(tp, 0x1f, 0x0004);
3582 rtl_writephy(tp, 0x1f, 0x0007);
3583 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3584 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3585 rtl_writephy(tp, 0x1f, 0x0002);
3586 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3587 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3588
3589 /* improve 10M EEE waveform */
3590 rtl_writephy(tp, 0x1f, 0x0005);
3591 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3592 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3593 rtl_writephy(tp, 0x1f, 0x0000);
3594
3595 /* Improve 2-pair detection performance */
3596 rtl_writephy(tp, 0x1f, 0x0005);
3597 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3598 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3599 rtl_writephy(tp, 0x1f, 0x0000);
3600
3601 /* EEE setting */
1814d6a8 3602 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
70090424
HW		 3603 rtl_writephy(tp, 0x1f, 0x0005);
3604 rtl_writephy(tp, 0x05, 0x8b85);
1814d6a8 3605 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
70090424
HW		 3606 rtl_writephy(tp, 0x1f, 0x0004);
3607 rtl_writephy(tp, 0x1f, 0x0007);
3608 rtl_writephy(tp, 0x1e, 0x0020);
1814d6a8 3609 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
70090424
HW		 3610 rtl_writephy(tp, 0x1f, 0x0002);
3611 rtl_writephy(tp, 0x1f, 0x0000);
3612 rtl_writephy(tp, 0x0d, 0x0007);
3613 rtl_writephy(tp, 0x0e, 0x003c);
3614 rtl_writephy(tp, 0x0d, 0x4007);
1814d6a8 3615 rtl_writephy(tp, 0x0e, 0x0006);
70090424
HW		 3616 rtl_writephy(tp, 0x0d, 0x0000);
3617
3618 /* Green feature */
3619 rtl_writephy(tp, 0x1f, 0x0003);
1814d6a8
HK		 3620 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3621 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
70090424 3622 rtl_writephy(tp, 0x1f, 0x0000);
b399a394
HK		 3623 rtl_writephy(tp, 0x1f, 0x0005);
3624 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3625 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3626
9ecb9aab 3627 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3628 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3629}
3630
5f886e08
HW		 3631static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3632{
3633 /* For 4-corner performance improve */
3634 rtl_writephy(tp, 0x1f, 0x0005);
3635 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3636 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3637 rtl_writephy(tp, 0x1f, 0x0000);
3638
3639 /* PHY auto speed down */
3640 rtl_writephy(tp, 0x1f, 0x0007);
3641 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3642 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3643 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3644 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3645
3646 /* Improve 10M EEE waveform */
3647 rtl_writephy(tp, 0x1f, 0x0005);
3648 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3649 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3650 rtl_writephy(tp, 0x1f, 0x0000);
3651}
3652
c2218925
HW		 3653static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3654{
3655 static const struct phy_reg phy_reg_init[] = {
3656 /* Channel estimation fine tune */
3657 { 0x1f, 0x0003 },
3658 { 0x09, 0xa20f },
3659 { 0x1f, 0x0000 },
3660
3661 /* Modify green table for giga & fnet */
3662 { 0x1f, 0x0005 },
3663 { 0x05, 0x8b55 },
3664 { 0x06, 0x0000 },
3665 { 0x05, 0x8b5e },
3666 { 0x06, 0x0000 },
3667 { 0x05, 0x8b67 },
3668 { 0x06, 0x0000 },
3669 { 0x05, 0x8b70 },
3670 { 0x06, 0x0000 },
3671 { 0x1f, 0x0000 },
3672 { 0x1f, 0x0007 },
3673 { 0x1e, 0x0078 },
3674 { 0x17, 0x0000 },
3675 { 0x19, 0x00fb },
3676 { 0x1f, 0x0000 },
3677
3678 /* Modify green table for 10M */
3679 { 0x1f, 0x0005 },
3680 { 0x05, 0x8b79 },
3681 { 0x06, 0xaa00 },
3682 { 0x1f, 0x0000 },
3683
3684 /* Disable hiimpedance detection (RTCT) */
3685 { 0x1f, 0x0003 },
3686 { 0x01, 0x328a },
3687 { 0x1f, 0x0000 }
3688 };
3689
3690 rtl_apply_firmware(tp);
3691
3692 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3693
5f886e08 3694 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3695
3696 /* Improve 2-pair detection performance */
3697 rtl_writephy(tp, 0x1f, 0x0005);
3698 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3699 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3700 rtl_writephy(tp, 0x1f, 0x0000);
3701}
3702
3703static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3704{
3705 rtl_apply_firmware(tp);
3706
5f886e08 3707 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3708}
3709
b3d7b2f2
HW		 3710static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3711{
b3d7b2f2
HW		 3712 static const struct phy_reg phy_reg_init[] = {
3713 /* Channel estimation fine tune */
3714 { 0x1f, 0x0003 },
3715 { 0x09, 0xa20f },
3716 { 0x1f, 0x0000 },
3717
3718 /* Modify green table for giga & fnet */
3719 { 0x1f, 0x0005 },
3720 { 0x05, 0x8b55 },
3721 { 0x06, 0x0000 },
3722 { 0x05, 0x8b5e },
3723 { 0x06, 0x0000 },
3724 { 0x05, 0x8b67 },
3725 { 0x06, 0x0000 },
3726 { 0x05, 0x8b70 },
3727 { 0x06, 0x0000 },
3728 { 0x1f, 0x0000 },
3729 { 0x1f, 0x0007 },
3730 { 0x1e, 0x0078 },
3731 { 0x17, 0x0000 },
3732 { 0x19, 0x00aa },
3733 { 0x1f, 0x0000 },
3734
3735 /* Modify green table for 10M */
3736 { 0x1f, 0x0005 },
3737 { 0x05, 0x8b79 },
3738 { 0x06, 0xaa00 },
3739 { 0x1f, 0x0000 },
3740
3741 /* Disable hiimpedance detection (RTCT) */
3742 { 0x1f, 0x0003 },
3743 { 0x01, 0x328a },
3744 { 0x1f, 0x0000 }
3745 };
3746
3747
3748 rtl_apply_firmware(tp);
3749
3750 rtl8168f_hw_phy_config(tp);
3751
3752 /* Improve 2-pair detection performance */
3753 rtl_writephy(tp, 0x1f, 0x0005);
3754 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3755 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3756 rtl_writephy(tp, 0x1f, 0x0000);
3757
3758 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3759
3760 /* Modify green table for giga */
3761 rtl_writephy(tp, 0x1f, 0x0005);
3762 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3763 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3764 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3765 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3766 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3767 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3768 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3769 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3770 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3771 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3772 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3773 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3774 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3775 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3776 rtl_writephy(tp, 0x1f, 0x0000);
3777
3778 /* uc same-seed solution */
3779 rtl_writephy(tp, 0x1f, 0x0005);
3780 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3781 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3782 rtl_writephy(tp, 0x1f, 0x0000);
3783
3784 /* eee setting */
706123d0 3785 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3786 rtl_writephy(tp, 0x1f, 0x0005);
3787 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3788 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3789 rtl_writephy(tp, 0x1f, 0x0004);
3790 rtl_writephy(tp, 0x1f, 0x0007);
3791 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3792 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3793 rtl_writephy(tp, 0x1f, 0x0000);
3794 rtl_writephy(tp, 0x0d, 0x0007);
3795 rtl_writephy(tp, 0x0e, 0x003c);
3796 rtl_writephy(tp, 0x0d, 0x4007);
3797 rtl_writephy(tp, 0x0e, 0x0000);
3798 rtl_writephy(tp, 0x0d, 0x0000);
3799
3800 /* Green feature */
3801 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3802 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3803 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3804 rtl_writephy(tp, 0x1f, 0x0000);
3805}
3806
c558386b
HW		 3807static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3808{
c558386b
HW		 3809 rtl_apply_firmware(tp);
3810
41f44d13 3811 rtl_writephy(tp, 0x1f, 0x0a46);
3812 if (rtl_readphy(tp, 0x10) & 0x0100) {
3813 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3814 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3815 } else {
3816 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3817 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3818 }
c558386b 3819
41f44d13 3820 rtl_writephy(tp, 0x1f, 0x0a46);
3821 if (rtl_readphy(tp, 0x13) & 0x0100) {
3822 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3823 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 3824 } else {
fe7524c0 3825 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3826 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3827 }
c558386b 3828
41f44d13 3829 /* Enable PHY auto speed down */
3830 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3831 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3832
fe7524c0 3833 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3834 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 3835 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3836 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 3837 rtl_writephy(tp, 0x1f, 0x0a43);
3838 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 3839 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3840 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 3841
41f44d13 3842 /* EEE auto-fallback function */
3843 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 3844 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3845
41f44d13 3846 /* Enable UC LPF tune function */
3847 rtl_writephy(tp, 0x1f, 0x0a43);
3848 rtl_writephy(tp, 0x13, 0x8012);
76564428 3849 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 3850
3851 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 3852 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 3853
fe7524c0 3854 /* Improve SWR Efficiency */
3855 rtl_writephy(tp, 0x1f, 0x0bcd);
3856 rtl_writephy(tp, 0x14, 0x5065);
3857 rtl_writephy(tp, 0x14, 0xd065);
3858 rtl_writephy(tp, 0x1f, 0x0bc8);
3859 rtl_writephy(tp, 0x11, 0x5655);
3860 rtl_writephy(tp, 0x1f, 0x0bcd);
3861 rtl_writephy(tp, 0x14, 0x1065);
3862 rtl_writephy(tp, 0x14, 0x9065);
3863 rtl_writephy(tp, 0x14, 0x1065);
3864
1bac1072
DC		 3865 /* Check ALDPS bit, disable it if enabled */
3866 rtl_writephy(tp, 0x1f, 0x0a43);
3867 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3868 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 3869
41f44d13 3870 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3871}
3872
57538c4a 3873static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3874{
3875 rtl_apply_firmware(tp);
3876}
3877
6e1d0b89
CHL		 3878static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3879{
3880 u16 dout_tapbin;
3881 u32 data;
3882
3883 rtl_apply_firmware(tp);
3884
3885 /* CHN EST parameters adjust - giga master */
3886 rtl_writephy(tp, 0x1f, 0x0a43);
3887 rtl_writephy(tp, 0x13, 0x809b);
76564428 3888 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 3889 rtl_writephy(tp, 0x13, 0x80a2);
76564428 3890 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 3891 rtl_writephy(tp, 0x13, 0x80a4);
76564428 3892 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 3893 rtl_writephy(tp, 0x13, 0x809c);
76564428 3894 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 3895 rtl_writephy(tp, 0x1f, 0x0000);
3896
3897 /* CHN EST parameters adjust - giga slave */
3898 rtl_writephy(tp, 0x1f, 0x0a43);
3899 rtl_writephy(tp, 0x13, 0x80ad);
76564428 3900 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 3901 rtl_writephy(tp, 0x13, 0x80b4);
76564428 3902 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 3903 rtl_writephy(tp, 0x13, 0x80ac);
76564428 3904 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 3905 rtl_writephy(tp, 0x1f, 0x0000);
3906
3907 /* CHN EST parameters adjust - fnet */
3908 rtl_writephy(tp, 0x1f, 0x0a43);
3909 rtl_writephy(tp, 0x13, 0x808e);
76564428 3910 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 3911 rtl_writephy(tp, 0x13, 0x8090);
76564428 3912 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 3913 rtl_writephy(tp, 0x13, 0x8092);
76564428 3914 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 3915 rtl_writephy(tp, 0x1f, 0x0000);
3916
3917 /* enable R-tune & PGA-retune function */
3918 dout_tapbin = 0;
3919 rtl_writephy(tp, 0x1f, 0x0a46);
3920 data = rtl_readphy(tp, 0x13);
3921 data &= 3;
3922 data <<= 2;
3923 dout_tapbin |= data;
3924 data = rtl_readphy(tp, 0x12);
3925 data &= 0xc000;
3926 data >>= 14;
3927 dout_tapbin |= data;
3928 dout_tapbin = ~(dout_tapbin^0x08);
3929 dout_tapbin <<= 12;
3930 dout_tapbin &= 0xf000;
3931 rtl_writephy(tp, 0x1f, 0x0a43);
3932 rtl_writephy(tp, 0x13, 0x827a);
76564428 3933 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3934 rtl_writephy(tp, 0x13, 0x827b);
76564428 3935 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3936 rtl_writephy(tp, 0x13, 0x827c);
76564428 3937 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3938 rtl_writephy(tp, 0x13, 0x827d);
76564428 3939 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 3940
3941 rtl_writephy(tp, 0x1f, 0x0a43);
3942 rtl_writephy(tp, 0x13, 0x0811);
76564428 3943 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3944 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3945 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3946 rtl_writephy(tp, 0x1f, 0x0000);
3947
3948 /* enable GPHY 10M */
3949 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3950 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3951 rtl_writephy(tp, 0x1f, 0x0000);
3952
3953 /* SAR ADC performance */
3954 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 3955 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 3956 rtl_writephy(tp, 0x1f, 0x0000);
3957
3958 rtl_writephy(tp, 0x1f, 0x0a43);
3959 rtl_writephy(tp, 0x13, 0x803f);
76564428 3960 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3961 rtl_writephy(tp, 0x13, 0x8047);
76564428 3962 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3963 rtl_writephy(tp, 0x13, 0x804f);
76564428 3964 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3965 rtl_writephy(tp, 0x13, 0x8057);
76564428 3966 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3967 rtl_writephy(tp, 0x13, 0x805f);
76564428 3968 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3969 rtl_writephy(tp, 0x13, 0x8067);
76564428 3970 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3971 rtl_writephy(tp, 0x13, 0x806f);
76564428 3972 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 3973 rtl_writephy(tp, 0x1f, 0x0000);
3974
3975 /* disable phy pfm mode */
3976 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3977 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3978 rtl_writephy(tp, 0x1f, 0x0000);
3979
3980 /* Check ALDPS bit, disable it if enabled */
3981 rtl_writephy(tp, 0x1f, 0x0a43);
3982 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3983 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3984
3985 rtl_writephy(tp, 0x1f, 0x0000);
3986}
3987
3988static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3989{
3990 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3991 u16 rlen;
3992 u32 data;
3993
3994 rtl_apply_firmware(tp);
3995
3996 /* CHIN EST parameter update */
3997 rtl_writephy(tp, 0x1f, 0x0a43);
3998 rtl_writephy(tp, 0x13, 0x808a);
76564428 3999 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 4000 rtl_writephy(tp, 0x1f, 0x0000);
4001
4002 /* enable R-tune & PGA-retune function */
4003 rtl_writephy(tp, 0x1f, 0x0a43);
4004 rtl_writephy(tp, 0x13, 0x0811);
76564428 4005 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 4006 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 4007 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 4008 rtl_writephy(tp, 0x1f, 0x0000);
4009
4010 /* enable GPHY 10M */
4011 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 4012 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 4013 rtl_writephy(tp, 0x1f, 0x0000);
4014
4015 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
4016 data = r8168_mac_ocp_read(tp, 0xdd02);
4017 ioffset_p3 = ((data & 0x80)>>7);
4018 ioffset_p3 <<= 3;
4019
4020 data = r8168_mac_ocp_read(tp, 0xdd00);
4021 ioffset_p3 |= ((data & (0xe000))>>13);
4022 ioffset_p2 = ((data & (0x1e00))>>9);
4023 ioffset_p1 = ((data & (0x01e0))>>5);
4024 ioffset_p0 = ((data & 0x0010)>>4);
4025 ioffset_p0 <<= 3;
4026 ioffset_p0 |= (data & (0x07));
4027 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
4028
05b9687b 4029 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
e2e2788e 4030 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
6e1d0b89
CHL		 4031 rtl_writephy(tp, 0x1f, 0x0bcf);
4032 rtl_writephy(tp, 0x16, data);
4033 rtl_writephy(tp, 0x1f, 0x0000);
4034 }
4035
4036 /* Modify rlen (TX LPF corner frequency) level */
4037 rtl_writephy(tp, 0x1f, 0x0bcd);
4038 data = rtl_readphy(tp, 0x16);
4039 data &= 0x000f;
4040 rlen = 0;
4041 if (data > 3)
4042 rlen = data - 3;
4043 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
4044 rtl_writephy(tp, 0x17, data);
4045 rtl_writephy(tp, 0x1f, 0x0bcd);
4046 rtl_writephy(tp, 0x1f, 0x0000);
4047
4048 /* disable phy pfm mode */
4049 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 4050 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 4051 rtl_writephy(tp, 0x1f, 0x0000);
4052
4053 /* Check ALDPS bit, disable it if enabled */
4054 rtl_writephy(tp, 0x1f, 0x0a43);
4055 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 4056 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 4057
4058 rtl_writephy(tp, 0x1f, 0x0000);
4059}
4060
935e2218
CHL		 4061static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4062{
4063 /* Enable PHY auto speed down */
4064 rtl_writephy(tp, 0x1f, 0x0a44);
4065 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4066 rtl_writephy(tp, 0x1f, 0x0000);
4067
4068 /* patch 10M & ALDPS */
4069 rtl_writephy(tp, 0x1f, 0x0bcc);
4070 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4071 rtl_writephy(tp, 0x1f, 0x0a44);
4072 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4073 rtl_writephy(tp, 0x1f, 0x0a43);
4074 rtl_writephy(tp, 0x13, 0x8084);
4075 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4076 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4077 rtl_writephy(tp, 0x1f, 0x0000);
4078
4079 /* Enable EEE auto-fallback function */
4080 rtl_writephy(tp, 0x1f, 0x0a4b);
4081 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4082 rtl_writephy(tp, 0x1f, 0x0000);
4083
4084 /* Enable UC LPF tune function */
4085 rtl_writephy(tp, 0x1f, 0x0a43);
4086 rtl_writephy(tp, 0x13, 0x8012);
4087 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4088 rtl_writephy(tp, 0x1f, 0x0000);
4089
4090 /* set rg_sel_sdm_rate */
4091 rtl_writephy(tp, 0x1f, 0x0c42);
4092 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4093 rtl_writephy(tp, 0x1f, 0x0000);
4094
4095 /* Check ALDPS bit, disable it if enabled */
4096 rtl_writephy(tp, 0x1f, 0x0a43);
4097 if (rtl_readphy(tp, 0x10) & 0x0004)
4098 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4099
4100 rtl_writephy(tp, 0x1f, 0x0000);
4101}
4102
4103static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4104{
4105 /* patch 10M & ALDPS */
4106 rtl_writephy(tp, 0x1f, 0x0bcc);
4107 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4108 rtl_writephy(tp, 0x1f, 0x0a44);
4109 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4110 rtl_writephy(tp, 0x1f, 0x0a43);
4111 rtl_writephy(tp, 0x13, 0x8084);
4112 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4113 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4114 rtl_writephy(tp, 0x1f, 0x0000);
4115
4116 /* Enable UC LPF tune function */
4117 rtl_writephy(tp, 0x1f, 0x0a43);
4118 rtl_writephy(tp, 0x13, 0x8012);
4119 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4120 rtl_writephy(tp, 0x1f, 0x0000);
4121
4122 /* Set rg_sel_sdm_rate */
4123 rtl_writephy(tp, 0x1f, 0x0c42);
4124 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4125 rtl_writephy(tp, 0x1f, 0x0000);
4126
4127 /* Channel estimation parameters */
4128 rtl_writephy(tp, 0x1f, 0x0a43);
4129 rtl_writephy(tp, 0x13, 0x80f3);
4130 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4131 rtl_writephy(tp, 0x13, 0x80f0);
4132 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4133 rtl_writephy(tp, 0x13, 0x80ef);
4134 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4135 rtl_writephy(tp, 0x13, 0x80f6);
4136 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4137 rtl_writephy(tp, 0x13, 0x80ec);
4138 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4139 rtl_writephy(tp, 0x13, 0x80ed);
4140 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4141 rtl_writephy(tp, 0x13, 0x80f2);
4142 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4143 rtl_writephy(tp, 0x13, 0x80f4);
4144 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4145 rtl_writephy(tp, 0x1f, 0x0a43);
4146 rtl_writephy(tp, 0x13, 0x8110);
4147 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4148 rtl_writephy(tp, 0x13, 0x810f);
4149 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4150 rtl_writephy(tp, 0x13, 0x8111);
4151 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4152 rtl_writephy(tp, 0x13, 0x8113);
4153 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4154 rtl_writephy(tp, 0x13, 0x8115);
4155 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4156 rtl_writephy(tp, 0x13, 0x810e);
4157 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4158 rtl_writephy(tp, 0x13, 0x810c);
4159 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4160 rtl_writephy(tp, 0x13, 0x810b);
4161 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4162 rtl_writephy(tp, 0x1f, 0x0a43);
4163 rtl_writephy(tp, 0x13, 0x80d1);
4164 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4165 rtl_writephy(tp, 0x13, 0x80cd);
4166 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4167 rtl_writephy(tp, 0x13, 0x80d3);
4168 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4169 rtl_writephy(tp, 0x13, 0x80d5);
4170 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4171 rtl_writephy(tp, 0x13, 0x80d7);
4172 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4173
4174 /* Force PWM-mode */
4175 rtl_writephy(tp, 0x1f, 0x0bcd);
4176 rtl_writephy(tp, 0x14, 0x5065);
4177 rtl_writephy(tp, 0x14, 0xd065);
4178 rtl_writephy(tp, 0x1f, 0x0bc8);
4179 rtl_writephy(tp, 0x12, 0x00ed);
4180 rtl_writephy(tp, 0x1f, 0x0bcd);
4181 rtl_writephy(tp, 0x14, 0x1065);
4182 rtl_writephy(tp, 0x14, 0x9065);
4183 rtl_writephy(tp, 0x14, 0x1065);
4184 rtl_writephy(tp, 0x1f, 0x0000);
4185
4186 /* Check ALDPS bit, disable it if enabled */
4187 rtl_writephy(tp, 0x1f, 0x0a43);
4188 if (rtl_readphy(tp, 0x10) & 0x0004)
4189 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4190
4191 rtl_writephy(tp, 0x1f, 0x0000);
4192}
4193
4da19633 4194static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 4195{
350f7596 4196 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 4197 { 0x1f, 0x0003 },
4198 { 0x08, 0x441d },
4199 { 0x01, 0x9100 },
4200 { 0x1f, 0x0000 }
4201 };
4202
4da19633 4203 rtl_writephy(tp, 0x1f, 0x0000);
4204 rtl_patchphy(tp, 0x11, 1 << 12);
4205 rtl_patchphy(tp, 0x19, 1 << 13);
4206 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 4207
4da19633 4208 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 4209}
4210
5a5e4443
HW		 4211static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4212{
4213 static const struct phy_reg phy_reg_init[] = {
4214 { 0x1f, 0x0005 },
4215 { 0x1a, 0x0000 },
4216 { 0x1f, 0x0000 },
4217
4218 { 0x1f, 0x0004 },
4219 { 0x1c, 0x0000 },
4220 { 0x1f, 0x0000 },
4221
4222 { 0x1f, 0x0001 },
4223 { 0x15, 0x7701 },
4224 { 0x1f, 0x0000 }
4225 };
4226
4227 /* Disable ALDPS before ram code */
eef63cc1
FR		 4228 rtl_writephy(tp, 0x1f, 0x0000);
4229 rtl_writephy(tp, 0x18, 0x0310);
4230 msleep(100);
5a5e4443 4231
953a12cc 4232 rtl_apply_firmware(tp);
5a5e4443
HW		 4233
4234 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4235}
4236
7e18dca1
HW		 4237static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4238{
7e18dca1 4239 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 4240 rtl_writephy(tp, 0x1f, 0x0000);
4241 rtl_writephy(tp, 0x18, 0x0310);
4242 msleep(20);
7e18dca1
HW		 4243
4244 rtl_apply_firmware(tp);
4245
4246 /* EEE setting */
fdf6fc06 4247 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 4248 rtl_writephy(tp, 0x1f, 0x0004);
4249 rtl_writephy(tp, 0x10, 0x401f);
4250 rtl_writephy(tp, 0x19, 0x7030);
4251 rtl_writephy(tp, 0x1f, 0x0000);
4252}
4253
5598bfe5
HW		 4254static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4255{
5598bfe5
HW		 4256 static const struct phy_reg phy_reg_init[] = {
4257 { 0x1f, 0x0004 },
4258 { 0x10, 0xc07f },
4259 { 0x19, 0x7030 },
4260 { 0x1f, 0x0000 }
4261 };
4262
4263 /* Disable ALDPS before ram code */
eef63cc1
FR		 4264 rtl_writephy(tp, 0x1f, 0x0000);
4265 rtl_writephy(tp, 0x18, 0x0310);
4266 msleep(100);
5598bfe5
HW		 4267
4268 rtl_apply_firmware(tp);
4269
fdf6fc06 4270 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4271 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4272
fdf6fc06 4273 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4274}
4275
5615d9f1
FR		 4276static void rtl_hw_phy_config(struct net_device *dev)
4277{
4278 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 4279
4280 rtl8169_print_mac_version(tp);
4281
4282 switch (tp->mac_version) {
4283 case RTL_GIGA_MAC_VER_01:
4284 break;
4285 case RTL_GIGA_MAC_VER_02:
4286 case RTL_GIGA_MAC_VER_03:
4da19633 4287 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 4288 break;
4289 case RTL_GIGA_MAC_VER_04:
4da19633 4290 rtl8169sb_hw_phy_config(tp);
5615d9f1 4291 break;
2e955856 4292 case RTL_GIGA_MAC_VER_05:
4da19633 4293 rtl8169scd_hw_phy_config(tp);
2e955856 4294 break;
8c7006aa 4295 case RTL_GIGA_MAC_VER_06:
4da19633 4296 rtl8169sce_hw_phy_config(tp);
8c7006aa 4297 break;
2857ffb7
FR		 4298 case RTL_GIGA_MAC_VER_07:
4299 case RTL_GIGA_MAC_VER_08:
4300 case RTL_GIGA_MAC_VER_09:
4da19633 4301 rtl8102e_hw_phy_config(tp);
2857ffb7 4302 break;
236b8082 4303 case RTL_GIGA_MAC_VER_11:
4da19633 4304 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 4305 break;
4306 case RTL_GIGA_MAC_VER_12:
4da19633 4307 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 4308 break;
4309 case RTL_GIGA_MAC_VER_17:
4da19633 4310 rtl8168bef_hw_phy_config(tp);
236b8082 4311 break;
867763c1 4312 case RTL_GIGA_MAC_VER_18:
4da19633 4313 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 4314 break;
4315 case RTL_GIGA_MAC_VER_19:
4da19633 4316 rtl8168c_1_hw_phy_config(tp);
867763c1 4317 break;
7da97ec9 4318 case RTL_GIGA_MAC_VER_20:
4da19633 4319 rtl8168c_2_hw_phy_config(tp);
7da97ec9 4320 break;
197ff761 4321 case RTL_GIGA_MAC_VER_21:
4da19633 4322 rtl8168c_3_hw_phy_config(tp);
197ff761 4323 break;
6fb07058 4324 case RTL_GIGA_MAC_VER_22:
4da19633 4325 rtl8168c_4_hw_phy_config(tp);
6fb07058 4326 break;
ef3386f0 4327 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 4328 case RTL_GIGA_MAC_VER_24:
4da19633 4329 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 4330 break;
5b538df9 4331 case RTL_GIGA_MAC_VER_25:
bca03d5f 4332 rtl8168d_1_hw_phy_config(tp);
daf9df6d 4333 break;
4334 case RTL_GIGA_MAC_VER_26:
bca03d5f 4335 rtl8168d_2_hw_phy_config(tp);
daf9df6d 4336 break;
4337 case RTL_GIGA_MAC_VER_27:
4da19633 4338 rtl8168d_3_hw_phy_config(tp);
5b538df9 4339 break;
e6de30d6 4340 case RTL_GIGA_MAC_VER_28:
4341 rtl8168d_4_hw_phy_config(tp);
4342 break;
5a5e4443
HW		 4343 case RTL_GIGA_MAC_VER_29:
4344 case RTL_GIGA_MAC_VER_30:
4345 rtl8105e_hw_phy_config(tp);
4346 break;
cecb5fd7
FR		 4347 case RTL_GIGA_MAC_VER_31:
4348 /* None. */
4349 break;
01dc7fec 4350 case RTL_GIGA_MAC_VER_32:
01dc7fec 4351 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4352 rtl8168e_1_hw_phy_config(tp);
4353 break;
4354 case RTL_GIGA_MAC_VER_34:
4355 rtl8168e_2_hw_phy_config(tp);
01dc7fec 4356 break;
c2218925
HW		 4357 case RTL_GIGA_MAC_VER_35:
4358 rtl8168f_1_hw_phy_config(tp);
4359 break;
4360 case RTL_GIGA_MAC_VER_36:
4361 rtl8168f_2_hw_phy_config(tp);
4362 break;
ef3386f0 4363
7e18dca1
HW		 4364 case RTL_GIGA_MAC_VER_37:
4365 rtl8402_hw_phy_config(tp);
4366 break;
4367
b3d7b2f2
HW		 4368 case RTL_GIGA_MAC_VER_38:
4369 rtl8411_hw_phy_config(tp);
4370 break;
4371
5598bfe5
HW		 4372 case RTL_GIGA_MAC_VER_39:
4373 rtl8106e_hw_phy_config(tp);
4374 break;
4375
c558386b
HW		 4376 case RTL_GIGA_MAC_VER_40:
4377 rtl8168g_1_hw_phy_config(tp);
4378 break;
57538c4a 4379 case RTL_GIGA_MAC_VER_42:
58152cd4 4380 case RTL_GIGA_MAC_VER_43:
45dd95c4 4381 case RTL_GIGA_MAC_VER_44:
57538c4a 4382 rtl8168g_2_hw_phy_config(tp);
4383 break;
6e1d0b89
CHL		 4384 case RTL_GIGA_MAC_VER_45:
4385 case RTL_GIGA_MAC_VER_47:
4386 rtl8168h_1_hw_phy_config(tp);
4387 break;
4388 case RTL_GIGA_MAC_VER_46:
4389 case RTL_GIGA_MAC_VER_48:
4390 rtl8168h_2_hw_phy_config(tp);
4391 break;
c558386b 4392
935e2218
CHL		 4393 case RTL_GIGA_MAC_VER_49:
4394 rtl8168ep_1_hw_phy_config(tp);
4395 break;
4396 case RTL_GIGA_MAC_VER_50:
4397 case RTL_GIGA_MAC_VER_51:
4398 rtl8168ep_2_hw_phy_config(tp);
4399 break;
4400
c558386b 4401 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 4402 default:
4403 break;
4404 }
4405}
4406
da78dbff 4407static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 4408{
1da177e4 4409 struct timer_list *timer = &tp->timer;
1da177e4
LT		 4410 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4411
bcf0bf90 4412 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 4413
4da19633 4414 if (tp->phy_reset_pending(tp)) {
5b0384f4 4415 /*
1da177e4
LT		 4416 * A busy loop could burn quite a few cycles on nowadays CPU.
4417 * Let's delay the execution of the timer for a few ticks.
4418 */
4419 timeout = HZ/10;
4420 goto out_mod_timer;
4421 }
4422
1ef7286e 4423 if (tp->link_ok(tp))
da78dbff 4424 return;
1da177e4 4425
9bb8eeb5 4426 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 4427
4da19633 4428 tp->phy_reset_enable(tp);
1da177e4
LT		 4429
4430out_mod_timer:
4431 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 4432}
4433
4434static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4435{
da78dbff
FR		 4436 if (!test_and_set_bit(flag, tp->wk.flags))
4437 schedule_work(&tp->wk.work);
da78dbff
FR		 4438}
4439
9de36ccf 4440static void rtl8169_phy_timer(struct timer_list *t)
da78dbff 4441{
9de36ccf 4442 struct rtl8169_private *tp = from_timer(tp, t, timer);
da78dbff 4443
98ddf986 4444 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 4445}
4446
ffc46952
FR		 4447DECLARE_RTL_COND(rtl_phy_reset_cond)
4448{
4449 return tp->phy_reset_pending(tp);
4450}
4451
bf793295
FR		 4452static void rtl8169_phy_reset(struct net_device *dev,
4453 struct rtl8169_private *tp)
4454{
4da19633 4455 tp->phy_reset_enable(tp);
ffc46952 4456 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 4457}
4458
2544bfc0
FR		 4459static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4460{
2544bfc0 4461 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
1ef7286e 4462 (RTL_R8(tp, PHYstatus) & TBI_Enable);
2544bfc0
FR		 4463}
4464
4ff96fa6
FR		 4465static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4466{
5615d9f1 4467 rtl_hw_phy_config(dev);
4ff96fa6 4468
77332894
MS		 4469 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4470 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 4471 RTL_W8(tp, 0x82, 0x01);
77332894 4472 }
4ff96fa6 4473
6dccd16b
FR		 4474 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4475
4476 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4477 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4478
bcf0bf90 4479 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6 4480 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 4481 RTL_W8(tp, 0x82, 0x01);
4ff96fa6 4482 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4483 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4484 }
4485
bf793295
FR		 4486 rtl8169_phy_reset(dev, tp);
4487
54405cde 4488 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 4489 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4490 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4491 (tp->mii.supports_gmii ?
4492 ADVERTISED_1000baseT_Half |
4493 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 4494
2544bfc0 4495 if (rtl_tbi_enabled(tp))
bf82c189 4496 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 4497}
4498
773d2021
FR		 4499static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4500{
da78dbff 4501 rtl_lock_work(tp);
773d2021 4502
1ef7286e 4503 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
908ba2bf 4504
1ef7286e
AS		 4505 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4506 RTL_R32(tp, MAC4);
908ba2bf 4507
1ef7286e
AS		 4508 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4509 RTL_R32(tp, MAC0);
908ba2bf 4510
9ecb9aab 4511 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4512 rtl_rar_exgmac_set(tp, addr);
c28aa385 4513
1ef7286e 4514 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
773d2021 4515
da78dbff 4516 rtl_unlock_work(tp);
773d2021
FR		 4517}
4518
4519static int rtl_set_mac_address(struct net_device *dev, void *p)
4520{
4521 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 4522 struct device *d = tp_to_dev(tp);
1f7aa2bc 4523 int ret;
773d2021 4524
1f7aa2bc
HK		 4525 ret = eth_mac_addr(dev, p);
4526 if (ret)
4527 return ret;
773d2021 4528
f51d4a10
CHL		 4529 pm_runtime_get_noresume(d);
4530
4531 if (pm_runtime_active(d))
4532 rtl_rar_set(tp, dev->dev_addr);
4533
4534 pm_runtime_put_noidle(d);
773d2021
FR		 4535
4536 return 0;
4537}
4538
5f787a1a
FR		 4539static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4540{
4541 struct rtl8169_private *tp = netdev_priv(dev);
4542 struct mii_ioctl_data *data = if_mii(ifr);
4543
8b4ab28d
FR		 4544 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4545}
5f787a1a 4546
cecb5fd7
FR		 4547static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4548 struct mii_ioctl_data *data, int cmd)
8b4ab28d 4549{
5f787a1a
FR		 4550 switch (cmd) {
4551 case SIOCGMIIPHY:
4552 data->phy_id = 32; /* Internal PHY */
4553 return 0;
4554
4555 case SIOCGMIIREG:
4da19633 4556 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 4557 return 0;
4558
4559 case SIOCSMIIREG:
4da19633 4560 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 4561 return 0;
4562 }
4563 return -EOPNOTSUPP;
4564}
4565
8b4ab28d
FR		 4566static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4567{
4568 return -EOPNOTSUPP;
4569}
4570
baf63293 4571static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4572{
4573 struct mdio_ops *ops = &tp->mdio_ops;
4574
4575 switch (tp->mac_version) {
4576 case RTL_GIGA_MAC_VER_27:
4577 ops->write = r8168dp_1_mdio_write;
4578 ops->read = r8168dp_1_mdio_read;
4579 break;
e6de30d6 4580 case RTL_GIGA_MAC_VER_28:
4804b3b3 4581 case RTL_GIGA_MAC_VER_31:
e6de30d6 4582 ops->write = r8168dp_2_mdio_write;
4583 ops->read = r8168dp_2_mdio_read;
4584 break;
2a71883c 4585 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
c558386b
HW		 4586 ops->write = r8168g_mdio_write;
4587 ops->read = r8168g_mdio_read;
4588 break;
c0e45c1c 4589 default:
4590 ops->write = r8169_mdio_write;
4591 ops->read = r8169_mdio_read;
4592 break;
4593 }
4594}
4595
e2409d83 4596static void rtl_speed_down(struct rtl8169_private *tp)
4597{
4598 u32 adv;
4599 int lpa;
4600
4601 rtl_writephy(tp, 0x1f, 0x0000);
4602 lpa = rtl_readphy(tp, MII_LPA);
4603
4604 if (lpa & (LPA_10HALF | LPA_10FULL))
4605 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4606 else if (lpa & (LPA_100HALF | LPA_100FULL))
4607 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4608 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4609 else
4610 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4611 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4612 (tp->mii.supports_gmii ?
4613 ADVERTISED_1000baseT_Half |
4614 ADVERTISED_1000baseT_Full : 0);
4615
4616 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4617 adv);
4618}
4619
649b3b8c 4620static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4621{
649b3b8c 4622 switch (tp->mac_version) {
b00e69de
CB		 4623 case RTL_GIGA_MAC_VER_25:
4624 case RTL_GIGA_MAC_VER_26:
649b3b8c 4625 case RTL_GIGA_MAC_VER_29:
4626 case RTL_GIGA_MAC_VER_30:
4627 case RTL_GIGA_MAC_VER_32:
4628 case RTL_GIGA_MAC_VER_33:
4629 case RTL_GIGA_MAC_VER_34:
2a71883c 4630 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4631 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
649b3b8c 4632 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4633 break;
4634 default:
4635 break;
4636 }
4637}
4638
4639static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4640{
fe87bef0 4641 if (!netif_running(tp->dev) || !tp->saved_wolopts)
649b3b8c 4642 return false;
4643
e2409d83 4644 rtl_speed_down(tp);
649b3b8c 4645 rtl_wol_suspend_quirk(tp);
4646
4647 return true;
4648}
4649
065c27c1 4650static void r8168_phy_power_up(struct rtl8169_private *tp)
4651{
4652 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4653 switch (tp->mac_version) {
4654 case RTL_GIGA_MAC_VER_11:
4655 case RTL_GIGA_MAC_VER_12:
2a71883c 4656 case RTL_GIGA_MAC_VER_17 ... RTL_GIGA_MAC_VER_28:
01dc7fec 4657 case RTL_GIGA_MAC_VER_31:
4658 rtl_writephy(tp, 0x0e, 0x0000);
4659 break;
4660 default:
4661 break;
4662 }
065c27c1 4663 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
b2d6cee1
DM		 4664
4665 /* give MAC/PHY some time to resume */
4666 msleep(20);
065c27c1 4667}
4668
4669static void r8168_phy_power_down(struct rtl8169_private *tp)
4670{
4671 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4672 switch (tp->mac_version) {
4673 case RTL_GIGA_MAC_VER_32:
4674 case RTL_GIGA_MAC_VER_33:
beb330a4 4675 case RTL_GIGA_MAC_VER_40:
4676 case RTL_GIGA_MAC_VER_41:
01dc7fec 4677 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4678 break;
4679
4680 case RTL_GIGA_MAC_VER_11:
4681 case RTL_GIGA_MAC_VER_12:
2a71883c 4682 case RTL_GIGA_MAC_VER_17 ... RTL_GIGA_MAC_VER_28:
01dc7fec 4683 case RTL_GIGA_MAC_VER_31:
4684 rtl_writephy(tp, 0x0e, 0x0200);
4685 default:
4686 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4687 break;
4688 }
065c27c1 4689}
4690
4691static void r8168_pll_power_down(struct rtl8169_private *tp)
4692{
9dbe7896 4693 if (r8168_check_dash(tp))
065c27c1 4694 return;
4695
01dc7fec 4696 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4697 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4698 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4699
649b3b8c 4700 if (rtl_wol_pll_power_down(tp))
065c27c1 4701 return;
065c27c1 4702
4703 r8168_phy_power_down(tp);
4704
4705 switch (tp->mac_version) {
2a71883c 4706 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4707 case RTL_GIGA_MAC_VER_37:
4708 case RTL_GIGA_MAC_VER_39:
4709 case RTL_GIGA_MAC_VER_43:
42fde737 4710 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4711 case RTL_GIGA_MAC_VER_45:
4712 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4713 case RTL_GIGA_MAC_VER_47:
4714 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4715 case RTL_GIGA_MAC_VER_50:
4716 case RTL_GIGA_MAC_VER_51:
1ef7286e 4717 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
065c27c1 4718 break;
beb330a4 4719 case RTL_GIGA_MAC_VER_40:
4720 case RTL_GIGA_MAC_VER_41:
935e2218 4721 case RTL_GIGA_MAC_VER_49:
706123d0 4722 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 4723 0xfc000000, ERIAR_EXGMAC);
1ef7286e 4724 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
beb330a4 4725 break;
065c27c1 4726 }
4727}
4728
4729static void r8168_pll_power_up(struct rtl8169_private *tp)
4730{
065c27c1 4731 switch (tp->mac_version) {
2a71883c 4732 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4733 case RTL_GIGA_MAC_VER_37:
4734 case RTL_GIGA_MAC_VER_39:
4735 case RTL_GIGA_MAC_VER_43:
1ef7286e 4736 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
065c27c1 4737 break;
42fde737 4738 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4739 case RTL_GIGA_MAC_VER_45:
4740 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4741 case RTL_GIGA_MAC_VER_47:
4742 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4743 case RTL_GIGA_MAC_VER_50:
4744 case RTL_GIGA_MAC_VER_51:
1ef7286e 4745 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
6e1d0b89 4746 break;
beb330a4 4747 case RTL_GIGA_MAC_VER_40:
4748 case RTL_GIGA_MAC_VER_41:
935e2218 4749 case RTL_GIGA_MAC_VER_49:
1ef7286e 4750 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
706123d0 4751 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 4752 0x00000000, ERIAR_EXGMAC);
4753 break;
065c27c1 4754 }
4755
4756 r8168_phy_power_up(tp);
4757}
4758
065c27c1 4759static void rtl_pll_power_down(struct rtl8169_private *tp)
4760{
4f447d29
HK		 4761 switch (tp->mac_version) {
4762 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4763 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4764 break;
4765 default:
4766 r8168_pll_power_down(tp);
4767 }
065c27c1 4768}
4769
4770static void rtl_pll_power_up(struct rtl8169_private *tp)
4771{
065c27c1 4772 switch (tp->mac_version) {
4f447d29
HK		 4773 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4774 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
065c27c1 4775 break;
065c27c1 4776 default:
4f447d29 4777 r8168_pll_power_up(tp);
065c27c1 4778 }
4779}
4780
e542a226
HW		 4781static void rtl_init_rxcfg(struct rtl8169_private *tp)
4782{
e542a226 4783 switch (tp->mac_version) {
2a71883c
HK		 4784 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4785 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
1ef7286e 4786 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
e542a226 4787 break;
2a71883c 4788 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
eb2dc35d 4789 case RTL_GIGA_MAC_VER_34:
3ced8c95 4790 case RTL_GIGA_MAC_VER_35:
1ef7286e 4791 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
e542a226 4792 break;
2a71883c 4793 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4794 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 4795 break;
e542a226 4796 default:
1ef7286e 4797 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
e542a226
HW		 4798 break;
4799 }
4800}
4801
92fc43b4
HW		 4802static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4803{
9fba0812 4804 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4805}
4806
d58d46b5
FR		 4807static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4808{
eda40b8c
HK		 4809 if (tp->jumbo_ops.enable) {
4810 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4811 tp->jumbo_ops.enable(tp);
4812 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4813 }
d58d46b5
FR		 4814}
4815
4816static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4817{
eda40b8c
HK		 4818 if (tp->jumbo_ops.disable) {
4819 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4820 tp->jumbo_ops.disable(tp);
4821 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4822 }
d58d46b5
FR		 4823}
4824
4825static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4826{
1ef7286e
AS		 4827 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4828 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
cb73200c 4829 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4830}
4831
4832static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4833{
1ef7286e
AS		 4834 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4835 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
8d98aa39 4836 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4837}
4838
4839static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4840{
1ef7286e 4841 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
d58d46b5
FR		 4842}
4843
4844static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4845{
1ef7286e 4846 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
d58d46b5
FR		 4847}
4848
4849static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4850{
1ef7286e
AS		 4851 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4852 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4853 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
cb73200c 4854 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4855}
4856
4857static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4858{
1ef7286e
AS		 4859 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4860 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4861 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
8d98aa39 4862 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4863}
4864
4865static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4866{
cb73200c 4867 rtl_tx_performance_tweak(tp,
f65d539c 4868 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4869}
4870
4871static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4872{
cb73200c 4873 rtl_tx_performance_tweak(tp,
8d98aa39 4874 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4875}
4876
4877static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4878{
d58d46b5
FR		 4879 r8168b_0_hw_jumbo_enable(tp);
4880
1ef7286e 4881 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
d58d46b5
FR		 4882}
4883
4884static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4885{
d58d46b5
FR		 4886 r8168b_0_hw_jumbo_disable(tp);
4887
1ef7286e 4888 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
d58d46b5
FR		 4889}
4890
baf63293 4891static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4892{
4893 struct jumbo_ops *ops = &tp->jumbo_ops;
4894
4895 switch (tp->mac_version) {
4896 case RTL_GIGA_MAC_VER_11:
4897 ops->disable = r8168b_0_hw_jumbo_disable;
4898 ops->enable = r8168b_0_hw_jumbo_enable;
4899 break;
4900 case RTL_GIGA_MAC_VER_12:
4901 case RTL_GIGA_MAC_VER_17:
4902 ops->disable = r8168b_1_hw_jumbo_disable;
4903 ops->enable = r8168b_1_hw_jumbo_enable;
4904 break;
4905 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4906 case RTL_GIGA_MAC_VER_19:
4907 case RTL_GIGA_MAC_VER_20:
4908 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4909 case RTL_GIGA_MAC_VER_22:
4910 case RTL_GIGA_MAC_VER_23:
4911 case RTL_GIGA_MAC_VER_24:
4912 case RTL_GIGA_MAC_VER_25:
4913 case RTL_GIGA_MAC_VER_26:
4914 ops->disable = r8168c_hw_jumbo_disable;
4915 ops->enable = r8168c_hw_jumbo_enable;
4916 break;
4917 case RTL_GIGA_MAC_VER_27:
4918 case RTL_GIGA_MAC_VER_28:
4919 ops->disable = r8168dp_hw_jumbo_disable;
4920 ops->enable = r8168dp_hw_jumbo_enable;
4921 break;
4922 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4923 case RTL_GIGA_MAC_VER_32:
4924 case RTL_GIGA_MAC_VER_33:
4925 case RTL_GIGA_MAC_VER_34:
4926 ops->disable = r8168e_hw_jumbo_disable;
4927 ops->enable = r8168e_hw_jumbo_enable;
4928 break;
4929
4930 /*
4931 * No action needed for jumbo frames with 8169.
4932 * No jumbo for 810x at all.
4933 */
2a71883c 4934 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 4935 default:
4936 ops->disable = NULL;
4937 ops->enable = NULL;
4938 break;
4939 }
4940}
4941
ffc46952
FR		 4942DECLARE_RTL_COND(rtl_chipcmd_cond)
4943{
1ef7286e 4944 return RTL_R8(tp, ChipCmd) & CmdReset;
ffc46952
FR		 4945}
4946
6f43adc8
FR		 4947static void rtl_hw_reset(struct rtl8169_private *tp)
4948{
1ef7286e 4949 RTL_W8(tp, ChipCmd, CmdReset);
6f43adc8 4950
ffc46952 4951 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4952}
4953
b6ffd97f 4954static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4955{
b6ffd97f
FR		 4956 struct rtl_fw *rtl_fw;
4957 const char *name;
4958 int rc = -ENOMEM;
953a12cc 4959
b6ffd97f
FR		 4960 name = rtl_lookup_firmware_name(tp);
4961 if (!name)
4962 goto out_no_firmware;
953a12cc 4963
b6ffd97f
FR		 4964 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4965 if (!rtl_fw)
4966 goto err_warn;
31bd204f 4967
1e1205b7 4968 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
b6ffd97f
FR		 4969 if (rc < 0)
4970 goto err_free;
4971
fd112f2e
FR		 4972 rc = rtl_check_firmware(tp, rtl_fw);
4973 if (rc < 0)
4974 goto err_release_firmware;
4975
b6ffd97f
FR		 4976 tp->rtl_fw = rtl_fw;
4977out:
4978 return;
4979
fd112f2e
FR		 4980err_release_firmware:
4981 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4982err_free:
4983 kfree(rtl_fw);
4984err_warn:
4985 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4986 name, rc);
4987out_no_firmware:
4988 tp->rtl_fw = NULL;
4989 goto out;
4990}
4991
4992static void rtl_request_firmware(struct rtl8169_private *tp)
4993{
4994 if (IS_ERR(tp->rtl_fw))
4995 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4996}
4997
92fc43b4
HW		 4998static void rtl_rx_close(struct rtl8169_private *tp)
4999{
1ef7286e 5000 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 5001}
5002
ffc46952
FR		 5003DECLARE_RTL_COND(rtl_npq_cond)
5004{
1ef7286e 5005 return RTL_R8(tp, TxPoll) & NPQ;
ffc46952
FR		 5006}
5007
5008DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5009{
1ef7286e 5010 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
ffc46952
FR		 5011}
5012
e6de30d6 5013static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4
LT		 5014{
5015 /* Disable interrupts */
811fd301 5016 rtl8169_irq_mask_and_ack(tp);
1da177e4 5017
92fc43b4
HW		 5018 rtl_rx_close(tp);
5019
b2d43e6e
HK		 5020 switch (tp->mac_version) {
5021 case RTL_GIGA_MAC_VER_27:
5022 case RTL_GIGA_MAC_VER_28:
5023 case RTL_GIGA_MAC_VER_31:
ffc46952 5024 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
b2d43e6e
HK		 5025 break;
5026 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
5027 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 5028 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
ffc46952 5029 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
b2d43e6e
HK		 5030 break;
5031 default:
1ef7286e 5032 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
92fc43b4 5033 udelay(100);
b2d43e6e 5034 break;
e6de30d6 5035 }
5036
92fc43b4 5037 rtl_hw_reset(tp);
1da177e4
LT		 5038}
5039
7f796d83 5040static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6 5041{
9cb427b6 5042 /* Set DMA burst size and Interframe Gap Time */
1ef7286e 5043 RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
9cb427b6
FR		 5044 (InterFrameGap << TxInterFrameGapShift));
5045}
5046
4fd48c4a 5047static void rtl_set_rx_max_size(struct rtl8169_private *tp)
1da177e4 5048{
4fd48c4a
HK		 5049 /* Low hurts. Let's disable the filtering. */
5050 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
07ce4064
FR		 5051}
5052
1ef7286e 5053static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
7f796d83
FR		 5054{
5055 /*
5056 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5057 * register to be written before TxDescAddrLow to work.
5058 * Switching from MMIO to I/O access fixes the issue as well.
5059 */
1ef7286e
AS		 5060 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5061 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5062 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5063 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 5064}
5065
1ef7286e 5066static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
6dccd16b 5067{
3744100e 5068 static const struct rtl_cfg2_info {
6dccd16b
FR		 5069 u32 mac_version;
5070 u32 clk;
5071 u32 val;
5072 } cfg2_info [] = {
5073 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5074 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5075 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5076 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 5077 };
5078 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 5079 unsigned int i;
5080 u32 clk;
5081
1ef7286e 5082 clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
cadf1855 5083 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b 5084 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1ef7286e 5085 RTL_W32(tp, 0x7c, p->val);
6dccd16b
FR		 5086 break;
5087 }
5088 }
5089}
5090
e6b763ea
FR		 5091static void rtl_set_rx_mode(struct net_device *dev)
5092{
5093 struct rtl8169_private *tp = netdev_priv(dev);
e6b763ea
FR		 5094 u32 mc_filter[2]; /* Multicast hash filter */
5095 int rx_mode;
5096 u32 tmp = 0;
5097
5098 if (dev->flags & IFF_PROMISC) {
5099 /* Unconditionally log net taps. */
5100 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5101 rx_mode =
5102 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5103 AcceptAllPhys;
5104 mc_filter[1] = mc_filter[0] = 0xffffffff;
5105 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5106 (dev->flags & IFF_ALLMULTI)) {
5107 /* Too many to filter perfectly -- accept all multicasts. */
5108 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5109 mc_filter[1] = mc_filter[0] = 0xffffffff;
5110 } else {
5111 struct netdev_hw_addr *ha;
5112
5113 rx_mode = AcceptBroadcast | AcceptMyPhys;
5114 mc_filter[1] = mc_filter[0] = 0;
5115 netdev_for_each_mc_addr(ha, dev) {
5116 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5117 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5118 rx_mode |= AcceptMulticast;
5119 }
5120 }
5121
5122 if (dev->features & NETIF_F_RXALL)
5123 rx_mode |= (AcceptErr | AcceptRunt);
5124
1ef7286e 5125 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
e6b763ea
FR		 5126
5127 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5128 u32 data = mc_filter[0];
5129
5130 mc_filter[0] = swab32(mc_filter[1]);
5131 mc_filter[1] = swab32(data);
5132 }
5133
0481776b
NW		 5134 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5135 mc_filter[1] = mc_filter[0] = 0xffffffff;
5136
1ef7286e
AS		 5137 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
5138 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
e6b763ea 5139
1ef7286e 5140 RTL_W32(tp, RxConfig, tmp);
e6b763ea
FR		 5141}
5142
52f8560e
HK		 5143static void rtl_hw_start(struct rtl8169_private *tp)
5144{
5145 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
5146
5147 tp->hw_start(tp);
5148
5149 rtl_set_rx_max_size(tp);
5150 rtl_set_rx_tx_desc_registers(tp);
5151 rtl_set_rx_tx_config_registers(tp);
5152 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
5153
5154 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5155 RTL_R8(tp, IntrMask);
5156 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5157 rtl_set_rx_mode(tp->dev);
5158 /* no early-rx interrupts */
5159 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
5160 rtl_irq_enable_all(tp);
5161}
5162
61cb532d 5163static void rtl_hw_start_8169(struct rtl8169_private *tp)
07ce4064 5164{
0ae0974e 5165 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
61cb532d 5166 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
9cb427b6 5167
1ef7286e 5168 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
1da177e4 5169
0ae0974e 5170 tp->cp_cmd |= PCIMulRW;
1da177e4 5171
cecb5fd7
FR		 5172 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5173 tp->mac_version == RTL_GIGA_MAC_VER_03) {
05b9687b 5174 dprintk("Set MAC Reg C+CR Offset 0xe0. "
1da177e4 5175 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 5176 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 5177 }
5178
1ef7286e 5179 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
bcf0bf90 5180
1ef7286e 5181 rtl8169_set_magic_reg(tp, tp->mac_version);
6dccd16b 5182
1da177e4
LT		 5183 /*
5184 * Undocumented corner. Supposedly:
5185 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5186 */
1ef7286e 5187 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4 5188
1ef7286e 5189 RTL_W32(tp, RxMissed, 0);
07ce4064 5190}
1da177e4 5191
ffc46952
FR		 5192DECLARE_RTL_COND(rtl_csiar_cond)
5193{
1ef7286e 5194 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
ffc46952
FR		 5195}
5196
ff1d7331 5197static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
beb1fe18 5198{
ff1d7331 5199 u32 func = PCI_FUNC(tp->pci_dev->devfn);
beb1fe18 5200
1ef7286e
AS		 5201 RTL_W32(tp, CSIDR, value);
5202 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
ff1d7331 5203 CSIAR_BYTE_ENABLE | func << 16);
7e18dca1 5204
ffc46952 5205 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 5206}
5207
ff1d7331 5208static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 5209{
ff1d7331
HK		 5210 u32 func = PCI_FUNC(tp->pci_dev->devfn);
5211
5212 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
5213 CSIAR_BYTE_ENABLE);
7e18dca1 5214
ffc46952 5215 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 5216 RTL_R32(tp, CSIDR) : ~0;
7e18dca1
HW		 5217}
5218
ff1d7331 5219static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
45dd95c4 5220{
ff1d7331
HK		 5221 struct pci_dev *pdev = tp->pci_dev;
5222 u32 csi;
45dd95c4 5223
ff1d7331
HK		 5224 /* According to Realtek the value at config space address 0x070f
5225 * controls the L0s/L1 entrance latency. We try standard ECAM access
5226 * first and if it fails fall back to CSI.
5227 */
5228 if (pdev->cfg_size > 0x070f &&
5229 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
5230 return;
5231
5232 netdev_notice_once(tp->dev,
5233 "No native access to PCI extended config space, falling back to CSI\n");
5234 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5235 rtl_csi_write(tp, 0x070c, csi | val << 24);
45dd95c4 5236}
5237
f37658da 5238static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
beb1fe18 5239{
ff1d7331 5240 rtl_csi_access_enable(tp, 0x27);
dacf8154
FR		 5241}
5242
5243struct ephy_info {
5244 unsigned int offset;
5245 u16 mask;
5246 u16 bits;
5247};
5248
fdf6fc06
FR		 5249static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5250 int len)
dacf8154
FR		 5251{
5252 u16 w;
5253
5254 while (len-- > 0) {
fdf6fc06
FR		 5255 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5256 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 5257 e++;
5258 }
5259}
5260
73c86ee3 5261static void rtl_disable_clock_request(struct rtl8169_private *tp)
b726e493 5262{
73c86ee3 5263 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 5264 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 5265}
5266
73c86ee3 5267static void rtl_enable_clock_request(struct rtl8169_private *tp)
e6de30d6 5268{
73c86ee3 5269 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 5270 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 5271}
5272
b51ecea8 5273static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5274{
b51ecea8 5275 u8 data;
5276
1ef7286e 5277 data = RTL_R8(tp, Config3);
b51ecea8 5278
5279 if (enable)
5280 data |= Rdy_to_L23;
5281 else
5282 data &= ~Rdy_to_L23;
5283
1ef7286e 5284 RTL_W8(tp, Config3, data);
b51ecea8 5285}
5286
a99790bf
KHF		 5287static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
5288{
5289 if (enable) {
5290 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
5291 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
5292 } else {
5293 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5294 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5295 }
5296}
5297
beb1fe18 5298static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 5299{
1ef7286e 5300 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 5301
12d42c50 5302 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 5303 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
b726e493 5304
faf1e785 5305 if (tp->dev->mtu <= ETH_DATA_LEN) {
8d98aa39 5306 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
faf1e785 5307 PCI_EXP_DEVCTL_NOSNOOP_EN);
5308 }
219a1e9d
FR		 5309}
5310
beb1fe18 5311static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 5312{
beb1fe18 5313 rtl_hw_start_8168bb(tp);
b726e493 5314
1ef7286e 5315 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
b726e493 5316
1ef7286e 5317 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
219a1e9d
FR		 5318}
5319
beb1fe18 5320static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 5321{
1ef7286e 5322 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
b726e493 5323
1ef7286e 5324 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 5325
faf1e785 5326 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5327 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
b726e493 5328
73c86ee3 5329 rtl_disable_clock_request(tp);
b726e493 5330
12d42c50 5331 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 5332 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
219a1e9d
FR		 5333}
5334
beb1fe18 5335static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 5336{
350f7596 5337 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 5338 { 0x01, 0, 0x0001 },
5339 { 0x02, 0x0800, 0x1000 },
5340 { 0x03, 0, 0x0042 },
5341 { 0x06, 0x0080, 0x0000 },
5342 { 0x07, 0, 0x2000 }
5343 };
5344
f37658da 5345 rtl_set_def_aspm_entry_latency(tp);
b726e493 5346
fdf6fc06 5347 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 5348
beb1fe18 5349 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5350}
5351
beb1fe18 5352static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 5353{
f37658da 5354 rtl_set_def_aspm_entry_latency(tp);
ef3386f0 5355
1ef7286e 5356 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
ef3386f0 5357
faf1e785 5358 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5359 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
ef3386f0 5360
12d42c50 5361 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 5362 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
ef3386f0
FR		 5363}
5364
beb1fe18 5365static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 5366{
f37658da 5367 rtl_set_def_aspm_entry_latency(tp);
7f3e3d3a 5368
1ef7286e 5369 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
7f3e3d3a
FR		 5370
5371 /* Magic. */
1ef7286e 5372 RTL_W8(tp, DBG_REG, 0x20);
7f3e3d3a 5373
1ef7286e 5374 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
7f3e3d3a 5375
faf1e785 5376 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5377 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7f3e3d3a 5378
12d42c50 5379 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 5380 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
7f3e3d3a
FR		 5381}
5382
beb1fe18 5383static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 5384{
350f7596 5385 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 5386 { 0x02, 0x0800, 0x1000 },
5387 { 0x03, 0, 0x0002 },
5388 { 0x06, 0x0080, 0x0000 }
5389 };
5390
f37658da 5391 rtl_set_def_aspm_entry_latency(tp);
b726e493 5392
1ef7286e 5393 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
b726e493 5394
fdf6fc06 5395 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 5396
beb1fe18 5397 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5398}
5399
beb1fe18 5400static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 5401{
350f7596 5402 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 5403 { 0x01, 0, 0x0001 },
5404 { 0x03, 0x0400, 0x0220 }
5405 };
5406
f37658da 5407 rtl_set_def_aspm_entry_latency(tp);
b726e493 5408
fdf6fc06 5409 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 5410
beb1fe18 5411 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5412}
5413
beb1fe18 5414static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 5415{
beb1fe18 5416 rtl_hw_start_8168c_2(tp);
197ff761
FR		 5417}
5418
beb1fe18 5419static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 5420{
f37658da 5421 rtl_set_def_aspm_entry_latency(tp);
6fb07058 5422
beb1fe18 5423 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 5424}
5425
beb1fe18 5426static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 5427{
f37658da 5428 rtl_set_def_aspm_entry_latency(tp);
5b538df9 5429
73c86ee3 5430 rtl_disable_clock_request(tp);
5b538df9 5431
1ef7286e 5432 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5b538df9 5433
faf1e785 5434 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5435 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5b538df9 5436
12d42c50 5437 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 5438 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5b538df9
FR		 5439}
5440
beb1fe18 5441static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 5442{
f37658da 5443 rtl_set_def_aspm_entry_latency(tp);
4804b3b3 5444
faf1e785 5445 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5446 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4804b3b3 5447
1ef7286e 5448 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4804b3b3 5449
73c86ee3 5450 rtl_disable_clock_request(tp);
4804b3b3 5451}
5452
beb1fe18 5453static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 5454{
5455 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 5456 { 0x0b, 0x0000, 0x0048 },
5457 { 0x19, 0x0020, 0x0050 },
5458 { 0x0c, 0x0100, 0x0020 }
e6de30d6 5459 };
e6de30d6 5460
f37658da 5461 rtl_set_def_aspm_entry_latency(tp);
e6de30d6 5462
8d98aa39 5463 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
e6de30d6 5464
1ef7286e 5465 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
e6de30d6 5466
1016a4a1 5467 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
e6de30d6 5468
73c86ee3 5469 rtl_enable_clock_request(tp);
e6de30d6 5470}
5471
beb1fe18 5472static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 5473{
70090424 5474 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5475 { 0x00, 0x0200, 0x0100 },
5476 { 0x00, 0x0000, 0x0004 },
5477 { 0x06, 0x0002, 0x0001 },
5478 { 0x06, 0x0000, 0x0030 },
5479 { 0x07, 0x0000, 0x2000 },
5480 { 0x00, 0x0000, 0x0020 },
5481 { 0x03, 0x5800, 0x2000 },
5482 { 0x03, 0x0000, 0x0001 },
5483 { 0x01, 0x0800, 0x1000 },
5484 { 0x07, 0x0000, 0x4000 },
5485 { 0x1e, 0x0000, 0x2000 },
5486 { 0x19, 0xffff, 0xfe6c },
5487 { 0x0a, 0x0000, 0x0040 }
5488 };
5489
f37658da 5490 rtl_set_def_aspm_entry_latency(tp);
01dc7fec 5491
fdf6fc06 5492 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5493
faf1e785 5494 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5495 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
01dc7fec 5496
1ef7286e 5497 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
01dc7fec 5498
73c86ee3 5499 rtl_disable_clock_request(tp);
01dc7fec 5500
5501 /* Reset tx FIFO pointer */
1ef7286e
AS		 5502 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5503 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
01dc7fec 5504
1ef7286e 5505 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
01dc7fec 5506}
5507
beb1fe18 5508static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424
HW		 5509{
5510 static const struct ephy_info e_info_8168e_2[] = {
5511 { 0x09, 0x0000, 0x0080 },
5512 { 0x19, 0x0000, 0x0224 }
5513 };
5514
f37658da 5515 rtl_set_def_aspm_entry_latency(tp);
70090424 5516
fdf6fc06 5517 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5518
faf1e785 5519 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5520 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
70090424 5521
fdf6fc06
FR		 5522 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5523 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5524 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5525 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5526 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5527 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 5528 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5529 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5530
1ef7286e 5531 RTL_W8(tp, MaxTxPacketSize, EarlySize);
70090424 5532
73c86ee3 5533 rtl_disable_clock_request(tp);
4521e1a9 5534
1ef7286e
AS		 5535 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5536 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
70090424
HW		 5537
5538 /* Adjust EEE LED frequency */
1ef7286e 5539 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
70090424 5540
1ef7286e
AS		 5541 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5542 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5543 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
aa1e7d2c
HK		 5544
5545 rtl_hw_aspm_clkreq_enable(tp, true);
70090424
HW		 5546}
5547
5f886e08 5548static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5549{
f37658da 5550 rtl_set_def_aspm_entry_latency(tp);
c2218925 5551
8d98aa39 5552 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c2218925 5553
fdf6fc06
FR		 5554 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5555 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5556 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5557 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 5558 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5559 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5560 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5561 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5562 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5563 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925 5564
1ef7286e 5565 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c2218925 5566
73c86ee3 5567 rtl_disable_clock_request(tp);
4521e1a9 5568
1ef7286e
AS		 5569 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5570 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5571 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5572 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5573 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
c2218925
HW		 5574}
5575
5f886e08
HW		 5576static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5577{
5f886e08
HW		 5578 static const struct ephy_info e_info_8168f_1[] = {
5579 { 0x06, 0x00c0, 0x0020 },
5580 { 0x08, 0x0001, 0x0002 },
5581 { 0x09, 0x0000, 0x0080 },
5582 { 0x19, 0x0000, 0x0224 }
5583 };
5584
5585 rtl_hw_start_8168f(tp);
5586
fdf6fc06 5587 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5588
706123d0 5589 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5590
5591 /* Adjust EEE LED frequency */
1ef7286e 5592 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5f886e08
HW		 5593}
5594
b3d7b2f2
HW		 5595static void rtl_hw_start_8411(struct rtl8169_private *tp)
5596{
b3d7b2f2
HW		 5597 static const struct ephy_info e_info_8168f_1[] = {
5598 { 0x06, 0x00c0, 0x0020 },
5599 { 0x0f, 0xffff, 0x5200 },
5600 { 0x1e, 0x0000, 0x4000 },
5601 { 0x19, 0x0000, 0x0224 }
5602 };
5603
5604 rtl_hw_start_8168f(tp);
b51ecea8 5605 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 5606
fdf6fc06 5607 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5608
706123d0 5609 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5610}
5611
5fbea337 5612static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b 5613{
1ef7286e 5614 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
beb330a4 5615
c558386b
HW		 5616 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5617 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5618 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5619 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5620
f37658da 5621 rtl_set_def_aspm_entry_latency(tp);
c558386b 5622
8d98aa39 5623 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c558386b 5624
706123d0
CHL		 5625 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5626 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5627 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 5628
1ef7286e
AS		 5629 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5630 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c558386b
HW		 5631
5632 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5633 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5634
5635 /* Adjust EEE LED frequency */
1ef7286e 5636 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
c558386b 5637
706123d0
CHL		 5638 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5639 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 5640
5641 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 5642}
5643
5fbea337
CHL		 5644static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5645{
5fbea337
CHL		 5646 static const struct ephy_info e_info_8168g_1[] = {
5647 { 0x00, 0x0000, 0x0008 },
5648 { 0x0c, 0x37d0, 0x0820 },
5649 { 0x1e, 0x0000, 0x0001 },
5650 { 0x19, 0x8000, 0x0000 }
5651 };
5652
5653 rtl_hw_start_8168g(tp);
5654
5655 /* disable aspm and clock request before access ephy */
a99790bf 5656 rtl_hw_aspm_clkreq_enable(tp, false);
5fbea337 5657 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
a99790bf 5658 rtl_hw_aspm_clkreq_enable(tp, true);
5fbea337
CHL		 5659}
5660
57538c4a 5661static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5662{
57538c4a 5663 static const struct ephy_info e_info_8168g_2[] = {
5664 { 0x00, 0x0000, 0x0008 },
5665 { 0x0c, 0x3df0, 0x0200 },
5666 { 0x19, 0xffff, 0xfc00 },
5667 { 0x1e, 0xffff, 0x20eb }
5668 };
5669
5fbea337 5670 rtl_hw_start_8168g(tp);
57538c4a 5671
5672 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 5673 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5674 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
57538c4a 5675 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5676}
5677
45dd95c4 5678static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5679{
45dd95c4 5680 static const struct ephy_info e_info_8411_2[] = {
5681 { 0x00, 0x0000, 0x0008 },
5682 { 0x0c, 0x3df0, 0x0200 },
5683 { 0x0f, 0xffff, 0x5200 },
5684 { 0x19, 0x0020, 0x0000 },
5685 { 0x1e, 0x0000, 0x2000 }
5686 };
5687
5fbea337 5688 rtl_hw_start_8168g(tp);
45dd95c4 5689
5690 /* disable aspm and clock request before access ephy */
a99790bf 5691 rtl_hw_aspm_clkreq_enable(tp, false);
45dd95c4 5692 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
a99790bf 5693 rtl_hw_aspm_clkreq_enable(tp, true);
45dd95c4 5694}
5695
6e1d0b89
CHL		 5696static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5697{
72521ea0 5698 int rg_saw_cnt;
6e1d0b89
CHL		 5699 u32 data;
5700 static const struct ephy_info e_info_8168h_1[] = {
5701 { 0x1e, 0x0800, 0x0001 },
5702 { 0x1d, 0x0000, 0x0800 },
5703 { 0x05, 0xffff, 0x2089 },
5704 { 0x06, 0xffff, 0x5881 },
5705 { 0x04, 0xffff, 0x154a },
5706 { 0x01, 0xffff, 0x068b }
5707 };
5708
5709 /* disable aspm and clock request before access ephy */
a99790bf 5710 rtl_hw_aspm_clkreq_enable(tp, false);
6e1d0b89
CHL		 5711 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5712
1ef7286e 5713 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6e1d0b89
CHL		 5714
5715 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5716 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5717 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5718 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5719
f37658da 5720 rtl_set_def_aspm_entry_latency(tp);
6e1d0b89 5721
8d98aa39 5722 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6e1d0b89 5723
706123d0
CHL		 5724 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5725 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 5726
706123d0 5727 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 5728
706123d0 5729 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 5730
5731 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5732
1ef7286e
AS		 5733 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5734 RTL_W8(tp, MaxTxPacketSize, EarlySize);
6e1d0b89
CHL		 5735
5736 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5737 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5738
5739 /* Adjust EEE LED frequency */
1ef7286e 5740 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6e1d0b89 5741
1ef7286e
AS		 5742 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5743 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89 5744
1ef7286e 5745 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6e1d0b89 5746
706123d0 5747 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 5748
5749 rtl_pcie_state_l2l3_enable(tp, false);
5750
5751 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 5752 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 5753 rtl_writephy(tp, 0x1f, 0x0000);
5754 if (rg_saw_cnt > 0) {
5755 u16 sw_cnt_1ms_ini;
5756
5757 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5758 sw_cnt_1ms_ini &= 0x0fff;
5759 data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec0 5760 data &= ~0x0fff;
6e1d0b89
CHL		 5761 data |= sw_cnt_1ms_ini;
5762 r8168_mac_ocp_write(tp, 0xd412, data);
5763 }
5764
5765 data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec0
CHL		 5766 data &= ~0xf0;
5767 data |= 0x70;
6e1d0b89
CHL		 5768 r8168_mac_ocp_write(tp, 0xe056, data);
5769
5770 data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec0
CHL		 5771 data &= ~0x6000;
5772 data |= 0x8008;
6e1d0b89
CHL		 5773 r8168_mac_ocp_write(tp, 0xe052, data);
5774
5775 data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec0 5776 data &= ~0x01ff;
6e1d0b89
CHL		 5777 data |= 0x017f;
5778 r8168_mac_ocp_write(tp, 0xe0d6, data);
5779
5780 data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec0 5781 data &= ~0x0fff;
6e1d0b89
CHL		 5782 data |= 0x047f;
5783 r8168_mac_ocp_write(tp, 0xd420, data);
5784
5785 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5786 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5787 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5788 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
a99790bf
KHF		 5789
5790 rtl_hw_aspm_clkreq_enable(tp, true);
6e1d0b89
CHL		 5791}
5792
935e2218
CHL		 5793static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5794{
003609da
CHL		 5795 rtl8168ep_stop_cmac(tp);
5796
1ef7286e 5797 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
935e2218
CHL		 5798
5799 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5800 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5801 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5802 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5803
f37658da 5804 rtl_set_def_aspm_entry_latency(tp);
935e2218 5805
8d98aa39 5806 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
935e2218
CHL		 5807
5808 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5809 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5810
5811 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5812
5813 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5814
1ef7286e
AS		 5815 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5816 RTL_W8(tp, MaxTxPacketSize, EarlySize);
935e2218
CHL		 5817
5818 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5819 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5820
5821 /* Adjust EEE LED frequency */
1ef7286e 5822 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
935e2218
CHL		 5823
5824 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5825
1ef7286e 5826 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
935e2218
CHL		 5827
5828 rtl_pcie_state_l2l3_enable(tp, false);
5829}
5830
5831static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5832{
935e2218
CHL		 5833 static const struct ephy_info e_info_8168ep_1[] = {
5834 { 0x00, 0xffff, 0x10ab },
5835 { 0x06, 0xffff, 0xf030 },
5836 { 0x08, 0xffff, 0x2006 },
5837 { 0x0d, 0xffff, 0x1666 },
5838 { 0x0c, 0x3ff0, 0x0000 }
5839 };
5840
5841 /* disable aspm and clock request before access ephy */
a99790bf 5842 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5843 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5844
5845 rtl_hw_start_8168ep(tp);
a99790bf
KHF		 5846
5847 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5848}
5849
5850static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5851{
935e2218
CHL		 5852 static const struct ephy_info e_info_8168ep_2[] = {
5853 { 0x00, 0xffff, 0x10a3 },
5854 { 0x19, 0xffff, 0xfc00 },
5855 { 0x1e, 0xffff, 0x20ea }
5856 };
5857
5858 /* disable aspm and clock request before access ephy */
a99790bf 5859 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5860 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5861
5862 rtl_hw_start_8168ep(tp);
5863
1ef7286e
AS		 5864 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5865 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
a99790bf
KHF		 5866
5867 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5868}
5869
5870static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5871{
935e2218
CHL		 5872 u32 data;
5873 static const struct ephy_info e_info_8168ep_3[] = {
5874 { 0x00, 0xffff, 0x10a3 },
5875 { 0x19, 0xffff, 0x7c00 },
5876 { 0x1e, 0xffff, 0x20eb },
5877 { 0x0d, 0xffff, 0x1666 }
5878 };
5879
5880 /* disable aspm and clock request before access ephy */
a99790bf 5881 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5882 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5883
5884 rtl_hw_start_8168ep(tp);
5885
1ef7286e
AS		 5886 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5887 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 5888
5889 data = r8168_mac_ocp_read(tp, 0xd3e2);
5890 data &= 0xf000;
5891 data |= 0x0271;
5892 r8168_mac_ocp_write(tp, 0xd3e2, data);
5893
5894 data = r8168_mac_ocp_read(tp, 0xd3e4);
5895 data &= 0xff00;
5896 r8168_mac_ocp_write(tp, 0xd3e4, data);
5897
5898 data = r8168_mac_ocp_read(tp, 0xe860);
5899 data |= 0x0080;
5900 r8168_mac_ocp_write(tp, 0xe860, data);
a99790bf
KHF		 5901
5902 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5903}
5904
61cb532d 5905static void rtl_hw_start_8168(struct rtl8169_private *tp)
07ce4064 5906{
1ef7286e 5907 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
2dd99530 5908
0ae0974e
HK		 5909 tp->cp_cmd &= ~INTT_MASK;
5910 tp->cp_cmd |= PktCntrDisable | INTT_1;
1ef7286e 5911 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2dd99530 5912
1ef7286e 5913 RTL_W16(tp, IntrMitigate, 0x5151);
2dd99530 5914
0e485150 5915 /* Work around for RxFIFO overflow. */
811fd301 5916 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5917 tp->event_slow |= RxFIFOOver | PCSTimeout;
5918 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5919 }
5920
219a1e9d
FR		 5921 switch (tp->mac_version) {
5922 case RTL_GIGA_MAC_VER_11:
beb1fe18 5923 rtl_hw_start_8168bb(tp);
4804b3b3 5924 break;
219a1e9d
FR		 5925
5926 case RTL_GIGA_MAC_VER_12:
5927 case RTL_GIGA_MAC_VER_17:
beb1fe18 5928 rtl_hw_start_8168bef(tp);
4804b3b3 5929 break;
219a1e9d
FR		 5930
5931 case RTL_GIGA_MAC_VER_18:
beb1fe18 5932 rtl_hw_start_8168cp_1(tp);
4804b3b3 5933 break;
219a1e9d
FR		 5934
5935 case RTL_GIGA_MAC_VER_19:
beb1fe18 5936 rtl_hw_start_8168c_1(tp);
4804b3b3 5937 break;
219a1e9d
FR		 5938
5939 case RTL_GIGA_MAC_VER_20:
beb1fe18 5940 rtl_hw_start_8168c_2(tp);
4804b3b3 5941 break;
219a1e9d 5942
197ff761 5943 case RTL_GIGA_MAC_VER_21:
beb1fe18 5944 rtl_hw_start_8168c_3(tp);
4804b3b3 5945 break;
197ff761 5946
6fb07058 5947 case RTL_GIGA_MAC_VER_22:
beb1fe18 5948 rtl_hw_start_8168c_4(tp);
4804b3b3 5949 break;
6fb07058 5950
ef3386f0 5951 case RTL_GIGA_MAC_VER_23:
beb1fe18 5952 rtl_hw_start_8168cp_2(tp);
4804b3b3 5953 break;
ef3386f0 5954
7f3e3d3a 5955 case RTL_GIGA_MAC_VER_24:
beb1fe18 5956 rtl_hw_start_8168cp_3(tp);
4804b3b3 5957 break;
7f3e3d3a 5958
5b538df9 5959 case RTL_GIGA_MAC_VER_25:
daf9df6d 5960 case RTL_GIGA_MAC_VER_26:
5961 case RTL_GIGA_MAC_VER_27:
beb1fe18 5962 rtl_hw_start_8168d(tp);
4804b3b3 5963 break;
5b538df9 5964
e6de30d6 5965 case RTL_GIGA_MAC_VER_28:
beb1fe18 5966 rtl_hw_start_8168d_4(tp);
4804b3b3 5967 break;
cecb5fd7 5968
4804b3b3 5969 case RTL_GIGA_MAC_VER_31:
beb1fe18 5970 rtl_hw_start_8168dp(tp);
4804b3b3 5971 break;
5972
01dc7fec 5973 case RTL_GIGA_MAC_VER_32:
5974 case RTL_GIGA_MAC_VER_33:
beb1fe18 5975 rtl_hw_start_8168e_1(tp);
70090424
HW		 5976 break;
5977 case RTL_GIGA_MAC_VER_34:
beb1fe18 5978 rtl_hw_start_8168e_2(tp);
01dc7fec 5979 break;
e6de30d6 5980
c2218925
HW		 5981 case RTL_GIGA_MAC_VER_35:
5982 case RTL_GIGA_MAC_VER_36:
beb1fe18 5983 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5984 break;
5985
b3d7b2f2
HW		 5986 case RTL_GIGA_MAC_VER_38:
5987 rtl_hw_start_8411(tp);
5988 break;
5989
c558386b
HW		 5990 case RTL_GIGA_MAC_VER_40:
5991 case RTL_GIGA_MAC_VER_41:
5992 rtl_hw_start_8168g_1(tp);
5993 break;
57538c4a 5994 case RTL_GIGA_MAC_VER_42:
5995 rtl_hw_start_8168g_2(tp);
5996 break;
c558386b 5997
45dd95c4 5998 case RTL_GIGA_MAC_VER_44:
5999 rtl_hw_start_8411_2(tp);
6000 break;
6001
6e1d0b89
CHL		 6002 case RTL_GIGA_MAC_VER_45:
6003 case RTL_GIGA_MAC_VER_46:
6004 rtl_hw_start_8168h_1(tp);
6005 break;
6006
935e2218
CHL		 6007 case RTL_GIGA_MAC_VER_49:
6008 rtl_hw_start_8168ep_1(tp);
6009 break;
6010
6011 case RTL_GIGA_MAC_VER_50:
6012 rtl_hw_start_8168ep_2(tp);
6013 break;
6014
6015 case RTL_GIGA_MAC_VER_51:
6016 rtl_hw_start_8168ep_3(tp);
6017 break;
6018
219a1e9d
FR		 6019 default:
6020 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
61cb532d 6021 tp->dev->name, tp->mac_version);
4804b3b3 6022 break;
219a1e9d 6023 }
07ce4064 6024}
1da177e4 6025
beb1fe18 6026static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 6027{
350f7596 6028 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 6029 { 0x01, 0, 0x6e65 },
6030 { 0x02, 0, 0x091f },
6031 { 0x03, 0, 0xc2f9 },
6032 { 0x06, 0, 0xafb5 },
6033 { 0x07, 0, 0x0e00 },
6034 { 0x19, 0, 0xec80 },
6035 { 0x01, 0, 0x2e65 },
6036 { 0x01, 0, 0x6e65 }
6037 };
6038 u8 cfg1;
6039
f37658da 6040 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 6041
1ef7286e 6042 RTL_W8(tp, DBG_REG, FIX_NAK_1);
2857ffb7 6043
8d98aa39 6044 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 6045
1ef7286e 6046 RTL_W8(tp, Config1,
2857ffb7 6047 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
1ef7286e 6048 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7 6049
1ef7286e 6050 cfg1 = RTL_R8(tp, Config1);
2857ffb7 6051 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
1ef7286e 6052 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
2857ffb7 6053
fdf6fc06 6054 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 6055}
6056
beb1fe18 6057static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 6058{
f37658da 6059 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 6060
8d98aa39 6061 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 6062
1ef7286e
AS		 6063 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
6064 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7
FR		 6065}
6066
beb1fe18 6067static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 6068{
beb1fe18 6069 rtl_hw_start_8102e_2(tp);
2857ffb7 6070
fdf6fc06 6071 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 6072}
6073
beb1fe18 6074static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443
HW		 6075{
6076 static const struct ephy_info e_info_8105e_1[] = {
6077 { 0x07, 0, 0x4000 },
6078 { 0x19, 0, 0x0200 },
6079 { 0x19, 0, 0x0020 },
6080 { 0x1e, 0, 0x2000 },
6081 { 0x03, 0, 0x0001 },
6082 { 0x19, 0, 0x0100 },
6083 { 0x19, 0, 0x0004 },
6084 { 0x0a, 0, 0x0020 }
6085 };
6086
cecb5fd7 6087 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 6088 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5a5e4443 6089
cecb5fd7 6090 /* Disable Early Tally Counter */
1ef7286e 6091 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5a5e4443 6092
1ef7286e
AS		 6093 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
6094 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5a5e4443 6095
fdf6fc06 6096 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 6097
6098 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 6099}
6100
beb1fe18 6101static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 6102{
beb1fe18 6103 rtl_hw_start_8105e_1(tp);
fdf6fc06 6104 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 6105}
6106
7e18dca1
HW		 6107static void rtl_hw_start_8402(struct rtl8169_private *tp)
6108{
7e18dca1
HW		 6109 static const struct ephy_info e_info_8402[] = {
6110 { 0x19, 0xffff, 0xff64 },
6111 { 0x1e, 0, 0x4000 }
6112 };
6113
f37658da 6114 rtl_set_def_aspm_entry_latency(tp);
7e18dca1
HW		 6115
6116 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 6117 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
7e18dca1 6118
1ef7286e
AS		 6119 RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6120 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7e18dca1 6121
fdf6fc06 6122 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1 6123
8d98aa39 6124 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7e18dca1 6125
fdf6fc06
FR		 6126 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6127 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 6128 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6129 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 6130 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6131 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 6132 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 6133
6134 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 6135}
6136
5598bfe5
HW		 6137static void rtl_hw_start_8106(struct rtl8169_private *tp)
6138{
5598bfe5 6139 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 6140 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5598bfe5 6141
1ef7286e
AS		 6142 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6143 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
6144 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
b51ecea8 6145
6146 rtl_pcie_state_l2l3_enable(tp, false);
5598bfe5
HW		 6147}
6148
61cb532d 6149static void rtl_hw_start_8101(struct rtl8169_private *tp)
07ce4064 6150{
da78dbff
FR		 6151 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6152 tp->event_slow &= ~RxFIFOOver;
811fd301 6153
cecb5fd7 6154 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 6155 tp->mac_version == RTL_GIGA_MAC_VER_16)
61cb532d 6156 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
8200bc72 6157 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 6158
1ef7286e 6159 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
1a964649 6160
12d42c50 6161 tp->cp_cmd &= CPCMD_QUIRK_MASK;
1ef7286e 6162 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1a964649 6163
2857ffb7
FR		 6164 switch (tp->mac_version) {
6165 case RTL_GIGA_MAC_VER_07:
beb1fe18 6166 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 6167 break;
6168
6169 case RTL_GIGA_MAC_VER_08:
beb1fe18 6170 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 6171 break;
6172
6173 case RTL_GIGA_MAC_VER_09:
beb1fe18 6174 rtl_hw_start_8102e_2(tp);
2857ffb7 6175 break;
5a5e4443
HW		 6176
6177 case RTL_GIGA_MAC_VER_29:
beb1fe18 6178 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 6179 break;
6180 case RTL_GIGA_MAC_VER_30:
beb1fe18 6181 rtl_hw_start_8105e_2(tp);
5a5e4443 6182 break;
7e18dca1
HW		 6183
6184 case RTL_GIGA_MAC_VER_37:
6185 rtl_hw_start_8402(tp);
6186 break;
5598bfe5
HW		 6187
6188 case RTL_GIGA_MAC_VER_39:
6189 rtl_hw_start_8106(tp);
6190 break;
58152cd4 6191 case RTL_GIGA_MAC_VER_43:
6192 rtl_hw_start_8168g_2(tp);
6193 break;
6e1d0b89
CHL		 6194 case RTL_GIGA_MAC_VER_47:
6195 case RTL_GIGA_MAC_VER_48:
6196 rtl_hw_start_8168h_1(tp);
6197 break;
cdf1a608
FR		 6198 }
6199
1ef7286e 6200 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4
LT		 6201}
6202
6203static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6204{
d58d46b5
FR		 6205 struct rtl8169_private *tp = netdev_priv(dev);
6206
d58d46b5
FR		 6207 if (new_mtu > ETH_DATA_LEN)
6208 rtl_hw_jumbo_enable(tp);
6209 else
6210 rtl_hw_jumbo_disable(tp);
6211
1da177e4 6212 dev->mtu = new_mtu;
350fb32a
MM		 6213 netdev_update_features(dev);
6214
323bb685 6215 return 0;
1da177e4
LT		 6216}
6217
6218static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6219{
95e0918d 6220 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 6221 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6222}
6223
6f0333b8
ED		 6224static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6225 void **data_buff, struct RxDesc *desc)
1da177e4 6226{
1d0254dd
HK		 6227 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
6228 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
48addcc9 6229
6f0333b8
ED		 6230 kfree(*data_buff);
6231 *data_buff = NULL;
1da177e4
LT		 6232 rtl8169_make_unusable_by_asic(desc);
6233}
6234
1d0254dd 6235static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
1da177e4
LT		 6236{
6237 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6238
a0750138
AD		 6239 /* Force memory writes to complete before releasing descriptor */
6240 dma_wmb();
6241
1d0254dd 6242 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
1da177e4
LT		 6243}
6244
6f0333b8
ED		 6245static inline void *rtl8169_align(void *data)
6246{
6247 return (void *)ALIGN((long)data, 16);
6248}
6249
0ecbe1ca
SG		 6250static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6251 struct RxDesc *desc)
1da177e4 6252{
6f0333b8 6253 void *data;
1da177e4 6254 dma_addr_t mapping;
1e1205b7 6255 struct device *d = tp_to_dev(tp);
d3b404c2 6256 int node = dev_to_node(d);
1da177e4 6257
1d0254dd 6258 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
6f0333b8
ED		 6259 if (!data)
6260 return NULL;
e9f63f30 6261
6f0333b8
ED		 6262 if (rtl8169_align(data) != data) {
6263 kfree(data);
1d0254dd 6264 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
6f0333b8
ED		 6265 if (!data)
6266 return NULL;
6267 }
3eafe507 6268
1d0254dd 6269 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
231aee63 6270 DMA_FROM_DEVICE);
d827d86b
SG		 6271 if (unlikely(dma_mapping_error(d, mapping))) {
6272 if (net_ratelimit())
6273 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 6274 goto err_out;
d827d86b 6275 }
1da177e4 6276
d731af78
HK		 6277 desc->addr = cpu_to_le64(mapping);
6278 rtl8169_mark_to_asic(desc);
6f0333b8 6279 return data;
3eafe507
SG		 6280
6281err_out:
6282 kfree(data);
6283 return NULL;
1da177e4
LT		 6284}
6285
6286static void rtl8169_rx_clear(struct rtl8169_private *tp)
6287{
07d3f51f 6288 unsigned int i;
1da177e4
LT		 6289
6290 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 6291 if (tp->Rx_databuff[i]) {
6292 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 6293 tp->RxDescArray + i);
6294 }
6295 }
6296}
6297
0ecbe1ca 6298static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 6299{
0ecbe1ca
SG		 6300 desc->opts1 |= cpu_to_le32(RingEnd);
6301}
5b0384f4 6302
0ecbe1ca
SG		 6303static int rtl8169_rx_fill(struct rtl8169_private *tp)
6304{
6305 unsigned int i;
1da177e4 6306
0ecbe1ca
SG		 6307 for (i = 0; i < NUM_RX_DESC; i++) {
6308 void *data;
4ae47c2d 6309
0ecbe1ca 6310 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 6311 if (!data) {
6312 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 6313 goto err_out;
6f0333b8
ED		 6314 }
6315 tp->Rx_databuff[i] = data;
1da177e4 6316 }
1da177e4 6317
0ecbe1ca
SG		 6318 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6319 return 0;
6320
6321err_out:
6322 rtl8169_rx_clear(tp);
6323 return -ENOMEM;
1da177e4
LT		 6324}
6325
b1127e64 6326static int rtl8169_init_ring(struct rtl8169_private *tp)
1da177e4 6327{
1da177e4
LT		 6328 rtl8169_init_ring_indexes(tp);
6329
b1127e64
HK		 6330 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
6331 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
1da177e4 6332
0ecbe1ca 6333 return rtl8169_rx_fill(tp);
1da177e4
LT		 6334}
6335
48addcc9 6336static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 6337 struct TxDesc *desc)
6338{
6339 unsigned int len = tx_skb->len;
6340
48addcc9
SG		 6341 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6342
1da177e4
LT		 6343 desc->opts1 = 0x00;
6344 desc->opts2 = 0x00;
6345 desc->addr = 0x00;
6346 tx_skb->len = 0;
6347}
6348
3eafe507
SG		 6349static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6350 unsigned int n)
1da177e4
LT		 6351{
6352 unsigned int i;
6353
3eafe507
SG		 6354 for (i = 0; i < n; i++) {
6355 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 6356 struct ring_info *tx_skb = tp->tx_skb + entry;
6357 unsigned int len = tx_skb->len;
6358
6359 if (len) {
6360 struct sk_buff *skb = tx_skb->skb;
6361
1e1205b7 6362 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
1da177e4
LT		 6363 tp->TxDescArray + entry);
6364 if (skb) {
7a4b813c 6365 dev_consume_skb_any(skb);
1da177e4
LT		 6366 tx_skb->skb = NULL;
6367 }
1da177e4
LT		 6368 }
6369 }
3eafe507
SG		 6370}
6371
6372static void rtl8169_tx_clear(struct rtl8169_private *tp)
6373{
6374 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 6375 tp->cur_tx = tp->dirty_tx = 0;
6376}
6377
4422bcd4 6378static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 6379{
c4028958 6380 struct net_device *dev = tp->dev;
56de414c 6381 int i;
1da177e4 6382
da78dbff
FR		 6383 napi_disable(&tp->napi);
6384 netif_stop_queue(dev);
6385 synchronize_sched();
1da177e4 6386
c7c2c39b 6387 rtl8169_hw_reset(tp);
6388
56de414c 6389 for (i = 0; i < NUM_RX_DESC; i++)
1d0254dd 6390 rtl8169_mark_to_asic(tp->RxDescArray + i);
56de414c 6391
1da177e4 6392 rtl8169_tx_clear(tp);
c7c2c39b 6393 rtl8169_init_ring_indexes(tp);
1da177e4 6394
da78dbff 6395 napi_enable(&tp->napi);
61cb532d 6396 rtl_hw_start(tp);
56de414c 6397 netif_wake_queue(dev);
1ef7286e 6398 rtl8169_check_link_status(dev, tp);
1da177e4
LT		 6399}
6400
6401static void rtl8169_tx_timeout(struct net_device *dev)
6402{
da78dbff
FR		 6403 struct rtl8169_private *tp = netdev_priv(dev);
6404
6405 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6406}
6407
6408static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 6409 u32 *opts)
1da177e4
LT		 6410{
6411 struct skb_shared_info *info = skb_shinfo(skb);
6412 unsigned int cur_frag, entry;
6e1d0b89 6413 struct TxDesc *uninitialized_var(txd);
1e1205b7 6414 struct device *d = tp_to_dev(tp);
1da177e4
LT		 6415
6416 entry = tp->cur_tx;
6417 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 6418 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 6419 dma_addr_t mapping;
6420 u32 status, len;
6421 void *addr;
6422
6423 entry = (entry + 1) % NUM_TX_DESC;
6424
6425 txd = tp->TxDescArray + entry;
9e903e08 6426 len = skb_frag_size(frag);
929f6189 6427 addr = skb_frag_address(frag);
48addcc9 6428 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 6429 if (unlikely(dma_mapping_error(d, mapping))) {
6430 if (net_ratelimit())
6431 netif_err(tp, drv, tp->dev,
6432 "Failed to map TX fragments DMA!\n");
3eafe507 6433 goto err_out;
d827d86b 6434 }
1da177e4 6435
cecb5fd7 6436 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 6437 status = opts[0] | len |
6438 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6439
6440 txd->opts1 = cpu_to_le32(status);
2b7b4318 6441 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 6442 txd->addr = cpu_to_le64(mapping);
6443
6444 tp->tx_skb[entry].len = len;
6445 }
6446
6447 if (cur_frag) {
6448 tp->tx_skb[entry].skb = skb;
6449 txd->opts1 |= cpu_to_le32(LastFrag);
6450 }
6451
6452 return cur_frag;
3eafe507
SG		 6453
6454err_out:
6455 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6456 return -EIO;
1da177e4
LT		 6457}
6458
b423e9ae 6459static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6460{
6461 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6462}
6463
e974604b 6464static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6465 struct net_device *dev);
6466/* r8169_csum_workaround()
6467 * The hw limites the value the transport offset. When the offset is out of the
6468 * range, calculate the checksum by sw.
6469 */
6470static void r8169_csum_workaround(struct rtl8169_private *tp,
6471 struct sk_buff *skb)
6472{
6473 if (skb_shinfo(skb)->gso_size) {
6474 netdev_features_t features = tp->dev->features;
6475 struct sk_buff *segs, *nskb;
6476
6477 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6478 segs = skb_gso_segment(skb, features);
6479 if (IS_ERR(segs) || !segs)
6480 goto drop;
6481
6482 do {
6483 nskb = segs;
6484 segs = segs->next;
6485 nskb->next = NULL;
6486 rtl8169_start_xmit(nskb, tp->dev);
6487 } while (segs);
6488
eb781397 6489 dev_consume_skb_any(skb);
e974604b 6490 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6491 if (skb_checksum_help(skb) < 0)
6492 goto drop;
6493
6494 rtl8169_start_xmit(skb, tp->dev);
6495 } else {
6496 struct net_device_stats *stats;
6497
6498drop:
6499 stats = &tp->dev->stats;
6500 stats->tx_dropped++;
eb781397 6501 dev_kfree_skb_any(skb);
e974604b 6502 }
6503}
6504
6505/* msdn_giant_send_check()
6506 * According to the document of microsoft, the TCP Pseudo Header excludes the
6507 * packet length for IPv6 TCP large packets.
6508 */
6509static int msdn_giant_send_check(struct sk_buff *skb)
6510{
6511 const struct ipv6hdr *ipv6h;
6512 struct tcphdr *th;
6513 int ret;
6514
6515 ret = skb_cow_head(skb, 0);
6516 if (ret)
6517 return ret;
6518
6519 ipv6h = ipv6_hdr(skb);
6520 th = tcp_hdr(skb);
6521
6522 th->check = 0;
6523 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6524
6525 return ret;
6526}
6527
5888d3fc 6528static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6529 struct sk_buff *skb, u32 *opts)
1da177e4 6530{
350fb32a
MM		 6531 u32 mss = skb_shinfo(skb)->gso_size;
6532
2b7b4318
FR		 6533 if (mss) {
6534 opts[0] |= TD_LSO;
5888d3fc 6535 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6536 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6537 const struct iphdr *ip = ip_hdr(skb);
6538
6539 if (ip->protocol == IPPROTO_TCP)
6540 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6541 else if (ip->protocol == IPPROTO_UDP)
6542 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6543 else
6544 WARN_ON_ONCE(1);
6545 }
6546
6547 return true;
6548}
6549
6550static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6551 struct sk_buff *skb, u32 *opts)
6552{
bdfa4ed6 6553 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 6554 u32 mss = skb_shinfo(skb)->gso_size;
6555
6556 if (mss) {
e974604b 6557 if (transport_offset > GTTCPHO_MAX) {
6558 netif_warn(tp, tx_err, tp->dev,
6559 "Invalid transport offset 0x%x for TSO\n",
6560 transport_offset);
6561 return false;
6562 }
6563
4ff36466 6564 switch (vlan_get_protocol(skb)) {
e974604b 6565 case htons(ETH_P_IP):
6566 opts[0] |= TD1_GTSENV4;
6567 break;
6568
6569 case htons(ETH_P_IPV6):
6570 if (msdn_giant_send_check(skb))
6571 return false;
6572
6573 opts[0] |= TD1_GTSENV6;
6574 break;
6575
6576 default:
6577 WARN_ON_ONCE(1);
6578 break;
6579 }
6580
bdfa4ed6 6581 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 6582 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 6583 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 6584 u8 ip_protocol;
1da177e4 6585
b423e9ae 6586 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6587 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
b423e9ae 6588
e974604b 6589 if (transport_offset > TCPHO_MAX) {
6590 netif_warn(tp, tx_err, tp->dev,
6591 "Invalid transport offset 0x%x\n",
6592 transport_offset);
6593 return false;
6594 }
6595
4ff36466 6596 switch (vlan_get_protocol(skb)) {
e974604b 6597 case htons(ETH_P_IP):
6598 opts[1] |= TD1_IPv4_CS;
6599 ip_protocol = ip_hdr(skb)->protocol;
6600 break;
6601
6602 case htons(ETH_P_IPV6):
6603 opts[1] |= TD1_IPv6_CS;
6604 ip_protocol = ipv6_hdr(skb)->nexthdr;
6605 break;
6606
6607 default:
6608 ip_protocol = IPPROTO_RAW;
6609 break;
6610 }
6611
6612 if (ip_protocol == IPPROTO_TCP)
6613 opts[1] |= TD1_TCP_CS;
6614 else if (ip_protocol == IPPROTO_UDP)
6615 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 6616 else
6617 WARN_ON_ONCE(1);
e974604b 6618
6619 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 6620 } else {
6621 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6622 return !eth_skb_pad(skb);
1da177e4 6623 }
5888d3fc 6624
b423e9ae 6625 return true;
1da177e4
LT		 6626}
6627
61357325
SH		 6628static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6629 struct net_device *dev)
1da177e4
LT		 6630{
6631 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 6632 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4 6633 struct TxDesc *txd = tp->TxDescArray + entry;
1e1205b7 6634 struct device *d = tp_to_dev(tp);
1da177e4
LT		 6635 dma_addr_t mapping;
6636 u32 status, len;
2b7b4318 6637 u32 opts[2];
3eafe507 6638 int frags;
5b0384f4 6639
477206a0 6640 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 6641 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 6642 goto err_stop_0;
1da177e4
LT		 6643 }
6644
6645 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 6646 goto err_stop_0;
6647
b423e9ae 6648 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6649 opts[0] = DescOwn;
6650
e974604b 6651 if (!tp->tso_csum(tp, skb, opts)) {
6652 r8169_csum_workaround(tp, skb);
6653 return NETDEV_TX_OK;
6654 }
b423e9ae 6655
3eafe507 6656 len = skb_headlen(skb);
48addcc9 6657 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 6658 if (unlikely(dma_mapping_error(d, mapping))) {
6659 if (net_ratelimit())
6660 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 6661 goto err_dma_0;
d827d86b 6662 }
3eafe507
SG		 6663
6664 tp->tx_skb[entry].len = len;
6665 txd->addr = cpu_to_le64(mapping);
1da177e4 6666
2b7b4318 6667 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 6668 if (frags < 0)
6669 goto err_dma_1;
6670 else if (frags)
2b7b4318 6671 opts[0] |= FirstFrag;
3eafe507 6672 else {
2b7b4318 6673 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 6674 tp->tx_skb[entry].skb = skb;
6675 }
6676
2b7b4318
FR		 6677 txd->opts2 = cpu_to_le32(opts[1]);
6678
5047fb5d
RC		 6679 skb_tx_timestamp(skb);
6680
a0750138
AD		 6681 /* Force memory writes to complete before releasing descriptor */
6682 dma_wmb();
1da177e4 6683
cecb5fd7 6684 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 6685 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6686 txd->opts1 = cpu_to_le32(status);
6687
a0750138 6688 /* Force all memory writes to complete before notifying device */
4c020a96 6689 wmb();
1da177e4 6690
a0750138
AD		 6691 tp->cur_tx += frags + 1;
6692
1ef7286e 6693 RTL_W8(tp, TxPoll, NPQ);
1da177e4 6694
87cda7cb 6695 mmiowb();
da78dbff 6696
87cda7cb 6697 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 6698 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6699 * not miss a ring update when it notices a stopped queue.
6700 */
6701 smp_wmb();
1da177e4 6702 netif_stop_queue(dev);
ae1f23fb
FR		 6703 /* Sync with rtl_tx:
6704 * - publish queue status and cur_tx ring index (write barrier)
6705 * - refresh dirty_tx ring index (read barrier).
6706 * May the current thread have a pessimistic view of the ring
6707 * status and forget to wake up queue, a racing rtl_tx thread
6708 * can't.
6709 */
1e874e04 6710 smp_mb();
477206a0 6711 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 6712 netif_wake_queue(dev);
6713 }
6714
61357325 6715 return NETDEV_TX_OK;
1da177e4 6716
3eafe507 6717err_dma_1:
48addcc9 6718 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 6719err_dma_0:
989c9ba1 6720 dev_kfree_skb_any(skb);
3eafe507
SG		 6721 dev->stats.tx_dropped++;
6722 return NETDEV_TX_OK;
6723
6724err_stop_0:
1da177e4 6725 netif_stop_queue(dev);
cebf8cc7 6726 dev->stats.tx_dropped++;
61357325 6727 return NETDEV_TX_BUSY;
1da177e4
LT		 6728}
6729
6730static void rtl8169_pcierr_interrupt(struct net_device *dev)
6731{
6732 struct rtl8169_private *tp = netdev_priv(dev);
6733 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 6734 u16 pci_status, pci_cmd;
6735
6736 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6737 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6738
bf82c189
JP		 6739 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6740 pci_cmd, pci_status);
1da177e4
LT		 6741
6742 /*
6743 * The recovery sequence below admits a very elaborated explanation:
6744 * - it seems to work;
d03902b8
FR		 6745 * - I did not see what else could be done;
6746 * - it makes iop3xx happy.
1da177e4
LT		 6747 *
6748 * Feel free to adjust to your needs.
6749 */
a27993f3 6750 if (pdev->broken_parity_status)
d03902b8
FR		 6751 pci_cmd &= ~PCI_COMMAND_PARITY;
6752 else
6753 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6754
6755 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 6756
6757 pci_write_config_word(pdev, PCI_STATUS,
6758 pci_status & (PCI_STATUS_DETECTED_PARITY |
6759 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6760 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6761
6762 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 6763 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
bf82c189 6764 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4 6765 tp->cp_cmd &= ~PCIDAC;
1ef7286e 6766 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1da177e4 6767 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 6768 }
6769
e6de30d6 6770 rtl8169_hw_reset(tp);
d03902b8 6771
98ddf986 6772 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6773}
6774
da78dbff 6775static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 6776{
6777 unsigned int dirty_tx, tx_left;
6778
1da177e4
LT		 6779 dirty_tx = tp->dirty_tx;
6780 smp_rmb();
6781 tx_left = tp->cur_tx - dirty_tx;
6782
6783 while (tx_left > 0) {
6784 unsigned int entry = dirty_tx % NUM_TX_DESC;
6785 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 6786 u32 status;
6787
1da177e4
LT		 6788 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6789 if (status & DescOwn)
6790 break;
6791
a0750138
AD		 6792 /* This barrier is needed to keep us from reading
6793 * any other fields out of the Tx descriptor until
6794 * we know the status of DescOwn
6795 */
6796 dma_rmb();
6797
1e1205b7 6798 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
48addcc9 6799 tp->TxDescArray + entry);
1da177e4 6800 if (status & LastFrag) {
87cda7cb
DM		 6801 u64_stats_update_begin(&tp->tx_stats.syncp);
6802 tp->tx_stats.packets++;
6803 tp->tx_stats.bytes += tx_skb->skb->len;
6804 u64_stats_update_end(&tp->tx_stats.syncp);
7a4b813c 6805 dev_consume_skb_any(tx_skb->skb);
1da177e4
LT		 6806 tx_skb->skb = NULL;
6807 }
6808 dirty_tx++;
6809 tx_left--;
6810 }
6811
6812 if (tp->dirty_tx != dirty_tx) {
6813 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6814 /* Sync with rtl8169_start_xmit:
6815 * - publish dirty_tx ring index (write barrier)
6816 * - refresh cur_tx ring index and queue status (read barrier)
6817 * May the current thread miss the stopped queue condition,
6818 * a racing xmit thread can only have a right view of the
6819 * ring status.
6820 */
1e874e04 6821 smp_mb();
1da177e4 6822 if (netif_queue_stopped(dev) &&
477206a0 6823 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6824 netif_wake_queue(dev);
6825 }
d78ae2dc
FR		 6826 /*
6827 * 8168 hack: TxPoll requests are lost when the Tx packets are
6828 * too close. Let's kick an extra TxPoll request when a burst
6829 * of start_xmit activity is detected (if it is not detected,
6830 * it is slow enough). -- FR
6831 */
1ef7286e
AS		 6832 if (tp->cur_tx != dirty_tx)
6833 RTL_W8(tp, TxPoll, NPQ);
1da177e4
LT		 6834 }
6835}
6836
126fa4b9
FR		 6837static inline int rtl8169_fragmented_frame(u32 status)
6838{
6839 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6840}
6841
adea1ac7 6842static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6843{
1da177e4
LT		 6844 u32 status = opts1 & RxProtoMask;
6845
6846 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6847 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6848 skb->ip_summed = CHECKSUM_UNNECESSARY;
6849 else
bc8acf2c 6850 skb_checksum_none_assert(skb);
1da177e4
LT		 6851}
6852
6f0333b8
ED		 6853static struct sk_buff *rtl8169_try_rx_copy(void *data,
6854 struct rtl8169_private *tp,
6855 int pkt_size,
6856 dma_addr_t addr)
1da177e4 6857{
b449655f 6858 struct sk_buff *skb;
1e1205b7 6859 struct device *d = tp_to_dev(tp);
b449655f 6860
6f0333b8 6861 data = rtl8169_align(data);
48addcc9 6862 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8 6863 prefetch(data);
e2338f86 6864 skb = napi_alloc_skb(&tp->napi, pkt_size);
6f0333b8 6865 if (skb)
8a67aa86 6866 skb_copy_to_linear_data(skb, data, pkt_size);
48addcc9
SG		 6867 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6868
6f0333b8 6869 return skb;
1da177e4
LT		 6870}
6871
da78dbff 6872static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6873{
6874 unsigned int cur_rx, rx_left;
6f0333b8 6875 unsigned int count;
1da177e4 6876
1da177e4 6877 cur_rx = tp->cur_rx;
1da177e4 6878
9fba0812 6879 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6880 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6881 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6882 u32 status;
6883
6202806e 6884 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 6885 if (status & DescOwn)
6886 break;
a0750138
AD		 6887
6888 /* This barrier is needed to keep us from reading
6889 * any other fields out of the Rx descriptor until
6890 * we know the status of DescOwn
6891 */
6892 dma_rmb();
6893
4dcb7d33 6894 if (unlikely(status & RxRES)) {
bf82c189
JP		 6895 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6896 status);
cebf8cc7 6897 dev->stats.rx_errors++;
1da177e4 6898 if (status & (RxRWT | RxRUNT))
cebf8cc7 6899 dev->stats.rx_length_errors++;
1da177e4 6900 if (status & RxCRC)
cebf8cc7 6901 dev->stats.rx_crc_errors++;
6202806e
HK		 6902 /* RxFOVF is a reserved bit on later chip versions */
6903 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6904 status & RxFOVF) {
da78dbff 6905 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6906 dev->stats.rx_fifo_errors++;
6202806e
HK		 6907 } else if (status & (RxRUNT | RxCRC) &&
6908 !(status & RxRWT) &&
6909 dev->features & NETIF_F_RXALL) {
6bbe021d 6910 goto process_pkt;
6202806e 6911 }
1da177e4 6912 } else {
6f0333b8 6913 struct sk_buff *skb;
6bbe021d
BG		 6914 dma_addr_t addr;
6915 int pkt_size;
6916
6917process_pkt:
6918 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6919 if (likely(!(dev->features & NETIF_F_RXFCS)))
6920 pkt_size = (status & 0x00003fff) - 4;
6921 else
6922 pkt_size = status & 0x00003fff;
1da177e4 6923
126fa4b9
FR		 6924 /*
6925 * The driver does not support incoming fragmented
6926 * frames. They are seen as a symptom of over-mtu
6927 * sized frames.
6928 */
6929 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6930 dev->stats.rx_dropped++;
6931 dev->stats.rx_length_errors++;
ce11ff5e 6932 goto release_descriptor;
126fa4b9
FR		 6933 }
6934
6f0333b8
ED		 6935 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6936 tp, pkt_size, addr);
6f0333b8
ED		 6937 if (!skb) {
6938 dev->stats.rx_dropped++;
ce11ff5e 6939 goto release_descriptor;
1da177e4
LT		 6940 }
6941
adea1ac7 6942 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6943 skb_put(skb, pkt_size);
6944 skb->protocol = eth_type_trans(skb, dev);
6945
7a8fc77b
FR		 6946 rtl8169_rx_vlan_tag(desc, skb);
6947
39174291 6948 if (skb->pkt_type == PACKET_MULTICAST)
6949 dev->stats.multicast++;
6950
56de414c 6951 napi_gro_receive(&tp->napi, skb);
1da177e4 6952
8027aa24
JW		 6953 u64_stats_update_begin(&tp->rx_stats.syncp);
6954 tp->rx_stats.packets++;
6955 tp->rx_stats.bytes += pkt_size;
6956 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6957 }
ce11ff5e 6958release_descriptor:
6959 desc->opts2 = 0;
1d0254dd 6960 rtl8169_mark_to_asic(desc);
1da177e4
LT		 6961 }
6962
6963 count = cur_rx - tp->cur_rx;
6964 tp->cur_rx = cur_rx;
6965
1da177e4
LT		 6966 return count;
6967}
6968
07d3f51f 6969static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6970{
ebcd5daa 6971 struct rtl8169_private *tp = dev_instance;
1da177e4 6972 int handled = 0;
9085cdfa 6973 u16 status;
1da177e4 6974
9085cdfa 6975 status = rtl_get_events(tp);
da78dbff
FR		 6976 if (status && status != 0xffff) {
6977 status &= RTL_EVENT_NAPI | tp->event_slow;
6978 if (status) {
6979 handled = 1;
1da177e4 6980
da78dbff 6981 rtl_irq_disable(tp);
9a899a35 6982 napi_schedule_irqoff(&tp->napi);
f11a377b 6983 }
da78dbff
FR		 6984 }
6985 return IRQ_RETVAL(handled);
6986}
1da177e4 6987
da78dbff
FR		 6988/*
6989 * Workqueue context.
6990 */
6991static void rtl_slow_event_work(struct rtl8169_private *tp)
6992{
6993 struct net_device *dev = tp->dev;
6994 u16 status;
6995
6996 status = rtl_get_events(tp) & tp->event_slow;
6997 rtl_ack_events(tp, status);
1da177e4 6998
da78dbff
FR		 6999 if (unlikely(status & RxFIFOOver)) {
7000 switch (tp->mac_version) {
7001 /* Work around for rx fifo overflow */
7002 case RTL_GIGA_MAC_VER_11:
7003 netif_stop_queue(dev);
934714d0
FR		 7004 /* XXX - Hack alert. See rtl_task(). */
7005 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 7006 default:
f11a377b
DD		 7007 break;
7008 }
da78dbff 7009 }
1da177e4 7010
da78dbff
FR		 7011 if (unlikely(status & SYSErr))
7012 rtl8169_pcierr_interrupt(dev);
0e485150 7013
da78dbff 7014 if (status & LinkChg)
1ef7286e 7015 rtl8169_check_link_status(dev, tp);
1da177e4 7016
7dbb4918 7017 rtl_irq_enable_all(tp);
1da177e4
LT		 7018}
7019
4422bcd4
FR		 7020static void rtl_task(struct work_struct *work)
7021{
da78dbff
FR		 7022 static const struct {
7023 int bitnr;
7024 void (*action)(struct rtl8169_private *);
7025 } rtl_work[] = {
934714d0 7026 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 7027 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7028 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7029 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7030 };
4422bcd4
FR		 7031 struct rtl8169_private *tp =
7032 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 7033 struct net_device *dev = tp->dev;
7034 int i;
7035
7036 rtl_lock_work(tp);
7037
6c4a70c5
FR		 7038 if (!netif_running(dev) ||
7039 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 7040 goto out_unlock;
7041
7042 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7043 bool pending;
7044
da78dbff 7045 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 7046 if (pending)
7047 rtl_work[i].action(tp);
7048 }
4422bcd4 7049
da78dbff
FR		 7050out_unlock:
7051 rtl_unlock_work(tp);
4422bcd4
FR		 7052}
7053
bea3348e 7054static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 7055{
bea3348e
SH		 7056 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7057 struct net_device *dev = tp->dev;
da78dbff
FR		 7058 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7059 int work_done= 0;
7060 u16 status;
7061
7062 status = rtl_get_events(tp);
7063 rtl_ack_events(tp, status & ~tp->event_slow);
7064
7065 if (status & RTL_EVENT_NAPI_RX)
7066 work_done = rtl_rx(dev, tp, (u32) budget);
7067
7068 if (status & RTL_EVENT_NAPI_TX)
7069 rtl_tx(dev, tp);
1da177e4 7070
da78dbff
FR		 7071 if (status & tp->event_slow) {
7072 enable_mask &= ~tp->event_slow;
7073
7074 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7075 }
1da177e4 7076
bea3348e 7077 if (work_done < budget) {
6ad20165 7078 napi_complete_done(napi, work_done);
f11a377b 7079
da78dbff
FR		 7080 rtl_irq_enable(tp, enable_mask);
7081 mmiowb();
1da177e4
LT		 7082 }
7083
bea3348e 7084 return work_done;
1da177e4 7085}
1da177e4 7086
1ef7286e 7087static void rtl8169_rx_missed(struct net_device *dev)
523a6094
FR		 7088{
7089 struct rtl8169_private *tp = netdev_priv(dev);
7090
7091 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7092 return;
7093
1ef7286e
AS		 7094 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
7095 RTL_W32(tp, RxMissed, 0);
523a6094
FR		 7096}
7097
1da177e4
LT		 7098static void rtl8169_down(struct net_device *dev)
7099{
7100 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 7101
4876cc1e 7102 del_timer_sync(&tp->timer);
1da177e4 7103
93dd79e8 7104 napi_disable(&tp->napi);
da78dbff 7105 netif_stop_queue(dev);
1da177e4 7106
92fc43b4 7107 rtl8169_hw_reset(tp);
323bb685
SG		 7108 /*
7109 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 7110 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7111 * and napi is disabled (rtl8169_poll).
323bb685 7112 */
1ef7286e 7113 rtl8169_rx_missed(dev);
1da177e4 7114
1da177e4 7115 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 7116 synchronize_sched();
1da177e4 7117
1da177e4
LT		 7118 rtl8169_tx_clear(tp);
7119
7120 rtl8169_rx_clear(tp);
065c27c1 7121
7122 rtl_pll_power_down(tp);
1da177e4
LT		 7123}
7124
7125static int rtl8169_close(struct net_device *dev)
7126{
7127 struct rtl8169_private *tp = netdev_priv(dev);
7128 struct pci_dev *pdev = tp->pci_dev;
7129
e1759441
RW		 7130 pm_runtime_get_sync(&pdev->dev);
7131
cecb5fd7 7132 /* Update counters before going down */
e71c9ce2 7133 rtl8169_update_counters(tp);
355423d0 7134
da78dbff 7135 rtl_lock_work(tp);
6c4a70c5 7136 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 7137
1da177e4 7138 rtl8169_down(dev);
da78dbff 7139 rtl_unlock_work(tp);
1da177e4 7140
4ea72445
L		 7141 cancel_work_sync(&tp->wk.work);
7142
ebcd5daa 7143 pci_free_irq(pdev, 0, tp);
1da177e4 7144
82553bb6
SG		 7145 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7146 tp->RxPhyAddr);
7147 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7148 tp->TxPhyAddr);
1da177e4
LT		 7149 tp->TxDescArray = NULL;
7150 tp->RxDescArray = NULL;
7151
e1759441
RW		 7152 pm_runtime_put_sync(&pdev->dev);
7153
1da177e4
LT		 7154 return 0;
7155}
7156
dc1c00ce
FR		 7157#ifdef CONFIG_NET_POLL_CONTROLLER
7158static void rtl8169_netpoll(struct net_device *dev)
7159{
7160 struct rtl8169_private *tp = netdev_priv(dev);
7161
6d8b8349 7162 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
dc1c00ce
FR		 7163}
7164#endif
7165
df43ac78
FR		 7166static int rtl_open(struct net_device *dev)
7167{
7168 struct rtl8169_private *tp = netdev_priv(dev);
df43ac78
FR		 7169 struct pci_dev *pdev = tp->pci_dev;
7170 int retval = -ENOMEM;
7171
7172 pm_runtime_get_sync(&pdev->dev);
7173
7174 /*
e75d6606 7175 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 7176 * dma_alloc_coherent provides more.
7177 */
7178 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7179 &tp->TxPhyAddr, GFP_KERNEL);
7180 if (!tp->TxDescArray)
7181 goto err_pm_runtime_put;
7182
7183 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7184 &tp->RxPhyAddr, GFP_KERNEL);
7185 if (!tp->RxDescArray)
7186 goto err_free_tx_0;
7187
b1127e64 7188 retval = rtl8169_init_ring(tp);
df43ac78
FR		 7189 if (retval < 0)
7190 goto err_free_rx_1;
7191
7192 INIT_WORK(&tp->wk.work, rtl_task);
7193
7194 smp_mb();
7195
7196 rtl_request_firmware(tp);
7197
ebcd5daa 7198 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6c6aa15f 7199 dev->name);
df43ac78
FR		 7200 if (retval < 0)
7201 goto err_release_fw_2;
7202
7203 rtl_lock_work(tp);
7204
7205 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7206
7207 napi_enable(&tp->napi);
7208
7209 rtl8169_init_phy(dev, tp);
7210
df43ac78
FR		 7211 rtl_pll_power_up(tp);
7212
61cb532d 7213 rtl_hw_start(tp);
df43ac78 7214
e71c9ce2 7215 if (!rtl8169_init_counter_offsets(tp))
6e85d5ad
CV		 7216 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7217
df43ac78
FR		 7218 netif_start_queue(dev);
7219
7220 rtl_unlock_work(tp);
7221
a92a0849 7222 pm_runtime_put_sync(&pdev->dev);
df43ac78 7223
1ef7286e 7224 rtl8169_check_link_status(dev, tp);
df43ac78
FR		 7225out:
7226 return retval;
7227
7228err_release_fw_2:
7229 rtl_release_firmware(tp);
7230 rtl8169_rx_clear(tp);
7231err_free_rx_1:
7232 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7233 tp->RxPhyAddr);
7234 tp->RxDescArray = NULL;
7235err_free_tx_0:
7236 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7237 tp->TxPhyAddr);
7238 tp->TxDescArray = NULL;
7239err_pm_runtime_put:
7240 pm_runtime_put_noidle(&pdev->dev);
7241 goto out;
7242}
7243
bc1f4470 7244static void
8027aa24 7245rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 7246{
7247 struct rtl8169_private *tp = netdev_priv(dev);
f09cf4b7 7248 struct pci_dev *pdev = tp->pci_dev;
42020320 7249 struct rtl8169_counters *counters = tp->counters;
8027aa24 7250 unsigned int start;
1da177e4 7251
f09cf4b7
CHL		 7252 pm_runtime_get_noresume(&pdev->dev);
7253
7254 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
1ef7286e 7255 rtl8169_rx_missed(dev);
5b0384f4 7256
8027aa24 7257 do {
57a7744e 7258 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 7259 stats->rx_packets = tp->rx_stats.packets;
7260 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 7261 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 7262
8027aa24 7263 do {
57a7744e 7264 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 7265 stats->tx_packets = tp->tx_stats.packets;
7266 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 7267 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 7268
7269 stats->rx_dropped = dev->stats.rx_dropped;
7270 stats->tx_dropped = dev->stats.tx_dropped;
7271 stats->rx_length_errors = dev->stats.rx_length_errors;
7272 stats->rx_errors = dev->stats.rx_errors;
7273 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7274 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7275 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 7276 stats->multicast = dev->stats.multicast;
8027aa24 7277
6e85d5ad
CV		 7278 /*
7279 * Fetch additonal counter values missing in stats collected by driver
7280 * from tally counters.
7281 */
f09cf4b7 7282 if (pm_runtime_active(&pdev->dev))
e71c9ce2 7283 rtl8169_update_counters(tp);
6e85d5ad
CV		 7284
7285 /*
7286 * Subtract values fetched during initalization.
7287 * See rtl8169_init_counter_offsets for a description why we do that.
7288 */
42020320 7289 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 7290 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 7291 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 7292 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 7293 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 7294 le16_to_cpu(tp->tc_offset.tx_aborted);
7295
f09cf4b7 7296 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 7297}
7298
861ab440 7299static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 7300{
065c27c1 7301 struct rtl8169_private *tp = netdev_priv(dev);
7302
5d06a99f 7303 if (!netif_running(dev))
861ab440 7304 return;
5d06a99f
FR		 7305
7306 netif_device_detach(dev);
7307 netif_stop_queue(dev);
da78dbff
FR		 7308
7309 rtl_lock_work(tp);
7310 napi_disable(&tp->napi);
6c4a70c5 7311 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 7312 rtl_unlock_work(tp);
7313
7314 rtl_pll_power_down(tp);
861ab440
RW		 7315}
7316
7317#ifdef CONFIG_PM
7318
7319static int rtl8169_suspend(struct device *device)
7320{
7321 struct pci_dev *pdev = to_pci_dev(device);
7322 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 7323
861ab440 7324 rtl8169_net_suspend(dev);
1371fa6d 7325
5d06a99f
FR		 7326 return 0;
7327}
7328
e1759441
RW		 7329static void __rtl8169_resume(struct net_device *dev)
7330{
065c27c1 7331 struct rtl8169_private *tp = netdev_priv(dev);
7332
e1759441 7333 netif_device_attach(dev);
065c27c1 7334
7335 rtl_pll_power_up(tp);
92bad850 7336 rtl8169_init_phy(dev, tp);
065c27c1 7337
cff4c162
AS		 7338 rtl_lock_work(tp);
7339 napi_enable(&tp->napi);
6c4a70c5 7340 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 7341 rtl_unlock_work(tp);
da78dbff 7342
98ddf986 7343 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 7344}
7345
861ab440 7346static int rtl8169_resume(struct device *device)
5d06a99f 7347{
861ab440 7348 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f
FR		 7349 struct net_device *dev = pci_get_drvdata(pdev);
7350
e1759441
RW		 7351 if (netif_running(dev))
7352 __rtl8169_resume(dev);
5d06a99f 7353
e1759441
RW		 7354 return 0;
7355}
7356
7357static int rtl8169_runtime_suspend(struct device *device)
7358{
7359 struct pci_dev *pdev = to_pci_dev(device);
7360 struct net_device *dev = pci_get_drvdata(pdev);
7361 struct rtl8169_private *tp = netdev_priv(dev);
7362
a92a0849
HK		 7363 if (!tp->TxDescArray) {
7364 rtl_pll_power_down(tp);
e1759441 7365 return 0;
a92a0849 7366 }
e1759441 7367
da78dbff 7368 rtl_lock_work(tp);
e1759441 7369 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 7370 rtl_unlock_work(tp);
e1759441
RW		 7371
7372 rtl8169_net_suspend(dev);
7373
f09cf4b7 7374 /* Update counters before going runtime suspend */
1ef7286e 7375 rtl8169_rx_missed(dev);
e71c9ce2 7376 rtl8169_update_counters(tp);
f09cf4b7 7377
e1759441
RW		 7378 return 0;
7379}
7380
7381static int rtl8169_runtime_resume(struct device *device)
7382{
7383 struct pci_dev *pdev = to_pci_dev(device);
7384 struct net_device *dev = pci_get_drvdata(pdev);
7385 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 7386 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 7387
7388 if (!tp->TxDescArray)
7389 return 0;
7390
da78dbff 7391 rtl_lock_work(tp);
e1759441 7392 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff 7393 rtl_unlock_work(tp);
e1759441
RW		 7394
7395 __rtl8169_resume(dev);
5d06a99f 7396
5d06a99f
FR		 7397 return 0;
7398}
7399
e1759441
RW		 7400static int rtl8169_runtime_idle(struct device *device)
7401{
7402 struct pci_dev *pdev = to_pci_dev(device);
7403 struct net_device *dev = pci_get_drvdata(pdev);
e1759441 7404
a92a0849
HK		 7405 if (!netif_running(dev) || !netif_carrier_ok(dev))
7406 pm_schedule_suspend(device, 10000);
7407
7408 return -EBUSY;
e1759441
RW		 7409}
7410
47145210 7411static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 7412 .suspend = rtl8169_suspend,
7413 .resume = rtl8169_resume,
7414 .freeze = rtl8169_suspend,
7415 .thaw = rtl8169_resume,
7416 .poweroff = rtl8169_suspend,
7417 .restore = rtl8169_resume,
7418 .runtime_suspend = rtl8169_runtime_suspend,
7419 .runtime_resume = rtl8169_runtime_resume,
7420 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 7421};
7422
7423#define RTL8169_PM_OPS (&rtl8169_pm_ops)
7424
7425#else /* !CONFIG_PM */
7426
7427#define RTL8169_PM_OPS NULL
7428
7429#endif /* !CONFIG_PM */
7430
649b3b8c 7431static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7432{
649b3b8c 7433 /* WoL fails with 8168b when the receiver is disabled. */
7434 switch (tp->mac_version) {
7435 case RTL_GIGA_MAC_VER_11:
7436 case RTL_GIGA_MAC_VER_12:
7437 case RTL_GIGA_MAC_VER_17:
7438 pci_clear_master(tp->pci_dev);
7439
1ef7286e 7440 RTL_W8(tp, ChipCmd, CmdRxEnb);
649b3b8c 7441 /* PCI commit */
1ef7286e 7442 RTL_R8(tp, ChipCmd);
649b3b8c 7443 break;
7444 default:
7445 break;
7446 }
7447}
7448
1765f95d
FR		 7449static void rtl_shutdown(struct pci_dev *pdev)
7450{
861ab440 7451 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 7452 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 7453
7454 rtl8169_net_suspend(dev);
1765f95d 7455
cecb5fd7 7456 /* Restore original MAC address */
cc098dc7
IV		 7457 rtl_rar_set(tp, dev->perm_addr);
7458
92fc43b4 7459 rtl8169_hw_reset(tp);
4bb3f522 7460
861ab440 7461 if (system_state == SYSTEM_POWER_OFF) {
433f9d0d 7462 if (tp->saved_wolopts) {
649b3b8c 7463 rtl_wol_suspend_quirk(tp);
7464 rtl_wol_shutdown_quirk(tp);
ca52efd5 7465 }
7466
861ab440
RW		 7467 pci_wake_from_d3(pdev, true);
7468 pci_set_power_state(pdev, PCI_D3hot);
7469 }
7470}
5d06a99f 7471
baf63293 7472static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 7473{
7474 struct net_device *dev = pci_get_drvdata(pdev);
7475 struct rtl8169_private *tp = netdev_priv(dev);
7476
9dbe7896 7477 if (r8168_check_dash(tp))
e27566ed 7478 rtl8168_driver_stop(tp);
e27566ed 7479
ad1be8d3
DN		 7480 netif_napi_del(&tp->napi);
7481
e27566ed
FR		 7482 unregister_netdev(dev);
7483
7484 rtl_release_firmware(tp);
7485
7486 if (pci_dev_run_wake(pdev))
7487 pm_runtime_get_noresume(&pdev->dev);
7488
7489 /* restore original MAC address */
7490 rtl_rar_set(tp, dev->perm_addr);
e27566ed
FR		 7491}
7492
fa9c385e 7493static const struct net_device_ops rtl_netdev_ops = {
df43ac78 7494 .ndo_open = rtl_open,
fa9c385e
FR		 7495 .ndo_stop = rtl8169_close,
7496 .ndo_get_stats64 = rtl8169_get_stats64,
7497 .ndo_start_xmit = rtl8169_start_xmit,
7498 .ndo_tx_timeout = rtl8169_tx_timeout,
7499 .ndo_validate_addr = eth_validate_addr,
7500 .ndo_change_mtu = rtl8169_change_mtu,
7501 .ndo_fix_features = rtl8169_fix_features,
7502 .ndo_set_features = rtl8169_set_features,
7503 .ndo_set_mac_address = rtl_set_mac_address,
7504 .ndo_do_ioctl = rtl8169_ioctl,
7505 .ndo_set_rx_mode = rtl_set_rx_mode,
7506#ifdef CONFIG_NET_POLL_CONTROLLER
7507 .ndo_poll_controller = rtl8169_netpoll,
7508#endif
7509
7510};
7511
31fa8b18 7512static const struct rtl_cfg_info {
61cb532d 7513 void (*hw_start)(struct rtl8169_private *tp);
31fa8b18 7514 u16 event_slow;
14967f94 7515 unsigned int has_gmii:1;
50970831 7516 const struct rtl_coalesce_info *coalesce_info;
31fa8b18
FR		 7517 u8 default_ver;
7518} rtl_cfg_infos [] = {
7519 [RTL_CFG_0] = {
7520 .hw_start = rtl_hw_start_8169,
31fa8b18 7521 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
14967f94 7522 .has_gmii = 1,
50970831 7523 .coalesce_info = rtl_coalesce_info_8169,
31fa8b18
FR		 7524 .default_ver = RTL_GIGA_MAC_VER_01,
7525 },
7526 [RTL_CFG_1] = {
7527 .hw_start = rtl_hw_start_8168,
31fa8b18 7528 .event_slow = SYSErr | LinkChg | RxOverflow,
14967f94 7529 .has_gmii = 1,
50970831 7530 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 7531 .default_ver = RTL_GIGA_MAC_VER_11,
7532 },
7533 [RTL_CFG_2] = {
7534 .hw_start = rtl_hw_start_8101,
31fa8b18
FR		 7535 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7536 PCSTimeout,
50970831 7537 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 7538 .default_ver = RTL_GIGA_MAC_VER_13,
7539 }
7540};
7541
6c6aa15f 7542static int rtl_alloc_irq(struct rtl8169_private *tp)
31fa8b18 7543{
6c6aa15f 7544 unsigned int flags;
31fa8b18 7545
6c6aa15f 7546 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1ef7286e
AS		 7547 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7548 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7549 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6c6aa15f
HK		 7550 flags = PCI_IRQ_LEGACY;
7551 } else {
7552 flags = PCI_IRQ_ALL_TYPES;
31fa8b18 7553 }
6c6aa15f
HK		 7554
7555 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
31fa8b18
FR		 7556}
7557
c558386b
HW		 7558DECLARE_RTL_COND(rtl_link_list_ready_cond)
7559{
1ef7286e 7560 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
c558386b
HW		 7561}
7562
7563DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7564{
1ef7286e 7565 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
c558386b
HW		 7566}
7567
baf63293 7568static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b 7569{
c558386b
HW		 7570 u32 data;
7571
7572 tp->ocp_base = OCP_STD_PHY_BASE;
7573
1ef7286e 7574 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
c558386b
HW		 7575
7576 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7577 return;
7578
7579 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7580 return;
7581
1ef7286e 7582 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
c558386b 7583 msleep(1);
1ef7286e 7584 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
c558386b 7585
5f8bcce9 7586 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7587 data &= ~(1 << 14);
7588 r8168_mac_ocp_write(tp, 0xe8de, data);
7589
7590 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7591 return;
7592
5f8bcce9 7593 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7594 data |= (1 << 15);
7595 r8168_mac_ocp_write(tp, 0xe8de, data);
7596
7597 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7598 return;
7599}
7600
003609da
CHL		 7601static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7602{
7603 rtl8168ep_stop_cmac(tp);
7604 rtl_hw_init_8168g(tp);
7605}
7606
baf63293 7607static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 7608{
7609 switch (tp->mac_version) {
2a71883c 7610 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
003609da
CHL		 7611 rtl_hw_init_8168g(tp);
7612 break;
2a71883c 7613 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
003609da 7614 rtl_hw_init_8168ep(tp);
c558386b 7615 break;
c558386b
HW		 7616 default:
7617 break;
7618 }
7619}
7620
929a031d 7621static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 7622{
7623 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3b6cf25d
FR		 7624 struct rtl8169_private *tp;
7625 struct mii_if_info *mii;
7626 struct net_device *dev;
c8d48d9c 7627 int chipset, region, i;
3b6cf25d
FR		 7628 int rc;
7629
7630 if (netif_msg_drv(&debug)) {
7631 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
7632 MODULENAME, RTL8169_VERSION);
7633 }
7634
4c45d24a
HK		 7635 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7636 if (!dev)
7637 return -ENOMEM;
3b6cf25d
FR		 7638
7639 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 7640 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 7641 tp = netdev_priv(dev);
7642 tp->dev = dev;
7643 tp->pci_dev = pdev;
7644 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7645
7646 mii = &tp->mii;
7647 mii->dev = dev;
7648 mii->mdio_read = rtl_mdio_read;
7649 mii->mdio_write = rtl_mdio_write;
7650 mii->phy_id_mask = 0x1f;
7651 mii->reg_num_mask = 0x1f;
14967f94 7652 mii->supports_gmii = cfg->has_gmii;
3b6cf25d 7653
3b6cf25d 7654 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4c45d24a 7655 rc = pcim_enable_device(pdev);
3b6cf25d 7656 if (rc < 0) {
22148df0 7657 dev_err(&pdev->dev, "enable failure\n");
4c45d24a 7658 return rc;
3b6cf25d
FR		 7659 }
7660
4c45d24a 7661 if (pcim_set_mwi(pdev) < 0)
22148df0 7662 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
3b6cf25d 7663
c8d48d9c
HK		 7664 /* use first MMIO region */
7665 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7666 if (region < 0) {
22148df0 7667 dev_err(&pdev->dev, "no MMIO resource found\n");
4c45d24a 7668 return -ENODEV;
3b6cf25d
FR		 7669 }
7670
7671 /* check for weird/broken PCI region reporting */
7672 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
22148df0 7673 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
4c45d24a 7674 return -ENODEV;
3b6cf25d
FR		 7675 }
7676
93a00d4d 7677 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
3b6cf25d 7678 if (rc < 0) {
22148df0 7679 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
4c45d24a 7680 return rc;
3b6cf25d
FR		 7681 }
7682
93a00d4d 7683 tp->mmio_addr = pcim_iomap_table(pdev)[region];
3b6cf25d
FR		 7684
7685 if (!pci_is_pcie(pdev))
22148df0 7686 dev_info(&pdev->dev, "not PCI Express\n");
3b6cf25d
FR		 7687
7688 /* Identify chip attached to board */
22148df0 7689 rtl8169_get_mac_version(tp, cfg->default_ver);
3b6cf25d 7690
0ae0974e 7691 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
27896c83
AB		 7692
7693 if ((sizeof(dma_addr_t) > 4) &&
7694 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7695 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
f0076436
AB		 7696 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7697 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
27896c83
AB		 7698
7699 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7700 if (!pci_is_pcie(pdev))
7701 tp->cp_cmd |= PCIDAC;
7702 dev->features |= NETIF_F_HIGHDMA;
7703 } else {
7704 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7705 if (rc < 0) {
22148df0 7706 dev_err(&pdev->dev, "DMA configuration failed\n");
4c45d24a 7707 return rc;
27896c83
AB		 7708 }
7709 }
7710
3b6cf25d
FR		 7711 rtl_init_rxcfg(tp);
7712
7713 rtl_irq_disable(tp);
7714
c558386b
HW		 7715 rtl_hw_initialize(tp);
7716
3b6cf25d
FR		 7717 rtl_hw_reset(tp);
7718
7719 rtl_ack_events(tp, 0xffff);
7720
7721 pci_set_master(pdev);
7722
3b6cf25d 7723 rtl_init_mdio_ops(tp);
3b6cf25d
FR		 7724 rtl_init_jumbo_ops(tp);
7725
7726 rtl8169_print_mac_version(tp);
7727
7728 chipset = tp->mac_version;
3b6cf25d 7729
6c6aa15f
HK		 7730 rc = rtl_alloc_irq(tp);
7731 if (rc < 0) {
22148df0 7732 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6c6aa15f
HK		 7733 return rc;
7734 }
3b6cf25d 7735
7edf6d31
HK		 7736 /* override BIOS settings, use userspace tools to enable WOL */
7737 __rtl8169_set_wol(tp, 0);
7738
3b6cf25d
FR		 7739 if (rtl_tbi_enabled(tp)) {
7740 tp->set_speed = rtl8169_set_speed_tbi;
6fa1ba61 7741 tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi;
3b6cf25d
FR		 7742 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7743 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7744 tp->link_ok = rtl8169_tbi_link_ok;
7745 tp->do_ioctl = rtl_tbi_ioctl;
7746 } else {
7747 tp->set_speed = rtl8169_set_speed_xmii;
6fa1ba61 7748 tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii;
3b6cf25d
FR		 7749 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7750 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7751 tp->link_ok = rtl8169_xmii_link_ok;
7752 tp->do_ioctl = rtl_xmii_ioctl;
7753 }
7754
7755 mutex_init(&tp->wk.mutex);
340fea3d
KM		 7756 u64_stats_init(&tp->rx_stats.syncp);
7757 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 7758
7759 /* Get MAC address */
b2d43e6e 7760 switch (tp->mac_version) {
353af85e 7761 u8 mac_addr[ETH_ALEN] __aligned(4);
b2d43e6e
HK		 7762 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7763 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
05b9687b 7764 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
353af85e 7765 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89 7766
353af85e
HK		 7767 if (is_valid_ether_addr(mac_addr))
7768 rtl_rar_set(tp, mac_addr);
b2d43e6e
HK		 7769 break;
7770 default:
7771 break;
6e1d0b89 7772 }
3b6cf25d 7773 for (i = 0; i < ETH_ALEN; i++)
1ef7286e 7774 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
3b6cf25d 7775
7ad24ea4 7776 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 7777 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d 7778
37621493 7779 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
3b6cf25d
FR		 7780
7781 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7782 * properly for all devices */
7783 dev->features |= NETIF_F_RXCSUM |
f646968f 7784 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7785
7786 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 7787 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7788 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7789 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7790 NETIF_F_HIGHDMA;
7791
929a031d 7792 tp->cp_cmd |= RxChkSum | RxVlan;
7793
7794 /*
7795 * Pretend we are using VLANs; This bypasses a nasty bug where
7796 * Interrupts stop flowing on high load on 8110SCd controllers.
7797 */
3b6cf25d 7798 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 7799 /* Disallow toggling */
f646968f 7800 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 7801
a4328ddb
HK		 7802 switch (rtl_chip_infos[chipset].txd_version) {
7803 case RTL_TD_0:
5888d3fc 7804 tp->tso_csum = rtl8169_tso_csum_v1;
a4328ddb
HK		 7805 break;
7806 case RTL_TD_1:
5888d3fc 7807 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 7808 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
a4328ddb
HK		 7809 break;
7810 default:
5888d3fc 7811 WARN_ON_ONCE(1);
a4328ddb 7812 }
5888d3fc 7813
3b6cf25d
FR		 7814 dev->hw_features |= NETIF_F_RXALL;
7815 dev->hw_features |= NETIF_F_RXFCS;
7816
c7315a95
JW		 7817 /* MTU range: 60 - hw-specific max */
7818 dev->min_mtu = ETH_ZLEN;
7819 dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
7820
3b6cf25d
FR		 7821 tp->hw_start = cfg->hw_start;
7822 tp->event_slow = cfg->event_slow;
50970831 7823 tp->coalesce_info = cfg->coalesce_info;
3b6cf25d 7824
9de36ccf 7825 timer_setup(&tp->timer, rtl8169_phy_timer, 0);
3b6cf25d
FR		 7826
7827 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7828
4c45d24a
HK		 7829 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7830 &tp->counters_phys_addr,
7831 GFP_KERNEL);
4cf964af
HK		 7832 if (!tp->counters)
7833 return -ENOMEM;
42020320 7834
19c9ea36
HK		 7835 pci_set_drvdata(pdev, dev);
7836
3b6cf25d
FR		 7837 rc = register_netdev(dev);
7838 if (rc < 0)
4cf964af 7839 return rc;
3b6cf25d 7840
2d6c5a61
HK		 7841 netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7842 rtl_chip_infos[chipset].name, dev->dev_addr,
90b989c5 7843 (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
29274991 7844 pci_irq_vector(pdev, 0));
3b6cf25d
FR		 7845 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7846 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7847 "tx checksumming: %s]\n",
7848 rtl_chip_infos[chipset].jumbo_max,
6ed0e08f 7849 tp->mac_version <= RTL_GIGA_MAC_VER_06 ? "ok" : "ko");
3b6cf25d
FR		 7850 }
7851
9dbe7896 7852 if (r8168_check_dash(tp))
3b6cf25d 7853 rtl8168_driver_start(tp);
3b6cf25d 7854
3b6cf25d
FR		 7855 netif_carrier_off(dev);
7856
a92a0849
HK		 7857 if (pci_dev_run_wake(pdev))
7858 pm_runtime_put_sync(&pdev->dev);
7859
4c45d24a 7860 return 0;
3b6cf25d
FR		 7861}
7862
1da177e4
LT		 7863static struct pci_driver rtl8169_pci_driver = {
7864 .name = MODULENAME,
7865 .id_table = rtl8169_pci_tbl,
3b6cf25d 7866 .probe = rtl_init_one,
baf63293 7867 .remove = rtl_remove_one,
1765f95d 7868 .shutdown = rtl_shutdown,
861ab440 7869 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7870};
7871
3eeb7da9 7872module_pci_driver(rtl8169_pci_driver);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git