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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net...
[thirdparty/kernel/stable.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4
LT		 31
32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 36#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 43#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 44#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 46#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 47#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 48#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 49#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 50#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 51#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 52#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 53#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
bca03d5f 54
1da177e4
LT		 55#ifdef RTL8169_DEBUG
56#define assert(expr) \
5b0384f4
FR		 57 if (!(expr)) { \
58 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 59 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 60 }
06fa7358
JP		 61#define dprintk(fmt, args...) \
62 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 63#else
64#define assert(expr) do {} while (0)
65#define dprintk(fmt, args...) do {} while (0)
66#endif /* RTL8169_DEBUG */
67
b57b7e5a 68#define R8169_MSG_DEFAULT \
f0e837d9 69 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 70
477206a0
JD		 71#define TX_SLOTS_AVAIL(tp) \
72 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
73
74/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
75#define TX_FRAGS_READY_FOR(tp,nr_frags) \
76 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 77
1da177e4
LT		 78/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
79 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 80static const int multicast_filter_limit = 32;
1da177e4 81
9c14ceaf 82#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 83#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 84#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
85
86#define R8169_REGS_SIZE 256
87#define R8169_NAPI_WEIGHT 64
88#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 89#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 90#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
91#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
92
93#define RTL8169_TX_TIMEOUT (6*HZ)
94#define RTL8169_PHY_TIMEOUT (10*HZ)
95
96/* write/read MMIO register */
97#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
98#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
99#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
100#define RTL_R8(reg) readb (ioaddr + (reg))
101#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 102#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 103
104enum mac_version {
85bffe6c
FR		 105 RTL_GIGA_MAC_VER_01 = 0,
106 RTL_GIGA_MAC_VER_02,
107 RTL_GIGA_MAC_VER_03,
108 RTL_GIGA_MAC_VER_04,
109 RTL_GIGA_MAC_VER_05,
110 RTL_GIGA_MAC_VER_06,
111 RTL_GIGA_MAC_VER_07,
112 RTL_GIGA_MAC_VER_08,
113 RTL_GIGA_MAC_VER_09,
114 RTL_GIGA_MAC_VER_10,
115 RTL_GIGA_MAC_VER_11,
116 RTL_GIGA_MAC_VER_12,
117 RTL_GIGA_MAC_VER_13,
118 RTL_GIGA_MAC_VER_14,
119 RTL_GIGA_MAC_VER_15,
120 RTL_GIGA_MAC_VER_16,
121 RTL_GIGA_MAC_VER_17,
122 RTL_GIGA_MAC_VER_18,
123 RTL_GIGA_MAC_VER_19,
124 RTL_GIGA_MAC_VER_20,
125 RTL_GIGA_MAC_VER_21,
126 RTL_GIGA_MAC_VER_22,
127 RTL_GIGA_MAC_VER_23,
128 RTL_GIGA_MAC_VER_24,
129 RTL_GIGA_MAC_VER_25,
130 RTL_GIGA_MAC_VER_26,
131 RTL_GIGA_MAC_VER_27,
132 RTL_GIGA_MAC_VER_28,
133 RTL_GIGA_MAC_VER_29,
134 RTL_GIGA_MAC_VER_30,
135 RTL_GIGA_MAC_VER_31,
136 RTL_GIGA_MAC_VER_32,
137 RTL_GIGA_MAC_VER_33,
70090424 138 RTL_GIGA_MAC_VER_34,
c2218925
HW		 139 RTL_GIGA_MAC_VER_35,
140 RTL_GIGA_MAC_VER_36,
7e18dca1 141 RTL_GIGA_MAC_VER_37,
b3d7b2f2 142 RTL_GIGA_MAC_VER_38,
5598bfe5 143 RTL_GIGA_MAC_VER_39,
c558386b
HW		 144 RTL_GIGA_MAC_VER_40,
145 RTL_GIGA_MAC_VER_41,
57538c4a 146 RTL_GIGA_MAC_VER_42,
58152cd4 147 RTL_GIGA_MAC_VER_43,
45dd95c4 148 RTL_GIGA_MAC_VER_44,
85bffe6c 149 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 150};
151
2b7b4318
FR		 152enum rtl_tx_desc_version {
153 RTL_TD_0 = 0,
154 RTL_TD_1 = 1,
155};
156
d58d46b5
FR		 157#define JUMBO_1K ETH_DATA_LEN
158#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
159#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
160#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
161#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
162
163#define _R(NAME,TD,FW,SZ,B) { \
164 .name = NAME, \
165 .txd_version = TD, \
166 .fw_name = FW, \
167 .jumbo_max = SZ, \
168 .jumbo_tx_csum = B \
169}
1da177e4 170
3c6bee1d 171static const struct {
1da177e4 172 const char *name;
2b7b4318 173 enum rtl_tx_desc_version txd_version;
953a12cc 174 const char *fw_name;
d58d46b5
FR		 175 u16 jumbo_max;
176 bool jumbo_tx_csum;
85bffe6c
FR		 177} rtl_chip_infos[] = {
178 /* PCI devices. */
179 [RTL_GIGA_MAC_VER_01] =
d58d46b5 180 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 181 [RTL_GIGA_MAC_VER_02] =
d58d46b5 182 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 183 [RTL_GIGA_MAC_VER_03] =
d58d46b5 184 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 185 [RTL_GIGA_MAC_VER_04] =
d58d46b5 186 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 187 [RTL_GIGA_MAC_VER_05] =
d58d46b5 188 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 189 [RTL_GIGA_MAC_VER_06] =
d58d46b5 190 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 191 /* PCI-E devices. */
192 [RTL_GIGA_MAC_VER_07] =
d58d46b5 193 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_08] =
d58d46b5 195 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 196 [RTL_GIGA_MAC_VER_09] =
d58d46b5 197 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 198 [RTL_GIGA_MAC_VER_10] =
d58d46b5 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 200 [RTL_GIGA_MAC_VER_11] =
d58d46b5 201 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 202 [RTL_GIGA_MAC_VER_12] =
d58d46b5 203 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 204 [RTL_GIGA_MAC_VER_13] =
d58d46b5 205 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_14] =
d58d46b5 207 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 208 [RTL_GIGA_MAC_VER_15] =
d58d46b5 209 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 210 [RTL_GIGA_MAC_VER_16] =
d58d46b5 211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 212 [RTL_GIGA_MAC_VER_17] =
d58d46b5 213 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_18] =
d58d46b5 215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_19] =
d58d46b5 217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 218 [RTL_GIGA_MAC_VER_20] =
d58d46b5 219 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 220 [RTL_GIGA_MAC_VER_21] =
d58d46b5 221 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 222 [RTL_GIGA_MAC_VER_22] =
d58d46b5 223 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 224 [RTL_GIGA_MAC_VER_23] =
d58d46b5 225 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 226 [RTL_GIGA_MAC_VER_24] =
d58d46b5 227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 229 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
230 JUMBO_9K, false),
85bffe6c 231 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 232 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
233 JUMBO_9K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_27] =
d58d46b5 235 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 236 [RTL_GIGA_MAC_VER_28] =
d58d46b5 237 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 238 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 239 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
240 JUMBO_1K, true),
85bffe6c 241 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 242 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
243 JUMBO_1K, true),
85bffe6c 244 [RTL_GIGA_MAC_VER_31] =
d58d46b5 245 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 246 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 247 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
248 JUMBO_9K, false),
85bffe6c 249 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 250 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
251 JUMBO_9K, false),
70090424 252 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 253 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
254 JUMBO_9K, false),
c2218925 255 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 256 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
257 JUMBO_9K, false),
c2218925 258 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 259 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
260 JUMBO_9K, false),
7e18dca1
HW		 261 [RTL_GIGA_MAC_VER_37] =
262 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
263 JUMBO_1K, true),
b3d7b2f2
HW		 264 [RTL_GIGA_MAC_VER_38] =
265 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
266 JUMBO_9K, false),
5598bfe5
HW		 267 [RTL_GIGA_MAC_VER_39] =
268 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
269 JUMBO_1K, true),
c558386b 270 [RTL_GIGA_MAC_VER_40] =
beb330a4 271 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
c558386b
HW		 272 JUMBO_9K, false),
273 [RTL_GIGA_MAC_VER_41] =
274 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
57538c4a 275 [RTL_GIGA_MAC_VER_42] =
276 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
277 JUMBO_9K, false),
58152cd4 278 [RTL_GIGA_MAC_VER_43] =
279 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
280 JUMBO_1K, true),
45dd95c4 281 [RTL_GIGA_MAC_VER_44] =
282 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
283 JUMBO_9K, false),
953a12cc 284};
85bffe6c 285#undef _R
953a12cc 286
bcf0bf90
FR		 287enum cfg_version {
288 RTL_CFG_0 = 0x00,
289 RTL_CFG_1,
290 RTL_CFG_2
291};
292
a3aa1884 293static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 294 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 295 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 296 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 297 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 298 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 299 { PCI_VENDOR_ID_DLINK, 0x4300,
300 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 301 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 302 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 303 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 304 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
305 { PCI_VENDOR_ID_LINKSYS, 0x1032,
306 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 307 { 0x0001, 0x8168,
308 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 309 {0,},
310};
311
312MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
313
6f0333b8 314static int rx_buf_sz = 16383;
4300e8c7 315static int use_dac;
b57b7e5a
SH		 316static struct {
317 u32 msg_enable;
318} debug = { -1 };
1da177e4 319
07d3f51f
FR		 320enum rtl_registers {
321 MAC0 = 0, /* Ethernet hardware address. */
773d2021 322 MAC4 = 4,
07d3f51f
FR		 323 MAR0 = 8, /* Multicast filter. */
324 CounterAddrLow = 0x10,
325 CounterAddrHigh = 0x14,
326 TxDescStartAddrLow = 0x20,
327 TxDescStartAddrHigh = 0x24,
328 TxHDescStartAddrLow = 0x28,
329 TxHDescStartAddrHigh = 0x2c,
330 FLASH = 0x30,
331 ERSR = 0x36,
332 ChipCmd = 0x37,
333 TxPoll = 0x38,
334 IntrMask = 0x3c,
335 IntrStatus = 0x3e,
4f6b00e5 336
07d3f51f 337 TxConfig = 0x40,
4f6b00e5
HW		 338#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
339#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 340
4f6b00e5
HW		 341 RxConfig = 0x44,
342#define RX128_INT_EN (1 << 15) /* 8111c and later */
343#define RX_MULTI_EN (1 << 14) /* 8111c only */
344#define RXCFG_FIFO_SHIFT 13
345 /* No threshold before first PCI xfer */
346#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 347#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 348#define RXCFG_DMA_SHIFT 8
349 /* Unlimited maximum PCI burst. */
350#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 351
07d3f51f
FR		 352 RxMissed = 0x4c,
353 Cfg9346 = 0x50,
354 Config0 = 0x51,
355 Config1 = 0x52,
356 Config2 = 0x53,
d387b427
FR		 357#define PME_SIGNAL (1 << 5) /* 8168c and later */
358
07d3f51f
FR		 359 Config3 = 0x54,
360 Config4 = 0x55,
361 Config5 = 0x56,
362 MultiIntr = 0x5c,
363 PHYAR = 0x60,
07d3f51f
FR		 364 PHYstatus = 0x6c,
365 RxMaxSize = 0xda,
366 CPlusCmd = 0xe0,
367 IntrMitigate = 0xe2,
368 RxDescAddrLow = 0xe4,
369 RxDescAddrHigh = 0xe8,
f0298f81 370 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
371
372#define NoEarlyTx 0x3f /* Max value : no early transmit. */
373
374 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
375
376#define TxPacketMax (8064 >> 7)
3090bd9a 377#define EarlySize 0x27
f0298f81 378
07d3f51f
FR		 379 FuncEvent = 0xf0,
380 FuncEventMask = 0xf4,
381 FuncPresetState = 0xf8,
382 FuncForceEvent = 0xfc,
1da177e4
LT		 383};
384
f162a5d1
FR		 385enum rtl8110_registers {
386 TBICSR = 0x64,
387 TBI_ANAR = 0x68,
388 TBI_LPAR = 0x6a,
389};
390
391enum rtl8168_8101_registers {
392 CSIDR = 0x64,
393 CSIAR = 0x68,
394#define CSIAR_FLAG 0x80000000
395#define CSIAR_WRITE_CMD 0x80000000
396#define CSIAR_BYTE_ENABLE 0x0f
397#define CSIAR_BYTE_ENABLE_SHIFT 12
398#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 399#define CSIAR_FUNC_CARD 0x00000000
400#define CSIAR_FUNC_SDIO 0x00010000
401#define CSIAR_FUNC_NIC 0x00020000
45dd95c4 402#define CSIAR_FUNC_NIC2 0x00010000
065c27c1 403 PMCH = 0x6f,
f162a5d1
FR		 404 EPHYAR = 0x80,
405#define EPHYAR_FLAG 0x80000000
406#define EPHYAR_WRITE_CMD 0x80000000
407#define EPHYAR_REG_MASK 0x1f
408#define EPHYAR_REG_SHIFT 16
409#define EPHYAR_DATA_MASK 0xffff
5a5e4443 410 DLLPR = 0xd0,
4f6b00e5 411#define PFM_EN (1 << 6)
f162a5d1
FR		 412 DBG_REG = 0xd1,
413#define FIX_NAK_1 (1 << 4)
414#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 415 TWSI = 0xd2,
416 MCU = 0xd3,
4f6b00e5 417#define NOW_IS_OOB (1 << 7)
c558386b
HW		 418#define TX_EMPTY (1 << 5)
419#define RX_EMPTY (1 << 4)
420#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 421#define EN_NDP (1 << 3)
422#define EN_OOB_RESET (1 << 2)
c558386b 423#define LINK_LIST_RDY (1 << 1)
daf9df6d 424 EFUSEAR = 0xdc,
425#define EFUSEAR_FLAG 0x80000000
426#define EFUSEAR_WRITE_CMD 0x80000000
427#define EFUSEAR_READ_CMD 0x00000000
428#define EFUSEAR_REG_MASK 0x03ff
429#define EFUSEAR_REG_SHIFT 8
430#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 431};
432
c0e45c1c 433enum rtl8168_registers {
4f6b00e5
HW		 434 LED_FREQ = 0x1a,
435 EEE_LED = 0x1b,
b646d900 436 ERIDR = 0x70,
437 ERIAR = 0x74,
438#define ERIAR_FLAG 0x80000000
439#define ERIAR_WRITE_CMD 0x80000000
440#define ERIAR_READ_CMD 0x00000000
441#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 442#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 443#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
444#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
445#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
446#define ERIAR_MASK_SHIFT 12
447#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
448#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
c558386b 449#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 450#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 451 EPHY_RXER_NUM = 0x7c,
452 OCPDR = 0xb0, /* OCP GPHY access */
453#define OCPDR_WRITE_CMD 0x80000000
454#define OCPDR_READ_CMD 0x00000000
455#define OCPDR_REG_MASK 0x7f
456#define OCPDR_GPHY_REG_SHIFT 16
457#define OCPDR_DATA_MASK 0xffff
458 OCPAR = 0xb4,
459#define OCPAR_FLAG 0x80000000
460#define OCPAR_GPHY_WRITE_CMD 0x8000f060
461#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 462 GPHY_OCP = 0xb8,
01dc7fec 463 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
464 MISC = 0xf0, /* 8168e only. */
cecb5fd7 465#define TXPLA_RST (1 << 29)
5598bfe5 466#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 467#define PWM_EN (1 << 22)
c558386b 468#define RXDV_GATED_EN (1 << 19)
5598bfe5 469#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 470};
471
07d3f51f 472enum rtl_register_content {
1da177e4 473 /* InterruptStatusBits */
07d3f51f
FR		 474 SYSErr = 0x8000,
475 PCSTimeout = 0x4000,
476 SWInt = 0x0100,
477 TxDescUnavail = 0x0080,
478 RxFIFOOver = 0x0040,
479 LinkChg = 0x0020,
480 RxOverflow = 0x0010,
481 TxErr = 0x0008,
482 TxOK = 0x0004,
483 RxErr = 0x0002,
484 RxOK = 0x0001,
1da177e4
LT		 485
486 /* RxStatusDesc */
e03f33af 487 RxBOVF = (1 << 24),
9dccf611
FR		 488 RxFOVF = (1 << 23),
489 RxRWT = (1 << 22),
490 RxRES = (1 << 21),
491 RxRUNT = (1 << 20),
492 RxCRC = (1 << 19),
1da177e4
LT		 493
494 /* ChipCmdBits */
4f6b00e5 495 StopReq = 0x80,
07d3f51f
FR		 496 CmdReset = 0x10,
497 CmdRxEnb = 0x08,
498 CmdTxEnb = 0x04,
499 RxBufEmpty = 0x01,
1da177e4 500
275391a4
FR		 501 /* TXPoll register p.5 */
502 HPQ = 0x80, /* Poll cmd on the high prio queue */
503 NPQ = 0x40, /* Poll cmd on the low prio queue */
504 FSWInt = 0x01, /* Forced software interrupt */
505
1da177e4 506 /* Cfg9346Bits */
07d3f51f
FR		 507 Cfg9346_Lock = 0x00,
508 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 509
510 /* rx_mode_bits */
07d3f51f
FR		 511 AcceptErr = 0x20,
512 AcceptRunt = 0x10,
513 AcceptBroadcast = 0x08,
514 AcceptMulticast = 0x04,
515 AcceptMyPhys = 0x02,
516 AcceptAllPhys = 0x01,
1687b566 517#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 518
1da177e4
LT		 519 /* TxConfigBits */
520 TxInterFrameGapShift = 24,
521 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
522
5d06a99f 523 /* Config1 register p.24 */
f162a5d1
FR		 524 LEDS1 = (1 << 7),
525 LEDS0 = (1 << 6),
f162a5d1
FR		 526 Speed_down = (1 << 4),
527 MEMMAP = (1 << 3),
528 IOMAP = (1 << 2),
529 VPD = (1 << 1),
5d06a99f
FR		 530 PMEnable = (1 << 0), /* Power Management Enable */
531
6dccd16b 532 /* Config2 register p. 25 */
57538c4a 533 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 534 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 535 PCI_Clock_66MHz = 0x01,
536 PCI_Clock_33MHz = 0x00,
537
61a4dcc2
FR		 538 /* Config3 register p.25 */
539 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
540 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 541 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 542 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 543
d58d46b5
FR		 544 /* Config4 register */
545 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
546
5d06a99f 547 /* Config5 register p.27 */
61a4dcc2
FR		 548 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
549 MWF = (1 << 5), /* Accept Multicast wakeup frame */
550 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 551 Spi_en = (1 << 3),
61a4dcc2 552 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 553 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 554 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 555
1da177e4
LT		 556 /* TBICSR p.28 */
557 TBIReset = 0x80000000,
558 TBILoopback = 0x40000000,
559 TBINwEnable = 0x20000000,
560 TBINwRestart = 0x10000000,
561 TBILinkOk = 0x02000000,
562 TBINwComplete = 0x01000000,
563
564 /* CPlusCmd p.31 */
f162a5d1
FR		 565 EnableBist = (1 << 15), // 8168 8101
566 Mac_dbgo_oe = (1 << 14), // 8168 8101
567 Normal_mode = (1 << 13), // unused
568 Force_half_dup = (1 << 12), // 8168 8101
569 Force_rxflow_en = (1 << 11), // 8168 8101
570 Force_txflow_en = (1 << 10), // 8168 8101
571 Cxpl_dbg_sel = (1 << 9), // 8168 8101
572 ASF = (1 << 8), // 8168 8101
573 PktCntrDisable = (1 << 7), // 8168 8101
574 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 575 RxVlan = (1 << 6),
576 RxChkSum = (1 << 5),
577 PCIDAC = (1 << 4),
578 PCIMulRW = (1 << 3),
0e485150
FR		 579 INTT_0 = 0x0000, // 8168
580 INTT_1 = 0x0001, // 8168
581 INTT_2 = 0x0002, // 8168
582 INTT_3 = 0x0003, // 8168
1da177e4
LT		 583
584 /* rtl8169_PHYstatus */
07d3f51f
FR		 585 TBI_Enable = 0x80,
586 TxFlowCtrl = 0x40,
587 RxFlowCtrl = 0x20,
588 _1000bpsF = 0x10,
589 _100bps = 0x08,
590 _10bps = 0x04,
591 LinkStatus = 0x02,
592 FullDup = 0x01,
1da177e4 593
1da177e4 594 /* _TBICSRBit */
07d3f51f 595 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 596
597 /* DumpCounterCommand */
07d3f51f 598 CounterDump = 0x8,
1da177e4
LT		 599};
600
2b7b4318
FR		 601enum rtl_desc_bit {
602 /* First doubleword. */
1da177e4
LT		 603 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
604 RingEnd = (1 << 30), /* End of descriptor ring */
605 FirstFrag = (1 << 29), /* First segment of a packet */
606 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 607};
608
609/* Generic case. */
610enum rtl_tx_desc_bit {
611 /* First doubleword. */
612 TD_LSO = (1 << 27), /* Large Send Offload */
613#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 614
2b7b4318
FR		 615 /* Second doubleword. */
616 TxVlanTag = (1 << 17), /* Add VLAN tag */
617};
618
619/* 8169, 8168b and 810x except 8102e. */
620enum rtl_tx_desc_bit_0 {
621 /* First doubleword. */
622#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
623 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
624 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
625 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
626};
627
628/* 8102e, 8168c and beyond. */
629enum rtl_tx_desc_bit_1 {
630 /* Second doubleword. */
631#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
632 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
633 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
634 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
635};
1da177e4 636
2b7b4318
FR		 637static const struct rtl_tx_desc_info {
638 struct {
639 u32 udp;
640 u32 tcp;
641 } checksum;
642 u16 mss_shift;
643 u16 opts_offset;
644} tx_desc_info [] = {
645 [RTL_TD_0] = {
646 .checksum = {
647 .udp = TD0_IP_CS | TD0_UDP_CS,
648 .tcp = TD0_IP_CS | TD0_TCP_CS
649 },
650 .mss_shift = TD0_MSS_SHIFT,
651 .opts_offset = 0
652 },
653 [RTL_TD_1] = {
654 .checksum = {
655 .udp = TD1_IP_CS | TD1_UDP_CS,
656 .tcp = TD1_IP_CS | TD1_TCP_CS
657 },
658 .mss_shift = TD1_MSS_SHIFT,
659 .opts_offset = 1
660 }
661};
662
663enum rtl_rx_desc_bit {
1da177e4
LT		 664 /* Rx private */
665 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
666 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
667
668#define RxProtoUDP (PID1)
669#define RxProtoTCP (PID0)
670#define RxProtoIP (PID1 | PID0)
671#define RxProtoMask RxProtoIP
672
673 IPFail = (1 << 16), /* IP checksum failed */
674 UDPFail = (1 << 15), /* UDP/IP checksum failed */
675 TCPFail = (1 << 14), /* TCP/IP checksum failed */
676 RxVlanTag = (1 << 16), /* VLAN tag available */
677};
678
679#define RsvdMask 0x3fffc000
680
681struct TxDesc {
6cccd6e7
REB		 682 __le32 opts1;
683 __le32 opts2;
684 __le64 addr;
1da177e4
LT		 685};
686
687struct RxDesc {
6cccd6e7
REB		 688 __le32 opts1;
689 __le32 opts2;
690 __le64 addr;
1da177e4
LT		 691};
692
693struct ring_info {
694 struct sk_buff *skb;
695 u32 len;
696 u8 __pad[sizeof(void *) - sizeof(u32)];
697};
698
f23e7fda 699enum features {
ccdffb9a
FR		 700 RTL_FEATURE_WOL = (1 << 0),
701 RTL_FEATURE_MSI = (1 << 1),
702 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 703};
704
355423d0
IV		 705struct rtl8169_counters {
706 __le64 tx_packets;
707 __le64 rx_packets;
708 __le64 tx_errors;
709 __le32 rx_errors;
710 __le16 rx_missed;
711 __le16 align_errors;
712 __le32 tx_one_collision;
713 __le32 tx_multi_collision;
714 __le64 rx_unicast;
715 __le64 rx_broadcast;
716 __le32 rx_multicast;
717 __le16 tx_aborted;
718 __le16 tx_underun;
719};
720
da78dbff 721enum rtl_flag {
6c4a70c5 722 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 723 RTL_FLAG_TASK_SLOW_PENDING,
724 RTL_FLAG_TASK_RESET_PENDING,
725 RTL_FLAG_TASK_PHY_PENDING,
726 RTL_FLAG_MAX
727};
728
8027aa24
JW		 729struct rtl8169_stats {
730 u64 packets;
731 u64 bytes;
732 struct u64_stats_sync syncp;
733};
734
1da177e4
LT		 735struct rtl8169_private {
736 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 737 struct pci_dev *pci_dev;
c4028958 738 struct net_device *dev;
bea3348e 739 struct napi_struct napi;
b57b7e5a 740 u32 msg_enable;
2b7b4318
FR		 741 u16 txd_version;
742 u16 mac_version;
1da177e4
LT		 743 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
744 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 745 u32 dirty_tx;
8027aa24
JW		 746 struct rtl8169_stats rx_stats;
747 struct rtl8169_stats tx_stats;
1da177e4
LT		 748 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
749 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
750 dma_addr_t TxPhyAddr;
751 dma_addr_t RxPhyAddr;
6f0333b8 752 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 753 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 754 struct timer_list timer;
755 u16 cp_cmd;
da78dbff
FR		 756
757 u16 event_slow;
c0e45c1c 758
759 struct mdio_ops {
24192210
FR		 760 void (*write)(struct rtl8169_private *, int, int);
761 int (*read)(struct rtl8169_private *, int);
c0e45c1c 762 } mdio_ops;
763
065c27c1 764 struct pll_power_ops {
765 void (*down)(struct rtl8169_private *);
766 void (*up)(struct rtl8169_private *);
767 } pll_power_ops;
768
d58d46b5
FR		 769 struct jumbo_ops {
770 void (*enable)(struct rtl8169_private *);
771 void (*disable)(struct rtl8169_private *);
772 } jumbo_ops;
773
beb1fe18 774 struct csi_ops {
52989f0e
FR		 775 void (*write)(struct rtl8169_private *, int, int);
776 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 777 } csi_ops;
778
54405cde 779 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 780 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 781 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 782 void (*hw_start)(struct net_device *);
4da19633 783 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 784 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 785 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 786
787 struct {
da78dbff
FR		 788 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
789 struct mutex mutex;
4422bcd4
FR		 790 struct work_struct work;
791 } wk;
792
f23e7fda 793 unsigned features;
ccdffb9a
FR		 794
795 struct mii_if_info mii;
355423d0 796 struct rtl8169_counters counters;
e1759441 797 u32 saved_wolopts;
e03f33af 798 u32 opts1_mask;
f1e02ed1 799
b6ffd97f
FR		 800 struct rtl_fw {
801 const struct firmware *fw;
1c361efb
FR		 802
803#define RTL_VER_SIZE 32
804
805 char version[RTL_VER_SIZE];
806
807 struct rtl_fw_phy_action {
808 __le32 *code;
809 size_t size;
810 } phy_action;
b6ffd97f 811 } *rtl_fw;
497888cf 812#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 813
814 u32 ocp_base;
1da177e4
LT		 815};
816
979b6c13 817MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 818MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 819module_param(use_dac, int, 0);
4300e8c7 820MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 821module_param_named(debug, debug.msg_enable, int, 0);
822MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 823MODULE_LICENSE("GPL");
824MODULE_VERSION(RTL8169_VERSION);
bca03d5f 825MODULE_FIRMWARE(FIRMWARE_8168D_1);
826MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 827MODULE_FIRMWARE(FIRMWARE_8168E_1);
828MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 829MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 830MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 831MODULE_FIRMWARE(FIRMWARE_8168F_1);
832MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 833MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 834MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 835MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 836MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 837MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 838MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 839MODULE_FIRMWARE(FIRMWARE_8168G_3);
1da177e4 840
da78dbff
FR		 841static void rtl_lock_work(struct rtl8169_private *tp)
842{
843 mutex_lock(&tp->wk.mutex);
844}
845
846static void rtl_unlock_work(struct rtl8169_private *tp)
847{
848 mutex_unlock(&tp->wk.mutex);
849}
850
d58d46b5
FR		 851static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
852{
7d7903b2
JL		 853 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
854 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 855}
856
ffc46952
FR		 857struct rtl_cond {
858 bool (*check)(struct rtl8169_private *);
859 const char *msg;
860};
861
862static void rtl_udelay(unsigned int d)
863{
864 udelay(d);
865}
866
867static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
868 void (*delay)(unsigned int), unsigned int d, int n,
869 bool high)
870{
871 int i;
872
873 for (i = 0; i < n; i++) {
874 delay(d);
875 if (c->check(tp) == high)
876 return true;
877 }
82e316ef
FR		 878 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
879 c->msg, !high, n, d);
ffc46952
FR		 880 return false;
881}
882
883static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
884 const struct rtl_cond *c,
885 unsigned int d, int n)
886{
887 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
888}
889
890static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
891 const struct rtl_cond *c,
892 unsigned int d, int n)
893{
894 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
895}
896
897static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
898 const struct rtl_cond *c,
899 unsigned int d, int n)
900{
901 return rtl_loop_wait(tp, c, msleep, d, n, true);
902}
903
904static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
905 const struct rtl_cond *c,
906 unsigned int d, int n)
907{
908 return rtl_loop_wait(tp, c, msleep, d, n, false);
909}
910
911#define DECLARE_RTL_COND(name) \
912static bool name ## _check(struct rtl8169_private *); \
913 \
914static const struct rtl_cond name = { \
915 .check = name ## _check, \
916 .msg = #name \
917}; \
918 \
919static bool name ## _check(struct rtl8169_private *tp)
920
921DECLARE_RTL_COND(rtl_ocpar_cond)
922{
923 void __iomem *ioaddr = tp->mmio_addr;
924
925 return RTL_R32(OCPAR) & OCPAR_FLAG;
926}
927
b646d900 928static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
929{
930 void __iomem *ioaddr = tp->mmio_addr;
b646d900 931
932 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 933
934 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
935 RTL_R32(OCPDR) : ~0;
b646d900 936}
937
938static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
939{
940 void __iomem *ioaddr = tp->mmio_addr;
b646d900 941
942 RTL_W32(OCPDR, data);
943 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 944
945 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
946}
947
948DECLARE_RTL_COND(rtl_eriar_cond)
949{
950 void __iomem *ioaddr = tp->mmio_addr;
951
952 return RTL_R32(ERIAR) & ERIAR_FLAG;
b646d900 953}
954
fac5b3ca 955static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 956{
fac5b3ca 957 void __iomem *ioaddr = tp->mmio_addr;
b646d900 958
959 RTL_W8(ERIDR, cmd);
960 RTL_W32(ERIAR, 0x800010e8);
961 msleep(2);
ffc46952
FR		 962
963 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
964 return;
b646d900 965
fac5b3ca 966 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 967}
968
969#define OOB_CMD_RESET 0x00
970#define OOB_CMD_DRIVER_START 0x05
971#define OOB_CMD_DRIVER_STOP 0x06
972
cecb5fd7
FR		 973static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
974{
975 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
976}
977
ffc46952 978DECLARE_RTL_COND(rtl_ocp_read_cond)
b646d900 979{
cecb5fd7 980 u16 reg;
b646d900 981
cecb5fd7 982 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 983
ffc46952 984 return ocp_read(tp, 0x0f, reg) & 0x00000800;
b646d900 985}
986
ffc46952 987static void rtl8168_driver_start(struct rtl8169_private *tp)
b646d900 988{
ffc46952 989 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
b646d900 990
ffc46952
FR		 991 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
992}
b646d900 993
ffc46952
FR		 994static void rtl8168_driver_stop(struct rtl8169_private *tp)
995{
996 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
4804b3b3 997
ffc46952 998 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
b646d900 999}
1000
4804b3b3 1001static int r8168dp_check_dash(struct rtl8169_private *tp)
1002{
cecb5fd7 1003 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 1004
cecb5fd7 1005 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 1006}
b646d900 1007
c558386b
HW		 1008static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
1009{
1010 if (reg & 0xffff0001) {
1011 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
1012 return true;
1013 }
1014 return false;
1015}
1016
1017DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1018{
1019 void __iomem *ioaddr = tp->mmio_addr;
1020
1021 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1022}
1023
1024static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1025{
1026 void __iomem *ioaddr = tp->mmio_addr;
1027
1028 if (rtl_ocp_reg_failure(tp, reg))
1029 return;
1030
1031 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1032
1033 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1034}
1035
1036static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1037{
1038 void __iomem *ioaddr = tp->mmio_addr;
1039
1040 if (rtl_ocp_reg_failure(tp, reg))
1041 return 0;
1042
1043 RTL_W32(GPHY_OCP, reg << 15);
1044
1045 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1046 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1047}
1048
c558386b
HW		 1049static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1050{
1051 void __iomem *ioaddr = tp->mmio_addr;
1052
1053 if (rtl_ocp_reg_failure(tp, reg))
1054 return;
1055
1056 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1057}
1058
1059static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1060{
1061 void __iomem *ioaddr = tp->mmio_addr;
1062
1063 if (rtl_ocp_reg_failure(tp, reg))
1064 return 0;
1065
1066 RTL_W32(OCPDR, reg << 15);
1067
3a83ad12 1068 return RTL_R32(OCPDR);
c558386b
HW		 1069}
1070
1071#define OCP_STD_PHY_BASE 0xa400
1072
1073static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1074{
1075 if (reg == 0x1f) {
1076 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1077 return;
1078 }
1079
1080 if (tp->ocp_base != OCP_STD_PHY_BASE)
1081 reg -= 0x10;
1082
1083 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1084}
1085
1086static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1087{
1088 if (tp->ocp_base != OCP_STD_PHY_BASE)
1089 reg -= 0x10;
1090
1091 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1092}
1093
eee3786f 1094static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1095{
1096 if (reg == 0x1f) {
1097 tp->ocp_base = value << 4;
1098 return;
1099 }
1100
1101 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1102}
1103
1104static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1105{
1106 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1107}
1108
ffc46952
FR		 1109DECLARE_RTL_COND(rtl_phyar_cond)
1110{
1111 void __iomem *ioaddr = tp->mmio_addr;
1112
1113 return RTL_R32(PHYAR) & 0x80000000;
1114}
1115
24192210 1116static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1117{
24192210 1118 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1119
24192210 1120 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1121
ffc46952 1122 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1123 /*
81a95f04
TT		 1124 * According to hardware specs a 20us delay is required after write
1125 * complete indication, but before sending next command.
024a07ba 1126 */
81a95f04 1127 udelay(20);
1da177e4
LT		 1128}
1129
24192210 1130static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1131{
24192210 1132 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1133 int value;
1da177e4 1134
24192210 1135 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1136
ffc46952
FR		 1137 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1138 RTL_R32(PHYAR) & 0xffff : ~0;
1139
81a95f04
TT		 1140 /*
1141 * According to hardware specs a 20us delay is required after read
1142 * complete indication, but before sending next command.
1143 */
1144 udelay(20);
1145
1da177e4
LT		 1146 return value;
1147}
1148
24192210 1149static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1150{
24192210 1151 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1152
24192210 1153 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1154 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1155 RTL_W32(EPHY_RXER_NUM, 0);
1156
ffc46952 1157 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1158}
1159
24192210 1160static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1161{
24192210
FR		 1162 r8168dp_1_mdio_access(tp, reg,
1163 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1164}
1165
24192210 1166static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1167{
24192210 1168 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1169
24192210 1170 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1171
1172 mdelay(1);
1173 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1174 RTL_W32(EPHY_RXER_NUM, 0);
1175
ffc46952
FR		 1176 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1177 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1178}
1179
e6de30d6 1180#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1181
1182static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1183{
1184 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1185}
1186
1187static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1188{
1189 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1190}
1191
24192210 1192static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1193{
24192210
FR		 1194 void __iomem *ioaddr = tp->mmio_addr;
1195
e6de30d6 1196 r8168dp_2_mdio_start(ioaddr);
1197
24192210 1198 r8169_mdio_write(tp, reg, value);
e6de30d6 1199
1200 r8168dp_2_mdio_stop(ioaddr);
1201}
1202
24192210 1203static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1204{
24192210 1205 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1206 int value;
1207
1208 r8168dp_2_mdio_start(ioaddr);
1209
24192210 1210 value = r8169_mdio_read(tp, reg);
e6de30d6 1211
1212 r8168dp_2_mdio_stop(ioaddr);
1213
1214 return value;
1215}
1216
4da19633 1217static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1218{
24192210 1219 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1220}
1221
4da19633 1222static int rtl_readphy(struct rtl8169_private *tp, int location)
1223{
24192210 1224 return tp->mdio_ops.read(tp, location);
4da19633 1225}
1226
1227static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1228{
1229 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1230}
1231
1232static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1233{
1234 int val;
1235
4da19633 1236 val = rtl_readphy(tp, reg_addr);
1237 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1238}
1239
ccdffb9a
FR		 1240static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1241 int val)
1242{
1243 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1244
4da19633 1245 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1246}
1247
1248static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1249{
1250 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1251
4da19633 1252 return rtl_readphy(tp, location);
ccdffb9a
FR		 1253}
1254
ffc46952
FR		 1255DECLARE_RTL_COND(rtl_ephyar_cond)
1256{
1257 void __iomem *ioaddr = tp->mmio_addr;
1258
1259 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1260}
1261
fdf6fc06 1262static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1263{
fdf6fc06 1264 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1265
1266 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1267 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1268
ffc46952
FR		 1269 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1270
1271 udelay(10);
dacf8154
FR		 1272}
1273
fdf6fc06 1274static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1275{
fdf6fc06 1276 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1277
1278 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1279
ffc46952
FR		 1280 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1281 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1282}
1283
fdf6fc06
FR		 1284static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1285 u32 val, int type)
133ac40a 1286{
fdf6fc06 1287 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1288
1289 BUG_ON((addr & 3) || (mask == 0));
1290 RTL_W32(ERIDR, val);
1291 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1292
ffc46952 1293 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1294}
1295
fdf6fc06 1296static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1297{
fdf6fc06 1298 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1299
1300 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1301
ffc46952
FR		 1302 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1303 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1304}
1305
fdf6fc06
FR		 1306static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1307 u32 m, int type)
133ac40a
HW		 1308{
1309 u32 val;
1310
fdf6fc06
FR		 1311 val = rtl_eri_read(tp, addr, type);
1312 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1313}
1314
c28aa385 1315struct exgmac_reg {
1316 u16 addr;
1317 u16 mask;
1318 u32 val;
1319};
1320
fdf6fc06 1321static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1322 const struct exgmac_reg *r, int len)
1323{
1324 while (len-- > 0) {
fdf6fc06 1325 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1326 r++;
1327 }
1328}
1329
ffc46952
FR		 1330DECLARE_RTL_COND(rtl_efusear_cond)
1331{
1332 void __iomem *ioaddr = tp->mmio_addr;
1333
1334 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1335}
1336
fdf6fc06 1337static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1338{
fdf6fc06 1339 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1340
1341 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1342
ffc46952
FR		 1343 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1344 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1345}
1346
9085cdfa
FR		 1347static u16 rtl_get_events(struct rtl8169_private *tp)
1348{
1349 void __iomem *ioaddr = tp->mmio_addr;
1350
1351 return RTL_R16(IntrStatus);
1352}
1353
1354static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1355{
1356 void __iomem *ioaddr = tp->mmio_addr;
1357
1358 RTL_W16(IntrStatus, bits);
1359 mmiowb();
1360}
1361
1362static void rtl_irq_disable(struct rtl8169_private *tp)
1363{
1364 void __iomem *ioaddr = tp->mmio_addr;
1365
1366 RTL_W16(IntrMask, 0);
1367 mmiowb();
1368}
1369
3e990ff5
FR		 1370static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1371{
1372 void __iomem *ioaddr = tp->mmio_addr;
1373
1374 RTL_W16(IntrMask, bits);
1375}
1376
da78dbff
FR		 1377#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1378#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1379#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1380
1381static void rtl_irq_enable_all(struct rtl8169_private *tp)
1382{
1383 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1384}
1385
811fd301 1386static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1387{
811fd301 1388 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1389
9085cdfa 1390 rtl_irq_disable(tp);
da78dbff 1391 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1392 RTL_R8(ChipCmd);
1da177e4
LT		 1393}
1394
4da19633 1395static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1396{
4da19633 1397 void __iomem *ioaddr = tp->mmio_addr;
1398
1da177e4
LT		 1399 return RTL_R32(TBICSR) & TBIReset;
1400}
1401
4da19633 1402static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1403{
4da19633 1404 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1405}
1406
1407static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1408{
1409 return RTL_R32(TBICSR) & TBILinkOk;
1410}
1411
1412static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1413{
1414 return RTL_R8(PHYstatus) & LinkStatus;
1415}
1416
4da19633 1417static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1418{
4da19633 1419 void __iomem *ioaddr = tp->mmio_addr;
1420
1da177e4
LT		 1421 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1422}
1423
4da19633 1424static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1425{
1426 unsigned int val;
1427
4da19633 1428 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1429 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1430}
1431
70090424
HW		 1432static void rtl_link_chg_patch(struct rtl8169_private *tp)
1433{
1434 void __iomem *ioaddr = tp->mmio_addr;
1435 struct net_device *dev = tp->dev;
1436
1437 if (!netif_running(dev))
1438 return;
1439
b3d7b2f2
HW		 1440 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1441 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1442 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1443 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1444 ERIAR_EXGMAC);
1445 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1446 ERIAR_EXGMAC);
70090424 1447 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1448 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1449 ERIAR_EXGMAC);
1450 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1451 ERIAR_EXGMAC);
70090424 1452 } else {
fdf6fc06
FR		 1453 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1454 ERIAR_EXGMAC);
1455 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1456 ERIAR_EXGMAC);
70090424
HW		 1457 }
1458 /* Reset packet filter */
fdf6fc06 1459 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1460 ERIAR_EXGMAC);
fdf6fc06 1461 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1462 ERIAR_EXGMAC);
c2218925
HW		 1463 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1464 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1465 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1466 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1467 ERIAR_EXGMAC);
1468 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1469 ERIAR_EXGMAC);
c2218925 1470 } else {
fdf6fc06
FR		 1471 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1472 ERIAR_EXGMAC);
1473 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1474 ERIAR_EXGMAC);
c2218925 1475 }
7e18dca1
HW		 1476 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1477 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1478 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1479 ERIAR_EXGMAC);
1480 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1481 ERIAR_EXGMAC);
7e18dca1 1482 } else {
fdf6fc06
FR		 1483 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1484 ERIAR_EXGMAC);
7e18dca1 1485 }
70090424
HW		 1486 }
1487}
1488
e4fbce74 1489static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1490 struct rtl8169_private *tp,
1491 void __iomem *ioaddr, bool pm)
1da177e4 1492{
1da177e4 1493 if (tp->link_ok(ioaddr)) {
70090424 1494 rtl_link_chg_patch(tp);
e1759441 1495 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1496 if (pm)
1497 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1498 netif_carrier_on(dev);
1519e57f
FR		 1499 if (net_ratelimit())
1500 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1501 } else {
1da177e4 1502 netif_carrier_off(dev);
bf82c189 1503 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1504 if (pm)
10953db8 1505 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1506 }
1da177e4
LT		 1507}
1508
e4fbce74
RW		 1509static void rtl8169_check_link_status(struct net_device *dev,
1510 struct rtl8169_private *tp,
1511 void __iomem *ioaddr)
1512{
1513 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1514}
1515
e1759441
RW		 1516#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1517
1518static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1519{
61a4dcc2
FR		 1520 void __iomem *ioaddr = tp->mmio_addr;
1521 u8 options;
e1759441 1522 u32 wolopts = 0;
61a4dcc2
FR		 1523
1524 options = RTL_R8(Config1);
1525 if (!(options & PMEnable))
e1759441 1526 return 0;
61a4dcc2
FR		 1527
1528 options = RTL_R8(Config3);
1529 if (options & LinkUp)
e1759441 1530 wolopts |= WAKE_PHY;
61a4dcc2 1531 if (options & MagicPacket)
e1759441 1532 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1533
1534 options = RTL_R8(Config5);
1535 if (options & UWF)
e1759441 1536 wolopts |= WAKE_UCAST;
61a4dcc2 1537 if (options & BWF)
e1759441 1538 wolopts |= WAKE_BCAST;
61a4dcc2 1539 if (options & MWF)
e1759441 1540 wolopts |= WAKE_MCAST;
61a4dcc2 1541
e1759441 1542 return wolopts;
61a4dcc2
FR		 1543}
1544
e1759441 1545static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1546{
1547 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1548
da78dbff 1549 rtl_lock_work(tp);
e1759441
RW		 1550
1551 wol->supported = WAKE_ANY;
1552 wol->wolopts = __rtl8169_get_wol(tp);
1553
da78dbff 1554 rtl_unlock_work(tp);
e1759441
RW		 1555}
1556
1557static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1558{
61a4dcc2 1559 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1560 unsigned int i;
350f7596 1561 static const struct {
61a4dcc2
FR		 1562 u32 opt;
1563 u16 reg;
1564 u8 mask;
1565 } cfg[] = {
61a4dcc2
FR		 1566 { WAKE_PHY, Config3, LinkUp },
1567 { WAKE_MAGIC, Config3, MagicPacket },
1568 { WAKE_UCAST, Config5, UWF },
1569 { WAKE_BCAST, Config5, BWF },
1570 { WAKE_MCAST, Config5, MWF },
1571 { WAKE_ANY, Config5, LanWake }
1572 };
851e6022 1573 u8 options;
61a4dcc2 1574
61a4dcc2
FR		 1575 RTL_W8(Cfg9346, Cfg9346_Unlock);
1576
1577 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
851e6022 1578 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1579 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1580 options |= cfg[i].mask;
1581 RTL_W8(cfg[i].reg, options);
1582 }
1583
851e6022
FR		 1584 switch (tp->mac_version) {
1585 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1586 options = RTL_R8(Config1) & ~PMEnable;
1587 if (wolopts)
1588 options |= PMEnable;
1589 RTL_W8(Config1, options);
1590 break;
1591 default:
d387b427
FR		 1592 options = RTL_R8(Config2) & ~PME_SIGNAL;
1593 if (wolopts)
1594 options |= PME_SIGNAL;
1595 RTL_W8(Config2, options);
851e6022
FR		 1596 break;
1597 }
1598
61a4dcc2 1599 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1600}
1601
1602static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1603{
1604 struct rtl8169_private *tp = netdev_priv(dev);
1605
da78dbff 1606 rtl_lock_work(tp);
61a4dcc2 1607
f23e7fda
FR		 1608 if (wol->wolopts)
1609 tp->features |= RTL_FEATURE_WOL;
1610 else
1611 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1612 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1613
1614 rtl_unlock_work(tp);
61a4dcc2 1615
ea80907f 1616 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1617
61a4dcc2
FR		 1618 return 0;
1619}
1620
31bd204f
FR		 1621static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1622{
85bffe6c 1623 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1624}
1625
1da177e4
LT		 1626static void rtl8169_get_drvinfo(struct net_device *dev,
1627 struct ethtool_drvinfo *info)
1628{
1629 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1630 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1631
68aad78c
RJ		 1632 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1633 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1634 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1635 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1636 if (!IS_ERR_OR_NULL(rtl_fw))
1637 strlcpy(info->fw_version, rtl_fw->version,
1638 sizeof(info->fw_version));
1da177e4
LT		 1639}
1640
1641static int rtl8169_get_regs_len(struct net_device *dev)
1642{
1643 return R8169_REGS_SIZE;
1644}
1645
1646static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1647 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1648{
1649 struct rtl8169_private *tp = netdev_priv(dev);
1650 void __iomem *ioaddr = tp->mmio_addr;
1651 int ret = 0;
1652 u32 reg;
1653
1654 reg = RTL_R32(TBICSR);
1655 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1656 (duplex == DUPLEX_FULL)) {
1657 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1658 } else if (autoneg == AUTONEG_ENABLE)
1659 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1660 else {
bf82c189
JP		 1661 netif_warn(tp, link, dev,
1662 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1663 ret = -EOPNOTSUPP;
1664 }
1665
1666 return ret;
1667}
1668
1669static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1670 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1671{
1672 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1673 int giga_ctrl, bmcr;
54405cde 1674 int rc = -EINVAL;
1da177e4 1675
716b50a3 1676 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1677
1678 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1679 int auto_nego;
1680
4da19633 1681 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1682 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1683 ADVERTISE_100HALF | ADVERTISE_100FULL);
1684
1685 if (adv & ADVERTISED_10baseT_Half)
1686 auto_nego |= ADVERTISE_10HALF;
1687 if (adv & ADVERTISED_10baseT_Full)
1688 auto_nego |= ADVERTISE_10FULL;
1689 if (adv & ADVERTISED_100baseT_Half)
1690 auto_nego |= ADVERTISE_100HALF;
1691 if (adv & ADVERTISED_100baseT_Full)
1692 auto_nego |= ADVERTISE_100FULL;
1693
3577aa1b 1694 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1695
4da19633 1696 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1697 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1698
3577aa1b 1699 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1700 if (tp->mii.supports_gmii) {
54405cde
ON		 1701 if (adv & ADVERTISED_1000baseT_Half)
1702 giga_ctrl |= ADVERTISE_1000HALF;
1703 if (adv & ADVERTISED_1000baseT_Full)
1704 giga_ctrl |= ADVERTISE_1000FULL;
1705 } else if (adv & (ADVERTISED_1000baseT_Half |
1706 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1707 netif_info(tp, link, dev,
1708 "PHY does not support 1000Mbps\n");
54405cde 1709 goto out;
bcf0bf90 1710 }
1da177e4 1711
3577aa1b 1712 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1713
4da19633 1714 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1715 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1716 } else {
1717 giga_ctrl = 0;
1718
1719 if (speed == SPEED_10)
1720 bmcr = 0;
1721 else if (speed == SPEED_100)
1722 bmcr = BMCR_SPEED100;
1723 else
54405cde 1724 goto out;
3577aa1b 1725
1726 if (duplex == DUPLEX_FULL)
1727 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1728 }
1729
4da19633 1730 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1731
cecb5fd7
FR		 1732 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1733 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1734 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1735 rtl_writephy(tp, 0x17, 0x2138);
1736 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1737 } else {
4da19633 1738 rtl_writephy(tp, 0x17, 0x2108);
1739 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1740 }
1741 }
1742
54405cde
ON		 1743 rc = 0;
1744out:
1745 return rc;
1da177e4
LT		 1746}
1747
1748static int rtl8169_set_speed(struct net_device *dev,
54405cde 1749 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1750{
1751 struct rtl8169_private *tp = netdev_priv(dev);
1752 int ret;
1753
54405cde 1754 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1755 if (ret < 0)
1756 goto out;
1da177e4 1757
4876cc1e
FR		 1758 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1759 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1760 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1761 }
1762out:
1da177e4
LT		 1763 return ret;
1764}
1765
1766static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1767{
1768 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1769 int ret;
1770
4876cc1e
FR		 1771 del_timer_sync(&tp->timer);
1772
da78dbff 1773 rtl_lock_work(tp);
cecb5fd7 1774 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1775 cmd->duplex, cmd->advertising);
da78dbff 1776 rtl_unlock_work(tp);
5b0384f4 1777
1da177e4
LT		 1778 return ret;
1779}
1780
c8f44aff
MM		 1781static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1782 netdev_features_t features)
1da177e4 1783{
d58d46b5
FR		 1784 struct rtl8169_private *tp = netdev_priv(dev);
1785
2b7b4318 1786 if (dev->mtu > TD_MSS_MAX)
350fb32a 1787 features &= ~NETIF_F_ALL_TSO;
1da177e4 1788
d58d46b5
FR		 1789 if (dev->mtu > JUMBO_1K &&
1790 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1791 features &= ~NETIF_F_IP_CSUM;
1792
350fb32a 1793 return features;
1da177e4
LT		 1794}
1795
da78dbff
FR		 1796static void __rtl8169_set_features(struct net_device *dev,
1797 netdev_features_t features)
1da177e4
LT		 1798{
1799 struct rtl8169_private *tp = netdev_priv(dev);
6bbe021d 1800 netdev_features_t changed = features ^ dev->features;
da78dbff 1801 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1802
f646968f
PM		 1803 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM |
1804 NETIF_F_HW_VLAN_CTAG_RX)))
6bbe021d 1805 return;
1da177e4 1806
f646968f 1807 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) {
6bbe021d
BG		 1808 if (features & NETIF_F_RXCSUM)
1809 tp->cp_cmd |= RxChkSum;
1810 else
1811 tp->cp_cmd &= ~RxChkSum;
350fb32a 1812
f646968f 1813 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
6bbe021d
BG		 1814 tp->cp_cmd |= RxVlan;
1815 else
1816 tp->cp_cmd &= ~RxVlan;
1817
1818 RTL_W16(CPlusCmd, tp->cp_cmd);
1819 RTL_R16(CPlusCmd);
1820 }
1821 if (changed & NETIF_F_RXALL) {
1822 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1823 if (features & NETIF_F_RXALL)
1824 tmp |= (AcceptErr | AcceptRunt);
1825 RTL_W32(RxConfig, tmp);
1826 }
da78dbff 1827}
1da177e4 1828
da78dbff
FR		 1829static int rtl8169_set_features(struct net_device *dev,
1830 netdev_features_t features)
1831{
1832 struct rtl8169_private *tp = netdev_priv(dev);
1833
1834 rtl_lock_work(tp);
1835 __rtl8169_set_features(dev, features);
1836 rtl_unlock_work(tp);
1da177e4
LT		 1837
1838 return 0;
1839}
1840
da78dbff 1841
810f4893 1842static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1843{
eab6d18d 1844 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1845 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1846}
1847
7a8fc77b 1848static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1849{
1850 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1851
7a8fc77b 1852 if (opts2 & RxVlanTag)
86a9bad3 1853 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1854}
1855
ccdffb9a 1856static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1857{
1858 struct rtl8169_private *tp = netdev_priv(dev);
1859 void __iomem *ioaddr = tp->mmio_addr;
1860 u32 status;
1861
1862 cmd->supported =
1863 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1864 cmd->port = PORT_FIBRE;
1865 cmd->transceiver = XCVR_INTERNAL;
1866
1867 status = RTL_R32(TBICSR);
1868 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1869 cmd->autoneg = !!(status & TBINwEnable);
1870
70739497 1871 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1872 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1873
1874 return 0;
1da177e4
LT		 1875}
1876
ccdffb9a 1877static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1878{
1879 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1880
1881 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1882}
1883
1884static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1885{
1886 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1887 int rc;
1da177e4 1888
da78dbff 1889 rtl_lock_work(tp);
ccdffb9a 1890 rc = tp->get_settings(dev, cmd);
da78dbff 1891 rtl_unlock_work(tp);
1da177e4 1892
ccdffb9a 1893 return rc;
1da177e4
LT		 1894}
1895
1896static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1897 void *p)
1898{
5b0384f4 1899 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1900
da78dbff 1901 rtl_lock_work(tp);
5b0384f4 1902 memcpy_fromio(p, tp->mmio_addr, regs->len);
da78dbff 1903 rtl_unlock_work(tp);
1da177e4
LT		 1904}
1905
b57b7e5a
SH		 1906static u32 rtl8169_get_msglevel(struct net_device *dev)
1907{
1908 struct rtl8169_private *tp = netdev_priv(dev);
1909
1910 return tp->msg_enable;
1911}
1912
1913static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1914{
1915 struct rtl8169_private *tp = netdev_priv(dev);
1916
1917 tp->msg_enable = value;
1918}
1919
d4a3a0fc
SH		 1920static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1921 "tx_packets",
1922 "rx_packets",
1923 "tx_errors",
1924 "rx_errors",
1925 "rx_missed",
1926 "align_errors",
1927 "tx_single_collisions",
1928 "tx_multi_collisions",
1929 "unicast",
1930 "broadcast",
1931 "multicast",
1932 "tx_aborted",
1933 "tx_underrun",
1934};
1935
b9f2c044 1936static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1937{
b9f2c044
JG		 1938 switch (sset) {
1939 case ETH_SS_STATS:
1940 return ARRAY_SIZE(rtl8169_gstrings);
1941 default:
1942 return -EOPNOTSUPP;
1943 }
d4a3a0fc
SH		 1944}
1945
ffc46952
FR		 1946DECLARE_RTL_COND(rtl_counters_cond)
1947{
1948 void __iomem *ioaddr = tp->mmio_addr;
1949
1950 return RTL_R32(CounterAddrLow) & CounterDump;
1951}
1952
355423d0 1953static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1954{
1955 struct rtl8169_private *tp = netdev_priv(dev);
1956 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1957 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1958 struct rtl8169_counters *counters;
1959 dma_addr_t paddr;
1960 u32 cmd;
1961
355423d0
IV		 1962 /*
1963 * Some chips are unable to dump tally counters when the receiver
1964 * is disabled.
1965 */
1966 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1967 return;
d4a3a0fc 1968
48addcc9 1969 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1970 if (!counters)
1971 return;
1972
1973 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1974 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1975 RTL_W32(CounterAddrLow, cmd);
1976 RTL_W32(CounterAddrLow, cmd | CounterDump);
1977
ffc46952
FR		 1978 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1979 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc
SH		 1980
1981 RTL_W32(CounterAddrLow, 0);
1982 RTL_W32(CounterAddrHigh, 0);
1983
48addcc9 1984 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1985}
1986
355423d0
IV		 1987static void rtl8169_get_ethtool_stats(struct net_device *dev,
1988 struct ethtool_stats *stats, u64 *data)
1989{
1990 struct rtl8169_private *tp = netdev_priv(dev);
1991
1992 ASSERT_RTNL();
1993
1994 rtl8169_update_counters(dev);
1995
1996 data[0] = le64_to_cpu(tp->counters.tx_packets);
1997 data[1] = le64_to_cpu(tp->counters.rx_packets);
1998 data[2] = le64_to_cpu(tp->counters.tx_errors);
1999 data[3] = le32_to_cpu(tp->counters.rx_errors);
2000 data[4] = le16_to_cpu(tp->counters.rx_missed);
2001 data[5] = le16_to_cpu(tp->counters.align_errors);
2002 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2003 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2004 data[8] = le64_to_cpu(tp->counters.rx_unicast);
2005 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2006 data[10] = le32_to_cpu(tp->counters.rx_multicast);
2007 data[11] = le16_to_cpu(tp->counters.tx_aborted);
2008 data[12] = le16_to_cpu(tp->counters.tx_underun);
2009}
2010
d4a3a0fc
SH		 2011static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2012{
2013 switch(stringset) {
2014 case ETH_SS_STATS:
2015 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2016 break;
2017 }
2018}
2019
7282d491 2020static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2021 .get_drvinfo = rtl8169_get_drvinfo,
2022 .get_regs_len = rtl8169_get_regs_len,
2023 .get_link = ethtool_op_get_link,
2024 .get_settings = rtl8169_get_settings,
2025 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2026 .get_msglevel = rtl8169_get_msglevel,
2027 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2028 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2029 .get_wol = rtl8169_get_wol,
2030 .set_wol = rtl8169_set_wol,
d4a3a0fc 2031 .get_strings = rtl8169_get_strings,
b9f2c044 2032 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2033 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2034 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2035};
2036
07d3f51f 2037static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2038 struct net_device *dev, u8 default_version)
1da177e4 2039{
5d320a20 2040 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2041 /*
2042 * The driver currently handles the 8168Bf and the 8168Be identically
2043 * but they can be identified more specifically through the test below
2044 * if needed:
2045 *
2046 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2047 *
2048 * Same thing for the 8101Eb and the 8101Ec:
2049 *
2050 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2051 */
3744100e 2052 static const struct rtl_mac_info {
1da177e4 2053 u32 mask;
e3cf0cc0 2054 u32 val;
1da177e4
LT		 2055 int mac_version;
2056 } mac_info[] = {
c558386b 2057 /* 8168G family. */
45dd95c4 2058 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2059 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2060 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2061 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2062
c2218925 2063 /* 8168F family. */
b3d7b2f2 2064 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2065 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2066 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2067
01dc7fec 2068 /* 8168E family. */
70090424 2069 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2070 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2071 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2072 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2073
5b538df9 2074 /* 8168D family. */
daf9df6d 2075 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2076 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2077 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2078
e6de30d6 2079 /* 8168DP family. */
2080 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2081 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2082 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2083
ef808d50 2084 /* 8168C family. */
17c99297 2085 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2086 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2087 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2088 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2089 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2090 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2091 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2092 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2093 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2094
2095 /* 8168B family. */
2096 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2097 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2098 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2099 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2100
2101 /* 8101 family. */
5598bfe5
HW		 2102 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2103 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2104 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2105 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2106 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2107 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2108 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2109 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2110 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2111 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2112 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2113 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2114 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2115 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2116 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2117 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2118 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2119 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2120 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2121 /* FIXME: where did these entries come from ? -- FR */
2122 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2123 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2124
2125 /* 8110 family. */
2126 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2127 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2128 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2129 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2130 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2131 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2132
f21b75e9
JD		 2133 /* Catch-all */
2134 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2135 };
2136 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2137 u32 reg;
2138
e3cf0cc0
FR		 2139 reg = RTL_R32(TxConfig);
2140 while ((reg & p->mask) != p->val)
1da177e4
LT		 2141 p++;
2142 tp->mac_version = p->mac_version;
5d320a20
FR		 2143
2144 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2145 netif_notice(tp, probe, dev,
2146 "unknown MAC, using family default\n");
2147 tp->mac_version = default_version;
58152cd4 2148 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2149 tp->mac_version = tp->mii.supports_gmii ?
2150 RTL_GIGA_MAC_VER_42 :
2151 RTL_GIGA_MAC_VER_43;
5d320a20 2152 }
1da177e4
LT		 2153}
2154
2155static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2156{
bcf0bf90 2157 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2158}
2159
867763c1
FR		 2160struct phy_reg {
2161 u16 reg;
2162 u16 val;
2163};
2164
4da19633 2165static void rtl_writephy_batch(struct rtl8169_private *tp,
2166 const struct phy_reg *regs, int len)
867763c1
FR		 2167{
2168 while (len-- > 0) {
4da19633 2169 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2170 regs++;
2171 }
2172}
2173
bca03d5f 2174#define PHY_READ 0x00000000
2175#define PHY_DATA_OR 0x10000000
2176#define PHY_DATA_AND 0x20000000
2177#define PHY_BJMPN 0x30000000
eee3786f 2178#define PHY_MDIO_CHG 0x40000000
bca03d5f 2179#define PHY_CLEAR_READCOUNT 0x70000000
2180#define PHY_WRITE 0x80000000
2181#define PHY_READCOUNT_EQ_SKIP 0x90000000
2182#define PHY_COMP_EQ_SKIPN 0xa0000000
2183#define PHY_COMP_NEQ_SKIPN 0xb0000000
2184#define PHY_WRITE_PREVIOUS 0xc0000000
2185#define PHY_SKIPN 0xd0000000
2186#define PHY_DELAY_MS 0xe0000000
bca03d5f 2187
960aee6c
HW		 2188struct fw_info {
2189 u32 magic;
2190 char version[RTL_VER_SIZE];
2191 __le32 fw_start;
2192 __le32 fw_len;
2193 u8 chksum;
2194} __packed;
2195
1c361efb
FR		 2196#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2197
2198static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2199{
b6ffd97f 2200 const struct firmware *fw = rtl_fw->fw;
960aee6c 2201 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2202 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2203 char *version = rtl_fw->version;
2204 bool rc = false;
2205
2206 if (fw->size < FW_OPCODE_SIZE)
2207 goto out;
960aee6c
HW		 2208
2209 if (!fw_info->magic) {
2210 size_t i, size, start;
2211 u8 checksum = 0;
2212
2213 if (fw->size < sizeof(*fw_info))
2214 goto out;
2215
2216 for (i = 0; i < fw->size; i++)
2217 checksum += fw->data[i];
2218 if (checksum != 0)
2219 goto out;
2220
2221 start = le32_to_cpu(fw_info->fw_start);
2222 if (start > fw->size)
2223 goto out;
2224
2225 size = le32_to_cpu(fw_info->fw_len);
2226 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2227 goto out;
2228
2229 memcpy(version, fw_info->version, RTL_VER_SIZE);
2230
2231 pa->code = (__le32 *)(fw->data + start);
2232 pa->size = size;
2233 } else {
1c361efb
FR		 2234 if (fw->size % FW_OPCODE_SIZE)
2235 goto out;
2236
2237 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2238
2239 pa->code = (__le32 *)fw->data;
2240 pa->size = fw->size / FW_OPCODE_SIZE;
2241 }
2242 version[RTL_VER_SIZE - 1] = 0;
2243
2244 rc = true;
2245out:
2246 return rc;
2247}
2248
fd112f2e
FR		 2249static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2250 struct rtl_fw_phy_action *pa)
1c361efb 2251{
fd112f2e 2252 bool rc = false;
1c361efb 2253 size_t index;
bca03d5f 2254
1c361efb
FR		 2255 for (index = 0; index < pa->size; index++) {
2256 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2257 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2258
42b82dc1 2259 switch(action & 0xf0000000) {
2260 case PHY_READ:
2261 case PHY_DATA_OR:
2262 case PHY_DATA_AND:
eee3786f 2263 case PHY_MDIO_CHG:
42b82dc1 2264 case PHY_CLEAR_READCOUNT:
2265 case PHY_WRITE:
2266 case PHY_WRITE_PREVIOUS:
2267 case PHY_DELAY_MS:
2268 break;
2269
2270 case PHY_BJMPN:
2271 if (regno > index) {
fd112f2e 2272 netif_err(tp, ifup, tp->dev,
cecb5fd7 2273 "Out of range of firmware\n");
fd112f2e 2274 goto out;
42b82dc1 2275 }
2276 break;
2277 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2278 if (index + 2 >= pa->size) {
fd112f2e 2279 netif_err(tp, ifup, tp->dev,
cecb5fd7 2280 "Out of range of firmware\n");
fd112f2e 2281 goto out;
42b82dc1 2282 }
2283 break;
2284 case PHY_COMP_EQ_SKIPN:
2285 case PHY_COMP_NEQ_SKIPN:
2286 case PHY_SKIPN:
1c361efb 2287 if (index + 1 + regno >= pa->size) {
fd112f2e 2288 netif_err(tp, ifup, tp->dev,
cecb5fd7 2289 "Out of range of firmware\n");
fd112f2e 2290 goto out;
42b82dc1 2291 }
bca03d5f 2292 break;
2293
42b82dc1 2294 default:
fd112f2e 2295 netif_err(tp, ifup, tp->dev,
42b82dc1 2296 "Invalid action 0x%08x\n", action);
fd112f2e 2297 goto out;
bca03d5f 2298 }
2299 }
fd112f2e
FR		 2300 rc = true;
2301out:
2302 return rc;
2303}
bca03d5f 2304
fd112f2e
FR		 2305static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2306{
2307 struct net_device *dev = tp->dev;
2308 int rc = -EINVAL;
2309
2310 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2311 netif_err(tp, ifup, dev, "invalid firwmare\n");
2312 goto out;
2313 }
2314
2315 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2316 rc = 0;
2317out:
2318 return rc;
2319}
2320
2321static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2322{
2323 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2324 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2325 u32 predata, count;
2326 size_t index;
2327
2328 predata = count = 0;
eee3786f 2329 org.write = ops->write;
2330 org.read = ops->read;
42b82dc1 2331
1c361efb
FR		 2332 for (index = 0; index < pa->size; ) {
2333 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2334 u32 data = action & 0x0000ffff;
42b82dc1 2335 u32 regno = (action & 0x0fff0000) >> 16;
2336
2337 if (!action)
2338 break;
bca03d5f 2339
2340 switch(action & 0xf0000000) {
42b82dc1 2341 case PHY_READ:
2342 predata = rtl_readphy(tp, regno);
2343 count++;
2344 index++;
2345 break;
2346 case PHY_DATA_OR:
2347 predata |= data;
2348 index++;
2349 break;
2350 case PHY_DATA_AND:
2351 predata &= data;
2352 index++;
2353 break;
2354 case PHY_BJMPN:
2355 index -= regno;
2356 break;
eee3786f 2357 case PHY_MDIO_CHG:
2358 if (data == 0) {
2359 ops->write = org.write;
2360 ops->read = org.read;
2361 } else if (data == 1) {
2362 ops->write = mac_mcu_write;
2363 ops->read = mac_mcu_read;
2364 }
2365
42b82dc1 2366 index++;
2367 break;
2368 case PHY_CLEAR_READCOUNT:
2369 count = 0;
2370 index++;
2371 break;
bca03d5f 2372 case PHY_WRITE:
42b82dc1 2373 rtl_writephy(tp, regno, data);
2374 index++;
2375 break;
2376 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2377 index += (count == data) ? 2 : 1;
bca03d5f 2378 break;
42b82dc1 2379 case PHY_COMP_EQ_SKIPN:
2380 if (predata == data)
2381 index += regno;
2382 index++;
2383 break;
2384 case PHY_COMP_NEQ_SKIPN:
2385 if (predata != data)
2386 index += regno;
2387 index++;
2388 break;
2389 case PHY_WRITE_PREVIOUS:
2390 rtl_writephy(tp, regno, predata);
2391 index++;
2392 break;
2393 case PHY_SKIPN:
2394 index += regno + 1;
2395 break;
2396 case PHY_DELAY_MS:
2397 mdelay(data);
2398 index++;
2399 break;
2400
bca03d5f 2401 default:
2402 BUG();
2403 }
2404 }
eee3786f 2405
2406 ops->write = org.write;
2407 ops->read = org.read;
bca03d5f 2408}
2409
f1e02ed1 2410static void rtl_release_firmware(struct rtl8169_private *tp)
2411{
b6ffd97f
FR		 2412 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2413 release_firmware(tp->rtl_fw->fw);
2414 kfree(tp->rtl_fw);
2415 }
2416 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2417}
2418
953a12cc 2419static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2420{
b6ffd97f 2421 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2422
2423 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2424 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2425 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2426}
2427
2428static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2429{
2430 if (rtl_readphy(tp, reg) != val)
2431 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2432 else
2433 rtl_apply_firmware(tp);
f1e02ed1 2434}
2435
4da19633 2436static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2437{
350f7596 2438 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2439 { 0x1f, 0x0001 },
2440 { 0x06, 0x006e },
2441 { 0x08, 0x0708 },
2442 { 0x15, 0x4000 },
2443 { 0x18, 0x65c7 },
1da177e4 2444
0b9b571d 2445 { 0x1f, 0x0001 },
2446 { 0x03, 0x00a1 },
2447 { 0x02, 0x0008 },
2448 { 0x01, 0x0120 },
2449 { 0x00, 0x1000 },
2450 { 0x04, 0x0800 },
2451 { 0x04, 0x0000 },
1da177e4 2452
0b9b571d 2453 { 0x03, 0xff41 },
2454 { 0x02, 0xdf60 },
2455 { 0x01, 0x0140 },
2456 { 0x00, 0x0077 },
2457 { 0x04, 0x7800 },
2458 { 0x04, 0x7000 },
2459
2460 { 0x03, 0x802f },
2461 { 0x02, 0x4f02 },
2462 { 0x01, 0x0409 },
2463 { 0x00, 0xf0f9 },
2464 { 0x04, 0x9800 },
2465 { 0x04, 0x9000 },
2466
2467 { 0x03, 0xdf01 },
2468 { 0x02, 0xdf20 },
2469 { 0x01, 0xff95 },
2470 { 0x00, 0xba00 },
2471 { 0x04, 0xa800 },
2472 { 0x04, 0xa000 },
2473
2474 { 0x03, 0xff41 },
2475 { 0x02, 0xdf20 },
2476 { 0x01, 0x0140 },
2477 { 0x00, 0x00bb },
2478 { 0x04, 0xb800 },
2479 { 0x04, 0xb000 },
2480
2481 { 0x03, 0xdf41 },
2482 { 0x02, 0xdc60 },
2483 { 0x01, 0x6340 },
2484 { 0x00, 0x007d },
2485 { 0x04, 0xd800 },
2486 { 0x04, 0xd000 },
2487
2488 { 0x03, 0xdf01 },
2489 { 0x02, 0xdf20 },
2490 { 0x01, 0x100a },
2491 { 0x00, 0xa0ff },
2492 { 0x04, 0xf800 },
2493 { 0x04, 0xf000 },
2494
2495 { 0x1f, 0x0000 },
2496 { 0x0b, 0x0000 },
2497 { 0x00, 0x9200 }
2498 };
1da177e4 2499
4da19633 2500 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2501}
2502
4da19633 2503static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2504{
350f7596 2505 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2506 { 0x1f, 0x0002 },
2507 { 0x01, 0x90d0 },
2508 { 0x1f, 0x0000 }
2509 };
2510
4da19633 2511 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2512}
2513
4da19633 2514static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2515{
2516 struct pci_dev *pdev = tp->pci_dev;
2e955856 2517
ccbae55e
SS		 2518 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2519 (pdev->subsystem_device != 0xe000))
2e955856 2520 return;
2521
4da19633 2522 rtl_writephy(tp, 0x1f, 0x0001);
2523 rtl_writephy(tp, 0x10, 0xf01b);
2524 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2525}
2526
4da19633 2527static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2528{
350f7596 2529 static const struct phy_reg phy_reg_init[] = {
2e955856 2530 { 0x1f, 0x0001 },
2531 { 0x04, 0x0000 },
2532 { 0x03, 0x00a1 },
2533 { 0x02, 0x0008 },
2534 { 0x01, 0x0120 },
2535 { 0x00, 0x1000 },
2536 { 0x04, 0x0800 },
2537 { 0x04, 0x9000 },
2538 { 0x03, 0x802f },
2539 { 0x02, 0x4f02 },
2540 { 0x01, 0x0409 },
2541 { 0x00, 0xf099 },
2542 { 0x04, 0x9800 },
2543 { 0x04, 0xa000 },
2544 { 0x03, 0xdf01 },
2545 { 0x02, 0xdf20 },
2546 { 0x01, 0xff95 },
2547 { 0x00, 0xba00 },
2548 { 0x04, 0xa800 },
2549 { 0x04, 0xf000 },
2550 { 0x03, 0xdf01 },
2551 { 0x02, 0xdf20 },
2552 { 0x01, 0x101a },
2553 { 0x00, 0xa0ff },
2554 { 0x04, 0xf800 },
2555 { 0x04, 0x0000 },
2556 { 0x1f, 0x0000 },
2557
2558 { 0x1f, 0x0001 },
2559 { 0x10, 0xf41b },
2560 { 0x14, 0xfb54 },
2561 { 0x18, 0xf5c7 },
2562 { 0x1f, 0x0000 },
2563
2564 { 0x1f, 0x0001 },
2565 { 0x17, 0x0cc0 },
2566 { 0x1f, 0x0000 }
2567 };
2568
4da19633 2569 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2570
4da19633 2571 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2572}
2573
4da19633 2574static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2575{
350f7596 2576 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2577 { 0x1f, 0x0001 },
2578 { 0x04, 0x0000 },
2579 { 0x03, 0x00a1 },
2580 { 0x02, 0x0008 },
2581 { 0x01, 0x0120 },
2582 { 0x00, 0x1000 },
2583 { 0x04, 0x0800 },
2584 { 0x04, 0x9000 },
2585 { 0x03, 0x802f },
2586 { 0x02, 0x4f02 },
2587 { 0x01, 0x0409 },
2588 { 0x00, 0xf099 },
2589 { 0x04, 0x9800 },
2590 { 0x04, 0xa000 },
2591 { 0x03, 0xdf01 },
2592 { 0x02, 0xdf20 },
2593 { 0x01, 0xff95 },
2594 { 0x00, 0xba00 },
2595 { 0x04, 0xa800 },
2596 { 0x04, 0xf000 },
2597 { 0x03, 0xdf01 },
2598 { 0x02, 0xdf20 },
2599 { 0x01, 0x101a },
2600 { 0x00, 0xa0ff },
2601 { 0x04, 0xf800 },
2602 { 0x04, 0x0000 },
2603 { 0x1f, 0x0000 },
2604
2605 { 0x1f, 0x0001 },
2606 { 0x0b, 0x8480 },
2607 { 0x1f, 0x0000 },
2608
2609 { 0x1f, 0x0001 },
2610 { 0x18, 0x67c7 },
2611 { 0x04, 0x2000 },
2612 { 0x03, 0x002f },
2613 { 0x02, 0x4360 },
2614 { 0x01, 0x0109 },
2615 { 0x00, 0x3022 },
2616 { 0x04, 0x2800 },
2617 { 0x1f, 0x0000 },
2618
2619 { 0x1f, 0x0001 },
2620 { 0x17, 0x0cc0 },
2621 { 0x1f, 0x0000 }
2622 };
2623
4da19633 2624 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2625}
2626
4da19633 2627static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2628{
350f7596 2629 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2630 { 0x10, 0xf41b },
2631 { 0x1f, 0x0000 }
2632 };
2633
4da19633 2634 rtl_writephy(tp, 0x1f, 0x0001);
2635 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2636
4da19633 2637 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2638}
2639
4da19633 2640static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2641{
350f7596 2642 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2643 { 0x1f, 0x0001 },
2644 { 0x10, 0xf41b },
2645 { 0x1f, 0x0000 }
2646 };
2647
4da19633 2648 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2649}
2650
4da19633 2651static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2652{
350f7596 2653 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2654 { 0x1f, 0x0000 },
2655 { 0x1d, 0x0f00 },
2656 { 0x1f, 0x0002 },
2657 { 0x0c, 0x1ec8 },
2658 { 0x1f, 0x0000 }
2659 };
2660
4da19633 2661 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2662}
2663
4da19633 2664static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2665{
350f7596 2666 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2667 { 0x1f, 0x0001 },
2668 { 0x1d, 0x3d98 },
2669 { 0x1f, 0x0000 }
2670 };
2671
4da19633 2672 rtl_writephy(tp, 0x1f, 0x0000);
2673 rtl_patchphy(tp, 0x14, 1 << 5);
2674 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2675
4da19633 2676 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2677}
2678
4da19633 2679static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2680{
350f7596 2681 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2682 { 0x1f, 0x0001 },
2683 { 0x12, 0x2300 },
867763c1
FR		 2684 { 0x1f, 0x0002 },
2685 { 0x00, 0x88d4 },
2686 { 0x01, 0x82b1 },
2687 { 0x03, 0x7002 },
2688 { 0x08, 0x9e30 },
2689 { 0x09, 0x01f0 },
2690 { 0x0a, 0x5500 },
2691 { 0x0c, 0x00c8 },
2692 { 0x1f, 0x0003 },
2693 { 0x12, 0xc096 },
2694 { 0x16, 0x000a },
f50d4275
FR		 2695 { 0x1f, 0x0000 },
2696 { 0x1f, 0x0000 },
2697 { 0x09, 0x2000 },
2698 { 0x09, 0x0000 }
867763c1
FR		 2699 };
2700
4da19633 2701 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2702
4da19633 2703 rtl_patchphy(tp, 0x14, 1 << 5);
2704 rtl_patchphy(tp, 0x0d, 1 << 5);
2705 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2706}
2707
4da19633 2708static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2709{
350f7596 2710 static const struct phy_reg phy_reg_init[] = {
f50d4275 2711 { 0x1f, 0x0001 },
7da97ec9 2712 { 0x12, 0x2300 },
f50d4275
FR		 2713 { 0x03, 0x802f },
2714 { 0x02, 0x4f02 },
2715 { 0x01, 0x0409 },
2716 { 0x00, 0xf099 },
2717 { 0x04, 0x9800 },
2718 { 0x04, 0x9000 },
2719 { 0x1d, 0x3d98 },
7da97ec9
FR		 2720 { 0x1f, 0x0002 },
2721 { 0x0c, 0x7eb8 },
f50d4275
FR		 2722 { 0x06, 0x0761 },
2723 { 0x1f, 0x0003 },
2724 { 0x16, 0x0f0a },
7da97ec9
FR		 2725 { 0x1f, 0x0000 }
2726 };
2727
4da19633 2728 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2729
4da19633 2730 rtl_patchphy(tp, 0x16, 1 << 0);
2731 rtl_patchphy(tp, 0x14, 1 << 5);
2732 rtl_patchphy(tp, 0x0d, 1 << 5);
2733 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2734}
2735
4da19633 2736static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2737{
350f7596 2738 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2739 { 0x1f, 0x0001 },
2740 { 0x12, 0x2300 },
2741 { 0x1d, 0x3d98 },
2742 { 0x1f, 0x0002 },
2743 { 0x0c, 0x7eb8 },
2744 { 0x06, 0x5461 },
2745 { 0x1f, 0x0003 },
2746 { 0x16, 0x0f0a },
2747 { 0x1f, 0x0000 }
2748 };
2749
4da19633 2750 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2751
4da19633 2752 rtl_patchphy(tp, 0x16, 1 << 0);
2753 rtl_patchphy(tp, 0x14, 1 << 5);
2754 rtl_patchphy(tp, 0x0d, 1 << 5);
2755 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2756}
2757
4da19633 2758static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2759{
4da19633 2760 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2761}
2762
bca03d5f 2763static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2764{
350f7596 2765 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2766 /* Channel Estimation */
5b538df9 2767 { 0x1f, 0x0001 },
daf9df6d 2768 { 0x06, 0x4064 },
2769 { 0x07, 0x2863 },
2770 { 0x08, 0x059c },
2771 { 0x09, 0x26b4 },
2772 { 0x0a, 0x6a19 },
2773 { 0x0b, 0xdcc8 },
2774 { 0x10, 0xf06d },
2775 { 0x14, 0x7f68 },
2776 { 0x18, 0x7fd9 },
2777 { 0x1c, 0xf0ff },
2778 { 0x1d, 0x3d9c },
5b538df9 2779 { 0x1f, 0x0003 },
daf9df6d 2780 { 0x12, 0xf49f },
2781 { 0x13, 0x070b },
2782 { 0x1a, 0x05ad },
bca03d5f 2783 { 0x14, 0x94c0 },
2784
2785 /*
2786 * Tx Error Issue
cecb5fd7 2787 * Enhance line driver power
bca03d5f 2788 */
5b538df9 2789 { 0x1f, 0x0002 },
daf9df6d 2790 { 0x06, 0x5561 },
2791 { 0x1f, 0x0005 },
2792 { 0x05, 0x8332 },
bca03d5f 2793 { 0x06, 0x5561 },
2794
2795 /*
2796 * Can not link to 1Gbps with bad cable
2797 * Decrease SNR threshold form 21.07dB to 19.04dB
2798 */
2799 { 0x1f, 0x0001 },
2800 { 0x17, 0x0cc0 },
daf9df6d 2801
5b538df9 2802 { 0x1f, 0x0000 },
bca03d5f 2803 { 0x0d, 0xf880 }
daf9df6d 2804 };
2805
4da19633 2806 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2807
bca03d5f 2808 /*
2809 * Rx Error Issue
2810 * Fine Tune Switching regulator parameter
2811 */
4da19633 2812 rtl_writephy(tp, 0x1f, 0x0002);
2813 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2814 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2815
fdf6fc06 2816 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2817 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2818 { 0x1f, 0x0002 },
2819 { 0x05, 0x669a },
2820 { 0x1f, 0x0005 },
2821 { 0x05, 0x8330 },
2822 { 0x06, 0x669a },
2823 { 0x1f, 0x0002 }
2824 };
2825 int val;
2826
4da19633 2827 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2828
4da19633 2829 val = rtl_readphy(tp, 0x0d);
daf9df6d 2830
2831 if ((val & 0x00ff) != 0x006c) {
350f7596 2832 static const u32 set[] = {
daf9df6d 2833 0x0065, 0x0066, 0x0067, 0x0068,
2834 0x0069, 0x006a, 0x006b, 0x006c
2835 };
2836 int i;
2837
4da19633 2838 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2839
2840 val &= 0xff00;
2841 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2842 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2843 }
2844 } else {
350f7596 2845 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2846 { 0x1f, 0x0002 },
2847 { 0x05, 0x6662 },
2848 { 0x1f, 0x0005 },
2849 { 0x05, 0x8330 },
2850 { 0x06, 0x6662 }
2851 };
2852
4da19633 2853 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2854 }
2855
bca03d5f 2856 /* RSET couple improve */
4da19633 2857 rtl_writephy(tp, 0x1f, 0x0002);
2858 rtl_patchphy(tp, 0x0d, 0x0300);
2859 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2860
bca03d5f 2861 /* Fine tune PLL performance */
4da19633 2862 rtl_writephy(tp, 0x1f, 0x0002);
2863 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2864 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2865
4da19633 2866 rtl_writephy(tp, 0x1f, 0x0005);
2867 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2868
2869 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2870
4da19633 2871 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2872}
2873
bca03d5f 2874static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2875{
350f7596 2876 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2877 /* Channel Estimation */
daf9df6d 2878 { 0x1f, 0x0001 },
2879 { 0x06, 0x4064 },
2880 { 0x07, 0x2863 },
2881 { 0x08, 0x059c },
2882 { 0x09, 0x26b4 },
2883 { 0x0a, 0x6a19 },
2884 { 0x0b, 0xdcc8 },
2885 { 0x10, 0xf06d },
2886 { 0x14, 0x7f68 },
2887 { 0x18, 0x7fd9 },
2888 { 0x1c, 0xf0ff },
2889 { 0x1d, 0x3d9c },
2890 { 0x1f, 0x0003 },
2891 { 0x12, 0xf49f },
2892 { 0x13, 0x070b },
2893 { 0x1a, 0x05ad },
2894 { 0x14, 0x94c0 },
2895
bca03d5f 2896 /*
2897 * Tx Error Issue
cecb5fd7 2898 * Enhance line driver power
bca03d5f 2899 */
daf9df6d 2900 { 0x1f, 0x0002 },
2901 { 0x06, 0x5561 },
2902 { 0x1f, 0x0005 },
2903 { 0x05, 0x8332 },
bca03d5f 2904 { 0x06, 0x5561 },
2905
2906 /*
2907 * Can not link to 1Gbps with bad cable
2908 * Decrease SNR threshold form 21.07dB to 19.04dB
2909 */
2910 { 0x1f, 0x0001 },
2911 { 0x17, 0x0cc0 },
daf9df6d 2912
2913 { 0x1f, 0x0000 },
bca03d5f 2914 { 0x0d, 0xf880 }
5b538df9
FR		 2915 };
2916
4da19633 2917 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2918
fdf6fc06 2919 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2920 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2921 { 0x1f, 0x0002 },
2922 { 0x05, 0x669a },
5b538df9 2923 { 0x1f, 0x0005 },
daf9df6d 2924 { 0x05, 0x8330 },
2925 { 0x06, 0x669a },
2926
2927 { 0x1f, 0x0002 }
2928 };
2929 int val;
2930
4da19633 2931 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2932
4da19633 2933 val = rtl_readphy(tp, 0x0d);
daf9df6d 2934 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2935 static const u32 set[] = {
daf9df6d 2936 0x0065, 0x0066, 0x0067, 0x0068,
2937 0x0069, 0x006a, 0x006b, 0x006c
2938 };
2939 int i;
2940
4da19633 2941 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2942
2943 val &= 0xff00;
2944 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2945 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2946 }
2947 } else {
350f7596 2948 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2949 { 0x1f, 0x0002 },
2950 { 0x05, 0x2642 },
5b538df9 2951 { 0x1f, 0x0005 },
daf9df6d 2952 { 0x05, 0x8330 },
2953 { 0x06, 0x2642 }
5b538df9
FR		 2954 };
2955
4da19633 2956 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2957 }
2958
bca03d5f 2959 /* Fine tune PLL performance */
4da19633 2960 rtl_writephy(tp, 0x1f, 0x0002);
2961 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2962 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2963
bca03d5f 2964 /* Switching regulator Slew rate */
4da19633 2965 rtl_writephy(tp, 0x1f, 0x0002);
2966 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2967
4da19633 2968 rtl_writephy(tp, 0x1f, 0x0005);
2969 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2970
2971 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2972
4da19633 2973 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2974}
2975
4da19633 2976static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2977{
350f7596 2978 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2979 { 0x1f, 0x0002 },
2980 { 0x10, 0x0008 },
2981 { 0x0d, 0x006c },
2982
2983 { 0x1f, 0x0000 },
2984 { 0x0d, 0xf880 },
2985
2986 { 0x1f, 0x0001 },
2987 { 0x17, 0x0cc0 },
2988
2989 { 0x1f, 0x0001 },
2990 { 0x0b, 0xa4d8 },
2991 { 0x09, 0x281c },
2992 { 0x07, 0x2883 },
2993 { 0x0a, 0x6b35 },
2994 { 0x1d, 0x3da4 },
2995 { 0x1c, 0xeffd },
2996 { 0x14, 0x7f52 },
2997 { 0x18, 0x7fc6 },
2998 { 0x08, 0x0601 },
2999 { 0x06, 0x4063 },
3000 { 0x10, 0xf074 },
3001 { 0x1f, 0x0003 },
3002 { 0x13, 0x0789 },
3003 { 0x12, 0xf4bd },
3004 { 0x1a, 0x04fd },
3005 { 0x14, 0x84b0 },
3006 { 0x1f, 0x0000 },
3007 { 0x00, 0x9200 },
3008
3009 { 0x1f, 0x0005 },
3010 { 0x01, 0x0340 },
3011 { 0x1f, 0x0001 },
3012 { 0x04, 0x4000 },
3013 { 0x03, 0x1d21 },
3014 { 0x02, 0x0c32 },
3015 { 0x01, 0x0200 },
3016 { 0x00, 0x5554 },
3017 { 0x04, 0x4800 },
3018 { 0x04, 0x4000 },
3019 { 0x04, 0xf000 },
3020 { 0x03, 0xdf01 },
3021 { 0x02, 0xdf20 },
3022 { 0x01, 0x101a },
3023 { 0x00, 0xa0ff },
3024 { 0x04, 0xf800 },
3025 { 0x04, 0xf000 },
3026 { 0x1f, 0x0000 },
3027
3028 { 0x1f, 0x0007 },
3029 { 0x1e, 0x0023 },
3030 { 0x16, 0x0000 },
3031 { 0x1f, 0x0000 }
3032 };
3033
4da19633 3034 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3035}
3036
e6de30d6 3037static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3038{
3039 static const struct phy_reg phy_reg_init[] = {
3040 { 0x1f, 0x0001 },
3041 { 0x17, 0x0cc0 },
3042
3043 { 0x1f, 0x0007 },
3044 { 0x1e, 0x002d },
3045 { 0x18, 0x0040 },
3046 { 0x1f, 0x0000 }
3047 };
3048
3049 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3050 rtl_patchphy(tp, 0x0d, 1 << 5);
3051}
3052
70090424 3053static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3054{
3055 static const struct phy_reg phy_reg_init[] = {
3056 /* Enable Delay cap */
3057 { 0x1f, 0x0005 },
3058 { 0x05, 0x8b80 },
3059 { 0x06, 0xc896 },
3060 { 0x1f, 0x0000 },
3061
3062 /* Channel estimation fine tune */
3063 { 0x1f, 0x0001 },
3064 { 0x0b, 0x6c20 },
3065 { 0x07, 0x2872 },
3066 { 0x1c, 0xefff },
3067 { 0x1f, 0x0003 },
3068 { 0x14, 0x6420 },
3069 { 0x1f, 0x0000 },
3070
3071 /* Update PFM & 10M TX idle timer */
3072 { 0x1f, 0x0007 },
3073 { 0x1e, 0x002f },
3074 { 0x15, 0x1919 },
3075 { 0x1f, 0x0000 },
3076
3077 { 0x1f, 0x0007 },
3078 { 0x1e, 0x00ac },
3079 { 0x18, 0x0006 },
3080 { 0x1f, 0x0000 }
3081 };
3082
15ecd039
FR		 3083 rtl_apply_firmware(tp);
3084
01dc7fec 3085 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3086
3087 /* DCO enable for 10M IDLE Power */
3088 rtl_writephy(tp, 0x1f, 0x0007);
3089 rtl_writephy(tp, 0x1e, 0x0023);
3090 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3091 rtl_writephy(tp, 0x1f, 0x0000);
3092
3093 /* For impedance matching */
3094 rtl_writephy(tp, 0x1f, 0x0002);
3095 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3096 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3097
3098 /* PHY auto speed down */
3099 rtl_writephy(tp, 0x1f, 0x0007);
3100 rtl_writephy(tp, 0x1e, 0x002d);
3101 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3102 rtl_writephy(tp, 0x1f, 0x0000);
3103 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3104
3105 rtl_writephy(tp, 0x1f, 0x0005);
3106 rtl_writephy(tp, 0x05, 0x8b86);
3107 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3108 rtl_writephy(tp, 0x1f, 0x0000);
3109
3110 rtl_writephy(tp, 0x1f, 0x0005);
3111 rtl_writephy(tp, 0x05, 0x8b85);
3112 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3113 rtl_writephy(tp, 0x1f, 0x0007);
3114 rtl_writephy(tp, 0x1e, 0x0020);
3115 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3116 rtl_writephy(tp, 0x1f, 0x0006);
3117 rtl_writephy(tp, 0x00, 0x5a00);
3118 rtl_writephy(tp, 0x1f, 0x0000);
3119 rtl_writephy(tp, 0x0d, 0x0007);
3120 rtl_writephy(tp, 0x0e, 0x003c);
3121 rtl_writephy(tp, 0x0d, 0x4007);
3122 rtl_writephy(tp, 0x0e, 0x0000);
3123 rtl_writephy(tp, 0x0d, 0x0000);
3124}
3125
9ecb9aab 3126static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3127{
3128 const u16 w[] = {
3129 addr[0] | (addr[1] << 8),
3130 addr[2] | (addr[3] << 8),
3131 addr[4] | (addr[5] << 8)
3132 };
3133 const struct exgmac_reg e[] = {
3134 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3135 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3136 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3137 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3138 };
3139
3140 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3141}
3142
70090424
HW		 3143static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3144{
3145 static const struct phy_reg phy_reg_init[] = {
3146 /* Enable Delay cap */
3147 { 0x1f, 0x0004 },
3148 { 0x1f, 0x0007 },
3149 { 0x1e, 0x00ac },
3150 { 0x18, 0x0006 },
3151 { 0x1f, 0x0002 },
3152 { 0x1f, 0x0000 },
3153 { 0x1f, 0x0000 },
3154
3155 /* Channel estimation fine tune */
3156 { 0x1f, 0x0003 },
3157 { 0x09, 0xa20f },
3158 { 0x1f, 0x0000 },
3159 { 0x1f, 0x0000 },
3160
3161 /* Green Setting */
3162 { 0x1f, 0x0005 },
3163 { 0x05, 0x8b5b },
3164 { 0x06, 0x9222 },
3165 { 0x05, 0x8b6d },
3166 { 0x06, 0x8000 },
3167 { 0x05, 0x8b76 },
3168 { 0x06, 0x8000 },
3169 { 0x1f, 0x0000 }
3170 };
3171
3172 rtl_apply_firmware(tp);
3173
3174 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3175
3176 /* For 4-corner performance improve */
3177 rtl_writephy(tp, 0x1f, 0x0005);
3178 rtl_writephy(tp, 0x05, 0x8b80);
3179 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3180 rtl_writephy(tp, 0x1f, 0x0000);
3181
3182 /* PHY auto speed down */
3183 rtl_writephy(tp, 0x1f, 0x0004);
3184 rtl_writephy(tp, 0x1f, 0x0007);
3185 rtl_writephy(tp, 0x1e, 0x002d);
3186 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3187 rtl_writephy(tp, 0x1f, 0x0002);
3188 rtl_writephy(tp, 0x1f, 0x0000);
3189 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3190
3191 /* improve 10M EEE waveform */
3192 rtl_writephy(tp, 0x1f, 0x0005);
3193 rtl_writephy(tp, 0x05, 0x8b86);
3194 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3195 rtl_writephy(tp, 0x1f, 0x0000);
3196
3197 /* Improve 2-pair detection performance */
3198 rtl_writephy(tp, 0x1f, 0x0005);
3199 rtl_writephy(tp, 0x05, 0x8b85);
3200 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3201 rtl_writephy(tp, 0x1f, 0x0000);
3202
3203 /* EEE setting */
fdf6fc06 3204 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3205 rtl_writephy(tp, 0x1f, 0x0005);
3206 rtl_writephy(tp, 0x05, 0x8b85);
3207 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3208 rtl_writephy(tp, 0x1f, 0x0004);
3209 rtl_writephy(tp, 0x1f, 0x0007);
3210 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3211 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3212 rtl_writephy(tp, 0x1f, 0x0002);
3213 rtl_writephy(tp, 0x1f, 0x0000);
3214 rtl_writephy(tp, 0x0d, 0x0007);
3215 rtl_writephy(tp, 0x0e, 0x003c);
3216 rtl_writephy(tp, 0x0d, 0x4007);
3217 rtl_writephy(tp, 0x0e, 0x0000);
3218 rtl_writephy(tp, 0x0d, 0x0000);
3219
3220 /* Green feature */
3221 rtl_writephy(tp, 0x1f, 0x0003);
3222 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3223 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3224 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3225
9ecb9aab 3226 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3227 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3228}
3229
5f886e08
HW		 3230static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3231{
3232 /* For 4-corner performance improve */
3233 rtl_writephy(tp, 0x1f, 0x0005);
3234 rtl_writephy(tp, 0x05, 0x8b80);
3235 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3236 rtl_writephy(tp, 0x1f, 0x0000);
3237
3238 /* PHY auto speed down */
3239 rtl_writephy(tp, 0x1f, 0x0007);
3240 rtl_writephy(tp, 0x1e, 0x002d);
3241 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3242 rtl_writephy(tp, 0x1f, 0x0000);
3243 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3244
3245 /* Improve 10M EEE waveform */
3246 rtl_writephy(tp, 0x1f, 0x0005);
3247 rtl_writephy(tp, 0x05, 0x8b86);
3248 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3249 rtl_writephy(tp, 0x1f, 0x0000);
3250}
3251
c2218925
HW		 3252static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3253{
3254 static const struct phy_reg phy_reg_init[] = {
3255 /* Channel estimation fine tune */
3256 { 0x1f, 0x0003 },
3257 { 0x09, 0xa20f },
3258 { 0x1f, 0x0000 },
3259
3260 /* Modify green table for giga & fnet */
3261 { 0x1f, 0x0005 },
3262 { 0x05, 0x8b55 },
3263 { 0x06, 0x0000 },
3264 { 0x05, 0x8b5e },
3265 { 0x06, 0x0000 },
3266 { 0x05, 0x8b67 },
3267 { 0x06, 0x0000 },
3268 { 0x05, 0x8b70 },
3269 { 0x06, 0x0000 },
3270 { 0x1f, 0x0000 },
3271 { 0x1f, 0x0007 },
3272 { 0x1e, 0x0078 },
3273 { 0x17, 0x0000 },
3274 { 0x19, 0x00fb },
3275 { 0x1f, 0x0000 },
3276
3277 /* Modify green table for 10M */
3278 { 0x1f, 0x0005 },
3279 { 0x05, 0x8b79 },
3280 { 0x06, 0xaa00 },
3281 { 0x1f, 0x0000 },
3282
3283 /* Disable hiimpedance detection (RTCT) */
3284 { 0x1f, 0x0003 },
3285 { 0x01, 0x328a },
3286 { 0x1f, 0x0000 }
3287 };
3288
3289 rtl_apply_firmware(tp);
3290
3291 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3292
5f886e08 3293 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3294
3295 /* Improve 2-pair detection performance */
3296 rtl_writephy(tp, 0x1f, 0x0005);
3297 rtl_writephy(tp, 0x05, 0x8b85);
3298 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3299 rtl_writephy(tp, 0x1f, 0x0000);
3300}
3301
3302static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3303{
3304 rtl_apply_firmware(tp);
3305
5f886e08 3306 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3307}
3308
b3d7b2f2
HW		 3309static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3310{
b3d7b2f2
HW		 3311 static const struct phy_reg phy_reg_init[] = {
3312 /* Channel estimation fine tune */
3313 { 0x1f, 0x0003 },
3314 { 0x09, 0xa20f },
3315 { 0x1f, 0x0000 },
3316
3317 /* Modify green table for giga & fnet */
3318 { 0x1f, 0x0005 },
3319 { 0x05, 0x8b55 },
3320 { 0x06, 0x0000 },
3321 { 0x05, 0x8b5e },
3322 { 0x06, 0x0000 },
3323 { 0x05, 0x8b67 },
3324 { 0x06, 0x0000 },
3325 { 0x05, 0x8b70 },
3326 { 0x06, 0x0000 },
3327 { 0x1f, 0x0000 },
3328 { 0x1f, 0x0007 },
3329 { 0x1e, 0x0078 },
3330 { 0x17, 0x0000 },
3331 { 0x19, 0x00aa },
3332 { 0x1f, 0x0000 },
3333
3334 /* Modify green table for 10M */
3335 { 0x1f, 0x0005 },
3336 { 0x05, 0x8b79 },
3337 { 0x06, 0xaa00 },
3338 { 0x1f, 0x0000 },
3339
3340 /* Disable hiimpedance detection (RTCT) */
3341 { 0x1f, 0x0003 },
3342 { 0x01, 0x328a },
3343 { 0x1f, 0x0000 }
3344 };
3345
3346
3347 rtl_apply_firmware(tp);
3348
3349 rtl8168f_hw_phy_config(tp);
3350
3351 /* Improve 2-pair detection performance */
3352 rtl_writephy(tp, 0x1f, 0x0005);
3353 rtl_writephy(tp, 0x05, 0x8b85);
3354 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3355 rtl_writephy(tp, 0x1f, 0x0000);
3356
3357 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3358
3359 /* Modify green table for giga */
3360 rtl_writephy(tp, 0x1f, 0x0005);
3361 rtl_writephy(tp, 0x05, 0x8b54);
3362 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3363 rtl_writephy(tp, 0x05, 0x8b5d);
3364 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3365 rtl_writephy(tp, 0x05, 0x8a7c);
3366 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3367 rtl_writephy(tp, 0x05, 0x8a7f);
3368 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3369 rtl_writephy(tp, 0x05, 0x8a82);
3370 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3371 rtl_writephy(tp, 0x05, 0x8a85);
3372 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3373 rtl_writephy(tp, 0x05, 0x8a88);
3374 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3375 rtl_writephy(tp, 0x1f, 0x0000);
3376
3377 /* uc same-seed solution */
3378 rtl_writephy(tp, 0x1f, 0x0005);
3379 rtl_writephy(tp, 0x05, 0x8b85);
3380 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3381 rtl_writephy(tp, 0x1f, 0x0000);
3382
3383 /* eee setting */
fdf6fc06 3384 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3385 rtl_writephy(tp, 0x1f, 0x0005);
3386 rtl_writephy(tp, 0x05, 0x8b85);
3387 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3388 rtl_writephy(tp, 0x1f, 0x0004);
3389 rtl_writephy(tp, 0x1f, 0x0007);
3390 rtl_writephy(tp, 0x1e, 0x0020);
3391 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3392 rtl_writephy(tp, 0x1f, 0x0000);
3393 rtl_writephy(tp, 0x0d, 0x0007);
3394 rtl_writephy(tp, 0x0e, 0x003c);
3395 rtl_writephy(tp, 0x0d, 0x4007);
3396 rtl_writephy(tp, 0x0e, 0x0000);
3397 rtl_writephy(tp, 0x0d, 0x0000);
3398
3399 /* Green feature */
3400 rtl_writephy(tp, 0x1f, 0x0003);
3401 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3402 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3403 rtl_writephy(tp, 0x1f, 0x0000);
3404}
3405
c558386b
HW		 3406static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3407{
c558386b
HW		 3408 rtl_apply_firmware(tp);
3409
41f44d13 3410 rtl_writephy(tp, 0x1f, 0x0a46);
3411 if (rtl_readphy(tp, 0x10) & 0x0100) {
3412 rtl_writephy(tp, 0x1f, 0x0bcc);
3413 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3414 } else {
3415 rtl_writephy(tp, 0x1f, 0x0bcc);
3416 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3417 }
c558386b 3418
41f44d13 3419 rtl_writephy(tp, 0x1f, 0x0a46);
3420 if (rtl_readphy(tp, 0x13) & 0x0100) {
3421 rtl_writephy(tp, 0x1f, 0x0c41);
3422 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3423 } else {
fe7524c0 3424 rtl_writephy(tp, 0x1f, 0x0c41);
3425 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3426 }
c558386b 3427
41f44d13 3428 /* Enable PHY auto speed down */
3429 rtl_writephy(tp, 0x1f, 0x0a44);
3430 rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3431
fe7524c0 3432 rtl_writephy(tp, 0x1f, 0x0bcc);
3433 rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3434 rtl_writephy(tp, 0x1f, 0x0a44);
3435 rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3436 rtl_writephy(tp, 0x1f, 0x0a43);
3437 rtl_writephy(tp, 0x13, 0x8084);
3438 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3439 rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3440
41f44d13 3441 /* EEE auto-fallback function */
3442 rtl_writephy(tp, 0x1f, 0x0a4b);
3443 rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3444
41f44d13 3445 /* Enable UC LPF tune function */
3446 rtl_writephy(tp, 0x1f, 0x0a43);
3447 rtl_writephy(tp, 0x13, 0x8012);
3448 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3449
3450 rtl_writephy(tp, 0x1f, 0x0c42);
3451 rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3452
fe7524c0 3453 /* Improve SWR Efficiency */
3454 rtl_writephy(tp, 0x1f, 0x0bcd);
3455 rtl_writephy(tp, 0x14, 0x5065);
3456 rtl_writephy(tp, 0x14, 0xd065);
3457 rtl_writephy(tp, 0x1f, 0x0bc8);
3458 rtl_writephy(tp, 0x11, 0x5655);
3459 rtl_writephy(tp, 0x1f, 0x0bcd);
3460 rtl_writephy(tp, 0x14, 0x1065);
3461 rtl_writephy(tp, 0x14, 0x9065);
3462 rtl_writephy(tp, 0x14, 0x1065);
3463
41f44d13 3464 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3465}
3466
57538c4a 3467static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3468{
3469 rtl_apply_firmware(tp);
3470}
3471
4da19633 3472static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3473{
350f7596 3474 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3475 { 0x1f, 0x0003 },
3476 { 0x08, 0x441d },
3477 { 0x01, 0x9100 },
3478 { 0x1f, 0x0000 }
3479 };
3480
4da19633 3481 rtl_writephy(tp, 0x1f, 0x0000);
3482 rtl_patchphy(tp, 0x11, 1 << 12);
3483 rtl_patchphy(tp, 0x19, 1 << 13);
3484 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3485
4da19633 3486 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3487}
3488
5a5e4443
HW		 3489static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3490{
3491 static const struct phy_reg phy_reg_init[] = {
3492 { 0x1f, 0x0005 },
3493 { 0x1a, 0x0000 },
3494 { 0x1f, 0x0000 },
3495
3496 { 0x1f, 0x0004 },
3497 { 0x1c, 0x0000 },
3498 { 0x1f, 0x0000 },
3499
3500 { 0x1f, 0x0001 },
3501 { 0x15, 0x7701 },
3502 { 0x1f, 0x0000 }
3503 };
3504
3505 /* Disable ALDPS before ram code */
eef63cc1
FR		 3506 rtl_writephy(tp, 0x1f, 0x0000);
3507 rtl_writephy(tp, 0x18, 0x0310);
3508 msleep(100);
5a5e4443 3509
953a12cc 3510 rtl_apply_firmware(tp);
5a5e4443
HW		 3511
3512 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3513}
3514
7e18dca1
HW		 3515static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3516{
7e18dca1 3517 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3518 rtl_writephy(tp, 0x1f, 0x0000);
3519 rtl_writephy(tp, 0x18, 0x0310);
3520 msleep(20);
7e18dca1
HW		 3521
3522 rtl_apply_firmware(tp);
3523
3524 /* EEE setting */
fdf6fc06 3525 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3526 rtl_writephy(tp, 0x1f, 0x0004);
3527 rtl_writephy(tp, 0x10, 0x401f);
3528 rtl_writephy(tp, 0x19, 0x7030);
3529 rtl_writephy(tp, 0x1f, 0x0000);
3530}
3531
5598bfe5
HW		 3532static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3533{
5598bfe5
HW		 3534 static const struct phy_reg phy_reg_init[] = {
3535 { 0x1f, 0x0004 },
3536 { 0x10, 0xc07f },
3537 { 0x19, 0x7030 },
3538 { 0x1f, 0x0000 }
3539 };
3540
3541 /* Disable ALDPS before ram code */
eef63cc1
FR		 3542 rtl_writephy(tp, 0x1f, 0x0000);
3543 rtl_writephy(tp, 0x18, 0x0310);
3544 msleep(100);
5598bfe5
HW		 3545
3546 rtl_apply_firmware(tp);
3547
fdf6fc06 3548 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3549 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3550
fdf6fc06 3551 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3552}
3553
5615d9f1
FR		 3554static void rtl_hw_phy_config(struct net_device *dev)
3555{
3556 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3557
3558 rtl8169_print_mac_version(tp);
3559
3560 switch (tp->mac_version) {
3561 case RTL_GIGA_MAC_VER_01:
3562 break;
3563 case RTL_GIGA_MAC_VER_02:
3564 case RTL_GIGA_MAC_VER_03:
4da19633 3565 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3566 break;
3567 case RTL_GIGA_MAC_VER_04:
4da19633 3568 rtl8169sb_hw_phy_config(tp);
5615d9f1 3569 break;
2e955856 3570 case RTL_GIGA_MAC_VER_05:
4da19633 3571 rtl8169scd_hw_phy_config(tp);
2e955856 3572 break;
8c7006aa 3573 case RTL_GIGA_MAC_VER_06:
4da19633 3574 rtl8169sce_hw_phy_config(tp);
8c7006aa 3575 break;
2857ffb7
FR		 3576 case RTL_GIGA_MAC_VER_07:
3577 case RTL_GIGA_MAC_VER_08:
3578 case RTL_GIGA_MAC_VER_09:
4da19633 3579 rtl8102e_hw_phy_config(tp);
2857ffb7 3580 break;
236b8082 3581 case RTL_GIGA_MAC_VER_11:
4da19633 3582 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3583 break;
3584 case RTL_GIGA_MAC_VER_12:
4da19633 3585 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3586 break;
3587 case RTL_GIGA_MAC_VER_17:
4da19633 3588 rtl8168bef_hw_phy_config(tp);
236b8082 3589 break;
867763c1 3590 case RTL_GIGA_MAC_VER_18:
4da19633 3591 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3592 break;
3593 case RTL_GIGA_MAC_VER_19:
4da19633 3594 rtl8168c_1_hw_phy_config(tp);
867763c1 3595 break;
7da97ec9 3596 case RTL_GIGA_MAC_VER_20:
4da19633 3597 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3598 break;
197ff761 3599 case RTL_GIGA_MAC_VER_21:
4da19633 3600 rtl8168c_3_hw_phy_config(tp);
197ff761 3601 break;
6fb07058 3602 case RTL_GIGA_MAC_VER_22:
4da19633 3603 rtl8168c_4_hw_phy_config(tp);
6fb07058 3604 break;
ef3386f0 3605 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3606 case RTL_GIGA_MAC_VER_24:
4da19633 3607 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3608 break;
5b538df9 3609 case RTL_GIGA_MAC_VER_25:
bca03d5f 3610 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3611 break;
3612 case RTL_GIGA_MAC_VER_26:
bca03d5f 3613 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3614 break;
3615 case RTL_GIGA_MAC_VER_27:
4da19633 3616 rtl8168d_3_hw_phy_config(tp);
5b538df9 3617 break;
e6de30d6 3618 case RTL_GIGA_MAC_VER_28:
3619 rtl8168d_4_hw_phy_config(tp);
3620 break;
5a5e4443
HW		 3621 case RTL_GIGA_MAC_VER_29:
3622 case RTL_GIGA_MAC_VER_30:
3623 rtl8105e_hw_phy_config(tp);
3624 break;
cecb5fd7
FR		 3625 case RTL_GIGA_MAC_VER_31:
3626 /* None. */
3627 break;
01dc7fec 3628 case RTL_GIGA_MAC_VER_32:
01dc7fec 3629 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3630 rtl8168e_1_hw_phy_config(tp);
3631 break;
3632 case RTL_GIGA_MAC_VER_34:
3633 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3634 break;
c2218925
HW		 3635 case RTL_GIGA_MAC_VER_35:
3636 rtl8168f_1_hw_phy_config(tp);
3637 break;
3638 case RTL_GIGA_MAC_VER_36:
3639 rtl8168f_2_hw_phy_config(tp);
3640 break;
ef3386f0 3641
7e18dca1
HW		 3642 case RTL_GIGA_MAC_VER_37:
3643 rtl8402_hw_phy_config(tp);
3644 break;
3645
b3d7b2f2
HW		 3646 case RTL_GIGA_MAC_VER_38:
3647 rtl8411_hw_phy_config(tp);
3648 break;
3649
5598bfe5
HW		 3650 case RTL_GIGA_MAC_VER_39:
3651 rtl8106e_hw_phy_config(tp);
3652 break;
3653
c558386b
HW		 3654 case RTL_GIGA_MAC_VER_40:
3655 rtl8168g_1_hw_phy_config(tp);
3656 break;
57538c4a 3657 case RTL_GIGA_MAC_VER_42:
58152cd4 3658 case RTL_GIGA_MAC_VER_43:
45dd95c4 3659 case RTL_GIGA_MAC_VER_44:
57538c4a 3660 rtl8168g_2_hw_phy_config(tp);
3661 break;
c558386b
HW		 3662
3663 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3664 default:
3665 break;
3666 }
3667}
3668
da78dbff 3669static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3670{
1da177e4
LT		 3671 struct timer_list *timer = &tp->timer;
3672 void __iomem *ioaddr = tp->mmio_addr;
3673 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3674
bcf0bf90 3675 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3676
4da19633 3677 if (tp->phy_reset_pending(tp)) {
5b0384f4 3678 /*
1da177e4
LT		 3679 * A busy loop could burn quite a few cycles on nowadays CPU.
3680 * Let's delay the execution of the timer for a few ticks.
3681 */
3682 timeout = HZ/10;
3683 goto out_mod_timer;
3684 }
3685
3686 if (tp->link_ok(ioaddr))
da78dbff 3687 return;
1da177e4 3688
9bb8eeb5 3689 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3690
4da19633 3691 tp->phy_reset_enable(tp);
1da177e4
LT		 3692
3693out_mod_timer:
3694 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3695}
3696
3697static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3698{
da78dbff
FR		 3699 if (!test_and_set_bit(flag, tp->wk.flags))
3700 schedule_work(&tp->wk.work);
da78dbff
FR		 3701}
3702
3703static void rtl8169_phy_timer(unsigned long __opaque)
3704{
3705 struct net_device *dev = (struct net_device *)__opaque;
3706 struct rtl8169_private *tp = netdev_priv(dev);
3707
98ddf986 3708 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3709}
3710
1da177e4
LT		 3711static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3712 void __iomem *ioaddr)
3713{
3714 iounmap(ioaddr);
3715 pci_release_regions(pdev);
87aeec76 3716 pci_clear_mwi(pdev);
1da177e4
LT		 3717 pci_disable_device(pdev);
3718 free_netdev(dev);
3719}
3720
ffc46952
FR		 3721DECLARE_RTL_COND(rtl_phy_reset_cond)
3722{
3723 return tp->phy_reset_pending(tp);
3724}
3725
bf793295
FR		 3726static void rtl8169_phy_reset(struct net_device *dev,
3727 struct rtl8169_private *tp)
3728{
4da19633 3729 tp->phy_reset_enable(tp);
ffc46952 3730 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 3731}
3732
2544bfc0
FR		 3733static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3734{
3735 void __iomem *ioaddr = tp->mmio_addr;
3736
3737 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3738 (RTL_R8(PHYstatus) & TBI_Enable);
3739}
3740
4ff96fa6
FR		 3741static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3742{
3743 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3744
5615d9f1 3745 rtl_hw_phy_config(dev);
4ff96fa6 3746
77332894
MS		 3747 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3748 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3749 RTL_W8(0x82, 0x01);
3750 }
4ff96fa6 3751
6dccd16b
FR		 3752 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3753
3754 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3755 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3756
bcf0bf90 3757 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3758 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3759 RTL_W8(0x82, 0x01);
3760 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3761 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3762 }
3763
bf793295
FR		 3764 rtl8169_phy_reset(dev, tp);
3765
54405cde 3766 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3767 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3768 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3769 (tp->mii.supports_gmii ?
3770 ADVERTISED_1000baseT_Half |
3771 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3772
2544bfc0 3773 if (rtl_tbi_enabled(tp))
bf82c189 3774 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3775}
3776
773d2021
FR		 3777static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3778{
3779 void __iomem *ioaddr = tp->mmio_addr;
773d2021 3780
da78dbff 3781 rtl_lock_work(tp);
773d2021
FR		 3782
3783 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3784
9ecb9aab 3785 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 3786 RTL_R32(MAC4);
3787
9ecb9aab 3788 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 3789 RTL_R32(MAC0);
3790
9ecb9aab 3791 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3792 rtl_rar_exgmac_set(tp, addr);
c28aa385 3793
773d2021
FR		 3794 RTL_W8(Cfg9346, Cfg9346_Lock);
3795
da78dbff 3796 rtl_unlock_work(tp);
773d2021
FR		 3797}
3798
3799static int rtl_set_mac_address(struct net_device *dev, void *p)
3800{
3801 struct rtl8169_private *tp = netdev_priv(dev);
3802 struct sockaddr *addr = p;
3803
3804 if (!is_valid_ether_addr(addr->sa_data))
3805 return -EADDRNOTAVAIL;
3806
3807 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3808
3809 rtl_rar_set(tp, dev->dev_addr);
3810
3811 return 0;
3812}
3813
5f787a1a
FR		 3814static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3815{
3816 struct rtl8169_private *tp = netdev_priv(dev);
3817 struct mii_ioctl_data *data = if_mii(ifr);
3818
8b4ab28d
FR		 3819 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3820}
5f787a1a 3821
cecb5fd7
FR		 3822static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3823 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3824{
5f787a1a
FR		 3825 switch (cmd) {
3826 case SIOCGMIIPHY:
3827 data->phy_id = 32; /* Internal PHY */
3828 return 0;
3829
3830 case SIOCGMIIREG:
4da19633 3831 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3832 return 0;
3833
3834 case SIOCSMIIREG:
4da19633 3835 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3836 return 0;
3837 }
3838 return -EOPNOTSUPP;
3839}
3840
8b4ab28d
FR		 3841static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3842{
3843 return -EOPNOTSUPP;
3844}
3845
fbac58fc
FR		 3846static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3847{
3848 if (tp->features & RTL_FEATURE_MSI) {
3849 pci_disable_msi(pdev);
3850 tp->features &= ~RTL_FEATURE_MSI;
3851 }
3852}
3853
baf63293 3854static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 3855{
3856 struct mdio_ops *ops = &tp->mdio_ops;
3857
3858 switch (tp->mac_version) {
3859 case RTL_GIGA_MAC_VER_27:
3860 ops->write = r8168dp_1_mdio_write;
3861 ops->read = r8168dp_1_mdio_read;
3862 break;
e6de30d6 3863 case RTL_GIGA_MAC_VER_28:
4804b3b3 3864 case RTL_GIGA_MAC_VER_31:
e6de30d6 3865 ops->write = r8168dp_2_mdio_write;
3866 ops->read = r8168dp_2_mdio_read;
3867 break;
c558386b
HW		 3868 case RTL_GIGA_MAC_VER_40:
3869 case RTL_GIGA_MAC_VER_41:
57538c4a 3870 case RTL_GIGA_MAC_VER_42:
58152cd4 3871 case RTL_GIGA_MAC_VER_43:
45dd95c4 3872 case RTL_GIGA_MAC_VER_44:
c558386b
HW		 3873 ops->write = r8168g_mdio_write;
3874 ops->read = r8168g_mdio_read;
3875 break;
c0e45c1c 3876 default:
3877 ops->write = r8169_mdio_write;
3878 ops->read = r8169_mdio_read;
3879 break;
3880 }
3881}
3882
e2409d83 3883static void rtl_speed_down(struct rtl8169_private *tp)
3884{
3885 u32 adv;
3886 int lpa;
3887
3888 rtl_writephy(tp, 0x1f, 0x0000);
3889 lpa = rtl_readphy(tp, MII_LPA);
3890
3891 if (lpa & (LPA_10HALF | LPA_10FULL))
3892 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
3893 else if (lpa & (LPA_100HALF | LPA_100FULL))
3894 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3895 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3896 else
3897 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3898 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3899 (tp->mii.supports_gmii ?
3900 ADVERTISED_1000baseT_Half |
3901 ADVERTISED_1000baseT_Full : 0);
3902
3903 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3904 adv);
3905}
3906
649b3b8c 3907static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3908{
3909 void __iomem *ioaddr = tp->mmio_addr;
3910
3911 switch (tp->mac_version) {
b00e69de
CB		 3912 case RTL_GIGA_MAC_VER_25:
3913 case RTL_GIGA_MAC_VER_26:
649b3b8c 3914 case RTL_GIGA_MAC_VER_29:
3915 case RTL_GIGA_MAC_VER_30:
3916 case RTL_GIGA_MAC_VER_32:
3917 case RTL_GIGA_MAC_VER_33:
3918 case RTL_GIGA_MAC_VER_34:
7e18dca1 3919 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 3920 case RTL_GIGA_MAC_VER_38:
5598bfe5 3921 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 3922 case RTL_GIGA_MAC_VER_40:
3923 case RTL_GIGA_MAC_VER_41:
57538c4a 3924 case RTL_GIGA_MAC_VER_42:
58152cd4 3925 case RTL_GIGA_MAC_VER_43:
45dd95c4 3926 case RTL_GIGA_MAC_VER_44:
649b3b8c 3927 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3928 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3929 break;
3930 default:
3931 break;
3932 }
3933}
3934
3935static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3936{
3937 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3938 return false;
3939
e2409d83 3940 rtl_speed_down(tp);
649b3b8c 3941 rtl_wol_suspend_quirk(tp);
3942
3943 return true;
3944}
3945
065c27c1 3946static void r810x_phy_power_down(struct rtl8169_private *tp)
3947{
3948 rtl_writephy(tp, 0x1f, 0x0000);
3949 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3950}
3951
3952static void r810x_phy_power_up(struct rtl8169_private *tp)
3953{
3954 rtl_writephy(tp, 0x1f, 0x0000);
3955 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3956}
3957
3958static void r810x_pll_power_down(struct rtl8169_private *tp)
3959{
0004299a
HW		 3960 void __iomem *ioaddr = tp->mmio_addr;
3961
649b3b8c 3962 if (rtl_wol_pll_power_down(tp))
065c27c1 3963 return;
065c27c1 3964
3965 r810x_phy_power_down(tp);
0004299a
HW		 3966
3967 switch (tp->mac_version) {
3968 case RTL_GIGA_MAC_VER_07:
3969 case RTL_GIGA_MAC_VER_08:
3970 case RTL_GIGA_MAC_VER_09:
3971 case RTL_GIGA_MAC_VER_10:
3972 case RTL_GIGA_MAC_VER_13:
3973 case RTL_GIGA_MAC_VER_16:
3974 break;
3975 default:
3976 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3977 break;
3978 }
065c27c1 3979}
3980
3981static void r810x_pll_power_up(struct rtl8169_private *tp)
3982{
0004299a
HW		 3983 void __iomem *ioaddr = tp->mmio_addr;
3984
065c27c1 3985 r810x_phy_power_up(tp);
0004299a
HW		 3986
3987 switch (tp->mac_version) {
3988 case RTL_GIGA_MAC_VER_07:
3989 case RTL_GIGA_MAC_VER_08:
3990 case RTL_GIGA_MAC_VER_09:
3991 case RTL_GIGA_MAC_VER_10:
3992 case RTL_GIGA_MAC_VER_13:
3993 case RTL_GIGA_MAC_VER_16:
3994 break;
3995 default:
3996 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3997 break;
3998 }
065c27c1 3999}
4000
4001static void r8168_phy_power_up(struct rtl8169_private *tp)
4002{
4003 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4004 switch (tp->mac_version) {
4005 case RTL_GIGA_MAC_VER_11:
4006 case RTL_GIGA_MAC_VER_12:
4007 case RTL_GIGA_MAC_VER_17:
4008 case RTL_GIGA_MAC_VER_18:
4009 case RTL_GIGA_MAC_VER_19:
4010 case RTL_GIGA_MAC_VER_20:
4011 case RTL_GIGA_MAC_VER_21:
4012 case RTL_GIGA_MAC_VER_22:
4013 case RTL_GIGA_MAC_VER_23:
4014 case RTL_GIGA_MAC_VER_24:
4015 case RTL_GIGA_MAC_VER_25:
4016 case RTL_GIGA_MAC_VER_26:
4017 case RTL_GIGA_MAC_VER_27:
4018 case RTL_GIGA_MAC_VER_28:
4019 case RTL_GIGA_MAC_VER_31:
4020 rtl_writephy(tp, 0x0e, 0x0000);
4021 break;
4022 default:
4023 break;
4024 }
065c27c1 4025 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4026}
4027
4028static void r8168_phy_power_down(struct rtl8169_private *tp)
4029{
4030 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4031 switch (tp->mac_version) {
4032 case RTL_GIGA_MAC_VER_32:
4033 case RTL_GIGA_MAC_VER_33:
beb330a4 4034 case RTL_GIGA_MAC_VER_40:
4035 case RTL_GIGA_MAC_VER_41:
01dc7fec 4036 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4037 break;
4038
4039 case RTL_GIGA_MAC_VER_11:
4040 case RTL_GIGA_MAC_VER_12:
4041 case RTL_GIGA_MAC_VER_17:
4042 case RTL_GIGA_MAC_VER_18:
4043 case RTL_GIGA_MAC_VER_19:
4044 case RTL_GIGA_MAC_VER_20:
4045 case RTL_GIGA_MAC_VER_21:
4046 case RTL_GIGA_MAC_VER_22:
4047 case RTL_GIGA_MAC_VER_23:
4048 case RTL_GIGA_MAC_VER_24:
4049 case RTL_GIGA_MAC_VER_25:
4050 case RTL_GIGA_MAC_VER_26:
4051 case RTL_GIGA_MAC_VER_27:
4052 case RTL_GIGA_MAC_VER_28:
4053 case RTL_GIGA_MAC_VER_31:
4054 rtl_writephy(tp, 0x0e, 0x0200);
4055 default:
4056 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4057 break;
4058 }
065c27c1 4059}
4060
4061static void r8168_pll_power_down(struct rtl8169_private *tp)
4062{
4063 void __iomem *ioaddr = tp->mmio_addr;
4064
cecb5fd7
FR		 4065 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4066 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4067 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 4068 r8168dp_check_dash(tp)) {
065c27c1 4069 return;
5d2e1957 4070 }
065c27c1 4071
cecb5fd7
FR		 4072 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4073 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4074 (RTL_R16(CPlusCmd) & ASF)) {
4075 return;
4076 }
4077
01dc7fec 4078 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4079 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4080 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4081
649b3b8c 4082 if (rtl_wol_pll_power_down(tp))
065c27c1 4083 return;
065c27c1 4084
4085 r8168_phy_power_down(tp);
4086
4087 switch (tp->mac_version) {
4088 case RTL_GIGA_MAC_VER_25:
4089 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4090 case RTL_GIGA_MAC_VER_27:
4091 case RTL_GIGA_MAC_VER_28:
4804b3b3 4092 case RTL_GIGA_MAC_VER_31:
01dc7fec 4093 case RTL_GIGA_MAC_VER_32:
4094 case RTL_GIGA_MAC_VER_33:
065c27c1 4095 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4096 break;
beb330a4 4097 case RTL_GIGA_MAC_VER_40:
4098 case RTL_GIGA_MAC_VER_41:
4099 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4100 0xfc000000, ERIAR_EXGMAC);
4101 break;
065c27c1 4102 }
4103}
4104
4105static void r8168_pll_power_up(struct rtl8169_private *tp)
4106{
4107 void __iomem *ioaddr = tp->mmio_addr;
4108
065c27c1 4109 switch (tp->mac_version) {
4110 case RTL_GIGA_MAC_VER_25:
4111 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4112 case RTL_GIGA_MAC_VER_27:
4113 case RTL_GIGA_MAC_VER_28:
4804b3b3 4114 case RTL_GIGA_MAC_VER_31:
01dc7fec 4115 case RTL_GIGA_MAC_VER_32:
4116 case RTL_GIGA_MAC_VER_33:
065c27c1 4117 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4118 break;
beb330a4 4119 case RTL_GIGA_MAC_VER_40:
4120 case RTL_GIGA_MAC_VER_41:
4121 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4122 0x00000000, ERIAR_EXGMAC);
4123 break;
065c27c1 4124 }
4125
4126 r8168_phy_power_up(tp);
4127}
4128
d58d46b5
FR		 4129static void rtl_generic_op(struct rtl8169_private *tp,
4130 void (*op)(struct rtl8169_private *))
065c27c1 4131{
4132 if (op)
4133 op(tp);
4134}
4135
4136static void rtl_pll_power_down(struct rtl8169_private *tp)
4137{
d58d46b5 4138 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4139}
4140
4141static void rtl_pll_power_up(struct rtl8169_private *tp)
4142{
d58d46b5 4143 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4144}
4145
baf63293 4146static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4147{
4148 struct pll_power_ops *ops = &tp->pll_power_ops;
4149
4150 switch (tp->mac_version) {
4151 case RTL_GIGA_MAC_VER_07:
4152 case RTL_GIGA_MAC_VER_08:
4153 case RTL_GIGA_MAC_VER_09:
4154 case RTL_GIGA_MAC_VER_10:
4155 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4156 case RTL_GIGA_MAC_VER_29:
4157 case RTL_GIGA_MAC_VER_30:
7e18dca1 4158 case RTL_GIGA_MAC_VER_37:
5598bfe5 4159 case RTL_GIGA_MAC_VER_39:
58152cd4 4160 case RTL_GIGA_MAC_VER_43:
065c27c1 4161 ops->down = r810x_pll_power_down;
4162 ops->up = r810x_pll_power_up;
4163 break;
4164
4165 case RTL_GIGA_MAC_VER_11:
4166 case RTL_GIGA_MAC_VER_12:
4167 case RTL_GIGA_MAC_VER_17:
4168 case RTL_GIGA_MAC_VER_18:
4169 case RTL_GIGA_MAC_VER_19:
4170 case RTL_GIGA_MAC_VER_20:
4171 case RTL_GIGA_MAC_VER_21:
4172 case RTL_GIGA_MAC_VER_22:
4173 case RTL_GIGA_MAC_VER_23:
4174 case RTL_GIGA_MAC_VER_24:
4175 case RTL_GIGA_MAC_VER_25:
4176 case RTL_GIGA_MAC_VER_26:
4177 case RTL_GIGA_MAC_VER_27:
e6de30d6 4178 case RTL_GIGA_MAC_VER_28:
4804b3b3 4179 case RTL_GIGA_MAC_VER_31:
01dc7fec 4180 case RTL_GIGA_MAC_VER_32:
4181 case RTL_GIGA_MAC_VER_33:
70090424 4182 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4183 case RTL_GIGA_MAC_VER_35:
4184 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4185 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4186 case RTL_GIGA_MAC_VER_40:
4187 case RTL_GIGA_MAC_VER_41:
57538c4a 4188 case RTL_GIGA_MAC_VER_42:
45dd95c4 4189 case RTL_GIGA_MAC_VER_44:
065c27c1 4190 ops->down = r8168_pll_power_down;
4191 ops->up = r8168_pll_power_up;
4192 break;
4193
4194 default:
4195 ops->down = NULL;
4196 ops->up = NULL;
4197 break;
4198 }
4199}
4200
e542a226
HW		 4201static void rtl_init_rxcfg(struct rtl8169_private *tp)
4202{
4203 void __iomem *ioaddr = tp->mmio_addr;
4204
4205 switch (tp->mac_version) {
4206 case RTL_GIGA_MAC_VER_01:
4207 case RTL_GIGA_MAC_VER_02:
4208 case RTL_GIGA_MAC_VER_03:
4209 case RTL_GIGA_MAC_VER_04:
4210 case RTL_GIGA_MAC_VER_05:
4211 case RTL_GIGA_MAC_VER_06:
4212 case RTL_GIGA_MAC_VER_10:
4213 case RTL_GIGA_MAC_VER_11:
4214 case RTL_GIGA_MAC_VER_12:
4215 case RTL_GIGA_MAC_VER_13:
4216 case RTL_GIGA_MAC_VER_14:
4217 case RTL_GIGA_MAC_VER_15:
4218 case RTL_GIGA_MAC_VER_16:
4219 case RTL_GIGA_MAC_VER_17:
4220 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4221 break;
4222 case RTL_GIGA_MAC_VER_18:
4223 case RTL_GIGA_MAC_VER_19:
4224 case RTL_GIGA_MAC_VER_20:
4225 case RTL_GIGA_MAC_VER_21:
4226 case RTL_GIGA_MAC_VER_22:
4227 case RTL_GIGA_MAC_VER_23:
4228 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4229 case RTL_GIGA_MAC_VER_34:
e542a226
HW		 4230 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4231 break;
beb330a4 4232 case RTL_GIGA_MAC_VER_40:
4233 case RTL_GIGA_MAC_VER_41:
57538c4a 4234 case RTL_GIGA_MAC_VER_42:
58152cd4 4235 case RTL_GIGA_MAC_VER_43:
45dd95c4 4236 case RTL_GIGA_MAC_VER_44:
beb330a4 4237 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4238 break;
e542a226
HW		 4239 default:
4240 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4241 break;
4242 }
4243}
4244
92fc43b4
HW		 4245static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4246{
9fba0812 4247 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4248}
4249
d58d46b5
FR		 4250static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4251{
9c5028e9 4252 void __iomem *ioaddr = tp->mmio_addr;
4253
4254 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4255 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4256 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4257}
4258
4259static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4260{
9c5028e9 4261 void __iomem *ioaddr = tp->mmio_addr;
4262
4263 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4264 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4265 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4266}
4267
4268static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4269{
4270 void __iomem *ioaddr = tp->mmio_addr;
4271
4272 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4273 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4274 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4275}
4276
4277static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4278{
4279 void __iomem *ioaddr = tp->mmio_addr;
4280
4281 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4282 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4283 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4284}
4285
4286static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4287{
4288 void __iomem *ioaddr = tp->mmio_addr;
4289
4290 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4291}
4292
4293static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4294{
4295 void __iomem *ioaddr = tp->mmio_addr;
4296
4297 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4298}
4299
4300static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4301{
4302 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4303
4304 RTL_W8(MaxTxPacketSize, 0x3f);
4305 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4306 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4307 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4308}
4309
4310static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4311{
4312 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4313
4314 RTL_W8(MaxTxPacketSize, 0x0c);
4315 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4316 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4317 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4318}
4319
4320static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4321{
4322 rtl_tx_performance_tweak(tp->pci_dev,
4323 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4324}
4325
4326static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4327{
4328 rtl_tx_performance_tweak(tp->pci_dev,
4329 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4330}
4331
4332static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4333{
4334 void __iomem *ioaddr = tp->mmio_addr;
4335
4336 r8168b_0_hw_jumbo_enable(tp);
4337
4338 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4339}
4340
4341static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4342{
4343 void __iomem *ioaddr = tp->mmio_addr;
4344
4345 r8168b_0_hw_jumbo_disable(tp);
4346
4347 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4348}
4349
baf63293 4350static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4351{
4352 struct jumbo_ops *ops = &tp->jumbo_ops;
4353
4354 switch (tp->mac_version) {
4355 case RTL_GIGA_MAC_VER_11:
4356 ops->disable = r8168b_0_hw_jumbo_disable;
4357 ops->enable = r8168b_0_hw_jumbo_enable;
4358 break;
4359 case RTL_GIGA_MAC_VER_12:
4360 case RTL_GIGA_MAC_VER_17:
4361 ops->disable = r8168b_1_hw_jumbo_disable;
4362 ops->enable = r8168b_1_hw_jumbo_enable;
4363 break;
4364 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4365 case RTL_GIGA_MAC_VER_19:
4366 case RTL_GIGA_MAC_VER_20:
4367 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4368 case RTL_GIGA_MAC_VER_22:
4369 case RTL_GIGA_MAC_VER_23:
4370 case RTL_GIGA_MAC_VER_24:
4371 case RTL_GIGA_MAC_VER_25:
4372 case RTL_GIGA_MAC_VER_26:
4373 ops->disable = r8168c_hw_jumbo_disable;
4374 ops->enable = r8168c_hw_jumbo_enable;
4375 break;
4376 case RTL_GIGA_MAC_VER_27:
4377 case RTL_GIGA_MAC_VER_28:
4378 ops->disable = r8168dp_hw_jumbo_disable;
4379 ops->enable = r8168dp_hw_jumbo_enable;
4380 break;
4381 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4382 case RTL_GIGA_MAC_VER_32:
4383 case RTL_GIGA_MAC_VER_33:
4384 case RTL_GIGA_MAC_VER_34:
4385 ops->disable = r8168e_hw_jumbo_disable;
4386 ops->enable = r8168e_hw_jumbo_enable;
4387 break;
4388
4389 /*
4390 * No action needed for jumbo frames with 8169.
4391 * No jumbo for 810x at all.
4392 */
c558386b
HW		 4393 case RTL_GIGA_MAC_VER_40:
4394 case RTL_GIGA_MAC_VER_41:
57538c4a 4395 case RTL_GIGA_MAC_VER_42:
58152cd4 4396 case RTL_GIGA_MAC_VER_43:
45dd95c4 4397 case RTL_GIGA_MAC_VER_44:
d58d46b5
FR		 4398 default:
4399 ops->disable = NULL;
4400 ops->enable = NULL;
4401 break;
4402 }
4403}
4404
ffc46952
FR		 4405DECLARE_RTL_COND(rtl_chipcmd_cond)
4406{
4407 void __iomem *ioaddr = tp->mmio_addr;
4408
4409 return RTL_R8(ChipCmd) & CmdReset;
4410}
4411
6f43adc8
FR		 4412static void rtl_hw_reset(struct rtl8169_private *tp)
4413{
4414 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 4415
6f43adc8
FR		 4416 RTL_W8(ChipCmd, CmdReset);
4417
ffc46952 4418 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4419}
4420
b6ffd97f 4421static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4422{
b6ffd97f
FR		 4423 struct rtl_fw *rtl_fw;
4424 const char *name;
4425 int rc = -ENOMEM;
953a12cc 4426
b6ffd97f
FR		 4427 name = rtl_lookup_firmware_name(tp);
4428 if (!name)
4429 goto out_no_firmware;
953a12cc 4430
b6ffd97f
FR		 4431 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4432 if (!rtl_fw)
4433 goto err_warn;
31bd204f 4434
b6ffd97f
FR		 4435 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4436 if (rc < 0)
4437 goto err_free;
4438
fd112f2e
FR		 4439 rc = rtl_check_firmware(tp, rtl_fw);
4440 if (rc < 0)
4441 goto err_release_firmware;
4442
b6ffd97f
FR		 4443 tp->rtl_fw = rtl_fw;
4444out:
4445 return;
4446
fd112f2e
FR		 4447err_release_firmware:
4448 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4449err_free:
4450 kfree(rtl_fw);
4451err_warn:
4452 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4453 name, rc);
4454out_no_firmware:
4455 tp->rtl_fw = NULL;
4456 goto out;
4457}
4458
4459static void rtl_request_firmware(struct rtl8169_private *tp)
4460{
4461 if (IS_ERR(tp->rtl_fw))
4462 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4463}
4464
92fc43b4
HW		 4465static void rtl_rx_close(struct rtl8169_private *tp)
4466{
4467 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4468
1687b566 4469 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4470}
4471
ffc46952
FR		 4472DECLARE_RTL_COND(rtl_npq_cond)
4473{
4474 void __iomem *ioaddr = tp->mmio_addr;
4475
4476 return RTL_R8(TxPoll) & NPQ;
4477}
4478
4479DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4480{
4481 void __iomem *ioaddr = tp->mmio_addr;
4482
4483 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4484}
4485
e6de30d6 4486static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4487{
e6de30d6 4488 void __iomem *ioaddr = tp->mmio_addr;
4489
1da177e4 4490 /* Disable interrupts */
811fd301 4491 rtl8169_irq_mask_and_ack(tp);
1da177e4 4492
92fc43b4
HW		 4493 rtl_rx_close(tp);
4494
5d2e1957 4495 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4496 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4497 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 4498 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925
HW		 4499 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4500 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
7e18dca1 4501 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
b3d7b2f2 4502 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
c558386b
HW		 4503 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4504 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
57538c4a 4505 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
58152cd4 4506 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
45dd95c4 4507 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
b3d7b2f2 4508 tp->mac_version == RTL_GIGA_MAC_VER_38) {
c2b0c1e7 4509 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 4510 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 4511 } else {
4512 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4513 udelay(100);
e6de30d6 4514 }
4515
92fc43b4 4516 rtl_hw_reset(tp);
1da177e4
LT		 4517}
4518
7f796d83 4519static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4520{
4521 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4522
4523 /* Set DMA burst size and Interframe Gap Time */
4524 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4525 (InterFrameGap << TxInterFrameGapShift));
4526}
4527
07ce4064 4528static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4529{
4530 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4531
07ce4064
FR		 4532 tp->hw_start(dev);
4533
da78dbff 4534 rtl_irq_enable_all(tp);
07ce4064
FR		 4535}
4536
7f796d83
FR		 4537static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4538 void __iomem *ioaddr)
4539{
4540 /*
4541 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4542 * register to be written before TxDescAddrLow to work.
4543 * Switching from MMIO to I/O access fixes the issue as well.
4544 */
4545 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4546 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4547 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4548 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4549}
4550
4551static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4552{
4553 u16 cmd;
4554
4555 cmd = RTL_R16(CPlusCmd);
4556 RTL_W16(CPlusCmd, cmd);
4557 return cmd;
4558}
4559
fdd7b4c3 4560static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4561{
4562 /* Low hurts. Let's disable the filtering. */
207d6e87 4563 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4564}
4565
6dccd16b
FR		 4566static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4567{
3744100e 4568 static const struct rtl_cfg2_info {
6dccd16b
FR		 4569 u32 mac_version;
4570 u32 clk;
4571 u32 val;
4572 } cfg2_info [] = {
4573 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4574 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4575 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4576 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4577 };
4578 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4579 unsigned int i;
4580 u32 clk;
4581
4582 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4583 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4584 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4585 RTL_W32(0x7c, p->val);
4586 break;
4587 }
4588 }
4589}
4590
e6b763ea
FR		 4591static void rtl_set_rx_mode(struct net_device *dev)
4592{
4593 struct rtl8169_private *tp = netdev_priv(dev);
4594 void __iomem *ioaddr = tp->mmio_addr;
4595 u32 mc_filter[2]; /* Multicast hash filter */
4596 int rx_mode;
4597 u32 tmp = 0;
4598
4599 if (dev->flags & IFF_PROMISC) {
4600 /* Unconditionally log net taps. */
4601 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4602 rx_mode =
4603 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4604 AcceptAllPhys;
4605 mc_filter[1] = mc_filter[0] = 0xffffffff;
4606 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4607 (dev->flags & IFF_ALLMULTI)) {
4608 /* Too many to filter perfectly -- accept all multicasts. */
4609 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4610 mc_filter[1] = mc_filter[0] = 0xffffffff;
4611 } else {
4612 struct netdev_hw_addr *ha;
4613
4614 rx_mode = AcceptBroadcast | AcceptMyPhys;
4615 mc_filter[1] = mc_filter[0] = 0;
4616 netdev_for_each_mc_addr(ha, dev) {
4617 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4618 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4619 rx_mode |= AcceptMulticast;
4620 }
4621 }
4622
4623 if (dev->features & NETIF_F_RXALL)
4624 rx_mode |= (AcceptErr | AcceptRunt);
4625
4626 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4627
4628 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4629 u32 data = mc_filter[0];
4630
4631 mc_filter[0] = swab32(mc_filter[1]);
4632 mc_filter[1] = swab32(data);
4633 }
4634
0481776b
NW		 4635 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4636 mc_filter[1] = mc_filter[0] = 0xffffffff;
4637
e6b763ea
FR		 4638 RTL_W32(MAR0 + 4, mc_filter[1]);
4639 RTL_W32(MAR0 + 0, mc_filter[0]);
4640
4641 RTL_W32(RxConfig, tmp);
4642}
4643
07ce4064
FR		 4644static void rtl_hw_start_8169(struct net_device *dev)
4645{
4646 struct rtl8169_private *tp = netdev_priv(dev);
4647 void __iomem *ioaddr = tp->mmio_addr;
4648 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4649
9cb427b6
FR		 4650 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4651 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4652 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4653 }
4654
1da177e4 4655 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4656 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4657 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4658 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4659 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4660 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4661
e542a226
HW		 4662 rtl_init_rxcfg(tp);
4663
f0298f81 4664 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4665
6f0333b8 4666 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4667
cecb5fd7
FR		 4668 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4669 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4670 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4671 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4672 rtl_set_rx_tx_config_registers(tp);
1da177e4 4673
7f796d83 4674 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4675
cecb5fd7
FR		 4676 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4677 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4678 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4679 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4680 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4681 }
4682
bcf0bf90
FR		 4683 RTL_W16(CPlusCmd, tp->cp_cmd);
4684
6dccd16b
FR		 4685 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4686
1da177e4
LT		 4687 /*
4688 * Undocumented corner. Supposedly:
4689 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4690 */
4691 RTL_W16(IntrMitigate, 0x0000);
4692
7f796d83 4693 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4694
cecb5fd7
FR		 4695 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4696 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4697 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4698 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4699 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4700 rtl_set_rx_tx_config_registers(tp);
4701 }
4702
1da177e4 4703 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4704
4705 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4706 RTL_R8(IntrMask);
1da177e4
LT		 4707
4708 RTL_W32(RxMissed, 0);
4709
07ce4064 4710 rtl_set_rx_mode(dev);
1da177e4
LT		 4711
4712 /* no early-rx interrupts */
4713 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4714}
1da177e4 4715
beb1fe18
HW		 4716static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4717{
4718 if (tp->csi_ops.write)
52989f0e 4719 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 4720}
4721
4722static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4723{
52989f0e 4724 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 4725}
4726
4727static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 4728{
4729 u32 csi;
4730
beb1fe18
HW		 4731 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4732 rtl_csi_write(tp, 0x070c, csi | bits);
4733}
4734
4735static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4736{
4737 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 4738}
4739
beb1fe18 4740static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 4741{
beb1fe18 4742 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 4743}
4744
ffc46952
FR		 4745DECLARE_RTL_COND(rtl_csiar_cond)
4746{
4747 void __iomem *ioaddr = tp->mmio_addr;
4748
4749 return RTL_R32(CSIAR) & CSIAR_FLAG;
4750}
4751
52989f0e 4752static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 4753{
52989f0e 4754 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4755
4756 RTL_W32(CSIDR, value);
4757 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4758 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4759
ffc46952 4760 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 4761}
4762
52989f0e 4763static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 4764{
52989f0e 4765 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4766
4767 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4768 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4769
ffc46952
FR		 4770 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4771 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 4772}
4773
52989f0e 4774static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 4775{
52989f0e 4776 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4777
4778 RTL_W32(CSIDR, value);
4779 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4780 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4781 CSIAR_FUNC_NIC);
4782
ffc46952 4783 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4784}
4785
52989f0e 4786static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4787{
52989f0e 4788 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4789
4790 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4791 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4792
ffc46952
FR		 4793 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4794 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 4795}
4796
45dd95c4 4797static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
4798{
4799 void __iomem *ioaddr = tp->mmio_addr;
4800
4801 RTL_W32(CSIDR, value);
4802 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4803 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4804 CSIAR_FUNC_NIC2);
4805
4806 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4807}
4808
4809static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
4810{
4811 void __iomem *ioaddr = tp->mmio_addr;
4812
4813 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
4814 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4815
4816 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4817 RTL_R32(CSIDR) : ~0;
4818}
4819
baf63293 4820static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 4821{
4822 struct csi_ops *ops = &tp->csi_ops;
4823
4824 switch (tp->mac_version) {
4825 case RTL_GIGA_MAC_VER_01:
4826 case RTL_GIGA_MAC_VER_02:
4827 case RTL_GIGA_MAC_VER_03:
4828 case RTL_GIGA_MAC_VER_04:
4829 case RTL_GIGA_MAC_VER_05:
4830 case RTL_GIGA_MAC_VER_06:
4831 case RTL_GIGA_MAC_VER_10:
4832 case RTL_GIGA_MAC_VER_11:
4833 case RTL_GIGA_MAC_VER_12:
4834 case RTL_GIGA_MAC_VER_13:
4835 case RTL_GIGA_MAC_VER_14:
4836 case RTL_GIGA_MAC_VER_15:
4837 case RTL_GIGA_MAC_VER_16:
4838 case RTL_GIGA_MAC_VER_17:
4839 ops->write = NULL;
4840 ops->read = NULL;
4841 break;
4842
7e18dca1 4843 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4844 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 4845 ops->write = r8402_csi_write;
4846 ops->read = r8402_csi_read;
4847 break;
4848
45dd95c4 4849 case RTL_GIGA_MAC_VER_44:
4850 ops->write = r8411_csi_write;
4851 ops->read = r8411_csi_read;
4852 break;
4853
beb1fe18
HW		 4854 default:
4855 ops->write = r8169_csi_write;
4856 ops->read = r8169_csi_read;
4857 break;
4858 }
dacf8154
FR		 4859}
4860
4861struct ephy_info {
4862 unsigned int offset;
4863 u16 mask;
4864 u16 bits;
4865};
4866
fdf6fc06
FR		 4867static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4868 int len)
dacf8154
FR		 4869{
4870 u16 w;
4871
4872 while (len-- > 0) {
fdf6fc06
FR		 4873 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4874 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4875 e++;
4876 }
4877}
4878
b726e493
FR		 4879static void rtl_disable_clock_request(struct pci_dev *pdev)
4880{
7d7903b2
JL		 4881 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4882 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4883}
4884
e6de30d6 4885static void rtl_enable_clock_request(struct pci_dev *pdev)
4886{
7d7903b2
JL		 4887 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4888 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4889}
4890
b726e493
FR		 4891#define R8168_CPCMD_QUIRK_MASK (\
4892 EnableBist | \
4893 Mac_dbgo_oe | \
4894 Force_half_dup | \
4895 Force_rxflow_en | \
4896 Force_txflow_en | \
4897 Cxpl_dbg_sel | \
4898 ASF | \
4899 PktCntrDisable | \
4900 Mac_dbgo_sel)
4901
beb1fe18 4902static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4903{
beb1fe18
HW		 4904 void __iomem *ioaddr = tp->mmio_addr;
4905 struct pci_dev *pdev = tp->pci_dev;
4906
b726e493
FR		 4907 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4908
4909 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4910
faf1e785 4911 if (tp->dev->mtu <= ETH_DATA_LEN) {
4912 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4913 PCI_EXP_DEVCTL_NOSNOOP_EN);
4914 }
219a1e9d
FR		 4915}
4916
beb1fe18 4917static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4918{
beb1fe18
HW		 4919 void __iomem *ioaddr = tp->mmio_addr;
4920
4921 rtl_hw_start_8168bb(tp);
b726e493 4922
f0298f81 4923 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4924
4925 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4926}
4927
beb1fe18 4928static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4929{
beb1fe18
HW		 4930 void __iomem *ioaddr = tp->mmio_addr;
4931 struct pci_dev *pdev = tp->pci_dev;
4932
b726e493
FR		 4933 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4934
4935 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4936
faf1e785 4937 if (tp->dev->mtu <= ETH_DATA_LEN)
4938 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4939
4940 rtl_disable_clock_request(pdev);
4941
4942 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4943}
4944
beb1fe18 4945static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4946{
350f7596 4947 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4948 { 0x01, 0, 0x0001 },
4949 { 0x02, 0x0800, 0x1000 },
4950 { 0x03, 0, 0x0042 },
4951 { 0x06, 0x0080, 0x0000 },
4952 { 0x07, 0, 0x2000 }
4953 };
4954
beb1fe18 4955 rtl_csi_access_enable_2(tp);
b726e493 4956
fdf6fc06 4957 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4958
beb1fe18 4959 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4960}
4961
beb1fe18 4962static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4963{
beb1fe18
HW		 4964 void __iomem *ioaddr = tp->mmio_addr;
4965 struct pci_dev *pdev = tp->pci_dev;
4966
4967 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 4968
4969 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4970
faf1e785 4971 if (tp->dev->mtu <= ETH_DATA_LEN)
4972 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
ef3386f0
FR		 4973
4974 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4975}
4976
beb1fe18 4977static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4978{
beb1fe18
HW		 4979 void __iomem *ioaddr = tp->mmio_addr;
4980 struct pci_dev *pdev = tp->pci_dev;
4981
4982 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 4983
4984 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4985
4986 /* Magic. */
4987 RTL_W8(DBG_REG, 0x20);
4988
f0298f81 4989 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a 4990
faf1e785 4991 if (tp->dev->mtu <= ETH_DATA_LEN)
4992 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
7f3e3d3a
FR		 4993
4994 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4995}
4996
beb1fe18 4997static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4998{
beb1fe18 4999 void __iomem *ioaddr = tp->mmio_addr;
350f7596 5000 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 5001 { 0x02, 0x0800, 0x1000 },
5002 { 0x03, 0, 0x0002 },
5003 { 0x06, 0x0080, 0x0000 }
5004 };
5005
beb1fe18 5006 rtl_csi_access_enable_2(tp);
b726e493
FR		 5007
5008 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5009
fdf6fc06 5010 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 5011
beb1fe18 5012 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5013}
5014
beb1fe18 5015static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 5016{
350f7596 5017 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 5018 { 0x01, 0, 0x0001 },
5019 { 0x03, 0x0400, 0x0220 }
5020 };
5021
beb1fe18 5022 rtl_csi_access_enable_2(tp);
b726e493 5023
fdf6fc06 5024 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 5025
beb1fe18 5026 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5027}
5028
beb1fe18 5029static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 5030{
beb1fe18 5031 rtl_hw_start_8168c_2(tp);
197ff761
FR		 5032}
5033
beb1fe18 5034static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 5035{
beb1fe18 5036 rtl_csi_access_enable_2(tp);
6fb07058 5037
beb1fe18 5038 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 5039}
5040
beb1fe18 5041static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 5042{
beb1fe18
HW		 5043 void __iomem *ioaddr = tp->mmio_addr;
5044 struct pci_dev *pdev = tp->pci_dev;
5045
5046 rtl_csi_access_enable_2(tp);
5b538df9
FR		 5047
5048 rtl_disable_clock_request(pdev);
5049
f0298f81 5050 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9 5051
faf1e785 5052 if (tp->dev->mtu <= ETH_DATA_LEN)
5053 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5b538df9
FR		 5054
5055 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5056}
5057
beb1fe18 5058static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 5059{
beb1fe18
HW		 5060 void __iomem *ioaddr = tp->mmio_addr;
5061 struct pci_dev *pdev = tp->pci_dev;
5062
5063 rtl_csi_access_enable_1(tp);
4804b3b3 5064
faf1e785 5065 if (tp->dev->mtu <= ETH_DATA_LEN)
5066 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804b3b3 5067
5068 RTL_W8(MaxTxPacketSize, TxPacketMax);
5069
5070 rtl_disable_clock_request(pdev);
5071}
5072
beb1fe18 5073static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 5074{
beb1fe18
HW		 5075 void __iomem *ioaddr = tp->mmio_addr;
5076 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 5077 static const struct ephy_info e_info_8168d_4[] = {
5078 { 0x0b, ~0, 0x48 },
5079 { 0x19, 0x20, 0x50 },
5080 { 0x0c, ~0, 0x20 }
5081 };
5082 int i;
5083
beb1fe18 5084 rtl_csi_access_enable_1(tp);
e6de30d6 5085
5086 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5087
5088 RTL_W8(MaxTxPacketSize, TxPacketMax);
5089
5090 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5091 const struct ephy_info *e = e_info_8168d_4 + i;
5092 u16 w;
5093
fdf6fc06
FR		 5094 w = rtl_ephy_read(tp, e->offset);
5095 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
e6de30d6 5096 }
5097
5098 rtl_enable_clock_request(pdev);
5099}
5100
beb1fe18 5101static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 5102{
beb1fe18
HW		 5103 void __iomem *ioaddr = tp->mmio_addr;
5104 struct pci_dev *pdev = tp->pci_dev;
70090424 5105 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5106 { 0x00, 0x0200, 0x0100 },
5107 { 0x00, 0x0000, 0x0004 },
5108 { 0x06, 0x0002, 0x0001 },
5109 { 0x06, 0x0000, 0x0030 },
5110 { 0x07, 0x0000, 0x2000 },
5111 { 0x00, 0x0000, 0x0020 },
5112 { 0x03, 0x5800, 0x2000 },
5113 { 0x03, 0x0000, 0x0001 },
5114 { 0x01, 0x0800, 0x1000 },
5115 { 0x07, 0x0000, 0x4000 },
5116 { 0x1e, 0x0000, 0x2000 },
5117 { 0x19, 0xffff, 0xfe6c },
5118 { 0x0a, 0x0000, 0x0040 }
5119 };
5120
beb1fe18 5121 rtl_csi_access_enable_2(tp);
01dc7fec 5122
fdf6fc06 5123 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5124
faf1e785 5125 if (tp->dev->mtu <= ETH_DATA_LEN)
5126 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
01dc7fec 5127
5128 RTL_W8(MaxTxPacketSize, TxPacketMax);
5129
5130 rtl_disable_clock_request(pdev);
5131
5132 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5133 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5134 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5135
cecb5fd7 5136 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5137}
5138
beb1fe18 5139static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5140{
beb1fe18
HW		 5141 void __iomem *ioaddr = tp->mmio_addr;
5142 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5143 static const struct ephy_info e_info_8168e_2[] = {
5144 { 0x09, 0x0000, 0x0080 },
5145 { 0x19, 0x0000, 0x0224 }
5146 };
5147
beb1fe18 5148 rtl_csi_access_enable_1(tp);
70090424 5149
fdf6fc06 5150 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5151
faf1e785 5152 if (tp->dev->mtu <= ETH_DATA_LEN)
5153 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
70090424 5154
fdf6fc06
FR		 5155 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5156 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5157 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5158 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5159 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5160 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5161 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5162 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5163
3090bd9a 5164 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5165
4521e1a9
FR		 5166 rtl_disable_clock_request(pdev);
5167
70090424
HW		 5168 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5169 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5170
5171 /* Adjust EEE LED frequency */
5172 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5173
5174 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5175 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4521e1a9 5176 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
70090424
HW		 5177}
5178
5f886e08 5179static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5180{
beb1fe18
HW		 5181 void __iomem *ioaddr = tp->mmio_addr;
5182 struct pci_dev *pdev = tp->pci_dev;
c2218925 5183
5f886e08 5184 rtl_csi_access_enable_2(tp);
c2218925
HW		 5185
5186 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5187
fdf6fc06
FR		 5188 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5189 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5190 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5191 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5192 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5193 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5194 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5195 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5196 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5197 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5198
5199 RTL_W8(MaxTxPacketSize, EarlySize);
5200
4521e1a9
FR		 5201 rtl_disable_clock_request(pdev);
5202
c2218925
HW		 5203 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5204 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5205 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4521e1a9
FR		 5206 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5207 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
c2218925
HW		 5208}
5209
5f886e08
HW		 5210static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5211{
5212 void __iomem *ioaddr = tp->mmio_addr;
5213 static const struct ephy_info e_info_8168f_1[] = {
5214 { 0x06, 0x00c0, 0x0020 },
5215 { 0x08, 0x0001, 0x0002 },
5216 { 0x09, 0x0000, 0x0080 },
5217 { 0x19, 0x0000, 0x0224 }
5218 };
5219
5220 rtl_hw_start_8168f(tp);
5221
fdf6fc06 5222 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5223
fdf6fc06 5224 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5225
5226 /* Adjust EEE LED frequency */
5227 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5228}
5229
b3d7b2f2
HW		 5230static void rtl_hw_start_8411(struct rtl8169_private *tp)
5231{
b3d7b2f2
HW		 5232 static const struct ephy_info e_info_8168f_1[] = {
5233 { 0x06, 0x00c0, 0x0020 },
5234 { 0x0f, 0xffff, 0x5200 },
5235 { 0x1e, 0x0000, 0x4000 },
5236 { 0x19, 0x0000, 0x0224 }
5237 };
5238
5239 rtl_hw_start_8168f(tp);
5240
fdf6fc06 5241 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5242
fdf6fc06 5243 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5244}
5245
c558386b
HW		 5246static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5247{
5248 void __iomem *ioaddr = tp->mmio_addr;
5249 struct pci_dev *pdev = tp->pci_dev;
5250
beb330a4 5251 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5252
c558386b
HW		 5253 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5254 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5255 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5256 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5257
5258 rtl_csi_access_enable_1(tp);
5259
5260 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5261
5262 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5263 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5264 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b
HW		 5265
5266 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4521e1a9 5267 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
c558386b
HW		 5268 RTL_W8(MaxTxPacketSize, EarlySize);
5269
5270 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5271 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5272
5273 /* Adjust EEE LED frequency */
5274 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5275
beb330a4 5276 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5277 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
c558386b
HW		 5278}
5279
57538c4a 5280static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5281{
5282 void __iomem *ioaddr = tp->mmio_addr;
5283 static const struct ephy_info e_info_8168g_2[] = {
5284 { 0x00, 0x0000, 0x0008 },
5285 { 0x0c, 0x3df0, 0x0200 },
5286 { 0x19, 0xffff, 0xfc00 },
5287 { 0x1e, 0xffff, 0x20eb }
5288 };
5289
5290 rtl_hw_start_8168g_1(tp);
5291
5292 /* disable aspm and clock request before access ephy */
5293 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5294 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5295 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5296}
5297
45dd95c4 5298static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5299{
5300 void __iomem *ioaddr = tp->mmio_addr;
5301 static const struct ephy_info e_info_8411_2[] = {
5302 { 0x00, 0x0000, 0x0008 },
5303 { 0x0c, 0x3df0, 0x0200 },
5304 { 0x0f, 0xffff, 0x5200 },
5305 { 0x19, 0x0020, 0x0000 },
5306 { 0x1e, 0x0000, 0x2000 }
5307 };
5308
5309 rtl_hw_start_8168g_1(tp);
5310
5311 /* disable aspm and clock request before access ephy */
5312 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5313 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5314 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5315}
5316
07ce4064
FR		 5317static void rtl_hw_start_8168(struct net_device *dev)
5318{
2dd99530
FR		 5319 struct rtl8169_private *tp = netdev_priv(dev);
5320 void __iomem *ioaddr = tp->mmio_addr;
5321
5322 RTL_W8(Cfg9346, Cfg9346_Unlock);
5323
f0298f81 5324 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 5325
6f0333b8 5326 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 5327
0e485150 5328 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 5329
5330 RTL_W16(CPlusCmd, tp->cp_cmd);
5331
0e485150 5332 RTL_W16(IntrMitigate, 0x5151);
2dd99530 5333
0e485150 5334 /* Work around for RxFIFO overflow. */
811fd301 5335 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5336 tp->event_slow |= RxFIFOOver | PCSTimeout;
5337 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5338 }
5339
5340 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 5341
1a964649 5342 rtl_set_rx_tx_config_registers(tp);
2dd99530
FR		 5343
5344 RTL_R8(IntrMask);
5345
219a1e9d
FR		 5346 switch (tp->mac_version) {
5347 case RTL_GIGA_MAC_VER_11:
beb1fe18 5348 rtl_hw_start_8168bb(tp);
4804b3b3 5349 break;
219a1e9d
FR		 5350
5351 case RTL_GIGA_MAC_VER_12:
5352 case RTL_GIGA_MAC_VER_17:
beb1fe18 5353 rtl_hw_start_8168bef(tp);
4804b3b3 5354 break;
219a1e9d
FR		 5355
5356 case RTL_GIGA_MAC_VER_18:
beb1fe18 5357 rtl_hw_start_8168cp_1(tp);
4804b3b3 5358 break;
219a1e9d
FR		 5359
5360 case RTL_GIGA_MAC_VER_19:
beb1fe18 5361 rtl_hw_start_8168c_1(tp);
4804b3b3 5362 break;
219a1e9d
FR		 5363
5364 case RTL_GIGA_MAC_VER_20:
beb1fe18 5365 rtl_hw_start_8168c_2(tp);
4804b3b3 5366 break;
219a1e9d 5367
197ff761 5368 case RTL_GIGA_MAC_VER_21:
beb1fe18 5369 rtl_hw_start_8168c_3(tp);
4804b3b3 5370 break;
197ff761 5371
6fb07058 5372 case RTL_GIGA_MAC_VER_22:
beb1fe18 5373 rtl_hw_start_8168c_4(tp);
4804b3b3 5374 break;
6fb07058 5375
ef3386f0 5376 case RTL_GIGA_MAC_VER_23:
beb1fe18 5377 rtl_hw_start_8168cp_2(tp);
4804b3b3 5378 break;
ef3386f0 5379
7f3e3d3a 5380 case RTL_GIGA_MAC_VER_24:
beb1fe18 5381 rtl_hw_start_8168cp_3(tp);
4804b3b3 5382 break;
7f3e3d3a 5383
5b538df9 5384 case RTL_GIGA_MAC_VER_25:
daf9df6d 5385 case RTL_GIGA_MAC_VER_26:
5386 case RTL_GIGA_MAC_VER_27:
beb1fe18 5387 rtl_hw_start_8168d(tp);
4804b3b3 5388 break;
5b538df9 5389
e6de30d6 5390 case RTL_GIGA_MAC_VER_28:
beb1fe18 5391 rtl_hw_start_8168d_4(tp);
4804b3b3 5392 break;
cecb5fd7 5393
4804b3b3 5394 case RTL_GIGA_MAC_VER_31:
beb1fe18 5395 rtl_hw_start_8168dp(tp);
4804b3b3 5396 break;
5397
01dc7fec 5398 case RTL_GIGA_MAC_VER_32:
5399 case RTL_GIGA_MAC_VER_33:
beb1fe18 5400 rtl_hw_start_8168e_1(tp);
70090424
HW		 5401 break;
5402 case RTL_GIGA_MAC_VER_34:
beb1fe18 5403 rtl_hw_start_8168e_2(tp);
01dc7fec 5404 break;
e6de30d6 5405
c2218925
HW		 5406 case RTL_GIGA_MAC_VER_35:
5407 case RTL_GIGA_MAC_VER_36:
beb1fe18 5408 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5409 break;
5410
b3d7b2f2
HW		 5411 case RTL_GIGA_MAC_VER_38:
5412 rtl_hw_start_8411(tp);
5413 break;
5414
c558386b
HW		 5415 case RTL_GIGA_MAC_VER_40:
5416 case RTL_GIGA_MAC_VER_41:
5417 rtl_hw_start_8168g_1(tp);
5418 break;
57538c4a 5419 case RTL_GIGA_MAC_VER_42:
5420 rtl_hw_start_8168g_2(tp);
5421 break;
c558386b 5422
45dd95c4 5423 case RTL_GIGA_MAC_VER_44:
5424 rtl_hw_start_8411_2(tp);
5425 break;
5426
219a1e9d
FR		 5427 default:
5428 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5429 dev->name, tp->mac_version);
4804b3b3 5430 break;
219a1e9d 5431 }
2dd99530 5432
1a964649 5433 RTL_W8(Cfg9346, Cfg9346_Lock);
5434
0e485150
FR		 5435 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5436
1a964649 5437 rtl_set_rx_mode(dev);
b8363901 5438
2dd99530 5439 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5440}
1da177e4 5441
2857ffb7
FR		 5442#define R810X_CPCMD_QUIRK_MASK (\
5443 EnableBist | \
5444 Mac_dbgo_oe | \
5445 Force_half_dup | \
5edcc537 5446 Force_rxflow_en | \
2857ffb7
FR		 5447 Force_txflow_en | \
5448 Cxpl_dbg_sel | \
5449 ASF | \
5450 PktCntrDisable | \
d24e9aaf 5451 Mac_dbgo_sel)
2857ffb7 5452
beb1fe18 5453static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5454{
beb1fe18
HW		 5455 void __iomem *ioaddr = tp->mmio_addr;
5456 struct pci_dev *pdev = tp->pci_dev;
350f7596 5457 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5458 { 0x01, 0, 0x6e65 },
5459 { 0x02, 0, 0x091f },
5460 { 0x03, 0, 0xc2f9 },
5461 { 0x06, 0, 0xafb5 },
5462 { 0x07, 0, 0x0e00 },
5463 { 0x19, 0, 0xec80 },
5464 { 0x01, 0, 0x2e65 },
5465 { 0x01, 0, 0x6e65 }
5466 };
5467 u8 cfg1;
5468
beb1fe18 5469 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5470
5471 RTL_W8(DBG_REG, FIX_NAK_1);
5472
5473 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5474
5475 RTL_W8(Config1,
5476 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5477 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5478
5479 cfg1 = RTL_R8(Config1);
5480 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5481 RTL_W8(Config1, cfg1 & ~LEDS0);
5482
fdf6fc06 5483 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5484}
5485
beb1fe18 5486static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5487{
beb1fe18
HW		 5488 void __iomem *ioaddr = tp->mmio_addr;
5489 struct pci_dev *pdev = tp->pci_dev;
5490
5491 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5492
5493 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5494
5495 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5496 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5497}
5498
beb1fe18 5499static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5500{
beb1fe18 5501 rtl_hw_start_8102e_2(tp);
2857ffb7 5502
fdf6fc06 5503 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5504}
5505
beb1fe18 5506static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 5507{
beb1fe18 5508 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 5509 static const struct ephy_info e_info_8105e_1[] = {
5510 { 0x07, 0, 0x4000 },
5511 { 0x19, 0, 0x0200 },
5512 { 0x19, 0, 0x0020 },
5513 { 0x1e, 0, 0x2000 },
5514 { 0x03, 0, 0x0001 },
5515 { 0x19, 0, 0x0100 },
5516 { 0x19, 0, 0x0004 },
5517 { 0x0a, 0, 0x0020 }
5518 };
5519
cecb5fd7 5520 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5521 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5522
cecb5fd7 5523 /* Disable Early Tally Counter */
5a5e4443
HW		 5524 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5525
5526 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5527 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 5528
fdf6fc06 5529 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5a5e4443
HW		 5530}
5531
beb1fe18 5532static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5533{
beb1fe18 5534 rtl_hw_start_8105e_1(tp);
fdf6fc06 5535 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5536}
5537
7e18dca1
HW		 5538static void rtl_hw_start_8402(struct rtl8169_private *tp)
5539{
5540 void __iomem *ioaddr = tp->mmio_addr;
5541 static const struct ephy_info e_info_8402[] = {
5542 { 0x19, 0xffff, 0xff64 },
5543 { 0x1e, 0, 0x4000 }
5544 };
5545
5546 rtl_csi_access_enable_2(tp);
5547
5548 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5549 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5550
5551 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5552 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5553
fdf6fc06 5554 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 5555
5556 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5557
fdf6fc06
FR		 5558 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5559 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5560 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5561 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5562 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5563 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5564 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
7e18dca1
HW		 5565}
5566
5598bfe5
HW		 5567static void rtl_hw_start_8106(struct rtl8169_private *tp)
5568{
5569 void __iomem *ioaddr = tp->mmio_addr;
5570
5571 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5572 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5573
4521e1a9 5574 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5598bfe5
HW		 5575 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5576 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5577}
5578
07ce4064
FR		 5579static void rtl_hw_start_8101(struct net_device *dev)
5580{
cdf1a608
FR		 5581 struct rtl8169_private *tp = netdev_priv(dev);
5582 void __iomem *ioaddr = tp->mmio_addr;
5583 struct pci_dev *pdev = tp->pci_dev;
5584
da78dbff
FR		 5585 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5586 tp->event_slow &= ~RxFIFOOver;
811fd301 5587
cecb5fd7 5588 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5589 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 5590 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5591 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5592
d24e9aaf
HW		 5593 RTL_W8(Cfg9346, Cfg9346_Unlock);
5594
1a964649 5595 RTL_W8(MaxTxPacketSize, TxPacketMax);
5596
5597 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5598
5599 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5600 RTL_W16(CPlusCmd, tp->cp_cmd);
5601
5602 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5603
5604 rtl_set_rx_tx_config_registers(tp);
5605
2857ffb7
FR		 5606 switch (tp->mac_version) {
5607 case RTL_GIGA_MAC_VER_07:
beb1fe18 5608 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5609 break;
5610
5611 case RTL_GIGA_MAC_VER_08:
beb1fe18 5612 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5613 break;
5614
5615 case RTL_GIGA_MAC_VER_09:
beb1fe18 5616 rtl_hw_start_8102e_2(tp);
2857ffb7 5617 break;
5a5e4443
HW		 5618
5619 case RTL_GIGA_MAC_VER_29:
beb1fe18 5620 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5621 break;
5622 case RTL_GIGA_MAC_VER_30:
beb1fe18 5623 rtl_hw_start_8105e_2(tp);
5a5e4443 5624 break;
7e18dca1
HW		 5625
5626 case RTL_GIGA_MAC_VER_37:
5627 rtl_hw_start_8402(tp);
5628 break;
5598bfe5
HW		 5629
5630 case RTL_GIGA_MAC_VER_39:
5631 rtl_hw_start_8106(tp);
5632 break;
58152cd4 5633 case RTL_GIGA_MAC_VER_43:
5634 rtl_hw_start_8168g_2(tp);
5635 break;
cdf1a608
FR		 5636 }
5637
d24e9aaf 5638 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5639
cdf1a608
FR		 5640 RTL_W16(IntrMitigate, 0x0000);
5641
cdf1a608 5642 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
cdf1a608 5643
cdf1a608
FR		 5644 rtl_set_rx_mode(dev);
5645
1a964649 5646 RTL_R8(IntrMask);
5647
cdf1a608 5648 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5649}
5650
5651static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5652{
d58d46b5
FR		 5653 struct rtl8169_private *tp = netdev_priv(dev);
5654
5655 if (new_mtu < ETH_ZLEN ||
5656 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5657 return -EINVAL;
5658
d58d46b5
FR		 5659 if (new_mtu > ETH_DATA_LEN)
5660 rtl_hw_jumbo_enable(tp);
5661 else
5662 rtl_hw_jumbo_disable(tp);
5663
1da177e4 5664 dev->mtu = new_mtu;
350fb32a
MM		 5665 netdev_update_features(dev);
5666
323bb685 5667 return 0;
1da177e4
LT		 5668}
5669
5670static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5671{
95e0918d 5672 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5673 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5674}
5675
6f0333b8
ED		 5676static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5677 void **data_buff, struct RxDesc *desc)
1da177e4 5678{
48addcc9 5679 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5680 DMA_FROM_DEVICE);
48addcc9 5681
6f0333b8
ED		 5682 kfree(*data_buff);
5683 *data_buff = NULL;
1da177e4
LT		 5684 rtl8169_make_unusable_by_asic(desc);
5685}
5686
5687static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5688{
5689 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5690
5691 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5692}
5693
5694static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5695 u32 rx_buf_sz)
5696{
5697 desc->addr = cpu_to_le64(mapping);
5698 wmb();
5699 rtl8169_mark_to_asic(desc, rx_buf_sz);
5700}
5701
6f0333b8
ED		 5702static inline void *rtl8169_align(void *data)
5703{
5704 return (void *)ALIGN((long)data, 16);
5705}
5706
0ecbe1ca
SG		 5707static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5708 struct RxDesc *desc)
1da177e4 5709{
6f0333b8 5710 void *data;
1da177e4 5711 dma_addr_t mapping;
48addcc9 5712 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5713 struct net_device *dev = tp->dev;
6f0333b8 5714 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5715
6f0333b8
ED		 5716 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5717 if (!data)
5718 return NULL;
e9f63f30 5719
6f0333b8
ED		 5720 if (rtl8169_align(data) != data) {
5721 kfree(data);
5722 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5723 if (!data)
5724 return NULL;
5725 }
3eafe507 5726
48addcc9 5727 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5728 DMA_FROM_DEVICE);
d827d86b
SG		 5729 if (unlikely(dma_mapping_error(d, mapping))) {
5730 if (net_ratelimit())
5731 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5732 goto err_out;
d827d86b 5733 }
1da177e4
LT		 5734
5735 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5736 return data;
3eafe507
SG		 5737
5738err_out:
5739 kfree(data);
5740 return NULL;
1da177e4
LT		 5741}
5742
5743static void rtl8169_rx_clear(struct rtl8169_private *tp)
5744{
07d3f51f 5745 unsigned int i;
1da177e4
LT		 5746
5747 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5748 if (tp->Rx_databuff[i]) {
5749 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5750 tp->RxDescArray + i);
5751 }
5752 }
5753}
5754
0ecbe1ca 5755static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5756{
0ecbe1ca
SG		 5757 desc->opts1 |= cpu_to_le32(RingEnd);
5758}
5b0384f4 5759
0ecbe1ca
SG		 5760static int rtl8169_rx_fill(struct rtl8169_private *tp)
5761{
5762 unsigned int i;
1da177e4 5763
0ecbe1ca
SG		 5764 for (i = 0; i < NUM_RX_DESC; i++) {
5765 void *data;
4ae47c2d 5766
6f0333b8 5767 if (tp->Rx_databuff[i])
1da177e4 5768 continue;
bcf0bf90 5769
0ecbe1ca 5770 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5771 if (!data) {
5772 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5773 goto err_out;
6f0333b8
ED		 5774 }
5775 tp->Rx_databuff[i] = data;
1da177e4 5776 }
1da177e4 5777
0ecbe1ca
SG		 5778 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5779 return 0;
5780
5781err_out:
5782 rtl8169_rx_clear(tp);
5783 return -ENOMEM;
1da177e4
LT		 5784}
5785
1da177e4
LT		 5786static int rtl8169_init_ring(struct net_device *dev)
5787{
5788 struct rtl8169_private *tp = netdev_priv(dev);
5789
5790 rtl8169_init_ring_indexes(tp);
5791
5792 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5793 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5794
0ecbe1ca 5795 return rtl8169_rx_fill(tp);
1da177e4
LT		 5796}
5797
48addcc9 5798static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5799 struct TxDesc *desc)
5800{
5801 unsigned int len = tx_skb->len;
5802
48addcc9
SG		 5803 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5804
1da177e4
LT		 5805 desc->opts1 = 0x00;
5806 desc->opts2 = 0x00;
5807 desc->addr = 0x00;
5808 tx_skb->len = 0;
5809}
5810
3eafe507
SG		 5811static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5812 unsigned int n)
1da177e4
LT		 5813{
5814 unsigned int i;
5815
3eafe507
SG		 5816 for (i = 0; i < n; i++) {
5817 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5818 struct ring_info *tx_skb = tp->tx_skb + entry;
5819 unsigned int len = tx_skb->len;
5820
5821 if (len) {
5822 struct sk_buff *skb = tx_skb->skb;
5823
48addcc9 5824 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5825 tp->TxDescArray + entry);
5826 if (skb) {
cac4b22f 5827 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5828 dev_kfree_skb(skb);
5829 tx_skb->skb = NULL;
5830 }
1da177e4
LT		 5831 }
5832 }
3eafe507
SG		 5833}
5834
5835static void rtl8169_tx_clear(struct rtl8169_private *tp)
5836{
5837 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5838 tp->cur_tx = tp->dirty_tx = 0;
5839}
5840
4422bcd4 5841static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5842{
c4028958 5843 struct net_device *dev = tp->dev;
56de414c 5844 int i;
1da177e4 5845
da78dbff
FR		 5846 napi_disable(&tp->napi);
5847 netif_stop_queue(dev);
5848 synchronize_sched();
1da177e4 5849
c7c2c39b 5850 rtl8169_hw_reset(tp);
5851
56de414c
FR		 5852 for (i = 0; i < NUM_RX_DESC; i++)
5853 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5854
1da177e4 5855 rtl8169_tx_clear(tp);
c7c2c39b 5856 rtl8169_init_ring_indexes(tp);
1da177e4 5857
da78dbff 5858 napi_enable(&tp->napi);
56de414c
FR		 5859 rtl_hw_start(dev);
5860 netif_wake_queue(dev);
5861 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5862}
5863
5864static void rtl8169_tx_timeout(struct net_device *dev)
5865{
da78dbff
FR		 5866 struct rtl8169_private *tp = netdev_priv(dev);
5867
5868 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5869}
5870
5871static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5872 u32 *opts)
1da177e4
LT		 5873{
5874 struct skb_shared_info *info = skb_shinfo(skb);
5875 unsigned int cur_frag, entry;
a6343afb 5876 struct TxDesc * uninitialized_var(txd);
48addcc9 5877 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5878
5879 entry = tp->cur_tx;
5880 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5881 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5882 dma_addr_t mapping;
5883 u32 status, len;
5884 void *addr;
5885
5886 entry = (entry + 1) % NUM_TX_DESC;
5887
5888 txd = tp->TxDescArray + entry;
9e903e08 5889 len = skb_frag_size(frag);
929f6189 5890 addr = skb_frag_address(frag);
48addcc9 5891 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5892 if (unlikely(dma_mapping_error(d, mapping))) {
5893 if (net_ratelimit())
5894 netif_err(tp, drv, tp->dev,
5895 "Failed to map TX fragments DMA!\n");
3eafe507 5896 goto err_out;
d827d86b 5897 }
1da177e4 5898
cecb5fd7 5899 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5900 status = opts[0] | len |
5901 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5902
5903 txd->opts1 = cpu_to_le32(status);
2b7b4318 5904 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5905 txd->addr = cpu_to_le64(mapping);
5906
5907 tp->tx_skb[entry].len = len;
5908 }
5909
5910 if (cur_frag) {
5911 tp->tx_skb[entry].skb = skb;
5912 txd->opts1 |= cpu_to_le32(LastFrag);
5913 }
5914
5915 return cur_frag;
3eafe507
SG		 5916
5917err_out:
5918 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5919 return -EIO;
1da177e4
LT		 5920}
5921
b423e9ae 5922static bool rtl_skb_pad(struct sk_buff *skb)
5923{
5924 if (skb_padto(skb, ETH_ZLEN))
5925 return false;
5926 skb_put(skb, ETH_ZLEN - skb->len);
5927 return true;
5928}
5929
5930static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5931{
5932 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5933}
5934
5935static inline bool rtl8169_tso_csum(struct rtl8169_private *tp,
2b7b4318 5936 struct sk_buff *skb, u32 *opts)
1da177e4 5937{
2b7b4318 5938 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5939 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5940 int offset = info->opts_offset;
350fb32a 5941
2b7b4318
FR		 5942 if (mss) {
5943 opts[0] |= TD_LSO;
5944 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5945 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5946 const struct iphdr *ip = ip_hdr(skb);
1da177e4 5947
b423e9ae 5948 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5949 return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
5950
1da177e4 5951 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5952 opts[offset] |= info->checksum.tcp;
1da177e4 5953 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5954 opts[offset] |= info->checksum.udp;
5955 else
5956 WARN_ON_ONCE(1);
b423e9ae 5957 } else {
5958 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5959 return rtl_skb_pad(skb);
1da177e4 5960 }
b423e9ae 5961 return true;
1da177e4
LT		 5962}
5963
61357325
SH		 5964static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5965 struct net_device *dev)
1da177e4
LT		 5966{
5967 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5968 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5969 struct TxDesc *txd = tp->TxDescArray + entry;
5970 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5971 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5972 dma_addr_t mapping;
5973 u32 status, len;
2b7b4318 5974 u32 opts[2];
3eafe507 5975 int frags;
5b0384f4 5976
477206a0 5977 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 5978 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5979 goto err_stop_0;
1da177e4
LT		 5980 }
5981
5982 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5983 goto err_stop_0;
5984
b423e9ae 5985 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5986 opts[0] = DescOwn;
5987
5988 if (!rtl8169_tso_csum(tp, skb, opts))
5989 goto err_update_stats;
5990
3eafe507 5991 len = skb_headlen(skb);
48addcc9 5992 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5993 if (unlikely(dma_mapping_error(d, mapping))) {
5994 if (net_ratelimit())
5995 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5996 goto err_dma_0;
d827d86b 5997 }
3eafe507
SG		 5998
5999 tp->tx_skb[entry].len = len;
6000 txd->addr = cpu_to_le64(mapping);
1da177e4 6001
2b7b4318 6002 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 6003 if (frags < 0)
6004 goto err_dma_1;
6005 else if (frags)
2b7b4318 6006 opts[0] |= FirstFrag;
3eafe507 6007 else {
2b7b4318 6008 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 6009 tp->tx_skb[entry].skb = skb;
6010 }
6011
2b7b4318
FR		 6012 txd->opts2 = cpu_to_le32(opts[1]);
6013
5047fb5d
RC		 6014 skb_tx_timestamp(skb);
6015
1da177e4
LT		 6016 wmb();
6017
cecb5fd7 6018 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 6019 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6020 txd->opts1 = cpu_to_le32(status);
6021
1da177e4
LT		 6022 tp->cur_tx += frags + 1;
6023
4c020a96 6024 wmb();
1da177e4 6025
cecb5fd7 6026 RTL_W8(TxPoll, NPQ);
1da177e4 6027
da78dbff
FR		 6028 mmiowb();
6029
477206a0 6030 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 6031 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6032 * not miss a ring update when it notices a stopped queue.
6033 */
6034 smp_wmb();
1da177e4 6035 netif_stop_queue(dev);
ae1f23fb
FR		 6036 /* Sync with rtl_tx:
6037 * - publish queue status and cur_tx ring index (write barrier)
6038 * - refresh dirty_tx ring index (read barrier).
6039 * May the current thread have a pessimistic view of the ring
6040 * status and forget to wake up queue, a racing rtl_tx thread
6041 * can't.
6042 */
1e874e04 6043 smp_mb();
477206a0 6044 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 6045 netif_wake_queue(dev);
6046 }
6047
61357325 6048 return NETDEV_TX_OK;
1da177e4 6049
3eafe507 6050err_dma_1:
48addcc9 6051 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 6052err_dma_0:
6053 dev_kfree_skb(skb);
e5195c1f 6054err_update_stats:
3eafe507
SG		 6055 dev->stats.tx_dropped++;
6056 return NETDEV_TX_OK;
6057
6058err_stop_0:
1da177e4 6059 netif_stop_queue(dev);
cebf8cc7 6060 dev->stats.tx_dropped++;
61357325 6061 return NETDEV_TX_BUSY;
1da177e4
LT		 6062}
6063
6064static void rtl8169_pcierr_interrupt(struct net_device *dev)
6065{
6066 struct rtl8169_private *tp = netdev_priv(dev);
6067 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 6068 u16 pci_status, pci_cmd;
6069
6070 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6071 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6072
bf82c189
JP		 6073 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6074 pci_cmd, pci_status);
1da177e4
LT		 6075
6076 /*
6077 * The recovery sequence below admits a very elaborated explanation:
6078 * - it seems to work;
d03902b8
FR		 6079 * - I did not see what else could be done;
6080 * - it makes iop3xx happy.
1da177e4
LT		 6081 *
6082 * Feel free to adjust to your needs.
6083 */
a27993f3 6084 if (pdev->broken_parity_status)
d03902b8
FR		 6085 pci_cmd &= ~PCI_COMMAND_PARITY;
6086 else
6087 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6088
6089 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 6090
6091 pci_write_config_word(pdev, PCI_STATUS,
6092 pci_status & (PCI_STATUS_DETECTED_PARITY |
6093 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6094 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6095
6096 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 6097 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
e6de30d6 6098 void __iomem *ioaddr = tp->mmio_addr;
6099
bf82c189 6100 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 6101 tp->cp_cmd &= ~PCIDAC;
6102 RTL_W16(CPlusCmd, tp->cp_cmd);
6103 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 6104 }
6105
e6de30d6 6106 rtl8169_hw_reset(tp);
d03902b8 6107
98ddf986 6108 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6109}
6110
da78dbff 6111static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 6112{
6113 unsigned int dirty_tx, tx_left;
6114
1da177e4
LT		 6115 dirty_tx = tp->dirty_tx;
6116 smp_rmb();
6117 tx_left = tp->cur_tx - dirty_tx;
6118
6119 while (tx_left > 0) {
6120 unsigned int entry = dirty_tx % NUM_TX_DESC;
6121 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 6122 u32 status;
6123
6124 rmb();
6125 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6126 if (status & DescOwn)
6127 break;
6128
48addcc9
SG		 6129 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6130 tp->TxDescArray + entry);
1da177e4 6131 if (status & LastFrag) {
17bcb684
FR		 6132 u64_stats_update_begin(&tp->tx_stats.syncp);
6133 tp->tx_stats.packets++;
6134 tp->tx_stats.bytes += tx_skb->skb->len;
6135 u64_stats_update_end(&tp->tx_stats.syncp);
6136 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 6137 tx_skb->skb = NULL;
6138 }
6139 dirty_tx++;
6140 tx_left--;
6141 }
6142
6143 if (tp->dirty_tx != dirty_tx) {
6144 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6145 /* Sync with rtl8169_start_xmit:
6146 * - publish dirty_tx ring index (write barrier)
6147 * - refresh cur_tx ring index and queue status (read barrier)
6148 * May the current thread miss the stopped queue condition,
6149 * a racing xmit thread can only have a right view of the
6150 * ring status.
6151 */
1e874e04 6152 smp_mb();
1da177e4 6153 if (netif_queue_stopped(dev) &&
477206a0 6154 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6155 netif_wake_queue(dev);
6156 }
d78ae2dc
FR		 6157 /*
6158 * 8168 hack: TxPoll requests are lost when the Tx packets are
6159 * too close. Let's kick an extra TxPoll request when a burst
6160 * of start_xmit activity is detected (if it is not detected,
6161 * it is slow enough). -- FR
6162 */
da78dbff
FR		 6163 if (tp->cur_tx != dirty_tx) {
6164 void __iomem *ioaddr = tp->mmio_addr;
6165
d78ae2dc 6166 RTL_W8(TxPoll, NPQ);
da78dbff 6167 }
1da177e4
LT		 6168 }
6169}
6170
126fa4b9
FR		 6171static inline int rtl8169_fragmented_frame(u32 status)
6172{
6173 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6174}
6175
adea1ac7 6176static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6177{
1da177e4
LT		 6178 u32 status = opts1 & RxProtoMask;
6179
6180 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6181 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6182 skb->ip_summed = CHECKSUM_UNNECESSARY;
6183 else
bc8acf2c 6184 skb_checksum_none_assert(skb);
1da177e4
LT		 6185}
6186
6f0333b8
ED		 6187static struct sk_buff *rtl8169_try_rx_copy(void *data,
6188 struct rtl8169_private *tp,
6189 int pkt_size,
6190 dma_addr_t addr)
1da177e4 6191{
b449655f 6192 struct sk_buff *skb;
48addcc9 6193 struct device *d = &tp->pci_dev->dev;
b449655f 6194
6f0333b8 6195 data = rtl8169_align(data);
48addcc9 6196 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 6197 prefetch(data);
6198 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6199 if (skb)
6200 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 6201 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6202
6f0333b8 6203 return skb;
1da177e4
LT		 6204}
6205
da78dbff 6206static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6207{
6208 unsigned int cur_rx, rx_left;
6f0333b8 6209 unsigned int count;
1da177e4 6210
1da177e4 6211 cur_rx = tp->cur_rx;
1da177e4 6212
9fba0812 6213 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6214 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6215 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6216 u32 status;
6217
6218 rmb();
e03f33af 6219 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 6220
6221 if (status & DescOwn)
6222 break;
4dcb7d33 6223 if (unlikely(status & RxRES)) {
bf82c189
JP		 6224 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6225 status);
cebf8cc7 6226 dev->stats.rx_errors++;
1da177e4 6227 if (status & (RxRWT | RxRUNT))
cebf8cc7 6228 dev->stats.rx_length_errors++;
1da177e4 6229 if (status & RxCRC)
cebf8cc7 6230 dev->stats.rx_crc_errors++;
9dccf611 6231 if (status & RxFOVF) {
da78dbff 6232 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6233 dev->stats.rx_fifo_errors++;
9dccf611 6234 }
6bbe021d
BG		 6235 if ((status & (RxRUNT | RxCRC)) &&
6236 !(status & (RxRWT | RxFOVF)) &&
6237 (dev->features & NETIF_F_RXALL))
6238 goto process_pkt;
1da177e4 6239 } else {
6f0333b8 6240 struct sk_buff *skb;
6bbe021d
BG		 6241 dma_addr_t addr;
6242 int pkt_size;
6243
6244process_pkt:
6245 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6246 if (likely(!(dev->features & NETIF_F_RXFCS)))
6247 pkt_size = (status & 0x00003fff) - 4;
6248 else
6249 pkt_size = status & 0x00003fff;
1da177e4 6250
126fa4b9
FR		 6251 /*
6252 * The driver does not support incoming fragmented
6253 * frames. They are seen as a symptom of over-mtu
6254 * sized frames.
6255 */
6256 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6257 dev->stats.rx_dropped++;
6258 dev->stats.rx_length_errors++;
ce11ff5e 6259 goto release_descriptor;
126fa4b9
FR		 6260 }
6261
6f0333b8
ED		 6262 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6263 tp, pkt_size, addr);
6f0333b8
ED		 6264 if (!skb) {
6265 dev->stats.rx_dropped++;
ce11ff5e 6266 goto release_descriptor;
1da177e4
LT		 6267 }
6268
adea1ac7 6269 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6270 skb_put(skb, pkt_size);
6271 skb->protocol = eth_type_trans(skb, dev);
6272
7a8fc77b
FR		 6273 rtl8169_rx_vlan_tag(desc, skb);
6274
56de414c 6275 napi_gro_receive(&tp->napi, skb);
1da177e4 6276
8027aa24
JW		 6277 u64_stats_update_begin(&tp->rx_stats.syncp);
6278 tp->rx_stats.packets++;
6279 tp->rx_stats.bytes += pkt_size;
6280 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6281 }
ce11ff5e 6282release_descriptor:
6283 desc->opts2 = 0;
6284 wmb();
6285 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 6286 }
6287
6288 count = cur_rx - tp->cur_rx;
6289 tp->cur_rx = cur_rx;
6290
1da177e4
LT		 6291 return count;
6292}
6293
07d3f51f 6294static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6295{
07d3f51f 6296 struct net_device *dev = dev_instance;
1da177e4 6297 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6298 int handled = 0;
9085cdfa 6299 u16 status;
1da177e4 6300
9085cdfa 6301 status = rtl_get_events(tp);
da78dbff
FR		 6302 if (status && status != 0xffff) {
6303 status &= RTL_EVENT_NAPI | tp->event_slow;
6304 if (status) {
6305 handled = 1;
1da177e4 6306
da78dbff
FR		 6307 rtl_irq_disable(tp);
6308 napi_schedule(&tp->napi);
f11a377b 6309 }
da78dbff
FR		 6310 }
6311 return IRQ_RETVAL(handled);
6312}
1da177e4 6313
da78dbff
FR		 6314/*
6315 * Workqueue context.
6316 */
6317static void rtl_slow_event_work(struct rtl8169_private *tp)
6318{
6319 struct net_device *dev = tp->dev;
6320 u16 status;
6321
6322 status = rtl_get_events(tp) & tp->event_slow;
6323 rtl_ack_events(tp, status);
1da177e4 6324
da78dbff
FR		 6325 if (unlikely(status & RxFIFOOver)) {
6326 switch (tp->mac_version) {
6327 /* Work around for rx fifo overflow */
6328 case RTL_GIGA_MAC_VER_11:
6329 netif_stop_queue(dev);
934714d0
FR		 6330 /* XXX - Hack alert. See rtl_task(). */
6331 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6332 default:
f11a377b
DD		 6333 break;
6334 }
da78dbff 6335 }
1da177e4 6336
da78dbff
FR		 6337 if (unlikely(status & SYSErr))
6338 rtl8169_pcierr_interrupt(dev);
0e485150 6339
da78dbff
FR		 6340 if (status & LinkChg)
6341 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 6342
7dbb4918 6343 rtl_irq_enable_all(tp);
1da177e4
LT		 6344}
6345
4422bcd4
FR		 6346static void rtl_task(struct work_struct *work)
6347{
da78dbff
FR		 6348 static const struct {
6349 int bitnr;
6350 void (*action)(struct rtl8169_private *);
6351 } rtl_work[] = {
934714d0 6352 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6353 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6354 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6355 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6356 };
4422bcd4
FR		 6357 struct rtl8169_private *tp =
6358 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6359 struct net_device *dev = tp->dev;
6360 int i;
6361
6362 rtl_lock_work(tp);
6363
6c4a70c5
FR		 6364 if (!netif_running(dev) ||
6365 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6366 goto out_unlock;
6367
6368 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6369 bool pending;
6370
da78dbff 6371 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6372 if (pending)
6373 rtl_work[i].action(tp);
6374 }
4422bcd4 6375
da78dbff
FR		 6376out_unlock:
6377 rtl_unlock_work(tp);
4422bcd4
FR		 6378}
6379
bea3348e 6380static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6381{
bea3348e
SH		 6382 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6383 struct net_device *dev = tp->dev;
da78dbff
FR		 6384 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6385 int work_done= 0;
6386 u16 status;
6387
6388 status = rtl_get_events(tp);
6389 rtl_ack_events(tp, status & ~tp->event_slow);
6390
6391 if (status & RTL_EVENT_NAPI_RX)
6392 work_done = rtl_rx(dev, tp, (u32) budget);
6393
6394 if (status & RTL_EVENT_NAPI_TX)
6395 rtl_tx(dev, tp);
1da177e4 6396
da78dbff
FR		 6397 if (status & tp->event_slow) {
6398 enable_mask &= ~tp->event_slow;
6399
6400 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6401 }
1da177e4 6402
bea3348e 6403 if (work_done < budget) {
288379f0 6404 napi_complete(napi);
f11a377b 6405
da78dbff
FR		 6406 rtl_irq_enable(tp, enable_mask);
6407 mmiowb();
1da177e4
LT		 6408 }
6409
bea3348e 6410 return work_done;
1da177e4 6411}
1da177e4 6412
523a6094
FR		 6413static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6414{
6415 struct rtl8169_private *tp = netdev_priv(dev);
6416
6417 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6418 return;
6419
6420 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6421 RTL_W32(RxMissed, 0);
6422}
6423
1da177e4
LT		 6424static void rtl8169_down(struct net_device *dev)
6425{
6426 struct rtl8169_private *tp = netdev_priv(dev);
6427 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6428
4876cc1e 6429 del_timer_sync(&tp->timer);
1da177e4 6430
93dd79e8 6431 napi_disable(&tp->napi);
da78dbff 6432 netif_stop_queue(dev);
1da177e4 6433
92fc43b4 6434 rtl8169_hw_reset(tp);
323bb685
SG		 6435 /*
6436 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6437 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6438 * and napi is disabled (rtl8169_poll).
323bb685 6439 */
523a6094 6440 rtl8169_rx_missed(dev, ioaddr);
1da177e4 6441
1da177e4 6442 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6443 synchronize_sched();
1da177e4 6444
1da177e4
LT		 6445 rtl8169_tx_clear(tp);
6446
6447 rtl8169_rx_clear(tp);
065c27c1 6448
6449 rtl_pll_power_down(tp);
1da177e4
LT		 6450}
6451
6452static int rtl8169_close(struct net_device *dev)
6453{
6454 struct rtl8169_private *tp = netdev_priv(dev);
6455 struct pci_dev *pdev = tp->pci_dev;
6456
e1759441
RW		 6457 pm_runtime_get_sync(&pdev->dev);
6458
cecb5fd7 6459 /* Update counters before going down */
355423d0
IV		 6460 rtl8169_update_counters(dev);
6461
da78dbff 6462 rtl_lock_work(tp);
6c4a70c5 6463 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6464
1da177e4 6465 rtl8169_down(dev);
da78dbff 6466 rtl_unlock_work(tp);
1da177e4 6467
4ea72445
L		 6468 cancel_work_sync(&tp->wk.work);
6469
92a7c4e7 6470 free_irq(pdev->irq, dev);
1da177e4 6471
82553bb6
SG		 6472 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6473 tp->RxPhyAddr);
6474 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6475 tp->TxPhyAddr);
1da177e4
LT		 6476 tp->TxDescArray = NULL;
6477 tp->RxDescArray = NULL;
6478
e1759441
RW		 6479 pm_runtime_put_sync(&pdev->dev);
6480
1da177e4
LT		 6481 return 0;
6482}
6483
dc1c00ce
FR		 6484#ifdef CONFIG_NET_POLL_CONTROLLER
6485static void rtl8169_netpoll(struct net_device *dev)
6486{
6487 struct rtl8169_private *tp = netdev_priv(dev);
6488
6489 rtl8169_interrupt(tp->pci_dev->irq, dev);
6490}
6491#endif
6492
df43ac78
FR		 6493static int rtl_open(struct net_device *dev)
6494{
6495 struct rtl8169_private *tp = netdev_priv(dev);
6496 void __iomem *ioaddr = tp->mmio_addr;
6497 struct pci_dev *pdev = tp->pci_dev;
6498 int retval = -ENOMEM;
6499
6500 pm_runtime_get_sync(&pdev->dev);
6501
6502 /*
e75d6606 6503 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6504 * dma_alloc_coherent provides more.
6505 */
6506 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6507 &tp->TxPhyAddr, GFP_KERNEL);
6508 if (!tp->TxDescArray)
6509 goto err_pm_runtime_put;
6510
6511 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6512 &tp->RxPhyAddr, GFP_KERNEL);
6513 if (!tp->RxDescArray)
6514 goto err_free_tx_0;
6515
6516 retval = rtl8169_init_ring(dev);
6517 if (retval < 0)
6518 goto err_free_rx_1;
6519
6520 INIT_WORK(&tp->wk.work, rtl_task);
6521
6522 smp_mb();
6523
6524 rtl_request_firmware(tp);
6525
92a7c4e7 6526 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 6527 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6528 dev->name, dev);
6529 if (retval < 0)
6530 goto err_release_fw_2;
6531
6532 rtl_lock_work(tp);
6533
6534 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6535
6536 napi_enable(&tp->napi);
6537
6538 rtl8169_init_phy(dev, tp);
6539
6540 __rtl8169_set_features(dev, dev->features);
6541
6542 rtl_pll_power_up(tp);
6543
6544 rtl_hw_start(dev);
6545
6546 netif_start_queue(dev);
6547
6548 rtl_unlock_work(tp);
6549
6550 tp->saved_wolopts = 0;
6551 pm_runtime_put_noidle(&pdev->dev);
6552
6553 rtl8169_check_link_status(dev, tp, ioaddr);
6554out:
6555 return retval;
6556
6557err_release_fw_2:
6558 rtl_release_firmware(tp);
6559 rtl8169_rx_clear(tp);
6560err_free_rx_1:
6561 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6562 tp->RxPhyAddr);
6563 tp->RxDescArray = NULL;
6564err_free_tx_0:
6565 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6566 tp->TxPhyAddr);
6567 tp->TxDescArray = NULL;
6568err_pm_runtime_put:
6569 pm_runtime_put_noidle(&pdev->dev);
6570 goto out;
6571}
6572
8027aa24
JW		 6573static struct rtnl_link_stats64 *
6574rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6575{
6576 struct rtl8169_private *tp = netdev_priv(dev);
6577 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 6578 unsigned int start;
1da177e4 6579
da78dbff 6580 if (netif_running(dev))
523a6094 6581 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 6582
8027aa24
JW		 6583 do {
6584 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6585 stats->rx_packets = tp->rx_stats.packets;
6586 stats->rx_bytes = tp->rx_stats.bytes;
6587 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6588
6589
6590 do {
6591 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6592 stats->tx_packets = tp->tx_stats.packets;
6593 stats->tx_bytes = tp->tx_stats.bytes;
6594 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6595
6596 stats->rx_dropped = dev->stats.rx_dropped;
6597 stats->tx_dropped = dev->stats.tx_dropped;
6598 stats->rx_length_errors = dev->stats.rx_length_errors;
6599 stats->rx_errors = dev->stats.rx_errors;
6600 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6601 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6602 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6603
6604 return stats;
1da177e4
LT		 6605}
6606
861ab440 6607static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6608{
065c27c1 6609 struct rtl8169_private *tp = netdev_priv(dev);
6610
5d06a99f 6611 if (!netif_running(dev))
861ab440 6612 return;
5d06a99f
FR		 6613
6614 netif_device_detach(dev);
6615 netif_stop_queue(dev);
da78dbff
FR		 6616
6617 rtl_lock_work(tp);
6618 napi_disable(&tp->napi);
6c4a70c5 6619 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 6620 rtl_unlock_work(tp);
6621
6622 rtl_pll_power_down(tp);
861ab440
RW		 6623}
6624
6625#ifdef CONFIG_PM
6626
6627static int rtl8169_suspend(struct device *device)
6628{
6629 struct pci_dev *pdev = to_pci_dev(device);
6630 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6631
861ab440 6632 rtl8169_net_suspend(dev);
1371fa6d 6633
5d06a99f
FR		 6634 return 0;
6635}
6636
e1759441
RW		 6637static void __rtl8169_resume(struct net_device *dev)
6638{
065c27c1 6639 struct rtl8169_private *tp = netdev_priv(dev);
6640
e1759441 6641 netif_device_attach(dev);
065c27c1 6642
6643 rtl_pll_power_up(tp);
6644
cff4c162
AS		 6645 rtl_lock_work(tp);
6646 napi_enable(&tp->napi);
6c4a70c5 6647 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6648 rtl_unlock_work(tp);
da78dbff 6649
98ddf986 6650 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6651}
6652
861ab440 6653static int rtl8169_resume(struct device *device)
5d06a99f 6654{
861ab440 6655 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6656 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6657 struct rtl8169_private *tp = netdev_priv(dev);
6658
6659 rtl8169_init_phy(dev, tp);
5d06a99f 6660
e1759441
RW		 6661 if (netif_running(dev))
6662 __rtl8169_resume(dev);
5d06a99f 6663
e1759441
RW		 6664 return 0;
6665}
6666
6667static int rtl8169_runtime_suspend(struct device *device)
6668{
6669 struct pci_dev *pdev = to_pci_dev(device);
6670 struct net_device *dev = pci_get_drvdata(pdev);
6671 struct rtl8169_private *tp = netdev_priv(dev);
6672
6673 if (!tp->TxDescArray)
6674 return 0;
6675
da78dbff 6676 rtl_lock_work(tp);
e1759441
RW		 6677 tp->saved_wolopts = __rtl8169_get_wol(tp);
6678 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6679 rtl_unlock_work(tp);
e1759441
RW		 6680
6681 rtl8169_net_suspend(dev);
6682
6683 return 0;
6684}
6685
6686static int rtl8169_runtime_resume(struct device *device)
6687{
6688 struct pci_dev *pdev = to_pci_dev(device);
6689 struct net_device *dev = pci_get_drvdata(pdev);
6690 struct rtl8169_private *tp = netdev_priv(dev);
6691
6692 if (!tp->TxDescArray)
6693 return 0;
6694
da78dbff 6695 rtl_lock_work(tp);
e1759441
RW		 6696 __rtl8169_set_wol(tp, tp->saved_wolopts);
6697 tp->saved_wolopts = 0;
da78dbff 6698 rtl_unlock_work(tp);
e1759441 6699
fccec10b
SG		 6700 rtl8169_init_phy(dev, tp);
6701
e1759441 6702 __rtl8169_resume(dev);
5d06a99f 6703
5d06a99f
FR		 6704 return 0;
6705}
6706
e1759441
RW		 6707static int rtl8169_runtime_idle(struct device *device)
6708{
6709 struct pci_dev *pdev = to_pci_dev(device);
6710 struct net_device *dev = pci_get_drvdata(pdev);
6711 struct rtl8169_private *tp = netdev_priv(dev);
6712
e4fbce74 6713 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6714}
6715
47145210 6716static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6717 .suspend = rtl8169_suspend,
6718 .resume = rtl8169_resume,
6719 .freeze = rtl8169_suspend,
6720 .thaw = rtl8169_resume,
6721 .poweroff = rtl8169_suspend,
6722 .restore = rtl8169_resume,
6723 .runtime_suspend = rtl8169_runtime_suspend,
6724 .runtime_resume = rtl8169_runtime_resume,
6725 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6726};
6727
6728#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6729
6730#else /* !CONFIG_PM */
6731
6732#define RTL8169_PM_OPS NULL
6733
6734#endif /* !CONFIG_PM */
6735
649b3b8c 6736static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6737{
6738 void __iomem *ioaddr = tp->mmio_addr;
6739
6740 /* WoL fails with 8168b when the receiver is disabled. */
6741 switch (tp->mac_version) {
6742 case RTL_GIGA_MAC_VER_11:
6743 case RTL_GIGA_MAC_VER_12:
6744 case RTL_GIGA_MAC_VER_17:
6745 pci_clear_master(tp->pci_dev);
6746
6747 RTL_W8(ChipCmd, CmdRxEnb);
6748 /* PCI commit */
6749 RTL_R8(ChipCmd);
6750 break;
6751 default:
6752 break;
6753 }
6754}
6755
1765f95d
FR		 6756static void rtl_shutdown(struct pci_dev *pdev)
6757{
861ab440 6758 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6759 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 6760 struct device *d = &pdev->dev;
6761
6762 pm_runtime_get_sync(d);
861ab440
RW		 6763
6764 rtl8169_net_suspend(dev);
1765f95d 6765
cecb5fd7 6766 /* Restore original MAC address */
cc098dc7
IV		 6767 rtl_rar_set(tp, dev->perm_addr);
6768
92fc43b4 6769 rtl8169_hw_reset(tp);
4bb3f522 6770
861ab440 6771 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6772 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6773 rtl_wol_suspend_quirk(tp);
6774 rtl_wol_shutdown_quirk(tp);
ca52efd5 6775 }
6776
861ab440
RW		 6777 pci_wake_from_d3(pdev, true);
6778 pci_set_power_state(pdev, PCI_D3hot);
6779 }
2a15cd2f 6780
6781 pm_runtime_put_noidle(d);
861ab440 6782}
5d06a99f 6783
baf63293 6784static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 6785{
6786 struct net_device *dev = pci_get_drvdata(pdev);
6787 struct rtl8169_private *tp = netdev_priv(dev);
6788
6789 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6790 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6791 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6792 rtl8168_driver_stop(tp);
6793 }
6794
ad1be8d3
DN		 6795 netif_napi_del(&tp->napi);
6796
e27566ed
FR		 6797 unregister_netdev(dev);
6798
6799 rtl_release_firmware(tp);
6800
6801 if (pci_dev_run_wake(pdev))
6802 pm_runtime_get_noresume(&pdev->dev);
6803
6804 /* restore original MAC address */
6805 rtl_rar_set(tp, dev->perm_addr);
6806
6807 rtl_disable_msi(pdev, tp);
6808 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6809 pci_set_drvdata(pdev, NULL);
6810}
6811
fa9c385e 6812static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6813 .ndo_open = rtl_open,
fa9c385e
FR		 6814 .ndo_stop = rtl8169_close,
6815 .ndo_get_stats64 = rtl8169_get_stats64,
6816 .ndo_start_xmit = rtl8169_start_xmit,
6817 .ndo_tx_timeout = rtl8169_tx_timeout,
6818 .ndo_validate_addr = eth_validate_addr,
6819 .ndo_change_mtu = rtl8169_change_mtu,
6820 .ndo_fix_features = rtl8169_fix_features,
6821 .ndo_set_features = rtl8169_set_features,
6822 .ndo_set_mac_address = rtl_set_mac_address,
6823 .ndo_do_ioctl = rtl8169_ioctl,
6824 .ndo_set_rx_mode = rtl_set_rx_mode,
6825#ifdef CONFIG_NET_POLL_CONTROLLER
6826 .ndo_poll_controller = rtl8169_netpoll,
6827#endif
6828
6829};
6830
31fa8b18
FR		 6831static const struct rtl_cfg_info {
6832 void (*hw_start)(struct net_device *);
6833 unsigned int region;
6834 unsigned int align;
6835 u16 event_slow;
6836 unsigned features;
6837 u8 default_ver;
6838} rtl_cfg_infos [] = {
6839 [RTL_CFG_0] = {
6840 .hw_start = rtl_hw_start_8169,
6841 .region = 1,
6842 .align = 0,
6843 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6844 .features = RTL_FEATURE_GMII,
6845 .default_ver = RTL_GIGA_MAC_VER_01,
6846 },
6847 [RTL_CFG_1] = {
6848 .hw_start = rtl_hw_start_8168,
6849 .region = 2,
6850 .align = 8,
6851 .event_slow = SYSErr | LinkChg | RxOverflow,
6852 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6853 .default_ver = RTL_GIGA_MAC_VER_11,
6854 },
6855 [RTL_CFG_2] = {
6856 .hw_start = rtl_hw_start_8101,
6857 .region = 2,
6858 .align = 8,
6859 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6860 PCSTimeout,
6861 .features = RTL_FEATURE_MSI,
6862 .default_ver = RTL_GIGA_MAC_VER_13,
6863 }
6864};
6865
6866/* Cfg9346_Unlock assumed. */
6867static unsigned rtl_try_msi(struct rtl8169_private *tp,
6868 const struct rtl_cfg_info *cfg)
6869{
6870 void __iomem *ioaddr = tp->mmio_addr;
6871 unsigned msi = 0;
6872 u8 cfg2;
6873
6874 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6875 if (cfg->features & RTL_FEATURE_MSI) {
6876 if (pci_enable_msi(tp->pci_dev)) {
6877 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6878 } else {
6879 cfg2 |= MSIEnable;
6880 msi = RTL_FEATURE_MSI;
6881 }
6882 }
6883 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6884 RTL_W8(Config2, cfg2);
6885 return msi;
6886}
6887
c558386b
HW		 6888DECLARE_RTL_COND(rtl_link_list_ready_cond)
6889{
6890 void __iomem *ioaddr = tp->mmio_addr;
6891
6892 return RTL_R8(MCU) & LINK_LIST_RDY;
6893}
6894
6895DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6896{
6897 void __iomem *ioaddr = tp->mmio_addr;
6898
6899 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6900}
6901
baf63293 6902static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 6903{
6904 void __iomem *ioaddr = tp->mmio_addr;
6905 u32 data;
6906
6907 tp->ocp_base = OCP_STD_PHY_BASE;
6908
6909 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6910
6911 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6912 return;
6913
6914 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6915 return;
6916
6917 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6918 msleep(1);
6919 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6920
5f8bcce9 6921 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6922 data &= ~(1 << 14);
6923 r8168_mac_ocp_write(tp, 0xe8de, data);
6924
6925 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6926 return;
6927
5f8bcce9 6928 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6929 data |= (1 << 15);
6930 r8168_mac_ocp_write(tp, 0xe8de, data);
6931
6932 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6933 return;
6934}
6935
baf63293 6936static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 6937{
6938 switch (tp->mac_version) {
6939 case RTL_GIGA_MAC_VER_40:
6940 case RTL_GIGA_MAC_VER_41:
57538c4a 6941 case RTL_GIGA_MAC_VER_42:
58152cd4 6942 case RTL_GIGA_MAC_VER_43:
45dd95c4 6943 case RTL_GIGA_MAC_VER_44:
c558386b
HW		 6944 rtl_hw_init_8168g(tp);
6945 break;
6946
6947 default:
6948 break;
6949 }
6950}
6951
baf63293 6952static int
3b6cf25d
FR		 6953rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6954{
6955 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6956 const unsigned int region = cfg->region;
6957 struct rtl8169_private *tp;
6958 struct mii_if_info *mii;
6959 struct net_device *dev;
6960 void __iomem *ioaddr;
6961 int chipset, i;
6962 int rc;
6963
6964 if (netif_msg_drv(&debug)) {
6965 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6966 MODULENAME, RTL8169_VERSION);
6967 }
6968
6969 dev = alloc_etherdev(sizeof (*tp));
6970 if (!dev) {
6971 rc = -ENOMEM;
6972 goto out;
6973 }
6974
6975 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 6976 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 6977 tp = netdev_priv(dev);
6978 tp->dev = dev;
6979 tp->pci_dev = pdev;
6980 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6981
6982 mii = &tp->mii;
6983 mii->dev = dev;
6984 mii->mdio_read = rtl_mdio_read;
6985 mii->mdio_write = rtl_mdio_write;
6986 mii->phy_id_mask = 0x1f;
6987 mii->reg_num_mask = 0x1f;
6988 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6989
6990 /* disable ASPM completely as that cause random device stop working
6991 * problems as well as full system hangs for some PCIe devices users */
6992 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6993 PCIE_LINK_STATE_CLKPM);
6994
6995 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6996 rc = pci_enable_device(pdev);
6997 if (rc < 0) {
6998 netif_err(tp, probe, dev, "enable failure\n");
6999 goto err_out_free_dev_1;
7000 }
7001
7002 if (pci_set_mwi(pdev) < 0)
7003 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
7004
7005 /* make sure PCI base addr 1 is MMIO */
7006 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
7007 netif_err(tp, probe, dev,
7008 "region #%d not an MMIO resource, aborting\n",
7009 region);
7010 rc = -ENODEV;
7011 goto err_out_mwi_2;
7012 }
7013
7014 /* check for weird/broken PCI region reporting */
7015 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7016 netif_err(tp, probe, dev,
7017 "Invalid PCI region size(s), aborting\n");
7018 rc = -ENODEV;
7019 goto err_out_mwi_2;
7020 }
7021
7022 rc = pci_request_regions(pdev, MODULENAME);
7023 if (rc < 0) {
7024 netif_err(tp, probe, dev, "could not request regions\n");
7025 goto err_out_mwi_2;
7026 }
7027
7028 tp->cp_cmd = RxChkSum;
7029
7030 if ((sizeof(dma_addr_t) > 4) &&
7031 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
7032 tp->cp_cmd |= PCIDAC;
7033 dev->features |= NETIF_F_HIGHDMA;
7034 } else {
7035 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7036 if (rc < 0) {
7037 netif_err(tp, probe, dev, "DMA configuration failed\n");
7038 goto err_out_free_res_3;
7039 }
7040 }
7041
7042 /* ioremap MMIO region */
7043 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
7044 if (!ioaddr) {
7045 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
7046 rc = -EIO;
7047 goto err_out_free_res_3;
7048 }
7049 tp->mmio_addr = ioaddr;
7050
7051 if (!pci_is_pcie(pdev))
7052 netif_info(tp, probe, dev, "not PCI Express\n");
7053
7054 /* Identify chip attached to board */
7055 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
7056
7057 rtl_init_rxcfg(tp);
7058
7059 rtl_irq_disable(tp);
7060
c558386b
HW		 7061 rtl_hw_initialize(tp);
7062
3b6cf25d
FR		 7063 rtl_hw_reset(tp);
7064
7065 rtl_ack_events(tp, 0xffff);
7066
7067 pci_set_master(pdev);
7068
7069 /*
7070 * Pretend we are using VLANs; This bypasses a nasty bug where
7071 * Interrupts stop flowing on high load on 8110SCd controllers.
7072 */
7073 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7074 tp->cp_cmd |= RxVlan;
7075
7076 rtl_init_mdio_ops(tp);
7077 rtl_init_pll_power_ops(tp);
7078 rtl_init_jumbo_ops(tp);
beb1fe18 7079 rtl_init_csi_ops(tp);
3b6cf25d
FR		 7080
7081 rtl8169_print_mac_version(tp);
7082
7083 chipset = tp->mac_version;
7084 tp->txd_version = rtl_chip_infos[chipset].txd_version;
7085
7086 RTL_W8(Cfg9346, Cfg9346_Unlock);
7087 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
7088 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
7089 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7090 tp->features |= RTL_FEATURE_WOL;
7091 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7092 tp->features |= RTL_FEATURE_WOL;
7093 tp->features |= rtl_try_msi(tp, cfg);
7094 RTL_W8(Cfg9346, Cfg9346_Lock);
7095
7096 if (rtl_tbi_enabled(tp)) {
7097 tp->set_speed = rtl8169_set_speed_tbi;
7098 tp->get_settings = rtl8169_gset_tbi;
7099 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7100 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7101 tp->link_ok = rtl8169_tbi_link_ok;
7102 tp->do_ioctl = rtl_tbi_ioctl;
7103 } else {
7104 tp->set_speed = rtl8169_set_speed_xmii;
7105 tp->get_settings = rtl8169_gset_xmii;
7106 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7107 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7108 tp->link_ok = rtl8169_xmii_link_ok;
7109 tp->do_ioctl = rtl_xmii_ioctl;
7110 }
7111
7112 mutex_init(&tp->wk.mutex);
7113
7114 /* Get MAC address */
7115 for (i = 0; i < ETH_ALEN; i++)
7116 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3b6cf25d
FR		 7117
7118 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
7119 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 7120
7121 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7122
7123 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7124 * properly for all devices */
7125 dev->features |= NETIF_F_RXCSUM |
f646968f 7126 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7127
7128 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 7129 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7130 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7131 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7132 NETIF_F_HIGHDMA;
7133
7134 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7135 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
f646968f 7136 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7137
7138 dev->hw_features |= NETIF_F_RXALL;
7139 dev->hw_features |= NETIF_F_RXFCS;
7140
7141 tp->hw_start = cfg->hw_start;
7142 tp->event_slow = cfg->event_slow;
7143
7144 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7145 ~(RxBOVF | RxFOVF) : ~0;
7146
7147 init_timer(&tp->timer);
7148 tp->timer.data = (unsigned long) dev;
7149 tp->timer.function = rtl8169_phy_timer;
7150
7151 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7152
7153 rc = register_netdev(dev);
7154 if (rc < 0)
7155 goto err_out_msi_4;
7156
7157 pci_set_drvdata(pdev, dev);
7158
92a7c4e7
FR		 7159 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7160 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7161 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 7162 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7163 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7164 "tx checksumming: %s]\n",
7165 rtl_chip_infos[chipset].jumbo_max,
7166 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7167 }
7168
7169 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7170 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7171 tp->mac_version == RTL_GIGA_MAC_VER_31) {
7172 rtl8168_driver_start(tp);
7173 }
7174
7175 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7176
7177 if (pci_dev_run_wake(pdev))
7178 pm_runtime_put_noidle(&pdev->dev);
7179
7180 netif_carrier_off(dev);
7181
7182out:
7183 return rc;
7184
7185err_out_msi_4:
ad1be8d3 7186 netif_napi_del(&tp->napi);
3b6cf25d
FR		 7187 rtl_disable_msi(pdev, tp);
7188 iounmap(ioaddr);
7189err_out_free_res_3:
7190 pci_release_regions(pdev);
7191err_out_mwi_2:
7192 pci_clear_mwi(pdev);
7193 pci_disable_device(pdev);
7194err_out_free_dev_1:
7195 free_netdev(dev);
7196 goto out;
7197}
7198
1da177e4
LT		 7199static struct pci_driver rtl8169_pci_driver = {
7200 .name = MODULENAME,
7201 .id_table = rtl8169_pci_tbl,
3b6cf25d 7202 .probe = rtl_init_one,
baf63293 7203 .remove = rtl_remove_one,
1765f95d 7204 .shutdown = rtl_shutdown,
861ab440 7205 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7206};
7207
3eeb7da9 7208module_pci_driver(rtl8169_pci_driver);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git